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User Manual: Motherboard Compal LA-7871P QAL51 - Schematics. Free.
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A B C D E 1 1 Compal Confidential QAL51 MB Schematic Document 2 2 LA-7871P Intel Ivy Bridge / Panther Point Discrete : N13P-GS / N13P-GT 3 3 Rev: 1.0 2012.02.29 4 4 Compal Secret Data Security Classification 2009/12/01 Issued Date 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. Cover Sheet Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet E 1 of 60 A B C D E Compal Confidential Model Name : QAL51 File Name : LA-7871P PEG(DIS) 100MHz PCI-E 2.0x16 5GT/s PER LANE 1 Mobile Ivy Bridge Memory BUS(DDRIII) CPU Dual / Quad Core Socket-rPGA989 N13P GS/GT 64*16 1G 128*16 2GB 1 204pin DDRIII-SO-DIMM X2 Dual Channel 1.5V DDRIII 1333/1600 page 10,11 BANK 0, 1, 2, 3 37.5mm*37.5mm page 4,5,6,7,8,9 page 20~28 CRT DMI X4 page 30 LVDS Conn. page 29 5V 480Mbps page 31 RTS5129 3IN1 Smart Card USB port 8,9 USB port 11 USB port 5 page 29 page 35 page 32 25mm*25mm SATA port 0 2 SATA HDD page 36 5V (6Gb/s) port 2 USB port 10 page 40 100MHz PCI-Express (PCIE 2.5GT/s) USB/B Right Int. Camera PCBGA989 HDMI Conn. 2 USB Intel Panther Point port 1 PCIeMini Card WLAN & BT 2.0 SATA port 2 RTL8105E 10/100M RTL8111E 1G 5V 1.5GHz(150MB/s) SATA ODD page 36 PCIe port 1 page 33 USB port 13 BIOS ROM PCIe port 2 page 32 page 39 page RJ45 12,13,14,15, 16,17,18,19 HD Audio 3.3V 24.576MHz/48Mhz page 33 LPC BUS HDA Codec ALC259 33MHz 3 PCIe 1x Express Card 1.5V 2.5GHz(250MB/s) PCIe port 3 USB port 4 Page 32 page 34 ENE KB930 (Co-Lay KB9012) page 38 3 Int. MIC CONN page 34 Touch Pad MIC CONN page 40 HP CONN page 40 SPK CONN page 34 Int.KBD page 35 page 42 EC ROM page 39 4 Function /B Fan Control page 40 page 41 USB&Audio/B RTC CKT. page 40 page 12 Power/B DC/DC Interface CKT. page 41 page 44 page 5 page 12 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. page 45~56 A Compal Secret Data Security Classification Power Circuit DC/DC page 35 4 PCH XDP Issued Date Touch Pad/B CPU XDP B C D Title Compal Electronics, Inc. Chief River-Block Diagram Size B Date: Document Number Rev 1.0 LA-7871P Wednesday, March 07, 2012 Sheet E 2 of 60 A Board ID Table for AD channel Vcc Ra Board ID 0 1 2 3 4 5 6 7 3.3V +/- 5% 100K +/- 5% Rb 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC USB PORT# BOARD ID Table V AD_BID min 0 V 0.168V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max 0 V 0.362 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V Board ID 0 1 2 3 4 5 6 7 PCB Revision QAL30 QAL31 / LP QAL31 / GT QAL50 QAL51 / GS QAL51 / GT PCH SMBUS Control Table SOURCE MIINI1 BATT 0001 011x b EC_SMB_CK1 EC_SMB_DA1 KB930 KB9012 EC_SMB_CK2 EC_SMB_DA2 KB930 KB9012 PCH_SMBCLK PCH_SMBDATA PCH PCH_SMLCLK PCH_SMLDATA PCH SODIMM SODIMM 1001 000x b 1001 010x b VGA Int. Thermal 0x9A JXDP1 JXDP2 X X V X X X X X X V V X V V X X X V V X X X X X CLKOUT DESTINATION PCI0 PCH_LOOPBACK PCI1 EC PCI2 TPM PCI3 None PCI4 None DESTINATION 0 USB2/3 (Left Hand side front) 1 USB2/3 (Left Hand side back) 2 None 3 None 4 USB2 (Right Hand side front) 5 Smart CARD 6 None 7 None 8 EXPRESS CARD 9 USB2 (Right Hand side back) 10 CAMERA 11 Card Reader 12 Finger Print 13 BT Comb 1 1 OPTIMUS: XDP@/D@ CLK DIFFERENTIAL DESTINATION FLEX CLOCKS CLKOUT_PCIE0 LAN CLKOUTFLEX0 CLKOUT_PCIE1 WLAN CLKOUT_PCIE2 DESTINATION SATA DESTINATION PCI EXPRESS None SATA0 HDD Lane 1 LAN CLKOUTFLEX1 None SATA1 None Lane 2 WLAN Express Card CLKOUTFLEX2 None SATA2 ODD Lane 3 Express Card CLKOUT_PCIE3 None CLKOUTFLEX3 None SATA3 None Lane 4 None CLKOUT_PCIE4 None SATA4 None Lane 5 None CLKOUT_PCIE5 None SATA5 None Lane 6 None CLKOUT_PCIE6 None Lane 7 None CLKOUT_PCIE7 None Lane 8 None CLKOUT_PEG_A VGA CLKOUT_PEG_B None Symbol Note : : means Digital Ground : means Analog Ground Compal Secret Data Security Classification 2011/05/23 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A Title DESTINATION Compal Electronics, Inc. Notes List Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 3 of 60 5 4 3 2 1 +V1.05S_VCCP JCPU1I RC1 24.9_0402_1% JCPU1A DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 B27 B25 A25 B24 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] 14 14 14 14 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 B28 B26 A24 B23 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] 14 14 14 14 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 G21 E22 F21 D21 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] 14 14 14 14 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 G22 D22 F20 C21 14 14 14 14 14 14 14 14 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 14 14 FDI_FSYNC0 FDI_FSYNC1 14 FDI_INT 14 14 FDI_LSYNC0 FDI_LSYNC1 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 A21 H19 E19 F18 B21 C20 D18 E17 FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 A22 G19 E20 G18 B20 C19 D19 F17 FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI_FSYNC0 FDI_FSYNC1 J18 J17 FDI0_FSYNC FDI1_FSYNC FDI_INT H20 FDI_LSYNC0 FDI_LSYNC1 J19 H17 A18 A17 B16 RC2 +V1.05S_VCCP 24.9_0402_1% EDP_COMP B C15 D15 EDP_HPD# +V1.05S_VCCP 10K_0402_5% @ RC8 C17 F16 C16 G15 C18 E16 D16 F15 Intel(R) FDI C FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_INT FDI0_LSYNC FDI1_LSYNC eDP_COMPIO eDP_ICOMPO eDP_HPD# eDP_AUX eDP_AUX# eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] eDP 14 14 14 14 14 14 14 14 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] PCI EXPRESS* - GRAPHICS 14 14 14 14 DMI D PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with - max length = 500 mils - typical impedance = 14.5 mohms PEG_COMP PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO J22 J21 H22 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32 PCIE_GTX_C_CRX_N15 PCIE_GTX_C_CRX_N14 PCIE_GTX_C_CRX_N13 PCIE_GTX_C_CRX_N12 PCIE_GTX_C_CRX_N11 PCIE_GTX_C_CRX_N10 PCIE_GTX_C_CRX_N9 PCIE_GTX_C_CRX_N8 PCIE_GTX_C_CRX_N7 PCIE_GTX_C_CRX_N6 PCIE_GTX_C_CRX_N5 PCIE_GTX_C_CRX_N4 PCIE_GTX_C_CRX_N3 PCIE_GTX_C_CRX_N2 PCIE_GTX_C_CRX_N1 PCIE_GTX_C_CRX_N0 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32 PCIE_GTX_C_CRX_P15 PCIE_GTX_C_CRX_P14 PCIE_GTX_C_CRX_P13 PCIE_GTX_C_CRX_P12 PCIE_GTX_C_CRX_P11 PCIE_GTX_C_CRX_P10 PCIE_GTX_C_CRX_P9 PCIE_GTX_C_CRX_P8 PCIE_GTX_C_CRX_P7 PCIE_GTX_C_CRX_P6 PCIE_GTX_C_CRX_P5 PCIE_GTX_C_CRX_P4 PCIE_GTX_C_CRX_P3 PCIE_GTX_C_CRX_P2 PCIE_GTX_C_CRX_P1 PCIE_GTX_C_CRX_P0 M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 PCIE_CTX_GRX_N15 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N0 CV1 CV2 CV3 CV4 CV5 CV6 CV7 CV8 CV9 CV10 CV11 CV12 CV13 CV14 CV15 CV16 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K PCIE_CTX_C_GRX_N15 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_N8 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_N0 M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25 PCIE_CTX_GRX_P15 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P0 CV17 CV18 CV19 CV20 CV21 CV22 CV23 CV24 CV25 CV26 CV27 CV28 CV29 CV30 CV31 CV32 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K PCIE_CTX_C_GRX_P15 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_P0 PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] 20 PCIE_GTX_C_CRX_N[0..15] 20 PCIE_GTX_C_CRX_P[0..15] PAY ATTENTION ON PCIE SWAP WHEN REVIEW 20 PCIE_CTX_C_GRX_N[0..15] 20 PCIE_CTX_C_GRX_P[0..15] T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3 D C B TYCO_2013620-2_IVY BRIDGE CONN@ TYCO_2013620-2_IVY BRIDGE CONN@ Close to CPU A RC3 DIS@ 1K_0402_5% FDI_FSYNC0 RC4 DIS@ 1K_0402_5% FDI_FSYNC1 RC5 DIS@ 1K_0402_5% FDI_LSYNC0 RC6 DIS@ 1K_0402_5% FDI_LSYNC1 RC7 DIS@ 1K_0402_5% FDI_INT A Compal Secret Data Security Classification Issued Date 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. PROCESSOR(1/6) DMI,FDI,PEG Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 4 of 60 5 4 3 2 1 +3V_PCH SYSTEM_PWROK @ RC13 10K_0402_5% 0_0402_5% RC11 1 B 200_0402_1% PM_DRAM_PWRGD D_PWG 0_0402_5% RC21 2 A 3 14 D UC1 VDDPWRGOOD 4 Y MC74VHC1G09DFT2G_SC70-5 @ RC25 39_0402_1% RC17 0_0402_5% S @ QC2 2 G @ RC16 SUSP D SSM3K7002FU_SC70-3 @ 44,9 RUN_ON_CPU1.5VS3# 44 RC14 200_0402_1% 1 5 +3V_PCH D +1.5V_CPU_VDDQ 3 RC12 G VCC 14 CC33 0.1U_0402_16V4Z +3VS 0_0402_5% +3VS +V1.05S_VCCP CC36 0.1U_0402_16V4Z P 2 A 1 UC2 Y 4 C RC35 BUFO_CPU_RST# BUF_CPU_RST# 43_0402_1% G 15,20,32,33,37,38 PLT_RST# NC 5 C RC38 75_0402_5% 3 SN74LVC1G07DCKR_SC70-5 C26 H_SNB_IVB# AN34 H_CATERR# H_CPUPWRGD_R 10K_0402_5% AL33 PROC_SELECT# SKTOCC# CATERR# RC45 16,38 AN33 H_PECI PECI @CC63 @ CC63 RC42 220P_0402_25V8J 38,46 H_PROCHOT# H_PROCHOT#_R AL32 56_0402_5% PROCHOT# B 16 H_THERMTRIP# H_THERMTRIP# AN32 THERMTRIP# A28 A27 CLK_CPU_DMI_R CLK_CPU_DMI#_R DPLL_REF_CLK DPLL_REF_CLK# A16 A15 CLK_CPU_DPLL_R CLK_CPU_DPLL#_R SM_DRAMRST# R8 H_DRAMRST# BCLK BCLK# CLOCKS 16 DDR3 MISC RC44 62_0402_5% @ CC62 220P_0402_25V8J MISC H_PROCHOT# THERMAL Processor Pullups @ RC40 0_0402_5% JCPU1B +V1.05S_VCCP SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] H_CPUPWRGD AM34 H_CPUPWRGD_R AP33 VDDPWRGOOD_R V8 PM_SYNC RC54 0_0402_5% UNCOREPWRGOOD RC58 VDDPWRGOOD 130_0402_1% BUF_CPU_RST# AR33 SM_DRAMPWROK RESET# JTAG & BPM 16 H_PM_SYNC_R 0_0402_5% PWR MANAGEMENT RC50 H_PM_SYNC XDP_PRDY#_R XDP_PREQ#_R TCK TMS TRST# AR26 AR27 AP30 XDP_TCK_R XDP_TMS_R XDP_TRST#_R TDI TDO AR28 AP26 XDP_TDI_R XDP_TDO_R DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] 0_0402_5% 0_0402_5% RC37 RC41 CLK_CPU_DMI 13 CLK_CPU_DMI# 13 PU/PD for JTAG signals 1K_0402_5% 1K_0402_5% H_DRAMRST# +V1.05S_VCCP +V1.05S_VCCP 6 XDP_TMS_R 51_0402_5% XDP_TDI_R 51_0402_5% RC46 RC47 DDR3 Compensation Signals XDP_PREQ#_R 51_0402_5% SM_RCOMP0 140_0402_1% RC56 XDP_TDO_R 51_0402_5% RC49 SM_RCOMP1 25.5_0402_1% RC59 SM_RCOMP2 200_0402_1% RC61 XDP_TCK_R 51_0402_5% RC53 XDP_TRST#_R 51_0402_5% RC55 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 AP29 AP27 PRDY# PREQ# 14 AK1 A5 A4 RC39 RC36 @ RC48 B AL35 XDP_DBRESET# AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 A A TYCO_2013620-2_IVY BRIDGE CONN@ Compal Secret Data Security Classification Issued Date 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. PROCESSOR(2/6) PM,XDP,CLK Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Sheet Wednesday, March 07, 2012 1 5 of 60 5 4 3 2 1 JCPU1C JCPU1D DDR_A_D[0..63] C B 10 10 10 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 10 10 10 DDR_A_CAS# DDR_A_RAS# DDR_A_WE# C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 AE10 AF10 V6 AE8 AD9 AF9 SA_CLK[0] SA_CLK#[0] SA_CKE[0] SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_CLK[1] SA_CLK#[1] SA_CKE[1] AA5 AB5 V10 RSVD_TP[1] RSVD_TP[2] RSVD_TP[3] AB4 AA4 W9 RSVD_TP[4] RSVD_TP[5] RSVD_TP[6] DDR SYSTEM MEMORY A DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDRA_CLK0 DDRA_CLK0# DDRA_CKE0 DDRA_CLK1 DDRA_CLK1# DDRA_CKE1 AK3 AL3 AG1 AH1 DDRA_SCS0# DDRA_SCS1# SA_ODT[0] SA_ODT[1] RSVD_TP[9] RSVD_TP[10] AH3 AG3 AG2 AH2 DDRA_ODT0 DDRA_ODT1 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] SA_BS[0] SA_BS[1] SA_BS[2] SA_CAS# SA_RAS# SA_WE# 11 DDR_B_D[0..63] DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 10 10 10 AB3 AA3 W10 SA_CS#[0] SA_CS#[1] RSVD_TP[7] RSVD_TP[8] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] 10 10 10 C4 G6 J3 M6 AL6 AM8 AR12 AM15 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 D4 F6 K3 N6 AL5 AM9 AR11 AM14 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 10 10 10 10 10 DDR_A_DQS#[0..7] 10 DDR_A_DQS[0..7] DDR_A_MA[0..15]10 11 11 11 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 11 11 11 DDR_B_CAS# DDR_B_RAS# DDR_B_WE# C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 AA9 AA7 R6 AA10 AB8 AB9 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] SB_CLK[0] SB_CLK#[0] SB_CKE[0] SB_CLK[1] SB_CLK#[1] SB_CKE[1] RSVD_TP[11] RSVD_TP[12] RSVD_TP[13] RSVD_TP[14] RSVD_TP[15] RSVD_TP[16] DDR SYSTEM MEMORY B 10 D AB6 AA6 V9 SB_BS[0] SB_BS[1] SB_BS[2] SB_CAS# SB_RAS# SB_WE# AE2 AD2 R9 DDRB_CLK0 DDRB_CLK0# DDRB_CKE0 11 11 11 AE1 AD1 R10 DDRB_CLK1 DDRB_CLK1# DDRB_CKE1 11 11 11 AB2 AA2 T9 AA1 AB1 T10 SB_CS#[0] SB_CS#[1] RSVD_TP[17] RSVD_TP[18] AD3 AE3 AD6 AE6 DDRB_SCS0# DDRB_SCS1# 11 11 SB_ODT[0] SB_ODT[1] RSVD_TP[19] RSVD_TP[20] AE4 AD4 AD5 AE5 DDRB_ODT0 DDRB_ODT1 11 11 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] D C D7 F3 K6 N3 AN5 AP9 AK12 AP15 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 C7 G3 J6 M3 AN6 AP8 AK11 AP14 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 11 DDR_B_DQS#[0..7] 11 DDR_B_DQS[0..7] DDR_B_MA[0..15]11 B TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE CONN@ CONN@ +1.5V @ RC75 DDR3_DRAMRST#_R 0_0402_5% RC76 1K_0402_5% Q3 H_DRAMRST# H_DRAMRST# D 3 1 SSM3K7002FU_SC70-3 RC77 1K_0402_5% SM_DRAMRST# 10,11 A G 2 5 S A RC78 4.99K_0402_1% DRAMRST_CNTRL RC73 DRAMRST_CNTRL_PCH 13 0_0402_5% RC9 1M_0402_5% CC37 0.047U_0402_16V4Z Issued Date @ 5 4 Compal Secret Data Security Classification 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 Title Compal Electronics, Inc. PROCESSOR(3/6) DDRIII Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 6 of 60 5 4 3 2 1 CFG Straps for Processor D D CFG2 JCPU1E RC115 49.9_0402_1% RC116 49.9_0402_1% @ RC105 @RC105 RC117 100_0402_1% 49.9_0402_1% C +VCC_CORE @ RC106 RC118 VCC_AXG_VAL_SENSE VSS_AXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE 100_0402_1% 49.9_0402_1% CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] VCC_DIE_SENSE VSS_DIE_SENSE RSVD28 RSVD29 RSVD30 RSVD31 AJ31 AH31 AJ33 AH33 VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE AJ26 RSVD5 INTEL recommand to add RC115, RC116, RC117, RC118 Please place as close as JCPU1 F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 J20 B18 J15 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD32 RSVD33 RSVD34 RSVD35 AH27 AH26 L7 AG7 AE7 AK2 PEG Static Lane Reversal - CFG2 is for the 16x CFG2 W8 1:(Default) Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed AT26 AM33 AJ27 CFG4 @RC82 @ RC82 1K_0402_1% RSVD37 RSVD38 RSVD39 RSVD40 T8 J16 H16 G16 C RESERVED +GFX_CORE AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 CFG CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 RC79 1K_0402_1% RSVD24 RSVD25 RSVD27 B RSVD_NCTF1 RSVD_NCTF2 RSVD_NCTF3 RSVD_NCTF4 RSVD_NCTF5 Display Port Presence Strap AR35 AT34 AT33 AP35 AR34 CFG4 1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port RSVD_NCTF6 RSVD_NCTF7 RSVD_NCTF8 RSVD_NCTF9 RSVD_NCTF10 RSVD51 RSVD52 BCLK_ITP BCLK_ITP# RSVD_NCTF11 RSVD_NCTF12 RSVD_NCTF13 B34 A33 A34 B35 C35 CFG6 CFG5 @ RC83 1K_0402_1% AJ32 AK32 AN35 AM35 CLK_RES_ITP CLK_RES_ITP# 13 13 PCIE Port Bifurcation Straps AT2 AT1 AR1 B 11: (Default) x16 - Device 1 functions 1 and 2 disabled CFG[6:5] KEY @ RC84 1K_0402_1% B1 TYCO_2013620-2_IVY BRIDGE 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled CONN@ CFG7 @RC85 @ RC85 1K_0402_1% PEG DEFER TRAINING CFG7 1: (Default) PEG Train immediately following RESETB de assertion 0: PEG Wait for BIOS for training A A Compal Secret Data Security Classification Issued Date 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. PROCESSOR(4/6) RSVD,CFG Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 7 of 60 4 3 JCPU1H JCPU1F AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2 1 POWER +V1.05S_VCCP +VCC_CORE TYCO_2013620-2_IVY BRIDGE VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 VCCIO40 J23 D C +V1.05S_VCCP VIDALERT# VIDSCLK VIDSOUT AJ29 AJ30 AJ28 H_CPU_SVIDALRT# RC90 H_CPU_SVIDCLK H_CPU_SVIDDAT H_CPU_SVIDCLK RC88 VR_SVID_CLK 0_0402_5% 53 Place the PU resistors close to CPU RC89 75_0402_5% VR_SVID_ALRT# 53 43_0402_1% +V1.05S_VCCP RC91 130_0402_1% B H_CPU_SVIDDAT RC92 VR_SVID_DAT 0_0402_5% Place the PU resistors close to CPU 53 +VCC_CORE RC93 100_0402_1% VCC_SENSE VSS_SENSE VCCIO_SENSE VSS_SENSE_VCCIO AJ35 VCCSENSE_R AJ34 VSSSENSE_R RC94 RC95 VCCSENSE VSSSENSE 0_0402_5% 0_0402_5% 53 53 RC97 100_0402_1% B10 A10 VCCIO_SENSE 50 1 CONN@ VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 CC50 0.1U_0402_16V4Z AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 PEG AND DDR 97AAG35 8.5A CC49 0.1U_0402_16V4Z B VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 2 SVID C VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 SENSE LINES D AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25 CORE SUPPLY 5 RC98 10_0402_1% Close to CPU 2 A TYCO_2013620-2_IVY BRIDGE VCCIO_SENSE Compal Secret Data Security Classification Issued Date 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 +V1.05S_VCCP A 2 10_0402_5% CONN@ 5 1 R75 3 2 Title Compal Electronics, Inc. PROCESSOR(5/6) PWR,BYPASS Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 8 of 60 5 4 3 2 1 +1.5V_CPU_VDDQ QC4 MDU1512RH_PPAK56-8-5 1 2 5 3 4 RC99 100K_0402_5% 3 RUN_ON_CPU1.5VS3 QC5B RUN_ON_CPU1.5VS3# 5 6 4 2N7002DW-7-F_SOT363-6 QC5A 2N7002DW-7-F_SOT363-6 @RC103 @ RC103 D 2 32,38,44,49,50,51,56 SUSP# 38 CC39 0.1U_0603_50V7K RC102 330K_0402_1% RC101 100K_0402_5% D +1.5V_CPU_VDDQ RC100 20K_0402_5% +VSBP CC38 10U_0805_10V4Z +1.5V +3VALW CPU1.5V_S3_GATE 1 0_0402_5% RC104 44,5 RUN_ON_CPU1.5VS3# 0_0402_5% R78 0_0402_5% DIS@ R79 0_0402_5% DIS@ Close to CPU POWER RC107 2 G VREF D S @ 1 3 SA_DIMM_VREFDQ SB_DIMM_VREFDQ B4 D1 +V_SM_VREF should have 10 mil trace width +V_SM_VREF PMV45EN_SOT23-3 RC110 1K_0402_1% RUN_ON_CPU1.5VS3 SA RAIL CC56 10U_0805_10VM VCCSA_SENSE MISC 2 PAD-OPEN 4x4m 1 + 2 CC57 330U_X_2VM_R6M B VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 VCCSA_VID[0] VCCSA_VID[1] VCCIO_SEL M27 M26 L26 J26 J25 J24 H26 H25 6A +VCCSA H23 C22 C24 CC43 10U_0603_6.3V6M 1.8V RAIL 1 CC42 10U_0805_6.3V6M VCCPLL1 VCCPLL2 VCCPLL3 +1.5V @JP0901 @ JP0901 10A AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1 CC55 10U_0805_10VM DDR3 -1.5V RAILS +1.5V_CPU_VDDQ VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 CC54 10U_0805_10VM @ AL1 +V_SM_VREF_CNT CC41 10U_0805_6.3V6M 2 C CC53 10U_0805_10VM + +1.5V_CPU_VDDQ RC108 1K_0402_1% CC40 10U_0805_6.3V6M 2 1 CC61 330U_X_2VM_R6M 1 CC60 1U_0402_6.3V6K 2 CC59 1U_0402_6.3V6K CC58 10U_0805_6.3V6M 1 VCC_AXG_SENSE53 VSS_AXG_SENSE53 QC6 1.5A B6 A6 A2 R79 +GFX_CORE UMA@ 100_0402_1% UMA@ 100_0402_1% 0_0402_5% SM_VREF +1.8VS_VCCPLL RC119 0_0805_5% VSS_AXG_SENSE CC52 10U_0805_10VM +1.8VS VAXG_SENSE VSSAXG_SENSE AK35 AK34 R78 CC51 10U_0805_10VM B VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 GRAPHICS +GFX_CORE C AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 SENSE LINES JCPU1G 33A VCC_AXG_SENSE @ 1 1 + RH235 CC44 330U_X_2VM_R6M 2+VCCSA_SENSE 100_0402_5% +1.5V_CPU_VDDQ CC45 0.1U_0402_10V7K CC46 0.1U_0402_10V7K CC47 0.1U_0402_10V7K CC48 0.1U_0402_10V7K @ +VCCSA_SENSE 52 @ RC111 0_0402_5% H_VCCSA_VID0 52 H_VCCSA_VID1 52 +1.5V 2 A19 +3VS TYCO_2013620-2_IVY BRIDGE CONN@ @RC112 @ RC112 10K_0402_5% H_VCCP_SEL 0_0402_5% A VCCP_PWRCTRL @RC114 @ RC114 A IVY Bridge drives VCCIO_SEL low VCCP_PWRCTRL:0 Sandy Bridge is NC for A19 VCCP_PWRCTRL:1 Compal Secret Data Security Classification Issued Date 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. PROCESSOR(6/6) PWR,VSS Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Sheet Wednesday, March 07, 2012 1 9 of 60 5 4 3 2 1 +1.5V 3A@1.5V +1.5V RD1 1K_0402_1% +1.5V DDR3 SO-DIMM A +V_DDR_REFA CD2 2.2U_0603_6.3V6K 1K_0402_1% CD1 0.1U_0402_10V6K CD50 0.1U_0402_10V6K RD2 D DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 @JDDRL @ JDDRL 1 VREF_DQ 3 VSS2 5 DQ0 7 DQ1 9 VSS4 11 DM0 13 VSS5 15 DQ2 17 DQ3 19 VSS7 21 DQ8 23 DQ9 25 VSS9 27 DQS#1 29 DQS1 31 VSS11 33 DQ10 35 DQ11 37 VSS13 39 DQ16 41 DQ17 43 VSS15 45 DQS#2 47 DQS2 49 VSS18 51 DQ18 53 DQ19 55 VSS20 57 DQ24 59 DQ25 61 VSS22 63 DM3 65 VSS23 67 DQ26 69 DQ27 71 VSS25 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 6 DDR_A_D[0..63] 6 DDR_A_DQS[0..7] 6 DDR_A_DQS#[0..7] 6 DDR_A_MA[0..15] DDR_A_D4 DDR_A_D5 DDR_A_DQS#0 DDR_A_DQS0 D DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 SM_DRAMRST# SM_DRAMRST#11,6 DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 Layout Note: Place near JDDRL C DDRA_CKE0 6 DDRA_CKE0 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 RD7 1K_0402_1% DDR_A_D44 DDR_A_D45 B DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 Layout Note: Place near JDDRL.203,204 DDR_A_D54 DDR_A_D55 +0.75VS DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 1 DDR_A_D62 DDR_A_D63 2 PCH_SMBDATA PCH_SMBCLK 1 2 1 2 1 2 A PCH_SMBDATA11,13,32 PCH_SMBCLK 11,13,32 +0.75VS 0.65A@0.75V TYCO_2-2013022-2 Compal Secret Data Security Classification 2011/05/23 Issued Date 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 CD14 206 10U_0603_6.3V6M G2 G1 +1.5V +VREF_CA CD24 1U_0402_6.3V6K 205 Layout Note: Place these 4 Caps near Command and Control signals of JDDRL CD23 1U_0402_6.3V6K RD9 10K_0402_5% RD8 10K_0402_5% CD26 0.1U_0402_10V6K CD25 2.2U_0603_6.3V6K +3VS 2 6 CD22 1U_0402_6.3V6K A DDRA_ODT1 CD21 1U_0402_6.3V6K DDR_A_D58 DDR_A_D59 2 1 @ CD20 0.1U_0402_10V6K DDR_A_D56 DDR_A_D57 CD13 DDR_A_D50 DDR_A_D51 1 10U_0603_6.3V6M DDR_A_DQS#6 DDR_A_DQS6 2 CD19 0.1U_0402_10V6K DDR_A_D48 DDR_A_D49 CD12 DDR_A_D42 DDR_A_D43 RD6 1K_0402_1% DDRA_SCS0# 6 DDRA_ODT0 6 CD18 0.1U_0402_10V6K DDR_A_D40 DDR_A_D41 2 1 +1.5V CD17 0.1U_0402_10V6K DDR_A_D34 DDR_A_D35 DDRA_ODT1 6 6 2 1 6 DDR_A_BS1 DDR_A_RAS# 6 CD16 2.2U_0603_6.3V6K DDR_A_DQS#4 DDR_A_DQS4 DDRA_SCS0# DDRA_ODT0 DDRA_CLK1 DDRA_CLK1# CD15 0.1U_0402_10V6K DDR_A_D32 DDR_A_D33 B DDR_A_BS1 DDR_A_RAS# 2 1 10U_0603_6.3V6M 6 DDRA_SCS1# DDRA_CLK1 DDRA_CLK1# 2 1 CD11 DDR_A_MA13 DDRA_SCS1# 2 DDR_A_MA2 DDR_A_MA0 1 10U_0603_6.3V6M DDR_A_WE# DDR_A_CAS# 6 DDR_A_WE# 6 DDR_A_CAS# DDR_A_MA6 DDR_A_MA4 CD10 6 DDR_A_BS0 + 10U_0603_6.3V6M DDR_A_MA10 DDR_A_BS0 @ 1 DDR_A_MA11 DDR_A_MA7 CD9 DDRA_CLK0 DDRA_CLK0# 6 DDRA_CLK0 6 DDRA_CLK0# DDR_A_MA15 DDR_A_MA14 10U_0603_6.3V6M DDR_A_MA3 DDR_A_MA1 6 DDRA_CKE1 C +1.5V CD8 DDR_A_MA8 DDR_A_MA5 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 DDRA_CKE1 10U_0603_6.3V6M DDR_A_MA12 DDR_A_MA9 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 CD7 330U_B2_2.5VM_R15M DDR_A_BS2 6 DDR_A_BS2 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 4 3 2 Title Compal Electronics, Inc. DDRIII-DDRL Size Document Number Custom Date: Rev 1.0 QAL51, LA-7871P MB Wednesday, March 07, 2012 Sheet 1 10 of 60 5 4 3 2 1 +1.5V +1.5V B DDR_B_D34 DDR_B_D35 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 RD14 10K_0402_5% CD49 0.1U_0402_10V6K CD48 2.2U_0603_6.3V6K +3VS A RD15 10K_0402_5% 205 G1 G2 SM_DRAMRST#10,6 Layout Note: Place these 4 Caps near Command and Control signals of JDDRH DDR_B_D20 DDR_B_D21 +1.5V DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 DDRB_CKE1 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDRB_CKE1 6 C DDR_B_MA15 DDR_B_MA14 Layout Note: Place near JDDRH.203 and 204 DDR_B_MA11 DDR_B_MA7 +0.75VS DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDRB_CLK1 DDRB_CLK1# DDRB_CLK1 DDRB_CLK1# DDR_B_BS1 DDR_B_RAS# 6 6 6 DDR_B_BS1 DDR_B_RAS# 6 DDRB_SCS0# DDRB_ODT0 +1.5V DDRB_SCS0# 6 DDRB_ODT0 6 DDRB_ODT1 DDRB_ODT1 RD12 1K_0402_1% 6 +VREF_CB DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 CD47 2.2U_0603_6.3V6K DDR_B_DQS#4 DDR_B_DQS4 RD13 B 1K_0402_1% DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 PCH_SMBDATA PCH_SMBCLK PCH_SMBDATA10,13,32 PCH_SMBCLK 10,13,32 +0.75VS A 0.65A@0.75V 206 TYCO 2-1932300-1 204P H8.0 Compal Secret Data Security Classification 2011/05/23 Issued Date 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 D DDR_B_D14 DDR_B_D15 CD46 0.1U_0402_10V6K DDR_B_D32 DDR_B_D33 10U_0603_6.3V6M DDR_B_MA13 DDRB_SCS1# 2 CD45 1U_0603_10V6K DDRB_SCS1# 1 CD33 0.1U_0402_10V6K 6 DDR_B_WE# DDR_B_CAS# CD41 DDR_B_WE# DDR_B_CAS# 2 CD44 1U_0603_10V6K DDR_B_BS0 6 6 1 CD30 0.1U_0402_10V6K 6 2 CD40 DDR_B_MA10 DDR_B_BS0 2 1 10U_0603_6.3V6M DDRB_CLK0 DDRB_CLK0# DDRB_CLK0 DDRB_CLK0# 2 1 CD43 1U_0603_10V6K 6 6 2 1 CD42 1U_0603_10V6K DDR_B_MA3 DDR_B_MA1 SM_DRAMRST# 2 1 CD39 DDR_B_MA8 DDR_B_MA5 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 DDR_B_D12 DDR_B_D13 2 1 @ 10U_0603_6.3V6M DDR_B_MA12 DDR_B_MA9 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 2 DDR_B_D6 DDR_B_D7 1 @ CD32 0.1U_0402_10V6K DDR_B_BS2 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 + 10U_0603_6.3V6M DDR_B_BS2 1 CD29 0.1U_0402_10V6K 6 DDRB_CKE0 DDRB_CKE0 DDR_B_MA[0..15] CD38 6 6 +1.5V CD37 DDR_B_D26 DDR_B_D27 DDR_B_DQS[0..7] 10U_0603_6.3V6M DDR_B_D24 DDR_B_D25 DDR_B_D[0..63] 6 CD36 DDR_B_D18 DDR_B_D19 DDR_B_DQS#0 DDR_B_DQS0 6 10U_0603_6.3V6M DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D4 DDR_B_D5 CD35 DDR_B_D16 DDR_B_D17 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 10U_0603_6.3V6M DDR_B_D10 DDR_B_D11 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 CD34 DDR_B_D8 DDR_B_D9 @ JDDRH 1 VREF_DQ 3 VSS2 5 DQ0 7 DQ1 9 VSS4 11 DM0 13 VSS5 15 DQ2 17 DQ3 19 VSS7 21 DQ8 23 DQ9 25 VSS9 27 DQS#1 29 DQS1 31 VSS11 33 DQ10 35 DQ11 37 VSS13 39 DQ16 41 DQ17 43 VSS15 45 DQS#2 47 DQS2 49 VSS18 51 DQ18 53 DQ19 55 VSS20 57 DQ24 59 DQ25 61 VSS22 63 DM3 65 VSS23 67 DQ26 69 DQ27 71 VSS25 DDR_B_DQS#[0..7] 10U_0603_6.3V6M DDR_B_D2 DDR_B_D3 DDR_B_DQS#1 DDR_B_DQS1 C Layout Note: Place near JDDRH 6 CD31 330U_B2_2.5VM_R15M DDR_B_D0 DDR_B_D1 CD51 0.1U_0402_10V6K CD27 CD28 0.1U_0402_10V6K 2.2U_0603_6.3V6K D RD11 1K_0402_1% +V_DDR_REFB +1.5V 3A@1.5V RD10 1K_0402_1% 4 3 2 Title Compal Electronics, Inc. DDRIII-DDRH Size Document Number Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 11 of 60 5 4 3 2 1 PCH_RTCX1 PCH_RTCX2 10M_0402_5% 32.768KHZ_12.5PF_CM31532768DZFT CH3 15P_0402_50V8J +RTCVCC HM75@ UH1 HM75 SM_INTRUDER# 50@ CH3 18P_50V_NPO_0402 RH12 1M_0402_5% 31@ CH3 18P_50V_NPO_0402 UH1A 1 +RTCVCC CMOS CLRP1 SHORT PADS 2 CH4 1U_0603_10V4Z PCH_RTCX1 A20 PCH_RTCX2 C20 D20 PCH_SRTCRST# G22 SM_INTRUDER# K22 INTRUDER# C17 INTVRMEN ME_EN from EC. Please place close to RH29 aviod the branch. 38 34 34 34 C ME_EN RH27 AZ_RST_HD# RH30 AZ_SDOUT_HD RH32 1 34 HDA_SDOUT 0_0402_5% RH25 AZ_BITCLK_HD CLRP2 PCH_INTVRMEN SHORT PADS ME CMOS CLP1 & CLP2 place near DIMM 2 CH5 1U_0603_10V4Z PCH_SPKR HDA_BIT_CLK 2 33_0402_5% 1 AZ_SDIN0_HD HDA_BIT_CLK N34 HDA_SYNC L34 PCH_SPKR T10 HDA_RST# K34 AZ_SDIN0_HD 34 E34 G34 HDA_RST# 2 33_0402_5% HDA_SDOUT 2 33_0402_5% 1 1 C34 A34 HDA_SDOUT +3V_PCH RH38 XDP@ 200_0402_5% +3V_PCH RH39 XDP@ 200_0402_5% PCH_JTAG_TDO RH40 XDP@ 200_0402_5% PCH_JTAG_TMS RH44 XDP@ 100_0402_1% RH45 XDP@ 100_0402_1% SPKR HDA_RST# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 H7 PCH_JTAG_TDI K5 PCH_JTAG_TDO H1 SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA2RXN SATA2RXP SATA2TXN SATA2TXP HDA_DOCK_EN# / GPIO33 PCH_JTAG_TMS SERIRQ HDA_SYNC HDA_SDO J3 LDRQ0# LDRQ1# / GPIO23 HDA_BCLK SATA3RXN SATA3RXP SATA3TXN SATA3TXP SATA4RXN SATA4RXP SATA4TXN SATA4TXP HDA_DOCK_RST# / GPIO13 39 51_0402_5% Intel DPDG Rev1.2 requirement. +5VS PCH_SPI_CLK PCH_SPI_CS# 39 PCH_SPI_CS1# 39 PCH_SPI_MOSI 39 PCH_SPI_MISO LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 D36 LPC_FRAME# E36 K36 LPC_LDRQ0# LPC_LDRQ1# V5 SERIRQ AM3 AM1 AP7 AP5 SATA_PRX_C_DTX_N0 SATA_PRX_C_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 AD7 AD5 AH5 AH4 SATAICOMPO Y11 SATAICOMPI PCH_SPI_CLK T3 SPI_CLK PCH_SPI_CS# Y14 SPI_CS0# PCH_SPI_CS1# T1 SPI_CS1# PCH_SPI_MOSI V4 SPI_MOSI PCH_SPI_MISO U3 SATA3RBIAS LPC_FRAME# 37,38 SERIRQ 37,38 36 SATA_PRX_C_DTX_N0 36 SATA_PRX_C_DTX_P0 36 SATA_PTX_DRX_N0 36 SATA_PTX_DRX_P0 HDD +3VS +RTCVCC SATA_PRX_C_DTX_N2 SATA_PRX_C_DTX_P2 SATA_PTX_DRX_N2 SATA_PTX_DRX_P2 PCH_INTVRMEN RH33 36 SATA_PRX_C_DTX_N2 36 SATA_PRX_C_DTX_P2 36 SATA_PTX_DRX_N2 36 SATA_PTX_DRX_P2 SERIRQ RH28 10K_0402_5% PCH_GPIO21 RH29 10K_0402_5% PCH_SATALED# RH31 10K_0402_5% @ RH34 4.7K_0402_5% 330K_0402_5% BBS_BIT0_R ODD PCH_INTVRMEN RH35 * LH： ：Integrated Integrated @ 330K_0402_5% INTVRMEN C VRM enable VRM disable +3VS PCH_SPKR RH36 Y7 Y5 AD3 AD1 JTAG_TMS JTAG_TDO 37,38 37,38 37,38 37,38 AB8 AB10 AF3 AF1 Y3 Y1 AB3 AB1 JTAG_TDI LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 AM10 AM8 AP11 AP10 SATA5RXN SATA5RXP SATA5TXN SATA5TXP SATA3COMPI RH46 XDP@ 100_0402_1% C38 A38 B37 C37 JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TCK XDP@ FWH4 / LFRAME# SRTCRST# A36 PCH_JTAG_TCK FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 SATA3RCOMPO 39 RH50 RTCRST# C36 N32 +3V_PCH RTCX2 PCH_RTCRST# RH23 20K_0402_5% RH24 20K_0402_5% RTCX1 LPC 50@ CH2 18P_50V_NPO_0402 D HM76@ UH1 HM76 SATA 6G 2 SATA 2 RTC 1 CH2 IHDA 15P_0402_50V8J D 1 2 YH1 JTAG 1 Y10 @ 1K_0402_5% LOW=Default Reboot *HIGH=No +1.05VS_VCC_SATA HDA_SDO +3V_PCH ME debug mode , this signal has a weak internal PD SATA_COMP HDA_SDOUT RH42 RH41 L=>security measures defined in the Flash Descriptor will be in effect (default) H=>Flash Descriptor Security will be overridden 37.4_0402_1% +1.05VS_SATA3 AB12 AB13 SATA3_COMP RH43 49.9_0402_1% AH1 RBIAS_SATA3 RH48 750_0402_1% @ 1K_0402_5% = Disabled *Low High = Enabled HDA_SYNC SPI RH2 SPI_MISO SATALED# SATA0GP / GPIO21 SATA1GP / GPIO19 P3 PCH_SATALED# V14 PCH_GPIO21 P1 BBS_BIT0_R PCH_SATALED# 42 This signal has a weak internal pull-down On Die PLL VR is supplied by 1.5V when smapled high 1.8V when sampled low Needs to be pulled High for Chief River platfrom PANTHER-POINT_FCBGA989 B +3V_PCH G 2 B 1 RH54 2 RH56 1M_0402_5% 1 HDA_SYNC D AZ_SYNC_HD 3 S 34 2 AZ_SYNC_HD_R 33_0402_5% 1 SPI ROM FOR ME ( 4MByte ) HDA_SYNC RH55 1K_0402_5% BSS138_SOT23 QH1 Intel recommend RTC Battery +RTCBATT CH7 MAX. 8000mil RH62 1K_0402_5% RH65 PCH_SPI_CLK Reserve for EMI DH1 1 0_0402_5% 10P_0402_50V8J W=20mils +CHGRTC CH8 1U_0603_10V4Z 2 W=20mils 1 3 +RTCVCC A A BAS40-04_SOT23-3W=20mils 2 Compal Secret Data Security Classification Issued Date 2011/05/23 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. PCH (1/8) SATA,HDA,SPI, LPC Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 1 Sheet 12 of 60 5 4 3 2 1 +3V_PCH PCH_GPIO11 RH105 10K_0402_5% RH70 2.2K_0402_5% RH72 2.2K_0402_5% RH77 2.2K_0402_5% RH73 2.2K_0402_5% RH74 2.2K_0402_5% RH78 2.2K_0402_5% RH75 10K_0402_5% RH76 1K_0402_1% SMBCLK SMBDATA UH1B SML0CLK 0.1U_0402_10V7K 0.1U_0402_10V7K PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 PCIE_PTX_WLANRX_N2_C PCIE_PTX_WLANRX_P2_C CH10 CH15 PCIE_PRX_EXPTX_N3 PCIE_PRX_EXPTX_P3 PCIE_PTX_EXPRX_N3_C PCIE_PTX_EXPRX_P3_C 0.1U_0402_10V7K 0.1U_0402_10V7K C 33 33 CLK_PCIE_LAN# CLK_PCIE_LAN 33 MiniWLAN (Mini Card 1)---> EXPRESS_CARD ---> 32 32 +3V_PCH LANCLK_REQ# CLK_PCIE_WLAN# CLK_PCIE_WLAN 32 WLANCLK_REQ# +3VS 32 32 CLK_PCIE_EXP# CLK_PCIE_EXP 32 EXPCLK_REQ# +3VS +3V_PCH RH92 RH93 0_0402_5% 0_0402_5% PCIE_LAN# PCIE_LAN RH95 10K_0402_5% LANCLK_REQ# RH97 RH98 0_0402_5% 0_0402_5% PCIE_WLAN# PCIE_WLAN WLANCLK_REQ# RH99 10K_0402_5% RH100 RH101 0_0402_5% 0_0402_5% PCIE_EXP# PCIE_EXP EXPCLK_REQ# RH104 10K_0402_5% RH107 10K_0402_5% PERN2 PERP2 PETN2 PETP2 BG36 BJ36 AV34 AU34 PERN3 PERP3 PETN3 PETP3 BF36 BE36 AY34 BB34 PERN4 PERP4 PETN4 PETP4 BG37 BH37 AY36 BB36 PERN5 PERP5 PETN5 PETP5 BJ38 BG38 AU36 AV36 PERN6 PERP6 PETN6 PETP6 BG40 BJ40 AY40 BB40 PERN7 PERP7 PETN7 PETP7 BE38 BC38 AW38 AY38 PERN8 PERP8 PETN8 PETP8 Y40 Y39 J2 AB49 AB47 M1 AA48 AA47 PCH_GPIO11 SML0DATA SMBCLK H14 SMBCLK SML1CLK C9 SMBDATA A12 DRAMRST_CNTRL_PCH C8 SML0CLK SML0DATA G12 SML0DATA SML1ALERT# / PCHHOT# / GPIO74 C13 PCH_HOT# SML1CLK / GPIO58 E14 SML1CLK SML1DATA / GPIO75 M16 SML1DATA SMBDATA SML0ALERT# / GPIO60 SML0CLK CL_CLK1 PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P T11 CL_RST1# P10 PEG_A_CLKRQ# / GPIO47 M10 CLKOUT_PCIE3N CLKOUT_PCIE3P 10K_0402_5% CLKIN_DMI2# CLKIN_DMI2 CLKIN_DMI# CLKIN_DMI CLKIN_DOT96# CLKIN_DOT96 CLKIN_SATA# CLKIN_SATA CLK_PCH_14M 38 PCH_HOT# RH79 RH80 RH81 RH82 RH83 RH84 RH85 RH86 RH87 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% If use extenal CLK gen, please place close to CLK gen else, please place close to PCH 10K_0402_5% DIS@ RH90 10K_0402_5% UMA@ RH89 PEG_CLKREQ# CLKOUT_PEG_A_N CLKOUT_PEG_A_P AB37 AB38 CLK_PCIE_VGA# CLK_PCIE_VGA CLKOUT_DMI_N CLKOUT_DMI_P AV22 AU22 CLK_CPU_DMI# CLK_CPU_DMI CLKOUT_DP_N CLKOUT_DP_P AM12 AM13 CLKIN_DMI_N CLKIN_DMI_P BF18 BE18 CLKIN_DMI# CLKIN_DMI CLKIN_GND1_N CLKIN_GND1_P BJ30 BG30 CLKIN_DMI2# CLKIN_DMI2 CLKIN_DOT_96N CLKIN_DOT_96P G24 E24 CLKIN_DOT96# CLKIN_DOT96 CLKIN_SATA_N CLKIN_SATA_P AK7 AK5 CLKIN_SATA# CLKIN_SATA REFCLK14IN K45 CLK_PCH_14M CLKIN_PCILOOPBACK H45 CLK_PCI_LPBACK XTAL25_IN XTAL25_OUT V47 V49 XTAL25_IN XTAL25_OUT XCLK_RCOMP Y47 CLKOUTFLEX0 / GPIO64 K43 CLKOUTFLEX1 / GPIO65 F47 CLKOUTFLEX2 / GPIO66 H47 CLKOUTFLEX3 / GPIO67 K49 CLKOUT_PCIE2N CLKOUT_PCIE2P Y37 Y36 DRAMRST_CNTRL_PCH C PCIECLKRQ1# / GPIO18 PCIECLKRQ2# / GPIO20 6 DRAMRST_CNTRL_PCH M7 CL_DATA1 CLKOUT_PCIE0N CLKOUT_PCIE0P V10 PCH_GPIO25 A8 CLK_PCIE_VGA# CLK_PCIE_VGA 20 20 CLK_CPU_DMI# CLK_CPU_DMI 5 5 +3V_PCH PEG_CLKREQ# 20 VGA +3VS +3VS RH102 2.2K_0402_5% RH103 2.2K_0402_5% PCIECLKRQ3# / GPIO25 PCH_GPIO26 L12 CLKOUT_PCIE4N CLKOUT_PCIE4P SMBCLK 6 1 PCH_SMBCLK 10,11,32 2N7002DW-T/R7_SOT363-6 QH3A B 5 Y43 Y45 RH109 SML1DATA PCH_HOT# B +3V_PCH MEMORY D 2 10/100/1G LAN ---> BE34 BF34 BB32 AY32 SMBALERT# / GPIO11 E12 SMBUS EXPRESS_CARD ---> CH13 CH14 PERN1 PERP1 PETN1 PETP1 Link PCIE_PRX_EXPTX_N3 32 PCIE_PRX_EXPTX_P3 32 32 PCIE_PTX_EXPRX_N3 32 PCIE_PTX_EXPRX_P3 0.1U_0402_10V7K 0.1U_0402_10V7K BG34 BJ34 AV32 AU32 Controller MiniWLAN (Mini Card 1)---> PCIE_PRX_WLANTX_N2 32 PCIE_PRX_WLANTX_P2 32 32 PCIE_PTX_WLANRX_N2 32 PCIE_PTX_WLANRX_P2 CH9 CH12 PCIE_PRX_GLANTX_N1 PCIE_PRX_GLANTX_P1 PCIE_PTX_GLANRX_N1_C PCIE_PTX_GLANRX_P1_C CLOCKS 10/100/1G LAN ---> PCIE_PRX_GLANTX_N1 33 PCIE_PRX_GLANTX_P1 33 33 PCIE_PTX_GLANRX_N1 33 PCIE_PTX_GLANRX_P1 PCI-E* D PCIECLKRQ4# / GPIO26 SMBDATA 3 4 PCH_SMBDATA 10,11,32 2N7002DW-T/R7_SOT363-6 +3V_PCH PCH_GPIO44 @ CH25 1 2 22P_0402_50V8J +3V_PCH RH114 10K_0402_5% PCH_GPIO56 RH116 10K_0402_5% +3V_PCH RH119 10K_0402_5% PCH_GPIO45 XTAL25_IN RH117 YH2 1 2 3 GND GND 2 4 3 1 CH27 25MHZ_20PF_7V25000016 2 12P_0402_50V8J 1 15P_0402_50V8J CH26 PCH_GPIO46 CLK_BCLK_ITP# CLK_BCLK_ITP 1 7 7 CLK_RES_ITP# CLK_RES_ITP E6 CLKOUT_PEG_B_N CLKOUT_PEG_B_P 15 CLK_PCI_LPBACK PEG_B_CLKRQ# / GPIO56 V40 V42 CLKOUT_PCIE6N CLKOUT_PCIE6P T13 PCIECLKRQ6# / GPIO45 V38 V37 CLKOUT_PCIE7N CLKOUT_PCIE7P XCLK_RCOMP RH115 90.9_0402_1% +1.05VS_VCCDIFFCLKN +3VS 2 +3V_PCH XTAL25_OUT A PCIECLKRQ5# / GPIO44 AB42 AB40 Reserve for EMI please close to UH4 1M_0402_5% CLKOUT_PCIE5N CLKOUT_PCIE5P L14 QH3B RH122 RH123 @ @ 0_0402_5% 0_0402_5% K12 AK14 AK13 PCIECLKRQ7# / GPIO46 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P SML1CLK 1 PCH_SMLCLK 20,38 PCH_SMLDATA 20,38 A PANTHER-POINT_FCBGA989 SML1DATA 3 4 2N7002DW-T/R7_SOT363-6 QH4B Compal Secret Data Security Classification Issued Date 2011/05/23 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 6 2N7002DW-T/R7_SOT363-6 QH4A 5 1 10K_0402_5% FLEX CLOCKS @ RH113 CLK_PCI_LPBACK 2 33_0402_5% RH112 V45 V46 4 3 2 Title Compal Electronics, Inc. PCH (2/8) PCIE, SMBUS, CLK Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Sheet Wednesday, March 07, 2012 1 13 of 60 5 4 3 2 1 Pull high at LVDS conn side. UH1C 4 4 4 4 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 BE24 BC20 BJ18 BJ20 DMI0RXP DMI1RXP DMI2RXP DMI3RXP 4 4 4 4 4 4 4 4 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 AW24 AW20 BB18 AV18 AY24 AY20 AY18 AU18 DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI0TXP DMI1TXP DMI2TXP DMI3TXP FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI_INT +1.05VS_VCC_EXP DMI_IRCOMP 49.9_0402_1% RBIAS_CPY 750_0402_1% RH126 RH127 DMI_ZCOMP FDI_FSYNC0 AV12 FDI_FSYNC0 BG25 DMI_IRCOMP FDI_FSYNC1 BC10 FDI_FSYNC1 BH21 DMI2RBIAS FDI_LSYNC0 AV14 FDI_LSYNC0 FDI_LSYNC1 BB10 FDI_LSYNC1 DSWVRMEN A18 DSWODVREN DPWROK E22 SYSTEM_PWROK RH130 38 PCH_PWROK SYSTEM_PWROK_I 0_0402_5% PM_PWROK_R 0_0402_5% RH131 RH132 5 38 0_0402_5% PM_DRAM_PWRGD PM_DRAM_PWRGD PCH_RSMRST#_R 0_0402_5% RH134 PCH_RSMRST# SUSWARN# 38 PBTN_OUT# 20,38,47 PBTN_OUT#_R 0_0402_5% RH137 DH2 1 ACIN SUSACK# K3 SYS_RESET# P12 SYS_PWROK L22 PWROK L10 APWROK System Power Management C12 C FDI_INT BJ24 4mil width and place within 500mil of the PCH XDP_DBRESET#_R AW16 B9 WAKE# CLKRUN# / GPIO32 N3 PM_CLKRUN# SUS_STAT# / GPIO61 G8 RH128 FDI_INT 4 FDI_FSYNC0 4 FDI_FSYNC1 4 FDI_LSYNC0 4 FDI_LSYNC1 4 0_0402_5% RH129 SUSCLK PCH_RSMRST#_R 32,33 37 SUSCLK / GPIO62 N14 SLP_S5# / GPIO63 D10 PM_SLP_S5# PM_SLP_S5# 38 SLP_S4# H4 PM_SLP_S4# PM_SLP_S4# 38 SLP_S3# F4 PM_SLP_S3# PM_SLP_S3# 38 DRAMPWROK C21 RSMRST# K16 SUSWARN#/SUSPWRDNACK/GPIO30 PWRBTN# SLP_A# SUSCLK_R 0_0402_5% PCH_BL_PWM P45 L_BKLTCTL LCD_EDID_CLK LCD_EDID_DATA T40 K47 L_DDC_CLK L_DDC_DATA T45 P39 L_CTRL_CLK L_CTRL_DATA 29 29 29 2 RH245 PM_CLKRUN# RH133 L_BKLTEN L_VDD_EN PCH_ENBKL PCH_ENVDD CTRL_CLK CTRL_DATA PCIE_WAKE# 0_0402_5% PCH_ENBKL J47 M45 38 29 FDI_CTX_PRX_P04 FDI_CTX_PRX_P14 FDI_CTX_PRX_P24 FDI_CTX_PRX_P34 FDI_CTX_PRX_P44 FDI_CTX_PRX_P54 FDI_CTX_PRX_P64 FDI_CTX_PRX_P74 PCH_DPWROK WAKE# B13 E20 FDI_CTX_PRX_N04 FDI_CTX_PRX_N14 FDI_CTX_PRX_N24 FDI_CTX_PRX_N34 FDI_CTX_PRX_N44 FDI_CTX_PRX_N54 FDI_CTX_PRX_N64 FDI_CTX_PRX_N74 29 29 LCD_TXCLKLCD_TXCLK+ 29 29 29 LCD_TXOUT0LCD_TXOUT1LCD_TXOUT2- 29 29 29 LCD_TXOUT0+ LCD_TXOUT1+ LCD_TXOUT2+ 29 29 LCD_TZCLKLCD_TZCLK+ 29 29 29 LCD_TZOUT0LCD_TZOUT1LCD_TZOUT2- 29 29 29 LCD_TZOUT0+ LCD_TZOUT1+ LCD_TZOUT2+ LVDS_IBG 1 2.37K_0402_1% 38 30 30 G10 30 30 30 PCH_CRT_B PCH_CRT_G PCH_CRT_R 30 30 PCH_CRT_CLK PCH_CRT_DATA PCH_CRT_HSYNC PCH_CRT_VSYNC AF37 AF36 LVD_IBG LVD_VBG AE48 AE47 LVD_VREFH LVD_VREFL LCD_TXCLKLCD_TXCLK+ AK39 AK40 LVDSA_CLK# LVDSA_CLK LCD_TXOUT0LCD_TXOUT1LCD_TXOUT2- AN48 AM47 AK47 AJ48 LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LCD_TXOUT0+ LCD_TXOUT1+ LCD_TXOUT2+ AN47 AM49 AK49 AJ47 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LCD_TZCLKLCD_TZCLK+ AF40 AF39 LVDSB_CLK# LVDSB_CLK LCD_TZOUT0LCD_TZOUT1LCD_TZOUT2- AH45 AH47 AF49 AF45 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LCD_TZOUT0+ LCD_TZOUT1+ LCD_TZOUT2+ AH43 AH49 AF47 AF43 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 PCH_CRT_B PCH_CRT_G PCH_CRT_R N48 P49 T49 CRT_BLUE CRT_GREEN CRT_RED PCH_CRT_CLK PCH_CRT_DATA T39 M40 CRT_DDC_CLK CRT_DDC_DATA 33_0402_5% UMA@ R286 2 1PCH_CRT_HSYNC_R UMA@ R288 2 1PCH_CRT_VSYNC_R 33_0402_5% M47 M49 CRT_HSYNC CRT_VSYNC T43 T42 DAC_IREF CRT_IRTN CRT_IREF AC_PRESENT_R 2 H20 ACPRESENT / GPIO31 PCH_GPIO72 E10 BATLOW# / GPIO72 RI# A10 RI# SLP_SUS# G16 PMSYNCH AP14 Can be left NC when IAMT is not support on the platfrom RB751V-40_SOD323-2 SLP_LAN# / GPIO29 H_PM_SYNC K14 H_PM_SYNC SDVO_TVCLKINN SDVO_TVCLKINP AP43 AP45 SDVO_STALLN SDVO_STALLP AM42 AM40 SDVO_INTN SDVO_INTP AP39 AP40 SDVO_CTRLCLK SDVO_CTRLDATA Digital Display Interface DMI0RXN DMI1RXN DMI2RXN DMI3RXN LVDS BC24 BE20 BG18 BG20 UMA_HDMI_CLK 31 31 UMA_HDMI_DATA AT49 AT47 AT40 DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49 DDPC_CTRLCLK DDPC_CTRLDATA D P38 M39 DDPB_AUXN DDPB_AUXP DDPB_HPD UMA_HDMI_HPD31 UMA_HDMI_TX2UMA_HDMI_TX2+ UMA_HDMI_TX1UMA_HDMI_TX1+ UMA_HDMI_TX0UMA_HDMI_TX0+ UMA_HDMI_TXCUMA_HDMI_TXC+ UMA_HDMI_TX2-31 UMA_HDMI_TX2+31 UMA_HDMI_TX1-31 UMA_HDMI_TX1+31 UMA_HDMI_TX0-31 UMA_HDMI_TX0+31 UMA_HDMI_TXC-31 UMA_HDMI_TXC+31 P46 P42 DDPC_AUXN DDPC_AUXP DDPC_HPD AP47 AP49 AT38 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 DDPD_CTRLCLK DDPD_CTRLDATA CRT DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI D DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 FDI UH1D 4 4 4 4 DPC_HPD C M43 M36 DDPD_AUXN DDPD_AUXP DDPD_HPD AT45 AT43 BH41 DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42 DPD_HPD PANTHER-POINT_FCBGA989 5 RH138 1K_0402_0.5% PCH_GPIO29 DPC_HPD 100K_0402_5% DPD_HPD 100K_0402_5% UMA_HDMI_HPD 100K_0402_5% PANTHER-POINT_FCBGA989 Check EC for S3 S4 LED RH254 @ RH141 @ RH142 B B +3VS UMA@ RH294 UMA@ RH295 2 RH147 0_0402_5% B PCH_PWROK 1 A Y 4 SYSTEM_PWROK UMA@ RH135 UMA@ RH136 UMA@ RH139 SYSTEM_PWROK 5 DSWODVREN RH150 330K_0402_5% NC7SZ08P5X_NL_SC70-5 DSWODVREN 1 2 2.2K_0402_5% 2 2.2K_0402_5% PCH_CRT_CLK PCH_CRT_DATA * PCH_GPIO72 RH155 10K_0402_5% RI# RH157 10K_0402_5% WAKE# RH159 10K_0402_5% AC_PRESENT_R RH161 330K_0402_5% RH234 10K_0402_5% @ RH162 10K_0402_5% SUSWARN# PCH_GPIO29 RH156 1K_0402_5% PCH_RSMRST# RH163 10K_0402_5% @ 330K_0402_5% 2 150_0402_1% PCH_CRT_B 1 2 150_0402_1% PCH_CRT_G 1 2 150_0402_1% PCH_CRT_R CTRL_CLK 2 2.2K_0402_5% CTRL_DATA 1 2 2.2K_0402_5% LCD_EDID_CLK 1 2 2.2K_0402_5% LCD_EDID_DATA 1 2 2.2K_0402_5% UMA_HDMI_CLK 1 2 2.2K_0402_5% UMA_HDMI_DATA ：： RH256 8.2K_0402_5% A PM_CLKRUN# RH160 10K_0402_5% @ Compal Secret Data Security Classification Issued Date 2011/05/23 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 2 2.2K_0402_5% 1 +3VS +3VS XDP_DBRESET#_R RH151 1 1 DSWODVREN - On Die DSW VR Enable H Enable L Disable +3V_PCH A 1 +RTCVCC G VGATE 3 38,53 UH5 P 5 +3VS +3VS UMA@ R368 UMA@ R369 UMA@ R394 UMA@ R393 UMA@ R395 UMA@ R396 4 3 2 Title Compal Electronics, Inc. PCH (3/8) DMI,FDI,PM,GFX,DP Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 14 of 60 5 4 3 2 1 USB3.0 Port0 USB3.0 Port1 Port 1 : Left USB3.0 with e-SATA 43 43 USB3_RX0_N USB3_RX1_N 43 43 USB3_RX0_P USB3_RX1_P C USB3_TX0_N USB3_TX1_N 43 43 USB3_TX0_P USB3_TX1_P 43 43 38 CLK_PCI_LPBACK CLK_PCI_LPC CLK_PCI_TPM CLK_PCI_LPBACK 13 RH166 CLK_PCI_LPC RH167 37 R285 TP21 TP22 TP23 TP24 BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30 USB3Rn1 USB3Rn2 USB3Rn3 USB3Rn4 USB3Rp1 USB3Rp2 USB3Rp3 USB3Rp4 USB3Tn1 USB3Tn2 USB3Tn3 USB3Tn4 USB3Tp1 USB3Tp2 USB3Tp3 USB3Tp4 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# K40 K38 H38 G38 PCH_GPIO50 PCH_GPIO52 PCH_GPIO54 C46 C44 E40 REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 PCH_GPIO51 PCH_GPIO53 PCH_GPIO55 D47 E42 F46 GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PCH_GPIO2 PCH_GPIO3 PCH_GPIO4 PCH_GPIO5 G42 G40 C42 D44 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 K10 PME# PCH_PLTRST# B B21 M20 AY16 BG46 22_0402_5% 22_0402_5% 22_0402_5% CLK_PCI0 CLK_PCI1 CLK_PCI2 CLK_PCI3 CLK_PCI4 C6 H49 H43 J48 K42 H40 PIRQA# PIRQB# PIRQC# PIRQD# RSVD1 RSVD2 RSVD3 RSVD4 AY7 AV7 AU3 BG4 RSVD5 RSVD6 AT10 BC8 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 RSVD23 RSVD24 AV5 AV10 RSVD25 AT8 RSVD26 RSVD27 AY5 BA2 RSVD28 RSVD29 AT12 BF3 GPIO19 => BBS_BIT0 GPIO51 => BBS_BIT1 Boot BIOS Strap BBS_BIT0 BBS_BIT1 0 0 PLTRST# CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 Boot BIOS Location LPC D 0 1 Reserved(NAND) 1 0 Reserved 1 1 SPI * NV_ALE Intel Anti-Theft Techonlogy High=Endabled NV_ALE Low=Disable(floating) * +1.8VS NV_ALE PCI Port 0 : Left USB3.0 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 USB D BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45 RSVD UH1E USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USBRBIAS# C33 USBRBIAS USBRBIAS B33 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 A14 K20 B17 C16 L16 A16 D14 C14 @ RH164 1K_0402_5% Reserved for USB3.0 43 43 43 43 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB3.0 Port0 for 2.0 Port 0 : Left USB3.0 USB3.0 Port1 for 2.0 Port 1 : Left USB3.0 with e-SATA USB3.0 Port2 for 2.0 C USB3.0 Port3 for 2.0 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11 USB20_N12 USB20_P12 USB20_N13 USB20_P13 USB20_N4 USB20_P4 USB20_N5 USB20_P5 40 40 36 36 USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11 USB20_N12 USB20_P12 USB20_N13 USB20_P13 32 32 40 40 29 29 40 40 35 35 32 32 Port 4 : RHS SB USB2.0 Port 5 : Smart Card Reader +3V_PCH RPH1 Port 8 : Express Card USB_OC0# Port 9 : RHS SB USB2.0 Port 10 : Int. Carema Port 11 : Card Reader USB_OC1# USB_OC4# USB_OC3# OC6# Port 12 : Finger Print Port 13 : BT 5 6 7 8 10K_1206_8P4R_5% RPH2 4 5 3 6 2 7 1 8 10K_1206_8P4R_5% Within 500 mils RH165 4 3 2 1 EXP_CPPE# OC5# USB_OC4# 22.6_0402_1% RH174 0_0402_5% USB_OC2# USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# OC5# OC6# EXP_CPPE# USB_OC0# (For 38,43 USB_OC4# 38,40 @ RH172 10K_0402_5% USB Port0, 1) B EXP_CPPE# 32 PANTHER-POINT_FCBGA989 +3VS @ @ RH171 10K_0402_5% 8.2K_0804_8P4R_5% RH170 CH30 UH6 RPH4 1 2 3 4 PCH_GPIO53 PCI_PIRQA# 1 2 3 4 8 7 6 5 20,32,33,37,38,5PLT_RST# 4 OUT 3 PCH_GPIO51 PCH_GPIO5 PCH_GPIO52 0_0402_5% +3VS 0.1U_0402_16V4Z 5 +3VS 8 7 6 5 VCC 1 2 3 4 GND RPH3 PCH_GPIO55 PCI_PIRQB# PCI_PIRQD# PCI_PIRQC# 8.2K_0804_8P4R_5% IN1 1 IN2 2 PCH_PLTRST# MC74VHC1G08DFT2G_SC70-5 RPH5 A PCH_GPIO3 8 7 6 5 RH173 100K_0402_5% A 8.2K_0804_8P4R_5% PCH_GPIO50 RH175 10K_0402_5% PCH_GPIO54 RH176 10K_0402_5% PCH_GPIO4 RH221 10K_0402_5% PCH_GPIO2 RH224 10K_0402_5% Compal Secret Data Security Classification Issued Date 2011/05/23 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. PCH (4/8) PCI, USB, NVRAM Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 15 of 60 5 4 3 2 1 +3VS PCH_GPIO0 10K_0402_5% RH177 UH1F PCH_GPIO36 10K_0402_5% RH178 @ 10K_0402_5% PCH_GPIO16 PCH_GPIO0 T7 PCH_GPIO34 PCH_GPIO1 A42 KB_RST# PCH_GPIO6 H36 RH179 10K_0402_5% RH180 10K_0402_5% PCH_GPIO48 38 RH181 PCH_GPIO22 10K_0402_5% 38 RH185 10K_0402_5% PCH_GPIO17 RH186 PID0 PID1 PID2 TACH2 / GPIO6 TACH6 / GPIO70 E38 TACH3 / GPIO7 TACH7 / GPIO71 A40 PCH_SMI# PCH_SMI# C10 GPIO8 PCH_GPIO12 EC_LID_OUT# EC_LID_OUT# ODD_EN# B41 EC_SCI# RH183 WOSC@ 10K_0402_5% C40 TACH5 / GPIO69 EC_SCI# ODD_EN# 10K_0402_5% TACH4 / GPIO68 TACH1 / GPIO1 C41 RH184 10K_0402_5% D BMBUSY# / GPIO0 38 RH88 LID_SW_OUT# 0_0402_5% PCH_GPIO16 LAN_PHY_PWR_CTRL / GPIO12 G2 GPIO15 U2 A20GATE PECI SATA4GP / GPIO16 @ RH192 10K_0402_5% RH193 10K_0402_5% RH194 10K_0402_5% RH195 10K_0402_5% RH197 PCH_GPIO22 PCH_GPIO37 10K_0402_5% E16 GPIO27 PCH_GPIO28 P8 GPIO28 PCH_GPIO49 PCH_GPIO34 K1 STP_PCI# / GPIO34 PCH_GPIO6 PCH_GPIO35 K4 GPIO35 PCH_GPIO36 V8 PCH_GPIO37 M5 SATA3GP / GPIO37 PCH_GPIO38 N2 SLOAD / GPIO38 PCH_GPIO39 M3 SDATAOUT0 / GPIO39 PCH_GPIO48 V13 PCH_GPIO57 RH203 38 H_CPUPWRGD 5 THRMTRIP# AY10 @ RH201 T14 DF_TVS AY1 TS_VSS1 AH8 TS_VSS2 AK11 TS_VSS3 AH10 TS_VSS4 AK10 NC_1 P37 SDATAOUT1 / GPIO48 VSS_NCTF_15 BG2 VSS_NCTF_16 BG48 GPIO57 VSS_NCTF_17 BH3 VSS_NCTF_18 BH47 VSS_NCTF_19 BJ4 PCH_GPIO12 B VSS_NCTF_1 A44 VSS_NCTF_2 VSS_NCTF_20 BJ44 A45 VSS_NCTF_3 VSS_NCTF_21 BJ45 VSS_NCTF_22 BJ46 A46 VSS_NCTF_4 A5 VSS_NCTF_5 VSS_NCTF_23 BJ5 A6 VSS_NCTF_6 VSS_NCTF_24 BJ6 B3 VSS_NCTF_7 VSS_NCTF_25 C2 B47 VSS_NCTF_8 VSS_NCTF_26 C48 BD1 VSS_NCTF_9 VSS_NCTF_27 D1 BD49 VSS_NCTF_10 VSS_NCTF_28 D49 BE1 VSS_NCTF_11 VSS_NCTF_29 E1 BE49 VSS_NCTF_12 VSS_NCTF_30 E49 BF1 VSS_NCTF_13 VSS_NCTF_31 F1 VSS_NCTF_32 F49 BF49 H_THERMTRIP# H_THERMTRIP# RH191 5 5 INIT3_3V NV_CLE H_SNB_IVB# RH189 CLOSE TO THE BRANCHING POINT RH149 and RH150 Follow CRB FAB2 setting This signal has weak internal PU, can't pull low C SATA5GP / GPIO49 / TEMP_ALERT# A4 H_THERMTRIP#_C 390_0402_5% RH187 2.2K_0402_5% NV_CLE 1K_0402_5% +3VS NCTF @ RH200 INIT3_3V# D Weak internal PU,Do not pull low+1.8VS 38,5 H_PECI RH188 KB_RST# V3 PCH_GPIO37 100K_0402_5% PCH_GPIO27 10K_0402_5% PCH_GPIO35 10K_0402_5% PCH_GPIO38 10K_0402_5% @ 0_0402_5% AY11 D6 RH207 RH198 PCH_PECI_R P5 SATA2GP / GPIO36 RH205 @ RH199 A20M# AU16 PCH_GPIO57 PCH_SMI# 10K_0402_5% P4 PCH_GPIO49 LID_SW_OUT# RH204 10K_0402_5% GPIO24 PCH_GPIO27 RH202 10K_0402_5% SCLOCK / GPIO22 PCH_GPIO39 PCH_GPIO28 10K_0402_5% T5 E8 PCH_GPIO38 +3V_PCH C TACH0 / GPIO17 CPU/MISC RH190 10K_0402_5% GPIO PCH_GPIO1 10K_0402_5% D40 DMI Termination Voltage Set to Vcc when HIGH NV_CLE Set to Vss when LOW +3VS PROCPWRGD RCIN# PCH_GPIO17 36 @ RH182 10K_0402_5% C4 EC_SCI# RH208 ODD_EN# VSS_NCTF_14 31@ RH301 10K_5% 50@ RH301 10K_5% 51@ RH301 10K_5% 31@ RH303 10K_5% 50@ RH302 10K_5% 51@ RH302 10K_5% PANTHER-POINT_FCBGA989 31@ RH304 10K_5% 50@ RH305 10K_5% 51@ RH304 10K_5% ID@ RH301 10K_0402_5% PID2 ID@ RH300 10K_0402_5% ID@ RH303 10K_0402_5% PID1 ID@ RH302 10K_0402_5% ID@ RH305 10K_0402_5% PID0 ID@ RH304 10K_0402_5% PID : 210 QAL30 000 QAL31 001 QAL50 010 QAL51 011 KSPD Q0000 1XX (UMA) (DIS) (UMA) (DIS) B GPIO28 On-Die PLL Voltage Regulator This signal has a weak internal pull up * H L ： voltage regulator enable ：On-Die On-Die PLL Voltage Regulator disable PCH_GPIO28 @ RH206 PCH_GPIO28 needs to be connected to XDP_FN8 PCH_GPIO35 needs to be connected to XDP_FN9 PCH_GPIO15 needs to be connected to XDP_FN16 Please refer to Huron River Debug Board DG 1.2 1K_0402_5% A A Compal Secret Data Security Classification Issued Date 2011/05/23 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. PCH (5/8) GPIO, CPU, MISC Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 16 of 60 5 4 3 2 1 +3VS +VCCADAC POWER UH1G UMA@ PJPH1 +V1.05S_VCCP RH209 +1.05VS_VCCDPLLEXPAN19 0_0603_5% VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17] 1mA VCCADAC U48 VSSADAC U47 CRT AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31 2 2 1 2 VSSALVDS VCCTX_LVDS[1] VCCTX_LVDS[2] 40mAVCCTX_LVDS[3] VCCTX_LVDS[4] AK36 +VCCALVDS AK37 UMA@ 1 C299 AM37 +VCCTX_LVDS AM38 AP36 PCH Power Rail Table Refer to CPU EDS R1.5 1 L13 0_0603_5% 2 1 RH227 0_0603_5% UMA@ C289 10U_0603_6.3V6M TEST@ L13 BLM18PG181SN1D_2P R332 UMA@ +3VS 0_0603_5% 1 2 +1.8VS L21 UMA@ 0.1UH_MLF1608DR10KT_10%_1608 2 1 0.1uH inductor, 200mA 1 UMA@ C295 C297 22U_0805_6.3V6M 0_0402_5% 2 DIS@ 2 0.1U_0402_10V7K UMA@ C296 .01U_0402_16V7K UMA@ C297 .01U_0402_16V7K AP37 1 2 AN16 CH41 10U_0805_6.3V6M AN17 VCCAPLLEXP VCCIO[15] VCCIO[16] +V1.05S_VCCP RH212 0_0805_5% AN27 +1.05VS_VCC_EXP AP21 C CH47 1U_0402_6.3V6K CH43 10U_0805_6.3V6M 2 AP23 CH46 1U_0402_6.3V6K 1 +3VS CH45 1U_0402_6.3V6K CH44 1U_0402_6.3V6K +1.05VS_VCC_EXP RH215 0_0805_5% +3VS_VCCA3GBG AP24 AP26 AT24 VCCIO[17] VCCIO[19] 3709mA VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCDMI[1] VCC3_3[3] 0.1U_0402_10V7K Place CH53 Near BG6 pin +1.05VS_VCCAPLL_FDI 0_0603_5% @ B +V1.05S_VCCP 0.001 V5REF 5 0.001 V5REF_Sus 5 0.001 Vcc3_3 3.3 0.228 VccADAC 3.3 0.001 VccADPLLA 1.05 0.075 VccADPLLB 1.05 0.075 VccCore 1.05 1.3 VccDMI 1.05 0.042 VccIO 1.05 3.709 VccASW 1.05 0.903 VccSPI 3.3 0.01 VccDSW 3.3 0.001 VccDFTERM 1.8 0.002 VccRTC 3.3 6 uA VccSus3_3 3.3 0.065 +1.5VS VCCVRM[2] VccAFDIPLL AT20 RH213 AB36 +V1.05S_VCCP C +VCCP_VCCDMI 0_0805_5% CH48 +V1.05S_VCCP +1.05VS_VCC_DMI_CCI 1U_0402_6.3V6K 0_0805_5% CH49 1U_0402_6.3V6K 2mA VCCDFTERM[2] VCCDFTERM[3] VCCDFTERM[4] AG16 VccSusHDA 3.3 / 1.5 VccVRM 1.8 / 1.5 0.01 +VCCPNAND AG17 RH216 0_0805_5% AJ16 AJ17 0.167 +1.8VS VccCLKDMI 1.05 0.075 VccSSC 1.05 0.095 VccDIFFCLKN 1.05 0.055 VccALVDS 3.3 0.001 VccTX_LVDS 1.8 0.04 RH218 +1.05VS_VCCDPLL_FDIAP17 0_0805_5% +VCCP_VCCDMI AU20 VCCIO[27] VCCDMI[2] @ FDI CH52 1U_0402_6.3V6K RH217 BG6 AT16 RH214 75mA VCCCLKDMI VCCDFTERM[1] +V1.05S_VCCP @ VCCVRM[3] VCCIO[21] AN34 AP16 CH42 0.1U_0402_10V7K V34 +VCCP_VCCDMI CH50 +1.5VS VCC3_3[7] +3VS 0_0805_5% VCCIO[20] AN33 BH29 VCC3_3[6] +3VS_VCC3_3_6 VCCIO[18] DFT / SPI AN26 VCCIO AN21 1.05 RH211 V33 CH51 0.1U_0402_10V7K @ Place C2011 Near BJ22 pin BJ22 HVCMOS +VCCAPLLEXP S0 Iccmax Current (A) VCCIO[28] DMI +VCCAPLLEXP_R1 2 0_0603_5% 1UH_LB2012T1R0M_20% @ Voltage D @ LH3 RH210 Voltage Rail V_PROC_IO DIS@ C299 0_0402_5% 1mAVCCALVDS LVDS +V1.05S_VCCP 1300mA VCC CORE D CH34 1U_0402_6.3V6K PAD-OPEN 4x4m 1 @ CH32 10U_0805_6.3V6M 2 CH33 1U_0402_6.3V6K +1.05VS_VCCCORE 1 CH31 1U_0402_6.3V6K 2 1 C294 0.1U_0402_10V7K +1.05VS_VCCCORE C287 .01U_0402_16V7K +V1.05S_VCCP 10mA VCCSPI V1 +3V_VCCPSPI RH219 CH53 RH220 1U_0402_6.3V6K PANTHER-POINT_FCBGA989 +3V_PCH 0_0805_5% 0_0603_5% +3VS B Intel recommand VCCVRM==>1.5V FOR MOBILE A A Compal Secret Data Security Classification Issued Date 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. PCH (6/8) PWR Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 17 of 60 5 4 3 2 1 @ JPH1 0_0603_5% POWER UH1J 3 +VCCSUS1 AL24 @ CH54 1U_0402_6.3V6K 1 2 AA26 CH65 22U_0805_6.3V6M AA27 AA29 AC26 CH69 1U_0402_6.3V6K CH67 1U_0402_6.3V6K AC27 AC29 AC31 AD29 +3VS RH239 0_0805_5% AD31 W21 LH5 10UH_LBR2012T100M_20% +3VS_VCC_CLKF33 1 2 @ W23 CH74 1U_0402_6.3V6K CH73 10U_0805_10V4Z VCCSUS3_3[9] DCPSUS[3] VCCSUS3_3[10] W24 W26 W29 W31 W33 VCCASW[1] VCCIO[34] 903mA +VCCRTCEXT 1mA VCCASW[3] VCCASW[4] VCCASW[5] VCCASW[6] VCCASW[7] VCCASW[8] VCCASW[9] VCCASW[10] VCCASW[11] VCCASW[12] VCCASW[13] VCCASW[14] VCCASW[15] V5REF_SUS DCPSUS[4] VCCSUS3_3[1] 1mA V5REF VCCSUS3_3[2] CH78 0.1U_0402_10V7K Y49 +1.5VS BD47 +1.05VS_VCCA_B_DPL 0_0603_5% BF47 +1.05VS_VCCDIFFCLKN +1.05VS_VCCDIFFCLKN RH247 0_0603_5% +1.05VS_SSCVCC CH81 1U_0402_6.3V6K +V1.05S_VCCP AG33 +VCCSST CH85 0.1U_0402_10V7K 0_0603_5% CH86 4.7U_0603_6.3V6K A +V1.05S_VCCP LH8 1 2 0_0603_5% +1.05VS_VCCA_A_DPL 1 + TEST@ LH7 10UH_LBR2012T100M_20% TEST@ LH8 10UH_LBR2012T100M_20% 5 2 @ +1.05VS_VCCA_B_DPL 1 + 2 @ CH96 1U_0402_6.3V6K 2 0_0603_5% CH95 220U_B2_2.5VM_R35 1 CH94 1U_0402_6.3V6K LH7 CH93 220U_B2_2.5VM_R35 +V1.05S_VCCP 2 +VCCA_USBSUS A22 VCC3_3[2] VCCASW[20] DCPRTC VCCVRM[4] VCCIO[13] VCCIO[6] VCCADPLLA75mA VCCADPLLB75mA VCCAPLLSATA VCCVRM[1] VCCIO[7] VCCDIFFCLKN[1] 55mA VCCDIFFCLKN[2] VCCDIFFCLKN[3] VCCIO[2] VCCSSC95mA AN24 P34 +PCH_V5REF_SUS CH63 .1U_0603_25V7K +PCH_V5REF_RUN N20 CH70 1U_0402_6.3V6K C DH4 RB751S40T1_SOD523-2 +3VS +PCH_V5REF_RUN 1 +3VS_VCCPCORE RH238 0_0805_5% 2 CH72 0.1U_0402_10V7K CH71 1U_0402_10V6K +3VS W16 T34 +3VS RH237 10_0402_5% +3V_PCH AA16 +3VS_VCCPPCI RH240 AJ2 +VCC3_3_2 0_0603_5% CH75 0.1U_0402_10V7K +1.05VS_SATA3 DCPSUS[1] DCPSUS[2] 1mA +1.05VS_SATA3 AH14 B AF14 AK1 AF11 AC16 AC17 VCCIO[4] AD17 VCCASW[23] VCCASW[21] 10mA VCCSUSHDA +1.5VS +1.05VS_VCC_SATA RH246 +1.05VS_VCC_SATA +V1.05S_VCCP 0_0805_5% +V1.05S_VCCP T21 V21 T19 P32 PANTHER-POINT_FCBGA989 Issued Date +V1.05S_VCCP 0_0805_5% CH77 1U_0402_6.3V6K AH13 VCCIO[3] VCCASW[22] RH242 0_0603_5% CH76 0.1U_0402_10V7K AF13 +VCCSUSHDA +3V_PCH RH250 0_0402_5% A Compal Secret Data Security Classification 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 DH3 RB751S40T1_SOD523-2 0.1U_0402_10V7K DCPSST VCCRTC RH232 10_0402_5% RH241 VCCASW[19] V_PROC_IO +3V_PCH +3V_PCH VCCASW[18] +RTCVCC CH91 1U_0402_6.3V6K RH249 BJ8 CH90 0.1U_0402_10V7K +V_CPU_IO T17 V19 @ CH83 1U_0402_6.3V6K CH89 0.1U_0402_10V7K CH87 0.1U_0402_10V7K CH84 1U_0402_6.3V6K +V1.05S_VCCP AN23 +1.05VM_VCCSUS 0_0603_5% CH88 0.1U_0402_10V7K RH248 V16 M26 +V1.05S_VCCP 0_0603_5% +3VS CPU 1U_0402_6.3V6K +5V_PCH +VCCA_USBSUS VCCASW[17] RTC +V1.05S_VCCP RH233 VCCSUS3_3[5] VCC3_3[4] CH79 AF17 AF33 AF34 AG34 +3V_PCH +1.05VS_VCCAUPLL +PCH_V5REF_SUS P22 VCC3_3[8] MISC RH244 T26 P20 VCC3_3[1] SATA +1.05VS_VCCA_A_DPL P24 N22 +V1.05S_VCCP +VCCDIFFCLK V24 VCCSUS3_3[4] VCCASW[16] HDA B V23 VCCSUS3_3[3] VCCIO[12] 0_0603_5% T24 +5VS +1.05VM_VCCSUS @ RH243 N16 T23 VCCASW[2] VCCIO[5] +V1.05S_VCCP T29 CH92 0.1U_0402_10V7K C CH68 1U_0402_6.3V6K AA31 +V1.05S_VCCP VCCIO[14] PCI/GPIO/LPC AA19 AA24 1 VCCSUS3_3[8] VCCSUS3_3[6] AA21 CH64 22U_0805_6.3V6M 2 VCCSUS3_3[7] 119mA VCCAPLLDMI2 D PCH_PWR_EN# CH66 AL29 +V1.05S_VCCP DcpSus and DcpSusByp do not require Decoupling. Stuffing Decoupling Caps may cause voltage oscillations, when Internal 1.05 Voltage Regulator is used. By CPET BH23 VCCIO[33] USB +VCCAPLL_CPY_PCH +V1.05S_VCCP VCCIO[32] 44 2 VCC3_3[5] CH56 1U_0402_6.3V6K 1 T38 T27 2 DCPSUSBYP +3VS_VCC_CLKF33 P28 1 V12 P26 VCCIO[31] 1 +V1.05S_VCCP @ CH62 1U_0402_6.3V6K +PCH_VCCDSW Clock and Miscellaneous @ CH58 0.1U_0402_10V7K VCCIO[30] VCCDSW3_33mA N26 CH82 1U_0402_6.3V6K T16 D VCCIO[29] CH61 0.1U_0402_10V7K CH55 0.1U_0402_10V7K VCCACLK CH60 0.1U_0402_10V7K AD49 RH3 20K_0402_5% QH2 AO3413L_SOT23-3 +VCCACLK @ @ RH226 0_0805_5% +5V_PCH PAD-OPEN 2x2m RH223 +3VALW 1 CH6 0.1U_0402_10V7K 2 +5VALW +V1.05S_VCCP 3 2 Title Compal Electronics, Inc. PCH (7/8) PWR Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 18 of 60 5 4 3 2 1 UH1I AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3 UH1H D H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3 C B VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28 PANTHER-POINT_FCBGA989 A VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28 D C B A PANTHER-POINT_FCBGA989 Compal Secret Data Security Classification Issued Date 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. PCH (8/8) VSS Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 19 of 60 B C D 56 DIS@ UV4A @RV48 @ RV48 0_0402_5% PEX_TSTCLK_OUT+ PEX_TSTCLK_OUT200_0402_1% 3 @ RV36 15,32,33,37,38,5 PLT_RST# PEX_TREMP 2.49K_0402_1% RV37 DIS@ RV33 DIS@ 0_0402_5% DIS@ RV154 DIS@ RV155 DIS@ RV156 VGA_CRT_HSYNC VGA_CRT_VSYNC I2CA_SCL I2CA_SDA R4 R5 VGA_CRT_CLK VGA_CRT_DATA I2CB_SCL I2CB_SDA R7 R6 I2CB_SCL I2CB_SDA I2CS_SCL I2CS_SDA VGA_CRT_CLK 30 VGA_CRT_DATA 30 PLLVDD PEX_WAKE_N VGA_LCD_CLK29 29 VGA_LCD_DATA AJ26 AK26 SM010018510--SM01000FE00-SM010007W00-- PEX_TSTCLK_OUT PEX_TSTCLK_OUT_N AJ12 AP29 PEX_RST_N PEX_TERMP DIS@ +GPU_PLLVDD AD7 VID_PLLVDD XTAL_IN XTAL_OUT H3 H2 XTALIN XTALOUT XTAL_OUTBUFF XTAL_SSIN J4 H1 XTAL_OUTBUFF XTAL_SSIN CRT 10K_0402_5% 1 RV175 RV176 10K_0402_5% RV174 RV173 RV172 @ 10K_0402_5% DIS@ 10K_0402_5% DIS@ 10K_0402_5% DIS@ 10K_0402_5% DIS@ 10K_0402_5% RV171 @ 56 56 56 56 56 56 3 3 GND 2 4 YV1 27MHZ_16PF_7V27000011 GPIO5 O GPU Core VID1 GPIO6 O GPU Core VID2 GPIO7 O 3D Vision GPIO8 I/O OVERT GPIO9 I/O ALERT GPIO10 O MEM_VREF_CTL GPIO11 O GPU Core VID0 GPIO12 I PWR_LEVEL GPIO13 O GPU Core VID5 GPIO14 I HPD_AB GPIO15 I HPD_C GPIO16 O MEM_VDD_CTL GPIO17 I HPD_D GPIO18 I HPD_E GPIO19 I HPD_F 1 GPIO20 Reserved GPIO21 Reserved 2 DIS@ DIS@ CV42, CV43, CV44 LV10 Near GPU 3 DIS@ 1 DIS@ 2 +V1.05S_VCCP BLM18PG181SN1D_2P DIS@ VGA_CRT_CLK RV38 DIS@ VGA_CRT_DATA RV39 DIS@ 2.2K_0402_5% 2.2K_0402_5% I2CB_SCL I2CB_SDA RV41 RV42 DIS@ DIS@ 2.2K_0402_5% 2.2K_0402_5% VGA_LCD_CLK RV43 VGA_LCD_DATA RV44 DIS@ DIS@ 2.2K_0402_5% 2.2K_0402_5% I2CS_SCL I2CS_SDA DIS@ DIS@ 2.2K_0402_5% 2.2K_0402_5% VGA_PNL_PWM@ RV53 VGA_ENVDD RV54 DIS@ VGA_BKL_EN RV56 DIS@ 10K_0402_5% 10K_0402_5% 10K_0402_5% XTAL_OUTBUFF RV45 DIS@ XTAL_SSIN RV52 DIS@ 10K_0402_5% 10K_0402_5% RV46 RV47 DIS@ CV47 18P_0402_50V8J CV38,CV40 under GPU close to ball : AE8,AD7 CV311, CV310, LV18 Near GPU 2 +3VS 4 I2CS_SCL 1 6 DMN66D0LDW-7_SOT363-6 DIS@ QV6A @RV35 @ RV35 PCH_SMLCLK 13,38 I2CS_SCL 0_0402_5% 4 @RV40 @ RV40 3 QV6B DIS@ B I2CS_SDA 0_0402_5% PCH_SMLDATA 13,38 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification +3VS I2CS_SDA A 1 DIS@ DIS@ GPU_VID0 GPU_VID1 GPU_VID2 GPU_VID3 GPU_VID4 GPU_VID5 4 1M_0402_5% GND 5 10K_0402_5% 10K_0402_5% 10K_0402_5% GPU_VID0 GPU_VID1 GPU_VID2 GPU_VID3 GPU_VID4 GPU_VID5 XTALIN @ DIS@ CV46 18P_0402_50V8J RV163 DIS@ RV164 DIS@ RV162 10K_0402_5% @ RV161 RV159 RV160 10K_0402_5% +3VS @ DIS@ +GPU_PLLVDD CV38 0.1U_0402_16V4Z 100mA RV55 LCD_BLEN +3VS N13P-PES-A1_FCBGA908 @ 30R@100MHz(ESR=0.5) +V1.05S_VCCP DIS@ LV10 1 2 BLM18PG330SN1D_0603 DIS@ LV18 XTALOUT O CV41 under GPU close to ball : AD8 +GPU_PLLVDD @ +3VS LVDS +PLLVDD AE8 SP_PLLVDD PEX_REFCLK PEX_REFCLK_N PEX_CLKREQ_N Design Guide page160 = 220R@100MHz(ESR=0.05) DIS@ LV9 under GPU 150mA +PLLVDD NC7SZ08P5X_NL_SC70-5 1 2 BLM18PG181SN1D_2P +PLLVDD AD8 LCD_VCC GPIO4 P 3 CRT reserved for A-test only I2CS_SCL I2CS_SDA T4 T3 LCD_BL_PWM O 38 150_0402_1% 150_0402_1% 150_0402_1% 120mA VGA_LCD_CLK VGA_LCD_DATA R2 R3 I2CC_SCL I2CC_SDA O GPIO3 14,38,47 P8_Throttling 30 30 30 VGA_CRT_HSYNC30 VGA_CRT_VSYNC30 +DACA_VDD DACA_VREF DACA_RSET AG10 AP9 AP8 DACA_VDD DACA_VREF DACA_RSET GPIO2 ACIN 1 DIS@ CV36 4.7U_0603_6.3V6K AM9 AN9 DACA_HSYNC DACA_VSYNC VGA_CRT_R VGA_CRT_G VGA_CRT_B GPU Core VID3 2 VGA_HDMI_HPD31 DIS@ CV34 0.1U_0402_16V4Z AK9 AL10 AL9 GPU Core VID4 DPRSLPVR_VGA56 dGPU_HDMI_HPD VGA_CRT_R VGA_CRT_G VGA_CRT_B DACA_RED DACA_GREEN DACA_BLUE O G 5 DPRSLPVR_VGA O GPIO1 A CV44 22U_0805_6.3V6M AL13 AK13 PEG_CLKREQ#_R AK12 USAGE GPIO0 B +3VS CV43 22U_0805_6.3V6M CLK_PCIE_VGA CLK_PCIE_VGA# 13 13 I/O U4903 Y CV310 22U_0805_6.3V6M PEG_CLKREQ# 10K_0402_5% DIS@ 330K_0402_5% RH168 4 +3VS CV311 4.7U_0402_6.3V6M 13 DIS@ RV177 10K_0402_5% 10K_0402_5% CV42 4.7U_0402_6.3V6M AJ11 +3VS DIS@ RV29 DIS@ RV30 GPU_VID0 ACIN_BUF GPU_VID5 +3VL CV41 0.1U_0402_16V4Z PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N GPIO AK14 AJ14 AH14 AG14 AK15 AJ15 AL16 AK16 AK17 AJ17 AH17 AG17 AK18 AJ18 AL19 AK19 AK20 AJ20 AH20 AG20 AK21 AJ21 AL22 AK22 AK23 AJ23 AH23 AG23 AK24 AJ24 AL25 AK25 0.22U_0402_10V6K PCIE_GTX_CRX_P0 0.22U_0402_10V6K PCIE_GTX_CRX_N0 0.22U_0402_10V6K PCIE_GTX_CRX_P1 0.22U_0402_10V6K PCIE_GTX_CRX_N1 0.22U_0402_10V6K PCIE_GTX_CRX_P2 0.22U_0402_10V6K PCIE_GTX_CRX_N2 0.22U_0402_10V6K PCIE_GTX_CRX_P3 0.22U_0402_10V6K PCIE_GTX_CRX_N3 0.22U_0402_10V6K PCIE_GTX_CRX_P4 0.22U_0402_10V6K PCIE_GTX_CRX_N4 0.22U_0402_10V6K PCIE_GTX_CRX_P5 0.22U_0402_10V6K PCIE_GTX_CRX_N5 0.22U_0402_10V6K PCIE_GTX_CRX_P6 0.22U_0402_10V6K PCIE_GTX_CRX_N6 0.22U_0402_10V6K PCIE_GTX_CRX_P7 0.22U_0402_10V6K PCIE_GTX_CRX_N7 0.22U_0402_10V6K PCIE_GTX_CRX_P8 0.22U_0402_10V6K PCIE_GTX_CRX_N8 0.22U_0402_10V6K PCIE_GTX_CRX_P9 0.22U_0402_10V6K PCIE_GTX_CRX_N9 0.22U_0402_10V6K PCIE_GTX_CRX_P10 0.22U_0402_10V6K PCIE_GTX_CRX_N10 0.22U_0402_10V6K PCIE_GTX_CRX_P11 0.22U_0402_10V6K PCIE_GTX_CRX_N11 0.22U_0402_10V6K PCIE_GTX_CRX_P12 0.22U_0402_10V6K PCIE_GTX_CRX_N12 0.22U_0402_10V6K PCIE_GTX_CRX_P13 0.22U_0402_10V6K PCIE_GTX_CRX_N13 0.22U_0402_10V6K PCIE_GTX_CRX_P14 0.22U_0402_10V6K PCIE_GTX_CRX_N14 0.22U_0402_10V6K PCIE_GTX_CRX_P15 0.22U_0402_10V6K PCIE_GTX_CRX_N15 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ GPIO VGA_PNL_PWM 29 29 VGA_ENVDD 38 VGA_BKL_EN CV40 0.1U_0402_16V4Z 2 CV309 CV290 CV286 CV306 CV295 CV288 CV293 CV298 CV278 CV305 CV285 CV308 CV284 CV292 CV281 CV279 CV302 CV291 CV283 CV299 CV301 CV303 CV289 CV296 CV297 CV287 CV307 CV304 CV280 CV294 CV282 CV300 1 DV6 CH751H-40PT_SOD323-2 DIS@ DIS@ CV33 0.1U_0402_16V4Z PCIE_GTX_C_CRX_P0 PCIE_GTX_C_CRX_N0 PCIE_GTX_C_CRX_P1 PCIE_GTX_C_CRX_N1 PCIE_GTX_C_CRX_P2 PCIE_GTX_C_CRX_N2 PCIE_GTX_C_CRX_P3 PCIE_GTX_C_CRX_N3 PCIE_GTX_C_CRX_P4 PCIE_GTX_C_CRX_N4 PCIE_GTX_C_CRX_P5 PCIE_GTX_C_CRX_N5 PCIE_GTX_C_CRX_P6 PCIE_GTX_C_CRX_N6 PCIE_GTX_C_CRX_P7 PCIE_GTX_C_CRX_N7 PCIE_GTX_C_CRX_P8 PCIE_GTX_C_CRX_N8 PCIE_GTX_C_CRX_P9 PCIE_GTX_C_CRX_N9 PCIE_GTX_C_CRX_P10 PCIE_GTX_C_CRX_N10 PCIE_GTX_C_CRX_P11 PCIE_GTX_C_CRX_N11 PCIE_GTX_C_CRX_P12 PCIE_GTX_C_CRX_N12 PCIE_GTX_C_CRX_P13 PCIE_GTX_C_CRX_N13 PCIE_GTX_C_CRX_P14 PCIE_GTX_C_CRX_N14 PCIE_GTX_C_CRX_P15 PCIE_GTX_C_CRX_N15 GPU_VID4 GPU_VID3 VGA_PNL_PWM VGA_ENVDD VGA_BKL_EN GPU_VID1 GPU_VID2 P6 M3 L6 P5 P7 L7 M7 N8 M1 M2 L1 M5 N3 M4 N4 P2 R8 M6 R1 P3 P4 P1 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 DACs PCIE_CTX_C_GRX_N[0..15] 4 PCIE_CTX_C_GRX_N[0..15] E 2 Part 1 of 7 I2C PCIE_CTX_C_GRX_P[0..15] 4 PCIE_CTX_C_GRX_P[0..15] PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N CLK PCIE_GTX_C_CRX_N[0..15] 4 PCIE_GTX_C_CRX_N[0..15] AN12 AM12 AN14 AM14 AP14 AP15 AN15 AM15 AN17 AM17 AP17 AP18 AN18 AM18 AN20 AM20 AP20 AP21 AN21 AM21 AN23 AM23 AP23 AP24 AN24 AM24 AN26 AM26 AP26 AP27 AN27 AM27 PCI EXPRESS PCIE_GTX_C_CRX_P[0..15] 4 PCIE_GTX_C_CRX_P[0..15] 1 PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_N8 PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_P15 PCIE_CTX_C_GRX_N15 ACIN_BUF ACIN_BUF RV34 124_0402_1% DIS@ A 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C D Title N13P PEG 1/9 Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Sheet Wednesday, March 07, 2012 E 20 of 60 A VRAM Interface MDA[15..0] MDA[15..0] 25 MDC[31..16] MDC[31..16] 27 MDA[47..32] MDA[47..32] 26 MDC[47..32] MDC[47..32] 28 MDA[63..48] MDA[63..48] 26 MDC[63..48] MDC[63..48] 28 DIS@ UV4C DQSA[3..0] DQSA[7..4] DQSA#[3..0] DQSA#[7..4] 25 DQSA0 DQSA1 DQSA2 DQSA3 26 DQSA4 DQSA5 DQSA6 DQSA7 M31 G31 E33 M33 AE31 AK30 AN33 AF33 25 DQSA#0 DQSA#1 DQSA#2 DQSA#3 26 DQSA#4 DQSA#5 DQSA#6 DQSA#7 M30 H30 E34 M34 AF30 AK31 AM34 AF32 FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 RV59 DIS@ DIS@ FBA_CLK0 FBA_CLK0_N FBA_CLK1 FBA_CLK1_N R30 R31 AB31 AC31 FBA_WCK01 FBA_WCK01_N FBA_WCK23 FBA_WCK23_N FBA_WCK45 FBA_WCK45_N FBA_WCK67 FBA_WCK67_N K31 L30 H34 J34 AG30 AG31 AJ34 AK34 FBA_WCKB01 FBA_WCKB01_N FBA_WCKB23 FBA_WCKB23_N FBA_WCKB45 FBA_WCKB45_N FBA_WCKB67 FBA_WCKB67_N 60.4_0402_1% CLKA0 CLKA0# CLKA1 CLKA1# 25 25 26 26 J30 J31 J32 J33 AH31 AJ31 AJ32 AJ33 27 DQMC0 DQMC1 DQMC2 DQMC3 28 DQMC4 DQMC5 DQMC6 DQMC7 DQMC[3..0] DQMC[7..4] DQSC[3..0] FB_CLAMP E1 DQSC[7..4] FB_DLL_AVDD K27 100mA +FB_PLLAVDD 100mA FBA_PLL_AVDD FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7 R28 FBA_DEBUG0 AC28 FBA_DEBUG1 FB_VREF U27 H26 DQSC#[3..0] +FB_PLLAVDD DIS@ CV49 0.1U_0402_16V4Z DQSC#[7..4] E11 E3 A3 C9 F23 F27 C30 A24 FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7 27 DQSC0 DQSC1 DQSC2 DQSC3 28 DQSC4 DQSC5 DQSC6 DQSC7 D10 D5 C3 B9 E23 E28 B30 A23 27 DQSC#0 DQSC#1 DQSC#2 DQSC#3 28 DQSC#4 DQSC#5 DQSC#6 DQSC#7 FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7 D9 E4 B2 A9 D22 D28 A30 B23 FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3 FBB_DQS_RN4 FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7 D13 E14 F14 A12 B12 C14 B14 G15 F15 E15 D15 A14 D14 A15 B15 C17 D18 E18 F18 A20 B20 C18 B18 G18 G17 F17 D16 A18 D17 A17 B17 E17 FBB_CMD_RFU0 FBB_CMD_RFU1 C12 C20 CMDC0 CMDC1 CMDC2 CMDC3 CMDC4 CMDC5 CMDC6 CMDC7 CMDC8 CMDC9 CMDC10 CMDC11 CMDC12 CMDC13 CMDC14 CMDC15 CMDC16 CMDC17 CMDC18 CMDC19 CMDC20 CMDC21 CMDC22 CMDC23 CMDC24 CMDC25 CMDC26 CMDC27 CMDC28 CMDC29 CMDC30 DIS@ RV58 FBB_DEBUG0 FBB_DEBUG1 FBB_CLK0 FBB_CLK0_N FBB_CLK1 FBB_CLK1_N FBB_WCK01 FBB_WCK01_N FBB_WCK23 FBB_WCK23_N FBB_WCK45 FBB_WCK45_N FBB_WCK67 FBB_WCK67_N FBB_WCKB01 FBB_WCKB01_N FBB_WCKB23 FBB_WCKB23_N FBB_WCKB45 FBB_WCKB45_N FBB_WCKB67 FBB_WCKB67_N FBB_PLL_AVDD G14 G20 RV60 DIS@ D12 E12 E20 F20 N13P-PES-A1_FCBGA908 60.4_0402_1% CLKC0 CLKC0# CLKC1 CLKC1# F8 E8 A5 A6 D24 D25 B27 C27 27 27 28 28 1 300mA +FB_PLLAVDD D6 D7 C6 B6 F26 E26 A26 A27 H17 DIS@ +FB_PLLAVDD +V1.05S_VCCP LV11 1 2 MPZ1608S300AT 0603 1 2 30ohm@100M // ESR=0.01 SM01000EQ00-SM010031100-- +FB_PLLAVDD +FB_PLLAVDD 100mA For EMI CV49 Under GPU close to ball : U27 +VRAM_1.5VS 60.4_0402_1% FBB_DEBUG0 FBB_DEBUG1 DIS@ CV53 1U_0402_6.3V6K FBA_DEBUG0 FBA_DEBUG1 60.4_0402_1% 27,28 CMDC[30..0] FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31 DIS@ CV51 1U_0402_6.3V6K RV57 MEMORY INTERFACE B MEMORY INTERFACE A FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 +VRAM_1.5VS FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63 DIS@ CV52 22U_0805_6.3V6M P30 F31 F34 M32 AD31 AL29 AM32 AF34 R32 AC32 G9 E9 G8 F9 F11 G11 F12 G12 G6 F5 E6 F6 F4 G4 E2 F3 C2 D4 D3 C1 B3 C4 B5 C5 A11 C11 D11 B11 D8 A8 C8 B8 F24 G23 E24 G24 D21 E21 G21 F21 G27 D27 G26 E27 E29 F29 E30 D30 A32 C31 C32 B32 D29 A29 C29 B29 B21 C23 A21 C21 B24 C24 B26 C26 DIS@ CV48 0.1U_0402_16V4Z DQMA[7..4] 25 DQMA0 DQMA1 DQMA2 DQMA3 26 DQMA4 DQMA5 DQMA6 DQMA7 FBA_CMD_RFU0 FBA_CMD_RFU1 DIS@ CV94 0.1U_0402_16V4Z DQMA[3..0] FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31 MDC0 MDC1 MDC2 MDC3 MDC4 MDC5 MDC6 MDC7 MDC8 MDC9 MDC10 MDC11 MDC12 MDC13 MDC14 MDC15 MDC16 MDC17 MDC18 MDC19 MDC20 MDC21 MDC22 MDC23 MDC24 MDC25 MDC26 MDC27 MDC28 MDC29 MDC30 MDC31 MDC32 MDC33 MDC34 MDC35 MDC36 MDC37 MDC38 MDC39 MDC40 MDC41 MDC42 MDC43 MDC44 MDC45 MDC46 MDC47 MDC48 MDC49 MDC50 MDC51 MDC52 MDC53 MDC54 MDC55 MDC56 MDC57 MDC58 MDC59 MDC60 MDC61 MDC62 MDC63 CMDA0 CMDA1 CMDA2 CMDA3 CMDA4 CMDA5 CMDA6 CMDA7 CMDA8 CMDA9 CMDA10 CMDA11 CMDA12 CMDA13 CMDA14 CMDA15 CMDA16 CMDA17 CMDA18 CMDA19 CMDA20 CMDA21 CMDA22 CMDA23 CMDA24 CMDA25 CMDA26 CMDA27 CMDA28 CMDA29 CMDA30 DIS@ CV50 0.1U_0402_16V4Z 1 FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 U30 T31 U29 R34 R33 U32 U33 U28 V28 V29 V30 U34 U31 V34 V33 Y32 AA31 AA29 AA28 AC34 AC33 AA32 AA33 Y28 Y29 W31 Y30 AA34 Y31 Y34 Y33 V31 Part 3 of 7 25,26 CMDA[30..0] Part 2 of 7 L28 M29 L29 M28 N31 P29 R29 P28 J28 H29 J29 H28 G29 E31 E32 F30 C34 D32 B33 C33 F33 F32 H33 H32 P34 P32 P31 P33 L31 L34 L32 L33 AG28 AF29 AG29 AF28 AD30 AD29 AC29 AD28 AJ29 AK29 AJ30 AK28 AM29 AM31 AN29 AM30 AN31 AN32 AP30 AP32 AM33 AL31 AK33 AK32 AD34 AD32 AC30 AD33 AF31 AG34 AG32 AG33 27 MDA[31..16] 25 DIS@ UV4B MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63 MDC[15..0] MDC[15..0] MDA[31..16] CV48 Under GPU close to ball : H17 N13P-PES-A1_FCBGA908 CV50 Under GPU close to ball : K27 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/05/23 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A Title N13P VRAM 2/9 Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 21 of 60 5 4 3 2 DIS@ UV4D 1 MULTI LEVEL STRAPS +3VS +3VS IFPC_L0 IFPC_L0_N IFPC_L1 IFPC_L1_N IFPC_L2 IFPC_L2_N IFPC_L3 IFPC_L3_N IFPD_L0 IFPD_L0_N IFPD_L1 IFPD_L1_N IFPD_L2 IFPD_L2_N IFPD_L3 IFPD_L3_N AD2 AD3 AD1 AC1 AC2 AC3 AC4 AC5 IFPE_L0 IFPE_L0_N IFPE_L1 IFPE_L1_N IFPE_L2 IFPE_L2_N IFPE_L3 IFPE_L3_N AE3 AE4 AF4 AF5 AD4 AD5 AG1 AF1 IFPF_L0 IFPF_L0_N IFPF_L1 IFPF_L1_N IFPF_L2 IFPF_L2_N IFPF_L3 IFPF_L3_N C 31 31 31 31 31 31 31 31 VGA_HDMI_TX2+ VGA_HDMI_TX2VGA_HDMI_TX1+ VGA_HDMI_TX1VGA_HDMI_TX0+ VGA_HDMI_TX0VGA_HDMI_CLK+ VGA_HDMI_CLK- GND_SENSE +3VS VGA_HDMI_CLK VGA_HDMI_DATA RV152 DIS@ HDMI B AG3 AG2 4.7K_0402_5% 4.7K_0402_5% 31 31 VGA_HDMI_CLK VGA_HDMI_DATA AK3 AK2 AB3 AB4 AF3 AF2 DIS@ RV71 4.99K_0402_1% DIS@ RV70 10K_0402_1% RV69 4.99K_0402_1% RV68 20K_0402_1% DIS@ RV67 4.99K_0402_1% @ RV66 34.8K_0402_1% RV65 4.99K_0402_1% STRAP3 STRAP4 @ RV79 34.8K_0402_1% RV77 @ RV78 4.99K_0402_1% @ 45.3K_0402_1% @ DIS@ RV76 10K_0402_1% @ VCCSENSE_VGA 56 L5 TESTMODE AK11 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N AM10 AM11 AP12 AP11 AN11 ROM_CS_N ROM_SCLK ROM_SI ROM_SO H6 H4 H5 H7 DIS@ RV82 DIS@ JTAG_TCK RV83 JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST ROM_CS# ROM_SCLK ROM_SI ROM_SO CEC RV85 DIS@ 10K_0402_5% IFPC_AUX_I2CW_SCL IFPC_AUX_I2CW_SDA_N IFPD_AUX_I2CX_SCL IFPD_AUX_I2CX_SDA_N J2 J7 J6 J5 J3 THERMDP THERMDN K3 K4 IFPE_AUX_I2CY_SCL IFPE_AUX_I2CY_SDA_N RV153 @ DIS@ RV86 10K_0402_5% 10K_0402_5% +3VS MULTI_STRAP_REF0_GND RV87 DIS@ STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 C +3VS L2 J1 LP@ RV74 20K_0402_1% 10K_0402_5% 10K_0402_5% L3 GS@ RV74 15K +-1% 0402 10K_0402_5% RV84 DIS@ GENERAL BUFRST_N VGA Chip Device ID VSSSENSE_VGA 56 SERIAL MULTI_STRAP_REF0_GND RV151 DIS@ @ ROM_SI ROM_SO ROM_SCLK D L4 TEST LVDS/TMDS AM1 AM2 AM3 AM4 AL3 AL4 AK4 AK5 @ X76VDD_SENSE AK1 AJ1 AJ3 AJ2 AH3 AH4 AG5 AG4 STRAP0 STRAP1 STRAP2 @ RV75 4.99K_0402_1% IFPB_TXC IFPB_TXC_N IFPB_TXD4 IFPB_TXD4_N IFPB_TXD5 IFPB_TXD5_N IFPB_TXD6 IFPB_TXD6_N IFPB_TXD7 IFPB_TXD7_N Straps RV74 10K_0402_1% AJ9 AH9 AP6 AP5 AM7 AL7 AN8 AM8 AK8 AL8 VGA_TZCLK+ VGA_TZCLKVGA_TZOUT0+ VGA_TZOUT0VGA_TZOUT1+ VGA_TZOUT1VGA_TZOUT2+ VGA_TZOUT2- P8 AC6 AJ28 AJ4 AJ5 AL11 C15 D19 D20 D23 D26 H31 T8 V32 GT@ D 29 29 29 29 29 29 29 29 NC NC NC NC NC NC NC NC NC NC NC NC NC NC DIS@ RV73 34.8K_0402_1% IFPA_TXC IFPA_TXC_N IFPA_TXD0 IFPA_TXD0_N IFPA_TXD1 IFPA_TXD1_N IFPA_TXD2 IFPA_TXD2_N IFPA_TXD3 IFPA_TXD3_N RV72 4.99K_0402_1% VGA_TXCLK+ VGA_TXCLKVGA_TXOUT0+ VGA_TXOUT0VGA_TXOUT1+ VGA_TXOUT1VGA_TXOUT2+ VGA_TXOUT2- NC 29 29 29 29 29 29 29 29 DIS@ RV64 45.3K_0402_1% Part 4 of 7 AM6 AN6 AP3 AN3 AN5 AM5 AL6 AK6 AJ6 AH6 40.2K_0402_1% STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 For N13P-GS/GT/LP strap table GPU IFPF_AUX_I2CZ_SCL IFPF_AUX_I2CZ_SDA_N Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK 900 MHz 64M* 16* 8 1GB Hynix SA000041S20 RV64 PU 45K RV73 PD 35K RV74 PD 15K RV67 PU 5K RV76 PD 10K RV77 PD 15K RV70 PU 10K RV71 PU 5K 900 MHz 64M* 16* 8 1GB Samsung SA00004GS00 RV64 PU 45K RV73 PD 35K RV74 PD 15K RV67 PU 5K RV76 PD 10K RV77 PD 20K RV70 PU 10K RV71 PU 5K 900 MHz 128M* 16* 8 2GB Hynix SA00003YO00 RV64 PU 45K RV73 PD 35K RV74 PD 15K RV67 PU 5K RV76 PD 10K RV77 PD 35K RV70 PU 10K RV71 PU 5K 900 MHz 128M* 16* 8 2GB Samsung SA000047Q00 RV64 PU 45K RV73 PD 35K RV74 PD 15K RV67 PU 5K RV76 PD 10K RV77 PD 45K RV70 PU 10K RV71 PU 5K 900 MHz 64M* 16* 8 1GB Hynix SA000041S20 RV64 PU 45K RV73 PD 35K RV74 PD 10K RV67 PU 5K RV76 PD 10K RV77 PD 15K RV70 PU 10K RV71 PU 5K 900 MHz 64M* 16* 8 1GB Samsung SA00004GS00 RV64 PU 45K RV73 PD 35K RV74 PD 10K RV67 PU 5K RV76 PD 10K RV77 PD 20K RV70 PU 10K RV71 PU 5K 900 MHz 128M* 16* 8 2GB Hynix SA00003YO00 RV64 PU 45K RV73 PD 35K RV74 PD 10K RV67 PU 5K RV76 PD 10K RV77 PD 35K RV70 PU 10K RV71 PU 5K 900 MHz 128M* 16* 8 2GB Samsung SA000047Q00 RV64 PU 45K RV73 PD 35K RV74 PD 10K RV67 PU 5K RV76 PD 10K RV77 PD 45K RV70 PU 10K RV71 PU 5K 900 MHz 64M* 16* 8 1GB Hynix SA000041S20 RV64 PU 45K RV73 PD 35K RV74 PD 20K RV67 PU 5K RV76 PD 10K RV77 PD 15K RV70 PU 10K RV71 PU 5K 900 MHz 64M* 16* 8 1GB Samsung SA00004GS00 RV64 PU 45K RV73 PD 35K RV74 PD 20K RV67 PU 5K RV76 PD 10K RV77 PD 20K RV70 PU 10K RV71 PU 5K 900 MHz 128M* 16* 8 2GB Hynix SA00003YO00 RV64 PU 45K RV73 PD 35K RV74 PD 20K RV67 PU 5K RV76 PD 10K RV77 PD 35K RV70 PU 10K RV71 PU 5K 900 MHz 128M* 16* 8 2GB Samsung SA000047Q00 RV64 PU 45K RV73 PD 35K RV74 PD 20K RV67 PU 5K RV76 PD 10K RV77 PD 45K RV70 PU 10K RV71 PU 5K Frenq. B N13P-GS N13P-PES-A1_FCBGA908 N13P-GT N13P-LP A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 A 2 Title N13P LVDS 3/9 Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 22 of 60 5 4 3 2 1 +V1.05S_VCCP Under GPU C FB_VDDQ_SENSE 10_0402_5% RV91 DIS@ FB_GND_SENSE 10_0402_5% RV93 DIS@ +VRAM_1.5VS DIS@ CV102 +IFPAB_PLLVDD 0.1U_0402_16V4Z CV101 100mA 1U_0402_6.3V6K CV100 B 4.7U_0603_6.3V6K +V1.05S_VCCP LV13 DIS@ PBY160808T-121Y-N 0603 2 1 RV96 DIS@ 2 RV98 DIS@ 1 RV101 DIS@ FB_CAL_PD_VDDQ 40.2_0402_1% FB_CAL_PU_GND 1 42.2_0402_1% F1 F2 J27 H27 FB_CAL_TERM_GND H25 2 51.1_0402_1% PEX_SVDD_3V3 PEX_PLLVDD VDD33_0 VDD33_1 VDD33_2 VDD33_3 0.1U_0402_16V4Z AG12 J8 K8 L8 M8 DIS@ CV60 22U_0805_6.3V6M DIS@ CV59 22U_0805_6.3V6M DIS@ CV68 22U_0805_6.3V6M DIS@ CV78 22U_0805_6.3V6M DIS@ CV67 10U_0603_6.3V6M DIS@ CV77 10U_0603_6.3V6M DIS@ CV198 0.1U_0402_16V4Z +PEX_PLLVDD +VDD33 210mA Under GPU 150mA 120mA Design guide no define DIS@ CV82 4.7U_0603_6.3V6K DIS@ CV81 4.7U_0603_6.3V6K 210mA AH12 AG26 DIS@ CV76 4.7U_0603_6.3V6K CV80,CV198 Under GPU close to ball DIS@ CV80 420mA DIS@ LV12 0_0603_5% Near GPU +V1.05S_VCCP C DIS@ DIS@ DIS@ Under GPU IFPAB_PLLVDD IFPAB_RSET +VRAM_1.5VS +3VS IFPA_IOVDD IFPB_IOVDD AH8 AJ8 +IFPAB_PLLVDD AG8 AG9 +IFPAB_IOVDD AF7 AF8 +IFPC_PLLVDD AF6 +IFPC_IOVDD AG7 AN2 +IFPD_PLLVDD AG6 +IFPD_IOVDD AB8 AD6 +IFPEF_PLLVDD AC7 AC8 +IFPEF_IOVDD @ RV90 1K_0402_5% RV92 DIS@ @ RV94 10K_0402_5% 1K_0402_5% RV95 DIS@ 10K_0402_5% FB_VDDQ_SENSE IFPC_PLLVDD IFPC_RSET FB_GND_SENSE IFPC_IOVDD DIS@ DIS@ DIS@ DIS@ DIS@ CV97 4.7U_0603_6.3V6K DIS@ PEX_PLL_HVDD D Near GPU CV96 1U_0402_6.3V6K DIS@ DIS@ CV86 22U_0805_6.3V6M 2 CV85 22U_0805_6.3V6M 1 2 CV95 1U_0402_6.3V6K DIS@ CV84 10U_0603_6.3V6M 2 CV83 10U_0603_6.3V6M 1 2 1 CV89 4.7U_0603_6.3V6K DIS@ 1 CV92 0.1U_0402_16V4Z CV73 0.1U_0402_16V4Z CV72 0.1U_0402_16V4Z DIS@ 3300 mA CV88 1U_0402_6.3V6K DIS@ Near GPU AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27 AJ27 AK27 AL27 AM28 AN28 Near GPU CV91 0.1U_0402_16V4Z DIS@ CV71 0.1U_0402_16V4Z CV79 0.1U_0402_16V4Z CV70 1U_0402_6.3V6K DIS@ CV69 4.7U_0603_6.3V6K DIS@ PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 +V1.05S_VCCP Under GPU AG19 AG21 AG22 AG24 AH21 AH25 CV87 0.1U_0402_16V4Z DIS@ 2 CV90 0.1U_0402_16V4Z DIS@ CV66 0.1U_0402_16V4Z CV65 0.1U_0402_16V4Z CV64 0.1U_0402_16V4Z DIS@ Under GPU PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 DIS@ CV74 1U_0402_6.3V6K DIS@ FBVDDQ_0 FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 FBVDDQ_38 FBVDDQ_39 FBVDDQ_40 FBVDDQ_41 FBVDDQ_42 FBVDDQ_43 POWER DIS@ CV63 0.1U_0402_16V4Z CV62 1U_0402_6.3V6K DIS@ CV61 4.7U_0603_6.3V6K D AA27 AA30 AB27 AB33 AC27 AD27 AE27 AF27 AG27 B13 B16 B19 E13 E16 E19 H10 H11 H12 H13 H14 H15 H16 H18 H19 H20 H21 H22 H23 H24 H8 H9 L27 M27 N27 P27 R27 T27 T30 T33 V27 W27 W30 W33 Y27 1 DIS@ CV58 10U_0603_6.3V6M Part 5 of 7 7200mA 2 DIS@ CV75 1U_0402_6.3V6K Under GPU +VRAM_1.5VS 1 DIS@ CV57 10U_0603_6.3V6M DIS@ UV4E DIS@ CV56 4.7U_0603_6.3V6K Design guide no define DIS@ CV55 1U_0402_6.3V6K DIS@ CV54 1U_0402_6.3V6K Near GPU +3VS RV89 0_0603_5% DIS@ DIS@ FB_CAL_PD_VDDQ IFPD_PLLVDD IFPD_RSET FB_CAL_PU_GND IFPD_IOVDD RV97 DIS@ @ RV99 10K_0402_5% 1K_0402_5% RV100 DIS@ 10K_0402_5% RV103 DIS@ 1K_0402_5% FB_CAL_TERM_GND IFPEF_PLVDD IFPEF_RSET IFPE_IOVDD IFPF_IOVDD B DIS@ DIS@ N13P-PES-A1_FCBGA908 +3VS RV2 0_0805_5% @ DIS@ DIS@ 0.1U_0402_16V4Z Under GPU(below 150mils) Near GPU DIS@ LV4 +IFPAB_IOVDD CV106 1U_0402_6.3V6K DIS@ CV104 LV14 BLM18PG181SN1D_2P +3VS 320mA 1 4.7U_0603_6.3V6K 2 CV103 +1.8VS 220mA 1U_0402_6.3V6K 2 1 PBY160808T-301Y-N 0603 DIS@ CV202 4.7U_0603_6.3V6K 1 CV199 DIS@ 2 CV200 DIS@ CV208 DIS@ CV201 DIS@ +IFPEF_PLLVDD CV206 0.1U_0402_16V4Z DIS@ DIS@ 4.7U_0603_6.3V6K +V1.05S_VCCP DIS@ 2 1 4.7U_0603_6.3V6K LV15 BLM18PG181SN1D_2P CV197 4.7U_0603_6.3V6K CV203 DIS@ A 0.1U_0402_16V4Z DIS@ 0.1U_0402_16V4Z A 570mA +IFPEF_IOVDD 0.1U_0402_16V4Z 1 2 CV204 DIS@ 1U_0402_6.3V6K CV205 DIS@ CV207 0.1U_0402_16V4Z DIS@ Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title N13P POWER & GND 4/9 Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 23 of 60 5 4 3 2 1 +VGA_CORE UV4F +VGA_CORE UV4G C B A GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98 GND_99 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198 GND_199 GND_OPT GND_OPT AA12 AA14 AA16 AA19 AA21 AA23 AB13 AB15 AB17 AB18 AB20 AB22 AC12 AC14 AC16 AC19 AC21 AC23 M12 M14 M16 M19 M21 M23 N13 N15 N17 N18 N20 N22 P12 P14 P16 P19 P21 P23 R13 R15 R17 R18 R20 R22 T12 T14 T16 T19 T21 T23 U13 U15 U17 U18 U20 U22 V13 V15 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 XVDD_1 XVDD_2 XVDD_3 XVDD_4 XVDD_5 XVDD_6 XVDD_7 XVDD_8 XVDD_9 XVDD_10 XVDD_11 XVDD_12 XVDD_13 XVDD_14 XVDD_15 XVDD_16 XVDD_17 XVDD_18 XVDD_19 XVDD_20 XVDD_21 XVDD_22 XVDD_23 XVDD_24 XVDD_25 XVDD_26 XVDD_27 XVDD_28 XVDD_29 XVDD_30 XVDD_31 XVDD_32 XVDD_33 XVDD_34 XVDD_35 XVDD_36 XVDD_37 XVDD_38 V17 V18 V20 V22 W12 W14 W16 W19 W21 W23 Y13 Y15 Y17 Y18 Y20 Y22 D U1 U2 U3 U4 U5 U6 U7 U8 V1 V2 V3 V4 V5 V6 V7 V8 C W2 W3 W4 W5 W7 W8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 B N13P-PES-A1_FCBGA908 DIS@ A Issued Date DIS@ Compal Electronics, Inc. Compal Secret Data Security Classification N13P-PES-A1_FCBGA908 5 Part 7 of 7 60A D2 D31 D33 E10 E22 E25 E5 E7 F28 F7 G10 G13 G16 G19 G2 G22 G25 G28 G3 G30 G32 G33 G5 G7 K2 K28 K30 K32 K33 K5 K7 M13 M15 M17 M18 M20 M22 N12 N14 N16 N19 N2 N21 N23 N28 N30 N32 N33 N5 N7 P13 P15 P17 P18 P20 P22 R12 R14 R16 R19 R21 R23 T13 T15 T17 T18 T2 T20 T22 AG11 T28 T32 T5 T7 U12 U14 U16 U19 U21 U23 V12 V14 V16 V19 V21 V23 W13 W15 W17 W18 W20 W22 W28 Y12 Y14 Y16 Y19 Y21 Y23 AH11 C16 W32 POWER A2 AA17 AA18 AA20 AA22 AB12 AB14 AB16 AB19 AB2 AB21 A33 AB23 AB28 AB30 AB32 AB5 AB7 AC13 AC15 AC17 AC18 AA13 AC20 AC22 AE2 AE28 AE30 AE32 AE33 AE5 AE7 AH10 AA15 AH13 AH16 AH19 AH2 AH22 AH24 AH28 AH29 AH30 AH32 AH33 AH5 AH7 AJ7 AK10 AK7 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 AL24 AL26 AL28 AL30 AL32 AL33 AL5 AM13 AM16 AM19 AM22 AM25 AN1 AN10 AN13 AN16 AN19 AN22 AN25 AN30 AN34 AN4 AN7 AP2 AP33 B1 B10 B22 B25 B28 B31 B34 B4 B7 C10 C13 C19 C22 C25 C28 C7 D GND Part 6 of 7 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title N13P POWER & GND 5/9 Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Sheet Wednesday, March 07, 2012 1 24 of 60 5 4 3 2 1 VRAM DDR3 chips (1GB) Mode D Address 0..31 CMD0 64Mx16 DDR3 *8==>1GB 128Mx16 DDR3 *8==>2GB 21,26 21,26 CMD2 DQSA[7..0] DQSA[7..0] UV8 DQMA[7..0] DQMA[7..0] MDA[63..0] MDA[63..0] CMDA[30..0] CMDA[30..0] M8 H1 VREFCA VREFDQ CMDA9 CMDA11 CMDA8 CMDA25 CMDA10 CMDA24 CMDA22 CMDA7 CMDA21 CMDA6 CMDA29 CMDA23 CMDA28 CMDA20 CMDA4 CMDA14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 CMDA12 CMDA27 CMDA26 M2 N8 M3 BA0 BA1 BA2 CLKA0 CLKA0# CMDA3 J7 K7 K9 CK CK CKE/CKE0 21,26 21,26 21,26 DIS@ RV105 240_0402_1% C 1 DIS@ RV106 240_0402_1% 2 CV109 0.1U_0402_16V4Z +MEM_VREF0 DIS@ CMDA2 CMDA0 CMDA30 CMDA15 CMDA13 +VRAM_1.5VS DIS@ RV107 240_0402_1% K1 L2 J3 K3 L3 DQSA1 DQSA2 2 CV110 0.1U_0402_16V4Z 1 DIS@ RV108 240_0402_1% DQMA1 DQMA2 E7 D3 DQSA#1 DQSA#2 G3 B7 CMDA5 21 VDD VDD VDD VDD VDD VDD VDD VDD VDD @ Group1 Group2 B2 D9 G7 K2 K8 N1 N9 R1 R9 +VRAM_1.5VS J1 L1 J9 L9 2 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 CMDA12 CMDA27 CMDA26 M2 N8 M3 BA0 BA1 BA2 CLKA0 CLKA0# CMDA3 J7 K7 K9 CK CK CKE/CKE0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 DQMA0 DQMA3 E7 D3 DQSA#0 DQSA#3 G3 B7 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B1 B9 D1 D8 E2 E8 F9 G1 G9 ZQ/ZQ0 VREFCA VREFDQ N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DQSA0 DQSA3 CMDA5 ZQ1 K1 L2 J3 K3 L3 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 310mAVDDQ DQSL VDDQ DQSU VDDQ Group0 Group3 B1 B9 D1 D8 E2 E8 F9 G1 G9 ZQ/ZQ0 CKE CMD4 A14 CMD5 RST RST CMD6 A9 A9 CMD7 A7 A7 CMD8 A2 A2 CMD9 A0 A0 CMD10 A4 A4 CMD11 A1 A1 CMD12 BA0 BA0 CMD13 WE* WE* CMD14 A15 A15 CMD15 CAS* A14 CAS* CS0_H# CMD16 C ODT_H CMD18 CKE_H CMD19 +VRAM_1.5VS A1 A8 C1 C9 D2 E9 F1 H2 H9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ RESET CMD3 CMD17 B2 D9 G7 K2 K8 N1 N9 R1 R9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 DQSL DQSU L8 D7 C3 C8 C2 A7 A2 B8 A3 MDA27 MDA29 MDA25 MDA30 MDA24 MDA28 MDA26 MDA31 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DML DMU T2 MDA3 MDA4 MDA2 MDA7 MDA0 MDA5 MDA1 MDA6 +VRAM_1.5VS ODT/ODT0 CS/CS0 RAS CAS WE F3 C7 E3 F7 F2 F8 H3 H8 G2 H7 ODT_L CMD20 A13 CMD21 A8 A8 CMD22 A6 A6 CMD23 A11 A11 CMD24 A5 A5 CMD25 A3 A3 CMD26 BA2 BA2 CMD27 BA1 BA1 CMD28 A12 A12 CMD29 A10 A10 CMD30 RAS* RAS* LOW HIGH A13 Not Available B 1 DIS@ RV110 243_0402_1% 1 CMDA9 CMDA11 CMDA8 CMDA25 CMDA10 CMDA24 CMDA22 CMDA7 CMDA21 CMDA6 CMDA29 CMDA23 CMDA28 CMDA20 CMDA4 CMDA14 A1 A8 C1 C9 D2 E9 F1 H2 H9 RESET NC/ODT1 NC/CS1 NC/CE1 NCZQ1 CLKA0# RV118 @ 80.6_0402_1% D7 C3 C8 C2 A7 A2 B8 A3 MDA17 MDA21 MDA18 MDA23 MDA19 MDA22 MDA16 MDA20 +MEM_VREF1 M8 H1 1 CLKA0 RV109 @ DIS@ 80.6_0402_1% RV15 160_0402_1% CLKA0# MDA12 MDA14 MDA8 MDA15 MDA9 MDA13 MDA10 MDA11 CMDA2 CMDA0 CMDA30 CMDA15 CMDA13 DQSL DQSU L8 E3 F7 F2 F8 H3 H8 G2 H7 +VRAM_1.5VS DML DMU T2 ZQ0 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VDDQ VDDQ VDDQ VDDQ VDDQ 310mAVDDQ VDDQ DQSL VDDQ DQSU VDDQ DIS@ B DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 ODT/ODT0 CS/CS0 RAS CAS WE F3 C7 +MEM_VREF1 CLKA0 UV9 swap 0329 +MEM_VREF0 +VRAM_1.5VS 21 @ DQSA#[7..0] DQSA#[7..0] D CMD1 @ CV111 0.01U_0402_16V7K DIS@ RV111 243_0402_1% J1 L1 J9 L9 2 D 32..63 CS0_L# 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 CMDA2 DIS@ CMDA3 DIS@ CMDA5 DIS@ CMDA18 DIS@ CMDA19 DIS@ RV112 1 RV113 1 RV115 1 RV116 1 RV117 1 2 2 2 2 2 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% Command Bit DDR3 Default Pull-down ODTx 10k CKEx 10k RST CS* 10k No Termination 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 NV recommand 0720 +VRAM_1.5VS +VRAM_1.5VS DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V ) CV130 0.1U_0402_16V4Z CV129 0.1U_0402_16V4Z CV128 0.1U_0402_16V4Z CV127 0.1U_0402_16V4Z CV126 0.1U_0402_16V4Z CV125 1U_0402_6.3V6K DIS@ CV124 1U_0402_6.3V6K DIS@ DIS@ CV123 1U_0402_6.3V6K 2 CV122 1U_0402_6.3V6K 2 1 CV121 0.1U_0402_16V4Z 2 1 CV120 0.1U_0402_16V4Z 2 1 CV119 0.1U_0402_16V4Z 2 1 CV118 0.1U_0402_16V4Z 2 1 CV117 0.1U_0402_16V4Z 1 CV116 0.1U_0402_16V4Z CV115 1U_0402_6.3V6K CV114 1U_0402_6.3V6K A CV113 1U_0402_6.3V6K CV112 1U_0402_6.3V6K Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P) AMD :SA00003PF10 (S IC D3 64M16/800 23EY2387MB-12 PG-TFBGA 96P 1.5V) A DIS@ DIS@ Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title N13P DDR3 6/9 Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 25 of 60 5 4 3 2 1 VRAM DDR3 chips (1GB) Mode D Address 64Mx16 DDR3 *8==>1GB 128Mx16 DDR3 *8==>2GB +MEM_VREF2 DQMA[7..0] DQMA[7..0] 21,25 CMDA[30..0] CMDA[30..0] 21,25 DQSA#[7..0] 21,25 DQSA[7..0] CMDA9 CMDA11 CMDA8 CMDA25 CMDA10 CMDA24 CMDA22 CMDA7 CMDA21 CMDA6 CMDA29 CMDA23 CMDA28 CMDA20 CMDA4 CMDA14 21,25 DQSA#[7..0] DQSA[7..0] MDA[63..0] MDA[63..0] 21,25 +VRAM_1.5VS DIS@ RV119 240_0402_1% M8 H1 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 CMDA12 CMDA27 CMDA26 M2 N8 M3 CLKA1 CLKA1# CMDA19 J7 K7 K9 @ UV11 VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 2 CV131 0.1U_0402_16V4Z C 1 CMDA18 CMDA16 CMDA30 CMDA15 CMDA13 BA0 BA1 BA2 DIS@ DQSA4 DQSA7 DIS@ RV121 240_0402_1% DQMA4 DQMA7 K1 L2 J3 K3 L3 ODT/ODT0 CS/CS0 RAS CAS WE F3 C7 DQSL DQSU 2 CMDA5 CLKA1 CLKA1 21 J1 L1 J9 L9 2 21 L8 DIS@ RV123 243_0402_1% DIS@ B T2 ZQ2 RV125 @ DIS@ 80.6_0402_1% RV16 160_0402_1% CLKA1# CLKA1# RV127 @ 80.6_0402_1% CMDA9 CMDA11 CMDA8 CMDA25 CMDA10 CMDA24 CMDA22 CMDA7 CMDA21 CMDA6 CMDA29 CMDA23 CMDA28 CMDA20 CMDA4 CMDA14 Group4 Group7 VDDQ VDDQ VDDQ VDDQ VDDQ 310mAVDDQ VDDQ VDDQ VDDQ DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 1 2 M8 H1 M2 N8 M3 CLKA1 CLKA1# CMDA19 J7 K7 K9 +VRAM_1.5VS A1 A8 C1 C9 D2 E9 F1 H2 H9 CMDA18 CMDA16 CMDA30 CMDA15 CMDA13 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 DQMA5 DQMA6 DQSA5 DQSA6 DQSA#5 DQSA#6 CMDA5 ZQ3 VREFCA VREFDQ N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 CMDA12 CMDA27 CMDA26 @ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE VDDQ VDDQ VDDQ VDDQ VDDQ 310mAVDDQ VDDQ DQSL VDDQ DQSU VDDQ F3 C7 E7 D3 DML DMU G3 B7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU T2 RESET L8 MDA45 MDA40 MDA46 MDA41 MDA47 MDA43 MDA44 MDA42 D7 C3 C8 C2 A7 A2 B8 A3 MDA53 MDA49 MDA55 MDA50 MDA52 MDA48 MDA54 MDA51 Group5 Group6 +VRAM_1.5VS BA0 BA1 BA2 K1 L2 J3 K3 L3 E3 F7 F2 F8 H3 H8 G2 H7 ZQ/ZQ0 B2 D9 G7 K2 K8 N1 N9 R1 R9 32..63 CS0_L# NC/ODT1 NC/CS1 NC/CE1 NCZQ1 RV124 243_0402_1% B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ J1 L1 J9 L9 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ DIS@ 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 CMD2 ODT_L CMD3 CKE D CMD4 A14 CMD5 RST RST CMD6 A9 A9 CMD7 A7 A7 CMD8 A2 A2 CMD9 A0 A0 CMD10 A4 A4 CMD11 A1 A1 CMD12 BA0 BA0 CMD13 WE* WE* CMD14 A15 A15 CMD15 CAS* CAS* A14 CS0_H# CMD16 CMD17 +VRAM_1.5VS A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 CMD18 ODT_H CMD19 CKE_H CMD20 A13 CMD21 A8 A8 CMD22 A6 A6 CMD23 A11 A11 CMD24 A5 A5 CMD25 A3 A3 CMD26 BA2 BA2 CMD27 BA1 BA1 CMD28 A12 A12 CMD29 A10 A10 CMD30 RAS* RAS* LOW HIGH C A13 Not Available 1 1 G3 B7 D7 C3 C8 C2 A7 A2 B8 A3 MDA61 MDA59 MDA60 MDA57 MDA63 MDA56 MDA62 MDA58 +MEM_VREF3 1 DIS@ RV122 240_0402_1% DQSA#4 DQSA#7 CV132 0.1U_0402_16V4Z +MEM_VREF3 E7 D3 MDA39 MDA35 MDA37 MDA33 MDA38 MDA32 MDA36 MDA34 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 +VRAM_1.5VS E3 F7 F2 F8 H3 H8 G2 H7 +VRAM_1.5VS +MEM_VREF2 DIS@ RV120 240_0402_1% 0..31 CMD1 UV10 2 D CMD0 B1 B9 D1 D8 E2 E8 F9 G1 G9 B 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 @ CV133 0.01U_0402_16V7K NV recommand 0720 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ CV152 0.1U_0402_16V4Z CV151 0.1U_0402_16V4Z CV150 0.1U_0402_16V4Z CV149 0.1U_0402_16V4Z 2 CV148 0.1U_0402_16V4Z 2 1 CV143 0.1U_0402_16V4Z 1 CV142 0.1U_0402_16V4Z 2 CV141 0.1U_0402_16V4Z CV140 0.1U_0402_16V4Z 2 1 CV147 1U_0402_6.3V6K DIS@ 1 CV146 1U_0402_6.3V6K DIS@ 2 CV139 0.1U_0402_16V4Z CV138 0.1U_0402_16V4Z 2 1 CV145 1U_0402_6.3V6K DIS@ 1 CV144 1U_0402_6.3V6K DIS@ CV137 1U_0402_6.3V6K DIS@ CV136 1U_0402_6.3V6K DIS@ +VRAM_1.5VS CV135 1U_0402_6.3V6K CV134 1U_0402_6.3V6K +VRAM_1.5VS DIS@ A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title N13P DDR3 7/9 Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 26 of 60 5 4 3 2 1 Mode D Address VRAM DDR3 chips (1GB) 0..31 CMD0 32..63 CS0_L# CMD1 64Mx16 DDR3 *8==>1GB 128Mx16 DDR3 *8==>2GB 21,28 21,28 DQSC[7..0] DQSC[7..0] DQSC#[7..0] DQSC#[7..0] UV12 21,28 MDC[63..0] MDC[63..0] CMDC[30..0] CMDC[30..0] +MEM_VREF4 21,28 M8 H1 CMDC9 CMDC11 CMDC8 CMDC25 CMDC10 CMDC24 CMDC22 CMDC7 CMDC21 CMDC6 CMDC29 CMDC23 CMDC28 CMDC20 CMDC4 CMDC14 21,28 +VRAM_1.5VS DIS@ RV128 240_0402_1% 2 CV153 0.1U_0402_16V4Z 1 DIS@ RV129 240_0402_1% CMDC12 CMDC27 CMDC26 DIS@ +VRAM_1.5VS DIS@ CV154 0.1U_0402_16V4Z 2 BA0 BA1 BA2 CK CK CKE/CKE0 CMDC2 CMDC0 CMDC30 CMDC15 CMDC13 K1 L2 J3 K3 L3 ODT/ODT0 CS/CS0 RAS CAS WE E7 D3 DQSC#1 DQSC#2 G3 B7 CMDC5 T2 ZQ4 L8 D7 C3 C8 C2 A7 A2 B8 A3 MDC18 MDC20 MDC17 MDC22 MDC16 MDC23 MDC19 MDC21 +MEM_VREF5 M8 H1 CMDC9 CMDC11 CMDC8 CMDC25 CMDC10 CMDC24 CMDC22 CMDC7 CMDC21 CMDC6 CMDC29 CMDC23 CMDC28 CMDC20 CMDC4 CMDC14 Group1 Group2 DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 M2 N8 M3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 J7 K7 K9 CK CK CKE/CKE0 A1 A8 C1 C9 D2 E9 F1 H2 H9 CMDC2 CMDC0 CMDC30 CMDC15 CMDC13 K1 L2 J3 K3 L3 ODT/ODT0 CS/CS0 RAS CAS WE A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 DQMC0 DQMC3 +VRAM_1.5VS DQSC0 DQSC3 F3 C7 E7 D3 DQSC#0 DQSC#3 G3 B7 CMDC5 T2 ZQ5 L8 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 MDC3 MDC7 MDC1 MDC4 MDC2 MDC6 MDC0 MDC5 D7 C3 C8 C2 A7 A2 B8 A3 MDC26 MDC31 MDC25 MDC30 MDC27 MDC28 MDC24 MDC29 Group0 Group3 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 310mAVDDQ DQSL VDDQ DQSU VDDQ DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 B2 D9 G7 K2 K8 N1 N9 R1 R9 ODT_L CMD3 CKE CMD4 A14 D A14 CMD5 RST RST CMD6 A9 A9 CMD7 A7 A7 CMD8 A2 A2 CMD9 A0 A0 CMD10 A4 A4 CMD11 A1 A1 CMD12 BA0 BA0 CMD13 WE* WE* CMD14 A15 A15 CMD15 CAS* CAS* CS0_H# CMD16 +VRAM_1.5VS BA0 BA1 BA2 CLKC0 CLKC0# CMDC3 2 J1 L1 J9 L9 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 CLKC0 RV139 @ DIS@ 80.6_0402_1% RV17 160_0402_1% DIS@ RV133 243_0402_1% B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ J1 L1 J9 L9 2 DIS@ RV132 243_0402_1% 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 CMD17 ODT_H CMD18 +VRAM_1.5VS A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 C CKE_H CMD19 CMD20 A13 CMD21 A8 A8 CMD22 A6 A6 CMD23 A11 A11 CMD24 A5 A5 CMD25 A3 A3 CMD26 BA2 BA2 CMD27 BA1 BA1 CMD28 A12 A12 CMD29 A10 A10 CMD30 RAS* RAS* LOW HIGH A13 Not Available NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B B1 B9 D1 D8 E2 E8 F9 G1 G9 CMDC2 DIS@ CMDC3 DIS@ CMDC5 DIS@ CMDC18 DIS@ CMDC19 DIS@ RV134 1 RV135 1 RV136 1 RV137 1 RV138 1 2 2 2 2 2 Command Bit 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% DDR3 Default Pull-down ODTx 10k CKEx 10k RST CS* 10k No Termination 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 CLKC0# DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ CV174 0.1U_0402_16V4Z CV173 0.1U_0402_16V4Z CV172 0.1U_0402_16V4Z CV171 0.1U_0402_16V4Z 2 DIS@ CV170 0.1U_0402_16V4Z 2 DIS@ 1 CV165 0.1U_0402_16V4Z 2 DIS@ 1 CV164 0.1U_0402_16V4Z 1 CV163 0.1U_0402_16V4Z 2 CV162 0.1U_0402_16V4Z 2 CV161 0.1U_0402_16V4Z 2 DIS@ 1 CV169 1U_0402_6.3V6K DIS@ 1 CV168 1U_0402_6.3V6K DIS@ 1 CV167 1U_0402_6.3V6K DIS@ CV159 1U_0402_6.3V6K 2 NV recommand 0720 +VRAM_1.5VS @ CV155 0.01U_0402_16V7K CV160 0.1U_0402_16V4Z +VRAM_1.5VS 1 CV158 1U_0402_6.3V6K RV141 @ 80.6_0402_1% CV157 1U_0402_6.3V6K CLKC0# CV156 1U_0402_6.3V6K CLKC0 @ VREFCA VREFDQ CMD2 1 ZQ/ZQ0 CMDC12 CMDC27 CMDC26 1 B MDC8 MDC12 MDC11 MDC13 MDC9 MDC14 MDC10 MDC15 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ 310mAVDDQ VDDQ DQSL VDDQ DQSU VDDQ F3 C7 E3 F7 F2 F8 H3 H8 G2 H7 +VRAM_1.5VS J7 K7 K9 DQMC1 DQMC2 1 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 CLKC0 CLKC0# CMDC3 +MEM_VREF5 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 M2 N8 M3 DQSC1 DQSC2 DIS@ RV130 240_0402_1% DIS@ RV131 240_0402_1% UV13 VREFCA VREFDQ N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 +MEM_VREF4 C @ swap 0329 DQMC[7..0] DQMC[7..0] CV166 1U_0402_6.3V6K D DIS@ A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title N13P DDR3 8/9 Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 27 of 60 5 4 3 2 1 VRAM DDR3 chips (1GB) 64Mx16 DDR3 *8==>1GB 128Mx16 DDR3 *8==>2GB D DQMC[7..0] DQMC[7..0] CMDC[30..0] CMDC[30..0] 21,27 21,27 UV15 DQSC[7..0] DQSC[7..0] MDC[63..0] MDC[63..0] +MEM_VREF6 21,27 CMDC9 CMDC11 CMDC8 CMDC25 CMDC10 CMDC24 CMDC22 CMDC7 CMDC21 CMDC6 CMDC29 CMDC23 CMDC28 CMDC20 CMDC4 CMDC14 +VRAM_1.5VS DIS@ RV142 240_0402_1% DIS@ RV143 240_0402_1% 1 2 CV175 0.1U_0402_16V4Z +MEM_VREF6 C Mode D Address 21,27 DQSC#[7..0] DQSC#[7..0] 21,27 D CMDC12 CMDC27 CMDC26 DIS@ +VRAM_1.5VS DIS@ RV144 240_0402_1% M8 H1 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 M2 N8 M3 @ VREFCA VREFDQ DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 CK CK CKE/CKE0 CMDC18 CMDC16 CMDC30 CMDC15 CMDC13 K1 L2 J3 K3 L3 ODT/ODT0 CS/CS0 RAS CAS WE E3 F7 F2 F8 H3 H8 G2 H7 MDC39 MDC33 MDC38 MDC32 MDC36 MDC34 MDC37 MDC35 D7 C3 C8 C2 A7 A2 B8 A3 MDC44 MDC43 MDC47 MDC40 MDC45 MDC42 MDC46 MDC41 +MEM_VREF7 Group4 Group5 CMDC9 CMDC11 CMDC8 CMDC25 CMDC10 CMDC24 CMDC22 CMDC7 CMDC21 CMDC6 CMDC29 CMDC23 CMDC28 CMDC20 CMDC4 CMDC14 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ 310mAVDDQ VDDQ DQSL VDDQ DQSU VDDQ CMDC12 CMDC27 CMDC26 B2 D9 G7 K2 K8 N1 N9 R1 R9 M8 H1 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 +VRAM_1.5VS BA0 BA1 BA2 J7 K7 K9 F3 C7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 CLKC1 CLKC1# CMDC19 DQSC4 DQSC5 UV14 M2 N8 M3 @ VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 J7 K7 K9 CK CK CKE/CKE0 A1 A8 C1 C9 D2 E9 F1 H2 H9 CMDC18 CMDC16 CMDC30 CMDC15 CMDC13 K1 L2 J3 K3 L3 ODT/ODT0 CS/CS0 RAS CAS WE A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 DQMC7 DQMC6 E7 D3 DQSC#7 DQSC#6 G3 B7 MDC63 MDC58 MDC62 MDC59 MDC60 MDC61 MDC57 MDC56 D7 C3 C8 C2 A7 A2 B8 A3 MDC54 MDC48 MDC52 MDC50 MDC53 MDC51 MDC55 MDC49 CMD0 VDD VDD VDD VDD VDD VDD VDD VDD VDD B2 D9 G7 K2 K8 N1 N9 R1 R9 Group6 +VRAM_1.5VS 2 DIS@ CV176 0.1U_0402_16V4Z 1 DQMC4 DQMC5 E7 D3 DQSC#4 DQSC#5 G3 B7 CMDC5 ZQ6 DQSC7 DQSC6 F3 C7 A1 A8 C1 C9 D2 E9 F1 H2 H9 L8 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 CMDC5 T2 ZQ7 RV148 @ 80.6_0402_1% VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ DIS@ RV18 160_0402_1% CLKC1# L8 ODT_L CMD3 CKE CMD4 A14 CMD5 RST A14 RST CMD6 A9 A9 CMD7 A7 A7 CMD8 A2 A2 CMD9 A0 A0 CMD10 A4 A4 CMD11 A1 A1 CMD12 BA0 BA0 CMD13 WE* WE* CMD14 A15 A15 CMD15 CAS* CAS* DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ C CS0_H# ODT_H CMD18 CKE_H CMD19 CMD20 A13 CMD21 A8 A13 A8 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 CMD22 A6 A6 CMD23 A11 A11 CMD24 A5 A5 CMD25 A3 A3 CMD26 BA2 BA2 CMD27 BA1 BA1 CMD28 A12 A12 B1 B9 D1 D8 E2 E8 F9 G1 G9 CMD29 A10 A10 CMD30 RAS* RAS* LOW HIGH B Not Available 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 +VRAM_1.5VS DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ CV196 0.1U_0402_16V4Z CV195 0.1U_0402_16V4Z 2 CV194 0.1U_0402_16V4Z 1 CV193 0.1U_0402_16V4Z 2 CV192 0.1U_0402_16V4Z 1 CV187 0.1U_0402_16V4Z 2 CV186 0.1U_0402_16V4Z 1 CV185 0.1U_0402_16V4Z 2 CV184 0.1U_0402_16V4Z CV183 0.1U_0402_16V4Z DIS@ 1 CV191 1U_0402_6.3V6K DIS@ 2 CV190 1U_0402_6.3V6K DIS@ 1 CV189 1U_0402_6.3V6K DIS@ 2 CV188 1U_0402_6.3V6K DIS@ 1 CV182 0.1U_0402_16V4Z +VRAM_1.5VS CV181 1U_0402_6.3V6K 2 J1 L1 J9 L9 96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 @ CV177 0.01U_0402_16V7K CV178 1U_0402_6.3V6K NV recommand 0720 1 CV180 1U_0402_6.3V6K RV150 @ 80.6_0402_1% CV179 1U_0402_6.3V6K CLKC1# DIS@ RV147 243_0402_1% B1 B9 D1 D8 E2 E8 F9 G1 G9 2 1 DIS@ RV146 243_0402_1% CLKC1 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 2 CLKC1 J1 L1 J9 L9 CMD2 CMD17 1 B T2 DML DMU 32..63 CS0_L# CMD16 VDDQ VDDQ VDDQ VDDQ VDDQ 310mAVDDQ VDDQ DQSL VDDQ DQSU VDDQ +MEM_VREF7 DIS@ RV145 240_0402_1% 0..31 CMD1 Group7 +VRAM_1.5VS BA0 BA1 BA2 CLKC1 CLKC1# CMDC19 +VRAM_1.5VS DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 DIS@ A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title N13P DDR3 9/9 Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 28 of 60 5 4 3 2 1 @ 2 1 RV204 +LCD_VDD 33_0402_5% 1 RV206 300_0603_5% +3VS BKOFF# BKOFF# RV207 33_0402_5% Vds=-20V Id=-3A Rds=130m ohm Vgs=-4.5 Vth=-1 BKOFF#_R QV5A 2N7002DW-T/R7_SOT363-6 RV208 100K_0402_5% CV250 .1U_0402_16V7K 1 2 RV209 10K_0402_5% 2 3 G D 38 +3VS 1 6 2 CV249 180P_0402_50V8J 3 14 +3VS 4.7K_0402_5% 1 0_0402_5% PCH_ENVDD QV5B UMA@ RV212 D QV7 AO3413_SOT23 2 47K_0402_5% CV251 0.01U_0402_25V7K 5 4 14 DIS@ RV205 0_0402_5% 20 VGA_ENVDD RV210 1 PCH_BL_PWM UMA@ RV211 20 LCD_BL_PWM 0_0402_5% D DIS@ RV203 S VGA_PNL_PWM +LCD_VDD 2N7002DW-T/R7_SOT363-6 REMOVE LCD_VDDR W=60mils RV213 100K_0402_5% 2 @ CV254 4.7U_0805_10V4Z CV255 0.1U_0402_16V4Z CV252 CV253 4.7U_0805_10V4Z 0.1U_0402_16V4Z Close to JLVDS1 C C LCD_TZOUT0+ LCD_TZOUT0LCD_TZOUT1+ LCD_TZOUT1LCD_TZOUT2+ LCD_TZOUT2- 14 14 LCD_TXCLK+ LCD_TXCLK- 14 14 LCD_TZCLKLCD_TZCLK+ RV504 UMA@ RV505 UMA@ RV506 UMA@ RV507 UMA@ RV508 UMA@ RV509 UMA@ PNL_TX_OUT0+ PNL_TX_OUT0PNL_TX_OUT1+ PNL_TX_OUT1PNL_TX_OUT2+ PNL_TX_OUT2- 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% RV510 UMA@ RV511 UMA@ RV512 UMA@ RV513 UMA@ RV514 UMA@ RV515 UMA@ PNL_TZ_OUT0+ PNL_TZ_OUT0PNL_TZ_OUT1+ PNL_TZ_OUT1PNL_TZ_OUT2+ PNL_TZ_OUT2- 0_0402_5% 0_0402_5% RV516 UMA@ PNL_TX_CLK+ RV517 UMA@ PNL_TX_CLK- PNL_TZ_OUT1+ PNL_TZ_OUT1- 0_0402_5% 0_0402_5% RV518 UMA@ PNL_TZ_CLKRV519 UMA@ PNL_TZ_CLK+ PNL_TZ_OUT0+ PNL_TZ_OUT0- @ +LCD_INV +LCD_INV +LCD_INV BKOFF#_R LCD_BL_PWM PNL_TZ_CLK+ PNL_TZ_CLKPNL_TZ_OUT2+ PNL_TZ_OUT2- PNL_TX_CLK+ PNL_TX_CLKPNL_TX_OUT2+ PNL_TX_OUT2VGA_TXOUT0+ VGA_TXOUT0VGA_TXOUT1+ VGA_TXOUT1VGA_TXOUT2+ VGA_TXOUT2- 22 22 22 22 22 22 VGA_TZOUT0+ VGA_TZOUT0VGA_TZOUT1+ VGA_TZOUT1VGA_TZOUT2+ VGA_TZOUT2- 22 22 VGA_TXCLK+ VGA_TXCLK- 22 22 VGA_TZCLK+ VGA_TZCLK- 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% RV520 DIS@ RV521 DIS@ RV522 DIS@ RV523 DIS@ RV524 DIS@ RV525 DIS@ PNL_TX_OUT0+ PNL_TX_OUT0PNL_TX_OUT1+ PNL_TX_OUT1PNL_TX_OUT2+ PNL_TX_OUT2- 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% RV526 DIS@ RV527 DIS@ RV528 DIS@ RV529 DIS@ RV530 DIS@ RV531 DIS@ PNL_TZ_OUT0+ PNL_TZ_OUT0PNL_TZ_OUT1+ PNL_TZ_OUT1PNL_TZ_OUT2+ PNL_TZ_OUT2- 0_0402_5% 0_0402_5% RV532 DIS@ PNL_TX_CLK+ RV533 DIS@ PNL_TX_CLK- 0_0402_5% 0_0402_5% RV534 DIS@ PNL_TZ_CLK+ RV535 DIS@ PNL_TZ_CLK- PNL_TX_OUT1+ PNL_TX_OUT1PNL_TX_OUT0+ PNL_TX_OUT0LCD_DATA LCD_CLK 0.1U_0402_16V4Z @ CV257 +3VS 1 22 22 22 22 22 22 +LCD_VDD +LCD_VDD 2 B +LVDS_CAM RV216 100K_0402_5% Check Camera power USB20_P10_R USB20_N10_R CV258 0.1U_0402_16V4Z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 JLVDS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 G1 G2 G3 G4 G5 G6 41 42 43 44 45 46 15 RU21 0_0402_5% WCM-2012-900T_0805 USB20_P10 3 3 2 2 USB20_P10_R 4 4 @ 15 1 1 LU7 RU20 0_0402_5% USB20_N10 USB20_N10_R USB20_P10_R B USB20_N10_R 2 14 14 14 14 14 14 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 3 LCD_TXOUT0+ LCD_TXOUT0LCD_TXOUT1+ LCD_TXOUT1LCD_TXOUT2+ LCD_TXOUT2- @ D5003 L30ESDL5V0C3-2_SOT23-3 1 14 14 14 14 14 14 1.5A STARC_107K40-000001-G2 2 +LCD_INV FBMA-L11-201209-221LMA30T_0805 LV30 1 B+ 1 +3VS 20 14 A 14 20 VGA_LCD_CLK LCD_EDID_CLK LCD_EDID_DATA VGA_LCD_DATA 0_0402_5% 0_0402_5% RV500 DIS@ LCD_CLK RV502 UMA@ 0_0402_5% 0_0402_5% RV503 UMA@ LCD_DATA RV501 DIS@ RV214 W=20mils 0_0603_5% +LVDS_CAM 2 +5VS @ RV215 0_0603_5% 1 CV259 68P_0402_50V8J LCD/PANEL BD. Conn. CV256 0.1U_0402_16V4Z 2 @ CV261 680P_0402_50V7K Rated Current MAX:3000mA A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/05/23 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 CV260 0.1U_0402_25V6 4 3 2 Title LVDS Size Document Number Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 29 of 60 5 4 3 2 1 AZC099-04S.R7G_SOT23-6 VGA_CRT_G_L2 1 I/O1 I/O3 4 2 GND VDD 5 3 I/O2 I/O4 @ DV1 6 VGA_CRT_R_L2 +5VS UMA@ RV194 RV195 RV196 CRT_B CV229 CV230 CV231 CV232 VGA_CRT_R_L2 VGA_CRT_G_L LV23 1 2 INDUC_ 39NH +-5% VGA_CRT_G_L2 VGA_CRT_B_L LV24 1 2 INDUC_ 39NH +-5% VGA_CRT_B_L2 CV233 CV234 CV235 2.2P_0402_50V8C DIS@ LV21 1 2 INDUC_ 39NH +-5% LV22 1 2 INDUC_ 39NH +-5% 2.2P_0402_50V8C 20 VGA_CRT_B CRT_G VGA_CRT_R_L 2.2P_0402_50V8C UMA@ 2.2P_0402_50V8C PCH_CRT_B DIS@ 2.2P_0402_50V8C 14 20 VGA_CRT_G LV20 1 2 INDUC_ 39NH +-5% 2.2P_0402_50V8C PCH_CRT_G LV19 1 2 INDUC_ 39NH +-5% 2.2P_0402_50V8C 14 UMA@ CRT_R 150_0402_1% PCH_CRT_R 0_0402_5% R190 0_0402_5% R191 0_0402_5% R188 0_0402_5% R189 0_0402_5% R186 0_0402_5% R187 150_0402_1% 14 DIS@ 150_0402_1% 20 VGA_CRT_R CV236 2.2P_0402_50V8C D VGA_CRT_B_L2 2.2P_0402_50V8C D CV237 +3VS C C +CRT_VCC RV198 RV197 14 20 PCH_CRT_CLK VGA_CRT_CLK 2 R182 0_0402_5% CRT_DATA UMA@ 0_0402_5% R184 CRT_CLK DIS@ 0_0402_5% R185 QV4A 6 1 5 DIS@ VGA_CRT_DATA R183 0_0402_5% 2 1 3 AZC099-04S.R7G_SOT23-6 @ CV242 470P_0402_50V8J HSYNC 1 I/O1 I/O3 4 CRT_DDC_CK 2 GND VDD 5 +5VS 3 I/O2 I/O4 @ DV3 6 CRT CONNECTOR CRT_DDC_DAT JCRT_T22 VGA_CRT_R_L2 +CRT_VCC 5 1 40mil Y 20DIS@ CRT_VSYNC 10_0402_5% A Y 4 D_VGA_CRT_VSYNC 10_0402_5% @ CV248 A Compal Secret Data Security Classification Issued Date 2011/05/23 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 16 17 VSYNC RV202 @ CV247 5 G G 5 1 2 A Close to CRT Connecter VSYNC JCRT_T21 B ALLTO_C10532-11505-L_15P-T UV17 SN74AHCT1G125GW_SOT353-5 R179 0_0402_5% HSYNC VGA_CRT_B_L2 CRT_DDC_CK G R175 0_0402_5% RV200 +CRT_VCC UV16 SN74AHCT1G125GW_SOT353-5 3 VGA_CRT_VSYNC 14UMA@ HSYNC @ JCRT 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 10P_0402_50V8J +CRT_VCC 1 2 CV246 0.1U_0402_16V4Z PCH_CRT_VSYNC D_VGA_CRT_HSYNC 4 10P_0402_50V8J R180 0_0402_5% A P OE# 20DIS@ 2 P OE# VGA_CRT_HSYNC CRT_HSYNC CRT_DDC_DAT VGA_CRT_G_L2 G R181 0_0402_5% 10K_0402_5% 3 14UMA@ CV240 @ 0.1U_0402_16V4Z CRT_DDC_CK 3 VSYNC PCH_CRT_HSYNC 40mil RB491D_SOT23-3 2N7002DW-T/R7_SOT363-6 QV4B 4 RV199 1 +CRT_VCC FV1 SMD1812P075TF .75A 13.2V 2 If=1A B 1 2 CV245 0.1U_0402_16V4Z +CRT_VCC_R DV2 CRT_DDC_DAT 2N7002DW-T/R7_SOT363-6 @ CV241 @CV244 @ CV244 470P_0402_50V8J 33P_0402_50V8K @ CV243 33P_0402_50V8K 4.7K_0402_5% 20 UMA@ PCH_CRT_DATA 4.7K_0402_5% 14 +5VS 3 2 Title Compal Electronics, Inc. CRT Size Document Number Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 30 of 60 5 4 3 2 1 +HDMI_5V_OUT +5VS_HDMI (pin 19) plug in 5V DIS@ VGA_HDMI_HPD +HDMI_5V_OUT R979 1K_0402_5% R165 0_0402_5% CV262 0.1U_0402_16V4Z L88 PBY160808T-121Y-N 0603 2 1 HDMI_HPD HDMI_HPD 1 20 2 0.5A 15VDC_FUSE R166 0_0402_5% 0.1U_0402_16V4Z D HDMI_SDATA HDMI_SCLK @ C380 D34 BAV99_SOT23-3 220P_0402_25V8J HDMI_R_CK- 2 F2 1 1 CV272 UMA@ UMA_HDMI_HPD R980 100K_0402_5% RB161M-20_SOD123-2 DV5 2 +5VS 14 3 40mil HDMI_R_CK+ HDMI_R_D0- +3VS ESD, near DV5. 1 CU8 2 .1U_0402_16V7K HDMI_R_D0+ HDMI_R_D1- 2011-1228 ESD Solution Close to D34 HDMI_R_D1+ HDMI_R_D2HDMI_R_D2+ @ JHDMI 19 HP_DET 18 +5V 17 DDC/CEC_GND 16 SDA 15 SCL 14 Reserved 13 CEC 12 CK11 CK_shield 10 CK+ 9 D08 D0_shield 7 D0+ 6 D15 D1_shield 4 D1+ GND 3 D2GND 2 D2_shield GND 1 D2+ GND +3VS D 23 22 21 20 SUYIN_100042GR019M23MZR +HDMI_5V_OUT UMA@ 22 VGA_HDMI_DATA DIS@ 2 UMA_HDMI_DATA SCLK_HDMI 3 1 2 14 R167 0_0402_5% R170 0_0402_5% D DIS@ HDMI_SCLK Q182 BSH111_SOT23-3 UMA_HDMI_TXCUMA_HDMI_TX0UMA_HDMI_TX1UMA_HDMI_TX2- 14 14 14 14 UMA_HDMI_TXC+ UMA_HDMI_TX0+ UMA_HDMI_TX1+ UMA_HDMI_TX2+ 14 14 14 14 UMA@ CV318 UMA@ CV321 G UMA@ VGA_HDMI_CLK S UMA_HDMI_CLK 22 R1328 4.7K_0402_5% 2 2 G 14 1 1 place near JHDMI connect R1329 4.7K_0402_5% VGA_HDMI_CLKVGA_HDMI_TX0VGA_HDMI_TX1VGA_HDMI_TX2- VGA_HDMI_CLKVGA_HDMI_TX0VGA_HDMI_TX1VGA_HDMI_TX2- 22 22 22 22 VGA_HDMI_CLK+ VGA_HDMI_TX0+ VGA_HDMI_TX1+ VGA_HDMI_TX2+ VGA_HDMI_CLK+ VGA_HDMI_TX0+ VGA_HDMI_TX1+ VGA_HDMI_TX2+ DIS@ CV275 DIS@ CV313 DIS@ CV276 DIS@ CV314 D 22 22 22 22 HDMI_SDATA 1 S C R171 SDATA_HDMI 3 0_0402_5% R174 Q183 0_0402_5% BSH111_SOT23-3 DIS@ CV312 .1U_0402_16V7K DIS@ CV273 .1U_0402_16V7K .1U_0402_16V7K DIS@ CV277 .1U_0402_16V7K DIS@ CV274 .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K VGA_DVI_TXCVGA_DVI_TXD0VGA_DVI_TXD1VGA_DVI_TXD2- UMA@ CV317 UMA@ CV322 UMA@ CV320 .1U_0402_16V7K UMA@ CV315 .1U_0402_16V7K .1U_0402_16V7K UMA@ CV319 .1U_0402_16V7K UMA@ CV316 .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K PCH_HDMI_TXCPCH_HDMI_TXD0PCH_HDMI_TXD1PCH_HDMI_TXD2PCH_HDMI_TXC+ PCH_HDMI_TXD0+ PCH_HDMI_TXD1+ PCH_HDMI_TXD2+ C PCH_HDMI_TXC+ 1 VGA_DVI_TXC+ VGA_DVI_TXD0+ VGA_DVI_TXD1+ VGA_DVI_TXD2+ 4 R164 @ 0_0402_5% L17 UMA@ 2 1 2 4 3 HDMI_R_CK+ 3 WCM-2012-900T PCH_HDMI_TXC- R168 0_0402_5% @ 12NH_LQG15HS12NJ02D_5%_0402 @ LV31 HDMI_R_CK+ 1 2 VGA_DVI_TXC+ PCH_HDMI_TXD0+ @ L14 WCM-2012-900T 4 4 1 3 3 4 1 1 L9 1 VGA_DVI_TXC- 2 2 HDMI_R_CK- 2 1 B VGA_DVI_TXD0- 4 3 PCH_HDMI_TXD1+ @ L15 1 3 4 4 3 @ PCH_HDMI_TXD2+ @ 1 1 R177 0_0402_5% UMA@ 2 2 4 3 VGA_DVI_TXD2+ PCH_HDMI_TXD2- 2 1 2 L11 HDMI_R_D11 2 DIS@LV36 @ 12NH_LQG15HS12NJ02D_5%_0402 12NH_LQG15HS12NJ02D_5%_0402 @ LV37 HDMI_R_D2+ 1 2 1 VGA_DVI_TXD2- 4 3 HDMI_R_D2+ 3 R178 0_0402_5% HDMI_R_D2- UMA 680_0402_5% DIS 499_0402_1% HDMI_R_CK+ DIS@ HDMI_R_CKDIS@ HDMI_R_D1DIS@ HDMI_R_D1+ DIS@ HDMI_R_D0DIS@ HDMI_R_D0+ DIS@ HDMI_R_D2+ DIS@ HDMI_R_D2DIS@ WCM-2012-900T 4 B HDMI_R_D1- WCM-2012-900T 3 3 2 1 2 L12 HDMI_R_D21 2 DIS@LV38 @ 12NH_LQG15HS12NJ02D_5%_0402 A 1 R690 1 R691 1 R692 1 R693 1 R694 1 R695 1 R696 1 R697 2 TMDS_GND 499_0402_1% 2 499_0402_1% 2 499_0402_1% 2 499_0402_1% 2 499_0402_1% 2 499_0402_1% 2 499_0402_1% 2 499_0402_1% D 1 VGA_DVI_TXD1- 3 R176 0_0402_5% @ 1 2 WCM-2012-900T 4 3 HDMI_R_D1+ 2 PCH_HDMI_TXD1- WCM-2012-900T 4 R173 0_0402_5% UMA@ 1 L16 4 HDMI_R_D0- 3 2 1 2 L10 HDMI_R_D01 2 DIS@LV34 @ 12NH_LQG15HS12NJ02D_5%_0402 12NH_LQG15HS12NJ02D_5%_0402 @ LV35 HDMI_R_D1+ 1 2 VGA_DVI_TXD1+ 3 R172 0_0402_5% @ WCM-2012-900T 4 4 HDMI_R_D0+ WCM-2012-900T PCH_HDMI_TXD0- DIS@ @ LV32 12NH_LQG15HS12NJ02D_5%_0402 12NH_LQG15HS12NJ02D_5%_0402 @ LV33 HDMI_R_D0+ 1 2 VGA_DVI_TXD0+ 1 R169 0_0402_5% UMA@ 2 2 HDMI_R_CK- 3 R698 R691 680_0402_5% UMA@ R692 680_0402_5% UMA@ R693 680_0402_5% UMA@ R694 680_0402_5% UMA@ R695 680_0402_5% UMA@ R696 680_0402_5% UMA@ R697 680_0402_5% UMA@ A QV12 SSM3K7002FU_SC70-3 2 G +3VS R690 680_0402_5% UMA@ S 1M_0402_5% Compal Secret Data Security Classification C266 Issued Date 0.1U_0402_16V4Z 2011/05/23 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 5 4 3 2 Compal Electronics, Inc. HDMI Connector Document Number Rev 1.0 QAL51, LA-7871P MB Wednesday, March 07, 2012 Sheet 1 31 of 60 A B C WLAN/BT combo D +3VS +1.5VS 1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z PCIE_WAKE# R5103 BT_ON R5141 @ 0_0402_5% 1 WLANCLK_REQ# 13 13 CLK_PCIE_WLAN# CLK_PCIE_WLAN PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 13 13 13 PCIE_PTX_WLANRX_N2 13PCIE_PTX_WLANRX_P2 +3VS E51_TXD E51_RXD BT_ON 0_0402_5% 13 BT_ON R5139 R5122 R5121 100K_0402_5% 0_0402_5% 0_0402_5% R5140 1K_0402_0.5% 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 CW23 CW25 JWLAN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 GND1 47P_0402_50V8J 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 CW24 CW26 2 CW28 2 CW27 @ E 4.7U_0805_10V4Z 47P_0402_50V8J 4.7U_0805_10V4Z +3VS WL_OFF# PLT_RST# R5111 1 For SED request +1.5VS For SED request 38 WL_OFF# 0_0603_5% +3VS PCH_SMBCLK PCH_SMBDATA USB20_N13 USB20_P13 15 15Bluetooth 3.0 54 GND2 LOTES_AAA-PCI-049-P06-A 2 2 NewCard & Smart Card 13 13 @ JMOD 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 GND 28 GND CLK_PCIE_EXP# CLK_PCIE_EXP PCIE_PRX_EXPTX_N3 13 PCIE_PRX_EXPTX_P3 13 13 PCIE_PTX_EXPRX_N3 13 PCIE_PTX_EXPRX_P3 NewCard USB20_N8 USB20_P8 13 EXPCLK_REQ# 14,33 PCIE_WAKE# +1.5VS +1.5VS +3VALW +3VS +3VS +3VS 15,20,33,37,38,5 PLT_RST# SUSP# 38,44,51 SYSON 15 EXP_CPPE# 10,11,13 PCH_SMBCLK 10,11,13 PCH_SMBDATA 3 15 15 EXPCLK_REQ# PCIE_WAKE# PLT_RST# SUSP# SYSON EXP_CPPE# 38,44,49,50,51,56,9 3 ACES_51522-02601-001 4 4 Compal Secret Data Security Classification Issued Date 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. WLAN/ WWAN/ m-SATA Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet E 32 of 60 A B C D U4201 13 PCIE_PRX_GLANTX_P1 C4201 .1U_0402_16V7K PCIE_PRX_GLANTX_P1_C 13 PCIE_PRX_GLANTX_N1 C4202 .1U_0402_16V7K PCIE_PRX_GLANTX_N1_C 23 22 17 18 13 PCIE_PTX_GLANRX_P1 13 PCIE_PTX_GLANRX_N1 +3V_LAN HSOP HSON HSIP HSIN LED3/EEDO LED1/EESK LED0 31 37 40 EECS/SCL EEDI/SDA 30 32 R4201 R4202 MDIP0 MDIN0 MDIP1 MDIN1 NC/MDIP2 NC/MDIN2 NC/MDIP3 NC/MDIN3 1 2 4 5 7 8 10 11 LAN_MDI0+ LAN_MDI0LAN_MDI1+ LAN_MDI1LAN_MDI2+ LAN_MDI2LAN_MDI3+ LAN_MDI3- L4201,C4205 will be changed to 2.2uH&4.7uF after EVT test R4212 0_0402_5% 10K_0402_5% 10K_0402_5% L4201 13 LANCLK_REQ# PLT_RST# 15,20,32,37,38,5 PLT_RST# 1 13 13 0_0402_5% CLK_PCIE_LAN CLK_PCIE_LAN# CLK_PCIE_LAN CLK_PCIE_LAN# +3VS LAN_X1 LAN_X2 16 CLKREQB 25 PERSTB 19 20 REFCLK_P REFCLK_N 43 CKXTAL1 44 R4206 1K_0402_1% 14,32 R4207 15K_0402_5% PCIE_WAKE# PCIE_WAKE# 28 LANW AKEB ISOLATEB 26 ISOLATEB R4204 R4205 +3V_LAN 10K_0402_5% 1K_0402_5% ENSWREG +3V_LAN @ PCIE_WAKE# R4209 100K_0402_5% +LAN_VDDREG C4234 0.1U_0402_16V4Z CKXTAL2 14 15 38 NC/SMBCLK NC/SMBDATA GPO/SMBALERT 33 ENSW REG 34 35 VDDREG VDDREG 46 R4208 2.49K_0402_1% 24 49 2 RSET GND PGND +LAN_VDD10 1 Layout Note: LL1 must be within 200mil to Pin36, C4205 CL13,CL9 must be within4.7U_0603_6.3V6K 200mil to LL1 R4213 0_0402_5% @ 2 C4206 0.1U_0402_16V4Z C4211 0.1U_0402_16V4Z C4212 0.1U_0402_16V4Z C4213 0.1U_0402_16V4Z C4214 0.1U_0402_16V4Z C4215 0.1U_0402_16V4Z C4216 13 29 41 +LAN_VDD10 DVDD33 DVDD33 27 39 +3V_LAN AVDD33 AVDD33 AVDD33 AVDD33 12 42 47 48 EVDD10 21 +LAN_EVDD10 0.1U_0402_16V4Z C4217 AVDD10 AVDD10 AVDD10 AVDD10 3 6 9 45 +LAN_VDD10 0.1U_0402_16V4Z C4218 0.1U_0402_16V4Z C4219 0.1U_0402_16V4Z C4220 REGOUT 36 0.1U_0402_16V4Z C4221 0.1U_0402_16V4Z C4222 0.1U_0402_16V4Z C4223 +LAN_VDD10 1 +LAN_EVDD10 0_0603_5% R4210 C4207 1U_0402_6.3V4Z +3V_LAN C4208 0.1U_0402_16V4Z Close to Pin 3,6,9,13,29,41,45 +LAN_VDD10 Close to Pin 21 +3V_LAN +LAN_VDDREG +LAN_REGOUT 60 mils 0_0603_5% RTL8111E-VL_QFN48_6X6 R4211 1 C4209 4.7U_0603_6.3V6K 25MHZ_20PF_7V25000016 C4210 0.1U_0402_16V4Z 2 2 C4218,C4219,C222 close to pin6,9,41, respectively 1 3 GND GND 2 4 LAN_X2 3 @ D11 U4202 C4203 27P_0402_50V8J C4204 27P_0402_50V8J LAN_MDI3- 要>1ms and <100ms 1 LAN_MDI3+ 2 +3V_Lan Rise time(10%~90%) 3 +3VALW TO +3V_LAN 4 5 LAN_MDI2@ PJ4201 3 0.1U_0402_16V4Z DVDD10 DVDD10 DVDD10 YL4201 LAN_X1 1 +3V_LAN Close to Pin 27,39,12,42,47,48 40 mils +LAN_REGOUT 1 2 2.2UH_1008HC-472EJFS-A_5%_1008 ENSWREG R4203 E 2 +3VALW 1 @ C4232 4.7U_0805_10V4Z QL1 AO3413_SOT23 D S 3 1:1 TD1+ T1/B 1 TX1+ 24 RJ45_MIDI3- TX1- 23 RJ45_MIDI3+ TDCT1 T1/A 1:1 TXCT1 22 1 R4214 TXCT2 21 TDCT2 TD2+ TX2+ 20 T1/B 6 2 75_0402_1% 1 2 R4215 75_0402_1% RJ45_MIDI2- @ JLAN TD2TX2- 19 LAN_MDI1- 7 1:1 TD3+ T1/B 18 RJ45_MIDI3- 8 PR4- RJ45_MIDI3+ 7 PR4+ RJ45_MIDI1- 6 PR2- RJ45_MIDI2- 5 PR3- RJ45_MIDI2+ 4 PR3+ RJ45_MIDI1+ 3 PR2+ RJ45_MIDI0- 2 PR1- RJ45_MIDI0+ 1 PR1+ RJ45_MIDI2+ T1/A RJ45_MIDI1- 2 G LAN_MDI1+ 38 8 C4235 0.1U_0402_16V4Z LAN_MDI0- LAN_MDI0+ TD3- 9 TDCT3 T1/A 10 11 TDCT4 TD4+ 1:1 12 4 TX3- 17 TXCT3 16 TXCT4 15 TX4+ 14 T1/B LAN Conn. RJ45_MIDI1+ 1 R4216 1 R4217 RJ45_MIDI0- 2 75_0402_1% TD4TX4- SANTA_130452-0E1 13 RJ45_MIDI0+ RJ45_GND C4224 C4228 1000P_1808_3KV7K 1000P_0402_50V7K LANGND 1 2 1 C4225 0.1U_0402_16V4Z 2 C4226 4 4.7U_0603_6.3V6K 350UH_LG-2419P-1~D Compal Secret Data Security Classification Issued Date 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B 10 9 2 75_0402_1% T1/A Place CL34 colse to LAN chip SHLD2 SHLD1 RJ45_C_GND C4227 0.1U_0402_25V6 A LANGND 3 L30ESDL5V0C3-2_SOT23-3 Close to JLAN.9 3 LAN_MDI2+ C4233 1U_0402_6.3V6K LAN_PWR_EN# LANGND 1 TX3+ RL1 0_0402_5% LANGND 3 L30ESDL5V0C3-2_SOT23-3 Close to JLAN.10 @ D7 LANGND 2 TD1- +3V_LAN PAD-OPEN 2x2m 2 1 C D Title Compal Electronics, Inc. PCIe-LAN-RTL8111E Size Document Number Custom Date: Rev 1.0 QAL51, LA-7871P MB Wednesday, March 07, 2012 Sheet E 33 of 60 5 4 3 2 1 RA2 600 mA0.1U_0402_16V4Z +PVDD1 CA57 1 2 CA56 D CA8 10U_0805_10V4Z @ 0_0402_5% RA34 @ 0_0402_5% RA32 0_0603_5% +DVDD_IO CA1 0.1U_0402_16V4Z 2 CA2 10U_0805_10V4Z 2 place close to chip CA61 2 2 2 10U_0805_10V4Z place close to chip MIC2R_R 2 21K_0402_5% MIC2R_L 1K_0402_5% 4.7U_0402_6.3V6M 4.7U_0402_6.3V6M CA26 CA28 MIC1_C_R 22 MIC1_C_L 21 1U_0402_6.3V6K 1U_0402_6.3V6K MIC2_R MIC2_L +MIC1_VREFO_L +MIC1_VREFO_R +MIC2_VREFO CA12 place close to chip CA18 2 1 0.1U_0402_16V4Z CA17 2 110U_0805_10V4Z MONO_IN 100P_0402_50V8J AZ_SYNC_HD 20K_0402_1% CA35 2 2.2U_0603_6.3V6K RA10 AC_JDREF 110U_0805_10V4Z AC_VREF CA14 CPVEE CA16 2.2U_0603_6.3V6K RA18 1 20K_0402_1% 2 RA16 39.2K_0402_1% 38 38 1 RA17 2 20K_0402_1% EAPD EC_MUTE# DVDD DVDD_IO AVDD1 AVDD2 MIC1_VREFO_L MIC1_VREFO_R MIC2_VREFO PVDD1 PVDD2 39 46 15 14 LINE2_R LINE2_L SPK_OUT_R+ SPK_OUT_R- 45 44 SPKR+ SPKR- 20 MONO_OUT SPK_OUT_L+ SPK_OUT_L- 40 41 SPKL+ SPKL- 12 PCBEEP_IN 10 SYNC HPOUT_R HPOUT_L 33 32 11 RESET# 19 28 27 34 35 36 JDREF LDO_CAP VREF CPVEE CBN CBP BITCLK 6 NC NC NC 13 18 SENSE_A SENSE_B EAPD EC_MUTE# 47 4 EAPD PD# CA6 +5VS 26 37 42 43 7 THERMAL_PAD 49 RA13 SPK_L1 0_0603_5% CA19 CA42 1U_0402_6.3V4Z @ CA46 @ 10U_0805_10V4Z SPKL- SPK_L2 RA14 0_0603_5% SPKR+ RA4 75_0402_1% RA5 75_0402_1% AZ_SDOUT_HD AZ_SDIN0_HD_R RA6 SPK_R1 RA15 0_0603_5% HP_R 35 HP_L 35 AZ_BITCLK_HD AZ_BITCLK_HD @ @ R1370 10U_0805_10V4Z CA45 1U_0402_6.3V4Z @ CA39 AZ_SDOUT_HD 12 12 AZ_SDIN0_HD 33_0402_5% C CA51 @ 10U_0805_10V4Z @ SPKR- SPK_R2 RA44 0_0603_5% 12 C692 SPEAKER CONN YSDA0502C_SOT23-3 10P_0402_50V8J 2 1 AGND Close to Audio Chip 3 DA8 DGND @ JSPK 1 1 2 2 3 3 4 4 5 G1 6 G1 SPK_L2 SPK_L1 SPK_R2 SPK_R1 YSDA0502C_SOT23-3 ALC259-VB5-GR_QFN48_7X7 B 10U_0805_10V4Z place close to chip 24 23 48 AVSS1 AVSS2 PVSS1 PVSS2 DVSS 1 @ +PVDD1 +PVDD2 10_0402_5% GPIO0/DMIC_DATA GPIO1/DMIC_CLK SENSE_A SENSE_B CA5 1 2 2 2 2 10U_0805_10V4Z 0.1U_0402_16V4Z MIC2_R MIC2_L 5 8 CA4 1 SPKL+ 31 30 29 SDATA_OUT SDATA_IN 1 CA3 1 9 25 38 2 3 MIC_PLUG HP_PLUG 2 10U_0805_10V4Z placement near Audio Codec MIC1_R MIC1_L 17 16 C AZ_RST_HD# 2 2 place close to chip CA47 1 2 0.1U_0603_50V7K CA48 1 2 0.1U_0603_50V7K CA49 1 2 0.1U_0603_50V7K CA50 1 3 DA9 EC Beep 38 PCH_SPKR CA15 RA9 47K_0402_5% INT_MIC 0.1U_0402_16V4Z 1 CA20 0.1U_0402_16V4Z 2 Ext.MIC/LINE IN JACK MIC1_LINE1_R_L SENSE A SENSE B Function 39.2K PORT-I (PIN 32, 33) Headphone out 20K PORT-B (PIN 21, 22) 20K PORT-F (PIN 16, 17) 5 2011/05/23 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Int. MIC 4 3 RA37 2 1K_0402_5% RA48 2 1 2 1 1K_0402_5% RA38 1 2.2K_0402_5% +MIC1_VREFO_R MIC1_R 35 MIC1_L 35 A 2 RA46 1 2.2K_0402_5% +MIC1_VREFO_L Compal Electronics, Inc. Compal Secret Data Security Classification Ext. MIC DA10 W M-64PCY_2 A Codec Signals 3 220P_0402_25V8J MIC1_LINE1_R_R Impedance 2 @ C379 W M-64PCY_2 MIC2 15@ 1 1 2 2 MONO_IN RA11 10K_0402_5% Sense Pin Int. MIC YSDA0502C_SOT23-3 MIC1 14@ 1 1 2 2 47K_0402_5% 1 12 2 RA51 1 4.7K_0402_5% +MIC2_VREFO RA8 EC_BEEP# PCI Beep 0_0603_5% B E&T_3802-E04N-01R 1 2 0.1U_0603_50V7K RA43 D RA3 10U_0805_10V4Z 0.1U_0402_16V4Z CA9 CA10 AZ_SYNC_HD 0.1U_0402_16V4Z +5VS 1 1 CA59 CA58 @ @ 0_0603_1% CA60 @ @ +AVDD MIC1_LINE1_R_R MIC1_LINE1_R_L 12 1 0.1U_0402_16V4Z U143 12 2 10U_0805_10V4Z RA12 1 0_0603_5% 1 RA25 1 RA26 2 +PVDD2 1 68 mA INT_MIC 2 10U_0805_10V4Z +3VS 1 CA7 0.1U_0402_16V4Z place close to chip RA39 @ +3VS_DVDD 35 mA RA1 +5VS CA43 1 0_0603_5% +3VS 2 1 JA1 JUMP_43X39 0.1U_0402_16V4Z 1 1 CA44 0_0603_5% 1 2 Title HD CODEC ALC259 Size Document Number Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 34 of 60 5 4 3 2 1 HEADPHONE OUT JACK CONN@ SINGA_2SJ2285-112252_6P-T 4 34 HP_R HP_L D HP_PLUG 6 HP_R 34RA52 1 2 0_0603_5% HP_R_1 5 2 HP_L 34RA53 1 2 0_0603_5% HP_L_1 1 SHLD1 HP_PLUG D 2 CA71 33P_0402_50V8J JHP @ DA12 YSDA0502C_SOT23-3 1 2 1 3 1 CA70 33P_0402_50V8J 2 3 MICROPHONE IN JACK CONN@ SINGA_2SJ2285-112252_6P-T 34 MIC_PLUG MIC1_R MIC1_L C 6 MIC1_R R4 134 2 0_0603_5% MIC1_R_1 5 2 MIC1_L R3 134 2 0_0603_5% MIC1_L_1 1 SHLD1 4 MIC_PLUG C 3 1 2 2 2 1 CA69 33P_0402_50V8J @ DA11 YSDA0502C_SOT23-3 1 CA68 33P_0402_50V8J 3 JMIC Touch/B Connector C5002 TP_CLK 3 D5002 AZ5125-02S.R7G_SOT23-3 JFP C480 0.1U_0402_16V4Z FP@ 15 15 15@ SMT1-05_4P 1 3 2 4 SW4 14@ SMT1-05_4P For ESD SW3 3 1 3 2 4 2 4 SW5 A SW6 Title Size Date: 4 R133 0_0603_5% FP@ 14@ SMT1-05_4P 1 6 5 A FP@ D82 L30ESDL5V0C3-2_SOT23-3 @ 1 2 3 4 GND GND 1 RIGHT_BTN# 1 4 6 5 3 2 6 5 1 1 2 3 4 5 6 ACES 85201-0405N 4P FP_GND 15@ SMT1-05_4P LEFT_BTN# 5 +3VS_FP USB20_N12 USB20_P12 USB20_N12 USB20_P12 3 1 R134 2 0_0603_5% FP@ 2 +3VS @ 1 @ D5001 AZ5125-02S.R7G_SOT23-3 38 38 TP_CLK TP_DATA 1 LEFT_BTN# RIGHT_BTN# C5004 100P_0402_50V8J 6 5 4 3 2 1 C5003 100P_0402_50V8J GND GND 6 5 4 3 2 1 @ JTP RIGHT_BTN# 3 8 7 B LEFT_BTN# TP_DATA 2 0.1U_0402_16V4Z 2 ACES_85201-0605N 2 B 6 5 +5VS Finger Printer Connector 3 2 Card Reader RTS5129 QAL51, LA-7871P MB Document Number Wednesday, March 07, 2012 Sheet 1 35 of 60 Rev 1.0 5 4 3 2 1 SATA ODD Conn. @ JODD 12 12 D SATA_PTX_DRX_P2 SATA_PTX_DRX_N2 12 SATA_PRX_C_DTX_N2 12 SATA_PRX_C_DTX_P2 0.01U_0402_25V7K14@ 0.01U_0402_25V7K14@ C518 C519 SATA_PTX_C_DRX_P2 SATA_PTX_C_DRX_N2 0.01U_0402_25V7K14@ 0.01U_0402_25V7K14@ C424 C425 SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 +5VS_ODD 1 2 3 4 5 6 7 GND A+ AGND BB+ GND 8 9 10 11 12 13 JODD_T23 +5VS DP +5V +5V MD GND GND R107 +5VS_ODD D 15 14 GND GND SANTA_206401-1_RV 0_0805_5% C3609 1U_0402_6.3V6K Placea caps. near ODD CONN. 0.1U_0402_16V4Z +5VS_ODD C3601 14@ 1000P_0402_50V7K 10U_0805_10V4Z C3602 14@ C3603 14@ 14@ C3604 1U_0402_6.3V4Z ACES_85201-14051 C C SATA_PTX_C_DRX_P2 SATA_PTX_C_DRX_N2 SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 15 USB20_N5 +5VS_ODD 15 USB20_P5 16 ODD_EN# +VSBP 14 13 12 11 10 9 8 7 6 5 4 3 2 1 @ J15ODD SATA HDD Conn. @ JHDD B 12 12 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 12 SATA_PRX_C_DTX_N0 12 SATA_PRX_C_DTX_P0 0.01U_0402_25V7K 0.01U_0402_25V7K C512 C513 SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0 0.01U_0402_25V7K 0.01U_0402_25V7K C410 C412 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 +5VS GND A+ AGND BB+ GND V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12 B GND GND 23 24 SANTA_190501-1 A A +5VS 1.2A Place component's closely HDD CONN. C387 10U_0805_10V4Z C388 0.1U_0402_16V4Z C389 0.1U_0402_16V4Z C390 0.1U_0402_16V4Z Compal Secret Data Security Classification 2011/05/23 Issued Date 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. SATA HDD / ODD Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 36 of 60 5 4 3 2 1 SPI ROM For Basic ME ROM size (w/o Braidwood & system BIOS): 4MByte D D +3VS TPM@ C764 TPM@ C765 0.1U_0402_16V4Z C764 close pin 24 TPM 1.2 +3VALW +3VL 1U_0402_6.3V4Z C765 close pin 10 Base I/O Address R12 0_0603_5% C @ R17 @R17 0_0603_5% 0 = 02Eh * 1 = 04Eh C +3VS TPM@ R727 10K_0402_5% LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 26 23 20 17 CLK_PCI_TPM15 LPC_FRAME# CLK_PCI_TPM 12,38 LPC_FRAME# 15,20,32,33,38,5 PLT_RST# 12,38 SERIRQ PM_CLKRUN# +3VS R665 TPM@ 4.7K_0402_5% +TPM_VSB @ R667 4.7K_0402_5% LPCPD# TESTB1/BADD TEST1 XTALO XTALI TPM SLB 9635 TT 1.1 LCLK LFRAME# GPIO2 LRESET# GPIO SERIRQ CLKRUN# PP NC NC NC GND GND GND GND PLT_RST# SERIRQ PM_CLKRUN#14 21 22 16 27 15 7 LAD0 LAD1 LAD2 LAD3 VSB VDD VDD VDD +3VS 4 11 18 25 12,38 12,38 12,38 12,38 5 24 19 10 +TPM_VSB TPM@ U36 28 9 8 14 13 TPM_TEST1 +3VS R661 TPM@ 0_0402_5% R659 TPM@ 4.7K_0402_5% TPM_XTALO TPM_XTALI @ R662 4.7K_0402_5% 2 6 1 3 12 SLB-9635-TT-1.2_TSSOP28 C766 TPM@ 15P_0402_50V8J @ R772 0_0402_5% TPM_XTALI 2 @ R669 10_0402_5% 1 @ C768 15P_0402_50V8J 1 CLK_PCI_TPM 2 B TPM@ R668 10M_0402_5% B Y4 32.768KHZ_12.5PF_CM31532768DZFT TPM@ TPM_XTALO C767 TPM@ 15P_0402_50V8J A A Compal Secret Data Security Classification Issued Date 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. TPM Size Document Number Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 37 of 60 5 4 3 +EC_VCCA L4901 FBMA-L11-160808-800LMT_0603 C4907 1 2 +EC_VCCA +3VALW _EC 0.1U_0402_16V4Z +3VL R4901 0_0805_5% @ C381 C4901 C4902 +3VALW _EC 0.1U_0402_16V4Z C4903 C4904 C4905 KSI[0..7] KSO[0..15] ECAGND 0.1U_0402_16V4Z KSI[0..7] 42 KSO[0..15] 42 Analog Board ID definition, Please see page 3. Board ID +3VL 31_LP@ R4903 8.2K_0402_5% 31_GT@ R4903 18K_0402_1% 1000P_0402_50V7K +3VL 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K PLT_RST# 820P_0402_25V R4902 100K_0402_5% Ra D 15,20,32,33,37,5 PLT_RST# 47K_0402_5% C4911 16 0.1U_0402_16V4Z EC_SCI# PW R_SAVING_LED KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 +3VL EC_SMB_CK1 2 2.2K_0402_5% EC_SMB_DA1 2 2.2K_0402_5% 1 R4906 1 R4909 C +3VS 2 PCH_SMLCLK 2.2K_0402_5% 2 PCH_SMLDATA 2.2K_0402_5% 1 R4922 1 R4923 +3VL D4902 @ R4920 EC_SMI# 1K_0402_1% 1 2 PCH_SMI# 16 RB751V-40_SOD323-2 +3VALW R4939 CHG_MODE1 10K_0402_5% R4942 CHG_MODE0 10K_0402_5% EC_SMB_CK1 EC_SMB_DA1 PCH_SMLCLK PCH_SMLDATA EC_SMB_CK1 EC_SMB_DA1 46,47 46,47 PCH_SMLCLK13,20 PCH_SMLDATA 13,20 GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC & MISC LPC_AD0 GPIO0F BEEP#/GPIO10 GPIO12 ACOFF/GPIO13 21 23 26 27 BATT_TEMP/GPIO38 GPIO39 ADP_I/GPIO3A GPIO3B GPIO42 IMON/GPIO43 63 64 65 66 75 76 DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D IREF/GPIO3E CHGVADJ/GPIO3F 68 70 71 72 EC_MUTE#/GPIO4A USB_EN#/GPIO4B CAP_INT#/GPIO4C EAPD/GPIO4D TP_CLK/GPIO4E TP_DATA/GPIO4F 83 84 85 86 87 88 EC_MUTE_R R4907 USB_EN# CHG_MODE0 EAPD TP_CLK TP_DATA CPU1.5V_S3_GATE/GPXIOA00 WOL_EN/GPXIOA01 HDA_SDO/GPXIOA02 VCIN0_PH/GPXIOD00 97 98 99 109 CPU1.5V_S3_GATE 9 CPU1.5V_S3_GATE W L_OFF# 32 W L_OFF# ME_EN ME_EN R4911 0_0402_5% VCIN0_PH 9012@ SPIDI/GPIO5B SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A 119 120 126 128 EC_SI_SPI_SO EC_SO_SPI_SI EC_SPICLK EC_SPICS# ENBKL/GPIO40 PECI_KB930/GPIO41 FSTCHG/GPIO50 BATT_CHG_LED#/GPIO52 CAPS_LED#/GPIO53 PWR_LED#/GPIO54 BATT_LOW_LED#/GPIO55 SYSON/GPIO56 VR_ON/GPIO57 PM_SLP_S4#/GPIO59 73 74 89 90 91 92 93 95 121 127 UMA@ R4914 DIS@ R4915 PECI_KB930 R4930 PCH_PW R_EN BATT_FULL_LED# CAPS_LED# PW R_ON_LED BATT_CHG_LOW _LED# SYSON VR_ON PM_SLP_S4# EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04 PROCHOT_IN/GPXIOA05 H_PROCHOT#_EC/GPXIOA06 VCOUT0_PH/GPXIOA07 GPO BKOFF#/GPXIOA08 PBTN_OUT#/GPXIOA09 PCH_APWROK/GPXIOA10 SA_PGOOD/GPXIOA11 100 101 102 103 104 105 106 107 108 PCH_RSMRST# EC_LID_OUT# R4913 9012@ PCH_PW ROK_930 BKOFF# PBTN_OUT# W L_BT_LED# SA_PGOOD AC_IN/GPXIOD01 EC_ON/GPXIOD02 ON/OFF/GPXIOD03 GPI LID_SW#/GPXIOD04 SUSP#/GPXIOD05 GPXIOD06 PECI_KB9012/GPXIOD07 110 112 114 115 116 117 118 ACIN_D EC_ON_R ON/OFF_R LID_SW _IN# SUSP# V18R 124 +V18R PWM Output AD Input CLK_PCI_EC PCIRST#/GPIO05 EC_RST# EC_SCII#/GPIO0E GPIO1D DA Output 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 77 78 79 80 EC_SMB_CK1/GPIO44 EC_SMB_DA1/GPIO45 SM EC_SMB_CK2/GPIO46 EC_SMB_DA2/GPIO47 PS2 Interface PM_SLP_S3# PM_SLP_S5# EC_SMI# SPI Flash ROM GPIO Bus R4937 53 VR_HOT# PCH_HOT# 10K_0402_5% 47 14,53 15,40 41 VR_HOT# 32 32 C4916 47P_0402_50V8J 14 R4931 @ 1 C4919 VCOUT1_PH 122 123 SUSCLK_R SUSCLK_R 2 @ XCLKI/GPIO5D XCLKO/GPIO5E 100K_0402_5% 20P_0402_50V8 9012@ GPIO R4929 100K_0402_5% 0.1U_0402_16V4Z ECAGND 1 100P_0402_50V8J 2 C4909 ADP_I AD_BID0 PCH_HOT#_R P8_Throttling 46 33 BATT_TEMPA LAN_PW R_EN# 46,47 ADP_I R4934 0_0402_5% PCH_HOT# 13 PCH_HOT# 20 P8_Throttling +5VS TP_CLK 2 4.7K_0402_5% 2 4.7K_0402_5% TP_DATA 0_0402_5% EC_MUTE# 34 EC_MUTE# 40,43 43 34 35 35 USB_EN# CHG_MODE0 EAPD TP_CLK TP_DATA 1 R4908 1 R4910 C 14,20,47 ACIN PECI_KB9012 +3VL D4901 ACIN_D 12 46 2 1 RB751V-40_SOD323-2 R4941 10K_0402_5% PCH_PW ROK 0_0402_5% 0_0402_5% 43_0402_1% 14 20 16,5 PCH_ENBKL VGA_BKL_EN H_PECI VR_ON R4943 10K_0402_5% PCH_PW R_EN 44 Please place R4930 close to EC with in 750mil 42 BATT_FULL_LED# +3VL 42 CAPS_LED# PW R_ON_LED 42 BATT_CHG_LOW42 _LED# R4916 330K_0402_5% 32,44,51 SYSON P8_Throttling 53 VR_ON PM_SLP_S4# 14 VCIN1_PH 1 2 @ R5013 47K_0402_5% R4912 9012@ 29 BKOFF# PBTN_OUT# W L_BT_LED# SA_PGOOD R4938 R4940 14 42 52 R4944 9012@ R5015 1 EC_ON ON/OFF 40 32,44,49,50,51,56,9 15,43 H_PECI 10P_0402_50V8J 41,48 41 C4918 SA_PGOOD 0.1U_0402_16V4Z 43_0402_1% Co-lay KB930/KB9012 PECI C4914 EC_MUTE# Stuff 4.7U_0805_10V4Z R4935 10K_0402_5% KB9012QF-A2_LQFP128_14X14 20mil L4902 ECAGND 2 1 FBMA-L11-160808-800LMT_0603 ECAGND PCH_PW ROK_930 0_0402_5% KB930 R4930 KB9012 R4944 ACIN C4915 2 100P_0402_50V8J 1 A 46 14 PCH_PW ROK Compal Secret Data Security Classification 2011/05/23 Issued Date PCH_PW ROK PCH_PW ROK_R 0_0402_5% R4918 9012@ 4 Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 B +3VL 2 47K_0402_5% LID_SW _IN# C5036 0_0402_5% 0_0402_5% LID_SW _IN# SUSP# USB_OC0# 14 16 46 46 48 PCH_RSMRST# EC_LID_OUT# VCIN1_PH VCOUT1_PH VCOUT0_PH VCIN1_PH 0_0402_5% 0_0402_5% 2 R4921 930@ 5 PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 GPIO0A GPIO0B GPIO0C GPIO0D EC_INVT_PWM/GPIO11 FAN_SPEED1/GPIO14 EC_PME#/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PCH_PWROK/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A @ P 2 43 PCH_PW ROK_R Breathing_LED 42 NUM_LED# G NC A FAN_SPEED CHG_MODE1 Breathing_LED 5 SN74LVC1G06DCKR_SC70-5 1 Y 3 46,5 4 1 H_PROCHOT# VGATE C4917 R4936 0_0402_5% U4902 H_PROCHOT# 0.1U_0402_16V4Z +3VS BT_ON 47 32 GND/GND GND/GND GND/GND GND/GND GND0 @ GREEN_PW R4 BT_ON GREEN_PW R VGATE USB_OC4# FAN_SPEED CHG_MODE1 E51_TXD E51_RXD 51_GT@ for R4903 NC 34 41 EC_BEEP# FANPW M BATT_TEMPA SPI Device Interface 11 24 35 94 113 14 14 +3VS EC_BEEP# FANPW M ACOFF 51_GS@ R4903 100K_0402_5% R4945 330K_0402_5% B 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 EC_VDD/AVCC EC_RST# EC_SCI# PW R_SAVING_LED 42 12 13 37 20 38 CLK_PCI_LPC R4905 +3VL 1 2 3 4 5 7 8 10 AGND/AGND 15 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 69 C4910 @ 22P_0402_50V8J R4904 2 1 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD0 EC_VDD/VCC 16 12,37 12,37 12,37 12,37 @ 33_0402_5% 12,37 12,37 ID@ C4908 R4903 0_0402_5% Rb D 50@ R4903 56K_0402_1% AD_BID0 67 9 22 33 96 111 125 +EC_VCCA U4901 A 1 C4906 KB_RST# 820P_0402_25V @ C383 2 2 Title Compal Electronics, Inc. EC ENE-KB930/Co-lay 9012 Size B Date: Document Number Rev 1.0 QAL51, LA-7871P MB W ednesday, March 07, 2012 Sheet 1 38 of 60 5 4 3 2 1 BIOS Bus switch SPI ROM For Basic ME ROM size 4MByte D D BIOS SPI Flash (4MByte*1) U59 12 12 12 PCH_SPI_MOSI PCH_SPI_CLK PCH_SPI_CS# R401 PCH_SPI_MOSI_R 5 PCH_SPI_CLK_R 6 PCH_SPI_CS_R# 1 33_0402_5% R402 33_0402_5% R407 0_0402_5% 7 +3VS SI SO PCH_SPI_MISO_R 2 PCH_SPI_MISO 12 PCH_SPI_MISO R403 33_0402_5% SCLK CS HOLD 3 WP 8 VCC GND 4 MX25L3205AZMC-20G_SON8 C405 0.1U_0402_16V4Z For EMI resuest. P/N: SA00003K800 C @C361 @ C361 C @ R419 PCH_SPI_CLK_R 6P_0402_25V C402 10_0402_5% 12P_0402_50V8J BIOS SPI Flash (2MByte*1) For Win8 +3VS WIN8@ R408 0_0402_5% 12 B PCH_SPI_CS1# PCH_SPI_MISO PCH_SPI_CS1# +3VS R406 33_0402_5% WIN8@ U60 WIN8@ PCH_SPI_CS1_R# 1 PCH_SPI_MISO_WIN8 2 3 4 CS# SO WP# GND VCC HOLD# SCLK SI 8 7 6 5 MX25L1606EM2I-12G_SO8 WIN8@ R405 PCH_SPI_CLK_WIN8 33_0402_5% PCH_SPI_CLK PCH_SPI_MOSI_WIN8 PCH_SPI_MOSI R404 33_0402_5% WIN8@ C406 0.1U_0402_16V4Z WIN8@ B For EMI resuest. @ C362 @ R420 PCH_SPI_CLK_WIN8 6P_0402_25V 10_0402_5% C403 12P_0402_50V8J WIN8@ A A Compal Secret Data Security Classification Issued Date 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. SBIOS & EC ROM Size Document Number Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet 1 39 of 60 5 4 3 2 1 USB + Audio SB HeadPhone/LINE Out JACK Ext.MIC/LINE IN JACK JUSB @ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 +5VALW W=200mils D 15 15 USB20_N4 USB20_P4 15 15 USB20_N9 USB20_P9 15,38 USB20_N4 USB20_P4 USB20_N9 USB20_P9 USB_OC4# USB_EN# USB_OC4# USB_EN# 38,43 USB20_N11 15 USB20_P11 15 USB20_N11 USB20_P11 LID_SW _IN# +3VL +3VS RV217 0_0402_5% 38 14@ 25 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 D GND1 GND2 ACES_85208-24071 C C Lid Switch +3VL (Hall Effect Switch) 1 VDD 2 GND OUTPUT 3 U5002 AH180W G-7_SC59-3 B 15@ RV218 0_0402_5% 2 15@ 1 LID_SW _IN# B C5034 0.1U_0402_16V4Z 15@ For EMI +V1.05S_VCCP @ 2 C5100 1 +3VS 0.1U_0402_16V4Z A A Compal Electronics, Inc. Compal Secret Data Security Classification 2011/05/23 Issued Date Deciphered Date 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Function Board Size Document Number Rev 1.0 QAL51, LA-7871P MB Date: W ednesday, March 07, 2012 Sheet 1 40 of 60 A B C D E Power Button To POWER/B ON/OFF switch +3VL +3VALW 1 +5VALW PWR_ON_LED# Breathing_LED# R4803 @ 100K_0402_5% TOP Side 100K_0402_5% D4801 2 R4806 ON/OFFBTN# 1 ZZZ 1 2 3 4 5 6 GND GND PCB-MB 7 8 ACES_85201-0605N 38 ON/OFF 1 51_ON# 3 100K_0402_5% ON/OFFBTN# R4804 JPOWER DAN202UT106_SC70-3 1 @ 1 ON/OFFBTN# Breathing_LED# R4805 FD2 EC_ON 2 G R4802 2 Test Only @ FIDUCIAL_C40M80 @ FIDUCIAL_C40M80 2 D @ FIDUCIAL_C40M80 FD4 38,48 Q4801 2N7002_SOT23-3 S D4802 AZ5125-02S.R7G_SOT23-3 3 EC_ON 100K_0402_5% @ 3 1 FIDUCIAL_C40M80 FD3 1 FD1 Bottom Side 1 @ @ 1 2 3 4 5 6 42 42 2 1 10K_0402_5% Screw Hole VGA @ H_3P0 @ @ H51 H_3P0N 1 H_3P0 @ H9 1 H_3P0 @ H8 1 H_3P0 @ H7 1 H6 1 H_3P0 @ H12 H_3P7X4P2 1 1 H11 3 H_3P0 @ H5 1 H_3P0 @ H4 1 H_3P0 @ H3 H_3P0 @ H13 H_3P7X4P2 @ 1 1 Fan Control Circuit H2 1 H1 1 MB Boss H_3P7 3 @ +3VS 2 38 FAN_SPEED 1 +5VS 2 +FAN1 C4803 0.01U_0402_25V7K @ @ H41 1 2 2 D4804 2 BAS16_SOT23-3 2 C4802 1 C4801 H_3P7 @ H_3P2 @ 1000P_0402_50V7K 1 1SS355TE-17_SOD323-2 10U_0805_10V6K 1 C4800 10U_0805_10V6K 1 @ Close to Connector D4803 H23 H_3P7X4P2 @ WLAN +5VS 1 @ 40 mils +FAN1 2 0_0603_5% H22 H_3P7X4P2 1 H21 1 G6 G5 4 3 2 1 JFAN H42 1 1 R4800 FANPWM FANPWM 1 1A 2 38 6 5 4 3 2 1 H_3P5X3P0N @ 4 1 H10 H_3P0 @ H_3P0 @ Compal Secret Data Security Classification 2011/05/23 Issued Date 4 H24 1 1 CPU ACES_85205-04001 R4801 10K_0402_5% 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. PWRBTN/ FAN / Screws Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet E 41 of 60 LED 15@ LED10 2 3 SATA INT_KBD Conn. HT-110NBQA_BULE_1204 R5006 820_0402_5% 1 2 +5VS 1 14@ Blue 1 LED2 2 PCH_SATALED# 12 HT-260NB-A168_BLUE_0603 14" Battery LED 15@ LED9 HT-210UD/NB_AMB/BLUE Battery R5008 820_0402_5% 1 2 +5VALW For EMC KSO10 C5017 38 BATT_CHG_LOW_LED# 100P_0402_50V8J C5019 100P_0402_50V8J C5021 100P_0402_50V8J KSI[0..7] C5022 100P_0402_50V8J KSO[0..15] C5024 100P_0402_50V8J C5025 100P_0402_50V8J C5026 100P_0402_50V8J C5027 100P_0402_50V8J KSO15 Blue 2 C5018 KSO12 1 NB 100P_0402_50V8J KSO11 Amber 3 UD 要要要要 BATT_FULL_LED#38 KSI7 KSI2 KSI[0..7] 38 KSO[0..15] 38 KSI3 A 2 3 B 4 1 KSI4 KSI0 JKB @ KSI5 LED3 14@ EVERLIGHT__18-225A/S2B6W-C01/3T 0603 ORG/BLU C5028 100P_0402_50V8J C5029 100P_0402_50V8J C5030 100P_0402_50V8J C5008 100P_0402_50V8J KSI0 KSI1 KSO0 KSO1 KSI2 KSI3 KSI4 KSI5 KSO2 KSI6 KSI7 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO2 KSI6 KSI1 LED11 15@ 2 Wireless +5VS A 3 R5011 820_0402_5% 1 2 KSO2 1 KSO1 HT-110UD5_AMBER 100P_0402_50V8J C5006 100P_0402_50V8J KSO0 Amber 14@ LED6 2 1 C5005 WL_BT_LED# KSO4 38 C5007 100P_0402_50V8J C5009 100P_0402_50V8J C5010 100P_0402_50V8J KSO3 HT-191UD_Amber_0603 KSO5 KSO14 Power R5007 820_0402_5% 1 2 +5VALW Blue 14@ 2 PWR_ON_LED# 1 LED4 PWR_ON_LED# 41 D 100P_0402_50V8J C5013 100P_0402_50V8J C5014 100P_0402_50V8J C5015 100P_0402_50V8J C5016 100P_0402_50V8J KSO13 Q4 2N7002_SOT23-3 2 G PWR_ON_LED 38 KSO8 3 S 2 3 15@ LED12 100P_0402_50V8J C5012 KSO7 1 HT-260NB-A168_BLUE_0603 C5011 KSO6 KSO9 1 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 G2 G1 28 27 ACES_88747-2601 HT-110NBQA_BULE_1204 3 R5012 2 3 G 15@ 15@ CAPS_LED# 38 LED7 15@ 14@ LED13 2 +5VALW White 1 HT-110BP5_WHITE LED8 12-23A-R6GHBHC-A01-2D_RGB B 200_0805_5% HT-110BP5_WHITE CAPS_LED# 1 3 PWR_ON_LED# G 2 2 Breathing_LED# R 1 +5VS G CAP Lock 1 R5017 1 2 4 200_0805_5% Breathing Blue 1 4 2 Breathing_LED# 3 PWR_ON_LED# 1 2 D Q2 2N7002_SOT23-3 2 G Breathing_LED 38 S B 200_0805_5% 3 1 G +5VALW Breathing_LED# 41 R R5014 12-23A-R6GHBHC-A01-2D_RGB LED5 LED15 15@ 2 +5VALW R5016 820_0402_5% 1 2 A 3 Power Saving 1 HT-110UD5_AMBER 14@ LED14 2 1 HT-191UD_Amber_0603 VL 1 @ R5018 2 820_0402_5% Amber Compal Secret Data Security Classification Issued Date 2011/05/23 Deciphered Date 2012/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Compal Electronics, Inc. KB/EC ROM/TP/FUN/LED 38 PWR_SAVING_LED Size B Date: Document Number Rev 1.0 QAL51, LA-7871P MB Wednesday, March 07, 2012 Sheet 42 of 60 A B USB3.0 Port 0 2.5A +5VALW C USB3.0 Port0 Port 0 : Left USB3.0 BUS_EN#_R 38,40 USB_EN# RU1 0_0402_5% GND VOUT VIN VOUT VIN VOUT EN FLG 1 + CU4 RU3 USB_OC0# 0_0402_5% 4.7U_0805_10V4Z USB_OC0# CU11 USB3_TX0_P_C 15 HM76@ 1 10 U3RXDN0_R_L U3RXDP0_R_L 2 9 U3RXDP0_R_L U3TXDN0_L 4 7 U3TXDN0_L U3TXDP0_L 5 6 U3TXDP0_L CHG_MODE0 3 U3TXDN0_L RU4 0_0402_5% 15 USB20_N0 15 USB20_P0 8 U3RXDP0_R_L @ RU7 0_0402_5% WCM-2012-121T_0805 4 3 4 3 HM76@ 1 LU2 USB3_RX0_N 3 38 8 USB20_N0 7 USB20_P0 6 5 +5VALW C892 .1U_0402_16V7K 1 CB TDM TDP VDD CEN# 1 DM 2 DP GND 4 Thermal Pad 9 CHG_MODE1 38 RU10 0_0402_5% 1 USB20_P0_U_L CB CHG_MODE0 1 1 LU3 2 RU8 0_0402_5% RU11 55584@ 0_0402_5% CHG_MODE1 L30ESDL5V0C3-2_SOT23-3 @ RU9 @ 0_0402_5% WCM-2012-900T_0805 3 3 4 4 2 USB20_N0_U USB20_P0_U 20 mil SLG55566VTR_TDFN8_2X2 2 SLG55566 (Pin4 to GND) USB20_P0_U USB20_N0_U 3 U3RXDN0_R_L RU6 0_0402_5% @ 2 2 USB20_N0_U_L 2 2 CHG_MODE0 DU2 USB20_P0_U_L 2011-1228 ESD Solution Close to RU2 UU3 AZ1045-04F_DFN2510 1 15 RU2 0_0603_5% 2 2 2 @ USB3_RX0_P 1 CU9 .1U_0402_16V7K 1 0.01U_0402_25V7K 15 USB30_GND USB30_GND USB30_GND USB30_GND 10 11 12 13 LOTES_AUSB0015-P001A SLG55566 1 LU1 USB3_TX0_N_C 15 1000P_0402_50V7K GND GND GND GND 15,38 U3RXDN0_R_L U3TXDP0_L RU5 0_0402_5% WCM-2012-121T_0805 4 4 3 3 1 CU12 U3TXDN0_L U3TXDP0_L 2 CU5 150U_B2_6.3VM_R35M @ DU1 @ 0.01U_0402_25V7K USB3_TX0_N U3RXDN0_R_L U3RXDP0_R_L CU2 1 2 USB3_TX0_P CU3 @ JUSB31 1 VBUS 2 D3 D+ 4 GND 5 StdA-SSRX6 StdA-SSRX+ 7 GND-DRAIN 8 StdA-SSTX9 StdA-SSTX+ USB20_N0_U_L USB20_P0_U_L 0.1U_0402_16V4Z CU1 4.7U_0805_10V4Z G547I2P81U_MSOP8 CU7 .1U_0402_16V7K +USB30_VCCP0 W=80mils 8 7 6 5 1 2011-1228 ESD Solution Close to UU1 E +USB30_VCCP0 UU2 1 2 3 4 D SELCDP CHG_MODE1 2 SLG55584 (Symbol Pin4) STATUS CB CHG_MODE0 SELCDP CHG_MODE1 STATUS 0 AUTO MODE 0 X AUTO MODE 1 Pass-Through (USB) Mode: Connect DP/DM to TDP/TDM 1 0 Pass-Through (USB) Mode: Connect DP/DM to TDP/TDM 1 1 S0 Charging with CDP or SDP only (depending on external device) USB20_N0_U_L @ USB3.0 Port 1 USB3.0 Port1 Port 1 : Left USB3.0 with e-SATA 3 3 USB3_TX1_P CU13 USB3_TX1_P_C 15 @ RU17 0_0402_5% WCM-2012-121T_0805 4 3 3 0.01U_0402_25V7K 4 HM76@ 1 USB3_TX1_N CU14 1 LU4 USB3_TX1_N_C 15 @ DU3 2 2 RU15 0_0402_5% @ U3TXDP1_L U3TXDN1_L 0.01U_0402_25V7K 15 @ RU16 0_0402_5% WCM-2012-121T_0805 4 3 3 USB3_RX1_P 4 HM76@ 1 15 15 1 LU5 USB3_RX1_N USB20_P1 USB20_P1 4 RU13 0_0402_5% 1 10 U3RXDN1_R_L U3RXDP1_R_L 2 9 U3RXDP1_R_L U3TXDN1_L 4 7 U3TXDN1_L U3TXDP1_L 5 6 U3TXDP1_L RU14 0_0402_5% U3RXDP1_R_L @ JUSB32 1 VBUS 2 D3 D+ 4 GND 5 StdA-SSRX6 StdA-SSRX+ 7 GND-DRAIN 8 StdA-SSTX9 StdA-SSTX+ U2DN1_L U2DP1_L U3RXDN1_R_L U3RXDP1_R_L U3TXDN1_L U3TXDP1_L 8 GND GND GND GND USB30_GND USB30_GND USB30_GND USB30_GND 10 11 12 13 LOTES_AUSB0015-P001A AZ1045-04F_DFN2510 CU6 .1U_0402_16V7K 2 U2DP1_L 3 15 USB20_N1 USB20_N1 2 1 1 3 3 4 4 WCM-2012-900T_0805 RU12 0_0402_5% @ U2DN1_L 2012-0109 ESD Solution Close to RU18 L30ESDL5V0C3-2_SOT23-3 @ Compal Secret Data Security Classification 2011/05/23 Issued Date 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B RU18 0_0603_5% 1 LU6 2 1 2 DU4 U2DN1_L U3RXDN1_R_L U2DP1_L @ +USB30_VCCP0 3 2 2 @ U3RXDN1_R_L C D Title 4 Compal Electronics, Inc. Power share ENE3810 Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet E 43 of 60 A B C D E +5VALW to +5VS For EMI R5531 820K_0402_5% VGA_PWROK# Q5518A Q5526 2N7002_SOT23-3 2 G VGA_PWROK Q5518B 2 VGA_PWROK# 2N7002DW-T/R7_SOT363-6 +5VALW @ +3VS For EMI Q5504 AO4478L 1N SO8 Q5506 2N7002_SOT23-3 C5528 0.1U_0402_25V6 1 +5VALW S SUSP SUSP 5 Q5511A 2 SUSP# +3VALW R5515 10K_0402_5% @ R5536 100K_0402_5% 3 5 R5517 10K_0402_5% 32,38,49,50,51,56,9 C5521 0.1U_0603_50V_X7R 3 Q5511B SYSON +1.5V_CPU_VDDQ 32,38,51 4 @ R5524 0_0402_5% 2N7002DW-7-F_SOT363-6 R5506 100K_0402_5% SYSON# R5507 100K_0402_5% 6 D 2 G 1 2 C5520 0.1U_0603_50V7K 3 Q5528 S SSM3K7002FU_SC70-3 +5VALW .1U_0402_16V7K C5511 C5513 0.1U_0603_50V7K 47K_0402_5% C5512 10U_0805_10V4Z 3 R5505 51 3 R5533 100K_0402_5% +1.5VS 1 Q5510 S SSM3K7002FU_SC70-3 R5534 20K_0402_5% 0.1U_0402_25V6 C3 C5527 2 47K_0402_5% D 2 G PCH_PWR_EN CHECK WITH CPU memory power AO3416_SOT23-3 Q5525 D @ 18 PCH_PWR_EN# 38 ERP LOT6 +1.5V 2 G R5510 PCH_PWR_EN# @ R5504 100K_0402_5% SUSP 1 @ R5523 0_0402_5% +1.5V To +1.5VS +5VALW 3 1 2 G R5529 100K_0402_5% 2N7002DW-7-F_SOT363-6 1 3 S C5510 0.1U_0603_50V7K SUSP C5509 1U_0603_10V4Z 100K_0402_5% D +3V_PCH Q5512 AO3413L_SOT23-3 C5508 10U_0805_10V4Z +VSBP 2 PAD-OPEN 2x2m 0.1U_0402_25V6 R5503 2 C5507 10U_0805_10V4Z PJP306 1 +3VALW 1 2 3 4 C5506 10U_0805_10V4Z S 5 +3VALW to +3VS +3VALW 8 7 6 5 D 3 1 1 56 3 C5523 R5532 +VSBP 220K_0402_5% R5516 10K_0402_5% 4 Q5502 @ 2 SUSP G 2N7002_SOT23-3 6 4 C2 470_0805_5% R5530 1U_0402_6.3V6K C5526 1 S C5524 4.7U_0805_10V4Z 1 3 S @ R5522 0_0402_5% R5528 100K_0402_5% C5525 1 2 3 5 4.7U_0805_10V4Z Q5503 2N7002_SOT23-3 3 1 C5505 0.1U_0603_50V7K D 2 G D Q5522 MDU1512RH_PPAK56-8-5 0.1U_0402_25V6 4 R5501 470_0603_5% 100K_0402_5% +VSBP SUSP C5504 +5VS_D R5502 C5503 C5502 10U_0805_10V4Z +5VALW +3VS +VRAM_1.5VS Vgs=10V,Id=14.5A,Rds=6mohm 1U_0603_10V4Z 1 +1.5V 1 2 3 10U_0805_10V4Z C5501 10U_0805_10V4Z +1.5V to +VRAM_1.5VS +5VS Q5501 AO4478L 1N SO8 8 7 6 5 0.1U_0402_25V6 +5VALW 3 +0.75VS +V1.05S_VCCP 3 0.75VR_EN +3VS +1.5VS +1.5V Q5520B 2N7002DW-T/R7_SOT363-6 R5520 22_0603_5% R5511 5 RUN_ON_CPU1.5VS3# D S 2 5,9 G @ R5526 1 3 Q5508B SUSP D 3 2 1 Q5509 S SSM3K7002FU_SC70-3 3 D 4 Q5508A 1 SUSP 2 Q5507 G S SSM3K7002FU_SC70-3 3 1 1 3 3 1 SSM3K7002FU_SC70-3 6 D 2 G S Q5516 SSM3K7002FU_SC70-3 S SUSP Q5517 SSM3K7002FU_SC70-3 4 D 2 G +3VS_D Q5514 SYSON# +1.5VS_D 2 2N7002DW-7-F_SOT363-6 470_0402_5% +DDR_CHG 470_0402_5% +1.5V_CPU_VDDQ_CHG 470_0402_5% 6 4 470_0402_5% +1.5V_D SUSP R5508 +V1.05S_VCCP_D Q5520A 2N7002DW-T/R7_SOT363-6 R5521 220_0402_5% R5509 R5518 R5535 100K_0402_5% 1 5 2N7002DW-7-F_SOT363-6 0.75VR_EN +V1.05S_VCCP_PWRGOOD 50,52 2 G 4 0_0402_5% R5527 SUSP 0_0402_5% Compal Secret Data Security Classification Issued Date 2011/05/23 2012/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. DC/DC Interface Size Document Number Custom Rev 1.0 QAL51, LA-7871P MB Date: Wednesday, March 07, 2012 Sheet E 44 of 60 www.s-manuals.com
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.4 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Create Date : 2012:03:07 15:51:38Z Creator Tool : PScript5.dll Version 5.2.2 Modify Date : 2016:01:23 10:51:32+02:00 Metadata Date : 2016:01:23 10:51:32+02:00 Format : application/pdf Creator : Title : Compal LA-7871P - Schematics. www.s-manuals.com. Subject : Compal LA-7871P - Schematics. www.s-manuals.com. Producer : GPL Ghostscript 8.15 Document ID : uuid:086aabcb-b077-436e-b268-870512f07f06 Instance ID : uuid:bd57c020-8157-4acc-8469-627bc6b18cac Page Count : 45 Keywords : Compal, LA-7871P, -, Schematics., www.s-manuals.com. Warning : [Minor] Ignored duplicate Info dictionaryEXIF Metadata provided by EXIF.tools