Compal LA 7983P Schematics. Www.s Manuals.com. R0.3 Schematics
User Manual: Motherboard Compal LA-7983P QIWG7 DIS - Schematics. Free.
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A B C D E 1 1 Compal Confidential 2 2 QIWG7 DIS M/B Schematics Document Intel Ivy Bridge Processor with DDRIII + Panther Point PCH nVIDIA N13P-GL 2011-12-28 3 3 LA-7983P REV:0.3 4 4 Issued Date 2011/10/27 2012/10/27 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. http://hobi-elektronika.net A Compal Electronics, Inc. Compal Secret Data Security Classification Cover Page Rev 0.3 LA-7983P Date: B C D Thursday, January 05, 2012 Sheet E 1 of 60 A B C D E Compal confidential ZZZ File Name : QIWG7 LS7988P CR_AUDIO/B LS7987P USB/B LS6753P PWR/B LS6758P LED/B LS675AP ODD/B LA7983 DA_PCB WĂŐĞϮϯͲϯϮ DA80000RL00 1 1 nVIDIA N13P-GL Intel Ivy Bridge PCI-E x16 ZĞǀĞƌƐĞDŽĚĞ VRAM 128*16 DDR3*8 WĂŐĞϯϱ HDMI Connector 2 CRT Connector USB3.0 *2(Left) 100MHz 2.7GT/s Zd LVDS WĂŐĞϯϯ Connector USB3.0 FDI *8 >s^ AZALIA USB2.0 *14 SATA *6 WĂŐĞϭϰͲϮϮ SPIROM BIOS WĂŐĞϭϰ WŽƌƚϱ Camera Conn.WĂŐĞϯϯ WŽƌƚϭϯ BlueTooth Conn. WĂŐĞϰϬ WŽƌƚϭϬ Mini Card Slot *1 WĂŐĞϯϲ Card Reader Reltek LPC BUS 3 Arthros WŽƌƚϭ WĂŐĞϰϮ EC WŽƌƚϭϭ WŽƌƚϵ WĂŐĞϯϳ WĂŐĞϰϭ WĂŐĞϰϯ WĂŐĞϰϯ 3 USB2.0 *1(Right) WĂŐĞϰϯ͖ϰϰ WĂŐĞϯϴ RJ-45 Connector Touch Pad WĂŐĞϰϯ WLAN 2 RTS5178 for SDR50 SDXC/MMC ENE KB9012 A3 AR8162(10/100) Audio Jacks WĂŐĞϰϭ PCI-E x1 *6 Renesas Mini Card Slot *1 Int. MIC x1 CX20671-21Z FCBGA 989 25mm*25mm WŽƌƚϯ͕WŽƌƚϰ uPD720202 PCI Express 2 channel speaker WĂŐĞϰϭ Audio Codec Conexant HM75 / HM76 WŽƌƚϰ AR8161(GLAN) WĂŐĞϭϮͲϭϯ Up to 8GB Dual Channel DDR3 1066MHz(1.5V) DDR3 1333MHz(1.5V) DDR3 1600MHz(1.5V) DMI *4 Intel Panther Point WĂŐĞϰϱ Option BANK 0, 1, 2, 3 WĂŐĞϱͲϭϭ W WĂŐĞϯϰ DDR3 SO-DIMM *2 Socket-rPGA989B 37.5mm*37.5mm WŽƌƚϭ WŽƌƚϮ WŽƌƚϯ Int. KBD WĂŐĞϰϯ WŽƌƚϬ PCI-E(WLAN) WŽƌƚϮ Thermal Sensor EMC1403 WŽƌƚϮ WĂŐĞϯϵ WĂŐĞϯϲ USB2.0 *3(Left) WĂŐĞϰϱ SATA HDD SATA ODD WĂŐĞϰϬ (Port 2/Port 3 co-layout with USB3.0 port3/port4) (Port 0/Port 1 support SATA3) WĂŐĞϰϬ 4 4 Issued Date 2011/10/27 2012/10/27 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. http://hobi-elektronika.net A Compal Electronics, Inc. Compal Secret Data Security Classification Block Diagram Rev 0.3 LA-7983P Date: B C D Thursday, January 05, 2012 Sheet E 2 of 60 A B C D Voltage Rails SIGNAL STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Full ON +5VS E +3VS power plane +1.5VS +V1.05S_VCCP 1 +5VALW +VGA_CORE +B +3VALW +VCC_GFXCORE_AXG BOARD ID Table +1.8VS Board ID / SKU ID Table for AD channel +0.75VS State Board ID 0 1 2 3 4 5 6 7 +1.05VS S0 O S3 1 +VCC_CORE +1.5V O O O O O O X O O X X O X X X X X X PCB Revision 0.1 Vcc Ra/Rc/Re Board ID 0 1 2 3 4 5 6 7 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V Porject G-series G-series G-series G-series Y-series Y-series Y-series Y-series Phase MP PVT DVT EVT EVT DVT PVT MP 2 2 S5 S4/AC S5 S4/ Battery only S5 S4/AC & Battery don't exist USB Port Table X USB 2.0 Port EC SM Bus2 address Device Device Smart Battery 0001 011X b Thermal Sensor F75303M UHCI1 Address EHCI1 1001_101xb USB3.0 Device Address DDR DIMM0 1001 000Xb DDR DIMM2 1001 010Xb UHCI4 EHCI2 Device Address Internal thermal sensor 1001 111Xb (0x9E) 4 SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 SMBCLK SMBDATA SML0CLK SML0DATA SML1CLK SML1DATA KB9012 +3VALW KB9012 +3VALW PCH +3VALW PCH +3VALW PCH +3VALW X X X X V +3VS BATT V X X X X +3VALW KB9012 SODIMM WLAN WWAN X X X X V +3VS X X V +3VS X X X X V +3VS X X http://hobi-elektronika.net A BTO Item USB Port (Left Side)USB2.0 USB Port (Left Side)USB3.0 USB Port (Left Side)USB3.0 Camera USB/B (Right Side USB-BD) Mini Card(WLAN) Card Reader Blue Tooth BOM Structure GPU:N13P-GL UMA only HDMI Interna-Intel-USB3.0 External-NEC-USB3.0 Blue Tooth Connector 45 LEVEL 10/100 LAN GIGA LAN Camera Green Clock Unpop SMBUS Control Table VGA UHCI5 UHCI6 NV-GPU SM Bus address SOURCE UHCI2 UHCI3 PCH SM Bus address 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 UHCI0 Address EC SM Bus1 address BOM Structure Table 3 External USB Port 3 Thermal Sensor PCH X X X X V +3VS X V +3VS X X X 4 2011/10/27 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/10/27 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: B N13P@ UMA@ HDMI@ IU3@ EU3@ BT@ ME@ 45@ 8162@ GIGA@ CMOS@ GCLK@ GCLK244@ @ C D Notes List Document Number Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet E 3 of 60 5 4 3 2 1 Hot plug detect for IFP link C VGA and GDDR3 Voltage Rails D ACTIVE (N13P GPIO) Performance Mode P0 TDP at Tj = 102 C* (DDR3) Function Description FBVDDQ (GPU+Mem) (1.35V) PCI Express I/O and PLLVDD (1.05V) (6) (1.8V) I/O and PLLVDD (1.05V) Other (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD GPIO I/O GPIO0 OUT - GPU VID4 GPIO1 OUT - GPU VID3 GPIO2 OUT H Panel Back-Light brightness(PWM capable) GPIO3 OUT H Panel Power Enable GPIO4 OUT H Panel Back-Light On/Off (PWM) Physical Strapping pin ROM_SCLK GPIO5 OUT - GPU VID1 ROM_SI +3VS_VGA RAM_CFG[3] ROM_SO +3VS_VGA FB[1] STRAP0 +3VS_VGA USER[3] USER[2] USER[1] STRAP1 +3VS_VGA STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0] STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED STRAP4 +3VS_VGA PCIE_SPEED_ CHANGE_GEN3 PCIE_MAX_SPEED DP_PLL_VDD33V GPIO6 OUT - GPIO7 OUT N/A GPIO8 I/O - Thermal Catastrophic Over Temperature GPIO9 OUT - Thermal Alert GPIO10 OUT - Memory VREF Control GPIO11 OUT - GPU VID0 GPU VID2 IN GPIO13 OUT - GPIO14 OUT N/A GPIO15 IN GPIO16 OUT AC Power Detect Input Mem (1,5) NVCLK /MCLK Products (W) (W) (MHz) (V) (A) (W) (A) N13P-GL 64bit 1GB DDR3 TBD TBD TBD TBD TBD TBD TBD IN GPIO18 IN GPIO19 (3.3V) D (10K pull low) Power Rail +3VS_VGA Logical Strapping Bit3 PCI_DEVID[4] Logical Strapping Bit2 SUB_VENDOR Logical Strapping Bit1 Logical Strapping Bit0 SLOT_CLK_CFG PEX_PLL_EN_TERM RAM_CFG[2] RAM_CFG[1] RAM_CFG[0] FB[0] SMB_ALT_ADDR VGA_DEVICE USER[0] 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] RESERVED 3GIO_PAD_CFG_ADR[0] C N13P-GL (28nm) ??? GPU VID5 Hot plug detect for IFP link C GPU GPIO17 FBVDD (1.35V) NVVDD Device ID C GPIO12 GPU (4) FB Memory (DDR3) ROM_SO ROM_SCLK ROM_SI STRAP2 STRAP1 STRAP0 64Mx16 PD 10K PD 15K PD 20K PU 20K PD 35K PU 45K 64Mx16 PD 10K PD 15K PD 15K PU 20K PD 35K PU 45K 128Mx16 PD 10K PD 15K PD 20K PU 20K PD 35K PU 45K N/A Samsung 900MHz N/A Hot Plug Detect for IFPE IN Hynix 900MHz N/A N13P-GL Samsung 900MHz B +3VS_VGA B Hynix 900MHz +VGA_CORE 128Mx16 PD 10K PD 15K PD 20K PU 20K PD 35K PU 45K tNVVDD >0 +1.5VS_VGA X76 tFBVDDQ >0 +1.05VS_VGA tPEX_VDD >0 1. all power rail ramp up time should be larger than 40us 2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ A A Tpower-off <10ms 2011/10/27 Issued Date Deciphered Date 2012/10/27 Title VGA Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. http://hobi-elektronika.net 5 Compal Electronics, Inc. Compal Secret Data Security Classification 1.all GPU power rails should be turned off within 10ms Rev 0.3 LA-7983P Date: 4 3 2 Thursday, January 05, 2012 Sheet 1 4 of 60 5 4 3 2 PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils - typical impedance = 14.5 mohms 1 +V1.05S_VCCP R1 24.9_0402_1% D DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 <16> <16> <16> <16> DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 <16> <16> <16> <16> DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 C +V1.05S_VCCP <16> <16> <16> <16> <16> <16> <16> <16> FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 <16> <16> <16> <16> <16> <16> <16> <16> FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 G21 E22 F21 D21 G22 D22 F20 C21 A21 H19 E19 F18 B21 C20 D18 E17 A22 G19 E20 G18 B20 C19 D19 F17 J18 J17 <16> FDI_FSYNC0 <16> FDI_FSYNC1 FDI_INT H20 <16> FDI_LSYNC0 <16> FDI_LSYNC1 J19 H17 1 <16> DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC 2 R7 24.9_0402_1% DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] EDP_COMP eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms eDP_HPD A18 A17 B16 C15 D15 C17 F16 C16 G15 C18 E16 D16 F15 eDP_COMPIO eDP_ICOMPO eDP_HPD# eDP_AUX eDP_AUX# eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] eDP B eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] PCI EXPRESS* - GRAPHICS <16> <16> <16> <16> B28 B26 A24 B23 PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI B27 B25 A25 B24 Intel(R) FDI DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 <16> <16> <16> <16> PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] J22 J21 H22 K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32 D 2 JCPU1A 1 PEG_COMP PCIE_CRX_GTX_N[0..15] PCIE_CRX_GTX_N15 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N0 <23> PEG Static Lane Reversal - CFG2 is for the 16x 1: Normal Operation; Lane # socket pin map definition CFG2 * PCIE_CRX_GTX_P[0..15] definition matches 0:Lane Reversed <23> J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32 PCIE_CRX_GTX_P15 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P0 M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 PCIE_CTX_GRX_C_N15 PCIE_CTX_GRX_C_N14 PCIE_CTX_GRX_C_N13 PCIE_CTX_GRX_C_N12 PCIE_CTX_GRX_C_N11 PCIE_CTX_GRX_C_N10 PCIE_CTX_GRX_C_N9 PCIE_CTX_GRX_C_N8 PCIE_CTX_GRX_C_N7 PCIE_CTX_GRX_C_N6 PCIE_CTX_GRX_C_N5 PCIE_CTX_GRX_C_N4 PCIE_CTX_GRX_C_N3 PCIE_CTX_GRX_C_N2 PCIE_CTX_GRX_C_N1 PCIE_CTX_GRX_C_N0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.22U_0402_10V6K PCIE_CTX_GRX_N15 0.22U_0402_10V6K PCIE_CTX_GRX_N14 0.22U_0402_10V6K PCIE_CTX_GRX_N13 0.22U_0402_10V6K PCIE_CTX_GRX_N12 0.22U_0402_10V6K PCIE_CTX_GRX_N11 0.22U_0402_10V6K PCIE_CTX_GRX_N10 0.22U_0402_10V6K PCIE_CTX_GRX_N9 0.22U_0402_10V6K PCIE_CTX_GRX_N8 0.22U_0402_10V6K PCIE_CTX_GRX_N7 0.22U_0402_10V6K PCIE_CTX_GRX_N6 0.22U_0402_10V6K PCIE_CTX_GRX_N5 0.22U_0402_10V6K PCIE_CTX_GRX_N4 0.22U_0402_10V6K PCIE_CTX_GRX_N3 0.22U_0402_10V6K PCIE_CTX_GRX_N2 0.22U_0402_10V6K PCIE_CTX_GRX_N1 0.22U_0402_10V6K PCIE_CTX_GRX_N0 M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25 PCIE_CTX_GRX_C_P15 PCIE_CTX_GRX_C_P14 PCIE_CTX_GRX_C_P13 PCIE_CTX_GRX_C_P12 PCIE_CTX_GRX_C_P11 PCIE_CTX_GRX_C_P10 PCIE_CTX_GRX_C_P9 PCIE_CTX_GRX_C_P8 PCIE_CTX_GRX_C_P7 PCIE_CTX_GRX_C_P6 PCIE_CTX_GRX_C_P5 PCIE_CTX_GRX_C_P4 PCIE_CTX_GRX_C_P3 PCIE_CTX_GRX_C_P2 PCIE_CTX_GRX_C_P1 PCIE_CTX_GRX_C_P0 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 N13P@1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.22U_0402_10V6K PCIE_CTX_GRX_P15 0.22U_0402_10V6K PCIE_CTX_GRX_P14 0.22U_0402_10V6K PCIE_CTX_GRX_P13 0.22U_0402_10V6K PCIE_CTX_GRX_P12 0.22U_0402_10V6K PCIE_CTX_GRX_P11 0.22U_0402_10V6K PCIE_CTX_GRX_P10 0.22U_0402_10V6K PCIE_CTX_GRX_P9 0.22U_0402_10V6K PCIE_CTX_GRX_P8 0.22U_0402_10V6K PCIE_CTX_GRX_P7 0.22U_0402_10V6K PCIE_CTX_GRX_P6 0.22U_0402_10V6K PCIE_CTX_GRX_P5 0.22U_0402_10V6K PCIE_CTX_GRX_P4 0.22U_0402_10V6K PCIE_CTX_GRX_P3 0.22U_0402_10V6K PCIE_CTX_GRX_P2 0.22U_0402_10V6K PCIE_CTX_GRX_P1 0.22U_0402_10V6K PCIE_CTX_GRX_P0 C PCIE_CTX_GRX_N[0..15] <23> PCIE_CTX_GRX_P[0..15] <23> B 12/07 update to SE124224K80 TYCO_2013620-2_IVY BRIDGE A A Compal Secret Data Security Classification Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title PROCESSOR(1/7) DMI,FDI,PEG THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.3 LA-7983P Date: 5 4 3 2 Thursday, January 05, 2012 Sheet 1 5 of 60 5 4 3 2 1 JCPU1B R10;R11 put on U4 side D D PROC_SELECT# SKTOCC# +V1.05S_VCCP R9 62_0402_5% AN33 2 <19,42> H_PECI R15 56_0402_5% 1 2 H_PROCHOT# <42,48> H_PROCHOT# AL32 H_PROCHOT#_R AN32 <19> H_THRMTRIP# CATERR# THERMAL 1 AL33 H_CATERR# T48 PECI PROCHOT# THERMTRIP# BCLK BCLK# CLOCKS AN34 CLK_CPU_DMI_R 0_0402_5% CLK_CPU_DMII#_R 0_0402_5% 1 1 2 2 CLK_CPU_DMI <15> CLK_CPU_DMI# <15> R11 DPLL_REF_CLK DPLL_REF_CLK# SM_DRAMRST# DDR3 MISC C26 <19> H_SNB_IVB# MISC R10 A28 A27 SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] 2 2 A16 A15 R12 R13 1 1K_0402_5% 1 1K_0402_5% R8 H_DRAMRST# AK1 A5 A4 SM_RCOMP0 2 R16 SM_RCOMP1 2 R17 SM_RCOMP2 2 R18 +V1.05S_VCCP H_DRAMRST# <7> 1 140_0402_1% 1 25.5_0402_1% 1 200_0402_1% DDR3 Compensation Signals +V1.05S_VCCP PRDY# PREQ# <16> H_PM_SYNC 2 H_PM_SYNC_R AM34 PWR MANAGEMENT R22 1 PM_SYNC 0_0402_5% 0_0402_5% 0_0402_5%1 R26 2 AP33 H_CPUPWRGD_R 2 <19> H_CPUPWRGD V8 SM_DRAMPWROK 1 100P_0402_50V8J 2 EMI Reserve R29 1 2 PM_DRAM_PWRGD_R 130_0402_5% R27 10K_0402_5% 1 @ C549 UNCOREPWRGOOD AR33 BUF_CPU_RST# RESET# TDI TDO DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] XDP_PRDY# XDP_PREQ# AR26 AR27 AP30 XDP_TCK XDP_TMS XDP_TRST# AR28 AP26 T97 T98 XDP_TDI XDP_TDO AL35 XDP_DBRESET# AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 R20 R21 R23 2 2 2 XDP_TCK R24 XDP_TRST# R25 2 2 XDP_TMS XDP_TDI XDP_TDO 2 R28 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7 1 1K_0402_5% @ 1 51_0402_5% 1 51_0402_5% 1 51_0402_5% PU/PD for JTAG signals C 1 51_0402_5% 1 51_0402_5% +3VS T49 T90 T91 T92 T93 T94 T95 T96 TYCO_2013620-2_IVY BRIDGE +3VALW Buffered reset to CPU 1 C33 0.1U_0402_16V4Z TCK TMS TRST# JTAG & BPM C AP29 AP27 +1.5V_CPU_VDDQ 2 +3VS B 1 B +V1.05S_VCCP O 4 1 PM_SYS_PWRGD_BUF S 2 G 1 BUF_CPU_RST# U2 BUFO_CPU_RST# 4 SN74LVC1G07DCKR_SC70-5 NC Y A 1 2 3V PCH_PLTRST# PCH_PLTRST# <18> 3 1 2 D 3 @ R33 39_0402_5% R35 @ 0_0402_5% Q1 @ 2N7002H_SOT23-3 2 <10> RUN_ON_CPU1.5VS3# R34 43_0402_1% 1 2 2 74AHC1G09GW_TSSOP5 1 2 R32 75_0402_5% 1 A C34 0.1U_0402_16V4Z P P B 3 2 G +3VS <16> PM_DRAM_PWRGD 1 2 5 U1 1 R161 2 10K_0402_5% 5 R30 200_0402_5% G 1 R880@ 2 0_0402_5% <16> SYS_PWROK A A Compal Secret Data Security Classification Issued Date 2011/10/27 2012/10/27 Deciphered Date Title Compal Electronics, Inc. PROCESSOR(2/7) PM,XDP,CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.3 LA-7983P Date: 5 4 3 2 Thursday, January 05, 2012 Sheet 1 6 of 60 5 4 3 2 JCPU1C 1 JCPU1D <13> DDR_B_D[0..63] D C AE10 AF10 V6 <12> DDR_A_BS0 <12> DDR_A_BS1 <12> DDR_A_BS2 B AE8 AD9 AF9 <12> DDR_A_CAS# <12> DDR_A_RAS# <12> DDR_A_WE# SA_CLK[0] SA_CLK#[0] SA_CKE[0] SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_CLK[1] SA_CLK#[1] SA_CKE[1] RSVD_TP[1] RSVD_TP[2] RSVD_TP[3] RSVD_TP[4] RSVD_TP[5] RSVD_TP[6] SA_CS#[0] SA_CS#[1] RSVD_TP[7] RSVD_TP[8] DDR SYSTEM MEMORY A C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 SA_ODT[0] SA_ODT[1] RSVD_TP[9] RSVD_TP[10] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] SA_BS[0] SA_BS[1] SA_BS[2] SA_CAS# SA_RAS# SA_WE# AB6 AA6 V9 M_CLK_DDR0 <12> M_CLK_DDR#0 <12> DDR_CKE0_DIMMA <12> AA5 AB5 V10 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 M_CLK_DDR1 <12> M_CLK_DDR#1 <12> DDR_CKE1_DIMMA <12> AB4 AA4 W9 AB3 AA3 W10 AK3 AL3 AG1 AH1 DDR_CS0_DIMMA# <12> DDR_CS1_DIMMA# <12> AH3 AG3 AG2 AH2 M_ODT0 <12> M_ODT1 <12> C4 G6 J3 M6 AL6 AM8 AR12 AM15 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_A_DQS#[0..7] D4 F6 K3 N6 AL5 AM9 AR11 AM14 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS[0..7] AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 <12> <12> DDR_A_MA[0..15] <12> C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 AA9 AA7 R6 <13> DDR_B_BS0 <13> DDR_B_BS1 <13> DDR_B_BS2 AA10 AB8 AB9 <13> DDR_B_CAS# <13> DDR_B_RAS# <13> DDR_B_WE# TYCO_2013620-2_IVY BRIDGE SB_CLK[0] SB_CLK#[0] SB_CKE[0] SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] SB_CLK[1] SB_CLK#[1] SB_CKE[1] RSVD_TP[11] RSVD_TP[12] RSVD_TP[13] RSVD_TP[14] RSVD_TP[15] RSVD_TP[16] SB_CS#[0] SB_CS#[1] RSVD_TP[17] RSVD_TP[18] DDR SYSTEM MEMORY B <12> DDR_A_D[0..63] SB_ODT[0] SB_ODT[1] RSVD_TP[19] RSVD_TP[20] SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] SB_BS[0] SB_BS[1] SB_BS[2] SB_CAS# SB_RAS# SB_WE# AE2 AD2 R9 M_CLK_DDR2 <13> M_CLK_DDR#2 <13> DDR_CKE2_DIMMB <13> AE1 AD1 R10 M_CLK_DDR3 <13> M_CLK_DDR#3 <13> DDR_CKE3_DIMMB <13> D AB2 AA2 T9 AA1 AB1 T10 AD3 AE3 AD6 AE6 DDR_CS2_DIMMB# <13> DDR_CS3_DIMMB# <13> AE4 AD4 AD5 AE5 M_ODT2 <13> M_ODT3 <13> D7 F3 K6 N3 AN5 AP9 AK12 AP15 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_DQS#[0..7] C7 G3 J6 M3 AN6 AP8 AK11 AP14 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS[0..7] AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 <13> C <13> DDR_B_MA[0..15] <13> B TYCO_2013620-2_IVY BRIDGE +1.5V D S 3 H_DRAMRST# 1 2 <6> H_DRAMRST# 1 R40 DDR3_DRAMRST#_R R38 1K_0402_5% 2 1 2 DRAMRST_CNTRL DRAMRST_CNTRL <10> 0_0402_5% DDR3_DRAMRST# <12,13> Q2 LBSS138LT1G_SOT-23-3 1 2 G R39 4.99K_0402_1% 1 <15> DRAMRST_CNTRL_PCH R37 1K_0402_5% 2 @ R36 0_0402_5% 1 2 A A DRAMRST_CNTRL 1 2 C35 .047U_0402_16V7K Eiffel used 0.01u Module design used 0.047u Compal Secret Data Security Classification Issued Date 2011/10/27 2012/10/27 Deciphered Date Title Compal Electronics, Inc. PROCESSOR(3/7) DDRIII THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.3 LA-7983P Date: 5 4 3 2 Thursday, January 05, 2012 Sheet 1 7 of 60 5 4 3 2 1 CFG Straps for Processor 1 CFG2 2 R41 1K_0402_1% D Interl request AH26 short GND check on EVT phase 2 R252 49.9_0402_1% R60 RSVD32 RSVD33 RSVD34 RSVD35 2 100_0402_1% R88 1 @ 2 100_0402_1% VCC_AXG_VAL_SENSE VSS_AXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE AJ31 AH31 AJ33 AH33 AJ26 Need PWR add new circuit on 1.05V(refer CRB) VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 2 2 VSS_VAL_SENSE Check 1 R257 49.9_0402_1% 1 R255 49.9_0402_1% INTEL 12/28 recommand to add RC120, RC121, RC122, RC123 Please place as close as JCPU1 B J20 B18 J15 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 0_0402_5% * L7 AG7 AE7 AK2 definition matches 0:Lane Reversed CFG4 W8 @ R42 1K_0402_1% AT26 AM33 AJ27 T8 J16 H16 G16 * CFG4 C 1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port RSVD5 VSS_AXG_VAL_SENSE 1: Normal Operation; Lane # socket pin map definition CFG2 RSVD24 RSVD25 RSVD27 RSVD_NCTF1 RSVD_NCTF2 RSVD_NCTF3 RSVD_NCTF4 RSVD_NCTF5 AR35 AT34 AT33 AP35 AR34 CFG6 CFG5 1 @ T13 Display Port Presence Strap RSVD37 RSVD38 RSVD39 RSVD40 RESERVED 1 R82 1 2 1 RSVD28 RSVD29 RSVD30 RSVD31 1 R253 49.9_0402_1% C PAD 1 1 2 +VCC_CORE AH27 AH26 @ R43 1K_0402_1% RSVD_NCTF6 RSVD_NCTF7 RSVD_NCTF8 RSVD_NCTF9 RSVD_NCTF10 RSVD51 RSVD52 BCLK_ITP BCLK_ITP# RSVD_NCTF11 RSVD_NCTF12 RSVD_NCTF13 @ R44 1K_0402_1% AJ32 AK32 PCIE Port Bifurcation Straps 11: (Default) x16 - Device 1 functions 1 and 2 disabled AN35 AM35 CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2 B disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled AT2 AT1 AR1 B1 CFG7 1 KEY B34 A33 A34 B35 C35 2 +VCC_GFXCORE_AXG VCC_DIE_SENSE VSS_DIE_SENSE 2 CFG4 CFG5 CFG6 CFG7 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] CFG CFG2 AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 PEG Static Lane Reversal - CFG2 is for the 16x 2 JCPU1E D @R45 @ R45 1K_0402_1% 2 TYCO_2013620-2_IVY BRIDGE PEG DEFER TRAINING CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training A Compal Secret Data Security Classification Issued Date 2011/10/27 2012/10/27 Deciphered Date Title A Compal Electronics, Inc. PROCESSOR(4/7) RSVD,CFG THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.3 LA-7983P Date: 5 4 3 2 Thursday, January 05, 2012 Sheet 1 8 of 60 5 4 JCPU1F 3 POWER 2 1 +V1.05S_VCCP +VCC_CORE 8.5A A VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 D E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 C J23 +V1.05S_VCCP 1 1 C99 .1U_0402_16V7K 2 2 R46 75_0402_5% VIDALERT# VIDSCLK VIDSOUT AJ29 AJ30 AJ28 H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT 0_0402_5% 0_0402_5% R50 1 R47 1 1 2 43_0402_1% 2 R48 2 R49 2 1 130_0402_5% VR_SVID_CLK series-resistors close to VR VR_SVID_ALRT# <55> VR_SVID_CLK <55> VR_SVID_DAT <55> +V1.05S_VCCP 0.1uF on power side B VCC_SENCE 100ohm +-1% pull-up to VCC near processor 1 +VCC_CORE Trace Impedance =27-33 ohm Trace Length Matc < 25 mils VCC_SENSE VSS_SENSE 2 R52 2 R53 2 1 1 AJ35 VCCSENSE_R AJ34 VSSSENSE_R R51 100_0402_1% 0_0402_5% 0_0402_5% VCCSENSE <55> VSSSENSE <55> VCCIO_SENSE VSS_SENSE_VCCIO B10 A10 VSSIO_SENSE_L 1 10/19 Update to @ for PWR modification. 1 R66 @2 100_0402_1% VCCIO_SENSE <52,53> 1 R74 2VSSIO_SENSE 10_0402_1% @ R54 100_0402_1% 2 B VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 VCCIO40 SVID C VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 SENSE LINES D CORE SUPPLY AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 PEG AND DDR EDS v1.5 QC=94A DC=53A R74 & R79 put together +V1.05S_VCCP R79 2 1 10_0402_1% VSSIO_SENSE_L <53> A 10/19 Add off page to PWR side. VSS_SENCE 100ohm +-1% pull-down to GND near processor Compal Secret Data Security Classification TYCO_2013620-2_IVY BRIDGE Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title PROCESSOR(5/7) PWR,BYPASS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.3 LA-7983P Date: 5 4 3 2 Thursday, January 05, 2012 Sheet 1 9 of 60 4 3 1 +1.5V_CPU_VDDQ D 2 1 S 2 G Q7 @ 2N7002_SOT23 1 Q4 2N7002_SOT23 2 S 2 G D 3 2 R59 RUN_ON_CPU1.5VS3 1 R885 2 15K_0402_1% R57 330K_0402_5% @ 3 1 D S 2 G R353 1K_0402_1% @ 2 DRAMRST_CNTRL S 1 RUN_ON_CPU1.5VS3# 11/03 update to 0.047u <7> R64 1K_0402_1% @ D M3 Circuit (Processor Generated SO-DIMM VREF_DQ) 1 2 DRAMRST_CNTRL +V_DDR_REFA_R +V_DDR_REFB_R +VCC_GFXCORE_AXG C97 0.047U_0402_25V7K R616 10_0402_1% 2 SUSP# 2 R58 1 0_0402_5% @ 2 G Q9 LBSS138LT1G_SOT-23-3 2 <25,42,46,51,52,53,54> 1 0_0402_5% @ 1 <42,53> CPU1.5V_S3_GATE D 3 RUN_ON_CPU1.5VS3# S 2 0_0402_5%~D 2 0_0402_5%~D R671@ D Q3 2N7002_SOT23 @ AP4800 Id=9.6A 2 @ R667 100K_0402_5% R670@ 1 1 4 R56 82K_0402_5% C92 @ .1U_0402_16V7K 1 1 1 D U3 DMN3030LSS-13_SOP8L-8 8 1 7 2 6 3 5 2 3 +VSB +3VALW R55 220_0402_5% @ 12 11/03 update to 82K +VREF_DQ_DIMMA +VREF_DQ_DIMMB 3 1 2 0_0402_5% 1 1 PAD-OPEN 4x4m <46,53,54> SUSP Q6 LBSS138LT1G_SOT-23-3 2 DRAMRST_CNTRL G 1 @ J1 1 R668 1 +1.5V 2 2 5 1 2 2 1 1 1 +V_SM_VREF C 1 1 @2 1 R61 0_0402_5% 2 R62 @ 1K_0402_1% 2 2 SENSE LINES D C98 .1U_0402_16V7K +V_DDR_REFA_R +V_DDR_REFB_R R78 1K_0402_1% 2 R63 @ 1K_0402_1% 2 B4 D1 2 VREF S SA_DIMM_VREFDQ SB_DIMM_VREFDQ +1.5V_CPU_VDDQ +1.5V 1 1 2 1 2 1 2 1 2 2 1 2 + C123 330U_2.5V_M C96 .1U_0402_16V7K 1 2 +VCCSA 1 2 1 2 1 2 1 2 @ B 1 + C128 @ 330U_D2_2.5VY_R9M 2 H23 +VCCSA_SENSE <52> +3VS MISC VCCSA_VID[0] VCCSA_VID[1] VCCIO_SEL H_VCCSA_VID0 H_VCCSA_VID1 A19 2 @ 1 2 R68 0_0402_5% <52> <52> R75 10K_0402_5% H_VCCP_SEL 1 R77 TYCO_2013620-2_IVY BRIDGE +3VALW 2 M27 +VCCSA M26 L26 J26 J25 J24 H26 H25 C22 C24 C129 @ .1U_0402_16V7K 1 2 2 2 R76 @ 10K_0402_5% 1 SA RAIL VCCSA_SENSE 1 C95 .1U_0402_16V7K 1 2 6A VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 +1.5V_CPU_VDDQ C396 @ .1U_0402_16V7K 1 2 1 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 C122 10U_0603_6.3V6M DDR3 -1.5V RAILS 5A AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1 C121 10U_0603_6.3V6M 2 1 1 C127 10U_0603_6.3V6M 2 1 VCCPLL1 VCCPLL2 VCCPLL3 +V_SM_VREF_CNT C120 10U_0603_6.3V6M 2 1 B6 A6 A2 AL1 C126 10U_0603_6.3V6M 1 C132 1U_0402_6.3V6K 2 @ C131 1U_0402_6.3V6K 1 C130 10U_0603_6.3V6M 2 @ C345 22U_0805_6.3V6M 1 C154 22U_0805_6.3V6M @ +1.8VS_VCCPLL SM_VREF PMV45EN_SOT23-3 Q5 @ 3 R67 1K_0402_1% +V_SM_VREF should have 20 mil trace width C119 10U_0603_6.3V6M 1.2A 0_0805_5% 2 +1.5V_CPU_VDDQ VSS_AXG_SENSE <55> R626 10_0402_1% C125 10U_0603_6.3V6M R69 1 AK35 AK34 C124 10U_0603_6.3V6M +1.8VS VAXG_SENSE VSSAXG_SENSE C118 10U_0603_6.3V6M B Q5-orignal part AP2302GN-HF_SOT23-3 SB523020210 +1.5V G C VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 RUN_ON_CPU1.5VS3 R89 @ 100_0402_1% C117 10U_0603_6.3V6M AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 SV-QC: 50A SV-DC(GT2): 33A VCC_AXG_SENSE <55> POWER GRAPHICS <6> +VCC_GFXCORE_AXG JCPU1G 1.8V RAIL RUN_ON_CPU1.5VS3# Check VCCP_PWRCTRL <52> 0_0402_5% IVY Bridge drives VCCIO_SEL low VCCP_PWRCTRL:0 Sandy Bridge is NC for A19 VCCP_PWRCTRL:1 A A Compal Secret Data Security Classification Issued Date 2011/10/27 2012/10/27 Deciphered Date Title PROCESSOR(6/7) PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.3 LA-7983P Date: 5 4 3 2 Thursday, January 05, 2012 Sheet 1 10 of 60 5 4 3 2 JCPU1H AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25 D C B 1 JCPU1I VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3 D C B A A TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE Compal Secret Data Security Classification Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title Compal Electronics, Inc. PROCESSOR(7/7) VSS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.3 LA-7983P Date: 5 4 3 2 Thursday, January 05, 2012 Sheet 1 11 of 60 5 4 3 2 1 +1.5V DDR_A_D2 DDR_A_D3 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 DDR_CKE0_DIMMA <7> DDR_CKE0_DIMMA DDR_A_BS2 <7> DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 <7> M_CLK_DDR0 <7> M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#0 <7> DDR_A_BS0 DDR_A_MA10 DDR_A_BS0 <7> DDR_A_WE# <7> DDR_A_CAS# DDR_A_WE# DDR_A_CAS# <7> DDR_CS1_DIMMA# DDR_A_MA13 DDR_CS1_DIMMA# 1 DDR_CKE1_DIMMA C <7> DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_BS1 DDR_A_RAS# OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00) M_CLK_DDR1 <7> M_CLK_DDR#1 <7> DDR_A_BS1 <7> DDR_A_RAS# <7> DDR_CS0_DIMMA# M_ODT0 M_ODT1 DDR_CS0_DIMMA# M_ODT0 <7> R72 1K_0402_1% +VREF_CA 1 DDR_A_DM4 2 DDR_A_D38 DDR_A_D39 (10uF_0603_6.3V)*8 (0.1uF_402_10V)*4 <7> M_ODT1 <7> DDR_A_D36 DDR_A_D37 Layout Note: Place near DIMM +1.5V 1 2 +1.5V 1 R73 1K_0402_1% @ DDR_A_D44 DDR_A_D45 2 1 @ 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1 EVT Check 2 1 + C149 @ 220U_6.3V_M B 2 DDR_A_DQS#5 DDR_A_DQS5 VDDQ(1.5V) = DDR_A_D46 DDR_A_D47 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs) DDR_A_D52 DDR_A_D53 6*0603 10uf (PER CONNECTOR) DDR_A_DM6 Layout Note: Place near DIMM VTT(0.75V) = DDR_A_D54 DDR_A_D55 3*0805 10uf 7/28 Update connect GND directly 4*0402 1uf +0.75VS VREF = DDR_A_D60 DDR_A_D61 1*0402 0.1uf DDR_A_DQS#7 DDR_A_DQS7 1*0402 0.1uf DDR_A_D62 DDR_A_D63 SMB_DATA_S3 SMB_CLK_S3 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 del 1*0402 2.2uf VDDSPD (3.3V)= 1*0402 2.2uf 1 2 @ 1 2 1 2 1 2 @ Layout Note: Place near DIMM SMB_DATA_S3 <13,15,36> SMB_CLK_S3 <13,15,36> +0.75VS A 1/76BA1/86W 206 FOX_AS0A626-U4SN-7F ME@ Compal Secret Data Security Classification Issued Date 2011/10/27 Deciphered Date 2012/10/27 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 1 C148 .1U_0402_16V7K 2 DDR_CKE1_DIMMA C147 .1U_0402_16V7K G2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 C146 .1U_0402_16V7K G1 DDR_A_D30 DDR_A_D31 C153 1U_0402_6.3V6K 2 205 DDR_A_DQS#3 DDR_A_DQS3 C152 1U_0402_6.3V6K 2 1 R83 10K_0402_5% 1 C156 .1U_0402_16V7K +3VS C155 2.2U_0402_6.3V6M A DDR_A_D28 DDR_A_D29 C151 1U_0402_6.3V6K DDR_A_D58 DDR_A_D59 1 R81 2 10K_0402_5% DDR_A_D22 DDR_A_D23 C150 1U_0402_6.3V6K DDR_A_DM7 DDR_A_DM2 C145 .1U_0402_16V7K DDR_A_D56 DDR_A_D57 DDR_A_D20 DDR_A_D21 C144 10U_0603_6.3V6M DDR_A_D50 DDR_A_D51 <7,13> C143 10U_0603_6.3V6M DDR_A_DQS#6 DDR_A_DQS6 DDR3_DRAMRST# DDR_A_D14 DDR_A_D15 C142 10U_0603_6.3V6M DDR_A_D48 DDR_A_D49 DDR_A_DM1 DDR3_DRAMRST# C141 10U_0603_6.3V6M DDR_A_D42 DDR_A_D43 DDR_A_D12 DDR_A_D13 C140 10U_0603_6.3V6M DDR_A_DM5 D DDR_A_D6 DDR_A_D7 C139 10U_0603_6.3V6M DDR_A_D40 DDR_A_D41 <7> DDR_A_MA[0..15] DDR_A_DQS#0 DDR_A_DQS0 C138 10U_0603_6.3V6M DDR_A_D34 DDR_A_D35 DDR_A_D4 DDR_A_D5 C137 10U_0603_6.3V6M B CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 <7> DDR_A_DQS#[0..7] 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 C136 2.2U_0402_6.3V6M DDR_A_DQS#4 DDR_A_DQS4 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 C135 .1U_0402_16V7K DDR_A_D32 DDR_A_D33 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 1 DDR_A_DM0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 2 2 1 2 2 C133 .1U_0402_16V7K 2 1 DDR_A_D0 DDR_A_D1 DDR_A_D8 DDR_A_D9 C <7> DDR_A_DQS[0..7] JDIMM1 C134 2.2U_0402_6.3V6M R71 1K_0402_1% <7> DDR_A_D[0..63] DDR3 SO-DIMM A +VREF_DQ_DIMMA 1 D +1.5V 4BA2/6W 1 1 +1.5V R70 1K_0402_1% 2 +VREF_DQ_DIMMA 4 3 2 Title Compal Electronics, Inc. DDRIII-SODIMM SLOT1 Size Document Number Custom Date: Rev 0.3 LA-7983P Sheet Thursday, January 05, 2012 1 12 of 60 5 4 2 DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11 For Arranale only +VREF_DQ_DIMMB supply from a external 1.5V voltage divide circuit. DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25 DDR_B_DM3 DDR_B_D26 DDR_B_D27 <7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB <7> DDR_B_BS2 DDR_B_BS2 C DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 <7> M_CLK_DDR2 <7> M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#2 <7> DDR_B_BS0 DDR_B_MA10 DDR_B_BS0 <7> DDR_B_WE# <7> DDR_B_CAS# DDR_B_WE# DDR_B_CAS# <7> DDR_CS3_DIMMB# DDR_B_MA13 DDR_CS3_DIMMB# <7> DDR_B_DQS[0..7] DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB# M_ODT2 M_ODT3 M_CLK_DDR3 <7> M_CLK_DDR#3 <7> DDR_B_BS1 <7> DDR_B_RAS# <7> DDR_CS2_DIMMB# M_ODT2 <7> +1.5V <7> M_ODT3 <7> +VREF_CB DDR_B_D36 DDR_B_D37 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 1/76BA1/86W 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 1 2 B 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs) 6*0603 10uf (PER CONNECTOR) Layout Note: Place near DIMM VTT(0.75V) = 3*0805 10uf 1*0402 0.1uf 4*0402 1uf +0.75VS 1*0402 2.2uf DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 VDDSPD (3.3V)= 1*0402 0.1uf 1*0402 2.2uf SMB_DATA_S3 <12,15,36> SMB_CLK_S3 <12,15,36> +0.75VS 1 2 @ 1 2 1 2 1 @ 2 A Layout Note: Place near DIMM FOX_AS0A626-U8SN-7F ME@ Compal Secret Data Security Classification Issued Date 2011/10/27 Deciphered Date 2012/10/27 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 1 VDDQ(1.5V) = DDR_B_D62 DDR_B_D63 SMB_DATA_S3 SMB_CLK_S3 2 @ C172 .1U_0402_16V7K DDR_B_D44 DDR_B_D45 1 C171 .1U_0402_16V7K @ C170 .1U_0402_16V7K R87 1K_0402_1% C169 .1U_0402_16V7K 2 +1.5V C168 2 1 C167 DDR_B_D38 DDR_B_D39 (0.1uF_402_10V)*4 10U_0603_6.3V6M DDR_B_DM4 (10uF_0603_6.3V)*8 10U_0603_6.3V6M 1 Layout Note: Place near DIMM R86 1K_0402_1% C166 206 DDR_B_MA11 DDR_B_MA7 10U_0603_6.3V6M G2 C DDR_B_MA15 DDR_B_MA14 C165 G1 DDR_CKE3_DIMMB C176 1U_0402_6.3V6K 2 205 DDR_B_D30 DDR_B_D31 C175 1U_0402_6.3V6K 1 DDR_B_DQS#3 DDR_B_DQS3 C174 1U_0402_6.3V6K 2 C177 2.2U_0402_6.3V6M 1 C178 .1U_0402_16V7K +3VS A DDR_B_D28 DDR_B_D29 C173 1U_0402_6.3V6K DDR_B_D58 DDR_B_D59 1 R95 2 10K_0402_5% 1 2 R97 10K_0402_5% DDR_B_D22 DDR_B_D23 10U_0603_6.3V6M DDR_B_DM7 <7> DDR_B_DM2 C164 DDR_B_D56 DDR_B_D57 DDR_CKE3_DIMMB DDR_B_D20 DDR_B_D21 10U_0603_6.3V6M DDR_B_D50 DDR_B_D51 <7,12> 10U_0603_6.3V6M DDR_B_DQS#6 DDR_B_DQS6 DDR3_DRAMRST# DDR_B_D14 DDR_B_D15 C163 DDR_B_D48 DDR_B_D49 DDR_B_DM1 DDR3_DRAMRST# 10U_0603_6.3V6M DDR_B_D42 DDR_B_D43 D DDR_B_D12 DDR_B_D13 C162 DDR_B_DM5 DDR_B_D6 DDR_B_D7 C161 DDR_B_D40 DDR_B_D41 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 <7> DDR_B_MA[0..15] DDR_B_DQS#0 DDR_B_DQS0 10U_0603_6.3V6M DDR_B_D34 DDR_B_D35 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 <7> DDR_B_DQS#[0..7] DDR_B_D4 DDR_B_D5 C160 2.2U_0402_6.3V6M DDR_B_DQS#4 DDR_B_DQS4 B CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 C159 .1U_0402_16V7K DDR_B_D32 DDR_B_D33 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 1 1 DDR_B_DM0 1 C157 2 C158 2 1 .1U_0402_16V7K 2.2U_0402_6.3V6M R85 1K_0402_1% VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 2 2 DDR_B_D0 DDR_B_D1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 1 1 1 +1.5V JDIMM2 +VREF_DQ_DIMMB 2 <7> DDR_B_D[0..63] +1.5V R84 1K_0402_1% D 3 4BA2/6W 2 +1.5V +VREF_DQ_DIMMB 4 3 2 Title Compal Electronics, Inc. DDRIII-SODIMM SLOT2 Size Document Number Rev 0.3 LA-7983P Date: Sheet Thursday, January 05, 2012 1 13 of 60 5 4 3 2 1 PCH_RTCX1 W=20mils W=20mils +RTCBATT +RTCVCC 1 2 10M_0402_5% R98 PCH_RTCX2 Y1 1 R99 1K_0402_5% 2 1 32.768KHZ_12.5PF_CM31532768DZFT CRYSTAL@ R4956 1 2 0_0402_5% R4957 1 2 0_0402_5% GCLK@ CMOS +RTCVCC 1 INTVRMEN Integrated VRM enable 烉Integrated * HL烉 VRM disable 2 1 C182 1U_0402_6.3V6K (INTVRMEN should always be pull high.) 2 CLRP3 SHORT PADS C183 1U_0402_6.3V6K 1 2 R103 20K_0402_5% 1 2 R100 20K_0402_5% 1 PCH_INTVRMEN 2 SM_INTRUDER# 2 330K_0402_5% 1 2 1M_0402_5% R102 1 2 R101 1 CLRP2 SHORT PADS +RTCVCC +3VS R105 1 * C 2 1K_0402_5% @ HDA_SPKR HIGH= Enable ( No Reboot ) LOW= Disable (Default) <41> HDA_SPKR +3V_PCH * @ 1 1K_0402_5% A20 PCH_RTCX2 C20 PCH_RTCRST# D20 PCH_SRTCRST# G22 SM_INTRUDER# K22 PCH_INTVRMEN C17 HDA_BIT_CLK N34 HDA_SYNC L34 HDA_SPKR T10 HDA_RST# K34 HDA_SDIN0 <41> HDA_SDIN0 R106 2 PCH_RTCX1_R C34 Low = Disabled (Default) High = Enabled [Flash Descriptor Security Overide] R108 * A34 2 1 1K_0402_5% R107 1 HDA_SYNC This signal has a weak internal pull-down On Die PLL VR is supplied by 1.5V when smapled high 1.8V when sampled low Needs to be pulled High for Chief River platfrom R109 0_0402_5% 1 2 ME_FLASH <42> ME_FLASH +3V_PCH E34 G34 HDA_SDOUT @ A36 2 1K_0402_1% PCH_GPIO33 C36 2 R264 @1 PCH_GPIO13 N32 10K_0402_5% +3V_PCH HDA_SDOUT 1 PCH_JTAG_TCK J3 51_0402_5% PCH_JTAG_TMS H7 PCH_JTAG_TDI K5 PCH_JTAG_TDO H1 2 R110 +5VS <41> HDA_RST_AUDIO# 2 2 HDA_RST# SPI_SB_CS0# R878 1M_0402_5% HDA_SDOUT +3V_PCH R121 @ 200_0402_5% R122 @ 200_0402_5% Y14 T1 0_0402_5% SPI_SI V4 Del Q10 check with codec VDDIO using 3VALW RTCX1 RTCX2 FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 RTCRST# FWH4 / LFRAME# SRTCRST# INTRUDER# INTVRMEN LDRQ0# LDRQ1# / GPIO23 SERIRQ HDA_BCLK HDA_SYNC SPKR HDA_RST# HDA_SDIN0 HDA_SDIN3 SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA2RXN SATA2RXP SATA2TXN SATA2TXP HDA_SDIN1 HDA_SDIN2 SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA3RXN SATA3RXP SATA3TXN SATA3TXP HDA_SDO HDA_DOCK_EN# / GPIO33 SATA4RXN SATA4RXP SATA4TXN SATA4TXP HDA_DOCK_RST# / GPIO13 JTAG_TCK SATA5RXN SATA5RXP SATA5TXN SATA5TXP JTAG_TMS SATAICOMPO JTAG_TDI JTAG_TDO SATAICOMPI U3 SPI_CLK SATA3RBIAS C38 A38 B37 C37 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 D36 LPC_FRAME# SPI_CS1# SPI_MOSI LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 SATALED# SPI_MISO SATA1GP / GPIO19 SERIRQ AM3 AM1 AP7 AP5 SATA_ITX_C_DRX_N0 0.01U_0402_16V7K SATA_ITX_C_DRX_P0 0.01U_0402_16V7K SERIRQ AM10 AM8 AP11 AP10 AD7 AD5 AH5 AH4 R125 @ 100_0402_1% 2 2 1 C184 1 C185 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 SATA_ITX_DRX_N0 SATA_ITX_DRX_P0 SATA_DTX_C_IRX_N0 <40> SATA_DTX_C_IRX_P0 <40> SATA_ITX_DRX_N0 <40> SATA_ITX_DRX_P0 <40> HDD CAP on Conn, side SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 SATA_ITX_C_DRX_N2 SATA_ITX_C_DRX_P2 SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 SATA_ITX_C_DRX_N2 SATA_ITX_C_DRX_P2 C <40> <40> <40> <40> ODD AB8 AB10 AF3 AF1 Y7 Y5 AD3 AD1 Y3 Y1 AB3 AB1 Y11 Y10 SATA_COMP R111 37.4_0402_1% +1.05VS_VCC_SATA 1 2 SATA3_COMP R113 49.9_0402_1% 1 2 AB12 AB13 AH1 P3 V14 P1 PCH_GPIO21 BBS_BIT0_R +1.05VS_SATA3 8MB SPI ROM FOR ME & Non-share ROM. 1 2 R115 750_0402_1% RBIAS_SATA3 +3VS B HDD_LED# <43> 2 R117 1 10K_0402_5% 2 R119 1 10K_0402_5% 2 R187 1 10K_0402_5% +3VS SPI_SB_CS1# SPI_SO_R +3VS R291 0_0402_5% 1 2 1 2 U6 1 2 3 4 CS1# SPI_SO1 SPI_WP#1 R188 33_0402_5% +3VS CS# SO WP# GND VCC HOLD# SCLK SI 8 7 6 5 SPI_HOLD#1 SPI_CLK1 SPI_SI1 1 1 0_0402_5% R199 2 SPI_CLK_PCH_R 2 SPI_SI R196 33_0402_5% 16M W25Q16CVSSIG SOIC 8P +3VS 1 2 PCH_JTAG_TDI R128 @ 100_0402_1% R124 33_0402_5% @ R124;c190 close to U4.T3 pin 11/28 update to @ for power saving. 2 SPI_WP#1 3.3K_0402_5% R221 1 2 SPI_HOLD#1 3.3K_0402_5% 2 SPI_WP# 3.3K_0402_5% R129 1 2 DPDG1.1 R266 1 R127 1 2 @ R126 100_0402_1% 2 2 <42> R123 @ 200_0402_5% 1 2 1 2 1 PCH_JTAG_TMS 1 10K_0402_5% V5 SPI_CLK_PCH_R PCH_JTAG_TDO EC and Mini card debug port LPC_FRAME# <36,42> 2 R104 HDD_LED# SATA0GP / GPIO21 <36,42> <36,42> <36,42> <36,42> +3VS E36 K36 SPI_CS0# PANTHER-POINT_FCBGA989 1 1 1 +3V_PCH T3 SPI_SB_CS1# SPI_SO_R +3V_PCH GCLK_32K <36> SATA3COMPI R175 @ 1 2 1 <41> HDA_SDOUT_AUDIO Q10 LBSS138LT1G_SOT-23-3 1 HDA_SYNC SPI_CLK_PCH_R D B 3 HDA_SYNC_R S <41> HDA_SYNC_AUDIO GCLK_32K U4A SATA3RCOMPO HDA_BIT_CLK G R112 33_0402_5% 1 2 R114 33_0402_5% 1 2 R116 33_0402_5% 1 2 R118 33_0402_5% 1 2 <41> HDA_BITCLK_AUDIO D PCH_RTCX1 LPC D SATA 6G 2 2 SATA 2 C181 18P_0402_50V8J RTC C179 1U_0402_6.3V6K 1 IHDA CLRP1 SHORT PADS C180 15P_0402_50V8J SPI 1 JTAG 1 2 2 1 2 SPI_HOLD# 3.3K_0402_5% C190 22P_0402_50V8J @ U6 Rersver 4M+2M Solution +3VS C191 1 2 SPI_SB_CS0# SPI_SO_R R130 0_0402_5% 1 2 1 2 0.1U_0402_16V4Z U5 CS# SPI_SO_L SPI_WP# 33_0402_5% R131 1 2 3 4 CS# SO WP# GND VCC HOLD# SCLK SI 8 7 6 5 SPI_HOLD# SPI_CLK_PCH 1 1 SPI_SI_R 32M W25Q32BVSSIG SOIC 8P 0_0402_5% R132 2 SPI_CLK_PCH_R 2 SPI_SI R133 33_0402_5% A A Compal Secret Data Security Classification Issued Date 2011/10/27 2012/10/27 Deciphered Date Title Compal Electronics, Inc. PCH (1/9) SATA,HDA,SPI, LPC, XDP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.3 LA-7983P Date: 5 4 3 2 Sheet Thursday, January 05, 2012 1 14 of 60 4 3 2 1 U4B <45> PCIE_PRX_DTX_N4 <45> PCIE_PRX_DTX_P4 <45> PCIE_PTX_C_DRX_N4 <45> PCIE_PTX_C_DRX_P4 C309 C308 1 1 EU3@ EU3@ 2 .1U_0402_16V7K 2 .1U_0402_16V7K BF36 BE36 AY34 BB34 PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4 BG37 BH37 AY36 BB36 CAP on Conn, side BJ38 BG38 AU36 AV36 BG40 BJ40 AY40 BB40 BE38 BC38 AW38 AY38 C R153 R154 <37> CLK_PCIE_LAN# <37> CLK_PCIE_LAN 2 2 0_0402_5% 0_0402_5% CLK_PCIE_LAN#_R CLK_PCIE_LAN_R CLKREQ_LAN# <37> CLKREQ_LAN# +3V_PCH WLAN 1 1 R152 2 <36> CLKREQ_WLAN# +3VS J2 1 10K_0402_5% R149 1 R150 1 <36> CLK_PCIE_WLAN1# <36> CLK_PCIE_WLAN1 Y40 Y39 R156 1 2 R158 2 0_0402_5% 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49 CLK_PCIE_WLAN1_R AB47 2 0_0402_5% 1 10K_0402_5% CLKREQ_WLAN#_R M1 AA48 AA47 +3VS USB3.0 <45> CLK_PCIE_USB30# <45> CLK_PCIE_USB30 <45> CLKREQ_USB30# +3V_PCH R147 2 1 10K_0402_5% R334 R330 1 EU3@ 1 EU3@ 2 0_0402_5% 2 0_0402_5% CLK_USB30# CLK_USB30 R326 R301 1 EU3@ 2 2 0_0402_5% 1 10K_0402_5% CLKREQ_USB30#_R PCH_GPIO20 V10 Y37 Y36 A8 Y43 Y45 +3V_PCH R165 2 1 10K_0402_5% PCH_GPIO26 L12 V45 V46 +3V_PCH R168 2 1 10K_0402_5% PCH_GPIO44 L14 1 2 R135 2.2K_0402_5% +3VS 1 2 R138 2.2K_0402_5% 4 SMB_DATA_S3 SML0CLK SML0DATA A12 DRAMRST_CNTRL_PCH C8 PCH_SML0CLK G12 PCH_SML0DATA DRAMRST_CNTRL_PCH <7> 2 R139 1 1K_0402_5% SML1ALERT# / PCHHOT# / GPIO74 SML1CLK / GPIO58 SML1DATA / GPIO75 PERN8 PERP8 PETN8 PETP8 CL_CLK1 E14 SML1CLK M16 SML1DATA Q61A 2N7002DW-T/R7_SOT363-6 6 1 EC_SMB_CK2 +3V_PCH PCH_HOT# <42> 2.2K_0402_5% 1 R141 2 +3V_PCH EC_SMB_CK2 <23,39,42> VGA EC thermal sensor +3VS 1 2 R142 2.2K_0402_5% 4 EC_SMB_DA2 EC_SMB_DA2 <23,39,42> 2N7002DW-T/R7_SOT363-6 Q61B M7 +3V_PCH +3V_PCH CL_DATA1 CL_RST1# T11 P10 R143 10K_0402_5% R144 1 PEG_A_CLKRQ# / GPIO47 CLKOUT_PCIE0N CLKOUT_PCIE0P CLKOUT_PCIE1N CLKOUT_PCIE1P 1 10K_0402_5% PCH_HOT# D +3V_PCH 3 PERN7 PERP7 PETN7 PETP7 PCIECLKRQ0# / GPIO73 C13 SMB_DATA_S3 <12,13,36> 2N7002DW-T/R7_SOT363-6 Q60B R544 2.2K_0402_5% CLKOUT_PEG_A_N CLKOUT_PEG_A_P CLKOUT_DMI_N CLKOUT_DMI_P PCIECLKRQ1# / GPIO18 CLKOUT_DP_N CLKOUT_DP_P CLKOUT_PCIE2N CLKOUT_PCIE2P CLKIN_DMI_N CLKIN_DMI_P PCIECLKRQ2# / GPIO20 CLKOUT_PCIE3N CLKOUT_PCIE3P CLKIN_GND1_N CLKIN_GND1_P PCIECLKRQ3# / GPIO25 CLKIN_DOT_96N CLKIN_DOT_96P CLKOUT_PCIE4N CLKOUT_PCIE4P CLKIN_SATA_N CLKIN_SATA_P PCIECLKRQ4# / GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P REFCLK14IN PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK M10 PEG_CLKREQ#_R 0_0402_5% 2 CLK_REQ_VGA# <23> PCH_SML0CLK 1 R145 2 10K_0402_5% @ AB37 AB38 CLK_PCIE_VGA#_R CLK_PCIE_VGA_R AV22 AU22 CLK_CPU_DMI# CLK_CPU_DMI R146 R148 1 1 2 2 R545 2.2K_0402_5% PCH_SML0DATA 0_0402_5% CLK_PCIE_VGA# 0_0402_5% CLK_PCIE_VGA CLK_PCIE_VGA# <23> CLK_PCIE_VGA <23> C CLK_CPU_DMI# <6> CLK_CPU_DMI <6> AM12 AM13 BF18 BE18 CLK_BUF_CPU_DMI# CLK_BUF_CPU_DMI R155 1 R157 1 2 2 10K_0402_5% 10K_0402_5% BJ30 BG30 CLKIN_DMI2# CLKIN_DMI2 R159 1 R160 1 2 2 10K_0402_5% 10K_0402_5% G24 E24 CLK_BUF_DREF_96M# CLK_BUF_DREF_96M R162 1 R163 1 2 2 10K_0402_5% 10K_0402_5% AK7 AK5 CLK_BUF_PCIE_SATA# R164 1 CLK_BUF_PCIE_SATA R166 1 2 2 10K_0402_5% 10K_0402_5% K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5% H45 CLK_PCI_LPBACK V47 V49 XTAL25_IN_R XTAL25_OUT Y47 XCLK_RCOMP 12/29, Y2 changes to SJ10000E800 S CRYSTAL 25MHZ 10PF +-20PPM 7V25000014 CLK_PCI_LPBACK <18> B B XTAL25_IN 2 1 10K_0402_5% PCH_GPIO56 E6 V40 V42 +3V_PCH 2 R172 110K_0402_5% PCH_GPIO45 T13 V38 V37 +3V_PCH R174 2 1 10K_0402_5% PCH_GPIO46 K12 AK14 PCIE_CLK_8N AK13 PCIE_CLK_8P PEG_B_CLKRQ# / GPIO56 XCLK_RCOMP 1 R169 XTAL25_OUT R171 90.9_0402_1% 1 2 +1.05VS_VCCDIFFCLKN Y2 3 CLKOUT_PCIE6N CLKOUT_PCIE6P 2 PCIECLKRQ7# / GPIO46 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P OSC NC NC OSC 4 1 25MHZ_20PF_FSX3M-25.M20FDO PCIECLKRQ6# / GPIO45 CLKOUT_PCIE7N CLKOUT_PCIE7P 2 1M_0402_5% 27M_SSC CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67 1 R170 XTAL25_IN XTAL25_OUT K43 C196 12P_0402_50V8J F47 2 +3V_PCH CLKOUT_PEG_B_N CLKOUT_PEG_B_P FLEX CLOCKS AB42 AB40 1 LAN SML0ALERT# / GPIO60 2 R140 PERN4 PERP4 PETN4 PETP4 PERN6 PERP6 PETN6 PETP6 +3V_PCH 3 PERN3 PERP3 PETN3 PETP3 PERN5 PERP5 PETN5 PETP5 PCH_SMBDATA DIMM1 DIMM2 MINI CARD H47 LAN_48M K49 PCH_GPIO67 1 R207 @2 22_0402_5% 2 USB3.0 C9 SMB_CLK_S3 <12,13,36> 2.2K_0402_5% 1 2 R137 2 D SMBDATA 2.2K_0402_5% 1 R136 2 2 BG36 BJ36 AV34 AU34 PERN2 PERP2 PETN2 PETP2 +3V_PCH 1 BE34 BF34 BB32 AY32 2 R134 1 10K_0402_5% PCH_GPIO11 PCH_SMBCLK 2 PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2 E12 H14 5 2 .1U_0402_16V7K 2 .1U_0402_16V7K SMBCLK 2 1 1 SMBALERT# / GPIO11 5 C194 C195 PERN1 PERP1 PETN1 PETP1 2 BG34 BJ34 AV32 AU32 1 PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1 SMBUS 2 .1U_0402_16V7K 2 .1U_0402_16V7K Link 1 1 Controller <36> PCIE_PRX_DTX_N2 <36> PCIE_PRX_DTX_P2 <36> PCIE_PTX_C_DRX_N2 <36> PCIE_PTX_C_DRX_P2 C192 C193 CLOCKS WLAN <37> PCIE_PRX_DTX_N1 <37> PCIE_PRX_DTX_P1 <37> PCIE_PTX_C_DRX_N1 <37> PCIE_PTX_C_DRX_P1 PCI-E* LAN Q60A 2N7002DW-T/R7_SOT363-6 6 1 SMB_CLK_S3 1 5 C197 12P_0402_50V8J PCH_LAN_48M <37> PCH_GPIO67 <19> BIOS Request SKU ID PANTHER-POINT_FCBGA989 XTAL25_IN <36> GCLK_PCH_25MHZ CRYSTAL@ 2 0_0402_5% R1381 1 GCLK_PCH_25MHZ R1382 1 XTAL25_IN_R 2 0_0402_5% GCLK@ A A Compal Secret Data Security Classification Issued Date 2011/10/27 2012/10/27 Deciphered Date Title Compal Electronics, Inc. PCH (2/9) PCIE, SMBUS, CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.3 LA-7983P Date: 5 4 3 2 Sheet Thursday, January 05, 2012 1 15 of 60 5 4 3 2 1 D D U4C 5 1 R180 @ 100K_0402_5% 2 +3VS <5> <5> <5> <5> DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 <5> <5> <5> <5> DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 <5> <5> <5> <5> DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 BE24 BC20 BJ18 BJ20 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 AW24 AW20 BB18 AV18 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 AY24 AY20 AY18 AU18 DMI0RXP DMI1RXP DMI2RXP DMI3RXP DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI0TXP DMI1TXP DMI2TXP DMI3TXP FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 FDI_INT +1.05VS BJ24 1 R177 1 R178 C 2 DMI_IRCOMP 49.9_0402_1% 2 RBIAS_CPY 750_0402_1% BG25 BH21 DMI_ZCOMP FDI_FSYNC0 DMI_IRCOMP FDI_FSYNC1 DMI2RBIAS FDI_LSYNC0 4mil width and place within 500mil of the PCH FDI_LSYNC1 SUSACK# is only used on platform that support the Deep Sx state. 2 10K_0402_5% R184 +3VS 1 SYS_RST# SYS_PWROK AEPWROK can be connect to PWROK if iAMT disable R191 1 PCH_POK 2 APWROK 0_0402_5% @ 2 R556 1 <42> PCH_APWROK 0_0402_5% <6> PM_DRAM_PWRGD +3VS +3V_PCH PCH_PWROK 1 R190 <42> PCH_PWROK 1 R193 <42> EC_RSMRST# 2 PCH_POK 0_0402_5% @ R302 2 C12 K3 P12 L22 APWROK L10 PM_DRAM_PWRGD B13 2 PCH_RSMRST#_R 0_0402_5% C21 SUSWARN# K16 System Power Management DSWVRMEN SUSACK# T72 SUSACK# SYS_RESET# SYS_PWROK PWROK APWROK DRAMPWROK RSMRST# 1 200_0402_5% R192 2 1 300_0402_5% PM_DRAM_PWRGD R194 2 1 10K_0402_5% SUSWARN# R195 1 2 200K_0402_5% AC_PRESENT_R R197 2 1 10K_0402_5% PCH_RSMRST#_R B 1 R198 <42> PBTN_OUT# <42,49> ACIN D29 1 2 2 PBTN_OUT#_R 0_0402_5% AC_PRESENT_R CH751H-40PT_SOD323-2 2 R200 1 PCH_GPIO72 10K_0402_5% +3V_PCH 2 R201 1 RI# 10K_0402_5% E20 H20 E10 A10 DPWROK WAKE# CLKRUN# / GPIO32 SUS_STAT# / GPIO61 SUSCLK / GPIO62 SLP_S5# / GPIO63 SLP_S4# SUSWARN#/SUSPWRDNACK/GPIO30 PWRBTN# SLP_S3# SLP_A# ACPRESENT / GPIO31 BATLOW# / GPIO72 SLP_SUS# PMSYNCH RI# SLP_LAN# / GPIO29 BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 AW16 FDI_INT AV12 FDI_FSYNC0 BC10 FDI_FSYNC1 AV14 FDI_LSYNC0 BB10 FDI_LSYNC1 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 <5> <5> <5> <5> <5> <5> <5> <5> FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 <5> <5> <5> <5> <5> <5> <5> <5> FDI_INT <5> A18 DSWODVREN E22 PCH_DPWROK B9 WAKE# FDI_FSYNC0 <5> FDI_FSYNC1 <5> FDI_LSYNC0 <5> FDI_LSYNC1 <5> 1 R181 N3 1 R185 1 R186 PM_CLKRUN# G8 SUS_STAT# 2 0_0402_5% 2 10K_0402_5% +RTCVCC * 1 SYS_PWROK <6> FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 2 PCH_RSMRST#_R 0_0402_5% 1 @ R189 8.2K_0402_5% 2 2 N14 R183 330K_0402_5% @ +3VS PCIE_WAKE# <36,37,45> +3V_PCH T74 C R179 330K_0402_5% 烉 烉 DSWODVREN - On Die DSW VR Enable H Enable L Disable 2 4 SYS_PWROK DMI0RXN DMI1RXN DMI2RXN DMI3RXN 1 Y B DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 2 A DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 FDI 2 PCH_PWROK <5> <5> <5> <5> DMI 1 VGATE P <55> G 3 U15 MC74VHC1G08DFT2G SC70 5P BC24 BE20 BG18 BG20 R299 10K_0402_5% 1 SUSCLK <42> D10 PM_SLP_S5# <42> H4 PM_SLP_S4# <42> F4 PM_SLP_S3# <42> G10 SLP_A# T99 G16 PM_SLP_SUS# T71 AP14 H_PM_SYNC K14 PCH_GPIO291 Can be left NC when IAMT is not support on the platfrom B H_PM_SYNC <6> 2 R261 @ 10K_0402_5% Can be left NC if no use integrated LAN. +3V_PCH PANTHER-POINT_FCBGA989 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/10/27 2012/10/27 Deciphered Date Title PCH (3/9) DMI,FDI,PM, THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.3 LA-7983P Date: 5 4 3 2 Thursday, January 05, 2012 Sheet 1 16 of 60 5 4 3 2 1 U4D T45 P39 2.2K_0402_5%1 R204 2.2K_0402_5%1 R205 2 2 CTRL_CLK CTRL_DATA 2 R206 2.37K_0402_1% 1 LVDS_IBG AF37 AF36 LVD_VREF AE48 AE47 AK39 AK40 <33> LVDS_ACLK# <33> LVDS_ACLK C <33> LVDS_A0# <33> LVDS_A1# <33> LVDS_A2# AN48 AM47 AK47 AJ48 <33> LVDS_A0 <33> LVDS_A1 <33> LVDS_A2 AN47 AM49 AK49 AJ47 AF40 AF39 <33> LVDS_BCLK# <33> LVDS_BCLK +3VS R524 2.2K_0402_5% <33> LVDS_B0 <33> LVDS_B1 <33> LVDS_B2 AH43 AH49 AF47 AF43 DAC_BLU 1 150_0402_1% DAC_GRN 1 150_0402_1% DAC_RED 1 150_0402_1% R208 2 <34> DAC_GRN R209 2 <34> DAC_RED R210 2 N48 P49 T49 SDVO_STALLN SDVO_STALLP L_DDC_CLK L_DDC_DATA SDVO_INTN SDVO_INTP CRT_DDC_CLK CRT_DDC_DATA <34> CRT_DDC_CLK <34> CRT_DDC_DATA CRT_DDC_CLK CRT_DDC_DATA T39 M40 M47 M49 1 <34> CRT_HSYNC <34> CRT_VSYNC CRT_IREF T43 T42 AP39 AP40 HDMI@ R202 2.2K_0402_5% LVD_IBG LVD_VBG SDVO_CTRLCLK SDVO_CTRLDATA LVD_VREFH LVD_VREFL LVDSA_CLK# LVDSA_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 DDPB_AUXN DDPB_AUXP DDPB_HPD LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 CRT_BLUE CRT_GREEN CRT_RED DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P DDPC_CTRLCLK DDPC_CTRLDATA DDPC_AUXN DDPC_AUXP DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P DDPD_CTRLCLK DDPD_CTRLDATA CRT_DDC_CLK CRT_DDC_DATA DDPD_AUXN DDPD_AUXP DDPD_HPD DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P CRT_HSYNC CRT_VSYNC DAC_IREF CRT_IRTN R203 HDMI@ 2.2K_0402_5% P38 HDMICLK_NB M39 HDMIDAT_NB AT49 AT47 AT40 HDMICLK_NB <35> HDMIDAT_NB <35> TMDS_B_HPD TMDS_B_HPD <35> AV42 TMDS_B_DATA2#_PCHHDMI@ AV40 TMDS_B_DATA2_PCH HDMI@ AV45 TMDS_B_DATA1#_PCHHDMI@ AV46 TMDS_B_DATA1_PCH HDMI@ AU48 TMDS_B_DATA0#_PCHHDMI@ AU47 TMDS_B_DATA0_PCH HDMI@ AV47 TMDS_B_CLK#_PCH HDMI@ AV49 TMDS_B_CLK_PCH HDMI@ P46 P42 C200 C201 C202 C203 C204 C205 C206 C207 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K HDMI_TX2-_CK HDMI_TX2+_CK HDMI_TX1-_CK HDMI_TX1+_CK HDMI_TX0-_CK HDMI_TX0+_CK HDMI_CLK-_CK HDMI_CLK+_CK <35> <35> <35> <35> <35> <35> <35> <35> HDMI D2 HDMI HDMI D1 HDMI D0 C HDMI CLK CAP move on Conn, side AP47 AP49 AT38 AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 M43 M36 B AT45 AT43 BH41 BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42 PANTHER-POINT_FCBGA989 2 R211 1K_0402_1% AM42 AM40 L_CTRL_CLK L_CTRL_DATA 2 R559 2.2K_0402_5% 2 B 1 1 <34> DAC_BLU <33> LVDS_B0# <33> LVDS_B1# <33> LVDS_B2# AH45 AH47 AF49 AF45 L_BKLTCTL 1 T40 K47 +3VS 1 EDID_CLK EDID_DATA D AP43 AP45 2 P45 PCH_PWM <33> EDID_CLK <33> EDID_DATA SDVO_TVCLKINN SDVO_TVCLKINP 2 +3VS L_BKLTEN L_VDD_EN Digital Display Interface <33> EDID_CLK EDID_DATA J47 M45 <33> PCH_ENBKL <33> PCH_ENVDD LVDS R234 2.2K_0402_5% 2 2 R523 2.2K_0402_5% CRT D 1 1 +3VS A A Compal Secret Data Security Classification Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 PCH (4/9) LVDS,CRT,DP,HDMI Document Number Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet 1 17 of 60 5 4 3 2 1 +3VS U4E RP2 1 2 3 4 PCI_PIRQA# PCI_PIRQD# PCI_PIRQC# PCI_PIRQB# BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45 8.2K_0804_8P4R_5% RP1 8 1 PCH_GPIO2 7 2 DGPU_PWR_EN_R 6 3 PCH_GPIO4 5 4 ODD_DA#_R D 8.2K_0804_8P4R_5% R213 1 2 8.2K_0402_5% PCH_GPIO5 R225 1 2 8.2K_0402_5% PCH_WL_OFF# R292 1 @ 2 8.2K_0402_5% PCH_GPIO51 R557 1 @ 2 8.2K_0402_5% PCH_GPIO53 R259 1 2 8.2K_0402_5% DGPU_PWR_EN1 R212 1 2 8.2K_0402_5% DGPU_HOLD_RST#_R R214 1 PPT EDS DOC#474146 B21 M20 AY16 BG46 9/22 NA 9/26 Mount 2 100K_0402_5% DGPU_HOLD_RST#_R @ RSVD1 RSVD2 RSVD3 RSVD4 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD 8 7 6 5 TP21 TP22 TP23 TP24 RSVD23 RSVD24 RSVD25 9/22 from 8.2K NA 9/26 NA Boot BIOS Strap bit1 BBS1 <45> USB3_RX3_N <45> USB3_RX4_N Boot BIOS Bit11 Bit10 Destination GNT1#/ GPIO51 0 1 Reserved 1 0 Reserved 1 1 0 0 1 DGPU_PWR_EN_R R319 * SPI <45> USB3_RX3_P <45> USB3_RX4_P <45> USB3_TX3_N <45> USB3_TX4_N (Default) LPC USB3_RX3_N USB3_RX4_N USB3_RX1_P T1832 T1826 USB3_RX3_P USB3_RX4_P USB3_TX1_N T1831 T1827 USB3_TX3_N USB3_TX4_N USB3_TX1_P T1830 T1828 USB3_TX3_P USB3_TX4_P <45> USB3_TX3_P <45> USB3_TX4_P 2 NVDD_PWR_EN 0_0402_5% PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# @ B PCH_WL_OFF# R215 1 @ R553 1 R692 1 R691 1 <23> DGPU_HOLD_RST# <54> NVDD_PWR_EN <23,25> DGPU_PWR_EN GPIO55 2 1K_0402_5% Low=A16 swap override/Top-Block PCI_GNT3# Swap Override enabled High=Default PCH_GPIO51 PCH_GPIO53 PCH_WL_OFF# R715 1 <40,42> ODD_DA# K40 K38 H38 G38 2 0_0402_5% DGPU_HOLD_RST#_RC46 2 0_0402_5% DGPU_PWR_EN1 C44 2 0_0402_5% DGPU_PWR_EN_R E40 <36> PCH_WL_OFF# A16 swap overide Strap/Top-Block Swap Override jumper BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30 @ PCH_GPIO2 2 0_0402_5% ODD_DA#_R PCH_GPIO4 PCH_GPIO5 D47 E42 F46 G42 G40 C42 D44 * <42> K10 PCI_PME# PCH_PLTRST# <6> PCH_PLTRST# 22_0402_5% 1 22_0402_5% 1 22_0402_5% 2 <15> CLK_PCI_LPBACK <42> CLK_PCI_EC <36> CLK_PCI_DB @ 2 R219 2 R220 1 R173 C6 CLK_PCI_LPBACK_R H49 H43 CLK_PCI_EC_R J48 CLK_PCI_DB_R K42 H40 1 R222 2 0_0402_5% USB3Rn1 USB3Rn2 USB3Rn3 USB3Rn4 USB3Rp1 USB3Rp2 USB3Rp3 USB3Rp4 USB3Tn1 USB3Tn2 USB3Tn3 USB3Tn4 USB3Tp1 USB3Tp2 USB3Tp3 USB3Tp4 RSVD28 RSVD29 AT10 BC8 D AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 AV5 AV10 AT8 AY5 BA2 AT12 BF3 C USB DEBUG=PORT1 AND PORT9 PIRQA# PIRQB# PIRQC# PIRQD# USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 USB C USB3_RX1_N PCI T1829 T1825 RSVD26 RSVD27 AY7 AV7 AU3 BG4 GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 USBRBIAS# USBRBIAS C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32 C33 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N5 USB20_P5 USB20_N9 USB20_P9 USB20_N11 USB20_P11 USB20_N13 USB20_P13 USBRBIAS <44> <44> <45> <45> <45> <45> (CR-B/D USB) LEFT USB LEFT USB USB20_N5 <33> USB20_P5 <33> USB Camera USB20_N9 <44> USB20_P9 <44> USB20_N10 <36> USB20_P10 <36> USB20_N11 <43> USB20_P11 <43> WLAN USB20_N13 <40> USB20_P13 <40> Bluetooth (USB 3.0) RIGHT USB 1 R218 2 22.6_0402_1% Within 500 mils B33 +3V_PCH PME# PLTRST# OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 A14 K20 B17 C16 L16 A16 D14 C14 B CARD READER USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# SMIB USB_OC7# USB_OC0# <44> USB_OC1# <45> 10K_1206_8P4R_5% RP3 4 USB_OC5# 3 USB_OC2# 2 USB_OC7# 1 USB_OC0# USB_OC4# <44> SMIB <45> USB_OC1# USB_OC4# USB_OC3# 3 G P 4 B Y 1 PLT_RST# C208 @ 1U_0402_6.3V4Z 2 5 1 2 <23,36,37,42,45> 1 A PCH_PLTRST# 2 U7@ MC74VHC1G08DFT2G SC70 5P Compal Secret Data Security Classification Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title PCH (5/9) PCI, USB THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. +3VS R223 100K_0402_5% Rev 0.3 LA-7983P Date: 5 5 6 7 8 1 R267 2 IU3@ 10K_0402_5% SMIB A 4 3 2 1 10K_1206_8P4R_5% RP4 PANTHER-POINT_FCBGA989 A 5 6 7 8 4 3 2 Thursday, January 05, 2012 Sheet 1 18 of 60 2 1 Weak internal pull-high 1 R235 2 10K_0402_5% 2 1 R704 PCH_GPIO71 PCH_GPIO71 0 1 USB3.0 by PCH USB3.0 by NEC 9/22 from 10K T7 PCH_GPIO1 A42 2 10K_0402_5% PCH_GPIO6 H36 EC_SCI# E38 EC_SMI# C10 GPIO28 On-Die PLL Voltage Regulator This signal has a weak internal pull up 1 9/22 from 10K 2 1K_0402_5% PCH_GPIO28 @ 1 R228 +3VS voltage regulator enable 烉 烉On-Die On-Die PLL Voltage Regulator disable H L +3V_PCH <42> EC_SCI# <42> EC_SMI# 1 R229@ 2 10K_0402_5% PCH_GPIO12 C4 1 R230 2 1K_0402_5% EC_LID_OUT# G2 1 R231 2 10K_0402_5% PCH_GPIO16 U2 BMBUSY# / GPIO0 TACH4 / GPIO68 TACH1 / GPIO1 TACH5 / GPIO69 TACH2 / GPIO6 TACH6 / GPIO70 TACH3 / GPIO7 TACH7 / GPIO71 1 2 10K_0402_5% @ PCH_GPIO27 +3VS GPIO15 A20GATE R232 1 +3VS <36> BT_DISABLE# @ D40 BT_DISABLE# T5 ODD_EN E8 10K_0402_5% <40> ODD_EN +3V_PCH PCH_GPIO27 E16 1 2 10K_0402_5% PCH_GPIO28 P8 1 R242 2 10K_0402_5% PCH_BT_ON# K1 1 R243 2 10K_0402_5% PCH_GPIO35 K4 R241 +3VS 1 1 +3VS R250 @ 10K_0402_5% 2 2 R244 @ 10K_0402_5% PCH_GPIO36 +3VS 1 1 PCH_GPIO37 R881 10K_0402_5% +3VS +3V_PCH PCH_GPIO36 V8 PCH_GPIO37 M5 PCH_GPIO38 N2 R247 1 2 10K_0402_5% PCH_GPIO39 M3 R248 1 2 10K_0402_5% PCH_GPIO48 V13 R249 1 2 10K_0402_5% PCH_GPIO49 V3 R251 1 2 10K_0402_5% PCH_GPIO57 D6 TACH0 / GPIO17 SCLOCK / GPIO22 GPIO24 GPIO27 GPIO28 PROCPW RGD THRMTRIP# INIT3_3V# DF_TVS TS_VSS1 STP_PCI# / GPIO34 TS_VSS2 GPIO35 TS_VSS3 SATA2GP / GPIO36 TS_VSS4 NC_1 A45 A46 BIOS Request SKU ID A5 +3VS A6 B3 UMA@ 1 2 R246 10K_0402_5% 1 R711 10K_0402_5% 2 B47 BD1 BD49 UMA@ BE1 BE49 PCH_GPIO38 1 R298 BF1 PCH_GPIO67 <15> BF49 10K_0402_5% A 2 1 N13P@ R708 10K_0402_5% 2 PCH_GPIO67 N 13P@ P4 AU16 P5 @ 2 R237 KBRST# AY11 AY10 H_PECI <6,42> KBRST# <42> H_CPUPWRGD PCH_THRMTRIP#_R 1 R239 SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16 GPIO57 VSS_NCTF_17 VSS_NCTF_1 VSS_NCTF_19 VSS_NCTF_2 VSS_NCTF_20 VSS_NCTF_3 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_6 VSS_NCTF_24 VSS_NCTF_7 VSS_NCTF_25 VSS_NCTF_8 VSS_NCTF_26 VSS_NCTF_9 VSS_NCTF_27 VSS_NCTF_10 VSS_NCTF_28 VSS_NCTF_11 VSS_NCTF_29 VSS_NCTF_12 VSS_NCTF_30 VSS_NCTF_13 VSS_NCTF_31 VSS_NCTF_14 VSS_NCTF_32 1 R226 2 10K_0402_5% 2 H_THRMTRIP# 390_0402_5% H_THRMTRIP# <6> C T14 PCH_THRMTRIP#_R <23> AY1 INIT3_3V AH8 This signal has weak internal PU,can't pull low +1.8VS AK11 AH10 DMI Termination Voltage AK10 Set to Vcc when HIGH NV_CLE R216 2.2K_0402_5% P37 2 1 R217 VSS_NCTF_15 VSS_NCTF_5 KBRST# <6> NV_CLE SDATAOUT1 / GPIO48 VSS_NCTF_4 +3VS GATEA20 <42> 1 PCH_PECI_R 0_0402_5% SDATAOUT0 / GPIO39 NCTF A44 B +3VS PCH_GPIO71 Set to Vss when LOW SLOAD / GPIO38 VSS_NCTF_18 A4 PCH_GPIO70 A40 SATA3GP / GPIO37 2 2 R547 10K_0402_5% SATA4GP / GPIO16 RCIN# DGPU_PWROK_R 10K_0402_1% 2 R238 <36,40> PCH_BT_ON# +3VS PECI 2 0_0402_5% 1 2 PU on power side C41 R236 10K_0402_5% CPU/MISC C R245 R297 1 <46,54> DGPU_PWROK PCH_GPIO69 LAN_PHY_PW R_CTRL / GPIO12 GPIO +3VS PCH_GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable Low: VCCVRM VR Disable 2 PCH_GPIO68 B41 GPIO8 <42> EC_LID_OUT# * 10K_0402_5%1 R224 C40 1 PCH_GPIO0 2 10K_0402_5% BG2 Weak internal PU,Do not pull low BG48 2 2 10K_0402_5% 1 R227 2 1 R233 9/22 from 10K +3VS 1 +3VS R240 D EC_SMI# U4F * R706 10K_0402_5% @ 14/15" 17" 0 1 2 2 R705 @ Function 1 1 +3V_PCH +3VS PCH_GPIO70 200K_0402_5% @ D PCH_GPIO70 2 R707 R703 1 1 2 PCH_GPIO69 10K_0402_5% @ R702 +3VS 10K_0402_5% 2 +3VS 1 3 10K_0402_5% 4 200K_0402_5% 5 H_SNB_IVB# <6> 1K_0402_5% CLOSE TO THE BRANCHING POINT BH3 BH47 BJ4 BJ44 B BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49 PANTHER-POINT_FCBGA989 PCH_GPIO38 PCH_GPIO67 Function A 0 0 Optimus 0 1 Reserved 1 0 DIS 1 1 UMA Compal Secret Data Security Classification Issued Date 2011/10/27 2012/10/27 Deciphered Date Title PCH (6/9) GPIO, CPU, MISC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 Rev 0.3 LA-7983P 4 3 2 Thursday, January 05, 2012 Sheet 19 of 1 Compal Electronics, Inc. 60 5 4 +1.05VS EDS v2.1 Integrated Graphic: 1.3A 3 2 L1 Change to 1 ohm P/N S RES 1/10W 1 +-1% 0603 POWER U4G +3VS @ J2 2 2 +1.05VS VCCADAC VSSADAC VCCALVDS VSSALVDS VCCTX_LVDS[1] VCCTX_LVDS[2] AN17 AN21 AN26 AN27 Integrated Graphic: 3.709A AP21 C AP23 +1.05VS_VCC_EXP 2 AP26 AT24 AN33 AN34 +3VS 1 0_0603_5% 2 R260 228mA 1 C227 .1U_0402_16V7K 2 This pin can be left as no connect in On-Die VR enabled mode (default). +1.05VS +1.05VS_VCCAPLL_FDI 2 R263 VCCIO[16] VCCIO[17] AP16 BG6 +1.05VS_VCCDPLL_FDIAP17 +VCCP_VCCDMI AU20 B VCC3_3[6] 2 1 C214 .1U_0402_16V7K 2 1 C215 10U_0603_6.3V6M C395 10U_0603_6.3V6M @ 2 Voltage Rail AK36 1mA* +VCCA_LVDS 2 R295 V_PROC_IO 1 0_0603_5% V5REF VCC3_3[7] AM38 40mA +VCCTX_LVDS 1 AP36 AP37 2 1 C216 0.01U_0402_16V7K 2 V5REF_Sus +1.8VS L2 0.1UH_MLF1608DR10KT_10%_1608 2 1 AM37 0.001 5 0.001 D C217 0.01U_0402_16V7K 2 V33 +3VS_VCC3_3_6 2 R256 5 0.001 Vcc3_3 3.3 0.228 VccADAC 3.3 0.001 VccADPLLA 1.05 0.075 VccADPLLB 1.05 0.075 VccCore 1.05 1.3 VccDMI 1.05 0.042 VccIO 1.05 3.709 0.1uH inductor, 200mA 1 C218 22U_0805_6.3V6M +3VS V34 2 VCCVRM[3] 1 0_0603_5% C219 .1U_0402_16V7K AT16 +VCCAFDI_VRM +VCCP_VCCDMI VCCIO[21] VCCIO[24] 1.05 AK37 VCCIO[20] VCCIO[23] S0 Iccmax Current (A) 167mA VCCIO[19] VCCIO[22] Voltage 1 VCCIO[18] VCCDMI[1] AT20 +VCCP_VCCDMI 42mA 1 +1.05VS VCCCLKDMI AB36 +1.05VS_VCC_DMI_CCI 75mA 2 R294 1 C226 1U_0402_6.3V6K VccASW 1.05 0.903 VccSPI 3.3 0.01 0.001 +V1.05S_VCCP 1 0_0603_5% 2 2 R258 C 1 0_0603_5% VccDSW 3.3 VccDFTERM 1.8 0.002 VccRTC 3.3 6 uA 3.3 0.065 C220 1U_0402_6.3V6K 2 VCCIO[25] VCCIO[26] VCCDFTERM[1] VCC3_3[3] 167mA +VCCAFDI_VRM T50 1 0_0603_5% BH29 +3VS_VCCA3GBG VCCIO[15] VCCVRM[2] VccAFDIPLL VCCDFTERM[2] VCCDFTERM[3] VCCDFTERM[4] AG16 VccSus3_3 +VCCPNAND AG17 +1.8VS VCCDMI[2] 2 R293 1 AJ17 1 0_0603_5% C228 .1U_0402_16V7K 2 VCCSPI VccSusHDA 3.3 / 1.5 0.01 VccVRM 1.8 / 1.5 0.167 2mA* AJ16 +3VS 10mA VCCIO[27] FDI 2 1 C225 1U_0402_6.3V6K 2 1 C224 1U_0402_6.3V6K 2 1 C223 1U_0402_6.3V6K 1 C222 1U_0402_6.3V6K 2 C221 10U_0603_6.3V6M 1 AP24 1 C213 0.01U_0402_16V7K 228mA VCCAPLLEXP HVCMOS AN16 DMI This pin can be left as no connect in On-Die VR enabled mode (default). 1 U47 PCH Power Rail Table Refer to CPU EDS R1.5 1_0603_1% 1 VCCIO[28] DFT / SPI BJ22 +VCCAPLLEXP T47 L1 2 63mA +VCCADAC +3VS VCCTX_LVDS[4] VCCIO AN19 1 +1.05VS_VCCDPLLEXP 0_0603_5% U48 2 VCCTX_LVDS[3] 2 R254 +1.05VS VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17] CRT 1 C212 1U_0402_6.3V6K 2 1 C211 1U_0402_6.3V6K 2 D 1 C210 1U_0402_6.3V6K 1 C209 10U_0603_6.3V6M PAD-OPEN 4x4m AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31 +1.05VS_VCCCORE LVDS 1 VCC CORE 2 1 V1 VccCLKDMI 1.05 0.075 VccSSC 1.05 0.095 R399 1 +3V_VCCPSPI PANTHER-POINT_FCBGA989 2 2 VccDIFFCLKN 1.05 0.055 VccALVDS 3.3 0.001 VccTX_LVDS 1.8 0.04 0_0402_5% 1 C230 1U_0402_6.3V6K B +VCCAFDI_VRM +1.5VS 2 R265 1 0_0603_5% +VCCAFDI_VRM Intel recommand stuff R265 and unstuff R266 VCCVRM==>1.5V FOR MOBILE VCCVRM==>1.8V FOR DESKTOP VCCVRM = 160mA detal waiting for newest spec A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/10/27 2012/10/27 Deciphered Date Title PCH (7/9) PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.3 LA-7983P Date: 5 4 3 2 Thursday, January 05, 2012 Sheet 1 20 of 60 5 4 3 2 1 Have internal VRM +3V_PCH V12 +3VS_VCC_CLKF33 T38 BH23 +VCCDPLL_CPY AL29 AL24 AA19 AA21 903mA AA24 +1.05VM_VCCASW 2 C242 22U_0805_6.3V6M 2 1 C241 22U_0805_6.3V6M 1 AA26 AA27 AA29 AA31 AC26 C AC27 AC29 AC31 AD29 1 +1.05VS_VCCA_A_DPL 2 C246 1U_0402_6.3V6K 2 2 1 C245 1U_0402_6.3V6K 2 L5 1 C244 1U_0402_6.3V6K 1 +1.05VS 10UH_LB2012T100MR_20% AD31 R300 0_0603_5% W21 W23 2 +1.05VS_VCCA_B_DPL W24 2 1 2 C253 1U_0402_6.3V6K @2 1 C187 22U_0805_6.3V6M 2 + C252 220U_B2_2.5VM_R35 @ 2 C251 1U_0402_6.3V6K C186 22U_0805_6.3V6M C250 220U_B2_2.5VM_R35 1 1 VCCSUS3_3[8] VCCIO[14] DCPSUS[3] 130mA VCCSUS3_3[9] VCCSUS3_3[10] W26 W29 W31 W33 VCCASW[1] VCCIO[34] N16 +VCCRTCEXT 1 Y49 D T29 +3V_PCH T23 R272 T24 1 V23 2 V24 P24 T26 2 +3V_VCCPUSB 1 +5VALW_PCH +3V_PCH 0_0603_5% +3V_PCH R273 2 +3V_VCCAUBG 1 2 +1.05VS_VCCAUPLL 1 0_0603_5% C238 .1U_0402_16V7K +1.05VS R276 2 1 R275 10_0402_5% 0_0603_5% 1mA V5REF_SUS VCCASW[3] VCCASW[4] VCCASW[5] VCCASW[6] VCCASW[7] VCCASW[8] VCCASW[9] VCCASW[10] VCCASW[11] VCCASW[12] VCCASW[13] VCCASW[14] VCCASW[15] DCPSUS[4] VCCSUS3_3[1] M26 +PCH_V5REF_SUS AN23 +VCCA_USBSUS C243 @1 @ 2 1U_0402_6.3V6K AN24 +3V_VCCPSUS C316 @1 @ 2 .1U_0402_16V7K P34 +PCH_V5REF_RUN N20 +3V_VCCPSUS +5VS 1mA V5REF +3V_PCH R278 2 VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCC3_3[1] VCC3_3[8] VCCASW[16] VCC3_3[4] 1 N22 2 P20 D1 CH751H-40PT_SOD323-2 +PCH_V5REF_SUS C240 0.1U_0402_25V6 1 AA16 +3VS_VCCPCORE DCPRTC 167mA VCCVRM[4] VCCIO[13] +PCH_V5REF_RUN 1 2 C249 0_0603_5% .1U_0402_16V7K C248 1U_0402_6.3V6K +3VS R282 T34 2 +3VS_VCCPPCI 1 +3VS VCCASW[20] +3VS 1 2 W16 C D2 CH751H-40PT_SOD323-2 R281 2 R283 VCC3_3[2] +3VS R279 10_0402_5% C247 1U_0402_6.3V 2 VCCASW[18] VCCASW[19] 1 0_0603_5% P22 VCCASW[17] VCCIO[12] +VCCAFDI_VRM 2 1 0_0603_5% T27 VCCASW[2] VCCIO[5] C258 .1U_0402_16V7K 2 0_0603_5% C233 1U_0402_6.3V6K 2 2 R277 0_0805_5% 1 2 80mA VCCAPLLDMI2 VCCSUS3_3[6] @ C239 1U_0402_6.3V6K P28 65mA VCCSUS3_3[7] USB +VCCAPLL_CPY_PCH +1.05VS 2 VCCIO[33] 1 P26 VCC3_3[5] PCI/GPIO/LPC 1 0_0603_5% 1 1 VCCIO[32] R289 C236 .1U_0402_16V7K 2 R271 +VCCSUS1 + DCPSUSBYP T101 +1.05VS +5VALW_PCH 1 2 +PCH_VCCDSW 2 +1.05VS_VCCUSBCORE 1 1 C235 @ .1U_0402_16V7K VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA L6 1 2 10UH_LB2012T100MR_20% 1 VCCIO[30] 1mA VCCDSW3_3 N26 1 T16 VCCIO[29] 2 C234 .1U_0402_16V7K VCCACLK VCCIO[31] 2 +5VALW R270 AD49 2 烉On-Die PLL voltage regulator enable 1 +1.05VS +VCCPDSW 1 1 1 0_0603_5% On-Die PLL Voltage Regulator H POWER U4J 2 1 2 R269 C232 1U_0402_6.3V6K 2 D 1 2 +3VS_VCC_CLKF33 1 +VCCACLK Clock and Miscellaneous 1 0_0603_5% C231 10U_0603_6.3V6M 2 R303 R268 @ 0_0603_5% 2 1 1 +1.05VS 2 +3VS AJ2 2 +VCC3_3_2 1 1 0_0603_5% C254 .1U_0402_16V7K 1 +1.05VS_SATA3 +1.05VS 0_0603_5% R285 AF13 2 C255 2 .1U_0402_16V7K 1 0_0603_5% C257 1U_0402_6.3V6K AH13 AH14 2 +1.05VS_SATA3 1 2 B C256 1U_0402_6.3V6K +1.05VS_VCCDIFFCLKN 2 +1.05VS_VCCA_B_DPL BF47 +VCCDIFFCLK AF17 AF33 AF34 AG34 55mA 1 0_0603_5% 1 2 +1.05VS 2 R284 +1.05VM_VCCSUS V16 +1.05VM_VCCSUS T17 V19 1 2 1 2 AF11 T100 VCCIO[2] VCCIO[4] 95mA AC16 烉On-Die PLL voltage regulator enable On-Die PLL Voltage Regulator +VCCAFDI_VRM +1.05VS_VCC_SATA +1.05VS 2 +1.05VS_VCC_SATA AC17 1 VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA 0_0603_5% C261 1U_0402_6.3V6K 1 AD17 +1.05VS DCPSST DCPSUS[1] DCPSUS[2] V_PROC_IO 1mA +RTCVCC VCCASW[22] VCCASW[23] VCCASW[21] T21 V21 T19 +3V_PCH R287 A22 2 1 2 1 2 C270 .1U_0402_16V7K 1 C269 .1U_0402_16V7K @ C268 1U_0402_6.3V6K C267 .1U_0402_16V7K 2 BJ8 +V_CPU_IO C266 .1U_0402_16V7K 1 0_0603_5% 1 1 C265 4.7U_0603_6.3V6K 2 A +VCCSST 2 1 C264 @ 1U_0402_6.3V6K +VCCSATAPLL +VCCAFDI_VRM R288 +V1.05S_VCCP 2 R286 @ R290 0_0603_5% 2 1 VCCIO[7] VCCDIFFCLKN[1] VCCDIFFCLKN[2] VCCDIFFCLKN[3] VCCSSC AK1 2 C263 .1U_0402_16V7K C262 1U_0402_6.3V6K AG33 +1.05VS_SSCVCC C259 1U_0402_6.3V6K B AF14 H VCCVRM[1] VCCIO[3] 1 0_0603_5% 1 2 +1.05VS +1.05VS_VCCDIFFCLKN 75mA VCCAPLLSATA MISC 2 R280 VCCADPLLB 75mA VCCRTC HDA +1.05VS VCCIO[6] VCCADPLLA SATA BD47 +1.05VS_VCCA_A_DPL CPU 1 0_0603_5% 1 RTC +1.05VS 2 R274 10mA VCCSUSHDA P32 +VCCSUSHDA 1 PANTHER-POINT_FCBGA989 @ 2 1 0_0603_5% C271 0.1U_0402_16V4Z A 2 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/10/27 2012/10/27 Deciphered Date Title PCH (8/9) PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.3 LA-7983P Date: 5 4 3 2 Thursday, January 05, 2012 Sheet 1 21 of 60 5 4 3 2 1 U4I D AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3 U4H H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3 C B VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28 PANTHER-POINT_FCBGA989 VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28 VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] D C B A A PANTHER-POINT_FCBGA989 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/10/27 2012/10/27 Deciphered Date Title PCH (9/9) VSS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.3 LA-7983P Date: 5 4 3 2 Thursday, January 05, 2012 Sheet 1 22 of 60 5 4 3 2 1 +3VS_VGA 2 C QV1A 1 VGA_SMB_DA2 6 EC_SMB_DA2 <15,39,42> 2N7002DW-T/R7_SOT363-6 N13P@ +3VS_VGA +3VS_VGA 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N0 PCIE_CRX_C_GTX_P1 PCIE_CRX_C_GTX_N1 PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2 PCIE_CRX_C_GTX_P3 PCIE_CRX_C_GTX_N3 PCIE_CRX_C_GTX_P4 PCIE_CRX_C_GTX_N4 PCIE_CRX_C_GTX_P5 PCIE_CRX_C_GTX_N5 PCIE_CRX_C_GTX_P6 PCIE_CRX_C_GTX_N6 PCIE_CRX_C_GTX_P7 PCIE_CRX_C_GTX_N7 PCIE_CRX_C_GTX_P8 PCIE_CRX_C_GTX_N8 PCIE_CRX_C_GTX_P9 PCIE_CRX_C_GTX_N9 PCIE_CRX_C_GTX_P10 PCIE_CRX_C_GTX_N10 PCIE_CRX_C_GTX_P11 PCIE_CRX_C_GTX_N11 PCIE_CRX_C_GTX_P12 PCIE_CRX_C_GTX_N12 PCIE_CRX_C_GTX_P13 PCIE_CRX_C_GTX_N13 PCIE_CRX_C_GTX_P14 PCIE_CRX_C_GTX_N14 PCIE_CRX_C_GTX_P15 PCIE_CRX_C_GTX_N15 AK14 AJ14 AH14 AG14 AK15 AJ15 AL16 AK16 AK17 AJ17 AH17 AG17 AK18 AJ18 AL19 AK19 AK20 AJ20 AH20 AG20 AK21 AJ21 AL22 AK22 AK23 AJ23 AH23 AG23 AK24 AJ24 AL25 AK25 PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N 2 <15> CLK_PCIE_VGA <15> CLK_PCIE_VGA# Differential signal Y PEX_TSTCLK_OUT PEX_TSTCLK_OUT# PLT_RST_VGA# PEX_TERMP DACA_VDD DACA_VREF DACA_RSET 0_0402_5% 1 3 2 4 6 1 D N13P@ 1 VGA_AC_DET <42,54> DV3 CH751H-40PT_SOD323-2 2 RV17 2 RV114 DPRSLPVR_VGA @ @ @ RV233 2 2PSI#_VGA PSI#_VGA <54> AK9 AL10 AL9 VGA_EDID_CLK AM9 AN9 VGA_EDID_DATA VGA_CRT_DATA AG10 AP9 AP8 +DACA_VDD 10K_0402_5% 2 RV107 1 VGA_CRT_CLK I2CB_SCL N13P@ VGA_GPIO12 I2CA_SCL I2CA_SDA I2CB_SCL I2CB_SDA I2CC_SCL I2CC_SDA R4 R5 PEX_RST_N PEX_TERMP VID_PLLVDD XTAL_IN XTAL_OUT XTAL_OUTBUFF XTAL_SSIN C VGA_CRT_CLK VGA_CRT_DATA R7 R6 I2CB_SCL I2CB_SDA R2 R3 VGA_EDID_CLK VGA_EDID_DATA T4 T3 +1.05VS_VGA VGA_SMB_CK2 VGA_SMB_DA2 60mA PEX_TSTCLK_OUT PEX_TSTCLK_OUT_N 1 N13P@ 2 RV49 10K_0402_5% 1 N13P@ 2 RV3 2.2K_0402_5% 1 N13P@ 2 RV4 2.2K_0402_5% 1 N13P@ 2 RV10 2.2K_0402_5% 1 N13P@ 2 RV11 2.2K_0402_5% 1 N13P@ 2 RV12 2.2K_0402_5% 1 N13P@ 2 RV13 2.2K_0402_5% 1 N13P@ 2 RV1 10K_0402_5% 1 N13P@ 2 RV2 10K_0402_5% GC6_EVENT#_R AD8 AE8 AD7 30 ohms @100MHz (ESR=0.05) 2 RV112 1 @ 0_0402_5% 45mA 45mA H3 H2 XTALIN_R XTAL_OUT J4 H1 XTALOUT XTALSSIN 1 2 1 2 +SP_PLLVDD N13P@ 1 2 RV230 0_0402_5% 1 2 RV231 0_0402_5% GCLK274@ RV26 10K_0402_5% N13P@ N13P-PES-A1_FCBGA908 LV7 1 2 FBMA-10-100505-300T 0402 N13P@ +PLLVDD Near GPU B XTALIN GCLK_27MHZ GCLK_27MHZ <36> Under GPU RV27 10K_0402_5% N13P@ 1 2 RV22 2.49K_0402_1% N13P@ QV7B DMN66D0LDW-7 2N_SOT363-6 N13P@ 5 if GC6 is supported, stuff the BOM option to pull high to 3.3vs system power, if not, stuff the BOM option to pull high to NV3V3; 2 RV18 100K_0402_5% N13P@ <54> VGA_GPIO15 100K_0402_5% 1 VGA_GPIO16 0_0402_5% 1 2 3 N13P@ UV2 NC7SZ08P5X_NL_SC70-5 <54> GPU_VID5 OVERT# SP_PLLVDD AJ12 AP29 GPU_VID0 <54> QV7A DMN66D0LDW-7 2N_SOT363-6 N13P@ 2 I2CB_SDA I2CS_SCL I2CS_SDA PEX_REFCLK PEX_REFCLK_N PEX_CLKREQ_N AJ26 AK26 GPU_VID0 VGA_GPIO12 GPU_VID5 1 A 1 2 @ RV20 200_0402_1% 4 DACA_HSYNC DACA_VSYNC PEX_WAKE_N AL13 AK13 AK12 <54> <54> OVERT# GC6_EVENT#_R 1 1 <18> DGPU_HOLD_RST# B P 2 PLT_RST# CLK_PCIE_VGA CLK_PCIE_VGA# CLK_REQ_GPU# G <18,36,37,42,45> 1 5 @ RV105 10K_0402_5% GPU_VID1 GPU_VID2 DPRSLPVR_VGA <19> +3VS_VGA DACA_RED DACA_GREEN DACA_BLUE PLLVDD AJ11 B GPU_VID1 GPU_VID2 2DPRSLPVR_VGA @ RV113 N13P@ CV40 2N7002DW-T/R7_SOT363-6 N13P@ CV6 N13P@ 1 CV7 N13P@ 1 CV8 N13P@ 1 CV9 N13P@ 1 CV10 N13P@1 CV11 N13P@1 CV12 N13P@1 CV13 N13P@1 CV15 N13P@1 CV17 N13P@1 CV19 N13P@1 CV14 N13P@1 CV16 N13P@1 CV18 N13P@1 CV20 N13P@1 CV22 N13P@1 CV24 N13P@1 CV26 N13P@1 CV21 N13P@1 CV23 N13P@1 CV25 N13P@1 CV27 N13P@1 CV29 N13P@1 CV31 N13P@1 CV33 N13P@1 CV28 N13P@1 CV30 N13P@1 CV32 N13P@1 CV36 N13P@1 CV41 N13P@1 CV34 N13P@1 CV35 N13P@1 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_P15 PCIE_CRX_GTX_N15 VGA_GPIO3 0_0402_5% 1 RV208 10K_0402_5% N13P@ <54> <54> N13P@ CV131 EC_SMB_CK2 <15,39,42> GPU_VID4 GPU_VID3 22U_0805_6.3V6M QV1B 3 4 VGA_SMB_CK2 GPU_VID4 GPU_VID3 .1U_0402_16V7K 5 12/07 update to SE124224K80 1 1 RV25 2.2K_0402_5% N13P@ P6 M3 L6 P5 P7 L7 M7 N8 M1 M2 L1 M5 N3 M4 N4 P2 R8 M6 R1 P3 P4 P1 1 2 2 +3VS_VGA RV24 2.2K_0402_5% N13P@ GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 2 +3VS_VGA Part 1 of 7 GPIO D PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N DACs PCIE_CRX_GTX_P[0..15] <5> PCIE_CRX_GTX_P[0..15] AN12 AM12 AN14 AM14 AP14 AP15 AN15 AM15 AN17 AM17 AP17 AP18 AN18 AM18 AN20 AM20 AP20 AP21 AN21 AM21 AN23 AM23 AP23 AP24 AN24 AM24 AN26 AM26 AP26 AP27 AN27 AM27 I2C PCIE_CRX_GTX_N[0..15] <5> PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_P15 PCIE_CTX_GRX_N15 CLK PCIE_CTX_GRX_P[0..15] <5> PCIE_CTX_GRX_P[0..15] PCI EXPRESS <5> PCIE_CTX_GRX_N[0..15] PCH_THRMTRIP#_R 1 N13P@ U65A PCIE_CTX_GRX_N[0..15] 1 2 RV23 10M_0402_5% 1 2 2 N13P@ CV5 2 N13P@ CV4 2 1 A @ 2 0_0402_5% @ RV32 10K_0402_5% Compal Secret Data Security Classification Issued Date 2011/10/27 2012/10/27 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 2 1 .1U_0402_16V7K CV38 18P_0402_50V8J N13P@ .1U_0402_16V7K 1 1 N13P@ CV113 180ohms (ESR=0.2) Bead 27MHZ 16PF +-30PPM X3G027000FG1H-HX CV37 N13P@ 18P_0402_50V8J N13P@ 1 4.7U_0402_6.3V6M 2 +SP_PLLVDD LV1 BLM18PG330SN1D_0603 2 QV2 N13P@ 2N7002H 1N_SOT23-3 1 RV110 NC +1.05VS_VGA XTAL_OUT CLK_REQ_GPU# 1 D 3 2 OSC 3 N13P@ CV112 RV30 10K_0402_5% N13P@ 1 OSC 2 S 1 <15> CLK_REQ_VGA# 1 2 1 XTALIN 2 G RV29 10K_0402_5% N13P@ CV42 2 1 N13P@ .1U_0402_16V7K NC 1 22U_0805_6.3V6M 2 4 150mA N13P@ YV1 +3VS_VGA A Under GPU(below 150mils) N13P@ <18,25> DGPU_PWR_EN 4 3 2 Compal Electronics, Inc. N13X-PCIE/DAC/GPIO Document Number Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet 1 23 of 60 5 4 3 2 1 U65D Part 4 of 7 IFPB_TXC IFPB_TXC_N IFPB_TXD4 IFPB_TXD4_N IFPB_TXD5 IFPB_TXD5_N IFPB_TXD6 IFPB_TXD6_N IFPB_TXD7 IFPB_TXD7_N VDD_SENSE AM1 AM2 AM3 AM4 AL3 AL4 AK4 AK5 C AD2 AD3 AD1 AC1 AC2 AC3 AC4 AC5 AE3 AE4 AF4 AF5 AD4 AD5 AG1 AF1 IFPC_L0 IFPC_L0_N IFPC_L1 IFPC_L1_N IFPC_L2 IFPC_L2_N IFPC_L3 IFPC_L3_N IFPD_L0 IFPD_L0_N IFPD_L1 IFPD_L1_N IFPD_L2 IFPD_L2_N IFPD_L3 IFPD_L3_N IFPE_L0 IFPE_L0_N IFPE_L1 IFPE_L1_N IFPE_L2 IFPE_L2_N IFPE_L3 IFPE_L3_N IFPF_L0 IFPF_L0_N IFPF_L1 IFPF_L1_N IFPF_L2 IFPF_L2_N IFPF_L3 IFPF_L3_N GND_SENSE B AK3 AK2 AB3 AB4 AF3 AF2 L4 VCCSENSE_VGA VCCSENSE_VGA L5 VSSSENSE_VGA VSSSENSE_VGA <54> <54> TEST TESTMODE JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N AK11 AM10 AM11 AP12 AP11 AN11 TESTMODE 1 RV34 TV2 TV3 TV4 TV5 2 10K_0402_5% 10K_0402_5% RV33 N13P@ C N13P@ SERIAL ROM_CS_N ROM_SCLK ROM_SI ROM_SO H6 H4 H5 H7 BUFRST_N CEC IFPC_AUX_I2CW _SCL IFPC_AUX_I2CW _SDA_N STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 IFPD_AUX_I2CX_SCL IFPD_AUX_I2CX_SDA_N IFPE_AUX_I2CY_SCL IFPE_AUX_I2CY_SDA_N THERMDP THERMDN ROM_CS ROM_SCLK ROM_SI ROM_SO ROM_SCLK <32> ROM_SI <32> ROM_SO <32> +3VS_VGA GENERAL MULTI_STRAP_REF0_GND AG3 AG2 D trace width: 16mils differential voltage sensing. differential signal routing. LVDS/TMDS AK1 AJ1 AJ3 AJ2 AH3 AH4 AG5 AG4 P8 AC6 AJ28 AJ4 AJ5 AL11 C15 D19 D20 D23 D26 H31 T8 V32 1 AJ9 AH9 AP6 AP5 AM7 AL7 AN8 AM8 AK8 AL8 NC NC NC NC NC NC NC NC NC NC NC NC NC NC 2 D IFPA_TXC IFPA_TXC_N IFPA_TXD0 IFPA_TXD0_N IFPA_TXD1 IFPA_TXD1_N IFPA_TXD2 IFPA_TXD2_N IFPA_TXD3 IFPA_TXD3_N NC AM6 AN6 AP3 AN3 AN5 AM5 AL6 AK6 AJ6 AH6 RV35 L2 L3 J1 10K_0402_5% 1 RV232 N13P@ 2 NV_CEC 2 10K_0402_5% 1 N13P@ 1 N13P@ 2 RV38 40.2K_0402_1% J2 J7 J6 J5 J3 STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 <32> <32> <32> <32> <32> B K3 K4 IFPF_AUX_I2CZ_SCL IFPF_AUX_I2CZ_SDA_N Reserve 1MB SPI ROM FOR VBIOS ROM +3VS_VGA CV295 2 20mils 1 1 N13P@ 0.1U_0402_16V4Z @ ROM_CS ROM_SO 0_0402_5% 2 ROM_CS_R 2 ROM_SO_R 0_0402_5% @ UV15 1 2 3 4 CS# DO W P# GND @ VCC HOLD# CLK DIO 8 7 6 5 MX25L1005AMC-12G SOP A Compal Secret Data Security Classification 2011/10/27 Issued Date Deciphered Date 2012/10/27 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 RV225 10K_0402_5% 2 RV229 @ 10K_0402_5% 2 @ RV224 @RV224 1 1 @RV226 @ RV226 1 N13P-PES-A1_FCBGA908 ROM_HOLD# @ RV228 ROM_SCLK_R 1 1 ROM_SI_R @ RV227 0_0402_5% 2 ROM_SCLK 2 ROM_SI 0_0402_5% A Compal Electronics, Inc. N13X-LVDS/HDMI/DP/THM Document Number Rev 0.3 LA-7983P Sheet Thursday, January 05, 2012 1 24 of 60 3 U65E FB_VSS_SENSE +1.5VS_VGA CALIBRATION PIN DDR3 RV6 FB_CAL_x_PD_VDDQ 40.2Ohm RV8 2 N13P@ 40.2_0402_1% 1 FB_CAL_xTERM_GND RV9 42.2Ohm J27 2 42.2_0402_1% H27 2 N13P@ 51.1_0402_1% H25 N13P@ 1 FB_CAL_x_PU_GND CV52 CV51 10U_0603_6.3V6M CV50 10U_0603_6.3V6M CV49 10U_0603_6.3V6M CV48 10U_0603_6.3V6M CV55 CV56 22U_0805_6.3V6M CV53 22U_0805_6.3V6M CV47 CV46 CV45 1U_0402_6.3V6K CV44 1U_0402_6.3V6K 1U_0402_6.3V6K CV43 CV54 22U_0805_6.3V6M 2 N13P@ Under GPU(below 150mils) IFPA_IOVDD IFPB_IOVDD FB_GND_SENSE IFPC_IOVDD FB_CAL_PD_VDDQ IFPD_PLLVDD IFPD_RSET FB_CAL_PU_GND IFPD_IOVDD IFPE_IOVDD IFPF_IOVDD 2 N13P@ 1 2 N13P@ +3VS_VGA Place near balls AH8 +IFPAB_PLLVDD1 AJ8 RV48 1 120mA +PEX_PLLVDD Place near GPU RV5 2 +VDD33 N13P@ RV40 2 10K_0402_5% 2 1K_0402_1% @ AG8 +IFPAB_IOVDD 1 RV65 2 10K_0402_5% AG9 N13P@ AF7 AF8 +IFPC_PLLVDD 1 RV43 2 N13P@ RV42 2 10K_0402_5% 1 1K_0402_1% @ AF6 +IFPC_IOVDD 1 RV44 2 10K_0402_5% 1 2 N13P@ 1 2 N13P@ 1 2 1 +1.05VS_VGA LV2 N13P@ 2 1 Place near balls +PEX_PLLVDD J8 K8 L8 M8 1 1 2 N13P@ 1 2 N13P@ 1 C BLM18PG121SN1D_0603 120ohms @100MHz (ESR=0.18) 2 N13P@ 0_0603_5% Place near balls 2 N13P@ +VDD33 N13P@ 1 2 1 2 Inc 2pcs 0.1u following DG N13P@ RV45 2 10K_0402_5% 2 1K_0402_1% @ N13P@ AG6 +IFPD_IOVDD 1 RV47 2 10K_0402_5% AG7 +IFPD_PLLVDD 1 AN2 RV46 1 FB_CAL_TERM_GND Place near balls 2 N13P@ 1 CV66 AG26 1 4.7U_0603_6.3V6K +PEX_SVDD3V3 FB_VDDQ_SENSE IFPC_PLLVDD IFPC_RSET 2 0_0402_5% CV3 AG12 RV138 1 @ CV73 +PEX_PLLHVDD 1U_0402_6.3V6K VDD33_0 VDD33_1 VDD33_2 VDD33_3 AH12 CV65 PEX_PLLVDD IFPEF_PLVDD IFPEF_RSET 51.1Ohm N13P@ +1.05VS_VGA 1 .1U_0402_16V7K PEX_SVDD_3V3 IFPAB_PLLVDD IFPAB_RSET F2 1 1 +3VS_VGA PEX_PLL_HVDD FB_VDDQ_SENSE F1 1 D 2 N13P@ CV304 2 RV141 @1 10_0402_5% @ 2 RV142 1 10_0402_5% N13P@ 1 N13P@ 2 CV303 .1U_0402_16V7K +1.5VS_VGA N13P@ 2 1 N13P@ 2 N13P@ N13P@ .1U_0402_16V7K C N13P@ 2 1 4.7U_0603_6.3V6K rise 1.5v system source voltage to 1.55-1.57V 2 1 2 CV75 N13P@ 1 2 N13P@ CV293 4.7U_0603_6.3V6K N13P@ 1U_0402_6.3V6K CV272 2 Under GPU(below 150mils) 2 N13P@ 1 CV74 N13P@ 1 CV286 CV285 2 2 N13P@ 1 CV70 N13P@ 1 2 N13P@ 1 4.7U_0603_6.3V6K 2 2 N13P@ 1 CV111 N13P@ 1 CV284 CV294 2 2 N13P@ 1 .1U_0402_16V7K N13P@ 1 AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27 AJ27 AK27 AL27 AM28 AN28 1 CV109 .1U_0402_16V7K 2 PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 +1.05VS_VGA .1U_0402_16V7K N13P@ 1 CV287 CV292 2 1 N13P@ N13P@ .1U_0402_16V7K N13P@ 1 .1U_0402_16V7K 2 .1U_0402_16V7K N13P@ 1 CV280 CV279 2 N13P@ 1 0.1uF X7R 0402 * 8 .1U_0402_16V7K N13P@ 1 .1U_0402_16V7K 2 .1U_0402_16V7K N13P@ 1 CV278 CV277 2 .1U_0402_16V7K N13P@ 1 .1U_0402_16V7K 2 1U_0402_6.3V6K CV268 1 1U_0402_6.3V6K CV267 2 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K Under GPU(below 150mils) 1uF X7R 0402 * 2 1 2 PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 AG19 AG21 AG22 AG24 AH21 AH25 22U_0805_6.3V6M N13P@ 4.7uF X7R 0402 * 2 1 1 2 FBVDDQ_0 FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 FBVDDQ_38 FBVDDQ_39 FBVDDQ_40 FBVDDQ_41 FBVDDQ_42 FBVDDQ_43 POWER @ 2 CV271 10U_0603_6.3V6M 2 2 AA27 AA30 AB27 AB33 AC27 AD27 AE27 AF27 AG27 B13 B16 B19 E13 E16 E19 H10 H11 H12 H13 H14 H15 H16 H18 H19 H20 H21 H22 H23 H24 H8 H9 L27 M27 N27 P27 R27 T27 T30 T33 V27 W27 W30 W33 Y27 Near GPU 2000mA Part 5 of 7 3.5A CV270 10U_0603_6.3V6M 1 CV269 10U_0603_6.3V6M +1.5VS_VGA CV273 22U_0805_6.3V6M D 10U_0603_6.3V6M Near GPU 1 1U_0402_6.3V6K +1.5VS_VGA 2 4.7U_0603_6.3V6K 4 4.7U_0603_6.3V6K 5 N13P@ RV72 2 10K_0402_5% RV50 2 1K_0402_1% N13P@ N13P@ +IFPE_IOVDD1 RV73 2 10K_0402_5% AB8 +IFPEF_PLLVDD1 1 AD6 AC7 AC8 B B N13P@ +3VS to +3VS_VGA N13P-PES-A1_FCBGA908 N13P@ +3VS J10 1 1 +3VS_VGA @ 2 2 JUMP_43X79 +5VALW 1 1 2 2 2 N13P@ RV206 470_0603_5% @ D QV6 2 G @ 2 S 2N7002_SOT23 A @ Compal Secret Data Security Classification Issued Date 2011/10/27 2012/10/27 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 RV207 @ 1 DGPU_PWR_EN# 10K_0402_5% CV242 R1105 100K_0402_5% N13P@ 1 1 N13P@ 3 Q128 2N7002_SOT23 N13P@ 1 2 2 N13P@ CV241 S 2 G 0_0402_5% RV205 1 2 10K_0402_5% N13P@ .1U_0402_16V7K 2 1 1 D 3 <18,23> DGPU_PWR_EN 1 G DGPU_PWR_EN# R1104 2 CV57 10U_0603_6.3V6M D SUSP# S <10,42,46,51,52,53,54> 3 1 2 .1U_0402_16V7K 1 QV5 LP2301ALT1G_SOT23 N13P@ R1103 100K_0402_5% R1109 @ 0_0402_5% 2 1 A Compal Electronics, Inc. N13X-POWER Document Number Rev 0.3 LA-7983P Sheet Thursday, January 05, 2012 1 25 of 60 5 4 3 2 1 U65F C B A GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198 GND_199 GND_OPT GND_OPT D2 D31 D33 E10 E22 E25 E5 E7 F28 F7 G10 G13 G16 G19 G2 G22 G25 G28 G3 G30 G32 G33 G5 G7 K2 K28 K30 K32 K33 K5 K7 M13 M15 M17 M18 M20 M22 N12 N14 N16 N19 N2 N21 N23 N28 N30 N32 N33 N5 N7 P13 P15 P17 P18 P20 P22 R12 R14 R16 R19 R21 R23 T13 T15 T17 T18 T2 T20 T22 AG11 T28 T32 T5 T7 U12 U14 U16 U19 U21 U23 V12 V14 V16 V19 V21 V23 W 13 W 15 W 17 W 18 W 20 W 22 W 28 Y12 Y14 Y16 Y19 Y21 Y23 AH11 C16 W 32 Part 7 of 7 AA12 AA14 AA16 AA19 AA21 AA23 AB13 AB15 AB17 AB18 AB20 AB22 AC12 AC14 AC16 AC19 AC21 AC23 M12 M14 M16 M19 M21 M23 N13 N15 N17 N18 N20 N22 P12 P14 P16 P19 P21 P23 R13 R15 R17 R18 R20 R22 T12 T14 T16 T19 T21 T23 U13 U15 U17 U18 U20 U22 V13 V15 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 XVDD_9 XVDD_10 XVDD_11 XVDD_12 XVDD_13 XVDD_14 XVDD_15 XVDD_16 XVDD_17 XVDD_18 XVDD_19 XVDD_20 XVDD_21 XVDD_22 XVDD_23 XVDD_24 XVDD_25 XVDD_26 XVDD_27 XVDD_28 XVDD_29 XVDD_30 XVDD_31 XVDD_32 XVDD_33 XVDD_34 XVDD_35 XVDD_36 XVDD_37 XVDD_38 D U1 U2 U3 U4 U5 U6 U7 U8 V1 V2 V3 V4 V5 V6 V7 V8 C W2 W3 W4 W5 W7 W8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 B A Issued Date Compal Secret Data 2011/10/27 Deciphered Date 2012/10/27 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 4 XVDD_1 XVDD_2 XVDD_3 XVDD_4 XVDD_5 XVDD_6 XVDD_7 XVDD_8 V17 V18 V20 V22 W 12 W 14 W 16 W 19 W 21 W 23 Y13 Y15 Y17 Y18 Y20 Y22 N13P@ N13P@ 5 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 N13P-PES-A1_FCBGA908 Security Classification N13P-PES-A1_FCBGA908 +VGA_CORE U65G +VGA_CORE POWER D GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98 GND_99 GND Part 6 of 7 A2 AA17 AA18 AA20 AA22 AB12 AB14 AB16 AB19 AB2 AB21 A33 AB23 AB28 AB30 AB32 AB5 AB7 AC13 AC15 AC17 AC18 AA13 AC20 AC22 AE2 AE28 AE30 AE32 AE33 AE5 AE7 AH10 AA15 AH13 AH16 AH19 AH2 AH22 AH24 AH28 AH29 AH30 AH32 AH33 AH5 AH7 AJ7 AK10 AK7 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 AL24 AL26 AL28 AL30 AL32 AL33 AL5 AM13 AM16 AM19 AM22 AM25 AN1 AN10 AN13 AN16 AN19 AN22 AN25 AN30 AN34 AN4 AN7 AP2 AP33 B1 B10 B22 B25 B28 B31 B34 B4 B7 C10 C13 C19 C22 C25 C28 C7 3 2 Compal Electronics, Inc. N13-VGA CORE, GND Document Number Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet 1 26 of 60 5 <28,29> FBA_D[0..63] 4 3 FBA_MA[15..0] FBA_D[0..63] 2 <28,29> FBC_D[0..63] <30,31> FBC_D[0..63] FBA_BA[2..0] 1 FBC_MA[15..0] <28,29> FBC_BA[2..0] <30,31> <30,31> U65C U65B Part 3 of 7 FBA_CAS# <28,29> FBA_CS0#_H <29> FBA_ODT_H FBA_CKE_H FBA_MA13 FBA_MA8 FBA_MA6 FBA_MA11 FBA_MA5 FBA_MA3 FBA_BA2 FBA_BA1 FBA_MA12 FBA_MA10 FBA_RAS# FBA_ODT_H <29> FBA_CKE_H <29> FBA_RAS# <28,29> +1.5VS_VGA RV58 RV59 1 1 @ @ 2 60.4_0402_1% 2 60.4_0402_1% can be unstuff by default R30 R31 AB31 AC31 FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1# FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1# <28> <28> <29> <29> K31 L30 H34 J34 AG30 AG31 AJ34 AK34 +FB_PLLAVDD Place close to BGA FB_CLAMP FB_DLL_AVDD J30 J31 J32 J33 AH31 AJ31 AJ32 AJ33 E1 200mA BLM18PG330SN1D_0603 1 2 +FB_PLLAVDD LV3 N13P@ FB_CLAMP RV66 2 @ 10K_0402_5% 1 +FB_PLLAVDD K27 CV106 1 .1U_0402_16V7K 2 N13P@ Place close to ball FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7 FB_VREF U27 H26 1 2 N13P@ Place close to ball 1 2 N13P@ +FB_PLLAVDD 1 2 N13P@ FBC_DQM0 FBC_DQM1 FBC_DQM2 FBC_DQM3 FBC_DQM4 FBC_DQM5 FBC_DQM6 FBC_DQM7 E11 E3 A3 C9 F23 F27 C30 A24 FBC_DQS0 FBC_DQS1 FBC_DQS2 FBC_DQS3 FBC_DQS4 FBC_DQS5 FBC_DQS6 FBC_DQS7 D10 D5 C3 B9 E23 E28 B30 A23 FBC_DQS#0 FBC_DQS#1 FBC_DQS#2 FBC_DQS#3 FBC_DQS#4 FBC_DQS#5 FBC_DQS#6 FBC_DQS#7 D9 E4 B2 A9 D22 D28 A30 B23 FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31 MEMORY INTERFACE B FBA_WE# <28,29> +1.05VS_VGA FBA_WCKB01 FBA_WCKB01_N FBA_WCKB23 FBA_WCKB23_N FBA_WCKB45 FBA_WCKB45_N FBA_WCKB67 FBA_WCKB67_N FBA_PLL_AVDD M30 FBA_DQS#0 H30 FBA_DQS#1 E34 FBA_DQS#2 M34 FBA_DQS#3 FBA_DQS#4 AF30 FBA_DQS#5 AK31 FBA_DQS#6 AM34 FBA_DQS#7 AF32 FBA_RST# <28,29> FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63 FBB_CMD_RFU0 FBB_CMD_RFU1 A <28,29> FBA_DQM[7..0] <28,29> FBA_DQS[7..0] <28,29> FBA_DQS#[7..0] FBC_CS0#_L FBC_CS0#_L FBC_ODT_L FBC_CKE_L FBC_MA14 FBC_RST# FBC_MA9 FBC_MA7 FBC_MA2 FBC_MA0 FBC_MA4 FBC_MA1 FBC_BA0 FBC_WE# FBC_MA15 FBC_CAS# FBC_CS0#_H <30> FBC_ODT_L <30> FBC_CKE_L <30> FBC_RST# <30,31> FBB_DEBUG0 FBB_DEBUG1 FBB_CLK0 FBB_CLK0_N FBB_CLK1 FBB_CLK1_N FBB_WCK01 FBB_WCK01_N FBB_WCK23 FBB_WCK23_N FBB_WCK45 FBB_WCK45_N FBB_WCK67 FBB_WCK67_N FBB_WCKB01 FBB_WCKB01_N FBB_WCKB23 FBB_WCKB23_N FBB_WCKB45 FBB_WCKB45_N FBB_WCKB67 FBB_WCKB67_N FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7 FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7 FBB_PLL_AVDD D FBC_WE# <30,31> FBC_CAS# <30,31> FBC_CS0#_H <31> FBC_ODT_H FBC_CKE_H FBC_MA13 FBC_MA8 FBC_MA6 FBC_MA11 FBC_MA5 FBC_MA3 FBC_BA2 FBC_BA1 FBC_MA12 FBC_MA10 FBC_RAS# FBC_ODT_H FBC_CKE_H <31> <31> Mode D - Mirror Mode Mapping DATA Bus FBC_RAS# <30,31> Address RV60 1 RV61 1 @ @ 2 60.4_0402_1% 2 60.4_0402_1% can be unstuff by default D12 E12 E20 F20 FBC_CLK0 FBC_CLK0# FBC_CLK1 FBC_CLK1# FBC_CLK0 <30> FBC_CLK0# <30> FBC_CLK1 <31> FBC_CLK1# <31> F8 E8 A5 A6 D24 D25 B27 C27 D6 D7 C6 B6 F26 E26 A26 A27 FBx_CMD2 ODT_L FBx_CMD3 CKE_L FBx_CMD4 A14 A14 FBx_CMD5 RST RST FBx_CMD6 A9 A9 FBx_CMD7 A7 A7 FBx_CMD8 A2 A2 FBx_CMD9 A0 A0 FBx_CMD10 A4 A4 FBx_CMD11 A1 A1 FBx_CMD12 BA0 BA0 FBx_CMD13 WE# WE# FBx_CMD14 A15 A15 FBx_CMD15 CAS# CAS# CS0#_H FBx_CMD17 ODT_H FBx_CMD18 +FB_PLLAVDD 1 2 N13P@ Place close to ball B CKE_H FBx_CMD19 FBx_CMD20 A13 A13 FBx_CMD21 A8 A8 FBx_CMD22 A6 A6 FBx_CMD23 A11 A11 FBx_CMD24 A5 A5 FBx_CMD25 A3 A3 FBx_CMD26 BA2 BA2 FBx_CMD27 BA1 BA1 FBx_CMD28 A12 A12 FBx_CMD29 A10 A10 FBx_CMD30 RAS# RAS# Place close to BGA N13P@ N13P@ 30ohms (ESR=0.01) Bead P/N;SM010007W00 <30,31> FBC_DQM[7..0] <30,31> FBC_DQS[7..0] <30,31> FBC_DQS#[7..0] A Compal Secret Data Security Classification Issued Date 2011/10/27 2012/10/27 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 C FBx_CMD16 H17 FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3 FBB_DQS_RN4 FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7 CS0#_L FBx_CMD1 C12 C20 G14 G20 32..63 0..31 FBx_CMD0 +1.5VS_VGA N13P-PES-A1_FCBGA908 N13P-PES-A1_FCBGA908 D13 E14 F14 A12 B12 C14 B14 G15 F15 E15 D15 A14 D14 A15 B15 C17 D18 E18 F18 A20 B20 C18 B18 G18 G17 F17 D16 A18 D17 A17 B17 E17 CV108 FBA_WCK01 FBA_WCK01_N FBA_WCK23 FBA_WCK23_N FBA_WCK45 FBA_WCK45_N FBA_WCK67 FBA_WCK67_N FBA_ODT_L <28> FBA_CKE_L <28> G9 E9 G8 F9 F11 G11 F12 G12 G6 F5 E6 F6 F4 G4 E2 F3 C2 D4 D3 C1 B3 C4 B5 C5 A11 C11 D11 B11 D8 A8 C8 B8 F24 G23 E24 G24 D21 E21 G21 F21 G27 D27 G26 E27 E29 F29 E30 D30 A32 C31 C32 B32 D29 A29 C29 B29 B21 C23 A21 C21 B24 C24 B26 C26 .1U_0402_16V7K FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 FBA_CLK0 FBA_CLK0_N FBA_CLK1 FBA_CLK1_N FBA_ODT_L FBA_CKE_L FBA_MA14 FBA_RST# FBA_MA9 FBA_MA7 FBA_MA2 FBA_MA0 FBA_MA4 FBA_MA1 FBA_BA0 FBA_WE# FBA_MA15 FBA_CAS# FBA_CS0#_H R32 AC32 R28 AC28 FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 FBC_D8 FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63 FBA_CS0#_L <28> CV39 M31 G31 E33 M33 AE31 AK30 AN33 AF33 FBA_DEBUG0 FBA_DEBUG1 FBA_CS0#_L CV110 FBA_DQS0 FBA_DQS1 FBA_DQS2 FBA_DQS3 FBA_DQS4 FBA_DQS5 FBA_DQS6 FBA_DQS7 FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 FBA_CMD_RFU0 FBA_CMD_RFU1 U30 T31 U29 R34 R33 U32 U33 U28 V28 V29 V30 U34 U31 V34 V33 Y32 AA31 AA29 AA28 AC34 AC33 AA32 AA33 Y28 Y29 W31 Y30 AA34 Y31 Y34 Y33 V31 22U_0805_6.3V6M P30 F31 F34 M32 AD31 AL29 AM32 AF34 FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31 CV107 B FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 1U_0402_6.3V6K C L28 M29 L29 M28 N31 P29 R29 P28 J28 H29 J29 H28 G29 E31 E32 F30 C34 D32 B33 C33 F33 F32 H33 H32 P34 P32 P31 P33 L31 L34 L32 L33 AG28 AF29 AG29 AF28 AD30 AD29 AC29 AD28 AJ29 AK29 AJ30 AK28 AM29 AM31 AN29 AM30 AN31 AN32 AP30 AP32 AM33 AL31 AK33 AK32 AD34 AD32 AC30 AD33 AF31 AG34 AG32 AG33 .1U_0402_16V7K D FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 MEMORY INTERFACE A Part 2 of 7 4 3 2 Compal Electronics, Inc. N13X-MEM Interface Document Number Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet 1 27 of 60 5 4 3 2 1 FBA_D[0..63] Memory Partition A - Lower 32 bits <27,29> FBA_MA[15..0] <27,29> FBA_BA[2..0] <27,29> UV3 +1.5VS_VGA +FBA_VREF0 1 D FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14 FBA_MA15 RV79 2 1.1K_0402_1% N13P@ RV68 2 1.1K_0402_1% N13P@ 1 CV118 0.01U_0402_16V7K 1 +FBA_VREF0 2 N13P@ FBA_BA0 FBA_BA1 FBA_BA2 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 M2 N8 M3 VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 RV80 160_0402_1% N13P@ FBA_CLK0 FBA_CLK0# FBA_CKE_L J7 K7 K9 FBA_ODT_L FBA_CS0#_L FBA_RAS# FBA_CAS# FBA_WE# K1 L2 J3 K3 L3 FBA_D4 FBA_D1 FBA_D7 FBA_D0 FBA_D6 FBA_D3 FBA_D5 FBA_D2 D7 C3 C8 C2 A7 A2 B8 A3 FBA_D29 FBA_D25 FBA_D28 FBA_D26 FBA_D31 FBA_D24 FBA_D30 FBA_D27 BA0 BA1 BA2 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 M8 H1 +FBA_VREF0 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14 FBA_MA15 Group0 (IN3) Group3 (BOT) B2 D9 G7 K2 K8 N1 N9 R1 R9 FBA_BA0 FBA_BA1 FBA_BA2 FBA_CLK0 FBA_CLK0# FBA_CKE_L J7 K7 K9 A1 A8 C1 C9 D2 E9 F1 H2 H9 FBA_ODT_L FBA_CS0#_L FBA_RAS# FBA_CAS# FBA_WE# K1 L2 J3 K3 L3 FBA_DQS2 FBA_DQS1 F3 C7 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 FBA_DQM2 FBA_DQM1 E7 D3 FBA_DQM[7..0] <27,29> VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 M2 N8 M3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 FBA_D19 FBA_D20 FBA_D17 FBA_D21 FBA_D16 FBA_D23 FBA_D18 FBA_D22 D7 C3 C8 C2 A7 A2 B8 A3 FBA_D10 FBA_D15 FBA_D8 FBA_D13 FBA_D9 FBA_D12 FBA_D11 FBA_D14 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 0..31 FBx_CMD1 B2 D9 G7 K2 K8 N1 N9 R1 R9 F3 C7 FBA_DQM0 FBA_DQM3 E7 D3 FBA_DQS#0 G3 FBA_DQS#3 B7 FBA_RST# <27,29> FBA_RST# T2 L8 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 ODT/ODT0 CS/CS0 RAS CAS WE DQSL DQSU DML DMU FBA_DQS#2 G3 FBA_DQS#1 B7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU T2 FBA_RST# VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ RESET L8 ZQ/ZQ0 A1 A8 C1 C9 D2 E9 F1 H2 H9 FBA_ODT_L FBA_CKE_L 2 FBA_DQS0 FBA_DQS3 ODT/ODT0 CS/CS0 RAS CAS WE RV67 10K_0402_5% N13P@ A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 RV76 10K_0402_5% N13P@ FBx_CMD2 ODT_L FBx_CMD3 CKE_L FBx_CMD4 A14 A14 FBx_CMD5 RST RST FBx_CMD6 A9 A9 FBx_CMD7 A7 A7 FBx_CMD8 A2 A2 FBx_CMD9 A0 A0 FBx_CMD10 A4 A4 FBx_CMD11 A1 A1 FBx_CMD12 BA0 BA0 FBx_CMD13 WE# WE# FBx_CMD14 A15 A15 FBx_CMD15 CAS# 1 J1 L1 J9 L9 RV69 243_0402_1% N13P@ 96-BALL SDRAM DDR3 K4W1G1646E-HC12_FBGA96 X76@ FBx_CMD20 B1 B9 D1 D8 E2 E8 F9 G1 G9 2 @ 2 N13P@ 2 @ 2 @ 2011/10/27 Deciphered Date 2012/10/27 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 1 A13 A13 FBx_CMD21 A8 A8 FBx_CMD22 A6 A6 FBx_CMD23 A11 A11 FBx_CMD24 A5 A5 FBx_CMD25 A3 A3 FBx_CMD26 BA2 BA2 FBx_CMD27 BA1 BA1 FBx_CMD28 A12 A12 FBx_CMD29 A10 A10 FBx_CMD30 RAS# RAS# B CV158 1 CV144 1U_0402_6.3V6K @ 1 CV143 1U_0402_6.3V6K 2 1 CV142 1U_0402_6.3V6K @ 1 CV138 1U_0402_6.3V6K 2 CV157 CV135 2 N13P@ 1 CV155 .1U_0402_16V7K 2 N13P@ 1 Compal Secret Data Security Classification Issued Date CV137 CV163 2 N13P@ 1 .1U_0402_16V7K @ 1 1U_0402_6.3V6K 2 1 1U_0402_6.3V6K 2 N13P@ 1 CV136 CV164 CV132 2 N13P@ 1 1U_0402_6.3V6K 2 N13P@ 1 CKE_H FBx_CMD19 UV4 SIDE .1U_0402_16V7K 2 2 2 2 N13P@ N13P@ N13P@ N13P@ 1 CV133 1U_0402_6.3V6K 1 CV160 1U_0402_6.3V6K 1 CV129 1U_0402_6.3V6K 1 CV134 1U_0402_6.3V6K @ 1 CV159 .1U_0402_16V7K 2 .1U_0402_16V7K 2 N13P@ 1 CV161 CV162 CV123 2 N13P@ 1 1U_0402_6.3V6K 2 N13P@ 1 1U_0402_6.3V6K CV121 1 .1U_0402_16V7K +1.5VS_VGA 1U_0402_6.3V6K 2 N13P@ 1U_0402_6.3V6K 2 N13P@ 1 CV120 CV119 1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ ODT_H FBx_CMD18 96-BALL SDRAM DDR3 K4W1G1646E-HC12_FBGA96 X76@ UV3 SIDE .1U_0402_16V7K A .1U_0402_16V7K +1.5VS_VGA NC/ODT1 NC/CS1 NC/CE1 NCZQ1 1U_0402_6.3V6K 2 B1 B9 D1 D8 E2 E8 F9 G1 G9 2 1 RV77 243_0402_1% N13P@ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 2 1 RV78 10K_0402_5% N13P@ NC/ODT1 NC/CS1 NC/CE1 NCZQ1 CS0#_H FBx_CMD17 B J1 L1 J9 L9 C CAS# FBx_CMD16 1 FBA_ODT_L FBA_CS0#_L FBA_RAS# FBA_CAS# FBA_WE# 32..63 CS0#_L FBx_CMD0 Group1 (TOP) 2 <27> <27> <27,29> <27,29> <27,29> <27,29> DATA Bus Address 1 FBA_CLK0# <27,29> Mode D - Mirror Mode Mapping +1.5VS_VGA BA0 BA1 BA2 FBA_DQS[7..0] FBA_DQS#[7..0] D Group2 (IN1) 1 C <27> FBA_CLK0 <27> FBA_CLK0# <27> FBA_CKE_L E3 F7 F2 F8 H3 H8 G2 H7 +1.5VS_VGA 2 FBA_CLK0 M8 H1 UV4 2 N13P@ A Compal Electronics, Inc. N13X-VRAM A Lower Document Number Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet 1 28 of 60 5 4 3 2 1 Memory Partition A - Upper 32 bits UV5 +1.5VS_VGA 1 +FBA_VREF1 RV70 D 2 1.1K_0402_1% N13P@ 2 1.1K_0402_1% N13P@ CV178 0.01U_0402_16V7K 1 +FBA_VREF1 RV82 FBA_D[0..63] 1 2 N13P@ FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14 FBA_MA15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 FBA_BA0 FBA_BA1 FBA_BA2 M2 N8 M3 RV83 160_0402_1% N13P@ FBA_CLK1 FBA_CLK1# FBA_CKE_H VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 FBA_D36 FBA_D34 FBA_D37 FBA_D35 FBA_D39 FBA_D32 FBA_D38 FBA_D33 D7 C3 C8 C2 A7 A2 B8 A3 FBA_D45 FBA_D42 FBA_D46 FBA_D41 FBA_D47 FBA_D43 FBA_D44 FBA_D40 Group4 (IN1) Group5 (TOP) +1.5VS_VGA BA0 BA1 BA2 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 M8 H1 +FBA_VREF1 B2 D9 G7 K2 K8 N1 N9 R1 R9 FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14 FBA_MA15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 FBA_BA0 FBA_BA1 FBA_BA2 M2 N8 M3 VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 FBA_D63 FBA_D58 FBA_D60 FBA_D59 FBA_D61 FBA_D56 FBA_D62 FBA_D57 D7 C3 C8 C2 A7 A2 B8 A3 FBA_D55 FBA_D51 FBA_D54 FBA_D49 FBA_D52 FBA_D50 FBA_D53 FBA_D48 FBA_BA[2..0] <27,28> Group7 (IN3) VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 FBA_DQS#4 G3 FBA_DQS#5 B7 DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU FBA_CKE_H FBA_RST# <27,28> FBA_RST# FBA_ODT_H T2 1 1 RV87 10K_0402_5% N13P@ J1 L1 J9 L9 RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 2 RV86 243_0402_1% N13P@ 2 RV84 10K_0402_5% N13P@ 2 B 1 L8 K1 L2 J3 K3 L3 FBA_DQS7 FBA_DQS6 F3 C7 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 FBA_DQM7 FBA_DQM6 E7 D3 B1 B9 D1 D8 E2 E8 F9 G1 G9 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 2 N13P@ 2 @ 1 2 CV173 CV179 1 1U_0402_6.3V6K 2 N13P@ CV172 CV166 CV170 @ 1 1U_0402_6.3V6K 2 1 1U_0402_6.3V6K 2 N13P@ 1 1U_0402_6.3V6K CV177 1 @ 1 2 @ <27,28> 2 0..31 32..63 CS0#_L FBx_CMD2 ODT_L FBx_CMD3 CKE_L FBx_CMD4 A14 A14 FBx_CMD5 RST RST FBx_CMD6 A9 A9 FBx_CMD7 A7 A7 FBx_CMD8 A2 A2 FBx_CMD9 A0 A0 FBx_CMD10 A4 A4 FBx_CMD11 A1 A1 FBx_CMD12 BA0 BA0 FBx_CMD13 WE# WE# FBx_CMD14 A15 A15 FBx_CMD15 CAS# C CAS# CS0#_H FBx_CMD17 ODT_H FBx_CMD18 CKE_H FBx_CMD19 B1 B9 D1 D8 E2 E8 F9 G1 G9 1 Address FBx_CMD16 UV6 SIDE .1U_0402_16V7K 2 N13P@ .1U_0402_16V7K 2 2 2 N13P@ N13P@ N13P@ 1 CV165 1 CV298 1U_0402_6.3V6K 1 CV297 1U_0402_6.3V6K 2 2 N13P@ N13P@ 1 CV300 1U_0402_6.3V6K 1 CV290 1U_0402_6.3V6K 1 CV299 .1U_0402_16V7K 2 N13P@ .1U_0402_16V7K 2 N13P@ 1 CV302 CV291 CV301 2 N13P@ 1 1U_0402_6.3V6K 2 N13P@ 1 1U_0402_6.3V6K CV296 1 ZQ/ZQ0 A1 A8 C1 C9 D2 E9 F1 H2 H9 96-BALL SDRAM DDR3 K4W1G1646E-HC12_FBGA96 X76@ +1.5VS_VGA 1U_0402_6.3V6K 2 N13P@ 1U_0402_6.3V6K CV174 CV145 2 N13P@ 1 RESET J1 L1 J9 L9 RV85 243_0402_1% N13P@ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU L8 UV5 SIDE .1U_0402_16V7K .1U_0402_16V7K 1 DML DMU T2 FBA_RST# VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU FBA_DQS#7 G3 FBA_DQS#6 B7 96-BALL SDRAM DDR3 K4W1G1646E-HC12_FBGA96 X76@ +1.5VS_VGA ODT/ODT0 CS/CS0 RAS CAS WE @ 1 1 2 2 N13P@ N13P@ 1 2 @ 1 2 CV175 E7 D3 FBA_ODT_H FBA_CS0#_H FBA_RAS# FBA_CAS# FBA_WE# FBA_DQS#[7..0] FBx_CMD1 CV168 1U_0402_6.3V6K FBA_DQM4 FBA_DQM5 DQSL DQSU A1 A8 C1 C9 D2 E9 F1 H2 H9 <27,28> D FBx_CMD0 CV171 1U_0402_6.3V6K F3 C7 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ CV167 1U_0402_6.3V6K FBA_DQS4 FBA_DQS5 ODT/ODT0 CS/CS0 RAS CAS WE <27,28> FBA_DQS[7..0] DATA Bus Group6 (BOT) B2 D9 G7 K2 K8 N1 N9 R1 R9 CV180 1U_0402_6.3V6K K1 L2 J3 K3 L3 CV169 .1U_0402_16V7K FBA_ODT_H FBA_CS0#_H FBA_RAS# FBA_CAS# FBA_WE# FBA_ODT_H FBA_CS0#_H FBA_RAS# FBA_CAS# FBA_WE# .1U_0402_16V7K <27> <27> <27,28> <27,28> <27,28> 1 FBA_CLK1# 2 C FBA_DQM[7..0] Mode D - Mirror Mode Mapping +1.5VS_VGA BA0 BA1 BA2 J7 FBA_CLK1 FBA_CLK1# K7 FBA_CKE_H K9 E3 F7 F2 F8 H3 H8 G2 H7 1 <27> FBA_CLK1 <27> FBA_CLK1# <27> FBA_CKE_H J7 K7 K9 FBA_MA[15..0] <27,28> UV6 2 FBA_CLK1 M8 H1 <27,28> FBx_CMD20 A13 FBx_CMD21 A8 A8 FBx_CMD22 A6 A6 FBx_CMD23 A11 A11 FBx_CMD24 A5 A5 FBx_CMD25 A3 A3 FBx_CMD26 BA2 BA2 FBx_CMD27 BA1 BA1 FBx_CMD28 A12 A12 FBx_CMD29 A10 A10 FBx_CMD30 RAS# RAS# A13 B @ A A Compal Secret Data Security Classification Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Compal Electronics, Inc. N13X-VRAM A Upper Document Number Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet 1 29 of 60 5 4 3 2 1 FBC_D[0..63] Memory Partition C - Lower 32 bits <27,31> FBC_MA[15..0] <27,31> FBC_BA[2..0] +1.5VS_VGA UV7 M8 H1 +FBB_VREF0 1 D RV111 2 1.1K_0402_1% N13P@ RV115 2 1.1K_0402_1% N13P@ 1 CV202 0.01U_0402_16V7K 1 +FBB_VREF0 2 N13P@ N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 FBC_BA0 FBC_BA1 FBC_BA2 M2 N8 M3 RV89 160_0402_1% N13P@ FBC_CLK0 FBC_CLK0# FBC_CKE_L J7 K7 K9 <27> FBC_CLK0 <27> FBC_CLK0# <27> FBC_CKE_L DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 FBC_D4 FBC_D3 FBC_D7 FBC_D0 FBC_D5 FBC_D1 FBC_D6 FBC_D2 D7 C3 C8 C2 A7 A2 B8 A3 FBC_D28 FBC_D27 FBC_D31 FBC_D25 FBC_D29 FBC_D24 FBC_D30 FBC_D26 M8 H1 +FBB_VREF0 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 Group0 (IN3)FBC_MA0 Group3 VREFCA VREFDQ FBC_MA1 FBC_MA2 FBC_MA3 FBC_MA4 FBC_MA5 FBC_MA6 FBC_MA7 FBC_MA8 FBC_MA9 FBC_MA10 (BOT)FBC_MA11 FBC_MA12 FBC_MA13 FBC_MA14 FBC_MA15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 +1.5VS_VGA BA0 BA1 BA2 310mA CK CK CKE/CKE0 VDD VDD VDD VDD VDD VDD VDD VDD VDD B2 D9 G7 K2 K8 N1 N9 R1 R9 M2 N8 M3 FBC_BA0 FBC_BA1 FBC_BA2 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 FBC_CLK0# <27> <27> <27,31> <27,31> <27,31> FBC_ODT_L FBC_CS0#_L FBC_RAS# FBC_CAS# FBC_WE# FBC_ODT_L FBC_CS0#_L FBC_RAS# FBC_CAS# FBC_WE# K1 L2 J3 K3 L3 FBC_DQS0 FBC_DQS3 F3 C7 FBC_DQM0 FBC_DQM3 E7 D3 FBC_D16 FBC_D21 FBC_D18 FBC_D17 FBC_D20 FBC_D23 FBC_D19 FBC_D22 T2 FBC_RST# <27,31> FBC_RST# L8 D7 C3 C8 C2 A7 A2 B8 A3 FBC_D8 FBC_D15 FBC_D11 FBC_D12 FBC_D9 FBC_D13 FBC_D10 FBC_D14 Group2 (IN1) Address CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU A1 A8 C1 C9 D2 E9 F1 H2 H9 FBC_ODT_L FBC_CS0#_L FBC_RAS# FBC_CAS# FBC_WE# K1 L2 J3 K3 L3 FBC_DQS2 FBC_DQS1 F3 C7 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 FBC_DQM2 FBC_DQM1 E7 D3 ODT/ODT0 CS/CS0 RAS CAS WE A1 A8 C1 C9 D2 E9 F1 H2 H9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU FBC_ODT_L RESET ZQ/ZQ0 FBC_DQS#2 G3 FBC_DQS#1 B7 DQSL DQSU T2 FBC_RST# RESET L8 ZQ/ZQ0 1 J1 L1 J9 L9 RV88 243_0402_1% N13P@ 96-BALL SDRAM DDR3 K4W1G1646E-HC12_FBGA96 X76@ RV117 10K_0402_5% N13P@ RV116 10K_0402_5% N13P@ 2 N13P@ RST FBx_CMD6 A9 A9 FBx_CMD7 A7 A7 FBx_CMD8 A2 A2 FBx_CMD9 A0 A0 FBx_CMD10 A4 A4 FBx_CMD11 A1 A1 FBx_CMD12 BA0 BA0 FBx_CMD13 WE# WE# FBx_CMD14 A15 A15 FBx_CMD15 CAS# 1 1 2 2 2 2 N13P@ N13P@ N13P@ N13P@ 1 2 N13P@ Compal Secret Data 2011/10/27 Deciphered Date 2012/10/27 Title CS0#_H ODT_H CKE_H A13 FBx_CMD21 A8 A8 FBx_CMD22 A6 A6 FBx_CMD23 A11 A11 FBx_CMD24 A5 A5 FBx_CMD25 A3 A3 FBx_CMD26 BA2 BA2 FBx_CMD27 BA1 BA1 FBx_CMD28 A12 A12 FBx_CMD29 A10 A10 FBx_CMD30 RAS# RAS# A13 B 1 2 N13P@ A Compal Electronics, Inc. N13X-VRAM C Lower Date: 4 CAS# FBx_CMD20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 C CV193 1 CV204 1U_0402_6.3V6K 2 N13P@ CV186 CV197 CV184 CV195 2 2 N13P@ N13P@ Security Classification Issued Date A14 RST FBx_CMD19 CV201 1U_0402_6.3V6K 2 N13P@ 1 CV200 1U_0402_6.3V6K 2 N13P@ CV203 CV192 CV194 @ 1 CV198 1U_0402_6.3V6K 2 1 CV187 .1U_0402_16V7K @ 1 .1U_0402_16V7K N13P@ 2 1 1U_0402_6.3V6K 2 1 1U_0402_6.3V6K N13P@ @ 1 A14 FBx_CMD5 UV8 SIDE .1U_0402_16V7K 2 1 .1U_0402_16V7K 2 1 CV185 1U_0402_6.3V6K @ 1 CV182 1U_0402_6.3V6K 2 1 CV181 1U_0402_6.3V6K @ 1 CV206 1U_0402_6.3V6K CV188 CV205 N13P@ 2 1 CV190 .1U_0402_16V7K N13P@ 2 1 .1U_0402_16V7K N13P@ 2 1 1U_0402_6.3V6K 2 CV189 CV199 CV183 @ 1 1U_0402_6.3V6K 2 1 1U_0402_6.3V6K @ 1 1U_0402_6.3V6K 2 CV191 1 +1.5VS_VGA CKE_L FBx_CMD4 FBx_CMD18 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ ODT_L FBx_CMD3 FBx_CMD17 96-BALL SDRAM DDR3 K4W1G1646E-HC12_FBGA96 X76@ UV7 SIDE .1U_0402_16V7K A .1U_0402_16V7K +1.5VS_VGA NC/ODT1 NC/CS1 NC/CE1 NCZQ1 1U_0402_6.3V6K 2 B1 B9 D1 D8 E2 E8 F9 G1 G9 1U_0402_6.3V6K VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 2 RV90 243_0402_1% N13P@ NC/ODT1 NC/CS1 NC/CE1 NCZQ1 FBx_CMD2 FBx_CMD16 1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 2 DQSL DQSU DML DMU 1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 2 DML DMU A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 32..63 CS0#_L FBx_CMD1 Group1 (TOP) B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD 0..31 FBx_CMD0 +1.5VS_VGA 2 1 1 RV91 10K_0402_5% N13P@ <27,31> Mode D - Mirror Mode Mapping B J1 L1 J9 L9 FBC_DQS#[7..0] D FBC_CKE_L FBC_DQS#0 G3 FBC_DQS#3 B7 <27,31> DATA Bus DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 BA0 BA1 BA2 J7 FBC_CLK0 FBC_CLK0# K7 FBC_CKE_L K9 E3 F7 F2 F8 H3 H8 G2 H7 1 C DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 2 FBC_CLK0 FBC_MA0 FBC_MA1 FBC_MA2 FBC_MA3 FBC_MA4 FBC_MA5 FBC_MA6 FBC_MA7 FBC_MA8 FBC_MA9 FBC_MA10 FBC_MA11 FBC_MA12 FBC_MA13 FBC_MA14 FBC_MA15 <27,31> FBC_DQS[7..0] UV8 VREFCA VREFDQ <27,31> FBC_DQM[7..0] 3 2 Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet 1 30 of 60 5 4 3 2 1 Memory Partition C - Upper 32 bits FBC_D[0..63] <27,30> FBC_MA[15..0] <27,30> UV9 1 C <27> <27> <27,30> <27,30> <27,30> FBC_CLK1# FBC_ODT_H FBC_CS0#_H FBC_RAS# FBC_CAS# FBC_WE# FBC_CLK1 FBC_CLK1# FBC_CKE_H J7 K7 K9 FBC_ODT_H FBC_CS0#_H FBC_RAS# FBC_CAS# FBC_WE# K1 L2 J3 K3 L3 FBC_DQS4 FBC_DQS5 F3 C7 FBC_DQM4 FBC_DQM5 E7 D3 FBC_DQS#4 G3 FBC_DQS#5 B7 FBC_ODT_H FBC_CKE_H T2 1 L8 1 RV119 10K_0402_5% N13P@ J1 L1 J9 L9 RV123 243_0402_1% N13P@ BA0 BA1 BA2 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE DQSL DQSU DML DMU VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 2 2 2 1 RV118 10K_0402_5% N13P@ B FBC_RST# <27,30> FBC_RST# +1.5VS_VGA B2 D9 G7 K2 K8 N1 N9 R1 R9 FBC_BA0 FBC_BA1 FBC_BA2 M2 N8 M3 A1 A8 C1 C9 D2 E9 F1 H2 H9 FBC_ODT_H FBC_CS0#_H FBC_RAS# FBC_CAS# FBC_WE# FBC_DQS7 FBC_DQS6 F3 C7 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 FBC_DQM7 FBC_DQM6 E7 D3 J7 FBC_CLK1 FBC_CLK1# K7 FBC_CKE_H K9 K1 L2 J3 K3 L3 FBC_DQS#7 G3 FBC_DQS#6 B7 T2 FBC_RST# L8 B1 B9 D1 D8 E2 E8 F9 G1 G9 J1 L1 J9 L9 RV128 243_0402_1% N13P@ 96-BALL SDRAM DDR3 K4W1G1646E-HC12_FBGA96 X76@ @ N13P@ 2 @ DQSL DQSU DML DMU DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 Group6 (BOT) VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ @ CV212 1 2 N13P@ 1 2 @ 1 2 2011/10/27 Deciphered Date B2 D9 G7 K2 K8 N1 N9 R1 R9 A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 ODT_L FBx_CMD3 CKE_L FBx_CMD4 A14 A14 FBx_CMD5 RST RST FBx_CMD6 A9 A9 FBx_CMD7 A7 A7 FBx_CMD8 A2 A2 FBx_CMD9 A0 A0 FBx_CMD10 A4 A4 FBx_CMD11 A1 A1 FBx_CMD12 BA0 BA0 FBx_CMD13 WE# WE# FBx_CMD14 A15 A15 FBx_CMD15 CAS# 3 C CAS# CS0#_H FBx_CMD16 FBx_CMD17 ODT_H FBx_CMD18 CKE_H FBx_CMD19 FBx_CMD20 B1 B9 D1 D8 E2 E8 F9 G1 G9 1 2 1 2 1 2 1 2 1 A13 A13 FBx_CMD21 A8 A8 FBx_CMD22 A6 A6 FBx_CMD23 A11 A11 FBx_CMD24 A5 A5 FBx_CMD25 A3 A3 FBx_CMD26 BA2 BA2 FBx_CMD27 BA1 BA1 FBx_CMD28 A12 A12 FBx_CMD29 A10 A10 FBx_CMD30 RAS# RAS# B 2 N13P@ A N13P@ N13P@ N13P@ N13P@ N13P@ 2012/10/27 Title Compal Electronics, Inc. N13X-VRAM C Upper Date: 4 32..63 CS0#_L FBx_CMD2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 0..31 FBx_CMD0 FBx_CMD1 Compal Secret Data Security Classification Issued Date 2 CV222 CV211 CV223 2 1 1U_0402_6.3V6K 2 1 1U_0402_6.3V6K N13P@ CV208 CV210 2 1 1U_0402_6.3V6K 2 N13P@ 1 1U_0402_6.3V6K @ 1 ODT/ODT0 CS/CS0 RAS CAS WE <27,30> DATA Bus Address +1.5VS_VGA VDD VDD VDD VDD VDD VDD VDD VDD VDD <27,30> FBC_DQS#[7..0] Mode D - Mirror Mode Mapping UV10 SIDE .1U_0402_16V7K 2 1 CV225 1U_0402_6.3V6K 2 2 N13P@ N13P@ 1 CV228 1U_0402_6.3V6K @ 1 CV221 1U_0402_6.3V6K 2 1 CV220 1U_0402_6.3V6K 2 N13P@ 1 CV230 .1U_0402_16V7K CV207 CV226 2 N13P@ 1 .1U_0402_16V7K 2 N13P@ 1 1U_0402_6.3V6K 2 N13P@ CV233 CV213 CV227 @ 1 1U_0402_6.3V6K 2 1 .1U_0402_16V7K +1.5VS_VGA 1U_0402_6.3V6K 2 N13P@ 1 1U_0402_6.3V6K CV209 1 CK CK CKE/CKE0 FBC_D54 FBC_D51 FBC_D55 FBC_D49 FBC_D52 FBC_D50 FBC_D53 FBC_D48 96-BALL SDRAM DDR3 K4W1G1646E-HC12_FBGA96 X76@ UV9 SIDE .1U_0402_16V7K A .1U_0402_16V7K +1.5VS_VGA BA0 BA1 BA2 D7 C3 C8 C2 A7 A2 B8 A3 <27,30> FBC_DQS[7..0] CV232 <27> FBC_CLK1 <27> FBC_CLK1# <27> FBC_CKE_H RV129 160_0402_1% N13P@ Group5 (TOP) DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 CV218 1U_0402_6.3V6K 2 FBC_CLK1 FBC_D47 FBC_D43 FBC_D46 FBC_D42 FBC_D40 FBC_D45 FBC_D44 FBC_D41 <27,30> FBC_DQM[7..0] D Group7 (IN3) CV217 1U_0402_6.3V6K M2 N8 M3 FBC_BA0 FBC_BA1 FBC_BA2 D7 C3 C8 C2 A7 A2 B8 A3 Group4 (IN1) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 CV215 1U_0402_6.3V6K 2 2 N13P@ DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 FBC_MA0 FBC_MA1 FBC_MA2 FBC_MA3 FBC_MA4 FBC_MA5 FBC_MA6 FBC_MA7 FBC_MA8 FBC_MA9 FBC_MA10 FBC_MA11 FBC_MA12 FBC_MA13 FBC_MA14 FBC_MA15 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 FBC_D60 FBC_D57 FBC_D63 FBC_D58 FBC_D61 FBC_D56 FBC_D62 FBC_D59 CV214 1U_0402_6.3V6K RV127 1.1K_0402_1% N13P@ 1 CV229 0.01U_0402_16V7K 1 +FBB_VREF1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 VREFCA VREFDQ E3 F7 F2 F8 H3 H8 G2 H7 CV224 .1U_0402_16V7K 2 1.1K_0402_1% N13P@ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 M8 H1 +FBB_VREF1 .1U_0402_16V7K RV120 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 VREFCA VREFDQ FBC_D39 FBC_D33 FBC_D38 FBC_D32 FBC_D36 FBC_D35 FBC_D37 FBC_D34 CV231 FBC_MA0 FBC_MA1 FBC_MA2 FBC_MA3 FBC_MA4 FBC_MA5 FBC_MA6 FBC_MA7 FBC_MA8 FBC_MA9 FBC_MA10 FBC_MA11 FBC_MA12 FBC_MA13 FBC_MA14 FBC_MA15 FBC_BA[2..0] UV10 E3 F7 F2 F8 H3 H8 G2 H7 1 1 D M8 H1 +FBB_VREF1 2 +1.5VS_VGA 2 Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet 1 31 of 60 5 4 3 RV96 45.3K_0402_1% N13P@ 2 2 SLOT_CLK_CFG PEX_PLL_EN_TERM +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0] ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0] STRAP1 +3VS_VGA STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0] STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED STRAP4 +3VS_VGA PCIE_SPEED_ CHANGE_GEN3 PCIE_MAX_SPEED DP_PLL_VDD33V RESERVED Pull-down to Gnd 10K 1001 0001 15K 1010 0010 20K 1011 0011 25K 1100 0100 30K 1101 0101 35K 1110 0110 45K 1111 0111 Logical Strapping Bit0 3GIO_PAD_CFG_ADR[0] D 1 2 2 Samsung S2GP@ X7634138L01 S1GM@ X7634138L05 ZZZ ZZZ 0000 Hynix H2GP@ X7634138L02 H1GM@ X7634138L06 ZZZ ZZZ C 1 ROM_SI ROM_SO ROM_SCLK Samsung 2 1 1 RV102 10K_0402_1% N13P@ S1GP@ X7634138L03 S512M@ X7634138L07 ZZZ ZZZ RV103 15K_0402_1% N13P@ Hynix H1GP@ X7634138L04 10/11 Updated for NVIDIA update. N13P-GL 900 MHz N13P-GL 900 MHz N13P-GL 900 MHz N13P-GL 900 MHz B Memory Size Frenq. 128M* 16* 8 2GB 128M* 16* 8 2GB 64M* 16* 8 1GB 64M* 16* 8 1GB Memory Config Samsung (2Gb) K4W2G1646C-HC11 Hynix (2Gb) H5TQ1G63DFR-11C Samsung (1Gb) K4W1G1646G-BC11 Hynix (1Gb) H5TQ1G63DFR-11C Hynix H512M@ X7634138L08 X76 For N13P-GL strap table GPU Samsung SUB_VENDOR 3GIO_PADCFG XCLK_417 0 No VBIOS ROM 3GIO_PADCFG[3:0] 0 277MHz (Default) 1 BIOS ROM is present (Default) 1 Reserved 0110 Notebook Default FB_0_BAR_SIZE SLOT_CLK_CFG 0 Reserved 0 GPU and MCH don't share a common reference clock 1 Reserved 1 GPU and MCH share a common reference clock (Default) 2 256MB (Default) SMBUS_ALT_ADDR VGA_DEVICE 3 Reserved 0 0x9E (Default) 0 3D Device (Class Code 302h) 1 0x9C (Multi-GPU usage) 1 VGA Device (Default) 1 RV101 20K_0402_1% X76@ X76 2 2 <24> ROM_SI <24> ROM_SO <24> ROM_SCLK 1 1 RV100 @ 4.99K_0402_1% 5K ZZZ Hynix RV99 @ 30K_0402_1% Logical Strapping Bit1 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] Pull-up to +3VS_VGA 1000 Resistor Values +3VS_VGA 2 PCI_DEVID[4] ROM_SI Power Rail RV125 @ 10K_0402_1% Samsung RV98 4.99K_0402_1% @ +3VS_VGA Logical Strapping Bit2 SUB_VENDOR 1 RV124 @ 4.99K_0402_1% ZZZ C 1 Logical Strapping Bit3 2 2 RV97 @ 10K_0402_1% 1 1 1 2 STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 @ RV95 45.3K_0402_1% 2 Physical Strapping pin ROM_SCLK RV122 @ 20K_0402_1% 1 RV121 @ 20K_0402_1% 1 RV94 10K_0402_1% N13P@ 1 STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 2 <24> <24> <24> <24> <24> 2 D @ RV93 45.3K_0402_1% 1 1 RV92 45.3K_0402_1% N13P@ 2 2 2 +3VS_VGA strap0 R PU 45K R PU 45K R PU 45K R PU 45K strap1 R PD 45K R PD 45K R PD 45K R PD 45K strap2 strap3 R PU 45K R PU 45K R PU 45K R PU 45K strap4 n/a n/a n/a n/a n/a n/a n/a n/a ROM_SI R PD 45K R PD 35K R PD 20K R PD 15K ROM_SO ROM_SCLK R PD 10K R PD 10K R PD 10K R PD 10K R PD 15K R PD 15K R PD 15K R PD 15K USER Straps B User[3:0] 1000-1100 Customer defined PEX_PLL_EN_TERM 10/11 Updated for NVIDIA update. 0 Disable (Default) 1 Enable PCIE_MAX_SPEED 0 Limit to PCIE Gen1 1 PCIE Gen 2/3 Capable A A Compal Secret Data Security Classification Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title Compal Electronics, Inc. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 N13X_MISC Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet 1 32 of 60 5 4 3 2 1 LCD POWER CIRCUIT +LCDVDD CMOS Camera +3VS +5VALW +3VS W=60mils 1 (20 MIL) R400 150_0603_1% D 1 R401 100K_0402_5% CMOS@ Q83 PMV65XP_SOT23-3~D C513 4.7U_0603_6.3V6K 1 OUT GND 3 1 3 1 Q80 PMV65XP_SOT23-3~D 1 2 2 1 3 2 R435 CMOS@ 150K_0402_5% W=60mils D IN G 2 <17> PCH_ENVDD C515 0.1U_0402_16V4Z 1 S Q79 2N7002_SOT23 S 3 G R403 220K_0402_5% 1 2 2 G D D S 2 (20 MIL) +3VS_CMOS R4953 0_0603_5% 1 2 CMOS@ +3VS_CMOS_R 1 CMOS@ C518 0.1U_0402_16V4Z 2 D 1 C519 10U_0603_6.3V6M 2 CMOS@ <42> CMOS_ON# 2 +LCDVDD L29 +LCDVDD_CONN 1 Q81 DTC124EK DTC124EKAT146_SC59-3 1 2 2 FBMA-L11-201209-221LMA30T_0805 C516 4.7U_0603_6.3V6K 2 @ R408 100K_0402_5% 1 1 2 2 C520 0.1U_0402_16V4Z CMOS@ C517 0.1U_0402_16V4Z +3VS C R717 0_0402_5% 1 2 1 C VGA LCD/PANEL BD. Conn. R433 @ BKOFF# 1 BKOFF# 2 +LEDVDD DISPOFF# R716 10K_0402_5% C539 680P_0402_50V7K @ 2 R538 1 <17> PCH_ENBKL B+ D4 @ CH751H-40PT_SOD323-2 1 <42> 2 4.7K_0402_5% 0_0402_5% 2 ENBKL 1 1 2 2 C541 4.7U_0805_25V6-K <42> +LCDVDD_CONN +LEDVDD +3VS 2 +3VS_CMOS CMOS R438 100K_0402_5% <18> <18> USB20_N5 USB20_P5 <17> <17> LVDS_A0# LVDS_A0 <17> <17> LVDS_A1# LVDS_A1 USB20_N5 USB20_P5 1 B 1 R813 2 0_0805_5% <17> <17> LVDS_A0# LVDS_A0 LVDS_A1# LVDS_A1 LVDS_A2# LVDS_A2 LVDS_A2# LVDS_A2 LVDS_ACLK# LVDS_ACLK <17> LVDS_ACLK# <17> LVDS_ACLK <17> <17> <17> <17> LVDS_B0 LVDS_B0# LVDS_B1# LVDS_B1 LVDS_B0 LVDS_B0# LVDS_B1# LVDS_B1 JLVDS1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 B 1 (60 MIL) 2 @ C540 680P_0402_50V7K INVPWM DISPOFF# 0_0402_5% 2 R430 1 0_0402_5% 2 R431 1 @ PCH_PWM <17> EC_INVT_PWM <42> EDID Pull high at chipset/VGA side EDID_CLK EDID_DATA LVDS_B2# LVDS_B2 EDID_CLK <17> EDID_DATA <17> LVDS_B2# <17> LVDS_B2 <17> LVDS_BCLK LVDS_BCLK# LVDS_BCLK <17> LVDS_BCLK# <17> 42 ACES_87142-4041 A A ME@ Compal Secret Data Security Classification Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title Compal Electronics, Inc. LVDS/CAMERA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet 1 33 of 60 A B I/O3 +5VS 4 BLUE 1 CRT Connector +CRT_VCC +5VS D10 AZC099-04S.R7G_SOT23-6 F1 2 1 1 2 +CRT_VCC_F 1 RB491D_SC59-3 2 W=40mils BLUE 1 2 1 2 JCRT1 1 PAD T66 2 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 NC11 RED CRT_DDC_DAT_CONN GREEN CLOSE TO CONN JVGA_HS BLUE JVGA_VS 2 +CRT_VCC CRT_DDC_CLK_CONN R448 1 2 C528 1 1K_0402_5% 100P_0402_50V8J 1 4 Y FCM1608CF-121T03 0603 1 2 L33 CRT_HSYNC_1 16 17 2 CONTE_80431-5K1-152 2 3 1 2 R451 1 9/21 EMI request 0ohm and mount @ C530 10P_0402_50V8J D8 JVGA_VS 3 @ I/O2 I/O4 GND VDD I/O1 I/O3 6 JVGA_HS 5 +5VS 4 CRT_DDC_DAT_CONN 2 2 1 1K_0402_5% 3 G A OE# 2 CRT_DDC_CLK_CONN 1 5 2 P <17> CRT_VSYNC G G JVGA_HS U23 SN74AHCT1G125DCKR_SC70-5 +CRT_VCC 3 10/27 change to 0402 footprint 1 G A OE# P 2 <17> CRT_HSYNC C531 0.1U_0402_16V4Z ME@ 2 5 C529 0.1U_0402_16V4Z C521 0.1U_0402_16V4Z 2 GREEN 10P_0402_50V8J C527 2 1 RED 10P_0402_50V8J C526 2 1 10P_0402_50V8J C525 R446 150_0402_1% 1 10P_0402_50V8J C524 1 10P_0402_50V8J C522 2 R443 150_0402_1% 2 1 1 2 R445 150_0402_1% 10P_0402_50V8J C523 <17> DAC_GRN <17> DAC_BLU 1.1A_6V_SMD1812P110TF FCM1608CF-121T03 0603 1 2 L30 FCM1608CF-121T03 0603 1 2 L31 FCM1608CF-121T03 0603 1 2 L32 <17> DAC_RED C536 0_0402_5% 1 I/O1 5 2 VDD GREEN C535 0_0402_5% 1 GND 6 2 I/O4 C538 0_0402_5% 1 1 RED @ I/O2 2 1 E C537 0_0402_5% 1 2 D 2 D73 3 C 4 Y FCM1608CF-121T03 0603 1 2 L34 CRT_VSYNC_1 @ C532 10P_0402_50V8J 1 1 +CRT_VCC +3VS 3 2 R457 2.2K_0402_5% 2 5 R456 2.2K_0402_5% 4 <17> CRT_DDC_DATA 3 1 2 Pull high at chipset/VGA side AZC099-04S.R7G_SOT23-6 JVGA_VS U24 SN74AHCT1G125DCKR_SC70-5 1 CRT_DDC_DAT_CONN 2 2N7002DW -T/R7_SOT363-6 Q62B 1 <17> CRT_DDC_CLK 6 2N7002DW -T/R7_SOT363-6 Q62A 4 @ C533 100P_0402_50V8J 1 2 CRT_DDC_CLK_CONN 1 @ C534 68P_0402_50V8K 2 Compal Secret Data Security Classification Issued Date 4 2011/10/27 Deciphered Date 2012/10/27 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Compal Electronics, Inc. CRT Connector Size Document Number Custom Date: Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet E 34 of 60 5 4 3 2 1 +5VS +5VS RB491D_SC59-3 D13 HDMI@ 2 1+HDMI_5V 2 2 3 +3VS R482 @ 0_0805_5% 2 HDMI@ R483 2.2K_0402_5% C +3VS C992 1 HDMI_CLK-_CONN C993 1 HDMI_TX0+_CONN C994 1 HDMI_TX0-_CONN C995 1 HDMI_TX1+_CONN C996 1 HDMI_TX1-_CONN C997 1 HDMI_TX2+_CONN C998 1 2 HDMI_TX2-_CONN C999 1 2 @ 2 @ 2 @ 2 @ 2 @ 2 @ 2 @ 2 @ 4.7P_0402_50V R484 HDMI@ 2.2K_0402_5% JHDMI1 1 HDMI_CLK+_CONN 1 R488 20K_0402_5% HDMI@ 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HDMI_DET 4.7P_0402_50V +5VS_HDMI HDMIDAT_R HDMICLK_R 4.7P_0402_50V 4.7P_0402_50V 4.7P_0402_50V <17> HDMI_CLK-_CK <17> HDMI_CLK+_CK 4.7P_0402_50V <17> HDMI_TX0-_CK <17> HDMI_TX0+_CK 4.7P_0402_50V 4.7P_0402_50V <17> HDMI_TX1-_CK <17> HDMI_TX1+_CK R783 0_0402_5% HDMI_CLK-_CK R465 1 @ 2 11NH +-5% 0402 HDMI_CLK-_CONN HDMI_CLK+_CKR464 1 @ HDMI_TX0-_CK R467 1 @ 2 11NH +-5% 0402 HDMI_CLK+_CONN 2 11NH +-5% 0402 HDMI_TX0-_CONN HDMI_TX0+_CK R466 1 @ HDMI_TX1-_CK R469 1 @ 2 11NH +-5% 0402 HDMI_TX0+_CONN 2 11NH +-5% 0402 HDMI_TX1-_CONN HDMI_TX1+_CK R468 1 @ HDMI_TX2-_CK R471 1 @ 2 11NH +-5% 0402 HDMI_TX1+_CONN 2 11NH +-5% 0402 HDMI_TX2-_CONN HDMI_TX2+_CK R470 1 @ 2 11NH +-5% 0402 HDMI_TX2+_CONN 1 <17> HDMI_TX2-_CK <17> HDMI_TX2+_CK 1 1 HDMI_CLK-_CK 4 2 4 3 2 HDMI_CLK+_CONN 3 HDMI_CLK-_CONN WCM-2012-900T_4P B <17> HDMIDAT_NB 4 3 HDMIDAT_R L36 Q63B HDMI@ 2N7002DW-T/R7_SOT363-6 HDMI_TX0+_CK 1 HDMI_TX0-_CK 4 2 4 3 L37 HDMI_TX1+_CK 1 HDMI_TX1-_CK 4 HDMI_CLK-_CONN HDMI_CLK+_CONN HDMI_TX1-_CONN HDMI_TX1+_CONN HDMI@ 1 2 HDMI_TX0+_CONN 3 HDMI_TX0-_CONN WCM-2012-900T_4P HDMIDAT_R 2 4 3 2 HDMI_TX1+_CONN 3 HDMI_TX1-_CONN SD309680080 S ROW RES 1/16W 680 +-5% 8P4R RP5 HDMI@ HDMI_TX0-_CONN HDMI_TX0+_CONN HDMI_TX2-_CONN HDMI_TX2+_CONN HDMI@ 1 680 +-5% 8P4R 5 4 6 3 7 2 8 1 +3VS RP6 HDMI@ D 2 3 3 S WCM-2012-900T_4P L38 HDMI_TX2+_CK 1 HDMI_TX2-_CK 4 B 680 +-5% 8P4R 5 4 6 3 7 2 8 1 HDMICLK_R D11 @ PJDLC05_SOT23-3 C HDMI@ 1 HDMICLK_R 5 <17> HDMICLK_NB 6 L35 HDMI_CLK+_CK 20 21 22 23 1 2 Q63A HDMI@ 2N7002DW-T/R7_SOT363-6 HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKG1 CK_shield G2 CK+ G3 D0G4 D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ SUYIN_100042GR019M23DZL ME@ 12/06 Update back to common mode choke. SM070000K00 Pull up R for PCH OR VGA SIDE D 2 1 C543 HDMI@ 0.1U_0402_16V4Z 2 D14 @ BAT54S-7-F_SOT23-3 2 3 D TMDS_B_HPD S <17> TMDS_B_HPD Q93 HDMI@ 2N7002H_SOT23-3 1 1 G 2 R485 1M_0402_5% HDMI@ 1 D W=40mils +5VS_HDMI F2 HDMI@ 1.1A_6VDC_FUSE 1 2 +5VS_HDMI 1 2 G Q95 HDMI@ 2N7002H_SOT23-3 HDMI@ 1 2 4 3 2 HDMI_TX2+_CONN 3 HDMI_TX2-_CONN WCM-2012-900T_4P A 1 A Issued Date Compal Electronics,Ltd. Compal Secret Data Security Classification 2011/10/27 Deciphered Date 2012/10/27 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HDMI CONN Document Number Date: Thursday, January 05, 2012 5 4 3 2 Rev 0.3 LA-7983P Sheet 1 35 of 60 A B C D E Mini-Express Card for WLAN/WiMAX(Half) +3VS_WLAN <19,40> PCH_BT_ON# <19> BT_DISABLE# 2 1 2 C548@ 4.7U_0603_6.3V6K 2 +1.5VS 1 1 +1.5VS_CONN 2 2 1 C547 0.1U_0402_16V4Z 2 1 C544 0.1U_0402_16V4Z 2 1 C545 @ 0.1U_0402_16V4Z JUMP_43X79 1 2 @ R4965 0_0402_5% R4964 1 1 @ Mini-Express Card(WLAN/WiMAX) 1 +3VALW +3VS_WLAN 80mil J6 @ +3VS 0_0402_5% 1 R514 2 1 R497 2 @ 0_0402_5% PCIE_WAKE# BT_ACTIVE BT_DISABLE#_R <16,37,45> PCIE_WAKE# <40> BT_ACTIVE 0_0402_5% JWLAN1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 <15> CLKREQ_WLAN# <15> CLK_PCIE_WLAN1# <15> CLK_PCIE_WLAN1 PCI_RST#_R CLK_PCI_DB <15> PCIE_PRX_DTX_N2 <15> PCIE_PRX_DTX_P2 <15> PCIE_PTX_C_DRX_N2 <15> PCIE_PTX_C_DRX_P2 +3VS_WLAN 100_0402_1% R505 1 2 1 2 R506 100_0402_1% 53 For EC to detect debug card insert. GND +1.5VS_CONN LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R 1 R498 2 0_0402_5% 1 R499 1 R500 2 @ 0_0402_5% 2 0_0402_5% 1 R501 1 R502 2 @ 0_0402_5% 2 @ 0_0402_5% USB20_N10 USB20_P10 R503 2 R504 2 1 0_0402_5% 1 0_0402_5% @ @ PCH_WL_OFF# <18> PLT_RST# <18,23,37,42,45> +3VALW +3VS SMB_CLK_S3 <12,13,15> SMB_DATA_S3 <12,13,15> <18> <18> WLAN_LED# NC Reserve for SW mini-pcie debug card. Series resistors closed to KBC side. 54 LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R PCI_RST#_R CLK_PCI_DB R507 100K_0402_5% 1 2 GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 TAITW_PFPET0-AFGLBG1ZZ4N0 ME@ 2 <42,43> EC_TX <42,43> EC_RX WAKE# 3.3V NC GND NC 1.5V CLKREQ# NC GND NC REFCLKNC REFCLK+ NC GND NC NC GND NC NC GND PERST# PERn0 +3.3Vaux PERp0 GND GND +1.5V GND SMB_CLK PETn0 SMB_DATA PETp0 GND GND USB_DNC USB_D+ NC GND NC LED_WWAN# NC LED_WLAN# NC LED_WPAN# NC +1.5V NC GND NC +3.3V Every power trace need: W=20mils +CHGRTC_R +3VLP +1.05VS +3V_LAN +3VS_VGA +RTCBATT SLG3NB244VTR 2 1 RG8 0_0402_5% 2 2 CG1 2 OSC +3VS_GCLK NC 3 GCLK@ 9/22 from 11 +3V_LAN 8 PCH_GCLK 3 1 16 VDD_RTC_OUT 1 2 LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 LPC_FRAME# <14,42> LPC_AD3 <14,42> LPC_AD2 <14,42> LPC_AD1 <14,42> LPC_AD0 <14,42> PLT_RST# CLK_PCI_DB 2 <18> 14 3 VDD VDDIO_27M 27MHz VDDIO_25M_A 25MHz_A VDDIO_25M_B 25MHz_B XTAL_IN XTAL_OUT 2 CG9 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% +V3.3A SLG3NB274VTR_TQFN16_2X3 GND4 VGA_GCLK GreenCLK_XTALI GreenCLK_XTALO OSC 2 VBAT 32kHz GCLK@ 25MHZ_20PF_FSX3M-25.M20FDO CG8 GCLK@ 15 GND1 GND2 GND3 NC 10 2 2 2 2 2 2 CG4 2.2U_0402_6.3V6M 2 GCLK@ 9 GCLK_32K_R RG1 12 GCLK_27MHZ_R RG2 6 GCLK_LAN_25MHZ_R 5 GCLK_PCH_25MHZ_R 1 2 0_0402_5% GCLK_32K GCLK_32K GCLK@ 1 2 33_0402_5% GCLK_27MHZ GCLK274@ 1 2 33_0402_5% GCLK_LAN_25MHZ GCLK@ 2 33_0402_5% GCLK_PCH_25MHZ RG4 1 GCLK@ GCLK_27MHZ RG3 <14> <23> GCLK_LAN_25MHZ <37> GCLK_PCH_25MHZ <15> PCH_32.768K NV_GPU LAN PCH_25M Close to GCLK Reserved for Swing Level adjustment ( Close GCLK side ) 17 33P_0402_50V8J 1 1 1 U68 0.1U_0402_16V4Z Y8 4 1 CG3 GCLK@ 22U_0603_6.3V6M 4 7 13 2 2 2 33P_0402_50V8J 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 GCLK274@ 0.1U_0402_16V4Z GCLK@ CG7 1 2 1 CG6 GCLK@ CG5 3 +3V_LAN GCLK274@ RG9 0_0402_5% 0_0402_5% RG11 1 1 1 2 0.1U_0402_16V4Z GCLK244@ 1 2 @ @ @ @ @ @ For GreenCLK generate CLK: Mount: All parts in this page except Swing Level RES (Marked "*") NA: PD108, Y1,R98,C180,C181, Y2,R169,C196,C197, Y6,C968,C969 +3VLP U68 GCLK@ CG2 1 1 1 1 1 1 R508 R509 R510 R511 R512 R513 GCLK274@ GCLK@ 15pF RG5 *1 @ GCLK_27MHZ RG6 *1 @ GCLK_LAN_25MHZ RG7 *1 @ GCLK_PCH_25MHZ 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 4 4 Compal Secret Data Security Classification Issued Date 2011/10/27 Deciphered Date 2012/10/27 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size B C D Document Number Rev 0.3 LA-7983P Date: A Compal Electronics, Inc. Mini-Card/Green CLK Thursday, January 05, 2012 Sheet E 36 of 60 5 4 3 2 1 Atheros request can't disable LAN power +3V_LAN +3VALW 2 L77 SWR@ 2 1 2 C317 2 1 1 2 G 2 2 +1.1_AVDDL_L 4.7UH_SIA4012-4R7M_20% Note: Place Close to LAN chip L39 DCR< 0.15 ohm Rate current > 1A 4.7U_0603_6.3V6K 1 1 FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P 1 2 1 2 +1.1_AVDDL +1.1_DVDDL C980 D S 3 1 2 +LX C967 Q130 LP2301ALT1G_SOT23 1 10U_0603_6.3V6M @ C935 1000P_0402_50V7K 2 0_0402_5% +LX_R @ D L78 L74 SWR@ 1 1U_0402_6.3V4Z R1357 +1.1_DVDDL 0.1U_0402_16V4Z 2 JUMP_43X79 C936 1 Close together 0.1U_0402_16V4Z C937 1 +LX Layout Notice : Place as close chip as possible. J18 D R4977 1 LAN_PWR_ON# <42> LAN_PWR_ON# 2 2 +3V_LAN 8162@ PLT_RST# R1367 SA000050E00_S IC AR8161-AL3A-R QFN 40P E-LAN CTRL SA000052J10_S IC AR8162-AL3A-R QFN 40P E-LAN CTRL 1 +AVDDH_AVDD3.3 AR8162-AL3A-R U41 2 4.7K_0402_5% 28 27 @ Vendor recommand reseve the PU resistor close LAN chip @ +3V_LAN R520 1 7 8 LAN_XTALO LAN_XTALI_R 2 4.7K_0402_5% 4 <15> CLKREQ_LAN# 13 19 31 34 6 Near Pin13 Near Pin19 2 Near Pin31 0.1U_0402_16V4Z C959 C958 2 1 1U_0402_6.3V4Z C960 2 1 0.1U_0402_16V4Z C957 1 0.1U_0402_16V4Z C956 2 0.1U_0402_16V4Z +1.1_AVDDL +1.1_AVDDL +1.1_AVDDL +1.1_AVDDL_L +1.1_AVDDL 1 SMCLK SMDATA RBIAS NC TESTMODE VDD33 LX XTLO XTLI 1 2 41 C981 CLKREQ# DVDDL/PPS DVDDL_REG/DVDDL AVDDL AVDDL AVDDL AVDDL AVDDL_REG/AVDDL +3V_LAN 1 +3V_LAN +LX 5 +1.7_VDDCT 24 37 +1.1_DVDDL 16 22 9 +AVDDH_AVDD3.3 +2.7_AVDDH +2.7_AVDDH +LX 1 30K_0402_1% 2 +3VS GND 1 Near Pin9 1 2 1 2 Near Pin22 1 2 1 2 2 1 2 1 2 B Near Pin37 LAN_XTALI CRYSTAL@ 2 0_0402_5% R1373 1 C988 5P_0402_50V8 LAN_XTALI 4 Place Close to C968 LAN_XTALO NC OSC OSC NC 3 <36> GCLK_LAN_25MHZ GCLK_LAN_25MHZ 2 1 LAN_XTALI_R 2 A GCLK@ C969 1 25MHZ_20PF_FSX3M-25.M20FDO 1 C968 15P_0402_50V8J 1 2 12/29, Y6 changes to SJ10000E800 S CRYSTAL 25MHZ 10PF +-20PPM 7V25000014 4 2 1 5P_0402_50V8 2 3.3V : Enable switching regulator 0V : Disable switching regulator 1 @ +2.7_AVDDH AVDDH/AVDD33 AVDDH AVDDH_REG Y6 5 Place Close to PIN1 2 40 2 @ 1 Place Close to PIN1 AR8161-AL3A-R_QFN40_5X5 1 Place close to Pin16 10K_0402_5% LDO@ R1371 2.37K_0402_1% Near Pin6 <15> PCH_LAN_48M A LAN_RBIAS R1372 VDDCT/ISOLAN B 10 <38> <38> <38> <38> <38> <38> <38> <38> C W AKE# C961 R521 1 25 26 PERST# MDI0MDI0+ MDI1MDI1+ MDI2MDI2+ MDI3MDI3+ 2 C954 3 2 15P_0402_50V8J +3V_LAN 2 0_0402_5% 2 0_0402_5% REFCLK_N REFCLK_P MDI0MDI0+ MDI1MDI1+ MDI2MDI2+ MDI3MDI3+ 1 1 R4959 C953 10U_0603_6.3V6M PCIE_WAKE#_R @ R1369 1 R1370 1 <16,36,45> PCIE_WAKE# <42> LAN_WAKE# RX_P 12 11 15 14 18 17 21 20 2 LAN_LINK# @ 10K_0402_5% C952 10U_0603_6.3V6M 2 TRXN0 TRXP0 TRXN1 TRXP1 TRXN2 TRXP2 TRXN3 TRXP3 ACTIVITY <38> LAN_LINK# <38> 1 C951 1U_0402_6.3V4Z PLT_RST# AR8151/AR8161 RX_N 2 LDO Mode ACTIVITY LAN_LINK# 2 LAN_CLK_SEL R4958 C950 0.1U_0402_16V4Z 32 33 <15> CLK_PCIE_LAN# <15> CLK_PCIE_LAN TX_P 38 39 23 1000P_0402_50V7K 1 2 35 <15> PCIE_PTX_C_DRX_P1 LED_0 LED_1 LED_2 Atheros 1 1U_0402_6.3V4Z 36 <15> PCIE_PTX_C_DRX_N1 TX_N C964 <15> PCIE_PRX_DTX_P1 PCIE_PRX_C_DTX_P1 30 0.1U_0402_16V4Z C965 PCIE_PRX_C_DTX_N1 29 2 .1U_0402_16V7K C963 2 .1U_0402_16V7K C947 1 0.1U_0402_16V4Z C946 1 1U_0402_6.3V4Z <15> PCIE_PRX_DTX_N1 GIGA@ 0.1U_0402_16V4Z C962 Place Close to Chip C948 H --> Overclocking mode L --> Not overclocking mode C 2 0_0402_5% 1U_0402_6.3V4Z U41 PLT_RST# C949 2 4.7K_0402_5% @ <18,23,36,42,45> Place close to Pin34 Close to Pin40 0.1U_0402_16V4Z R525 1 +3V_LAN 1 .1U_0402_16V7K Vendor recommand reseve the PU resistor close LAN chip C1001 10K_0402_5% Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/10/27 2012/10/27 Deciphered Date Title LAN-AR8151/8161 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Thursday, January 05, 2012 Date: Rev 0.3 LA-7983P 3 2 Sheet 1 37 of 60 5 4 3 2 1 MDI3+ T1,T2 P/N to SP050007K00 MDI3T2 2 6 7 8 9 10 @ 11 <37> <37> MDI3+ MDI3- MDI3+ MDI3- 1 6 7 8 9 10 D C970 0.1U_0402_16V4Z GND CT 5 4 3 2 1 RCLAMP3304N.TCT_SLP2626P10-10 D69 @ 1 5 4 3 2 1 @ 2 <37> <37> C972 0.1U_0402_16V4Z MDI2+ MDI2- MDI2+ MDI2- 1 2 3 4 5 6 7 8 TD+ TDCT NC NC CT RD+ RD- TX+ TXCT NC NC CT RX+ RX- 16 15 14 13 12 11 10 9 MDO3+ R4966 MDO3- R4967 MCT0 2 8162@ 1 0_0402_5% 2 8162@ 1 0_0402_5% D MCT0 MDO2+ R4968 MDO2- R4969 2 8162@ 1 0_0402_5% 2 8162@ 1 0_0402_5% EMI Request BOTHHAND_NS0013LF GIGA@ R1376 1 MDI2- 2 MDI2+ C973 1 2 MCT0_1 75_0603_5% 10P_0603_50V T1 2 Place Close to T2 MDI1- @ C974 0.1U_0402_16V4Z <37> <37> MDI0+ MDI0- MDI0+ MDI0- 1 MDI1+ 1 6 7 8 9 10 @ 2 <37> <37> C975 0.1U_0402_16V4Z MDI1+ MDI1- MDI1+ MDI1- C TD+ TDCT NC NC CT RD+ RD- TX+ TXCT NC NC CT RX+ RX- 16 15 14 13 12 11 10 9 MDO0+ MDO0- 2 MCT0 1 LSE-200NX3216TRLF_1206-2 DL1 @ MCT0 Reserve gas tube for EMI go rural solution MDO1+ MDO1- Place Close to T1,T2 C 6 7 8 9 10 BOTHHAND_NS0013LF GND SWR or LDO Mode Update RCLAMP3304N.TCT_SLP2626P10-10 D68 @ 5 4 3 2 1 5 4 3 2 1 11 1 2 3 4 5 6 7 8 For ESD request, 10/26 update reserved LDO@ R4960 2 D74 1 0_0402_5% MDI0MDI0+ LAN_LINK# <37> LAN_LINK# Place Close to T1 R4961 2 SWR@ 1 0_0402_5% 12 R4962 2 LDO@ 11 1 220_0402_5% 220_0402_5% 2 1 R1378 SWR@ +3V_LAN @ C978 470P_0402_50V7K 1 2 B For ESD surge, Modify R1443 near to LAN chip side. MDO3- 8 MDO3+ 7 MDO1- 6 MDO2- 5 MDO2+ 4 MDO1+ 3 MDO0- 2 MDO0+ 1 R1443 <37> ACTIVITY 2 ACTIVITY 1 10 9 220_0402_5% @ C979 470P_0402_50V7K @ 2 CHASSIS_GND JRJ1 1 Green LED- 3 MCT0_1 Green LED+ SHLD2 PR4SHLD1 16 PJDLC05_SOT23-3 15 PR4+ For EMI request, 10/27 update reserved PR2- @ PR3- R4971 2 R4972 2 R4973 2 R4974 2 1 0_0402_5% @ PR3+ 1 0_0402_5% @ PR2+ 1 0_0402_5% B @ PR1SHLD2 PR1+ SHLD1 1 0_0402_5% 14 13 @ Yellow LED- CHASSIS_GND Yellow LED+ C989 1 2 470P_0603_50V8J C990 1 2 0.1U_0603_25V4Z C991 1 2 1U_0603_25V6 LIYO_101007-08203-033 1 +3V_LAN ME@ 2 CHASSIS_GND A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/10/27 Deciphered Date 2012/10/27 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 LAN_Transformer Document Number Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet 1 38 of 60 5 4 3 2 1 +3VS REMOTE1- REMOTE2+ 2 1 C590 0.1U_0402_16V4Z REMOTE2- 1 2 REMOTE1- 3 REMOTE2+ 4 REMOTE2- 5 1 C 2 B E 1 3 2 Q97 MMST3904-7-F_SOT323-3 N13P@ REMOTE1- 2 U27 1 2 R540 10K_0402_5% @ Close to DDR REMOTE1+ @ C586 100P_0402_50V8J 1 1 +3VS 1 C588 @ 2200P_0402_50V7K D 1 REMOTE1+ C587 2200P_0402_50V7K 2 N13P@ Close to VRAM REMOTE1+ Close U27 VDD SMCLK DP1 SMDATA DN1 ALERT# DP2 THERM# DN2 GND 10 EC_SMB_CK2 9 EC_SMB_DA2 EC_SMB_CK2 <15,23,42> EC_SMB_DA2 <15,23,42> near PL402 REMOTE2+ 8 7 @ C589 100P_0402_50V8J 6 C 2 B 2 Q98 @ MMST3904-7-F_SOT323-3 E 3 D REMOTE2- EMC1403-2-AIZL-TR_MSOP10 REMOTE1,2+/-: Trace width/space:10/10 mil Trace length:<8" FD1 H_3P3 H_3P3 H_3P0 H10 HOLEA H11 HOLEA H12 HOLEA H13 HOLEA C591 10U_0603_6.3V6M 1 1 1 1 1 1 1 2 3 4 G5 G6 1 2 1 2 3 4 5 6 1 <42> EC_TACH <42> EC_FAN_PWM 1 2 R581 1 0_0603_5% H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H15 HOLEA H16 HOLEA H_3P0X4P5N H_3P0X4P0N ⚻⫼ 月役桐㇯ ⚻⫼ H17 HOLEA H18 HOLEA B H14 HOLEA 1 H9 HOLEA M/B 1 H8 HOLEA JFAN1 㨊⚻⫼ R 1 H7 HOLEA M/B L 1 H6 HOLEA +5VS FD4 C C FAN1 Conn B FD3 1 A FD2 1 H19 HOLEA 1 H_3P8 H5 HOLEA 1 H_3P8 VGA_R H4 HOLEA 1 1 H_3P8 VGA_L 1 1 H3 HOLEA 1 CPU H2 HOLEA 1 H1 HOLEA 1 Address 1001_101xb C H_5P5N H_3P0N H_3P3 B ACES_85205-04001 ME@ E 2P8 * 8pcs A A Issued Date Compal Electronics,Ltd. Compal Secret Data Security Classification 2011/10/27 Deciphered Date 2012/10/27 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Fintek-Thermal IC/FAN/screw Document Number Date: Thursday, January 05, 2012 5 4 3 2 Rev 0.3 LA-7983P Sheet 1 39 of 60 A B C D E F G H SATA HDD Conn. BT MODULE CONN JHDD1 <14> SATA_ITX_DRX_P0 <14> SATA_ITX_DRX_N0 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 <14> SATA_DTX_C_IRX_N0 <14> SATA_DTX_C_IRX_P0 1 1 <19,36> PCH_BT_ON# R632 BT@ 100K_0402_5% 2 C596 1 C597 1 1 2 3 4 5 6 7 SATA_ITX_DRX_P0 SATA_ITX_DRX_N0 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_DTX_IRX_N0 SATA_DTX_IRX_P0 1 C709 BT@ 0.1U_0402_16V4Z 1 2 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 +3VS +3VS_BT +3VS D S 3 1 +3VS_BT_R 2 0_0603_5% R583 BT@ 1 30mils 1 2 G Q104 PMV65XP_SOT23-3~D BT@ 2 1 R550 2 0_0805_5% +5VS +5V_HDD 0.1U_0402_16V4Z C712 BT@ +5V_HDD +3VS JBT1 <18> <18> <36> 1 2 3 4 5 6 USB20_P13 USB20_N13 USB20_P13 USB20_N13 BTON_LED:NC BT_ACTIVE BT_ACTIVE GND RX+ RXGND TXTX+ GND 1 2 3 4 5 G1 6 G2 1 7 8 2 1 C598 1000P_0402_50V7K 2 1 C599 0.1U_0402_16V4Z 2 1 C600 @ 1U_0402_6.3V6K 2 1 C601 @ 10U_0603_6.3V6M 2 1 C602 10U_0603_6.3V6M 2 @ C603 0.1U_0402_16V4Z 3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND Reserved GND 12V 12V 12V GND GND 23 24 SUYIN_127043FB022G278ZR ME@ ACES_87213-0600G ME@ ODD Power Control 2 @ 1 +5VALW 1 2 1 1 2 1 2 2 1 OUT GND 2 1 2 3 JODD1 1 Q99 PMV65XP_SOT23-3~D @ 1 R675 2 100K_0402_5% @ IN SATA ODD FFC Conn. 1 G R552 @ 10K_0402_5% 2 +5V_ODD D S 3 <19> ODD_EN 2 JUMP_43X79 +5VS @ R568 10K_0402_5% 2 J9 @ C607 0.01U_0402_16V7K 2 @ C604 0.1U_0402_16V4Z <14> SATA_ITX_C_DRX_P2 <14> SATA_ITX_C_DRX_N2 <14> SATA_DTX_C_IRX_N2 <14> SATA_DTX_C_IRX_P2 SATA_ITX_C_DRX_P2 SATA_ITX_C_DRX_N2 C605 1 C606 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_ITX_DRX_P2_15 SATA_ITX_DRX_N2_15 SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 C618 1 C617 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K 1 R710 check ODD_DA# SATA_DTX_IRX_N2_15 SATA_DTX_IRX_P2_15 2 ODD_DETECT# @ 0_0402_5% +5V_ODD @ C608 10U_0603_6.3V6M <18,42> ODD_DA# +3VS 1 2 3 4 5 6 7 8 9 10 11 12 1 R555 2 10K_0402_5% 1 2 3 4 5 6 7 8 9 10 GND GND ACES_87056-01001-001 Q100 DTC124EKAT146_SC59-3 @ ME@ 3 3 4 4 Compal Secret Data Security Classification 2011/10/27 Issued Date Deciphered Date 2012/10/27 Title Compal Electronics, Inc. HDD/ODD/BT Connector THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D E F Thursday, January 05, 2012 G Rev 0.3 LA-7983P Sheet 40 of H 60 5 4 3 2 1 CX20671 High Definition Audio Codec SoC With Integrated Class-D Stereo Amplifier. An integrated 5 V to 3.3 V Low-dropout voltage regulator (LDO). An integrated 3.3 V to 1.8V Low-dropout voltage regulator (LDO). D D 1 +3VS HDA_RST_AUDIO# +3VS 2 @ Layout Note:Path from +5VS to LPWR_5.0 RPWR_5.0 must be very low resistance (<0.01 ohms) 1 @ 2 1 2 HDA_RST_AUDIO# @ 2 C641 @ 1 22P_0402_50V8J C578 1 22P_0402_50V8J C577 2 HDA_BITCLK_AUDIO @ AVDD_3.3 pinis output of internal LDO. NOT connect to external supply. 22P_0402_50V8J C576 1 0.1U_0402_16V4Z C625 2 4.7U_0603_6.3V6K C592 2 1 100P_0402_50V8J 1 2 2 @ ESD Reserve 0_0402_5% <42> EAPD <42> EC_MUTE# 10 PC_BEEP EAPD active low 0=power down ex AMP 1=power up ex AMP 2 R519 1 R496 0_0402_5% 38 37 CX_GPIO0 PORTB_R PORTB_L B_BIAS SPK_L2+ SPK_L1- 11 13 SPK_R2+ SPK_R1- 16 14 Internal SPEAKER C_BIAS PORTC_R PORTC_L GPIO0/EAPD# GPIO1/SPK_MUTE# DMIC_CLK DMIC_1/2 NC NC NC LEFT+ LEFTAVEE FLY_P FLY_N RIGHT+ RIGHT- 2 4.7U_0603_6.3V6K 0.1U_0402_16V4Z C595 2 4.7U_0603_6.3V6K C628 C632 0.1U_0402_16V4Z C594 @ 1 35 34 33 1 2 5.11K_0402_1% R491 1 1 R494 2 20K_0402_1% 2 39.2K_0402_1% R458 SENSE_A +3VS Port B A MIC_JD PLUG_IN C MIC_JD <43> Port PLUG_IN <43> Please bypass caps very close to device. 2.2U_0603_6.3V6K 2 C621 1 2 C622 1 EXT_MIC_R_C EXT_MIC_L_C +MICBIASB 32 31 30 R4946 R4947 3.3K_0402_5% 3.3K_0402_5% +MICBIASB R517 100_0402_1% R4948 100_0402_1% +MICBIASC MIC_INR MIC_INL EXT_MIC_R <43> EXT_MIC_L <43> External MIC Internal MIC R481 R493 24 25 39 Changed from 15ohm to 39ohm for "POP"noise. 1 C635 EXT_MIC_R EXT_MIC_L 2.2U_0603_6.3V6K 23 22 21 19 20 Sense resistors must be connected same power that is used for VAUX_3.3 SENSE_A 2 1U_0402_6.3V6K CX20671-21Z_QFN40_6X6 41 2 0_0402_5% 1 EXT_MIC_L_CR EXT_MIC_R_CR 36 GND Short GND and GNDA on GND1 & GND2 on layout 2 PC_BEEP PORTA_R PORTA_L 40 1 0.1U_0402_16V4Z C620 SENSE_A @ 1 2 4.7U_0603_6.3V6K C631 C638 BIT_CLK SYNC SDATA_IN SDATA_OUT 2 12 15 17 1 @ 2 C609 HDA_SDOUT_AUDIO 2 1 1 1 2 1 1 2 2 39_0402_5% 39_0402_5% HP_OUTR <43> HP_OUTL <43> Headphone 4.7U_0603_6.3V6K 5 8 6 4 LPWR_5.0 RPWR_5.0 CLASS-D_REF 1 0.1U_0402_16V4Z HDA_BITCLK_AUDIO HDA_SYNC_AUDIO 2 33_0402_5% RESET# 2 +5VS C629 R495 1 9 2 1 0.1U_0402_16V4Z <14> HDA_BITCLK_AUDIO <14> HDA_SYNC_AUDIO <14> HDA_SDIN0 <14> HDA_SDOUT_AUDIO HDA_RST_AUDIO# @ AVDD_3.3 AVDD_5V AVDD_HP @ <14> HDA_RST_AUDIO# 1 27 28 26 U25 29 2 FILT_1.65 1 3 7 2 18 2 FILT_1.8 VDD_IO VAUX_3.3 DVDD_3.3 1 0.1U_0402_16V4Z 10U_0603_6.3V6M C634 2 +5VS 10 mils C626 1 0.1U_0402_16V4Z 1 1U_0402_6.3V6K C623 1R528 @ 2 0_0402_5% @ GND 1 0.1U_0402_16V4Z C584 2 C R516 @ 1 1 R515 2 0_0402_5% +LDO_OUT_3.3V 1 0_0402_5% 2 B R351 @ 4.7K_0402_5% HDA_SDOUT_AUDIO 1U_0402_6.3V6K C585 2 @ 0.1U_0402_16V4Z 2 1 2 C593 +3VALW 1 22P_0402_50V8J C575 R527 1 2 0.1U_0402_16V4Z C581 C579 2 1 0.1U_0402_16V4Z C582 1 4.7U_0603_6.3V6K C583 2 4.7U_0603_6.3V6K C580 +3VS +3VS EMI HDA_SYNC_AUDIO 1 B GNDA PC Beep EC Beep <42> ICH Beep <14> HDA_SPKR 1 2 C619 0.1U_0402_16V4Z 1 2PC_BEEP1 C612 0.1U_0402_16V4Z R492 1 2 33_0402_5% PC_BEEP 1 BEEP# @ R480 10K_0402_5% Place close to Codec chip close to Codec 1 C640 0.1U_0402_16V4Z 2 @ MIC_INL EMI Request 2 Issued Date 2 1 2 1 2 2011/10/27 Deciphered Date 4 3 2 2 3 1 2 3 4 GND1 GND2 A ACES_88231-04001 @ D70 TVNST52302AB0 C/C SOT523 D71 @ TVNST52302AB0 C/C SOT523 Compal Electronics, Inc. 2012/10/27 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 5 6 Compal Secret Data Security Classification @ 2 1 1 1 1 2 3 MIC_INR 1 2 2.2U_0603_6.3V6K 1000P_0402_50V7K C633 1 GNDA C636 0.1U_0402_16V4Z WM-64PCY_2P 45@ MIC_INTERNAL JSPK1 ME@ 1 2 3 4 SPK_R1-_CONN SPK_R2+_CONN SPK_L1-_CONN SPK_L2+_CONN C610 MIC1 1 2 2 0_0603_5% 2 0_0603_5% 2 0_0603_5% 2 0_0603_5% wide 30MIL 2 A 1 1 1 1 1000P_0402_50V7K C611 R518 2.2K_0402_5% L41 L42 L43 L46 1000P_0402_50V7K C624 1 SPK_R1SPK_R2+ SPK_L1SPK_L2+ 1000P_0402_50V7K C627 2 EMI Request: SM01001678L +MICBIASC Title CX20671 Codec Size Document Number Custom Rev 0.3 LA-7983P Date: Thursday, January 05, 2012 Sheet 1 41 of 60 R595 1 2 47K_0402_5% KSO1 @ R597 1 2 47K_0402_5% KSO2 @ +3VALW +3VS R600 1 2 EC_SMB_CK1 2.2K_0402_5% R604 R601 2.2K_0402_5% 1 R602 2.2K_0402_5% 2 EC_SMB_DA1 2.2K_0402_5% <43> <43> EC_SMB_CK2 EC_SMB_DA2 2 @ C666 100P_0402_50V8J <48,49> <48,49> <15,23,39> <15,23,39> EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 <16> PM_SLP_S3# <16> PM_SLP_S5# <19> EC_SMI# +3VS 1 <33> CMOS_ON# <43> RF_LED# RF_LED# R605 10K_0402_5% 2 EC_SMI# ODD_DA# EC_INVT_PWM EC_TACH EC_PME# EC_TX EC_RX PCH_PWROK EC_FAN_PWM NUM_LED# <18,40> ODD_DA# <33> EC_INVT_PWM <39> EC_TACH EC_TACH <36,43> EC_TX <36,43> EC_RX <16> PCH_PWROK 2 <39> EC_FAN_PWM <43> NUM_LED# 1 77 78 79 80 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 GPIO0A GPIO0B GPIO0C GPIO0D EC_INVT_PWM/GPIO11 FAN_SPEED1/GPIO14 EC_PME#/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PCH_PWROK/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A GPIO Bus GPIO SUSCLK 0_0402_5% 122 123 XCLKI/GPIO5D XCLKO/GPIO5E 1 1 <16> EC_RTCX1 SUSCLK_R 1 2 C93 20P_0402_50V8 EC_RTCX1 1 2 SPIDI/GPIO5B SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04 PROCHOT_IN/GPXIOA05 H_PROCHOT#_EC/GPXIOA06 VCOUT0_PH/GPXIOA07 GPO BKOFF#/GPXIOA08 PBTN_OUT#/GPXIOA09 PCH_APWROK/GPXIOA10 SA_PGOOD/GPXIOA11 ECAGND R740 100K_0402_5% check @ 32.768KHZ_12.5PF_9H03200413 OSC 4 OSC NC 3 NC 1 2 C347 @ 2 18P_0402_50V8J 1 1 1 BRDID R695 33K_0402_5% 1 +5VALW +3VALW 83 84 85 86 87 88 97 98 99 109 R694 100K_0402_5% R588 10K_0402_5% @ 2 EC_FAN_PWM IMVP_IMON <55> 68 70 71 72 1 R593 2 10K_0402_5% USB_ON# EC_MUTE# <41> USB_ON# <44,45> TP_CLK TP_DATA EAPD <41> TP_CLK <43> TP_DATA <43> CPU1.5V_S3_GATE VGA_AC_DET 2 R750 NTC_V_R 1 0_0402_5% AC_IN/GPXIOD01 EC_ON/GPXIOD02 ON/OFF/GPXIOD03 LID_SW#/GPXIOD04 SUSP#/GPXIOD05 GPXIOD06 PECI_KB9012/GPXIOD07 V18R 119 120 126 128 73 74 89 90 91 92 93 95 121 127 100 101 102 103 104 105 106 107 108 PCH_PWR_EN R594 USB_ON# 1 2 +5VS 10K_0402_5% CPU1.5V_S3_GATE <10,53> VGA_AC_DET <23,54> ME_FLASH <14> NTC_V <48> PCH_PWR_EN ENBKL LAN_PWR_ON# BATT_CHG_LED# CAPS_LED# LAN_PWR_ON# <37> BATT_CHG_LED# <43> CAPS_LED# <43> PWR_LED# <43> BATT_LOW_LED# <43> SYSON <45,46,51> VR_ON <55> PM_SLP_S4# <16> BATT_LOW_LED# SYSON EC_RSMRST# <16> EC_LID_OUT# <19> EC_LID_OUT# Turbo_V H_PROCHOT#_EC MAINPWON_EC BKOFF# PBTN_OUT# 110 112 114 115 116 117 118 LID_SW# SUSP# PCH_HOT#_R PECI_KB9012 124 +V18R <46,48> TP_CLK R591 1 2 4.7K_0402_5% TP_DATAR592 1 2 4.7K_0402_5% 1 BATT_TEMP +3VALW 2 C663 100P_0402_50V8J 1 ACIN PCH_PWR_EN 2 R599 2 ACIN EC_ON R792 2 @ 1 R669 1 0_0402_5% 2 43_0402_1% @1 100K_0402_5% 100P_0402_50V8J 1 2 R522 @ 4.7K_0402_5% <33> +3VLP KB9012A2 work around R4945 @ 47K_0402_5% <55> VR_HOT# VR_HOT# Turbo_V <48> PROCHOT <48> MAINPWON <48,50> 1 0_0402_5% R757 2 1 R4978 2 0_0402_5% @ BKOFF# <33> PBTN_OUT# <16> PCH_APWROK <16> SA_PGOOD <52> 1 R737 2 ACIN <16,49> EC_ON <43,50> ON/OFF# <43> LID_SW# <43> SUSP# <10,25,46,51,52,53,54> PCH_HOT# <15> H_PECI <6,19> H_PROCHOT# 0_0402_5% D S 2 H_PROCHOT#_EC <6,48> 1 G Q37 2N7002H_SOT23-3 2 C493 47P_0402_50V8J +3VALW R606 10K_0402_5% 1 C667 4.7U_0603_6.3V6K R609 2 2 1 LAN_WAKE# <37> 0_0402_5% 2 R610 KB9012QF A3 LQFP 128P_14X14 SYSON @ S IC KB9012QF A3 LQFP 128P KB CONTROLLER 1 0_0402_5% @ EMC Request R120 @ 10M_0402_5% Y5 MP PVT DVT EVT 1 BATT_TEMP <48> GPU_IMON <54> <48,49> SUSCLK_R PN : SA00004OB20 V V V +3VALW C664 ENBKL/GPIO40 PECI_KB930/GPIO41 FSTCHG/GPIO50 BATT_CHG_LED#/GPIO52 CAPS_LED#/GPIO53 PWR_LED#/GPIO54 BATT_LOW_LED#/GPIO55 SYSON/GPIO56 VR_ON/GPIO57 PM_SLP_S4#/GPIO59 GPI max 2 SPI Flash ROM GND/GND GND/GND GND/GND GND/GND GND0 R611 ADP_I BRDID SPI Device Interface @ R608 10K_0402_5% 2 EC_VDD/AVCC EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD0 EC_VDD/VCC 67 9 22 33 96 111 125 EC_SMB_CK1/GPIO44 EC_SMB_DA1/GPIO45 SM EC_SMB_CK2/GPIO46 EC_SMB_DA2/GPIO47 EC_MUTE#/GPIO4A USB_EN#/GPIO4B CAP_INT#/GPIO4C EAPD/GPIO4D TP_CLK/GPIO4E TP_DATA/GPIO4F CPU1.5V_S3_GATE/GPXIOA00 WOL_EN/GPXIOA01 HDA_SDO/GPXIOA02 VCIN0_PH/GPXIOD00 11 24 35 94 113 2 1 @ C665 100P_0402_50V8J 2 1 KSO16 KSO17 +3VS N13P@ BATT_TEMP 1 0_0402_5% VGA_IMVP_IMON 2 R758 1 +3VALW 63 64 65 66 75 76 EC_MUTE# PS2 Interface V V V 3 KSI[0..7] 33K +/- 5% VAD_BID 0 V 0.289 0.538 0.875 EC_PME# 1 3 S KSI[0..7] KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 BATT_TEMP/GPIO38 GPIO39 ADP_I/GPIO3A GPIO3B GPIO42 IMON/GPIO43 DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D IREF/GPIO3E CHGVADJ/GPIO3F DA Output <41> <43> <49> V V V typ V AD_BID 0 V 0.250 0.503 0.819 D KSO[0..15] AD Input BEEP# NOVO# ACOFF 18K +/- 5% min PCI_PME# <18> Q102 @ 2N7002_SOT23 2 G <43> <43> 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 PWM Output CLK_PCI_EC PCIRST#/GPIO05 EC_RST# EC_SCII#/GPIO0E GPIO1D BEEP# NOVO# ACOFF VAD_BID 0 V 0.216 0.436 0.712 1 1 KSO[0..15] GPIO0F BEEP#/GPIO10 GPIO12 ACOFF/GPIO13 21 23 26 27 R695 0 8.2K +/- 5% 1 EC_SCI# BATT_LEN# GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC & MISC LPC_AD0 0 1 2 3 U31 2 <19> <48> 2 2 .1U_0402_16V7K C492 <18> CLK_PCI_EC <18,23,36,37,45> PLT_RST# 47K_0402_5% C661 0.1U_0402_16V4Z EC_RST# EC_SCI# BATT_LEN# 12 13 37 20 38 10_0402_5% 2 R590 LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 1 2 3 4 5 7 8 10 2 100K +/- 5% Board ID 2 1 1 @ R589 2 +EC_VCCA AGND/AGND 2 <19> GATEA20 <19> KBRST# <14> SERIRQ <14,36> LPC_FRAME# <14,36> LPC_AD3 <14,36> LPC_AD2 <14,36> LPC_AD1 <14,36> LPC_AD0 2 1 69 1 22P_0402_50V8J 2 1 C658 1000P_0402_50V7K 2 @ C660 2 2 1 C657 1000P_0402_50V7K 2 ECAGND 2 L45 FBM-11-160808-601-T_0603 1 +3VALW 1000P_0402_50V7K 1 C655 0.1U_0402_16V4Z C656 0.1U_0402_16V4Z +EC_VCCA C659 1 C662 0.1U_0402_16V4Z 1 1 C654 0.1U_0402_16V4Z 1 C653 0.1U_0402_16V4Z +3VALW 2 3.3V +/- 5% Vcc R694 +3VALW L44 FBM-11-160808-601-T_0603 1 +3VLP 2 +3VALW 1 +3VALW 2 C367 @ 18P_0402_50V8J 2 Compal Secret Data Security Classification Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title Compal Electronics, Inc. BIOS & EC I/O Port THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Thursday, January 05, 2012 Rev 0.3 LA-7983P Sheet 42 of 60 INT_KBD Conn. KSI[0..7] KSI[0..7] KSO[0..17] EC DEBUG PORT +3VALW <36,42> EC_TX <36,42> EC_RX JKB1 <42> KSO16 C693 1 2 @ 100P_0402_50V8J KSO17 C692 1 2 @ 100P_0402_50V8J KSO2 C668 1 2 @ 100P_0402_50V8J KSO1 C669 1 2 @ 100P_0402_50V8J KSO15 C670 1 2 @ 100P_0402_50V8J KSO7 C671 1 2 @ 100P_0402_50V8J KSO6 C672 1 2 @ 100P_0402_50V8J KSI2 C673 1 2 @ 100P_0402_50V8J KSO8 C674 1 2 @ 100P_0402_50V8J KSO5 C675 1 2 @ 100P_0402_50V8J KSO13 C676 1 2 @ 100P_0402_50V8J KSI3 C677 1 2 @ 100P_0402_50V8J KSO12 C678 1 2 @ 100P_0402_50V8J KSO14 C679 1 2 @ 100P_0402_50V8J KSO11 C680 1 2 @ 100P_0402_50V8J KSI7 C681 1 2 @ 100P_0402_50V8J KSO10 C682 1 2 @ 100P_0402_50V8J KSI6 C683 1 2 @ 100P_0402_50V8J KSO3 C684 1 2 @ 100P_0402_50V8J KSI5 C685 1 2 @ 100P_0402_50V8J KSO4 C686 1 2 @ 100P_0402_50V8J KSI4 C687 1 2 @ 100P_0402_50V8J KSI0 C688 1 2 @ 100P_0402_50V8J KSO9 C689 1 2 @ 100P_0402_50V8J KSO0 C690 1 2 @ 100P_0402_50V8J KSI1 C691 1 2 @ 100P_0402_50V8J <42> <42> 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15 KSO16 KSO17 KSO16 KSO17 Reserve for ESD. CONN PIN define need double check JP3 1 2 3 4 KSO[0..17] the same wtih G770 <42> ME@ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND GND ACES_88514-3001 1 2 3 4 Power Bottom Board Conn. 8pin ACES_85205-0400 ME@ Card Reader/Audio Jack SB CONN +5VALW JPWRB1 2 +3VALW +3VLP 2 1 EXT_MIC_L EXT_MIC_R MIC_JD R725 1 2 0_0402_5% 1 2 R722 @ 0_0402_5% ON/OFFBTN# DAN202UT106_SC70-3 3 ON/OFF# 2 51_ON# ON/OFF# 1 1 0_0402_5% 1 0_0402_5% R4954 R4955 ACES_88058-080N EMI ME@ D24 PJSOT24C 3P C/A SOT-23 @ 1 51_ON# NOVO_BTN# 1 ON/OFF# USB20_P11 2 USB20_N11 2 <18> USB20_P11 <18> USB20_N11 NOVO_BTN# 2 1 3 1 2 0_0402_5% ON/OFFBTN# <41> EXT_MIC_L <41> EXT_MIC_R <41> MIC_JD +3VS 2 NOVO# NOVO# 1 2 @ SHORT PADS Bottom Side <42> R720 J11 1 GND GND HP_OUTL HP_OUTR PLUG_IN D26 R535 @ 100K_0402_5% 1 6 5 TOP Side JCR1 <41> HP_OUTL <41> HP_OUTR <41> PLUG_IN C987 1000P_0402_50V7K R701 100K_0402_5% 4 2 3 2 9 10 3 Power Button @ R642 100K_0402_5% R532@ 100K_0402_5% 2 SMT1-05_4P SW3 1 NOVO_BTN# ON/OFFBTN# 1 2 3 4 5 6 7 8 1 ON/OFF switch +3VALW 2 +3VLP 1 2 3 4 5 6 7 8 <42> NUM_LED# <42> CAPS_LED# <42> PWR_LED# 1 2 3 4 5 6 7 8 USB20_P11_C 9 USB20_N11_C 10 11 12 13 14 WCM-2012-900T_4P USB20_N11 4 USB20_P11 1 4 1 L81 3 2 3 USB20_N11_C 2 USB20_P11_C 1 2 3 4 5 6 7 8 9 10 11 12 GND GND ACES_88058-120N ME@ @ <42> 51_ON# <47> 1 2 G Q106 @ 2N7002_SOT23-3 EC_ON EC_ON 2 <42,50> D 3 D23 @ DAN202UT106_SC70-3 S 1 R639 @ 10K_0402_5% To TP/B Conn. +5VS JTP1 LED B/D Conn, ME@ C696 8 7 0.1U_0402_16V4Z 2 SW/L SW/R C698 @ 100P_0402_50V8J @ D15 PSOT24C_SOT23-3 @ 1 2 @ JLED1 R617 6 5 4 3 2 1 1 2 100K_0402_5% LID_SW# <42> +5VALW +3VALW +5VS LID_SW# <42> PWR_LED# <42> BATT_LOW_LED# <42> BATT_CHG_LED# RF_LED# <42> RF_LED# ACES_88058-060N .1U_0402_16V7K C491 2 1 .1U_0402_16V7K C490 1 2 @ C697 100P_0402_50V8J TP_CLK TP_DATA 1 TP_CLK TP_DATA 3 <42> <42> 6 5 4 3 2 1 +3VALW GND GND <14> HDD_LED# SW/L SW/R 1 2 pin 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 G1 14 G2 15 16 ACES_85202-1405L ME@ 1 VDD 2 CLK 3 4 5 DAT L Compal Secret Data Security Classification R GND Issued Date 2011/10/27 Deciphered Date 2012/10/27 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: Compal Electronics, Inc. ROM/KBD/PWR/CR/LED/TP Conn. Document Number Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet 43 of 60 A B C D 1 E 1 Left Ext.USB Conn. +USB_VCCB +5VALW +USB_VCCB C985 0.1U_0402_16V4Z 2 1 <42,45> USB_ON# GND VOUT VIN VOUT VIN VOUT EN FLG 8 7 6 5 220U_6.3V_M USB_OC0# USB_OC0# <18> 6.3ĭ * 5.9 SF000001500 USB20_N1 R4951 2 @ 1 0_0402_5% USB20_N1_C 2 USB20_P1 R4952 2 @ 1 0_0402_5% USB20_P1_C 3 2 U66 1 +USB_VCCB 1 1 <18> USB20_N1 + C984 <18> USB20_P1 470P_0402_50V7K 2 2 4 3 C983 1 2 3 4 JUSB3 W=80mils Left USB PORT X1 G547I2P81U_MSOP8 5 VCC GND1 D- GND2 D+ GND3 6 7 8 GND GND4 OCTEK_USB-04APEB ME@ 4 USB20_P1 1 C986 @ 1000P_0402_50V7K 2 4 1 L80 3 2 3 USB20_N1_C 2 USB20_P1_C 2 1 1 2 USB20_N1 WCM-2012-900T_4P D72 @ PJDLC05_SOT23-3 Update to SM070001S00 for EMI request Right Ext.USB Cable Conn. 3 3 +5VALW JUSB4 +USB_VCCA +USB_VCCA 8 7 RIGHT USB PORT X1 W=80mils <42,45> USB_ON# 220U_6.3V_M USB_OC4# USB_OC4# <18> R870 2 R871 2 @ @ 1 0_0402_5% 1 0_0402_5% USB20_N9_C USB20_P9_C 2 GND VOUT VIN VOUT VIN VOUT EN FLG USB20_N9 USB20_P9 USB20_P9 4 USB20_N9 1 C730 @ 1000P_0402_50V7K 2 4 3 1 L67 2 6 5 4 3 2 1 ACES_88058-060N ME@ WCM-2012-900T_4P 1 GND GND 6 5 4 3 2 1 6.3ĭ * 5.9 SF000001500 G547I2P81U_MSOP8 3 USB20_P9_C 2 USB20_N9_C 1 C731 0.1U_0402_16V4Z 2 1 C732 8 7 6 5 3 U67 1 2 3 USB_ON# 4 +USB_VCCA 1 1 <18> USB20_N9 + <18> USB20_P9 C733 470P_0402_50V7K 2 2 D28 @ PJDLC05_SOT23-3 Update to SM070001S00 for EMI request 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/10/27 Deciphered Date 2012/10/27 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C 4 D USB ext. ports Document Number Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet E 44 of 60 5 4 +1.5V to +1.05V Transfer GND 1 2 1 2 D27 @ 1 U3RXDN1 U3RXDN2 9 1 U3RXDN2 U3RXDP1 8 2 U3RXDP1 U3RXDP2 8 2 U3RXDP2 U3TXDN1 7 4 U3TXDN1 U3TXDN2 7 4 U3TXDN2 U3TXDP1 6 5 U3TXDP1 U3TXDP2 6 5 U3TXDP2 3 3 2 2 1 YSCLAMP0524P_SLP2510P8-10-9 2 GND VDD I/O1 I/O3 GND Intel_PCH_USB2.0 +1.05VDD <18> USB20_N3 <18> USB20_P3 R730 2 IU3@ 1 0_0402_5% R640 2 IU3@ 1 0_0402_5% EU3@ 1 C835 PCIE_PRX_C_DTX_P4 1 C834 PCIE_PRX_C_DTX_N4 EU3@ 7 8 <15> PCIE_PTX_C_DRX_P4 <15> PCIE_PTX_C_DRX_N4 1 2 4 5 +3V C837 EU3@ 1000P_0402_50V7K <18,23,36,37,42> PLT_RST# <18> 47 PLT_RST#_USB3 PCIE_WAKE#_USB3 48 10 CLKREQ_USB3 10/14 R1172 modify to 300K +3V 1 C832 1U_0402_6.3V6K EU3@ R1172 1 EU3@ 2 2 +3V PERXP PERXN U2DP2 U3RXDP2 PERSTB PEWAKEB PECREQB USB3_XT1 24 USB3_XT2 23 R776 2 R772 2 U3RXDN2_R R763 2 EU3@ 1 0_0402_5% U3RXDN2_L 38 45 U3TXDN2_R C846 1 U2DN2_R R774 2 U2DN2_L 1 U2DP2_L 4 1 2 4 3 1 U3TXDN1 U2DM1 U2DP1 U3RXDP1 U3RXDN1 1 1 2 2 +3V +3V C843 29 36 U3TXDN1_R U2DN1_R C845 EU3@ 1 R759 2 EU3@ 2 .1U_0402_16V7K U3TXDN1_L 1 0_0402_5% U2DN1_L 35 31 U2DP1_R U3RXDP1_R R754 2 EU3@ R760 2 EU3@ 1 0_0402_5% 1 0_0402_5% U2DP1_L U3RXDP1_L 32 U3RXDN1_R R762 2 EU3@ 1 0_0402_5% U3RXDN1_L EU3@ 1 8 7 6 SPI_CLK_USB USB_SO_SPI_SI 5 R1175 10K_0402_5% EU3@ 2 2 U53 2 4 3 U3RXDN2 3 U3RXDP2 2 U3TXDP2_L .1U_0402_16V7K <42,44> USB_ON# 1 4 1 2 4 3 1 2 3 4 5 6 7 8 9 LP2 U3RXDN2 U3RXDP2 @ U3TXDN2 U3TXDP2 2 U3TXDN2 3 U3TXDP2 VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+ C GND GND GND GND 10 11 12 13 OCTEK_USB-09EAEB ME@ L53 IU3@ @ 1 R563 2 @ 0_0402_5% <18> USB20_P2 <18> USB20_N2 2 2 R741 1 IU3@ 0_0402_5% IU3@ 1 R755 0_0402_5% U2DP1_L 1 U2DN1_L 4 1 2 4 L51 3 2 U2DP1 3 U2DN1 R1152 EU3@ 1 2 B +USB3_VCCA 1 R564 2 @ 0_0402_5% Intel_PCH_USB3.0 R773 U3RXDN1_L IU3@ 1 0_0402_5% R739 2 U3RXDP1_L IU3@ 1 0_0402_5% 2 WCM-2012-900T_4P 1 1 2 2 U3RXDN1 W=80mils 3 U3RXDP1 1 2 3 4 5 6 7 8 9 4 3 U2DN1 U2DP1 U3RXDN1 U3RXDP1 1 R565 2 @ 0_0402_5% <18> USB3_TX3_N 8 7 6 5 <18> USB3_TX3_P USB_OC1# USB_OC1# <18> 1 1 4 U3TXDP1_L C847 IU3@ .1U_0402_16V7K for DFT G547I2P81U_MSOP8 .1U_0402_16V7K C849 IU3@ 1 2 U3TXDN1_L 2 LP1 JUSB1 4 U3TXDN1 U3TXDP1 WCM-2012-900T_4P 1 2 4 L49 3 2 U3TXDN1 3 U3TXDP1 VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+ GND GND GND GND 10 11 12 13 OCTEK_USB-09EAEB ME@ 1 R546 2 @ 0_0402_5% EU3@ 2A/Active Low R1176 47K_0402_5% SPI_CS_USB# USB_SI_SPI_SO Place TX AC coupling Cap (C843~C850). Close to connector 1 C736 220U_6.3V_M 6.3ĭ * 5.9 SF000001500 + 2 1 C735 470P_0402_50V7K A 2 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 12/07 update to SA00002AA00 2011/10/27 Deciphered Date 2012/10/27 Title USB3.0/Left USB Ports THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 D WCM-2012-900T_4P U35 USB_ON# W=80mils U2DN2 U2DP2 WCM-2012-900T_4P W=80mils EU3@ 1 VCC CS# 2 HOLD# SO 3 SCK WP# 4 SI GND AT25F512AN-10SU-2.7_SO8~D 1 2 .1U_0402_16V7K U3TXDP1_L +USB3_VCCA GND VOUT VIN VOUT VIN VOUT EN FLG U2DN2 +USB3_VCCA 2 1 R561 2 @ 0_0402_5% 1 2 3 4 4 @ @ L50 1 2 1 2 1 R1177 10K_0402_5% EU3@ A C895 .1U_0402_16V7K EU3@ U2DP2 1 R638 2 0_0402_5% <18> USB3_RX3_P for DFT 1 C850 IU3@ 2 U3TXDN2_L .1U_0402_16V7K C848 <18> USB3_RX3_N C704 .1U_0402_16V7K 1 2 I/O3 +5VALW JUSB2 4 2 10K_0402_5% 2 10K_0402_5% 1.6K_0402_1% +5VALW +3V 1 <18> USB3_TX4_P U3TXDP1_R 26 RREF C897 12P_0402_50V8J EU3@ 10/14 Modify to +3V from +3VALW I/O1 5 1 R562 2 @ 0_0402_5% 24MHZ_12PF_X5H024000DC1H 1 EU3@ 1 C898 15P_0402_50V8J EU3@ 2 2 C836 1000P_0402_50V7K EU3@ 1 <18> USB3_TX4_N 28 GND Y7 U2DN2 3 1 R636 2 0_0402_5% 2 1 CLKREQ_USB3 2 WCM-2012-900T_4P 1 XT1 XT2 IC(L) VDD @ 1 R743 2 0_0402_5% @ 49 D <15> CLKREQ_USB30# 3 S 1 27 EU3@ R1180 100_0402_1% R745 EU3@ 10K_0402_5% 2 G EU3@ Q121 SSM3K7002FU_SC70-3 R709 U3RXDN2_L IU3@ 1 0_0402_5% R714 2 U3RXDP2_L IU3@ 1 0_0402_5% 2 Intel_PCH_USB2.0 PONRSTB SPISCK SPICSB SPISI SPISO GND 6 18 20 PPON2 PPON1 SMIB R1161 EU3@ OCI2B 1 OCI1B 1 R1162 EU3@ 17 19 OCI2B OCI1B EU3@ +3V U2DP2_R U3RXDP2_R 41 U3TXDP2_R C844 1 +3V U3TXDP1 SPI_CLK_USB 15 SPI_CS_USB# 14 USB_SO_SPI_SI 16 USB_SI_SPI_SO 13 44 40 EU3@ 2 .1U_0402_16V7K U3TXDP2_L EU3@ 2 .1U_0402_16V7K U3TXDN2_L 1 0_0402_5% U2DN2_L EU3@ EU3@ 1 0_0402_5% U2DP2_L EU3@ 1 0_0402_5% U3RXDP2_L 37 2 B 11 2 300K_0402_5% 1 2 D67 1 2 1 1SS355TE-17_SOD323-2 EU3@ C894 1U_0402_6.3V6K 10/14 R747 modify to 430K C832 to 1U. 46 SMIB SMIB 25 3 U3TXDP2 U3TXDN2 U2DM2 I/O4 AZC099-04S.R7G_SOT23-6 L54 U3RXDN2 1 R4970 2 10K_0402_5% EU3@ PLT_RST#_USB3 <18> USB3_RX4_P PETXP PETXN UPD720202K8-701-BAA_QFN48_7X7 EU3@ 1 R747 2 430K_0402_5% <18> USB3_RX4_N PECLKP PECLKN 10/20 add 10k pu 1 U2DP1 1 R742 2 0_0402_5% AVDD33 AVDD33 39 33 30 21 42 VDD10 VDD10 VDD10 VDD10 VDD10 6 43 34 22 9 VDD10 VDD10 VDD33 VDD33 12 2 G 1 .1U_0402_16V7K2 .1U_0402_16V7K2 <15> PCIE_PRX_DTX_P4 <15> PCIE_PRX_DTX_N4 PCIE_WAKE#_USB3 S 1 2 <15> CLK_PCIE_USB30 <15> CLK_PCIE_USB30# VDD33 2 10/11 Corrected. R1187 10K_0402_5% EU3@ 3 D EU3@ Q125 SSM3K7002FU_SC70-3 1 <16,36,37> PCIE_WAKE# VDD33 C 4 @ I/O2 WCM-2012-900T_4P +3AVDD Intel_PCH_USB3.0 +3V 2 +5VALW 1 R728 2 0_0402_5% 2 U32 EU3@ +3V 5 3 For EMI request 1 +3V U2DP2 L55 1 R721 2 0_0402_5% R766 0_0603_5% EU3@ RT9701-PB_SOT23-5 6 Update to SM070001S00 for EMI request 1 +1.05V 1 5 VIN VOUT VIN/CE VOUT I/O4 2 3 4 <42,46,51> SYSON D31 @ I/O2 AZC099-04S.R7G_SOT23-6 U30 EU3@ 0.2A 3 U2DN1 8 0.01U_0402_16V7K EU3@ 2 1 C827 2 1 .1U_0402_16V7K EU3@ C823 2 1 0.01U_0402_16V7K EU3@ Close to U32.25 C825 2 1 Close to U32.3 .1U_0402_16V7K EU3@ 1 10U_0603_6.3V6M EU3@ C888 2 +3AVDD L60 EU3@ 1 2 FBMA-L11-201209-221LMA30T_0805 0.01U_0402_16V7K EU3@ 2 1 C813 1 0.01U_0402_16V7K EU3@ 2 C812 1 0.01U_0402_16V7K EU3@ 2 C811 1 0.01U_0402_16V7K EU3@ C810 2 0.01U_0402_16V7K EU3@ 1 C809 2 .1U_0402_16V7K EU3@ 1 C817 +3V .1U_0402_16V7K EU3@ 2 C816 10U_0603_6.3V6M EU3@ C887 1 +3V D22 D30 U3RXDN1 9 YSCLAMP0524P_SLP2510P8-10-9 +3V C821 2 1 0.01U_0402_16V7K EU3@ 2 C808 1 0.01U_0402_16V7K EU3@ C806 2 0.01U_0402_16V7K EU3@ 1 C803 2 0.01U_0402_16V7K EU3@ 1 C800 2 0.01U_0402_16V7K EU3@ 1 C805 2 0.01U_0402_16V7K EU3@ 2 1 C798 1 1 8 нϯs>tƚŽнϯsdƌĂŶƐĨĞƌ +3VALW 1 .1U_0402_16V7K EU3@ 2 2 C797 Vout=0.8(1+10K/32.4K) 1.042 ~ 1.0469 ~ 1.0519V Spec: 0.9975 ~ 1.05 ~ 1.1025 1 2 1 .1U_0402_16V7K EU3@ EU3@ R1151 32.4K_0402_1% EU3@ APL5930KAI-TRG_SO8 D 1 R1149 2 10K_0402_1% 2 FB C802 EN POK 1 .1U_0402_16V7K EU3@ 2 8 SYSON 2 1 7 R1150 5.11K_0402_1% EU3@ C799 1 22U_0603_6.3V6M EU3@ 3 4 VOUT VOUT C794 VCNTL VIN VIN +5VALW 2 @ 22U_0603_6.3V6M EU3@ 6 5 9 2 +1.05V U52 EU3@ +1.5V C886 EU3@ 10U_0603_6.3V6M EU3@ 1 +5VALW C796 2 C863 1U_0402_6.3V6K 1 +1.5V EU3@ C864 10U_0603_6.3V6M +5VALW 3 +1.05VDD 4 3 2 Rev 0.3 Thursday, January 05, 2012 1 Sheet 45 of 60 A B C +5VALW TO +5VS +5VALW D E +3VALW TO +3VS +5VS +3VALW +3VALW TO +3VALW(PCH AUX Power) 11/28 @ +3VS U38 2 1 1 C782 10U_0603_6.3V6M 2 @ 1 U40 DMN3030LSS-13_SOP8L-8 8 1 7 2 6 3 5 @ 2 SUSP G Q108 2N7002_SOT23 @ 1 S 2 @ +VSB 1 2 C727 0.01U_0402_25V7K R777 470_0603_5% @ C780 @ 1U_0402_6.3V6K C783 10U_0603_6.3V6M @ D 2 PCH_PWR_EN# G Q118 2N7002_SOT23 @ S 3 R650 0_0402_5% Q111 2N7002_SOT23 2 1 1 D 2 G SUSP 1 EVT short PJ1, U40 @ 9/22 NA D 1 1 C726 0.01U_0402_25V7K @ R778 470K_0402_1% 9/22 NA 1 2 2 3 3 JUMP_43X118 R645 470_0603_5% @ S 1 S C725 1U_0402_6.3V6K R647 470K_0402_1% 15VS_GATE_R 82K_0402_5% Q110 2N7002_SOT23 2 2 5VS_GATE 2 R649 C724 10U_0603_6.3V6M 1 2 3 S D 2 G 2 +VSB 2 SUSP G Q107 2N7002_SOT23 @ 1 1 2 R646 150K_0402_5% 2 +3V_PCH @ 1 2 D +VSB SUSP 10U_0603_6.3V6M PJ1 2 4 R644 470_0603_5% @ 1 1 2 C722 1U_0402_6.3V6K 1 2 2 +3VALW 1 3 C721 10U_0603_6.3V6M 1 C723 4 2 4 2 1 1 1 1 1 DMN3030LSS-13_SOP8L-8 8 1 7 2 6 3 5 C720 10U_0603_6.3V6M 1 U39 DMN3030LSS-13_SOP8L-8 8 1 7 2 6 3 5 D 2 G R779 0_0402_5% Q120 2N7002_SOT23 S 1 @ 2 @ 1 @ 3 PCH_PWR_EN# C781 0.01U_0402_25V7K +1.5V to +1.5VS +5VALW 2 1 1 2 2 C718 10U_0603_6.3V6M 2 C719 1U_0402_6.3V6K 1 PCH_PWR_EN# 2 2 +1.5V to +1.5VS_VGA Transfer 1 +1.5V 300mil(7.2A) 2 1 R1110 @ 100K_0402_5% @ 2 1 3 1 JUMP_43X118 C856 10U_0603_6.3V6M AO4430: Rdson: 5.5mohm @ VGS=10V 2 2 8 7 6 5 9/27 BOM Structure change to N13P@ 2 4 1 1 N13P@ C855 0.1U_0402_25V6 N13P@ @ 2 R790 1 0_0402_5% 2 G @ Q127 2N7002_SOT23 1 1 2 R782 1 DGPU_PWROK# N13P@ 0_0402_5% R1101 @ 470_0603_5% SUSP 2 R791 @1 0_0402_5% 4 R1108 100K_0402_5% @ Issued Date Compal Electronics, Inc. Compal Secret Data 2011/10/27 2012/10/27 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: B SUSP 2 R789 @1 0_0402_5% Security Classification A DGPU_PWROK# S 3 3 S Q129 2N7002_SOT23 N13P@ 1 4 Q126 2N7002_SOT23 D N13P@ 2 G S C854 0.1U_0402_16V4Z 2 D 2 1 D 2 G N13P@ 1 C853 10U_0603_6.3V6M N13P@ R4963 0_0402_5% @ 10K_0402_5% 1 N13P@ <54> 2 N13P@ R1102 2 R1107 100K_0402_5% N13P@ 2 <19,54> DGPU_PWROK 1 R1106 0_0402_5% 2 1 1 C852 10U_0603_6.3V6M 2 2 +5VALW DGPU_PWROK# 300mil(7.2A) 1 2 3 1 +VSB C851 10U_0603_6.3V6M N13P@ AO4304L_SO8 U49 N13P@ N13P@ DGPU_PWROK# 1 2 2 J12 1 IN 3 1 +1.5VS_VGA 3 2 1 3 3 C729 0.1U_0402_25V6 3 SYSON @ OUT @ Q119 DTC124EKAT146_SC59-3 <42,45,51> SYSON IN GND 2 SUSP# C728 S 0.1U_0402_25V6 GND 3 0,25,42,51,52,53,54> SYSON# OUT Q117 DTC124EKAT146_SC59-3 @ R654 100K_0402_5% D R781 100K_0402_5% 1.5VS_GATE 2 2 1 SUSP 1 <10,53,54> SUSP 1 0_0402_5% SUSP# 2 G 2N7002_SOT23S 1 1 2 @ R653 100K_0402_5% Check R652 220K_0402_5% 2 R651 D 2 G Q124 2N7002_SOT23 PCH_PWR_EN 1 Q112 2 +5VALW 1 +5VALW 1 2 100K_0402_5% R648 <42,48> PCH_PWR_EN 3 1 2 SUSP G Q109 2N7002_SOT23 @ S +RTCVCC @ D +3VALW For Intel S3 Power Reduction. R780 100K_0402_5% R643 470_0603_5% @ 2 C717 10U_0603_6.3V6M 1 1 2 2 SUSP G Q115 2N7002_SOT23 1 2 1 1 1 S 3 S +1.5VS Q8 PMV65XP_SOT23-3~D 3 D 2 SUSP G Q116 2N7002_SOT23 @ 3 S 3 3 S D 2 SYSON# G Q114 2N7002_SOT23 @ +1.5V R658 22_0603_5% 1 2 1 2 1 2 1 2 D 2 SUSP G Q113 2N7002_SOT23 @ R659 470_0603_5% @ G D R656 470_0603_5% @ D R655 470_0603_5% @ S 2 +0.75VS 1 +1.05VS 1 +1.5V 1 +1.8VS C D DC Interface Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet E 46 of 60 5 4 3 1 2 1 PC104 1000P_0402_50V7K 2 JDCIN1 ME@ 2 1 4602-Q04C-09R 4P P2.5 1 2 PC103 100P_0402_50V8J 3 2 1 PL101 SMB3025500YA_2P 1 2 PC102 100P_0402_50V8J D PF101 7A_24VDC_429007.WRML 1 2 APDIN1 1 2 APDIN PC101 1000P_0402_50V7K 3 4 1 VIN DC030006J00 4 2 D VIN 1 1 2 1 VS 1 PC113 0.1U_0603_25V7K 2 @ 2 2 1 2 @ PR124 22K_0402_1% 1 2 <43> 51_ON# 3 51ON-2 PR119 68_1206_5% @ PR123 100K_0402_1% 51ON-3 2 +3VLP C @ PC112 0.22U_0603_25V7K @ 51ON-1 @ PR118 68_1206_5% PQ104 TP0610K-T1-GE3_1P_SOT23-3 @ 2 @PR120 @ PR120 200_0603_5% 1 2 1 CHGRTCP PJ101 @ JUMP_43X39 1 2 1 2 @ PD103 LL4148_LL34-2 1 @ PD104 LL4148_LL34-2 2 1 BATT+ C 2 Unpop for KB9012 1 RTCVREF PR127 0_0402_5% @ 1 @ PU102 2 B 2 VOUT 2 CHGRTCIN VIN GND @ PC114 1 10U_0603_6.3V6M @ PC115 1U_0805_25V6K B 2 1 3 1 3.3V PR128 200_0603_5% APL5156-33DI-TRL_SOT89-3 +CHGRTC - JRTC2 + 1 PR131 560_0603_5% 1 2 @ MAXEL_ML1220T10 +CHGRTC_R 2 PR132 560_0603_5% 1 2 PD109 RB751V-40_SOD323-2 2 1 1 2 +RTCBATT RTCVREF PD108 RB751V-40_SOD323-2 RTC Battery A A Compal Secret Data Security Classification Issued Date 2010/01/25 2012/07/11 Deciphered Date Title Compal Electronics, Inc. PWR DCIN / Vin Detector /Pre-charge THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C38-G series Chief River Schematic0.1 Date: 5 4 3 2 Thursday, January 05, 2012 Sheet 1 47 of 60 5 4 VMB2 1 PL201 SMB3025500YA_2P 1 2 BATT+ 1 2 2 PC201 1000P_0402_50V7K D PC202 0.01U_0402_25V7K ADP_I need to write Charge Options Register (0x12H)=> bit6=1 0: IOUT is the 20x current amplifier output1: IOUT is the 40x current amplifier output EC_SMB_DA1 <42,49> VL +3VALW 2 1 PR206 12.7K_0402_1% 2 1 PR209 10K_0402_1% 1 2 @ MAINPWON <42,50> @ 1 2 27.4K_0402_1% 2 ADP_OCP_2 1 5 PR228 47K_0402_1% 1 2 PR230 1 PR213 0_0402_5% +3VALW 2 PR232 47K_0402_1% @ 2 Turbo_V 0_0402_5% C PH201 100K_0402_1%_TSM0B104F4251RZ PR227 0_0402_5% PR210 1 1 2 Turbo_V_1 90W(DIS) : 27.4K 65W(UMA) : 5.11K 2 NTC_V_1 <42> 3 PR212 0_0402_5% 1 2 @ PROCHOT 6 G718TM1U_SOT23-8 2 ADP_OCP_1 G S SSM3K7002FU_SC70-3 <42> OT2 RHYST2 OTP_N_002 NTC_V 4 7 2 PQ201 8 PR211 D OT1 TMSNS2 OTP_N_003 1 1 <6,42,49> H_PROCHOT# GND RHYST1 1 3 VCC TMSNS1 10K_0402_1% 2 PR229 2 PR208 C PU201 1 @ <42> +3VS 100K_0402_1% PC203 0.1U_0603_16V7K 90W(DIS) : 4.42K 65W(UMA) : 402 ohm 1 A/D 1 BATT_TEMP <42> PR205 4.42K_0402_1% 1 2 PR204 10K_0402_5% ADP_I 2 1 PR207 21.5K_0402_1% +3VLP <42,49> 0_0402_5% 2 1 1 2 PR203 6.49K_0402_1% For KB930 --> Keep PU201 circuit (Vth = 0.825V) For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206 PH201, PR205, PR211,PQ201,PR208,PR212 PH1 under CPU botten side : CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C EC_SMB_CK1 <42,49> 2 TYCO_1775789-1 ME@ 2 1 PR202 100_0402_1% 1 EC_SMCA EC_SMDA 2 1 PR201 100_0402_1% D 1 2 3 4 5 6 7 8 9 2 VMB PF201 12A_65V_451012MRL 1 2 JBATT1 1 2 3 4 5 6 7 GND GND 3 +3VLP B B S RTCVREF S <50> PCH_PWR_EN 1 PR224 @ 1K_0402_5% 2 PR231 1K_0402_5% 1 2 A PR225 10K_0402_1% @ <42> 1 SPOK D 3 <50> S 2 G PC207 1U_0402_6.3V6K 2 G 3 PR226 100K_0402_1% PQ203 D 2N7002KW_SOT323-3 1 PR223 10K_0402_1% 2 1 2VREF_8205 2 1 PC206 0.1U_0603_25V7K 1 2 1 1 1 2 +VSBP PR222 100K_0402_1% +3VLP 1 PU202A LM393DG_SO8 2 2 1 PR216 100K_0402_1% VL 2 G PC205 0.22U_0603_25V7K PQ202 D 2N7002KW_SOT323-3 PR220 22K_0402_1% 1 2 2 - 1 1 P O <49> 1 1 2 1 BATT_OUT 3 2 + 3 B+ PR215 100K_0402_1% 2 2 1 2 PQ205 TP0610K-T1-GE3_1P_SOT23-3 2 +3VALW 8 3 PR221 221K_0402_1% +3VLP PR214 100K_0402_1% PR218 10M_0402_5% 1 PR219 10K_0402_1% 1 2 G PR217 768K_0402_1% 4 2 1 2 2 VMB2 PC204 0.01U_0402_25V7K 1 P2 PQ204 2N7002W-T/R7_SOT323-3 +VSBP PJ201 @ JUMP_43X39 1 2 1 2 +VSB A BATT_LEN# Compal Secret Data Security Classification Issued Date 2010/01/25 2012/07/11 Deciphered Date Title Compal Electronics, Inc. PWR-BATTERY CONN/OTP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev C38-G series Chief River Schematic0.1 Date: 5 4 3 2 Thursday, January 05, 2012 Sheet 1 48 of 60 5 4 3 2 B+ P3 Need EC write ChargeOption() bit[8]=1 Setting (ACP to PHASE Rising Threshold)=1350mV(min) P2 PQ301 AO4407A_SO8 PQ302 AO4423L_SO8 PR302 0.01_1206_1% DISCHG_G VIN 2 2ACOFF-1 1SS355_SOD323-2 1 PD302 1SS355_SOD323-2 2 PQ309 PQ310 AO4466L_SO8 3 2 1 PD303 2 REGN 4 2 16 1 1 PR324 PC314 2.2_0603_5% 0.047U_0603_16V7K 1 2 2 1 BST_CHG 2 BQ24727VDD DL_CHG PC320 0.1U_0603_25V7K 2 1 B 2 1 15 14 PR328 10_0603_5% 13 1 2 11 RB751V-40_SOD323-2 PC318 1U_0603_25V6K 3 1 CHG 4 2 3 SRP BATT+ SRN PC317 10U_0805_25V6K 2 1 SRN BM 17 2 PR322 4.7_1206_5% BTST PR326 100K_0402_1% 1 DH_CHG 16251_SN 2 ILIM 18 C SH000005Z80 LX_CHG HIDRV SA000051W00 SCL 1U_0603_25V6K 19 PACIN PC316 10U_0805_25V6K 2 1 1 5 6 7 8 PR319 10_1206_5% 2 1 ACP 2 3 CMPIN CMPOUT ACN PHASE PU301 BQ24727RGRR_VQFN20_3P5X3P5 2 G S PL302 10UH_PCMB104T-100MS_6A_20% PR320 0.01_1206_1% 5 6 7 8 SDA 2N7002W -T/R7_SOT323-3 PC319 680P_0603_50V7K 10 4 2 PQ312 AO4466L_SO8 PR323 1 2 316K_0402_1% BQ24727VCC 1 20 3 2 1 <42,48> EC_SMB_CK1 VCC LODRV 9 21 PC313 GND 100P_0603_50V8 8 0.1U_0603_25V7K <42,48> EC_SMB_DA1 TP IOUT SRP 7 4 5 PC312 1 2 64.9K_0603_1% PC323 1 2 ACDET D PC311 0.1U_0603_25V7K 2 1 1 1 3 P2 2 S ADP_I 6 +3VALW ACOK <42,48> 2 3 2 1 3 BATT_OUT 2 @ PR315 10K_0402_5% 1 2 PR316 10K_0402_5% 1 2 PR314 2 1 390K_0603_1% PR317 1 @ 2N7002KW_SOT323-3 <48> 2 G 1 0.1U_0603_25V7K 2 VIN PR325 0_0402_5% D PR306 200K_0402_1% S PR321 1 2ACOFF-12 10K_0402_5% PQ313 2 0.1U_0603_25V7K 1 ACOFF 2 PQ306 DTC115EUA_SC70-3 PC310 <48> 1 <42> 1 6.8_0603_5% 1 12 PR327 PQ311 DTC115EUA_SC70-3 1 ACON ACPRN 3 1 4 5 PR308 150K_0402_1% 2 P2-2 3 PQ307B PR318 47K_0402_1% 1 2 PACIN PQ308 2N7002KW _SOT323-3 2 BATT_OUT G D 2N7002KDW-2N_SOT363-6 1 C 1 2 3 6 PQ307A 2N7002KDW -2N_SOT363-6 PACIN <50> PR307 20K_0402_1% PC309 1 DTC115EUA_SC70-3 PC308 PD301 1DISCHG_G-1 1 1 +3VALW 0.1U_0603_25V7K 1 P2-1 PR305 10K_0402_1% 1 1 2 ACN 2 2 D PR304 47K_0402_1% 1 2 ACP PQ305 8 7 6 5 4 1 2 3 PC307 2200P_0402_50V7K PC306 4.7U_0805_25V6-K 1 2 PC305 4.7U_0805_25V6-K 1 2 2 1 2 2 PC304 5600P_0402_25V7K 1 1 2 PC301 0.1U_0603_25V7K 2 1 PR303 200K_0402_1% 3 2 2 1 PR301 47K_0402_5% 1 DTA144EUA_SC70-3 PQ303 AO4407A_SO8 PL301 1UH_PCMB061H-1R0MS_7A_20% PC303 4.7U_0805_25V6-K 1 2 3 2 2 2 1 1 4 PQ304 D CHG_B+ SH00000AA00 1 PC315 @ 10U_0805_25V6K 8 7 6 5 PC302 @ 10U_0805_25V6K 1 2 3 4 1 2 3 4 8 7 6 5 VIN 1 B 0V 1 CHGVADJ 4V PC321 0.1U_0603_25V7K 2 2 Vcell 1 CHGVADJ=(Vcell-4)/0.10627 4.2V 1.882V 4.35V 3.2935V @ PC322 0.1U_0603_25V7K BQ24727VDD PR337 10K_0402_1% 1 2 IREF=1.016*Icharge 1 1 CC=0.25A~3A PR336 10K_0402_1% ACIN <16,42> PACIN 1 2 VCHLIM need over 95mV 1 2 PR335 47K_0402_1% IREF=0.254V~3.048V ACPRN <50> PR339 2 2 PQ316 A 3 DTC115EUA_SC70-3 A 12K_0402_1% For disable pre-charge circuit. 2010/01/13 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/07/11 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 CHARGER Document Number Rev 0.1 C38-G series Chief River Schematic Thursday, January 05, 2012 Sheet 1 49 of 60 5 4 3 2 1 Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO 2VREF_8205 PJ402 2 +3VALW P 2 1 1 +3VALW PC401 1U_0603_10V6K @ JUMP_43X118 1 D PJ403 2 +5VALW P 2 D @ RT8205_B+ PJ401 PR403 20K_0402_1% 1 2 PR404 19.6K_0402_1% 1 2 +5VALW 5 6 7 8 PC410 0.1U_0603_25V7K 2 1 RT8205EGQW _W QFN24_4X4 PC421 4.7U_0805_10V6K 1 2 1 2 PC422 0.1U_0603_25V7K 2VREF_8205 PR413 0_0402_5% 2 1 2 3 2 1 TPC8A03-H_SO8 PC420 1U_0603_10V6K 2 1 2 5 4 2 1 4 VL RT8205_B+ +5VALWP 1 LG_5V Typ: 175mA PR410 4.7_1206_5% 19 PL402 3.3UH_PCMB064T-3R3MS_7A_20% 1 2 2 LX_5V @ PC424 150U_V_6.3VM_R18 PC419 680P_0603_50V7K UG_5V 5 6 7 8 21 20 3 2 1 PR408 PC413 2.2_0603_5% 0.1U_0603_25V7K 2 1 2 BST_5V 1 C TPC8065-H_SO8 PQ402 PC409 2200P_0402_50V7K 2 1 22 PQ404 NC <48> 18 17 16 VREG5 LGATE1 VIN LGATE2 13 PC408 4.7U_0805_25V6-K 2 1 1 ENTRIP1 3 4 2 FB1 REF FB2 TONSEL PHASE1 EN UGATE1 PHASE2 23 SPOK 1 6 PQ405A 2N7002KDW -2N_SOT363-6 PC407 4.7U_0805_25V6-K 2 1 ENTRIP1 ENTRIP2 6 5 VFB=2.0V UGATE2 PQ405B 2N7002KDW -2N_SOT363-6 1 <42,48> MAINPWON ENTRIP2 3 ENTRIP1 PR418 2.2K_0402_5% 2 1 BOOT1 24 B+ B For KB9012 12 PGOOD BOOT2 PR411 499K_0402_1% 1 2 1 2 3 2 <42,43> EC_ON 1 RT8205_B+ 4 VREG3 4 PC415 150U_B2_6.3VM_R35M PC418 680P_0603_50V7K 2 1 + LG_3V PQ403 AO4712L_SO8 PR412 100K_0402_1% 1 8 7 6 5 PR409 4.7_1206_5% 2 1 PL401 4.7UH +-20% PCMC063T-4R7MN 5.5A 1 2 PR406 66.5K_0402_1% 2 VO1 GND 1 2 3 8 PR407 2 1 2 BST_3V 9 2.2_0603_5% PC412 UG_3V 10 0.1U_0603_25V7K 11 LX_3V 1 VO2 SKIPSEL 7 +3VALWP P PAD 1 15 4 25 ENTRIP2 AO4466L_SO8 PU401 1 PQ401 PR405 130K_0402_1% 1 2 2 8 7 6 5 PC403 4.7U_0805_25V6-K 2 1 C PC411 4.7U_0805_10V6K +3VLP 14 1 1 PC406 2200P_0402_50V7K 2 1 2 @ JUMP_43X118 PC404 4.7U_0805_25V6-K 2 1 2 PR402 30K_0402_1% 1 2 1 Typ: 175mA PC402 0.1U_0603_25V7K 2 1 PC405 0.1U_0603_25V7K 2 1 B+ PR401 13K_0402_1% 1 2 2 JUMP_43X118 1 1 + + 2 2 PC417 150U_V_6.3VM_R15 B +3.3VALWP OCP(min)=5.81A +5VALWP OCP(min)=8.44A PR414 100K_0402_1% 2 1 2 PQ408 DTC115EUA_SC70-3 3 @ PQ406 DTC115EUA_SC70-3 A 3 @ 2 PC423 4.7U_0603_6.3V6M EC_ON 2 PR416 100K_0402_1% 1 1 @ 1 2 S VS A <42,43> D 2 G 2 1 PR417 40.2K_0402_1% PR415 200K_0402_1% 2 1 PQ407 2N7002W-T/R7_SOT323-3 ACPRN 1 9> 3 1 VL 2010/01/25 Issued Date For KB9012 @ 5 Compal Secret Data Security Classification @ 4 Deciphered Date 2012/07/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 Title Compal Electronics, Inc. 3VALWP/5VALWP Size Document Number Custom C38-G series Chief River Schematic Date: Thursday, January 05, 2012 Sheet 1 50 of 60 Rev 0.1 A B C D PJ501 2 PC505 2 1 2200P_0402_50V7K PC504 2 1 0.1U_0402_25V6 @ 2 1 B+ 1 JUMP_43X118 3 2 1 4 PC503 10U_0805_25V6K 2 1 PQ501 TPC8065-H_SO8 PC502 10U_0805_25V6K 2 1 5 6 7 8 1.5V_B+ VFB 5 V5IN RF DRVL TP 2 9 DH_1.5V 8 LX_1.5V PR503 PC506 2.2_0603_5% 0.22U_0603_16V7K 1 2BST_1.5V-1 1 2 PL501 1UH_PCMC063T-1R0MN_11A_20% 1 2 5 6 7 8 1 BST_1.5V 7 +5VALW 6 DL_1.5V PQ502 11 PC508 1U_0603_10V6K 4 1 TPS51212DSCR_SON10_3X3 VFB=0.7V 3 2 1 1 11.5K_0402_1% TPC8A03-H_SO8 2 1 PC501 @ .1U_0402_16V7K 2 SW 470K_0402_1% PR507 1 PR5062 DRVH EN 4 1 TRIP 10 1 2 VBST 2 1 3 PR502 47K_0402_5% 1 2 <42,45,46> SYSON 2 PR501 0_0402_5% 1 2 PGOOD 1 +1.5VP PR504 @ 4.7_1206_5% PU501 1 PR505 1 + 2 100K_0402_1% OCP(min)=15.6A PJ502 2 @ 2 1 1 JUMP_43X118 PJ503 2 +1.5VP @ 2 PR508 10K_0402_1% PC507 220U_D2_4VY_R15M +1.5VP 2 PC509 @ 1000P_0603_50V7K 1 2 +1.5V 1 1 JUMP_43X118 2 2 3 3 1 2 2 1 1 PC511 68P_0402_50V8J 2 1 PC514 22U_0805_6.3VAM SY8033BDBC_DFN10_3X3 2 1 1 2 FB=0.6Volt PR510 20K_0402_1% PC513 22U_0805_6.3VAM 1 6 +1.8VSP PJ504 2 +1.8VSP 2 @ 1 1 +1.8VS JUMP_43X118 1.8VSP max current=4A 1.8VSP_FB 1 1 2 PR512 1M_0402_5% PG FB EN TP EN_1.8VSP PC515 @ 0.1U_0402_10V7K 0_0402_5% 2 3 SVIN 11 PR511 1 2 <10,25,42,46,52,53,54> SUSP# LX 1.8VSP_LX 2 2 5 PVIN 2 PC512 PR509 680P_0603_50V7K 4.7_1206_5% 8 PC510 22U_0805_6.3VAM LX NC 9 JUMP_43X118 PVIN NC 10 1.8VSP_VIN 1 1 7 1 1 @ 2 PL503 1UH_PH041H-1R0MS_3.8A_20% 1 2 4 PU502 PJ505 2 +5VALW PR513 10K_0402_1% 4 2 4 Compal Secret Data Security Classification Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title Compal Electronics, Inc. PWR-+1.5VP/+1.8VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 C38-G series Chief River Schematic Date: A B C Thursday, January 05, 2012 D Sheet 51 of 60 4 3 +3VS PR602 100K_0402_5% 1 13 24 7 @ PC604 1000P_0603_50V7K @ PC612 22U_0805_6.3V6M 1 2 2 1 8 @ PC611 22U_0805_6.3V6M 1 2 1 PR607 4.7_1206_5% 9 +VCCSAP @ COMP VREF 3 1 GND JUMP_43X118 MODE VIN TP 25 C 6 +VCCSA_PWR_SRC VOUT +VCCSA_PWR_SRC SW SLEW 1 10 PC609 22U_0805_6.3V6M 1 2 EN SW SW 5 1 PL601 0.47UH_FDVE0630-H-R47M=P3_17.7A_20% 1 2 VIN 2 @ C 2 +VCCSA_PHASE VIN 23 4 2 11 PR606 PC603 0_0603_5% 0.22U_0603_16V7K 2+VCCSA_BT_1 1 2 PC608 22U_0805_6.3V6M 1 2 14 SW PJ601 +3VALW +VCCSA_BT 1 PGND TPS51461RGER_QFN24_4X4 1 12 PGND 22 +VCCSA 1 D PC610 2200P_0402_50V7K 2 1 1 BST SW 21 2 1 2 2 10U_0805_6.3V6M PC616 10U_0805_6.3V6M PC615 2 0.1U_0603_25V7K PC614 1 2 2200P_0402_50V7K PC613 1 2 JUMP_43X118 +V1.05S_VCCP_PWRGOOD <53> PC607 0.1U_0402_10V7K 2 1 PGND 20 @ <10> PR605 0_0402_5% 1 2 +VCCSA_EN PGOOD 19 V5FILT 18 V5DRV PU601 17 PC602 2.2U_0603_10V7K 1 2 2 +VCCSAP The 1k PD on the VCCSA VIDs are empty. These should be stuffed to ensure that VCCSA VID is 00 prior to VCCIO stability. +VCCSA_VID0 +VCCSA_VID1 15 2 1 PC601 1U_0603_10V6K 16 PR604 10_0402_1% 2 1 +VCCSA_PWRGD +5VALW H_VCCSA_VID0 PJ602 +VCC_SAP TDC 4.2A Peak Current 6A OCP current 7.2A <10> PR603 1K_0402_5% 2 1 VID1 output voltage adjustable network D H_VCCSA_VID1 VID0 <42> SA_PGOOD 1 PC606 22U_0805_6.3V6M 1 2 VCCSA Vout 0.9V 0.8V 0.725V 0.675V 2 VID[1] 0 1 0 1 +VCCSA_PWRGD VID [0] 0 0 1 1 2 PR601 1K_0402_5% 2 1 PC605 22U_0805_6.3V6M 1 2 5 @ PR608 2 1 33K_0402_5% PC617 2 1 PR609 100_0402_5% 2 1 PR612 100K_0402_5% @ DRVL 1 SW_+V1.05S_VCCPP +V1.05S_VCCPP_5V 6 LG_+V1.05S_VCCPP B @ 2 1 PC628 1000P_0603_50V7K 2 TPC8A03-H_SO8 @ @ PC631 220U_D2_4VY_R15M 2 +V1.05S_VCCPP PJ604 2 @ 2 +V1.05S_VCCP 1 1 JUMP_43X118 @ 2 1000P_0402_50V7K @ PR617 4.7_1206_5% 3 2 1 PR619 @ PR618 @ 1 +V1.05S_VCCPP + PQ602 PC626 1U_0603_6.3V6M 2 PC629 JUMP_43X118 1 4 2 B+ 3 2 1 @ PR616 470K_0402_1% 1 @ +5VALW @ @ 1 @ PL602 1UH_PCMC063T-1R0MN_11A_20% 1 2 11 TPS51212DSCR_SON10_3X3 @ 2 0.1U_0402_10V7K RF 8 7 1 @ @ @ 2 V5IN UG_+V1.05S_VCCPP 1 5 SW VFB BST_+V1.05S_VCCPP 9 PC627 RF_+V1.05S_VCCPP EN 10 TP 2 @ PC625 0.1U_0402_16V7K 4 DRVH 1 3 FB_+V1.05S_VCCPP VBST TRIP 4 5 6 7 8 EN_+V1.05S_VCCPP PGOOD @ PC624 0.22U_0603_16V7K 1 2 1 PR615 0_0402_5% 1 2 SUSP# 2 1 <10,25,42,46,51,53,54> TRIP_+V1.05S_VCCPP 2 @ B 0_0603_5% PU602 1 @ PR614 1 2 66.5K_0402_1% PR613 2 1 @ <53> +V1.05S_VCCP_PWRGOOD @ PC623 4.7U_0805_25V6-K 2 PQ601 TPC8037-H_SO8 1 @ +VCCSA_SENSE <10> PJ603 2 +V1.05S_VCCPP_B+ 5 6 7 8 +3VS PR611 0_0402_5% 2 1 2 1 PC622 4.7U_0805_25V6-K 2 1 2 PR610 5.1K_0402_1% PC621 2200P_0402_50V7K 2 1 1 PC620 0.1U_0402_25V6 2 1 2 PC618 3300P_0402_50V7K PC619 0.01U_0402_25V7K 1 2 0.22U_0402_10V6K 1 1.2K_0402_1% @ 4.32K_0402_1% 2 1 PR620 0_0402_5% 2 1 VCCIO_SENSE <9,53> 2 1 VCCP_PWRCTRL = "High" , VCCP_PWRCTRL = "Low" , Vo = 1.05V (SNB) Vo = 1V (IVB) PR623 100K_0402_5% 1 @ PR624 0_0402_5% 2 1 D S 1 2 @ .01U_0402_16V7K 1 2 2 G PC630 PQ603 @ SSM3K7002FU_SC70-3 A @ 2 @ PR622 71.5K_0402_1% 1 PR621 10K_0402_1% 1 @ 3 2 +3VS A VCCP_PWRCTRL <10> PR625 100K_0402_5% @ Compal Secret Data Security Classification Issued Date 2010/01/25 Deciphered Date 2012/07/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 5 4 3 2 Compal Electronics, Inc. PWR +VCCSAP/1.0 Document Number C38-G series Chief River Schematic Thursday, January 05, 2012 Sheet 1 52 of 60 Rev 0.1 5 4 3 2 1 1 1 +1.5V PJ701 JUMP_43X79 @ D 2 2 D PU701 PR720 10K_0402_1% 1 2 1 VOUT PC703 5 NC 1 +0.75VS 1U_0603_10V6K 9 PJ703 2 2 1 1 @ JUMP_43X118 PJ704 2 1 2 1 +1.05VS_VCCPP PC706 10U_0603_6.3V6M 2 2 PR704 1 1 1 6 VREF VCNTL 2 JUMP_43X79 @ +0.75VSP PC705 10U_0603_6.3V6M 2 1 PC704 .1U_0402_16V7K 2 1 1 S NC 2 +0.75VSP 7 TP 1K_0402_1% 1 D 4 GND PJ702 +3VALW 8 NC APL5336KAI-TRL_SOP8P8 2 G PC701 0.1U_0402_10V7K 2 1 <10,46,54> SUSP 3 PQ701 2N7002W -T/R7_SOT323-3 PR703 49.9K_0402_1% 1 2 3 VIN 2 @ CPU1.5V_S3_GATE 2 PR702 1K_0402_1% 1 2 PC702 4.7U_0805_6.3V6K 2 1 pu701vin @ +1.05VS JUMP_43X118 PJ605 @ 2 +1.05VS C 2 2 1 +V1.05S_VCCP 1 JUMP_43X118 PJ606 @ 1 2 1 C JUMP_43X118 Ivy Bridge CPU ES2 Using 13 DH_1.05VS_VCCP DL_1.05VS_VCCP TPCA8057-H_PPAK56-8-5 2 10 2 2 2 10_0402_1% 1 2 PC713 1U_0603_10V6K 1 3 2 1 2 PGND +5VALW 8 GND 7 6 @ 10_0402_5% 0.01UF_0402_25V7K 9 1 1 PR711 75K_0402_1% 2 1 PR714 1 2 TRIP COMP V5 5 PC712 PR716 1 PC717 4.7U_0805_25V6-K 2 1 B+ B +1.05VS_VCCPP 1 PC709 330U_2.5V_M_LESR9M PQ703 DL VSNS 1 TPCA8065-H_PPAK56-8-5 PL701 1.0UH +-20% PCMC104T-1R0MN 20A 2 1 4 4 1 1 11 LX_1.05VS_VCCP PC715 PR712 1000P_0603_50V7K 4.7_1206_5% GSNS 2 JUMP_43X118 4 5 DH 12 TPS51219RTER_QFN16_3X3 3 2 @ 2.2_0402_5% SW REFIN 1 3 2 1 EN BST 14 MODE PGOOD VREF PR717 2 PC719 4.7U_0805_25V6-K 2 1 PC714 0.1U_0402_25V6 2 1 1 PC720 0.01UF_0402_25V7K 15 16 17 PAD 2 2 12K_0402_1% 1 0_0402_1% <9,52> VCCIO_SENSE PQ702 1 1 PU702 1 PR718 2 PC710 0.1U_0603_25V7K 1 2 10.7K_0402_1% PR707 2 1 PR708 2 VSSIO_SENSE_L <9> PC708 0.1U_0402_25V6 2 1 B 5 PR713 2.2_0603_5% 1 2 BST_1.05VS_VCCP PC718 2200P_0402_50V7K 2 1 100K_0402_1% PJ705 1.05VS_B+ 1 PR706 2 PR705 100K_0402_1% 2 1 2 PR715 0_0402_5% 1 2 <52> +V1.05S_VCCP_PW RGOOD +1.05VS_VCCPP OCP(min)=20.75A +3VS PC707 .1U_0402_16V7K 1 PR709 2 1,52,54> SUSP# @ 10K_0402_1% PR710 60.4K_0402_1% 1 2 + 2 PC716 1000P_0402_50V7K PR719 A 1 2 1 A 2 10_0402_1% PC721 1000P_0402_50V7K Compal Secret Data Security Classification 2010/01/25 Issued Date Deciphered Date 2012/07/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. PWR +1.05VS_VCCPP/+0.75VSP Size Document Number Custom C38-G series Chief River Schematic Date: Thursday, January 05, 2012 Sheet 1 53 of 60 Rev 0.1 A B C D 2 2 1 PC804 10U_0805_25V6K 2 1 2 1 + 2 PC808 330U_D2_2.5V_Y 1 PR809 10K_0402_1% 2 1 PR808 3.65K_0805_1% 2 1 1 2 2 SNUB2_VGA TPCA8057-H_PPAK56-8-5 1 + VSUM-_VGA VSUM+_VGA ISEN2_VGA 1 2 PC809 @680P_0402_50V7K 2 Near VGA Core PC819 22U_0805_6.3V6M 2 1 PC820 47U_0805_4V 1 PC821 22U_0805_6.3V6M 2 1 PC822 4.7U_0805_6.3V6K PC833 4.7U_0805_6.3V6K 2 1 PC834 4.7U_0805_6.3V6K 2 1 PC835 4.7U_0805_6.3V6K 1 2 PC832 4.7U_0805_6.3V6K 2 1 PC818 4.7U_0603_6.3V6M PC817 4.7U_0603_6.3V6M 2 1 2 PC831 4.7U_0603_6.3V6M PC816 4.7U_0603_6.3V6M 2 1 PC830 4.7U_0603_6.3V6M 2 1 PC815 4.7U_0603_6.3V6M 2 1 PC829 4.7U_0603_6.3V6M 2 1 PC813 4.7U_0603_6.3V6M 2 1 PC814 4.7U_0603_6.3V6M 2 1 PC828 4.7U_0603_6.3V6M 2 1 PC827 4.7U_0603_6.3V6M 2 1 PC812 4.7U_0603_6.3V6M 2 1 PC811 4.7U_0603_6.3V6M 2 1 PC826 4.7U_0603_6.3V6M 2 1 1 2 PC846 @0.1U_0402_10V7K PC845 @0.1U_0402_10V7K 2 1 PC843 0.1U_0402_10V7K 2 1 PC844 @0.1U_0402_10V7K 2 1 +VGA_B+ PR827 2.2_0603_5% 2 1 BOOT1_1_VGA PC856 0.22U_0603_10V7K 1 2 TPCA8065-H_PPAK56-8-5 1 1 1 +VGA_CORE 3 2 1 PC855 10U_0805_25V6K 2 1 JUMP_43X118 PL804 0.36UH_VMPI1004AR-R36M-Z03_30A_20% 1 PHASE1_VGA LF1_VGA 3 2 1 @ 4 +VGA_COREP 3 V1N_VGA 2 1 + 2 PC861 330U_D2_2.5V_Y @ PC860 330U_D2_2.5V_Y 1 1 PR833 1_0402_1% + 2 2 1 2 PR832 10K_0402_1% 2 @4.7_1206_5% SNUB1_VGA 2 Layout Note: Place near Phase1 Choke 4 3 2 1 1 PR830 4 LGATE1_VGA PR831 3.65K_0805_1% 2 1 TPCA8057-H_PPAK56-8-5 1 5 5 PQ806 PQ805 VSUM-_VGA VSUM-_VGA VSUM+_VGA ISEN1_VGA 4 PC865 @680P_0402_50V7K PC866 0.1U_0402_16V7K 2 POP:PR815,PC803 PC854 10U_0805_25V6K 4 UGATE1_VGA PC853 2200P_0402_50V7K 2 1 5 PC852 0.1U_0402_25V6 2 1 @ PQ804 2 JUMP_43X118 PJ803 2 1 2 1 +VGA_COREP <24> PH801 10K_0402_1%_TSM0A103F34D1RZ PR837 1K_0402_1% 1 2 PJ802 2 @ 3 2 1 VSSSENSE_VGA PC842 0.1U_0402_10V7K 2 1 <42> PC841 0.1U_0402_10V7K 2 1 GPU_IMON @ PC840 0.1U_0402_10V7K 2 1 1 +5VS 0_0402_5% 2 PR828 2.61K_0402_1% 2 1 NTC_VGA PR834 11K_0402_1% 2 1 PC859 0.022U_0603_25V7K 2 1 PC858 0.22U_0603_10V7K 2 1 PR826 @82.5_0402_5% PC864 @0.01U_0402_25V7K 1 1 2 1 2 1 2 @:PR806,PR812,PC823,PC848,PC849,PR832, PC801,PC802,PQ801,PQ802,PQ803,PR804, PC805,PC803,PR808,PR809,PR810,PC807, PC804 PR810 1_0402_1% 1 For N13M-GE(15W without turbo) @4.7_1206_5% TPCA8059-H_PPAK56-8-5 PR836 10_0402_5% 1 2 1 PC862 1000P_0402_50V7K PC863 @330P_0402_50V7K 2 1 PC857 330P_0402_50V7K VSUM_VGA_N001 2 2 PR835 0_0402_5% 1 2 PC803 10U_0805_25V6K 5 3 2 1 5 3 2 1 @ PR807 +VGA_COREP 3 V2N_VGA Under VGA Core PC825 4.7U_0603_6.3V6M 2 1 1 +5VS PC851 0.22U_0603_25V7K PC850 1U_0603_10V6K 2 1 1 1 2 2 +VGA_B+ PR865 1 VSUM+_VGA 2 PR829 0_0402_5% <24> VSSSENSE_VGA PC802 2200P_0402_50V7K 2 1 1 3 2 0_0402_5% 2 PR823 1_0402_5% 1 2 2 1 <24> VCCSENSE_VGA PC801 0.1U_0402_25V6 2 1 1 2 <23> <23> GPU_VID0 <23> GPU_VID1 <23> GPU_VID2 5 3 2 1 4 4 2 PC807 330U_D2_2.5V_Y 1 1 2 4 1 2 PR821 1 0.047U_0402_16V7-K 1 2 PR850 11.3K_0402_1% VIN_VGA 2 VDD_VGA IMON_VGA @ 0_0402_5% 1 2 VSEN_VGA PR825 10_0402_5% 4 4 BOOT1_VGA 2 PC824 1U_0603_10V6K VSUM-_VGA 1 +VGA_COREP 1 LF2_VGA PQ803 ISEN1_VGA PR824 68K_0402_1% +5VS ISL62883CHRTZ-T_TQFN40_5X5 For 15W one phase ISEN2_VGA PR814 1 2 0_0402_5% VCCP_VGA PR819 +5VS 2 PR822 33K_0402_1% 30 29 28 27 26 25 24 23 22 21 PC874 2 1 2 @ PR815 0_0402_5% 2 1 PC847 150P_0402_50V8J 11 12 13 14 15 16 17 18 19 20 390P_0402_50V7K PR820 1.15K_0402_1% 1 2 1 PC848 0.22U_0402_10V6K 3 2FB2_VGA1 AGND 2 1 1 PR818 499_0402_1% PC837 2FB1_VGA1 41 BOOT2 UGATE2 PHASE2 VSSP2 LGATE2 VCCP PWM3 LGATE1 VSSP1 PHASE1 PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2 RTN_VGA ISUM-_VGA PC836 1000P_0402_50V7K 1 2 PR817 8.06K_0402_1% 2 1 PR816 @249K_0402_1% 1 2 PC823 22P_0402_50V8J PC838 100P_0402_50V8J 1 2 3 1 COMP_VGA FB_VGA 2ISEN3_VGA 1 1 2 3 4 5 6 7 8 9 10 1 VW_VGA PH802 1 PQ802 PC871 1U_0603_10V6K 2 470K_0402_5%_TSM0B474J4702RE 2 1 2 PR871 1 4.02K_0402_1% PL803 0.36UH_VMPI1004AR-R36M-Z03_30A_20% 2 PU801 40 39 38 37 36 35 34 33 32 31 2 PR869 @ 0_0402_5% B+ TPCA8065-H_PPAK56-8-5 +VGA_CORE CLK_EN# DPRSLPVR VR_ON VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 1 1 PHASE2_VGA +VGA_CORE RBIAS_VGA PSI#_VGA +3VS BOOT2_2_VGA UGATE2_VGA PR813 147K_0402_1% 2 1 @ PR870 100K_0402_5% 1 2 <23,42> VGA_AC_DET PC805 0.22U_0603_10V7K 1 2 PC839 0.1U_0402_10V7K 2 1 +3VS 1 ISEN1 VSEN RTN ISUMISUM+ VDD VIN IMON BOOT1 UGATE1 PR873 0_0402_5% PSI#_VGA 2 BOOT2_VGA 2 JUMP_43X118 4 PR804 2.2_0603_5% 2 1 PR812 100K_0402_5% 1 2 PC849 0.22U_0402_10V6K @ 2 PR849 @ 0_0402_5% TPCA8059-H_PPAK56-8-5 2 <19,46> DGPU_PWROK 1 0.1U_0603_25V7K SUSP LGATE2_VGA PR811 1.91K_0402_1% +3VS_VGA 2 PR847 0_0402_5% 1 2 1 CLK_ENABLE#_VGA PC870 1 @ DGPU_PWROK# <46> SUSP <10,46,53> N13P-GL:0.95V(VID5~0=101100) N13M-GE:0.9V(VID5~0=110000) S PR843 0_0402_5% 1 2 @ D GPU_VID5 <23> PR801 0_0402_5% 1 GPU_VID6 PR806 1.91K_0402_1% 1 2 .1U_0402_16V7K 2 G 2 @ PR851 0_0402_5% 1 2 PQ801 PR842 0_0402_5% 1 2 PC806 DPRSLPVR_VGA +VGA_B+ PQ808 2N7002KW_SOT323-3 @ 2 G 2 PR805 10K_0402_1% 1 2 +1.05VS_VGA PJ801 D PR846 0_0402_5% 1 2 10K_0402_5% 2 PR862 1 GPU_VID0 1 +3VS 1 10K_0402_5% 2 PR861 1 GPU_VID1 DPRSLPVR_VGA 2 10K_0402_5% 2 PR860 1 GPU_VID2 <10,25,42,46,51,52,53> 2@ PR863 1 47K_0402_5% 2 1 1 @ PR838 470_0603_1% S PR841 @ 0_0402_5% PR802 147K_0402_1% 1 2VRON_VGA PD809 1 2 RB751V-40_SOD323-2 @ 1 PR803 2 @0_0402_5% SUSP# 2 PC869 2 @ JUMP_43X118 PQ809 2N7002KW_SOT323-3 GPU_VID3 <23> 10K_0402_5% 2 PR859 1 GPU_VID3 <10,25,42,46,51,52,53> 1 2 RB751V-40_SOD323-2 RB751V-40_SOD323-21 <18> NVDD_PWR_EN SUSP PR848 0_0402_5% 2 PC868 2 10U_0805_10V6K 1U_0603_10V6K TPC8A03-H_SO8 PQ807 PR845 0_0402_5% 1 2 10K_0402_5% 2 PR858 1 GPU_VID4 <46> DGPU_PWROK# <10,46,53> SUSP PD808 1 PJ806 +1.05VS 1 2 3 PR839 100K_0402_5% 1 2 PR844 0_0402_5% 1 2 10K_0402_5% 2 PR857 1 @ 2 10K_0402_5% 2 @ +1.05VS_VGA 8 7 6 5 PR840 20K_0402_1% 1 10K_0402_5% 2 PR856 1 GPU_VID0 @ PC867 10U_0805_10V6K 1 10K_0402_5% 2 PR855 1 GPU_VID1 @ 1 +1.05VS +5VALW GPU_VID4 10K_0402_5% 2 PR854 1 @ GPU_VID5 10K_0402_5% 2 PR864 1 GPU_VID3 @ GPU_VID2 10K_0402_5% 2 PR852 1 GPU_VID4 GPU_VID5 PR853 1 +3VS_VGA PR816->120K(SD034120380) PR820->1.69K(SD00000JB80) PR822->22K(SD034220280) PR837->866(SD034866080) PC858->0.1uF(SE026104M80) PC859->0.068uF(SE026683K80) PR850->22.1K(SD034221280) Compal Secret Data Security Classification Issued Date 2008/09/15 Deciphered Date 2012/07/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title PWR - VGA_COREP Size B C Document Number Rev 0.1 C38 Chief River Schematic Date: A Compal Electronics, Inc. Thursday, January 05, 2012 D Sheet 54 of 60 PC902 2 .1U_0402_16V7K 1 PR904 2 CSREFA PR955 1 2 1K_0402_1% DROOP PC937 1 2 PUT COLSE TO VCORE Phase 1 Inductor A <42> PC920 1 2 2.2U_0603_10V7K <56> 1 PR9302 0_0402_5% HG1 BST1 PC919 2 0.22U_0603_25V7K +5VS SW1A <56> SW2 <56> SW1 <56> Option for 1 phase GFX +5VS <56> <56> 1 PR9312 BST1_1 1 2.2_0603_5% PC922 2 0.22U_0603_25V7K PR928 0_0402_5% CSP2A PR9342 41.2K_0402_1% 3P: 73.2K 2P: 41.2K Option for 2 phase CPU PR935 0_0402_5% CSP3 1 CSP2 CSREF 2 PC932 1000P_0402_50V7K PC931 0.047U_0402_16V7K 3P: 1500p 2P: 1200p CSSUM PC934 2 1200P_0402_50V7K 2 PC936 680P_0402_50V7K <56> B TSENSE 1 CSP1 <56> SWN2 @ PR960 6.98K_0402_1% 2 PC927 0.047U_0402_16V7K PR9412 6.98K_0402_1% CSREF PR9452 6.98K_0402_1% SWN1 <56> PR946 1 PC924 2 .1U_0402_16V7K @ PR961 6.98K_0402_1% 1 PR9492 130K_0603_1% SWN1 1 PR9512 130K_0603_1% SWN2 2 100K_0402_1%_TSM0B104F4251RZ PUT COLSE TO VCORE HOT SPOT 1 220K_0402_5%_ERTJ0EV224J A IMVP_IMON Issued Date Compal Secret Data 2009/12/01 2012/07/11 Deciphered Date Title Compal Electronics, Inc. PWR-CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 4 PH902 1 PR952 2NTC_PH201 1 PR953 2 75K_0402_1% 165K_0402_1% PH903 Security Classification 5 3Phase: @ 2Phase: install 2 6132_PWM 1 2Phase: @ 1Phase: install 1 <56> 1 PR9242 BST2_1 1 2.2_0603_5% <56> LG1 TSENSE CSCOMP CSREF 1000P_0402_50V7K 3P: 806 2P: 1K LG2 6132P_VCCP PR921 PC918 2 BSTA1_11 2 2.2_0603_5% 0.22U_0603_25V7K <56> C 2 HG2 CSREF 1 2 2 LG1A BST2 3P: 21K 2P: 12.4K 3P: 3.65K 2P: 9.53K 3P: 23.7K 2P: 24.9K CSCOMP HG1A CSP1 CSP2 CSP3 3P: 2200p 2P: 3300p 2 2 PC933 3P: 348 2P: 1.21K 806_0402_1% 3P: 6.04K 2P: 4.32K 100K_0402_1%_TSM0B104F4251RZ +5VS 1 22P_0402_50V8J PR943 PC929 2 1COMP_CPU1 2 1 6.04K_0402_1% 1800P_0402_50V7K PR950 1 1 8.06K_0402_1% 0.033u_0402_16V7K PR942 PC928 1 2FB_CPU1 1 2 PR944 PC930 49.9_0402_1% 1 2FB_CPU3 1 2 680P_0402_50V7K 10_0402_1% 0.033u_0402_16V7K PR947 PR948 1 2 1 2 FB_CPU2 PH904 PUT COLSE TO V_GT HOT SPOT 2 PC926 2 1 1 PR940 2 1K_0402_1% 3P: 330p 2P: 1000p 1 BSTA1 2 PC923 1000P_0402_50V7K VSP 3P: 22p 2P: 10p B TRBST# 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 1 PR938 1 2 0_0402_5% VCCSENSE VSN .1U_0402_16V7K PR936 1 2 0_0402_5% PC935 1 2 <9> VGATE VSSSENSE 2 <16> <9> 1 2 VR_HOT# 2P: 36K 1P: 26.1K 6132_PWMA PWMA BSTA HGA SWA LGA BST2 HG2 SW2 NCP6132AMNR2G_QFN60_7X7 LG2 PVCC PGND LG1 SW1 HG1 BST1 TRBST# FB_CPU COMP_CPU IMVP_IMON IMON 1 2 ILIM_CPU PR939 12.4K_0402_1% DROOP 2 <42> <56> <56> PR918 1 2 26.1K_0402_1% 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PR933 10K_0402_5% CSP2A CSP1A TSENSEA DIFFA TRBSTA# FBA COMPA IMONA ILIMA DROOPA 2 1 1 PR932 @ 75_0402_1% VCC VDDBP VRDYA EN SDIO ALERT# SCLK VBOOT ROSC VRMP VRHOT# VRDY VSN VSP DIFF 24.9K_0402_1% 1 2 1 0.01U_0402_25V7K +V1.05S_VCCP SWN1A .1U_0402_16V7K PAD VSNA VSPA DIFFA TRBSTA# FBA COMPA IOUTA ILIMA DROOPA CSCOMPA CSSUMA CSREFA CSP2A CSP1A TSNSA 6132_VCC .1U_0402_16V7K PR923 1 2 54.9_0402_1% PR922 2 1 <9> VR_SVID_DAT <9> VR_SVID_ALRT# <9> VR_SVID_CLK 6.98K_0402_1% 2 PU901 1 2.2U_0603_10V7K 2 3 PR920 1 2VR_ON_CPU 4 <42> VR_ON PC917 VR_SVID_DAT1 5 0_0402_5% VR_SVID_ALRT# 6 PR927 PR925 7 VR_SVID_CLK 1 2 VBOOT 8 95.3K_0402_1% 0_0402_5% 10K_0402_1% 9 1 PR926 2VR_SVID_DAT1 1 2 ROSC_CPU 10 1 2 VRMP CPU_B+ 11 VR_HOT# 12 PR929 1K_0402_1% VGATE 13 PC921 14 +3VS 15 DIFF_CPU 130_0402_1% 1 2 .1U_0402_16V7K PC916 CSREFA TRBST# FB COMP IOUT ILIM DROOP CSCOMP CSSUM CSREF CSP3 CSP2 CSP1 TSNS DRVEN PWM PR9192 1 2_0603_5% PC915 1 2 +5VS C PR913 1 TSENSEA PC914 1 2 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 +V1.05S_VCCP CSP1A PC910 0.047U_0402_16V7K PC911 1000P_0402_50V7K 1 1PR914 2 15.8K_0402_1% CSCOMPA 2 PC912 1000P_0402_50V7K CSSUMA PR954 1 2 0_0402_5% <10> VSS_AXG_SENSE SWN1A 63.4K_0603_1% 2P: 21.5K 1P: 15.8K 1 PR937 1 2 0_0402_5% <10> VCC_AXG_SENSE PR9122 1 1 1 1800P_0402_50V7K 2 5.11K_0402_1% CSREFA 1000P_0402_50V7K 2P: 1.65K 1P: 1K PR910 22P_0402_50V8J PC909 2 COMPA1 1 2 2 1K_0402_1% PC906 1 2 DROOPA 1 1 PR906 2 1K_0402_1% 1 PR9092 1 CSCOMPA 220K_0402_5%_ERTJ0EV224J NTC_PH203 PR915 2 680P_0402_50V7K 1 2 PR9071 165K_0402_1% 1 FBA2 PC908 1 2 1 1 2 10_0402_1% PC907 1 2 D 2 PR908 2 24.9K_0402_1% 2P: 24K 1P: 24.9K 806_0402_1% PC905 0.033u_0402_16V7K PUT COLSE TO GT Inductor PH901 1 1 8.06K_0402_1% 2 2 1 FBA1 1 PR9022 1 0.033u_0402_16V7K PR903 1 PC903 1 2 10_0402_1% TRBSTA# 8.25K_0402_1% 1 8.25K_0402_1% 2 PC901 1 1 1 2 FBA3 PR905 1 2 75K_0402_1% PR901 2 D 2 PC904 1 2 1 3 680P_0402_50V7K 4 1200P_0402_50V7K 5 3 2 C38-G series Chief River Schematic Thursday, January 05, 2012 Sheet 1 55 of 60 Rev 0.1 5 4 3 2 1 2 3 PC946 2200P_0402_25V7K 2 1 PC944 0.1U_0402_25V6 2 1 PC943 10U_0805_25V6K 2 1 5 SW2 D 2 3 PR957 4.7_1206_5% PR958 1 CSREF <55> SWN1 <55> <55> LG2 4 10_0402_1% TPCA8057-H_PPAK56-8-5 PC948 V2N_CPU 2 PR959 1 10_0402_1% <55> PC949 2 680P_0603_50V7K CSREF SWN2 1 +VCC_CORE PL903 0.36UH_VMPI1004AR-R36M-Z03_30A_20% 1 4 2 2 3 2 1 TPCA8057-H_PPAK56-8-5 TPCA8065-H_PPAK56-8-5 PQ904 V1N_CPU2 1SNUB_CPU1 4 LG1 3 2 1 <55> PR956 4.7_1206_5% PQ903 <55> 4 1 4 HG2 SNUB_CPU2 5 1 <55> + + PC947 100U_25V_M 100U_25V_M 2 2 5 SW1 PQ902 CPU_B+ 1 +VCC_CORE PC950 PC942 10U_0805_25V6K 2 1 1 PL902 0.36UH_VMPI1004AR-R36M-Z03_30A_20% TPCA8065-H_PPAK56-8-5 1 <55> PL901 FBMA-L11-453215-121LMA90T_1812 1 2 3 2 1 D CPU_B+ B+ PC941 2200P_0402_25V7K 2 1 4 HG1 3 2 1 <55> PC940 0.1U_0402_25V6 2 1 PQ901 PC939 10U_0805_25V6K 2 1 5 PC938 10U_0805_25V6K 2 1 CPU_B+ 2 680P_0603_50V7K C C QC 45W CPU VID1=0.9V IccMax=94A Icc_Dyn=66A Icc_TDC=52A R_LL=1.9m ohm OCP~110A DC 35W CPU VID1=1.05V IccMax=53A Icc_Dyn=43A Icc_TDC=36A R_LL=1.9m ohm OCP~65A PQ907 <55> PC960 2200P_0402_25V7K 2 1 PC959 0.1U_0402_25V6 2 1 PC958 10U_0805_25V6K 2 1 5 PC957 10U_0805_25V6K 2 1 CPU_B+ B B 4 HG1A SW1A 5 1 <55> +VCC_GFXCORE_AXG 0.36UH_VMPI1004AR-R36M-Z03_30A_20% PR967 4.7_1206_5% 2 PQ909 4 2 3 SNUB_GFX1 4 LG1A 2 TPCA8057-H_PPAK56-8-5 1 3 2 1 5> 1 V1N_GFX 3 2 1 PL905 TPCA8065-H_PPAK56-8-5 PR971 1 CSREFA <55> SWN1A <55> 10_0402_1% PC968 2 680P_0603_50V7K A A QC 45W GT2 VID1=1.23V IccMax=46A Icc_Dyn=37A Icc_TDC=38A R_LL=3.9m ohm OCP~55A DC 35W GT2 VID1=1.23V IccMax=33A Icc_Dyn=20.2A Icc_TDC=21.5A R_LL=3.9m ohm OCP~40A Compal Secret Data Security Classification Issued Date 2009/12/01 Deciphered Date 2012/07/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title PWR-CPU_CORE Size C Date: 5 4 3 2 Compal Electronics, Inc. Document Number C38-G series Chief River Schematic Thursday, January 05, 2012 Sheet 1 56 of 60 Rev 0.1 5 4 +VCC_CORE 1 2 3 2 +VCC_CORE 1 PC1 10U_0805_6.3VAM 2 1 PC2 10U_0805_6.3VAM 2 1 PC3 10U_0805_6.3VAM 2 1 Below is 458544_CRV_PDDG_0.5 Table 5-8. +VCC_GFXCORE_AXG Socket Bottom 5 x 22 ȝF (0805) 5 x (0805) no-stuff sites Socket Top 7 x 22 ȝF (0805) 2 x (0805) no-stuff sites 1 PC4 10U_0805_6.3VAM 2 PC5 10U_0805_6.3VAM +VCC_GFXCORE_AXG D @ 2 +VCC_CORE 1 2 1 2 1 2 1 2 1 2 1 2 1 2 PC19 22U_0805_6.3V6M 1 PC18 22U_0805_6.3V6M 2 @ PC11 10U_0805_6.3VAM @ PC17 22U_0805_6.3V6M 2 1 PC10 10U_0805_6.3VAM PC16 22U_0805_6.3V6M 2 1 PC9 10U_0805_6.3VAM PC15 22U_0805_6.3V6M 2 1 PC8 10U_0805_6.3VAM PC14 22U_0805_6.3V6M 2 1 PC7 10U_0805_6.3VAM PC13 22U_0805_6.3V6M 2 1 PC6 10U_0805_6.3VAM PC12 22U_0805_6.3V6M 1 @ +V1.05S_VCCP 2 1 2 @ PC56 22U_0805_6.3V6M 2 @ 1 PC35 22U_0805_6.3V6M C 1 + 2 3 1 + @ 2 3 1 + 2 3 PC68 330U_D2_2.5V_Y_R9M 2 1 @ PC55 22U_0805_6.3V6M 1 2 @ 2 PC34 22U_0805_6.3V6M 2 PC71 22U_0805_6.3V6M 2 1 1 PC67 330U_D2_2.5V_Y_R9M 1 @ PC65 22U_0805_6.3V6M 2 2 PC54 22U_0805_6.3V6M 2 @ PC70 22U_0805_6.3V6M 2 2 1 1 PC33 22U_0805_6.3V6M 1 2 1 PC64 22U_0805_6.3V6M 2 2 PC53 22U_0805_6.3V6M 2 @ PC69 22U_0805_6.3V6M 2 1 PC63 22U_0805_6.3V6M 2 3 @ 1 PC32 22U_0805_6.3V6M 1 2 1 PC62 22U_0805_6.3V6M + 1 PC66 330U_D2_2VM_R9M 2 1 PC61 22U_0805_6.3V6M 2 3 2 1 PC60 330U_2V_M_X_LESR6M 2 3 + PC58 330U_D2_2.5V_Y_R9M C PC57 330U_D2_2.5V_Y_R9M 1 1 1 PC52 22U_0805_6.3V6M PC48 22U_0805_6.3V6M 1 PC31 22U_0805_6.3V6M 2 @ 2 2 PC51 22U_0805_6.3V6M PC47 22U_0805_6.3V6M + 1 1 1 2 PC30 22U_0805_6.3V6M 2 2 1 PC50 22U_0805_6.3V6M PC46 22U_0805_6.3V6M 2 2 1 +V1.05S_VCCP 1 1 PC29 22U_0805_6.3V6M 2 2 1 1 PC49 22U_0805_6.3V6M PC45 22U_0805_6.3V6M 2 1 2 @ PC28 22U_0805_6.3V6M 2 1 2 1 1 PC27 22U_0805_6.3V6M PC44 22U_0805_6.3V6M 1 2 1 2 @ PC26 22U_0805_6.3V6M 2 1 2 1 PC43 22U_0805_6.3V6M 1 2 1 PC42 22U_0805_6.3V6M 2 1 PC41 22U_0805_6.3V6M 1 @ PC40 22U_0805_6.3V6M 2 PC24 22U_0805_6.3V6M PC39 22U_0805_6.3V6M 2 1 PC23 22U_0805_6.3V6M PC38 22U_0805_6.3V6M 2 1 PC22 22U_0805_6.3V6M PC37 22U_0805_6.3V6M 2 1 PC21 22U_0805_6.3V6M PC36 22U_0805_6.3V6M 2 1 PC20 22U_0805_6.3V6M PC25 22U_0805_6.3V6M 1 1 D @ PC72 22U_0805_6.3V6M +VCC_CORE 1 + B 1 + PC73 PC74 330U_D2_2.5V_Y_R9M 330U_D2_2.5V_Y_R9M 2 3 2 3 1 + B 1 + PC77 330U_2V_M_X_LESR6M 2 3 PC78 330U_D2_2.5V_Y_R9M 2 3 A A Compal Secret Data Security Classification 2008/09/15 Issued Date Deciphered Date 2012/07/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. PWR - PROCESSOR DECOUPLING Size Document Number Rev 0.1 C38-G series Chief River Schematic Date: Thursday, January 05, 2012 Sheet 1 57 of 60 5 4 3 2 9HUVLRQFKDQJHOLVW 3,5/LVW ,WHP D 3* 3DJHRI IRU3:5 0RGLI\/LVW 'DWH 3KDVH To facilitate EA test P54 Change net name of pin 1 of PR825 from +VGA_CORE to +VGA_COREP 2011/10/19 DVT Sense VSSIO_SENSE_L net close to IC P53 Add PR718 2011/10/19 DVT CPU controller compensation RC tunning P55 Change PC904, PC907, PC908, PC909, PC926, PC928, PR929, PC936 and PR943 2011/10/19 DVT EMI request P51 Change PR503 2011/10/19 DVT Back to Back MOS change P49 Change PQ302 2011/12/06 PVT Sense VSSIO_SENSE_L change according to FAE P53 Add PR719 and PC721. Change PR718 and PR714 2011/12/06 PVT Add IC G718 P48 Change PR205 to 4.42k (90W) and PR210 to 27.4k (90W) 2011/12/06 PVT EC_ON RC change P50 Change PR418 from 10k to 2.2k 2011/12/06 PVT Unpop PR224 and add PR231 by HW request P48 Unpop PR224 and add PR231 2011/12/21 PVT Change CPU&GFX compensation RC by FAE recommendation P55 PR902, PR903, PR947, PR948, PC901, PC905, PC929, PC930 and PC933 2011/12/21 PVT Change charger's choke from 4.7u to 10u P49 PL302 2011/12/21 PVT C 5HDVRQIRUFKDQJH 1 D C B B A A 2009/01/06 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2012/07/11 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PIR (PWR) Rev C38-G series Chief River Schematic0.1 Date: 5 4 3 2 Sheet Thursday, January 05, 2012 1 58 of 60 5 4 3 2 1 COMPAL CONFIDENTIAL 3 3 3 10 +5VALW V B4 4 EC PQ2 PCH_RSMRST#_R A4 PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# PM_SLP_SUS# B6 H_CPUPWRGD PLT_RST# SYSON 7 12 16 CPU 6 SYSON# V +1.5V PU501 V V V PU702 +V1.05S V PU602 +V1.05S_VCCP SA_PGOOD A V 9 C 8a (DIS) U38 +5VS 8b B (DIS) U39 +3VS 8a DGPU Q8 +1.5VS PU701 +0.75VS 13 VR_ON SVID DGPU_PWR_EN PU601 +VCC_SA B 13 DGPU_PWROK 8 SUSP#,SUSP VGATE 14 11 V ON/OFF 5 PBTN_OUT# 15 V B7 SYS_PWROK PM_DRAM_PWRGD PCH V A5 EC_ON V 51ON# V V B3 C PCH_PWROK V V V B2 B+ B7 V B1 A5 V V +3VALW V PU401 +3V_PCH +5V_PCH B5 V B+ 10 V PU301 A3 VV V V A2 V BATT MODE BATT VIN V A1 D PCH_PWROK AC MODE V D MODEL NAME: Power Sequence Block Diagram LA-7981P PCB NAME: REVISION: 2011/07/13 DATE: SVID PU901 +VCC_CORE A 14 VGATE Compal Secret Data Security Classification Issued Date 2011/10/27 2012/10/27 Deciphered Date Title Compal Electronics, Inc. Power sequence THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.3 LA-7983P Date: 5 4 3 2 Thursday, January 05, 2012 Sheet 1 59 of 60 5 4 3 2 9HUVLRQFKDQJHOLVW 3,5/LVW ,WHP D 1 3DJHRI IRU+: 5HDVRQIRUFKDQJH 3* 0RGLI\/LVW 'DWH 3KDVH )RU19,',$XSGDWH6WUDSSLQJVHWWLQJ 59FKDQJHWR.RKP % 3&,(%86FRUUHFWHGIRUH[WHUQDO86%FRQWUROOHU 3&,(B35;B'7;B316ZDSSHG % 0RGLI\86%&RQWUROOHUFLUFXLW 5WRN5WRN&WR8 % 0RGLI\86%&RQWUROOHUFLUFXLW 8WR95WR9$GG5 % 0RGLI\/$1IXQFWLRQGHVLJQIRUVXUJH $GG5 5 5 5 IRU6.8 % 0RGLI\5QHDUWR/$1FKLSVLGH'HOHWH5RKP % 0RGLI\5QHDUWR/$1FKLSVLGH % $GG&+$66,6B*1'& & & % 'HOHWH555'/a'/ % D C C 5HVHUYH+'0,(0,VROXWLRQ $GG& a& % 5HVHUYH/$1(6'VROXWLRQ $GG'OLQNERWK0&7BDQGFKDVVLVWRJURXQG % &KDQJHFRPSRQHQWW\SH & FKDQJHWRW\SH % &FKDQJHWRW\SH % 5HVHUYH/$1(0,VROXWLRQ $GG5 a5 % 5HVHUYH0$,13:21RKP $GG5 & /$13RZHU6ZLWFK $GG45 & & B B A A Compal Secret Data Security Classification Issued Date 2011/10/27 2012/10/27 Deciphered Date Title Compal Electronics, Inc. HW-PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Rev 0.3 LA-7983P Thursday, January 05, 2012 Sheet 1 60 of 60 www.s-manuals.com
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Create Date : 2012:04:17 22:19:03+07:00 Creator Tool : PScript5.dll Version 5.2.2 Modify Date : 2015:11:13 22:22:30+02:00 Metadata Date : 2015:11:13 22:22:30+02:00 Producer : Acrobat Distiller 10.0.0 (Windows) Format : application/pdf Creator : Title : Compal LA-7983P - Schematics. www.s-manuals.com. Subject : Compal LA-7983P - Schematics. www.s-manuals.com. Document ID : uuid:b5af61e7-1df0-4234-98cf-b410096f8b9f Instance ID : uuid:f4475860-cf0d-4c4f-92dd-885670a19f56 Has XFA : No Page Count : 61 Keywords : Compal, LA-7983P, -, Schematics., www.s-manuals.com. Warning : [Minor] Ignored duplicate Info dictionaryEXIF Metadata provided by EXIF.tools