Compal LA 8321P Schematics. Www.s Manuals.com. R0.3 Schematics
User Manual: Notebook Dell Alienware M18x R2 - Service manuals and Schematics, Disassembly / Assembly. Free.
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A B C D E MODEL NAME : QBR10 PCB NO : LA-8321P BOM P/N : 4619H531L01 1 1 Compal Confidential 2 2 Avenger MLK rPGA Ivy Bridge + FCBGA PCH Panther Point-M + MXM Ⅲ x2 3 3 Rev: 0.3 (X02) 2011.12.08 @ : Nopop component CONN@ : ME connector 4 4 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title Cover Sheet Size B C D Rev 0.1 LA-8321P Date: A Document Number Tuesday, January 17, 2012 Sheet E 1 of 65 A B C D Compal Confidential Project Code : QBR10 File Name : LA-8321P 1 LVDS Conn HDMI to LVDS SW STDP6038 P.30 LVDS MUX LVDS MUX P.25 P.24 P.25 CRT Conn CRT MUX Thermal sensor / Fan Control EMC1412 P.41 HDMI 1.3 input Conn LVDS (DIS) MXM III Conn. CRT (DIS) HDMI MUX PEG x8 (DIS) DP Port C (DIS) DP Port B (UMA) 4C 45W, 55W PEG x8 (DIS) MXM III Conn. P.27 DP MUX Mini Card -2 Wireless Display DMC (Full) P.35 DP MUX P.29 (UMA) Mini Card-2 DMC (Full) LAN(GbE) AR8151 P.36 100MHz 5GB/s SATA Port 3 SATA Port 2 DMC USB 2.0 /3.0 Conn x 2 dual-stack IO Board USB Port 1,2 USB Port 12 Digital Camera thourgh LVDS cable Card Reader RTS5209 Express Card ( 54mm ) Power On/Off +VCCP P.43 BATTERY / OTP +1.8V P.44 DCIN / DECTOR P.45 3V/5V ALW P.31 Intel Panther Point PCH USB3.0 USB Port 3,4 USB Port 2 USB2.0 BGA 989 Balls USB Port 6 HM77 USB Port 8 P.48 +1.5V/+0.75V P.50 VCCSA P.46 P.51 CPU_CORE P.47 LS-6571P P.52 LS-6572P LS-6577P L-Speaker LED Board Touch pad Board LS-6575P LS-6608P R-Speaker LED Board Power Button Board LS-6574P LS-6578P Audio Codec Malcolm HDA015-B P.32 LPC Bus USB Charger AlienFX/ELC C8051F347 BT 2.1 /BT 3.0 VPK P.40 Amplifier x2 MAX9736 P.33 Touch Pad SPI P.38 Int.KBD P.43 Media Board BIOS ROM P.40 Media / Mode P.38 Buttons P.37~39 P.35 3 Int. Speaker 4Ω 2.5Wx 2 P.33 Subwoofer 4Ω 5W P.33 MIC + Rear LF P.25 S/PDIF Out P.33 4 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Power LED Board PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LS-6579P Title Block Diagram Size B C D Document Number Rev 0.1 LA-8321P Date: A MAX7313D x3 Head phone Jack x1 Mic phone Jack x1P.32 P.40 PS2 P.37 P.35 ENE KB930 ENE 3810 P.24 USB 2.0/3.0 Conn x 2 dual-stack P.16 LS-6573P Alienware Logo Board USB / eSATA Conn. P16~23 SPI ROM NUM/CAP LED Board USB Port 13 HD Audio SPI Media Board P.49 USB Port 11 IO Board IO Board 4 CHARGER 9 in 1 Socket 2 P.34 USB Port 0,1 Mini Card-1 WLAN (Half) Sub-board P.42 SATA ODD Conn. DisplayPort PCIE Port 5 USB Port 4 DC/DC Interface P.34 HDMI PCIE Port 4 P.35 mSATA Conn. SATA HDD-3 Conn. SATA Port 4 USB Port 9 PCIE Port 3 P.31 SATA Port 5 P.34 3 RJ45 Conn SATA HDD-2 Conn. P.34 SATA PCIE BUS PCIE Port 1 P.34 CRT USB Port 5 PCIE Port 2 SATA HDD-1 Conn. P.4~9 LVDS DP Port A DP Port D P.10,11,12,13 BANK 0, 1, 2, 3 DMI x4 gen 2 100MHz 2.7GT/s (DIS) 2 204pin DDRIII SO-DIMM x4 SATA Port 0 rPGA 989 Socket FDI x8 (UMA) P.28 CPU XDP Conn. P.5 1 SATA Port 1 DP Port B (DIS) DP Port C (UMA) PCH XDP Conn. P.16 1.5V DDRIII 1600/1333 MHz GPU P.15 mini DP Conn P.28 Dual Channel P.14 Slave HDMI 1.4 Conn P.27 (DDRIII) Memory Bus Intel Ivy Bridge Processor Master GPU P.26 P.26 E Tuesday, January 17, 2012 Sheet E 2 of 65 A Board ID Table for AD channel Vcc Ra Board ID 0 1 2 3 4 5 6 7 3.3V +/- 5% 100K +/- 5% Rb 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC USB PORT# V AD_BID min 0 V 0.168 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max 0 V 0.362 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V Board ID 0 1 2 3 4 5 6 7 POWER STATES Signal State S0 (Full ON) / M0 USB PORT# PCB Revision 0.1 0.2 0.3 0.4 1.0 USB3.0 JUSB1 0 JUSB1 1 JUSB2 1 JUSB2 2 JUSB3 2 JUSB3 3 JUSB4 3 JUSB4 4 Mini Card (WLAN) 5 Mini Card (DMC) 6 AlienFX/ELC 7 None 8 Bluetooth 9 USB / eSATA combo 10 None 11 EXPRESS CARD 12 CAMERA 13 VPK USB SLP S3# LOW SLP S4# HIGH SLP S5# HIGH HIGH S4 STATE# HIGH HIGH SLP M# ALWAYS PLANE HIGH LOW ON ON SUS PLANE ON ON RUN PLANE ON OFF CLOCKS +5VS +5VALW power plane ON +1.5V +3VS +3VALW +1.8VS +3VLP +1.5VS +3V_PCH +0.75VS OFF +3VMXM +5VMXM S4 (Suspend to DISK) / M-OFF S5 (SOFT OFF) / M-OFF DESTINATION 0 PM TABLE HIGH S3 (Suspend to RAM) / M-OFF DESTINATION BOARD ID Table LOW LOW LOW LOW HIGH LOW LOW LOW LOW LOW ON ON OFF OFF OFF OFF OFF +VCCP State +VCCSA OFF +VCC_CORE +1.5V_CPU_VDDQ S0 ON ON ON S3 ON ON OFF S5 S4/AC ON OFF OFF S5 S4/AC don't exist OFF OFF OFF 1 1 DIFFERENTIAL CLK DESTINATION FLEX CLOCKS DESTINATION SATA DESTINATION PCI EXPRESS DESTINATION CLKOUT DESTINATION CLKOUT_PCIE0 None CLKOUTFLEX0 None SATA0 HDD1 Lane 1 10/100/1G LAN PCI0 CLKOUT_PCIE1 10/100/1G LAN CLKOUTFLEX1 None SATA1 HDD2 Lane 2 MINI CARD-2 DMC PCI1 EC CLKOUT_PCIE2 MINI CARD-2 DMC CLKOUTFLEX2 None SATA2 ODD Lane 3 MINI CARD-1 WLAN PCI2 DEBUG CLKOUT_PCIE3 MINI CARD-1 WLAN CLKOUTFLEX3 None SATA3 HDD3 Lane 4 CARD READER PCI3 None CLKOUT_PCIE4 CARD READER SATA4 E-SATA Lane 5 EXPRESS CARD PCI4 None CLKOUT_PCIE5 EXPRESS CARD SATA5 mSATA Lane 6 None CLKOUT_PCIE6 None Lane 7 None CLKOUT_PCIE7 None Lane 8 None CLKOUT_PEG_A MXM I CLKOUT_PEG_B MXM II Symbol Note : Digital Ground Power plane Analog Ground Voltage PCH_LOOPBACK +3VALW +3VLP +3V_PCH 3.3V +3VS DELL CONFIDENTIAL/PROPRIETARY +3VMXM Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title Index and Config. Size Rev 0.1 LA-8321P Date: A Document Number Tuesday, January 17, 2012 Sheet 3 of 65 5 4 3 2 1 PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with - max length = 500 mils - typical impedance = 14.5 mohms 1 +VCCP RC2 24.9_0402_1% CONN@ DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 B28 B26 A24 B23 <18> <18> <18> <18> DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 <18> <18> <18> <18> DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 <18> <18> <18> <18> <18> <18> <18> <18> <18> <18> <18> <18> <18> <18> <18> <18> G21 E22 F21 D21 G22 D22 F20 C21 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 A21 H19 E19 F18 B21 C20 D18 E17 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 A22 G19 E20 G18 B20 C19 D19 F17 <18> FDI_FSYNC0 <18> FDI_FSYNC1 FDI_FSYNC0 FDI_FSYNC1 J18 J17 <18> FDI_INT FDI_INT H20 <18> FDI_LSYNC0 <18> FDI_LSYNC1 FDI_LSYNC0 FDI_LSYNC1 J19 H17 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC +VCCP 2 +EDP_COM A18 A17 B16 24.9_0402_1% C15 D15 B C17 F16 C16 G15 C18 E16 D16 F15 eDP_COMPIO eDP_ICOMPO eDP_HPD# eDP_AUX eDP_AUX# eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] eDP RC14 1 eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] PCI EXPRESS* - GRAPHICS <18> <18> <18> <18> PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO DMI B27 B25 A25 B24 Intel(R) FDI C DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 CONN@ 2 JCPUA D <18> <18> <18> <18> JCPUI PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] J22 J21 H22 PEG_COMP K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32 PEG_GTX_C_HRX_N0 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_N12 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N14 PEG_GTX_C_HRX_N15 CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC10 CC11 CC12 CC13 CC14 CC15 CC16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D PEG_GTX_HRX_N0 PEG_GTX_HRX_N1 PEG_GTX_HRX_N2 PEG_GTX_HRX_N3 PEG_GTX_HRX_N4 PEG_GTX_HRX_N5 PEG_GTX_HRX_N6 PEG_GTX_HRX_N7 PEG_GTX_HRX_N8 PEG_GTX_HRX_N9 PEG_GTX_HRX_N10 PEG_GTX_HRX_N11 PEG_GTX_HRX_N12 PEG_GTX_HRX_N13 PEG_GTX_HRX_N14 PEG_GTX_HRX_N15 J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32 PEG_GTX_C_HRX_P0 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_P15 CC17 CC18 CC19 CC20 CC21 CC22 CC23 CC24 CC25 CC26 CC27 CC28 CC29 CC30 CC31 CC32 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D PEG_GTX_HRX_P0 PEG_GTX_HRX_P1 PEG_GTX_HRX_P2 PEG_GTX_HRX_P3 PEG_GTX_HRX_P4 PEG_GTX_HRX_P5 PEG_GTX_HRX_P6 PEG_GTX_HRX_P7 PEG_GTX_HRX_P8 PEG_GTX_HRX_P9 PEG_GTX_HRX_P10 PEG_GTX_HRX_P11 PEG_GTX_HRX_P12 PEG_GTX_HRX_P13 PEG_GTX_HRX_P14 PEG_GTX_HRX_P15 M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 PEG_HTX_GRX_N0 PEG_HTX_GRX_N1 PEG_HTX_GRX_N2 PEG_HTX_GRX_N3 PEG_HTX_GRX_N4 PEG_HTX_GRX_N5 PEG_HTX_GRX_N6 PEG_HTX_GRX_N7 PEG_HTX_GRX_N8 PEG_HTX_GRX_N9 PEG_HTX_GRX_N10 PEG_HTX_GRX_N11 PEG_HTX_GRX_N12 PEG_HTX_GRX_N13 PEG_HTX_GRX_N14 PEG_HTX_GRX_N15 CC33 CC34 CC35 CC36 CC37 CC38 CC39 CC40 CC41 CC42 CC43 CC44 CC45 CC46 CC47 CC48 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N15 M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25 PEG_HTX_GRX_P0 PEG_HTX_GRX_P1 PEG_HTX_GRX_P2 PEG_HTX_GRX_P3 PEG_HTX_GRX_P4 PEG_HTX_GRX_P5 PEG_HTX_GRX_P6 PEG_HTX_GRX_P7 PEG_HTX_GRX_P8 PEG_HTX_GRX_P9 PEG_HTX_GRX_P10 PEG_HTX_GRX_P11 PEG_HTX_GRX_P12 PEG_HTX_GRX_P13 PEG_HTX_GRX_P14 PEG_HTX_GRX_P15 CC49 CC50 CC51 CC52 CC53 CC54 CC55 CC56 CC57 CC58 CC59 CC60 CC61 CC62 CC63 CC64 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P15 PEG_GTX_HRX_N[0..15] <14,15> PEG_GTX_HRX_P[0..15] <14,15> PEG_HTX_C_GRX_N[0..15] <14,15> PEG_HTX_C_GRX_P[0..15] <14,15> T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS D F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3 C B Near MXM Connector TYCO_2134146-3_IVYBRIDGE~D TYCO_2134146-3_IVYBRIDGE~D A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title PROCESSOR(1/6) DMI,FDI,PEG Size 4 3 2 Rev 0.1 LA-8321P Date: 5 Document Number Tuesday, January 17, 2012 Sheet 1 4 of 65 5 4 3 +VCCP 2 1 +VCCP +3VALW +3VS PBTN_OUT# <7> <16,18,53> CFG0 VGATE +3VALW 5,43> PCH_SMBDATA 5,43> PCH_SMBCLK <16> PCH_JTAG_TCK 1K_0402_5% @1 0_0402_5% @ @1 2 RC5 H_CPUPWRGD_XDP 2 RC6 CFD_PWRBTN#_XDP 1K_0402_5% @1 0_0402_5% @1 1K_0402_5% @1 2 RC7 XDP_HOOK2 2 RC9 SYS_PWROK_XDP 2 RC3 0_0402_5% @1 2 RC98 XDP_TCK1 XDP_TCK The resistor for HOOK2 should be placed such that the stub is very small on CFG0 net CFG0 CFG1 <7> <7> CFG2_R CFG3_R @ RC88 1 @ RC89 1 2 2 0_0402_5% 0_0402_5% CFG2 CFG3 <7> <7> CFG8_R CFG9_R @ RC90 1 @ RC91 1 2 2 0_0402_5% 0_0402_5% CFG8 CFG9 <7> <7> RC18 10K_0402_5%~D 2 <16,18,53> VGATE @ R1905 1 @ RC92 1 @ RC93 1 2 2 0_0402_5% 0_0402_5% CFG4 CFG5 <7> <7> CFG6_R CFG7_R @ RC94 1 @ RC95 1 2 2 0_0402_5% 0_0402_5% CFG6 CFG7 <7> <7> RC12 200_0402_1% 2 0_0402_5% 1 B 2 <18> PM_DRAM_PWRGD UC2 A VDDPWRGOOD 4 Y D MC74VHC1G09DFT2G_SC70-5 2 CFG4_R CFG5_R CLK_CPU_ITP CLK_CPU_ITP# XDP_RST#_R RC8 XDP_DBRESET# RC58 10K_0402_5%~D 1 0_0402_5% 0_0402_5% 2 2 2 5 @ RC86 1 @ RC87 1 1 1 CFG0_R CFG1_R CC156 0.1U_0402_25V6K~D 2 <7> <7> 2 CFG16 CFG17 R1910 100K_0402_5% @ RC64 39_0402_1% 1 H_CPUPWRGD 16,18,40> 0_0402_5% 0_0402_5% CLK_CPU_ITP <17> CLK_CPU_ITP# <17> 2 @ XDP_TDO @ RC99 1 XDP_TRST# XDP_TDI @ RC100 1 XDP_TMS @ RC101 1 1 1K_0402_5% PLT_RST# RUN_ON_CPU1.5VS3# <9,42> RUN_ON_CPU1.5VS3# 2 0_0402_5% PCH_JTAG_TDO 2 0_0402_5% 2 0_0402_5% PCH_JTAG_TDI <16> PCH_JTAG_TMS <16> 1 XDP_BPM#6 XDP_BPM#7 2 2 D 3 XDP_BPM#4 XDP_BPM#5 @ RC84 1 @ RC85 1 S @ QC1 2N7002E-T1-E3_SOT23-3 2 G <16> +3VALW +VCCP 1 RC4 75_0402_1% 2 PLT_RST# A T137 @ H_CATERR# AL33 AN33 <20,40> H_PECI CATERR# PECI RC57 B 1 2 56_0402_5% <40,45> H_PROCHOT# H_PROCHOT#_R H_THRMTRIP# <20> H_THRMTRIP# AL32 AN32 CLOCKS PAD~D SKTOCC# PROCHOT# THERMTRIP# BCLK BCLK# A28 A27 CLK_CPU_DMI_R CLK_CPU_DMI#_R A16 A15 CLK_CPU_DPLL CLK_CPU_DPLL# @ RC13 1 @ RC15 1 2 0_0402_5%~D 2 0_0402_5%~D DPLL_REF_CLK DPLL_REF_CLK# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] R8 H_DRAMRST# AK1 A5 A4 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 H_DRAMRST# 1 2 @ RC25 VDDPWRGOOD 1 RC28 H_CPUPWRGD_R 0_0402_5%~D 2 VDDPWRGOOD_R 130_0402_1% BUF_CPU_RST# AP33 V8 AR33 PM_SYNC UNCOREPWRGOOD SM_DRAMPWROK RESET# A JTAG & BPM <20> H_CPUPWRGD AM34 PWR MANAGEMENT 1 @ RC22 SN74LVC1G07DCKR_SC70-5 CLK_CPU_DMI <17> CLK_CPU_DMI# <17> CLK_CPU_DPLL# RU25 1 2 1K_0402_5% CLK_CPU_DPLL RU24 1 2 1K_0402_5% +3VS Processor Pullups +VCCP 62_0402_5%1 2 XDP_DBRESET# 1K_0402_5% 1 TCK TMS TRST# TDI TDO DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] AP29 AP27 XDP_PRDY# XDP_PREQ# AR26 AR27 AP30 XDP_TCK XDP_TMS XDP_TRST# AR28 AP26 XDP_TDI_R XDP_TDO_R AL35 XDP_DBRESET#_R AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R XDP_BPM#4_R XDP_BPM#5_R XDP_BPM#6_R XDP_BPM#7_R @ RC23 1 @ RC24 1 @ RC26 1 @ RC30 @ RC31 @ RC33 @ RC34 @ RC36 @ RC37 @ RC38 @ RC39 1 1 1 1 1 1 1 1 2 0_0402_5% 2 0_0402_5% 2 2 2 2 2 2 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7 +VCCP RC44 XDP_TDI XDP_TDO 2 0_0402_5%~D XDP_DBRESET# B PU/PD for JTAG signals 2 RC19 H_CPUPWRGD_R 10K_0402_5%~D 1 PRDY# PREQ# <18> H_PM_SYNC C BUF_CPU_RST# <6> H_PROCHOT# 2 H_PM_SYNC_R 0_0402_5%~D RC10 1 2 43_0402_1% BUFO_CPU_RST# +VCCP SM_DRAMRST# DDR3 MISC AN34 PROC_SELECT# THERMAL C26 <20> H_SNB_IVB# 4 CONN@ MISC JCPUB UC1 Y 3 <16,19,31,35,40,43> NC G 1 C P 5 2 2 CC140 0.1U_0402_25V6K~D 1 CFG10 CFG11 XDP_BPM#2 XDP_BPM#3 1 RC112 CFG10_R 1 RC113 CFG11_R @2 @2 CFG16_R CFG17_R G VCC <7> <7> XDP_BPM#0 XDP_BPM#1 +1.5V_CPU_VDDQ 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 3 D 0_0402_5% 0_0402_5% 2 XDP_PREQ# XDP_PRDY# GND0 GND1 OBSFN_A0 OBSFN_C0 OBSFN_A1 OBSFN_C1 GND2 GND3 OBSDATA_A0 OBSDATA_C0 OBSDATA_A1 OBSDATA_C1 GND4 GND5 OBSDATA_A2 OBSDATA_C2 OBSDATA_A3 OBSDATA_C3 GND6 GND7 OBSFN_B0 OBSFN_D0 OBSFN_B1 OBSFN_D1 GND8 GND9 OBSDATA_B0 OBSDATA_D0 OBSDATA_B1 OBSDATA_D1 GND10 GND11 OBSDATA_B2 OBSDATA_D2 OBSDATA_B3 OBSDATA_D3 GND12 GND13 PWRGOOD/HOOK0 ITPCLK/HOOK4 HOOK1 ITPCLK#/HOOK5 VCC_OBS_AB VCC_OBS_CD HOOK2 RESET#/HOOK6 HOOK3 DBR#/HOOK7 GND14 GND15 SDA TD0 SCL TRST# TCK1 TDI TCK0 TMS GND16 GND17 SAMTE_BSH-030-01-L-D-A CONN@ 1 2 @ +3V_PCH JCPUXDP 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 @ 1 CC66 0.1U_0402_25V6K~D CC65 0.1U_0402_25V6K~D 1 2 RC21 DDR3 Compensation Signals XDP_DBRESET# <16,18> SM_RCOMP0 140_0402_1% 1 2 RC42 SM_RCOMP1 25.5_0402_1%~D 1 2 RC43 SM_RCOMP2 200_0402_1% 1 2 RC45 XDP_TMS 51_0402_5% 1 XDP_TDI_R 51_0402_5% 1 2 RC27 XDP_PREQ# 51_0402_5% 1 XDP_TDO_R 51_0402_5% 1 2 RC35 XDP_TCK 51_0402_5% 1 2 RC40 XDP_TRST# 51_0402_5% 1 2 RC41 2 RC29 @ 2 RC32 A TYCO_2134146-3_IVYBRIDGE~D DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title PROCESSOR(2/6) PM,XDP,CLK Size Document Number Date: Tuesday, January 17, 2012 Rev 0.1 LA-8321P Sheet 1 5 of 65 5 4 2 CONN@ JCPUD <10,12> DDR_A_D[0..63] C B C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 AE10 AF10 V6 <10,12> DDR_A_BS0 <10,12> DDR_A_BS1 <10,12> DDR_A_BS2 AE8 AD9 AF9 <10,12> DDR_A_CAS# <10,12> DDR_A_RAS# <10,12> DDR_A_WE# SA_CK[0] SA_CLK#[0] SA_CKE[0] SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_CK[1] SA_CLK#[1] SA_CKE[1] SA_CK[2] SA_CLK#[2] SA_CKE[2] SA_CK[3] SA_CLK#[3] SA_CKE[3] SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3] SA_ODT[0] SA_ODT[1] SA_ODT[2] SA_ODT[3] DDR SYSTEM MEMORY A DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 D 1 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] SA_BS[0] SA_BS[1] SA_BS[2] SA_CAS# SA_RAS# SA_WE# AB6 AA6 V9 M_CLK_DDR0 M_CLK_DDR#0 DDR_CKE0_DIMMA0 M_CLK_DDR0 <12> M_CLK_DDR#0 <12> DDR_CKE0_DIMMA0 <12> AA5 AB5 V10 M_CLK_DDR1 M_CLK_DDR#1 DDR_CKE1_DIMMA0 M_CLK_DDR1 <12> M_CLK_DDR#1 <12> DDR_CKE1_DIMMA0 <12> AB4 AA4 W9 M_CLK_DDR4 M_CLK_DDR#4 DDR_CKE4_DIMMA1 M_CLK_DDR4 <10> M_CLK_DDR#4 <10> DDR_CKE4_DIMMA1 <10> AB3 AA3 W10 M_CLK_DDR5 M_CLK_DDR#5 DDR_CKE5_DIMMA1 M_CLK_DDR5 <10> M_CLK_DDR#5 <10> DDR_CKE5_DIMMA1 <10> AK3 AL3 AG1 AH1 DDR_CS0_DIMMA0# DDR_CS1_DIMMA0# DDR_CS4_DIMMA1# DDR_CS5_DIMMA1# DDR_CS0_DIMMA0# DDR_CS1_DIMMA0# DDR_CS4_DIMMA1# DDR_CS5_DIMMA1# AH3 AG3 AG2 AH2 M_ODT0 M_ODT1 M_ODT4 M_ODT5 M_ODT0 M_ODT1 M_ODT4 M_ODT5 C4 G6 J3 M6 AL6 AM8 AR12 AM15 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 D4 F6 K3 N6 AL5 AM9 AR11 AM14 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 <11,13> DDR_B_D[0..63] DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 <12> <12> <10> <10> <12> <12> <10> <10> DDR_A_DQS#[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..15] CONN@ <10,12> <10,12> <10,12> <11,13> <11,13> <11,13> DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 <11,13> <11,13> <11,13> DDR_B_CAS# DDR_B_RAS# DDR_B_WE# C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 AA9 AA7 R6 AA10 AB8 AB9 SB_CK[0] SB_CLK#[0] SB_CKE[0] SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] SB_CK[1] SB_CLK#[1] SB_CKE[1] SB_CK[2] SB_CLK#[2] SB_CKE[2] SB_CK[3] SB_CLK#[3] SB_CKE[3] SB_CS#[0] SB_CS#[1] SB_CS#[2] SB_CS#[3] DDR SYSTEM MEMORY B JCPUC 3 SB_ODT[0] SB_ODT[1] SB_ODT[2] SB_ODT[3] SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] SB_BS[0] SB_BS[1] SB_BS[2] SB_CAS# SB_RAS# SB_WE# AE2 AD2 R9 M_CLK_DDR2 M_CLK_DDR#2 DDR_CKE2_DIMMB0 AE1 AD1 R10 M_CLK_DDR3 M_CLK_DDR#3 DDR_CKE3_DIMMB0 AB2 AA2 T9 M_CLK_DDR6 M_CLK_DDR#6 DDR_CKE6_DIMMB1 AA1 AB1 T10 M_CLK_DDR7 M_CLK_DDR#7 DDR_CKE7_DIMMB1 AD3 AE3 AD6 AE6 DDR_CS2_DIMMB0# DDR_CS3_DIMMB0# DDR_CS6_DIMMB1# DDR_CS7_DIMMB1# AE4 AD4 AD5 AE5 M_ODT2 M_ODT3 M_ODT6 M_ODT7 D7 F3 K6 N3 AN5 AP9 AK12 AP15 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 C7 G3 J6 M3 AN6 AP8 AK11 AP14 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 D M_CLK_DDR2 <13> M_CLK_DDR#2 <13> DDR_CKE2_DIMMB0 <13> M_CLK_DDR3 <13> M_CLK_DDR#3 <13> DDR_CKE3_DIMMB0 <13> M_CLK_DDR6 <11> M_CLK_DDR#6 <11> DDR_CKE6_DIMMB1 <11> M_CLK_DDR7 <11> M_CLK_DDR#7 <11> DDR_CKE7_DIMMB1 <11> DDR_CS2_DIMMB0# DDR_CS3_DIMMB0# DDR_CS6_DIMMB1# DDR_CS7_DIMMB1# M_ODT2 M_ODT3 M_ODT6 M_ODT7 <13> <13> <11> <11> <13> <13> <11> <11> DDR_B_DQS#[0..7] C <11,13> DDR_B_DQS[0..7] <11,13> DDR_B_MA[0..15] <11,13> B TYCO_2134146-3_IVYBRIDGE~D TYCO_2134146-3_IVYBRIDGE~D 1 +1.5V 2 RC49 1K_0402_5% D S H_DRAMRST# 3 1 DDR3_DRAMRST#_R 2 2 1K_0402_5% DDR3_DRAMRST# <10,11,12,13> BSS138_SOT23~D 2 QC2 G RC50 4.99K_0402_1% 1 RC124 1 <5> H_DRAMRST# A A <10,11,17> DRAMRST_CNTRL_PCH <40> DRAMRST_CNTRL_EC 1 2 @ RC46 1 @RC47 @ RC47 DRAMRST_CNTRL 0_0402_5%~D 2 0_0402_5% 2 5 DELL CONFIDENTIAL/PROPRIETARY 1 CC177 0.047U_0402_16V7K~D Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 4 3 2 Title PROCESSOR(3/6) DDRIII Size Document Number Date: Tuesday, January 17, 2012 Rev 0.1 LA-8321P Sheet 1 6 of 65 5 4 3 2 1 CFG Straps for Processor D D 1 CFG2 CONN@ @RC51 @ RC51 1K_0402_1% 2 JCPUE RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 AH27 AH26 @ T7 @ T8 PAD~D PAD~D L7 AG7 AE7 AK2 @ T1 @ T2 @ T9 @ T10 PAD~D PAD~D PAD~D PAD~D W8 @ T11 PAD~D AT26 AM33 AJ27 @ T12 @ T14 @ T16 PAD~D PAD~D PAD~D T8 J16 H16 G16 @ T4 @ T18 @ T19 @ T21 PAD~D PAD~D PAD~D PAD~D AR35 AT34 AT33 AP35 AR34 @ T23 @ T25 @ T27 @ T29 @ T31 PAD~D PAD~D PAD~D PAD~D PAD~D B34 A33 A34 B35 C35 @ T33 @ T34 @ T35 @ T40 @ T42 PAD~D PAD~D PAD~D PAD~D PAD~D CFG4 PAD~D T28 @ AJ26 VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE 2 @ RC121 50_0402_1% 1 1 2 VSS_VAL_SENSE @ RC123 50_0402_1% INTEL 12/28 recommand to add RC120, RC121, RC122, RC123 Please place as close as JCPU1 PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D T36 T37 T38 T39 T41 T43 T44 T45 T46 T48 T49 T50 T51 T53 T55 T56 @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 PAD~D PAD~D T57 @ T58 @ J20 B18 PAD~D T62 @ J15 C RSVD5 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD27 B RSVD_NCTF1 RSVD_NCTF2 RSVD_NCTF3 RSVD_NCTF4 RSVD_NCTF5 Display Port Presence Strap CFG4 1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port RSVD_NCTF6 RSVD_NCTF7 RSVD_NCTF8 RSVD_NCTF9 RSVD_NCTF10 CFG6 CFG5 1 VSS_AXG_VAL_SENSE 1:(Default) Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed RSVD51 RSVD52 @ T47 @ T59 AJ32 AK32 RC54 1K_0402_1% PAD~D PAD~D @RC53 @ RC53 1K_0402_1% 2 C AJ31 AH31 AJ33 AH33 CFG2 @ RC52 1K_0402_1% RSVD37 RSVD38 RSVD39 RSVD40 RESERVED 1 VCC_AXG_VAL_SENSE VSS_AXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE PEG Static Lane Reversal - CFG2 is for the 16x 1 CFG16 CFG17 VCC_DIE_SENSE VSS_DIE_SENSE 2 <5> <5> CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] 1 @ RC120 50_0402_1% AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 1 2 @ RC122 50_0402_1% CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 T5 @ T20 @ T24 @ T22 @ CFG16 CFG17 BCLK_ITP BCLK_ITP# RSVD_NCTF11 RSVD_NCTF12 RSVD_NCTF13 AN35 AM35 CLK_RES_ITP <17> CLK_RES_ITP# <17> @ T60 @ T61 @ T63 AT2 AT1 AR1 PAD~D PAD~D PAD~D PCIE Port Bifurcation Straps B 11: (Default) x16 - Device 1 functions 1 and 2 disabled Need PWR add new circuit on 1.05V(refer CRB) KEY 2 2 +VCC_CORE CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 PAD~D PAD~D PAD~D PAD~D CFG +VCC_GFXCORE_AXG <5> <5> <5> <5> <5> <5> <5> <5> <5> <5> <5> <5> @ T64 B1 PAD~D CFG[6:5] TYCO_2134146-3_IVYBRIDGE~D 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled 1 CFG7 2 @ RC56 1K_0402_1% PEG DEFER TRAINING CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title PROCESSOR(4/6) RSVD,CFG Size Document Number Date: Tuesday, January 17, 2012 Rev 0.1 LA-8321P Sheet 1 7 of 65 5 4 3 JCPUF CONN@ 2 1 POWER +VCC_CORE PEG AND DDR VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 PDDG 0.7@P12 AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 D E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 C J23 +VCCP 1 1 Place the PU resistors close to CPU VIDALERT# VIDSCLK VIDSOUT AJ29 AJ30 AJ28 H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT RC61 1 @ RC59 1 @ RC65 1 2 RC60 75_0402_1% 2 RC63 130_0402_1% 2 43_0402_1% 2 0_0402_5%~D 2 0_0402_5%~D VR_SVID_ALRT# <53,55> VR_SVID_CLK <53,55> VR_SVID_DAT <53,55> B 1 +VCC_CORE 2 RC66 100_0402_1% AJ35 VCCSENSE_R AJ34 VSSSENSE_R @ RC67 1 @RC67 @RC68 @ RC68 1 2 0_0402_5%~D 2 0_0402_5%~D VCCSENSE VSSSENSE <53> <53> 1 VCC_SENSE VSS_SENSE VCCIO_SENSE VSS_SENSE_VCCIO B10 A10 VCCIO_SENSE VSSIO_SENSE VCCIO_SENSE RC70 100_0402_1% <49> +VCCP VCCIO_SENSE VSSIO_SENSE RC1701 1 RC1702 1 2 B VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 VCCIO40 SVID C +VCCP 8.5A VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 SENSE LINES AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 CORE SUPPLY 94AAG35 D 2 10_0402_5%~D 2 10_0402_5%~D A A 0902 RC1701 and RC1702 near close to CPU, ask power to remove PR111 and PR104 TYCO_2134146-3_IVYBRIDGE~D DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title PROCESSOR(5/6) PWR,BYPASS Size Document Number Date: Tuesday, January 17, 2012 Rev 0.1 LA-8321P Sheet 1 8 of 65 5 4 3 2 1 +1.5V_CPU_VDDQ Source QC3 AO4728L_SO8~D D 5 @ RC77 1 <40> CPU1.5V_S3_GATE @ RC79 1 2 0_0402_5% 6 SUSP# S 2 S QC4B DMN66D0LDW-7 2 2 1 +1.5V_CPU_VDDQ RC118 1K_0402_1%~D G +VCC_GFXCORE_AXG QC4A DMN66D0LDW-7 RUN_ON_CPU1.5VS3# <5,42> RC119 1K_0402_1%~D +VCC_GFXCORE_AXG 2 +VCC_GFXCORE_AXG 2 0_0402_5%~D +V_SM_VREF_CNT 1 <21,40,42,43,49,50,51> 1 4 G D 1 2 AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25 1 1 3 RUN_ON_CPU1.5VS3# CC136 0.1U_0603_50V7K~D D RC75 330K_0402_5%~D 2 RUN_ON_CPU1.5VS3 JCPUH 1 2 2 4 RC72 100K_0402_5% RC74 100K_0402_5% +1.5V_CPU_VDDQ 1 2 3 2 1 1 8 7 6 5 RC73 20K_0402_5% B+_BIAS CC135 10U_0805_25V6K~D +1.5V +3VALW SENSE LINES VAXG_SENSE VSSAXG_SENSE B4 D1 +V_DDR_REFA_R +V_DDR_REFB_R <10> <11> AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1 1 0.1U_0402_25V6K~D CC178 2 1 0.1U_0402_25V6K~D CC182 2 1 0.1U_0402_25V6K~D 1 2 +1.5V PAD-OPEN 4x4m 2 1 2 1 2 1 2 1 + 2 PJP30 OPEN CC167 330U_D2_2.5VM_R6M~D2 1 CC166 10U_0805_25V6K~D 2 1 CC165 10U_0805_25V6K~D 1 CC164 10U_0805_25V6K~D DDR3 -1.5V RAILS 1 0.1U_0402_25V6K~D 2 @ PJP30 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 +VCCSA 1 2 1 2 1 2 1 2 @ 1 + 2 CC172 330U_D2_2.5VM_R6M~D H23 VCCSA_SENSE H_FC_C22 H_FC_C22 VCCSA_SEL C B <52> <52> <52> 1 C22 C24 VSS D TYCO_2134146-3_IVYBRIDGE~D VCCSA_VID[0] VCCSA_VID[1] 6A CC171 10U_0603_6.3V6M~D VCCSA_SENSE M27 M26 L26 J26 J25 J24 H26 H25 CC170 10U_0805_25V6K~D VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 CC169 10U_0805_25V6K~D 1.8V RAIL 2 CC150 +1.5V_CPU_VDDQ CC163 10U_0805_25V6K~D VCCPLL1 VCCPLL2 VCCPLL3 CC149 AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 @RC55 @ RC55 VCCIO_SEL A19 H_VCCP_SEL 1 2 0_0402_5%~D VCCP_PWRCTRL <49> @ RC81 0_0402_5% 2 VREF SA_DIMM_VREFDQ SB_DIMM_VREFDQ CC168 10U_0805_25V6K~D 2 B6 A6 A2 +V_SM_VREF_CNT AL1 CC162 10U_0805_25V6K~D 2 1 CC175 1U_0402_6.3V6K~D 2 1 CC174 1U_0402_6.3V6K~D 2 1 CC173 10U_0805_25V6K~D + CC176 330U_D2_2.5VM_R6M~D 1 +1.8VS_VCCPLL QC5 Follow E3 Macallan 13" <55> <55> 5A TBD 2 0_0805_5%~D VCC_AXG_SENSE VSS_AXG_SENSE +V_SM_VREF should have 10 mil trace width SM_VREF +1.8VS @ RC80 1 AK35 AK34 CC161 10U_0805_25V6K~D B VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 POWER SA RAIL C AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 CONN@ MISC 33A JCPUG GRAPHICS PJP34 PAD-OPEN 4x4m 1 1 PJP33 PAD-OPEN 4x4m 1 PJP31 PAD-OPEN 4x4m 2 2 2 +VCC_GFXCORE_AXG_P CONN@ VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 TYCO_2134146-3_IVYBRIDGE~D A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title PROCESSOR(6/6) PWR,VSS Size Document Number Date: Tuesday, January 17, 2012 Rev 0.1 LA-8321P Sheet 1 9 of 65 3 RD1 0_0402_5%~D @ 2 2 QD1 3 BSS138_NL_SOT23-3 S D 1 +V_DDR_REFA_R <9> 1 DDR_A_D2 DDR_A_D7 2 DDR_A_D8 DDR_A_D9 DRAMRST_CNTRL_PCH DDR_A_DQS#1 DDR_A_DQS1 2 <6,11,17> 2 DDR_A_D4 DDR_A_D5 RD16 1K_0402_5%~D @ G 2 1 +V_DDR_REFA 1 +1.5V +DIMM0_VREF CD2 2 0_0402_5%~D CD1 @ RD15 1 D RD8 1K_0402_1%~D 0.1U_0402_25V6K~D M3 Circuit (Processor Generated SO-DIMM VREF_DQ) 2.2U_0603_10V7K~D 1 2 <6,12> DDR_A_MA[0..15] DDR_A_D10 DDR_A_D15 DDR_A_D21 DDR_A_D20 DDR_A_DQS#2 DDR_A_DQS2 Layout Note: Place near JDIMMA DDR_A_D19 DDR_A_D18 DDR_A_D28 DDR_A_D29 +1.5V 2 1 CD6 1 CD5 2 1U_0402_6.3V6K~D 1 CD4 2 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D CD3 1U_0402_6.3V6K~D C 1 DDR_A_D26 DDR_A_D27 2 DDR_CKE4_DIMMA1 <6> DDR_CKE4_DIMMA1 DDR_A_BS2 <6,12> DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 +1.5V DDR_A_MA3 DDR_A_MA1 2 @ 1 + 2 <6> M_CLK_DDR4 <6> M_CLK_DDR#4 CD14 330U_SX_2VY~D 2 1 CD13 2 1 10U_0603_6.3V6M~D CD12 2 1 10U_0603_6.3V6M~D CD11 2 1 10U_0603_6.3V6M~D CD10 2 1 10U_0603_6.3V6M~D CD9 1 10U_0603_6.3V6M~D CD8 2 10U_0603_6.3V6M~D CD7 10U_0603_6.3V6M~D 1 M_CLK_DDR4 M_CLK_DDR#4 <6,12> DDR_A_BS0 DDR_A_MA10 DDR_A_BS0 <6,12> DDR_A_WE# <6,12> DDR_A_CAS# DDR_A_WE# DDR_A_CAS# DDR_A_MA13 DDR_CS5_DIMMA1# <6> DDR_CS5_DIMMA1# DDR_A_D41 DDR_A_D40 +0.75VS DDR_A_D42 DDR_A_D43 +3VS DDR_A_D55 DDR_A_D54 2 2 DDR_A_DQS#6 DDR_A_DQS6 2 2 1 CD20 1U_0402_6.3V6K~D 2 1 CD19 1U_0402_6.3V6K~D 1 CD18 1U_0402_6.3V6K~D 2 CD17 1U_0402_6.3V6K~D 1 DDR_A_D48 DDR_A_D49 DDR_A_D60 DDR_A_D61 @ R1832 10K_0402_5%~D DDR_A_D63 DDR_A_D62 1 1 R1831 10K_0402_5%~D 2 2 +3VS 2 1 1 CD21 1 1 2 CD22 2.2U_0603_10V7K~D RD3 10K_0402_5%~D 0.1U_0402_25V6K~D @ RD2 10K_0402_5%~D A +0.75VS 205 G1 G2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DIMM A0 REV TYPE (H9.2) DDR_A_D1 DDR_A_D0 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D3 DDR_A_D6 D DDR_A_D12 DDR_A_D13 DDR3_DRAMRST# DDR3_DRAMRST# <6,11,12,13> DDR_A_D14 DDR_A_D11 DDR_A_D17 DDR_A_D16 DDR_A_D22 DDR_A_D23 TOP CPU DDR_A_D24 DDR_A_D31 DDR_A_DQS#3 DDR_A_DQS3 BOT CH A1 (H9.2)(Rev) CH B1 (H5.2)(Rev) CH B0 (H5.2)(Std) DDR_A_D30 DDR_A_D25 CH A0 (H9.2) (Std) DDR_CKE5_DIMMA1 DDR_CKE5_DIMMA1 DIMM A0 DIMM B0 DIMM B1 DIMM A1 <6> C DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR5 M_CLK_DDR#5 DDR_A_BS1 DDR_A_RAS# DDR_CS4_DIMMA1# M_ODT4 M_ODT5 M_CLK_DDR5 M_CLK_DDR#5 <6> <6> DDR_A_BS1 DDR_A_RAS# <6,12> <6,12> +1.5V DDR_CS4_DIMMA1# M_ODT4 <6> M_ODT5 <6> RD9 1K_0402_1% <6> +VREF_CA DDR_A_D32 DDR_A_D33 DDR_A_D35 DDR_A_D38 DDR_A_D44 DDR_A_D45 1 2 RD10 1K_0402_1% 1 2 CD16 DDR_A_D34 DDR_A_D39 B CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 CD15 DDR_A_DQS#4 DDR_A_DQS4 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 0.1U_0402_25V6K~D Layout Note: Place near JDIMMA.203,204 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 2.2U_0603_10V7K~D DDR_A_D37 DDR_A_D36 +1.5V JDIMMA0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 1 RD7 1K_0402_1%~D <6,12> DDR_A_D[0..63] 2 +V_DDR_REFA 1 1 +1.5V <6,12> DDR_A_DQS[0..7] 2 2 <6,12> DDR_A_DQS#[0..7] 1 4 1 5 B DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D53 DDR_A_D52 DDR_A_D51 DDR_A_D50 DDR_A_D56 DDR_A_D57 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D59 DDR_A_D58 M_THERMAL# PCH_SMBDATA PCH_SMBCLK M_THERMAL# <11,12,13,40> PCH_SMBDATA <5,11,12,13,16,17,34,35,43> PCH_SMBCLK <5,11,12,13,16,17,34,35,43> +0.75VS 206 TYCO_2-2013311-1 CONN@ A CIS link OK DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title DDRIII DIMMA0 Size Document Number Date: Tuesday, January 17, 2012 Rev 0.1 LA-8321P Sheet 1 10 of 65 5 4 3 2 1 +1.5V +V_DDR_REFB 1 <6,13> DDR_B_DQS[0..7] 1 <6,13> DDR_B_DQS#[0..7] <6,13> DDR_B_D[0..63] <6,13> DDR_B_MA[0..15] RD4 0_0402_5%~D @ +1.5V 2 2 RD11 1K_0402_1%~D DIMM B0 REV TYPE (H5.2) +1.5V JDIMMB0 +DIMM1_VREF 1 RD12 1K_0402_1%~D M3 Circuit (Processor Generated SO-DIMM VREF_DQ) 2 S D 2 DDR_B_D7 DDR_B_D3 DDR_B_D13 DDR_B_D9 <9> DDR_B_DQS#1 DDR_B_DQS1 RD18 1K_0402_5%~D @ DRAMRST_CNTRL_PCH DDR_B_D14 DDR_B_D15 2 <6,10,17> G 2 1 +V_DDR_REFB_R 2 1 CD24 1 +V_DDR_REFB 2 0_0402_5%~D QD2 3 BSS138_NL_SOT23-3 1 CD23 @RD17 @ RD17 1 0.1U_0402_25V6K~D 2.2U_0603_10V7K~D D DDR_B_D5 DDR_B_D4 DDR_B_D21 DDR_B_D20 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D23 DDR_B_D22 DDR_B_D28 DDR_B_D24 Layout Note: Place near JDIMMB DDR_B_D30 DDR_B_D31 C 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDR_B_D1 DDR_B_D0 DDR_B_DQS#0 DDR_B_DQS0 D DDR_B_D2 DDR_B_D6 DDR_B_D8 DDR_B_D12 DDR3_DRAMRST# DDR3_DRAMRST# <6,10,12,13> DDR_B_D10 DDR_B_D11 DDR_B_D17 DDR_B_D16 TOP CPU DDR_B_D19 DDR_B_D18 DDR_B_D29 DDR_B_D25 BOT DDR_B_DQS#3 DDR_B_DQS3 CH A1 (H9.2)(Rev) CH B1 (H5.2)(Rev) CH B0 (H5.2)(Std) CH A0 (H9.2) (Std) DDR_B_D26 DDR_B_D27 DIMM A0 DIMM B0 DIMM B1 DIMM A1 C +1.5V DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 M_CLK_DDR6 M_CLK_DDR#6 <6> M_CLK_DDR6 <6> M_CLK_DDR#6 +1.5V DDR_B_MA10 DDR_B_BS0 <6,13> DDR_B_BS0 2 1 + 2 DDR_B_WE# DDR_B_CAS# <6,13> DDR_B_WE# <6,13> DDR_B_CAS# DDR_B_MA13 DDR_CS7_DIMMB1# <6> DDR_CS7_DIMMB1# DDR_B_D40 DDR_B_D47 Layout Note: Place near JDIMMB.203,204 DDR_B_D43 DDR_B_D44 DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 +3VS DDR_B_D55 DDR_B_D51 2 DDR_B_D61 DDR_B_D57 R1833 10K_0402_5%~D RD5 10K_0402_5%~D DDR_B_D63 DDR_B_D59 1 2 1 2 1 CD42 1U_0402_6.3V6K~D 2 1 CD41 1U_0402_6.3V6K~D 1 CD40 1U_0402_6.3V6K~D 2 CD39 1U_0402_6.3V6K~D 1 2 +0.75VS 2 2 1 2 +0.75VS 205 1 2 CD44 1 CD43 @ R1834 10K_0402_5%~D 2.2U_0603_10V7K~D @ RD6 10K_0402_5%~D A 0.1U_0402_25V6K~D 1 +3VS G1 G2 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR7 M_CLK_DDR#7 M_CLK_DDR7 <6> M_CLK_DDR#7 <6> DDR_B_BS1 DDR_B_RAS# DDR_B_BS1 <6,13> DDR_B_RAS# <6,13> DDR_CS6_DIMMB1# M_ODT6 DDR_CS6_DIMMB1# M_ODT6 <6> M_ODT7 M_ODT7 +1.5V <6> RD13 1K_0402_1% <6> +VREF_CB DDR_B_D32 DDR_B_D33 DDR_B_D38 DDR_B_D39 DDR_B_D41 DDR_B_D45 1 2 RD14 1K_0402_1% 1 2 CD38 DDR_B_D34 DDR_B_D35 <6> DDR_B_MA15 DDR_B_MA14 CD37 DDR_B_DQS#4 DDR_B_DQS4 B DDR_CKE7_DIMMB1 0.1U_0402_25V6K~D DDR_B_D37 DDR_B_D36 DDR_CKE7_DIMMB1 2.2U_0603_10V7K~D CD36 330U_SX_2VY~D 2 @ 1 CD35 2 1 10U_0603_6.3V6M~D CD34 2 1 10U_0603_6.3V6M~D CD33 2 1 10U_0603_6.3V6M~D CD32 2 1 10U_0603_6.3V6M~D CD31 1 10U_0603_6.3V6M~D CD30 2 10U_0603_6.3V6M~D CD29 10U_0603_6.3V6M~D 1 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 1 2 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 2 DDR_B_MA12 DDR_B_MA9 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 1 2 DDR_B_BS2 <6,13> DDR_B_BS2 1 CD28 CD27 2 1 1U_0402_6.3V6K~D CD26 2 1 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D CD25 1U_0402_6.3V6K~D 1 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 B 2 DDR_CKE6_DIMMB1 <6> DDR_CKE6_DIMMB1 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D42 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D50 DDR_B_D60 DDR_B_D56 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D58 M_THERMAL# PCH_SMBDATA PCH_SMBCLK M_THERMAL# <10,12,13,40> PCH_SMBDATA <5,10,12,13,16,17,34,35,43> PCH_SMBCLK <5,10,12,13,16,17,34,35,43> +0.75VS 206 A TYCO_2-2013290-1 CONN@ CIS link OK DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title DDRIII DIMMB0 Size Document Number Date: Tuesday, January 17, 2012 Rev 0.1 LA-8321P Sheet 1 11 of 65 3 +1.5V +V_DDR_REFA 1 4 1 5 RD27 0_0402_5%~D @ 2 +1.5V DDR_A_D8 DDR_A_D9 1 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D15 Layout Note: Place near JDIMMC DDR_A_D21 DDR_A_D20 DDR_A_DQS#2 DDR_A_DQS2 +1.5V DDR_A_D19 DDR_A_D18 2 DDR_A_D28 DDR_A_D29 1 CD56 CD55 2 1 1U_0402_6.3V6K~D CD54 1 1U_0402_6.3V6K~D 2 1U_0402_6.3V6K~D CD53 1U_0402_6.3V6K~D 1 DDR_A_D26 DDR_A_D27 2 DDR_CKE0_DIMMA0 <6> DDR_CKE0_DIMMA0 C DDR_A_BS2 <6,10> DDR_A_BS2 +1.5V DDR_A_MA12 DDR_A_MA9 2 + 2 CD64 330U_SX_2VY~D 1 CD63 2 @ 2 1 10U_0603_6.3V6M~D CD62 2 1 10U_0603_6.3V6M~D CD61 2 1 10U_0603_6.3V6M~D CD60 2 1 10U_0603_6.3V6M~D CD59 2 1 10U_0603_6.3V6M~D CD58 10U_0603_6.3V6M~D CD57 10U_0603_6.3V6M~D 1 1 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 M_CLK_DDR0 M_CLK_DDR#0 <6> M_CLK_DDR0 <6> M_CLK_DDR#0 <6,10> DDR_A_BS0 DDR_A_MA10 DDR_A_BS0 <6,10> DDR_A_WE# <6,10> DDR_A_CAS# DDR_A_WE# DDR_A_CAS# DDR_A_MA13 DDR_CS1_DIMMA0# <6> DDR_CS1_DIMMA0# Layout Note: Place near JDIMMC.203,204 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 +3VS DDR_A_D55 DDR_A_D54 2 2 DDR_A_D42 DDR_A_D43 1 2 1 CD70 1U_0402_6.3V6K~D 2 1 CD69 1U_0402_6.3V6K~D 2 1 CD68 1U_0402_6.3V6K~D CD67 1U_0402_6.3V6K~D 1 DDR_A_D60 DDR_A_D61 @ R1835 10K_0402_5%~D DDR_A_D63 DDR_A_D62 1 2 @RD32 @ RD32 10K_0402_5%~D 2 1 +3VS 1 1 2 CD71 2 +0.75VS 1 2 CD72 2.2U_0603_10V7K~D RD33 10K_0402_5%~D 0.1U_0402_25V6K~D RD53 10K_0402_5%~D A 205 G1 G2 D DDR_A_D12 DDR_A_D13 DDR3_DRAMRST# DDR3_DRAMRST# <6,10,11,13> DDR_A_D14 DDR_A_D11 CH A1 (H9.2)(Rev) CH B1 (H5.2)(Rev) CH B0 (H5.2)(Std) DDR_A_D17 DDR_A_D16 DDR_A_D22 DDR_A_D23 TOP CPU DDR_A_D24 DDR_A_D31 BOT DDR_A_DQS#3 DDR_A_DQS3 CH A0 (H9.2) (Std) DDR_A_D30 DDR_A_D25 DDR_CKE1_DIMMA0 DDR_CKE1_DIMMA0 DIMM A0 DIMM B0 DIMM B1 DIMM A1 <6> C DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR1 M_CLK_DDR#1 M_CLK_DDR1 M_CLK_DDR#1 <6> <6> DDR_A_BS1 DDR_A_RAS# DDR_A_BS1 DDR_A_RAS# <6,10> <6,10> DDR_CS0_DIMMA0# M_ODT0 DDR_CS0_DIMMA0# M_ODT0 <6> M_ODT1 M_ODT1 +1.5V <6> RD30 1K_0402_1% <6> +VREF_CC DDR_A_D32 DDR_A_D33 DDR_A_D35 DDR_A_D38 DDR_A_D44 DDR_A_D45 1 2 RD31 1K_0402_1% 1 2 CD66 DDR_A_D41 DDR_A_D40 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_A_D3 DDR_A_D6 CD65 DDR_A_D34 DDR_A_D39 +0.75VS CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 DIMM A1 STD TYPE (H9.2) DDR_A_DQS#0 DDR_A_DQS0 0.1U_0402_25V6K~D DDR_A_DQS#4 DDR_A_DQS4 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 DDR_A_D1 DDR_A_D0 2.2U_0603_10V7K~D DDR_A_D37 DDR_A_D36 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 DDR_A_D2 DDR_A_D7 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 2 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 1 1 CD52 2 DDR_A_D4 DDR_A_D5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 2 1 CD51 2 <6,10> DDR_A_MA[0..15] 0.1U_0402_25V6K~D RD29 1K_0402_1%~D 2.2U_0603_10V7K~D <6,10> DDR_A_D[0..63] B 1 JDIMMA1 +DIMM3_VREF <6,10> DDR_A_DQS[0..7] D +1.5V 2 RD28 1K_0402_1%~D <6,10> DDR_A_DQS#[0..7] 2 B DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D53 DDR_A_D52 DDR_A_D51 DDR_A_D50 DDR_A_D56 DDR_A_D57 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D59 DDR_A_D58 M_THERMAL# PCH_SMBDATA PCH_SMBCLK M_THERMAL# <10,11,13,40> PCH_SMBDATA <5,10,11,13,16,17,34,35,43> PCH_SMBCLK <5,10,11,13,16,17,34,35,43> +0.75VS 206 TYCO_2-2013310-1 CONN@ A CIS link OK DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title DDRIII DIMMA1 Size Document Number Date: Tuesday, January 17, 2012 Rev 0.1 LA-8321P Sheet 1 12 of 65 3 +1.5V +V_DDR_REFB 1 4 1 5 RD40 0_0402_5%~D @ +1.5V 2 2 RD41 1K_0402_1%~D 2 1 +1.5V JDIMMB1 +DIMM4_VREF 1 2 <6,11> DDR_B_D[0..63] <6,11> DDR_B_MA[0..15] 2 DDR_B_D5 DDR_B_D4 1 2 CD77 <6,11> DDR_B_DQS[0..7] 1 0.1U_0402_25V6K~D <6,11> DDR_B_DQS#[0..7] CD76 2.2U_0603_10V7K~D D RD42 1K_0402_1%~D DDR_B_D7 DDR_B_D3 DDR_B_D13 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D14 DDR_B_D15 DDR_B_D21 DDR_B_D20 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D23 DDR_B_D22 Layout Note: Place near JDIMMD DDR_B_D28 DDR_B_D24 DDR_B_D30 DDR_B_D31 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DIMM B1 STD TYPE (H5.2) DDR_B_D1 DDR_B_D0 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D2 DDR_B_D6 D DDR_B_D8 DDR_B_D12 DDR3_DRAMRST# DDR3_DRAMRST# <6,10,11,12> DDR_B_D10 DDR_B_D11 CH A1 (H9.2)(Rev) CH B1 (H5.2)(Rev) CH B0 (H5.2)(Std) DIMM A0 DDR_B_D17 DDR_B_D16 DDR_B_D19 DDR_B_D18 TOP CPU DDR_B_D29 DDR_B_D25 BOT DDR_B_DQS#3 DDR_B_DQS3 DIMM B0 DIMM B1 CH A0 (H9.2) (Std) DDR_B_D26 DDR_B_D27 DIMM A1 +1.5V DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 <6> M_CLK_DDR2 <6> M_CLK_DDR#2 +1.5V 2 1 + 2 <6,11> DDR_B_BS0 DDR_B_MA10 DDR_B_BS0 <6,11> DDR_B_WE# <6,11> DDR_B_CAS# DDR_B_WE# DDR_B_CAS# DDR_B_MA13 DDR_CS3_DIMMB0# <6> DDR_CS3_DIMMB0# DDR_B_D40 DDR_B_D47 Layout Note: Place near JDIMMD.203,204 DDR_B_D43 DDR_B_D44 DDR_B_D48 DDR_B_D49 +0.75VS 2 +3VS DDR_B_D55 DDR_B_D51 2 DDR_B_D61 DDR_B_D57 @ RD54 10K_0402_5%~D R1836 10K_0402_5%~D DDR_B_D63 DDR_B_D59 1 2 1 2 2 1 CD95 1U_0402_6.3V6K~D 1 CD94 1U_0402_6.3V6K~D CD93 1U_0402_6.3V6K~D 2 CD92 1U_0402_6.3V6K~D 1 1 DDR_B_DQS#6 DDR_B_DQS6 2 1 2 2 +0.75VS 205 1 CD97 1 CD96 @RD45 @ RD45 10K_0402_5%~D 2.2U_0603_10V7K~D RD46 10K_0402_5%~D A 0.1U_0402_25V6K~D 1 +3VS G1 G2 C DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB0# M_ODT2 M_ODT3 M_CLK_DDR3 <6> M_CLK_DDR#3 <6> DDR_B_BS1 DDR_B_RAS# +1.5V <6,11> <6,11> DDR_CS2_DIMMB0# M_ODT2 <6> M_ODT3 <6> RD43 1K_0402_1% <6> +VREF_CD DDR_B_D32 DDR_B_D33 DDR_B_D38 DDR_B_D39 DDR_B_D41 DDR_B_D45 1 2 RD44 1K_0402_1% 1 2 CD91 DDR_B_D34 DDR_B_D35 B <6> DDR_B_MA11 DDR_B_MA7 CD90 DDR_B_DQS#4 DDR_B_DQS4 DDR_CKE3_DIMMB0 DDR_B_MA15 DDR_B_MA14 0.1U_0402_25V6K~D DDR_B_D37 DDR_B_D36 DDR_CKE3_DIMMB0 2.2U_0603_10V7K~D CD89 330U_SX_2VY~D 2 1 CD88 2 1 @ 2 1 10U_0603_6.3V6M~D CD87 2 1 10U_0603_6.3V6M~D CD86 1 10U_0603_6.3V6M~D CD85 2 10U_0603_6.3V6M~D CD84 1 10U_0603_6.3V6M~D CD83 2 10U_0603_6.3V6M~D CD82 10U_0603_6.3V6M~D 1 M_CLK_DDR2 M_CLK_DDR#2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 1 DDR_B_MA12 DDR_B_MA9 2 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 2 DDR_B_BS2 <6,11> DDR_B_BS2 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 1 2 1 CD81 CD80 2 1 1U_0402_6.3V6K~D CD79 2 1 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D CD78 1U_0402_6.3V6K~D 1 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 2 DDR_CKE2_DIMMB0 <6> DDR_CKE2_DIMMB0 C B DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D42 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D50 DDR_B_D60 DDR_B_D56 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D58 M_THERMAL# PCH_SMBDATA PCH_SMBCLK M_THERMAL# <10,11,12,40> PCH_SMBDATA <5,10,11,12,16,17,34,35,43> PCH_SMBCLK <5,10,11,12,16,17,34,35,43> +0.75VS 206 TYCO_2-2013289-1 CONN@ A 2 CIS link OK DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title DDRIII DIMMB1 Size Document Number Date: Tuesday, January 17, 2012 Rev 0.1 LA-8321P Sheet 1 13 of 65 5 4 3 2 1 +3VALW 1 2 0_0402_5%~D VGA_DISABLE# 1 <24> DGPU_ENVDD <24> DGPU_BKL_EN <24> VGA_PNL_PWM VGA_HDMI_CEC VGA_LCD_DAT <24> VGA_LCD_DAT VGA_LCD_CLK <24> VGA_LCD_CLK LVDS DDC Module have 4.7K Pull-UP R92 1 @ 2 10K_0402_5%~D R93 1 @ 2 36K_0402_1% 1 +3VALW 1 +3V_MXM1 R105 10K_0402_5%~D 3 1 S D <15> VGA_TH_OVERT# 2 2 G 2 R94 10K_0402_5%~D TH_OVERT# Q7 2N7002E-T1-E3_SOT23-3 B <4> PEG_GTX_HRX_N7 <4> PEG_GTX_HRX_P7 <4> PEG_GTX_HRX_N6 <4> PEG_GTX_HRX_P6 <4> PEG_GTX_HRX_N5 <4> PEG_GTX_HRX_P5 <4> PEG_GTX_HRX_N4 <4> PEG_GTX_HRX_P4 <4> PEG_GTX_HRX_N3 <4> PEG_GTX_HRX_P3 <40> 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 GND GND GND GND GND E3 GND GND GND GND 5V 5V 5V 5V 5V GND GND GND GND PEX_STD_SW# VGA_DISABLE# PNL_PWR_EN PNL_BL_EN PNL_BL_PWM HDMI_CEC DVI_HPD LVDS_DDC_DAT LVDS_DDC_CLK GND OEM OEM OEM OEM GND PEX_RX15# PEX_RX15 GND PEX_RX14# PEX_RX14 GND PEX_RX13# PEX_RX13 GND PEX_RX12# PEX_RX12 GND PEX_RX11# PEX_RX11 GND PEX_RX10# PEX_RX10 GND PEX_RX9# PEX_RX9 GND PEX_RX8# PEX_RX8 GND PEX_RX7# PEX_RX7 GND PEX_RX6# PEX_RX6 GND PEX_RX5# PEX_RX5 GND PEX_RX4# PEX_RX4 GND PEX_RX3# PEX_RX3 GND E2 PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC GND GND GND GND GND E4 GND GND GND GND PRSNT_R# WAKE# PWR_GOOD PWR_EN RSVD RSVD RSVD RSVD PWR_LEVEL TH_OVERT# TH_ALERT# TH_PWM GPIO0 GPIO1 GPIO2 SMB_DAT SMB_CLK GND OEM OEM OEM OEM GND PEX_TX15# PEX_TX15 GND PEX_TX14# PEX_TX14 GND PEX_TX13# PEX_TX13 GND PEX_TX12# PEX_TX12 GND PEX_TX11# PEX_TX11 GND PEX_TX10# PEX_TX10 GND PEX_TX9# PEX_TX9 GND PEX_TX8# PEX_TX8 GND PEX_TX7# PEX_TX7 GND PEX_TX6# PEX_TX6 GND PEX_TX5# PEX_TX5 GND PEX_TX4# PEX_TX4 GND PEX_TX3# PEX_TX3 GND 1 1 R86 Q5 2N7002E-T1-E3_SOT23-3 <15> R87 4.7K_0402_5%~D 2 AC_BATT# MC74VHC1G09DFT2G_SC70-5 <40,44,45> EC_SMB_DA1 <40,44,45> EC_SMB_CK1 1 3 4.7K_0402_5%~D 2 AC_BATT# VGA_SMB_DA1 VGA_SMB_DA1 <15> VGA_SMB_CK1 <15> 2 G 2 4 6 8 10 12 14 16 18 4 1 D VGA_SMB_CK1 3 S PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC E1 PWR_SRC PWR_SRC PWR_SRC PWR_SRC Y D 1 3 5 7 9 11 13 15 17 U618 +3V_MXM +3V_MXM S 3 Add R90 increase NV MXM PEG Swing +3V_MXM A Q6 2N7002E-T1-E3_SOT23-3 JMXM1B MXM_PS_0 @ C2029 MXM_PS_1 @ C2031 MXM_PS_2 @ C2030 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D 1 1 1 <4> PEG_GTX_HRX_N2 <4> PEG_GTX_HRX_P2 <4> PEG_GTX_HRX_N1 <4> PEG_GTX_HRX_P1 <4> PEG_GTX_HRX_N0 <4> PEG_GTX_HRX_P0 (Pull-UP 10K at PCH) VGA_PRSNT_R# VGA_WAKE# DGPU_PWROK VGA_ON <17> CLK_PEG_PCH# <17> CLK_PEG_PCH VGA_PRSNT_R# DGPU_PWROK VGA_ON @ R103 1 @ R104 1 2 0_0402_5%~D CLK_PEG_PCH#_R 2 0_0402_5%~D CLK_PEG_PCH_R <20> <20> <15,17> AC_BATT# VGA_TH_OVERT# VGA_TH_OVERT# 1 2 +3V_MXM R91 10K_0402_5%~D <24> VGA_TZCLK<24> VGA_TZCLK+ <15> LVDS VGA_SMB_DA1 VGA_SMB_CK1 MXM_PS_0 MXM_PS_1 MXM_PS_2 <24> VGA_TZOUT2<24> VGA_TZOUT2+ <24> VGA_TZOUT1<24> VGA_TZOUT1+ TO EC <24> VGA_TZOUT0<24> VGA_TZOUT0+ +3VMXM <27> GPU_HDMI_TXD2<27> GPU_HDMI_TXD2+ R2589 0_0402_5%~D 2 1 +5V_MXM @ R90 B @ @ @ @ @ @ PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_P7 <27> GPU_HDMI_TXD1<27> GPU_HDMI_TXD1+ HDMI <27> GPU_HDMI_TXD0<27> GPU_HDMI_TXD0+ MXM_PS_0 MXM_PS_1 MXM_PS_2 R2592 0_0402_5%~D 2 1 1 100mil(2.5A, 5VIA) C <40> EC_AC_BAT# 2 R2588 0_0402_5%~D 2 1 2 2 C222 C225 2 1 0.1U_0603_50V7K~D C224 68P_0402_50V8J~D C223 680P_0402_50V7K~D 10U_0805_25V6K~D 2 1 R2591 0_0402_5%~D 2 1 160mil(4A) 1 B+_MXM JMXM1A 2 B+_MXM 1 ACIN <18,37,40,43,47> +3V_MXM R88 10K_0402_5%~D 1 1 5 1 R2587 0_0402_5%~D 2 1 2 2 JUMP_43X118 C228 C227 D 0.1U_0402_25V6K~D C226 4.7U_0603_10V6K~D 1 G VCC 2 1 R2590 0_0402_5%~D 2 1 2 1 0_0805_5%~D 2 +3V_MXM C1823 0.1U_0402_25V6K~D PJP9 10U_0603_6.3V6M~D @ R98 1 2 +5VMXM D +5V_MXM 2 G +3VMXM 2 +3V_MXM <27> GPU_HDMI_TXC<27> GPU_HDMI_TXC+ <27> GPU_HDMI_SDATA <27> GPU_HDMI_SCLK <4> <4> PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_P6 <4> <4> PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_P5 <4> <4> PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_P4 <4> <4> PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_P3 <4> <4> <29> VGA_DPC_N0 <29> VGA_DPC_P0 <29> VGA_DPC_N1 <29> VGA_DPC_P1 DMC <29> VGA_DPC_N2 <29> VGA_DPC_P2 <29> VGA_DPC_N3 <29> VGA_DPC_P3 <29> VGA_DPC_AUXN/DDC <29> VGA_DPC_AUXP/DDC <20> VGA_PRSNT_L# (Pull-UP 10K at PCH) JAE_MM70-314-310B1-1-R300 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231 233 235 237 239 241 243 245 247 249 251 253 255 257 259 261 263 265 267 269 271 273 275 277 279 281 283 285 287 289 291 293 295 297 299 301 303 305 307 309 310 311 GND PEX_RX2# PEX_RX2 GND PEX_RX1# PEX_RX1 GND PEX_RX0# PEX_RX0 GND PEX_REFCLK# PEX_REFCLK GND RSVD RSVD RSVD RSVD RSVD LVDS_UCLK# LVDS_UCLK GND LVDS_UTX3# LVDS_UTX3 GND LVDS_UTX2# LVDS_UTX2 GND LVDS_UTX1# LVDS_UTX1 GND LVDS_UTX0# LVDS_UTX0 GND DP_C_L0# DP_C_L0 GND DP_C_L1# DP_C_L1 GND DP_C_L2# DP_C_L2 GND DP_C_L3# DP_C_L3 GND DP_C_AUX# DP_C_AUX RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GND DP_A_L0# DP_A_L0 GND DP_A_L1# DP_A_L1 GND DP_A_L2# DP_A_L2 GND DP_A_L3# DP_A_L3 GND DP_A_AUX# DP_A_AUX PRSNT_L# GND PEX_TX2# PEX_TX2 GND PEX_TX1# PEX_TX1 GND PEX_TX0# PEX_TX0 GND PEX_CLK_REQ# PEX_RST# VGA_DDC_DAT VGA_DDC_CLK VGA_VSYNC VGA_HSYNC GND VGA_RED VGA_GREEN VGA_BLUE GND LVDS_LCLK# LVDS_LCLK GND LVDS_LTX3# LVDS_LTX3 GND LVDS_LTX2# LVDS_LTX2 GND LVDS_LTX1# LVDS_LTX1 GND LVDS_LTX0# LVDS_LTX0 GND DP_D_L0# DP_D_L0 GND DP_D_L1# DP_D_L1 GND DP_D_L2# DP_D_L2 GND DP_D_L3# DP_D_L3 GND DP_D_AUX# DP_D_AUX DP_C_HPD DP_D_HPD RSVD RSVD RSVD GND DP_B_L0# DP_B_L0 GND DP_B_L1# DP_B_L1 GND DP_B_L2# DP_B_L2 GND DP_B_L3# DP_B_L3 GND DP_B_AUX# DP_B_AUX DP_B_HPD DP_A_HPD 3V3 3V3 GND GND 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262 264 266 268 270 272 274 276 278 280 282 284 286 288 290 292 294 296 298 300 302 304 306 308 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_P2 <4> <4> PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_P1 <4> <4> PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_P0 <4> <4> VGA_DDC_DATA VGA_DDC_CLK PEG_CLKREQ# <17> PLTRST_VGA# <15,19> VGA_DDC_DATA <26> VGA_DDC_CLK <26> VGA_CRT_VSYNC <26> VGA_CRT_HSYNC <26> VGA_CRT_R VGA_CRT_G VGA_CRT_B <26> <26> <26> VGA_TXCLKVGA_TXCLK+ <24> <24> C LVDS VGA_TXOUT2- <24> VGA_TXOUT2+ <24> VGA_TXOUT1- <24> VGA_TXOUT1+ <24> VGA_TXOUT0- <24> VGA_TXOUT0+ <24> Reserve for eDP VGA_HDMI_DET <27> VGA_DPD_N0 VGA_DPD_P0 <28> <28> VGA_DPD_N1 VGA_DPD_P1 <28> <28> VGA_DPD_N2 VGA_DPD_P2 <28> <28> VGA_DPD_N3 VGA_DPD_P3 <28> <28> VGA_DPD_AUXN/DDC VGA_DPD_AUXP/DDC VGA_DPD_HPD <28> VGA_DMC_HPD <29> B mini DP <28> <28> +3V_MXM 40mil(1A) 312 JAE_MM70-314-310B1-1-R300 +3V_MXM MXM A PCH VGA_DDC_CLK VGA_DDC_DATA R1826 1 R1827 1 2 2.2K_0402_5%~D 2 2.2K_0402_5%~D Port A VGA_HDMI_CEC VGA_DISABLE# VGA_WAKE# R100 1 R101 1 @ R102 1 @ 2 10K_0402_5%~D 2 10K_0402_5%~D 2 10K_0402_5%~D Port B DP HDMI Port C HDMI DP Port D eDP DMC(HDMI) VGA_LCD_CLK VGA_LCD_DAT DGPU_PWROK R95 R96 R97 1 1 2 DMC(HDMI) A 2 4.3K_0402_5% 2 4.3K_0402_5% 1 10K_0402_5%~D DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title MXMIII Connector (Master) Size 4 3 2 Rev 0.1 LA-8321P Date: 5 Document Number Tuesday, January 17, 2012 Sheet 1 14 of 65 4 3 2 1 +3V_MXM1 +3V_MXM1 1 +3V_MXM1 1 5 2 JUMP_43X118 <17,30,40,41,44> +3V_MXM A1 A0 SDA SCL 8 7 6 5 B+_MXM_A1 B+_MXM_A0 MXM_CUR_DAT MXM_CUR_CLK INA219AIDCNRG4_SOT23-8 B 2 <46> MXM1_CUR_VIN- 2 0_0402_5%~D 1 @ R1729 0_0402_5%~D 2 1 2 @ C1805 0.1U_0402_25V6K~D 1 @ C1804 0.1U_0402_25V6K~D <46> MXM1_CUR_VIN+ @ R1728 1 MXM2 Current Monitor +3V_MXM1 U613 1 2 3 4 VIN+ VINGND VS A1 A0 SDA SCL 8 7 6 5 B+_MXM1_A1 B+_MXM1_A0 MXM_CUR_DAT MXM_CUR_CLK INA219AIDCNRG4_SOT23-8 <4> PEG_GTX_HRX_N15 <4> PEG_GTX_HRX_P15 <4> PEG_GTX_HRX_N14 <4> PEG_GTX_HRX_P14 <4> PEG_GTX_HRX_N13 <4> PEG_GTX_HRX_P13 A +3V_MXM1 R1830 <4> PEG_GTX_HRX_N12 <4> PEG_GTX_HRX_P12 2 @ R112 1 1 10K_0402_5%~D 2 10K_0402_5%~D MXM2_PCH_PWROK <4> PEG_GTX_HRX_N11 <4> PEG_GTX_HRX_P11 PEG_GTX_HRX_N15 PEG_GTX_HRX_P15 PEG_GTX_HRX_N14 PEG_GTX_HRX_P14 PEG_GTX_HRX_N13 PEG_GTX_HRX_P13 PEG_GTX_HRX_N12 PEG_GTX_HRX_P12 PEG_GTX_HRX_N11 PEG_GTX_HRX_P11 VGA_SMB_DA2 VGA_SMB_CK2 MXM_PS_3 MXM_PS_4 MXM_PS_5 2 10K_0402_5%~D 5 @ @ @ @ @ PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_P11 MXM_PS_3 MXM_PS_4 MXM_PS_5 PEG_HTX_C_GRX_N15 <4> PEG_HTX_C_GRX_P15 <4> PEG_HTX_C_GRX_N14 <4> PEG_HTX_C_GRX_P14 <4> PEG_HTX_C_GRX_N13 <4> PEG_HTX_C_GRX_P13 <4> PEG_HTX_C_GRX_N12 <4> PEG_HTX_C_GRX_P12 <4> 311 GND GND +3VALW C1849 1 2 0.1U_0402_25V6K~D 1 MXM2_EC_RST# <20> IN1 MXM2_RST# 4 O 2 IN2 PLTRST_VGA# <14,19> B RH264 100K_0402_5% UH7 SN74AHC1G08DCKR_SC70-5 +3VALW C1850 1 2 MXM2_PWR_ON 4 0.1U_0402_25V6K~D 1 MXM2_PCH_PWR_ON IN1 O IN2 +3V_MXM1 2 VGA_ON <16,20> <14,17> UH8 SN74AHC1G08DCKR_SC70-5 40mil(1A) 312 JAE_MM70-314-310B1-1-R300 A DELL CONFIDENTIAL/PROPRIETARY PEG_HTX_C_GRX_N11 <4> PEG_HTX_C_GRX_P11 <4> Compal Electronics, Inc. VGA2_WAKE# PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. VGA2_DISABLE# 4 @ PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_P15 JAE_MM70-314-310B1-1-R300 @ R111 1 +3VMXM C 5 VIN+ VINGND VS AC_BATT# AC_BATT# <14> VGA_TH_OVERT# VGA_TH_OVERT# <14> 1 2 +3V_MXM1 R109 10K_0402_5%~D MXM2_CLKREQ# <17> P U612 1 2 3 4 MXM2_PCH_PWROK <20> PEG_HTX_C_GRX_N8 <4> PEG_HTX_C_GRX_P8 <4> MXM2_CLKREQ# MXM2_RST# G @ R1726 0_0402_5%~D 2 1 2 MXM1 Current Monitor MXM2_PRSNT_R# <16,20> PEG_HTX_C_GRX_N9 <4> PEG_HTX_C_GRX_P9 <4> PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_P8 3 2 0_0402_5%~D 1 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D PEG_HTX_C_GRX_N10 <4> PEG_HTX_C_GRX_P10 <4> PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_P9 5 2 <46> MXM_CUR_VIN- @ R1725 1 @ C1803 0.1U_0402_25V6K~D 1 @ C1802 0.1U_0402_25V6K~D <46> MXM_CUR_VIN+ 2 0_0402_5%~D VGA2_DISABLE# MXM2_PRSNT_R# VGA2_WAKE# MXM2_PCH_PWROK MXM2_PWR_ON 1 1 1 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_P10 P @ R110 1 MXM_PS_3 @ C2032 MXM_PS_4 @ C2034 MXM_PS_5 @ C2033 MXM2_PEG_PCH#_R 2 MXM2_PEG_PCH_R 20_0402_5%~D 0_0402_5%~D 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262 264 266 268 270 272 274 276 278 280 282 284 286 288 290 292 294 296 298 300 302 304 306 308 G VGA_SMB_DA1 <14> VGA_SMB_CK1 <14> 1 <17> MXM2_PEG_PCH# <17> MXM2_PEG_PCH @ R1071 @ R106 GND PEX_TX2# PEX_TX2 GND PEX_TX1# PEX_TX1 GND PEX_TX0# PEX_TX0 GND PEX_CLK_REQ# PEX_RST# VGA_DDC_DAT VGA_DDC_CLK VGA_VSYNC VGA_HSYNC GND VGA_RED VGA_GREEN VGA_BLUE GND LVDS_LCLK# LVDS_LCLK GND LVDS_LTX3# LVDS_LTX3 GND LVDS_LTX2# LVDS_LTX2 GND LVDS_LTX1# LVDS_LTX1 GND LVDS_LTX0# LVDS_LTX0 GND DP_D_L0# DP_D_L0 GND DP_D_L1# DP_D_L1 GND DP_D_L2# DP_D_L2 GND DP_D_L3# DP_D_L3 GND DP_D_AUX# DP_D_AUX DP_C_HPD DP_D_HPD RSVD RSVD RSVD GND DP_B_L0# DP_B_L0 GND DP_B_L1# DP_B_L1 GND DP_B_L2# DP_B_L2 GND DP_B_L3# DP_B_L3 GND DP_B_AUX# DP_B_AUX DP_B_HPD DP_A_HPD 3V3 3V3 3 2 0_0402_5%~D 2 0_0402_5%~D 1 1 PEG_GTX_HRX_N8 PEG_GTX_HRX_P8 <4> PEG_GTX_HRX_N8 <4> PEG_GTX_HRX_P8 GND PEX_RX2# PEX_RX2 GND PEX_RX1# PEX_RX1 GND PEX_RX0# PEX_RX0 GND PEX_REFCLK# PEX_REFCLK GND RSVD RSVD RSVD RSVD RSVD LVDS_UCLK# LVDS_UCLK GND LVDS_UTX3# LVDS_UTX3 GND LVDS_UTX2# LVDS_UTX2 GND LVDS_UTX1# LVDS_UTX1 GND LVDS_UTX0# LVDS_UTX0 GND DP_C_L0# DP_C_L0 GND DP_C_L1# DP_C_L1 GND DP_C_L2# DP_C_L2 GND DP_C_L3# DP_C_L3 GND DP_C_AUX# DP_C_AUX RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GND DP_A_L0# DP_A_L0 GND DP_A_L1# DP_A_L1 GND DP_A_L2# DP_A_L2 GND DP_A_L3# DP_A_L3 GND DP_A_AUX# DP_A_AUX PRSNT_L# 1 100mil(2.5A, 5VIA) MXM_CUR_DAT @ R1714 MXM_CUR_CLK @ R1715 PEG_GTX_HRX_N9 PEG_GTX_HRX_P9 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231 233 235 237 239 241 243 245 247 249 251 253 255 257 259 261 263 265 267 269 271 273 275 277 279 281 283 285 287 289 291 293 295 297 299 301 303 305 307 309 310 2 +5V_MXM1 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 <4> PEG_GTX_HRX_N9 <4> PEG_GTX_HRX_P9 R2595 0_0402_5%~D 2 1 1 0_0402_5% 1 0_0402_5% GND GND GND GND GND E4 GND GND GND GND PRSNT_R# WAKE# PWR_GOOD PWR_EN RSVD RSVD RSVD RSVD PWR_LEVEL TH_OVERT# TH_ALERT# TH_PWM GPIO0 GPIO1 GPIO2 SMB_DAT SMB_CLK GND OEM OEM OEM OEM GND PEX_TX15# PEX_TX15 GND PEX_TX14# PEX_TX14 GND PEX_TX13# PEX_TX13 GND PEX_TX12# PEX_TX12 GND PEX_TX11# PEX_TX11 GND PEX_TX10# PEX_TX10 GND PEX_TX9# PEX_TX9 GND PEX_TX8# PEX_TX8 GND PEX_TX7# PEX_TX7 GND PEX_TX6# PEX_TX6 GND PEX_TX5# PEX_TX5 GND PEX_TX4# PEX_TX4 GND PEX_TX3# PEX_TX3 GND 2 4 6 8 10 12 14 16 18 R2598 0_0402_5%~D 2 1 2 R1720 C B+_MXM1_A1 1 2 3.3K_0402_5%~D @ R1717 B+_MXM1_A0 1 2 3.3K_0402_5%~D @ R1721 GND GND GND GND GND E3 GND GND GND GND 5V 5V 5V 5V 5V GND GND GND GND PEX_STD_SW# VGA_DISABLE# PNL_PWR_EN PNL_BL_EN PNL_BL_PWM HDMI_CEC DVI_HPD LVDS_DDC_DAT LVDS_DDC_CLK GND OEM OEM OEM OEM GND PEX_RX15# PEX_RX15 GND PEX_RX14# PEX_RX14 GND PEX_RX13# PEX_RX13 GND PEX_RX12# PEX_RX12 GND PEX_RX11# PEX_RX11 GND PEX_RX10# PEX_RX10 GND PEX_RX9# PEX_RX9 GND PEX_RX8# PEX_RX8 GND PEX_RX7# PEX_RX7 GND PEX_RX6# PEX_RX6 GND PEX_RX5# PEX_RX5 GND PEX_RX4# PEX_RX4 GND PEX_RX3# PEX_RX3 GND E2 PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC R2594 0_0402_5%~D 2 1 2 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC E1 PWR_SRC PWR_SRC PWR_SRC PWR_SRC PEG_GTX_HRX_N10 PEG_GTX_HRX_P10 R2597 0_0402_5%~D 2 1 +3V_MXM1 1 3 5 7 9 11 13 15 17 <4> PEG_GTX_HRX_N10 <4> PEG_GTX_HRX_P10 R2593 0_0402_5%~D 2 1 1 B+_MXM1 JMXM2A R2596 0_0402_5%~D 2 1 2 2 C1737 C1740 2 1 0.1U_0603_50V7K~D C1739 1 68P_0402_50V8J~D 2 C1738 1 10K_0402_5%~D 1 10K_0402_5%~D 1 680P_0402_50V7K~D 10U_0805_25V6K~D +3V_MXM R1716 D JMXM2B B+_MXM1 B+_MXM_A1 1 2 10K_0402_5%~D R1719 B+_MXM_A0 1 2 10K_0402_5%~D R1723 VGA_SMB_DA2 Q278 3 2N7002E-T1-E3_SOT23-3VGA_SMB_CK2 1 EC_SMB_CK2 4.7K_0402_5%~D 2 160mil(4A) 2 @ R1718 2 @ R1722 1 EC_SMB_DA2 2 G <17,30,40,41,44> R1887 S 1 S 1 D 2 4.7K_0402_5%~D Q277 3 2N7002E-T1-E3_SOT23-3 D 1 C1743 2 0.1U_0402_25V6K~D C1742 4.7U_0603_10V6K~D 1 C1741 D 2 2 10U_0603_6.3V6M~D 2 0_0805_5%~D 1 +5VMXM PJP10 2 +5V_MXM1 +3VMXM @ R1633 1 2 G R1886 +3V_MXM1 3 2 Title MXMIII Connector (Slave) Size Document Number Date: Tuesday, January 17, 2012 Rev 0.1 LA-8321P Sheet 1 15 of 65 5 4 3 2 1 +3V_PCH <19,43> USB_OC0# <19,43> USB_OC1# <19,51> 1.5VDDR_VID0 <19,51> 1.5VDDR_VID1 <19,43> USB_OC4# <19,36> USB_OC2# <19,36> USB_OC3# <19,43> ESATA_DETECT# <20> PCH_GPIO16 <15,20> MXM2_PCH_PWR_ON D <20,34> <20> <20> <15,20> <20> <20> ODD_DETECT# PCH_GPIO37 PCH_GPIO16 MXM2_PRSNT_R# PCH_GPIO15 CRT_DET USB_OC0# USB_OC1# 1.5VDDR_VID0 1.5VDDR_VID1 USB_OC4# USB_OC2# USB3_SMI# ESATA_DETECT# PCH_GPIO16 MXM2_PCH_PWR_ON PCH_GPIO21 BBS_BIT0_R ODD_DETECT# PCH_GPIO37 PCH_GPIO16 MXM2_PRSNT_R# PCH_GPIO15 CRT_DET @ RH1 @ RH3 @ RH4 @ RH5 @ RH6 @ RH7 @ RH8 @ RH9 @ RH10 @ RH12 @ RH13 @ RH14 @ RH15 @ RH16 @ RH17 @ RH18 @ RH19 @ RH20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D XDP_FN0 XDP_FN1 XDP_FN2 XDP_FN3 XDP_FN4 XDP_FN5 XDP_FN6 XDP_FN7 XDP_FN8 XDP_FN9 XDP_FN10 XDP_FN11 XDP_FN12 XDP_FN13 XDP_FN14 XDP_FN15 XDP_FN16 XDP_FN17 1 @ CH1 0.1U_0402_25V6K~D @ RH51 1 2 0_0402_5% JPCHXDP +3V_PCH_XDP 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 XDP_FN0 XDP_FN1 2 XDP_FN2 XDP_FN3 XDP_FN4 XDP_FN5 XDP_FN6 XDP_FN7 <5,18,53> <5,18,40> Please close to JXDP2 VGATE PBTN_OUT# VGATE 2 PCH_PWRBTN#_XDP 0_0402_5% 1 @ RH21 UH4A QH7 BSS138_SOT23~D R1906 1M_0402_5%~D 2 1 @ RH263 K22 PCH_INTVRMEN C17 HDA_BIT_CLK N34 HDA_SYNC L34 HDA_SPKR T10 HDA_RST# K34 HDA_SDIN0 E34 INTRUDER# INTVRMEN 1 RH29 PCH_JTAG_TCK 1 PCH_JTAG_TDI HDA_RST# HDA_SDIN0 2 2 RH59 51_0402_5% J3 PCH_JTAG_TMS H7 PCH_JTAG_TDI K5 PCH_JTAG_TDO H1 SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA2RXN SATA2RXP SATA2TXN SATA2TXP HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 A36 PCH_JTAG_TCK LPC SPKR A34 HDA_SDOUT 33_0402_5%~D SERIRQ HDA_SYNC 2 0_0402_5%~D 2 LDRQ0# LDRQ1# / GPIO23 HDA_BCLK SATA3RXN SATA3RXP SATA3TXN SATA3TXP HDA_SDO HDA_DOCK_EN# / GPIO33 N32 RH49 100_0402_1% RH48 100_0402_1% SRTCRST# C34 1 2 PCH_JTAG_TMS FWH4 / LFRAME# G34 @ RH52 1 FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 SATA 6G SM_INTRUDER# RTCRST# RTC G22 @ RH45 200_0402_5% 2 2 RH47 100_0402_1% PCH_SRTCRST# RTCX2 C36 1 2 @ RH44 200_0402_5% 1 PCH_JTAG_TDO 1 2 @ RH43 200_0402_5% D20 2 0_0402_5% <32> HDA_SDOUT_AUDIO +3V_PCH 1 1 +3V_PCH 1 <32> HDA_SDIN0 <40> HDA_SDO +3V_PCH 2 1 2 1 RH26 1 D <32> HDA_SYNC_AUDIO <32> HDA_SPKR 3 S 1 C20 PCH_RTCRST# SATA RH27 2 PCH_RTCX2 RTCX1 IHDA 1 <32> HDA_RST_AUDIO# +5VS 1 @ CLRME SHORT PADS RH25 CH5 1U_0603_25V6-K~D <32> HDA_BITCLK_AUDIO 2 G HDA_BIT_CLK 2 33_0402_5%~D HDA_RST# 2 33_0402_5%~D HDA_SYNC_R 2 33_0402_5%~D 1 1 @ CLRCMOS SHORT PADS C 2 20K_0402_5% 2 20K_0402_5% 2 1M_0402_5%~D CH4 1U_0603_25V6-K~D 1 RH22 1 RH23 1 RH11 2 +RTCVCC A20 SATA4RXN SATA4RXP SATA4TXN SATA4TXP HDA_DOCK_RST# / GPIO13 JTAG_TCK SATA5RXN SATA5RXP SATA5TXN SATA5TXP JTAG_TMS SATAICOMPO JTAG_TDI JTAG_TDO JTAG PCH_RTCX1 SATAICOMPI SATA3RCOMPO B SATA3COMPI LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 <35,40> <35,40> <35,40> <35,40> D36 LPC_FRAME# LPC_FRAME# <35,40> E36 K36 LPC_LDRQ0# LPC_LDRQ1# V5 SERIRQ @ @ <5,10,11,12,13,17,34,35,43> <5,10,11,12,13,17,34,35,43> SERIRQ <40> <34> <34> <34> <34> HDD1 AM10 AM8 AP11 AP10 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 <34> <34> <34> <34> HDD2 AD7 AD5 AH5 AH4 SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 SATA_PTX_DRX_N2 SATA_PTX_DRX_P2 <34> <34> <34> <34> AB8 AB10 AF3 AF1 SATA_PRX_DTX_N3 SATA_PRX_DTX_P3 SATA_PTX_DRX_N3 SATA_PTX_DRX_P3 <34> <34> <34> <34> HDD3 Y7 Y5 AD3 AD1 SATA_PRX_DTX_N4 SATA_PRX_DTX_P4 SATA_PTX_DRX_N4 SATA_PTX_DRX_P4 <43> <43> <43> <43> E-SATA Y3 Y1 AB3 AB1 SATA_PRX_DTX_N5 SATA_PRX_DTX_P5 SATA_PTX_DRX_N5 SATA_PTX_DRX_P5 <34> <34> <34> <34> mSATA 1 RH40 2 37.4_0402_1% AB13 SATA3_COMP 1 RH42 2 49.9_0402_1% AH1 RBIAS_SATA3 1 RH46 2 750_0402_1% XDP_FN8 XDP_FN9 XDP_FN10 XDP_FN11 D XDP_FN12 XDP_FN13 XDP_FN14 XDP_FN15 @ RH24 1K_0402_5% 1 2 PLT_RST# XDP_DBRESET# <5,18> +3V_PCH_XDP PLTRST1#_XDP XDP_DBRESET# PCH_JTAG_TDO PCH_JTAG_TDO <5> PCH_JTAG_TDI PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TMS <5> <5> <5,19,31,35,40,43> ODD +3VS +RTCVCC PCH_INTVRMEN RH38 PCH_INTVRMEN RH39 2 SERIRQ RH28 2 1 10K_0402_5%~D PCH_GPIO21 RH30 2 1 10K_0402_5%~D PCH_SATALED# RH31 2 1 10K_0402_5%~D 1 330K_0402_5%~D 2 @ 1 330K_0402_5%~D INTVRMEN H：Integrated VRM enable L：Integrated VRM disable * +3VS HDA_SPKR RH35 2 @ 1 1K_0402_5% LOW=Default Reboot *HIGH=No HDA_SDO +3V_PCH ME debug mode , this signal has a weak internal PD HDA_SDOUT RH41 L=>security measures defined in the Flash Descriptor will be in effect (default) 2 @ 1 1K_0402_5% = Disabled *Low High = Enabled +1.05VS_SATA3 AB12 XDP_FN16 XDP_FN17 C +1.05VS_VCC_SATA SATA_COMP 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 SAMTE_BSH-030-01-L-D-A CONN@ T79 PAD~D T77 PAD~D SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 Y10 PCH_JTAG_TCK <5> PCH_JTAG_TCK AM3 AM1 AP7 AP5 Y11 PCH_SMBDATA PCH_SMBCLK GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 H=>Flash Descriptor Security will be overridden B RH240 PCH_SPI_CLK_R 1 22P_0402_50V8J~D 2 33_0402_5%~D PCH_SPI_CLK T3 PCH_SPI_CS# Y14 SPI_CLK RH240 & CH97 as close as UH4 PCH_SPI_SI V4 PCH_SPI_SO U3 SATA3RBIAS HDA_SYNC SPI_CS0# T1 SPI_CS1# SPI_MOSI SPI @ CH97 2 1 C38 A38 B37 C37 GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 SATALED# SATA0GP / GPIO21 SPI_MISO SATA1GP / GPIO19 P3 PCH_SATALED# V14 PCH_GPIO21 P1 BBS_BIT0_R PCH_SATALED# This signal has a weak internal pull-down On Die PLL VR is supplied by 1.5V when smapled high 1.8V when sampled low Needs to be pulled High for Huron River platfrom <38> +3VS 1 RH266 2 10K_0402_5%~D +3V_PCH BD82HM77 QPRG-C1 BGA989~D HDA_SYNC BBS_BIT0 - BIOS BOOT STRAP BIT 0 RH66 1 1K_0402_5% 2 PCH_RTCX1 2 2 RH53 3.3K_0402_5%~D SPI ROM FOR ME ( 8MByte ) RH55 3.3K_0402_5%~D 2 2 CH3 18P_0402_50V8J~D 1 CH2 15P_0402_50V8J~D A @ RH57 3.3K_0402_5%~D 1 1 +3V_PCH 2 32.768KHZ_12.5PF_9H03200019 1 GPIO19: If not used, requires 8.2-kΩ to 10-kΩ pull-up to +Vcc_3.3 (+3.3VS) check list Rev 1.0 +3V_PCH YH1 1 1 RH2 PCH_RTCX2 2 10M_0402_5% 2 1 A U1 PCH_SPI_CS# PCH_SPI_SO 1 @ RH60 1 @ RH58 2 0_0402_5%~D 2 0_0402_5%~D PCH_SPI_CS#_R 1 PCH_SPI_SO_R 2 PCH_SPI_WP# 3 4 /CS VCC DO /HOLD /WP CLK GND DIO 8 +3V_PCH 7 PCH_SPI_HOLD# 6 PCH_SPI_CLK_R 5 PCH_SPI_SI_R 1 @ RH168 1 2 PCH_SPI_SI 0_0402_5%~D 2 DELL CONFIDENTIAL/PROPRIETARY CH6 0.1U_0402_25V6K~D Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. W25Q64CVSSIG_SO8~D Title PCH (1/8) SATA,HDA,SPI, LPC Size 4 3 2 Rev 0.1 LA-8321P Date: 5 Document Number Tuesday, January 17, 2012 Sheet 1 16 of 65 5 4 3 2 1 +3V_PCH EC_LID_OUT# 0_0402_5%~D 1 2 @ RH162 EC_LID_OUT# <40> SMBCLK 1 UH4B SMBDATA @ RH251 @ CH99 CLK_PCI_LPBACK 2 1 1 2 33_0402_5%~D 22P_0402_50V8J~D C Reserve for EMI please close to PAD~D PAD~D RH81 +3V_PCH 1 T95 @ T96 @ 2 10K_0402_5%~D Y40 Y39 PCIECLKREQ0# J2 MiniDMC (Mini Card 2)---> MiniWLAN (Mini Card 1)---> Card Reader ---> EXPRESS_CARD ---> @ RH88 @ RH90 RH152 <31> CLK_PCIE_LAN# <31> CLK_PCIE_LAN +3VS <31> LANCLK_REQ# <43> CLK_PCIE_CD# <43> CLK_PCIE_CD +3V_PCH <43> CDCLK_REQ# <43> CLK_PCIE_EXP# <43> CLK_PCIE_EXP +3V_PCH <43> EXPCLK_REQ# 2 0_0402_5%~D 2 0_0402_5%~D 1 10K_0402_5%~D PCIE_LAN# PCIE_LAN AB49 AB47 LANCLK_REQ# <35> CLK_PCIE_MINI2# <35> CLK_PCIE_MINI2 +3VS <35> MINI2CLK_REQ# <35> CLK_PCIE_MINI3# <35> CLK_PCIE_MINI3 +3V_PCH <35> MINI1CLK_REQ# 1 1 2 @ RH98 @ RH191 RH103 @ RH82 @ RH83 RH84 1 1 2 1 1 2 2 0_0402_5%~D 2 0_0402_5%~D 1 10K_0402_5%~D 2 0_0402_5%~D 2 0_0402_5%~D 1 10K_0402_5%~D M1 PCIE_MINI2# PCIE_MINI2 AA48 AA47 MINI2CLK_REQ# V10 PCIE_MINI3# PCIE_MINI3 Y37 Y36 MINI1CLK_REQ# @ RH92 @ RH93 RH94 1 1 2 2 0_0402_5%~D 2 0_0402_5%~D 1 10K_0402_5%~D A8 PCIE_CD# PCIE_CD Y43 Y45 CDCLK_REQ# @ RH105 @ RH125 RH97 1 1 1 2 0_0402_5%~D 2 0_0402_5%~D 2 10K_0402_5%~D L12 PCIE_EXP# PCIE_EXP V45 V46 EXPCLK_REQ# L14 MXM2_PEG_PCH# MXM2_PEG_PCH AB42 AB40 SML0CLK C8 PCH_GPIO74 2 1 2 R1907 G12 SML0DATA C13 PCH_GPIO74 E14 SML1CLK M16 SML1DATA D 1K_0402_5% 10K_0402_5%~D +3VALW PERN7 PERP7 PETN7 PETP7 PERN8 PERP8 PETN8 PETP8 CL_CLK1 CL_RST1# No support iAMT 2 PEG_CLKREQ# R1528 10K_0402_5%~D RH80 10K_0402_5%~D P10 10K_0402_5%~D RH235 1K_0402_5% +3V_MXM M7 T11 1 +3V_MXM +3V_PCH CL_DATA1 2 R1730 20090512 add dual mosfet prevent ATI M92 electric leakage 5 PERN6 PERP6 PETN6 PETP6 LID_SW_IN# EC <14> 1 SML1CLK / GPIO58 SML1DATA / GPIO75 G PERN5 PERP5 PETN5 PETP5 1 SML1ALERT# / PCHHOT# / GPIO74 RH236 @ 10K_0402_5%~D 3 4 QH3B DMN66D0LDW-7 PEG_A_CLKRQ# / GPIO47 CLKOUT_PCIE0N CLKOUT_PCIE0P PCIECLKRQ0# / GPIO73 UH4 10/100/1G LAN ---> 2 1 RH67 2 BE38 BC38 AW38 AY38 DRAMRST_CNTRL_PCH <6,10,11> CLKOUT_PEG_A_N CLKOUT_PEG_A_P CLKOUT_PCIE1N CLKOUT_PCIE1P M10 PEG_CLKREQ#_R AB37 AB38 CLK_PEG_PCH# CLK_PEG_PCH CLK_PEG_PCH# CLK_PEG_PCH 6 1 QH3A DMN66D0LDW-7 <14> <14> 1 @ RH237 CLKOUT_DMI_N CLKOUT_DMI_P PCIECLKRQ1# / GPIO18 CLKOUT_DP_N CLKOUT_DP_P CLKOUT_PCIE2N CLKOUT_PCIE2P CLKIN_DMI_N CLKIN_DMI_P PCIECLKRQ2# / GPIO20 CLKOUT_PCIE3N CLKOUT_PCIE3P CLKIN_GND1_N CLKIN_GND1_P PCIECLKRQ3# / GPIO25 CLKIN_DOT_96N CLKIN_DOT_96P CLKOUT_PCIE4N CLKOUT_PCIE4P CLKIN_SATA_N CLKIN_SATA_P PCIECLKRQ4# / GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P REFCLK14IN AV22 AU22 CLK_CPU_DMI# CLK_CPU_DMI CLK_CPU_DMI# CLK_CPU_DMI <5> <5> CLKIN_PCILOOPBACK +3VS AM12 AM13 BF18 BE18 CLKIN_DMI# CLKIN_DMI BJ30 BG30 CLKIN_DMI2# CLKIN_DMI2 G24 E24 CLKIN_DOT96# CLKIN_DOT96 AK7 AK5 CLKIN_SATA# CLKIN_SATA RH146 2.2K_0402_5%~D SMBCLK 6 1 RH147 2.2K_0402_5%~D 1 @ RH239 PCH_SMBCLK 2 0_0402_5% SMBDATA K45 CLK_PCH_14M H45 CLK_PCI_LPBACK V47 V49 XTAL25_IN XTAL25_OUT Y47 XCLK_RCOMP 1 CLK_PCI_LPBACK <5,10,11,12,13,16,34,35,43> QH1A DMN66D0LDW-7 @ RH252 PCIECLKRQ5# / GPIO44 C 2 0_0402_5% +3VS 2 2 DRAMRST_CNTRL_PCH 2.2K_0402_5%~D 1 1 SML0DATA DRAMRST_CNTRL_PCH S 1 PERN4 PERP4 PETN4 PETP4 SML0CLK A12 2 2 33_0402_5%~D 22P_0402_50V8J~D Reserve for EMI please close to UH4 PERN3 PERP3 PETN3 PETP3 SML0ALERT# / GPIO60 1 CLK_PCH_14M BG40 BJ40 AY40 BB40 @ CH98 2 1 RH70 D @ RH250 SML1DATA 2.2K_0402_5%~D 5 BJ38 BG38 AU36 AV36 1 G BG37 BH37 AY36 BB36 2 2.2K_0402_5%~D RH65 3 4 S PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5_C PCIE_PTX_DRX_P5_C 1 SML1CLK D 2 0.1U_0402_25V6K~D 2 0.1U_0402_25V6K~D MEMORY SMBDATA C9 2 2.2K_0402_5%~D RH64 1 CH16 1 CH17 1 SML0DATA 2 PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5 SMBCLK 2 <43> <43> <43> <43> EXPRESS_CARD ---> 2 2.2K_0402_5%~D 1 RH63 G 2 0.1U_0402_25V6K~D 2 0.1U_0402_25V6K~D BF36 BE36 AY34 BB34 1 SML0CLK <37,38,40> S CH14 1 CH15 1 PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4_C PCIE_PTX_DRX_P4_C H14 LID_SW_IN# 0_0402_5% D PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4 2 2 <43> <43> <43> <43> 1 1 SMBDATA 1 @ RH172 G BG36 BJ36 AV34 AU34 CH8 CH9 PERN2 PERP2 PETN2 PETP2 PCH_LID_SW_IN# S PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3 SMBCLK E12 D CARD_READER ---> <35> <35> <35> <35> SMBALERT# / GPIO11 1 2 0.1U_0402_25V6K~D 2 0.1U_0402_25V6K~D PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3_C PCIE_PTX_DRX_P3_C CH10 1 CH20 1 BE34 BF34 BB32 AY32 2.2K_0402_5%~D RH62 PERN1 PERP1 PETN1 PETP1 2 2 0.1U_0402_25V6K~D 2 0.1U_0402_25V6K~D PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2_C PCIE_PTX_DRX_P2_C D MiniWLAN (Mini Card 1)---> BG34 BJ34 AV32 AU32 SMBUS PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2 PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1_C PCIE_PTX_DRX_P1_C 2 0.1U_0402_25V6K~D 2 0.1U_0402_25V6K~D Link <35> <35> <35> <35> CH12 1 CH13 1 Controller PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1 CLOCKS DMC ---> <31> <31> <31> <31> PCI-E* 10/100/1G LAN ---> 2 RH61 PCH_SMBDATA <5,10,11,12,13,16,34,35,43> QH1B DMN66D0LDW-7 2 0_0402_5% <19> +3VS B YH2 1 PAD~D PAD~D <14,15> 25MHZ_12PF_7V25000012 1 3 <5> CLK_CPU_ITP# <5> CLK_CPU_ITP 3 GND 1 4 2 <7> CLK_RES_ITP# <7> CLK_RES_ITP 1 T107 @ T108 @ V38 V37 2 10K_0402_5%~D VGA_ON K12 @ RH106 @ RH107 1 1 2 0_0402_5%~D CLK_BCLK_ITP# 2 0_0402_5%~D CLK_BCLK_ITP @ RH108 @ RH109 2 2 1 0_0402_5% 1 0_0402_5% AK14 AK13 +3V_MXM G PCIECLKRQ7# / GPIO46 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67 BD82HM77 QPRG-C1 BGA989~D IO_DET# K43 IO_DET# F47 DMC_PCH_DET# H47 BT_DET# K49 CAM_DET# IO_DET# 1 CAM_DET# 1 5 BT_DET# 2 S D SML1DATA DMN66D0LDW-7 <35> BT_DET# <35> CAM_DET# <25> DMC_PCH_DET# 2 10K_0402_5%~D 2 10K_0402_5%~D 6 D 4 4 EC_SMB_DA2 <15,30,40,41,44> RH91 RH89 RH74 RH75 RH76 RH77 RH78 RH79 RH183 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 2 10K_0402_5%~D 2 10K_0402_5%~D If use extenal CLK gen, please place close to CLK gen . else, please place close to PCH A DELL CONFIDENTIAL/PROPRIETARY MXM2_CLKREQ#_R QH9A DMN66D0LDW-7 Compal Electronics, Inc. 0_0402_5% PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title PCH (2/8) PCIE, SMBUS, CLK Size 3 2 Document Number Rev 0.1 LA-8321P Date: 5 <15,30,40,41,44> 2 1 S 2 1 R1735 QH6B 3 CLKIN_DMI2# CLKIN_DMI2 CLKIN_DMI# CLKIN_DMI CLKIN_DOT96# CLKIN_DOT96 CLKIN_SATA# CLKIN_SATA CLK_PCH_14M RH154 10K_0402_5%~D G DMN66D0LDW-7 1 EC_SMB_CK2 2 1 3 1 R1734 1 G 4 1 R1732 +3V_PCH R1565 10K_0402_5%~D 1 <43> DMC_PCH_DET# 12/08-74 01/03-92 +3V_MXM QH9B @ RH258 6 G CLKOUT_PCIE7N CLKOUT_PCIE7P R1737 2 SML1CLK QH6A DMN66D0LDW-7 +3VS <15> MXM2_CLKREQ# RH257 @ 10K_0402_5%~D +1.05VS_VCCDIFFCLKN PCIECLKRQ6# / GPIO45 RH256 1K_0402_5% A 2 90.9_0402_1% 5 1 RH100 S XCLK_RCOMP CLKOUT_PCIE6N CLKOUT_PCIE6P 2 2 T13 RH99 CH18 15P_0402_50V8J~D 2 CH19 15P_0402_50V8J~D 1 @ RH104 2 10K_0402_5%~D XTAL25_OUT 1 GND +3V_PCH VGA_ON 1 S 2 1M_0402_5%~D RH101 PEG_B_CLKRQ# / GPIO56 1 XTAL25_IN +3V_PCH <34> mSATA_DET# B D E6 V40 V42 XTAL25_IN XTAL25_OUT 2 MXM2_CLKREQ#_R CLKOUT_PEG_B_N CLKOUT_PEG_B_P D <15> MXM2_PEG_PCH# <15> MXM2_PEG_PCH FLEX CLOCKS MXM2 ---> Tuesday, January 17, 2012 Sheet 1 17 of 65 5 4 3 2 1 UH4C DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 BE24 BC20 BJ18 BJ20 D <4> <4> <4> <4> DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 <4> <4> <4> <4> DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 AW24 AW20 BB18 AV18 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 AY24 AY20 AY18 AU18 DMI0RXP DMI1RXP DMI2RXP DMI3RXP DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI0TXP DMI1TXP DMI2TXP DMI3TXP FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 FDI_INT +VCCP BJ24 DMI_IRCOMP 2 49.9_0402_1% RBIAS_CPY 2 750_0402_1% 1 RH111 1 RH112 BG25 BH21 DMI_ZCOMP FDI_FSYNC0 DMI_IRCOMP FDI_FSYNC1 DMI2RBIAS FDI_LSYNC0 4mil width and place within 500mil of the PCH FDI_LSYNC1 XDP_DBRESET# <5,16> XDP_DBRESET# <5,16,53> VGATE C12 K3 SUSACK# SYS_RESET# 1 2 PCH_SYS_PWROK P12 0_0402_5%~D SYS_PWROK 1 2 PM_PWROK_R 0_0402_5%~D PWROK @ R1911 C <40> PCH_PWROK @ RH117 1 <40> PCH_APWROK L10 2 @ RH118 L22 0_0402_5%~D PM_DRAM_PWRGD B13 <5> PM_DRAM_PWRGD PCH_RSMRST#_R C21 2 0_0402_5%~D 1 <40> PCH_RSMRST# @ RH120 <40> SUSPWRDNACK 1 2 SUSPWRDNACK_R K16 0_0402_5%~D 1 2 PBTN_OUT#_R 0_0402_5%~D @ RH121 <5,16,40> PBTN_OUT# @ RH122 ACIN_PCH +3V_PCH E20 H20 BATLOW# E10 RI# A10 APWROK DRAMPWROK RSMRST# System Power Management DSWVRMEN SUSACK#_R DPWROK WAKE# CLKRUN# / GPIO32 SUS_STAT# / GPIO61 SUSCLK / GPIO62 SLP_S5# / GPIO63 SLP_S4# SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PWRBTN# SLP_A# ACPRESENT / GPIO31 SLP_SUS# BATLOW# / GPIO72 PMSYNCH RI# SLP_LAN# / GPIO29 BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 AW16 FDI_INT AV12 FDI_FSYNC0 BC10 FDI_FSYNC1 AV14 FDI_LSYNC0 BB10 FDI_LSYNC1 A18 E22 PCH_DPWROK_R 1 @ RH113 B9 WAKE# PM_CLKRUN# G8 SUS_STAT# N14 PM_SLP_S5# H4 PM_SLP_S4# G16 PM_SLP_SUS# PCH_LCD_CLK PCH_LCD_DATA <24> PCH_LCD_CLK <24> PCH_LCD_DATA CTRL_CLK CTRL_DATA LVDS_IBG PAD~D T203 @ FDI_LSYNC0 <4> FDI_LSYNC1 <4> PAD~D T113 PAD~D AF37 AF36 AK39 AK40 <24> PCH_TXCLK<24> PCH_TXCLK+ PCIE_WAKE# <31,35,40,43> <24> PCH_TXOUT0<24> PCH_TXOUT1<24> PCH_TXOUT2- AN48 AM47 AK47 AJ48 <24> PCH_TXOUT0+ <24> PCH_TXOUT1+ <24> PCH_TXOUT2+ AN47 AM49 AK49 AJ47 AF40 AF39 <24> PCH_TZCLK<24> PCH_TZCLK+ <24> PCH_TZOUT0<24> PCH_TZOUT1<24> PCH_TZOUT2- AH45 AH47 AF49 AF45 <24> PCH_TZOUT0+ <24> PCH_TZOUT1+ <24> PCH_TZOUT2+ AH43 AH49 AF47 AF43 SUSCLK_R <40> PM_SLP_S5# <37,40> PM_SLP_S4# <40> PM_SLP_S3# <37,40> <26> PCH_CRT_DDC_CLK <26> PCH_CRT_DDC_DAT <26> PCH_CRT_BLU <26> PCH_CRT_GRN <26> PCH_CRT_RED PAD~D T115 PAD~D T116 PAD~D T165 PAD~D <26> PCH_CRT_HSYNC <26> PCH_CRT_VSYNC H_PM_SYNC @ K14 T45 P39 PAD~D T112 T114 T40 K47 PCH_CRT_BLU PCH_CRT_GRN PCH_CRT_RED N48 P49 T49 PCH_CRT_DDC_CLK PCH_CRT_DDC_DAT T39 M40 33_0402_5%~D 2 HSYNC 2 VSYNC 33_0402_5%~D M47 M49 RH123 1 1 RH124 CRT_IREF <5> T43 T42 SDVO_TVCLKINN SDVO_TVCLKINP L_BKLTCTL SDVO_STALLN SDVO_STALLP L_DDC_CLK L_DDC_DATA SDVO_INTN SDVO_INTP RH126 1K_0402_0.5% If not using integrated @ LAN,signal may be left as NC. AP43 AP45 AM42 AM40 D AP39 AP40 L_CTRL_CLK L_CTRL_DATA LVD_IBG LVD_VBG SDVO_CTRLCLK SDVO_CTRLDATA LVD_VREFH LVD_VREFL LVDSA_CLK# LVDSA_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 DDPB_AUXN DDPB_AUXP DDPB_HPD LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 CRT_BLUE CRT_GREEN CRT_RED CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_VSYNC DAC_IREF CRT_IRTN DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P DDPC_CTRLCLK DDPC_CTRLDATA DDPC_AUXN DDPC_AUXP DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P DDPD_CTRLCLK DDPD_CTRLDATA DDPD_AUXN DDPD_AUXP DDPD_HPD DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P P38 M39 HDMICLK_NB HDMIDAT_NB <27> <27> AT49 AT47 AT40 TMDS_B_HPD <27> AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49 TMDS_B_DATA2# <27> TMDS_B_DATA2 <27> TMDS_B_DATA1# <27> TMDS_B_DATA1 <27> TMDS_B_DATA0# <27> TMDS_B_DATA0 <27> TMDS_B_CLK# <27> TMDS_B_CLK <27> P46 P42 PCH_DPC_CLK PCH_DPC_DAT AP47 AP49 AT38 PCH_DPC_AUXN <28> PCH_DPC_AUXP <28> PCH_DPC_HPD <28> AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 PCH_DPC_N0 PCH_DPC_P0 PCH_DPC_N1 PCH_DPC_P1 PCH_DPC_N2 PCH_DPC_P2 PCH_DPC_N3 PCH_DPC_P3 M43 M36 PCH_DPD_CLK PCH_DPD_DAT AT45 AT43 BH41 PCH_DPD_AUXP <29> PCH_DPD_AUXN <29> PCH_DMC_HPD <29> BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42 PCH_DPD_N0 PCH_DPD_P0 PCH_DPD_N1 PCH_DPD_P1 PCH_DPD_N2 PCH_DPD_P2 PCH_DPD_N3 PCH_DPD_P3 HDMI <28> <28> <28> <28> <28> <28> <28> <28> <28> <28> C mini DP <29> <29> <29> <29> <29> <29> <29> <29> <29> <29> DMC ( HDMI ) BD82HM77 QPRG-C1 BGA989~D 2 1 @ AP14 H_PM_SYNC BD82HM77 QPRG-C1 BGA989~D 1 2 3 2 6 <24> PCH_INV_PWM L_BKLTEN L_VDD_EN +3VS B ACIN_PCH 1 2 1 2 1 2 1 2 1 2 1 2 RH128 D RH130 D RH153 4 2 S QH11B DMN66D0LDW-7 G 1 <4> Can be left NC when IAMT is not support on the platfrom G +RTCVCC RH166 RV59 S QH11A DMN66D0LDW-7 DSWODVREN follow CRB Rev 0.7 SUSPWRDNACK FDI_FSYNC1 PM_SLP_S3# 5 ACIN <4> @ G10 P45 <4> 2 0_0402_5%~D 1 J47 M45 AE48 AE47 FDI_FSYNC0 2 0_0402_5%~D 1 @ R1900 10K_0402_5%~D R1899 10K_0402_5%~D <14,37,40,43,47> <4> <4> <4> <4> <4> <4> <4> <4> UH4D IGPU_BKLT_EN PCH_ENVDD <24> IGPU_BKLT_EN <24,40> PCH_ENVDD 2 0_0402_5%~D PCH_RSMRST#_R @ F4 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 T110 @ SUSCLK @ RH119 +3V_PCH B @ RH115 D10 <4> <4> <4> <4> <4> <4> <4> <4> FDI_INT DSWODVREN N3 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 Digital Display Interface DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 LVDS <4> <4> <4> <4> DMI0RXN DMI1RXN DMI2RXN DMI3RXN CRT BC24 BE20 BG18 BG20 1 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 FDI DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI <4> <4> <4> <4> RH127 2 RH129 2 1 330K_0402_5%~D @ 1 330K_0402_5%~D DSWODVREN - On Die DSW VR Enable H：Enable L：Disable * @ RH135 +3V_PCH BATLOW# RH139 1 2 10K_0402_5%~D RI# RH140 1 2 10K_0402_5%~D WAKE# RH142 1 2 1K_0402_5% @ RH144 1 2 10K_0402_5%~D RH145 1 2 10K_0402_5%~D A 1 @ R1901 1 R1736 1 RH110 1 RH243 2 RH244 1 RH131 1 RH132 1 RH133 1 RH134 2 SUSACK#_R 0_0402_5% 1 RV61 PCH_CRT_DDC_CLK 2.2K_0402_5%~D PCH_CRT_DDC_DAT 2.2K_0402_5%~D CTRL_CLK 2.2K_0402_5%~D CTRL_DATA 2.2K_0402_5%~D PCH_LCD_CLK 2.2K_0402_5%~D PCH_LCD_DATA 2.2K_0402_5%~D 2 10K_0402_5%~D PM_CLKRUN# 2 10K_0402_5%~D IGPU_BKLT_EN 2 100K_0402_5% TMDS_B_HPD 2 100K_0402_5%~D LVDS_IBG 1 2.37K_0402_1% PCH_CRT_BLU 2 150_0402_1% PCH_CRT_GRN 2 150_0402_1% PCH_CRT_RED 2 150_0402_1% PCH_ENVDD 2 100K_0402_5% A DELL CONFIDENTIAL/PROPRIETARY SUSPWRDNACK PCH_RSMRST# Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title PCH (3/8) DMI,FDI,PM,GFX,DP Size 4 3 2 Rev 0.1 LA-8321P Date: 5 Document Number Tuesday, January 17, 2012 Sheet 1 18 of 65 5 4 3 2 1 UH4E PAD~D PAD~D PAD~D PAD~D T142 T143 T144 T145 @ @ @ @ B21 M20 AY16 BG46 USB3RN1 USB3RN2 USB3RN3 USB3RN4 USB3RP1 USB3RP2 USB3RP3 USB3RP4 USB3TN1 USB3TN2 USB3TN3 USB3TN4 USB3TP1 USB3TP2 USB3TP3 USB3TP4 USB3RN1 USB3RN2 USB3RN3 USB3RN4 USB3RP1 USB3RP2 USB3RP3 USB3RP4 USB3TN1 USB3TN2 USB3TN3 USB3TN4 USB3TP1 USB3TP2 USB3TP3 USB3TP4 BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# <24,26,27,28,29> DGPU_SELECT# <42> DGPU_PWR_EN <35> DMC_RADIO_OFF# <24> HDMI_IN_PWMSEL# <35> WL_OFF# <34> <34> <28> <35> DMC_RADIO_OFF# HDMI_IN_PWMSEL# WL_OFF# FFS_INT1 ODD_DA# FFS_INT1 ODD_DA# DP_CBL_DET BT_ON# PAD~D DGPU_HOLD_RST# DGPU_SELECT# BT_ON# T206 @ <17> CLK_PCI_LPBACK <40> CLK_PCI_LPC <35> CLK_DEBUG CLK_PCI_LPBACK CLK_PCI_LPC CLK_DEBUG RH160 RH102 RH169 1 22_0402_5% 2 22_0402_5% 1 22_0402_5% 2 1 2 PAD~D PAD~D T200 @ T199 @ C46 C44 E40 D47 E42 F46 G42 G40 C42 D44 K10 PCH_PLTRST# B K40 K38 H38 G38 CLK_PCI0 CLK_PCI1 CLK_PCI2 CLK_PCI3 CLK_PCI4 C6 H49 H43 J48 K42 H40 RSVD1 RSVD2 RSVD3 RSVD4 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45 TP21 TP22 TP23 TP24 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 USB3Rn1 USB3Rn2 USB3Rn3 USB3Rn4 USB3Rp1 USB3Rp2 USB3Rp3 USB3Rp4 USB3Tn1 USB3Tn2 USB3Tn3 USB3Tn4 USB3TP1 USB3Tp2 USB3Tp3 USB3Tp4 PIRQA# PIRQB# PIRQC# PIRQD# RSVD28 RSVD29 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P EHCIⅠ REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 USB C @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ USB30 <43> <43> <36> <36> <43> <43> <36> <36> <43> <43> <36> <36> <43> <43> <36> <36> T118 T119 T130 T120 T131 T132 T121 T122 T139 T123 T124 T134 T140 T125 T126 T135 T136 T127 T128 T129 PCI D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D EHCIⅡ GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 USBRBIAS# USBRBIAS AY7 AV7 AU3 BG4 AT10 BC8 AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 D AV5 AV10 AT8 AY5 BA2 AT12 BF3 C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 C33 USBRBIAS USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N11 USB20_P11 USB20_N12 USB20_P12 USB20_N13 USB20_P13 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 <43> <43> <43> <43> <36> <36> <36> <36> <35> <35> <35> <35> <37> <37> USB20_N8 USB20_P8 USB20_N9 USB20_P9 <35> <35> <43> <43> USB20_N11 USB20_P11 USB20_N12 USB20_P12 USB20_N13 USB20_P13 <43> <43> <25> <25> <44> <44> USB/B USB/B USB/B C USB/B Mini Card(WLAN) DMC ELC Bluetooth USB / eSATA combo Conn. EXPRESS CARD +3V_PCH Camera USB_OC0# 1.5VDDR_VID1 USB_OC3# USB_OC2# USB_OC1# USB_OC4# ESATA_DETECT# 1.5VDDR_VID0 VPK Within 500 mils 1 RH151 2 22.6_0402_1% B33 PME# PLTRST# OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 A14 K20 B17 C16 L16 A16 D14 C14 USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# 1.5VDDR_VID0 1.5VDDR_VID1 ESATA_DETECT# USB_OC0# <16,43> (For USB_OC1# <16,43> (For USB_OC2# <16,36> (For USB_OC3# <16,36> (For USB_OC4# <16,43> (For 1.5VDDR_VID0 <16,51> 1.5VDDR_VID1 <16,51> ESATA_DETECT# <16,43> USB USB USB USB USB Port Port Port Port Port RH267 RH268 RH269 RH270 RH271 RH272 RH273 RH274 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 0) 1) 2) 3) 9) B BD82HM77 QPRG-C1 BGA989~D +3VS +3V_MXM +3VS 1 2 @ RH254 0_0402_5% +3VS C1847 1 5 PCH_PLTRST# <14,15> PLTRST_VGA# 2 1 4 RH230 0_0402_5%~D 2 SN74AHC1G08DCKR_SC70-5 1 PCH_PLTRST# 2 DGPU_HOLD_RST# IN1 O IN2 3 IN2 1 IN1 O 2 0.1U_0402_25V6K~D UH5 UH3 4 PLT_RST# 1 2 5 0.1U_0402_25V6K~D P <5,16,31,35,40,43> C1848 @ R1908 10K_0402_5%~D 2 P 1 G @ RH262 10K_0402_5%~D G 8.2K_0402_5%~D 8.2K_0402_5%~D 8.2K_0402_5%~D 8.2K_0402_5%~D 8.2K_0402_5%~D 8.2K_0402_5%~D 8.2K_0402_5%~D 8.2K_0402_5%~D 8.2K_0402_5%~D 8.2K_0402_5%~D 8.2K_0402_5%~D 10K_0402_5%~D SN74AHC1G08DCKR_SC70-5 RH231 100K_0402_5% 3 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 RH275 RH276 RH277 RH278 RH279 RH280 RH281 RH282 RH283 RH284 RH285 @ RH165 1 WL_OFF# PCI_PIRQB# PCI_PIRQD# PCI_PIRQC# DMC_RADIO_OFF# BT_ON# DGPU_SELECT# FFS_INT1 HDMI_IN_PWMSEL# PCI_PIRQA# ODD_DA# DGPU_HOLD_RST# 1 +3VS 2 2 RH157 100K_0402_5% 12/19-86 A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title PCH (4/8) PCI, USB, NVRAM Size 4 3 2 Rev 0.1 LA-8321P Date: 5 Document Number Tuesday, January 17, 2012 Sheet 1 19 of 65 5 4 3 2 1 2 +3VS RH232 10K_0402_5%~D High: CRT Plugged UH4F CRT_DET T7 BMBUSY# / GPIO0 TACH4 / GPIO68 TACH1 / GPIO1 TACH5 / GPIO69 TACH2 / GPIO6 TACH6 / GPIO70 TACH3 / GPIO7 TACH7 / GPIO71 C40 DGPU_BKL_PWM_SEL# <24> 1 <16> CRT_DET 1 <24,27,28,29> D G 3 D <27> DGPU_HPD_INT# QH2 2N7002E-T1-E3_SOT23-3 2 <26> CRT_DET# DGPU_EDIDSEL# DGPU_EDIDSEL# A42 DGPU_HPD_INT# H36 EC_SMI# C10 E38 <40> EC_SCI# S <40> EC_SMI# C4 C41 MXM2_PCH_PWROK LVDS_CAB_DET# LVDS_CAB_DET# A40 MXM2_EC_RST# DMI Termination Voltage <15> <25> <15> +3VS Set to Vcc when HIGH NV_CLE Set to Vss when LOW RH158 10K_0402_5%~D GPIO8 Weak internal PU,Do not pull low G2 LAN_PHY_PWR_CTRL / GPIO12 On-Die PLL Voltage Regulator This signal has a weak internal pull up GPIO15 A20GATE E8 PCH_GPIO27 E16 PCH_GPIO28 P8 PCH_GPIO28 2 1K_0402_5% STP_PCI# <15,16> MXM2_PCH_PWR_ON K4 ODD_DETECT# V8 <16> PCH_GPIO37 PCH_GPIO37 M5 <14> VGA_PRSNT_R# VGA_PRSNT_R# N2 <14> VGA_PRSNT_L# VGA_PRSNT_L# M3 MXM2_PCH_PWR_ON <16,34> PCH_GPIO37 FDI TERMINATION VOLTAGE OVERRIDE C * LOW - Tx, Rx terminated to same voltage (DC Coupling Mode) ODD_DETECT# <34> <15,16> +3VS 2 RH174 @ 1 1K_0402_5% MXM2_PRSNT_R# MXM2_PRSNT_R# V3 HDD2_DETECT# D6 PCH_GPIO27 (Have internal Pull-High) VCCVRM VR Enable Low: VCCVRM VR Disable *High: 1 2 GPIO28 PCH_GPIO27 10K_0402_5%~D VSS_NCTF_1 A4 VSS_NCTF_2 A44 VSS_NCTF_3 A45 VSS_NCTF_4 A46 VSS_NCTF_5 A5 VSS_NCTF_6 A6 VSS_NCTF_7 B3 VSS_NCTF_8 B47 VSS_NCTF_9 Layout note: Trace wide 10mil & length 30mil All NCTF pins should have thick traces at 45°from the pad. B INIT3_3V# DF_TVS TS_VSS1 STP_PCI# / GPIO34 TS_VSS2 GPIO35 TS_VSS3 SATA2GP / GPIO36 TS_VSS4 BD1 VSS_NCTF_10 BD49 VSS_NCTF_11 BE1 VSS_NCTF_12 BE49 VSS_NCTF_13 BF1 VSS_NCTF_14 BF49 PCH_PECI_R P5 KB_RST# @ 1 0_0402_5% AY11 KB_RST# T14 AY1 NV_CLE H_PECI <40> RH149 2.2K_0402_5%~D <5,40> <40> H_CPUPWRGD H_THERMTRIP#_C 1 390_0402_5% INIT3_3V# AY10 2 RH159 NV_CLE H_THRMTRIP# 2 1 RH150 <5> H_THRMTRIP# RH161 2 H_SNB_IVB# 1K_0402_5% <5> CLOSE TO THE BRANCHING POINT <5> INIT3_3V AH8 @ RH261 10K_0402_5%~D This signal has weak internal PU, can't pull low AK11 AH10 AK10 SATA3GP / GPIO37 SLOAD / GPIO38 NC_1 P37 @ T141 PAD~D BG2 VSS_NCTF_15 BG48 VSS_NCTF_16 MXM2_PRSNT_R# 1 RH265 2 10K_0402_5%~D BH3 VSS_NCTF_17 DGPU_HPD_INT# 1 RH163 2 10K_0402_5%~D BH47 VSS_NCTF_18 DGPU_EDIDSEL# 1 RH164 2 10K_0402_5%~D BJ4 VSS_NCTF_19 BJ44 VSS_NCTF_20 VGA_PRSNT_L# 1 RH182 2 10K_0402_5%~D BJ45 VSS_NCTF_21 VGA_PRSNT_R# 1 RH167 2 10K_0402_5%~D BJ46 VSS_NCTF_22 BJ5 VSS_NCTF_23 PCH_GPIO16 1 2 10K_0402_5%~D BJ6 VSS_NCTF_24 C2 VSS_NCTF_25 C48 VSS_NCTF_26 +3VS SDATAOUT0 / GPIO39 C SDATAOUT1 / GPIO48 VSS_NCTF_15 SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16 GPIO57 VSS_NCTF_17 VSS_NCTF_18 GPIO27 @ RH241 GPIO27 PCH_GPIO37 2 10K_0402_5%~D 1 V13 FFS_INT2 <34> HDD2_DETECT# RH173 K1 GPIO24 THRMTRIP# GATEA20 AU16 1 1 @ RH238 ODD_EN# SCLOCK / GPIO22 PROCPWRGD P4 2 <34> ODD_EN# 2 10K_0402_5%~D T5 TACH0 / GPIO17 CPU/MISC PCH_GPIO22 GPIO D40 <14> DGPU_PWROK +3V_PCH 1 SATA4GP / GPIO16 RCIN# H：On-Die voltage regulator enable L：On-Die PLL Voltage Regulator disable RH286 U2 PECI VSS_NCTF_1 VSS_NCTF_19 VSS_NCTF_2 VSS_NCTF_20 VSS_NCTF_3 VSS_NCTF_21 NCTF * <16> PCH_GPIO16 PCH_GPIO16 1 PCH_GPIO15 GPIO28 2 <16> PCH_GPIO15 D +1.8VS 1 <35> BT_RADIO_DIS# B41 2 CRT_DET VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_6 VSS_NCTF_24 VSS_NCTF_7 VSS_NCTF_25 VSS_NCTF_8 VSS_NCTF_26 VSS_NCTF_9 VSS_NCTF_27 VSS_NCTF_10 VSS_NCTF_28 VSS_NCTF_11 VSS_NCTF_29 VSS_NCTF_12 VSS_NCTF_30 VSS_NCTF_13 VSS_NCTF_31 VSS_NCTF_14 VSS_NCTF_32 RH181 D1 VSS_NCTF_27 D49 VSS_NCTF_28 E1 VSS_NCTF_29 +3V_PCH ODD_EN# 1 HDD2_DETECT# 1 2 10K_0402_5%~D RH176 2 10K_0402_5%~D RH170 E49 VSS_NCTF_30 F1 VSS_NCTF_31 F49 VSS_NCTF_32 Layout note: Trace wide 10mil & length 30mil All NCTF pins should have thick traces at 45°from the pad. BD82HM77 QPRG-C1 BGA989~D PCH_GPIO15 1 EC_SMI# 1 2 1K_0402_5% B RH177 2 10K_0402_5%~D RH71 CRT_DET# @ +3VS 2 10K_0402_5%~D 1 RH178 PCH_GPIO28 needs to be connected to XDP_FN8 PCH_GPIO35 needs to be connected to XDP_FN9 PCH_GPIO15 needs to be connected to XDP_FN16 STP_PCI# 1 KB_RST# 1 2 10K_0402_5%~D RH180 SATA2GP/GPIO36 2 10K_0402_5%~D RH203 Please refer to Huron River Debug Board DG 0.5 * When Used as SATA2GP/SATA3GP for Mechanical Presence detect - Use a weak external pull-up (150K-200K ohms) to Vcc3_3 PCH_GPIO22 1 check list LVDS_CAB_DET# 1 2 10K_0402_5%~D RH179 Rev 1.0 2 10K_0402_5%~D R1740 +3VS RH171 200K_0402_5% ODD_DETECT# 1 2 A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title PCH (5/8) GPIO, CPU, MISC Size 4 3 2 Rev 0.1 LA-8321P Date: 5 Document Number Tuesday, January 17, 2012 Sheet 1 20 of 65 5 4 3 2 1 +VCCP 2 VCCALVDS 2 0_0603_5%~D +1.05VS_VCCDPLLEXP 1 AN19 @ LH8 1+VCCAPLLEXP_R 1 2 1UH_LB2012T1R0M_20%~D 0_0603_5% 1 Place CH40 Near BJ22 pin 2 RH187 0_0805_5%~D @ BJ22 AN16 AN17 AN21 AN26 1 +VCCP @ CH40 10U_0805_25V6K~D +VCCAPLLEXP AN27 +1.05VS_VCC_EXP AP36 2 VCCAPLLEXP VCCIO[16] VCCIO[17] AP26 AT24 AN33 AN34 @ RH186 1 +3VS_VCC3_3_6 V33 VCC3_3[6] VCCIO[15] 1 V34 VCC3_3[7] 2 VCCIO[19] 2925mA +VCCAFDI_VRM Place CH53 Near BG6 pin 2 @ +VCCP @ RH193 1 2+1.05VS_VCCDPLL_FDI AP16 BG6 VCCIO[22] VCCIO[23] VCCIO[24] AP17 AU20 2 CH39 22U_0805_6.3V6M~D 2 +3VS +VCCP @ RH188 1 1 +1.05VS_VCC_DMI_CCI 1 @ RH287 1 AB36 VCCCLKDMI 2 2 0_0603_5%~D 2 1U_0402_6.3V6K~D CH50 1U_0402_6.3V6K~D VCCIO[26] AG16 VCCDFTERM[1] +VCCPNAND VCCVRM[2] VccAFDIPLL 1 AJ17 VCCDFTERM[4] VCCIO[27] VCCDMI[2] 1 AJ16 VCCDFTERM[3] 20mA RH192 AG17 190mA VCCDFTERM[2] VCC3_3[3] V1 VCCSPI 2 +3V_VCCPSPI VccADAC 3.3 0.001 VccADPLLA 1.05 0.08 VccADPLLB 1.05 0.08 VccCore 1.05 1.3 VccDMI 1.05 0.042 VccIO 1.05 2.925 VccASW 1.05 1.01 VccSPI 3.3 0.02 VccDSW 3.3 0.003 VccpNAND 1.8 0.19 VccRTC 3.3 6 uA VccSus3_3 3.3 0.119 2 2 VccSusHDA 3.3 / 1.5 0.01 VccVRM 1.8 / 1.5 0.16 VccCLKDMI 1.05 0.02 VccSSC 1.05 0.095 VccDIFFCLKN 1.05 0.055 VccALVDS 3.3 0.001 VccTX_LVDS 1.8 0.06 +3V_PCH 0_0805_5%~D CH54 1U_0402_6.3V6K~D B VCCVRM = 160mA detal waiting for newest spec 1 2 +VCCAFDI_VRM @ RH197 2 1 0_0603_5% +VCCAFDI_VRM @ RH198 1 2 0_0603_5%~D U8 1 SUSP# C +1.8VS RH194 1 1 2 0_0805_5%~D +1.5VS SUSP# 0.266 0_0805_5%~D +3VALW <9,40,42,43,49,50,51> 3.3 CH49 20mA BD82HM77 QPRG-C1 BGA989~D C2 1U_0402_6.3V6K~D Vcc3_3 2 VCCIO[25] 0_0805_5%~D +VCCP_VCCDMI 0.001 0.1uH inductor, 200mA +VCCP FDI CH53 1U_0402_6.3V6K~D 1 B +1.05VS_VCCAPLL_FDI 1 0_0603_5% 2 1 0.1UH_MLF1608DR10KT_10%_1608 1 +VCCP_VCCDMI AT20 VCCDMI[1] 0.1U_0402_25V6K~D @ +1.8VS +VCCAFDI_VRM AT16 VCCVRM[3] VCCIO[21] CH51 2 RH195 0.001 5 LH2 +VCCP_VCCDMI +VCCP 2 5 V5REF_Sus CH43 0.1U_0402_25V6K~D CH52 0.1U_0402_25V6K~D BH29 V5REF 0_0805_5%~D VCCIO[20] DFT / SPI +3VS_VCCA3GBG 1 0.001 D VCCIO[18] DMI AP24 1.05 VCCIO[28] VCCIO 1 CH48 1U_0402_6.3V6K~D 2 CH47 1U_0402_6.3V6K~D 2 1 S0 Iccmax Current (A) 2 AP37 VCCTX_LVDS[4] Voltage +3VS @ RH184 1 +VCCTX_LVDS CH37 1 1 0.01U_0402_16V7K~D CH38 0.01U_0402_16V7K~D 2 2 AM38 VCCTX_LVDS[2] 2 RH190 0_0805_5%~D @ 2 1 CH46 1U_0402_6.3V6K~D 1 2 1 CH44 10U_0805_25V6K~D 1 +3VS CH45 1U_0402_6.3V6K~D AP23 2 0_0805_5%~D 2 AP21 V_PROC_IO CH36 47U_0805_4V6M~D Near AP43 AM37 VCCTX_LVDS[1] HVCMOS @ RH185 2 Voltage Rail 1 AK37 VSSALVDS 60mA VCCTX_LVDS[3] +VCCP +VCCA_LVDS AK36 1 CH35 0.1U_0402_25V6K~D 1 U47 VSSADAC 1mA +VCCP C VCCADAC CRT VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17] +VCCADAC U48 CH34 0.01U_0402_16V7K~D 1mA LVDS 2 CH31 1U_0402_6.3V6K~D 2 1 CH33 1U_0402_6.3V6K~D 2 1 CH32 1U_0402_6.3V6K~D CH30 10U_0805_25V6K~D 2 D 1 AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31 VCC CORE +1.05VS_VCCCORE 1 PAD-OPEN 4x4m 1 @ +3VS LH1 BLM18PG181SN1_0603~D 1 2 1300mA 2 2 RH247 PCH Power Rail Table POWER UH4G PJP25 3 5 VOUT 4 NC 2 EN GND RT9013-15GB_SOT23-5 VIN 1 2 C1867 1U_0402_6.3V6K~D A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title PCH (6/8) PWR Size 4 3 2 Rev 0.1 LA-8321P Date: 5 Document Number Tuesday, January 17, 2012 Sheet 1 21 of 65 5 4 3 2 1 VCC3_3 = 266mA detal waiting for newest spec +VCCP VCCDMI = 42mA detal waiting for newest spec POWER 2 0_0603_5%~D @ RH206 AL29 +VCCSUS1 1 2 AL24 @ CH61 1U_0402_6.3V6K~D AA19 1 AA21 +1.05VM_VCCASW +VCCP AA26 AA27 AA29 AA31 1 2 C 1 2 1 2 CH69 1U_0402_6.3V6K~D AC26 2 0_0805_5%~D CH68 1U_0402_6.3V6K~D 1 @ RH211 CH67 1U_0402_6.3V6K~D <40> PCH_VREG_EN# 2 AA24 CH65 22U_0805_6.3V6M~D 2 2 1 CH64 22U_0805_6.3V6M~D G 1 AC27 AC29 AC31 AD29 AD31 +3VS W21 W23 2 0_0805_5%~D +3VS_VCC_CLKF33 1 2 1 2 @ W24 CH74 1U_0402_6.3V6K~D 1 CH73 10U_0805_25V6K~D @ RH216 VCCSUS3_3[7] VCCSUS3_3[8] VCCIO[14] DCPSUS[3] VCCSUS3_3[10] VCCSUS3_3[6] D S 3 119mA VCCAPLLDMI2 VCCSUS3_3[9] +3V_DSW @ QH5 AO3413_SOT23-3 W26 W29 W31 W33 VCCASW[1] VCCASW[2] VCCIO[34] 1010mA 1mA V5REF_SUS VCCASW[3] VCCASW[4] VCCASW[5] VCCASW[6] VCCASW[7] VCCASW[8] VCCASW[9] VCCASW[10] VCCASW[11] VCCASW[12] VCCASW[13] VCCASW[14] VCCASW[15] DCPSUS[4] VCCSUS3_3[1] +VCCRTCEXT N16 1mA V5REF VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCC3_3[1] VCC3_3[8] VCCASW[16] 2 +VCCAFDI_VRM Y49 VCC3_3[4] VCC3_3[2] VCCASW[20] VCCVRM[4] VCCIO[13] 2 +1.05VS_VCCDIFFCLKN 2 0_0603_5%~D 1 CH81 AG33 1 1 2 2 LH6 10UH_LBR2012T100M_20%~D 1 2 +VCCP @ R229 1 2 +VCCA_DPLL_L 1 2 A22 1 2 +1.05VS_VCCA_B_DPL + 2 1 2 1U_0402_6.3V6K~D CH93 2 1 220U_B2_2.5VM_R35M~D CH95 2 1 1U_0402_6.3V6K~D CH92 + 220U_B2_2.5VM_R35M~D CH94 1 VCCSSC +PCH_V5REF_SUS AN23 +VCCA_USBSUS AN24 +3V_VCCPSUS_1 1 2 1 2 2 1 0_0603_5%~D VCCIO[2] VCCIO[4] DCPSUS[1] DCPSUS[2] VCCASW[22] VCCASW[23] VCCASW[21] 10mA VCCSUSHDA 1 0_0603_5%~D CH63 0.1U_0603_50V7K~D +3V_PCH 2 +5VS CH66 0.1U_0402_25V6K~D +3V_VCCPSUS 2 1 0_0603_5%~D RH212 1 +3V_PCH P20 2 +3VS_VCCPCORE 1 0_0805_5%~D @ RH214 2 CH72 0.1U_0402_25V6K~D DH3 RB751S40T1_SOD523-2~D C +PCH_V5REF_RUN 1 2 1 +3VS RH213 10_0402_1% CH70 1U_0402_6.3V6K~D +3VS 2 CH71 1U_0603_25V6-K~D AA16 W16 +3VS_VCCPPCI T34 2 2 @ RH218 1 AF13 +3VS CH75 0.1U_0402_25V6K~D +VCC3_3_2 AJ2 1 0_0603_5%~D RH217 1 1 0_0603_5%~D +3VS 2 0_0805_5%~D +VCCP CH76 0.1U_0402_25V6K~D +1.05VS_SATA3 AH13 1 RH219 1 AH14 CH77 1U_0402_6.3V6K~D 2 AF14 AK1 +VCCSATAPLL AF11 +VCCAFDI_VRM 1 1 +1.05VS_VCC_SATA +1.05VS_VCC_SATA AC16 RH223 AC17 1 AD17 T21 1 2 2 @ LH5 10UH_LBR2012T100M_20%~D 2 +VCCSATAPLL_R @ RH221 2 1 +VCCP B 0_0805_5% @ CH80 10U_0805_25V6K~D Place CH80 Near AK1 pin 0_0805_5%~D V21 T19 +VCCSUSHDA P32 @ RH233 1 0_0603_5%~D 2 +3V_PCH 1 BD82HM77 QPRG-C1 BGA989~D CH91 0.1U_0402_25V6K~D 2 @ A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title PCH (7/8) PWR Size 4 3 2 Document Number Rev 0.1 LA-8321P Date: 5 1 1 N22 P22 +PCH_V5REF_SUS +VCCP 2 2 +PCH_V5REF_RUN N20 DH2 RB751S40T1_SOD523-2~D @ CH62 1U_0402_6.3V6K~D 2 @ RH210 P34 +3V_PCH 1 +VCCP VCCRTC +5V_PCH RH208 10_0402_1% +VCCP 95mA V_PROC_IO 1mA +3V_PCH CH60 0.1U_0402_25V6K~D @ RH209 DCPSST +RTCVCC +1.05VS_VCCA_A_DPL 2 LH7 10UH_LBR2012T100M_20%~D 0_0805_5%~D 1 1 +1.05VM_VCCSUS 0_0603_5% 1 T17 @ V19 CH83 1U_0402_6.3V6K~D 2 +V_CPU_IO BJ8 CH90 1U_0402_6.3V6K~D CH85 +1.05VS_VCCAUPLL M26 @ CH89 0.1U_0402_25V6K~D 2 2 +VCCP CH84 RH248 0.1U_0402_25V6K~D CH88 0.1U_0402_25V6K~D 2 2 0_0603_5%~D 1 4.7U_0603_10V6K~D A 1 CH87 0.1U_0402_25V6K~D @ RH226 1 CH86 0.1U_0402_25V6K~D CH96 1U_0402_6.3V6K~D T26 2 2 V16 2 0_0603_5%~D 1 P24 +3V_PCH D 1 2 +VCCSST @ RH246 VCCVRM[1] VCCIO[7] VCCDIFFCLKN[1] 55mA VCCDIFFCLKN[2] VCCDIFFCLKN[3] VCCIO[3] +1.05VS_SSCVCC 1U_0402_6.3V6K~D 2 V24 1 0_0603_5%~D 1 0_0603_5%~D 2 @ RH207 +VCCAFDI_VRM MISC 1 AF17 AF33 AF34 AG34 +1.05VS_VCCDIFFCLKN VCCADPLLB 80mA VCCAPLLSATA HDA 1U_0402_6.3V6K~D BF47 VCCIO[6] VCCADPLLA 80mA CPU CH79 @ RH222 +1.05VS_VCCA_B_DPL 1 V23 2 @ RH205 +3V_VCCAUBG 2 DCPRTC RTC B BD47 +VCCDIFFCLK 1 2 VCCASW[19] SATA +1.05VS_VCCA_A_DPL 2 0_0603_5%~D 1 T24 VCCASW[18] +VCCP @ RH220 +3V_VCCPUSB T23 VCCASW[17] VCCIO[12] CH78 0.1U_0402_25V6K~D 2 1 VCCIO[5] 1 1 <42> PCH_PWR_EN# R57 20K_0402_5% BH23 +VCCDPLL_CPY T29 2 1 +VCCAPLL_CPY_PCH T27 VCC3_3[5] 2 +VCCP 2 T38 VCCIO[33] 1 +3VALW 1 +3VS_VCC_CLKF33 VCCIO[32] @ RH245 CH56 1U_0402_6.3V6K~D 2 CH58 10U_0805_25V6K~D @ 0_0805_5% @ CH57 0.1U_0402_25V6K~D DCPSUSBYP 2 1 RH234 150_0402_1% 2 1 +VCCAPLL_CPY 2 V12 1 USB @ LH3 10UH_LBR2012T100M_20%~D 1 2 RH204 PCI/GPIO/LPC @ 1 P28 3 2 VCCIO[31] 1 +5VALW_PCH 0_0603_5%~D G +VCCP D VCCIO[30] 3mA VCCDSW3_3 +5V_PCH AO3413_SOT23-3 2 1 T16 +PCH_VCCDSW +5VALW +VCCP 1 +VCCPDSW P26 1 0_0603_5%~D 2 2 +1.05VS_VCCUSBCORE 2 @ RH202 1 N26 1 2 0_0603_5% VCCIO[29] D @ CH55 0.1U_0402_25V6K~D QH4 VCCACLK S 1 RH253 AD49 1 2 2 0_0603_5%~D @ RH201 Clock and Miscellaneous 1 +3V_DSW 2 UH4J C18 0.1U_0402_25V6K~D +VCCACLK 1 0_0603_5% CH82 1U_0402_6.3V6K~D @ CH59 0.1U_0402_25V6K~D 2 RH200 +3V_PCH Tuesday, January 17, 2012 Sheet 1 22 of 65 5 4 3 2 1 UH4I D AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3 UH4H H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3 C B VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28 BD82HM77 QPRG-C1 BGA989~D A VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28 D C B A BD82HM77 QPRG-C1 BGA989~D DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title PCH (8/8) PWR Size 4 3 2 Rev 0.1 LA-8321P Date: 5 Document Number Tuesday, January 17, 2012 Sheet 1 23 of 65 5 4 3 2 1 U43 LCD Backlight / PWM Selector @ R1917 2 1 0_0402_5% CV43 0.1U_0402_25V6K~D 2 U7 <14> VGA_PNL_PWM <30> HDMI_IN_PWM <18> PCH_INV_PWM @ R2560 1 @ R2570 1 @ R2580 1 1B1 1B2 1B3 1B4 10 11 12 13 2 0_0402_5%~D DGPU_BKL_EN_R 2 0_0402_5%~D HDMI_IN_BKL_EN_R IGPU_BKLT_EN 1 VCC S0 S1 2B1 2B2 2B3 2B4 1A 2A 2OE 1OE GND 16 INV_PWM_R ENBKL 7 9 15 8 HDMI IN 0 1 1B2 2B2 DSC 1 C Y 1B3 2B3 <18> PCH_TXOUT2<18> PCH_TXOUT2+ 71 70 <14> VGA_TXCLK<14> VGA_TXCLK+ VGA_TXCLKVGA_TXCLK+ 68 67 <18> PCH_TXCLK<18> PCH_TXCLK+ PCH_TXCLKPCH_TXCLK+ 66 65 0_0402_5%~D 1 2 @ RV111 2 BLM15BB221SN1D_2P~D DGPU_BKL_PWM_SEL# INV_PWM ENBKL <20> <25> <40> 64 63 1 2 S1 +3VS 1 1B1 1B2 1B3 1B4 10 11 12 13 1 CV48 0.1U_0402_25V6K~D 2 U3 6 5 4 3 <14> VGA_LCD_DAT <30> HDMI_IN_EDID_DAT <18> PCH_LCD_DATA 73 72 PCH_TXOUT2PCH_TXOUT2+ 62 61 16 VCC 14 2 S0 S1 2B1 2B2 2B3 2B4 2OE 1OE GND HDMI_IN_SELECT# DGPU_EDIDSEL_R# I2CC_SCL I2CC_SDA 7 9 1A 2A HDMI_IN_SELECT# DGPU_EDIDSEL_R# I2CC_SCL I2CC_SDA S0 1A 2A Y 0 0 1B1 2B1 HDMI IN 0 1 1B2 2B2 DSC 1 0 1B3 2B3 HDMI IN 1 1 1B4 2B4 UMA <25,40> <26> <25> <25> <14> VGA_TZOUT0<14> VGA_TZOUT0+ VGA_TZOUT0VGA_TZOUT0+ 60 59 <18> PCH_TZOUT0<18> PCH_TZOUT0+ PCH_TZOUT0PCH_TZOUT0+ 58 57 <14> VGA_TZOUT1<14> VGA_TZOUT1+ VGA_TZOUT1VGA_TZOUT1+ 56 55 <18> PCH_TZOUT1<18> PCH_TZOUT1+ PCH_TZOUT1PCH_TZOUT1+ 54 53 <14> VGA_TZOUT2<14> VGA_TZOUT2+ VGA_TZOUT2VGA_TZOUT2+ 51 50 <18> PCH_TZOUT2<18> PCH_TZOUT2+ PCH_TZOUT2PCH_TZOUT2+ 49 48 <14> VGA_TZCLK<14> VGA_TZCLK+ VGA_TZCLKVGA_TZCLK+ 46 45 <18> PCH_TZCLK<18> PCH_TZCLK+ PCH_TZCLKPCH_TZCLK+ 44 43 42 41 15 8 40 39 SN74CB3Q3253PWR_TSSOP16 3 13 20 21 31 38 52 74 25 7 1 CV50 0.1U_0402_25V6K~D 1 2 RV57 10K_0402_5%~D 2 LCDVDD_ON A 2 1 5 P 2 NC DGPU_EDIDSEL_R# 0_0402_5%~D Y 4 IGPU_EDIDSEL# IGPU_EDIDSEL# <26> QV12 SI2301CDS-T1-GE3_SOT23-3~D 3 +LCDVDD +5VALW 2 G CV37 4.7U_0603_10V6K~D 2 CV38 4.7U_0603_10V6K~D <14> DGPU_ENVDD <30> HDMI_IN_ENVDD <18,40> PCH_ENVDD 2 G DGPU_ENVDD HDMI_IN_ENVDD PCH_ENVDD 10 11 12 13 1 220K_0402_5%~D 3 QV5A DMN66D0LDW-7 SYS_TXOUT1SYS_TXOUT1+ <25> <25> D 2B2 3B2 4B1 5B1 A4 A5 11 12 SYS_TXOUT2SYS_TXOUT2+ SYS_TXOUT2SYS_TXOUT2+ <25> <25> 14 15 SYS_TXCLKSYS_TXCLK+ SYS_TXCLKSYS_TXCLK+ <25> <25> 23 24 SYS_TZOUT0SYS_TZOUT0+ SYS_TZOUT0SYS_TZOUT0+ <25> <25> 26 27 SYS_TZOUT1SYS_TZOUT1+ SYS_TZOUT1SYS_TZOUT1+ <25> <25> 29 30 SYS_TZOUT2SYS_TZOUT2+ SYS_TZOUT2SYS_TZOUT2+ <25> <25> 32 33 SYS_TZCLKSYS_TZCLK+ SYS_TZCLKSYS_TZCLK+ <25> <25> 4B2 5B2 6B1 7B1 A6 A7 6B2 7B2 8B1 9B1 A8 A9 17 18 8B2 9B2 10B1 11B1 A10 A11 34 10B2 11B2 12B1 13B1 A12 A13 @ RV42 1 2 0_0402_5%~D D QV5B DMN66D0LDW-7 5 G 4 2 0_0402_5%~D 14B1 15B1 A14 A15 14B2 15B2 16B1 17B1 A16 A17 16B2 17B2 18B1 19B1 A18 A19 35 36 18B2 19B2 +3VS GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 OE2# OE1# VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 4 10 19 22 28 37 47 69 CV53 1 2 1B1 1B2 1B3 1B4 VCC S0 S1 16 2 1 CV54 2 1 2 CV55 4.7U_0603_10V6K~D B CV67 0.1U_0402_25V6K~D 14 2 HDMI_IN_SELECT#_P DGPU_SELECT# 7 9 LCDVDD_ON @ RV113 1 DGPU_SELECT# 2 0_0402_5%~D <19,26,27,28,29> 2 2B1 2B2 2B3 2B4 2OE 1A 2A HDMI_IN_SELECT# <25,40> 1OE GND LCDVDD_ON <25> S1 S0 0 0 1A 1B1 2B1 2A HDMI IN Y 0 1 1B2 2B2 DSC 1 0 1B3 2B3 HDMI IN 1 1 1B4 2B4 UMA 15 8 SN74CB3Q3253PWR_TSSOP16 CV42 0.047U_0402_16V7K~D A DELL CONFIDENTIAL/PROPRIETARY S RV45 100K_0402_5% Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title LVDS SW - GPU & PCH Size 4 3 2 Document Number Rev 0.1 LA-8321P Date: 5 C 12B2 13B2 1 @ RV40 1 1 2 <40> EC_ENVDD 6 5 4 3 1 2 6 1 A LCDVDD_ON A2 A3 1 U610 3 RV36 2 S 2B1 3B1 +3VS S 1 2 SYS_TXOUT1SYS_TXOUT1+ 0B2 1B2 2 1 RV34 47K_0402_5% 8 9 SEL=LOW, B1, GPU SEL=High, B2, PCH +3VS 1 D 1 CV40 0.1U_0402_25V6K~D CV39 0.1U_0402_25V6K~D 2 1 D W=60mils 2 1 LCD VDD Selector RV32 47_0805_5%~D <25> <25> PI3LVD1012BE_BQSOP80 +LCDVDD 1 SYS_TXOUT0SYS_TXOUT0+ NC7SZ14P5X_NL_SC70-5~D LCD POWER 1 3 QV13 2N7002E-T1-E3_SOT23-3 G 2 @ RV55 D 1 DGPU_EDIDSEL# UV10 S <20,27,28,29> <19,26,27,28,29> SYS_TXOUT0SYS_TXOUT0+ +3VS G B DGPU_SELECT# 5 6 0.1U_0402_25V6K~D DGPU_SELECT# A0 A1 DGPU_SELECT# 16 0.1U_0402_25V6K~D +3VS @ RV54 0_0402_5% 1 2 0B1 1B1 SEL2 UMA LCD DDC Selector <14> VGA_LCD_CLK <30> HDMI_IN_EDID_CLK <18> PCH_LCD_CLK VGA_TXOUT2VGA_TXOUT2+ HDMI IN 1B4 2B4 1 <14> VGA_TXOUT2<14> VGA_TXOUT2+ RH138 1B1 2B1 76 75 100K_0402_5% 0 0 2A PCH_TXOUT1PCH_TXOUT1+ RV48 0 1 1A <18> PCH_TXOUT1<18> PCH_TXOUT1+ 10K_0402_5%~D S0 1 L100 C1840 SN74CB3Q3253PWR_TSSOP16 S1 78 77 HDMI_IN_PWM_SELECT# DGPU_BKL_PWM_SEL#_R 14 2 680P_0402_50V7K~D <14> DGPU_BKL_EN <30> HDMI_IN_BKL_EN <18> IGPU_BKLT_EN 6 5 4 3 2 0_0402_5%~D VGA_EC_PWM HDMI_IN_PWM 2 0_0402_5%~D PCH_INV_PWM_R <14> VGA_TXOUT1<14> VGA_TXOUT1+ 1 @ RV38 1 80 79 VGA_TXOUT1VGA_TXOUT1+ 2 0_0402_5% 2 10K_0402_5%~D 1 @ RV39 1 PCH_TXOUT0PCH_TXOUT0+ +3VS 1 +3VS D <40> EC_INV_PWM <18> PCH_TXOUT0<18> PCH_TXOUT0+ HDMI_IN_PWM_SELECT# 1 2 0_0402_5%~D 2 1 2 @ RV35 1 <14> VGA_TXOUT0<14> VGA_TXOUT0+ VGA_TXOUT0VGA_TXOUT0+ 2 HDMI_IN_SELECT# 2 0_0402_5% RV110 <19> HDMI_IN_PWMSEL# SLE1 @ RV33 1 @ DGPU_SELECT# Tuesday, January 17, 2012 Sheet 1 24 of 65 5 4 3 2 1 +3VS 1 SEL=LOW : B1, HDMI IN SEL=High: B2, SYSTEM @ RV62 10K_0402_5%~D 64 63 62 61 C <24> SYS_TZOUT0<24> SYS_TZOUT0+ SYS_TZOUT0SYS_TZOUT0+ 58 57 <30> LVDS_SW_TZOUT1<30> LVDS_SW_TZOUT1+ LVDS_SW_TZOUT1LVDS_SW_TZOUT1+ 56 55 <24> SYS_TZOUT1<24> SYS_TZOUT1+ SYS_TZOUT1SYS_TZOUT1+ 54 53 <30> LVDS_SW_TZOUT2<30> LVDS_SW_TZOUT2+ LVDS_SW_TZOUT2LVDS_SW_TZOUT2+ 51 50 <24> SYS_TZOUT2<24> SYS_TZOUT2+ SYS_TZOUT2SYS_TZOUT2+ 49 48 <30> LVDS_SW_TZCLK<30> LVDS_SW_TZCLK+ LVDS_SW_TZCLKLVDS_SW_TZCLK+ 46 45 <24> SYS_TZCLK<24> SYS_TZCLK+ SYS_TZCLKSYS_TZCLK+ 44 43 42 41 40 39 B A6 A7 14 15 <40> EN_CAM A8 A9 10B1 11B1 A10 A11 1 2 2 1 S D QV14 2N7002E-T1-E3_SOT23-3 1 R423 23 24 TZOUT0TZOUT0+ 26 27 TZOUT1TZOUT1+ LVDS Connector A12 A13 3 C LCD_BKL_EN +INVPWR_B+ C1852 0.1U_0402_25V6K~D A14 A15 29 30 TZOUT2TZOUT2+ +LCDVDD 1 CV45 A16 A17 32 33 0.1U_0402_25V6K~D TZCLKTZCLK+ 2 +3VS A18 A19 35 36 RV60 0_0603_5%~D @ VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 4 10 19 22 28 37 47 69 1 2 <24> 1 <40> W=60mils D73 INV_PWM BKOFF# 2 DMIC_CLK 2 1 CV60 2 1 2 6 V I/O 5 +5VS DMIC0 1 JLVDS 2 INV_PWM DISPOFF# 1 SDMK0340L-7-F_SOD323-2~D V I/O 2 R1918 10K_0402_5%~D V BUS Ground 4 V I/O V I/O IP4223CZ6_SO6-6 2 TXOUT0TXOUT0+ TXOUT1TXOUT1+ TXOUT2TXOUT2+ USB20_CMOS_N12 1 I2CC_SCL I2CC_SDA <24> I2CC_SCL <24> I2CC_SDA D61 2 +3VS_SWITCH CV59 1 +3VS 18B2 19B2 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 OE2# OE1# Q44 SSM3K7002FU_SC70-3~D W=60mils @ LV9 1 2 FBMA-L11-201209-221LMA30T_0805 16B2 17B2 18B1 19B1 C340 0.1U_0603_50V7K~D B+ 14B2 15B2 16B1 17B1 2 2 1 47K_0402_5% <40> LCD_BKL_EN 34 12B2 13B2 14B1 15B1 1 PWR_SRC_ON S 10B2 11B2 12B1 13B1 R422 100K_0402_5% Q11 2N7002E-T1-E3_SOT23-3 8B2 9B2 0.1U_0402_25V6K~D G 3 3 13 20 21 31 38 52 74 25 7 D 2 G 17 18 0.1U_0402_25V6K~D RV58 10K_0402_5%~D 1 2 6B2 7B2 8B1 9B1 C1851 0.1U_0402_25V6K~D TXCLKTXCLK+ +3VS <24> LCDVDD_ON 2 +INVPWR_B+ S 6B1 7B1 R1644 100K_0402_5% 1 10U_0805_25V6K~D CV46 60 59 C1747 0.1U_0402_25V6K~D 1 0.1U_0402_25V6K~D CV47 LVDS_SW_TZOUT0LVDS_SW_TZOUT0+ 2 4B2 5B2 SEL2 <30> LVDS_SW_TZOUT0<30> LVDS_SW_TZOUT0+ TXOUT2TXOUT2+ 2 G 66 65 11 12 80 mil 6 5 2 1 3 SYS_TXCLKSYS_TXCLK+ A4 A5 4 D 68 67 <24> SYS_TXCLK<24> SYS_TXCLK+ 4B1 5B1 80 mil 1 <30> LVDS_SW_TXCLK<30> LVDS_SW_TXCLK+ LVDS_SW_TXCLKLVDS_SW_TXCLK+ 2B2 3B2 Q45 FDC654P-G_SSOT-6~D B+ 1 2 71 70 AO3413_SOT23-3 3 2 SYS_TXOUT2SYS_TXOUT2+ A2 A3 +3VS_CAM Q1 1 <24> SYS_TXOUT2<24> SYS_TXOUT2+ 2B1 3B1 LCD Backlight Control +3VS 2 73 72 Camera Power Control 1 LVDS_SW_TXOUT2LVDS_SW_TXOUT2+ TXOUT1TXOUT1+ 3 <30> LVDS_SW_TXOUT2<30> LVDS_SW_TXOUT2+ 8 9 0B2 1B2 1 76 75 TXOUT0TXOUT0+ G <24> SYS_TXOUT1<24> SYS_TXOUT1+ SYS_TXOUT1SYS_TXOUT1+ 5 6 D 78 77 A0 A1 S LVDS_SW_TXOUT1LVDS_SW_TXOUT1+ 0B1 1B1 C346 1000P_0402_50V7K~D 80 79 <30> LVDS_SW_TXOUT1<30> LVDS_SW_TXOUT1+ 2 1 G <24> SYS_TXOUT0<24> SYS_TXOUT0+ SYS_TXOUT0SYS_TXOUT0+ D <24,40> D LVDS_SW_TXOUT0LVDS_SW_TXOUT0+ HDMI_IN_SELECT# S <30> LVDS_SW_TXOUT0<30> LVDS_SW_TXOUT0+ HDMI_IN_SELECT# 16 1 SLE1 2 D 2 U46 Carmer TXCLKTXCLK+ USB20_CMOS_P12 3 TZOUT0TZOUT0+ CV58 4.7U_0603_10V6K~D TZOUT1TZOUT1+ TZOUT2TZOUT2+ TZCLKTZCLK+ PI3LVD1012BE_BQSOP80 USB20_N12 USB20_P12 <19> USB20_N12 <19> USB20_P12 @ RV10 1 2 0_0402_5% @ RV51 1 2 0_0402_5% +3VS_CAM <32> DMIC_CLK <32> DMIC0 <17> CAM_DET# <20> LVDS_CAB_DET# <40> LCD_TEST USB20_CMOS_N12 USB20_CMOS_P12 DMIC_CLK DMIC0 CAM_DET# LVDS_CAB_DET# LCD_TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 L101 A USB20_N12 1 USB20_P12 4 1 4 2 3 2 USB20_CMOS_N12 3 USB20_CMOS_P12 B GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 45 46 47 48 49 50 51 52 53 54 55 JAE_FI-TD44SB-VF93-R750~D CONN@ A WCM2012F2S-900T04_0805 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title LVDS SW - SYSTEM & HDMI IN Size 4 3 2 Rev 0.1 LA-8321P Date: 5 Document Number Tuesday, January 17, 2012 Sheet 1 25 of 65 A B C D E +3VS VGA SW for PCH / GPU SEL=Low, N0 SEL=High, N1 2 UV11 PCH_CRT_RED PCH_CRT_GRN PCH_CRT_BLU PCH_CRT_HSYNC PCH_CRT_VSYNC 23 21 16 15 13 A1 B1 C1 D1 E1 YD YE CRT_R CRT_G CRT_B 8 11 CRT_HSYNC CRT_VSYNC @ RV114 1 2 0_0402_5%~D DGPU_SELECT# <19,24,27,28,29> 1 +3VS 3 7 10 20 GND GND GND GND CRT_DDC_DATA 1 D_DDCDATA 6 Q260A DMN66D0LDW-7 G <18> <18> <18> <18> <18> A0 B0 C0 D0 E0 DGPU_SELECT#_CRT 2 5 6 D 24 22 18 17 14 YA YB YC S VGA_CRT_R VGA_CRT_G VGA_CRT_B VGA_CRT_HSYNC VGA_CRT_VSYNC 12 SEL G <14> <14> <14> <14> <14> VDD VDD VDD VDD 5 1 4 9 19 2 2 1 CV71 CV70 1 0.1U_0402_25V6K~D 2 CV69 1 0.1U_0402_25V6K~D CV68 2 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 1 1 PI3V512QE_QSOP24 4 3 S D CRT_DDC_CLK D_DDCCLK Q260B DMN66D0LDW-7 LCD DDC Selector +3VS 2 U611 7 2S2 D2 2S3 GND 1 CRT_DDC_DATA <24> @ DV2 5 @ DV3 2 1 1.1A_6V_SMD1812P110TF 3 6 IGPU_EDIDSEL# 2 CRT_DDC_CLK 3 IGPU_EDIDSEL# 4 <24> 2 10 DGPU_EDIDSEL_R# 3 D1 DGPU_EDIDSEL_R# 2 IN2 2S1 1 0822 12 BAT1000-7-F_SOT23-3~D 1 8 1S3 11 1 <18> PCH_CRT_DDC_DAT IN1 1 9 VCC 1S2 FV1 C1853 0.1U_0402_25V6K~D 3 <14> VGA_DDC_DATA 1S1 +CRT_VCC 2 DV5 DAN217T146_SC59-3 2 DAN217T146_SC59-3 1 +R_CRT_VCC 3 2 DAN217T146_SC59-3 <14> VGA_DDC_CLK <18> PCH_CRT_DDC_CLK +5VS +3VS CV72 0.1U_0402_25V6K~D NC 1 2 @ DV4 2 2 1 @ R1897 0_1206_5% CRT Connector JCRT STG3856QTR_QFN1 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 @ PAD~D T80 1 1 2 UMA 3 1 2 1 2 1 2 1 2 1 2 1 2 CV49 6.8P_0402_50V8D~D 2S2 CV21 6.8P_0402_50V8D~D 1S2 CV20 6.8P_0402_50V8D~D 0 CV18 6.8P_0402_50V8D~D 1 CRT_B_2 CV17 6.8P_0402_50V8D~D DSC CRT_G_2 2 BLM18BB600SN1D_0603~D CV16 6.8P_0402_50V8D~D 2S1 2 BLM18BB600SN1D_0603~D 1 RV14 150_0402_1% 1S1 1 LV3 RV13 150_0402_1% 1 LV2 CRT_B RV12 150_0402_1% 0 CRT_G 1 Y CRT_R_2 2 D2 2 BLM18BB600SN1D_0603~D 1 D1 0 1 2 IN2 0 LV1 1 IN1 CRT_R <20> CRT_DET# CRT_DET# G G 16 17 TYCO_2041186-2~D CONN@ 3 CIS Link OK +CRT_VCC +CRT_VCC P 2 A 1 10K_0402_5%~D CRT_DET# Y LV4 1 2 0_0603_5%~D CRT_HSYNC_2 D_DDCDATA 3 1 RV24 1 RV25 D_DDCCLK 74AHCT1G125GW_SOT353-5 1 5 P OE# 4 CRT_VSYNC_1 3 G Y 74AHCT1G125GW_SOT353-5 LV5 1 2 0_0603_5%~D 1 CRT_VSYNC_2 1 CV24 4.7P_0402_50V8C~D 2 2 CV25 4.7P_0402_50V8C~D 2 2 1 2 68P_0402_50V8J~D A 2 2.2K_0402_5%~D 2 2.2K_0402_5%~D CV27 2 1 68P_0402_50V8J~D 1 UV2 100P_0402_50V8J~D 2 0.1U_0402_25V6K~D CV26 CV22 CRT_VSYNC 2 10K_0402_5%~D 1 +CRT_VCC CRT_HSYNC_1 4 +CRT_VCC CV28 1 @ RV115 UV1 G CRT_HSYNC 1 RV15 2 5 2 0.1U_0402_25V6K~D OE# CV23 1 4 4 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title CRT SW Size B C D Rev 0.1 LA-8321P Date: A Document Number Tuesday, January 17, 2012 Sheet E 26 of 65 5 4 3 2 1 +3VS +3VS +3VS 1 2 4.7K_0402_5%~D HDMI_PRE_EMI 3 C E 2 B Q264 @ MMST3904-7-F_SOT323~D @ R1856 1 2 4.7K_0402_5%~D HDMI_IN1_PEQ 1 2 4.7K_0402_5%~D HDMI_IN2_PEQ @ R1858 2 G 2 HDMI_CFG_HPD R1742 @ 10K_0402_5%~D S R1743 @ 200K_0402_5% 1 2 Q77 2N7002E-T1-E3_SOT23-3 C1126 C1114 C1123 C1116 C1122 C1115 C1124 C1125 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D PCH_HDMI_C_TXD2PCH_HDMI_C_TXD2+ PCH_HDMI_C_TXD1PCH_HDMI_C_TXD1+ PCH_HDMI_C_TXD0PCH_HDMI_C_TXD0+ PCH_HDMI_C_TXCPCH_HDMI_C_TXC+ <14> VGA_HDMI_DET <18> TMDS_B_HPD <14> GPU_HDMI_SCLK <14> GPU_HDMI_SDATA <18> HDMICLK_NB <18> HDMIDAT_NB <20,24,28,29> <19,24,26,28,29> 44 45 47 48 1 2 4 5 8 9 11 12 13 14 16 17 46 10 41 42 19 20 HDMICLK_NB HDMIDAT_NB 22 21 DGPU_EDIDSEL# DGPU_SELECT# HDMI_IN1_PEQ HDMI_IN2_PEQ 3 15 HDMICLK_NB 2.2K_0402_5%~D 2 1 R438 GPU_HDMI_SDATA 2.2K_0402_5%~D 2 1 R461 GPU_HDMI_SCLK 2.2K_0402_5%~D 2 1 R462 D PWDN_ASQ IN1_D1n IN1_D1p IN1_D2n IN1_D2p IN1_D3n IN1_D3p IN1_D4n IN1_D4p CFG_HPD DDCBUF PRE_EMI RTERM 1 2 as close as connector 10U_0603_6.3V6M~D TMDS_B_DATA2# TMDS_B_DATA2 TMDS_B_DATA1# TMDS_B_DATA1 TMDS_B_DATA0# TMDS_B_DATA0 TMDS_B_CLK# TMDS_B_CLK GPU_HDMI_C_TX2GPU_HDMI_C_TX2+ GPU_HDMI_C_TX1GPU_HDMI_C_TX1+ GPU_HDMI_C_TX0GPU_HDMI_C_TX0+ GPU_HDMI_C_CLKGPU_HDMI_C_CLK+ 2 C1077 TMDS_B_DATA2# TMDS_B_DATA2 TMDS_B_DATA1# TMDS_B_DATA1 TMDS_B_DATA0# TMDS_B_DATA0 TMDS_B_CLK# TMDS_B_CLK 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 1 0.1U_0402_25V6K~D <18> <18> <18> <18> <18> <18> <18> <18> 1 1 1 1 1 1 1 1 C1184 C 2 2 2 2 2 2 2 2 6 31 0.1U_0402_25V6K~D C1185 1 2 VDD VDD C1059 C1060 C1061 C1062 C1063 C1064 C1065 C1066 1 R437 +5VS U57 GPU_HDMI_TXD2GPU_HDMI_TXD2+ GPU_HDMI_TXD1GPU_HDMI_TXD1+ GPU_HDMI_TXD0GPU_HDMI_TXD0+ GPU_HDMI_TXCGPU_HDMI_TXC+ 2 +3V_MXM +3VS <14> <14> <14> <14> <14> <14> <14> <14> 2.2K_0402_5%~D @ D9 BAV99_SOT23-3 D 1 2 4.7K_0402_5%~D 1 1 0_0402_5%~D 2 2 D @ R1848 <20> DGPU_HPD_INT# HDMI_SW_DETECT @ R2652 1 HDMIDAT_NB HDMI_SINK_HPD C1058 220P_0402_50V7K~D HDMI_IN2_PEQ 1 HDMI_IN1_PEQ 2 4.7K_0402_5%~D 3 2 4.7K_0402_5%~D 1 L56 MBK1608221YZF_2P 1 2 2 R2600 1 R1741 @ 200K_0402_5% 1 2 1 R1857 1 HDMI_CFG_HPD 3 R1855 2 4.7K_0402_5%~D 1 @ R1847 @ R905 1 L59 DVI_TXD2+_R 3 DVI_TXD2-_R 2 25 3 0_0402_5% 2 DLW21SN900HQ2L_0805_4P~D 4 C_DVI_R_TXD2+ 4 1 1 @ R907 2 0_0402_5% 28 HDMI_CFG_HPD @ R917 1 40 34 7 HDMI_PRE_EMI L57 DVI_TXD1+_R 3 DVI_TXD1-_R 2 3 OUT_D1n OUT_D1p OUT_D2n OUT_D2p OUT_D3n OUT_D3p OUT_D4n OUT_D4p DVI_TXD2-_R DVI_TXD2+_R DVI_TXD1-_R DVI_TXD1+_R DVI_TXD0-_R DVI_TXD0+_R DVI_TXC-_R DVI_TXC+_R 36 35 33 32 30 29 27 26 0_0402_5% 2 IN1_HPD IN2_HPD IN1_SCL IN1_SDA IN2_SCL IN2_SDA 1 2 0_0402_5% DVI_TXD0-_R 3 DVI_TXD0+_R 2 3 OUT_HPD OUT_SCL OUT_SDA 39 38 37 1 1 2 0_0402_5% @ R918 1 0_0402_5% 2 3 DVI_TXC-_R 2 HDMI_SW_DETECT DVI_SCLK_L DVI_SDATA_L 0_0402_5% 2 2 DVI_TXC+_R 3 C C_DVI_R_TXD1- DLW21SN900HQ2L_0805_4P~D C_DVI_R_TXD04 4 1 @ R915 L58 SW_DDC SW_MAIN 1 2 1 @ R921 L55 C_DVI_R_TXD2- DLW21SN900HQ2L_0805_4P~D C_DVI_R_TXD1+ 4 4 @ R906 1 IN2_D1n IN2_D1p IN2_D2n IN2_D2p IN2_D3n IN2_D3p IN2_D4n IN2_D4p 1 2 C_DVI_R_TXD0+ DLW21SN900HQ2L_0805_4P~D C_DVI_R_TXC+ 4 4 1 2 1 1 @ R922 2 0_0402_5% C_DVI_R_TXC- IN1_PEQ IN2_PEQ B B 18 43 49 2 2 R1859 499_0402_1%~D C1824 2.2U_0603_10V7K~D 1 CEXT REXT GND GND PAD PS8271QFN48GTR-A1_QFN48_7X7 1 JHDMI HDMI_SINK_HPD 3 2 <30> HDMI_IN_TX <30> HDMI_IN_RX @ R1919 @ R1920 1 1 DVI_SDATA DVI_SCLK 2 0_0402_5%~D HDMI_IN_TX_CONN 0_0402_5%~D HDMI_IN_RX_CONN 2 C_DVI_R_TXCC_DVI_R_TXC+ C_DVI_R_TXD0C_DVI_R_TXD0+ C_DVI_R_TXD1- 1 Place LC Filter closed to JHDMI 1 1 1 IN2 @ R2559 @ R2561 2 0_0805_5%~D 2 0_0805_5%~D 1 1 C_DVI_R_TXD1+ C_DVI_R_TXD2- DVI_SDATA DVI_SCLK C_DVI_R_TXD2+ @ C1056 1 2 @ C1057 1 2 10P_0402_50V8J~D A DVI_SDATA_L DVI_SCLK_L 1 HDMI Connector +HDMI_5V_OUT @ D69 DAN217T146_SC59-3 10P_0402_50V8J~D 0_1206_5% 2 IN1 2 NC @ R1896 2 CV57 2 2 1 @ D68 DAN217T146_SC59-3 R901 2 2.2K_0402_5%~D 1 1.1A_6V_SMD1812P110TF R900 +HDMI_5V BAT1000-7-F_SOT23-3~D 1U_0603_25V6-K~D @ CV56 1U_0603_25V6-K~D 1 W=40mils 2.2K_0402_5%~D 1 +HDMI_5V_OUT FV2 3 2 +HDMI_5V_OUT D4 Y 0 +HDMI_5V_OUT +5VS 3 2 SEL 1 23 24 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ 20 21 22 23 SUYIN_100042GR019M23UZL CONN@ A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title HDMI SW Size 4 3 2 Rev 0.1 LA-8321P Date: 5 Document Number Tuesday, January 17, 2012 Sheet 1 27 of 65 A B C D E +3VS 1 +3VS_DP 2 DISP_DAT_AUXN_CONN R442 2 1 100K_0402_5%~D DISP_CLK_AUXP_CONN R59 1 2 100K_0402_5%~D U633 <14> VGA_DPD_AUXP/DDC <18> PCH_DPC_AUXP <18> PCH_DPC_CLK U634 1 <18> PCH_DPC_HPD PCH_DPC_HPD <14> VGA_DPD_HPD VGA_DPD_HPD 1 2 3 B2 GND B1 S VCC A DGPU_SELECT# 6 5 4 SN74LVC1G3157DCKR_SC70-6 2 1 R509 PCH_DPC_HPD 100K_0402_5%~D DGPU_SEL# Chanel <14> VGA_DPD_AUXN/DDC +3VS DISP_HPD_SINK 2.2K_0402_5%~D 2 1 R2264 PCH_DPC_DAT 2.2K_0402_5%~D 2 1 R2263 PCH_DPC_CLK <18> PCH_DPC_AUXN <18> PCH_DPC_DAT 0.1U_0402_25V6K~D 2 1 C1205 VGA_DPD_SW_AUXP 0.1U_0402_25V6K~D 2 1 C1204 PCH_DPC_AUXP_SW PCH_DPC_CLK 0.1U_0402_25V6K~D 2 1 C1206 VGA_DPD_SW_AUXN 0.1U_0402_25V6K~D 2 1 C1203 PCH_DPC_AUXN_SW PCH_DPC_DAT B1 GPU 4.7K_0402_5%~D 2 1 R2262 @ VGA_DPD_AUXN/DDC 1 B2 PCH 4.7K_0402_5%~D 2 1 R2261 @ VGA_DPD_AUXP/DDC +3VS 1 2 2 10/10 For ATI/Nvidia GPU 2 2 1 C1070 1 C1069 DISP_C_A0P DISP_C_A0N 42 41 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 2 2 1 C1073 1 C1071 DISP_C_A1P DISP_C_A1N 40 39 <14> VGA_DPD_P2 <14> VGA_DPD_N2 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 2 2 1 C1074 1 C1072 DISP_C_A2P DISP_C_A2N 38 37 <14> VGA_DPD_P3 <14> VGA_DPD_N3 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 2 2 1 C1076 1 C1075 DISP_C_A3P DISP_C_A3N 36 35 NC0+ NC0- For Intel PCH 3 <18> PCH_DPC_P2 <18> PCH_DPC_N2 <18> PCH_DPC_P3 <18> PCH_DPC_N3 2OE 1OE GND 2 2 1 C1079 1 C1109 PCH_DPC_C_P0 PCH_DPC_C_N0 15 8 S1 S0 0 0 1A 1B1 2B1 2A MXM_AUX Y 0 1 1B2 2B2 MXM_DDC 1 0 1B3 2B3 PCH_AUX 1 1 1B4 2B4 PCH_DDC 34 33 2 2 1 C1127 1 C1128 PCH_DPC_C_P1 PCH_DPC_C_N1 32 31 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 2 2 1 C1138 1 C1139 PCH_DPC_C_P2 PCH_DPC_C_N2 30 29 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 2 2 1 C1140 1 C1141 PCH_DPC_C_P3 PCH_DPC_C_N3 28 27 COM0+ COM0COM1+ COM1COM2+ COM2- NC3+ NC3- COM3+ COM3- NC4+ NC4- COM4+ COM4- 2 3 DISP_A0P_L DISP_A0N_L C1192 C1164 2 2 1 1 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D DISP_A0P DISP_A0N 4 5 DISP_A1P_L DISP_A1N_L C1191 C1194 2 2 1 1 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D DISP_A1P DISP_A1N 7 8 DISP_A2P_L DISP_A2N_L C1178 C1177 2 2 1 1 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D DISP_A2P DISP_A2N 9 10 DISP_A3P_L DISP_A3N_L C1193 C1190 2 2 1 1 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D DISP_A3P DISP_A3N 3 2 +3VS +3VS_DP D71 F2 1 1 1.1A_6V_SMD1812P110TF BAT1000-7-F_SOT23-3~D 11 12 2 0_1206_5% COM5+ COM5- 1 2 14 15 NO1+ NO1NO2+ NO2- JDP NO3+ NO3- SEL1 SEL2 16 17 DGPU_SELECT# DGPU_EDIDSEL# R2562 @ 2 0_0402_5%~D 1 DGPU_SELECT# DGPU_SELECT# <19,24,26,27,29> 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DISP_HPD_SINK DISP_A0P DGPU_EDIDSEL# NO4+ NO4- <20,24,27,29> DP_CBL_DET <19> DP_CBL_DET DISP_A0N DISP_CEC NO5+ NO5- EP DGPU_SEL# 43 MAX14998ETOLFT Chanel Source 0 NC GPU 1 NO PCH DISP_A1P DISP_A3P DISP_A1N DISP_A3N DISP_A2P DISP_CLK_AUXP_CONN DISP_A2N DISP_DAT_AUXN_CONN Place close JDP @ D10 DISP_A0N 1 1 @ R923 2 NO0+ NO0- 19 18 VGA_DPD_AUXP/DDC VGA_DPD_AUXN/DDC W=40mils 2 NC5+ NC5- 21 20 10 DISP_A0N 1 DISP_A0P 2 9 DISP_A0P DISP_A3P 4 7 DISP_A3P DISP_A3N 5 6 DISP_A3N +3VS_DP 3 GND HOT PLUG LANE0_P CONFIG1 LANE0_N CONFIG2 GND GND LANE1_P LANE3_P LANE1_N LANE3_N GND GND LANE2_P AUX_CH_P LANE2_N AUX_CH_N GND DP_PWR GND1 GND2 GND3 GND4 21 22 23 24 1 2 1 2 1 2 2 2 6 1 C1080 2 C1081 <29,40> 1 0.1U_0402_25V6K~D DP_MXM_CARD_SEL 1M_0402_5%~D DP_MXM_CARD_SEL G 22U_0805_6.3V6M~D RCLAMP0524P.TCT~D 2 4 R933 D 8 5.1M_0402_5% 3 R932 R529 100K_0402_5% 1M_0402_5%~D R507 100K_0402_5% R936 1 FOX_3V112M3-NH0RD7-7H~D 1 <14> VGA_DPD_AUXP/DDC <14> VGA_DPD_AUXN/DDC 1 2 NC2+ NC2- 23 22 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 1A 2A DISP_CLK_AUXP_CONN DISP_DAT_AUXN_CONN 7 9 U129 NC1+ NC1- 25 24 <18> PCH_DPC_P1 <18> PCH_DPC_N1 2B1 2B2 2B3 2B4 DP_CBL_DET DGPU_SELECT# 14 2 C1068 0.1U_0402_25V6K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D <14> VGA_DPD_P1 <14> VGA_DPD_N1 <18> PCH_DPC_P0 <18> PCH_DPC_N0 S0 S1 16 C1067 10U_0603_6.3V6M~D <14> VGA_DPD_P0 <14> VGA_DPD_N0 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D VCC +3VS 1 6 13 26 2 PCH/GPU AUX&LANE SW VDD_1 VDD_2 VDD_3 VDD_4 1 C60 0.1U_0402_16V4Z~D 2 C56 0.1U_0402_16V4Z~D 1 C61 0.1U_0402_16V4Z~D C57 0.1U_0402_16V4Z~D 2 1B1 1B2 1B3 1B4 SN74CB3Q3253PWR_TSSOP16 0 1 10 11 12 13 1 +3V_MXM Source 6 5 4 3 NC 2 C2037 0.1U_0402_16V4Z~D 1 C2038 0.1U_0402_16V4Z~D +3VS 2 4 Q263A DMN66D0LDW-7 3 D 1 @ D11 S DISP_A1P 1 10 DISP_A1P DISP_A1N 2 9 DISP_A1N DISP_A2P 4 7 DISP_A2P DISP_A2N 5 6 DISP_A2N DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. 5 4 G S Q263B DMN66D0LDW-7 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 3 8 Title DP SW for DP CONN Size Date: B C D Rev 0.1 LA-8321P RCLAMP0524P.TCT~D A Document Number Tuesday, January 17, 2012 Sheet E 28 of 65 5 4 3 2 1 +3VS 2 1 1 1 2 +3VS C2024 0.1U_0402_16V4Z~D R11 4.7K_0402_5%~D D R7 4.7K_0402_5%~D 2 +5VS D U4 1 1A 2A 1OE# 2OE# VCC 1B 2B GND 8 3 6 4 VGA_DPC_AUXP/DDC VGA_DPC_AUXN/DDC SN74CBTD3306CPWR_TSSOP8~D 2 R6 100K_0402_5%~D 2 5 1 7 DMC_DISP_CAB_DET# 1 +3VS VGA_DPC_AUXN/DDC @ R170 1 2 2.2K_0402_5%~D 2 <14> <14> <14> <14> <14> <14> <14> <14> From ATI/Nvidia GPU C1110 C1113 C1111 C1083 C1112 C1085 C1084 C1082 VGA_DPC_P3 VGA_DPC_N3 VGA_DPC_P2 VGA_DPC_N2 VGA_DPC_P1 VGA_DPC_N1 VGA_DPC_P0 VGA_DPC_N0 <18> <18> <18> <18> <18> <18> <18> <18> B 2 2 2 2 2 2 2 2 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D <14> VGA_DPC_AUXP/DDC <14> VGA_DPC_AUXN/DDC From Intel PCH 1 1 1 1 1 1 1 1 C1149 C1148 C1147 C1146 C1145 C1144 C1143 C1142 PCH_DPD_P3 PCH_DPD_N3 PCH_DPD_P2 PCH_DPD_N2 PCH_DPD_P1 PCH_DPD_N1 PCH_DPD_P0 PCH_DPD_N0 C1210 C1209 <18> PCH_DPD_AUXP <18> PCH_DPD_AUXN <18> PCH_DPD_CLK <18> PCH_DPD_DAT 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 1 1 2 C1208 2 C1207 2 2 2 2 2 2 2 2 1 1 2 0.1U_0402_25V6K~D 2 0.1U_0402_25V6K~D 3 DMC_IN2_PEQ DMC_IN1_PEQ DMC_IN1_AEQ# DMC_IN2_AEQ# 49 50 3 51 VGA_DPC_SW_P3 VGA_DPC_SW_N3 VGA_DPC_SW_P2 VGA_DPC_SW_N2 VGA_DPC_SW_P1 VGA_DPC_SW_N1 VGA_DPC_SW_P0 VGA_DPC_SW_N0 52 53 55 56 1 2 4 5 24 23 20 19 PCH_DPD_SW_P3 PCH_DPD_SW_N3 PCH_DPD_SW_P2 PCH_DPD_SW_N2 PCH_DPD_SW_P1 PCH_DPD_SW_N1 PCH_DPD_SW_P0 PCH_DPD_SW_N0 7 8 10 11 13 14 15 16 PCH_DPD_AUXP_P PCH_DPD_AUXN_N PCH_DPD_CLK PCH_DPD_DAT 26 25 22 21 VDD VDD SW_AUX OUT_AUXp_SCL OUT_AUXn_SDA IN2_PEQ/SDA_CTL IN1_PEQ/SCL_CTL IN1_AEQ# IN2_AEQ# AC_AUXp AC_AUXn I2C_CTL_EN IN1_D0p IN1_D0n IN1_D1p IN1_D1n IN1_D2p IN1_D2n IN1_D3p IN1_D3n IN1_AUXp IN1_AUXn IN1_SCL IN1_SDA IN2_D0p IN2_D0n IN2_D1p IN2_D1n IN2_D2p IN2_D2n IN2_D3p IN2_D3n CFG_OUTPUT CA_DET OUT_D0p OUT_D0n OUT_D1p OUT_D1n OUT2_D2p OUT2_D2n OUT_D3p OUT_D3n 47 DGPU_EDIDSEL# 28 27 DP_DMC_AUXP DP_DMC_AUXN 30 29 DP_DMC_AUXP_R DP_DMC_AUXN_R 1 2 100K_0402_5%~D R2651 1 2 100K_0402_5%~D @ R1924 1 2 4.7K_0402_5%~D @ R1929 1 2 4.7K_0402_5%~D @ R1916 1 2 4.7K_0402_5%~D @ R1915 1 2 4.7K_0402_5%~D @ R1926 1 2 4.7K_0402_5%~D @ R1913 1 2 4.7K_0402_5%~D @ R1925 1 2 4.7K_0402_5%~D @ R1921 1 2 4.7K_0402_5%~D @ R1922 1 2 4.7K_0402_5%~D @ R1909 1 2 4.7K_0402_5%~D @ R1923 1 2 4.7K_0402_5%~D @ R1914 1 2 4.7K_0402_5%~D <20,24,27,28> DP_DMC_AUXP DP_DMC_AUXN C2000 C2001 +3VS <35> <35> 2 0.1U_0402_25V6K~D 2 0.1U_0402_25V6K~D 1 1 DMC_CFG_OUTPUT 34 DMC_CFG_OUTPUT 44 DMC_DISP_CAB_DET 42 41 39 38 36 35 33 32 DMC_SW_P3 DMC_SW_N3 DMC_SW_P2 DMC_SW_N2 DMC_SW_P1 DMC_SW_N1 DMC_SW_P0 DMC_SW_N0 DMC_DISP_CAB_DET C2016 C2017 C2018 C2019 C2020 C2021 C2022 C2023 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 DMC_IN1_AEQ# <35> 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D DP_DMC_ML3P DP_DMC_ML3N DP_DMC_ML2P DP_DMC_ML2N DP_DMC_ML1P DP_DMC_ML1N DP_DMC_ML0P DP_DMC_ML0N DP_DMC_ML3P DP_DMC_ML3N DP_DMC_ML2P DP_DMC_ML2N DP_DMC_ML1P DP_DMC_ML1N DP_DMC_ML0P DP_DMC_ML0N <35> <35> <35> <35> <35> <35> <35> <35> DMC_IN2_AEQ# DMC_IN1_PEQ DMC_IN2_PEQ SW_ML/I2C_ADDR CFG_HPD OUT_HPD REXT CEXT IN1_HPD IN2_HPD GND GND Epad PD 46 43 DGPU_SELECT# DGPU_SELECT# C DP_DMC_HPD 18 17 45 12 57 40 <19,24,26,27,28> B DMC_CFG_HPD DP_DMC_HPD <35> SW_ML/I2C_ADDR Chanel Source 0 IN1 GPU 1 IN2 PCH +3VS PCH_DPD_CLK R448 2 1 2.2K_0402_5%~D PCH_DPD_DAT R449 2 1 2.2K_0402_5%~D +3VS 1 IN2_AUXp IN2_AUXn IN2_SCL IN2_SDA 48 2 DMC_DISP_CAB_DET @ R2659 2 10K_0402_5%~D 1 R2513 100K_0402_5%~D D 6 2 1 2 PS8321QFN56GTR-A0_QFN56_7X7 1 R1874 1 DGPU_EDIDSEL# 4.99K_0402_1% R2649 100K_0402_5%~D R2512 100K_0402_5%~D R2650 DP_DMC_AUXP DMC_CFG_HPD C1825 VGA_DPC_AUXN/DDC DP_DMC_AUXN 37 2.2U_0603_10V7K~D 6 9 <14> VGA_DMC_HPD <18> PCH_DMC_HPD VGA_DPC_AUXP/DDC 2N7002K_SOT23-3 U132 VGA_DPC_AUXP/DDC_P VGA_DPC_AUXN/DDC_N 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 1 1 1 1 1 1 1 1 S 2 54 31 C Q302 G 1 2 2.2K_0402_5%~D PCH/GPU AUX&LANE SW for DMC 1 +3VS D 2 2 @ R169 1 1 0.1U_0402_16V4Z~D C188 VGA_DPC_AUXP/DDC 0.1U_0402_16V4Z~D C197 +3V_MXM DMC_DISP_CAB_DET 2 S 1 2 G 3 5 MXM_MFG_SEL GPU Source 0 NVDIA 1 AMD 4 DMN66D0LDW-7 S A DELL CONFIDENTIAL/PROPRIETARY G Q301B <28,40> Q301A DMN66D0LDW-7 A D DP_MXM_CARD_SEL Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title HDMI SW for DMC Size 4 3 2 Rev 0.1 LA-8321P Date: 5 Document Number Tuesday, January 17, 2012 Sheet 1 29 of 65 5 4 +1.2VS_HDMI +5VS 1 1 2 2 CVDD_12 CVDD_12 CVDD_12 CVDD_12 AVDD_OUT_33 AVDD_OUT_33 ADC_DVDD_1V2 DPRX_VDDA_1V2 DPRX_VDDA_1V2 DPRX_VDDA_1V2 VDDA_1V2 2 22_0402_5% 2 22_0402_5% HDMI_DAT HDMI_CLK 70 71 72 73 74 44 45 1 3 1 2 5 O_CH0N_LV / TTL_D29 / GPIO_67 O_CH0P_LV / TTL_D28 / GPIO_66 O_CH1N_LV / TTL_D27 / GPIO_65 O_CH1P_LV / TTL_D26 / GPIO_64 O_CH2N_LV / TTL_D25 / GPIO_63 O_CH2P_LV / TTL_D24 / GPIO_62 O_CLKN_LV / TTL_D23 / GPIO_61 O_CLKP_LV / TTL_D22 / GPIO_60 O_CH3N_LV / TTL_D21 / GPIO_59 O_CH3P_LV / TTL_D20 / GPIO_58 XTAL TCLK NC RESETn STI_TM2 ADC_A_N ADC_A_P ADC_B_N ADC_B_P ADC_C_N ADC_C_P HSYNC_IN VSYNC_IN E_CH0N_LV / TTL_D19 / GPIO_57 E_CH0P_LV / TTL_D18 / GPIO_56 E_CH1N_LV / TTL_D17 / GPIO_55 E_CH1P_LV / TTL_D16 / GPIO_54 E_CH2N_LV / TTL_D15 / GPIO_53 E_CH2P_LV / TTL_D14 / GPIO_52 E_CLKN_LV / TTL_D13 / GPIO_51 E_CLKP_LV / TTL_D12 / GPIO_50 E_CH3N_LV / TTL_D11 / GPIO_49 E_CH3P_LV / TTL_D10 / GPIO_48 VEDID_VDD_3V3 A_I2C_SDA A_I2C_SCL D1_I2C_SDA / GPIO_28 D1_I2C_SCL / GPIO_29 D2_I2C_SDA / GPIO_24 D2_I2C_SCL / GPIO_25 GPIO_44 / S_I2C_SCL GPIO_43 / S_I2C_SDA PBIAS / TTL_D9 / GPO_4 PPOWER / TTL_D8 / GPO_3 10_0402_5% HDMI_IN_SW_CK10_0402_5% HDMI_IN_SW_CK+ 10_0402_5% HDMI_IN_SW_D010_0402_5% HDMI_IN_SW_D0+ 10_0402_5% HDMI_IN_SW_D110_0402_5% HDMI_IN_SW_D1+ 10_0402_5% HDMI_IN_SW_D210_0402_5% HDMI_IN_SW_D2+ 249_0402_1%~D HDMI_IN_SW_HPD <43> HDMI_IN_SW_HPD 2 2 2 2 2 2 2 2 2 75 76 78 79 81 82 84 85 87 113 114 GPO_2 / TTL_D7 / PWM2(BS_OCM_BOOT_SEL) STI_TM1 / PWM1 / TTL_D6 / GPO_1 GPO_0 / PWM0 / TTL_D5(BS_OSC_SEL) TTL_D4 / GPIO_21(BS_I2C_DEV_ID2) TTL_D3 / GPIO_20(BS_I2C_DEV_ID1) TTL_D2 / GPIO_19(BS_I2C_DEV_ID0) TTL_D1 / GPIO18 / M_I2C_SCL TTL_D0 / GPIO17 / M_I2C_SDA DPRX_AUXN DPRX_AUXP DPRX_ML_L0P DPRX_ML_L0N DPRX_ML_L1P DPRX_ML_L1N DPRX_ML_L2P DPRX_ML_L2N DPRX_ML_L3P TTL_CKOUT / GPIO16(BS_EXTKEY_EN) DPRX_ML_L3N UART_TX / TTL_SYNC1 / GPO_7(BS_XTAL_TCLK_SEL) DPRX_REXT UART_RX / TTL_SYNC2 / GPO_6 DPRX_HPD_OUT / GPO_5 VBUFC_RPLL HDMI_RXCN HDMI_RXCP HDMI_RX0N HDMI_RX0P HDMI_RX1N HDMI_RX1P HDMI_RX2N HDMI_RX2P HDMI_REXT HDMI_HPD / GPIO_22 HDMI_CEC / GPIO_23 HDMI_SPI_CS# HDMI_SPI_CLK HDMI_SPI_SO HDMI_SPI_SI 1 0_0402_5%~D 1 0_0402_5%~D 2 0_0402_5%~D 2 2 1 65 66 67 68 1 +3VS_DVDD 2 1 0.1U_0402_25V6K~D R85 10K_0402_5%~D BS_I2C_SRC_SEL R289 2 1 10K_0402_5%~D BS_EXTKEY_EN R295 2 1 10K_0402_5%~D BS_I2C_DEV_ID0 33 32 31 30 29 28 27 26 25 24 LVDS_SW_TXOUT0LVDS_SW_TXOUT0+ LVDS_SW_TXOUT1LVDS_SW_TXOUT1+ LVDS_SW_TXOUT2LVDS_SW_TXOUT2+ LVDS_SW_TXCLKLVDS_SW_TXCLK+ LVDS_SW_TXOUT0<25> LVDS_SW_TXOUT0+ <25> LVDS_SW_TXOUT1<25> LVDS_SW_TXOUT1+ <25> LVDS_SW_TXOUT2<25> LVDS_SW_TXOUT2+ <25> LVDS_SW_TXCLK<25> LVDS_SW_TXCLK+ <25> R296 2 1 10K_0402_5%~D BS_I2C_DEV_ID1 R297 2 1 10K_0402_5%~D BS_I2C_DEV_ID2 R288 2 1 10K_0402_5%~D BS_I2C_ON_SPI_EN 21 20 19 18 17 16 15 14 13 12 LVDS_SW_TZOUT0LVDS_SW_TZOUT0+ LVDS_SW_TZOUT1LVDS_SW_TZOUT1+ LVDS_SW_TZOUT2LVDS_SW_TZOUT2+ LVDS_SW_TZCLKLVDS_SW_TZCLK+ LVDS_SW_TZOUT0LVDS_SW_TZOUT0+ LVDS_SW_TZOUT1LVDS_SW_TZOUT1+ LVDS_SW_TZOUT2LVDS_SW_TZOUT2+ LVDS_SW_TZCLKLVDS_SW_TZCLK+ R276 2 1 10K_0402_5%~D BS_OSC_SEL R277 2 1 10K_0402_5%~D BS_XTAL_TCLK_SEL R278 2 1 10K_0402_5%~D BS_INTERFACE_SEL0 R280 2 1 10K_0402_5%~D BS_INTERFACE_SEL1 R282 2 1 10K_0402_5%~D BS_OCM_BOOT_SEL 3 2 HDMI_IN_BKL_EN HDMI_IN_ENVDD <25> <25> <25> <25> <25> <25> <25> <25> HDMI_IN_BKL_EN HDMI_IN_ENVDD <24> <24> 1 127 126 124 123 122 121 120 EDID_WP 119 118 117 BS_OCM_BOOT_SEL 5 C 1 2 Q261 MMST3904-7-F_SOT323~D 2 B HDMI_IN_PWM BS_I2C_DEV_ID2 BS_I2C_DEV_ID1 BS_I2C_DEV_ID0 HDMI_IN_NV_CLK HDMI_IN_NV_DAT C HDMI_IN_PWM @ R1641 1 2 0_0402_5%~D @ R1880 @ R1881 2 2 1 0_0402_5% 1 0_0402_5% @ R1645 1 2 0_0402_5%~D BS_XTAL_TCLK_SEL 22_0402_5% <24> E BS_OSC_SEL HDMI_IN_EDID_CLK HDMI_IN_EDID_DAT <24> <24> BS_EXTKEY_EN HDMI_IN_TX HDMI_IN_RX 2 1 R1784 <27> <27> +3VS_DVDD +5VS 4.7K_0402_5%~D R1674 10K_0402_5%~D B LBADC_IN4 / GPIO_35 LBADC_IN3 / GPIO_34 LBADC_IN2 / GPIO_33 / TTL_SYNC4 LBADC_IN1 / GPIO_32 / TTL_SYNC3 103 104 101 102 R291 2 1 10K_0402_5%~D R293 2 R294 2 1 1 10K_0402_5%~D 10K_0402_5%~D R1673 33K_0402_5% HDMI_IN_CABDET 1 1 110 HDMI_TOGGLE# 2 HDMI_IN_CAB_DET# <40,43> C292 0.1U_0402_25V6K~D <40> +3VS_DVDD I2S_0 (S/PDIF) / GPO_12(BS_RESERVED) I2S_AUMCLK / GPO_13(BS_SPI_FUN_SEL) I2S_WS / GPO_14(BS_I2C_SRC_SEL) I2S_SCLK / GPO_15(BS_I2C_ON_SPI_EN) VSSA_33 +3VS_DVDD 7 LVVSS LVVSS SPI_CSn / IRQ_IN / GPO_8 SPI_CLK / GPO_9(BS_INTERFACE_SEL1) SPI_DI / GPO_10(BS_INTERFACE_SEL0) SPI_DO / GPO_11(BS_UART_FUNCTION_SEL) CRVSS CRVSS CRVSS CRVSS DPRX_VSSD DPRX_VSSA DPRX_VSSA ADC_VSSA ADC_VSSA ADC_VSSA ADC_VSSD HDMI_VSSA HDMI_VSSA 34 22 115 107 69 37 @ R1786 4.7K_0402_5%~D 1 16Kbit NVRAM 2 U614 1 2 3 4 97 94 91 89 E0 E1 E2 VSS VCC WC SCL SDA 8 7 6 5 R1788 1 R1789 1 2 22_0402_5% 2 22_0402_5% HDMI_IN_NV_CLK HDMI_IN_NV_DAT M24C16-WMN6TP_SO8 (EEPROM) STDP6038-AC_PQFP128_20X14~D A U609 HDMI_SPI_CS#_R HDMI_SPI_SO_R HDMI_SPI_W# R275 15_0402_5% 1 2 3 4 S# Q W# VSS VCC RESET# C D 8 7 6 5 2 1 2 1 2Mbit SPI ROM R444 10K_0402_5%~D 2 1 77 83 C314 2 1 10K_0402_5%~D 2 39 40 41 42 47 55 61 +3VS_DVDD 2 R1787 4.7K_0402_5%~D R1650 R1651 @ R1652 BS_SPI_FUN_SEL R286 R1785 4.7K_0402_5%~D BS_INTERFACE_SEL1 BS_INTERFACE_SEL0 BS_UART_FUNCTION_SEL 1 10K_0402_5%~D C1811 0.1U_0402_25V6K~D 01/02-90 2 2 BS_RESERVED BS_SPI_FUN_SEL BS_I2C_SRC_SEL BS_I2C_ON_SPI_EN 2 BS_RESERVED R285 6 0.1U_0402_25V6K~D 1 BS_UART_FUNCTION_SEL 1 10K_0402_5%~D 1 <32> I2S_DAT/SPDIF_IN I2S_DAT/SPDIF_IN 1 10K_0402_5%~D 2 1 1 1 1 1 1 1 1 1 1 2 R284 R1687 GPIO_45 HDMI_SPI_CS# HDMI_SPI_SO +1.2VS_AVDD 2 R1688 R1689 R1690 R1691 R1692 R1693 R1694 R1695 R1637 HDMI_IN_CKHDMI_IN_CK+ HDMI_IN_D0HDMI_IN_D0+ HDMI_IN_D1HDMI_IN_D1+ HDMI_IN_D2HDMI_IN_D2+ C2039 R439 15_0402_5% 64 58 52 HDMI_IN_RX HDMI_IN_CKHDMI_IN_CK+ HDMI_IN_D0HDMI_IN_D0+ HDMI_IN_D1HDMI_IN_D1+ HDMI_IN_D2HDMI_IN_D2+ R283 50 1 P A R1636 300_0402_1% BS_RESERVED 2 +3VS_DVDD 88 2 G 2 NC O 48 49 53 54 56 57 59 60 62 63 51 43 +1.2VS_DVDD RVDD_33 RVDD_33 RVDD_33 2 +1.2VS_AVDD 116 108 46 35 1 1 HDMI_VDDA_3V3 HDMI_VDDA_3V3 ADC_AVDD_3V3 ADC_AVDD_3V3 2 1 1 2 1 2 +3VS_DVDD 0.1U_0402_25V6K~D 111 112 +3VS_AVDD A 2 1 2 C1751 12P_0402_50V8J~D C1750 2 2 1 3 1 2 2 3 G2 4 12P_0402_50V8J~D 2 1 4 I2S_DAT/SPDIF_IN <43> <43> <43> <43> <43> <43> <43> <43> 2 1 1 C279 22U_0805_6.3V6M~D 1 @ U635 NL17SZ17DFT2G_SOT353-5~D R1638 0_0402_5%~D @ 1 2 1 C281 0.1U_0402_25V6K~D XTALIN XTALOUT 1 2 1 C280 0.1U_0402_25V6K~D R1698 1 R1699 1 1 B 2 1 C278 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 92 0.1U_0402_25V6K~D 93 0.1U_0402_25V6K~D 95 0.1U_0402_25V6K~D 96 0.1U_0402_25V6K~D 98 0.1U_0402_25V6K~D 99 0.1U_0402_25V6K~D 105 0.1U_0402_25V6K~D 106 @ C2040 0.1U_0402_25V6K~D G1 2 1 C277 0.1U_0402_25V6K~D EC_SMB_DA2 EC_SMB_CK2 HDMI_SW_DAT HDMI_SW_CLK 4 125 2 2 2 2 2 2 2 2 +3VS 1 2 1 C276 0.1U_0402_25V6K~D 22_0402_5% 2 EDID_WP 1 10K_0402_5%~D 1 1 1 1 1 1 1 1 C291 Y5 2 2 C275 0.1U_0402_25V6K~D EDID_WP_R 1 HDMI_SW_CLK HDMI_SW_DAT EC_SMB_DA2 <15,17,40,41,44> EC_SMB_CK2 <43> HDMI_SW_DAT <43> HDMI_SW_CLK 27MHZ_10PF_7V27000050~D 2 1 +1.2VS_HDMI L22 BLM18BD601SN1D_0603~D 1 C274 22U_0805_6.3V6M~D C1793 C1794 C1795 C1796 C1797 C1798 C1799 C1800 2 M24C02-WMN6TP_SO8 <15,17,40,41,44> (EEPROM) 2 1 C273 0.1U_0402_25V6K~D VCC WC SCL SDA 2 1 C272 0.1U_0402_25V6K~D R271 2 1 C290 4700P_0402_25V7K~D R1686 8 7 6 5 2 1 C271 0.1U_0402_25V6K~D HDMI _RST# 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D E0 E1 E2 VSS 8 9 36 U9 1 2 3 4 80 86 90 100 38 109 128 XTALOUT XTALIN R272 2.2K_0402_5%~D R1685 R1684 R1683 2Kbit EDID ROM C 2 +3VS_DVDD +5VS_HDMI_IN_EDID 2 2 1 +1.2VS_DVDD D VDDA_3V3 DPRX_VDDD_1V2 +3VS_AVDD +5VS 1SS355TE-17_SOD323-2 C1792 0.1U_0402_25V6K~D 2 1 +3VS_DVDD 1 2 1 C270 0.1U_0402_25V6K~D 2 2 1 C284 0.1U_0402_25V6K~D 1 D24 2 1 C283 0.1U_0402_25V6K~D 2 1 D33 1SS355TE-17_SOD323-2 2 1 C282 0.1U_0402_25V6K~D 2 1 C289 0.1U_0402_25V6K~D +HDMI_IN_5VS is from plug-in device C288 0.1U_0402_25V6K~D C293 0.1U_0402_25V6K~D 1 +HDMI_IN_5VS 11 23 2 L25 BLM18BD601SN1D_0603~D 2 2 1 +1.2VS_HDMI L21 BLM18BD601SN1D_0603~D 2 C286 22U_0805_6.3V6M~D 1 1 2 1 +3.3V_AVDD_LVTX Vout = 0.8 *(R564+R565) / R565 1 2 1 1 +1.2VS_AVDD U2 10 +3VS_AVDD RT9025-25PSP_SO8~D 2 2 1 +3VS_DVDD 2 C268 0.1U_0402_25V6K~D R565 20K_0402_5% C1752 10U_0805_25V6K~D 2 9 GND L23 BLM18BD601SN1D_0603~D 1 8 GND ADJ 2 1 C267 0.1U_0402_25V6K~D EN 7 2 5 NC 2 C1749 10U_0805_25V6K~D 2 6 VOUT VIN C287 pin 2 as close as U2 pin7 GND C266 0.1U_0402_25V6K~D VDD 3 1 +3VS 1 C265 0.1U_0402_25V6K~D 1 +1.2VS_HDMI 2 +3VS_AVDD 2 C269 22U_0805_6.3V6M~D PGOOD 4 1 D 1 C287 0.1U_0402_25V6K~D U608 L20 BLM18BD601SN1D_0603~D 1 L24 BLM18BD601SN1D_0603~D R563 100K_0402_5% +3VS 2 C285 22U_0805_6.3V6M~D 2 +3VS C362 1U_0402_6.3V6K~D 1 +3.3V_AVDD_RPLL 1 R564 10K_0402_5%~D 3 +3VS_AVDD 2 +1.2VS_HDMI HDMI_SPI_CLK_R HDMI_SPI_SI_R R420 1 1 R445 15_0402_5% HDMI_SPI_CLK 2 HDMI_SPI_SI 2 15_0402_5% DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. M25PE20-VMN6TP_SO8N8 (Flash ROM) @ R419 1 @ C507 2 1 15_0402_5% PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 2 15P_0402_50V8J~D Title HDMI input - STDP6038 Size 4 3 2 Rev 0.1 LA-8321P Date: 5 Document Number Tuesday, January 17, 2012 Sheet 1 30 of 65 5 4 3 2 1 UL1 PCIE_PTX_DRX_P1 35 PCIE_PTX_DRX_N1 36 <17> CLK_PCIE_LAN CLK_PCIE_LAN 33 <17> CLK_PCIE_LAN# CLK_PCIE_LAN# 32 CLKREQ_LAN#_R 4 <17> PCIE_PTX_DRX_P1 <17> PCIE_PTX_DRX_N1 PLT_RST# PCIE_WAKE# PLT_RST# 2 PCIE_WAKE# 3 +LAN0 CL6 CL1 CL8 CL2 CL9 CL3 CL10 CL4 +LAN1 +LAN2 +LAN3 1 1 1 1 1 1 1 1 AVDDL AVDDL AVDDL AVDDL AVDDL_REG CLKREQ# PERST# 13 19 31 34 6 +AVDDL 16 22 9 +AVDDH 1000P_0402_50V7K~D 0.1U_0402_25V6K~D 1000P_0402_50V7K~D 0.1U_0402_25V6K~D 1000P_0402_50V7K~D 0.1U_0402_25V6K~D 1000P_0402_50V7K~D 0.1U_0402_25V6K~D 2 2 2 2 2 2 2 2 close to Lan chip REFCLK_N AVDDH AVDDH AVDDH_REG SMCLK SMDATA 28 27 41 NC TESTMODE GND 7 8 1 VDD33 +LX 1 2 +VDDCT 2.2UH_1225AS-H-2R2M-P2_1.3A_20% W=40mils W=40mils CL11 +VDDCT close to Lan pin40 2 2 18P_0402_50V8J~D 2 W=40mils close to Lan pin9 D 1A 0.1U_0402_25V6K~D 1.5M_0402_5%~D 2 1 RL20 B 1 CL36 2 2 CL33 2 1 CL34 2 1 CL35 2 10U_0603_6.3V6M~D CL32 1 10U_0603_6.3V6M~D 1 1 2 QL2 SSM3K7002FU_SC70-3~D 1 1 1U_0603_25V6-K~D 3 1 0.1U_0402_25V6K~D G QL1 SI3456DDV-T1-GE3_TSOP6~D 1000P_0402_50V7K~D 4 2 2 1 3 S close to Lan pin16 CL21 1 CL22 2 2 1 CL23 2 1 CL24 2 1 CL25 close to Lan pin22 1 CL26 2 1 2 3 4 5 6 7 8 9 10 11 12 LAN_MDIP3 LAN_MDIN3 LL2 BLM18AG601SN1D_2P LAN_MDIP2 LAN_MDIN2 LAN_MDIP1 LAN_MDIN1 LAN_MDIP0 LAN_MDIN0 TCT1 TD1+ TD1TCT2 TD2+ TD2TCT3 TD3+ TD3TCT4 TD4+ TD4- MCT1 MX1+ MX1MCT2 MX2+ MX2MCT3 MX3+ MX3MCT4 MX4+ MX4- RL22 1 2 75_0402_1% RL23 1 2 75_0402_1% RL24 1 2 75_0402_1% RL25 1 2 75_0402_1% RJ45_CT3 RJ45_MDI3+ RJ45_MDI3RJ45_CT2 RJ45_MDI2+ RJ45_MDI2RJ45_CT1 RJ45_MDI1+ RJ45_MDI1RJ45_CT0 RJ45_MDI0+ RJ45_MDI0- 24 23 22 21 20 19 18 17 16 15 14 13 LAN_LINK10# +LAN_IO LAN_LINK100# TAIMAG: SP050004Q10 BOTHHAND: SP050003T10 2 1 CL48 CL47 @ 1 2 2 close to Lan pin34 1 R1790 RL27 1 @ RL21 1 RL28 1 CL39 1000P_1808_3KV7K 2 510_0402_5% C1812 470P_0402_50V7K~D 2 12 RJ45_MDI3- 8 RJ45_MDI3+ 7 RJ45_MDI1- 6 RJ45_MDI2- 5 RJ45_MDI2+ 4 RJ45_MDI1+ 3 RJ45_MDI0- 2 RJ45_MDI0+ 1 2 120_0402_5%~D LAN_LINK10#_R 2 0_0402_5%~D +LAN_LED_VCC1 9 2 300_0402_5%~D LAN_LINK100#_R 11 1 CL30 2 10 Yellow LEDB Yellow LED+ PR4PR4+ PR2PR3PR3+ PR2+ PR1- SHLD2 PR1+ SHLD1 15 14 Green LEDLED+ ORANGE_LED- CIS link OK 10 Mbps: Green 100 Mbps: Orange 1000 Mbps: Yellow A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title GLAN AR8151 AL1A Size 3 2 Document Number Rev 0.1 LA-8321P Date: 4 1 CL29 close to Lan pin13 LAN_ACTIVITY#_R Dell LED spec: PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. close to TS1 5 2 1 CL28 TYCO_2041333-1~D CONN@ 0.1U_0402_25V6K~D 2 2 1000P_0402_50V7K~D 1 CL46 CL45 @ 1 0.1U_0402_25V6K~D 2 2 1000P_0402_50V7K~D 1 CL44 CL42 CL43 @ 1 0.1U_0402_25V6K~D 2 2 1000P_0402_50V7K~D 1 1 0.1U_0402_25V6K~D @ 1000P_0402_50V7K~D CL41 CL40 2 1U_0603_25V6-K~D close to LL2 2 1 CL27 1 2 1 close to Lan pin31 JLAN 350uH_GSL5009-1 LF A close to Lan pin24 close to Lan pin19 13 LAN_ACTIVITY# TS1 +VDDCT_L 1 2 close to Pin 1 2 2 close to Lan pin37 close to Lan pin6 1 +VDDCT 2 1 CL17 +AVDDL +LAN_IO S 6 5 2 1 1 EN_WOL D 2 1 CL16 W=20mils +AVDDH 2 2 G 2 1 CL15 C RL19 300K_0402_5%~D <40> EN_WOL# 2 1 CL14 W=20mils CL31 R1904 10K_0402_5%~D 2 1 CL13 close to Lan pin5 +3VALW B+_BIAS 1 CL12 AR8151-BL1A-R_QFN40_5X5 W=40mils +3VALW D W=20mils +RBIAS 1 RL16 2 2.37K_0402_1% CL19 18P_0402_50V8J~D CL20 1U_0402_6.3V6K~D 2 4.7K_0402_5%~D 0.1U_0402_25V6K~D 1 2 4.7K_0402_5%~D @ RL14 1 0.1U_0402_25V6K~D 4 CL18 @ RL13 1 CLKREQ_LAN#_R 0.1U_0402_25V6K~D C PCIE_WAKE# 0.1U_0402_25V6K~D GND 2 10 RBIAS 0.1U_0402_25V6K~D GND 1 1 LED_0 LED_1 LED_2 1U_0603_25V6-K~D 3 2 4.7K_0402_5%~D +DVDDL 1 +LAN_IO +LX 40 5 LX VDDCT 2 1 LAN_X2 3 @ RL11 1 W=40mils +DVDDL 24 37 DVDDL DVDDL_REG XTLO XTLI 38 39 23 RL26 5.1K_0402_1%~D 1 1 YL1 25MHZ_12PF_7V25000012 LAN_ACTIVITY# LAN_LINK10# LAN_LINK100# PLT_RST# LL1 2 RL17 0_0402_5%~D @ +LAN_IO 1000p reserved for EMI WAKE# 25 26 LAN_X1 LAN_X2_R 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 0.1U_0402_25V6K~D <18,35,40,43> REFCLK_P 1 1 1 1 1 1 1 1 1U_0603_25V6-K~D <5,16,19,35,40,43> 2 0_0402_5%~D 2 2 2 2 2 2 2 2 0.1U_0402_25V6K~D @ RL15 1 <17> LANCLK_REQ# RX_N RL4 RL1 RL5 RL2 RL6 RL8 RL9 RL10 0.1U_0402_25V6K~D D RX_P LAN_MDIP0 LAN_MDIN0 LAN_MDIP1 LAN_MDIN1 LAN_MDIP2 LAN_MDIN2 LAN_MDIP3 LAN_MDIN3 11 12 14 15 17 18 20 21 TRXP0 TRXN0 TRXP1 TRXN1 TRXP2 TRXN2 TRXP3 TRXN3 TX_N 0.1U_0402_25V6K~D 29 <17> PCIE_PRX_DTX_N1 Atheros AR8151-BL1A TX_P 0.1U_0402_25V6K~D PCIE_PRX_DTX_N1_C 1U_0603_25V6-K~D 2 1 0.1U_0402_25V6K~D CL7 0.1U_0402_25V6K~D 30 0.1U_0402_25V6K~D PCIE_PRX_DTX_P1_C 10U_0603_6.3V6M~D 1 0.1U_0402_25V6K~D 1000P_0402_50V7K~D 2 CL5 <17> PCIE_PRX_DTX_P1 Tuesday, January 17, 2012 Sheet 1 31 of 65 5 4 3 2 1 Reserve for pop noise +3.3V_MUTE +3VS @ RA26 +3.3V_AVDD U11 <33> <33> VSS_SW_1 VSS_SW_2 VSSQ_SW EAPD / MPIO0 AVSS PORTA_VSS PORTD_VSS 1 C122 100U_1206_6.3V6M 1 1 39 25 30 1 2 0_0402_5%~D @ R1883 1 2 0_0402_5%~D @ R2599 1 2 0_0402_5%~D C1845 1 2 0.1U_0603_50V7K~D C1846 1 2 0.1U_0603_50V7K~D +3.3V_AVDD +3.3V_AVDD +3VS 2 @ R1750 2 0_0805_5%~D 1 +3VS 2 C142 0.1U_0402_25V6K~D 1 2 C143 0.1U_0402_25V6K~D 1 2 C145 0.1U_0402_25V6K~D 1 2 C146 0.1U_0402_25V6K~D S1: PORTA Front L/R + HP1 1 G G 5 LINEIN_L 1 LINEIN_R 1 2 C11 LINEIN_L_R 2.2U_0805_25V6K~D LINEIN_R_R 2 C14 2.2U_0805_25V6K~D normal close type HP1_A_R_R RA21 1 2 0_0402_5%~D A3 B1 DEPOP# DEPOP# 2 HP1_A_L1_JK 2 HP1_A_R1_JK INL INR /MUTE +3.3V_MUTE VDD B3 SET C1872 0.1U_0402_16V4Z~D 1 Setting the Turn-Off Time: Ton (ms) = 0.02 x Cset (pF) @ D18 PJDLC05C_SOT23-3 A2 3 1 1 2 0_0402_5%~D LINEIN_L_L1 6 1 2 RA17 1 2 0_0402_5%~D LINEIN_R_L1 LINEIN_JD 3 4 U632 LINEIN_L_R RA31 1 2 0_0402_5%~D A1 LINEIN_R_R DEPOP# RA30 1 2 0_0402_5%~D A3 B1 S 1 1 HP1_JD D D S S 2 INR /MUTE +3.3V_MUTE B2 VDD SET C1874 0.1U_0402_16V4Z~D MAX9892ERT+T_UCSP6~D MAX9892ERT+T_UCSP6~D G Q288A DMN66D0LDW-7 Q288B DMN66D0LDW-7 1 C148 1 C149 BEEP_C# 0.1U_0402_16V4Z~D 1 R145 2 100K_0402_5%~D PCH_SPKR_C 0.1U_0402_16V4Z~D R144 2 1 100K_0402_5%~D 2 2 G G SPDIF 3 LINEIN_R_L1 01/03-92 2 LINEIN_L_L1 <40> SPDIF_DET# 5 Place close to Jack @ D16 PJDLC05C_SOT23-3 7 8 3 10 SPDIF_OUT 1 3 + + S D 2 2 SLEEVE L_MIC1 220U_B_4VM_R35M HP2_D_R1_R HP2_D_L1_R RA19 RA18 1 1 2 0_0402_5%~D 2 0_0402_5%~D 4 3 2 1 HP2_D_R1_JK HP2_D_L1_JK 2 JACK_PLUG# 5 1 2 2 0_0402_5%~D 2 0_0402_5%~D 2 C335 10U_0603_6.3V6M~D TS3A225ERTER_PWQFN16_3X3 1 A1 A3 B1 B3 INR /MUTE +3.3V_MUTE VDD SET C1871 0.1U_0402_16V4Z~D Setting the Turn-Off Time: Ton (ms) = 0.02 x Cset (pF) Combo JACK Mic. switch 1 1 B2 2 2 4 3 1 TYCO_1775792-1 normal open type 3 A 1 2 SPDIF_OUT D29 PJDLC05C_SOT23-3 @ Place close to Jack 3 HP2_D_L1_JK 2 HP2_D_R1_JK 1 Compal Electronics, Inc. Title CODEC Size 2 Document Number Rev 0.1 LA-8321P @ D17 PJDLC05C_SOT23-3 Date: 5 @ 7 8 normal open type INL 2 2 0_0402_5%~D 2 RA22 1 HP2_D_R1_R RA23 1 @ R1245 DEPOP# 1 GND SLEEVE HP2_D_L1_R A2 15 6 17 3 10 2 0_0402_5%~D HP2_D_L1_JK R1244 1 2 JACK_PLUG 0_0402_5%~D G SINGA_2SJ3062-000111F CONN@ 100P_0402_50V8J~D SLEEVE_SENSE SLEEVE GND GND GND 14 7 L_MIC1 100P_0402_50V8J~D R8 24.9K_0402_1% 12/22-88 MIC_PRESENT MIC_P MIC_N RA12 1 DET_TRI G G 6 C746 8 11 12 RING2_SENSE RING2 9 5 1K_0402_5%~D MIC_PRESENT# SCL SDA ADDR_SEL TIP_SENSE DET_TRIGGER MAX9892ERT+T_UCSP6~D 1K_0402_5%~D 1 2 4 VDD VDD U629 1 G 220U_B_4VM_R35M C745 UA3 13 16 1 100K_0402_5%~D RC115 2 1 C132 1 1 +3.3V_AVDD MIC1 1 HP2_D_R HP2_D_L +3.3V_AVDD C133 <44> VPK_SMB_CK1 <44> VPK_SMB_DA1 2 1 G S A @ 2 RC109 R3 3.3K_0402_5%~D 2 MICBIAS_C JACK_PLUG# CONN@ 2 2 C738 0.1U_0402_16V4Z~D 3 1 C744 100P_0402_50V8J~D 1 2 JSPDIF G 1 JHP2 Front R2653 D <33> SPDIF OUT JACK 9 6 1 4 JACK_PLUG QU8 2N7002E-T1-E3_SOT23-3 PC_BEEP B 01/17-100 QU6 PC_BEEP 7 8 +5VS AO3413_SOT23-3 PORRT:B R143 @ 10K_0402_5%~D normal close type Setting the Turn-Off Time: Ton (ms) = 0.02 x Cset (pF) S2: PORTD+C Ctr/LFE + HP2 + Mic* LINEIN_JD 5 G PORRT:A C TYCO_2041187-1~D INL B3 BEEP# <16> HDA_SPKR 5 B2 2 <40> JMIC CONN@ RA16 1 A1 GND 2 2 2 0_0402_5%~D 12/19-85 R2550 24.9K_0402_1% RA20 1 C1601 0.1U_0402_10V6K~D R2540 24.9K_0402_1% 1K_0402_5%~D 1K_0402_5%~D Place close to Jack HP1_A_L_R 1 2 U631 B QU4 +3.3V_AVDD PCBEEP 1 Front 7 8 TYCO_2041187-1~D 1 + + 3 4 3 QU7 AO3413_SOT23-3 3.3K_0402_5%~D RC114 RC107 RA15 MICBIAS_B R1727 2 1 <40> G D 10/22 G HP1_A_L1_JK 0_0402_5%~D HP1_A_R1_JK 2 0_0402_5%~D HP1_JD 1 RA14 01/17-100 2 D 1 JACK_PLUG PORRT:D C336 10U_0603_6.3V6M~D S HP1_A_R 2 C123 HP1_A_L_R 220U_B_4VM_R35M 2 C129 HP1_A_R_R 220U_B_4VM_R35M 2 01/06-95 01/09-96 01/11-98 6 1 2 Front 1 C147 0.1U_0402_25V6K~D 2 S3: PORTB Rear L/R + Line In + Mic JHP1 CONN@ HP1_A_L 1 1 1 +3.3V_AVDD R150 5.1K_0402_5% @ RA24 0_0402_5%~D 2 0.1U_0603_50V7K~D 1 MIC_PRESENT# 1 1 2 0.1U_0603_50V7K~D 2 C141 0.1U_0402_25V6K~D 2 0.1U_0603_50V7K~D 1 GND 1 1 C1870 C1844 2 2 C139 0.1U_0402_25V6K~D 1 C1873 A2 2 1 10K_0402_5%~D SENSE_A R1696 100K_0402_5%~D @ R1879 57 MALCOLM-EX_QFN56_7X7~D 2 R152 2 C152 0.1U_0402_25V6K~D +1.2VS 2 2 2 R1748 20K_0402_1%~D DVSS_1 DVSS_2 DVSS_3 DVSS_4 VSSQ_PLL 2 13 14 17 6 inveter schematics 40 2 VREF_FILT PCBEEP / MPIO5 3 R9 @ 5.11K_0402_1% 2 SPK_CD_L SPK_CD_R 2 1 SPDIF_OUT QA1A R146 100K_0402_5%~D 1 SPDIF IN / MPIO4 Thermal PAD R10 20K_0402_5%~D SPK_CD_L SPK_CD_R RA29 10K_0402_5%~D R147 39.2K_0402_1% 2 23 22 56 12/22-88 +3.3V_AVDD R149 100K_0402_5%~D 1 8 21 49 18 HP2_D_L HP2_D_R MIC1 2 2 52 33 31 35 32 1 3 EAPD# MIC1_R 5 4 53 0_0402_5%~D EAPD# C_MIC1_L C_MIC1_R 45 46 0.1U_0402_25V6K~D QA1B 1 2 C2042 12/08-75 2 <40> 1 15P_0402_50V8J~D 15P_0402_50V8J~D C 2 @ C347 @ C345 1 DET_TRI 1 @ R2585 SPDIF OUT0 / MPIO2 1 D +3.3V_AVDD RA28 100K_0402_5%~D 6 50 <30> I2S_DAT/SPDIF_IN PORTG_L PORTG_R DMIC_MCLK / MPIO1 DMIC_DATA0 / MPIO3 LINEIN_L LINEIN_R C12 47U_0805_6.3V6M~D 1 55 51 2 0_0402_5% +1.2VS 2 1 RA13 1 R1243 1 MIC_BIASB MIC_BIASC 44 43 12/13-80 +RTCVCC 2 2 0_0402_5% 01/09-97 <25> DMIC_CLK <25> DMIC0 PORTD_L PORTD_R PORTD_S PORTD_VCOM +3VALW 1 42 41 PORTC_L PORTC_R HP1_A_L HP1_A_R C151 0.1U_0402_25V6K~D 2N7002DW-7-F_SOT363-6 MICBIAS_B MICBIAS_C SENSE_A SENSE_B SENSE_I 2 4.7UH_CBC2012T4R7M_20%~D 28 26 24 27 1 2N7002E-T1-E3_SOT23-3 1 R268 +3.3V_AVDD 2 0_0402_5%~D SLEEVE 2 C150 0.1U_0402_25V6K~D 1 47 37 2 10K_0402_5%~D 36 PORTB_L PORTB_R 2 0_0402_5%~D 1 2 SENSE_A HDA_BCLK HDA_SDI HDA_SDO HDA_SYNC HDA_RSTN 1 1 HDA_SDIN0_AUDIO 33_0402_5%~D 2 C334 10U_0603_6.3V6M~D 3 2 L3 1 12 VDDQ_PLL PORTA_L PORTA_R PORTA_S PORTA_VCOM 2 4 1 R251 5 7 4 3 2 SWOUT 1 10 11 16 1 HDA_BITCLK_AUDIO HDA_SDIN0 HDA_SDOUT_AUDIO HDA_SYNC_AUDIO HDA_RST_AUDIO# VDD_SW_1 VDD_SW_2 VDDQ_SW DVDD_IO DVDD_HDAIO 2N7002DW-7-F_SOT363-6 19 FBDC 1 <16> <16> <16> <16> <16> 54 6 2 D 2 0_0402_5%~D 1 0_0402_5% 2 0_0402_5%~D 1 2 1 1 15 @ R1745 @ R1746 @ R1751 +3VS +1.5VS +3VS 1 RA27 38 29 34 2 EAPD# AVDD PORTA_VDD PORTD_VDD 2 2 20K_0402_1%~D DVDD_1 DVDD_2 DVDD_3 @ RA25 1 0.1U_0402_25V6K~D 2 1 R1217 1 9 20 48 @ C2041 2 +3VS 2 0_0402_5%~D 1 1 +1.2VS Tuesday, January 17, 2012 Sheet 1 32 of 65 4 3 2 SS1040_SOD123-2 C2035 1 1 2 2 C901 22U_1210_25V6K~D 1 + SS1040_SOD123-2 2 10U_0805_25V6K~D 2 1 1 2 C902 22U_1210_25V6K~D 1 1 C903 22U_1210_25V6K~D 1 C904 0.1U_0603_50V7K~D 2 1 1 R939 2 1 2 5 182K_0402_1%~D C917 1 R935 R930 SPK_CD_L4 2 6 20.5K_0402_1%~D PC_BEEP_2 2 0.1U_0402_25V6K~D 182K_0402_1%~D 1 each one is 4 ohm/2.5W 2 AMP_SPK_JK_LAMP_SPK_JK_L+ AMP_SPK_JK_RAMP_SPK_JK_R+ AMP_SPKL+_L AMP_SPK_JK_L+ 1 2 22UH_LQH55PN220MR0L_0.85A_20%~D 2 1 1 2 3 4 C918 330P_0402_50V7K~D 1 R938 2 19 182K_0402_1%~D SPK_CD_R4 18 7 8 17 FB_R IN_R 2 EC_MUTE# SPK_AMP_MUTE_R# 10 11 9 OUTR+1 OUTR+2 25 26 L69 BLM18PG181SN1_0603~D AMP_SPKR+ 1 2 2 G5 G6 5 6 D L86 AMP_SPKR+_R AMP_SPK_JK_R+ 1 2 22UH_LQH55PN220MR0L_0.85A_20%~D 1 SHDN# REGEN MUTE# 1 2 3 4 MOLEX_53398-0471~D CONN@ 2SPK_CD_R2_FBL 1 0.022U_0402_25V7K~D 2 17.8K_0402_1%~D R934 R927 JSPK L85 R924 1 1 NC1 NC2 NC3 16.2K_0402_1%~D C916 2200P_0402_50V7K~D C930 1 2 SPK_CD_R3 1 2 SPK_CD_R1 1U_0603_25V6-K~D AMP_SPKL+ 1 2 IN_L 2 R929 31 32 FB_L 0.022U_0402_25V7K~D 17.8K_0402_1%~D 182K_0402_1%~D 2 1 OUTL+1 OUTL+2 R926 SPK Board CONN C931 330P_0402_50V7K~D 1 PC_BEEP_1 0.1U_0402_25V6K~D C922 1 PGND2 PGND1 2 SPK_CD_R2 PC_BEEP 28 29 20.5K_0402_1%~D 2 SPK_CD_R 1 C929 AMP_SPK_JK_L- 2 @ D22 PJSOT24CH_SOT23-3 1 C919 2200P_0402_50V7K~D 1 2 SPK_CD_L3 1 <32> SPK_CD_R 1 @ D21 PJSOT24CH_SOT23-3 SPK_CD_L1 2 1U_0603_25V6-K~D PC_BEEP 1 C920 AMP_SPKL- 2 SPKER_CD_L2_FBL 2 16.2K_0402_1%~D <32> PC_BEEP 1 2 C905 0.1U_0603_50V7K~D R928 SPK_CD_L2 D SPK_CD_L 1 C921 OUTL-1 OUTL-2 L68 BLM18PG181SN1_0603~D @ <32> SPK_CD_L 2 PVDD1 PVDD2 2 1 CAP 220U 25V 2 C2036 3 D75 1 27 30 +AMP_VDD D74 1 L67 BLM18PG181SN1_0603~D 3 B+ 2 U21 +AMP_VDD 2 5 C925 330P_0402_50V7K~D +3VS For filterless modualation/spread-spectrum mode @ R940 1 20 2 0_0402_5%~D High Pass Filter with -3dB = 500Hz pass band gain = 16dB Mono Select. Set MONO high for mono mode. 4 16 D59 1 2 1 2 R1567 200_0402_1% C1553 2.2U_0603_10V7K~D 1 15 12 21 1 2 1 2 1 2 1U_0603_25V6-K~D 1 SPK_AMP_MUTE_R# 1U_0603_25V6-K~D C926 <40> EC_MUTE# Internal Regulator Output. Internal 2V Bias. 2 SDMK0340L-7-F_SOD323-2~D C923 EC_MUTE# 1U_0603_25V6-K~D C927 C MONO OUTR-1 OUTR-2 23 24 AMP_SPKR- VS REG COM C1N 1 2 22 13 14 3 2 EP 33 C1P AGND AGND 2 C1089 22U_1210_25V6K~D 1 2 C1090 22U_1210_25V6K~D 1 1 C1091 22U_1210_25V6K~D 2 1 C1092 0.1U_0603_50V7K~D 2 PVDD1 PVDD2 OUTL-1 OUTL-2 1 2 AMP_SW- 1 1 C1093 0.1U_0603_50V7K~D R1195 C1096 2 2 OUTL+1 OUTL+2 14K_0402_1%~D 1U_0603_25V6-K~D SUB_FB_L3 0.1U_0402_25V6K~D 2 1 1 2 R1196 5 100K_0402_1%~D 6 R1197 20K_0402_1%~D SPK_CD_L C1098 1 C1100 SUB_CD_R 0.47U_0603_10V7K~D 1 2 SUB_CD_L 0.47U_0603_10V7K~D 1 2 2 R1201 9.09K_0402_1%~D 1 1 R1198 1 C1099 15.8K_0402_1%~D 2 19 0.01U_0402_16V7K~D SUB_IN_R 18 EC_MUTE# SUB_AMP_MUTE_R# 10 11 9 @ R2520 1 2 0_0402_5%~D 4 @ D60 2 0_0402_5% 2 SUB_AMP_MUTE_R# @ C1558 2.2U_0603_10V7K~D 1 1 2 1 2 1 2 C1106 1U_0603_25V6-K~D 2 C1105 1U_0603_25V6-K~D R1568 1 15 12 21 C1104 1U_0603_25V6-K~D 1 20 16 Internal Regulator Output. Internal 2V Bias. SDMK0340L-7-F_SOD323-2~D 1 2 22UH_LQH55PN220MR0L_0.85A_20%~D 1 C1094 330P_0402_50V7K~D G G MOLEX_53398-0271~D CONN@ CIS link OK B 7 8 17 FB_R IN_R OUTR+1 OUTR+2 25 26 AMP_SW+ 23 24 AMP_SW- 3 2 SHDN# REGEN MUTE# +3VS Band Pass Filter at 80Hz to 500Hz pass band gain = 16dB EC_MUTE# L96 AMP_SW_JK+ 2 1 2 SUB_FB_L 2 SUB_CD_R2 2 C1101 0.1U_0402_25V6K~D For filterless modualation/spread-spectrum mode A 3 4 6.49K_0402_1%~D R1200 SUB_CD_R1 2 2 1 BLM18PG181SN1_0603~D 2 IN_L 1 <32> SPK_CD_L 1 AMP_SW+ FB_L NC1 NC2 NC3 1 R1199 9.09K_0402_1%~D SPK_CD_R JWFER 0.047U_0402_16V7K~D SUB_IN_L <32> SPK_CD_R 31 32 SUB WOOFER amp 4 ohm/5W 1 2 L88 SUB_FB_L4 2 2 C1088 330P_0402_50V7K~D PGND2 PGND1 C1097 1 2 1 1 22UH_LQH55PN220MR0L_0.85A_20%~D 1 2 28 29 11.5K_0402_1% SUB_FB_L1 2 AMP_SW_JK- 2 BLM18PG181SN1_0603~D R1194 C1095 L95 L87 SUB_FB_L2 1 C 1U_0603_25V6-K~D U16 2 SUB_FB_L 2 1 C928 330P_0402_50V7K~D MAX9736AETJ+T_TQFN32_7X7 27 30 B 1 C932 BOOT AMP_SPK_JK_R- 2 +AMP_VDD C924 0.1U_0603_50V7K~D +AMP_VDD 1 L70 BLM18PG181SN1_0603~D MODE 1 2 MODE MONO OUTR-1 OUTR-2 +AMP_VDD VS REG COM C1N C1102 BOOT 1 1U_0603_25V6-K~D EP 33 A C1103 0.1U_0603_50V7K~D 22 13 14 C1P AGND AGND Compal Electronics, Inc. Title MAX9736AETJ+T_TQFN32_7X7 Sub woofer / Speaker AMP Size Document Number Rev 0.1 LA-8321P Date: 5 4 3 2 Tuesday, January 17, 2012 Sheet 1 33 of 65 SATA_PTX_DRX_N5_C SATA_PTX_DRX_P5_C 11 9 INT 1 INT 2 7 6 4 PCH_SMBDATA PCH_SMBCLK GND GND SDO/SA0 SDA / SDI / SDO SCL/SPC NC CS NC 8 <19> ODD_DA# <16,20> ODD_DETECT# 5 12 <16> SATA_PRX_DTX_P2 <16> SATA_PRX_DTX_N2 2 3 <16> SATA_PTX_DRX_N2 <16> SATA_PTX_DRX_P2 ACES_50406-02071-001 CONN@ +5VS 2 2 2 2 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D SATA_PTX_DRX_P0_CO SATA_PTX_DRX_N0_CO SATA_PRX_DTX_N0_CO SATA_PRX_DTX_P0_CO @ CS69 @ CS70 @ CS71 @ CS72 1 1 1 1 2 2 2 2 2 PAD~D T212 @ ODD_DA#_R ODD_DETECT#_R 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D SATA_PTX_DRX_P0_C SATA_PTX_DRX_N0_C SATA_PRX_DTX_N0_C SATA_PRX_DTX_P0_C FFS_INT2 CS27 1U_0402_6.3V6K~D @ R343 100K_0402_5% 3 1 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P2_C 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N2_C CS15 1 CS14 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N2_C 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P2_C +5VS_ODD 6 5 2 1 1 2 B+_BIAS FFS_INT2_CONN ODD_DA#_R RS7 300K_0402_5%~D 12/08-77 <20> ODD_EN# +3VS +3VS 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D <16> SATA_PTX_DRX_P0 <16> SATA_PTX_DRX_N0 <16> SATA_PRX_DTX_N0 <16> SATA_PRX_DTX_P0 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P0_R SATA_PTX_DRX_N0_R 1 2 CS55 1 CS56 1 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N0_RC SATA_PRX_DTX_P0_RC 4 5 SATA_PTX_DRX_P0_RC SATA_PTX_DRX_N0_RC 11 12 SATA_PRX_DTX_P0_R SATA_PRX_DTX_N0_R 2 2 1 MAX4951CCTPLFT_TQFN20_4X4~D EN 3 CAD STATUS 0 0 LowPower 1 1 LowPower 1 0 Active 1 1 LowPower 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 SATA HDD Conn. SATA_PTX_DRX_P0_RC SATA_PTX_DRX_N0_RC CS6 CS7 1 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P0_C 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N0_C SATA_PRX_DTX_N0_R SATA_PRX_DTX_P0_R CS8 CS9 <16> SATA_PRX_DTX_P3 <16> SATA_PRX_DTX_N3 <16> SATA_PTX_DRX_N3 <16> SATA_PTX_DRX_P3 1 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N0_C 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P0_C CS18 1 CS29 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P3_C 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N3_C CS31 1 CS30 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N3_C 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P3_C JHDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 +3VS FFS_INT2_CONN @ R1653 1 2 0_0402_5%~D <20> HDD2_DETECT# +3VS +3VS FFS_INT2_CONN_R HDD2_DETECT# SATA_PTX_DRX_P1_RC SATA_PTX_DRX_N1_RC CS23 1 CS24 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P1_C 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N1_C SATA_PRX_DTX_N1_R SATA_PRX_DTX_P1_R CS25 1 CS26 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N1_C 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P1_C US3 4 1 1 1 1 1 1 @ RS35 1 RS36 1 RS37 1 2 2 2 2 2 2 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 2 0_0402_5%~D 2 0_0402_5%~D 2 0_0402_5%~D COLAY_HDD1_REXT SATA_HDD1_ENABLE SATA_HDD1_PA SATA_HDD1_PB SATA_HDD1_OOB_TEST SATA_HDD1_PIN17 <16> SATA_PTX_DRX_P1 <16> SATA_PTX_DRX_N1 <16> SATA_PRX_DTX_N1 <16> SATA_PRX_DTX_P1 CS63 1 CS65 1 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P1_R SATA_PTX_DRX_N1_R 1 2 CS67 1 CS68 1 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N1_RC SATA_PRX_DTX_P1_RC 4 5 COLAY_HDD1_REXT SATA_HDD1_CAB_DET SATA_HDD1_PIN17 SATA_HDD1_PIN17 3 13 17 21 EN DD OL HAP HAM HBM HBP GND GND GND EP VCC VCC VCC VCC PA PB DAP DAM DBP DBM 6 10 16 20 COLAY_HDD1_REXT 9 8 SATA_HDD1_PA SATA_HDD1_PB 15 14 SATA_PTX_DRX_P1_RC SATA_PTX_DRX_N1_RC 11 12 SATA_PRX_DTX_P1_R SATA_PRX_DTX_N1_R 1 2 1 2 CS66 0.1U_0402_16V4Z~D RS29 RS30 RS31 RS32 @ RS33 @ RS34 7 18 19 CS64 0.01U_0402_16V7K~D SATA_HDD1_ENABLE SATA_HDD1_CAB_DET SATA_HDD1_OOB_TEST +3VS 2 QU3 2N7002E-T1-E3_SOT23-3 +5VS Close to pin 6, 10 or pin 16, 20 CS19 1000P_0402_50V7K~D SATA_HDD0_PA SATA_HDD0_PB 15 14 1 CS2 1000P_0402_50V7K~D DBP DBM 9 8 1 S G RS50 100K_0402_5%~D CS20 0.1U_0402_25V6K~D GND GND GND EP PA PB DAP DAM COLAY_HDD0_REXT 2 CS3 0.1U_0402_25V6K~D 3 13 17 21 HBM HBP 6 10 16 20 1 CS22 1U_0402_6.3V6K~D HDD Redriver SATA_HDD0_PIN17 HAP HAM VCC VCC VCC VCC CS28 CS4 1U_0402_6.3V6K~D COLAY_HDD0_REXT SATA_HDD0_CAB_DET SATA_HDD0_PIN17 CS54 1 CS51 1 EN DD OL CS21 10U_0805_25V6K~D 2 0_0402_5%~D 2 0_0402_5%~D 2 0_0402_5%~D COLAY_HDD0_REXT SATA_HDD0_ENABLE SATA_HDD0_PA SATA_HDD0_PB SATA_HDD0_OOB_TEST SATA_HDD0_PIN17 S CS5 10U_0805_25V6K~D @ RS17 1 RS18 1 RS19 1 2 2 2 2 2 2 RS8 G CS52 0.1U_0402_16V4Z~D 1 1 1 1 1 1 CS53 0.01U_0402_16V7K~D RS11 RS12 RS13 RS14 @ RS15 @ RS16 7 18 19 2 QS2 SSM3K7002FU_SC70-3~D US1 SATA_HDD0_ENABLE SATA_HDD0_CAB_DET SATA_HDD0_OOB_TEST +3VS D D 2 <40> ODD_EJEECT# 1 SATA_PTX_DRX_P1_C SATA_PTX_DRX_N1_C SATA_PRX_DTX_N1_C SATA_PRX_DTX_P1_C 2 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D 0.1U_0402_25V6K~D 2 2 2 2 1.5M_0402_5%~D 1 1 1 1 2 @ CS77 @ CS78 @ CS79 @ CS80 1 SATA_PTX_DRX_P1_CO SATA_PTX_DRX_N1_CO SATA_PRX_DTX_N1_CO SATA_PRX_DTX_P1_CO 1 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 3 2 2 2 2 GND GND QS1 SI3456DDV-T1-GE3_TSOP6~D ODD_EN 1 1 1 1 1 TYCO_1-2041070-6~D CONN@ 12/13-78 2 D12 SDMK0340L-7-F_SOD323-2~D 2 @ RS46 @ RS47 @ RS48 @ RS49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 2 D S Q118 SSM3K7002FU_SC70-3~D SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 JODD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T212NET CS17 1 CS16 1 +5VS 2 1 1 1 1 1 D +3VS 2 @ RS38 @ RS39 @ RS40 @ RS41 2 0_0402_5%~D 2 0_0402_5%~D 2 LNG3DMTR_LGA16_3X3~D G SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 @ RS10 1 @ RS9 1 1 S 2 VDD_IO VDD ODD_DETECT# : High Active 10 13 15 16 1 2 1 CS35 0.1U_0402_25V6K~D 2 1 CS34 1U_0402_6.3V6K~D 1 CS33 0.1U_0402_25V6K~D 2 CS32 1U_0402_6.3V6K~D 1 +3VS FFS_INT1 FFS_INT2 <19> FFS_INT1 <20> FFS_INT2 RES RES RES RES G +1.5VS LNG3DM 1 14 2 3 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D 1 1 U41 1 CS13 10U_0805_25V6K~D CS49 CS48 <16> SATA_PTX_DRX_N5 <16> SATA_PTX_DRX_P5 SATA_PRX_DTX_P5_C SATA_PRX_DTX_N5_C 2 +5VS_ODD CS12 1U_0402_6.3V6K~D <16> SATA_PRX_DTX_P5 <16> SATA_PRX_DTX_N5 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D 1 1 1 CS11 0.1U_0402_25V6K~D CS50 CS47 2 SATA ODD Conn. CS10 1000P_0402_50V7K~D 1 2 C821 PCH_SMBCLK PCH_SMBDATA PCH_SMBCLK PCH_SMBDATA 1 10U_0805_25V6K~D <5,10,11,12,13,16,17,35,43> <5,10,11,12,13,16,17,35,43> 1 C820 +3VS 0.1U_0402_25V6K~D <17> mSATA_DET# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 G1 G2 G3 G4 E Free Fall Sensor +3VS JP2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 +1.5VS D 1 mSATA CONN C 1 B 3 A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 3 G1 G2 G3 G4 31 32 33 34 ACES_50554-03001-001 CONN@ 4 Close to pin 6, 10 or pin 16, 20 DELL CONFIDENTIAL/PROPRIETARY MAX4951CCTPLFT_TQFN20_4X4~D Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. SATA HDD & ODD & FFS Size B C Rev 0.1 LA-8321P Date: A Document Number D Tuesday, January 17, 2012 Sheet E 34 of 65 A B C +1.5VS_WLAN 2 1 2 CE19 0.1U_0402_25V6K~D 2 1 CE15 0.1U_0402_25V6K~D 2 1 CE14 4.7U_0603_10V6K~D 2 1 PJP23 1 1 JWLAN 1 <18,31,40,43> PCIE_WAKE# COEX2 COEX1 PCIE_WAKE# @ RE19 @RE19 @RE442 @ RE442 @RE441 @ RE441 2 0_0402_5% 2 0_0402_5%~D 2 0_0402_5%~D 1 3 5 7 9 11 13 15 2 0_0402_5%~D 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 EC_TX_DAT 49 EC_RX_CLK 51 1 1 1 <17> MINI1CLK_REQ# <17> CLK_PCIE_MINI3# <17> CLK_PCIE_MINI3 @ RE37 1 <5,16,19,31,40,43> PLT_RST# <19> CLK_DEBUG <17> PCIE_PRX_DTX_N3 <17> PCIE_PRX_DTX_P3 <17> PCIE_PTX_DRX_N3 <17> PCIE_PTX_DRX_P3 +3VS_WLAN @ RE41 1 RE42 1 <40> E51TXD_P80DATA <40> E51RXD_P80CLK 2 0_0402_5%~D 2 0_0402_5%~D 53 BT_RADIO_DIS# RE43 1 2 1K_0402_5%~D 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND1 RE17 1 +1.5VS_WLAN LPC_LFRAME#_C LPC_AD3_C LPC_AD2_C LPC_AD1_C LPC_AD0_C @ RE36 @RE36 @RE32 @ RE32 @RE33 @ RE33 @RE34 @ RE34 @RE35 @ RE35 2 0_1206_5% 1 1 1 1 1 2 2 2 2 2 +3VS 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D WL_OFF# PLT_RST# @RE27 @ RE27 1 2 0_0402_5%~D 2 2 +1.5VS 1 JUMP_43X118 LPC_FRAME# <16,40> LPC_AD3 <16,40> LPC_AD2 <16,40> LPC_AD1 <16,40> LPC_AD0 <16,40> WL_OFF# PLT_RST# +3VS_WLAN <19> <5,16,19,31,40,43> PCH_SMBCLK <5,10,11,12,13,16,17,34,43> PCH_SMBDATA <5,10,11,12,13,16,17,34,43> USB20_N4 USB20_P4 <19> <19> 54 GND2 MOLEX_48338-1088~D CONN@ 0823 (U) match the conn list 1 01/03-91 01/16-99 2 R1697 100K_0402_5% 2 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 +3VS_WLAN E +3VS_WLAN CE18 0.1U_0402_25V6K~D 2 1 CE17 0.1U_0402_25V6K~D Wireless LAN CE16 4.7U_0603_10V6K~D 1 D BlueTooth Display Mini Card 1 1 L98 +1.5VS BLM18AG601SN1D_2P 3 BLM18PG330SN1D_2P~D 2 <19> BT_ON# BT_ON# 1 RU6 2 1 R944 @R1875 @ R1875 1 <17> DMC_PCH_DET# <29> DP_DMC_AUXN <29> DP_DMC_AUXP 2 0_0402_5%~D DMC_DET# 53 55 57 59 61 63 65 67 69 71 73 75 <29> DP_DMC_ML2N <29> DP_DMC_ML2P <29> DP_DMC_ML0N <29> DP_DMC_ML0P 77 10K_0402_5%~D CU15 0.1U_0402_25V6K~D 1U_0603_25V6-K~D W=40mils M/B signal Pin +3VS_BT 53 55 57 59 61 63 65 67 69 71 73 75 GND1 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 GND2 54 56 58 60 62 64 66 68 70 72 74 76 DMC_RADIO_OFF# PLT_RST# DMC_RADIO_OFF# CU16 4.7U_0603_10V6K~D <19> 2 CU17 0.1U_0402_25V6K~D D S QU2 2N7002E-T1-E3_SOT23-3 2 USB20_N5 USB20_P5 G <19> <19> 3 +3VS_BT 1 2 R943 1M_0402_5%~D 1 DP_DMC_HPD DP_DMC_ML3N DP_DMC_ML3P <29> <29> DP_DMC_ML1N DP_DMC_ML1P <29> <29> C1703 0.1U_0402_25V6K~D <29> <17> BT_DET# DMC ( HDMI ) <20> BT_RADIO_DIS# 2 JBT 1 2 3 4 5 6 7 8 9 10 11 12 COEX1 BT_RADIO_DIS# COEX2 <19> USB20_N8 <19> USB20_P8 78 13 14 LOTES_AAA-PCI-112-K01 CONN@ DMC Module B0 Ver. Signal RU8 300_0603_5% 2 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 1 DMC_CKN DMC_CKP 1 DDP 1P DDP 1N TMDS DATA 1 TMDS DATA 1# DP_DMC_ML2N DP_DMC_ML2P 63 65 DMC_D0N DMC_D0P 2 DDP 2P DDP 2N TMDS DATA 0 TMDS DATA 0# DP_DMC_ML1N DP_DMC_ML1P 68 70 DMC_D1N DMC_D1P DDP 3P DDP 3N TMDS CLK TMDS CLK# DP_DMC_ML0N DP_DMC_ML0P 71 73 DMC_D2N DMC_D2P DDP AUXP DDP AUXN HDMI_CTRL_CLK HDMI_CTRL_DAT DP_DMC_AUXN DP_DMC_AUXP 55 57 DMC_DDC_DAT DMC_DDC_CLK @ C1342 60 62 1 2 1 2 3 4 5 6 7 8 9 10 11 12 GND GND AMPHE_G846A12211EU CONN@ 100P_0402_50V8J~D DP_DMC_ML3N DP_DMC_ML3P R1407 10K_0402_5%~D TMDS DATA 2 TMDS DATA 2# C1704 33P_0402_50V8J~D DDP 0P DDP 0N A 2 QU1 AO3413_SOT23-3 2 1 L97 +1.5VS_DMC +3VS 1 1M_0402_5%~D +3VS_DMC <29> DMC_DISP_CAB_DET 4 1 1 01/04-93 2 HDMI usage 2 1 <17> PCIE_PRX_DTX_N2 <17> PCIE_PRX_DTX_P2 3 PCH DP Port +3VS_DMC 3 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 <17> PCIE_PTX_DRX_N2 <17> PCIE_PTX_DRX_P2 DMC ( HDMI ) 2 4 6 8 10 12 14 16 2 2 <17> CLK_PCIE_MINI2# <17> CLK_PCIE_MINI2 2 4 6 8 10 12 14 16 G 2 1 CE24 0.1U_0402_25V6K~D 2 1 CE23 0.1U_0402_25V6K~D 1 CE22 4.7U_0603_10V6K~D 2 CE21 0.1U_0402_25V6K~D CE20 4.7U_0603_10V6K~D 2 1 1 3 5 7 9 11 13 15 D <17> MINI2CLK_REQ# 1 CU12 JDMC 1 3 5 7 9 11 13 15 +1.5VS_DMC S +3VS_DMC +3VS 4 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B C D Title Mini Card - WLAN/ BT/DMC Size Document Number Date: Tuesday, January 17, 2012 Rev 0.1 LA-8321P Sheet E 35 of 65 5 4 3 2 1 please close to JUSB 2.0A +5VALW +5V_USB2_A @ R620 1 2 0_0402_5%~D U42 1 2 3 4 <40,43> USB_PWR_EN# GND IN EN1# EN2# OC1# OUT1 OUT2 OC2# 8 7 6 5 USB_OC2# <16,19> 10U_1206_16V4Z~D C1584 D 1 C1585 2 1 2 4 <19> USB20_P2 1 0.1U_0402_16V4Z~D TPS2062ADR_SO8~D <19> USB20_N2 3 1 L50 2 3 2 USB20_N2_CONN D28 USB3RN3_RC USB3RP3_RC USB3TN3_RC USB3TP3_RC USB20_P2_CONN 1 2 3 4 RR+ TT+ 8 7 6 5 VCC GND DD+ USB20_N2_CONN USB20_P2_CONN LXES4XBAA6-027_MSOP8 @ R619 1 2 0_0402_5%~D @ R622 1 2 0_0402_5%~D D 2.0A +5V_USB2_B U45 1 2 3 4 GND IN EN1# EN2# OC1# OUT1 OUT2 OC2# 8 7 6 5 USB_OC3# <19> USB20_N3 4 <19> USB20_P3 1 <16,19> 4 3 1 L51 2 +5V_USB2_B For ESD request WCM2012F2S-900T04_0805 +5VALW <40,43> USB_PWR_EN# 4 +5V_USB2_A For ESD request WCM2012F2S-900T04_0805 3 USB20_N3_CONN 2 USB20_P3_CONN D30 USB3RN4_RC USB3RP4_RC USB3TN4_RC USB3TP4_RC 1 2 3 4 RR+ TT+ VCC GND DD+ 8 7 6 5 USB20_N3_CONN USB20_P3_CONN LXES4XBAA6-027_MSOP8 @ R621 1 2 0_0402_5%~D 10U_1206_16V4Z~D 1 2 C1587 1 2 0.1U_0402_16V4Z~D TPS2062ADR_SO8~D C1586 +5V_USB2_A 2 0_0402_5%~D L46 <19> USB3TP3 C1599 1 2 0.1U_0402_10V6K~D USB3TP3_C 1 <19> USB3TN3 C1600 1 2 0.1U_0402_10V6K~D USB3TN3_C 4 1 2 4 3 2 USB3TP3_RC 3 USB3TN3_RC 150U_D_10VM_R40M @ R623 1 1 C1583 + 2 0.1U_0402_16V4Z~D 2.0A C 1 C1582 2 USB3RN3_RC USB3RP3_RC 2 0_0402_5%~D USB3TN3_RC USB3TP3_RC 2 0_0402_5%~D L47 USB3RP3 <19> USB3RN3 1 4 1 2 4 3 2 USB3RP3_RC 3 USB3RN3_RC DLW21SN900HQ2L_0805_4P~D @ R627 1 2 0_0402_5%~D B @ R628 1 2 0_0402_5%~D <19> USB3TP4 USB3TN4 C1604 1 C1603 1 2 0.1U_0402_10V6K~D USB3TP4_C 2 0.1U_0402_10V6K~D USB3TN4_C 1 4 1 4 2 3 2 3 C1589 + 2 2 0_0402_5%~D @ R630 1 2 0_0402_5%~D For customer request @ R1654 2 0_0603_5%~D 1 @ R1574 1 GND_Frame 1 C804 JAE_PC2RN1SU41A17J6R350-DT~D CONN@ GND GND 2 0_0603_5%~D 2 0.1U_0402_25V6K~D 10 11 1 C1588 2 USB3TP4_RC USB20_N3_CONN USB20_P3_CONN USB3TN4_RC USB3RN4_RC USB3RP4_RC USB3TN4_RC USB3TP4_RC DLW21SN900HQ2L_0805_4P~D @ R629 1 VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+ 2.0A 1 L48 <19> 1 2 3 4 5 6 7 8 9 +5V_USB2_B 150U_D_10VM_R40M <19> 0.1U_0402_16V4Z~D @ R626 1 USB CONN JUSB3 USB20_N2_CONN USB20_P2_CONN DLW21SN900HQ2L_0805_4P~D @ R625 1 C B JUSB4 1 2 3 4 5 6 7 8 9 VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+ For customer request @ R1562 2 0_0603_5%~D 1 @ R1566 1 GND_Frame 1 C801 JAE_PC2RN1SU41A17J6R350-DT~D CONN@ GND GND 2 0_0603_5%~D 2 0.1U_0402_25V6K~D 10 11 L49 <19> USB3RP4 <19> USB3RN4 1 4 1 2 4 3 2 USB3RP4_RC 3 USB3RN4_RC DLW21SN900HQ2L_0805_4P~D @ R631 1 2 0_0402_5%~D A A Compal Electronics, Inc. Title USB 3.0 *2 Size Document Number Date: Tuesday, January 17, 2012 Rev 0.1 LA-8321P 5 4 3 2 Sheet 1 36 of 65 5 4 3 2 +3.3V_F347 +3.3V_F347 1 2 2 +3.3V_F347_R C1707 C1706 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 1 2 2 1 C1708 22P_0402_50V8J~D 1 1 2 0_0402_5%~D 1 1 @ R1569 C1705 1U_0603_25V6-K~D 1 R1570 4.7K_0402_5%~D R1571 4.7K_0402_5%~D U602 6 +5VALW +5VS @ R1572 0_0603_5% 2 <19> <19> 1 1 W=40mils 2 @ R1575 0_0402_5%~D C1711 1U_0603_25V6-K~D 1 2 2 4 5 2 REGIN VBUS 9 10 R1577 1K_0402_1% RST#/C2CK P3.0/C2D 18 17 16 15 14 13 12 11 C1712 0.1U_0402_25V6K~D P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 D+ D- 7 8 +3.3V_F347 1 +3.3V_F347 1 USB20_P6 USB20_N6 USB20_P6 USB20_N6 VDD P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 2 1 32 31 30 29 28 27 SPI_MOCLK 1 SPI_MOSO @ R1564 SPI_MOSI SPI_MOCS# I2C_DAT I2C_CLK C1710 @ 1 2 26 25 24 23 22 21 20 19 SLP_S3 BATT_CHG_LED ACIN# LID_SW_IN_D# BATT_LOW_LED SLP_S5 C1713 @ 1 2 C1714 @ 1 2 2 D 2 place R1564 as close as U602 D 2 SPI_MOCLK_R 0_0402_5%~D I2C_DAT I2C_CLK 0.1U_0402_25V6K~D R1576 2 1 +3.3V_F347 R1841 +3.3V_F347 <38,39> <38,39> 1K_0402_5% 2 10K_0402_5%~D 1 2 1 LID_SW_IN# <17,38,40> D70 SDMK0340L-7-F_SOD323-2~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 3 GND C8051F347-GQ_LQFP32_7X7 @ C1721 @ C1717 @ C1722 @ C1718 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 2 @ C1716 7 8 AMPHE_G846A06211EU~D 1 0.1U_0402_25V6K~D C1730 1U_0402_6.3V6K~D @ C1720 S S S S IC IC IC IC C8051F347-GQ C8051F347-GQ C8051F347-GQ C8051F347-GQ LQFP LQFP LQFP LQFP 32P 32P 32P 32P MCU MCU MCU MCU for for for for PALB0 PAR00 PAR10 PAP00 (Specter) blue (Voyager) green (Avenger) white (Phantom MLK) silver 2 1 R1584 5 SPI_MOCLK_R 15_0402_5% 2 1 R1583 6 10K_0402_5%~D 1 2 R1580 SPI_MOCS# 1 10K_0402_5%~D 1 2 R1581 7 10K_0402_5%~D 1 2 R1582 3 8 +3.3V_F347 1 Q210 <18,40> PM_SLP_S5# 2N7002E-T1-E3_SOT23-3 1 2 S 1 C1724 22P_0402_50V8J~D 2 D S Q211 2N7002E-T1-E3_SOT23-3 DI SO 2 +3.3V_F347 2 +3.3V_F347 1 1 1 HOLD WP VCC VSS 4 EN25F80-75HCP_SO8 SA00001V400 (S IC FL 8M EN25F80-75HCP SOIC 8P) 《EON》 SA00003EW00 (S IC FL 8M W25Q80BVSSIG SOIC 8P) 《WINBOND》 SA000041O00 (S IC FL 8M MX25L8006EM2I-12G SOP 8P 3V) 《MXIC》 S0 S3 S4 S5 AC IN ON ON ON ON BAT only ON ON OFF OFF DEVICE MAXIM - LED MAXIM - GPIO I2C EEPROM S 3 S D 2 G S R1593 100K_0402_1%~D Q215 2N7002E-T1-E3_SOT23-3 S 1 Q214 2N7002E-T1-E3_SOT23-3 2 2 1 D 2 G 2 3 1 <40> 3V_F347_ON 1 2 1 2 R1591 100K_0402_1%~D 2 3 1 1 1 R1842 1 2 C1727 0.1U_0402_25V6K~D Q216 2N7002E-T1-E3_SOT23-3 R1589 100K_0402_1%~D 2 C1726 0.1U_0402_25V6K~D 300K_0402_5%~D 3 BATT_CHG_LED S AC mode battery full in S5:turn off ELC controller B+_BIAS R1590 100K_0402_1%~D R1592 100K_0402_1%~D 2 G C1725 4.7U_0603_10V6K~D 1 +3VALW <40> BATT_CHG_LED# B ADDRESS 000b 001b 000b G 1 Q247 2N7002E-T1-E3_SOT23-3 +3.3V_F347 A SMBUS 0100 0100 1010 4 2 D SPI_MOSO 1 2 1 D 2 G 3 S 6 5 2 1 BATT_LOW_LED D 1 2 1 Q213 <40> BATT_LOW_LED# 2N7002E-T1-E3_SOT23-3 Q212 SI3456DDV-T1-GE3_TSOP6~D R1635 100K_0402_1%~D D 2 G ACIN 3 <14,18,40,43,47> 15_0402_5% CS JUMP_43X118 ACIN# 2 STATE @ PJP24 2 R1588 100K_0402_1%~D R1585 1 CLK +3.3V_F347 behavior +3VALW B +3.3V_F347 2 SLP_S5 2 G C U604 15_0402_5% 0.1U_0402_25V6K~D D 8Mb SPI ROM SPI_MOSI R1587 100K_0402_1%~D SLP_S3 2 G 3 SA00003IR10 SA00003IR20 ★ SA00003IR30 SA00003IR40 C1723 1 1 2 R1586 100K_0402_1%~D <18,40> PM_SLP_S3# Each CPN represent different boot loader individually +3.3V_F347 1 +3.3V_F347 3 GND GND 1 1 0.1U_0402_25V6K~D C 1 2 3 4 5 6 @ C1715 1 2 3 4 5 6 @ C1719 +3.3V_F347 CONN@ JELCDBG A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title ELC (1) Size 4 3 2 Rev 0.1 LA-8321P Date: 5 Document Number Tuesday, January 17, 2012 Sheet 1 37 of 65 1 4 +3.3V_F347 1 5 +3.3V_F347 3 2 1 +3.3V_F347 L/R SPK, Logo, TP R1595 4.7K_0402_5%~D 1 2 2 R1594 4.7K_0402_5%~D U23 <39> 7313_INT# 1 1 18 23 24 TP_LED_R_DRV# TP_LED_G_DRV# TP_LED_B_DRV# SCL SDA AD0 AD1 AD2 14 15 16 17 P12 P13 P14 OSC 2 2 AD0_0 AD0_1 AD0_2 INT#/O16 9 GND V+ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 GND 21 1 2 3 4 5 6 7 8 10 11 12 13 25 LSPK_LED_R_DRV# LSPK_LED_G_DRV# LSPK_LED_B_DRV# RSPK_LED_R_DRV# RSPK_LED_G_DRV# RSPK_LED_B_DRV# 1 C1729 0.1U_0402_25V6K~D 1 C1732 0.1U_0402_25V6K~D 2 2 JCAP LOGO_LED_R_DRV# LOGO_LED_G_DRV# LOGO_LED_B_DRV# <40> CAPS_LED# <40> NUM_LED# <40> SCR_LED# MAX7313DATG+T_TQFN-EP24_4X4~D +5VS 1 2 3 4 5 6 7 8 9 10 LED_R_7313#_1 LED_B_7313#_1 LED_G_7313#_1 CAPS_LED# NUM_LED# SCR_LED# 1 2 3 4 5 6 LID_SW LOGO_LED_R_DRV# LOGO_LED_G_DRV# LOGO_LED_B_DRV# 1 2 3 4 5 6 7 8 GND1 GND2 2 JLOGO 20mil 1 2 3 4 5 6 G7 G8 1 7 8 <40> WLES ON/OFF LED# MOLEX_53398-0671~D CONN@ 1 C1745 R1597 4.7K_0402_5%~D 19 20 2 0.1U_0402_25V6K~D R1596 4.7K_0402_5%~D 22 +5VALW +5VS C1731 D 7313_INT# I2C_CLK I2C_DAT Media Board CONN LOGO Board CONN +5VS 0.1U_0402_25V6K~D <37,39> I2C_CLK <37,39> I2C_DAT Num LED CONN C1728 0.1U_0402_25V6K~D 2 D JMEDIA 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 LED_R_7313#_1 LED_B_7313#_1 LED_G_7313#_1 WLES ON/OFF LED# FOX_HS8108E CONN@ +3.3V_F347 +3.3V_F347 R1600 4.7K_0402_5%~D CAP, Media, Eyes, Rim 1 1 2 1 7313_INT# 22 I2C_CLK I2C_DAT 19 20 AD2_0 AD2_1 AD2_2 18 23 24 HDD_R_7313# HDD_G_7313# HDD_B_7313# 14 15 16 17 2 1 2 R1599 4.7K_0402_5%~D INT#/O16 SCL SDA AD0 AD1 AD2 P12 P13 P14 OSC 2 R1601 4.7K_0402_5%~D 9 C1733 0.1U_0402_25V6K~D 2 U24 R1598 4.7K_0402_5%~D C <39,40,44> <39,40,44> <39,40,44> <39,40,44> <40,44> <40,44> <40,44> <40,44> 1 +3.3V_F347 GND V+ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 GND 21 1 2 3 4 5 6 7 8 10 11 12 13 25 Touchpad LED CONN LED_R_7313#_1 LED_G_7313#_1 LED_B_7313#_1 JTP +5VS 1 2 C554 0.1U_0402_25V6K~D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TP_CLK TP_DAT <40> TP_CLK <40> TP_DAT +3VALW <17,37,40> LID_SW_IN# 1 C1734 0.1U_0402_25V6K~D MAX7313DATG+T_TQFN-EP24_4X4~D LID_SW_IN# TP_LED_R_DRV# TP_LED_G_DRV# TP_LED_B_DRV# 2 3 HDD_B D @ D27 5 TP_DAT 1 HDD_R G Q273B DMN66D0LDW-7 S 1 Q271A 1 HDD_R_7313# B R1660 300K_0402_5%~D 2 Q273A DMN66D0LDW-7 S Q3 SSM3K7002FU_SC70-3~D 2 HDD_G_7313# LID_SW R1643 1.5M_0402_5%~D G 3 1 2 1 2 <40> EN_TPLED# S 2 D 1 R1603 100K_0402_5% D 1 1 6 1 G 1 EN_TPLED D 2 4 Q2 SI3456DDV-T1-GE3_TSOP6~D 2 HDD_G +5VALW 2 C1756 0.1U_0402_25V6K~D 2 1 2 JSPKLED 1 2 3 4 5 6 7 8 9 10 3 1 C1744 0.1U_0402_25V6K~D 1 Reference AD2 AD1 AD0 MAX7313 2 <43> ON/OFFBTN# G S Q221 SSM3K7002F_SC59-3~D 3 B 11 12 +5VS S LID_SW_IN# G11 G12 PWR BTN Board CONN G D 1 2 3 4 5 6 7 8 9 10 ACES_87212-10G0 CONN@ 2 Q222 SSM3K7002F_SC59-3~D C C62 1U_0603_25V6-K~D C1746 0.1U_0402_25V6K~D S DMN66D0LDW-7 1 D 6 5 2 1 B+_BIAS LSPK_LED_R_DRV# LSPK_LED_G_DRV# LSPK_LED_B_DRV# RSPK_LED_R_DRV# RSPK_LED_G_DRV# RSPK_LED_B_DRV# S G D 2 G PCH_SATALED# +5VS 5 4 <16> PCH_SATALED# SATA_LED_ACT +5VS_TP_LED D 1 3 6 2 3 R1602 100K_0402_5% KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO3 KSO9 LID_SW PWR_G_7313# PWR_R_7313# PWR_B_7313# +5VS PJDLC05C_SOT23-3 HDD_B_7313# +5VS +5VALW LED_R_7313#_1 LED_B_7313#_1 LED_G_7313#_1 WLES ON/OFF LED# C1736 3 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 SPK LED Board CONN MOLEX_53398-1371~D CONN@ 0.1U_0402_25V6K~D TP_CLK 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 AMPHE_G283010211CEU CONN@ C1735 Q271B DMN66D0LDW-7 2 1 2 3 4 5 6 7 8 9 10 11 12 13 GND1 GND2 0.1U_0402_25V6K~D 4 G +5VS KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO3 KSO9 LID_SW PWR_G_7313# PWR_R_7313# PWR_B_7313# +5VS_TP_LED PWR_R_7313# PWR_G_7313# PWR_B_7313# S KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO3 KSO9 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 U23 0 1 0 L/R Headlight , Logo, TP 2 JBTN 1 2 3 4 5 6 ON/OFFBTN# HDD_R HDD_G HDD_B 1 2 3 4 5 6 G7 G8 7 8 MOLEX_53398-0671~D CONN@ A U24 0 1 1 Num, CAP , SCR EJECT, REV, PLAY/PAUSE FFWD, Vol_DWN, Vol_UP Wireless ON/OFF AWCC Button Alien Adrenaline Power Button Eyes Power Button Rim A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title ELC (2) Size 4 3 2 Rev 0.1 LA-8321P Date: 5 Document Number Tuesday, January 17, 2012 Sheet 1 38 of 65 5 4 2 <38> 1 1 <37,38> I2C_CLK <37,38> I2C_DAT I2C_CLK I2C_DAT 19 20 AD1_0 AD1_1 AD1_2 18 23 24 KP_LED_R1_DRV# KP_LED_G1_DRV# KP_LED_B1_DRV# R1609 4.7K_0402_5%~D 22 14 15 16 17 INT#/O16 SCL SDA AD0 AD1 AD2 P12 P13 P14 OSC 2 2 R1608 4.7K_0402_5%~D AD0 1 Keypad Backlight CONN 9 GND V+ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 GND JKBBL 1 2 C1854 0.1U_0402_25V6K~D KB_LED_R1_DRV#_A# KB_LED_B1_DRV#_A# 1 2 3 4 5 6 7 8 10 11 12 13 25 Keypad CONN +5VS 1 21 1 1 AD1 0 U25 7313_INT# 7313_INT# K/B Backlight CONN +3.3V_F347 AD2 0 R1606 4.7K_0402_5%~D 2 R1605 4.7K_0402_5%~D D K/B Backlight 1 1 +3.3V_F347 2 KB_LED_R1_DRV# KB_LED_G1_DRV# KB_LED_B1_DRV# KB_LED_R2_DRV# KB_LED_G2_DRV# KB_LED_B2_DRV# KB_LED_R3_DRV# KB_LED_G3_DRV# KB_LED_B3_DRV# KB_LED_R4_DRV# KB_LED_G4_DRV# KB_LED_B4_DRV# KB_LED_R1_DRV# KB_LED_G1_DRV# KB_LED_B1_DRV# KB_LED_R2_DRV# KB_LED_G2_DRV# KB_LED_B2_DRV# KB_LED_R3_DRV# KB_LED_G3_DRV# KB_LED_B3_DRV# KB_LED_R4_DRV# KB_LED_G4_DRV# KB_LED_B4_DRV# <44> KB_LED_G2_DRV#_A# <44> <44> KB_LED_R3_DRV#_A# <44> <44> KB_LED_B3_DRV#_A# <44> <44> +5VS KB_LED_G4_DRV#_A# <44> <44> 1 2+5VS_KBBL <44> F3 <44> 0.5A_13.2V_NANOSMDC050F-13.2-2 1 <44> C1855 0.1U_0402_25V6K~D MAX7313DATG+T_TQFN-EP24_4X4~D 2 3 5 7 9 11 13 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 G1 G3 G2 G4 F5 0.5A_13.2V_NANOSMDC050F-13.2-2 2 KB_LED_G1_DRV#_A# 4 6 KB_LED_R2_DRV#_A# 8 KB_LED_B2_DRV#_A# 10 KB_LED_G3_DRV#_A# 12 KB_LED_R4_DRV#_A# 14 KB_LED_B4_DRV#_A# 16 +5VS_KBBL 2 +3.3V_F347 3 JKP 1 KP_LED_G1_DRV#_A# +5VS_KPBL 1 2 3 3 4 5 5 6 1 2 C1856 0.1U_0402_25V6K~D 7 9 G1 G3 G2 G4 2 KP_LED_B1_DRV#_A# 4 KP_LED_R1_DRV#_A# +5VS_KPBL 6 KP_DET# KP_KSO16 KSI0 KSI5 KSI1 KSI4 KSI2 KSI3 <40> KP_DET# <40> KSO16 <40,44> KSI0 <38,40,44> KSI5 <40,44> KSI1 <38,40,44> KSI4 <38,40,44> KSI2 <38,40,44> KSI3 JKPBL 1 3 5 7 9 11 13 15 17 19 1 3 5 7 9 11 13 15 17 19 8 10 2 4 6 8 10 12 14 16 18 20 KP_DET# KP_KSO16 KSI0 KSI5 KSI1 KSI4 KSI2 KSI3 2 4 6 8 10 12 14 16 18 20 D AMPHE_G281010112CHR~D CONN@ AMPHE_G25061021A6EU CONN@ 18 20 AMPHE_G25161021A6EU CONN@ +3VS +3VS +3VS 1 1 1 Q84A DMN66D0LDW-7 S S D S KB_LED_R4_DRV 5 G D S C Q90B DMN66D0LDW-7 2 G Q87A DMN66D0LDW-7 S 3 1 KB_LED_R4_DRV# Q81A DMN66D0LDW-7 S 4 R1630 4.7K_0402_5%~D 3 2 1 Q87B DMN66D0LDW-7 S KB_LED_R4_DRV#_A# D 4 2 G D 2 G 6 KB_LED_R3_DRV# R1631 4.7K_0402_5%~D D KB_LED_R3_DRV 5 G 1 Q84B DMN66D0LDW-7 S 2 G +3VS 3 R1624 4.7K_0402_5%~D 4 D 2 1 3 KB_LED_R2_DRV# KB_LED_R3_DRV#_A# 2 4 Q81B DMN66D0LDW-7 S D KB_LED_R2_DRV 5 G 1 KB_LED_R1_DRV# D R1625 4.7K_0402_5%~D 6 KB_LED_R1_DRV 5 G C +3VS KB_LED_R2_DRV#_A# 4 R1618 4.7K_0402_5%~D 6 2 6 D 2 1 KB_LED_R1_DRV#_A# 3 R1613 4.7K_0402_5%~D 2 1 R1612 4.7K_0402_5%~D 2 +3VS R1619 4.7K_0402_5%~D 2 1 1 +3VS +3VS Q90A DMN66D0LDW-7 +3VS +3VS +3VS 3 Q88B DMN66D0LDW-7 S 1 2 1 4 D R1661 4.7K_0402_5%~D 2 G Q85A DMN66D0LDW-7 S D S Q91B DMN66D0LDW-7 2 G Q88A DMN66D0LDW-7 S KB_LED_G4_DRV 5 G 6 KB_LED_G3_DRV# KB_LED_G4_DRV#_A# R1662 4.7K_0402_5%~D 1 2 1 Q85B DMN66D0LDW-7 S +3VS D KB_LED_G3_DRV 5 G KB_LED_G4_DRV# Q82A DMN66D0LDW-7 S D 2 G 1 1 3 KB_LED_G2_DRV# 2 G R1626 4.7K_0402_5%~D KB_LED_G2_DRV 5 G KB_LED_G3_DRV#_A# 2 S D 1 4 D Q82B DMN66D0LDW-7 KB_LED_G2_DRV#_A# 4 R1620 4.7K_0402_5%~D KB_LED_G1_DRV 5 G 6 2 6 2 KB_LED_G1_DRV# D 2 1 3 1 R1614 4.7K_0402_5%~D R1621 4.7K_0402_5%~D R1627 4.7K_0402_5%~D 6 +3VS KB_LED_G1_DRV#_A# R1615 4.7K_0402_5%~D 2 +3VS +3VS 2 1 1 1 +3VS Q91A DMN66D0LDW-7 B B +3VS +3VS +3VS 2 G 1 3 2 KB_LED_B4_DRV# S KB_LED_B4_DRV 5 G D S Q92B DMN66D0LDW-7 2 G Q89A DMN66D0LDW-7 S KB_LED_B4_DRV#_A# D 4 4 6 R1663 4.7K_0402_5%~D Q89B DMN66D0LDW-7 S 2 KB_LED_B3_DRV# Q86A DMN66D0LDW-7 S D R1664 4.7K_0402_5%~D 1 3 2 1 2 3 D Q86B DMN66D0LDW-7 +3VS KB_LED_B3_DRV 5 G 6 1 1 KB_LED_B2_DRV 5 G 2 G Q83A DMN66D0LDW-7 S S R1628 4.7K_0402_5%~D D 1 KB_LED_B2_DRV# 2 G D KB_LED_B3_DRV#_A# R1629 4.7K_0402_5%~D KB_LED_B2_DRV#_A# 4 D R1622 4.7K_0402_5%~D Q83B DMN66D0LDW-7 6 KB_LED_B1_DRV 5 G 2 S +3VS R1623 4.7K_0402_5%~D 1 D +3VS 1 KB_LED_B1_DRV# 3 6 2 R1616 4.7K_0402_5%~D KB_LED_B1_DRV#_A# 4 2 1 R1617 4.7K_0402_5%~D 2 +3VS 1 1 1 +3VS Q92A DMN66D0LDW-7 Keypad LED contorl 2 G 2 G 1 6 2 KP_LED_B1_DRV# A 3 S Q94B DMN66D0LDW-7 2 R1669 4.7K_0402_5%~D KP_LED_B1_DRV#_A# D 4 4 2 6 KP_LED_G1_DRV# D KP_LED_G1_DRV 5 G D R1670 4.7K_0402_5%~D 1 KP_LED_G1_DRV#_A# 3 1 S R1668 4.7K_0402_5%~D Q93B DMN66D0LDW-7 +3VS R1667 4.7K_0402_5%~D 2 2 6 KP_LED_R1_DRV 5 G D 4 R1665 4.7K_0402_5%~D 2 3 1 KP_LED_R1_DRV#_A# D +3VS 1 +3VS R1666 4.7K_0402_5%~D A S KP_LED_B1_DRV 5 G D Q95B DMN66D0LDW-7 Compal Electronics, Inc. 2 G Title Q93A DMN66D0LDW-7 S Q94A DMN66D0LDW-7 1 S 1 1 KP_LED_R1_DRV# +3VS 1 +3VS +3VS S Q95A DMN66D0LDW-7 ELC (3) Size Document Number Rev 0.1 LA-8321P Date: 5 4 3 2 Tuesday, January 17, 2012 Sheet 1 39 of 65 5 4 3 2 1 +3VALW_EC GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 <19> CLK_PCI_LPC PLT_RST# 1 <5,16,19,31,35,43> <20> EC_SCI# <25> EN_CAM @ R468 33_0402_5%~D R469 1 R476 1 R478 1 R470 1 R473 1 @ R485 1 R1530 C 1 R1531 1 R2660 SPDIF_DET# 47K_0402_5% @ C542 22P_0402_50V8J~D 1 EC_RST# 47K_0402_5% 2 KSO1 47K_0402_5% 2 KSO2 47K_0402_5% 2 EC_SMB_CK1 4.7K_0402_5%~D 2 EC_SMB_DA1 4.7K_0402_5%~D 2 EC_SMI# 1K_0402_1% 2 EC_ESB_CLK 4.7K_0402_5%~D 2 EC_ESB_DAT 4.7K_0402_5%~D 2 KB_DET# 100K_0402_5%~D 1 1 R486 1 R489 1 R490 1000P_0402_50V7K~D U14 GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 1 2 3 4 5 7 8 10 CLK_PCI_LPC PLT_RST# EC_RST# EC_SCI# EN_CAM 12 13 37 20 38 KSI0_EC KSI1_EC KSI2_EC KSI3_EC KSI4_EC KSI5_EC KSI6_EC KSI7_EC KSO0_EC KSO1_EC KSO2_EC KSO3_EC KSO4_EC KSO5_EC KSO6_EC KSO7_EC KSO8_EC KSO9_EC KSO10_EC KSO11_EC KSO12_EC KSO13_EC KSO14_EC KSO15_EC KSO16 DEPOP# 1 2 C543 0.1U_0402_25V6K~D 2 12/15-82 12/08-74 +3VS 1 <39> <32> EC_SCI# 10K_0402_5%~D 2 EC_SMB_CK2 2.2K_0402_5%~D 2 EC_SMB_DA2 2.2K_0402_5%~D 2 KSO16 DEPOP# 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 <14,44,45> EC_SMB_CK1 <14,44,45> EC_SMB_DA1 <15,17,30,41,44> EC_SMB_CK2 <15,17,30,41,44> EC_SMB_DA2 77 78 79 80 BATT_TEMP_Q GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ# LPC_FRAME#/LFRAME# LPC_AD3/LAD3 LPC_AD2/LAD2 LPC_AD1/LAD1 LPC_AD0/LAD0 PWM 2 0_0402_5%~D PM_SLP_S3#_R 2 0_0402_5%~D PM_SLP_S5#_R EC_SMI# PS_ID 2 0_0402_5%~D EC_ESB_CLK_R EC_ESB_DAT @ R496 1 12/08-74 <18> <41> <41> <41> <35> <35> <43> <44> <38> 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 SUSPWRDNACK MXM2_FAN_PWM SYSTEM_FAN_FB MXM1_FAN_FB E51TXD_P80DATA E51RXD_P80CLK ON/OFF KB_DET# NUM_LED# MXM2_FAN_PWM SYSTEM_FAN_FB MXM1_FAN_FB E51TXD_P80DATA E51RXD_P80CLK ON/OFF KB_DET# NUM_LED# AVCC LPC & MISC PS2 Interface EC_MUTE#/PSCLK1/GPIO4A USB_EN#/PSDAT1/GPIO4B CAP_INT#/PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F 122 123 SPI Flash ROM GPIO PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 GPIO0A GPIO0B GPIO GPIO0C SUS_PWR_DN_ACK/GPIO0D INVT_PWM/PWM2/GPIO11 FAN_SPEED1/FANFB0/GPIO14 FANFB1/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A 2 GPIO40 H_PECI/GPIO41 FSTCHG/GPIO50 BATT_CHG_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 PWR_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04 EC_ON/GPXIOA05 EC_SWI#/GPXIOA06 ICH_PWROK/GPXIOA07 BKOFF#/GPXIOA08 GPO RF_OFF#/GPXIOA09 GPXIOA10 GPXIOA11 GPI PM_SLP_S4#/GPXIOD01 ENBKL/GPXIOD02 EAPD/GPXIOD03 EC_THERM#/GPXIOD04 SUSP#/GPXIOD05 PBTN_OUT#/GPXIOD06 EC_PME#/GPXIOD07 V18R 2 EC_CRY2 69 @ 11 24 35 94 113 X1 EC_CRY1 1 SPIDI/MISO SPIDO/MOSI SPICLK/GPIO58 SPICS# XCLK1 XCLK0 KB930QF-A1_LQFP128_14X14 Ra: 100k Rb: 33k Ver: 0.4 63 64 65 66 75 76 BATT_TEMP_Q 68 70 71 72 H_PROCHOT#_EC AC_SEL IREF CHGVADJ 83 84 85 86 87 88 EC_MUTE_R# @ @R471 R471 1 2 0_0402_5%~D SA_PGOOD SA_PGOOD <52> LCD_BKL_EN LCD_BKL_EN <25> ESATA/USB_OFF ESATA/USB_OFF <43> TP_CLK TP_CLK <38> TP_DAT TP_DAT <38> 97 98 99 109 EN_WOL# HDA_SDO LID_SW_IN# ADP_I AD_BID0 KP_DET# SPDIF_DET# EAPD# ADP_I <32> <45,47> KP_DET# SPDIF_DET# <39> <32> AC_SEL IREF CHGVADJ <45> <47> <47> AD_BID0 1 R466 01/04-94 CPU1.5V_S3_GATE <9> BEEP# <32> SYSTEM_FAN_PWM <41> MXM1_FAN_PWM <41> Rb 33K_0402_5%~D C541 D Board ID definition, Please see page 3. L40 ECAGND 2 1 FBMA-L11-160808-800LMT_0603 1 C540 0.1U_0402_25V6K~D 2 100P_0402_50V8J~D H_PROCHOT# <5,45> H_PROCHOT# @R520 @ R520 1 01/03-92 D S 2 0_0402_5%~D VR_HOT# VR_HOT# <53,55> Q205 2N7002E-T1-E3_SOT23-3 2 ODD_EJEECT# EN_WOL# HDA_SDO LID_SW_IN# SPI Device I/F EC_SMB_CK1/SCL0/GPIO44 EC_SMB_DA1/SDA0/GPIO45 EC_SMB_CK2/SCL1/GPIO46 EC_SMB_DA2/SDA1/GPIO47 1 R1885 100K_0402_5% CPU1.5V_S3_GATE BEEP# SYSTEM_FAN_PWM MXM1_FAN_PWM 119 120 126 128 R481 R482 R484 G +5VS EC_MUTE# EC_MUTE# <33> 1 1 1 <34> <31> <16> <17,37,38> FRD# FWR# SPI_CLK FSEL# 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 2 2 2 73 74 89 90 91 92 93 95 121 127 PCH_VREG_EN# EC_PECI FSTCHG BATT_CHG_LED# CAPS_LED# BATT_LOW_LED# SCR_LED# SYSON VR_ON ACIN 100 101 102 103 104 105 106 107 108 C550 100P_0402_50V8J~D PCH_RSMRST# PCH_RSMRST# <18> MXM2_FAN_FB MXM2_FAN_FB <41> EC_ON EC_ON <43,48> 3S/4S# 3S/4S# <47> PCH_PWROK PCH_PWROK <18> BKOFF# <25> PCH_PWR_EN PCH_PWR_EN <42> PCH_APWROK PCH_APWROK <18> EC_LID_OUT# EC_LID_OUT# <17> 110 112 114 115 116 117 118 PM_SLP_S4#_R ENBKL M_THERMAL# ACOFF SUSP# PBTN_OUT# PCIE_WAKE#_EC 124 +V18R 2 PCH_VREG_EN# TP_CLK R472 2 1 4.7K_0402_5%~D TP_DAT R474 2 1 4.7K_0402_5%~D 1 C547 <22> 1 @ R480 1 ENBKL M_THERMAL# ACOFF SUSP# PBTN_OUT# 1 BKOFF# R495 2 1 10K_0402_5%~D M_THERMAL# R517 2 1 10K_0402_5%~D C +3VALW_EC Please place R503 close to EC with in 750mil R503 1 2 43_0402_1% H_PECI <5,20> FSTCHG <47> BATT_CHG_LED# <37> CAPS_LED# <38> BATT_LOW_LED# <37> SCR_LED# <38> SYSON <42,43,51> VR_ON <41,53,55> ACIN <14,18,37,43,47> @R467 @ R467 AGND EC_CRY1 EC_CRY2 2 0_0402_5%~D 21 23 26 27 R465 100K_0402_5% Ra <43,45> +3VS SDICS#/GPXIOA00 WOL_EN/SDICLK/GPXIOA01 ME_EN/SDIMOSI/GPXIOA02 LID_SW#/GPXIOD00 GND GND GND GND GND @ R511 1 DAC_BRIG/DA0/GPO3C EN_DFAN1/DA1/GPO3D IREF/DA2/GPO3E DA3/GPO3F DA Output BATT_TEMP 2 0_0402_5%~D 2 B <18> SUSCLK_R 1 2N7002E-T1-E3_SOT23-3 BATT_TEMP/AD0/GPI38 BATT_OVP/AD1/GPI39 ADP_I/AD2/GPI3A AD3/GPI3B AD Input AD4/GPI42 AD5/GPI43 CLK_PCI_EC/PCICLK PCIRST#/GPIO05 EC_RST#/ECRST# EC_SCI#/GPIO0E CLKRUN#/GPIO1D KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 3 R2661 1 PWM0/GPIO0F BEEP#/PWM1/GPIO10 Output FANPWM0/GPIO12 ACOFF/FANPWM1/GPIO13 SM Bus @ R513 1 @ R514 1 <18,37> PM_SLP_S3# <18,37> PM_SLP_S5# <20> EC_SMI# <46> PS_ID EC_ESB_CLK @ Q307 0.1U_0402_25V6K~D 2 1000P_0402_50V7K~D 2 01/03-92 2 C538 VCC VCC VCC VCC VCC VCC <20> <20> <16> <16,35> <16,35> <16,35> <16,35> <16,35> 2 1 KSO[0..15] D R1829 C537 1 +3VALW_EC 1 0.1U_0402_25V6K~D KSI[0..7] KSI[0..7] <38,44> KSO[0..15] +3VALW_EC C536 2 Board ID +3VALW_EC ECAGND 2 1 0.1U_0402_25V6K~D <38,39,44> C535 2 12/08-76 C539 1 2 C534 2 2 1 C533 2 2 3 2 0_0805_5%~D 1 1 L39 FBMA-L11-160808-800LMT_0603 1 2 +EC_VCCA +3VALW_EC 0.1U_0402_25V6K~D D @ R2586 1 S +3VLP 1 G 1 67 0.1U_0402_25V6K~D 2 0_0805_5% 1 9 22 33 96 111 125 @ R464 2 +3VALW 2 0_0402_5%~D PM_SLP_S4# PM_SLP_S4# <18> <24> <10,11,12,13> <46,47> <9,21,42,43,49,50,51> <5,16,18> 2 PCIE_WAKE# 0_0402_5%~D <18,31,35,43> 2 4.7U_0603_10V6K~D KSO0 KSI0 KSO13 KSI1 KSO5 KSO2 KSI3 KSO7 KSO15 KSO14 KSO4 KSO8 KSI5 KSO12 KSO6 KSO11 KSI7 KSO9 KSO10 KSI6 KSO3 KSI4 KSI2 KSO1 DEPOP# R493 2 1 100K_0402_5%~D EC_MUTE# R483 2 1 100K_0402_5%~D R2625 R2626 R2627 R2628 R2629 R2630 R2631 R2632 R2633 R2634 R2635 R2636 R2637 R2638 R2639 R2640 R2641 R2642 R2643 R2644 R2645 R2646 R2647 R2648 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D KSO0_EC KSI0_EC KSO13_EC KSI1_EC KSO5_EC KSO2_EC KSI3_EC KSO7_EC KSO15_EC KSO14_EC KSO4_EC KSO8_EC KSI5_EC KSO12_EC KSO6_EC KSO11_EC KSI7_EC KSO9_EC KSO10_EC KSI6_EC KSO3_EC KSI4_EC KSI2_EC KSO1_EC B 20mil ECAGND 1 32.768KHZ_12.5PF_9H03200019 1 @ C545 27P_0402_50V8J~D C546 20P_0402_50V8J~D +3VALW_EC 2 1 U44 2 <30> HDMI_TOGGLE# 2 C623 0.1U_0402_25V6K~D 1 <36,43> USB_PWR_EN# <24,25> HDMI_IN_SELECT# +3VALW_EC 1Mb SPI ROM A @R497 @ R497 1 2 0_0402_5%~D FRD# @R500 @ R500 1 2 0_0402_5%~D SPI_SO 1 SPI_FSEL# U15 +3VALW 1 2 3 4 CS# SO WP# GND VCC HOLD# SCLK SI 8 7 6 5 1 HDMI_TOGGLE# 2 RST# 3 EC_ESB_DAT 4 USB_PWR_EN# 5 HDMI_IN_SELECT# <30,43> HDMI_IN_CAB_DET# C551 0.1U_0402_25V6K~D 6 7 <45> DYN_TURBO_SEL 8 <6> DRAMRST_CNTRL_EC 9 <24> EC_INV_PWM 10 <18,24> PCH_ENVDD 11 2 12 SPI_CLK_R @ R498 1 2 0_0402_5%~D SPI_CLK SPI_FWR# @ R499 1 2 0_0402_5%~D FWR# ESB_CLK GPIO00 TEST_EN# GPIO08/CAS_DAT RST# GPIO09 ESB_DAT GPIO0A GPIO01 GPIO0B GPIO02 GPIO0C/PWM0 GPIO03 GPIO0D/PWM1 GPIO04 GPIO0E/PWM2 GPIO05 GPIO0F/PWM3 GPIO06 GPIO10/ESB_RUN# GPIO07/CAS_CLK GND KC3810_QFN24_4X4 GPIO11/BaseAddOpt VCC 13 14 EC_ENVDD 15 EN_TPLED# 16 17 EC_ENVDD <24> EN_TPLED# <38> CP_SEL CP_SEL <47> PWRSHARE_OE# PWRSHARE_OE# 18 WLES ON/OFF LED# WLES ON/OFF LED# 19 EC_AC_BAT# EC_AC_BAT# 20 @R494 @ R494 1 21 DP_MXM_CARD_SEL DP_MXM_CARD_SEL 22 LCD_TEST LCD_TEST <25> 3V_F347_ON <37> 2 1 @ R1533 33_0402_5%~D 1 60 mil C624 1 2 MX25L1005AMC-12G_SO8 2 @ C626 22P_0402_50V8J~D 2 0_0402_5%~D 3V_F347_ON 23 24 0.1U_0402_25V6K~D FSEL# EC_ESB_CLK GND R1529 47K_0402_5% 25 2 4 3 2 <38> <14> TH_OVERT# <14> <28,29> A +3VALW_EC Compal Electronics, Inc. Title EC ENE-KB930 Size Document Number Rev 0.1 LA-8321P Date: 5 <43> Tuesday, January 17, 2012 Sheet 1 40 of 65 A B C D E System Thermal Sensor Diode circuit s used for skin temp sensor (placed between CPU and MXM). Place C295 close to Q13 as possible. +3VS 3 4 2 1 REMOTE_P2 1 1 C E 2 B Q267 MMBT3904WT1G_SC70-3~D 2 SENSOR_DIODE_N2 @ R1807 2 0_0402_5%~D 1 1 1 @ R1815 1 2 0_0402_5%~D SENSOR_DIODE_N3 @ R1816 1 2 0_0402_5%~D Pull up resistor on thermtrip pin 4.7k 6.8k 10k 15k 22k 33k 2 GND EC_SMB_DA2 EC_SMB_DA2 <15,17,30,40,44> 6 5 1 R1811 10K_0402_5%~D MXM1_FAN_PWM MXM1_FAN_FB <40> MXM1_FAN_PWM <40> MXM1_FAN_FB 2 C1858 0.1U_0402_25V6K~D 1 JMFAN1 1 2 3 4 1 1 2 3 4 G5 G6 5 6 MOLEX_53398-0471~D CONN@ 3 U617 1 VDD SMCLK DP SMDATA DN ALERT THERM#/ADDR GND EMC1412-A-ACZL-TR_MSOP8 8 EC_SMB_CK2 7 EC_SMB_DA2 EC_SMB_CK2 <15,17,30,40,44> EC_SMB_DA2 <15,17,30,40,44> 6 5 MXM2_FAN_PWM MXM2_FAN_FB <40> MXM2_FAN_PWM <40> MXM2_FAN_FB R1820 10K_0402_5%~D 2 2 1 C1859 0.1U_0402_25V6K~D JMFAN2 1 2 3 4 1 D67 SDMK0340L-7-F_SOD323-2~D 1 2 3 4 5 G5 6 G6 MOLEX_53398-0471~D CONN@ @ Q276 SSM3K7002FU_SC70-3~D VR_ON SMBUS address 4 1111_100xb 1011_100xb 1001_100xb 1101_100xb 0011_100xb 0111_100xb DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title Theraml Sensor & FAN Size B C D Document Number Rev 0.1 LA-8321P Date: A 2 3 D 1 2 G 4 THERM#/ADDR 7 <15,17,30,40,44> +5VS 4 15K_0402_5% MAINPWON <40,53,55> ALERT EC_SMB_CK2 +3VS 3 1 R1821 <45,46,48> SMDATA DN EC_SMB_CK2 D66 SDMK0340L-7-F_SOD323-2~D 2 REMOTE_N3 2 +3VS DP 8 S 2 2 C1821 470P_0402_50V7K~D 2 SMCLK MXM2 Thermal Sensor REMOTE_P3 1 1 3 @ C1820 100P_0402_50V8J~D VDD @ Q275 SSM3K7002FU_SC70-3~D C1822 0.1U_0402_25V6K~D SENSOR_DIODE_P3 5 6 VR_ON 1 2 B E Q268 MMBT3904WT1G_SC70-3~D G5 G6 MOLEX_53398-0471~D CONN@ 2 1 3 +3VS C 1 2 3 4 D65 SDMK0340L-7-F_SOD323-2~D EMC1412-A-ACZL-TR_MSOP8 3 1 1 +5VS 4 MAINPWON <40,53,55> 2 JSYSFAN 1 2 3 4 U616 6.8K_0402_1%~D 2 G <45,46,48> SYSTEM_FAN_PWM SYSTEM_FAN_FB <40> SYSTEM_FAN_PWM <40> SYSTEM_FAN_FB +3VS 3 2 R1808 5 GND 1 MXM1 Thermal Sensor 2 REMOTE_N2 +3VS <15,17,30,40,44> S 2 2 C1817 470P_0402_50V7K~D D @ C1818 100P_0402_50V8J~D 3 1 EC_SMB_DA2 @ Q274 SSM3K7002FU_SC70-3~D C1819 0.1U_0402_25V6K~D 2 0_0402_5%~D 1 EC_SMB_DA2 6 1 C1857 0.1U_0402_25V6K~D VR_ON 1 @ R1806 2 R1802 10K_0402_5%~D 3 +3VS SENSOR_DIODE_P2 THERM#/ADDR 7 EMC1412-A-ACZL-TR_MSOP8 MAINPWON <40,53,55> 2 ALERT 4.7K_0402_1%~D 2 G <45,46,48> SMDATA DN <15,17,30,40,44> 2 R1798 DP EC_SMB_CK2 2 1 +3VS 2 REMOTE_N1 EC_SMB_CK2 1 2 0_0402_5%~D 8 1 1 SMCLK S @ R1796 VDD R1801 10K_0402_5%~D 1 2 2 SENSOR_DIODE_N1 D 2 U615 1 R1819 10K_0402_5%~D 1 2 1 3 @ C1814 100P_0402_50V8J~D 2 C1815 470P_0402_50V7K~D R1800 10K_0402_5%~D 1 2 2 0_0402_5%~D 1 2 B E Q266 MMBT3904WT1G_SC70-3~D R1810 10K_0402_5%~D 1 2 1 C 1 +5VS R1813 10K_0402_5%~D 1 2 @ R1797 1 REMOTE_P1 R1822 10K_0402_5%~D 1 2 SENSOR_DIODE_P1 +3VS C1816 0.1U_0402_25V6K~D 1 Tuesday, January 17, 2012 Sheet E 41 of 65 A B C D E +5VALW to +5VS +3VALW to +3VMXM Transfer +3VALW +3VMXM Q18 SI4800BDY-T1-E3_SO8~D 4 2 2 2 4 R535 200K_0402_5% +5VS_D 1 B+_BIAS 3 G Q28 2N7002E-T1-E3_SOT23-3 2 S 1 DGPU_PWR_EN# SUSP 2 @ R1482 0_0402_5% 1 G G S Q27 2N7002E-T1-E3_SOT23-3 C602 2 Q29A S 2 1 C603 R534 470_0603_5% 2 +3VMXM_D 1 D 2 1 1 D 2 D 3 SUSP 1 R533 102K_0402_1% 1 +3VMXM_GATE 2 D C605 0.1U_0603_50V7K~D 2 C604 0.1U_0603_50V7K~D 1 B+_BIAS 40mil(1A) 2 R532 470_0603_5% 6 1 C600 1 C601 10U_0805_25V6K~D 1 C599 C598 10U_0805_25V6K~D 1 0.1U_0402_25V6K~D 2 1 1 2 3 10U_0805_25V6K~D C597 10U_0805_25V6K~D 1 2 3 1U_0603_25V6-K~D 2 8 7 6 5 1 10U_0805_25V6K~D 1 8 7 6 5 1 Q26 SI4800BDY-T1-E3_SO8~D 2 DMN66D0LDW-7 3 +5VS @ R1485 0_0402_5% SUSP 5 G S 4 +5VALW Q29B DMN66D0LDW-7 +3VALW to +3V_PCH +5VALW to +5VMXM Transfer +3VALW +3V_PCH C608 10U_0805_25V6K~D 2 1 C609 1U_0603_25V6-K~D 2 2 1 C618 10U_0805_25V6K~D 2 C622 1U_0603_25V6-K~D R539 200K_0402_5% 2 +5VMXM_GATE 1 B+_BIAS 3 G Q32 2N7002E-T1-E3_SOT23-3 2 S PCH_PWR_EN# S 2 G 2 R550 102K_0402_1% 1 1 2 1 B+_BIAS @ R1483 0_0402_5% D 1 S 2 2 G Q35 2N7002E-T1-E3_SOT23-3 C621 0.1U_0603_50V7K~D 1 D 1 D @ R1488 0_0402_5% 2 Q36A DMN66D0LDW-7 C610 2 2 1 C612 R537 470_0603_5% 2 1 4 1 DGPU_PWR_EN# 2 R538 102K_0402_1% SUSP 2 C619 10U_0805_25V6K~D C614 0.1U_0603_50V7K~D 1 B+_BIAS C613 0.1U_0603_50V7K~D 2 1 C620 10U_0805_25V6K~D 100mil(2.5A) 1 +5VMXM_D @ R1486 0_0402_5% D SUSP 5 2 G S 4 2 4 C607 10U_0805_25V6K~D 1 2 1 2 3 3 2 4 C606 10U_0805_25V6K~D 1 1 2 3 0.1U_0402_25V6K~D 2 1 8 7 6 5 1 C611 10U_0805_25V6K~D Q31 SI4800BDY-T1-E3_SO8~D 1 2 3 8 7 6 5 10U_0805_25V6K~D 1 Q19 SI4800BDY-T1-E3_SO8~D 1 JUMP_43X118 Q30 SI4800BDY-T1-E3_SO8~D 8 7 6 5 1 6 +3VS 2 1 2 +3VALW +5VMXM @ PJP38 3 +5VALW +3VALW to +3VS Q36B DMN66D0LDW-7 +1.5V To +1.5VS +1.5VS Q20 AO4728L_SO8~D +5VALW 1 @ R556 10K_0402_5%~D R551 100K_0402_5% 2 S SUSP Q41 2N7002E-T1-E3_SOT23-3 <9,21,40,43,49,50,51> 2 1 1 +0.75VS 1 R552 100K_0402_5% 2 3 Q40 2N7002E-T1-E3_SOT23-3 @ 1 1 R555 470_0402_5% R1479 220_0402_5% R624 22_0603_5% 2 2 +1.5V_D 2 +1.5V_CPU_VDDQ @ 2 S G 2 R553 100K_0402_5% +1.5V D 2 SUSP# 1 1 C628 0.1U_0603_50V7K~D G C630 0.1U_0603_50V7K~D D 3 <40> PCH_PWR_EN R544 100K_0402_5% 2 <22> PCH_PWR_EN# 1 PCH_PWR_EN# 1 R1484 100K_0402_5% 3 1 +5VALW 2 2 +3VALW 1 4 1 Q37 SSM3K7002FU_SC70-3~D G 2 3 1 2 1 3 S 2 1 0.1U_0402_25V6K~D D 1 2 C617 0.1U_0603_50V7K~D SUSP C615 R540 100K_0402_5% 1 2 3 C616 10U_0805_25V6K~D 8 7 6 5 2 +1.5V 1 B+_BIAS +3VS_D 1 1 2 @ 1 S Q39 2N7002E-T1-E3_SOT23-3 2 1 <19> DGPU_PWR_EN Q38 2N7002E-T1-E3_SOT23-3 1 S R549 100K_0402_5% 2 2 R554 10K_0402_5%~D 1 D 3 2 1 G 3 1 3 D 2 SYSON 2 2 2 2 PCH_PWR_EN# S DMN66D0LDW-7 4 1 S Q33B DMN66D0LDW-7 D D G @ 4 DELL CONFIDENTIAL/PROPRIETARY 2 5 G Q34A Compal Electronics, Inc. SUSP G S S DMN66D0LDW-7 4 SUSP G 3 6 5 G 1 D 3 D 2 Q33A <40,43,51> DGPU_PWR_EN# +VCCP_D 6 SUSP G 470_0402_5% +3V_D +1.5VS_D S 2 R542 100K_0402_5% SYSON# 1 1 1 1 1 2 R548 470_0402_5% D C631 0.1U_0603_50V7K~D R547 470_0402_5% R543 100K_0402_5% C629 0.1U_0603_50V7K~D R546 470_0402_5% S 2 G +3VS 2 2 +5VALW +5VALW Q78 SSM3K7002FU_SC70-3~D R545 4 +3V_PCH D Q204 SSM3K7002FU_SC70-3~D <5,9> RUN_ON_CPU1.5VS3# +VCCP 1 3 S 3 1 Q42 SSM3K7002FU_SC70-3~D +DDR_CHG D 2 G +1.5VS +1.5V_CPU_VDDQ_CHG SYSON# Q34B DMN66D0LDW-7 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title DC/DC Interface Size B C D Rev 0.1 LA-8321P Date: A Document Number Tuesday, January 17, 2012 Sheet E 42 of 65 @ H19 H_3P0 @ H20 H_3P3 @ 1 @ H18 H_3P3 1 @ H17 H_3P3 1 @ H16 H_3P8 1 @ H15 H_3P0 1 @ H14 H_3P0 1 @ H13 H_3P0 1 @ H12 H_3P0 1 @ H11 H_3P0 1 @ 1 H10 H_3P0 1 @ H9 H_3P8 1 @ H8 H_3P8 1 @ H7 H_3P0 @ 2 @ H6 H_3P8 1 @ H5 H_3P0 1 @ H4 H_3P3 1 @ 1 <38> ON/OFFBTN# 2 H3 H_3P0 1 +3VALW_EC H2 H_3P0 1 from IO/B PWR BTN 3 H1 H_3P5 1 Power Button 4 1 5 R502 4 1 H26 H_3P8 H27 H_3P8 H28 H_2P5 H31 H_2P1N FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 ZZZ @ FIDUCIAL_C40M80 D IO Board CONN 1 6251VDD 1 3 2 <14,18,37,40,47> ACIN JIO1 1 12/14-81 4 D S DMN66D0LDW-7 S 1 DMN66D0LDW-7 6 @ Q305A 2 G 5 G D 3 1 <40,45> BATT_TEMP 1 1 3 2 10K_0402_5%~D Q305B @ 1 2 C1862 S D 1 C1861 Q43 2N7002E-T1-E3_SOT23-3 2 0.1U_0402_25V6K~D R2658 @ 100K_0402_5% D 2 G C1860 EC_ON 2 0.1U_0402_25V6K~D 51ON# 4 6 5 @ FD4 @ PCB PJSOT24C_SOT23-3 R488 2 @ FD3 @ +5VALW 0.1U_0402_25V6K~D <40,48> EC_ON @ FD2 @ @ D64 ON/OFF switch (BOT) SW2 EVQPLHA15_4P 1 3 FD1 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 @ 1 <46> 1 <40> 51ON# 1 ON/OFF 51ON# 1 ON/OFF 3 BAV70W_SOT323-3 C555 0.1U_0402_25V6K~D H33 H35 H_4P2X2P1N H_1P2 1 H25 H_2P5 1 H24 H_3P0 1 2 2 1 3 2 2 ON/OFFBTN# 6 5 D H22 H_3P3 1 H21 H_3P3 100K_0402_5% D20 SW1 EVQPLHA15_4P 1 3 1 ON/OFF switch (TOP) S Q306 @ 2N7002E-T1-E3_SOT23-3 2 G PCH_SMBCLK PCH_SMBDATA PCIE_WAKE# EXPCLK_REQ# SUSP# USB_PWR_EN# PLT_RST# CLK_REQ# <5,10,11,12,13,16,17,34,35> PCH_SMBCLK <5,10,11,12,13,16,17,34,35> PCH_SMBDATA <18,31,35,40> PCIE_WAKE# <17> EXPCLK_REQ# <9,21,40,42,49,50,51> SUSP# <36,40> USB_PWR_EN# <5,16,19,31,35,40> PLT_RST# <17> CDCLK_REQ# CLK_PCIE_CD CLK_PCIE_CD# <17> CLK_PCIE_CD <17> CLK_PCIE_CD# PCIE_PTX_DRX_P4 PCIE_PTX_DRX_N4 <17> PCIE_PTX_DRX_P4 <17> PCIE_PTX_DRX_N4 C PCIE_PRX_DTX_P4 PCIE_PRX_DTX_N4 <17> PCIE_PRX_DTX_P4 <17> PCIE_PRX_DTX_N4 <19> <19> USB20_N0 USB20_P0 USB20_N0 USB20_P0 SATA_PRX_DTX_P4 SATA_PRX_DTX_N4 <16> SATA_PRX_DTX_P4 <16> SATA_PRX_DTX_N4 SATA_PTX_DRX_N4 SATA_PTX_DRX_P4 <16> SATA_PTX_DRX_N4 <16> SATA_PTX_DRX_P4 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 USB20_N11 USB20_P11 USB20_N11 USB20_P11 ESATA/USB_OFF PWRSHARE_OE# USB_OC4# ESATA_DETECT# SYSON USB_OC1# USB_OC0# CLK_PCIE_EXP# CLK_PCIE_EXP <19> <19> ESATA/USB_OFF <40> PWRSHARE_OE# <40> IO_DET# <17> USB_OC4# <16,19> ESATA_DETECT# <16,19> SYSON <40,42,51> USB_OC1# <16,19> USB_OC0# <16,19> CLK_PCIE_EXP# <17> CLK_PCIE_EXP <17> PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 <17> <17> PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5 <17> <17> USB20_N1 USB20_P1 USB20_N1 USB20_P1 USB20_N9 USB20_P9 C <19> <19> USB20_N9 <19> USB20_P9 <19> +1.5VS +3VALW +3VS 1 2 C1865 2 C1864 C1863 2 72 GND GND 74 GND GND 1 CONN@ FOX_QT00070A-1120-9H~D 0.1U_0402_25V6K~D 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 0.1U_0402_25V6K~D 71 73 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 0.1U_0402_25V6K~D 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 1 IO Board CONN 2 +HDMI_IN_5VS ACES_87152-30051 B B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 <30> HDMI_IN_SW_HPD <30,40> HDMI_IN_CAB_DET# <30> HDMI_SW_DAT <30> HDMI_SW_CLK <30> HDMI_IN_CK<30> HDMI_IN_CK+ <30> HDMI_IN_D1<30> HDMI_IN_D1+ <30> HDMI_IN_D2+ <30> HDMI_IN_D2<30> HDMI_IN_D0+ <30> HDMI_IN_D0- 12/20-87 12/22-89 <19> <19> USB3TP1 USB3TN1 <19> <19> USB3RP1 USB3RN1 <19> <19> USB3TP2 USB3TN2 <19> <19> USB3RP2 USB3RN2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 GND2 GND1 32 31 A A JIO2 CONN@ DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title IO/B CONN / KB Size 4 3 2 Rev 0.1 LA-8321P Date: 5 Document Number Tuesday, January 17, 2012 Sheet 1 43 of 65 5 4 3 2 1 +3VS 2 @ @ 1 2 CD75 10U_0603_6.3V6M~D U628 11 15 40 D 1 0.22U_0402_16V7K~D 55 KSI0_VPK KSI1_VPK KSI2_VPK KSI3_VPK KSI4_VPK KSI5_VPK KSI6_VPK KSI7_VPK 18 19 20 21 22 23 24 25 KSO0_VPK KSO1_VPK KSO2_VPK KSO3_VPK KSO4_VPK KSO5_VPK KSO6_VPK KSO7_VPK 26 27 28 29 30 31 32 33 KSI[0..7] KSO[0..15] KSO8_VPK KSO9_VPK KSO10_VPK KSO11_VPK KSO12_VPK PAD~D PAD~D PAD~D PAD~D PAD~D T71 @ T70 @ T69 @ T66 @ T65 @ P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 P1.5/TA0.4 P1.6/TA1CLK/CBOUT P1.7/TA1.0 TDO/PJ.0 TDI/TCLK/PJ.1 TMS/PJ.2 TCK/PJ.3 P2.0/TA1.1 P2.1/TA1.2 P2.2/TA2CLK/SMCLK P2.3/TA2.0 P2.4/TA2.1 P2.5/TA2.2 P2.6/RTCCLK/DMAE0 P2.7/UCB0STE/UCA0CLK 34 35 36 37 38 DP/PU.0 DM/PU.1 PUR RST#/NMI/SBWTDIO TEST/SBWTCK P3.0/UCB0SIMO/UCB0SDA P3.1/UCB0SOMI/UCB0SCL P3.2/UCB0CLK/UCA0STE P3.3/UCA0TXD/UCA0SIMO P3.4/UCA0RXD/UCA0SOMI 41 42 43 44 45 46 47 48 VBUS VUSB VPK_A0 VPK_A1 VPK_A2 VPK_A3 VPK_A4 VPK_A5 VPK_A6 VPK_A7 1 2 3 4 5 6 7 8 60 61 62 63 VPK_GPIO_0 VPK_GPIO_1 50 52 51 USB20_P13 USB20_N13 VSSU DVSS1 DVSS2 AVSS1 AVSS2 GND_PAD @ T207 @ T208 @ T209 @ T210 <19> <19> 64 59 53 54 49 W=40mils 16 39 14 56 65 2 1 @ 1 1 2 2 1 1 24MHZ_12PF_7V24000020 1 3 GND GND 2 4 PAD~D PAD~D PAD~D PAD~D @1 2 100_0402_5%~D +3VS 1 47K_0402_5%~D +3VS R1607 @1 R1578 @1 2 0_0603_5%~D 2 0_0603_5%~D +5VS +3VS KSO[0..15] JKB 62 61 <40> R227 @2 PAD~D KSI[0..7] KSI[0..7] <38,40> KSO[0..15] KB_DET# KSO7 KSO0 KSI1 KSI7 KSO9 KSI6 KSI5 KSO3 KSI4 KSI2 KSO1 KSI3 KSI0 KSO13 KSO5 KSO2 KSO4 KSO8 KSO6 KSO11 KSO10 KSO12 KSO14 KSO15 KB_DET# @ Pin1 & Pin2 Loop on KB side (GND_Return) GND2 GND1 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 64 63 GND4 GND3 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 KB_DET# KSO7 KSO0 KSI1 KSI7 KSO9 KSI6 KSI5 KSO3 KSI4 KSI2 KSO1 KSI3 KSI0 KSO13 KSO5 KSO2 KSO4 KSO8 KSO6 KSO11 KSO10 KSO12 KSO14 KSO15 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 C FOX_GB1SV301-160K-8H CONN@ Analog Keys CIS link OK @@ @@ 1 0_0603_5% 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D KSO0_VPK KSI0_VPK KSO13_VPK KSI1_VPK KSO5_VPK KSO2_VPK KSI3_VPK KSO7_VPK KSO15_VPK KSO14_VPK KSO4_VPK KSO8_VPK KSI5_VPK KSO12_VPK KSO6_VPK KSO11_VPK KSI7_VPK KSO9_VPK KSO10_VPK KSI6_VPK KSO3_VPK KSI4_VPK KSI2_VPK KSO1_VPK <14,40,45> 6 1 VPK_SMB_CK1 VPK_SMB_CK1 <32> VPK_SMB_DA1 <32> Q304A @ 5 EC_SMB_DA1 3 4 DMN66D0LDW-7 <15,17,30,40,41> <15,17,30,40,41> EC_SMB_CK2 EC_SMB_DA2 VPK_SMB_DA1 Q304B @ R2662 1 2 0_0402_5%~D VPK_SMB_CK1 R2663 1 2 0_0402_5%~D VPK_SMB_DA1 A DELL CONFIDENTIAL/PROPRIETARY @ R197 0_0603_5% 2 Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 EC_SMB_CK1 G +3VS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 @ R196 <14,40,45> 1 2 KSO0 @ R2601 KSI0 @ R2602 KSO13 @ R2603 KSI1 @ R2604 KSO5 @ R2605 KSO2 @ R2606 KSI3 @ R2607 KSO7 @ R2608 KSO15 @ R2609 KSO14 @ R2610 KSO4 @ R2611 KSO8 @ R2612 KSI5 @ R2613 KSO12 @ R2614 KSO6 @ R2615 KSO11 @ R2616 KSI7 @ R2617 KSO9 @ R2618 KSO10 @ R2619 KSI6 @ R2620 KSO3 @ R2621 KSI4 @ R2622 KSI2 @ R2623 KSO1 @ R2624 2 10K_0402_5%~D 2 10K_0402_5%~D R1838 R1837 @@ B DMN66D0LDW-7 1 1 2 10K_0402_5%~D 2 10K_0402_5%~D 2 10K_0402_5%~D 2 10K_0402_5%~D R1840 R1843 1 1 R1825 R1839 1 1 2 10K_0402_5%~D 2 10K_0402_5%~D R1823 R1824 @@ 12/15-82 @ R199 0_0603_5% VPK_A6 2 2.2K_0402_5%~D 2 2.2K_0402_5%~D 1 1 +3VS +5VS @ F6 0.5A_13.2V_NANOSMDC050F-13.2-2 +5VS_VPK 1 2 1 @ 1 +3VS C1753 0_0603_5% 0.1U_0402_16V4Z 2 2 @ R198 VPK_A7 VPK_A5 VPK_A4 A VPK_SMB_CK1 @ R2583 VPK_SMB_DA1 @ R2584 S VPK_A1 VPK_A0 VPK_A3 VPK_A2 +3VS <39> <39> <39> <39> <39> <39> <39> <39> <39> <39> <39> <39> D KB_LED_R1_DRV# KB_LED_G1_DRV# KB_LED_B1_DRV# KB_LED_R2_DRV# KB_LED_G2_DRV# KB_LED_B2_DRV# KB_LED_R3_DRV# KB_LED_G3_DRV# KB_LED_B3_DRV# KB_LED_R4_DRV# KB_LED_G4_DRV# KB_LED_B4_DRV# 2 KB_LED_R1_DRV# KB_LED_G1_DRV# KB_LED_B1_DRV# KB_LED_R2_DRV# KB_LED_G2_DRV# KB_LED_B2_DRV# KB_LED_R3_DRV# KB_LED_G3_DRV# KB_LED_B3_DRV# KB_LED_R4_DRV# KB_LED_G4_DRV# KB_LED_B4_DRV# G 28 GND 27 GND 26 26 25 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 CONN@ JKB2 1 1 B 1 2 MSP430F5508IRGCR_VQFN64_9X9 TYCO_2-2041070-6~D <38,39,40> @ 3 2 R2 @ T211 @ P4.0/PM_UCB1STE/PM_UCA1CLK P4.1/PM_UCB1SIMO/PM_USB1SDA P4.2/PM_UCB1SOMI/PM_UCB1SCL P4.3/PM_UCB1CLK/PM_UCA1STE P4.4/PM_UCA1TXD/PM_UCA1SIMO P4.5/PM_UCA1RXD/PM_UCA1SOMI P4.6/PM_NONE P4.7/PM_NONE @ D 2 1 1M_0402_5%~D C1755 0.1U_0402_16V4Z~D VPK_SMB_DA1 VPK_SMB_CK1 CB0/A0/P6.0 CB1/A1/P6.1 CB2/A2/P6.2 CB3/A3/P6.3 CB4/A4/P6.4 CB5/A5/P6.5 CB6/A6/P6.6 CB7/A7/P6.7 C1754 1U_0805_10V7 T68 @ V18 @ YH3 C294 0.1U_0402_16V4Z~D PAD~D C VCORE @ RH137 S <38,40> KSO[0..15] C2012 @2 KSO13_VPK KSO14_VPK VPK_XTAL25_IN VPK_XTAL25_OUT KSO15_VPK 9 10 57 58 12 13 CH101 12P_0402_50V8J~D KSI[0..7] 1 0.47U_0603_16V7K~D 17 A8/VeREF+/P5.0 A9/VeREF-/P5.1 XT2IN/P5.2 XT2OUT/P5.3 XIN/P5.4 XOUT/P5.5 DVCC1 DVCC2 CH100 12P_0402_50V8J~D <38,39,40> C2011 @2 @ AVCC1 D 2 @ 1 C2013 0.1U_0402_10V6K~D 1 C2015 0.1U_0402_10V6K~D 2 @ C2014 0.1U_0402_10V6K~D 1 4 3 2 Title ELC (3) Size Document Number LA-8321P Date: Tuesday, January 17, 2012 Sheet 1 Rev 0.1 44 of 65 5 4 3 2 BATT+ 1 Place clsoe to EC pin PJPB1 battery connector BATT_TEMP 2 2 VL MAINPWON 2 <41,46,48> 2 PR5 0_0402_5%~D @ +3VALW_EC PR7 13.7K_0402_1% PR6 10K_0402_5%~D 1 6 2 2 3 TM_REF1 + - 6251VDD D PQ109A DMN66D0LDW-7_SOT363-6~D 2 1 O 2 G PU1A LM393DG_SO8 1 PR3 100_0402_5%~D 1 8 PR9 100_0402_5%~D 2 P 1 G 1 4 1 1 S C 1 VL PR11 100K_0402_1%~D 1 1 PR12 100K_0402_1%~D 2 2 2 2 @ PR171 34K_0402_1% PC7 1000P_0402_50V7K 1 3.2V PR10 16.9K_0402_1% 1 PC6 0.22U_0603_25V7K~D @ PR170 20K_0402_1%~D 1 SUYIN_200275GR013G10PZR~D 1 2 1.BATT++ 2.BATT++ 3.BATT++ 4.BATT++ 5.CLK_SMB 6.DAT_SMB 7.BATT_PRS 8.SYS_PRES 9.BAT_SLERT 10.GND 11.GND 12.GND 13.GND <40> PR8 100_0402_5%~D CLK_SMB DAT_SMB BATT_PRS SYS_PRES 1 SMART Battery: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 1 2 3 4 5 6 7 8 9 10 11 12 13 GND GND PH1 1 <14,40,44> PR1 28K_0402_1% PR4 47K_0402_1%~D 1 <14,40,44> 2 EC_SMB_DA1 100K_0402_1%_TSM0B104F4251RZ EC_SMB_CK1 2 1 PC3 1000P_0402_50V7K~D 2 2 PC2 0.01U_0402_25V7K~D 2 1 2 1 PC1 100P_0402_50V8J~D D VL VL JMBTY1 C PH1 under CPU botten side : CPU thermal protection at 93 degree C Recovery at 50 degree C BATT++ 2 1 1 2 2 BATT++ OTP PL2 C8B BPH 853025_2P~D PC4 100P_0402_50V8J~D D 2 2 1 3 PL1 C8B BPH 853025_2P~D BATT+ @ PD2 PESD24VS2UT_SOT23-3 3 1 CPU @ PD1 PESD24VS2UT_SOT23-3 1 PQ2 TP0610K-T1-E3_SOT23-3 +3VALW 2 1 3 4 G G P 7 PU1B @ PR196 0_0402_5%~D <5,40> H_PROCHOT# 2 1 D 2 + O - 2 @ 5 <40,47> 1 AC_SEL <40> PC5 1000P_0402_50V7K~D 4 PQ109B S DMN66D0LDW-7_SOT363-6~D 1 ADP_I @ PR185 0_0402_5%~D 6 LM393DG_SO8 G MOLEX_53398-0271 1 5 1 1 0_0402_5% 1 2 @ PR186 0_0402_5%~D 2 2 2 @ PC144 1000P_0402_50V7K~D +RTCVCC @ 2 1 1 2 PQ3 2N7002KW 1N SOT323-3 +COINCELL 1 VL 8 1 2 PD3 BAT54CW_SOT323-3 2 G 1 0_0402_5% PR183 2 JRTC1 2 S 3 1 3 2 PC10 .1U_0402_16V7K~D 1 D 2 G 2 SPOK <40> Dyn_turbo_SEL +COINCELL PR16 0_0402_5% 1 <48> PR31 1K_0402_5% +CHGRTC PR15 100K_0402_1%~D @ B @ PR192 PR184 10K_0402_5%~D +COINCELL 1 1 2 @ PC9 0.1U_0603_50V7K~D 2 1 B+_BIAS 4 2 1 3 1 2 1 2 PR14 22K_0402_1%~D +5VALW PR13 100K_0402_1%~D B+ B @ PC8 0.22U_0603_25V7K~D 3 PC17 1U_0603_25V6-K~D RTC Battery A Security Classification Issued Date A Compal Electronics, Inc. Compal Secret Data 2009/2/6 Deciphered Date 2010/2/6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title BATTERY CONN/OTP Size A3 Date: Document Number Tuesday, January 17, 2012 Rev 0.1 Sheet 45 of 65 C D S 2 2 3 3 2 2 3 2 @ PR164 PR32 0_0402_5% 68_1206_5%~D 1 LL4148_LL34-2 1 1 1 PD9 BATT+ PR126 0_0402_5% PR33 68_1206_5%~D 1 VS 2 2 2 3 1 51ON# 3 PC16 0.1U_0603_50V7K~D 1 2 2 PC15 0.22U_0603_25V7K~D 1 @ PR127 100K_0402_5% 2 PR36 22K_0402_5%~D 2 1 1 <43> PR35 100K_0402_5% @ PQ38 TP0610K-T1-E3_SOT23-3 1 BATT ONLY Precharge detector Min. typ. Max. H-->L 4.92V 6.1V 5.25V L-->H 6.062V 6.244V 6.43V 2 PQ9 TP0610K-T1-E3_SOT23-3 2 2 1 2 1 1 @ PR30 1 PD18 12/12 Pre_V 1 Precharge detector Min. typ. Max. H-->L 14.589V 14.84V 15.243V L-->H 15.562V 15.97V 16.388V 100K_0402_5% 1 2 @ PR29 100K_0402_5% 1 2 @ PR28 100K_0402_5% 2 PD8 LL4148_LL34-2 ACIN 2 2 2 @ PQ8 DTC115EUA_SC70-3 @ PU10 MAX1615EUK+_SOT23-5~D 3 2 4 2 1 2 PR197 @ 200_0805_5% 1 1 OUT #SHDN 5/3+ @ 5 @ PR138 22K_0402_5%~D <43> 1 51ON# 2 "US California Energy Efficiency" (Reserve 130mW for no battery mode) 2 1 1 3 +3VLP IN 2 @ PR300 0_0603_5%~D 1U_0603_25V6K +CHGRTC 2 PC147 3 @ PQ7 DTC115EUA_SC70-3 GND RB715F_SOT323-3 PC146 4.7U_0603_6.3V6K ACOFF +5VALW 1 1 3 2 1 2 2 B+ RLS4148_LL34-2 VIN1 <40,47> 1 1 2 @ PR27 1K_1206_5%~D @ 2 VIN @ PD7 @ PR26 1K_1206_5%~D 1 1 @ PQ6 TP0610K-T1-E3_SOT23-3 @ PR25 1K_1206_5%~D 2 @ PD6 BAV99W-7-F @ PR24 10K_0402_1%~D 2 1 E PR22 15K_0402_1%~D 1 1 PQ5 MMST3904-7-F_SOT323~D B <40> +5VALW +5VALW C @ PD5 SM24_SOT23 @ PR23 1K_1206_5%~D 1 PS_ID PR20 100K_0402_1%~D 2 VIN 2 2 D G 2 1 2 1 2 1 FOX_JPD113D-DB570-7F 1 1 PQ4 FDV301N_NL_SOT23-3~D 1 4 3 1 3 2 DC-_2 1 DC-_1 GND_1 1 3 GND_2 DOCK_PSID 2 6 PR19 33_0402_5%~D PC14 1000P_0402_50V7K~D 7 PC13 100P_0402_50V8J~D 2 2 DC+_2 2 GND_3 1 PC12 100P_0402_50V8J~D 8 2 5 1 DC+_1 PC11 1000P_0402_50V7K~D DETECT GND_4 2 PR18 2.2K_0402_5%~D 1 PR17 1 0_0402_5% PR21 10K_0402_1%~D DC_IN_S1 JDCIN1 9 @ PL5 C8B BPH 853025_2P~D rating current = 18A 1 VIN 2 2 1 3 PL3 C8B BPH 853025_2P~D ADPIN +3VALW 1 PL4 FBMA-L11-160808-601LMT_2P 2 1 DOCK_PSID PD4 BAV99W-7-F +5VALW 2 B 1 A 3 3 1 VS @ PR203 499K_0402_1%~D 2 8 4 2 3 1 B+ 2 2 1 PC149 0.01U_0402_25V7K~D PRG++ 1 @ PR201 2 D @ PACIN 47K_0402_5%~D PACIN <47> G S @ +5VALW 2 3 1 PQ11 SSM3K7002FU_SC70-3~D B+_MXM1 @ PQ10 DTC115EUA_SC70-3 4 PC22 1 + 2 100U_25V_M~D 4 @ PL7 SMB3025500YA_2P 2 PR120 0.004_2512_1% +CHGRTC 1 PC206 1000P_0402_50V7K~D For HW request, this is MXM power net @ PR199 34K_0402_1%~D 2 @ PR200 @ PR204 499K_0402_1%~D 191K_0402_1%~D @ 2 1 2 2 @ PU18A LM393DR_SO8 3 1 - 1 RB715F_SOT323-3 <15> + O 2 1 1 1 3 3 2 ACON P MAINPWON <47> 2 MXM_CUR_VIN- <15> G <41,45,48> MXM_CUR_VIN+ @ PD10 4 PC20 100U_25V_M~D 2 B+ 1 @ 1 + 2 @ PR198 2.2M_0402_5%~D PC148 0.1U_0603_25V7K~D 3 B+ 2 1 2 1 PR202 100K_0402_1%~D 4 2 1 1 B+_MXM VL 1 PR119 0.004_2512_1% PL6 SMB3025500YA_2P MXM1_CUR_VIN+ <15> MXM1_CUR_VIN- <15> Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/2/6 Deciphered Date 2010/2/6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title DCIN & DETECTOR Size Document Number Custom Date: A B C Rev 0.1 Tuesday, January 17, 2012 Sheet D 46 of 65 A B @ PD11 B540C-13-F_SMC2~D 2 PQ12 AOD403_TO252-3~D P2 1 C D B+ Iada=0~16.923A(330W) @ PD12 2 B540C-13-F_SMC2~D 1 D S ADP_I = 19.9*Iadapter*Rsense 3 1 6251aclim 1 1 1 2 1 2 PC28 2200P_0402_50V7K~D 1 2 2 2 PC47 0.01U_0402_25V7K~D VADJ LGATE GND PGND 6251VREF 1 CP_SEL PR73 PC48 4.7_0603_5%~D 1U_0402_6.3V6K~D 1 1 3 1 1 2 1 1 5 6 7 8 4 6251VDD 2 3 1 1 D S PR75 12.7K_0402_1%~D 2 1 2 PR182 1.43K_0402_1%~D 3 <40> 13 2 3 ISL6251AHAZ-T_QSOP24 2 PR74 11.5K_0402_1%~D 3 3 12 1 3 5 6 7 8 PQ24 1 DL_CHG 14 2 11 @ PC36 0.1U_0603_50V7K~D 1 1 2 1 PD17 RB751V40 SC76 6251VDDP 15 2 1 VDDP 2 2 PR72 100K_0402_1%~D 2 10 16 PC42 0.1U_0603_50V7K~D BST_CHGA 2 1 1 ACLIM PR70 2.2_0603_5%~D BST_CHG 1 2 2 BOOT DH_CHG AO4712L_SO8~D 9 1 1 PQ27 PDTC115EU_SOT323-3 8 PQ26 6251VREF 2 3 2 1 2 IREF 1 .1U_0402_16V7K~D BATT+ 4 2 CHLIM 17 PR67 PL9 0.02_2512_1% 10UH_PCMB104T-100MS_6A_20% 1 2 CHG 1 PC145 10U_0805_25V6K~D UGATE 2 PR65 2.2_0603_5%~D <48> 2 1 VREF LX_CHG ACPRN @ PQ68 2N7002KW 1N SOT323-3 PC84 10U_0805_25V6K~D PHASE 18 ACPRN 2 ICM 1 19 2 G PC44 10U_0805_25V6K~D CSIP 1 <46> S 1 7 2 VIN 2PACIN PACIN G @ PQ23 2N7002KW 1N SOT323-3 2 6 V1 2 PC43 10U_0805_25V6K~D 2 4 S 1 PR66 100_0402_1% 1 1 PR63 100K_0402_5%~D 1 D 2 2 2 PR62 20_0603_5% PC38 0.1U_0603_50V7K~D <40,46> D PC46 10U_0805_25V6K~D VCOMP 20 PR61 20_0603_5% PQ22 PDTC115EU_SOT323-3 PR69 4.7_1206_5%~D CSIN CSOP 2 1 S <40> ACOFF ICOMP CSON 2 ACOFF 2 PC45 680P_0402_50V7K~D 5 ADP_I PQ25 2N7002KW 1N SOT323-3 PR71 68.1K_0402_1%~D G ACOFF 1 2 2 ACON <40,46> 1 2 2 10K_0402_1%~D 1 <48> PC41 3 <46> 100K_0402_1%~D 1 1 2 21 1 PC34 0.047U_0603_16V7K~D 1 1 22 1 PACIN <40,45> D CSOP @ PD16 1SS355TE-17_SOD323-2 2 AO4466L_SO8~D 1 CELLS 23 VIN @ PR55 200K_0402_1%~D 1 PC33 0.1U_0603_50V7K~D ACPRN ACPRN PR60 20_0603_5% 1 2 2 CSON PR53 15.4K_0402_1%~D 2 2 PR54 10K_0402_1%~D 2 PR64 EN 1 3 2 1 PC39 1 PACIN 3 ACSET ACPRN DCIN 24 6800P_0402_25V7K~D 0.01U_0402_25V7K~D <46> 6251_EN DCIN 2 PC37 1 PR68 47K_0402_5% 2 VDD 1 3 S 1 4 2 PQ21 2N7002KW 1N SOT323-3 G 2 3S/4S# 3 3 1 2 @ PQ20 PDTC115EU_SOT323-3 <40> PR59 150K_0402_1%~D D PR58 PR57 47K_0402_5% 2 2 PC32 .1U_0402_16V7K~D 2 1 2 V1 1 PR51 47K_0402_1%~D @ PD15 1SS355TE-17_SOD323-2 ACOFF 1 2 ACSETIN 2 1 PU2 1 1 6251VDD 2 2 2 2 FSTCHG 1 1 <40> PQ18 PDTA144EU_SOT323-3 PC31 1000P_0402_25V7K PR47 2 PR56 10K_0402_5%~D 1 1 1 47K PR52 10_1206_5%~D PD14 1SS355 SOD323 2 1 3 PR50 191K_0402_1%~D 2 ACSETIN @ PR49 0_0402_5% 1 2 2 1 PC30 2.2U_0603_10V7K~D 1 PC29 5600P_0402_25V7K~D 6251VDD @ PR46 0_0402_5%~D 1 1 RB751V40 SC76 PD13 1 PR48 200K_0402_1%~D 2 1 2 3 2 PC24 0.1U_0603_50V7K~D S 47K 5.075V VIN1 2 CSIP VIN PQ13 AOD403_TO252-3~D PQ16 AOD403_TO252-3~D 2 CSIN 2 CHG_B+ PL8 HCB2012KF-121T50_0805 1 PC27 0.1U_0603_50V7K~D 2 1 1 D G 1 1 2 1 PR131 3 200K_0402_1%~D 1 PR130 3.3_1210_5%~D 2 2 1 2 3 1 G 3.3_1210_5%~D 2 PL17 1.1UH_LFA915AY-H-1R1M=P3_4.07A_20%~D S 3 G PC35 2.2U_0805_25V 4 D D PQ17 AOD403_TO252-3~D PQ19 PDTC115EU_SOT323-3 2 1 2 G PQ15 AOD403_TO252-3~D S 1 PR45 0.005_2512_1% P3 3 PC26 4.7U_0805_25V6-K~D 1 2 2 1 1 G S D G VIN 2 @ PC82 2200P_0402_50V7K~D 2 PC25 4.7U_0805_25V6-K~D PQ14 AOD403_TO252-3~D 2 D S @ PJP11 JUMP_43X118 3 3 2 G 6251VDD PQ48 2N7002KW 1N SOT323-3 2 PR78 47K_0402_1%~D PR80 10K_0402_1%~D PR79 10K_0402_1%~D PACIN 1 2 ACIN <14,18,37,40,43> 1 2 2 PR77 100K_0402_1%~D 2 1 1 CHGVADJ 1 <40> 1 PR76 57.6K_0402_1%~D 1 CP mode PR81 14.3K_0402_1%~D Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05) <48> ACPRN ACPRN 2 3 2 Vaclim=2.87*((11.5K//152K)/((2.87K//152K)+(11.5K//152K))) CC=0.22~4.62A IREF=1*Icharge 4 ACSET=16.89V CHGVADJ IREF=0.22V~3.294V PQ28 PDTC115EU_SOT323-3 CV mode 4 0V 4V per cell 1.882V 4.2V per cell 3S/4S# signal High 3S Low 4S Issued Date 3.294V 4.35V per cell Compal Electronics, Inc. Compal Secret Data Security Classification 2009/2/6 Deciphered Date 2010/2/6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title CHARGER Size Date: A B C Document Number Tuesday, January 17, 2012 Rev 0.1 ULV D Sheet 47 of 65 4 3 Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO TPS51125_B+ 1 1 2 1 1 2 1 2 @ PR118 100K_0402_1%~D G S SIR472DP-T1-GE3_POWERPAK8-5~D 5 1 PQ30 2 1 2 PC85 4.7U_0805_25V6-K~D 3 2 1 + 2 1 + 2 @ PC207 330U_D_6.3VM_R18M~D PR91 1 2 PC64 680P_0402_50V7K~D 4.7_1206_5%~D 1 2 SI7170DP-T1-GE3_POWERPAK8-5~D 5 PQ32 3 2 1 PC66 22U_0805_6.3V6M~D Typ: 175mA 1 PC63 330U_D_6.3VM_R18M~D 1 2 PC57 0.1U_0603_25V7K~D 1 2 PC56 2200P_0402_50V7K~D 1 2 PC54 4.7U_0805_25V6-K~D 2 1 4 18 NC PU3 RT8205LZQW(2)_WQFN24_4X4 +5VALWP 2 B 1 3 2 2 @ PJP2 1 1 2 JUMP_43X118 @ PQ70 SSM3K7002FU_SC70-3~D 2 2 1 1 2 1 1 JUMP_43X118 @ PJP3 @ PJP5 +3VALWP +5VALWP +3VALW 2 2 1 1 +5VALW JUMP_43X118 JUMP_43X118 @ PQ69 DTC115EUA_SC70-3 Security Classification 3 Issued Date Compal Electronics, Inc. Compal Secret Data 2009/2/6 Deciphered Date 2010/2/6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 9/2 for EC power rail 5 1 @ PJP4 @ PC68 0.01U_0402_25V7K~D 2 EC_ON ENTRIP1 3 VIN 1 1 2VREF_51125 S 2 1 D 2 2 A <40,43> LG_5V PL11 2.2UH_FDVE1040-2R2M=P3_14.2A_20%~D 2 @ PR99 40.2K_0402_1%~D 1 1 LX_5V 19 1 2 3 ACPRN 20 2 2 PR89 2.2_0603_1% PR100 2.2K_0402_5%~D 1 @ PR98 100K_0402_1%~D 1 <47> UG_5V PQ34 PDTC115EU_SOT323-3 EC_ON VS BST_5V 1 PR97 100K_0402_1%~D <41,45,46> MAINPWON <40,43> 22 21 C 1 2 VL PQ33A DMN66D0LDW-7_SOT363-6~D G 4 S D 2 <45> PC60 0.1U_0603_25V7K~D VL 2 1 2 2 6 3 5 G SPOK 1 @ PR94 0_0402_5% PC67 0.1U_0603_25V7K~D 2 ENTRIP2 1 TPS51125_B+ PQ33B DMN66D0LDW-7_SOT363-6~D 17 16 EN 13 1 B D FB1 REF LGATE1 VREG5 PHASE1 LGATE2 2 2 @ PR96 499K_0402_1%~D 1 4 PHASE2 24 23 2 PR95 499K_0402_1%~D 1 TONSEL UGATE1 GND 12 BOOT1 VFB=2.0V UGATE2 15 11 2 Pre_V 2 PR93 100K_0402_1%~D VS 5 6 LX_3V BOOT2 SKIPSEL 2 BST_3V 9 PR88 2.2_0603_1% UG_3V 10 PGOOD @ PR92 499K_0402_1%~D 1 FB2 VREG3 1 1 LG_3V VO1 14 PQ31 1 2 3 SI7170DP-T1-GE3_POWERPAK8-5~D 1 2 <41,45,46> MAINPWON B+ ENTRIP1 ENTRIP2 1 2 PC58 4.7U_0805_10V6K~D PQ29 5 2 VO2 8 @ PR205 0_0402_5% 4 2 4 PC59 0.1U_0603_25V7K~D 1 2 PC62 680P_0402_50V7K~D PR90 4.7_1206_5%~D 2 + P PAD 7 2 1 PR87 93.1K_0402_1%~D 2 25 5 1 +3VALWP TPS51125_B+ 2 ENTRIP1 PR86 57.6K_0402_1%~D PC65 1U_0603_25V6-K~D PL10 2.2UH_FDVE1040-2R2M=P3_14.2A_20%~D 2 PR85 20K_0402_1%~D 1 1 2 3 SIR472DP-T1-GE3_POWERPAK8-5~D 1 C 4 +5VALWP 2 PR84 20K_0402_1%~D 1 2 2 1 PC53 2200P_0402_50V7K~D 1 2 PC52 4.7U_0805_25V6-K~D 1 2 PR83 30K_0402_1%~D 1 2 D ENTRIP2 +3VLP 2 PC61 330U_D_6.3VM_R18M~D PR82 13K_0402_1%~D 1 Typ: 175mA PC51 4.7U_0805_25V6-K~D 1 PC50 0.1U_0603_25V7K~D B+ PL18 FBMA-L11-453215800LMA90T_2P 1 PC49 1U_0603_25V6-K~D +3VALWP 1 5VALWP TDC 13.9A Peak Current 19.8A OCP current 23.8A H/S RDS(on) 12.2m ohm(typ),15m ohm(max) L/S RDS(on) 3.6m ohm(typ),4.5m ohm(max) FSW 375KHz 2VREF_51125 3.3VALWP TDC 8.8A Peak Current 12.5A OCP current 15.A H/S RDS(on) 12.2m ohm(typ),15m ohm(max) L/S RDS(on) 3.6m ohm(typ),4.5m ohm(max) FSW 375KHz D 2 PC55 4.7U_0805_25V6-K~D 5 4 3 2 Title +5VALWP/+3VALWP Size Document Number Custom Date: Tuesday, January 17, 2012 Rev 0.1 Sheet 1 48 of 65 A A B C D +VCCPP TDC 10.7A Peak Current 15.3A OCP current 18.3A H/S RDS(on) 12.2m ohm(typ),15m ohm(max) L/S RDS(on) 2.7m ohm(typ),3.3m ohm(max) FSW 300KHz 1 1 @ PJP6 VCCP_RT8290B_B+ 2 2 1 1 B+ 3 2 1 DL_VCCP 4 11 TP PQ36 +5VALW PC77 4.7U_0805_10V6K~D 2 2 PR121 470K_0402_1% 1 2 3 1 1 TPS51212DSCR_SON10_3X3 @ PC79 1000P_0402_50V7K +3VS @ PR108 162K_0402_1%~D PR109 4.99K_0402_1%~D 2 1 1 2 1 S 2 2 VCCIO_SENSE 1 2 PC73 4.7U_0805_25V6-K~D 1 2 1 PC72 4.7U_0805_25V6-K~D <8> 1 2 PQ37 2N7002KW 1N SOT323-3 PC81 0.01U_0402_25V7K~D 1 @ PR116 2 100K_0402_5% G 3 @ PR112 0_0402_5%~D 1 2 1 <9> VCCP_PWRCTRL D 2 VCCIO_VFB 2 PR110 10K_0402_1%~D 3 1 PR115 0_0402_5% 1 1 1 PR113 10K_0402_5%~D + 2 @ PR107 1.2K_0402_1% 2 2 1 2 PC71 4.7U_0805_25V6-K~D 2 PC76 1 220U_D2_4VY_R15M~D 6 1 PR105 0_0402_5% +VCCPP 2 PR104 22_0402_5% 2 1 2 DRVL LX_VCCP 7 PL12 1UH_FDV0630-1R0MN_11A_20% 1 1 RF 8 2 2 V5IN PC74 0.1U_0603_25V7K~D BST_VCCP-1 1 SW VFB DH_VCCP 2 1 5 EN 2 2 4 @ PC75 @PC75 .1U_0402_16V7K~D 9 1 PR103 4.7_1206_5%~D 3 @ PR194 300K_0402_5%~D DRVH BST_VCCP 2 2 TRIP 10 @ 1 2 VBST 680P_0402_50V7K~D PC80 1 SUSP# 2 1 <9,21,40,42,43,50,51> 1 2 1 PGOOD SIR818DP-T1_POWERPAK-SO8-5~D PR101 0_0402_5% 1 5 PR102 2.2_0603_1% PU4 PR106 43K_0402_1%~D @ PC83 0.1U_0402_10V7K 4 2 SIR472DP-T1-GE3_POWERPAK8-5~D 5 2 PQ35 1 @ PR117 10K_0402_1%~D 1 +3VALW 2 2 10K_0402_1%~D 2 PR114 1 <52> VTTPWRGOOD PC70 2200P_0402_50V7K~D PC69 0.1U_0603_25V7K~D JUMP_43X118 3 PJP7 2 @ VCCP_PWRCTRL 0 1 VCCPP Vout 1.05V 1.07V(reserve) 2 @ 2 1 1 JUMP_43X118 PJP8 +VCCPP 2 1 +VCCP 1 JUMP_43X118 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/2/5 Deciphered Date 2008/6/05 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title +VCCPP Size Document Number Custom Date: A B C Rev 0.1 Sheet Tuesday, January 17, 2012 D 49 of 65 A B C D 1 1 +1.8VSP TDC 0.9A Peak Current 1.2A OCP current 3A 1 PR129 10K_0402_1% 1 2 PC95 22U_0805_6.3VAM 1 2 SY8033BDBC_DFN10_3X3 PC93 22U_0805_6.3VAM 2 PR128 20K_0402_1% PC96 22P_0402_50V8J 1 1 1.8VSP_FB @ 2 2 1 @ 1 @ PR195 47K_0402_5% 7 11 EN_1.8VSP 2 2 2 PR122 0_0402_5% PC91 0.1U_0402_10V7K 1 SUSP# 1 <9,21,40,42,43,49,51> +1.8VSP 1 EN 6 2 2 FB TP 2 1 SVIN NC 5 3 2 8 1.8VSP_LX PR124 4.7_1206_5% @ JUMP_43X118 PC88 22U_0805_6.3VAM LX 2 2 1 1 PVIN 2 @ 2 9 1 LX SNUB_1.8VSP PJP12 2 PVIN PC97 680P_0603_50V7K 10 NC 1.8VSP_VIN 2 1 1 PL13 1UH_PH041H-1R0MS_3.8A_20% 4 PU6 HCB1608KF-121T30_0603 PG PL16 +3VALW 3 3 PJP13 +1.8VSP 2 @ 2 1 1 +1.8VS JUMP_43X118 4 4 Compal Secret Data Security Classification Issued Date 2008/2/5 Deciphered Date 2008/6/05 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title +1.8VSP Size Document Number Custom Date: A B C Compal Electronics, Inc. Rev 0.1 Sheet Tuesday, January 17, 2012 D 50 of 65 A B C D @ PJP14 JUMP_43X118 1.5VP_RT8290B_B+ BST_1.5VP 1 2 21 PAD 1 2 PC117 4.7U_0805_6.3V6K~D 2 20 VTT 19 BOOT LGATE PU7 @ 1 2 15 18 1 1 VLDOIN 1 VTTGND PR162 1K_0402_1% DH_1.5VP 1 3 2 2 PR158 1K_0402_1% 5 VDDQ 6 7 8 10 2 PR144 @ PC163 3300P_0402_50V7K~D 1 PR149 1 +3VALW PR136 5.1_0603_5%~D +5VALW PQ46 PMST3906_SOT323-3~D 1 PR137 7.15K_0402_1% 1 FB VDD PC115 .1U_0402_16V7K~D 4 VTTREF 2 VDDP 3 GND RT8207MZQW_WQFN20_3X3 S3 1 1 11 CS S5 12 TON 13 PGOOD CS_1.5VP VDDP_1.5VP 2 1 2 3 PC107 4.7U_0805_10V6K~D VTTSNS 9 5 1 2 PC108 680P_0402_50V7K~D 2 2 +5VALW DL_1.5VP 4 1 + PQ41 FDMS0309S_POWER56-8-5 PR135 4.7_1206_5%~D 220U_D2_4VY_R15M~D 220U_D2_4VY_R15M~D 2 PC169 1 PGND B + LX_1.5VP 2 E PC105 14 1 2 17 16 PR134 0_0603_5% 2 BST_1.5VP_2 UGATE 1 PHASE 1 PC116 4.7U_0805_6.3V6K~D DL_1.5VP PC104 0.1U_0603_25V7K~D 1 2 3 PL14 0.47UH_FDVE0630-H-R47M=P3_17.7A_20% 1 2A +0.75VSP 4 2 0.75VSP TDC 1.4A Peak Current +1.5VP 1 1 PQ40 FDMS7696A_POWER56-8-5 1 +1.5VP 2 PC109 JUMP_43X118 4.7U_0805_6.3V6K~D 2 5 1 2 PC98 0.1U_0603_25V7K~D 1 2 PC99 2200P_0402_50V7K~D 1 2 PC100 4.7U_0805_25V6-K~D 1 2 2 @ PC101 4.7U_0805_25V6-K~D 1 1 1 2 PC102 4.7U_0805_25V6-K~D 2 C B+ @ PJP18 2 1 1.2K_0402_1%~D 2 1 2 PR139 10K_0402_1%~D 1K_0402_1% 2 +1.5VP 2 2 2 2 PR132 1M_0402_1%~D PR150 1K_0402_1% 2 2 1 +3VALW 1 2 2 1 D S 2 @ PR143 10K_0402_5%~D 2 2 1.65V 0 1 1.6V 1.55V 1 1.5V (Default) PR152 10K_0402_5%~D 2 1 +0.75VS PR156 10K_0402_5%~D JUMP_43X118 1 2 2 D 2 @ 1 @ PR155 10K_0402_5%~D 1 S PQ44 2N7002KW 1N SOT323-3 S 3 1 2 PJP16 JUMP_43X118 3 @ 1 2 +1.5V 2 2 2 +0.75VSP G 2 G PJP19 2 2 1 1 1 1.5VDDR_VID1 2 PQ45 D 1N SOT323-3 2N7002KW PC119 0.01U_0402_25V7K~D 1 1 2 @ PR151 10K_0402_5%~D 2 PJP15 JUMP_43X118 @ @ 1 2 1 1 0 1 1 1 PR147 75K_0402_1%~D +3VALW 1 <16,19> @ 3 +3VALW PR153 10K_0402_5%~D +1.5VP PC110 0.01U_0402_25V7K~D PQ43 2N7002KW 1N SOT323-3 PQ42 2N7002KW 1N SOT323-3 1 0 2 1 1 2 +1.5VP TDC 14.4A Peak Current 20.6A OCP current 24.7A H/S RDS(on) 12.2m ohm(typ),15m ohm(max) L/S RDS(on) 2.7 ohm(typ),3.5m ohm(max) FSW 300KHz 0 PC111 0.01U_0402_25V7K~D DDR Vout 2 1.5VDDR_VID0 3 1 2 G @ PR148 10K_0402_5%~D DDR GPIO Output Voltage Selection 1.5VDDR_VID1 S @ PR146 10K_0402_5%~D 2 D 2 1 1.5VDDR_VID0 1 2 <16,19> 2 PC118 .1U_0402_16V7K~D PR145 10K_0402_5%~D 3 G 1 SUSP# PC78 1000P_0402_25V7K 1 2 PR154 10K_0402_5%~D <9,21,40,42,43,49,50> PR142 10K_0402_5%~D 1 PR141 150K_0402_1%~D +3VALW 3 @ PC103 @PC103 .1U_0402_16V7K~D 1 2 @ PR193 300K_0402_5%~D PC120 0.01U_0402_25V7K~D 1 1 1 SYSON 1 <40,42,43> 1.5VP_RT8290B_B+ 1 PR133 0_0402_5% PR140 10K_0402_1%~D 2 PC106 1U_0603_25V6-K~D 2 1 1 1 PJP17 JUMP_43X118 4 1 1 2 4 2 Compal Secret Data Security Classification Issued Date 2008/2/5 Deciphered Date 2008/6/05 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title +1.5VSP/0.75VSP Size Document Number Custom Date: A B C Compal Electronics, Inc. Rev 0.1 Sheet Tuesday, January 17, 2012 D 51 of 65 5 4 3 2 1 +VCCP D 1 <9> H_FC_C22 1 @PR163 @ PR163 10K_0402_1%~D The 1k PD on the VCCSA VIDs are empty. These should be stuffed to ensure that VCCSA VID is 00 prior to VCCIO stability. 1 @ PR161 10K_0402_1%~D @ PR262 0_0402_5%~D VID [0] 0 0 1 1 2 2 D VID0_SA 2 PR176 1K_0402_5%~D @ PR166 0_0402_5%~D 1 <9> VCCSA_SEL 2 +3VS VID1_SA 2 VID[1] 0 1 0 1 VCCSA Vout 0.9V 0.8V 0.725V 0.675V output voltage adjustable network 1 1 VID1_SA PR168 100K_0402_5%~D +VCCSAP TDC 4.2A Peak Current VID0_SA 1 PR157 10_0402_1%~D 2 2 1 2 PR261 0_0402_5%~D 1 PC121 1U_0603_10V6K~D +5VALW 1 PC122 2.2U_0603_10V7K~D 2 C VTTPWRGOOD <49> SW 24 7 2 1 2 PC159 22U_0805_6.3V6M~D @ 1 1 PC157 22U_0805_6.3V6M~D 2 2 1 2 1 1 2 2 2 1 @ PC156 2200P_0402_50V7K~D @ PC131 680P_0603_50V7K~D PC155 22U_0805_6.3V6M~D VIN PC154 22U_0805_6.3V6M~D 8 1 SW 23 +VCCSAP PC153 0.1U_0402_25V6K~D 9 2 SW VIN PC130 22U_0805_6.3V6M~D TPS51461RGER_QFN24_4X4~D @ PR165 4.7_1206_5%~D 1 1 10 PC129 22U_0805_6.3V6M~D EN 14 VID0 VID1 15 13 11 PC128 0.1U_0603_25V7K~D PR159 +VCCSA_BT 1 2+VCCSA_BT_1 2 1 PL15 2.2_0603_5%~D 0.47UH_FDVE0630-H-R47M=P3_17.7A_20% +VCCSA_PHASE 2 1 PGND 22 MODE TP 25 6 SLEW VOUT 5 1 COMP VIN 3 +VCCSA_PWR_SRC 12 2 PC127 10U_0805_25V6M~D PC126 10U_0805_25V6M~D 1 2 SW 21 VREF 1 2 16 SW GND 2 2 1 PGND 2 PAD-OPEN 43X118 PC125 2200P_0402_50V7K~D 1 2 @ PJP20 PC124 0.1U_0402_25V6K~D +3VALW BST PGND 20 1 PR125 0_0402_5%~D +VCCSA_EN PGOOD 19 17 18 V5DRV PU9 1 6A 1 2 V5FILT 1 2 4 C PR177 1K_0402_5%~D 2 +VCCSA_PWRGD <40> SA_PGOOD 2 PR173 0_0402_5%~D @ PR160 2 B 1 B 33K_0402_5%~D PR175 100_0402_5%~D PC132 VCCSA_VOUT 2 1 1 PR169 5.1K_0402_1%~D 2 1 1 2 VCCSA_SENSE <9> 2 1 1 2 PC152 3300P_0402_50V7K~D PR181 0_0402_5%~D PC133 0.01U_0402_25V7K~D 2 0.22U_0402_10V6K~D +VCCSAP PJP21 2 @ 2 +VCCSA 1 1 JUMP_43X118 A A Security Classification Issued Date Compal Secret Data 2009/12/01 Deciphered Date 2010/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. PWR-VCCSA_COREP Size C Date: Document Number Rev 0.1 Tuesday, January 17, 2012 Sheet 1 52 of 65 5 4 3 2 1 10/14 modify CSSUM PR41 75K_0402_1%~D Near to CSCOMP 2 1 PR42 165K_0402_1% Next to near controller 1 2 2 2 1 2 1 PC19 4700P_0402_25V7K~D 2 1 2 2 PC18 1500P_0402_7K~D 1 1 PR34 39K_0402_1% 2 2 1 1 PR286 1K_0402_1% PR37 4.7K_0402_1% 1 2 1 2 1 1 1 2 1 1 2 2 2 2 1 1 11 12 2 1 2 13 PC87 0.01U_0402_25V7K~D 1 2 1 39 <54> CSN4 <54> 1 2 CSN2 <54> CSP2 CSP2 <54> CSN3 CSN3 <54> CSP3 CSP3 <54> CSN1 CSN1 <54> CSP1 CSP1 DRVON <54> <54> PR319 10K_0402_1%~D 1 38 37 2 36 0.047U_0402_16V7K~D PC214 1 C 2 PR289 10K_0402_1%~D 1 35 34 PC40 0.047U_0402_16V7K~D 1 2 VBOOTA CSN2 0.047U_0402_16V7K~D PC229 2 PWMA/IMAXA TSENSEA CSP4 40 42 41 CSP4 CSN4 IOUT CSREF CSSUM 43 CSCOMP 45 44 CSSUM CSCOMP 47 48 46 DROOP ILIM COMP 50 51 52 49 FB TRBST VSN PWM4 ROSC 2 PR277 33 10K_0402_1%~D 32 PWM1 31 PWM3 30 PWM2 PWM4 29 <54> <54> 28 27 VCORE IMAX SET AT 99A VCORE VBOOT SET AT 0V NCP6151_VCC PWM ADDRESS PR273 76.8K_0402_1%~D PR297 10K_0402_1%~D PR267 10K_0402_1%~D 2 1 2 PC227 0.1U_0402_25V6K~D 1 2 1 2 TSENSE 6.65K_0402_1% PR316 100K_0402_1%_NCP15WF104F03RC PH6 B <54> <54> 2 14 near Power Stage heat source PWM2/VBOOT VCC VRMP CSN4 1 2 9.09K_0402_1%~D CSP4 2 0.047U_0402_16V7K~D PC220 CSNA 1 PR292 PWM3/IMAX ENABLE CSPA 1 10 2 PC226 1U_0402_6.3V6K~D PR39 10K_0402_1%~D 1 26 1 VR_RDYA 25 CPU_B+ 9 2 0_0402_5% NCP6151_VCC 2 PR266 1K_0402_1% CSN4 2 CSREF 1 2 1 1 PR268 PWM1/ADDR CSSUMA +5VS <40,41,55> VR_ON VR_RDY 24 PR293 2.2_0603_5%~D DRON NCP6151S52MNR2G_QFN52_6X6 IOUTA 8 CSP1 ALERT# 23 7 SCLK CSCOMPA 6 DROOPA 5 2 1.91K_0402_1% 22 54.9_0402_1% 1 PR317 CSN1 21 PR290 SDIO ILIMA 4 2 20 130_0402_1% 1 CSP3 COMPA <5,16,18> VGATE PR279 VR_HOT# TRBSTA +3VS 3 2 CSP2 19 <8,55> VR_SVID_CLK <8,55> VR_SVID_ALRT# For VR_SVID_DAT and CLK 51_0402_5% 1 CSN2 CSN3 18 <8,55> VR_SVID_DAT 2 PC1056 1U_0402_6.3V6K~D PR307 CSN3 1 PR305 10_0402_1% 2 PR320 27K_0402_1% PC218 1000P_0402_50V7K TSENSE DIFFOUTA <40,55> VR_HOT# 1 C 2 2 17 TSENSE 1 VSP FBA 0_0402_5%~D 1 VSPA VCORE_VSP 16 2 DIFFOUT 1 VCCSENSE 2 <8> +VCCP PC225 1000P_0402_50V7K FLAG / GND PU5 1 2 @ PR298 VSNA @ PR299 0_0402_5%~D 53 DIFFOUT 15 DIFFOUT 1 CSN2 1 PR40 10_0402_1% PC230 0.1U_0402_25V6K~D VCORE_VSN VSSSENSE 1 PR274 10_0402_1% 2 PR314 22K_0402_1%~D CSN1 1 PR276 10_0402_1% 1 <8> D 2 PC211 6800P_0402_25V7K 62K_0603_1% 2 PR38 8.2K_0402_1% 2 2 CSP4 1 PR281 PR315 2.32K_0402_1%~D 1 62K_0603_1% PR296 PC23 10_0402_1% 820P_0402_25V7K 2 PC174 820P_0402_50V7K 1 PR313 PC216 412_0402_1% 680P_0402_50V7K 2 PR303 1K_0402_1% 2 CSP3 1 PR280 1 PC223 22P_0402_50V8J~D 2 2 PC21 1000P_0402_50V7-K 2 D CSP2 62K_0603_1% 1 2 PR310 5.49K_0402_1%~D 1 PR43 2 2 1 PC224 220P_0402_25V 62K_0603_1% 2 1 1 PR312 47_0402_1% 1 PH7 220K_0402_5%_ERTJ0EV224J~D CSP1 1 PR44 B A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/10/09 Deciphered Date 2010/10/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title CPUCORE1 Size Document Number Custom Date: Rev 0.1 Tuesday, January 17, 2012 Sheet 1 53 of 65 5 4 VCC_core TDC 70A Peak Current 97.5A OCP current 117A Loadline = 1.9mohm 4 1 2 3 PC236 1U_0402_6.3V6K~D <53> CSP3 <53> CSN3 4 1 PC135 2 10U_0805_25V6K~D 1 2 PC244 10U_0805_25V6K~D 1 2 PC237 1U_0805_25V6K 5 PQ95 1 PQ94 6 5 2 GND DRVL NCP5911MNTBG_DFN8_2X2 PL29 0.36UH_ETQP4LR36AFC_28A_20%~D 1 VCC PR328 2.2_0603_1% 7 2 4 1 SW PR188 4.7_1206_5%~D PC140 680P_0402_50V7K~D EN SIR818DP-T1_POWERPAK-SO8-5~D SIR472DP-T1-GE3_POWERPAK8-5~D 3 4 DRVH2 DRVH2 8 3 2 1 5 9 5 2 +5VS 1 4.02K_0402_1%~D 2 DRVON DRVH PQ96 1 2 3 <53> FLAG PWM 3 2 1 PR324 +VCC_CORE 4 BST 5 2 1 10U_0805_25V6K~D 2 1 10U_0805_25V6K~D PC134 1 2 PC248 PC249 1U_0805_25V6K SIR472DP-T1-GE3_POWERPAK8-5~D 2 1 2 1 4 1 3 PU13 2 SIR818DP-T1_POWERPAK-SO8-5~D SIR472DP-T1-GE3_POWERPAK8-5~D 1 2 3 4 4 1 PWM2 PQ93 2 0.22U_0603_25V7K~D PR333 2.2_0603_1% <53> 2 PC239 1U_0402_6.3V6K~D PQ91 PR187 PC139 4.7_1206_5%~D 680P_0402_50V7K~D 1 5 1 PQ90 5 NCP5911MNTBG_DFN8_2X2 2 DRVL 7 6 1 GND PC238 1 PL28 0.36UH_ETQP4LR36AFC_28A_20%~D 2 SW VCC 4 3 2 1 DRVH3 8 SIR818DP-T1_POWERPAK-SO8-5~D EN PR329 2.2_0603_1% 2 9 5 DRVH PQ92 1 2 3 FLAG PWM 3 2 1 3 4 1 4 BST SIR818DP-T1_POWERPAK-SO8-5~D 1 SIR472DP-T1-GE3_POWERPAK8-5~D DRVH3 PU17 2 PR332 1 4.02K_0402_1%~D DRVON 2 2 PQ89 2 0.22U_0603_25V7K~D 5 1 5 PC250 1 2 +5VS 1 CPU_B+ PWM3 D 2 CPU_B+ PR335 2.2_0603_1% <53> 3 <53> CSP2 <53> CSN2 4 1 3 2 D +VCC_CORE CSP1 <53> CSN1 NCP5911MNTBG_DFN8_2X2 PC235 1U_0402_6.3V6K~D 4 PQ103 4 1 PC137 2 10U_0805_25V6K~D 1 2 10U_0805_25V6K~D PC247 1U_0805_25V6K 1 2 PC251 5 1 PQ102 2 DRVL 6 5 C PL31 0.36UH_ETQP4LR36AFC_28A_20%~D 1 GND 7 3 2 1 5 DRVH4 8 PR190 4.7_1206_5%~D PC142 680P_0402_50V7K~D VCC PR326 2.2_0603_1% SW 2 4 1 DRVH EN SIR472DP-T1-GE3_POWERPAK8-5~D 3 4 5 2 +5VS PWM 3 2 1 PR327 1 4.02K_0402_1%~D DRVON 2 SIR472DP-T1-GE3_POWERPAK8-5~D DRVH4 2 +VCC_CORE 9 5 1 PC136 2 10U_0805_25V6K~D 1 2 PC246 1 2 1U_0805_25V6K PC241 <53> 2 FLAG SIR818DP-T1_POWERPAK-SO8-5~D 4 1 3 4 BST PQ104 1 2 3 1 2 3 4 4 PU15 1 1 2 3 PC245 1U_0402_6.3V6K~D PQ99 2 SIR818DP-T1_POWERPAK-SO8-5~D 5 NCP5911MNTBG_DFN8_2X2 2 5 1 PQ98 1 PWM4 1 DRVL 7 6 2 PR331 2.2_0603_1% SW GND 1 VCC <53> PQ101 2 0.22U_0603_25V7K~D PR336 2.2_0603_1% PL30 0.36UH_ETQP4LR36AFC_28A_20%~D 2 EN PC252 1 2 DRVH1 8 10U_0805_25V6K~D 9 PR189 PC141 4.7_1206_5%~D 680P_0402_50V7K~D DRVH SIR472DP-T1-GE3_POWERPAK8-5~D 3 4 1 +5VS 1 4.02K_0402_1%~D 2 1 FLAG PWM 3 2 1 PR325 DRVON 2 BST CPU_B+ SIR818DP-T1_POWERPAK-SO8-5~D 2 3 2 1 1 4 5 2 PWM1 4 5 1 <53> PU14 PQ100 1 2 3 PR334 2.2_0603_1% C PQ97 2 0.22U_0603_25V7K~D SIR818DP-T1_POWERPAK-SO8-5~D 1 5 PC242 SIR472DP-T1-GE3_POWERPAK8-5~D DRVH1 CPU_B+ <53> CSP4 <53> CSN4 4 1 3 2 +VCC_CORE B B B+ PL22 FBMA-L11-453215800LMA90T_2P 2 1 2 1 PC259 0.1U_0603_25V 2 2 PC258 + PC243 330P_0402_50V7K~D 2 1 100U_25V_M~D 1 PC257 + 100U_25V_M~D CPU_B+ 1 @ 2 PC240 680P_0402_50V7K~D 1 2 PC234 680P_0402_50V7K~D 1 @ A A Security Classification Issued Date Compal Electronics, Inc. Compal Secret Data 2009/10/09 Deciphered Date 2010/10/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title CPUCORE2 Size Document Number Custom Date: Rev 0.1 Tuesday, January 17, 2012 Sheet 1 54 of 65 5 4 3 2 1 10/14 modify, non CIS parts 10/14 modify Next to near controller CSSUM2 1 1 PC1042 180P_0402_50V8J~D 2 1 2 PR628 4.12K_0402_1%~D PC1043 2200P_0402_50V7K 1 1 2 1 220K_0402_5%_ERTJ0EV224J 2 PH3 1 2 2 PR631 1K_0402_1% 1 2 PR632 4.7K_0402_1% PR639 2K_0402_1% 1 1 2 1 2 1 <56> 2 32 PWM5 CSP5 CSP5 DRVON2 <56> <56> 31 PWM6 PC1055 0.047U_0402_16V7K 1 2 PR650 4.87K_0402_1%~D PWM5 PWM6 <56> <56> IMAX_AXG NCP6131_VCC 1 VCORE VBOOT SET AT 0V PR678 36K_0402_1% PWM ADDRESS 1 GFX CORE IMAX SET AT 50A PR677 22K_0402_1%~D 2 2 PR660 10K_0402_1% 2 27 CSNA CSPA CSSUMA CSN5 1 41 40 NC NC CSREF IOUT 42 CSSUM2 43 CSCOMP2 45 44 CSSUM CSCOMP 47 48 46 DROOP ILIM COMP 50 51 49 FB TRBST 52 CSREF2 1 DRVON2 26 PC1060 0.01U_0402_50V7K <56> CSN5 28 VBOOTA 25 2 TSENSEA 24 1 VRMP 33 29 IMAX PWMA/IMAXA IOUTA 13 PWM2 ROSC 23 1U_0402_6.3V6K~D 2 <56> CSP6 30 VCC CSCOMPA 1 12 2 PR656 1K_0402_1% PC1059 11 DROOPA 1 2 9.09K_0402_1% PWM3/VBOOT ENABLE 22 1 PR654 VR_RDYA ILIMA 10 NCP6131_VCC 2 DRON PWM1/ADDR 14 1 VR_RDY CSN6 CSP6 C 2 34 CSP1 ALERT# 20 9 2 0_0402_5% PR653 2.2_0603_5% PC1058 0.1U_0402_25V6 1 1 2 1 PR652 1 PR646 4.87K_0402_1%~D SCLK NCP6131S52MNR2G_QFN52_6X6 CSN6 0.047U_0402_16V7K PC1054 35 CSN1 COMPA <40,41,53> VR_ON 36 SDIO TRBSTA 8 37 CSP3 19 6 38 CSN3 DIFFOUTA 5 39 CSN2 VRHOT# 18 <8,53> VR_SVID_CLK <8,53> VR_SVID_ALRT# 7 2 2 2 CSP2 17 4 <8,53> VR_SVID_DAT 2 CSN6 1 10_0402_1% PC1051 1000P_0402_50V8-J TSENSE FBA 3 <40,53> VR_HOT# VSP 16 2 VSPA 1 VSN GND VAXG_VSP TSENSE2 15 C DIFFOUT 2 2 1 PC1052 1000P_0402_50V8-J VSNA 1 PU1004 53 1 2 @ PR643 21 2 2 1 @ PR642 0_0402_5%~D 1 0_0402_5%~D 1 PR638 PC1050 0.1U_0402_25V6K 1 DIFFOUT2 <9> VCC_AXG_SENSE 6.65K_0402_1% PR649 2 PR637 1 8.2K_0402_1% 1 <9> VSS_AXG_SENSE 100K_0402_1%_NCP15WF104F03RC PH4 CSN5 1 10_0402_1% 2 2 2 VAXG_VSN CPU_B+_GFX 2 PR634 PR641 24.3K_0402_1% PR682 100_0402_1% +5VS 2 2 1 PR640 22K_0402_1% DIFFOUT2 TSENSE2 1 1 PC1048 820PF_0402_50V7K +VCC_GFXCORE_AXG PR672 100_0402_1% D 10_0402_1% 2 PC1049 4700P_0402_25V7K PC1047 4700P_0402_25V7K 2 2 1 1 2 2 1 PR636 412_0402_1% CSP6 1 36.5K_0603_1% PC1046 820PF_0402_50V7K PR633 1 Close to CPU 2 PR626 2 PC1044 560P_0402_50V7K PR630 1K_0402_1% 1 2 2 PC1041 560P_0402_50V7K 1 2 PC1045 10P_0402_50V8J 1 1 1 PR629 34K_0402_1% D 36.5K_0603_1% PR624 165K_0402_1% 2 1 PR627 24.9_0402_1% 2 CSP5 2 PR622 PR623 75K_0402_1% CSCOMP2 B B A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/02/08 Deciphered Date 2012/02/08 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Size C Date: GFXCORE1 HMA51_HR Document Number Tuesday, January 17, 2012 Sheet 1 Rev 0.1 55 of 65 5 4 VCC_GFXCORE TDC 38A Peak Current 46A OCP current 55A Loadline = 3.9mohm 2 2 +5VS 2 4.02K_0402_1%~D 1 3 4 1 DRVH EN SW VCC GND PR337 2.2_0603_1% DRVL 1 1 PC138 2 10U_0805_25V6K~D 1 PC253 2 10U_0805_25V6K~D 2 1 2 DRVH6 8 7 7 6 5 3 6 4 5 NCP5911MNTBG_DFN8_2X2 1 1 PC256 1U_0402_6.3V6K~D 2 2 PC254 1 PWM 9 8 DRVON2 DRVON2 FLAG 1 PWM6 BST 2 1 PR330 <55> PQ105 CSD87351Q5D_SON8~D PU16 2 PR191 PC143 4.7_1206_5%~D 680P_0402_50V7K~D 1 2 0.22U_0603_25V7K~D 1U_0805_25V6K PC255 PR338 2.2_0603_1% <55> 2 CPU_B+_GFX 1 D 3 1 4 2 3 D +VCC_GFXCORE_AXG PL32 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D <55> CSP6 <55> CSN6 CPU_B+_GFX FLAG PWM DRVH VCC PR342 2.2_0603_1% SW GND DRVL 1 2 PC161 10U_0805_25V6K~D 1 2 C DRVH5 7 3 6 4 7 6 5 5 NCP5911MNTBG_DFN8_2X2 2 1 PC151 1U_0402_6.3V6K~D 2 2 9 8 2 1 BST EN 4 1 1 +5VS 3 1 2 4.02K_0402_1%~D 1 8 DRVON2 1 2 PR341 <55> 2 PWM5 DRVON2 2 PQ107 CSD87351Q5D_SON8~D PU19 PR206 PC150 4.7_1206_5%~D 680P_0402_50V7K~D 1 <55> 2 0.22U_0603_25V7K~D PR340 2.2_0603_1% PC160 PC158 1 1U_0805_25V6K C <55> CSP5 <55> CSN5 1 4 2 3 +VCC_GFXCORE_AXG PL33 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D B B B+ PL23 FBMA-L11-453215800LMA90T_2P 1 2 CPU_B+_GFX A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/02/08 Deciphered Date 2012/02/08 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Size C Date: GFXCORE2 HMA51_HR Document Number Tuesday, January 17, 2012 Sheet 1 Rev 0.1 56 of 65 5 4 3 2 1 D D +VCC_CORE 1 +VCC_CORE 1 PC1218 10U_0805_6.3VAM 1 PC1222 10U_0805_6.3VAM PC1224 10U_0805_6.3VAM 2 1 PC1230 10U_0805_6.3VAM 2 PC1214 10U_0805_6.3VAM 2 1 PC1215 10U_0805_6.3VAM 2 5 x 22 μF (0805) 5 x (0805) no-stuff sites 2 @ PC1213 10U_0805_6.3VAM 1 2 +VCC_CORE 1 2 1 2 1 2 1 2 1 2 1 Socket Top 7 x 22 μF (0805) 2 x (0805) no-stuff sites 2 PC1243 22U_0805_6.3V6M PC1220 10U_0805_6.3VAM 2 1 PC1242 22U_0805_6.3V6M 1 Socket Bottom +VCC_GFXCORE_AXG_P PC1241 22U_0805_6.3V6M 1 2 PC1239 22U_0805_6.3V6M 1 2 PC1238 22U_0805_6.3V6M 2 PC1219 10U_0805_6.3VAM PC1237 22U_0805_6.3V6M 2 Below is 458544_CRV_PDDG_0.5 Table 5-8. 1 PC1217 10U_0805_6.3VAM PC1236 22U_0805_6.3V6M 2 1 PC1221 10U_0805_6.3VAM +VCC_GFXCORE_AXG +VCCP 2 +VCC_CORE 1 1 1 + + + 2 @ 1 2 @ 1 2 @ 1 + 2 1 2 @ 1 2 @ 1 + 1 2 @ 1 2 @ 1 2 @ 1 2 @ 1 2 @ 1 2 @ 1 2 B PC1284 22U_0805_6.3V6M @ PC1287 22U_0805_6.3V6M 1 PC1282 22U_0805_6.3V6M @ PC1205 470U_D2_2VM_R4.5M~D 2 2 1 1 PC1281 22U_0805_6.3V6M 2 2 @ PC1280 22U_0805_6.3V6M 2 PC1203 470U_D2_2VM_R4.5M~D 1 PC1279 22U_0805_6.3V6M 2 PC1201 470U_D2_2VM_R4.5M~D PC1278 22U_0805_6.3V6M PC1200 470U_D2_2VM_R4.5M~D PC1271 22U_0805_6.3V6M B @ 2 C PC1265 22U_0805_6.3V6M 1 2 1 PC1275 220U_D2_4VY_R15M~D @ PC1235 22U_0805_6.3V6M 2 + 2 PC1286 22U_0805_6.3V6M 2 1 1 PC1272 22U_0805_6.3V6M + 2 PC1264 22U_0805_6.3V6M 1 1 2 PC1263 22U_0805_6.3V6M 2 @ PC1234 22U_0805_6.3V6M 2 2 PC1262 22U_0805_6.3V6M 2 1 2 2 PC1261 22U_0805_6.3V6M @ PC1233 22U_0805_6.3V6M 2 2 PC1260 22U_0805_6.3V6M 2 1 PC1232 22U_0805_6.3V6M 2 PC1231 22U_0805_6.3V6M + PC1256 22U_0805_6.3V6M 1 2 1 PC1225 22U_0805_6.3V6M 1 1 PC1285 22U_0805_6.3V6M 2 1 PC1229 22U_0805_6.3V6M + 2 PC1270 22U_0805_6.3V6M 2 1 PC1228 22U_0805_6.3V6M 1 1 1 PC1276 330U_D2_2.5VM_R6M~D 1 PC1227 22U_0805_6.3V6M + 2 @ PC1277 220U_D2_4VY_R15M~D 2 1 1 1 1 PC1266 22U_0805_6.3V6M + 2 PC1269 22U_0805_6.3V6M 2 1 1 1 PC1273 22U_0805_6.3V6M PC1226 22U_0805_6.3V6M 2 PC1268 22U_0805_6.3V6M 2 1 1 PC1283 22U_0805_6.3V6M 1 PC1216 22U_0805_6.3V6M 2 PC1255 470U_D2_2VM_R4.5M~D 2 2 1 2 PC1267 22U_0805_6.3V6M 1 PC1212 22U_0805_6.3V6M @ PC1254 470U_D2_2VM_R4.5M~D 2 2 1 1 PC1274 22U_0805_6.3V6M 1 PC1223 22U_0805_6.3V6M @ PC1253 470U_D2_2VM_R4.5M~D 2 2 1 2 PC1259 22U_0805_6.3V6M 1 PC1207 22U_0805_6.3V6M PC1252 470U_D2_2VM_R4.5M~D 2 2 1 1 PC1258 22U_0805_6.3V6M 1 2 1 2 PC1251 22U_0805_6.3V6M 2 1 PC1249 22U_0805_6.3V6M C 1 PC1248 22U_0805_6.3V6M 2 PC1208 22U_0805_6.3V6M PC1247 22U_0805_6.3V6M 2 1 PC1211 22U_0805_6.3V6M PC1246 22U_0805_6.3V6M 2 1 PC1210 22U_0805_6.3V6M PC1245 22U_0805_6.3V6M 2 1 PC1206 22U_0805_6.3V6M PC1244 22U_0805_6.3V6M 2 1 PC1209 22U_0805_6.3V6M PC1257 22U_0805_6.3V6M 1 1 @ 1 + + 2 PC1204 2 PC1202 470U_D2_2VM_R4.5M~D 470U_D2_2VM_R4.5M~D A A Compal Secret Data Security Classification Issued Date 2008/09/15 Deciphered Date 2009/09/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. PWR - PROCESSOR DECOUPLING Size Document Number Rev 0.1 PBL21 LA6771P M/B Date: Tuesday, January 17, 2012 Sheet 1 57 of 65 5 4 VR_ON ADAPTER VTTPWRGOOD 3 NCP6151S(PU5) NCP6131S(PU1004) 2 1 +VCC_CORE +VCC_GFXCORE TPS51461 (PU9) +VCCSA D D SYSON B+ BATTERY SUSP# CHARGER ISL6251A (PU2) SUSP# SUSP# SUSP RT8207M (PU7) +1.5V RT8207M (PU7) AO4728L (Q20) +1.5VS CPU1.5V_S3_GATE +0.75VS SY8033 (PU6) +1.8VS TPS51212 (PU4) +VCCP AO4728L (QC3) +1.5V_CPU_VDDQ C C RT8205L (PU3) DGPU_PWR_EN# +VCCAFDI_VRM +3VMXM +5VALW SI4800BDY (Q30) SI4800BDY (Q31) SI3456BDV (Q212) SI3456BDV (QS1) +3VS +3V_PCH +3.3V_F347 +LAN_IO AO3413 (QH4) +5V_PCH SUSP BT_ON# LCDVDD_ON / EC_ENVDD EN_CAM SI2301BDS (QV12) SI2301BDS (Q1) RT9025 (U608) DGPU_PWR_EN# SI4800BDY (U18) SYSON# SUSP PCH_PWR_EN# EN_WOL# SUSP PCH_PWR_EN# SI4800BDY (U19) +5VMXM B SI4800BDY (Q26) TPS2062A (U45) TPS2062A (U42) +5VS +USB3_VCCB +USB3_VCCA ODD_EN# SUSP RT9013 (U8) B +3VALW SUSP B+_MXM1 SUSP B+_MXM SYSON# EC_ON SI3456BDV (QV6) SI3456BDV (Q2) SI3456BDV (QS1) +HDMI_5V_OUT +5VS_TP_LED +5VS_ODD AO3413 (QU1) A A +LCDVDD +3VS_CAM +1.2VS_HDMI +3VS_BT DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title Power Rail Size Document Number Date: Tuesday, January 17, 2012 Rev 1.0 LA-6561P Sheet 1 58 of 65 5 4 3 2 Version Change List ( P. I. R. List ) Item Page# Title Date Request Owner 1 Page 1 Issue Description Solution Description Rev. 1 52 PWR-VCCSA_COREP 10/05 Alan SMT NC part (PR262) BOM structure change to "Do Not Display" X01 2 45 BATTERY CONN/OTP 10/13 Alan EC detect the battery is insertion when only adapter in BATT_PRS pull high from +3VALW to +3VALW_EC 3 53 CPUCORE1 10/14 Alan For Intel VCORE test Change PC18=1500P X01 4 55 GFXCORE1 10/14 Alan For Intel Vgfx test Change PC1042=180P, PR628=4.12K, PC1041=560P, PR622=PR626=36.5K X01 5 47 CHARGER 10/17 Alan For charger voltage and current setting Change PR71=68.1K, PR75=12.7K, PR182=1.43K, PR45=0.005 X01 6 48, 51 3VALWP/5VALWP, +1.5VP/0.75VSP Alan Find tune OC setting Change PR86 =57.6K, PR87 =93.1K, PR137 =7.15K X01 7 45,46 DCIN/DECTOR Alan "US California Energy Efficiency" 8 46, 47 CHARGER 11/11 Alan NC revise parts NC: PD6, PQ23,PQ68, PD11, PD12, PQ20, X01 9 ** ALL 11/11 Alan Change source for affected by “Thailand flood” Refer to PT-Build_SMT MEMO X01 10 ** ALL 12/13 Alan 50 1.8VSP 12/14 Alan PL13 footprint is too small to find the 2nd source Change PL13 footprint for 2nd source X01 12/23 Alan PL18, PL22, PL23 footprint DFB modify to larger size PL18, PL22, PL23 update CIS PART X02 D D 11 C 12 48,54,56 DCIN/DECTOR 10/17 10/25 (Reserve 130mW for no battery mode) Change 0 ohm to short pad Refer to page 45 PR170, PR171 and page 46 modify X01 PR5, PR196, PR186, PR185, PR300, PR46, PR112, PR262, PR298, PR299, PR642, PR643 13 47 DCIN/DECTOR 12/24 Alan Revise PR164 for EE Jeffy request 14 45 OTP Value modify 01/11 Alan CPU OTP caculate and test value 93C not mach with schematic 90C X01 C X02 Double check with thermal team and agree change to 93C X02 B B A A Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 PWR-PIR1 Size Document Number Rev 0.1 LA-8321P Date: Tuesday, January 17, 2012 Sheet 1 59 of 65 5 4 SMBUS Address [TBD] 3 2.2K PCH SMBCLK C9 SMBDATA +3V_PCH PCH_SMBCLK 202 PCH_SMBDATA 200 2N7002 E14 C8 SML0CLK G12 SML0DATA DIMMA0 SMBUS Address [A0] DIMMB0 SMBUS Address [A4] DIMMA1 SMBUS Address [A2] DIMMB1 SMBUS Address [A6] CPUXDP SMBUS Address [TBD] PCHXDP SMBUS Address [TBD] 202 2.2K 53 51 +3V_PCH 2.2K System Thermal sensor EMC1412 200 D SMBUS Address [1111_100xb] 202 M16 53 2.2K SML1CLK SML1DATA 51 MXM Thermal sensor EMC1412 200 SMBUS Address [1011_100xb] 202 +3V_PCH 2.2K 200 2N7002 53 2N7002 +3VS 2.2K 2N7002 D 1 2.2K 2.2K H14 2 51 MXM1 Thermal sensor EMC1412 SMBUS Address [1101_100xb] 53 51 EC_SMB_CK2 111 EC_SMB_DA2 112 HDMI IN STDP6038 53 SMBUS Address [C0] 51 2.2K 4.7K +3VS C 2.2K C 4.7K 79 +3V_MXM1 2N7002 VGA_SMB_CK2 2N7002 VGA_SMB_DA2 80 MXM2 CONN 14 SCL2 SDA2 4.7K KBC 78 4.7K 13 NV MXM SMBUS Address: 0x98 0x9E 0x56 0x32 4.7K +3VALW 4.7K 77 G sensor SMBUS Address [TBD] +3V_MXM 2N7002 VGA_SMB_DA1 32 EC_SMB_DA1 MXM1 CONN SMBUS Address [32] WLAN CONN SMBUS Address [TBD] EXP CONN SMBUS Address [TBD] mSATA CONN SMBUS Address [TBD] 30 VGA_SMB_CK1 EC_SMB_CK1 LNG3DMTR SMBUS Address [TBD] 2N7002 7 SCL1 0 Ω SDA1 0 Ω 8 MXM_CUR_DAT B MXM Current Monitor B INA219 MXM_CUR_CLK KB930 30 SMBUS Address [1000_000xb] 32 0 Ω 0 Ω MXM Current Monitor INA219 BATT CONN SMBUS Address [1000_101xb] SMBUS Address [16] Combo JACK Mic. switch TS3A225 VPK_SMB_CK1 2N7002 A VPK_SMB_DA1 2N7002 NC NC 4 VPK MSP430F5508 SMBUS Address [TBD] A 2.2K 2.2K 5 SMBUS Address [76] DELL CONFIDENTIAL/PROPRIETARY +3VS Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 3 2 Title SMBUS TOPOLOGY Size Document Number Date: Tuesday, January 17, 2012 Rev 0.1 LA-8321P Sheet 1 60 of 65 5 4 3 2 1 Version Change List ( P. I. R. List ) Item Page# D C B Title Date Request Owner Issue Description Solution Description Rev. 1 34 SATA HDD 2011/10/4 Compal HDD EA fial Add HDD re-driver *3, Add RS11~RS37, US1~US3, CS51~CS68 X01 2 35 WLAN 2011/10/4 Compal LPC pin assignment error for 80 port Re-assignment pin X01 3 40 EC 2011/10/10 Compal There are double power source for EC Depop R464 X01 4 40, 18 PCH, EC 2011/10/10 Compal correct net name for not support deep S4/S5 Change net name from SUSWARN# to SUSPWRDNACK, Change net name from SUSWARN#_R to SUSPWRDNACK_R X01 5 28 DP SW 2011/10/10 Compal DP no function, because double CAP for MUX Delete C1069, C1070, C1071, C1072, C1073, C1074, C1075, C1076, C1079, C1109, C1127, C1128, C1138, C1139, C1140, C1141, C1203, C1204, C1205, C1206 X01 6 40 EC 2011/10/10 Compal Change board ID to V0.2 Change R466 from 0 ohm to 8.2K ohm X01 7 17 PCH 2011/10/11 Compal Sourcer require change crystal size to 3225 Change YH2 PN to SJ10000EF00 X01 8 31 GLAN 2011/10/11 Compal Sourcer require change crystal size to 3225 Change YL1 PN to SJ10000EF00 X01 9 44 VPK 2011/10/11 Compal Sourcer require change crystal size to 3225 Change YH3 PN to SJ10000DI00 X01 10 16 PCH 2011/10/11 Compal Sourcer require change crystal size to 3215 Change YH1 PN to SJ10000DM00 X01 11 40 EC 2011/10/11 Compal Sourcer require change crystal size to 3215 Change X1 PN to SJ10000DM00 X01 12 30 HDMI IN 2011/10/11 Compal Sourcer require change crystal size to 3225 Change Y5 PN to SJ10000970L X01 13 30 HDMI IN 2011/10/11 Compal Follow Vandor feedback modify CAP value of crystal Change C1751, C1750 from 27P to 12P X01 14 27 HDMI SW 2011/10/11 Compal HDMI eye diagram fail Add R2600, pop R1855, R1857 X01 15 34 SATA HDD 2011/10/12 Compal Add SATA re-driver co-lay circuit Add RS38~RS49, CS69~CS80 X01 16 5 PCH 2011/10/13 Compal PM_DRAM_PWRGD have glitch and leakage Change RC18 from 200 ohm to 10k ohm X01 17 44 VPK 2011/10/14 Compal Depop VPK function Depop CD75, C2011~C2015, RH137, CH100, CH101, YH3, R2, R227, R1607, R1578 C294, C1754, C1755, F6, R198, C1753, R197, R1823~R1825, R1837~R1840, R1843 X01 18 44 VPK 2011/10/14 Compal Sourcer require change arreay resister to single Delete RP1~RP6, add R2601~R2624 X01 19 40 EC 2011/10/14 Compal Sourcer require change arreay resister to single Delete RP7~RP12, add R2625~R2648 X01 20 19 PCH 2011/10/14 Compal Sourcer require change arreay resister to single Delete RPH1~RPH5, add RH267~RH285 X01 21 34 SATA HDD 2011/10/18 Compal Delete HDD3 SATA re-driver circuit Delete RS42~RS45, CS73~CR76, RS20~RS28, CS57~CS62, US2 X01 22 27 HDMI SW 2011/10/19 Compal Intel feedback change HDMI DDC pull high resister value Change R437, R438, R461, R462 from 4.7k ohm to 2.2k ohm X01 23 27 HDMI SW 2011/10/19 Compal Intel feedback change HDMI HPD implementation Depop Q264, R1741, R1742, C1058, R1743, add R2652 X01 D C B A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Changed-List History 1 Size Document Number Date: Tuesday, January 17, 2012 LA-8321P Sheet 1 Rev 0.1 61 of 65 5 4 3 2 1 Version Change List ( P. I. R. List ) Item Page# D C B A Title Date Request Owner Issue Description Solution Description Rev. 24 29 DMC SW 2011/10/19 Compal Intel feedback change DMC HPD implementation Delete R1236, R1237, Add R2649 X01 25 29 DMC SW 2011/10/19 Compal Intel feedback add DMC AUX PU/PD resister Add R2650, R2651 X01 26 9 CPU 2011/10/19 Compal Modify CPU DDR Vref circuit Delete QC5, RC76, RC77, change RC118 connect from +1.5V to +1.5V_CPU_VDDQ X01 27 22 PCH 2011/10/19 Compal Intel feedback follow PDDG Delete LH4, depop CH73 X01 28 22 PCH 2011/10/19 Compal Intel feedback follow PDDG Delete RH224, RH225, RH227 X01 29 21 PCH 2011/10/19 Compal Intel feedback follow PDDG Change LH9 to RH287 (0 ohm) X01 30 20 PCH 2011/10/19 Compal Intel feedback follow PDG Pop RH181, Add RH286 X01 31 33 Audio Amplifier 2011/10/20 Compal Audio Amplifier burned issue Add D74, D75, C2035, C2036 X01 32 33 Audio Amplifier 2011/10/21 Compal Audio Amplifier burned issue Change C932, C1102 connect from B+ to +AMP_VDD X01 33 32 Audio Jcak 2011/10/21 Compal Change JHP2 connector Change JHP2 footprint to SINGA_2SJ3062-000111F_6P-T X01 35 5 XDP 2011/10/21 Compal Depop CPU XDP Depop RC84~RC95, RC5~RC9, RC112, RC113, CC65, CC66 X01 36 16 XDP 2011/10/21 Compal Depop PCH XDP Depop RH1, RH3~RH10, RH12~RH21, RH24, RH51, CH1 X01 37 20, 26 PCH, CRT 2011/10/21 Compal CRT leakage Depop RH178, add RV115 X01 38 32 Audio Jcak 2011/10/22 Compal Change JHP2 connector from NC to NO Change JHP2 symbol, add RA24, depop R149, QU4 X01 39 29 DMC SW 2011/10/22 Compal DMC AUX channel pu/pd location error Change R2650, R2651 connect from U132 to CONN X01 40 32 AUDIO 2011/10/22 Compal Reserve for pop noise Add RA25~RA27, change U631 and U629 pin B2 connect to +3.3V_MUTE X01 41 34 ODD 2011/10/24 Compal Zero power ODD function Pop RS10 X01 42 28 DP SW 2011/10/24 Compal Vendor feedback DP MUX need CAP for input and output Add C1069, C1070, C1071, C1072, C1073, C1074, C1075, C1076, C1079, C1109, C1127, C1128, C1138, C1139, C1140, C1141, C1203, C1204, C1205, C1206 Change C1190~C1194, C1164, C1177, C1178, C1200, C1201 to 220nF X01 43 25 CCD 2011/10/24 Compal Reserve for EMI Add L101, depop RV10, RV51, change D61 connect to onnector side X01 44 28 DP SW 2011/10/24 Compal DP dongle can't display on UMA mode Change U633, delete C1200, C1201, add U634, C2037, C2038 Change C1203~C1206 from 0.22uF to 0.1uF Change AUX, DDC, HDP connect X01 45 43 PWR BTN 2011/10/24 Compal Avoid SW reverse at SMT NC SW1 pin 1 & pin 4 and SW2 pin 1 & pin 4 X01 46 30 HDMI IN 2011/10/24 Compal (STDP6038) doesn’t need to read / write the panel EDID de-pop R1880, R1881 X01 D C B A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Changed-List History 1 Size Document Number Date: Tuesday, January 17, 2012 LA-8321P Sheet 1 Rev 0.1 62 of 65 5 4 3 2 1 Version Change List ( P. I. R. List ) Item Page# D C Title Date Request Owner Issue Description Solution Description Rev. 47 30 HDMI IN 2011/10/24 Compal keep I2S_DAT/SPDIF_IN has fine performance change R1882 to C2039 0.1UF X01 48 30 HDMI IN 2011/10/24 Compal reserver these soltion to avoid I2S_DAT/SPDIF_IN signal has attenuation problem duo to long trance add U635, C2040 X01 49 32 Audio 2011/10/24 Compal change combo jack dection method de-pop R2585, pop R1244 X01 50 32 AUDIO 2011/10/24 Compal Reserve for pop noise Add C2041 X01 51 32 AUDIO 2011/10/24 Compal JACK_PLUG funcion reverse duo to JACK change to normal open type add R2653 and QU8 X01 52 32 AUDIO 2011/10/24 Compal vendor suggestion change R1752 to C2042 0.1UF X01 53 32 AUDIO 2011/10/25 Compal change combo jack dection circuit pop R149, QU4, depop RA24, change QU8 connect X01 54 32 AUDIO 2011/10/25 Compal HP fast plug in/out issue change RC107, RC114 to 1k ohm and pop X01 55 32 AUDIO 2011/10/25 Compal pop noise issue change RA20, RA21 to 0 ohm X01 56 32 AUDIO 2011/10/26 Compal pop noise issue change RA22, RA23 to 0 ohm X01 57 43 USB3.0 2011/10/26 Compal base on EA result, depop MB usb3.0 re-driver change C205~C208 to 0 ohm (R2654~R2657) and pop, pop C209~C212, R358~365 depop C100, C111~C113, C140, C156, C186, C187, C194~C196, C200, C2025~C2028, R374, R375, R378, R379, R416~R418, R421, U630, U632 X01 58 43 PWR BTN 2011/10/26 Compal "US California Energy Efficiency" (Reserve 130mW for no battery mode) Add Q305, Q306, R2658 X01 59 5 XDP 2011/10/26 Compal Depop CPU XDP Depop RC23~RC24, RC30~RC31, RC33~RC34, RC36~RC39 X01 60 32 AUDIO 2011/10/26 Compal HP fast plug in/out issue change RC109, RC115 to 1k ohm and pop X01 61 29 DMC 2011/10/26 Compal Reserve for DMC card Add R2659 X01 62 29 DMC 2011/10/26 Compal add ESD protect for DMC card change Q302 to SB00000EN00 X01 63 26 CRT 2011/10/27 Compal rise and fall time fail change LV1~LV3 from 75 ohm to 47 ohm X01 64 32 Audio 2011/10/27 Compal audio THD+N fail change C11, C14 to 2.2uF 0805 16V X01 65 40 EC 2011/11/09 Compal For Erp lot 6, reduce power consumption on S5 mode change R483, R493 from 10K to 100K ohm X01 66 26 CRT 2011/11/09 Compal For EMI test fail change LV1~LV3 from 47 ohm to 60 ohm X01 67 42 DC-DC 2011/11/09 Compal For PCH_PWR_EN leakage depop R556, pop R553 X01 68 28 DP 2011/11/25 Compal DP can't hot plug issue depop R2261 and R2262 X01 D C B B A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Changed-List History 1 Size Document Number Date: Tuesday, January 17, 2012 LA-8321P Sheet 1 Rev 0.1 63 of 65 5 4 3 2 1 Version Change List ( P. I. R. List ) Item Page# D C B Title Date Request Owner Issue Description Solution Description Rev. 69 34 HDD 2011/11/25 Compal SATA EA test fail pop RS13, RS14, RS31, RS32 X01 70 24 LCD 2011/11/30 Compal LCD EA test fail Change RV32 from 100 ohm to 47 ohm X01 71 26 CRT 2011/11/30 Compal CRT EA test fail Change LV4, LV5 from bead to 0 ohm, CV24, V25 from 10P to 4.7P X01 72 33 Audio 2011/11/30 Compal Audio amplifier fine tune Change R929, R939 from 16.5k ohm to 20.5k ohm, R1195 from 10k ohm to 14k ohm X01 73 16 Crystal 2011/11/30 Compal Crystal fine tune Change CH2 from 18P to 15P X01 74 17, 40 PCH, EC 2011/12/08 Compal Chang KB_DET# from PCH to EC (pin 34) Chang KB_DET# from PCH to EC (pin 34), DEL R1733, add R2660 X02 75 32 Audio 2011/12/08 Compal S3/S4/S5/G3 have noise when insert external speaker Add QA1, RA28, RA29 X02 76 40 EC 2011/12/08 Compal "US California Energy Efficiency" Add R2661, Q307 X02 77 34 ODD 2011/12/08 Compal ADD pull down resister for ODD_EJEECT# Add RS50 X02 78 34 ODD 2011/12/13 Compal Reduce 0 ohm delete RS6 X02 79 All All 2011/12/13 Compal Reduce 0 ohm change 0 ohm to short pad X02 80 32 Audio 2011/12/13 Compal change HP mute IC's power rail to +3VALW change HP mute IC's power rail to +3VALW, pop RA27, depop RA25 X02 81 43 IO CONN 2011/12/14 Compal add +5V_ALW pin for USB change JIO1 pin 13 to +5VALW, pin 14 to ground X02 82 40 44 SMBus 2011/12/15 Compal Battery can't charge when with N13-GS MXM card add R2662, R2663, depop R2583, R2584, Q304, Change R470, R473 to 4.7k X02 83 16-23 PCH 2011/12/16 Compal change PCH to QS sample change UH4 part number to SA00005AG1L X02 84 40 EC 2011/12/16 Compal Change board ID to V0.3 Change R466 from 8.2K ohm to 18K ohm X02 85 32 Audio 2011/12/19 Compal Modify line-in circuit Change R2550 connect to LINEIN_L_L1 X02 86 19 PCH 2011/12/19 Compal nVIDIA N-13 GE can't detect Change UH5 to SN74AHC1G08DCKR, RH230 to 0 ohm, depop R1908, pop RH231 X02 87 43 USB 3.0 2011/12/20 Compal delete USB 3.0 redriver and co-lay circuit delete U630, U632, C100, C111~C113, R1844, R1845, R424, R411~R418, R374, R375, R378, R379, R4, R5, R12, R17, R25, R30, R32, R35, R44~R53, R63, R66, R67, R81, R83 R108, R190, R195, R290, R313, R314, R323, R326, R337, R421, R358~R365, R2654~R2657, C140, C156, C186, C187, C2025~C2028, C194~C196, C200, C209~C212 X02 88 32 Audio 2011/12/22 Compal iPHONE's mic can't recording depop R8, R9 X02 89 43 USB 3.0 2011/12/22 Compal delete USB 3.0 redriver and co-lay circuit delete C209~C212 X02 90 30 HDMI IN 2012/01/02 Compal HDMI IN debug function pop R1650, R1651 X02 91 35 BT 2012/01/03 Compal can't disable bt of combo card change RE42 to 0 ohm, add RE43, connect BT_RADIO_DIS# to JWLAN pin 51 X02 D C B A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Changed-List History 1 Size Document Number Date: Tuesday, January 17, 2012 LA-8321P Sheet 1 Rev 0.1 64 of 65 5 4 3 2 1 Version Change List ( P. I. R. List ) Item Page# D Title Date Request Owner Issue Description Solution Description Rev. 92 32 40 17 AUDIO 2012/01/03 Compal ADD SPDIF detect pin add net SPDIF_DET# connect JSPDIF pin 5 to EC pin 76, change R1829 connect to SPDIF_DET#, change IO_DET# to PCH gpio64, add R1737 X02 93 35 DMC 2012/01/04 Compal double pull up del R945 X02 94 40 board ID 2012/01/04 Compal Change board ID to V0.4 Change R466 from 18K ohm to 33K ohm X02 95 32 audio 2012/01/06 Compal pop noise issue add U632, RA30, RA31, C1874 X02 96 32 audio 2012/01/09 Compal THD+N measure add C1601, change RA30, RA31 to RA16 RA17 pin 2 X02 97 32 audio 2012/01/09 Compal MIC fine turn Change RA13 R1243 from short pad to 0 ohm X02 98 32 audio 2012/01/11 Compal THD+N fail change C11, C14 to 25V X5R X02 99 35 BT 2012/01/16 Compal enable debug function on minicard pop RE42, change RE43 to 1k ohm X02 100 32 AUDIO 2012/01/17 Compal Thailand flood impact change C123, C129, C132, C133 to SGA00004D00 X02 D C C B B A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Changed-List History 1 Size Document Number Date: Tuesday, January 17, 2012 LA-8321P Sheet 1 Rev 0.1 65 of 65 www.s-manuals.com
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