Compal LA 8331P Schematics. Www.s Manuals.com. R0.4 Schematics

User Manual: Motherboard Compal LA-8331P Q5WV8 - Schematics. Free.

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Compal Confidential
Q5WV8 Schematics Document

2

2

AMD "Comal" Platform
AMD Trinity APU / Hudson M3 FCH / ATI Thames XT

3

3

2012-01-05A
LA-8331P REV: 0.4

4

4

2011/07/08

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2015/07/08

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SCHEMATIC,MB A8331
Document Number

Rev
B

4019H2
Sheet

Wednesday, February 29, 2012
E

1

of

52

A

B

C

D

E

Compal Confidential
Model Name : Q5WV8
VRAM 1G/2G
64M16/128M16 x 8

1

1

page 18, 19

AMD Comal

DDR3

R03 Resverd

Thermal Sensor
ADM1032

ATI Vancuver
Thames XT 128Bit DDR3
uFCBGA-962

page 14

PCIe x 16

LVDS
(DIS Only)

DP2

APU HDMI
(UMA / Muxless)

Page 13~17

HDMI
(DIS Only)

Gen2

VGA
(DIS Only)

DP0

AMD FS1R2 APU
Trinity

Memory BUS(DDR3)
Dual Channel

204pin DDRIII-SO-DIMM X2
Page 11,12

BANK 0, 1, 2, 3

1.5V DDRIII 800~1866MHz

uPGA-722 Package

HDMI Conn.
page 23

2

LVDS
Translator
RTD2132S

LVDS Conn.

page 22

Page 6~10

DP1

DP x 4
(DP1 TXP/N 0~4)

P_GPP x 3
GEN1

page 21

2

UMI

ML for FCH VGA

USB20
M/B*1

UMA eDP

eDP Panel
page 22

page 36

FCH CRT (VGA DAC)

CRT Conn.
page 24

GPP3

GPP2

GPP1

GPP0

FCH
Hudson-M2/M3

USB

MINI Card 2
(Option)
31

MINI Card 1
(Wireless LAN)

page 34

LAN(GbE)
Atheros
AR8151 page

page 34

page 36

Port 10
(USB3.0)

Port 0
Port 1

USB30
M/B*1

CMOS
Camera

page 36

Bluetooth
Conn.

Mini
Card 1

Mini
Card 2

page 22

page 36

page 34

page 34

Port 5

Port 7

Port 8

Port 9

Port 0
(USB3.0)

3.3V 48MHz

HD Audio 3.3V 24.576MHz/48Mhz

uFCBGA-656
Card Reader
Realtek
RTS5209 page

USB20
Sub/B*2

Page 25~29

SATA Gen2

32

3

GPP0
GEN2

port 0

LPC BUS

3

SATA HDD1
Conn.

Transformer / RJ45

page 33

page 30

LED

port 1

ODD
Conn.
page

30

HDA Codec
ALC271X VB6
ALC281X page

38

ENE
KB930/KB9012
page 38

page 39

RTC CKT.

USB30
Fresco FL1009
On M/B page 35

page 25

Power On/Off CKT.

Sub board

Touch Pad

Int.KBD

page 39

page 39

page 37

LID SW - Power/B
Fan Control
4

page 39

page 30

DC/DC
Interface CKT.page

USB20/B
-USB20 x2

4

BIOS ROM
page 36

SYS BIOS (4M)

41

page 26

USB30/B
-USB20 x1+ USB30 x1

Power Circuit

page 42~51

page 36

2011/07/08

Issued Date

EC BIOS (128K)

page 39

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2015/07/08

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SCHEMATIC,MB A8331
Document Number

Rev
B

4019H2
Sheet

Wednesday, February 29, 2012
E

2

of

52

5

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2

1

DISPLAY DISTRIBUTION

CLOCK DISTRIBUTION

: LVDS PATH
,

: eDP PATH
: APU HDMI PATH

A_SODIMM

B_SODIMM

D

LVDS CONN

: VGA HDMI PATH

D

TXOUT[0:2]+/TXCLK+/TZOUT[0:2]+/TZCLK+/I2CC_SCL/DA

AMD

TXOUT[1:2]+/I2CC_SCL/DA
TXOUT[1:2]+/I2CC_SCL/DA

R

TXOUT[0:2]+/TXCLK+/I2CC_SCL/DA

ATI VGA
1066~1866MHz

MEM_MA_CLK1_P/N
MEM_MA_CLK7_P/N

1066~1866MHz

MEM_MB_CLK1_P/N
MEM_MB_CLK7_P/N

Whistler/Seymour/Thames

100MHz

AMD

100MHz

CPU FS1 SOCKET

APU_CLKP/N
100MHz

C

APU_TXOUT[0:2]+/APU_TXOUT_CLK+/APU_TZOUT[0:2]+/APU_TZOUT_CLK+/APU_LVDS_CLK/DATA

CLK_PEG_VGAP/N

APU_DISP_CLKP/N
C

TZOUT[0:2]+/TZCLK+/-

APU_TXOUT[1:2]+/APU_LVDS_CLK/DATA

R

R

Place near
the pin
C

AMD

LVDS_OUT

C

DP0_TXP/N[0:1]_R
DP0_AUXP/N_R

RTD2132

FCH
Hudson-M2/M3
Internal CLK GEN

DP_IN

VGA_TXOUT[1:2]+/VGA_LCD_CLK/DATA
VGA_TXOUT[0:2]+/VGA_TXCLK+/VGA_LCD_CLK/DATA

R

VGA_TZOUT[0:2]+/VGA_TZCLK+/-

Place near
the pin

DP0_AUX

GPP_CLK
100MHz

32.768KHz 25MHz

LVDS Transtator

C

R

DP0_TXP/N[0:1]
DP0_AUXP/N
B

GPP4

USB30 M/B

GPP3

USB30 SUS/B

GPP2

GPP1

WLAN
OPT PCI Socket

WLAN
Mini PCI Socket

GPP0

APU

GbE LAN

DP0
PCIE_GFX[0:11]

C

DPE

PCIE_GFX[12:15]

C

B

VGA
PCIE_GFX[0:15]

R

DP1

DPF

DAC1

DPA

25MHz

FCH
R
R

R

R

A

A

CRT CONN

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Issued Date

HDMI CONN

2015/07/08

Deciphered Date

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 4019H2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
B
Sheet

Wednesday, February 29, 2012
1

3

of

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ZZZ

ZZZ2

ZZZ3

PCB

X76

X76

ZZZ1

ZZZ4

X76

X76

Voltage Rails
Power Plane

1

2

Description

S1

S3

S5

STATE
Full ON

VIN

Adapter power supply (19V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

+CPU_CORE_NB

Voltage for On-die VGA of APU

ON

OFF

OFF

+VGA_CORE

0.95-1.2V switched power rail

ON

OFF

OFF

4

Clock
ON

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

OFF

+1.0VSG

1.0V switched power rail for VGA

ON

OFF

OFF

+1.1ALW

1.1V switched power rail for FCH

ON

ON

ON*

+1.1VS

1.1V switched power rail for FCH

ON

OFF

OFF

+1.2VS

1.2V switched power rail for APU

ON

OFF

OFF

Vcc
Ra/Rc/Re

+1.5V

1.5V power rail for CPU VDDIO and DDR

ON

ON

OFF

Board ID

+1.5VS

1.5V switched power rail

ON

OFF

OFF

+1.8VSG

1.8V switched power rail

ON

OFF

OFF

+2.5VS

2.5V for CPU_VDDA

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3V_LAN

3.3V power rail for LAN

ON

ON

ON

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

0
1
2
3
4
5
6
7

+VSB

VSB always on power rail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

EC SM Bus2 address

ON

LOW

OFF

EC SM Bus1 address

+VS

ON

ON

OFF

3

+V

ON

ON

ON

Interrupts

+VALW

ON

ON

REQ#/GNT#

HIGH
HIGH

ON

IDSEL#

HIGH
HIGH

0.95-1.2V switched power rail

Device

HIGH
HIGH

0.75V switched power rail for DDR terminator

External PCI Devices

HIGH
LOW

+VDDCI

x = 1 is read cmd, x= 0 is writee cmd.

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

S1(Power On Suspend)

+0.75VS

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

SIGNAL

Part Number = DA60000QV00
PCB 0OH LA-8331P REV0 M/B

Part Number = X76356BOL02
TMSSAM2G@

1

Part Number = X76356BOL01
TMSHYN2G@

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

BOARD ID Table
V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

BOM Option Table

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

Board ID
0
1
2
3
4
5
6
7

PCB Revision
EVT
EVT2
DVT

2

BOM Config

BOM
Structure

Description

M2@

Use Hudson-M2

M3@

Use Hudson-M3

V

V

930@

Use EC 930

V

V

9012@

Use EC 9012

UMA@

Display output from APU (UMA only or PX)

V

V

DISO@

Display output from VGA (DIS only)

VGALVDS@

VGA output LVDS (DIS only)

UMA

Thames

DVT
PX5
1G-eDP

DVT
UMA-eDP

DVT
PX5
1G-LVDS

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

VGA@

Use VGA (PX or DIS only)

V

V

V

V

THA@

VGA: Thames

V

V

V

V

SEY@

VGA: Seymour

128@

Use VRAM channel A&B

V

V

V

V

PX@

PX function

V

V

V

V

BACO@

BACO function (PX4.0)

V

NOBACO@

Without BACO function (DISO and PX5.0)

V

V

V

3

V

V

V

V

TL@

LVDS Translator (for LVDS)

HEX

Device

Address

HEX

EDP@

Use eDP Panel

V

V

Smart Battery

0001 011X b

16H

ADI ADM1032 (VGA)

1001 101X b

9AH

APUEDP@

APU output eDP

V

V

SB-TSI (APU)

1001 100X b

98H

VGAEDP@

VGA output eDP (DIS only)

LVDS TR( RTD-2132S) 1010 100X b

A8H

271@

Realtek ALC271x VB6

VGA Internal Thermal

82H

281@

Realtek ALC281x

ZERO@

ZERO Power ODD function

FL@

Fresco FL1009 USB3.0 Controller

V

8151@

LAN Atheros AR8151 10/100/1000M LAN

V

8152@

LAN Atheros AR8152 10/100M LAN

X76@

VRAM ID Table (Load By X76J)

CONN@

Connector (Control by ME)

FCH
SM Bus 1 address

Device

Address

HEX

DDR DIMM1

1101 000X b

90

DDR DIMM2

1101 001X b

94

Device

Address

HEX

V

V

V

V

V

V

V

V

V

V

V

V

V

V

Compal Electronics, Inc.

Compal Secret Data
2011/07/08

Issued Date

V

4

Security Classification

2015/07/08

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

DVT
PX5
2G-LVDS

DVT
UMA-LVDS

EVT2
UMA

Address

FCH
SM Bus 0 address

Part Number = X76356BOL04
SEYSAM1G@

Board ID / SKU ID Table for AD channel

Device

1000 001X b

Part Number = X76356BOL03
SEYHYN1G@

C

D

SCHEMATIC,MB A8331
Document Number

Rev
B

4019H2
Sheet

Wednesday, February 29, 2012
E

4

of

52

5

4

3

2

1

AMD APU FS1R2
BATTERY
12.6V

PU21
CHARGER
BQ24725RGRR

BATT+

PU27
ISL6277HRTZ-T

+CPU_CORE

PU25
APL5508
D

AC ADAPTOR
19V 90W

PU19
RT8209MGQW

VIN

+CPU_CORE

0.7~1.475V

VDD CORE 60A

+CPU_CORE_NB

0.7~1.475V

VDDNB 37A

+2.5VS

+2.5VS

VDDA 750mA

+1.5V

+1.5V

VDDIO 3.2A

+1.2VS

+1.2VS

VDDR 8.5A

+CPU_CORE_NB

+1.2VS

D

RAM DDRIII SODIMMX2
+1.5V
PU26
RT8207MZQW

B+

+1.5V

+1.5V

+0.75VS
+0.75VS

VDD_MEM 4A

+0.75VS

VTT_MEM 0.5A

VGA ATI
Whistler/Seymour/Granville

+VGA_CORE
+VGA_CORE

PU10
TPS51218DSCR

PU7
SY8033BDBC
PU20
TPS51212DSCR

+1.5V

+VDDCI

U41
AO4430L

PU24
APL5930

+1.5VSG

0.85~1.1V

VDDC 47A

0.9~1.0V

VDDCI 4.6A

+1.0VSG

DPLL_VDDC: 125 mA
SPV10: 120 mA
PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA

+1.5VSG

VDDR1: 3400 mA

+1.0VSG

VRAM 512/1GB/2GB
64M / 128Mx16 * 4 / 8

+1.5VSG
PU5
RT8209MGQW

+1.1VALW

PU2
RT8205EGQW

+3VALW

C

U40
SI4800

PU23
SY8033BDBC

+1.8VSG

+1.8VSG

+INVPWR_B+

+3VS

+5VALW

+3VS

Q98
AP2301GN

U38
SI4800

+3VSG

+3VSG

B+ 300mA

U39
AO4430L

+3.3 350mA

+1.1VS

+1.1VS

FAN Control
APL5607
Q63
AP2301

+5VS 500mA

+1.1VALW

VDDAN_11_USB_S: 140 mA
VDDCR_11_USB_S: 197 mA
VDDAN_11_SSUSB_S: 282 mA
VDDCR_11_SSUSB_S: 424 mA
VDDCR_11_S: 187 mA
VDDPL_11_SYS: 70 mA

+5VALW

U54
TPA2301DRG4

+3VS
+3VS

+3VS

+1.5VS

USB X2
+5V
Dual+1
2.5A

+3VALW
+3VALW

+3VALW

SATA
HDD*1
ODD*1
+5V 3A
+3.3V

Audio Codec
ALC271X

Card reader
RTS5209

+5V 45mA

+3.3VS

+3.3VS 25mA

A2VDD: 130 mA
VDDR3: 60 mA

VDDPL_11_DAC: 7 mA
VDDAN_11_ML: 226 mA
VDDCR_11: 1007 mA
VDDAN_11_CLK: 340 mA
VDDAN_11_PCIE: 1088 mA
VDDAN_11_SATA: 1337 mA

+1.1VALW

+USB_VCCA

EC
ENE KB9012 A13

LAN
Atheros AR8151

+3.3VALW 30mA
+3.3VS 3mA

+3.3VALW 201mA

Mini Card
+1.5VS 500mA
+3.3VS 1A
+3.3VALW 330mA

RTC
Bettary

A

Issued Date

2011/07/08

Deciphered Date

VDDPL_33_SSUSB_S: 20 mA
VDDPL_33_USB_S: 17 mA
VDDAN_33_USB_S: 658 mA
VDDIO_33_S: 59 mA
VDDXL_33_S: 5 mA
VDDAN_33_HWM_S: 12 mA

GND

VDDIO_33_GBE_S
VDDCR_11_GBE_S
VDDIO_GBE_S

RTC BAT

VDDBT_RTC_G

A

Compal Electronics, Inc.
2015/07/08

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

4

3

2

B

VDDIO_33_PCIGP: 131 mA
VDDPL_33_SYS: 47 mA
VDDPL_33_DAC: 20 mA
VDDPL_33_ML: 20 mA
VDDAN_33_DAC: 200 mA
VDDPL_33_PCIE: 43 mA
VDDPL_33_SATA: 93 mA
VDDIO_AZ_S: 26 mA

Compal Secret Data

Security Classification

5

2.4 A

C

+1.1VS

+5VS
B

+1.5VSG

FCH AMD Hudson M2/M3

+5VS

LCD panel
15.6"

PLL_PVDD: 75 mA
TSVDD: 20 mA
AVDD: 70 mA
VDD1DI: 100 mA
VDD2DI: 50 mA
A2VDDQ: 1.5 mA
VDD_CT: 110 mA
VDDR4: 170 mA
PCIE_PVDD: 40 mA
MPV18: 150 mA
SPV18: 75 mA
PCIE_VDDR: 400 mA
DP[A:F]_VDD18: 920 mA
DP[A:F]_PVDD: 120 mA

Rev
B

4019H2

Wednesday, February 29, 2012
1

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5

of

52

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D

<13> PCIE_GTX_C_FRX_P[0..15]

PCIE_FTX_C_GRX_P[0..15] <13>

<13> PCIE_GTX_C_FRX_N[0..15]

PCIE_FTX_C_GRX_N[0..15]

E

<13>

JCPU1A

2

3

<32>
<32>
<34>
<34>
<34>
<34>
<31>
<31>

PCIE_DTX_C_FRX_P0
PCIE_DTX_C_FRX_N0
PCIE_DTX_C_FRX_P1
PCIE_DTX_C_FRX_N1
PCIE_DTX_C_FRX_P2
PCIE_DTX_C_FRX_N2
PCIE_DTX_C_FRX_P3
PCIE_DTX_C_FRX_N3

AE5
AE6
AD8
AD7
AC9
AC8
AC5
AC6

P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3

<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>

UMI_MTX_C_FRX_P0
UMI_MTX_C_FRX_N0
UMI_MTX_C_FRX_P1
UMI_MTX_C_FRX_N1
UMI_MTX_C_FRX_P2
UMI_MTX_C_FRX_N2
UMI_MTX_C_FRX_P3
UMI_MTX_C_FRX_N3

AG8
AG9
AG6
AG5
AF7
AF8
AE8
AE9

P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3

+1.2VS

1
R539

P_ZVDDP AG11
2
196_0402_1%

GRAPHICS

PCI EXPRESS
P_GFX_RXP0
P_GFX_RXN0
P_GFX_RXP1
P_GFX_RXN1
P_GFX_RXP2
P_GFX_RXN2
P_GFX_RXP3
P_GFX_RXN3
P_GFX_RXP4
P_GFX_RXN4
P_GFX_RXP5
P_GFX_RXN5
P_GFX_RXP6
P_GFX_RXN6
P_GFX_RXP7
P_GFX_RXN7
P_GFX_RXP8
P_GFX_RXN8
P_GFX_RXP9
P_GFX_RXN9
P_GFX_RXP10
P_GFX_RXN10
P_GFX_RXP11
P_GFX_RXN11
P_GFX_RXP12
P_GFX_RXN12
P_GFX_RXP13
P_GFX_RXN13
P_GFX_RXP14
P_GFX_RXN14
P_GFX_RXP15
P_GFX_RXN15

GPP

1

AB8
AB7
AA9
AA8
AA5
AA6
Y8
Y7
W9
W8
W5
W6
V8
V7
U9
U8
U5
U6
T8
T7
R9
R8
R5
R6
P8
P7
N9
N8
N5
N6
M8
M7

UMI

PCIE_GTX_C_FRX_P0
PCIE_GTX_C_FRX_N0
PCIE_GTX_C_FRX_P1
PCIE_GTX_C_FRX_N1
PCIE_GTX_C_FRX_P2
PCIE_GTX_C_FRX_N2
PCIE_GTX_C_FRX_P3
PCIE_GTX_C_FRX_N3
PCIE_GTX_C_FRX_P4
PCIE_GTX_C_FRX_N4
PCIE_GTX_C_FRX_P5
PCIE_GTX_C_FRX_N5
PCIE_GTX_C_FRX_P6
PCIE_GTX_C_FRX_N6
PCIE_GTX_C_FRX_P7
PCIE_GTX_C_FRX_N7
PCIE_GTX_C_FRX_P8
PCIE_GTX_C_FRX_N8
PCIE_GTX_C_FRX_P9
PCIE_GTX_C_FRX_N9
PCIE_GTX_C_FRX_P10
PCIE_GTX_C_FRX_N10
PCIE_GTX_C_FRX_P11
PCIE_GTX_C_FRX_N11
PCIE_GTX_C_FRX_P12
PCIE_GTX_C_FRX_N12
PCIE_GTX_C_FRX_P13
PCIE_GTX_C_FRX_N13
PCIE_GTX_C_FRX_P14
PCIE_GTX_C_FRX_N14
PCIE_GTX_C_FRX_P15
PCIE_GTX_C_FRX_N15

P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3
P_GFX_TXP4
P_GFX_TXN4
P_GFX_TXP5
P_GFX_TXN5
P_GFX_TXP6
P_GFX_TXN6
P_GFX_TXP7
P_GFX_TXN7
P_GFX_TXP8
P_GFX_TXN8
P_GFX_TXP9
P_GFX_TXN9
P_GFX_TXP10
P_GFX_TXN10
P_GFX_TXP11
P_GFX_TXN11
P_GFX_TXP12
P_GFX_TXN12
P_GFX_TXP13
P_GFX_TXN13
P_GFX_TXP14
P_GFX_TXN14
P_GFX_TXP15
P_GFX_TXN15

AB2
AB1
AA3
AA2
Y5
Y4
Y2
Y1
W3
W2
V5
V4
V2
V1
U3
U2
T5
T4
T2
T1
R3
R2
P5
P4
P2
P1
N3
N2
M5
M4
M2
M1

PCIE_FTX_GRX_P0
PCIE_FTX_GRX_N0
PCIE_FTX_GRX_P1
PCIE_FTX_GRX_N1
PCIE_FTX_GRX_P2
PCIE_FTX_GRX_N2
PCIE_FTX_GRX_P3
PCIE_FTX_GRX_N3
PCIE_FTX_GRX_P4
PCIE_FTX_GRX_N4
PCIE_FTX_GRX_P5
PCIE_FTX_GRX_N5
PCIE_FTX_GRX_P6
PCIE_FTX_GRX_N6
PCIE_FTX_GRX_P7
PCIE_FTX_GRX_N7
PCIE_FTX_GRX_P8
PCIE_FTX_GRX_N8
PCIE_FTX_GRX_P9
PCIE_FTX_GRX_N9
PCIE_FTX_GRX_P10
PCIE_FTX_GRX_N10
PCIE_FTX_GRX_P11
PCIE_FTX_GRX_N11
PCIE_FTX_GRX_P12
PCIE_FTX_GRX_N12
PCIE_FTX_GRX_P13
PCIE_FTX_GRX_N13
PCIE_FTX_GRX_P14
PCIE_FTX_GRX_N14
PCIE_FTX_GRX_P15
PCIE_FTX_GRX_N15

P_GPP_TXP0
P_GPP_TXN0
P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3

AD5
AD4
AD2
AD1
AC3
AC2
AB5
AB4

P_UMI_TXP0
P_UMI_TXN0
P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3

P_ZVDDP

P_ZVSS

VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K

PCIE_FTX_DRX_P0
PCIE_FTX_DRX_N0
PCIE_FTX_DRX_P1
PCIE_FTX_DRX_N1
PCIE_FTX_DRX_P2
PCIE_FTX_DRX_N2
PCIE_FTX_DRX_P3
PCIE_FTX_DRX_N3

C950
C951
C952
C953
C954
C955
C1014
C1011

1
2
1
2
1
2
1
2
1 @ 2
1 @ 2
1
2
1
2

.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K

AG2
AG3
AF4
AF5
AF1
AF2
AE2
AE3

UMI_FTX_MRX_P0
UMI_FTX_MRX_N0
UMI_FTX_MRX_P1
UMI_FTX_MRX_N1
UMI_FTX_MRX_P2
UMI_FTX_MRX_N2
UMI_FTX_MRX_P3
UMI_FTX_MRX_N3

C956
C957
C958
C959
C960
C961
C962
C963

1
1
1
1
1
1
1
1

.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K

AH11

P_ZVSS

1
R540

C917
C918
C919
C920
C921
C922
C923
C924
C925
C926
C927
C928
C929
C930
C931
C932
C933
C934
C936
C937
C938
C939
C940
C941
C942
C943
C944
C945
C946
C947
C948
C949

2
2
2
2
2
2
2
2

PCIE_FTX_C_GRX_P0
PCIE_FTX_C_GRX_N0
PCIE_FTX_C_GRX_P1
PCIE_FTX_C_GRX_N1
PCIE_FTX_C_GRX_P2
PCIE_FTX_C_GRX_N2
PCIE_FTX_C_GRX_P3
PCIE_FTX_C_GRX_N3
PCIE_FTX_C_GRX_P4
PCIE_FTX_C_GRX_N4
PCIE_FTX_C_GRX_P5
PCIE_FTX_C_GRX_N5
PCIE_FTX_C_GRX_P6
PCIE_FTX_C_GRX_N6
PCIE_FTX_C_GRX_P7
PCIE_FTX_C_GRX_N7
PCIE_FTX_C_GRX_P8
PCIE_FTX_C_GRX_N8
PCIE_FTX_C_GRX_P9
PCIE_FTX_C_GRX_N9
PCIE_FTX_C_GRX_P10
PCIE_FTX_C_GRX_N10
PCIE_FTX_C_GRX_P11
PCIE_FTX_C_GRX_N11
PCIE_FTX_C_GRX_P12
PCIE_FTX_C_GRX_N12
PCIE_FTX_C_GRX_P13
PCIE_FTX_C_GRX_N13
PCIE_FTX_C_GRX_P14
PCIE_FTX_C_GRX_N14
PCIE_FTX_C_GRX_P15
PCIE_FTX_C_GRX_N15
PCIE_FTX_C_DRX_P0
PCIE_FTX_C_DRX_N0
PCIE_FTX_C_DRX_P1
PCIE_FTX_C_DRX_N1
PCIE_FTX_C_DRX_P2
PCIE_FTX_C_DRX_N2
PCIE_FTX_C_DRX_P3
PCIE_FTX_C_DRX_N3
UMI_FTX_C_MRX_P0
UMI_FTX_C_MRX_N0
UMI_FTX_C_MRX_P1
UMI_FTX_C_MRX_N1
UMI_FTX_C_MRX_P2
UMI_FTX_C_MRX_N2
UMI_FTX_C_MRX_P3
UMI_FTX_C_MRX_N3

1

2

<32>
<32>
<34>
<34>
<34>
<34>
<31>
<31>

GLAN
WLAN
Option Mini (R03 modify Reserved)
Card Reader

<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>

3

2
196_0402_1%

LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Deciphered Date

2015/07/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SCHEMATIC,MB A8331
Document Number

Rev
B

4019H2
Wednesday, February 29, 2012

Sheet
E

6

of

52

A

B

C

D

E

1

1

JCPU1C
JCPU1B
<11> DDRA_SMA[15..0]

<11>
<11>
<11>
<11>

DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#
DDRA_SDM[7..0]

<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#

U24
U21
L23

MA_BANK0
MA_BANK1
MA_BANK2

E14
J17
E21
F25
AD27
AC23
AD19
AC15

DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#

DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#

<11> DDRA_CKE0
<11> DDRA_CKE1
<11> DDRA_ODT0
<11> DDRA_ODT1
<11> DDRA_SCS0#
<11> DDRA_SCS1#

3

U20
R20
R21
P22
P21
N24
N23
N20
N21
M21
U23
M22
L24
AA25
L21
L20

DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7

2

<11> DDRA_SRAS#
<11> DDRA_SCAS#
<11> DDRA_SWE#
<11> MEM_MA_RST#
<11> MEM_MA_EVENT#

G14
H14
G18
H18
J21
H21
E27
E26
AE26
AD26
AB22
AA22
AB18
AA18
AA14
AA15

1
R541

+1.5V

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#

T21
T22
R23
R24

MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1

DDRA_CKE0
DDRA_CKE1

H28
H27

MA_CKE0
MA_CKE1

DDRA_ODT0
DDRA_ODT1

Y25
AA27

MA_ODT0
MA_ODT1

DDRA_SCS0#
DDRA_SCS1#

V22
AA26

MA_CS_L0
MA_CS_L1

DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#

V21
W24
W23

MEM_MA_RST#
MEM_MA_EVENT#

H25
T24

MA_RESET_L
MA_EVENT_L

W20

M_VREF

W21

M_ZVDDIO

+MEM_VREF

15mil

<12> DDRB_SMA[15..0]

MEMORY CHANNEL A

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15

2 M_ZVDDIO
39.2_0402_1%

MA_RAS_L
MA_CAS_L
MA_WE_L

DDRA_SDQ[63..0]

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7

E13
J13
H15
J15
H13
F13
F15
E15

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7

MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15

H17
F17
E19
J19
G16
H16
H19
F19

DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15

MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23

H20
F21
J23
H23
G20
E20
G22
H22

DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23

MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31

G24
E25
G27
G26
F23
H24
E28
F27

DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31

MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39

AB28
AC27
AD25
AA24
AE28
AD28
AB26
AC25

DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39

MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47

Y23
AA23
Y21
AA20
AB24
AD24
AA21
AC21

DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47

MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55

AA19
AC19
AC17
AA17
AB20
Y19
AD18
AD17

DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55

MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

AA16
Y15
AA13
AC13
Y17
AB16
AB14
Y13

DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63

<11>

<12>
<12>
<12>
<12>

DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
DDRB_SDM[7..0]

<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>

DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#

<12>
<12>
<12>
<12>

DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#

<12> DDRB_CKE0
<12> DDRB_CKE1
<12> DDRB_ODT0
<12> DDRB_ODT1
<12> DDRB_SCS0#
<12> DDRB_SCS1#
<12> DDRB_SRAS#
<12> DDRB_SCAS#
<12> DDRB_SWE#
<12> MEM_MB_RST#
<12> MEM_MB_EVENT#

MEMORY CHANNEL B

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15

T27
P24
P25
N27
N26
M28
M27
M24
M25
L26
U26
L27
K27
W26
K25
K24

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#

U27
T28
K28

MB_BANK0
MB_BANK1
MB_BANK2

DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7

D14
A18
A22
C25
AF25
AG22
AH18
AD14

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#

C15
B15
E18
D18
E22
D22
B26
A26
AG24
AG25
AG21
AF21
AG17
AG18
AH14
AG14

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#

R26
R27
P27
P28

MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1

DDRB_CKE0
DDRB_CKE1

J26
J27

MB_CKE0
MB_CKE1

DDRB_ODT0
DDRB_ODT1

W27
Y28

MB_ODT0
MB_ODT1

DDRB_SCS0#
DDRB_SCS1#

V25
Y27

MB_CS_L0
MB_CS_L1

DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#

V24
V27
V28

MB_RAS_L
MB_CAS_L
MB_WE_L

MEM_MB_RST#
MEM_MB_EVENT#

J25
T25

MB_RESET_L
MB_EVENT_L

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7

A14
B14
D16
E16
B13
C13
B16
A16

DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7

MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15

C17
B18
B20
A20
E17
B17
B19
C19

DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15

MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23

C21
B22
C23
A24
D20
B21
E23
B23

DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23

MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31

E24
B25
B27
D28
B24
D24
D26
C27

DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31

MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39

AG26
AH26
AF23
AG23
AG27
AF27
AH24
AE24

DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39

MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47

AE22
AH22
AE20
AH20
AD23
AD22
AD21
AD20

DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47

MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55

AF19
AE18
AE16
AH16
AG20
AG19
AF17
AD16

DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55

MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

AG15
AD15
AG13
AD13
AG16
AF15
AE14
AF13

DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63

DDRB_SDQ[63..0]

<12>

2

3

LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@

Place them close to APU within 1"
LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@

EVENT# pull high

0.75V reference voltage

+1.5V
2

+1.5V
4

4

R542
1K_0402_1%
R545 1

2 1K_0402_5% MEM_MB_EVENT#

15mil
1

2 1K_0402_5% MEM_MA_EVENT#

+MEM_VREF

2

R544 1

1

R543
1K_0402_1%

1000P_0402_50V7K

2

1

C965
.1U_0402_16V7K

2011/07/08

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2015/07/08

Deciphered Date

Title

SCHEMATIC,MB A8331

1

2

C964

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

A

B

C

D

Sheet

Wednesday, February 29, 2012
E

7

of

52

A

B

C

D

Place near APU

E

Place near APU
JCPU1D
DP0_TXP0
DP0_TXN0

L3
L2

DP0_TXP0
DP0_TXN0

To eDP
Panel

<21> DP0_TXP1_C
<21> DP0_TXN1_C

C966 1
C967 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

APUEDP@ DP0_TXP1
APUEDP@ DP0_TXN1

K5
K4

DP0_TXP1
DP0_TXN1

K2
K1

DP0_TXP2
DP0_TXN2

J3
J2

DP0_TXP3
DP0_TXN3

H5
H4

DP1_TXP0
DP1_TXN0

ALERT_L

R604 2

ALLOW_STOP

1 1K_0402_5%

To HDMI
R577 2
+1.5VS

@

1 1K_0402_5%

Allow_STOP leakage issue

2 .1U_0402_16V7K
2 .1U_0402_16V7K

UMA@
UMA@

DP1_TXP1
DP1_TXN1

H2
H1

DP1_TXP1
DP1_TXN1

C978 1
C979 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

UMA@
UMA@

DP1_TXP2
DP1_TXN2

G3
G2

DP1_TXP2
DP1_TXN2

<26> ML_VGA_TXP3
<26> ML_VGA_TXN3

C980 1
C981 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

UMA@
UMA@

DP1_TXP3
DP1_TXN3

F2
F1

DP1_TXP3
DP1_TXN3

<23> APU_HDMI_TXD2+
<23> APU_HDMI_TXD2-

L9
L8

DP2_TXP0
DP2_TXN0

<23> APU_HDMI_TXD1+
<23> APU_HDMI_TXD1-

L5
L6

DP2_TXP1
DP2_TXN1

<23> APU_HDMI_TXD0+
<23> APU_HDMI_TXD0-

K8
K7

DP2_TXP2
DP2_TXN2

J6
J5

<23> APU_HDMI_TXC+
<23> APU_HDMI_TXCR578 2

1 300_0402_5%

APU_RST#

100MHz
R580 2

2

1 300_0402_5%

APU_PWRGD

R575 1

@

2 1K_0402_5%

APU_SVC

R576 1

@

2 1K_0402_5%

APU_SVD

R92

@

2 1K_0402_5%

APU_SVT

1

100MHz
NSS

C38
C36
C35

2
2

<25> APU_DISP_CLKP
<25> APU_DISP_CLKN
<50> APU_SVC

APU_RST#
33P_0402_50V8J
APU_PWRGD
33P_0402_50V8J
APU_PROCHOT#
1
22P_0402_50V8J
APU_THERMTRIP#
1
22P_0402_50V8J

AE11
AD11

CLKIN_H
CLKIN_L

APU_DISP_CLKP
APU_DISP_CLKN

AB11
AA11

DISP_CLKIN_H
DISP_CLKIN_L

B3
A3
C3

SB-TSI (S5 Domain)

<25> APU_RST#
<25,50> APU_PWRGD
<25> ALLOW_STOP

APU_RST#
R598 1
APU_PWRGD R615 1
ALLOW_STOP

APU_SIC
APU_SID

Internal PU when no use HDT

AG12
AH12

APU_VDD_SEN

<50> APU_VDD_SEN

RESET_L
PWROK
DMAACTIVE_L
PROCHOT_L
THERMTRIP_L
ALERT_L
TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L

B4
C5
A4
A5
C4
B5

APU_VDDNB_SEN

E1
E2

ML_VGA_AUXP
ML_VGA_AUXN

C975 1
C976 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

UMA@
UMA@

DP2_AUXP
DP2_AUXN

D5
D6

APU_HDMI_CLK
APU_HDMI_DATA

DP3_AUXP
DP3_AUXN

E5
E6

DP4_AUXP
DP4_AUXN

F5
F6

DP5_AUXP
DP5_AUXN

G5
G6

DP0_HPD
DP1_HPD
DP2_HPD
DP3_HPD
DP4_HPD
DP5_HPD

D3
E3
D7
E7
F7
G7

DP0_HPD
DP1_HPD
DP2_HPD

DP_BLON
DP_DIGON
DP_VARY_BL

C6
B6
A6

DP_ENBKL
DP_ENVDD
DP_INT_PWM

C1

DP_AUX_ZVSS R569 1

DP_AUX_ZVSS
TEST6
TEST28_H
TEST28_L
TEST30_H
TEST30_L
TEST32_H
TEST32_L

SIC
SID

H10
J10
F10
G10
F9
G9
H9

<50> APU_VDD_RUN_FB_L
<50> APU_VDDNB_SEN

SVC
SVD
SVT

AF10
2 0_0402_5% APU_RST#_APU
2 0_0402_5% APU_PWRGD_APU AB12
AC12
APU_PROCHOT#
AC10
APU_THERMTRIP# AE12
ALERT_L
AF12
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

DP1_AUXP
DP1_AUXN

DP2_TXP3
DP2_TXN3

APU_CLKP
APU_CLKN

APU_SVC
APU_SVD
APU_SVT

SVI 2.0
<50> APU_SVD
(0 ohm
<50> APU_SVT
at Power Side)

For ESD request close APU side

C40

<25> APU_CLKP
<25> APU_CLKN

UMA@
UMA@

TEST

2 1K_0402_5%

C969 1
C970 1

<26> ML_VGA_TXP2
<26> ML_VGA_TXN2

2 .1U_0402_16V7K
2 .1U_0402_16V7K

VSS_SENSE
VDDP_SENSE
VDDNB_SENSE
VDDIO_SENSE
VDD_SENSE
VDDR_SENSE

RSVD

R791 1

<26> ML_VGA_TXP1
<26> ML_VGA_TXN1

C972 1
C974 1

CLK

APU_SID

DP1_TXP0
DP1_TXN0

SER.

APU_SIC

2 1K_0402_5%

UMA@
UMA@

DP0_AUXP
DP0_AUXN

CTRL

2 1K_0402_5%

R581 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

D1
D2

DP0_AUXP_C <21>
DP0_AUXN_C <21>

To LVDS
Translator

ML_VGA_AUXP_C <26>
ML_VGA_AUXN_C <26>

To FCH

APU_HDMI_CLK <23>
APU_HDMI_DATA <23>

To HDMI

2
1
UMA@
1.8K_0402_5%
2
1
R555
UMA@
1.8K_0402_5%
ML_VGA_AUXP
2
1
R547
UMA@
1.8K_0402_5%
ML_VGA_AUXN
2
1
R556
UMA@
1.8K_0402_5%
R554

DP0_AUXN

1

AD12
L10
M10
P19
R19
T19
N19

LVDS/eDP
CRT
HDMI

DP0_HPD <10>
DP1_HPD <10>
DP2_HPD <23>

VDDIO level
Need Level shift

DP_ENBKL <10>
DP_ENVDD <10>
DP_INT_PWM <10>

2 150_0402_1%

T16
T15

TEST4
TEST5
TEST9
TEST10
TEST14
TEST15
TEST16
TEST17

P18
R18
M18
N18
F11
G11
H11
J11

TEST18
TEST19
TEST20
TEST24

F12
G12
J12
H12

APU_TEST18
APU_TEST19
APU_TEST20
APU_TEST24

R582
R583
R584
R574

1
1
1
1

TEST35

AA12

TEST35

TEST25_H
TEST25_L

AE10
AD10

TEST25_H
TEST25_L

R558
R559
R557
R548

1
1
1
1

TEST31

K22

M_TEST

R564 1
R567 1

FS1R2

W10

FS1R2

R571 1

RSVD1
RSVD2
RSVD3
RSVD4

Y10
AA10
Y12
K21

T6
T7
T8
T9
T10
T11
T12
T13

JTAG

R579 1

C977 1
C968 1

SENSE

To FCH
VGA ML

<26> ML_VGA_TXP0
<26> ML_VGA_TXN0

DP0_AUXP
DP0_AUXN

DISPLAY PORT
MISC.

UMA@
UMA@

DISPLAY PORT
0

2 .1U_0402_16V7K
2 .1U_0402_16V7K

DISPLAY PORT 1

C971 1
C973 1

DISPLAY PORT 2

<21> DP0_TXP0_C
<21> DP0_TXN0_C

1

+1.5V

DP0_AUXP

ANALOG/DISPLAY/MISC

To LVDS
Translator

2

@

@

2
2
2
2

1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%

2
2
2
2

300_0402_5%
300_0402_5%
510_0402_1%
510_0402_1%

+1.5V

2 39.2_0402_1%
2 39.2_0402_1%

+1.5V

2 10K_0402_5%

+3VALW

TEST35 change to PU for
HDMI can not output
20110126

+1.2VS

+HDT_VCC

LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@

Route as differential with APU_VDD_RUN_FB_L
3

CPU TSI interface level shift

30K_0402_1%

G

2

31.6K_0402_1%

2

Vg = 1.607 V

3

1
D

EC_SMB_DA2

T14

+1.5V

THERMTRIP shutdown
temperature: 115 degree
2

Indicates to the FCH that a thermal trip
has occurred. Its assertion will cause the FCH
to transition the system to S5 immediately

1

S

D

2 0_0402_5%

1

EC_SMB_CK2 <14,21,37>
APU_THERMTRIP#

3

Q12
1

C

4

E

BSH111_SOT23-3

2 1K_0402_5%

APU_TMS_R

R595 1

2 1K_0402_5%

APU_TRST#

R596 1

2 1K_0402_5%

APU_DBREQ#_R
3

MMBT3904_SOT23-3

1
R611
1
R612 @

2
0_0402_5%
2
0_0402_5%

1

1

2

2

APU_TCK_R

R606 1

2 0_0402_5%

APU_TCK

3

3

4

4

APU_TMS_R

R613 1

2 0_0402_5%

APU_TMS

5

5

6

6

APU_TDI_R

R616 1

2 0_0402_5%

APU_TDI

7

7

8

8

R618 1

2 0_0402_5%

9

9

10

10

R599 1

@

2 0_0402_5%

APU_PWRGD

@

APU_TDO

R601 1

2 10K_0402_5%

11

11

12

12

R602 1

2 0_0402_5%

APU_RST#

R603 1

2 10K_0402_5%

13

13

14

14

R621 1

2 0_0402_5%

APU_DBRDY

R605 1

2 10K_0402_5%

15

15

16

16

APU_DBREQ#_R R6221

2 0_0402_5%

APU_DBREQ#

17

17

18

18

R607 1

2 0_0402_5%

APU_TEST19

19

19

20

20

R608 1

2 0_0402_5%

APU_TEST18

2 2

EC_SMB_CK2

R609
10K_0402_5%

R84

B

3

R610
1K_0402_5%

1

2

G

Q10

APU_TCK_R

R594 1

JP1

2
0_0603_5%

EC_THERM# <25,37,44,50>

APU_TRST#

EC_SMB_DA2 <14,21,37>

BSH111_SOT23-3

APU_SIC

R89

1

APU_PROCHOT# 1
2
R591
0_0402_5%

APU_TDI_R

2 1K_0402_5%

+HDT_VCC
R586
1K_0402_5%

When APU High -> MOS OFF (Vgs < 0.4V )
APU Low -> MOS ON (Vgs > 1.3V)

Q9

S

APU_SID

2

1

+3VS

2 0.1U_0402_16V4Z

1 R536

2

2 1K_0402_5%

R593 1

HDT Debug conn

1

C935 1

1 R535

+1.5V

Asserted as an input to
force processor into
HTC-active state

BSH111, the Vgs is:
min = 0.4V
Max = 1.3V

Close to Header

R592 1

H_THERMTRIP# <27>

4

MAINPWON <37,42,44>

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

SAMTE_ASP-136446-07-B
CONN@

2011/07/08

Deciphered Date

2015/07/08

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

A

B

C

D

Wednesday, February 29, 2012
E

Sheet

8

of

52

A

C

D

E

+CPU_CORE Decoupling

1

JCPU1F

2

330uF x 3@ x2
22uF x 10 @ x5
0.22uF x2
0.01uF x3
180pF x2 @ x1

2

J20
L4
R7
W18
A15
AB17
AC22
AE21
AF24
AH23
AH25
B7
C14
C16
C2
C20
C22
C24
C26
C28
D13
D15
D17
D19
D23
D25
D27
E4
E9
F14
F16
F18
F20
F22
F26
F28
G13
G15
G17
G19
G21
G23
G25
G4
J22
J24
J4
J7
K11
K14
K9
AC11
L19
L7
M11
AF11
V19
V9
W16
W4
W7
Y11
Y20
Y22
Y9
A17
A13
K16
F24
G8
H7
J8

2

330uF x2
22uF x2 @ x5
10uF x1
0.22uF x2
180pF x3

2

Decoupling between CPU and DIMMs
across VDDIO and VSS split

2

1

2

1

180P_0402_50V8J

180P_0402_50V8J

1

C1030

2

0.22U_0402_10V4Z

1

2

10uF x3
0.22uF x2
1000pF x1
180pF x2

2

1

1

1

VDDP Decoupling
Close JCPU1.AH3~7

C1038

+1.2VS
C1035

1

330uF x1
22uF x4
4.7uF x4
0.22uF x6
180pF x1 @x1

C1029

2

+1.5V

0.22U_0402_10V4Z

2

+1.5V / VDDIO Decoupling

C1028

1
+

330U_D2_2V_Y

2

1

C1027

1

1

2

2

FBMA-L11-201209-221LMA30T_0805
L1
1

180P_0402_50V8J

+1.2VS

C1043

0.22U_0402_10V4Z

+1.5V

2

3300P_0402_50V7-K

C1041

47U_0805_4V6

2

1

2

VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143

A19
A21
A23
A25
A7
AA4
AA7
AB13
AB15
AB19
AB21
AB23
AB25
AB27
AB9
AC14
AC16
AC18
AC20
AC24
AC26
AC28
AC4
AC7
AD9
AE13
AE15
AE17
M9
N10
N4
N7
R10
R4
T11
T9
U10
U18
U4
U7
V11
AE19
AE23
AE25
AE27
AE4
AE7
AF14
AF16
AF18
AF20
AF22
AF26
AF28
AF9
AG4
AG7
AH13
AH15
AH17
AH19
AH21
P9
C18
D21
W14
P11
C7
E8
K18
W12

1

2

3

LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@

+APU_VDDA
C1040

C18

1

220U_6.3V_M

2

180P_0402_50V8J

180P_0402_50V8J

2

2

Northbridge Power Pins
for Remote Decoupling

AG10
AH8
AH9
AH10

2

1000P_0402_50V7K

2

0.22U_0402_10V4Z

2

0.22U_0402_10V4Z

+2.5VS

2

10U_0603_6.3V6M

2

2

10U_0603_6.3V6M

2

10U_0603_6.3V6M

22U_0805_6.3V6M

2

1

22uF x1
10uF x3
0.22uF x2
1000pF @x1
180pF x2

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72

GND

+
330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

2

+

VDDR Decoupling
Close JCPU1.AG10,AH8,AH9,AH10

1

C1034

1

C50

1

C1037

1

C1036

1

C6

C7

C8

C51

POWER

+

C29

C995

2

C999

2

+

330U_D2_2V_Y

330U_D2_2V_Y

2

+

C994

1

C993

180P_0402_50V8J

180P_0402_50V8J

2

C68

180P_0402_50V8J

2

1

1

+CPU_CORE_NB Decoupling
+

@

1

2

1

1

1

C5

180P_0402_50V8J

2

180P_0402_50V8J

2

1

C1025

1

C1024

0.22U_0402_10V4Z

2

0.22U_0402_10V4Z

2

2

C1023

180P_0402_50V8J

1

0.22U_0402_10V4Z

180P_0402_50V8J

2

C1045

2

1

C1044

2

1

1000P_0402_50V7K

0.22U_0402_10V4Z

1

C1048

C1053

0.22U_0402_10V4Z

10U_0603_6.3V6M

2

1

C1052

C52

2

1

2

1

C1022

2

1

C1021

1

0.22U_0402_10V4Z

2

0.22U_0402_10V4Z

0.22U_0402_10V4Z

2

1

C1020

1

C1019

C1018

2

4.7U_0603_6.3V6K

2

1

C17

1

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2

C16

2

1

C15

1

4.7U_0603_6.3V6K

22U_0805_6.3V6M

22U_0805_6.3V6M

2

C14

1

C55

C56

2

1

C992

+

330U_D2_2V_Y

2

1

C1010

1

330U_D2_2V_Y

2

C1009

2

180P_0402_50V8J

2

1

C1008

2

1

180P_0402_50V8J

180P_0402_50V8J

1

C1007

C1006

0.22U_0402_10V4Z

2

1

C1005

1

0.22U_0402_10V4Z

2

C1004

1

10U_0603_6.3V6M

2

C57

1

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

.01U_0402_16V7K

2

.01U_0402_16V7K

.01U_0402_16V7K

2

1

C991

1

C990

1

C998

2

C989

1

0.22U_0402_10V4Z

0.22U_0402_10V4Z

2

C988

C987

1

22U_0805_6.3V6M

2

C65

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

2

C66

C67

C986

C985

2

1

1

@
C61

C62

1

10U_0603_6.3V6M

VDDR_1
VDDR_2
VDDR_3
VDDR_4

10U_0603_6.3V6M

VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5

T23
T26
U22
U25
U28
Y26
T20
R28
R25
R22
V20
V23
V26
W22
W25
W28
Y24
G28

180P_0402_50V8J

AB10

VDDIO_19
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
VDDIO_30
VDDIO_31
VDDIO_32
VDDIO_33
VDDIO_34
VDDIO_35
VDDIO_36

1

C1026

K13
K12

22U_0805_6.3V6M

+APU_VDDA

AH6
AH5
AH4
AH3
AH7

VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10
VDDIO_11
VDDIO_12
VDDIO_13
VDDIO_14
VDDIO_15
VDDIO_16
VDDIO_17
VDDIO_18

2

1

@
1

+
VDDNB_CAP

22U_0805_6.3V6M

+1.2VS

H26
K20
J28
K23
K26
L22
L25
L28
M20
M23
M26
N22
N25
N28
P20
P23
P26
AA28

2

1

+1.2VS

C1003

+1.5V

2

C53

C54

+CPU_CORE_NB

1

3

2

2

1

+1.2VS

C1002

VDDNB_CAP_1
VDDNB_CAP_2

1

22U_0805_6.3V6M

C11
C12
D9
D8
D12
D11
B11
A12
B10
E12
B9

22U_0805_6.3V6M

VDDNB_13
VDDNB_14
VDDNB_15
VDDNB_16
VDDNB_17
VDDNB_18
VDDNB_19
VDDNB_20
VDDNB_21
VDDNB_22
VDDNB_23

1

1

+1.5V
C1013

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDNB_6
VDDNB_7
VDDNB_8
VDDNB_9
VDDNB_10
VDDNB_11
VDDNB_12

R11
T10
H8
G1
U11
W11
W13
W15
W17
W19
AB3
AD3
AD6
AE1
L1
Y6
M6
N11
N1
T3
T6
U19
U1
Y16
Y18
Y3
D4
F4
AF6
AF3
L11

C1012

C8
D10
B8
B12
C9
A9
A10
A8
A11
E10
E11
C10

VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62

22U_0805_6.3V6M

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31

22U_0805_6.3V6M

+CPU_CORE_NB

F8
H6
J1
J14
P6
P10
J16
J18
J9
K19
K3
K17
M3
K6
V10
V18
V3
F3
L18
V6
W1
T18
Y14
AA1
AB6
AC1
R1
P3
K10
H3
M19

2

C1001

C1000

2

+CPU_CORE

JCPU1E

1

1

22U_0805_6.3V6M

@

+CPU_CORE_NB

+CPU_CORE

2

C997

0.75A

2

1

22U_0805_6.3V6M

VDDA
+2.5VS

1

22U_0805_6.3V6M

5A / 3.5A

2

22U_0805_6.3V6M

22U_0805_6.3V6M

3.2A

VDDP / VDDR
+1.2VS

1

C984

37A

C983

VDDNB
+CPU_CORE_NB

@

+CPU_CORE
C996

60A

C982

VDD
+CPU_CORE

VDDIO
+1.5V

1

B

Consumption

Power Name

1

2

1

2

VDDA Decoupling

Power Sequence of APU

47uF x1
0.22uF x1
3300pF x1
180pF x1

+1.5V
Group A

+2.5VS
+1.5VS

VDDA

+CPU_CORE

LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@

Group B

+CPU_CORE_NB
4

4

Decoupling Caps.
Pop / @

+1.2VS

330uF 220uF 47uF 22uF 10uF 4.7uF 0.22uF 0.01uF 3300pF 1nF

Pumori 2.0

0

19/11 7

5

17

3

1

1/1

180pF
13/3

Comal

7/2

1

1

19/11 7

4

17

3

1

1/1

14/2

P5WS5

7/2

1

1

13

8

19

3

1

4

16

3

2011/07/08

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2015/07/08

Deciphered Date

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

Rev
B

4019H2

C

D

Sheet

Wednesday, February 29, 2012
E

9

of

52

5

4

3

2

1

L
K
B
N
E
l
e
n
a
P

D
P
H

+3VS

2

1

DP0_HPD <8>

2

1

DP0_HPD

2

3

G
S

D16
2

@
1

PLT_RST# <25,37>

RB751V-40_SOD323-2

1

3

C

E
UMA@
R620
100K_0402_5%

1 UMA@ 2 0_0402_5%

1

UMA@
UMA@
Q15
1
2
2
R619
2.2K_0402_5% B

<8> DP_ENBKL

R86

UMA@
Q14
2N7002K_SOT23-3

2

@
Q92B
DMN66D0LDW-7_SOT363-6

MMBT3904_SOT23-3

@
5
Q92A
DMN66D0LDW-7_SOT363-6

4

1

2

D

APU_ENBKL
D

LVDS_HPD

<21,22> LVDS_HPD

UMA@
R617
100K_0402_5%

1

From Translator or Conn.

R87
0_0402_5%
1 @
2

1

6

Translator and eDP HPD

3

D

UMA@
R614
4.7K_0402_5%

2

@
R53
1K_0402_5%
2

@
R68
4.7K_0402_5%

1

+3VS

+5VS

APU_ENBKL

+3VS

+5VS

2

1

1

2

@
R69
1K_0402_5%

DP1_HPD

DP1_HPD <8>

+3VS

C

1

@
Q94B
DMN66D0LDW-7_SOT363-6

APUEDP@
R631
100K_0402_5%

APUEDP@
R632
4.7K_0402_5%
2

@
5
Q94A
DMN66D0LDW-7_SOT363-6

2

1

2

4

6
FCH_CRT_HPD

<26> FCH_CRT_HPD

R85
0_0402_5%
1 @
2

3

CRT HPD

From FCH

ENBKL <37>

D
D
V
N
E
l
e
n
a
P

@
R71
4.7K_0402_5%
C

R624 1 UMA@ 2 0_0402_5%
R625 1 DISO@ 2 0_0402_5%

<14> VGA_ENBKL

1

1

APU_ENVDD <22>
D

1 UMA@ 2 0_0402_5%
2

APUEDP@
MMBT3904_SOT23-3
C
Q19
1
2
2
R633
2.2K_0402_5% B
E
APUEDP@

G
S

2

3

<8> DP_ENVDD

APUEDP@
Q18
2N7002K_SOT23-3

3

1

R88

1

APUEDP@
R634
100K_0402_5%

M
W
P
l
e
n
a
P

B

B

1

+3VS

1

UMA@
R636
4.7K_0402_5%
2

UMA@
R635
47K_0402_5%

1

2

APU_INVT_PWM <21,22>
D
G
S
3

C
Q21
UMA@

2
B

UMA@
Q20
2N7002K_SOT23-3

MMBT3904_SOT23-3

3

E

1

<8> DP_INT_PWM

2
1

UMA@
R637
2.2K_0402_5%
1
2

2

UMA@
R638
4.7K_0402_5%

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

2015/07/08

Deciphered Date

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
B

4019H2
Sheet

Wednesday, February 29, 2012
1

10

of

52

A

B

+1.5V

DDRA_SDQ26
DDRA_SDQ27

<7> DDRA_CKE0
2

<7> DDRA_SBS2#

DDRA_CKE0
DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

<7> DDRA_CLK0
<7> DDRA_CLK0#
<7> DDRA_SBS0#

DDRA_SWE#
DDRA_SCAS#
DDRA_SMA13
DDRA_SCS1#

DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35

3

DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
<7> DDRA_SDQS6#
<7> DDRA_SDQS6

DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
R643
10K_0402_5%
1
2

+3VS

1

+3VS

1
C1080
2.2U_0603_6.3V4Z

2

R645

1

2

C1081
0.1U_0402_16V4Z

10K_0402_5%
2

4

205

G1

G2

206

Place near DIMM1

MEM_MA_RST# <7>

DDRA_SDQ14
DDRA_SDQ15

+1.5V

DDRA_SDQ20
DDRA_SDQ21

2

0.1U_0402_16V4Z
2

DDRA_SDM2

C1067
1
0.1U_0402_16V4Z

DDRA_SDQ22
DDRA_SDQ23

0.1U_0402_16V4Z
2

2

C1068
1

C1069

2

C1070

1
0.1U_0402_16V4Z

1

0.1U_0402_16V4Z
2
C1071

1
0.1U_0402_16V4Z

1

0.1U_0402_16V4Z
2

2

C1072

C1073

C1074

1
0.1U_0402_16V4Z

1

DDRA_SDQS3#
DDRA_SDQS3

DDRA_SDQS3# <7>
DDRA_SDQS3 <7>

+0.75VS

DDRA_SDQ30
DDRA_SDQ31

C1075

1
0.1U_0402_16V4Z

C1076
1

+1.5V
0.1U_0402_16V4Z
2

2

C1077
DDRA_CKE1

1
0.1U_0402_16V4Z

DDRA_CKE1 <7>

C1078
1

C1106

1

1

2
0.1U_0402_16V4Z

C1079

2
4.7U_0603_6.3V6K

DDRA_SMA15
DDRA_SMA14

2

DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
+VREF_CA

DDRA_SMA2
DDRA_SMA0
DDRA_CLK1
DDRA_CLK1#
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1

+VREF_DQ

15mil

DDRA_SCS0# <7>
DDRA_ODT0 <7>
DDRA_ODT1 <7>

CONN@
SUYIN_600023HB204G256ZL

1

C1066

1

2

@

DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39

15mil
+VREF_DQ

1

2

C1061
2

R640
1K_0402_1%

R639
1K_0402_1%

DDRA_SBS1# <7>
DDRA_SRAS# <7>

+VREF_CA
DDRA_SDQ36
DDRA_SDQ37

+1.5V

+1.5V

DDRA_CLK1 <7>
DDRA_CLK1# <7>

15mil

1

R641
1K_0402_1%

2

1

2

@

+VREF_CA

1

2

C1064

1

C1065

R642
1K_0402_1%

2

C1062

1000P_0402_50V7K
3

DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5#
DDRA_SDQS5

DDRA_SDQS5# <7>
DDRA_SDQS5 <7>

DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7

DDRA_SDQS7# <7>
DDRA_SDQS7 <7>

DDRA_SDQ62
DDRA_SDQ63
MEM_MA_EVENT#

MEM_MA_EVENT# <7>
FCH_SDATA0 <12,27,34>
FCH_SCLK0 <12,27,34>

+0.75VS
4

Part Number = SP07000PE00
PCB Footprint = SUYIN_600023HB204G256ZL_204P

2011/07/08

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

DIMM_A STD H:8mm

2015/07/08

Deciphered Date

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.



Rev
B

4019H2

Date:

A

0.1U_0402_16V4Z
2

2

DDRA_SDQ28
DDRA_SDQ29

C1063

<7> DDRA_SDQS4#
<7> DDRA_SDQS4

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDRA_SDM1
MEM_MA_RST#

C1060

DDRA_SDQ32
DDRA_SDQ33

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

1

DDRA_SDQ12
DDRA_SDQ13

4.7U_0603_6.3V6K

<7> DDRA_SCS1#

DDRA_SMA10
DDRA_SBS0#

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDRA_SDQ6
DDRA_SDQ7

4.7U_0603_6.3V6K

<7> DDRA_SWE#
<7> DDRA_SCAS#

DDRA_CLK0
DDRA_CLK0#

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

<7>

2

DDRA_SDM3

<7>

DDRA_SMA[0..15]

1

DDRA_SDQ24
DDRA_SDQ25

DDRA_SMA[0..15]

<7>

DDRA_SDM[0..7]

2

DDRA_SDQ18
DDRA_SDQ19

DDRA_SDQS0# <7>
DDRA_SDQS0 <7>

1

<7> DDRA_SDQS2#
<7> DDRA_SDQS2

DDRA_SDQS2#
DDRA_SDQS2

DDRA_SDQS0#
DDRA_SDQS0

1000P_0402_50V7K

DDRA_SDQ16
DDRA_SDQ17

DDRA_SDQ[0..63]

DDRA_SDM[0..7]

0.1U_0402_16V4Z

DDRA_SDQ10
DDRA_SDQ11

DDRA_SDQ[0..63]

DDRA_SDQ4
DDRA_SDQ5

2

DDRA_SDQS1#
DDRA_SDQS1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

1

<7> DDRA_SDQS1#
<7> DDRA_SDQS1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2

DDRA_SDQ8
DDRA_SDQ9

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

1

DDRA_SDQ2
DDRA_SDQ3
1

JDIMM1

1000P_0402_50V7K

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDRA_SDM0

E

+1.5V

15mil
DDRA_SDQ0
DDRA_SDQ1

D

0.1U_0402_16V4Z

+VREF_DQ

C

B

C

D

Sheet

Wednesday, February 29, 2012
E

11

of

52

A

B

+VREF_DQ

+1.5V

DDRB_SDM0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17
<7> DDRB_SDQS2#
<7> DDRB_SDQS2

E

+1.5V

DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26
DDRB_SDQ27

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

205

G1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDRB_SDQ[0..63]

DDRB_SDQ4
DDRB_SDQ5

DDRB_SDQ[0..63]

DDRB_SDM[0..7]
DDRB_SDQS0#
DDRB_SDQS0

DDRB_SDQS0# <7>
DDRB_SDQS0 <7>

<7>

DDRB_SDM[0..7]

DDRB_SMA[0..15]

<7>

DDRB_SMA[0..15]

<7>

DDRB_SDQ6
DDRB_SDQ7
1

DDRB_SDQ12
DDRB_SDQ13
DDRB_SDM1
MEM_MB_RST#

MEM_MB_RST# <7>

DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ20
DDRB_SDQ21

Place near DIMM2
DDRB_SDM2
DDRB_SDQ22
DDRB_SDQ23

+1.5V

DDRB_SDQ28
DDRB_SDQ29

2

0.1U_0402_16V4Z
2
C1089

DDRB_SDQS3#
DDRB_SDQS3

DDRB_SDQS3# <7>
DDRB_SDQS3 <7>

0.1U_0402_16V4Z
2

2

C1090

1
0.1U_0402_16V4Z

1

C1091

2

C1092

1
0.1U_0402_16V4Z

1

1
0.1U_0402_16V4Z

<7> DDRB_SBS2#

DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

<7> DDRB_CLK0
<7> DDRB_CLK0#
<7> DDRB_SBS0#
<7> DDRB_SWE#
<7> DDRB_SCAS#

<7> DDRB_SCS1#

DDRB_CLK0
DDRB_CLK0#
DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SCAS#
DDRB_SMA13
DDRB_SCS1#

DDRB_SDQ32
DDRB_SDQ33

DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
<7> DDRB_SDQS6#
<7> DDRB_SDQS6

DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
R646
10K_0402_5%
1
2

1

+3VS

4

R648

2

10K_0402_5%

G2

206

TYCO 2-2013022-1 204P H4 DDR3
CONN@

2

C1099
DDRB_SMA11
DDRB_SMA7

1
0.1U_0402_16V4Z

1
0.1U_0402_16V4Z

C1096
1

1

C1107

1

C1097

1
0.1U_0402_16V4Z

C1098
1

1
+

C1101

2
4.7U_0603_6.3V6K

2

2

@
C9
330U_D2_2V_Y

Change To D2 Type 20110905

DDRB_SMA2
DDRB_SMA0
DDRB_CLK1
DDRB_CLK1#
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1

DDRB_CLK1 <7>
DDRB_CLK1# <7>
DDRB_SBS1# <7>
DDRB_SRAS# <7>
DDRB_SCS0# <7>
DDRB_ODT0 <7>
DDRB_ODT1 <7>

+VREF_DQ

15mil
DDRB_SDQ36
DDRB_SDQ37

1

DDRB_SDM4
DDRB_SDQ38
DDRB_SDQ39

C1088
1000P_0402_50V7K

2

DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5

+VREF_CA

15mil

+VREF_CA

1

2

1

2

15mil

+VREF_DQ

C1083

1

C1084

2

1

2

1

2

+VREF_CA

C1086

1

C1087

2

3

DDRB_SDQS5# <7>
DDRB_SDQS5 <7>

DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDM6
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQS7#
DDRB_SDQS7

DDRB_SDQS7# <7>
DDRB_SDQS7 <7>

DDRB_SDQ62
DDRB_SDQ63
MEM_MB_EVENT#

MEM_MB_EVENT# <7>
FCH_SDATA0 <11,27,34>
FCH_SCLK0 <11,27,34>

+0.75VS
4

PCB Footprint = FOX_AS0A626-U4SN-7F_204P
Part Number = SP07000JN10

Compal Electronics, Inc.

Compal Secret Data
2011/07/08

Issued Date

2015/07/08

Deciphered Date

Title

SCHEMATIC,MB A8331

Date:

B

0.1U_0402_16V4Z
2

2

+1.5V

2
0.1U_0402_16V4Z

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.


A

0.1U_0402_16V4Z
2
C1095

DDRB_SMA6
DDRB_SMA4

Security Classification

DIMM_B STD H:4mm

C1100

C1085

DDRB_SDM5

DDRB_SMA15
DDRB_SMA14

1

0.1U_0402_16V4Z

DDRB_SDQ40
DDRB_SDQ41

1

+1.5V
0.1U_0402_16V4Z
2

4.7U_0603_6.3V6K

3

DDRB_CKE1 <7>

C1082

DDRB_SDQ34
DDRB_SDQ35

DDRB_CKE1

0.1U_0402_16V4Z

DDRB_SDQS4#
DDRB_SDQS4

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

4.7U_0603_6.3V6K

<7> DDRB_SDQS4#
<7> DDRB_SDQS4

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

1000P_0402_50V7K

2

DDRB_CKE0

2

C1094

DDRB_SDQ30
DDRB_SDQ31

+0.75VS
<7> DDRB_CKE0

0.1U_0402_16V4Z
2
C1093

1000P_0402_50V7K

DDRB_SDQ0
DDRB_SDQ1

<7> DDRB_SDQS1#
<7> DDRB_SDQS1

D

JDIMM2

15mil

1

C

C

D

Rev
B

4019H2
Sheet

Wednesday, February 29, 2012
E

12

of

52

A

B

C

D

GFX PCIE LANE REVERSAL

U8G

U8A

PCIE_FTX_C_GRX_P2
PCIE_FTX_C_GRX_N2
PCIE_FTX_C_GRX_P3
PCIE_FTX_C_GRX_N3

Y35
W36
W38
V37
V35
U36

T35
R36

PCIE_RX5P
PCIE_RX5N

PCIE_FTX_C_GRX_P6
PCIE_FTX_C_GRX_N6

R38
P37

PCIE_RX6P
PCIE_RX6N

PCIE_FTX_C_GRX_P7
PCIE_FTX_C_GRX_N7

P35
N36

PCIE_FTX_C_GRX_P9
PCIE_FTX_C_GRX_N9

M35
L36

PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N

PCIE_FTX_C_GRX_P10
PCIE_FTX_C_GRX_N10

L38
K37

PCIE_RX10P
PCIE_RX10N

PCIE_FTX_C_GRX_P11
PCIE_FTX_C_GRX_N11

K35
J36

PCIE_RX11P
PCIE_RX11N

PCIE_FTX_C_GRX_P12
PCIE_FTX_C_GRX_N12

J38
H37

PCIE_RX12P
PCIE_RX12N

H35
G36

PCIE_RX13P
PCIE_RX13N

PCIE_TX3P
PCIE_TX3N

PCI EXPRESS INTERFACE

PCIE_FTX_C_GRX_P5
PCIE_FTX_C_GRX_N5

N38
M37

PCIE_TX2P
PCIE_TX2N

PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N

PCIE_FTX_C_GRX_P8
PCIE_FTX_C_GRX_N8

PCIE_TX1P
PCIE_TX1N

PCIE_RX2P
PCIE_RX2N

U38
T37

PCIE_FTX_C_GRX_P13
PCIE_FTX_C_GRX_N13

3

PCIE_RX1P
PCIE_RX1N

PCIE_FTX_C_GRX_P4
PCIE_FTX_C_GRX_N4

2

PCIE_TX0P
PCIE_TX0N

W33
W32
U33
U32
U30
U29

PCIE_GTX_FRX_P0
PCIE_GTX_FRX_N0
PCIE_GTX_FRX_P1
PCIE_GTX_FRX_N1
PCIE_GTX_FRX_P2
PCIE_GTX_FRX_N2
PCIE_GTX_FRX_P3
PCIE_GTX_FRX_N3

C580 1
C291
C247 1
C473
C572 1
C288
C579 1
C316

2
1
VGA@
2
1
VGA@

2
1
VGA@
2
1
VGA@

PCIE_TX5P
PCIE_TX5N

T30
T29

PCIE_GTX_FRX_P5
PCIE_GTX_FRX_N5

C224 1
C576

2
1
VGA@

PCIE_TX6P
PCIE_TX6N

P33
P32

PCIE_GTX_FRX_P6
PCIE_GTX_FRX_N6

C295 1
C472

2
1
VGA@

PCIE_TX7P
PCIE_TX7N

P30
P29

PCIE_GTX_FRX_P7
PCIE_GTX_FRX_N7

C242 1
C468

2
1
VGA@
2
1
VGA@

PCIE_TX9P
PCIE_TX9N

N30
N29

PCIE_GTX_FRX_P9
PCIE_GTX_FRX_N9

C574 1
C223

2
1
VGA@

PCIE_GTX_FRX_P10
PCIE_GTX_FRX_N10

C474 1
C200

2
1
VGA@

PCIE_TX11P
PCIE_TX11N

L30
L29

PCIE_GTX_FRX_P11
PCIE_GTX_FRX_N11

C337 1
C246

2
1
VGA@

PCIE_TX12P
PCIE_TX12N

K33
K32

PCIE_GTX_FRX_P12
PCIE_GTX_FRX_N12

C582 1
C578

2
1
VGA@

J33
J32

PCIE_GTX_FRX_P13
PCIE_GTX_FRX_N13

F35
E37

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

H33
H32

PCIE_GTX_FRX_P15
PCIE_GTX_FRX_N15

2
VGA@

L33
L32

PCIE_FTX_C_GRX_P15
PCIE_FTX_C_GRX_N15

2
VGA@

PCIE_TX10P
PCIE_TX10N

C570 1
C571

2
VGA@

C581 1
C286

PCIE_GTX_FRX_P14
PCIE_GTX_FRX_N14

2
VGA@

PCIE_GTX_FRX_P8
PCIE_GTX_FRX_N8

K30
K29

2
VGA@

N33
N32

PCIE_TX14P
PCIE_TX14N

2
VGA@

PCIE_TX8P
PCIE_TX8N

PCIE_RX14P
PCIE_RX14N

2
VGA@

C287 1
C228

G38
F37

2
VGA@

PCIE_GTX_FRX_P4
PCIE_GTX_FRX_N4

PCIE_FTX_C_GRX_P14
PCIE_FTX_C_GRX_N14

2
VGA@

2
1
VGA@

T33
T32

C577 1
C338

2
VGA@

PCIE_TX4P
PCIE_TX4N

PCIE_TX13P
PCIE_TX13N

.1U_0402_16V7K
.1U_0402_16V7K

2
VGA@
2
VGA@
2
VGA@

2
1
VGA@

2
VGA@

2
1
VGA@

2

.1U_0402_16V7K
.1U_0402_16V7K

R386 1 DISO@ 2 10K_0402_5%
LVDS CONTROL

VARY_BL
DIGON

AK27
AJ27

VGA_INVT_PWM <22>
VGA_ENVDD <22>

PCIE_GTX_C_FRX_P0
PCIE_GTX_C_FRX_N0

R387 1 DISO@ 2 10K_0402_5%

PCIE_GTX_C_FRX_P1
PCIE_GTX_C_FRX_N1

.1U_0402_16V7K
.1U_0402_16V7K

PCIE_GTX_C_FRX_P2
PCIE_GTX_C_FRX_N2

.1U_0402_16V7K
.1U_0402_16V7K

PCIE_GTX_C_FRX_P3
PCIE_GTX_C_FRX_N3

.1U_0402_16V7K
.1U_0402_16V7K

PCIE_GTX_C_FRX_P4
PCIE_GTX_C_FRX_N4

.1U_0402_16V7K
.1U_0402_16V7K

PCIE_GTX_C_FRX_P5
PCIE_GTX_C_FRX_N5

.1U_0402_16V7K
.1U_0402_16V7K

PCIE_GTX_C_FRX_P6
PCIE_GTX_C_FRX_N6

.1U_0402_16V7K
.1U_0402_16V7K

PCIE_GTX_C_FRX_P7
PCIE_GTX_C_FRX_N7

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

AK35
AL36

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

AJ38
AK37

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

AH35
AJ36

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

AG38
AH37

TXOUT_U3P
TXOUT_U3N

AF35
AG36

Display Port E config

eDP

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

AP34
AR34

VGA_TXCLK+
VGA_TXCLK-

VGA_TXCLK+ <22>
VGA_TXCLK- <22>

DP3

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

AW37
AU35

VGA_TXOUT0+
VGA_TXOUT0-

VGA_TXOUT0+ <22>
VGA_TXOUT0- <22>

DP2

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

AR37
AU39

VGA_TXOUT1+
VGA_TXOUT1-

VGA_TXOUT1+ <22>
VGA_TXOUT1- <22>

DP1

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

AP35
AR35

VGA_TXOUT2+
VGA_TXOUT2-

VGA_TXOUT2+ <22>
VGA_TXOUT2- <22>

DP0

TXOUT_L3P
TXOUT_L3N

AN36
AP37

LVTMDP

.1U_0402_16V7K
.1U_0402_16V7K

PCIE_GTX_C_FRX_P8
PCIE_GTX_C_FRX_N8

.1U_0402_16V7K
.1U_0402_16V7K

PCIE_GTX_C_FRX_P9
PCIE_GTX_C_FRX_N9

.1U_0402_16V7K
.1U_0402_16V7K

PCIE_GTX_C_FRX_P10
PCIE_GTX_C_FRX_N10

.1U_0402_16V7K
.1U_0402_16V7K

PCIE_GTX_C_FRX_P11
PCIE_GTX_C_FRX_N11

.1U_0402_16V7K
.1U_0402_16V7K

PCIE_GTX_C_FRX_P12
PCIE_GTX_C_FRX_N12

.1U_0402_16V7K
.1U_0402_16V7K

PCIE_GTX_C_FRX_P13
PCIE_GTX_C_FRX_N13

.1U_0402_16V7K
.1U_0402_16V7K

PCIE_GTX_C_FRX_P14
PCIE_GTX_C_FRX_N14

.1U_0402_16V7K
.1U_0402_16V7K

PCIE_GTX_C_FRX_P15
PCIE_GTX_C_FRX_N15

1

Display Port F config

S IC 216-0833000 A11 THAMES XT M2
THA@

2

Link E and link F can only be configured as one
DisplayPort link at a time (mutually exclusive).
( eDP is connected to link E. )

+3VSG

@
R394
2.2K_0402_5%

5

PCIE_FTX_C_GRX_P1
PCIE_FTX_C_GRX_N1

PCIE_RX0P
PCIE_RX0N

Y33
Y32

<6>

PX@
U21

VGA@
C336 1
2
C197
1
2
VGA@
VGA@

<25,27> PE_GPIO0

2

B

<25,31,32,34,35> APU_PCIE_RST#

1

A

P

1

AA38
Y37

PCIE_GTX_C_FRX_N[0..15]

2

PCIE_FTX_C_GRX_P0
PCIE_FTX_C_GRX_N0

<6>

Y
3

PCIE_GTX_C_FRX_N[0..15]

PCIE_GTX_C_FRX_P[0..15]

1

PCIE_GTX_C_FRX_P[0..15]
PCIE_FTX_C_GRX_N[0..15]

<6> PCIE_FTX_C_GRX_N[0..15]

4

3

VGA_RST#

G

PCIE_FTX_C_GRX_P[0..15]

<6> PCIE_FTX_C_GRX_P[0..15]

E


LCD PWM (pulse width modulated)
output to adjust LCD brightness
Active High
External 10-kΩ pull-down recommended.


Controls panel digital power on/off.
Active High
External 10-kΩ pull-down recommended.

NC7SZ08P5X_NL_SC70-5

CLOCK
AB35
AA36

<25> CLK_PEG_VGA
<25> CLK_PEG_VGA#

PCIE_REFCLKP
PCIE_REFCLKN

1 DISO@ 2
R159
0_0402_5%
CALIBRATION

2
1
R389 VGA@ 10K_0402_5%
VGA_RST#

AA30

PWRGOOD

PCIE_CALRP

Y30

VGA_PCIE_CALRP

R388 1

PCIE_CALRN

Y29

VGA_PCIE_CALRN

R390 1

VGA@
VGA@

2

1.27K_0402_1%

2

2K_0402_1%

+1.0VSG

PERSTB

1

3.3-V tolerant

AH16

S IC 216-0833000 A11 THAMES XT M2
THA@
Part Number = SA00004WI20

2

@
R402
10K_0402_5%

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Issued Date

Deciphered Date

2015/07/08

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

A

B

C

D

Sheet

Wednesday, February 29, 2012
E

13

of

52

A

B

C

D

E

U8B

Setting

GPIO0

TX_DEEMPH_EN

GPIO1

1

CONFIG[2]

GPIO13

CONFIG[1]

GPIO12

CONFIG[0]

GPIO11

HSYNC

AUD(0)

VSYNC

PCI Express Transmitter De-emphasis Enable (Internal PD)
0: Tx de-emphasis diabled
1: Tx de-emphasis enabled

1

GPIO13,12,11 (config 2,1,0) : (Internal PD)
memory apertures
a) If BIOS_ROM_EN = 1, then Config[2:0] defines CONFIG[3:0]
the ROM type.
128 MB 000
b) If BIOS_ROM_EN = 0, then Config[2:0] defines 256 MB 001 *
64 MB 010
the primary memory aperture size.

BIF_GEN2_EN GPIO2
H2SYNC

AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3

0

00: No audio function;
10: Audio for DisplayPort only;
01: Audio for DisplayPort and HDMI if adapter is detected;
11: Audio for both DisplayPort and HDMI
0= Advertises the PCI-E device as 2.5 GT/s capable at power-on
1= Advertises the PCI-E device as 5.0 GT/s capable at power-on
5.0 GT/s capability will be controlled by software

11
0

Internal use only. THIS PAD HAS AN INTERNAL

(GENLK_CLK) PULL-DOWN AND MUST BE 0 V AT RESET. The

RESERVED

GPIO8

pad may be left unconnected

DNI

GPIO21

Global Swap Lock on
Multiple GPUs

+3VSG
1 VGA@
1 VGA@
@
1
@
1
@
1

2
2
2
2
2

R405
R406
R408
R409

1 VGA@
@
1
@
1
@
1

2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%
2 3K_0402_5%

VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
VGA_GPIO3
VGA_GPIO4

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
GPIO_22_ROMCSB

AJ21
AK21

Move to
DDCCLK_AUX3P,DDCDATA_AUX3N, AK26
AJ26

GPIO6 voltage control signal ,No use can NC
VGA_GPIO0
VGA_GPIO1
R02 modify, R03 modify BOM
VGA_GPIO2
VGA_SMB_DA2 R469 1 VGA@ 2 0_0402_5% VGA_GPIO3
VGA_SMB_CK2 R527 1 VGA@ 2 0_0402_5% VGA_GPIO4

DISCRETE ONLY

<10> VGA_ENBKL

D
I
M
A
R
V

VGA_ENBKL

2 DISO@ 1
R413 10K_0402_5%

GPIO7 Controls backlight on/off.
Active High ,need external PD

ROM

if GPIO22 High ,GPIO 11-13->CFG[0:2]
Config ROM type ,GPU has internal PD

1
2
1

For ATI Cross fire
no use can NC
VGA_HDMI_DET

0

SAM 933 K4W1G1646G-BC11 64Mx16

01h

0

0

0

1

SAM 933 K4W2G1646C-HC11 128Mx16

02h

0

0

1

0

03h

0

0

1

1

04h

0

1

0

0

AMD 900 23EY2387MB11 64Mx16

05h

0

1

0

1

AMD 900 23EY4187MA11 128Mx16

0

1

1

0

07h

0

1

1

1

R430 1 VGA@

+1.8VSG

R431 1 VGA@
C335

0

HYN 900 H5TQ1G63DFR-11C

0

1

HYN 900 H5TQ2G63BFR-11C

0Ah

1

0

1

0

0Bh

1

0

1

1

0Ch

1

1

0

0

MIC 900 MT41J64M16JT-107G:G

0Dh

1

1

0

1

MIC 900 MT41J128M16HA-107G:D

2

2

VGA@ L11
+DPLL_VDDC
2
1
BLM18AG121SN1D_2P 1 VGA@ 1 VGA@ 1 VGA@

0

1

1

2

2

2

20mil

27MCLK

AK24

HPD1

2

6

THM_ALERT#

GND

5

1
R391 @

THERM#

2
4.7K_0402_5%

+3VSG

ADM1032ARMZ-2REEL_MSOP8
+3VSG

R393
4.7K_0402_5%
VGA@

VGA@
Q8A
DMN66D0LDW-7_SOT363-6

1

6

EC_SMB_CK2

EC_SMB_CK2 <8,21,37>

DPD

4

EC_SMB_DA2

3

EC_SMB_DA2 <8,21,37>

VGA@ Q8B DMN66D0LDW-7_SOT363-6

AU20
AT19

NC_TX3P_DPD2P
NC_TX3M_DPD2N

AT21
AR20

NC_TX4P_DPD1P
NC_TX4M_DPD1N

AU22
AV21

NC_TX5P_DPD0P
NC_TX5M_DPD0N

AT23
AR22

R
RB

AD39
AD37

VGA_CRT_R <24>

G
GB

AE36
AD35

VGA_CRT_G <24>

B
BB

AF37
AE38

VGA_CRT_B <24>

HSYNC
VSYNC

AC36
AC38

VGA_CRT_HSYNC <24>
VGA_CRT_VSYNC <24>

RSET

AB34

DAC1

70mA
100mA

R414

1

2

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

499_0402_1%

2
VGA@

AVDD
AVSSQ

AD34
AE34

+AVDD

VDD1DI
VSS1DI

AC33
AC34

+VDD1DI

10mil
VGA@

10mil

1

2
R2/NC
R2B/NC

AC30
AC31

G2/NC
G2B/NC

AD30
AD31

B2/NC
B2B/NC

AF30
AF31

C/NC
Y/NC
COMP/NC

AC32
AD32
AF32

H2SYNC/GENLK_CLK
V2SYNC/GENLK_VSYNC

AD29
AC29

VDD2DI/NC
VSS2DI/NC

AG31
AG32

A2VDD/NC

AG33

A2VDDQ/NC

AD33

2
VGA@

VGA@
1

2

1

2

2

2

DAC2

2

T2
T3

R423 1 DISO@ 2 150_0402_1%
R424 1 DISO@ 2 150_0402_1%
R425 1 DISO@ 2 150_0402_1%

HSYNC:VSYNC
11: Audio for both DisplayPort and HDMI

L8
BLM18AG121SN1D_2P
1
+1.8VSG
VGA@

AUD Strap

AMD ref:120ohm/0.3A

CRT,HDMI
DDC

VGA_CRT_VSYNC
VGA_CRT_HSYNC

R417 1 DISO@ 2 10K_0402_5%
R418 1 DISO@ 2 10K_0402_5%

VGA_HDMI_SDATA
VGA_HDMI_SCLK

R419 1 DISO@ 2 10K_0402_5%
R420 1 DISO@ 2 10K_0402_5%

VGA_CRT_CLK
VGA_CRT_DATA

R421 1 DISO@ 2 10K_0402_5%
R422 1 DISO@ 2 10K_0402_5%

+3VSG

L9

VGA@ 1 VGA@ 1 VGA@ 1

2

1
+1.8VSG
VGA@
BLM18AG121SN1D_2P

AMD ref:120ohm/0.3A
SM010030010
200ma 120ohm@100mhz DCR 0.2

3

2mA
VREFG

A2VSSQ/TSVSSQ

AF33

R2SET/NC

AA29

VGA@

DDC1CLK
DDC1DATA

AM26
AN26

AUX1P
AUX1N

AM27
AL27

DDC2CLK
DDC2DATA

AM19
AL19

2

DDC/AUX
AN31

AW34
AW35

1
2
R436 VGA@ 715_0402_1%

75mA

PLL/CLOCK
DPLL_VDDC
XTALIN
XTALOUT
XO_IN

AUX2P
AUX2N

AN20
AM20

DDCCLK_AUX3P
DDCDATA_AUX3N

AL30
AM30

NC_DDCCLK_AUX4P
NC_DDCDATA_AUX4N

AL29
AM29

DDCCLK_AUX5P
DDCDATA_AUX5N

AN21
AM21

XO_IN2

@
0_0402_5%

10mil
1

DPLL_PVDD
DPLL_PVSS

VGA_HDMI_SCLK
VGA_HDMI_SDATA

4.7K_0402_5%
4.7K_0402_5%

AF29
AG29

DPLUS
DMINUS

AK32

TS_FDO

AL31

TS_A/NC

AJ32
AJ33

TSVDD
TSVSS

THERMAL

20mA

DDC6CLK
DDC6DATA

AJ30
AJ31

NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N

AK30
AK29

2
2

VGA_HDMI_SCLK <23>
VGA_HDMI_SDATA <23>

+3VSG
VGALVDS@
R399
1
R400
1
VGALVDS@

VGA_LCD_CLK
VGA_LCD_DAT

VGA_CRT_CLK
VGA_CRT_DATA

HDMI

Outputs are open drain and 5-V tolerant.
External pull-up resistors to 3.3 V or 5 V are required.
These signals must be pulled high (to 3.3 V or 5 V) before
or after VDDC and VDD_CT are powered up.

VGA_LCD_CLK <22>
VGA_LCD_DAT <22>

LVDS

VGA_CRT_CLK <24>
VGA_CRT_DATA <24>

CRT

A source detection pull-down resistor (100-k
5% tolerance) is required on each AUXP signal
and a pull-up resistor (100-k 5% tolerance) to
3.3 V is required on each AUXN signal.
4

S IC 216-0833000 A11 THAMES XT M2
THA@

VGA@
C352
0.1U_0402_16V4Z

2

ALERT#

VGA_SMB_DA2

AT17
AR16

100mA

R444

+TSVDD
1

D-

4

VGA_SMB_CK2

TX2P_DPC0P
TX2M_DPC0N

100mA

27MCLK
AV33
XTALOUT AU34

XO_IN2

R443
@
0_0402_5%

C351
1U_0402_6.3V6K

VGA@
C353
18P_0402_50V8J

L12
BLM18AG121SN1D_2P
2
1
VGA@
1
VGA@
C350
10U_0603_6.3V6M

VGA@ X4
2
1
27MHZ_16PF_X5H027000FG1H
VGA@
C354
18P_0402_50V8J

+1.8VSG

VGA_SMB_DA2

3

GPU_THERM_D-

1

NC_TXCDP_DPD3P
NC_TXCDM_DPD3N

125mA

4

VGA@
2
1
R445
1M_0402_5%

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
NC_GENERICF_HPD5
NC_GENERICG_HPD6

AM32
AN32

GPU_THERM_D+
GPU_THERM_D-

XTALOUT

AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

+VGA_VREF AH13

XO_IN

2

1

1

HPD

1 VGA@ 1 VGA@

C347
1U_0402_6.3V6K

0

0

1

TX1P_DPC1P
TX1M_DPC1N

AU16
AV15

DPC

20mil

C346
0.1U_0402_16V4Z

0

1

1

AT15
AR14

VGA_SMB_CK2

7

Not share via for other GND

VGA@

VGA@ L10
+DPLL_PVDD
2
1
BLM18AG121SN1D_2P
1
VGA@
C339
10U_0603_6.3V6M
2

C345
10U_0603_6.3V6M

1

1

TX0P_DPC2P
TX0M_DPC2N

8

SDATA

+3VSG

SCL
SDA

20mil

2 249_0402_1%

+1.0VSG

09h

0Fh

AT33
AU32
AU14
AV13

SCLK

D+

2 499_0402_1%

2 0.1U_0402_16V4Z

1

+1.8VSG

08h

0Eh

TX5P_DPB0P
TX5M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N

VDD

2

R392
4.7K_0402_5%
VGA@

2

0

C341
1U_0402_6.3V6K

0

C340
0.1U_0402_16V4Z

0

06h

SWAPLOCKA
SWAPLOCKB

VREFG:Use a voltage divider to set VREFG = 1.80 V / 3
(or 0.60-V nominal).

Van SPD Name

00h

1

DVPDATA ID3ID2ID1ID0

1

2

2

T21
T18
T22
T25
T17

Internal Debug
no use can floating
ON(1)/OFF(0)
Stereo Sync
no use can NC

2

1

1
2

2
1

1

1
2

GPIO_22_ROMCSB

<23> VGA_HDMI_DET

3

TX4P_DPB1P
TX4M_DPB1N

AR32
AT31

DPB

1
GPU_THERM_D+
2200P_0402_50V7K
C325 1
2 @

R03 modify BOM

C334
10U_0603_6.3V6M

1

GPU_VID1

<49> GPU_VID1

External BIOS device
ON(1)/OFF(0) inter PD

R435

AV31
AU30

C333
0.1U_0402_16V4Z

R434

AR30
AT29

TX3P_DPB2P
TX3M_DPB2N

C332
1U_0402_6.3V6K

R433

GPU_VID0
VDDCI_VID
THM_ALERT#
VGA_EDP_HPD

<49> GPU_VID0
<45> VDDCI_VID

Reserved
VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3

VGA_GPIO11
VGA_GPIO12
VGA_GPIO13

<22> VGA_EDP_HPD

Critical temperature fault

10K_0402_5%
X76@

10K_0402_5%
X76@

10K_0402_5%
X76@

10K_0402_5%
X76@
2

10K_0402_5%
X76@

10K_0402_5%
X76@

10K_0402_5%

X76@

10K_0402_5%
X76@
R432

GPIO6,15,16,20
Voltage control signal
GPIO6,15 no use can NC
Thermal monitor interrupt

R429

TXCBP_DPB3P
TXCBM_DPB3N

C331
22U_0805_6.3V6M

R428

VGA_HDMI_TXD2+ <23>
VGA_HDMI_TXD2- <23>

2

C330
0.1U_0402_16V4Z

R427

TX2P_DPA0P
TX2M_DPA0N

AT27
AR26

VGA_HDMI_TXD0+ <23>
VGA_HDMI_TXD0- <23>

C329
1U_0402_6.3V6K

R426

VGA_HDMI_TXD1+ <23>
VGA_HDMI_TXD1- <23>

GENERAL PURPOSE I/O

2

+1.8VSG

NC_DVPCNTL_MVP_0
NC_DVPCNTL_MVP_1
NC_DVPCNTL_0
NC_DVPCNTL_1
NC_DVPCNTL_2
NC_DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
NC_DVPDATA_17
NC_DVPDATA_18
NC_DVPDATA_19
NC_DVPDATA_20
NC_DVPDATA_21
NC_DVPDATA_22
NC_DVPDATA_23

I2C

GPIO5 fast-power reduction:
HW control will casue display disturb
should use SW method control

e
d
i
s
C
E
t
a
K
0
0
1
D
P

R395
R396
R397
R398
R401

TX1P_DPA1P
TX1M_DPA1N

AU26
AV25

DPA

001

Enable external BIOS ROM device (Internal PD)
0: Diable, 1: Enable

BIOS_ROM_EN GPIO22
AUD[1]

1

AT25
AR24

1 @

2

TX_PWRS_ENB

Transmitter Power Saving Enable (Internal PD)
0: 50% Tx output swing
1: full Tx output swing

TX0P_DPA2P
TX0M_DPA2N

MUTI GFX

0

VGA_HDMI_TXC+ <23>
VGA_HDMI_TXC- <23>

5

GPIO9

AU24
AV23

2

VGA Disable determines (Internal PD)
0: VGA Controller capacity enabled
1: The device will not be recognized as the system’s VGA controller

TXCAP_DPA3P
TXCAM_DPA3N

2

0

C324
0.1U_0402_16V4Z

VGA_DIS

External VGA Thermal Sensor

+3VSG

U9 @

VIP Device Strap Enable indicates to the software driver (Internal PD)
V2SYNC 0: Driver would ignore the value sampled on VHAD_0 during reset
(GENLK_VSYNC) 1: VHAD_0 to determine whether or not a VIP slave device

VIP_DEVICE_EN

1

Pin Straps description 

1

Strap Name

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Deciphered Date

2015/07/08

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

A

B

C

D

Wednesday, February 29, 2012
E

Sheet

14

of

52

2

15mil

1

MVREFSA

2

VGA@

2

+1.5VSG
3

R454
R455
R456
R457
R458
R460

L27
1 VGA@ 2
1 VGA@ 2 243_0402_1% N12
1 VGA@ 2 243_0402_1% AG12
243_0402_1%
M12
1 VGA@ 2
1 VGA@ 2 243_0402_1% M27
1 VGA@ 2 243_0402_1% AH12
243_0402_1%

CLKA0
CLKA0#

J14
H14

CLKA1
CLKA1#

K23
K19

RASA0#
RASA1#

K20
K17

CASA0#
CASA1#

K24
K27

CSA0#_0

M13
K16

CSA1#_0

NC_CKEA0
NC_CKEA1

K21
J20

CKEA0
CKEA1

NC_MEM_CALRN0
MEM_CALRN1
NC_MEM_CALRN2

NC_WEA0B
NC_WEA1B

K26
L15

WEA0#
WEA1#

MEM_CALRP1
NC_MEM_CALRP0
NC_MEM_CALRP2

NC_MAA0_8
NC_MAA1_8

H23
J19

1

2

QSA#[0..7] <18>
+1.5VSG

R451
VGA@
40.2_0402_1%
ODTA0 <18>
ODTA1 <18>

15mil
MVREFSB

CLKA0 <18>
CLKA0# <18>
CLKA1 <18>
CLKA1# <18>

1

R453
VGA@
100_0402_1%

VGA@

RASA0# <18>
RASA1# <18>

2

CASA0# <18>
CASA1# <18>
CSA0#_0 <18>
CSA1#_0 <18>
CKEA0 <18>
CKEA1 <18>

MVREFDB Y12
MVREFSB AA12

WEA0# <18>
WEA1# <18>
MAA13 <18>

TESTEN

AK10
AL10

CLKTESTA
CLKTESTB

2

2

1

1

C361
0.1U_0402_16V4Z

@
S IC 216-0833000 A11 THAMES XT M2
THA@

AD28

TEST_MCLK
TEST_YCLK
C360
0.1U_0402_16V4Z

Differential for testing
and DNI component
for normal operation.

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7

H3
H1
T3
T5
AE4
AF5
AK6
AK5

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

DDBIB0_0/QSB_0B/WDQSB_0
DDBIB0_1/QSB_1B/WDQSB_1
DDBIB0_2/QSB_2B/WDQSB_2
DDBIB0_3/QSB_3B/WDQSB_3
DDBIB1_0/QSB_4B/WDQSB_4
DDBIB1_1/QSB_5B/WDQSB_5
DDBIB1_2/QSB_6B/WDQSB_6
DDBIB1_3/QSB_7B/WDQSB_7

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

T7
W7

ODTB0
ODTB1

CLKB0
CLKB0B

L9
L8

CLKB0
CLKB0#

CLKB1
CLKB1B

AD8
AD7

CLKB1
CLKB1#

RASB0B
RASB1B

T10
Y10

RASB0#
RASB1#

CASB0B
CASB1B

W10
AA10

CASB0#
CASB1#

CSB0B_0
CSB0B_1

P10
L10

CSB0#_0

CSB1B_0
CSB1B_1

AD10
AC10

CSB1#_0

CKEB0
CKEB1

U10
AA11

CKEB0
CKEB1

WEB0B
WEB1B

N10
AB11

WEB0#
WEB1#

MAB0_8
MAB1_8

T8
W8

ADBIB0/ODTB0
ADBIB1/ODTB1

MVREFDB
MVREFSB

R459
5.11K_0402_1%
TESTEN
2 VGA@ 1

MAB[0..12]

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

MEMORY INTERFACE B

NC_MVREFDA
NC_MVREFSA

2

L18
L20

H27
G27

1

MVREFDA
MVREFSA

ODTA0
ODTA1

QSA#[0..7]

C358
0.1U_0402_16V4Z

100_0402_1%

C357
0.1U_0402_16V4Z

R452 VGA@

1

J21
G19

VGA@

DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63

DRAM_RST

B_BA[0..2]

B_BA[0..2] <19>

DQMB#[0..7] <19>

QSB[0..7] <19>

QSB#[0..7]

QSB#[0..7] <19>

2

ODTB0 <19>
ODTB1 <19>
CLKB0 <19>
CLKB0# <19>
CLKB1 <19>
CLKB1# <19>
RASB0# <19>
RASB1# <19>
CASB0# <19>
CASB1# <19>
CSB0#_0 <19>
CSB1#_0 <19>
CKEB0 <19>
CKEB1 <19>
3

WEB0# <19>
WEB1# <19>
MAB13 <19>

AH11

1
2
VGA@
R461
10_0402_5%
VGA@
R463
5.11K_0402_1%

S IC 216-0833000 A11 THAMES XT M2
THA@

1
2
VGA@
R462
51.1_0402_1%

VRAM_RST# <18,19>

1 VGA@
C359
120P_0402_50V8
2

R465
@
51.1_0402_1%

Place all these components very close
to GPU (Within 25mm) and
keep all component close to
each Other (within5mm) except Rser2

2

2

1

QSB[0..7]

@

R464
@
51.1_0402_1%

MAB[0..12] <19>

DQMB#[0..7]

2

40.2_0402_1%

1

R449 VGA@
100_0402_1%

DDR2
GDDR5/GDDR3
DDR3

1

VGA@

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

15mil
MVREFDB

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

GDDR5

R450

A34
E30
E26
C20
C16
C12
J11
F8

QSA[0..7] <18>

1

1

2

R447
VGA@
40.2_0402_1%
QSA[0..7]

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

DQMA#[0..7] <18>

1

+1.5VSG

+1.5VSG
DQMA#[0..7]

C34
D29
D25
E20
E16
E12
J10
D7

A_BA[0..2] <18>

2

1
2

VGA@

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

A_BA[0..2]

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

C356
0.1U_0402_16V4Z

2

C355
0.1U_0402_16V4Z

1

A32
C32
D23
E22
C14
A14
E10
D9

<19> MDB[0..63]

E

U8D
DDR2
GDDR3/GDDR5
DDR3

MDB[0..63]

1

15mil
MVREFDA

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1

MAA[0..12] <18>

2

2

VGA@
40.2_0402_1%

NC_DQA0_0/DQA_0
NC_MAA0_0/MAA_0
NC_DQA0_1/DQA_1
NC_MAA0_1/MAA_1
NC_DQA0_2/DQA_2
NC_MAA0_2/MAA_2
NC_DQA0_3/DQA_3
NC_MAA0_3/MAA_3
NC_DQA0_4/DQA_4
NC_MAA0_4/MAA_4
NC_DQA0_5/DQA_5
NC_MAA0_5/MAA_5
NC_DQA0_6/DQA_6
NC_MAA0_6/MAA_6
NC_DQA0_7/DQA_7
NC_MAA0_7/MAA_7
NC_DQA0_8/DQA_8
NC_MAA1_0/MAA_8
NC_DQA0_9/DQA_9
NC_MAA1_1/MAA_9
NC_DQA0_10/DQA_10
NC_MAA1_2/MAA_10
NC_DQA0_11/DQA_11
NC_MAA1_3/MAA_11
NC_DQA0_12/DQA_12
NC_MAA1_4/MAA_12
NC_DQA0_13/DQA_13
NC_MAA1_5/MAA_13_BA2
NC_DQA0_14/DQA_14
NC_MAA1_6/MAA_14_BA0
NC_DQA0_15/DQA_15
NC_MAA1_7/MAA_A15_BA1
NC_DQA0_16/DQA_16
NC_DQA0_17/DQA_17
NC_WCKA0_0/DQMA_0
NC_DQA0_18/DQA_18
NC_WCKA0B_0/DQMA_1
NC_DQA0_19/DQA_19
NC_WCKA0_1/DQMA_2
NC_DQA0_20/DQA_20
NC_WCKA0B_1/DQMA_3
NC_DQA0_21/DQA_21
NC_WCKA1_0/DQMA_4
NC_DQA0_22/DQA_22
NC_WCKA1B_0/DQMA_5
NC_DQA0_23/DQA_23
NC_WCKA1_1/DQMA_6
NC_DQA0_24/DQA_24
NC_WCKA1B_1/DQMA_7
GDDR5/DDR2/GDDR3
NC_DQA0_25/DQA_25
NC_DQA0_26/DQA_26 NC_EDCA0_0/QSA_0/RDQSA_0
NC_DQA0_27/DQA_27 NC_EDCA0_1/QSA_1/RDQSA_1
NC_DQA0_28/DQA_28 NC_EDCA0_2/QSA_2/RDQSA_2
NC_DQA0_29/DQA_29 NC_EDCA0_3/QSA_3/RDQSA_3
NC_DQA0_30/DQA_30 NC_EDCA1_0/QSA_4/RDQSA_4
NC_DQA0_31/DQA_31 NC_EDCA1_1/QSA_5/RDQSA_5
NC_DQA1_0/DQA_32
NC_EDCA1_2/QSA_6/RDQSA_6
NC_DQA1_1/DQA_33
NC_EDCA1_3/QSA_7/RDQSA_7
NC_DQA1_2/DQA_34
NC_DQA1_3/DQA_35 NC_DDBIA0_0/QSA_0B/WDQSA_0
NC_DQA1_4/DQA_36 NC_DDBIA0_1/QSA_1B/WDQSA_1
NC_DQA1_5/DQA_37 NC_DDBIA0_2/QSA_2B/WDQSA_2
NC_DQA1_6/DQA_38 NC_DDBIA0_3/QSA_3B/WDQSA_3
NC_DQA1_7/DQA_39 NC_DDBIA1_0/QSA_4B/WDQSA_4
NC_DQA1_8/DQA_40 NC_DDBIA1_1/QSA_5B/WDQSA_5
NC_DQA1_9/DQA_41 NC_DDBIA1_2/QSA_6B/WDQSA_6
NC_DQA1_10/DQA_42NC_DDBIA1_3/QSA_7B/WDQSA_7
NC_DQA1_11/DQA_43
NC_DQA1_12/DQA_44
NC_ADBIA0/ODTA0
NC_DQA1_13/DQA_45
NC_ADBIA1/ODTA1
NC_DQA1_14/DQA_46
NC_DQA1_15/DQA_47
NC_CLKA0
NC_DQA1_16/DQA_48
NC_CLKA0B
NC_DQA1_17/DQA_49
NC_DQA1_18/DQA_50
NC_CLKA1
NC_DQA1_19/DQA_51
NC_CLKA1B
NC_DQA1_20/DQA_52
NC_DQA1_21/DQA_53
NC_RASA0B
NC_DQA1_22/DQA_54
NC_RASA1B
NC_DQA1_23/DQA_55
NC_DQA1_24/DQA_56
NC_CASA0B
NC_DQA1_25/DQA_57
NC_CASA1B
NC_DQA1_26/DQA_58
NC_DQA1_27/DQA_59
NC_CSA0B_0
NC_DQA1_28/DQA_60
NC_CSA0B_1
NC_DQA1_29/DQA_61
NC_DQA1_30/DQA_62
NC_CSA1B_0
NC_DQA1_31/DQA_63
NC_CSA1B_1

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

D

1

R446

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

MAA[0..12]

GDDR5

1

+1.5VSG

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

C

DDR2
GDDR5/GDDR3
DDR3

MEMORY INTERFACE A

1

R448 VGA@

U8C
DDR2
GDDR3/GDDR5
DDR3

MDA[0..63]

<18> MDA[0..63]

100_0402_1%

B

2

A

The suggested components are tested on the AMD
reference board only. Customers must measure the slew
on each memory part to ensure that the slew rate meets
the DRAM specification.

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Deciphered Date

2015/07/08

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

A

B

C

4

D

Wednesday, February 29, 2012
E

Sheet

15

of

52

A

B

C

D

E

R04 Modify BOM
U8E
+1.5VSG

1
2

+

C425
1U_0402_6.3V6K

1

VGA@
C436
330U_2.5V_M

2

VGA@
1

VGA@
1

VGA@
1

VGA@
1

VGA@
1

VGA@
1

L19 VGA@
2
1
FBMA-L11-201209-121LMA50T_0805

2

2

2

2

2

2

2

2

2

2

+VGA_CORE

L21 VGA@
2
1
FBMA-L11-201209-121LMA50T_0805

No Pop for Heathrow and Chelsea
VGA@

1

2

VGA@

1

2

VGA@

1

2

VGA@

1

2

VGA@

1

2

C465
10U_0603_6.3V6M

FB_GND

2

C457
1U_0402_6.3V6K

FB_VDDCI

AH29

VGA@
1

C464
10U_0603_6.3V6M

AG28

VGA@
1

C463
10U_0603_6.3V6M

@
R466
0_0402_5%

FB_VDDC

2

2

VGA@
1

C462
0.1U_0402_16V4Z

FB_GND

AF28

2

C456
1U_0402_6.3V6K

VDDCI_SEN

10mil

1

VGA@

VGA@
C435
330U_2.5V_M

VGA@
1

C455
1U_0402_6.3V6K

GCORE_SEN

+

2

VGA@

+VDDCI

C454
1U_0402_6.3V6K

VOLTAGE
SENESE

1

VGA@

2

160mil

C461
1U_0402_6.3V6K

<45> VDDCI_SEN

SPVSS

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

+VDDCI

C453
1U_0402_6.3V6K

<49> GCORE_SEN

AN10

1

2

VGA@

SM01000BY00 5000ma 120ohm@100mhz DCR 0.02
Granville VDDCI:4.6A

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
5A VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
ISOLATED VDDCI#15
CORE I/O VDDCI#16
VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22

2

1

VGA@

2

3

C452
1U_0402_6.3V6K

2

120mA

1

VGA@

2

VGA@

BIF_VDDC
Park/Madison:Connect to VDDC
Seymour/Whisler:
dGPU operating:VDDC
BACO mode:+1.0V

C451
1U_0402_6.3V6K

2

SPV10

2

1

VGA@

2

(GDDR3/DDR3 1.12V@4A VDDCI)

C450
1U_0402_6.3V6K

2

470ohm/1A

SM010030010
200ma 120ohm@100mhz DCR 0.2

VGA@

AN9

1

VGA@

2

VGA@

VDDCI and VDDC should have seperate regulators with a merge option on PCB
For Madison and Park, VDDCI and VDDC can share one common regulator

C449
1U_0402_6.3V6K

1

75mA

2

1

VGA@

2

+VGA_CORE

2010/04/27
non-BACO design,N27,T27
connect BIF_VDDC to VDDC
For BACO design

C448
1U_0402_6.3V6K

VGA@
1

+SPV10

C447
0.1U_0402_16V4Z

VGA@
1

C446
1U_0402_6.3V6K

BLM18AG121SN1D_2P
VGA@

20mil

SPV18

1

VGA@

2

VGA@

1

C414
1U_0402_6.3V6K

1

150mA

AM10

+BIF_VDDC

2

1

VGA@

2

1

C424
1U_0402_6.3V6K

2

+SPV_18

1

VGA@

2

VGA@

1

C413
1U_0402_6.3V6K

+1.0VSG

C445
10U_0603_6.3V6M

2

L18

+BIF_VDDC

2

1

VGA@

2

1

C423
1U_0402_6.3V6K

VGA@
1

C460
0.1U_0402_16V4Z

2

C459
1U_0402_6.3V6K

C458
10U_0603_6.3V6M

2

VGA@
1

MPV18#1
MPV18#2

1

VGA@

2

2

VGA@

1

C412
1U_0402_6.3V6K

10mil
VGA@
1

H7
H8

VGA@

2

1

VGA@

2

2

1

C434
10U_0603_6.3V6M

L20
2
1
BLM18AG121SN1D_2P
VGA@

+MPV_18

1
VGA@

1

VGA@

2

VGA@

2

1

C422
1U_0402_6.3V6K

+1.8VSG

20mil

1
VGA@

1

VGA@

2

1

C411
1U_0402_6.3V6K

SM010030010
200ma 120ohm@100mhz DCR 0.2

PLL

VGA@

1

C395
10U_0603_6.3V6M

2

1

C433
10U_0603_6.3V6M

2

2

C421
1U_0402_6.3V6K

2

NC_VDDRHB
NC_VSSRHB

2

+1.0VSG

C410
1U_0402_6.3V6K

2

V12
U12

2

C394
1U_0402_6.3V6K

2

C444
0.1U_0402_16V4Z

VGA@
1

C443
1U_0402_6.3V6K

VGA@
1

C442
0.1U_0402_16V4Z

VGA@
1

C441
1U_0402_6.3V6K

VGA@
1

C440
10U_0603_6.3V6M

3

VGA@
1

2

C432
10U_0603_6.3V6M

L17
2
1
BLM18AG121SN1D_2P
VGA@

NC_VDDRHA
NC_VSSRHA

2

C420
1U_0402_6.3V6K

+1.8VSG

M20
M21

2

C409
1U_0402_6.3V6K

SM010030010
200ma 120ohm@100mhz DCR 0.2

2

C370
1U_0402_6.3V6K

470ohm/1A

2

C431
10U_0603_6.3V6M

170mA

VGA@
1

C419
1U_0402_6.3V6K

VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#6

VGA@
1

C408
1U_0402_6.3V6K

AD12
AF11
AF12
AG11

VGA@
1

C369
1U_0402_6.3V6K

VDDR4#4
VDDR4#5
VDDR4#7
VDDR4#8

VGA@
1

C430
10U_0603_6.3V6M

AF13
AF15
AG13
AG15

20mil
+VDDR4_5

60mA

VGA@
1

C418
1U_0402_6.3V6K

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

1

VGA@
1

C407
1U_0402_6.3V6K

AF23
AF24
AG23
AG24

1
+1.8VSG
L13 VGA@
FBMA-L11-201209-221LMA30T_0805

220ohm/2A

VGA@
1

C393
1U_0402_6.3V6K

+VDDR3

10mil

2

VGA@
1

C368
1U_0402_6.3V6K

I/O

2

C429
10U_0603_6.3V6M

2

219mA

2

2

C417
1U_0402_6.3V6K

1

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

2

C406
1U_0402_6.3V6K

AF26
AF27
AG26
AG27

2

C428
10U_0603_6.3V6M

2

20mil
+VDD_CT

2

C416
1U_0402_6.3V6K

2

VGA@

VGA@
C439
0.1U_0402_16V4Z

VGA@

VGA@
1

C438
1U_0402_6.3V6K

VGA@
1

C437
10U_0603_6.3V6M

L16
120ohm/0.3ABLM18AG121SN1D_2P

2

LEVEL
TRANSLATION

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

VGA@
1

C405
1U_0402_6.3V6K

1

1

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
47A VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC/BIF_VDDC#33
VDDC#34
VDDC#35
VDDC#36
55mA VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC/BIF_VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
CORE

POWER

2

+1.8VSG

2

VGA@
C426
1U_0402_6.3V6K

2

C415
10U_0603_6.3V6M

2

1

VGA@

VGA@

2

C427
0.1U_0402_16V4Z

1

1

VGA@
1

C392
1U_0402_6.3V6K

Ref137-12~ remove Bead
+3VSG

2

VGA@
C403
1U_0402_6.3V6K

2

C402
10U_0603_6.3V6M

VGA@

1

VGA@

3400mA 2A

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

+PCIE_VDDR
VGA@ VGA@
1
1

C391
1U_0402_6.3V6K

1

2

C404
0.1U_0402_16V4Z

2
1
L14
BLM18AG121SN1D_2P

2

C401
1U_0402_6.3V6K

2

C400
1U_0402_6.3V6K

2

C399
1U_0402_6.3V6K

2

C398
1U_0402_6.3V6K

2

C397
10U_0603_6.3V6M

+1.8VSG

2

C373
10U_0603_6.3V6M

2

C372
10U_0603_6.3V6M

VGA@
1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

VGA@
1

C384
10U_0603_6.3V6M

2

VGA@
1

C365
1U_0402_6.3V6K

2

SM010014520 3000ma 220ohm@100mhz DCR 0.04

40mil

AA31
AA32
AA33
AA34
V28
W29
W30
Y31
AB37

C383
1U_0402_6.3V6K

2

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
440mA PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
PCIE_VDDR/PCIE_PVDD

C364
1U_0402_6.3V6K

2

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34

C382
0.1U_0402_16V4Z

2

C390
1U_0402_6.3V6K

2

C389
1U_0402_6.3V6K

2

C367
1U_0402_6.3V6K

2

C388
1U_0402_6.3V6K

VGA@
1

C387
1U_0402_6.3V6K

VGA@
1

C386
1U_0402_6.3V6K

VGA@
1

C366
1U_0402_6.3V6K

VGA@
1

PCIE

AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

C381
0.1U_0402_16V4Z

C363
1U_0402_6.3V6K

2

VGA@
1

120ohm/0.3A

SM010030010
300ma 120ohm@100mhz DCR 0.3

2

C380
1U_0402_6.3V6K

2

C379
1U_0402_6.3V6K

2

MEM I/O

VGA@
1

VGA@
1

C371
10U_0603_6.3V6M

SM010030010
300ma 120ohm@100mhz DCR 0.3

2

VGA@
1

VGA@
1

C385
1U_0402_6.3V6K

2

C396
10U_0603_6.3V6M

VGA@

2

VGA@
1

VGA@
1
1

1

2

VGA@
1

C378
1U_0402_6.3V6K

2

VGA@
1

C377
1U_0402_6.3V6K

2

VGA@
1

C362
1U_0402_6.3V6K

+

VGA@
1

C376
1U_0402_6.3V6K

@
C374
330U_2.5V_M

C375
1U_0402_6.3V6K

VGA@
1

1

S IC 216-0833000 A11 THAMES XT M2
THA@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Deciphered Date

2015/07/08

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

A

B

C

D

Wednesday, February 29, 2012
E

Sheet

16

of

52

A

B

U8F

1

1

U8H
DP C/D POWER

Manhatann:300mA
Seymour:150mA

20mil
+DPABCD_VDD18

AP13
AT13
AN17
AP16
AP17
AW14
AW16

20mil
+DPABCD_VDD18

DPCD/DPC_VDD18#1
DPCD/DPC_VDD18#2

DPCD/DPC_VDD10#1
DPCD/DPC_VDD10#2

DPAB/DPA_VDD18#1
DPAB/DPA_VDD18#2

AN24
AP24

DPAB/DPA_VDD10#1
DPAB/DPA_VDD10#2

AP31
AP32

DP/DPA_VSSR#1
DP/DPA_VSSR#2
DP/DPA_VSSR#3
DP/DPA_VSSR#4
DP/DPA_VSSR#5

AN27
AP27
AP28
AW24
AW26

DP/DPC_VSSR#1
DP/DPC_VSSR#2
DP/DPC_VSSR#3
DP/DPC_VSSR#4
DP/DPC_VSSR#5

20mil
+DPABCD_VDD18

20mil
+DPABCD_VDD10

+DPABCD_VDD10

1

2

VGA@

DPCD/DPD_VDD18#1
DPCD/DPD_VDD18#2

DPAB/DPB_VDD18#1
DPAB/DPB_VDD18#2

AP25
AP26

+DPABCD_VDD18

2

VGA@

1

2

+1.8VSG

VGA@

AP14
AP15

DPCD/DPD_VDD10#1
DPCD/DPD_VDD10#2

DPAB/DPB_VDD10#1
DPAB/DPB_VDD10#2

AN33
AP33

+DPABCD_VDD10

20mil

SM01000BL00
1000ma 470ohm@100mhz DCR 0.2
L25
MCK1608471YZF_0603
2
1
VGA@

220mA

+1.0VSG
2

PX_EN <20>
2

PX_EN: PU at P.20
SBIOS will control VGA power on/off.
High :BACO mode enable
LOW:BACO disable

2

2

+1.0VSG

+DPEF_VDD18

DP mode:220mA

2

DPAB_CALR

AW28

AH34
AJ34

DP E/F POWER
DPEF/DPE_VDD18#1
DPEF/DPE_VDD18#2

DP PLL POWER
DPAB_VDD18/DPA_PVDD
DP_VSSR/DPA_PVSS

AU28
AV27

AL33
AM33

DPEF/DPE_VDD10#1
DPEF/DPE_VDD10#2

DPAB_VDD18/DPB_PVDD
DP_VSSR/DPB_PVSS

AV29
AR28

AN34
AP39
AR39
AU37

DP/DPE_VSSR#1
DP/DPE_VSSR#2
DP/DPE_VSSR#3
DP/DPE_VSSR#4

DPCD_VDD18/DPC_PVDD
DP_VSSR/DPC_PVSS

AU18
AV17

DPCD_VDD18/DPD_PVDD
DP_VSSR/DPD_PVSS

AV19
AR18

DPEF_VDD18/DPE_PVDD
DP_VSSR/DPE_PVSS

AM37
AN38

DPEF_VDD18/DPF_PVDD
DP_VSSR/DPF_PVSS

AL38
AM35

1

R468
150_0402_1%
2
VGA@

20mA
+DPABCD_VDD18

20mA
+DPABCD_VDD18

AF34
AG34

AK33
AK34

AF39
AH39
AK39
AL34
AM34

+DPABCD_VDD18

20mA
+DPABCD_VDD18

+DPEF_VDD18

20mA

DPEF/DPF_VDD10#1
DPEF/DPF_VDD10#2

2

2

10mil

10mil

10mil

10mil
3

20mA

DPEF/DPF_VDD18#1
DPEF/DPF_VDD18#2

20mil
+DPEF_VDD10

C483
0.1U_0402_16V4Z

C482
1U_0402_6.3V6K

2

DPCD_CALR

2

20mA

L27
MCK1608471YZF_0603 LVDS mode:240mA
2
1
VGA@
1 VGA@ 1 VGA@ 1 VGA@

2

AW18

20mil
+DPEF_VDD10

20mil
SM01000BL00
1000ma 470ohm@100mhz DCR 0.2

AN29
AP29
AP30
AW30
AW32

20mil
+DPEF_VDD18

C480
0.1U_0402_16V4Z

PX_EN

L26
MCK1608471YZF_0603
2
1
VGA@
1 VGA@ 1 VGA@ 1 VGA@

DP/DPB_VSSR#1
DP/DPB_VSSR#2
DP/DPB_VSSR#3
DP/DPB_VSSR#4
DP/DPB_VSSR#5

C477
10U_0603_6.3V6M

+1.8VSG

R467
150_0402_1%
2
1
VGA@

DP mode:300mA
LVDS mode:440mA

DP/DPD_VSSR#1
DP/DPD_VSSR#2
DP/DPD_VSSR#3
DP/DPD_VSSR#4
DP/DPD_VSSR#5

C476
1U_0402_6.3V6K

SM01000BL00
1000ma 470ohm@100mhz DCR 0.2

AN19
AP18
AP19
AW20
AW22

C475
0.1U_0402_16V4Z

1 VGA@ 1 VGA@ 1 VGA@

+DPEF_VDD18

10mil

10mil

DP/DPF_VSSR#1
DP/DPF_VSSR#2
DP/DPF_VSSR#3
DP/DPF_VSSR#4
DP/DPF_VSSR#5

R470
2

1 AM39
VGA@
150_0402_1%

DPEF_CALR
S IC 216-0833000 A11 THAMES XT M2
THA@

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

A39
AW1
AW39

Seymour/Whistler:
AL21:PX_EN
use to control discreate GPU regulators
for power express BACO mode
Support BACO:
output High3.3V:turn off regulators (BACO mode on)
output Low0V:turn on regulators (BACO mode off)
need PD resistor
No support BACO:
left NC

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

2015/07/08

Deciphered Date

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

Rev
B

4019H2

Date:

A

1

20mil

AP22
AP23

20mil
Manhatann:220mA
Seymour:110mA

L23
MCK1608471YZF_0603
2
1
VGA@

300mA

C471
1U_0402_6.3V6K

20mil
+DPABCD_VDD10

AP20
AP21

SM01000BL00
1000ma 470ohm@100mhz DCR 0.2

DP A/B POWER

Park/Madison :AL21left NC

S IC 216-0833000 A11 THAMES XT M2
THA@

REF137-13 update

DPx-VSSR,DPx_PVSS can combian to DP_VSSR
(Manhatann should have individual GND)
where x is A,B,C,D,E,F

C479
1U_0402_6.3V6K

GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162

E

C470
0.1U_0402_16V4Z

GND

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

C481
10U_0603_6.3V6M

4

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND/PX_EN#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98

C478
10U_0603_6.3V6M

3

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35

D

Seymour/Whistler：
DPA_VDD10,DPB_VDD10
can combian to DPAB_VDD10
DPC_VDD10,DPD_VDD10
can combian to DPCD_VDD10
DPE_VDD10,DPD_VDD10
can combian to DPEF_VDD10

C469
10U_0603_6.3V6M

2

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

C

DPA_VDD18,DPA_PVDD,DPB_VDD18,DPB_PVDD
can combian to DPAB_VDD18
DPC_VDD18,DPC_PVDD,DPD_VDD18,DPD_PVDD
can combian to DPCD_VDD18
(DPD_VDD18,DPD_PVDD not applicable on Robson/Park)
DPE_VDD18,DPE_PVDD,DPF_VDD18,DPF_PVDD
can combian to DPEF_VDD18

C

D

Sheet

Wednesday, February 29, 2012
E

17

of

52

C

M2
N8
M3

BA0
BA1
BA2

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSA2
QSA0

F3
C7

DQSL
DQSU

DQMA#2
DQMA#0

E7
D3

DML
DMU

QSA#2
QSA#0

G3
B7

DQSL
DQSU

T2

RESET

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

D7
C3
C8
C2
A7
A2
B8
A3

MDA0
MDA5
MDA1
MDA7
MDA3
MDA4
MDA2
MDA6

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

A_BA0
A_BA1
A_BA2

M2
N8
M3

BA0
BA1
BA2

CLKA0
CLKA0#
CKEA0

J7
K7
K9

CK
CK
CKE/CKE0

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTA0_1
CSA0#_0
RASA0#
CASA0#
WEA0#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSA3
QSA1

F3
C7

DQSL
DQSU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#3
DQMA#1

E7
D3

DML
DMU

QSA#3
QSA#1

G3
B7

DQSL
DQSU

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSG

<15> DQMA#[7..0]

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

<15>
<15>
<15>
<15>

CLKA1
CLKA1#

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSA4
QSA5

F3
C7

DQSL
DQSU

DQMA#4
DQMA#5

E7
D3

DML
DMU

QSA#4
QSA#5

G3
B7

DQSL
DQSU

CSA1#_0
RASA1#
CASA1#
WEA1#

VRAM_RST# T2

RESET

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

R473
243_0402_1%
128@

E3
F7
F2
F8
H3
H8
G2
H7

MDA35
MDA32
MDA38
MDA34
MDA37
MDA36
MDA39
MDA33

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDA43
MDA44
MDA40
MDA45
MDA42
MDA46
MDA41
MDA47

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VREFCA_A4
VREFDA_Q4

M8
H1

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

A_BA0
A_BA1
A_BA2

M2
N8
M3

BA0
BA1
BA2

CLKA1
CLKA1#
CKEA1

J7
K7
K9

CK
CK
CKE/CKE0

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTA1_1
CSA1#_0
RASA1#
CASA1#
WEA1#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSA6
QSA7

F3
C7

DQSL
DQSU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#6
DQMA#7

E7
D3

DML
DMU

QSA#6
QSA#7

G3
B7

DQSL
DQSU

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

+1.5VSG

+1.5VSG

VRAM_RST# T2

RESET

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

R474
243_0402_1%
128@

96-BALL
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
X76@
+1.5VSG

+1.5VSG

R477
4.99K_0402_1% 128@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDA48
MDA51
MDA55
MDA54
MDA50
MDA52
MDA49
MDA53

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDA63
MDA58
MDA60
MDA59
MDA61
MDA56
MDA62
MDA57

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

1

+1.5VSG

+1.5VSG

2

R478
4.99K_0402_1% 128@

96-BALL
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
X76@
+1.5VSG

+1.5VSG

R479
4.99K_0402_1% 128@

+1.5VSG

R480
4.99K_0402_1%
128@

R481
4.99K_0402_1% 128@

R482
4.99K_0402_1% 128@
3

128@

1

2

+1.5VSG

R491
4.99K_0402_1%
128@

C488
128@

1

2

2

2

VREFDA_Q3
R492
C489
4.99K_0402_1%
128@

1

VREFCA_A4

128@

2

R493
4.99K_0402_1%
128@

1

C490

VREFDA_Q4

128@

2

R494
C491
4.99K_0402_1%
128@
2

2

C487

1

VREFCA_A3
1

VREFDA_Q2

R490
4.99K_0402_1%
128@
2

2

+1.5VSG

2

128@

1

15mil
1

0.1U_0402_16V4Z

C485
128@

C486

15mil

0.1U_0402_16V4Z

2

VREFCA_A2
R489
4.99K_0402_1%
128@

15mil

0.1U_0402_16V4Z

1

15mil

0.1U_0402_16V4Z

2

R488
4.99K_0402_1%
128@

0.1U_0402_16V4Z

128@

1

0.1U_0402_16V4Z

C484

15mil

1

VREFDA_Q1
1

VREFCA_A1
R487
4.99K_0402_1%
128@

15mil

2

15mil

2

2

15mil

0.1U_0402_16V4Z

ODTA1_1

R476
4.99K_0402_1% 128@

0.1U_0402_16V4Z

R486
56_0402_1%
2
128@

R475
4.99K_0402_1% 128@

BA0
BA1
BA2

ODTA1_1

96-BALL
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
X76@
+1.5VSG

+1.5VSG

1

R484
56_0402_1%
128@
ODTA0 2
1
1
2
R483
0_0402_5% 128@

M2
N8
M3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

1

96-BALL
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
X76@
+1.5VSG

A_BA0
A_BA1
A_BA2

2

2

R472
243_0402_1%
128@

1

ODTA0_1

R485
0_0402_5%
ODTA1 2
1
1
128@

J1
L1
J9
L9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

<15> CKEA1

+1.5VSG

1

Pull high for Madison and Park...

<15> ODTA1

ZQ/ZQ0

1

+1.5VSG

<15> ODTA0

RESET

L8

B2
D9
G7
K2
K8
N1
N9
R1
R9

VREFCA
VREFDQ

1

1
2

R471
243_0402_1%
128@

3

VRAM_RST# T2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

1

VRAM_RST#

<15,19> VRAM_RST#

MDA15
MDA11
MDA14
MDA10
MDA13
MDA9
MDA12
MDA8

M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSG

2

<15> QSA#[7..0]

D7
C3
C8
C2
A7
A2
B8
A3

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

1

2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VREFCA_A3
VREFDA_Q3

1

<15> QSA[7..0]

MDA25
MDA30
MDA24
MDA29
MDA26
MDA31
MDA27
MDA28

2

CSA0#_0
RASA0#
CASA0#
WEA0#

E3
F7
F2
F8
H3
H8
G2
H7

2

<15>
<15>
<15>
<15>

+1.5VSG

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2

ODTA0_1

<15> MAA[13..0]

VREFCA
VREFDQ

1

CLKA0
CLKA0#
<15> CKEA0

M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

MDA[0..63]

<15> MDA[0..63]

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

2

<15> A_BA0
<15> A_BA1
<15> A_BA2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VREFCA_A2
VREFDA_Q2

2

1

MDA22
MDA19
MDA21
MDA18
MDA23
MDA16
MDA20
MDA17

1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2

VREFCA
VREFDQ

U14

2

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

E

U13

1

VREFCA_A1 M8
VREFDA_Q1 H1

D

U12

1

B

U11

1

A

128@

2

+1.5VSG
+1.5VSG

2

2

2

2

2

2

2

2

2

2

1
128@
2

C521
.01U_0402_16V7K

2

2

128@
1

128@
1

2

2

2

2

2

2

2

2

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

128@
1

2

C518
10U_0603_6.3V6M

1
128@

2

128@
1

C517
10U_0603_6.3V6M

2
56_0402_1%

128@
1
C516
10U_0603_6.3V6M

2

128@

128@
1
C515
10U_0603_6.3V6M

1
R498

C514
10U_0603_6.3V6M

<15> CLKA1#

2
56_0402_1%

C513
10U_0603_6.3V6M

1
R497

128@
1

C520
10U_0603_6.3V6M

128@
<15> CLKA1

128@
1

C519
10U_0603_6.3V6M

4

+1.5VSG

+1.5VSG
C512
.01U_0402_16V7K

128@
1

2011/07/08

C511
1U_0402_6.3V6K

2

128@
1

C510
1U_0402_6.3V6K

2

128@
1

C509
1U_0402_6.3V6K

2

128@
1

C508
1U_0402_6.3V6K

2

2
56_0402_1%

128@
1

C507
1U_0402_6.3V6K

2

128@

C506
1U_0402_6.3V6K

128@
1

C505
1U_0402_6.3V6K

128@
1

C504
1U_0402_6.3V6K

128@
1

C503
1U_0402_6.3V6K

128@
1

C502
1U_0402_6.3V6K

128@
1

C501
1U_0402_6.3V6K

128@
1

C500
1U_0402_6.3V6K

128@
1

C499
1U_0402_6.3V6K

128@
1

C498
1U_0402_6.3V6K

128@
1

C497
1U_0402_6.3V6K

128@
1

C496
1U_0402_6.3V6K

128@
1

C495
1U_0402_6.3V6K

1
R496

128@
1

C494
1U_0402_6.3V6K

<15> CLKA0#

2
56_0402_1%

128@
1

C493
1U_0402_6.3V6K

1
R495

128@
1

C492
1U_0402_6.3V6K

128@
<15> CLKA0

128@
1

2015/07/08

Deciphered Date

Title

SCHEMATIC,MB A8331

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

A

B

C

D

Sheet

Wednesday, February 29, 2012
E

18

of

52

A

B

C

U15
VREFCB_A1 M8
VREFDB_Q1 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

BA0
BA1
BA2

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSB3
QSB1

F3
C7

DQSL
DQSU

DQMB#3
DQMB#1

E7
D3

DML
DMU

QSB#3
QSB#1

G3
B7

DQSL
DQSU

T2

RESET

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

<15> B_BA0
<15> B_BA1
<15> B_BA2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB26
MDB28
MDB27
MDB31
MDB25
MDB30
MDB24
MDB29

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB15
MDB10
MDB12
MDB11
MDB13
MDB9
MDB14
MDB8

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

1

CLKB0
CLKB0#
<15> CKEB0
<15> MAB[13..0]

ODTB0_1
<15>
<15>
<15>
<15>

<15> DQMB#[7..0]

CSB0#_0
RASB0#
CASB0#
WEB0#

VREFCB_A2 M8
VREFDB_Q2 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

+1.5VSG

E

U17
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB22
MDB20
MDB21
MDB18
MDB19
MDB17
MDB23
MDB16

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB1
MDB6
MDB0
MDB4
MDB3
MDB7
MDB2
MDB5

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B_BA0
B_BA1
B_BA2

M2
N8
M3

BA0
BA1
BA2

CLKB0
CLKB0#
CKEB0

J7
K7
K9

CK
CK
CKE/CKE0

ODTB0_1
CSB0#_0
RASB0#
CASB0#
WEB0#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSB2
QSB0

F3
C7

DQSL
DQSU

DQMB#2
DQMB#0

E7
D3

DML
DMU

QSB#2
QSB#0

G3
B7

DQSL
DQSU

+1.5VSG

MDB[0..63]

<15> MDB[0..63]

D

U16
VREFCB_A3 M8
VREFDB_Q3 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B_BA0
B_BA1
B_BA2

M2
N8
M3

BA0
BA1
BA2

CLKB1
CLKB1#

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSB4
QSB5

F3
C7

DQSL
DQSU

DQMB#4
DQMB#5

E7
D3

DML
DMU

QSB#4
QSB#5

G3
B7

DQSL
DQSU

VRAM_RST#

T2

RESET

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

<15> CKEB1
ODTB1_1
<15>
<15>
<15>
<15>

CSB1#_0
RASB1#
CASB1#
WEB1#

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB35
MDB37
MDB34
MDB39
MDB33
MDB38
MDB32
MDB36

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB44
MDB43
MDB47
MDB41
MDB45
MDB40
MDB46
MDB42

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSG

+1.5VSG

U18
VREFCB_A4 M8
VREFDB_Q4 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B_BA0
B_BA1
B_BA2

M2
N8
M3

BA0
BA1
BA2

CLKB1
CLKB1#
CKEB1

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSB6
QSB7

F3
C7

DQSL
DQSU

DQMB#6
DQMB#7

E7
D3

DML
DMU

QSB#6
QSB#7

G3
B7

DQSL
DQSU

VRAM_RST#

T2

RESET

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

+1.5VSG

+1.5VSG

ODTB1_1
CSB1#_0
RASB1#
CASB1#
WEB1#

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB55
MDB49
MDB52
MDB50
MDB53
MDB48
MDB54
MDB51

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB56
MDB59
MDB63
MDB62
MDB57
MDB61
MDB58
MDB60

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

VREFCA
VREFDQ

1

+1.5VSG

+1.5VSG

<15> QSB[7..0]

96-BALL
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
X76@
+1.5VSG

R502
243_0402_1%

96-BALL
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
X76@

96-BALL
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
X76@

+1.5VSG

R524

2

2

1

2

R520
4.99K_0402_1%

C527
VGA@
VGA@

1

2

R521
4.99K_0402_1%

2

2

2

2

2

+1.5VSG

VGA@

1

2

1
VGA@ VGA@
2

1

2

VGA@
1

VGA@
1

VGA@
1

VGA@
1

VGA@
1

2

2

2

2

2

2

VGA@
4

Compal Electronics, Inc.

Compal Secret Data
2011/07/08

1

C558
10U_0603_6.3V6M

2

Issued Date

C529
VGA@
VGA@

C550
1U_0402_6.3V6K

VGA@
1

C549
1U_0402_6.3V6K

VGA@
1

1

Security Classification

VREFDB_Q4

R522
4.99K_0402_1%

C548
1U_0402_6.3V6K

VGA@
1

C557
10U_0603_6.3V6M

2

VGA@
1

C556
10U_0603_6.3V6M

2

2

2

C547
1U_0402_6.3V6K

2

VGA@
1

C555
10U_0603_6.3V6M

C559
.01U_0402_16V7K

2

1

+1.5VSG

C553
10U_0603_6.3V6M

2

2

2

C554
10U_0603_6.3V6M

VGA@

2

1 VGA@

C552
10U_0603_6.3V6M

1

2

1 VGA@ 1 VGA@ 1 VGA@
C551
10U_0603_6.3V6M

R525
56_0402_1%
1
2
VGA@
R526
56_0402_1%
1
2
VGA@

+1.5VSG

VGA@
1

C546
1U_0402_6.3V6K

2

VGA@
1

C528
VGA@
VGA@

C545
1U_0402_6.3V6K

2

VGA@
1

C544
1U_0402_6.3V6K

2

VGA@
1

C543
1U_0402_6.3V6K

2

VGA@
1

C542
1U_0402_6.3V6K

2

3

VGA@

VREFCB_A4

1

VREFDB_Q3

1
C526
VGA@
VGA@

2

2

R519
4.99K_0402_1%

2

2

1

C541
1U_0402_6.3V6K

C530
.01U_0402_16V7K

R510
4.99K_0402_1%

VGA@

2
1

VREFCB_A3

C525
VGA@
VGA@

C540
1U_0402_6.3V6K

VGA@
1

1

1

1

1

1

1

1
2

2

C539
1U_0402_6.3V6K

2

<15> CLKB1#

VREFDB_Q2

R518
4.99K_0402_1%

C538
1U_0402_6.3V6K

VGA@

4

1

C537
1U_0402_6.3V6K

VGA@
1

C536
1U_0402_6.3V6K

VGA@
1

C535
1U_0402_6.3V6K

VGA@
1

C534
1U_0402_6.3V6K

VGA@
1

1

<15> CLKB1

R509
4.99K_0402_1%

VGA@

+1.5VSG

56_0402_1%
2

C533
1U_0402_6.3V6K

VGA@

C524
VGA@
VGA@

+1.5VSG

C532
1U_0402_6.3V6K

1

2

+1.5VSG

C531
1U_0402_6.3V6K

<15> CLKB0#

VREFCB_A2
R517
4.99K_0402_1%

R508
4.99K_0402_1%

VGA@

0.1U_0402_16V4Z

R523 56_0402_1%
2
VGA@

1

+1.5VSG

0.1U_0402_16V4Z

1

2

C523
VGA@
VGA@

+1.5VSG

0.1U_0402_16V4Z

<15> CLKB0

VREFDB_Q1

R516
4.99K_0402_1%

+1.5VSG

0.1U_0402_16V4Z

ODTB1_1

1

R507
4.99K_0402_1%

VGA@

0.1U_0402_16V4Z

0_0402_5%

R515
C522
4.99K_0402_1% VGA@
VGA@

0.1U_0402_16V4Z

R514
56_0402_1%
2
VGA@

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

VGA@
ODTB1 R513

VGA@

1

VREFCB_A1

0_0402_5%

<15> ODTB1

VGA@

2

R512
56_0402_1%
2
VGA@

R506
4.99K_0402_1%

2

1

R505
4.99K_0402_1%

2

VGA@
ODTB0 R511

R504
4.99K_0402_1%

2

<15> ODTB0

R503
4.99K_0402_1% VGA@
2

3

1

1

+1.5VSG
ODTB0_1

VGA@

1

+1.5VSG

VGA@

2

+1.5VSG

R501
243_0402_1%

1

96-BALL
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
X76@
+1.5VSG

Pull high for Madison and Park...

VGA@

2

R500
243_0402_1%
2

2

VGA@

2

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

1

J1
L1
J9
L9

2

ZQ/ZQ0

2

1

RESET

L8

2

1
R499
243_0402_1%

VRAM_RST# T2

1

VRAM_RST#

<15,18> VRAM_RST#

2

<15> QSB#[7..0]

1

2

2015/07/08

Deciphered Date

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

A

B

C

D

Sheet

Wednesday, February 29, 2012
E

19

of

52

5

4

3

Power Sequence of Thames
VGA_PWR_ON
1.5_VDDC_PWREN
+3.3VSG
+1.8VSG
+1.0VSG
+VGA_CORE
+1.5VSG
+BIF_VDDC

SUSP#
+3VSG
10ms

VGA_ON
VGA_PWR_ON

D

1.5_VDDC_PWREN
+VGA_CORE
+1.5VSG
+1.0VSG
+1.8VSG

20ms

For PX sequence, >2mS delay is required between
PE_GPIO1 and VGA_PWR_ON

2

+5VALW

@
R1113
100K_0402_5%
1

PE_GPIO1

1

VGA_PWR_ON

G
S

D

Mapping table
Whistler and Seymour
VGA_ON
SUSP#
VGA_PWR_ON
VGA_PWR_ON
Combine with +VGA_CORE
1.5_VDDC_PWREN
1.5_VDDC_PWREN

Pop for matreial reduce 
NOBACO@ R649 1
+3VS

>2ms

@
Q62
2N7002K_SOT23-3
+3VS

2

B

R650 1 BACO@ 2 10K_0402_5%

1

A

C

1.5_VDDC_PWREN

4

Y

1.5_VDDC_PWREN

<40,45,47,49>

NC7SZ08P5X_NL_SC70-5

1

2

2 0_0402_5%

C1103 BACO@
0.1U_0402_16V4Z
1
2
BACO@
U19

VGA_PWR_ON

3

3

VGA@
R1115
100K_0402_5%

VGA Power Enable Signal
Graville
VGA_PWR_ON source signal INT_VGAPWR_ON
+3.3VSG
VGA_PWR_ON
VGA_PWR_ON
+1.8VSG
VGA_PWR_ON
+1.0VSG
VGA_PWR_ON
+VDDCI
VGA_PWR_ON
+VGA_CORE
VGA_PWR_ON
+1.5VSG

P

1

2

VGA Muxless with BACO Status Mapping table
Normal mode
BACO mode
PX_EN
0
1
1.5_VDDC_PWREN
1
0
VDDC_EN
1
0
1.0_EN
0
1
ON
+3.3VSG
ON
ON
+1.8VSG
ON
ON
+1.0VSG
ON
OFF
+VGA_CORE
ON
OFF
+1.5VSG
ON
+BIF_VDDC
+VGA_CORE
+1.0VSG

5

D
PE_GPIO1

1

G

PE_GPIO1#
C

2

VGA Muxless and Dis only Status Mapping table
Dis only
Muxless High performance GPU
Muxless Power-saving GPU
1
1
0
1
1
0
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
OFF
+VGA_CORE
+VGA_CORE

D

+3VALW

1 BACO@ 2
2
R651
0_0402_5% G

IN

BACO@
R653
1K_0402_5%
1

IN
7

74LVC14APW_TSSOP14

@

2
0_0402_5%

2

C213
.1U_0402_16V7K
1 VGA@

1
74LVC14APW_TSSOP14

R120
0_0402_5%

2

VGA_PWR_ON <40,46>
2

1

3
4

6

G
3

Pop for PX5 & DISO

2
G

1
VGA@
C1105
2 22U_0805_6.3V6M

R03 Modify BOM

30mil

3

3

1

+VGA_CORE
NOBACO@
1
2
R656
0_0805_5%

1
BACO@
Q26
AO3416L_SOT23-3

1

3
BACO@
Q27
AO3416L_SOT23-3

AO3416 NMOS
Vgs(th)(Max)= 1V
Rds(on)(Max)= 22m ohm @Vgs=4.5V

A

VGA@
Q89B
DMN66D0LDW-7_SOT363-6

5
4

1 VGA@ 2
R122
0_0402_5%
@
1
2
R123
0_0402_5%

MAN_GPIO1_DELAY

3

VDDC_EN

@
C214
0.1U_0402_16V4Z

+VGA_CORE
VAN_GPIO1_DELAY

1

For VGA Power on control

PX@
1

D

DMN66D0LDW-7_SOT363-6

30mil

AO3416L_SOT23-3
2

14

U44F
VGA@
O 12

S

A

1

2

74LVC14APW_TSSOP14

+BIF_VDDC

1.0_EN

G

IN
7

14
P
G

13

P

5
2

1
R121

VGA@
Q89A

U44E
VGA@
O 10

3

AO3416L_SOT23-3

G

PE_GPIO1#

7

2

IN

P

1
2

6

11

B

BACO@

BACO@ Q25

20mil

G

PX@
1 R119
2
30K_0402_1%

<25,27> PE_GPIO1

2
0_0805_5%

BACO@ Q24
D

VGA@
C211
2 0.1U_0402_16V4Z

+1.0VSG

DISO@
R116
0_0402_5%

5

@

R02 Modify

+3VALW

1

BACO@

Heathrow and Chelsea +1.0VSG connect to +BIF_VDDC

74LVC14APW_TSSOP14

S

@
R118
31.6K_0402_1%

2

2
0_0402_5%

1
R657

+3VALW

4

NC7SZ08P5X_NL_SC70-5

From +VGA_CORE regulator
@
1
R172

MAN_GPIO1_DELAY

+3VS

Y
A

2
G

1

U44D
VGA@
O 8

B

D

14
9

2
1 BACO@ 2
R655
0_0402_5%
1

D

2

U44C
VGA@
O 6

G

C210
@
0.1U_0402_16V4Z

IN

P

P
5

2
0_0402_5%

7

@
1
R115

G

14

1.5_VDDC_PWREN

Q23B
DMN66D0LDW-7_SOT363-6

+3VALW

<27,49> VGA_PWRGD

VDDC_EN
1.0_EN

BACO@
U20

Q23A
DMN66D0LDW-7_SOT363-6

+3VALW
B

Delay EC_PWROK 50ms

BACO@
R654
1K_0402_5%

+3VS

1

VAN_GPIO1_DELAY
BACO@ C1104
0.1U_0402_16V4Z
2
1

<37> INT_VGAPWR_ON

2

2

1 VGA@ 2
R170
0_0402_5%

74LVC14APW_TSSOP14

S

7
1

74LVC14APW_TSSOP14

+5VS

2

14
P
3

G

IN

+5VS

S

1
2

VGA@
C208
0.1U_0402_16V4Z

7

1 VGA@ 2
R111
0_0402_5%

G

14
P

Delay SUSP# 10ms
<37> VGA_ON

U44B
VGA@
O 4

3

BACO@
R652
5.11K_0402_1%

VGA Power ON Circuit
U44A
VGA@
O 2

BACO@
Q22
2N7002K_SOT23-3

S

1

+3VALW

1

<17> PX_EN

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
For VGA Sequence Issue 0923

2011/07/08

2015/07/08

Deciphered Date

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

5

4

3

2

Sheet

Wednesday, February 29, 2012
1

20

of

52

5

4

3

2

1

Swap for Meet 40 pin LVDS define (FW Support)
+3VS

+3VS_PS
+3VS_PS
1

U46 TL@

+1.2VS
D

Close to Pin3

60mil

DP_V33
C1483
TL@
0.1U_0402_16V4Z

C1482
TL@
0.1U_0402_16V4Z

C20
TL@
10U_0603_6.3V6M

1

1

2

2

2
R1178
TL@
0_0603_5%

1

SWR_V12

1

R04 Modify BOM

60mil13
18

60mil12
11
27
7

60mil

Close to P18

SWR_VDD
PVCC

TXE2+
TXE2-

21
22

APU_TXOUT1APU_TXOUT1+

APU_TXOUT1- <22>
APU_TXOUT1+ <22>

TXE1+
TXE1-

23
24

APU_TXOUT2APU_TXOUT2+

APU_TXOUT2- <22>
APU_TXOUT2+ <22>

TXE0+
TXE0-

25
26

APU_TXOUT_CLKAPU_TXOUT_CLK+

APU_TXOUT_CLK- <22>
APU_TXOUT_CLK+ <22>

GPIO(PWM OUT)
GPIO(Panel_VCC)
GPIO(PWM IN)
GPIO(BL_EN)

14
15
16
17

1 TL@
R1161
1 TL@
R1162

MIICSCL1
MIICDA1

29
28

APU_LVDS_CLK
APU_LVDS_DAT

MIICSCL0
MIICSDA0

31
30

MIIC_SCL
MIIC_SDA

GND

33

SWR_LX
SWR_VCCK
VCCK
DP_V12

2
1

AUX_P
AUX_N

DP0_TXP0_C
DP0_TXN0_C

5
6

LANE0P
LANE0N

CSCL
CSDA

9
10

CIICSCL1
CIICSDA1

2

1

<10,22> LVDS_HPD
1

2

R1169
1K_0402_5%
TL@
TL@
R1168
100K_0402_5%

TL_HPD

32

HPD

8
4

2

2

1

1

TL@
R30
12K_0402_1%

Close to
Pin27

LVDS
EDID
ROM

DP_REXT
DP_GND

1

2

C1492
TL@
0.1U_0402_16V4Z

2

C1491
TL@
0.1U_0402_16V4Z

C1490
TL@
0.1U_0402_16V4Z

C1489
TL@
22U_0805_6.3V6M

2

1

APU_LVDS_CLK <22>
APU_LVDS_DAT <22>

+3VS_PS

R1163
APU_LVDS_CLK
R1164

R04 Modify BOM

MIIC_SCL

Pop when no use
EEEPRON

R1165
MIIC_SDA
R1166
CSCL

@
R1177
10K_0402_5%

R1167
CSDA
R1170

1 TL@

C

2
4.7K_0402_5%
2
4.7K_0402_5%
2
4.7K_0402_5%
2
4.7K_0402_5%
2
4.7K_0402_5%
2
4.7K_0402_5%

1 TL@
1 TL@
1 TL@
1 TL@
1 TL@

1

SWR_V12

1

D

TL_INVT_PWM <22>
TL_ENVDD <22>
APU_INVT_PWM <10,22>
TL_BKOFF# <22>

APU_LVDS_DAT

Change to 12Kohm 1% (DG ref.)
20101114

Close to
Pin7

2
0_0402_5%
2
0_0402_5%

RTD2132S-VE-CG_QFN32_5X5
Part Number = SA00004EU10

1

2

Close to
L3

APU_TXOUT0- <22>
APU_TXOUT0+ <22>

Other

C1488
TL@
0.1U_0402_16V4Z

2

C1487
TL@
0.1U_0402_16V4Z

2

1

APU_TXOUT0APU_TXOUT0+

DP-IN

Close to Pin13

C1486
TL@
22U_0805_6.3V6M

C1485
TL@
0.1U_0402_16V4Z

C21
TL@
10U_0603_6.3V6M

2

1

19
20

DP0_AUXP_C
DP0_AUXN_C

SWR_VDD

1

TXEC+
TXEC-

RTD2132S
<8> DP0_TXP0_C
<8> DP0_TXN0_C

C

DP_V33

2
<8> DP0_AUXP_C
<8> DP0_AUXN_C

Close to L2

40mil 3

Power

TL@
L76 2
1 DP_V33
FBMA-L11-201209-221LMA30T_0805
TL@
L78 2
1 SWR_VDD
FBMA-L11-201209-221LMA30T_0805
L77 1
2 SWR_LX
4.7UH_PG031B-4R7MS_1.1A_20%
@

0_0603_5%

2

TL@

30mil

LVDS

R1160

2

GPIO

30mil

APU Co-lay eDP function

1

2
<8> DP0_TXP1_C
<8> DP0_TXN1_C

B

DP0_TXP0_C
DP0_TXN0_C
DP0_TXP1_C
DP0_TXN1_C
DP0_AUXP_C
DP0_AUXN_C

R1171
R1172
R1173
R1174
R1175
R1176

1
1
1
1
1
1

2
2
2
2
2
2

APUEDP@
APUEDP@
APUEDP@
APUEDP@
APUEDP@
APUEDP@

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

APU_TXOUT2+
APU_TXOUT2APU_TXOUT1+
APU_TXOUT1APU_LVDS_CLK
APU_LVDS_DAT

B

M
O
R
E
E
+3VS

+3VS_PS

U2 TL@
A0
A1
A2
GND

10K_0402_5%
R1182

1
2
3
4

10K_0402_5%
R1181
2

VCC
WP
SCL
SDA

<37> TL_DATA

TL@
Q90A

@
1
2 CSDA 1
6
R1179
0_0402_5% DMN66D0LDW-7_SOT363-6

5

CAT24C64WI-GT3_SO8

2

MIIC_SCL
MIIC_SDA

2

8
7
6
5

1

1

SWR_VDD

<37> TL_CLK
A

CSCL

4

2011/07/08

Deciphered Date

3

EC_SMB_CK2

3

A

Title

Date:

4

EC_SMB_CK2 <8,14,37>

Compal Electronics, Inc.
2015/07/08

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

EC_SMB_DA2 <8,14,37>

DMN66D0LDW-7_SOT363-6

Compal Secret Data

Security Classification
Issued Date

@
1
2
R1180
0_0402_5%

EC_SMB_DA2
TL@
Q90B

2

SCHEMATIC,MB A8331
Document Number

Rev
B

4019H2
Wednesday, February 29, 2012

Sheet
1

21

of

52

5

4

3

Panel LCDVDD Control

1

60mils

LVDS

6 2

1

1

R708
10K_0402_5%
3
2

2
R709

4

R711 1 DISO@ 2 0_0402_5%

1

UMA@
R713
100K_0402_5%

1
C1152
.047U_0402_16V7K

+3VS

BKOFF#

A

Y

2
10K_0402_5%
2
10K_0402_5%

C1154
0.1U_0402_16V4Z

2

R972

R730
10K_0402_5%

1 DISO@ 2
R714
0_0402_5%

VGA_TXOUT1+
VGA_TXOUT1-

eDP_TX1P
eDP_TX1N

TXOUT1+
TXOUT1-

APU_TXOUT2+
APU_TXOUT2-

DP0_TXP0_R
DP0_TXN0_R

VGA_TXOUT2+
VGA_TXOUT2-

eDP_TX0P
eDP_TX0N

TXOUT2+
TXOUT2-

VGA_TXCLK+
VGA_TXCLK-

TXCLK+
TXCLK-

APU_TZOUT0+
APU_TZOUT0-

VGA_TZOUT0+
VGA_TZOUT0-

TZOUT0+
TZOUT0-

APU_TZOUT1+
APU_TZOUT1-

VGA_TZOUT1+
VGA_TZOUT1-

TZOUT1+
TZOUT1-

APU_TZOUT2+
APU_TZOUT2-

VGA_TZOUT2+
VGA_TZOUT2-

TZOUT2+
TZOUT2-

APU_TZOUT_CLK+
APU_TZOUT_CLK-

VGA_TZCLK+
VGA_TZCLK-

TZCLK+
TZCLK-

APU_INVT_PWM

<10,21> APU_INVT_PWM

TL_INVT_PWM

<21> TL_INVT_PWM

1

<27> USB20_P5

1

<27> USB20_N5

L90 @
4 4

3

1

2

USB20_P5_R

2

2

OCE2012120YZF_4P
USB20_N5_R
3
+INVPWR_B+

0_0402_5%

B+

2

2

DISPOFF#
R719
100K_0402_5%

1
C1163
1
C1164

INVT_PWM

2
2

220P_0402_50V7K

+3VS

1

6

I/O4

I/O2

3

5

VDD

GND

2

4

I/O3

I/O1

1

USB20_P5_R

1

2

4

5

USB20_N5_R

EDP@
Q31A
DMN66D0LDW-7_SOT363-6

LCD/LED PANEL Conn.

AZC099-04S.R7G_SOT23-6

JLVDS1
CONN@

2
0_0402_5%

+LCDVDD

R728
100K_0402_5%
EDP@

+3VS

B

<21> APU_TXOUT1<21> APU_TXOUT1+

eDP_TX0N
eDP_TX0P

<21> APU_TXOUT2<21> APU_TXOUT2+
<21> APU_TXOUT_CLK<21> APU_TXOUT_CLK+

TXOUT0TXOUT0+

UMA@
UMA@

R1242 1
R1243 1

2 0_0402_5%
2 0_0402_5%

TXOUT1TXOUT1+

+3VS

TXOUT1TXOUT1+

UMA@
UMA@

R1244 1
R1245 1

2 0_0402_5%
2 0_0402_5%

TXOUT2TXOUT2+

TXOUT2TXOUT2+

UMA@
UMA@

R1246 1
R1247 1

2 0_0402_5%
2 0_0402_5%

TXCLKTXCLK+
I2CC_SDA
I2CC_SCL
I2CC_SDA

<13> VGA_TXOUT0<13> VGA_TXOUT0+

VGALVDS@ R732 1
VGALVDS@ R735 1

2 0_0402_5%
2 0_0402_5%

TXOUT0TXOUT0+

eDP_TX1N
eDP_TX1P

<13> VGA_TXOUT1<13> VGA_TXOUT1+

VGALVDS@ R731 1
VGALVDS@ R733 1

2 0_0402_5%
2 0_0402_5%

TXOUT1TXOUT1+

eDP_TX0N
eDP_TX0P

<13> VGA_TXOUT2<13> VGA_TXOUT2+

VGALVDS@ R734 1
VGALVDS@ R736 1

2 0_0402_5%
2 0_0402_5%

TXOUT2TXOUT2+

<13> VGA_TXCLK<13> VGA_TXCLK+

VGALVDS@ R737 1
VGALVDS@ R738 1

2 0_0402_5%
2 0_0402_5%

TXCLKTXCLK+

<14> VGA_LCD_CLK
<14> VGA_LCD_DAT

VGALVDS@ R741 1
VGALVDS@ R742 1

2 0_0402_5%
2 0_0402_5%

I2CC_SCL
I2CC_SDA

2
100K_0402_5%

VGA Co-lay eDP function

EDP@ R1250
EDP@ R1251

1
1

2 0_0402_5%
2 0_0402_5%

EDP_TX0N
EDP_TX0P

TXOUT1TXOUT1+

EDP@ R1252
EDP@ R1253

1
1

2 0_0402_5%
2 0_0402_5%

EDP_TX1N
EDP_TX1P

I2CC_SDA
I2CC_SCL

EDP@ R1254
EDP@ R1255

1
1

2 0_0402_5%
2 0_0402_5%

EDP_AUXN
EDP_AUXP

VGAEDP@ R732 .1U_0402_16V7K

EDP_HPD

VGAEDP@ R735 .1U_0402_16V7K
1

+3VS

1

VGAEDP@ R737 .1U_0402_16V7K
2

USB20_N5_R
USB20_P5_R

VGAEDP@ R738 .1U_0402_16V7K
1

2

VGAEDP@ R741 .1U_0402_16V7K
VGAEDP@ R742 .1U_0402_16V7K

41
42
43
44
45
46
B

A

1

2

2011/07/08

Issued Date

2015/07/08

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

4

G1
G2
G3
G4
G5
G6

Compal Electronics, Inc.

Compal Secret Data

Security Classification

5

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

I-PEX_20143-040E-20F
Part Number = SP010016810
PCB Footprint = I-PEX_20143-040E-20F_40P

1

2

eDP_AUXP
eDP_AUXN

I2CC_SCL 1
APUEDP@ R33

2

A

TXCLKTXCLK+
TXOUT2TXOUT2+

1

2 0_0402_5%
2 0_0402_5%

UMA@
UMA@

APUEDP@
R34
100K_0402_5%

2

VGA
LVDS Output

2 0_0402_5%
2 0_0402_5%

R1248 1
R1249 1

eDP_AUXP <21> APU_LVDS_CLK
eDP_AUXN <21> APU_LVDS_DAT

TXOUT0TXOUT0+

DG ref. Need close to eDP Conn.
201011251400

R1240 1
R1241 1

2

eDP_TX1N
eDP_TX1P

INVT_PWM
DISPOFF#
I2CC_SCL
I2CC_SDA

UMA@
UMA@

1

<21> APU_TXOUT0<21> APU_TXOUT0+

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

+INVPWR_B+

EDP_HPD

2
1
R727
200K_0402_5%
EDP@

1

6

2

EDP@
R724
10K_0402_5%

2

1
3
EDP@
Q31B

@
1
R729

Translator
LVDS Output

C

220P_0402_50V7K

+3VS

2

VGAEDP@
2
1
R725
0_0402_5%
APUEDP@
2
1
R726
0_0402_5%

Place near LVDS Conn

1

C1156
68P_0402_50V8J

@
D6

EDP@
R723
10K_0402_5%

DMN66D0LDW-7_SOT363-6

C1155
680P_0402_50V7K
2
1

40mils

1
2
FBMA-L11-201209-221LMA30T_0805

INVT_PWM

1 DISO@ 2
R716
0_0402_5%
@
1
2
R717
0_0402_5%
1APUEDP@ 2
R720
0_0402_5%
1 TL@
2
R721
0_0402_5%

+3VS

<10,21> LVDS_HPD

I2CC_SCL
I2CC_SDA

eDP_AUXP
eDP_AUXN

0_0402_5%

2

1

R975

Mosify for Fn+F5 function issue
20110315

eDP HDP for APU and VGA

<14> VGA_EDP_HPD

VGA_LCD_CLK
VGA_LCD_DATA

1

VGA_INVT_PWM

<13> VGA_INVT_PWM

DP0_AUXP_R
DP0_AUXN_R

L36

EC_INVT_PWM

<37> EC_INVT_PWM

D

APU_TXOUT_CLK+
APU_TXOUT_CLK-

Panel PWM Control
C

TXOUT0+
TXOUT0-

DP0_TXP1_R
DP0_TXN1_R

APU_LVDS_CLK
APU_LVDS_DAT

DISPOFF#

4

2

1 TL@
R715
1 @
R722

B

1

2

1

EDP@
R714
0_0402_5%

TL@
U22
NC7SZ08P5X_NL_SC70-5

3

<37> BKOFF#

2

1

1

2 0_0402_5%

G

TL_BKOFF# R718 1 TL@

2

VGA_TXOUT0+
VGA_TXOUT0-

APU_TXOUT1+
APU_TXOUT1-

P

5

Panel Backlight Control

+LCDVDD

60mils
C1149

<13> VGA_ENVDD

5

Q29
AP2301GN-HF_SOT23-3

2

4.7U_0603_6.3V6K

R710 1APUEDP@ 2 0_0402_5%

e
d
i
s
A
G
V
t
a
D
P
D
D
V
N
E
_
A
G
V

<10> APU_ENVDD

1
1K_0402_5%

1

3

2 0_0402_5%

2

R712 1 TL@

Q28B
DMN66D0LDW-7_SOT363-6

1

D

UMA/DIS LVDS/eDP Mapping table
Panel
UMA
DIS
LVDS
eDP
Conn.
eDP

APU_TXOUT0+
APU_TXOUT0-

C1153
4.7U_0603_6.3V6K

2

2

Q28A
DMN66D0LDW-7_SOT363-6

<21> TL_BKOFF#

1

+3VS
+3VALW
R707
300_0603_5%

<21> TL_ENVDD

2

+LCDVDD

3

2

SCHEMATIC,MB A8331
Document Number

Rev
B

4019H2
Sheet

Wednesday, February 29, 2012
1

22

of

52

5

4

3

+3VS

2

+3VS

1

+HDMI_5V_OUT

+HDMI_5V_OUT

JHDMI1

1
2

2

1
2

HDMI_SDATA

2

1
2N7002K_SOT23-3

1
2

HDMI_C_CLK-

2

HDMI_C_CLK+

1
HDMI_C_TX2-_R
HDMI_C_TX2+_R
HDMI_C_TX1-_R
HDMI_C_TX1+_R
HDMI_C_TX0-_R
HDMI_C_TX0+_R
HDMI_C_CLK-_R
HDMI_C_CLK+_R

UMA@ R770
UMA@ R772
UMA@ R773
UMA@ R774
UMA@ R776
UMA@ R777
UMA@ R778
UMA@ R780

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

HDMI_C_TX2-_R
HDMI_C_TX2+_R
HDMI_C_TX1-_R
HDMI_C_TX1+_R
HDMI_C_TX0-_R
HDMI_C_TX0+_R
HDMI_C_CLK-_R
HDMI_C_CLK+_R

HDMI_C_TX0-

R769 1

2

1

HDMI_C_TX0+

For UMA HDMI
termination BOM option

HDMI_C_TX1-

HDMI_C_TX2-DISO@
DISO@R784
R784 1
1 .1U_0402_16V7K
DISO@R786
R786 1
HDMI_C_TX2+DISO@
1 .1U_0402_16V7K

2 499_0402_1%
2 499_0402_1%

HDMI_C_TX1-_R C1168 2
HDMI_C_TX1+_R C1169 2

HDMI_C_TX1-DISO@
DISO@R788
R788 1
1 .1U_0402_16V7K
HDMI_C_TX1+DISO@
DISO@R790
R790 1
1 .1U_0402_16V7K

2 499_0402_1%
2 499_0402_1%

HDMI_C_TX0-_R C1170 2
HDMI_C_TX0+_R C1171 2

DISO@R792
R792 1
HDMI_C_TX0-DISO@
1 .1U_0402_16V7K
HDMI_C_TX0+DISO@
DISO@R795
R795 1
1 .1U_0402_16V7K

2 499_0402_1%
2 499_0402_1%

HDMI_C_CLK-_R C1172 2
HDMI_C_CLK+_R C1173 2

HDMI_C_CLK-DISO@
DISO@R797
R797 1
1 .1U_0402_16V7K
HDMI_C_CLK+DISO@
DISO@R799
R799 1
1 .1U_0402_16V7K

2 499_0402_1%
2 499_0402_1%

2

R781 1

2

1
@ L40
WCM2012F2S-900T04_0805
4 4

R792 2 UMA@1 604_0402_1%
R795 2 UMA@1 604_0402_1%

HDMI_C_TX1+

R797 2 UMA@1 604_0402_1%
R799 2 UMA@1 604_0402_1%

HDMI_C_TX2-

1

2

R783 1

2

R782

1

Q35
2N7002K_SOT23-3
2
G

+HDMI_5V_OUT

3
HDMI_R_CK+
0_0402_5%
0_0402_5%

2

2

3

3

HDMI_R_D0-

HDMI_R_D0+
0_0402_5%
0_0402_5%

HDMI_R_D1B

1

R788 2 UMA@1 604_0402_1%
R790 2 UMA@1 604_0402_1%

HDMI_C_TX2-_R C1166 2
HDMI_C_TX2+_R C1167 2

1

R779

R784 2 UMA@1 604_0402_1%
R786 2 UMA@1 604_0402_1%

Near the connector

1

@ L39
WCM2012F2S-900T04_0805
4 4

UMA use 604 ohm SCL v1.01
VGA use 499 ohm

1
@ L41
WCM2012F2S-900T04_0805
4 4

1

APU_HDMI_TXD2APU_HDMI_TXD2+
APU_HDMI_TXD1APU_HDMI_TXD1+
APU_HDMI_TXD0APU_HDMI_TXD0+
APU_HDMI_TXCAPU_HDMI_TXC+

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

3

HDMI_R_CK-

D

HDMI_C_TX2+
R794

1

2

2

2

3

3
HDMI_R_D1+
0_0402_5%
0_0402_5%

2

2

3

3

HDMI_R_D2-

HDMI_R_D2+
0_0402_5%

S
R801

3

From APU

<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>

2
2
2
2
2
2
2
2

1

B

1
1
1
1
1
1
1
1

2

2

2

100K_0402_5%
2

From VGA

DISO@R757
DISO@R757
DISO@R758
DISO@
R758
DISO@R759
DISO@
R759
DISO@R760
DISO@
R760
DISO@R761
DISO@
R761
DISO@R763
DISO@
R763
DISO@R764
DISO@
R764
DISO@R766
DISO@
R766

1

R765

0_0402_5%

2

1
@ L38
WCM2012F2S-900T04_0805
4 4

HDMI_HPD

2

R756 1
1

R75
100K_0402_5%

VGA_HDMI_TXD2VGA_HDMI_TXD2+
VGA_HDMI_TXD1VGA_HDMI_TXD1+
VGA_HDMI_TXD0VGA_HDMI_TXD0+
VGA_HDMI_TXCVGA_HDMI_TXC+

D

C

6
5
Q96A
DMN66D0LDW-7_SOT363-6

4

Q96B
DMN66D0LDW-7_SOT363-6

20
21
22
23

SUYIN_100042GR019M23BZR
CONN@
Part Number = DC232001100
PCB Footprint = ACON_HMR2E-AK120D_19P

1

3

2

1

DISO@
R72
4.7K_0402_5%

For APU_HDMI_HPD

<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>

HDMI_R_D2+

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

R74

2 DISO@ 1
R767
0_0402_5%
2 UMA@ 1
R771
0_0402_5%

<8> DP2_HPD

HDMI_R_D1+
HDMI_R_D2-

+5VS
4.7K_0402_5%

2

+3VSG

UMA@
R73
1K_0402_5%
<14> VGA_HDMI_DET

HDMI_R_D0+
HDMI_R_D1-

0_0402_5%
+3VS

C

1

2

1

3

0_0402_5%

1

R754

1 UMA@ 2

R750

<8> APU_HDMI_DATA

1 DISO@ 2

HDMI_R_CK+
HDMI_R_D0-

Q33
D

R753

0_0402_5%
S

<14> VGA_HDMI_SDATA

1 UMA@ 2

HDMI_R_CK-

HDMI_SCLK

1
2N7002K_SOT23-3

D

R752

R749

G

<8> APU_HDMI_CLK

0_0402_5%

S

R751

HDMI_SDATA
HDMI_SCLK

Q32

3
G

<14> VGA_HDMI_SCLK

1 DISO@ 2

2K_0402_1%

UMA@
R748
0_0402_5%
R746

R745

2
D

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+HDMI_5V_OUT

2K_0402_1%

C1165
0.1U_0402_16V4Z

UMA@

2

1

1.1A_6V_SMD1812P110TF

UMA@

2

2

4.7K_0402_5%

1

W=40mils

4.7K_0402_5%

+5VS

F1

1

HDMI_HPD

W=40mils

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Deciphered Date

2015/07/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

SCHEMATIC,MB A8331
Document Number

Rev
B

4019H2
Wednesday, February 29, 2012

Sheet
1

23

of

52

A

B

C

D

E

W=40mils
+R_CRT_VCC
D22

2

3

2

3

+5VS

1

L43 1
2
FCM2012CF-800T06_2P

CRT_G_2

CRT_B

L44 1
2
FCM2012CF-800T06_2P

CRT_B_2

1
2

2

2

2

1

JCRT1
CONN@
DC060005800

2
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

2
1

2

C1181

R808 2

5
P
A

1 10K_0402_5%

CRT_HSYNC_1

C1183
10P_0402_50V8J

1

CRT_VSYNC_2
1

2

2

1

C1184
10P_0402_50V8J

C1185 2
68P_0402_50V8J

DSUB_15
1

3

CRT_VSYNC_1

CRT_G

FCH_CRT_B

R811 2 UMA@ 1 0_0402_5%

CRT_B

FCH_CRT_HSYNC

R814 2 UMA@ 1 0_0402_5% CRT_HSYNC

FCH_CRT_VSYNC

R815 2 UMA@ 1 0_0402_5% CRT_VSYNC

<26> FCH_CRT_DDC_SDA

FCH_CRT_DDC_SDA R816 2 UMA@ 1 0_0402_5%

DSUB_12

<26> FCH_CRT_DDC_SCL

FCH_CRT_DDC_SCL

DSUB_15

<14> VGA_CRT_R
<14> VGA_CRT_G
<14> VGA_CRT_B
<14> VGA_CRT_HSYNC
<14> VGA_CRT_VSYNC

4

<14> VGA_CRT_DATA
<14> VGA_CRT_CLK

R817 2 UMA@ 1 0_0402_5%

VGA_CRT_R

R818 2 DISO@ 1 0_0402_5%

CRT_R

VGA_CRT_G

R819 2 DISO@ 1 0_0402_5%

CRT_G

VGA_CRT_B

R820 2 DISO@ 1 0_0402_5%

CRT_B

VGA_CRT_HSYNC

R821 2 DISO@ 1 0_0402_5% CRT_HSYNC

VGA_CRT_VSYNC

R822 2 DISO@ 1 0_0402_5% CRT_VSYNC

Close to Conn side

3

+3VSG

+CRT_VCC

VGA_CRT_DATA

1

CRT_R

R810 2 UMA@ 1 0_0402_5%

R812
4.7K_0402_5%

R813
4.7K_0402_5%

1

2

R809 2 UMA@ 1 0_0402_5%

FCH_CRT_G

1

FCH_CRT_R

2

<26> FCH_CRT_VSYNC

4

U24
74AHCT1G125GW_SOT353-5

6

DISO@ Q5A
DMN66D0LDW-7_SOT363-6
VGA_CRT_CLK

DSUB_12

5

<26> FCH_CRT_HSYNC

Y

2

OE#

5
<26> FCH_CRT_B

From VGA

C1186
68P_0402_50V8J

1

P
A
G

2

3
<26> FCH_CRT_R
<26> FCH_CRT_G

From FCH

4
DISO@

DSUB_15

3
Q5B DMN66D0LDW-7_SOT363-6

4

VGA_CRT_DATA
VGA_CRT_CLK

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

2011/07/08

Deciphered Date

2015/07/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

2

2 0.1U_0402_16V4Z

CRT_VSYNC

Use common via

16
17

DSUB_12

2

3

G
G

T20

+CRT_VCC
C1187 1

SUYIN_070546HR015M25FZR
PCB Footprint = SUYIN_070546HR015M25FZR_15P

CRT_HSYNC_2

L46 1
2
FCM2012CF-800T06_2P

U23
74AHCT1G125GW_SOT353-5
Y 4

G

2

OE#

CRT_HSYNC

1

1
2
C1182 0.1U_0402_16V4Z

L45 1
2
FCM2012CF-800T06_2P

1

100P_0402_50V8J

+CRT_VCC
2

T19

C1180

10P_0402_50V8J

1

C1179

2

10P_0402_50V8J

2

1

C1178

10P_0402_50V8J

C1177

C1176

2

10P_0402_50V8J

C1175

2

10P_0402_50V8J

10P_0402_50V8J

R807

150_0402_1%

R806

150_0402_1%

R805

150_0402_1%

1

CRT_G

1

CRT_R_2

1

2

1.1A_6V_SMD1812P110TF
1

r
o
t
c
e
n
n
o
C
T
R
C

L42 1
2
FCM2012CF-800T06_2P

1

1

RB491D_SC59-3

C1174
0.1U_0402_16V4Z

CRT_R

1

1

W=40mils

2

3
1

@
D21
AZC199-02SPR7G_SOT23-3

1

1

1

2

3

2
@
D20
AZC199-02SPR7G_SOT23-3

+CRT_VCC

F2

B

C

D

SCHEMATIC,MB A8331
Document Number

Rev
B

4019H2
Wednesday, February 29, 2012

Sheet
E

24

of

52

A

B

C

D

E

U25A
2 150P_0402_50V8J

2 2K_0402_1% CLK_CALRN

R833 1

+1.1VS_CKVDD

F27

PCIE_RCLKP
PCIE_RCLKN

R26
T26

DISP_CLKP
DISP_CLKN

H33
H31

DISP2_CLKP
DISP2_CLKN

APU_CLKP
APU_CLKN

T24
T23

APU_CLKP
APU_CLKN

CLK_PEG_VGA
CLK_PEG_VGA#

J30
K29

SLT_GFX_CLKP
SLT_GFX_CLKN

H27
H28

GPP_CLK0P
GPP_CLK0N

J27
K26

GPP_CLK1P
GPP_CLK1N

APU_DISP_CLKP
APU_DISP_CLKN

<8> APU_DISP_CLKP
<8> APU_DISP_CLKN

APU DISP

NSS
<8> APU_CLKP
<8> APU_CLKN

APU

<13> CLK_PEG_VGA
<13> CLK_PEG_VGA#

VGA

Wireless LAN

<34> CLK_PCIE_MINI1
<34> CLK_PCIE_MINI1#

Ethernet LAN

<32> CLK_PCIE_LAN
<32> CLK_PCIE_LAN#

MINI2(option)

<34> CLK_PCIE_MINI2
<34> CLK_PCIE_MINI2#

Card Reader

<31> CLK_PCIE_CR
<31> CLK_PCIE_CR#

SS
3

<35> CLK_PCIE_USB30
CLK_PCIE_USB30#

USB3.0(FL1009)<35>

F33
F31

GPP_CLK2P
GPP_CLK2N

CLK_PCIE_LAN
CLK_PCIE_LAN#

E33
E31

GPP_CLK3P
GPP_CLK3N

CLK_PCIE_MINI2
CLK_PCIE_MINI2#

M23
M24

GPP_CLK4P
GPP_CLK4N

CLK_PCIE_CR
CLK_PCIE_CR#

M27
M26

GPP_CLK5P
GPP_CLK5N

CLK_PCIE_USB30
CLK_PCIE_USB30#

N25
N26

GPP_CLK6P
GPP_CLK6N

R23
R24

GPP_CLK7P
GPP_CLK7N

1
R856

1

1
2
C1200
27P_0402_50V8J

CLK_PCIE_MINI1
CLK_PCIE_MINI1#

GPP_CLK8P
GPP_CLK8N

J26

14M_25M_48M_OSC

25M_X1
2
0_0402_5%

C31

25M_X1

25M_X2

C33

25M_X2

R858
1M_0402_5%

1
2
C1201
27P_0402_50V8J

T26

1
R835
1
R879

USB30_CLKREQ#

2
8.2K_0402_5%
2
10K_0402_5%

CRCLK_REQ#
R854 1
R873 1

1

4

OSC

NC

3

1

OSC

NC

2

P

Removed R02

CRCLK_REQ# <31>
@
@

2 0_0402_5%
2 0_0402_5%

PE_GPIO0 <13,27>
PE_GPIO1 <20,27>

T24

+RTCBATT

LPC_CLK0_EC

1
R58

2
1
10_0402_5% C44

@

2
@ 10P_0402_50V8J

For EMI Requirement Close to U25

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48

B25

LPC_CLK0_EC

D25
D27
C28
A26
A29
A31
B27
AE27
AE19

LPC_CLK1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

G25
E28
E26
G26
F26

ALLOW_STOP
EC_THERM_R#
APU_PWRGD

JBATT1
CONN@
CCM_060003HA002G202ZL
Part Number = SP07000OU10
PCB Footprint = CCM_060003HA002G202ZL_2P

LPC_CLK0_EC <28,37>
LPC_CLK1 <28>
LPC_AD0 <37>
LPC_AD1 <37>
LPC_AD2 <37>
LPC_AD3 <37>
LPC_FRAME# <37>

USB30_CLKREQ#
SERIRQ

3

USB30_CLKREQ# <35>
SERIRQ <37>
APU_PWRGD
C41

DMA_ACTIVE#
PROCHOT#
APU_PG
LDT_STP#
APU_RST#

@
1
R853

2
0_0402_5%

APU_RST#

S5_CORE_EN
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G

H7
F1
F3
E6

32K_X1

G2

32K_X1

32K_X2

G4

32K_X2

RTC_CLK_R

C42
33P_0402_50V8J
for ESD Close FCH Side

APU_RST# <8>

1
R855

2
22_0402_5%

33P_0402_50V8J

APU_RST#

ALLOW_STOP <8>
EC_THERM# <8,37,44,50>
APU_PWRGD <8,50>

APU_PG/APU_RST#/LDT_STP# : OD pin
DMA_ACTIVE# : IN/OD, 0.8V threshold
+RTCBATT
PROCHOT# : IN, 0.8V threshold
LDT_STP : No use, NC
DMA active. The FCH drives the DMA_ACTIVE# to
APU to notify DMA activity. This will cause the APU
R857
to reestablish the UMI link quicker.
1K_0402_5%

RTC_CLK <28,37>

RTCVCC_R

D23

+RTCVCC

2
1
R859
C1202
0.1U_0402_16V4Z

1

1

2
510_0402_5%

W=20mils
C1203
1U_0402_6.3V6K

2

R860

for Clear CMOS

1

C1204

1

@
0_0603_5%

2

1

M3@

3

+CHGRTC

BAV70W_SOT323-3
If a diode is implemented between the FCH and battery,
the VDDBT_RTC_G input voltage is within 200 mV of
the battery voltage.

32K_X2

2011/07/08

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2015/07/08

Deciphered Date

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Close to HUDSON-M2

Rev
B

4019H2

Date:

A

4

U25
218-0755042 A13 HUDSON-M3 656P
Part Number = SA000043IB0

32.768KHZ_12.5PF_Q13MC14610002

2

C1206
22P_0402_50V8J

+3VS

X5

1

R861
20M_0402_5%
2

C1205,C1206
Change for G3
RTC timing issue

R03 Modify to 22pF
follow Vender suggest

APU_PCIE_RST# <13,31,32,34,35>

2

CRCLK_REQ#

2
C1205
22P_0402_50V8J

@

4

<28>
<28>
<28>
<28>
<28>

VGA_PWRGD_R Change to GPIO51

4

32K_X1

G

5
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27

25MHZ_20PF_7A25000012

2

Y

U26
NC7SZ08P5X_NL_SC70-5

2

HUDSON-M2_FCBGA656
M2@

1

A

R826
8.2K_0402_5%

3

AF18
AE18
AC16
AD18

2

X1

N27
R27

INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35

C1195
150P_0402_50V8J

B

1

.
n
n
o
C
T
T
A
B
C
T
R

G30
G28

For "EXT" CLK mode, input to PCIE,

SS

CLK_CALRN

1

2

1

2

2 33_0402_5%

+

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N

R829 1

-

AA27
AA26
W27
V27
V26
W26
W24
W23

APU_PCIE_RST#_C

1

2

PCIE_DTX_C_MRX_P0
PCIE_DTX_C_MRX_N0

C1193
1
2
0.1U_0402_16V4Z

1

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N

+3VALW

For PCIE device reset on FS1
(GFX,GLAN,WLAN,LVDS Travis)

7
7
2
6
L
S
I
o
t
t
f
i
h
s
l
e
v
e
L

V33
V31
W30
W32
AB26
AB27
AA24
AA23

3
0
1
1
0
1
0
B2
/
S
B
U/
SM
n
no
o
0
03
3
BB
SS
UU
r
ro
o
F
F
1
0t
t
r
r
o
oP
P
PP
PP
GG

PCIE_CALRP
PCIE_CALRN

AJ3
AL5
AG4
AL6
AH3
AJ5
AL1
AN5
AN6
AJ1
AL8
AL3
AM7
AJ6
AK7
AN8
AG9
AM11
AJ10
AL12
AK11
AN12
AG12
AE12
AC12
AE13
AF13
AH13
AH14
AD15
AC15
AE16
AN3
AJ8
AN10
AD12
AG10
AK9
AL10
AF10
AE10
AH1
AM9
AH8
AG15
AG13
AF15
AM17
AD16
AD13
AD21
AK17
AD19
AH9

2

<35> PCIE_DTX_C_MRX_P0
<35> PCIE_DTX_C_MRX_N0

AF29
AF31

PCIE_MTX_DRX_P0
PCIE_MTX_DRX_N0

AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT0#
GNT1#/GPO44
GNT2#/SD_LED/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLKRUN#
LOCK#

PCI_CLK3 <28>
PCI_CLK4 <28>

0.1U_0402_16V4Z

2 .1U_0402_16V7K
2 .1U_0402_16V7K

PCIRST#

AB5

PCI_CLK1 <28>

2

UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N

AF3
AF1
AF5
AG2
AF6

1

AB33
AB31
AB28
AB29
Y33
Y31
Y28
Y29

PCI CLKS

UMI_FTX_C_MRX_P0
UMI_FTX_C_MRX_N0
UMI_FTX_C_MRX_P1
UMI_FTX_C_MRX_N1
UMI_FTX_C_MRX_P2
UMI_FTX_C_MRX_N2
UMI_FTX_C_MRX_P3
UMI_FTX_C_MRX_N3
2 590_0402_1% PCIE_CALRP
2 2K_0402_1% PCIE_CALRN

FL@ C1207 1
FL@C1207
FL@C1208
FL@
C1208 1

<35> PCIE_MTX_C_DRX_P0
<35> PCIE_MTX_C_DRX_N0

UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N

PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39

2

R827 1
R828 1

+PCIE_VDDR_FCH

AE30
AE32
AD33
AD31
AD28
AD29
AC30
AC32

PCI INTERFACE

UMI_FTX_C_MRX_P0
UMI_FTX_C_MRX_N0
UMI_FTX_C_MRX_P1
UMI_FTX_C_MRX_N1
UMI_FTX_C_MRX_P2
UMI_FTX_C_MRX_N2
UMI_FTX_C_MRX_P3
UMI_FTX_C_MRX_N3

UMI_MTX_FRX_P0
UMI_MTX_FRX_N0
UMI_MTX_FRX_P1
UMI_MTX_FRX_N1
UMI_MTX_FRX_P2
UMI_MTX_FRX_N2
UMI_MTX_FRX_P3
UMI_MTX_FRX_N3

LPC

<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>

2
2
2
2
2
2
2
2

PCIE_RST#
A_RST#

APU

UMI_MTX_C_FRX_P0
UMI_MTX_C_FRX_N0
UMI_MTX_C_FRX_P1
UMI_MTX_C_FRX_N1
UMI_MTX_C_FRX_P2
UMI_MTX_C_FRX_N2
UMI_MTX_C_FRX_P3
UMI_MTX_C_FRX_N3

.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K

AE2
AD5

S5 PLUS

1

<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>

C1189 1
C1190 1
C1191 1
C1192 1
C1196 1
C1197 1
C1198 1
C1194 1

HUDSON-2

APU_PCIE_RST#_C
2 33_0402_5%

PCI EXPRESS INTERFACES

R825 1

<10,37> PLT_RST#

CLOCK GENERATOR

C1188 1

PCI Host Bus Reset (To EC)

B

C

D

Sheet

Wednesday, February 29, 2012
E

25

of

52

A

B

C

D

4MB SPI ROM
(Non-share)

U25B

SATA_STX_DRX_P1
SATA_STX_DRX_N1

AN22
AL22

SATA_TX1P
SATA_TX1N

SATA_DTX_C_SRX_N1
SATA_DTX_C_SRX_P1

AH20
AJ20

SATA_RX1N
SATA_RX1P

AJ22
AH22

SATA_TX2P
SATA_TX2N

AM23
AK23

SATA_RX2N
SATA_RX2P

AH24
AJ24

SATA_TX3P
SATA_TX3N

AN24
AL24

SATA_RX3N
SATA_RX3P

AL26
AN26

SATA_TX4P
SATA_TX4N

AJ26
AH26

SATA_RX4N
SATA_RX4P

AN29
AL28

SATA_TX5P
SATA_TX5N

AK27
AM27

SATA_RX5N
SATA_RX5P

AL29
AN31

NC6
NC7

AL31
AL33

NC8
NC9

2

+AVDD_SATA

AH33
AH31

NC10
NC11

AJ33
AJ31

NC12
NC13

1K_0402_1% 2

1 R899

SATA_CALRP

AF28

SATA_CALRP

931_0402_1%2

1 R900

SATA_CALRN

AF27

SATA_CALRN

SATA_LED#

AD22

SATA_ACT#/GPIO67

AF21

SATA_X1

<38> SATA_LED#
R902 1

+3VS

SD_CLK/SCLK_2/GPIO73
SD_CMD/SLOAD_2/GPIO74
SD_CD/GPIO75
SD_WP/GPIO76
SD_DATA0/SDATI_2/GPIO77
SD_DATA1/SDATO_2/GPIO78
SD_DATA2/GPIO79
SD_DATA3/GPIO80

SATA_X2

<34> WL_OFF#_2

BT_ON#

<36> BT_ON#

W_DISABLE#_2
WL_OFF#

<34> W_DISABLE#_2
<34> WL_OFF#

ODD_PWR

<30> ODD_PWR

R14
R15
R16

1

2

1

2

1

2

10K_0402_5%
10K_0402_5%
10K_0402_5%

AH16
AM15
AJ16
AK15
AN16
AL16
K6
K5

FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54

L30

FCH_CRT_R
R896 1

2 150_0402_1%

VGA_GREEN

L32

FCH_CRT_G
R897 1

2 150_0402_1%

VGA_BLUE

M29

FCH_CRT_B
R898 1

2 150_0402_1%

VGA_HSYNC/GPO68
VGA_VSYNC/GPO69

M28
N30

FCH_CRT_HSYNC
FCH_CRT_VSYNC

VGA_DDC_SDA/GPO70
VGA_DDC_SCL/GPO71

M33
N32

FCH_CRT_DDC_SDA
FCH_CRT_DDC_SCL

VGA_DAC_RSET

K31

VIN4/SLOAD_1/GPIO179

P1

VIN5/SCLK_1/GPIO180

P3

VIN6/GBE_STAT3/GPIO181

M1

K3

VIN7/GBE_LED3/GPIO182

M5

TEMPIN2/GPIO173

M6

TEMPIN3/TALERT#/GPIO174

NC1
NC2
NC3
NC4
NC5

1

1

@C23
@
C23
2
1
2
10_0402_5%
10P_0402_50V8J

R5
R6
R7
R8
R9
R10
R11

R35

R12

2 0_0402_5%

+3VALW

2
10K_0402_5%

FCH_SPI_CLK

FCH_CRT_R <24>
FCH_CRT_G <24>
FCH_CRT_B <24>
<24>
<24>

FCH_CRT_DDC_SDA <24>
FCH_CRT_DDC_SCL <24>

ML_VGA_AUXP_C <8>
ML_VGA_AUXN_C <8>
2
100_0402_1%

+VDDAN_11_ML
ML_VGA_TXP0
ML_VGA_TXN0
ML_VGA_TXP1
ML_VGA_TXN1
ML_VGA_TXP2
ML_VGA_TXN2
ML_VGA_TXP3
ML_VGA_TXN3

FCH_CRT_HPD
2
10K_0402_5%
FCH_CRT_HPD <10>
2

1

2

1

2

1

2

1

2

1

2

1

1

FCH_CRT_HSYNC
FCH_CRT_VSYNC

1

1

1
R892

Removed RGMII/MII support and updated termination
requirements for GBE_COL, GBE_CRS, GBE_RXERR
and GBE_MDIO when RGMII/MII interface is not used.
FCH DGv1.20 / SCL v1.20

C29 FCH_CRT_HPD

N4

1
R935
10K_0402_5%

2
715_0402_1%

T31
T33
T29
T28
R32
R30
P29
P28

TEMPIN0/GPIO171
TEMPIN1/GPIO172

1
R901

AUXCAL

VIN3/SDATO_1/GPIO178

2

2

ML_VGA_L0P
ML_VGA_L0N
ML_VGA_L1P
ML_VGA_L1N
ML_VGA_L2P
ML_VGA_L2N
ML_VGA_L3P
ML_VGA_L3N

VIN2/SDATI_1/GPIO177

FCH_SPI_VCC
FCH_SPI_HOLD#
FCH_SPI_CLK
FCH_SPI_MOSI

GBE_PHY_INTR

AUXCAL1
R903
ML_VGA_TXP0
ML_VGA_TXN0
ML_VGA_TXP1
ML_VGA_TXN1
ML_VGA_TXP2
ML_VGA_TXN2
ML_VGA_TXP3
ML_VGA_TXN3

L2

8
7
6
5

VCC
HOLD#
SCLK
SI/SIO0

GBE_PHY_INTR
Pulled-up to +3.3V_S5 with a 10-KΩ 5% resistor.
FCH SCL v1.20 #19-85

U28

M3

CS#
SO/SIO1
WP#
GND

GBE_COL / GBE_CRS / GBE_MDIO
GBE_RXERR / Left unconnected.
FCH SCL V1.20 19-35

V28
V29

N2

1
2
3
4

@R36
@
R36

AUX_VGA_CH_P
AUX_VGA_CH_N

VIN1/GPIO176

C466
1

U28
FCH_SPI_CS1#
FCH_SPI_MISO
FCH_SPI_WP#

FCH_SPI_CLK

ML_VGA_AUXP_C
ML_VGA_AUXN_C

VIN0/GPIO175

+3VALW
0.1U_0402_16V4Z
2

EON_32M_EN25Q32B-104HIP_SOP_8P

VGA_RED

HW MONITOR

FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58

1
2
R934
10K_0402_5%

FCH_SPI_MISO
FCH_SPI_MOSI
FCH_SPI_CLK_R
FCH_SPI_CS1#
FCH_SPI_WP#

ML_VGA_HPD/GPIO229
WL_OFF#_2

R626
10K_0402_5%
1
2

V6
V5
V3
T6
V1

SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/SPI_WP#/GPIO161

3

AL14
AN14
AJ12
AH12
AK13
AM13
AH15
AJ14

GBE_PHY_INTR

2 10K_0402_5%

AG21

+3VALW

AC4
AD3
AD9
W10
AB8
AH7
AF7
AE7
AD7
AG8
AD1
AB7
AF9
AG6
AE8
AD8
AB9
AC2
AA7
W9

GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR

GBE LAN

<30> SATA_DTX_C_SRX_N1
<30> SATA_DTX_C_SRX_P1

SATA_RX0N
SATA_RX0P

SPI ROM

1

<30> SATA_STX_DRX_P1
<30> SATA_STX_DRX_N1

SATA_TX0P
SATA_TX0N

AL20
AN20

VGA MAINLINK

ODD

AK19
AM19

SATA_DTX_C_SRX_N0
SATA_DTX_C_SRX_P0

VGA DAC

<30> SATA_DTX_C_SRX_N0
<30> SATA_DTX_C_SRX_P0

SATA_STX_DRX_P0
SATA_STX_DRX_N0

SERIAL ATA

<30> SATA_STX_DRX_P0
<30> SATA_STX_DRX_N0

SD CARD

HUDSON-2

HDD1

E

@

2
2

<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
1
R904

+FCH_VDDAN_33_DAC_R

3

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

GPIO181 Enabled integrated pull-down/up and left unconnected.
10K_0402_5%
10K_0402_5%

AG16
AH10
A28
G27
L4

HUDSON-M2_FCBGA656
M2@
4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Deciphered Date

2015/07/08

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

A

B

C

D

Wednesday, February 29, 2012

Sheet
E

26

of

52

A

B

1

<32,34,35> FCH_PCIE_WAKE#
<8> H_THERMTRIP#

EC_RSMRST#
MINI2_CLKREQ#
LAN_CLKREQ#

<34> MINI2_CLKREQ#
<32> LAN_CLKREQ#

FCH GEVENT (S5 domain)
with isolation circuit to avoid leakage

FCH_SPKR
FCH_SCLK0
FCH_SDATA0
FCH_SCLK1
FCH_SDATA1
MINI1_CLKREQ#

2

R03 modify for TP 6P/8P

G
1ODD_DA#_1

3
D

S

Q84
2N7002K_SOT23-3
ZERO@
+3VS

<35> SMIB

ODD_DA#_1

2

R78

<30> ODD_PLUG#

2

R955
10K_0402_5%

USB MISC

CLK_REQ4#/SATA_IS0#/GPIO64
CLK_REQ3#/SATA_IS1#/GPIO63
SMARTVOLT1/SATA_IS2#/GPIO50
CLK_REQ0#/SATA_IS3#/GPIO60
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#/VGA_PD
GBE_LED0/GPIO183
SPI_HOLD#/GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

1

T32

ZERO@

G
1CARD_DET_FCH

3

2 0_0402_5%

1

CARD_DET_FCH
USB_OC1#
USB_OC0#

D

S

<36> USB_OC1#
<36> USB_OC0#

M7
R8
T1
P6
F5
P5
J7
T8

BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC2#/TCK/GEVENT14#
USB_OC1#/TDI/GEVENT13#
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#

Q85
2N7002K_SOT23-3

33ohm termination
resistor at CODEC side
R868 1
R869 1

<39> HDA_SYNC_AUDIO
<39> HDA_RST_AUDIO#

2 33_0402_5%
2 33_0402_5%

+3VALW

FCH_GPIO187
FCH_GPIO188
FCH_GPIO166
H_THERMTRIP#

FCH_SDATA1

SYS_RESET#
SMIB
LAN_CLKREQ#

R03 modify

1

1

2

1

2

1

2

2
FCH_SCLK0

PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192

F21
E20
F20
A22
E18
A20
J18
H18
G18
B21
K18
D19
A18
C18
B19
B17
A24
D17

KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226

EMBEDDED CTRL

1
2

1
2

2

2 11.8K_0402_1%

Hudson-M2/M3
OHCI CTL
DEV 20, Fn 5


USB_HSD13P
USB_HSD13N

H10
G10

USB_HSD12P
USB_HSD12N

K10
J12

USB_HSD11P
USB_HSD11N

G12
F12

USB_HSD10P
USB_HSD10N

K12
K13

USB30_P10
USB30_N10

USB_HSD9P
USB_HSD9N

B11
D11

USB20_P9
USB20_N9

USB_HSD8P
USB_HSD8N

E10
F10

USB20_P8
USB20_N8

USB_HSD7P
USB_HSD7N

C10
A10

USB20_P7
USB20_N7

USB_HSD6P
USB_HSD6N

H9
G9

USB_HSD5P
USB_HSD5N

A8
C8

USB_HSD4P
USB_HSD4N

F8
E8

USB_HSD3P
USB_HSD3N

C6
A6

USB_HSD2P
USB_HSD2N

C5
A5

USB_HSD1P
USB_HSD1N

C1
C3

USB20_P1
USB20_N1

USB_HSD0P
USB_HSD0N

E1
E3

USB20_P0
USB20_N0

USBSS_CALRP
USBSS_CALRN

C16
A16

USBSS_CALRP
USBSS_CALRN

USB_SS_TX3P
USB_SS_TX3N

A14
C14

USB_SS_RX3P
USB_SS_RX3N

C12
A12

1

30 Pin Sub board USB3.0 Conn
30 Pin Sub board USB3.0 Conn
USB30_P10 <36>
USB30_N10 <36>

USB20_P5
USB20_N5

Hudson-M2
EHCI CTL
DEV 22, Fn 2


Hudson-M3
xHCI CTL
DEV 16, Fn 1
xHCI CTL
DEV 16, Fn 0

On board USB Conn

USB20_P9 <34>
USB20_N9 <34>

Mini2-Option

USB20_P8 <34>
USB20_N8 <34>

Mini1-WLAN

USB20_P7 <36>
USB20_N7 <36>

BT

USB20_P5 <22>
USB20_N5 <22>

Camera

Hudson-M2/M3
EHCI CTL
DEV 19, Fn 2

Hudson-M2/M3
EHCI CTL
DEV 18, Fn 2


USB20_P1 <36>
USB20_N1 <36>

R864 1 M3@
R865 1 M3@

USB_SS_TX2P
USB_SS_TX2N

D15
B15
E14
F14

USB30_MRX_DTX_P2
USB30_MRX_DTX_N2

USB_SS_TX1P
USB_SS_TX1N

F15
G15

USB30_MTX_DRX_P1
USB30_MTX_DRX_N1

USB_SS_RX1P
USB_SS_RX1N

H13
G13

USB30_MRX_DTX_P1
USB30_MRX_DTX_N1

USB_SS_TX0P
USB_SS_TX0N

J16
H16

USB30_MTX_DRX_P0 C39 M3@1
USB30_MTX_DRX_N0 C37 M3@1

USB_SS_RX0P
USB_SS_RX0N

J15
K15

USB30_MRX_DTX_P0
USB30_MRX_DTX_N0

SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/WOL_EN/GPIO199
EC_PWM3/EC_TIMER3/GPIO200

H19
G19
G22
G21
E22
H22
J22
H21

R870
R872
R90
R91

KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208

K21
K22
F22
F24
E24
B23
C24
F18

1
1
1
1

For Right Side USB2.0 Port
2

USB20_P0 <36>
USB20_N0 <36>

USB_SS_RX2P
USB_SS_RX2N

PS2_DAT/SDA4/GPIO187
PS2_CLK/CEC/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166

D21
C20
D23
C22

R863 1

2
2
2
2

2 1K_0402_1%
2 1K_0402_1%

+FCH_VDD_11_SSUSB_S

Hudson-M3
xHCI CTL
DEV 16, Fn 1
xHCI CTL
DEV 16, Fn 0

USB30_MTX_DRX_P2 <36>
USB30_MTX_DRX_N2 <36>

30 Pin Sub board
USB3.0 Conn

USB30_MRX_DTX_P2 <36>
USB30_MRX_DTX_N2 <36>
USB30_MTX_DRX_P1 <36>
USB30_MTX_DRX_N1 <36>

30 Pin Sub board
USB3.0 Conn

USB30_MRX_DTX_P1 <36>
USB30_MRX_DTX_N1 <36>
2 .1U_0402_16V7K
2 .1U_0402_16V7K

USB30TXP <35,36>
USB30TXN <35,36>

On board
USB Conn

USB30_MRX_DTX_P0 <36>
USB30_MRX_DTX_N0 <36>

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

EC_PWM2

EC_PWM2 <28>

3

For PCIE device reset on FS1
(GFX,GLAN,WLAN,LVDS Travis)

HUDSON-M2_FCBGA656
M2@

FCH_GPIO189
FCH_GPIO190
FCH_GPIO188
FCH_GPIO187
FCH_GPIO166

+3VALW
@ C1199
1
2

R44
100K_0402_5%

R46
100K_0402_5%

LAN_CLKREQ#

R48
100K_0402_5%

@
WD_PWRGD

R55
100K_0402_5%

MINI2_CLKREQ#

1

MINI1_CLKREQ#

1

FCH_SDATA0
R61
100K_0402_5%

@

R43
2.2K_0402_5%

@

2
2.2K_0402_5%
2
2.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
10K_0402_5%
2
8.2K_0402_5%

VGA@

R45
2.2K_0402_5%

TEST2

+3VS
1
R880
1
R881
1
R882
1
R883
1
R862
1
R940

M2@ PX@
R47
2.2K_0402_5%

EDP@
TEST1
R57
2.2K_0402_5%

@

+3VALW

TEST0

2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%

R62
2.2K_0402_5%

@

FCH_GPIO189
FCH_GPIO190

1
1 R842
R843

FCH_PCIE_WAKE#

2

@

2 PX@
2 PX@

0_0402_5%
0_0402_5%

K19
J19
J21

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST#

EC_LID_OUT#

For FCH internal debug use
1
R887
1
R889
1
R890

<13,25> PE_GPIO0
<20,25> PE_GPIO1

AB3
AB1
AA2
Y5
Y3
Y1
AD6
AE4

R03 modify for Resverd

FCH_SCLK1

1

@

R03 modify
remove D44/D45

2

@

USB_OC1#

1

@

2
100K_0402_5%
2
10K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
100K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
8.2K_0402_5%

2

3

H6
H5

USB_RCOMP

USB30_MTX_DRX_P2
USB30_MTX_DRX_N2

HD AUDIO

HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SYNC
HDA_RST#

2 33_0402_5%
2 33_0402_5%

USB 3.0

R866 1
R867 1

<39> HDA_BITCLK_AUDIO
<39> HDA_SDOUT_AUDIO
<39> HDA_SDIN0

1
R54
1
R871
1
R874
1
R876
1
R877
1
R878
1
R18
1
R37
1
R942

USB_FSD0P/GPIO185
USB_FSD0N

+3VS

2

<31> CARD_DET

H1
H3

RSMRST#

USB OC

<30> ODD_DA#

KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
LPC_PD#/GEVENT5#
SYS_RESET#/GEVENT19#
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
WD_PWRGD

B9

USB_FSD1P/GPIO186
USB_FSD1N

VGA_PWRGD

<20,49> VGA_PWRGD

@ U27
2
1

0.1U_0402_16V4Z

5

1

VGA_PWRGD_R

U2
AG24
AE24
AE26
AF22
AH17
AG18
AF24
AD26
AD25
T7
R7
AG25
AG22
J2
AG26
V8
W8
Y6
V10
AA8
AF25

GA20IN/GEVENT0#

G8

USB_RCOMP

B

P

2

ZERO@
R954
10K_0402_5%

AE22

USBCLK/14M_25M_48M_OSC

Y
A

4

G

<39> FCH_SPKR
<11,12,34> FCH_SCLK0
<11,12,34> FCH_SDATA0
<38> FCH_SCLK1
<38> FCH_SDATA1
<34> MINI1_CLKREQ#

+3VS

TEST0
TEST1/TMS
TEST2

AG19
R9
C26
T5
SYS_RESET#
U4
FCH_PCIE_WAKE# K1
V7
H_THERMTRIP#
R10
WD_PWRGD
AF19

<37> EC_RSMRST#

+3VS

T9
T10
V9

EC_KBRST#
EC_SCI#
EC_SMI#

<37> EC_KBRST#
<37> EC_SCI#
<37> EC_SMI#

SM bus 0-->S0 PWR domain
SM bus 1-->S5 PWR domain

TEST0
TEST1
TEST2
EC_GA20

<37> EC_GA20

THERMTRIP:
Need level shift from +3VALW to +1.5V
Note: Ensure FCH internal pull-up resistor
to +3.3V S5 is disabled to prevent leakage
when APU is powered down.

SLP_S3#
SLP_S5#
PBTN_OUT#
FCH_PWRGD

PCIE_RST2#/PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD

USB 1.1

<37> SLP_S3#
<37> SLP_S5#
<37> PBTN_OUT#
<37> FCH_PWRGD

HUDSON-2
AB6
R2
W7
T3
W2
J4
N7

ACPI / WAKE UP EVENTS

<35> FCH_PCIE_RST#
<37> EC_LID_OUT#

E

U25D

FL@
FCH_PCIE_RST#_R
1
2
R837
33_0402_5% EC_LID_OUT#

USB 2.0

1

D

GPIO

FCH_PCIE_RST# IS FOR PCIE
DEVICES ON Hudson-M2/M3

C

R03 modify
Update BOM Structure

FL@
C1211
2 150P_0402_50V8J

1
R830

@

1
R831

2
@ 100K_0402_5%

2
0_0402_5%

VGA_PWRGD_R

4

1
R884
1
R885
1
R886
1
R888
1
R891
1
R893

@
@
@
@
@

2
2.2K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

3

NC7SZ08P5X_NL_SC70-5
EC_RSMRST#
HDA_BITCLK
1
R832

HDA_SDIN0
HDA_SDIN1

Project SKU ID

2
0_0402_5%

4

Value

GPIO189 (use VGA)

Low (UMA)

High (VGA)

GPIO190 (use PX)

Low (noPX)

High (PX)

GPIO188 (USB2/3)

High (2.0)

Low (3.0)

GPIO187 (LVDS/eDP)

Low (LVDS)

High (eDP)

HDA_SDIN2
HDA_SDIN3

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

GPIO166 (Resverd)

2011/07/08

Deciphered Date

2015/07/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SCHEMATIC,MB A8331
Document Number

Rev
B

4019H2
Wednesday, February 29, 2012
E

Sheet

27

of

52

A

B

C

D

E

STRAP PINS
1

PULL
HIGH

PCI_CLK1

PCI_CLK3

PCI_CLK4

ALLOW
PCIE GEN2

USE
DEBUG
STRAPS

NON_FUSION EC
CLOCK MODE ENABLED

LPC_CLK0

DEFAULT

PULL
LOW

LPC_CLK1

EC_PWM2

CLKGEN
ENABLED

LPC ROM

DEFAULT

FORCE
PCIE GEN1

IGNORE
DEBUG
STRAP

FUSION
CLOCK
MODE

EC
DISABLED

DEFAULT

DEFAULT

DEFAULT

RTC_CLK
1

S5 PLUS
MODE
DISABLED
DEFAULT

SPI ROM

CLKGEN
DISABLE

S5 PLUS
MODE
ENABLED

DEFAULT
L47
1
2
FBMA-L11-201209-221LMA30T_0805

30mil

220 ohm
+3VS

2

1

2

0.1U_0402_16V4Z

1

2.2U_0603_6.3V4Z

1
2

1
2

1
2

1
2

1
2

1
2

Remove VGA_PD

C1210

C1209

R911 10K_0402_5%

@

+FCH_VDDAN_33_DAC_R

+3VALW

R910 10K_0402_5%

2

+3VALW

R909 10K_0402_5%

@

+3VALW

R908 10K_0402_5%

@

+3VALW
R907 10K_0402_5%

@

+3VS
R906 10K_0402_5%

2

10K_0402_5%

<25> PCI_CLK1

+3VS
R905

1

+3VS

<25> PCI_CLK3

2

<25> PCI_CLK4
<25,37> LPC_CLK0_EC
<25> LPC_CLK1
<27> EC_PWM2

1
2

1
2

1
2

1
2

1
2

1
2

2

@

1
R912

R922 2.2K_0402_5%

R921 2.2K_0402_5%

@

R920 10K_0402_5%

R919 10K_0402_5%

R918 10K_0402_5%

R917 10K_0402_5%

@

R915 10K_0402_5%

1

<25,37> RTC_CLK

2
0_0402_5%

+1.1VS

+FCH_VDDAN_11_MLDAC

30mil

DEBUG STRAPS

Remove VGA_PD

FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]
3

3

PCI_AD26

PCI_AD27
PULL
HIGH

PULL
LOW

PCI_AD25

PCI_AD24

PCI_AD23

USE PCI
PLL

DISABLE
ILA
AUTORUN

USE FC
PLL

USE DEFAULT
PCIE STRAPS

DISABLE PCI
MEM BOOT

DEFAULT

DEFAULT

DEFAULT

DEFAULT

DEFAULT

BYPASS
PCI PLL

ENABLE
ILA
AUTORUN

BYPASS
FC PLL

USE EEPROM
PCIE STRAPS

ENABLE PCI
MEM BOOT

<25> PCI_AD27
<25> PCI_AD26
<25> PCI_AD25
<25> PCI_AD24

1
2

1
2

1
2

2

1
2

@

R930 2.2K_0402_5%

@

R929 2.2K_0402_5%

@

R928 2.2K_0402_5%

@

R927 2.2K_0402_5%

R926 2.2K_0402_5%

@

1

<25> PCI_AD23

4

4

2011/07/08

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2015/07/08

Deciphered Date

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

A

B

C

D

Sheet

Wednesday, February 29, 2012
E

28

of

52

B

C

D

E

+VCC_FCH_R
U25C

PCI/GPIO I/O

CORE S0
CLKGEN I/O

1

2

PCI EXPRESS

1

2

2

1

2

C1247

MAIN LINK

2
0_0603_5%

1
R938

2
0_0805_5%

1
R941

2
0_0805_5%

R25

1

2

22U_0805_6.3V6M

2

1

C1246

1

.1U_0402_16V7K

SERIAL ATA

C1237

2

+1.1VS

+3VALW

59mA

+VDDIO_33_S

2

1

2

C1252

1

1

2

2.2U_0603_6.3V4Z

GBE LAN

1

1337mA+AVDD_SATA

C1245

3.3V_S5 I/O

+1.1VS

2.2U_0603_6.3V4Z

1

R26

1

2
0_0402_5%

+3VALW

10mils

5mA

+VDDXL_3.3V

2

220 ohm

G

2

VSSAN_HWM

K25

VSSXL

USB

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

H25

VSSPL_SYS

VSSPL_DAC
VSSAN_DAC
VSSANQ_DAC
VSSIO_DAC
EFUSE

D

S

10mils

T25
T27
U6
U14
U17
U20
U21
U30
U32
V11
V16
V18
W4
W6
W25
W28
Y14
Y16
Y18
AA6
AA12
AA13
AA14
AA16
AA17
AA25
AA28
AA30
AA32
AB25
AC6
AC18
AC28
AD27
AE6
AE15
AE21
AE28
AF8
AF12
AF16
AF33
AG30
AG32
AH5
AH11
AH18
AH19
AH21
AH23
AH25
AH27
AJ18
AJ28
AJ29
AK21
AK25
AL18
AM21
AM25
AN1
AN18
AN28
AN33

1

2

3

T21
L28
K33
N28
R6

VDDPL_11_SYS_S

J24

L29

70mA

+VDDPL_1.1V

2

C1272

1

1

2

1
2
MBK1608221YZF_2P

.1U_0402_16V7K

VDDCR_11_USB_S_1
VDDCR_11_USB_S_2

C1271

2

T12
T13

2.2U_0603_6.3V4Z

2

1

@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

+1.1VALW

10mils

.1U_0402_16V7K

1

C1270

2

C1269

1

.1U_0402_16V7K

C1268

220 ohm

2.2U_0603_6.3V4Z

1
2
MBK1608221YZF_2P

N8

Q13
1 AO3416L_SOT23-3

3
+VDDCR_1.1V_USB

2
0_0603_5%
SYSON <35,37,40,48>

2

C1265

2

1

1
R1145

1U_0402_6.3V6K

C1264

VDDCR_11_S_1
VDDCR_11_S_2

187mA

+VDDCR_1.1V

1

197mA

+3VS

M2@ L30
1
2
MBK1608221YZF_2P

+1.1VALW

10mils

N20
M20

1U_0402_6.3V6K

VDDAN_11_USB_S_1
VDDAN_11_USB_S_2

C1261

10mils

1

2.2U_0603_6.3V4Z

C1260

2

.1U_0402_16V7K

1

M3@ L28
1
2
MBK1608221YZF_2P

+1.1VALW
L59

22U_0805_6.3V6M

C1230

C1236

2

.1U_0402_16V7K

2

C1251

G24

HUDSON-2
A3
A33
B7
B13
D9
D13
E5
E12
E16
E29
F7
F9
F11
F13
F16
F17
F19
F23
F25
F29
G6
G16
G32
H12
H15
H29
J6
J9
J10
J13
J28
J32
K7
K16
K27
K28
L6
L12
L13
L15
L16
L21
M13
M16
M21
M25
N6
N11
N13
N23
N24
P12
P18
P20
P21
P31
P33
R4
R11
R25
R28
T11
T16
T18

1088mA
.1U_0402_16V7K

C1235

1

.1U_0402_16V7K

VDDXL_33_S

U25E

+1.1VS

C1244

VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12

2

2.2U_0603_6.3V4Z

2

.1U_0402_16V7K

2

1

+AVDD_SATA

10mils

VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8

C1219

C1217

C1226

1

.1U_0402_16V7K

C1225

.1U_0402_16V7K

AA21
Y20
AB21
AB22
AC22
AC21
AA20
AA18
AB20
AC19
N18
L19
M18
V12
V13
Y12
Y13
W11

2.2U_0603_6.3V4Z

C1216

.1U_0402_16V7K

C1215

1

1U_0402_6.3V6K

2

VDDIO_GBE_S_1
VDDIO_GBE_S_2

1

2

C1250

1

2

+PCIE_VDDR_FCH

.1U_0402_16V7K

2

C1263

1

VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2

U12
U13

VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
VDDAN_11_SATA_8
VDDAN_11_SATA_9
VDDAN_11_SATA_10

VDDIO_33_GBE_S

AA9
AA10

AB24
Y21
AE25
AD24
AB23
AA22
AF26
AG27

C1243

C1257

2

.1U_0402_16V7K

2

1

.1U_0402_16V7K

C1262

2

2

1

+VDDAN_11_USB_S
2.2U_0603_6.3V4Z

C1267

1

220 ohm
.1U_0402_16V7K

C1266

2

2.2U_0603_6.3V4Z

1

2

1

2

1

340mA

1

60mils

VDDAN_11_ML_1
VDDAN_11_ML_2
VDDAN_11_ML_3
VDDAN_11_ML_4

AB11
AA11

G7
H8
J8
K8
K9
M9
M10
N9
N10
M12
N12
M11

VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8

VDDPL_11_DAC

30mils

+1.1VALW

+3VS

220 ohm

1

C1256

2

L57
140mA
1
2
MBK1608221YZF_2P
L22
+VDDPL_33_SATA
1
2
MBK1608221YZF_2P

2
0_0402_5%

10U_0603_6.3V6M

2

2

Y22
V23
V24
V25

AB10

10U_0603_6.3V6M

1

1

C1255

2

C1259

1

.1U_0402_16V7K

C1258

220 ohm

2.2U_0603_6.3V4Z

+VDDPL_33_PCIE
1
2
MBK1608221YZF_2P

C1254

L15

2

1

+VDDAN_33_USB
1U_0402_6.3V6K

220 ohm/3A

1U_0402_6.3V6K

C1253

L54
658mA
1
2
FBMA-L11-201209-221LMA30T_0805

+3VS

1

1
R945

+3VALW

V21

1

2
0_0805_5%

+PCIE_VDDR_FCH

1U_0402_6.3V6K

2

LDO_CAP

20mils

.1U_0402_16V7K

C1249

1

.1U_0402_16V7K

C1248

2

2.2U_0603_6.3V4Z

1

C1241
4.7U_0603_6.3V6K

2

220 ohm

3

1

C1242
.1U_0402_16V7K

2
0_0603_5%

+VDDAN_33_USB
L7
1
2+FCH_VDDPL_33_USB_S
MBK1608221YZF_2P

VDDPL_33_SATA

+VDDAN_11_ML

226mA
1
R1148

VDDPL_33_PCIE

10mils

+VDDPL_11_DAC

2
0_0402_5%

.1U_0402_16V7K

220 ohm/2A

1

2

C1234

7mA
R24

M31

2
2.2U_0603_6.3V4Z

2

50mils

VDDPL_33_USB_S

@
1
C1232

2

1

1U_0402_6.3V6K

AG28

1

VDDPL_33_SSUSB_S

C1233

10mils

C1240

M3@

M3@

2

L24
1
2
MBK1608221YZF_2P

D7

AH29

VDDAN_33_DAC

1

C1224

10mils

+VDDPL_33_PCIE

VDDPL_33_ML

2

+1.1VS_CKVDD
1U_0402_6.3V6K

43mA

+FCH_VDDPL_33_USB_S

L18

VDDPL_33_DAC

2

1

1
R937

+1.1VS_CKVDD

20mils

VDDPL_33_SYS

C1214

10mils

H26
J25
K24
L22
M22
N21
N22
P22

2

1

1U_0402_6.3V6K

17mA

VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8

1

1U_0402_6.3V6K

C1239

1

.1U_0402_16V7K

C1238

2

2.2U_0603_6.3V4Z

1
2 +FCH_VDDPL_33_SSUSB_S
MBK1608221YZF_2P

2

10mils

M2@ 10_0402_5% +FCH_VDDPL_33_SSUSB_S

93mA
LDO_CAP: Internally generated 1.8V +VDDPL_33_SATA
supply for the RGB outputs
For A11: Cap = 1nF
For A12, Cap = DNI
+FCH_VDDAN_11_MLDAC

M3@ L6

1

20mA

R936 2

T14
T17
T20
U16
U18
V14
V17
V20
Y17

C1223

VDDPL_33_SSUSB_S
For Hudson3 USB3.0 only
For Hudson2, connect to GND

50mils

VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9

1U_0402_6.3V6K

1

2

+3VALW

220 ohm

1

VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10

C1213

2

.1U_0402_16V7K

220 ohm

10mils

+VDDPL_33_DAC
V22
2
0_0402_5%
10mils
+VDDPL_33_ML
U22
2
0_0402_5%
200mA R23
10mils
+FCH_VDDAN_33_DAC_R
T22

20mA R22

1

.1U_0402_16V7K

1

C1231

C1227

1
2
MBK1608221YZF_2P

10mils

20mA

+FCH_VDDPL_33_MLDAC

@ L4

2

HUDSON-2

AB17
AB18
AE9
AD10
AG7
AC13
AB12
AB13
AB14
AB16
H24

2 +FCH_VDDPL_33_MLDAC
0_0603_5%
2.2U_0603_6.3V4Z

R19

+3VS

2

1

47mA
+VDDPL_3.3V

+FCH_VDDAN_33_DAC_R
1

2

C1221

2

2

1

.1U_0402_16V7K

1

1

C1220

.1U_0402_16V7K

2

C1229

C1222

1

2.2U_0603_6.3V4Z

220 ohm

1

1

C1228

+VDDPL_3.3V

1
2
MBK1608221YZF_2P

+VDDIO_33_PCIGP

2
0_0603_5%

.1U_0402_16V7K

1

C1218

R20

L3

22U_0805_6.3V6M

+3VS

+3VS

+1.1VS

1007mA

10mils

1U_0402_6.3V6K

131mA

GROUND

A

HUDSON-M2_FCBGA656
M2@

+1.1VS

Connected to VSS through a dedicated via.

L31
@
1
2
MBK1608221YZF_2P

220 ohm
+3VALW

+FCH_VDD_11_SSUSB_S

20mils

1

USB SS

+FCH_VDD_11_SSUSB_S

1
2

1
2

VDDAN_33_HWM_S

30mils

N16
N17
P17
M17

2

VDDCR_11_SSUSB_S_1
VDDCR_11_SSUSB_S_2
VDDCR_11_SSUSB_S_3
VDDCR_11_SSUSB_S_4

M3@

2

C1281

1

1

2

.1U_0402_16V7K

M3@

2

C1280

1

.1U_0402_16V7K

M3@

M3@

2

C1279

1

1U_0402_6.3V6K

C1278

42 ohm/4A

+VDDCR_11_SSUSB
10U_0603_6.3V6M

M3@ 2
0_0603_5%

1

2

R27

1

2
0_0402_5%

AMD reply:
VDDAN_33_HWM_S: Please connect
it to +3.3V_S5 directly if HWM is not used.

+3VS

10mils

VDDIO_AZ_S

AA4

1

1
C1276
1
C1277

HUDSON-M2_FCBGA656
M2@

R28
2
2.2U_0603_6.3V4Z
2
.1U_0402_16V7K

2
0_0402_5%

2011/07/08

4

VDDIO_AZ_S should be tied to
+3.3/1.5V_S5 rail if Wake on Ring
is supported

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

26mA

+VDDIO_AZ

POWER

424mA

C1473

VDDAN_11_SSUSB_S_1
VDDAN_11_SSUSB_S_2
VDDAN_11_SSUSB_S_3
VDDAN_11_SSUSB_S_4
VDDAN_11_SSUSB_S_5

12mA

+VDDAN_33_HWM

.1U_0402_16V7K

2

10mils

M8

C1472

1

.1U_0402_16V7K

M3@

2

C1275

1

.1U_0402_16V7K

2

M3@

2
1
1
L61 M3@
R1150
FBMA-L11-201209-221LMA30T_0805

1

C1274

+1.1VALW

M3@

M2@
C1281
0_0402_5%

+VDDAN_SSUSB

M3@ 2
0_0603_5%
C1273

4

M2@
C1275
0_0402_5%

40mils

1U_0402_6.3V6K

1
R1149
For FCH M2 - BOM option
VDDAN_11_SSUSB_S / VDDAN_11_SSUSB_S
Connected to VSS.

P16
M14
N14
P13
P14

2.2U_0603_6.3V4Z

282mA

2015/07/08

Deciphered Date

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

A

B

C

D

Sheet

Wednesday, February 29, 2012
E

29

of

52

A

B

C

D

E

F

G

H

SATA ODD Conn.

SATA HDD1 Conn.
JHDD1
<26> SATA_STX_DRX_P0
<26> SATA_STX_DRX_N0
<26> SATA_DTX_C_SRX_N0
<26> SATA_DTX_C_SRX_P0

C1283 1
C1285 1

2 .01U_0402_16V7K
2 .01U_0402_16V7K

SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0

C1287 1
C1289 1

2 .01U_0402_16V7K
2 .01U_0402_16V7K

SATA_DTX_SRX_N0
SATA_DTX_SRX_P0

1
2
3
4
5
6
7

GND
RX+
RXGND
TXTX+
GND

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Rsv
GND
12V
12V
12V
GND
GND

JODD1
S H-CONN SANTA 205503-1 13P H5.5

1

+3VS
1

2

+3VS

C1290
0.1U_0402_16V4Z

2
R953

+5VS

+5VS_HDD1

1
0_0805_5%
10U_0603_6.3V6M
C1292

80mils

1

C1293

2

0.1U_0402_16V4Z
1

C1294

2

1

C1295

2

1U_0402_6.3V6K

1

2
1000P_0402_50V7K

<26> SATA_STX_DRX_P1
<26> SATA_STX_DRX_N1

C1301 1
C1300 1

2 .01U_0402_16V7K
2 .01U_0402_16V7K

SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1

<26> SATA_DTX_C_SRX_N1
<26> SATA_DTX_C_SRX_P1

C1302 1
C1303 1

2 .01U_0402_16V7K
2 .01U_0402_16V7K

SATA_DTX_SRX_N1
SATA_DTX_SRX_P1

R79

<27> ODD_PLUG#

1

ZERO@

2 0_0402_5%

100mils

+5VS_ODD
R80

<27> ODD_DA#

10U_0805_10V4Z

1

ZERO@

2 0_0402_5%

1
2
3
4
5
6
7

GND
A+
AGND
BB+
GND

8
9
10
11
12
13

DP
+5V
+5V
MD
GND
GND

1

GND
GND
GND
GND

17
16
15
14

0.1U_0402_16V4Z
CONN@

C1304

1

C1305

1

1

C1306

C1307

1
Part Number = SP010013G00

2

2

2

1U_0402_6.3V6K

2

PCB Footprint = OCTEK_SLS-13SB1G_13P_RV

1000P_0402_50V7K

CONN@
OCTEK_SAT-22DD1G
Part Number = DC010002Q00
PCB Footprint = OCTEK_SAT-22DD1G_22P

+5VS_ODD

+5VS
R793
0_0805_5%
2
1

ZERO@
R1129
470_0603_5%

S

D

1

4
ZERO@
Q86
SI3456BDV-T1-E3_TSOP6

2

1

ZERO@
R789
470K_0402_5%

D
2

1

2

ZERO@
R21
10K_0402_5%

3

2

6
5
1
ZERO@
2
C812
1
1U_0402_6.3V6K
2

G

1

+VSB
2

+5VS

Change to +5VS
20110208

+5VS_ODD

100mils
2

100mils

ODD_EN#

G
1 ZERO@
C811
.1U_0603_25V7K

3

ZERO@
ZERO@
R785
Q91B
1.5M_0402_5%
DMN66D0LDW-7_SOT363-6

ZERO@
Q75
2N7002K_SOT23-3

2

0
E
W
5
P
w
o
l
l
o
F

e
l
o
H
w
e
r
c
S
f
f
O
d
n
a
t
S
N
A
F

FAN

4

1

1

5

S
2

3

2

<26> ODD_PWR

ODD_EN

6

ODD_EN#
ZERO@
Q91A
DMN66D0LDW-7_SOT363-6

C1404
1

@

H7
H_3P4
@

1

@

H3
H_3P4

1

+5VS
3

H2
H_3P4

1

1

H1
H_3P4

@
3

10U_0805_10V4Z
2
H8
H_3P0

H9
H_3P0

H10
H_3P0

H11
H_3P0

H13
H_3P0

H14
H_3P0

H15
H_3P0

H16
H_3P0

H17
H_3P0

H18
H_3P0

H28
H_3P0

1

FD1

+VCC_FAN1

<37> FAN_SPEED1
1

C1408
1000P_0402_50V7K

JFAN1
1
2
3
4
5

2

1

2

40mil
4

1
2
3

H27
H_3P5X3P0N

@

FIDUCIAL_C40M80

FIDUCIAL_C40M80

@

1

@

1

@

1

@

1

1

1
1

@

@

@

R03 Add

@

FD2
@

@

H24
H_4P2

H29
H_3P5N

@

FD3
@

1

1

@

1

1

H26
H_3P0N

1

R1066
10K_0402_5%

@

H23
H_4P2

@

FD4
@

1

For Layout request
Delete H25
20110419

C1407
1000P_0402_50V7K
1
2

@

H22
H_4P2

1

+3VS

@

H21
H_4P2

@

1

C1406
10U_0805_10V4Z
1
2

H20
H_4P0

@

1

H19
H_4P0

@

1

@
APL5607KI-TRG_SO8
C1405
0.1U_0402_16V4Z

@

1

GND
GND
GND
GND

1

2

EN
VIN
VOUT
VSET

1

2
0_0402_5% 1

1

1
R1065

1

+VCC_FAN1
<37> EN_DFAN1

8
7
6
5

1

U35
1
2
3
4

FIDUCIAL_C40M80

@
4

FIDUCIAL_C40M80

GND
GND
CONN@
ACES_85205-03001
Part Number = SP02000AG00
PCB Footprint = ACES_85205-03001_3P

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

2015/07/08

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC,MB A8331
Document Number

Date:

A

B

C

D

E

F

Rev
B

4019H2
Wednesday, February 29, 2012
G

Sheet

30
H

of

52

5

4

3

U55

D

<6> PCIE_FTX_C_DRX_P3

PCIE_FTX_C_DRX_P3 1

<6> PCIE_FTX_C_DRX_N3

PCIE_FTX_C_DRX_N3 2

48

RREF

60mil

1
R1700

2
6.2K_0402_1%

3V3_IN

CLK_PCIE_CR

3

REFCLKP

CLK_REQ#

46

CRCLK_REQ#

<25> CLK_PCIE_CR#

CLK_PCIE_CR#

4

REFCLKN

PERST#

45

APU_PCIE_RST#

<6> PCIE_DTX_C_FRX_P3
<6> PCIE_DTX_C_FRX_N3
AV12 1
R1704

C

RREF

<25> CLK_PCIE_CR

@

2 DV12
0_0402_5%

20mil
AV12
2
4.7U_0603_6.3V6K
PCIE_DTX_FRX_P3
2
.1U_0402_16V7K
PCIE_DTX_FRX_N3
2
.1U_0402_16V7K

HSIN

5

AV12

EEDO

44

6

HSOP

EECS

43

7

HSON

8

GND

20mil

9

+CARDPWR

40mil

10

Card1_3V3

+3VS_CR

60mil

11

3V3_IN

1
C1703

1
C1706
1
C1705

DV12
2
0.1U_0402_16V4Z

20mil

2

SD_D1_R
SD_D0_R
1
2
C1720
4.7P_0402_50V8C

SD_CLK_R
SD_CMD_R
SD_D3_R

1
R1705
1
R1706
1
R1707
1
R1708
1
R1709

+3VS_CR
CRCLK_REQ# <25>

1
R1701

2
0_0402_5%

EESK

42

GPIO/EEDI

41

5IN1_LED#

MS_INS#

40

MS_INS#

SD_CD#

39

SD_CD#

SP15

38

SP15_SDWP_XDD7

SP14

37

SP13

36

SP14_XDD6 1
R1703
SP13_MSD7_XDD5
SP12_MSD3_XDD4

DV12

800mA

400mA

CARD_DET <27>

D3-Delink function for AMD
0: Card remove, PCIE De-link
1: Card Insert PCIE link

5IN1_LED# <38>

PU on LED side

JREAD1

Card2_3V3

XD_CD#

13

XD_CD#

DV33_18

14

DV33_18

SP12

35

15

GND

SP11

34

SP11_MSD6_XDD3

SP1_SDD7_XDRDY16

SP1

SP10

33

SP10_MSD2_XDD2

SP2_SDD6_XDRE# 17

SP2

SP9

32

SP9_MSD0_XDD1
SP8_MSD4_XDD0

SP3_SDD5_XDCE# 18

SP3

SP8

31

SP4_SDD4_XDWE#19

SP4

SP7

30

SP7_MSD1_XDWP#
SP6_MSD5_XDALE

SD_D1
2
0_0402_5%
SD_D0
2
0_0402_5%
SD_CLK
2
10_0402_5%
SD_CMD
2
0_0402_5%
SD_D3
2
0_0402_5%

D

APU_PCIE_RST# <13,25,32,34,35>

12

1U_0402_6.3V6K
2
@ 4.7U_0603_6.3V6K

1

10mil

HSIP

47

1
C1700
1
C1701
1
C1702

2

20

SD_D1

SP6

29

21

SD_D0

SP5

28

SP5_MSBS_XDCLE

22

SD_CLK

DV12_S

27

DV12_S

23

SD_CMD

GND

26

24

SD_D3

SD_D2

25

SD_D2

+XDPWR_SDPWR_MSPWR
MSCLK
2
0_0402_5%

1

40mil

2

@ C1719
10P_0402_50V8J

11
18
39

SD_CLK_R
8
SD_CMD_R
16
SD_CD#
1
SP15_SDWP_XDD7 2
SD_D0_R
4
SD_D1_R
3
SD_D2_R
21
SD_D3_R
19

SD_CLK
SD_CMD
SD_CD
SD_WP
SD/MMC_DAT0
SD/MMC_DAT1
SD/MMC_DAT2
SD/MMC_DAT3

Card Reader
Connector
1
C1707
1
C1709

2
4.7U_0603_6.3V6K
2
0.1U_0402_16V4Z

SD_D2_R
2
0_0402_5%

1
R1710

XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7

31
32
33
34
35
36
37
38

SP8_MSD4_XDD0
SP9_MSD0_XDD1
SP10_MSD2_XDD2
SP11_MSD6_XDD3
SP12_MSD3_XDD4
SP13_MSD7_XDD5
SP14_XDD6
SP15_SDWP_XDD7

XD_CD
XD_R/B
XD_RE
XD_CE
XD_CLE
XD_ALE
XD_WE
XD_WP-IN

22
23
24
25
26
27
28
29

XD_CD#
SP1_SDD7_XDRDY
SP2_SDD6_XDRE#
SP3_SDD5_XDCE#
SP5_MSBS_XDCLE
SP6_MSD5_XDALE
SP4_SDD4_XDWE#
SP7_MSD1_XDWP#

SD_GND
SD_GND
MS_GND
MS_GND
XD_GND
XD_GND
GND
GND

6
13
5
20
30
40
41
42

SD_VCC
MS_VCC
XD_VCC

SP9_MSD0_XDD1 10
SP7_MSD1_XDWP# 9
SP10_MSD2_XDD2 12
SP12_MSD3_XDD4 15
MSCLK
17
MS_INS#
14
SP5_MSBS_XDCLE 7

MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3
MS_SCLK
MS_INS
MS_BS

C

TAITW_R013-P17-HM_NR
CONN@
Part Number = SP07000RU00
PCB Footprint = TAITW_R013-P17-HM_40P_NR

RTS5209-GR_LQFP48_7X7
Part Number = SA000042A00
PCB Footprint = RTS5209-GR_LQFP48_7X7
B

B

60mil

60mil

40mil

+3VS

+3VS_CR

+CARDPWR

For EMI Requirement Close to JREAD1

40mil
+XDPWR_SDPWR_MSPWR

SD_CLK_R
R1713
1
2
0_0603_5%

2

2

Close to Pin 11,47

1

2

C1712
0.1U_0402_16V4Z

2

1

C1711
0.1U_0402_16V4Z

100K_0402_5%
@R1715
@
R1715

1

R1711

1
2
1
10_0402_5% C1710

2
4.7P_0402_50V8C

R1714

1
2
1
10_0402_5% C1714

2
10P_0402_50V8J

MSCLK
C1713
10U_0603_6.3V6M

2

1

C1718
0.1U_0402_16V4Z

1

C1717
0.1U_0402_16V4Z

2

C1716
0.1U_0402_16V4Z

C1715
10U_0603_6.3V6M

1

1

2
0_0603_5%

2

1
R1712

1

2

close to JREAD1

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Deciphered Date

2015/07/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

SCHEMATIC,MB A8331
Document Number

Rev
B

4019H2
Wednesday, February 29, 2012

Sheet
1

31

of

52

5

4

3

2

1

Power On strapping
Pin

Description
H:Over Clock Enable

LED0
LED0,1,2 intel Pull UP

U56
1
C1800
1
C1801

<6> PCIE_DTX_C_FRX_N0
D

<6> PCIE_DTX_C_FRX_P0

PCIE_DTX_FRX_N0 29

2
.1U_0402_16V7K
2
.1U_0402_16V7K

PCIE_DTX_FRX_P0 30

LED_0
LED_1
LED_2

38
39
23

TRXN0
TRXP0
TRXN1
TRXP1
TRXN2
TRXP2
TRXN3
TRXP3

12
11
15
14
18
17
21
20

SMCLK
SMDATA

RBIAS

10

TEST_RST
TESTMODE

VDD33

TX_N
TX_P

<6> PCIE_FTX_C_DRX_N0

PCIE_FTX_C_DRX_N036

RX_N

<6> PCIE_FTX_C_DRX_P0

PCIE_FTX_C_DRX_P035

RX_P

<25> CLK_PCIE_LAN#
<25> CLK_PCIE_LAN
<13,25,31,34,35> APU_PCIE_RST#

R1801 1
R1802 1

2 0_0402_5% CLK_PCIE_LAN#_R
2 0_0402_5% CLK_PCIE_LAN_R

R1804 1

2 0_0402_5%

<37> EC_PME#

R1805 1

<27,34,35> FCH_PCIE_WAKE#

R1806 1

PU at EC side

2 0_0402_5% LAN_PME#
@

2 0_0402_5%

32
33

PERST#

3

WAKE#

+2.7_AVDDH

GND
S IC AR8151-BL1A-RL QFN 40P E-LAN CTRL
8151@

2

Near
Pin6

1

2

Near
Pin9

1

2

1

2

Near
Pin22

1

2

1

2

Near
Pin37

1

2

2

+3V_LAN

2

1

2

1

@

2

LAN_MIDI0+

R1809 1

@1

LAN_MIDI0-

R1810 1

1

LAN_MIDI1+
LAN_MIDI1-

LAN_MIDI2-

S

D

Q1801 @
AO3419L_SOT23-3
1
3

LAN_MIDI3+
LAN_MIDI3-

2
2

R1819
0_0402_5%

1

2

R03 change footprint

2
C

2
49.9_0402_1%
2
49.9_0402_1%
R1811 1
2
49.9_0402_1%
R1812 1
2
49.9_0402_1%
R1813 1
2
8151@ 49.9_0402_1%
R1814 1
2
8151@ 49.9_0402_1%
R1815 1
2
8151@ 49.9_0402_1%
R1816 1
2
8151@ 49.9_0402_1%

@1
1

2 C1826 1000P_0402_50V7K
2 C1827 0.1U_0402_16V4Z

B

2 C1828 1000P_0402_50V7K
2 C1829 0.1U_0402_16V4Z

@1

2 C1830 1000P_0402_50V7K

1

2 C1831 0.1U_0402_16V4Z
8151@
2 C1832 1000P_0402_50V7K

@1
1

2 C1833 0.1U_0402_16V4Z
8151@

Note 1 : 8152 no mount MDI3+, MDI3-, MDI2-, MDI2+
resister and cap

G
<37> LAN_PWR_EN#

2

1

Place Close to LAN chip

Near
Pin16

+3VALW

@

1

Near
Pin24

LAN_MIDI2+

1

@

2

L1800
1
2
FBMA-L11-201209-221LMA30T_0805

LAN_PWR_EN#

1
2
4.7UH_PG031B-4R7MS_1.1A_20%
PCB Footprint = CYNTE_PG031B-4R7MS_2P

1

B

R04 modify 1219

1

C1804
10U_0805_10V4Z

R1818 8151@ 0_0402_5%
1
2

C1823
0.1U_0402_16V4Z

Pin16 for AR8152 LED2

1

C1810
0.1U_0402_16V4Z

AVDDH
AVDDH
AVDDH_REG

16
22
9

2
0.1U_0402_16V4Z

C1820
8151@
0.1U_0402_16V4Z

Near Near Near Near
Pin13 Pin19 Pin31 Pin34

41

1

AVDDL
AVDDL
AVDDL
AVDDL
AVDDL_REG

1
C1806

C1819
0.1U_0402_16V4Z

2

+1.1_DVDDL

C1818
1U_0402_6.3V6K

2

24
37

C1817
0.1U_0402_16V4Z

2

1

C1816
0.1U_0402_16V4Z

2

1

C1815
1U_0402_6.3V6K

2

1

C1814
0.1U_0402_16V4Z

2

1

C1813
0.1U_0402_16V4Z

1

1

C1812
8151@
0.1U_0402_16V4Z

33P_0402_50V8J

C1811
8151@
0.1U_0402_16V4Z

C1825

33P_0402_50V8J

2

25MHZ_20PF_7A25000012

C1824

1

2

DVDDL
DVDDL_REG

+1.7_VDDCT

C1822
1U_0402_6.3V6K

X3
1

13
19
31
34
6

+1.7_LX
L1801

+1.7_LX

C1821
0.1U_0402_16V4Z

+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL

LAN_XTALO

5

+1.7_VDDCT

CLKREQ#

PU at FCH side
LAN_XTALI

+1.7_VDDCT

1
40

LX
XTLO
XTLI
VDDCT

4

+3V_LAN

Close Pin 10
C1803
1000P_0402_50V7K

<27> LAN_CLKREQ#

1
2
R1807 2.37K_0402_1%

C1809
10U_0805_10V4Z

C

2
8152@ 0.1U_0402_16V4Z
2
8151@ 0_0402_5%

Place Close to Pin40
DCR< 0.15 ohm
Rate current > 1A

C1808
10U_0805_10V4Z

1
C1805
1
R1808

7
8

D

<33>
<33>
<33>
<33>
<33>
<33>
<33>
<33>

C1802
1U_0402_6.3V6K

LAN_XTALO
LAN_XTALI

--

AR8151 Pin23=LED2.
AR8152, Pin23 is CLKREQ

LAN_MIDI0LAN_MIDI0+
LAN_MIDI1LAN_MIDI1+
LAN_MIDI2LAN_MIDI2+
LAN_MIDI3LAN_MIDI3+

+1.7_LX

H

PD 5.1K

*

H:SWR Switch mode regulator Select *

LED2

LAN_ACT <33>
LAN_LINK# <33>

LAN_CLKREQ#
1
2
R1803 8152@ 0_0402_5%

LAN_RBIAS

L:Over Clock Disable

2
5.1K_0402_5%

C1807
0.1U_0402_16V4Z

28
27

8151-AL1A

REFCLK_N
REFCLK_P

2

25
26

Atheros

1
R1800

Chip Default

@
C1839
0.1U_0402_16V4Z

Note 2 : C1, C3, C5, C7 reserved for EMI.

A

A

Configure
R1808 C1805

Pin4
AR8152

VDDCT_REG

AR8151

CLKREQn

*
*

Configure
Pin23
CLKREQn

R1803

Issued Date

*

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Deciphered Date

2015/07/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LED[2]

Date:

5

4

3

2

SCHEMATIC,MB A8331
Document Number

Rev
B

4019H2
Wednesday, February 29, 2012

Sheet
1

32

of

52

5

4

3

2

1

D

D

LAN Connector

Timag only (Height)
T30

LAN_MIDI1+
LAN_MIDI1-

TD+
TDCT
NC
NC
CT
RD+
RD-

RJ45_MIDI0+
RJ45_MIDI0-

16
15
14
13
12
11
10
9

TX+
TXCT
NC
NC
CT
RX+
RX-

2
220P_0402_50V7K

1
C1533
JRJ45
9

Green LED+

2
1K_0402_5%
RJ45_MIDI0+

10

Green LED-

1

PR1+

RJ45_MIDI0-

2

PR1-

RJ45_MIDI1+

3

PR2+

RJ45_MIDI2+

4

PR3+

RJ45_MIDI2-

5

PR3-

RJ45_MIDI1-

6

PR2-

RJ45_MIDI3+

7

PR4+

RJ45_MIDI3-

8

PR4-

+3V_LAN
<32> LAN_LINK#

RJ45_MIDI1+
RJ45_MIDI1-

1

2

TAIMAG_HD-024A

1
R1215
C1534
68P_0402_50V8J
@

T31 8151@
16
15
14
13
12
11
10
9

Yellow LED+

12

Yellow LED-

1

40mil

CONN@
SANTA_130451-K
Part Number = DC234005010
PCB Footprint = SANTA_130451-K_12P

R04 modify for EMI
2
10P_0603_50V8-J
2
10P_1206_2KV8J

@

1 @

B

C24

JP5

2

L86

@ JP3
B88069X9231T203_4P5X3P2-2

C43

Place close to TCT pin

1

2

1

@ JP4
B88069X9231T203_4P5X3P2-2
2
1

.1U_0402_16V7K

2

10U_0603_6.3V6M

40mil

B88069X9231T203_4P5X3P2-2

RJ45_GND

1

LANGND
100UH_SSC0301101MCF_0.18A_20%

@ 1
C1538
1
C1537

2

RJ45_GND

1

2

2

2

1000P_0402_50V7K

2

.1U_0402_16V7K

2

1

@

2

C3

C4
1

C1838

1

@
1000P_0402_50V7K

2

C1837

C2

C1836

C1

C1835

C1834

1
.1U_0402_16V7K

2

1000P_0402_50V7K

2

.1U_0402_16V7K

2

1000P_0402_50V7K

.1U_0402_16V7K

1U_0402_6.3V6K

2

1

@

75_0402_1%

1

75_0402_1%

1

@

75_0402_1%

1

C1535
220P_0402_50V7K

14
13

C

11

2

75_0402_1%

1

R1218
1K_0402_5%
1
2

<32> LAN_ACT

8151@

+1.7_VDDCT_R

1
2
R1817
0_0603_5%

B

8151@

+1.7_VDDCT

RJ45_MIDI3+
RJ45_MIDI31 R4

TAIMAG_HD-024A

check value

1 R2

TX+
TXCT
NC
NC
CT
RX+
RX-

1 R3

LAN_MIDI3+
LAN_MIDI3-

TD+
TDCT
NC
NC
CT
RD+
RD-

1 R1

<32> LAN_MIDI3+
<32> LAN_MIDI3-

1
2
3
4
5
6
7
8

2

<32> LAN_MIDI2+
<32> LAN_MIDI2-

RJ45_MIDI2+
RJ45_MIDI2-

2

C

LAN_MIDI2+
LAN_MIDI2-

SHLD1
SHLD2

3

1
2
3
4
5
6
7
8

2

<32> LAN_MIDI1+
<32> LAN_MIDI1-

LAN_MIDI0+
LAN_MIDI0-

2
1

<32> LAN_MIDI0+
<32> LAN_MIDI0-

D42
AZ5125-02S.R7G_SOT23-3
SCA00001A00

R03 modify for ESD Pop

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Deciphered Date

2015/07/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

SCHEMATIC,MB A8331
Document Number

Rev
B

4019H2
Wednesday, February 29, 2012

Sheet
1

33

of

52

A

B

C

R04 Modify
R1009 0_0402_5%
1

@

2

R984 0_0402_5%
@
1
1
R991 0_0402_5%
2
RB751V-40_SOD323-2

2
2

<37> WLAN_PME#
<27,32,35> FCH_PCIE_WAKE#
<27> MINI1_CLKREQ#
1

<25> CLK_PCIE_MINI1#
<25> CLK_PCIE_MINI1

<6> PCIE_DTX_C_FRX_N1
<6> PCIE_DTX_C_FRX_P1
<6> PCIE_FTX_C_DRX_N1
<6> PCIE_FTX_C_DRX_P1

R04 Modify

+3VS_MINI1

R993 1
R995 1
R996 1
R997 1
R1017 1

<37> E51TXD_P80DATA
<37> E51RXD_P80CLK
<26> W_DISABLE#_2
<37> EC_BT_OFF#
2

@

D

E

TOP View - Right (Wireless LAN)
(STD H6.7 mm)

R04 Modify
+1.5VS_MINI1

JMINI1

WLAN_PME#_R1
3
5
1
7
D44 @
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
2 100K_0402_5%
47
0_0402_5%
E51TXD_P80DATA_R
2
49
E51RXD_P80CLK_R
2 0_0402_5%
51
2 1K_0402_5%
0_0402_5%
2
53

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GNDGND

54

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

40mil

+3VS_MINI1

20mil

R04 Modify

1

+1.5VS_MINI1

1

C1342

1

C1343

C1344

R04 Modify
2
1

@

R1016
R985 1

WL_OFF#_EC

2

0_0402_5%
2 0_0402_5%

4.7U_0603_6.3V6K

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

WL_OFF#_EC <37>

WL_OFF#
APU_PCIE_RST#

WL_OFF# <26>
APU_PCIE_RST# <13,25,31,32,35>

+3VS_MINI1

R04 Modify

R04 Modify
MINI1_SMBCLK
MINI1_SMBDAT

R988 1
R989 1

@
@

2 0_0402_5%
2 0_0402_5%

FCH_SCLK0
FCH_SDATA0

1

FCH_SCLK0 <11,12,27>
FCH_SDATA0 <11,12,27>

USB20_N8
USB20_P8

USB20_N8 <27>
USB20_P8 <27>
R992 2
R50 2

WIMAX_LED1#
MINI1_LED#_R

@

1 0_0402_5%
1 0_0402_5%

2
1
R994 100K_0402_5%

2

1
C1339
10U_0603_6.3V6M

R986
0_0805_5%
1
2

40mil
+3VS

2

C1341
1U_0402_6.3V6K

40mil

+1.5VS_MINI1

3

+3VALW

+3VS_MINI1

@ Q1901
AO3419L_SOT23-3
1
1

20mil

2

40mil

D

R987
0_0603_5%
2

S

1

+1.5VS

2

1
C1340
1U_0402_6.3V6K

+3VS_MINI1
MINI1_LED# <37>

R04 Modify

CONN@
ACES_51711-0520W-001
Part Number = SP07000PV00
PCB Footprint = ACES_51711-0520W-001_52P

For Combo Card BT Disable

R04 Modify

@

R990
470_0603_5%

2 0_0402_5%

<27> MINI2_CLKREQ#
<25> CLK_PCIE_MINI2#
<25> CLK_PCIE_MINI2

<6> PCIE_DTX_C_FRX_N2
<6> PCIE_DTX_C_FRX_P2
<6> PCIE_FTX_C_DRX_N2
<6> PCIE_FTX_C_DRX_P2
+3VS

E51TXD_P80DATA_R
E51RXD_P80CLK_R

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

GND1

4

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2

54

C1366
0.1U_0402_16V4Z

+1.5VS

R999 2

@

1 0_0402_5%

R1000 1
R1001 1

@
@

2 0_0603_5%
2 0_0603_5%

MINI2_SMBCLK
MINI2_SMBDAT

R1002 1
R1003 1

@
@

2 0_0402_5%
2 0_0402_5%

R1006 2

@

1 0_0402_5%

WL_OFF#_2
APU_PCIE_RST#

2

2

3

WL_OFF#_2 <26>

FCH_SCLK0
FCH_SDATA0

+1.5VS
USB20_N9 <27>
USB20_P9 <27>

MINI1_LED#
1
R1007

@

1

2

+3VS

@
C1336
4.7U_0603_6.3V6K

1

2

@
C1337
0.1U_0402_16V4Z

1

2

@
C1338
0.1U_0402_16V4Z

1

2

@
C1333
10U_0603_6.3V6M

1

2

1

@
C1334
1U_0402_6.3V6K

2

@
C1335
1U_0402_6.3V6K

2
+3VS
100K_0402_5%
4

(9~16mA)

CONN@
BELLW_80003-1021
Part number = SP07000JZ00
PCB Footprint = BELLW_80003-1021_52P

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Deciphered Date

2015/07/08

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

3VSWLAN_GATE

Q1902B
DMN66D0LDW-7_SOT363-6

+3VS
+3VALW

USB20_N9
USB20_P9
WIMAX_LED2#
MINI1_LED#

5

2

1

+3VS

+3VS_MINI2

2

3

6
<37> WLAN_PWR_ON

3VSWLAN_R

1

Q1902A
DMN66D0LDW-7_SOT363-6

4

@

R1008
1K_0402_5%
1
2

1

R998 1

FCH_PCIE_WAKE#

2 3VSWLAN_GATE
R1004
1K_0402_5%

0.1U_0402_16V4Z

JMINI2

3

1

C1355

TOP View - Left (Option)
(STD H5.7mm)

1
23VSWLAN_GATE_R
R1005
100K_0402_5%

2

G

+3VALW

B

C

D

Document Number

Rev
B

4019H2
Wednesday, February 29, 2012

Sheet
E

34

of

52

4

3

2

1

U58 FL@

1 C1907
0.1U_0402_10V7K
FL@

82mA A17
A22
A60
B7

AVCC10X
AVCC10X
AVCC10X
AVCC10X

+1.05V_USB3.0

2

2

2

FL@ 2 0_0402_5%

R1920

1

FL@ 2 0_0402_5%

2

+V2.5_IN_3

1

2

1

2

2

C1939
FL@
0.1U_0402_10V7K

C1938
FL@
1U_0402_6.3V6K

2

A1
A20
A54
B10

PGND
PGND
PGND
PGND

A44
B12
B38

DVCC33X
DVCC33X
DVCC33X

A26
B25
B30

DVCC33
DVCC33
DVCC33

SSRXP1
SSRXM1

A9
A10

U3RXDP1_L
U3RXDN1_L

UREF1
UCAP1
UV1281
PPWR1
OVCN1

B4
A6
B5
A48
A46

UREF1
UCAP1
V1281

XCKSEL0
XCKSEL1

A51
B41

XCK

A52

XSCI

B43

2 10K_0402_5%

+3V_USB3.0

R03 modify BOM
C1911 for reduce +1.5v noise

U2DP1 <36>
U2DN1 <36>
FL@ C1908
FL@C1908
FL@C1909
FL@
C1909

1
1

0.1U_0402_10V7K
0.1U_0402_10V7K

2
2

+5VALW

USB30TXP <27,36>
USB30TXN <27,36>
U3RXDP1_L <36>
U3RXDN1_L <36>

FL@ R1911
FL@R1911
FL@C1912
FL@
C1912
FL@C1914
FL@
C1914

1
1
1

2 12.1K_0402_1%
2200P_0402_50V7K
4.7U_0603_6.3V6K

2
2

USB_OC_FL#

GND
RT9701-PB_SOT23-5

1

2

Close to Chip

+1.05V_USB3.0

U59 FL@
APL5930KAI-TRG_SO8

1

2

+5VALW
+1.5V

6
5
9

VCNTL
VIN
VIN

+1.05V_USB3.0_EN
1
2
+5VALW
FL@ R1909
5.1K_0402_1%

8
7

EN
POK

VOUT
VOUT

3
4

FB

2

FL@R1910
FL@
R1910
10K_0402_5%
1
2
R1912
FL@
32.4K_0402_1%

2

USB_OC_FL# <36>

1
2
C1918
FL@
22P_0402_50V8J

3

XSCI

X6
FL@

R1915
1M_0402_5%

3
GND

PU at
Power MOS side

SYSON
R1914

XSCO

A53

1

12MHZ_12PF_7V12000011
4

1

2

+1.05V_USB3.0_EN
2
10K_0402_5%
1
FL@
C1923
0.1U_0402_10V7K
2

FL@

D

+1.5V to +1.05V Transfer

+1.5V

@

C

GND

Vout=0.8(1+10K/32.4K)
1.042 ~ 1.0469 ~ 1.0519V
Spec: 0.9975 ~ 1.05
~ 1.1025

2

1
FL@R1916
FL@
R1916
1
1
2
0_0402_5%

XSCO

PPWRCTL

B34

AUXDET
OD pin
WAKE#
OD pin CLKREQ#
OD pin
SMIN

A39
A14
A15
B28

USB30_CLKREQ#_L
SMIN

ROMSDA
ROMSCL
ROMPRES

B27
A35
A33

ROMSDA
ROMSCL
ROMPRES

U2LNKN
PCIELNKN
SSLNKN
DATTXN
DATRXN

B22
B21
A27
A28
B24

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

A2
A29
A30
A31
A32
A34
A37
A38
A40
A43
A45
A47
A49
A63
A64
B1
B29
B31
B33
B35
B36

TESTN

B37

FL@ R1917
FL@R1917
FL@R1918
FL@
R1918

FL@ C1928
FL@C1928
22P_0402_50V8J
1
2

1
1

2 4.7K_0402_5%
2 0_0402_5%

+3V_USB3.0
FCH_PCIE_WAKE#

FCH:WAKE#/GEVENT8#
<27,32,34>

(S5)
PU 10k to +3VALW at FCH side
+3V_USB3.0

2

1

2

23mA A11
A13
B40
B42
B52

DVCC10X
DVCC10X
DVCC10X
DVCC10X
DVCC10X

71mA A16
A25
A36
A41
A42
B23
B26
B32

DVCC10
DVCC10
DVCC10
DVCC10
DVCC10
DVCC10
DVCC10
DVCC10

A65

DGND

Digital Core power

C1941
FL@
0.1U_0402_10V7K

C1940
FL@
1U_0402_6.3V6K

2

PVCC25X
PVCC25X
PVCC25X

1

+1.05V_USB3.0

1

A5
A21
B46

Digital IO power

6mA

1

PVCC25OX

1

+3V_USB3.0

B

100mA B11

+V2.5_IN_1
C1934
FL@
0.1U_0402_10V7K

1

C1933
FL@
1000P_0402_50V7K

R1919

2

U3TX_DP1
U3TX_DN1

1

2

Close to Chip

T34
T33
@R1921
@
R1921

1

2 4.7K_0402_5%

+3VS

+3V_USB3.0

FL@
R1928
10K_0402_5%

FL@
Q1900B
DMN66D0LDW-7_SOT363-6

2

1

C1932
FL@
4.7U_0603_6.3V6K

2

C1931
FL@
1000P_0402_50V7K

C1930
FL@
0.1U_0402_10V7K

C1929
FL@
4.7U_0603_6.3V6K

1

AGND10
AGND10
AGND10
AGND10
AGND10
AGND10

FL1009

internal power

+V2.5_OUT

AVCC10

A19
A61
A62
B8
B9
B20

1

A7
A8

FL@R1903
FL@
R1903

2
2

2 12.1K_0402_1%
2200P_0402_50V7K
4.7U_0603_6.3V6K

USB30_CLKREQ#_L

3

4

CLKREQ# (A15),output,OD
Fresco suggest 10kohm pull up

USB30_CLKREQ# <25>

FCH:LDRQ1#/CLK_REQ6#/GPIO49 (S0)

B

+3V_USB3.0

R1929
@
4.7K_0402_5%
SMIN

2

2

1

C1927
FL@
1000P_0402_50V7K

C

1

C1926
FL@
0.1U_0402_10V7K

C1925
FL@
1U_0402_6.3V6K

C1924
FL@
10U_0603_6.3V6M

1

36mA B14

SSTXP1
SSTXM1

1
1
1

1
5

1

1

1

U2DP1
U2DN1

FL@ R1906
FL@R1906
FL@C1902
FL@
C1902
FL@C1905
FL@
C1905

VIN
VOUT
VIN/CE VOUT

FL@
Q1900A
DMN66D0LDW-7_SOT363-6

2

2

2

C1922
FL@
1000P_0402_50V7K

2

1

C1921
FL@
0.1U_0402_10V7K

1

2

C1920
FL@
1U_0402_6.3V6K

C1919
FL@
10U_0603_6.3V6M

1

B2
B3

Crystal

20mil

1

EEPROM

2

U2DP1
U2DM1

<29,37,40,48> SYSON
UREF0
UCAP0
V1280

+3V_USB3.0

U57 FL@

3
4

SYSON

C1915
FL@
10U_0603_6.3V6M

PVCC33X

Analog 1.05V power

C1917
FL@
1000P_0402_50V7K

C1916
FL@
0.1U_0402_10V7K

C1913
FL@
10U_0603_6.3V6M

2

2

73mA A12

+1.05V_USB3.0

1

1

AGND33
AGND33
AGND33
AGND33

A57
B47
A58
A50
B39

+3VALW

C1911
10U_0603_6.3V6M

PVCC33X

1
2
FL@ R1908
0_0603_5%

A3
A59
B6
B44

B50
B51

UREF0
UCAP0
UV1280
PPWR0
OVCN0

C1910
FL@
1U_0402_6.3V6K

2

AVCC33X
AVCC33X

SSRXP0
SSRXM0

+3VALW to +3V Transfer

1

C1906 1
1U_0402_6.3V6K
FL@

USB30_RST#
2
@ 10P_0402_50V8J

A4
B45

40mA V1281

2
0_0402_5%
2
0_0402_5%

GND

93mA

+3V_USB3.0

PCIEREXT
PCIECAP

B48
B49

1
R1902 FL@
1
R1905 FL@

1

A18
B19

SSTXP0
SSTXM0

40mA V1280

1

PCIERXP
PCIERXM

2 12.1K_0402_1% PCIEREXT
2 0.1U_0402_10V7K PCIERCAP

2

+3V_USB3.0

PCIE_MTX_C_DRX_P0B15
PCIE_MTX_C_DRX_N0B16

Analog 3.3V power

1
C1904

PCIETXP
PCIETXM

A55
A56

1

ESD request

A23
A24

+1.05V_USB3.0

U2DP0
U2DM0

2

R1907 1
C1903 1

PCIECKP
PCIECKM

1

6

SMIB <27>

FCH:BLINK/USB_OC7#/GEVENT18# (S5)

+3V_USB3.0

SMIN(B28)
output pin,GPIO,
internal 75kohm pull-up

1

FL@
FL@

PERST#

B17
B18

2 0.1U_0402_10V7K PCIE_DTX_MRX_P0
2 0.1U_0402_10V7K PCIE_DTX_MRX_N0

<25> PCIE_MTX_C_DRX_P0
<25> PCIE_MTX_C_DRX_N0
D

B13

CLK_PCIE_USB30
CLK_PCIE_USB30#

FL@
4.7K_0402_5%
R1925

2

1
1

USB30_RST#

Super speed USB Port 0

<25> PCIE_DTX_C_MRX_P0
<25> PCIE_DTX_C_MRX_N0

C1900
C1901

2 0_0402_5%
2 0_0402_5%

PCI Express

FL@
FL@

R1900 1
R1901 1

Super speed USB Port 1

FL@
@

<27> FCH_PCIE_RST#
<13,25,31,32,34> APU_PCIE_RST#
<25> CLK_PCIE_USB30
<25> CLK_PCIE_USB30#

5

5

FLTESTN

FL1009-2Q0_DRQFN116_9X9
Part Number = SA00004T700
S IC FL1009-2Q0 DRQFN 116P D-USB3.0 CONT

Fresco USB3.0 Power Down Sequence

Fresco USB3.0 Power Up Sequence

A

A

3.3V Should be power down before 1.05V

at least 1ms

+3V_USB3.0
+3V_USB3.0

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

+1.05V_USB3.0

2011/07/08

Deciphered Date

2015/07/08

Title

SCHEMATIC,MB A8331
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size

+1.05V_USB3.0

Date:

5

Document Number

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

Rev
B

4019H2
Wednesday, February 29, 2012
1

Sheet

35

of

52

5

4

3

2

1

For ESD request
R1224

@

1

0_0402_5%

2

USB30TXN
USB30TXP

From FCH
D

<27> USB30_MRX_DTX_N0
<27> USB30_MRX_DTX_P0
<27> USB30_P10
<27> USB30_N10

R1237
R1236

1 M3@
1 M3@

2 0_0402_5%
2 0_0402_5%

USB30RXN
USB30RXP

R1235
R1232

1 M3@
1 M3@

2 0_0402_5%
2 0_0402_5%

USB20P
USB20N

4
L88 1
R1225
R1226

USB30RXN
USB30RXP

4

3

1

2

OCE2012120YZF_4P
USB30TXP_L
2

1

@

2

0_0402_5%

1

@

2

0_0402_5%

4

4

3

L89 1

1

2

R1228

USB30TXN_L

3

@

1

109

USB30TXP_L

USB30TXN_L2 2

98

USB30TXN_L

USB30RXP_L4 4

77

USB30RXP_L

USB30RXN_L5 5

66

USB30RXN_L

3 3

USB30RXN_L

3

OCE2012120YZF_4P
USB30RXP_L
2

R971
R1238
R1239

1 FL@
1 FL@

R1234
R1233

<35> U2DP1
<35> U2DN1

1 FL@
1 FL@

2 0_0402_5%
2 0_0402_5%

USB30RXN
USB30RXP

2 0_0402_5%
2 0_0402_5%

USB20P

USB20P
USB20N

1

@

1

USB30TXP_L
D4

1

2

4

3

L64
USB20N

4
R974

@

1

2

4

0_0402_5%

2

2
D

JUSB1
ACON TARAC-9V1391 9P USB3.0 H0.4

YSCLAMP0524P_SLP2510P8-10-9

From Fresco
<35> U3RXDN1_L
<35> U3RXDP1_L

2

1

8

9
1
8
3
7
2
6
4
5

0_0402_5%

2

1

+

C1571
470P_0402_50V7K

USB30TXN
USB30TXP

C1572
220U_6.3V_M

D43 @
USB30TXP_L1 1

Usb Cap for BOM select
<27,35> USB30TXN
<27,35> USB30TXP

+USB3_VCCA

I/O3

I/O1

1

USB30TXN_L
USB20P_L

USB20N_L

USB20N_L
USB30RXP_L

USB20P_L

2

OCE2012120YZF_4P
USB20N_L
3
0_0402_5%

+USB3_VCCA

USB20P_L

5

VDD

GND

2

6

I/O4

I/O2

3

USB30RXN_L

SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-

10
11
12
13

GND
GND
GND
GND

CONN@
Part Number = DC23300AG00
PCB Footprint = ACON_TARA4-9K1311_9P

60mils

.
n
n
o
C
f
i
Z
B
/
0
3
B
S
U
n
i
P
0
3
<40> SYSON#

+5VALW
B

SYSON#
GND
GND

13
14

ACES_85201-1205N

<27> USB_OC1#
<27> USB30_MRX_DTX_N2
<27> USB30_MRX_DTX_P2
<27> USB30_MTX_DRX_N2
<27> USB30_MTX_DRX_P2
USB20_P1_R
USB20_N1_R

<27> USB30_MTX_DRX_N1
<27> USB30_MTX_DRX_P1

+3VALW

USB_OC_FL# <35>

C1320
0.1U_0402_16V4Z

+3VS

1
C1326
0.1U_0402_16V4Z

C1327
1U_0402_6.3V6K

Bluetooth Conn.

2

<26> BT_ON#

1
2
R982 10K_0402_5%
C1330
0.1U_0402_16V4Z

GND2

32

GND1

31

JBT1

AP2301GN-HF_SOT23-3
Q42

10

W=40mils
+BT_VCC

1

2

B

+BT_VCC

2

C1332
0.1U_0402_16V4Z

<27> USB30_MRX_DTX_N1
<27> USB30_MRX_DTX_P1

USB_OC0# <27>

FL@ 2 0_0402_5%

2

C1331
4.7U_0603_6.3V6K

USB20_P0_R
USB20_N0_R

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

M3@ 2 0_0402_5%

R59 1

1

SYSON#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

+5VALW

R60 1

R983
300_0603_5%

9

GND 8
7
6
5
4
3
2
GND 1

8
7
6
5
4
3
2
1

USB20_P7 <27>
USB20_N7 <27>

ACES_87213-0800G
CONN@
Part Number = SP02000CZ00
PCB Footprint = ACES_87213-0800G_8P

1

USB20_N1
USB20_P1

1
2
3
4
5
6
7
8
9
10
11
12

1
2
R969
10K_0402_5% 1

3

USB20_N0
USB20_P0

1

JUSB2
CONN@
1
2
3
4
5
6
7
8
9
10
11
12

C

R965
100K_0402_5%

9

JUSB3
CONN@

U54
AP2301MPG-13_MSOP8
GND
VOUT 8
VIN
VOUT 7
VIN
VOUT 6
EN
FLG 5

2

n
n
o
C
B
/
0
2
B
S
U
n
i
P
2
1

1
2
3
4

+3VALW

60mils

EPAD

C22
10U_0805_10V4Z
1
2

+USB3_VCCA

2

+5VALW
C

1

AZC099-04S.R7G_SOT23-6
SC300001G00

D

A

<27> USB20_N1
<27> USB20_P1

R29
R31

1
1

@
@

2 0_0402_5%
2 0_0402_5%

USB20_N0_R
USB20_P0_R

R32
R51

1
1

@
@

2 0_0402_5%
2 0_0402_5%

USB20_N1_R
USB20_P1_R

2

ACES_87152-30051
Part Number = SP010015Z00
PCB Footprint = ACES_87152-30051_30P-S

G
S

Q43
2N7002K_SOT23-3

3

<27> USB20_N0
<27> USB20_P0

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Deciphered Date

2015/07/08

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Document Number

Rev
B

4019H2
Wednesday, February 29, 2012

Sheet
1

36

of

52

4

3

2

1

Analog Project ID definition

+3VALW

Analog Board ID definition

ECAGND

<25,28> LPC_CLK0_EC
+3VALW

2
R1011
2
C1353

<10,25> PLT_RST#

1
47K_0402_5%
1
0.1U_0402_16V4Z

<27> EC_SCI#
<34> WLAN_PWR_ON

LPC_CLK0_EC
PLT_RST#
EC_RST#
EC_SCI#
1
2
R1015
0_0402_5%

12
13
37
20
38

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

77
78
79
80

EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47

BATT_TEMP/AD0/GPIO38
AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
IMON/AD5/GPIO43

63
64
65
66
75
76

KSI[0..7] <38>

<43,44>
<43,44>
<8,14,21>
<8,14,21>

<27> SLP_S3#
<27> SLP_S5#
<27> EC_SMI#
<20> INT_VGAPWR_ON
<34> MINI1_LED#
<32> LAN_PWR_EN#
R04 Modify
<34> WL_OFF#_EC
<22> EC_INVT_PWM
<30> FAN_SPEED1
<32> EC_PME#
<34> E51TXD_P80DATA
<34> E51RXD_P80CLK
FCH_PWRGD 1 9012@ 2
R1058 0_0402_5%
<38> PWR_SUSP_LED#
<38> WLAN_LED#

Delay EC_PWROK 50ms
for VGA criterial

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00

97
98
99
109

VGATE

VGATE <50>

VLDT_EN
9012_PH1

VLDT_EN <40,47>
9012_PH1 <44>

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

119
120
126
128

EC_SI_SPI_SO
EC_SO_SPI_SI
EC_SPICLK_L
EC_SPICS#/FSEL#

ENBKL/AD6/GPIO40
PECI_KB930/AD7/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

73
74
89
90
91
92
93
95
121
127

ENBKL

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11

100
101
102
103
104
105
106
107
108

EC_RSMRST#
EC_LID_OUT#
9012_VCIN
EC_THERM
GPXO07
BKOFF#
PBTN_OUT#

AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07

110
112
114
115
116
117
118

ACIN
EC_ON
ON/OFF
LID_SW#
SUSP#

C1358
9012@
KB9012QF-A3_LQFP128_14X14
Part Number = SA00004OB20

22P_0402_50V8J

2

1

@

XCLKI/GPIO5D
XCLKO/GPIO5E

V18R

124

A

EN_DFAN1

2
1 9012@ 2
R66
1 930@ 2
0_0402_5%
R67

2
2.2K_0402_5%
EC_SMB_DA1
2
2.2K_0402_5%

EN_DFAN1 <30>

KSO1
EC_MUTE# <39>
EAPD <39>
TL_CLK <21>
TL_DATA <21>
TP_CLK <38>
TP_DATA <38>

SPI Device Interface
SPI Flash ROM

GPIO

GPIO

D

0.1U_0402_16V4Z

0_0402_5%
+EC_VCC_VL

1
R1027
1
R1028
@

2
47K_0402_5%
2
47K_0402_5%
1
100K_0402_5%
2
10K_0402_5%
1
100K_0402_5%

KSO2
LID_SW#
EC_PME#
ENBKL

Bus

C1356

ECAGND

R04 Modify
Remove C1361,C1362

EC_MUTE#
EAPD
TL_CLK
TL_DATA
TP_CLK
TP_DATA

@

2
2.2K_0402_5%
2
2.2K_0402_5%
EC_SMB_DA2
2
2.2K_0402_5%
2
2.2K_0402_5%
EC_SMB_CK2

EC_SI_SPI_SO <38>
EC_SO_SPI_SI <38>
EC_SPICS#/FSEL# <38>

TP_CLK

ENBKL <10>

FSTCHG
BATT_BLUE_LED#
BATT_AMB_LED#
PWR_LED
SYSON
VR_ON

BATT_AMB_LED# <38>
PWR_LED <38>
SYSON <29,35,40,48>
VR_ON <50>

@

2
100K_0402_5%

BATT_TEMP

2
100P_0402_50V8J
2
100P_0402_50V8J

+3VLP
+3VALW
+3VALW

1
R1029
1
R1030
2
R1031
1
R1032
2
R1034

1
R1020
1
R1021
1
R1022
1
R1023
1
R1018
1
R1019

VR_ON

ACIN
EC_RSMRST# <27>
EC_LID_OUT# <27>
9012_VCIN <44>

@

2
4.7K_0402_5%
2
4.7K_0402_5%

TP_DATA

FSTCHG <43>
BATT_BLUE_LED# <38>

C

+3VALW
+3VS

+3VALW

+5VS

1
R1012
1
C1360
1
C1363

B

Reserve for EMI, close to EC
EC_SPICLK <38>

BKOFF# <22> Delay
PBTN_OUT# <27>

VGA_ON

EC_SPICLK_L 1
R1033
10_0402_5%

SUSP# 10ms

2
1
2
C1357
10P_0402_50V8J

VGA_ON <20>
GPXO07

GND/GND
GND/GND
GND/GND
GND/GND
GND0

2

122
123

1

ADP_I <43,44>

83
84
85
86
87
88

PS2 Interface

11
24
35
94
113

1
R1037
100K_0402_5%

EC_CRY1
2 EC_CRY2
0_0402_5%

ADP_I
AD_BID0
AD_PID0

2
BATT_TEMP <44>

EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F

T27
1
R1036

<25,28> RTC_CLK

.01U_0402_16V7K

BATT_TEMP

68
70
71
72

B

SLP_S3#
SLP_S5#
EC_SMI#
INT_VGAPWR_ON
MINI1_LED#
LAN_PWR_EN#
WL_OFF#_EC
EC_INVT_PWM
FAN_SPEED1
EC_PME#
E51TXD_P80DATA
E51RXD_P80CLK
GPIO18
PWR_SUSP_LED#
WLAN_LED#

WLAN_PME#
ACOFF

DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

DA Output

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

2

EC_BT_OFF# <34>
BEEP# <39>
WLAN_PME# <34>
ACOFF <41>
C1354

AGND/AGND

KSO[0..17] <38>

KSI[0..7]

33K_0402_5%

EC_SMB_CK1

69

KSO[0..17]

1

R1026

Rb

0.1U_0402_16V4Z

R04 modify BID=03 for PVT
21
23
26
27

PWM Output
AD

AD_BID0

R04 Modify
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13

R04 Modify

C

2

C1364

2
EC_VDD/AVCC

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0

67

9
22
33
96
111
125

1
2
3
4
5
7
8
10

1

1

1 930@ 2
0_0402_5%
R64
@
1
2
0_0402_5%
R65

ACIN <40,42,43>
EC_ON <38,42>
ON/OFF <38>
LID_SW# <38>
SUSP# <40,43,48>

FCH_PWRGD <27>
MAINPWON <8,42,44>

EC_THERM# <8,25,44,50>
1

C1352
R1014
22P_0402_50V8J 22_0402_5%
2
1
2
1

EC_GA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

AD_PID0
@
R1035
100K_0402_5%

Rb

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

<27> EC_GA20
<27> EC_KBRST#
<25> SERIRQ
<25> LPC_FRAME#
<25> LPC_AD3
<25> LPC_AD2
<25> LPC_AD1
<25> LPC_AD0

R1024
100K_0402_5%

Ra

1

2

D

U31

@
R1025
100K_0402_5%

1

2

+EC_VCC_VL

1

Ra
1

1

C1351
0.1U_0402_16V4Z

1

2

1000P_0402_50V7K

2

1000P_0402_50V7K

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

+3VALW
2

+3VALW
L65
+EC_VCCA
1
2
BLM18AG601SN1D_2P

C1345 C1346 C1347 C1348 C1349 C1350
1
1
1
1
2
2

C1359

Low Active (+1.5V)
D

2

EC_THERM 2

4.7U_0603_6.3V6K

G

20mil

S

High Active

ECAGND 2

Q30
2N7002K_SOT23-3

3

5

A

1
L66
BLM18AG601SN1D_2P

2011/07/08

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2015/07/08

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

5

4

3

2

Sheet

Wednesday, February 29, 2012
1

37

of

52

.
n
n
o
C
P
T

B
/
R
E
W
O
P

2
1

1

JPWR1

D26
2

ON/OFF <37>

3

51ON# <41>

1
BAV70W_SOT323-3
930@

1

ACES_FAN10-08203-9800
PCB Footprint = ACES_FAN10-08203-9800_8P-T
ACES_85201-0605N
Part Number = SP01000LB00

ACES_85201-0805N
CONN@
Part Number = SP01000H200
PCB Footprint = ACES_85201-0805N_8P

D
EC_ON

2
2

G

2

RIGHT_BTN#

930@
Q44
2N7002K_SOT23-3

LEFT_BTN#

SW3
EVQPLHA15_4P
3
1

RIGHT_BTN#

2

4

2

1

5
6

3

4

SW4
EVQPLHA15_4P
3
1

1

S
930@
R1043
10K_0402_5%

2

2

1

Power/SUS

LED Status
KSI[0..7]

ON

Battery
Full

ACIN

KSO7

C1381 1

2

100P_0402_50V8J

KSO6

C1382 1

2

100P_0402_50V8J

KSO5

C1385 1

2

100P_0402_50V8J

KSO4

C1387 1

2

100P_0402_50V8J

KSO0

C1397 1

2

100P_0402_50V8J

KSI5

C1399 1

2

100P_0402_50V8J

KSI6

C1401 1

2

100P_0402_50V8J

KSI7

C1403 1

2

100P_0402_50V8J

removed

PWR_LED#

LED5
LTST-C191TBKT-CA_BLUE
+3VALW

1
2
R374
51_0402_5%

2

B

1

1

100P_0402_50V8J

PWR_LED#

D

1
2
R378
390_0402_5%

2

A

1

2

<37> PWR_LED

LED1
LTST-C191KFKT-2CA_ORANGE

S

PWR_SUSP_LED#

R1063
100K_0402_5%

PWR_SUSP_LED# <37>

+3VALW

1
2
R379
51_0402_5%

2

B

1

BATT_BLUE_LED#

BATT_BLUE_LED# <37>
+3VS

C1396 1

2 100P_0402_50V8J

KSO14

C1383 1

2

100P_0402_50V8J

KSO9

C1398 1

2 100P_0402_50V8J

KSO13

C1384 1

2

100P_0402_50V8J

KSI3

C1400 1

2 100P_0402_50V8J

2

100P_0402_50V8J

KSO8

C1402 1

2 100P_0402_50V8J

C1388 1

2

100P_0402_50V8J

KSO3

C1389 1

2

100P_0402_50V8J

KSO11

C1390 1

2

100P_0402_50V8J

KSI4

C1391 1

2

100P_0402_50V8J

KSO10

C1392 1

2

100P_0402_50V8J

KSO2

C1393 1

2

100P_0402_50V8J

KSI1

C1394 1

2

100P_0402_50V8J

KSO1

C1395 1

2

100P_0402_50V8J

1
2
R376
390_0402_5%
+3VALW
+3VS

@
1
2
R381
390_0402_5%
1
2
R377
390_0402_5%

2

A

1

2

BATT_AMB_LED#

BATT_AMB_LED# <37>

R1060
10K_0402_5%

LED4
LTST-C191KFKT-2CA_ORANGE
2

A

1

WLAN_LED#

5

KSI2

+3VS

MEDIA_LED#

WLAN_LED# <37>

4

U34
B

2

5IN1_LED# <31>

A

1

SATA_LED# <26>

Y
3

100P_0402_50V8J

Q48
2N7002K_SOT23-3

LED6
LTST-C191TBKT-CA_BLUE

LED2
LTST-C191KFKT-2CA_ORANGE

2

G

1

100P_0402_50V8J

2

Amber

2

2

C1379 1

C1380 1

KSI0

BlueTooth

WLAN

1

C1378 1

KSO17

KSO15

C1386 1

3G

P

KSO16

CONN@
PCB Footprint = ACES_85201-26051_26P
ACES_85201-26051 Part Number = SP01000GE00

KSO12

3G / WLAN

Charge

NEW70/80/90 Blue Amber Blue Amber

KSO[0..17] <37>

+3VALW

27
28

SUS

KSI[0..7] <37>

KSO[0..17]

G1
G2

D27 @
AZ5125-02S.R7G_SOT23-3

G

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

D29 @
AZ5125-02S.R7G_SOT23-3

D
E
L

.
n
n
o
C
B
K
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

TP_DATA

Part Number = SCA00001A00
PCB Footprint = AZ5125-02SPR7G_SOT23-3

JKB1
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

TP_CLK

3

2

<37,42> EC_ON

1

LEFT_BTN#

1

@
R1061
0_0603_5%

930@
C1365
1000P_0402_50V7K

FCH_SDATA1 <27>

2

1

ON/OFF

FCH_SDATA1

1 C1371
0.1U_0402_16V4Z

3

2

+3VS

1

R04 modify

PWR_LED#
ON/OFFBTN#

+5VS
TP_CLK <37>
TP_DATA <37>

2

ON/OFFBTN#

+3VALW
LID_SW# <37>

LID_SW#

+3VS

FCH_SCLK1 <27>

C1377
220P_0402_50V7K

1
0_0402_5%

1
2
3
4
5
6
7
8
9
10

FCH_SCLK1
TP_VDD
TP_CLK
TP_DATA
LEFT_BTN#
RIGHT_BTN#

1
2
3
4
5
6
7
8
9
10

C1376
220P_0402_50V7K

2
9012@ R1056

1
2
3
4
5
6
7
8
GND
GND

1
2
3
4
5
6
7
8
GND
GND

+5VS

3

2
9012@
R56
100K_0402_5%

2
1
R1059 0_0402_5%
@
2
1
R1057 0_0402_5%

TP_VDD

CONN@
JTP1

930@
R1040
100K_0402_5%

5
6

n
o
t
t
u
B
r
e
w
o
P

+3VALW

+3VLP

NC7SZ08P5X_NL_SC70-5

LED7
+3VS

1
2
R380
130_0402_5%

2

B

1

MEDIA_LED#

LTST-C191TBKT-CA_BLUE
LED3
2

B

1

LTST-C191TBKT-CA_BLUE

R04 Modify LED Vender to LITE-ON
Change R follow Q5WVH

EC BIOS ROM

930@
+3VALW

1
R1049

2
0_0603_5%

930@
C1370 1
2 0.1U_0402_16V4Z
+SPI_VCC
2 930@ 1
R1055
10_0402_5%

U42 930@
<37> EC_SPICS#/FSEL#
+3VALW

EC_SPICS#/FSEL#
R1050 1 930@ 2 4.7K_0402_5%
R1052 1 930@ 2 4.7K_0402_5%

1
EC_SPI_WP# 3
EC_SPI_HOLD#7
4

CE#
WP#
HOLD#
VSS

VDD
SCK
SI
SO

8
6
5
2

EC_SPICLK_R
EC_SO_SPI_SI_R
EC_SI_SPI_SO_R

R1051 1 930@
R1053 1 930@
R1054 1 930@

930@
C1374 22P_0402_50V8J
2
1

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

EC_SPICLK <37>
EC_SO_SPI_SI <37>
EC_SI_SPI_SO <37>

MX25L1005AMC-12G_SO8

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Deciphered Date

2015/07/08

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Document Number

Rev
B

4019H2
Wednesday, February 29, 2012

Sheet

38

of

52

5

4

3

2

1

+VDDA

4

1

1

3

1
2
560_0402_5%

Combo MIC

MIC2_L

CBP

+MIC2_VREFO

External MIC

+MIC1_VREFO

MIC2_R

SPK_OUT_L-

SPKL-

LINE1_L

SPK_OUT_R+

45

SPKR+

SPK_OUT_R-

44

SPKR-

HPOUT_L

32

24

LINE1_R
MIC1_L

22

MIC1_R

35

CBN

36

CBP

29

MIC2_VREFO

HPOUT_R

33

SDATA_IN

8

SDATA_OUT

5

10mil

30

MIC1_VREFO_R

31

MIC1_VREFO_L

SYNC

10

RESET#

11

BCLK

10mil

HP_PLUG#

1

2 2.2U_0603_6.3V4Z

SENSE_A
2 20K_0402_1% SENSE_B
EAPD_R
2 0_0402_5%

19

LDD_CAP

1

@
R1107
0_0402_5%

10mil

CPVEE

13
18
47

SENSE A
SENSE B
EAPD

48

2

GPIO1/DMIC_CLK

3

PD#

4

PCBEEP
MONO_OUT
AVSS2

10mil

12

VREF

HDA_SDOUT_AUDIO
HDA_SYNC_AUDIO

<27>

7

DVSS

49

GND

AVSS1
PVSS2
PVSS1

26
43
42

3
1

1

2
1

2

2

3

HDA_BITCLK_AUDIO

4
MIC_PLUG# 5
6

D40
AZ5125-02S.R7G_SOT23-3
Part Number = SCA00001A00

R02 modify 0926 for ESD

<27>

B

HDA_RST_AUDIO# <27>
<27>

R1133
0_0402_5%
281@ 2
1

EAPD_R

+MIC2_VREFO
COM_MIC

2
22P_0402_50V8J
MIC2JD

R1088
2.2K_0402_5%

D
Q50
271@
BSH111_SOT23-3
S

EC_MUTE# <37>

R1089
1
2
22K_0402_5%

2
G
C1437
10U_0805_10V4Z

1

COM_MIC
R52
22K_0402_5%

D41
AZ5125-02S.R7G_SOT23-3
SCA00001A00

R02 modify 0926 for ESD

2

MONO_IN

C1439
CODEC_VREF

SPDIFO

MIC1_R_R

HDA_SDIN0 <27>

20
37
27

MIC1_L_R

2

2
33_0402_5%

6

GPIO0/DMIC_DATA
JDREF

34

2

HP_RIGHT
1
R1086

@
1
2
1
R1087 0_0402_5% C1435

10mil

2

<37> EAPD

C1438
1
R1091
39.2K_0402_1%
MIC_PLUG#
2
1
MIC2JD
R1092
20K_0402_1% R1093 1 271@
R1094 1 271@
2

1
20K_0402_1%

28

L72 1
2
FBMA-L11-160808-700LMT_2P
L73 1
2
FBMA-L11-160808-700LMT_2P

SM010004010 300ma 70ohm@100mhz DCR 0.3 1

HP_LEFT

JMIC1
CONN@
HONGLIN 13-18200601CP 3.6D 6P AUDIO
Part Number = DC230007R00
PCB Footprint = SUYIN_010030HR006G132ZL_6P
1
2

R1085
4.7K_0402_5%

2

2
R1090

10U_0805_10V4Z
2

2 MIC1_L_1
1K_0603_5%
2 MIC1_R_1
1K_0603_5%

1

C1436
1

R1081
4.7K_0402_5%

R02 modify 0926 for ESD

3

+INTMIC_VREFO

D37
AZ5125-02S.R7G_SOT23-3
Part Number = SCA00001A00

MIC1_L
1
R1084
MIC1_R
1
R1083

@

Internal MIC

MIC JACK
D39
RB751V-40_SOD323-2

2

SPKL+

41

23

2
1

46

39

38

40

C

HP_PLUG#

9

35mA

1
C1441
1
@ C1442

2
0.1U_0402_16V4Z
2
2.2U_0402_6.3V6M

330P_0402_50V7K
HP_LEFT
HP_RIGHT

1
R1095
1
R1096

2
51.1_0402_1%
2
51.1_0402_1%

HPOUT_L_1 1
L74
HPOUT_R_1 1
L75

2

1

2

Headphone
Out
JHP1 CONN@

C1440

330P_0402_50V7K
1

COM_MIC

HPOUT_L_2
2
FBMA-L11-160808-700LMT_2P
HPOUT_R_2
2
FBMA-L11-160808-700LMT_2P

2
4

HP_PLUG#

AGND

3
6
1

ALC271X-VB6-CG_QFN48_6X6

DGND

220P_0402_50V7K

+MIC1_VREFO

MIC_PLUG#

D38
RB751V-40_SOD323-2

SPK_OUT_L+

68mA 600mA

17

21

C1425
10U_0603_6.3V6M
2
2
C1421
0.1U_0402_16V4Z

3

16

2

2

LINE2_R

1

1

MIC1_C_L
2
4.7U_0603_6.3V6K
MIC1_C_R
2
4.7U_0603_6.3V6K
CBN

C1434
2.2U_0603_6.3V4Z

3
1

15

PVDD2

LINE2_L

1

C1419

3

2
B

14

1

1

MIC1_R

15mil

2

2

1
C1430
1
C1431
1

3
4

C1433 220P_0402_50V7K

2

MIC2_C_L
2
4.7U_0603_6.3V6K
MIC2_C_R
2
4.7U_0603_6.3V6K
LINE2_C_L
2
4.7U_0603_6.3V6K
LINE2_C_R
2
4.7U_0603_6.3V6K

External MIC
MIC1_L

G1
G2

INT_MIC_L

1

C1432 220P_0402_50V7K

1

1 COM_MIC_R
1K_0402_5%

1
C1426
1
C1427
1
C1428
1
C1429

1
2

1

INT_MIC

2
R1082

C1580
1000P_0402_50V7K

Combo MIC COM_MIC

2
R1080

INT_MIC
1
1K_0402_5%

AVDD1

U37
INT_MIC_R

PVDD1

2

C1424
0.1U_0402_16V4Z

25

2

40mil

AVDD2

2

10mil

3

C1423
0.1U_0402_16V4Z
1
1

1

1
2

R1079
10K_0402_5%

L69 Part Number = SM010004010
FBMA-L11-160808-700LMT_2P
INT_MIC_R
1
2

15mil

ACES_88266-02001
Part Number = SP020008Y00
PCB Footprint = ACES_88266-02001_2P

L70
BLM18AG121SN1D_2P
Part Number = SM010030010
2
1
+3VS

C1420
+3VS_DVDD 0.1U_0402_16V4Z

+AVDD_HDA

C1422
10U_0805_10V4Z

Internal MIC

2

C1418
0.1U_0402_16V4Z

1

2

CONN@
JMIC2
@
D36
AZ5125-02S.R7G_SOT23-3

HD Audio Codec

DVDD

2

L71
Part Number = SM010030010
BLM18AG121SN1D_2P
2
1

+VDDA

+PVDD1_HDA

1

DVDD_IO

C1417
10U_0805_10V4Z

For EMI

INT_MIC_L
2

40mil
1

+INTMIC_VREFO

R03 modify for ESD Resverd

1
L68
Part Number = SM010014520
FBMA-L11-201209-221LMA30T_0805
2
1

+VDDA

C

Int. MIC Conn.

D35
RB751V-40_SOD323-2

R1078
0_0603_5%

R03 modify

ACES_88266-02001
CONN@

1 1

2

G1
G2

2SC2411K_SOT23-3

1 1

2

R1077

1
2
C1414
1U_0402_6.3V6K

<27> FCH_SPKR
C1416
0.1U_0402_16V4Z

3
4

R02 modify 0926 for ESD

2
2.4K_0402_1%

2

1

1
R1076

Q49

1
2
D

D34
AZ5125-02S.R7G_SOT23-3
SCA00001A00

E

2

@
C1415
10U_0805_10V4Z

2
B

2

+5VS

C

R1075
1
2
560_0402_5%

1
2
C1413
1U_0402_6.3V6K

<37> BEEP#

+PVDD_HDA

40mil

D33
AZ5125-02S.R7G_SOT23-3
SCA00001A00

1
2

1

@
L67
Part Number = SM010014520
FBMA-L11-201209-221LMA30T_0805
2
1

MONO_IN

2
1U_0402_6.3V6K

1

1
C1412

G1
G2
ACES_88266-02001
CONN@
JSPK1

2

(output = 300 mA)

1
2

3
4

R1074
10K_0402_5%

4.75V

D

20mil

2

R1073
10K_0402_5%

@ 1
2
C1411
G9191-475T1U_SOT23-5 0.01U_0402_16V7K
BYP

2
1U_0402_6.3V6K

2

GND
SHDN

1
C1410

SPK_L+
SPK_LSPK_R+
SPK_R-

MBK1608301YZF_2P~N
MBK1608301YZF_2P~N
MBK1608301YZF_2P~N
MBK1608301YZF_2P~N
3

2
+VDDA

L94
L91
L92
L93

1

2
3

2

5

1

OUT

1

C1409
0.1U_0402_16V4Z

60mil

IN

SPKL+
SPKLSPKR+
SPKR-

2

60mil 1

R1068
10K_0402_5%

+3VS

@
U36

1

JSPK2
1
2

Int. Speaker Conn.

1

R1067
0_0805_5%
2
1

+5VS

5

A

A

PJ27
JUMP_43X39
1 1
2 2

1

PJ28
JUMP_43X39
1 1
2 2

PJ29
JUMP_43X39
1
2 2

1

PJ31
JUMP_43X39
1 1
2 2

GND

HONGLIN 13-18200613CP 3.6D 6P AUDIO
Part Number = DC230008000
PCB Footprint = SINGA_2SJ2326-001111_6P-T

PJ30
JUMP_43X39
1
2 2

GNDA GND
5

2011/07/08

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

PJ26
JUMP_43X39
1 1
2 2

2015/07/08

Deciphered Date

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

GNDA

Date:

4

3

2

Sheet

Wednesday, February 29, 2012
1

39

of

52

)
A
3
.
3
(
S
V
3
+
O
T
W
L
A
V
3
+

2
1

1

3

1
1

1

3
2

2

2
1

1
2

2
VGA@
R1114
470_0603_5%

2

+5VALW
2

2

VGA_PWR_ON#

1

2

@
C1464
.1U_0402_16V7K

1

2
@
R1121
510K_0402_5%
D
ACIN 2
G

D

@
Q69
2N7002K_SOT23-3

VGA@
Q68
2N7002K_SOT23-3

2

<20,46> VGA_PWR_ON

G

3

S

VGA@
R1123
100K_0402_5%

3

1

1

2
@
R1120
47K_0402_5%

VGA@
R1119
100K_0402_5%

1

1 @
C1462
.1U_0603_25V7K

5 1.5_VDDC_PWREN#
Q64B
DMN66D0LDW-7_SOT363-6
VGA@

1

1.5_VDDC_PWREN#

Q65B

2

1.5VSG_GATE

1

SUSP

@
C1458
1

3 1

2

@
C1460
2 10U_0603_6.3V6M

@
C1457
1

4

1

6

2

1

VGA@
Q64A
DMN66D0LDW-7_SOT363-6
5

1
2
3

1 2

2

+VSB

8
7
6
5

@
R1118
100K_0402_5%
1
2

3 1

2
6
1

1

C1463
0.22U_0402_10V4Z

@
C1459
10U_0603_6.3V6M

R1117
470_0603_5%

4

2
1

Q65A

2

DMN66D0LDW-7_SOT363-6

2

R1109
10K_0402_5%

+1.5VSG

1U_0402_6.3V6K

1

4

2

+1.5V

+1.5VS

C1461

DMN66D0LDW-7_SOT363-6

R1122
2
1
47K_0402_5%

10U_0603_6.3V6M

R1116
100K_0402_5%

2

<37,43,48> SUSP#

2

@
U41
AO4430L_SO8

AP2301GN-HF_SOT23-3
Q63
1

Q52A
DMN66D0LDW-7_SOT363-6

+1.5V to +1.5VSG (1.5A)

10U_0603_6.3V6M

3

For Power noise
20110127
1
680P_0402_50V7K
1
680P_0402_50V7K
1
680P_0402_50V7K
1
680P_0402_50V7K

3 1

SUSP

4

C1456
.1U_0603_25V7K

5
Q60B

)
A
5
.
1
(
S
V
5
.
1
+
O
T
V
5
.
1
+
+1.5V

3

Q57 change to SB000008J10
20101228

1

2

2
C19
2
C27
2
C28
2
C31

2

6
Q60A

2

DMN66D0LDW-7_SOT363-6

+3VS

r
e
w
o
P
A
G
V

1

SUSP#

R1108
100K_0402_5%

R1110
470_0603_5%

4

4

2

DMN66D0LDW-7_SOT363-6

C1452

2

1

C1455

1U_0402_6.3V6K

1

+5VALW

C1451
.1U_0603_25V7K

Q57
2N7002K_SOT23-3

G
3

U40
SI4800BDY-T1-GE3_SO8
1
2
3

10U_0603_6.3V6M

8
7
6
5

1

R1104
100K_0402_5%

SUSP

ACIN 2
S

3VS_GATE
1
200K_0402_5%

SUSP

Q54B
DMN66D0LDW-7_SOT363-6

5

<29,35,37,48> SYSON

1

2

+3VS

C1454

C1453

2
R1112

+VSB

10U_0603_6.3V6M

10U_0603_6.3V6M

2

R1102
10K_0402_5%

D

1

2

Q51
2N7002K_SOT23-3

1

2
Q54A
DMN66D0LDW-7_SOT363-6

Q52B
DMN66D0LDW-7_SOT363-6

6

VLDT_EN#

+3VALW

2

4

1.1VS_GATE

1
2
R1105
47K_0402_5%

G
S

VLDT_EN#

SYSON#

<36> SYSON#
D

2

<37,47> VLDT_EN

5

1

+VSB

<37,42,43> ACIN

1

4

1
2

3 1
Q53B

1

DMN66D0LDW-7_SOT363-6

2

R1098
100K_0402_5%

1 2

2

Q53A

2

R1101
470_0603_5%

SUSP

5

R1106
300K_0402_5%

SUSP

C1450
.1U_0603_25V7K

2

VLDT_EN#

1

6

6

1

1

3 1

2

5VS_GATE

2
100K_0402_5%

2

1

1
R1103

+VSB

4

4

1

1

1
2
3

C1449
1U_0402_6.3V6K

2

@
R1100
1K_0402_5%

R1099
470_0603_5%

+5VALW

R1097
100K_0402_5%

8
7
6
5

C1447
10U_0603_6.3V6M

2

1

C1448
10U_0603_6.3V6M

1

DMN66D0LDW-7_SOT363-6

2

+1.1VS
U39
AO4430L_SO8

C1444
1U_0402_6.3V6K

1

E

+5VALW

+1.1VALW

C1446
10U_0805_10V4Z

2

U38
SI4800BDY-T1-GE3_SO8
1
2
3

8
7
6
5
C1445

C1443

10U_0805_10V4Z

10U_0805_10V4Z

1

+5VS

D

2

+5VALW

C

)
A
1
.
1
(
S
V
1
.
1
+
O
T
W
L
A
V
1
.
1
+

B

)
A
5
(
S
V
5
+
O
T
W
L
A
V
5
+

A

+1.2VS
2

VLDT_EN#

Q74
2N7002K_SOT23-3

VGA@
R1124
2
1
200K_0402_5%

VGA@
R1130
1
2
10K_0402_5%

2

2

SUSP

2

G

VGA@
C1577

1

D
G

VGA@
Q77
2N7002K_SOT23-3

S
VGA@
R1134
10K_0402_5%

Q99B
VGA@
5 VGA_PWR_ON#
DMN66D0LDW-7_SOT363-6

S

2011/07/08

Issued Date

Q80
2N7002K_SOT23-3

4

Compal Electronics, Inc.
2015/07/08

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

2

<20,45,47,49> 1.5_VDDC_PWREN

2

Compal Secret Data

Security Classification

SUSP

G
Q79
2N7002K_SOT23-3

3

3

S

1

D

SYSON#

Q78
2N7002K_SOT23-3

VGA@
Q99A

C1579
2

1.5_VDDC_PWREN#

VGA@
R1132
470_0603_5%

1

1 1

1 1

R1137
470_0603_5%

D
2
G

VGA_PWR_ON 2
DMN66D0LDW-7_SOT363-6

2

2

2
D

S

+0.75VS

R1136
470_0603_5%

1 1

R1135
470_0603_5%

3

4

+2.5VS

1

C1578

0.1U_0402_16V4Z

+1.5V

2

VGA@

+5VALW

6

3

3

S

1U_0402_6.3V6K

3

2
G

Q73
2N7002K_SOT23-3
VGA@

1

2 VGA_PWR_ON#
G
S

10U_0603_6.3V6M

3

1.5_VDDC_PWREN#

Q72
2N7002K_SOT23-3
VGA@

1

2
G
S

VGA@
R1131
100K_0402_5%

1
VGA@

VGA_PWR_ON#

Q71
2N7002K_SOT23-3
VGA@

3

VGA@

2
G
S

R03 modify for
VGA power sequence

3

D

1

D

+5VALW

Q98
AP2301GN-HF_SOT23-3

2

D

+3VSG

2

D

@
R1111
0_0603_5%
1
2

1

1 1

R1128
470_0603_5%

1 1

R1127
470_0603_5%
VGA@

1 1

R1126
470_0603_5%
VGA@

1 1

R1125
470_0603_5%
VGA@

2

2

2

+3VS

3

+1.8VSG

4

+VGA_CORE

2

+1.0VSG

2

3

S

B

C

D

SCHEMATIC,MB A8331
Document Number

Rev
B

4019H2
Sheet

Wednesday, February 29, 2012
E

40

of

52

5

4

3

2

1

Part Number = SP02000VQ00
PCB Footprint = LIYO_309001-04301-031_4P
S W-CONN CVILUX CI0104M1HRR-NH 4P P2.0

PC3
100P_0402_50V8J

2

2

PC2
100P_0402_50V8J

1

1

1
PC1
1000P_0402_50V7K

2

CONN@

2

1
2
3
4
5
6

1

1
2
3
4
GND
GND

VIN

PL1
SMB3025500YA_2P
1
2

PJP1

PC4
1000P_0402_50V7K

D

D

2

VIN

1

PD2
LL4148_LL34-2
2
1

BATT+

1

1

PD1 @
LL4148_LL34-2

2
1

<38> 51ON#

2

VS

1
PJ1
PC6
0.1U_0603_25V7K

+3VALWP

1

1

PJ2
2

2

+3VALW

+5VALWP

1

1

Pre_CHG

+5VALW

1

+1.1VALWP

B

2

+1.1VALW

(7A,280mils ,Via NO.=14)

1
1

+VGA_COREP

1

PJ6
2

2

+VSB

PJP3
JUMP_43X118
1
2 2

1

+0.75VSP

1

2

2

+0.75VS

JUMP_43X79

(3A,120mils ,Via NO.=6)

Short R02 modify
PJ8

+1.5VSGP

1

1

2

+1.5VSG

2

JUMP_43X118

PJP4
JUMP_43X118
1 1
2 2

(8.1A,320mils ,Via NO.=17)
+VGA_CORE

1

PR12
1K_1206_5%
1
2

2

(5A,200mils ,Via NO.= 10)

(120mA,40mils ,Via NO.= 2)

2

PR10
1

PR9
1
2

PR11
1K_1206_5%
1
2

3
100K_0402_5%

2

PR8
1K_1206_5%
1
2

1

JUMP_43X118

1

C

B+

2

+3VLP

PQ2
TP0610K-T1-E3_SOT23-3

LL4148_LL34-2
PD3
1
100K_0402_5%

+CHGRTC

PR7
1K_1206_5%
1
2

+1.8VSG

PJ4
2

2

JUMP_43X39

VIN

2

JUMP_43X118

PJ5

+VSBP

2

(3A,120mils ,Via NO.=6)

PJ3

PR4
22K_0402_5%

PR5
0_0603_5%
1
2

1

JUMP_43X118

(3.9A,160mils ,Via NO.= 8)

2

1

+1.8VSGP

JUMP_43X118

2

1

3

PR2 @
68_1206_5%

2

1
PR3
100K_0402_5%

C

PC5
0.22U_0603_25V7K
2
1

N1

2

PR1 @
68_1206_5%
PQ1
TP0610K-T1-E3_SOT23-3

PJ9

+2.5VSP

PR13
100K_0402_5%

1

1

2

B

2

+2.5VS

2

+1.2VS

JUMP_43X39

1

12

PJ11

+1.0VSGP

2

PJ10

2
1

2

3

1

2

JUMP_43X118

3
BAS40CW_SOT323-3

1

+1.2VSP

2
PQ3
PDTC115EU_SOT323-3

PQ4
PDTC115EU_SOT323-3
3

<42> +5VALWP

1

+1.0VSG

2

JUMP_43X39

PD4
<37> ACOFF

1

@

+VDDCIP

1

PJ24

1

2

+VDDCI

2

JUMP_43X118

PJ7

+1.5VP

1

1

2

+1.5V

2

JUMP_43X118
PJ13
1 1
2 2
JUMP_43X118

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/08

2015/07/08

Deciphered Date

Title

Compal Electronics, Inc.
SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

5

4

3

2

Sheet

Wednesday, February 29, 2012
1

41

of

52

5

4

3

2

1

PQ24 930@
PDTC115EUA_SC70-3

S

2
G

1

3
2
1

S

PC46
1U_0603_10V6K
2
1

PQ106B
DMN66D0LDW-7_SOT363-6

2

1

1

VL

RT8205_B+

2VREF_8205

1

PQ25
PDTC115EUA_SC70-3

Typ: 175mA

+5VALWP

1
PC43
220U_6.3V_M

+

2

B

TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
(2)SMPS2=375KHZ(+3VALWP)

+3.3VALWP
Ipeak=5.78A ; 1.2Ipeak=6.94A; Imax=4.05A
f=375KHz, L=4.7UH
Rdson=15~18m ohm
1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=0.716A
Vlimit=10*10^-6*110Kohm/10=0.14V
Ilimit=0.11/(18m*1.2)~0.11/(15m)=6.34A~9.13A
Iocp=7.06A~9.85AA (7.06A>6.94A -> ok) -DVT-

+5VALWP
Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A
f=300KHz, L=4.7UH,Rentrip=154k ohm
Rdson=15~18m ohm
1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A
Vlimit=10*10^-6*154Kohm/10=0.15V
Ilimit=0.15/(18m*1.2)~0.15/(15m)=7.13~10.26A
Iocp=8.44~11.57A (8.44>8.4 -> OK)

3

PC67
4.7U_0603_6.3V6K

1
2

2 930@ 1
PR82
402K_0402_1%

1

4

PR60
4.7_1206_5%

5

2

NC

RT8205LGQW_WQFN24_4X4

18

17

VREG5

LG_5V

VIN

19

13

5

PC38
0.1U_0603_25V7K
2
1

PC37
2200P_0402_50V7K
2
1

PC36
4.7U_0805_25V6-K
2
1

PC35
4.7U_0805_25V6-K
2
1

ENTRIP1

1

2
FB1

REF

3

4

6

5

LGATE1

PL5
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2

3
2
1
D

5
G

1

2

PR85
930@
D

A

D

PQ105A
930@
DMN66D0LDW-7_SOT363-6

930@ PQ105B
DMN66D0LDW-7_SOT363-6

5
G

Compal Secret Data

Security Classification
2011/07/08

Issued Date

S

Deciphered Date

2015/07/08

Title

Compal Electronics, Inc.
SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

7,40,43> ACIN

PR83
316K_0402_1%
1 930@ 2

LGATE2

PC47
4.7U_0805_10V6K

2

2

4

VS

VS

6

1

930@ PR84
1M_0402_1%
1
2

1

VL

A

930@ PR81
1M_0402_1%
1
2

3 2
1
10K_0402_1%

930@ PD15
LL4148_LL34-2
2
1

LX_5V

PR79
100K_0402_1%
2
1

PR80
0_0402_5%
1
2

<8,37,44> MAINPWON
VIN

9012@ PR102
0_0402_5%
1
2

UG_5V

20

2
1
PC48
0.1U_0603_25V7K

G

3

ENTRIP2

6

ENTRIP1

S

<37,38> EC_ON

21

PHASE1

PQ23
SI7716ADN-T1-GE3_POWERPAK8-5

2
1
PR62
100K_0402_1%

RLZ5.1B_LL34

PQ106A
DMN66D0LDW-7_SOT363-6

VL

UGATE1

PHASE2

2

2

UGATE2

C

PC45
680P_0402_50V7K

1

PR57
PC41
2.2_0603_1% 0.1U_0603_25V7K
BST_5V 1
2 1
2

SPOK <44,45>

B+

D
B

PR59 @
0_0402_5%
2
1

PR61
499K_0402_1%
1
2

PD8

1
2
3

PC44
680P_0402_50V7K
2
1

2

12

4

+

PC42
220U_6.3V_M

22

GND

MAINPWON

23

BOOT1

EN

PQ22
SI7716ADN-T1-GE3_POWERPAK8-5

PGOOD

BOOT2

16

LG_3V

4

1

5

PR58
4.7_1206_5%
2
1

4.7UH_PCMC063T-4R7MN_5.5A_20%
PL4
1
2

+3VALWP

VREG3

VFB=2.0V

PQ21
SIS412DN-T1-GE3_POWERPAK8-5

4
24

15

1

PR55
154K_0402_1%
2

VO1

VO2

8
PR56
2 1
2 BST_3V 9
2.2_0603_1%
PC40
UG_3V 10
0.1U_0603_25V7K
LX_3V
11

1
2
3

C

RT8205_B+

ENTRIP1

2

P PAD

7

TONSEL

25

4

1

FB2

PU2

1

PC39
4.7U_0805_10V6K

5

PC34
2200P_0402_50V7K
2
1

PC33
4.7U_0805_25V6-K
2
1

PQ20
SIS412DN-T1-GE3_POWERPAK8-5

PR54
137K_0402_1%
1
2

ENTRIP2

PR53
20K_0402_1%
1
2

Typ: 175mA +3VLP
PC32
4.7U_0805_25V6-K
2
1

PC31
0.1U_0603_25V7K
2
1

1
2

PC200
0.1U_0402_25V6

PL3
HCB4532KF-800T90_1812
1
2

PR52
20K_0402_1%
1
2

ENTRIP2

RT8205_B+

PR51
30K_0402_1%
1
2

SKIPSEL

@

B+

2

D

PR50
13.3K_0402_1%
1
2

14

@

PC110
10U_0805_25V6K
2
1

D

PC104
10U_0805_25V6K
2
1

PC29
1U_0603_10V6K

2VREF_8205

Rev
B

4019H2

Date:

5

4

3

2

Wednesday, February 29, 2012

Sheet
1

42

of

52

A

B

C

D

1

D

3

for reverse input protection

S

SRP

13

SRP

BQ24725_ACDRV

4

ACDRV

SRN

12

SRN

5

ACOK

BATDRV

11

1
2

PC301
0.01U_0402_25V7K

2

2
1

S

Close EC

1

PR291
0_0402_5%

1

PC297
0.01U_0402_50V7K

2

PC296
2200P_0402_50V7K

PC294
10U_0805_25V6K
2
1

PC293
10U_0805_25V6K
2
1

PD13
SX34 SMA
2
1

1
2

PC295
0.1U_0402_25V6
2
1

CSON1

CSOP1

1
2

PC298
0.1U_0402_25V6

PR301
4.7_1206_5%

ILIM and external DPM

EC_SMB_DA1 <37,44>

Min.
3.906A

Typ
Max.
4.006A 4.108A
4

@ PC304
0.1U_0402_16V7K

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

Max.
18.275V
17.898V

ADP_I <37,44>

1

1

Typ
18.063V
17.687V

2

PQ92
2N7002KW_SOT323-3

2

PR313
0_0402_5%
1
2

Min.
17.852V
17.476V

EC_SMB_CK1 <37,44>
PR312
66.5K_0603_0.1%

PC303
100P_0402_50V8J

G

2

Vin Dectector
L-->H
H-->L

2

PC302
0.1U_0402_16V7K

1
2

2

3

<37,40,48> SUSP#

3

D

4

3

2
PR305
316K_0402_1%

PR310
154K_0603_0.1%

1 2
2

@

1

ACDET

PQ91
PDTC115EUA_SC70-3

1

<37> FSTCHG

PR311
100K_0402_1%
1
2

1

5

ILIM
10

9

8

SDA

IOUT

1
1
PR309
2M_0402_1%

3

+3VALW

PR308
100K_0402_1%

PR307
280K_0603_0.1%
1
2

1

VIN

2

PR306
2M_0402_1%

2

1

PD14
RB751V-40_SOD323-2

1
2 CSON1
PR303
6.8_0603_5%
BQ24725_BATDRV

2

1

Pre_CHG

ACDET

7

<37,40,42> ACIN

6

2
PR304
100K_0402_1%

SCL

CMSRC

ACDET

3

PR302
10_0603_5%
1
2 CSOP1

1

14

4

2

GND

DL_CHG

BQ24725_CMSRC

1

+3VLP

2

2
3
2
1

2

15

BQ24725ARGRR_VQFN20_3P5X3P5

3

1

1

PC279
10U_0805_25V6K

2

5

1
PR296
0_0603_5%
1
2
17

18

16
LODRV

PL27
PR300
10UH_FDVE1040-H-100M=P3_6.5A_20% 0.01_1206_1%
BQ24725_LX
1
2 CHG
1
4

PC300
680P_0402_50V7K

ACP

2

BATT+

PC292
1
2

PQ90
SIS412DN-T1-GE3_POWERPAK8-5

2

PQ89
SIS412DN-T1-GE3_POWERPAK8-5

REGN

ACN

HIDRV

PAD

1

PHASE

VCC

21

19

20

2
@ PC291
2.2U_0805_25V6K

2

PD12
RB751V-40_SOD323-2

1U_0603_25V6K
PU21

1
2

PR298
0_0402_5%
DH_CHG 1
2DH_CHG-1 4

3
2
1

@ PR299
3.3_1210_5%

DH_CHG

1U_0603_25V6K

BQ24725_LX

PC290
1
2

@

PR292
4.12K_0603_1%

PC288
0.047U_0402_25V7K
1
2
PR295
10_1206_1%

1
BQ24725_ACP

1
2

PC289
0.1U_0603_25V7K

1 2

BQ24725_ACN

@ PR297
3.3_1210_5%

BQ24725_BATDRV 1

PC286
0.01U_0402_50V7K

2
2

3

PD11
BAS40CW_SOT323-3

1

2

PR294
4.12K_0603_1%

1

PR293
4.12K_0603_1%
2
1

1

2

VIN
2

1
2
3

4

VIN

PC283
2200P_0402_50V7K

1.2UH_1231AS-H-1R2N=P3_2.9A_30%

PC285
0.1U_0402_25V6
1
2

PQ88
AO4466L_SO8

8
7
6
5

2
1
PC299
0.1U_0603_25V7K

3

@

PC282
0.1U_0402_25V6
2
1

2

1

2CHG_B+

1

1

4

@

PC281
10U_0805_25V6K
2
1

1

1

8
7
6
5
4

1
2

PL26

1

2

@

1
2
3

PC275
0.1U_0402_25V6

1

PR290
0_0402_5%

1
2
3

4

PC284
2200P_0402_50V7K
2
1

8
7
6
5

JUMP_43X118

B+

PR289
0.02_2512_1%

1

2

P2
PQ87
AO4466L_SO8

1

2

P1
PQ86
AO4466L_SO8

2

VIN

2

1

@
PJ32

2

PC280
10U_0805_25V6K

2

PR288
3M_0402_5%

BQ24725_BST

1

BTST

2

PR287
1M_0402_5%

PC287
0.1U_0402_25V6

1
1

PC278
10U_0805_25V6K

PQ85
SI1304BDL-T1-E3_SC70-3

2
G

2011/07/08

Deciphered Date

2015/07/08

Title

SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

A

B

C

Wednesday, February 29, 2012
D

Sheet

43

of

52

5

4

3

2

1

Part Number = DC040008G00
PCB Footprint = SUYIN_200275GR008G13GZR_8P-T
PJP2
SUYIN_200275GR008G16BZR 8P
D

2

EC_SMDA
EC_SMCA
TH
PI

PR250
100_0402_1%

CONN@

PH1 under CPU botten side :
CPU thermal protection at 92 +/- 3 degree C

PR251
100_0402_1%

EC_SMB_DA1 <37,43>

+3VLP

ADP_I <37,43>

1

<40,41>
VMB
1

UMA@ PR34
3.92K_0402_1%

<40,41>
BATT+

1
PR254
21K_0402_1%

+3VLP

2
1

VCC TMSNS1

8

2

GND RHYST1

7

2 PR259

3

OT1 TMSNS2

6

9.53K_0402_1%

4

OT2 RHYST2

5

2

1
2
1

BATT_TEMP <37>

1

2

2

VGA@ PR36
16.2K_0402_1%

PR257
100K_0402_1%

UMA@ PR36
10.5K_0402_1%

PH1
100K_0402_1%_NCP15WF104F03RC

PR253 @
100K_0402_1%

PR38
10K_0402_1%
2

3

S

C

1

PR261
0_0402_5%

2

2
G

9012_PH1 <37>
9012_VCIN <37>

1

G718TM1U_SOT23-8

1

D
PQ65
2N7002W-T/R7_SOT323-3

1

PR266
0_0402_5%

1

2

+3VLP

PR267 @
100K_0402_1%

1

1
2

<8,37,42> MAINPWON
<8,25,37,50> EC_THERM#

VGA@ PR34
8.87K_0402_1%
2

PU17

@ PR256
100K_0402_1%
PR258
1K_0402_1%

C

1

1

1
PC233
0.1U_0603_25V7K
+3VALWP
2

PC235
0.01U_0402_25V7K

2

2

PR255
6.49K_0402_1%
2
1

1
2

1
2

PC234
1000P_0402_50V7K

+3VLP

EC_SMB_CK1 <37,43>
PR252
1K_0402_5%

2

PL19
SMB3025500YA_2P
1
2

1

10
9
8
7
6
5
4
3
2
1

1

GND
GND
8
7
6
5
4
3
2
1

2

D

PQ77
TP0610K-T1-E3_SOT23-3

3

1

+VSBP

2

@
@P

PC237
0.1U_0603_25V7K

2

1
2

1

2

VL

PC236
C236
0.22U_0603_25V7K

PR263
22K_0402_1%
1
2

2
1
PR262
100K_0402_1%

B+

PR264
100K_0402_1%
1

D

S

PQ78
2N7002W-T/R7_SOT323-3

2
G

2

PC238
1U_0402_6.3V6K

1

<42,45> SPOK

PR265
1K_0402_5%
1
2

3

B

1

B

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/08

2015/07/08

Deciphered Date

Title

Compal Electronics, Inc.
SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

5

4

3

2

Sheet

Wednesday, February 29, 2012
1

44

of

52

A

B

C

D

VFB= 0.7V
Vo=VFB*(1+5.76K/10K)= 1.1V
Freq= 266~314KHz , 290KHz(typ)

TRIP_1.1VALW

2

TRIP

DRVH

9

DH_1.1VALW

EN_1.1VALW

3

EN

SW

8

SW_1.1VALW

FB_1.1VALW

4

VFB

V5IN

7

1.1VALW_5V

RF_1.1VALW

5

TST

DRVL

6

DL_1.1VALW

PC311
0.1U_0603_25V7K
1
2

1
2

PC310
2200P_0402_50V7K

PC308
0.1U_0402_25V6
2
1

1

PC307
4.7U_0805_25V6-K
2
1

2

+

PR317
4.7_1206_5%
PQ94
SI7716ADN-T1-GE3_POWERPAK8-5

4

3
2
1

1

2

2

TPS51212DSCR_SON10_3X3

1

1
PC313
1U_0603_10V6K

2

PR318
470K_0402_1%

+1.1VALWP

+5VALW

11

TP

PC306
4.7U_0805_25V6-K

PL29
2.2U_FDV0630-2R2M-P3_7.2A_20%
1
2

1

BST_1.1VALW

1

10

1

@

5

1
2

@ PC312
@PC312
0.1U_0402_16V7K

VBST

1

PR316
0_0402_5%
1
2

<42,44> SPOK

PGOOD

B+

3
2
1

PR314
0_0603_5%
1
2

PU22
1

2

1

PQ93
SIS412DN-T1-GE3_POWERPAK8-5

4

PR315
105K_0402_1%
2
1

PC305
2200P_0402_50V7K

2

1

PC309
0.1U_0402_25V6

PL28
FBMA-L18-453215-900LMA90T_1812
2
1

1.1VALW_B+

Iocp=6.25A
5

Cesr= 15m ohm
Ipeak= 5.21A Imax= 3.65A
Iocp= 7.7A~11.84A

PC316
680P_0402_50V7K

2

Rds=2.6mΩ(Typ)
3.2mΩ(Max)

PC314
330U_6.3V_M

2

PR319
5.76K_0402_1%
2
1

VFB=0.7V

2

1

2

2

PR320
10K_0402_1%

EN

6

FB_VDDCIP

@
PR97

1 @

1

FB=0.6Volt

1

@
PC78

2

@
PC82

3

PR100
3.4K_0402_1%
1

7

@
PR101
0_0402_5%

SY8033BDBC_DFN10_3X3
2

@
PC79
@

PC77
680P_0603_50V7K

1

@
PR104
1M_0402_5%

2

PR99
100K_0402_5%
@

0.1U_0402_10V7K

2
2

1

11

3

<20,40,47,49> 1.5_VDDC_PWREN

+VDDCIP

@
PC75

1

FB

LX_VDDCIP

22U_0805_6.3VAM

EN_VDDCIP
5

3

2

SVIN

2

LX

22U_0805_6.3VAM
2
1

8

LX

2

PVIN

1

PVIN

9

68P_0402_50V8J
2
1

1
2

PC76 @
22U_0805_6.3VAM

10

2
1
4.7_1206_5%

2

NC

2

PG

1

JUMP_43X79

NC

1

TP

+5VS

@
PL9
2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%
1
2

4

@
PU7

@
PJ17

@
1
2
PR107
10_0402_5%

VDDCI_SEN <16>

1

+3VSG

1

@
PR111
10K_0402_5%
2
1

2

D

1

@
PQ28
2N7002W-T/R7_SOT323-3

VDDCI_VID

<14>

@
PC85
4700P_0402_25V7K

@
PR112
100K_0402_5%
2

2

3

S

1

2
G

@
PR109
10K_0402_5%

2

2

1

@
PR108
20K_0402_1%

1
@
PR95
10K_0402_1%

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Deciphered Date

2015/07/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

SCHEMATIC,MB A8331
Rev
B

4019H2

Wednesday, February 29, 2012
D

Sheet

45

of

52

5

4

3

2

1

D

D

Note:Imax=3.3A

1

VGA@

VGA@ PR324
4.99K_0402_1%
2

1
2

@

VGA@ PC321
680P_0603_50V7K

1
2

PC323
0.1U_0402_10V7K

1
2

VGA@ PC322
0.22U_0603_25V7K

1

1

FB=0.6V

SY8033BDBC_DFN10_3X3

2

1
VGA@

PC320
22U_0805_6.3VAM

NC

NC

VGA@

FB_1.8V

1

11

1.8V_EN

6

+1.8VSGP

2

VGA@
FB

VGA@
PR322
10K_0402_1%

PC319
22U_0805_6.3VAM

EN

3

VGA@ PL30
2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%
1
2
PC318
68P_0402_50V8J
2
1

SVIN

5

LX

LX_1.8V

2

8

2

1

PVIN

LX

2

9

TP

VGA@ PR323
100K_0402_1%
VGA_PWR_ON
1
2

PVIN

PR321
4.7_1206_5%

1

VGA@ PC317
22U_0805_6.3VAM

10

PG

2

2

7

1

JUMP_43X79

2

1

+3VS

4

VGA@
PU23

PJ14

C

C

+3VALW

VGA@ PC324
1U_0402_6.3V6K

PJ15
JUMP_43X79

Note:Imax=3.0A

OUT

3

1
1
2

PC328
1U_0402_6.3V6K

VGA@ PR327
6.04K_0402_1%

B

@ PR326
150_1206_5%

@
PR329
22K_0402_5%
2

2

VGA@ PC330
0.22U_0402_6.3V6K

1

1

2

VGA@ PR328
20K_0402_1%
1
2

<20,40> VGA_PWR_ON

+2.5VSP

GND

2

APL5930

IN

1

2

2

VGA@ PC326
22U_0805_6.3V6M

PC329
4.7U_0805_6.3V6K

2

VGA@ PC325
0.022U_0402_25V7K

1

1

VGA@ PR325
1.54K_0402_1%

1

2

+3VS

1

ADJ

FB=0.8V

VEN
POK

PU25
APL5508-25DC-TRL_SOT89-3

+1.0VSGP
2

3
4

1

VO
VO

2

2
1

8
7

VGA@ PC327
4.7U_0603_6.3V6K

2

B

VPP
VIN
TP
GND

2

PU24 VGA@
6
5
9

1

1

1

2

1

+1.5V

Ien=10uA, Vth=0.3V, notice
the res. and pull high
voltage from HW

A

A

Compal Secret Data

Security Classification
Issued Date

2011/07/08

Deciphered Date

2015/07/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
SCHEMATIC,MB A8331
Document Number

Rev
B

4019H2
Wednesday, February 29, 2012
1

Sheet

46

of

52

5

4

3

2

1

VFB= 0.7V
Vo=VFB*(1+7.15K/10K)= 1.2V
Freq= 266~314KHz , 290KHz(typ)

9

DH_1.2V

EN

SW

8

SW_1.2V

VFB

V5IN

7

1.2V_5V

TST

DRVL

6

DL_1.2V

TRIP

EN_1.2V

3

FB_1.2V

4

RF_1.2V

5

PC259
1U_0603_10V6K

4

1
2

PC254
0.1U_0402_25V6
2
1

1

PC253
4.7U_0805_25V6-K
2
1

+

PR276
4.7_1206_5%

2

2

TPS51212DSCR_SON10_3X3

2

1
PQ82
FDS6670AS_NL_SO8

3
2
1

1

2

PR277
470K_0402_1%

+1.2VSP

+5VALW

11

TP

1

PL23
2.2U_FDV0630-2R2M-P3_7.2A_20%
1
2

1

VBST

2

PC257
0.1U_0603_25V7K
1
2

1

DRVH

PGOOD

TRIP_1.2V

1

@ PC258
0.1U_0402_16V7K

2

1

<37,40> VLDT_EN

BST_1.2V

D

@

5
6
7
8

PR275
0_0402_5%
1
2

10

1

B+

3
2
1

PR274
0_0603_5%
1
2

PU19
PR273
105K_0402_1%
2
1

PC252
4.7U_0805_25V6-K

1
2
PQ81
AO4466L_SO8

4

2

PC251
2200P_0402_50V7K

5
6
7
8
D

PC256
2200P_0402_50V7K

PL22
FBMA-L18-453215-900LMA90T_1812
2
1

1.2V_B+

PC255
0.1U_0402_25V6

Cesr= 15m ohm
Ipeak= 8.5A Imax= 6A Iocp=10.2
Iocp= 10.86A~17.33A

2
PC262
680P_0402_50V7K

2

Rds=2.6mΩ(Typ)
3.2mΩ(Max)

PC260
330U_2.5V_M

C

C

PR278
7.15K_0402_1%
2
1

1

VFB=0.7V

2

PR279
10K_0402_1%

VFB= 0.704V
Vo=VFB*(1+11.5K/10K)= 1.5V
Freq=290KHz(typ)

1

B+

PC268
2200P_0402_50V7K

2

VGA@ PC266
0.1U_0402_25V6
2
1

1
2

1
2

VGA@ PC265
4.7U_0805_25V6-K
2
1

PQ83 VGA@
SIS412DN-T1-GE3_POWERPAK8-5

VGA@ PC264
4.7U_0805_25V6-K

4

VGA@ PC263
2200P_0402_50V7K

2

1

5

Cesr= 15m ohm
Ipeak= 5A Imax= 3.5A Iocp=6A
Iocp= 6.4A~9.8A

VGA@ PC267
0.1U_0402_25V6

VGA@ PL24
FBMA-L18-453215-900LMA90T_1812
2
1

1.5VSG_B+

@

B

B

BST_1.5VSG

DRVH

9

DH_1.5VSG

SW

8

SW_1.5VSG

VFB

V5IN

7

1.5VSG_5V

TST

DRVL

6

DL_1.5VSG

TRIP

EN_1.5VSG

3

EN

FB_1.5VSG

4

RF_1.5VSG

5

VGA@ PL25
2.2U_FDV0630-2R2M-P3_7.2A_20%
1
2

1

PQ84 VGA@
SI7716ADN-T1-GE3_POWERPAK8-5

1
3
2
1

PC272 VGA@
330U_2.5V_M

2

PC274 VGA@
680P_0402_50V7K

2

Rds=2.6mΩ(Typ)
3.2mΩ(Max)
VFB=0.7V

+

PR283 VGA@
4.7_1206_5%

4

2

TPS51212DSCR_SON10_3X3

PC271 VGA@
1U_0603_10V6K

2

PR284 VGA@
470K_0402_1%

11
2

TP

+1.5VSGP

+5VALW

1

10

5

VBST

PGOOD

2

1

VGA@ PC270
0.22U_0402_16V7K

2

1

45,49> 1.5_VDDC_PWREN

1
TRIP_1.5VSG

1

VGA@ PR280
82.5K_0402_1%
2
1

VGA@
PR282
20K_0402_1%
1
2

PC269 VGA@
0.1U_0603_25V7K
1
2

3
2
1

VGA@ PR281
0_0603_5%
1
2

PU20 VGA@

VGA@ PR285
11.5K_0402_1%
2
1
A

1

A

PR286 VGA@
10K_0402_1%

Compal Electronics, Inc.

Compal Secret Data

2

Security Classification
2011/07/08

Issued Date

Deciphered Date

2015/07/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

SCHEMATIC,MB A8331
Rev
B

4019H2

Wednesday, February 29, 2012

Sheet
1

47

of

52

C

4

1
2

5

+1.5VP

1

PL31
FBMA-L18-453215-900LMA90T_1812
2
1

PC331
2
1
4.7U_0805_25V6-K
PC332
2
1
4.7U_0805_25V6-K
PC333
2
1
2200P_0402_50V7K
PC334
2
1
0.1U_0402_25V6
PC335
2
1
0.1U_0402_25V6

1.5V_B+

D

B+

PC337
2200P_0402_50V7K

B

PC336
2
1
560P_0402_50V7K

A

@

1

1

1

PQ95
MDU1516URH_POWERDFN56-8-5

GND

4

VTTREF

5

VDDQ

1
PGND

14

CS

13

VDDP

12

LG_1.5V

4

PR332
6.19K_0402_1%
2
1

1

2

PHASE

RT8207MZQW_WQFN20_3X3

15

PR331
4.7_1206_5%

+

PC341
330U_X_2VM_R9M

1

LX_1.5V

+1.5VP

5

UG_1.5V
17

16

19

BOOT

UGATE

PQ96
MDU1511RH_POWERDFN56-8-5

LGATE

VTTSNS

3

PL32
1UH_MMD-10DZ-1R0M-X1A_18A_20%
1
2

Rds=2.6mΩ(Typ)
3.2mΩ(Max)

2

VTTGND

PR330
PC338
2.2_0603_1%
0.1U_0603_25V7K
1
2 BST_1.5V-1
1
2

3
2
1

2

PAD

BST_1.5V

2
1

VLDOIN

PU26
21

20

靠近Output Cap PAD

VTT

1

PC340
10U_0805_25V6K

2

2

1

PC339
10U_0805_25V6K

+0.75VSP

18

2

3
2
1

PJ16
JUMP_43X79

2

PC342
680P_0402_50V7K

2

1
PR333
5.1_0603_5%

11

+5VALW

2

1

+3VALW

2
1
PR334
10K_0402_5%
PC344
1U_0603_10V6K
2
1

PGOOD
10

VDD

PC345
1U_0603_10V6K

@

PGOOD_1.5V

PR337
887K_0402_1%
2
1 1.5V_B+
1

PR338
5.9K_0402_1%
2
1
1

2

@ PC347
0.1U_0402_16V7K

2

@ PC346
0.1U_0402_16V7K

1

<29,35,37,40> SYSON

TON

S5

PR336
0_0402_5%
1
2

9

8

S3
7

<37,40,43> SUSP#

S5_1.5V

PR335
0_0402_5%
1
2

S3_1.5V

FB

PC343
0.033U_0402_16V7K

6

1

2

+1.5VP

2

2

FB=0.75V
To GND = 1.5V
To VDD = 1.8V

2

PR339
5.76K_0402_1%

3

3

STATE

S3

S5

S0

Hi

Hi

On

S3

Lo

Hi

On

Lo

Lo

S4/S5

1.5VP

Off
(Discharge)

VFB= 0.75V
Ipeak= 15A Imax= 10.5A
Iocp= 17.24A~25.47A

0.75VSP

Iocp=18A

On
Off
(Hi-Z)
Off
(Discharge)

Note: S3 - sleep ; S5 - power off

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Deciphered Date

2015/07/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

SCHEMATIC,MB A8331
Document Number

Rev
B

4019H2
Wednesday, February 29, 2012
D

Sheet

48

of

52

5

1

1

5

<20,27> VGA_PWRGD
PQ42 VGA@
MDU1516URH_POWERDFN56-8-5

4

BST_VCORE

9

DH_VCORE

3

EN

SW

8

SW_VCORE

4

VFB

V5IN

7

5

RF

DRVL

6

VGA@ PL16
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2

VGA@ PR147
4.7_1206_5%

VGA@ PC109
680P_0603_50V7K

1

VGA@ PR212
10_0402_5%
2
1

+

2

3
2
1
THA@ PR202

PR202 SEY@
5.9K_0402_1%

C

PR222 VGA@
1.2K_0402_1%

2

1

1 1

3
2
1

VGA@ PC166
.1U_0402_16V7K

Rds=2.9m/3.5mOHM

GCORE_SEN

GCORE_SEN <16>

PC202 VGA@
1000P_0402_50V7K

5.11K_0402_1%

2

1

1

2

+3VSG

SEY@ PR218
THA@ PR218
36.5K_0402_1%

VGA@ PR211
10K_0402_5%

2

1

VGA@ PR198
20.5K_0402_1%

2

VGA@ PC169
2200P_0402_25V7K

1

6

1
S

1

1

DMN66D0LDW-7_SOT363-6
VGA@ PQ47A

2

2

G

SEY@ PR208
THA@ PR208
124K_0402_1%

VGA@ PR199
40.2K_0402_1%
1
2

D

27.4K_0402_1%

VGA_CORE
F=1/(75*e-12*44.2)=300K
Ipeak=25A Imax=17.5A Iocp=30A

VGA@ PC168
4700P_0402_25V7K

@ PR207
10K_0402_5%
1

2

+3VSG
2

2

41.2K_0402_1%
B

B

3

GPU_VID1

GPU_VID0

1

1

Thames
Core Voltage Level

Seymour
Core Voltage Level

2

1

6

For Whistler
1/2Delta I=4.05A
Vtrip=36.5K*10uA=0.365V
Iocpmin=0.365V/(8*1.6m)+1/2Delta I=28.51A+4.05A
=32.56A

@ PR201
10K_0402_5%

D

G

VGA@PQ68A
DMN66D0LDW-7_SOT363-6

2

VGA@ PR210
10K_0402_5%
2
1

1.0V

1

0.95V

1.05V

0

0

1.00V

1.15V

2

2
G

VGA@ PQ68B
DMN66D0LDW-7_SOT363-6

VGA@ PR213
10K_0402_5%
5 2

@ PR209
10K_0402_5%
1

GPU_VID0 <14>
VGA@ PR205
10K_0402_5%

S

A

2

0

D

11

0.9V

For Seymour
1/2Delta I=4.31A
Vtrip=40.2K*10uA=0.402V
Iocp=0.402V/(8*3.2m)+1/2Delta I
=15.70A+4.31A=20.01A

3

0

0.9V

4

1

GPU_VID1 <14>
VGA@ PR197
10K_0402_5%

S

+3VSG

0.875V

1

@ PR165
10K_0402_5%

2

2

VGA@ PC167
4700P_0402_25V7K

1

GPIO 15

+3VSG

1

GPIO 20

S

4

VGA@ PQ47B
DMN66D0LDW-7_SOT363-6

5
1

G

1

VGA@ PR203
10K_0402_5%
VGA@ PR219
10K_0402_5%
1
2

D

A

PC108 VGA@
560U_2.5V_M

2
2

1
2

ESR=10mohm

VGA@ PR206
0_0402_5%
2

4
2

4

C

VGA@
PC201
.1U_0402_16V7K
2

2

VGA@ PQ44
MDU1511RH_POWERDFN56-8-5

VFB=0.6V

1

VGA@ PQ45
MDU1511RH_POWERDFN56-8-5
VGA@ PC106
1U_0603_6.3V6M

1

1

DL_VCORE

11

1

TP

+VGA_COREP

+5VALW

TPS51212DSCR_SON10_3X3
1

3
2
1

10

DRVH

5

2

VGA@ PR200
470K_0402_1%

VBST

TRIP

VGA@ PC105
0.1U_0603_25V7K
1
2

5

2

1
@ PR146
10K_0402_5%

PGOOD

2

VGA@ PR143
2.2_0603_1%
1
2

2

+3VS

1

1

VGA@ PR145
42.2K_0402_1%
1
2

VGA@ PR217
10K_0402_1%
1
2

D

2

10U_0805_25V6K
PC100 2
1 VGA@

VGA@ PR142
10K_0402_5%

PU10 VGA@

<20,40,45,47> 1.5_VDDC_PWREN

2

B+_CORE

10U_0805_25V6K
PC99 2
1 VGA@

@

0.1U_0603_25V7K
PC98 2
1 VGA@

D

3

+3VS
2200P_0402_25V7K
PC97 2
1 VGA@

2

1

VGA@ PL15
FBMA-L18-453215-900LMA90T_1812
1
2
PC190
2200P_0402_50V7K

B+

4

Compal Secret Data

Security Classification
Issued Date

2011/07/08

AP

2015/07/08

Deciphered Date

Title

Compal Electronics, Inc.
SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

5

4

3

2

Wednesday, February 29, 2012

Sheet
1

49

of

52

3

2

1

3
2
1
LGATE1

IMON

PHASE1

26

PHASE1

NTC

UGATE1

25

UGATE1

5
1

UGATE1

PR385
0_0603_5%
2

3
2
1

ISEN1

LGATE1

1

1
2

PC359
10U_0805_25V6K

1
2

PC358
10U_0805_25V6K

PC357
0.01U_0402_25V7K
2
1

PC356
0.01U_0402_25V7K
2
1

PC355
2200P_0402_50V7K
2
1

PC354
2200P_0402_50V7K
2
1
3

1

+CPU_CORE
2

ISEN2

PR388
10K_0402_1%
B

PR396
1_0402_1%
2
1

VSUM-

5

+CPU_CORE

UGATE2

PR403
0_0603_5%
2
1UGATE2-1 4

PQ103
MDU1516URH_POWERDFN56-8-5

PC402
10U_1206_25V6M
2
1

CPU_B+

3
2
1

APU_VDD_SEN <8>
PL37
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
4

PHASE2

<8>

PR408
PC407
2.2_0603_1% 0.22U_0603_25V7K
BOOT2 2
1 2
1

LGATE2

2

4

PR411
3.65K_0402_1%
VSUM+ 2
1

3

1

+CPU_CORE
2

ISEN1

PR407
10K_0402_1%

3
2
1

2

PC408
680P_0603_50V7K

PR412
1_0402_1%
VSUM- 2
1

A

Compal Secret Data

Security Classification
Issued Date

2 PR406 1
10K_0402_1%

PR410
4.7_1206_5%

PQ104
MDU1511RH_POWERDFN56-8-5
A

ISEN2

1

APU_VDD_RUN_FB_L

1 2

PC406
0.01U_0402_25V7K

PR405
0_0402_5%
2
1
PR409
10_0402_5%
2
1

2

PR391
3.65K_0402_1%
2
1

PC394
680P_0603_50V7K

2

3
2
1

PR398
PC395
137K_0402_1% 390P_0402_50V7K
2
1
2
1

PR402
10_0402_5%
2
1
PR404
0_0402_5%
2
1

1

1 2

4

PR400
PC399
2K_0402_1% 680P_0402_50V7K
2
1
2
1

@ PC401
@ PR401
820P_0402_25V7
100_0402_1%
2
1
2
1

PR379
1_0402_1%
VSUMN_NB 2
1

2 PR387 1
10K_0402_1%

PR390
4.7_1206_5%
VSUM+

@ PR394
32.4K_0402_1%
2
1

PQ102
MDU1511RH_POWERDFN56-8-5
PR397
2.1K_0402_1%
2
1

2 ISEN1_NB
PR370
10K_0402_1%

PL36
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
4

5

PR389
PC391
2.2_0603_1% 0.22U_0603_25V7K
BOOT1 2
1 2
1

5

2
1

PC398
330P_0402_50V7K

2
1

PC397
0.22U_0402_10V6K

PR399
549_0402_1%
2
1

2

PC400
0.1U_0603_50V7K

PC396
0.022U_0402_16V7K
1
2

PH6
10K_0402_5%_ERTJ0ER103J
2
12
1
PR392
2.61K_0402_1%
2

1

VSUM-

PC393
100P_0402_50V8J
2
1

PR373
3.65K_0402_1%
VSUMP_NB 2
1

PHASE1

PC390
10P_0402_50V8J
2
1

PR393
301_0402_1%
2
1

1

PQ101
MDU1516URH_POWERDFN56-8-5
VGATE <37>

PC392
1000P_0402_50V7K
2
1

PR369
10K_0402_1%
2
1

ISEN2_NB
PC380
680P_0603_50V7K

1UGATE1-1 4

VSUM+

B

PC350
100U_25V_M

1

PQ100
MDU1511RH_POWERDFN56-8-5

CPU_B+

PR381
100K_0402_5%

2
1
PC388
0.22U_0402_10V6K
2
1
PC389
0.22U_0402_10V6K

1

VSUM-

1 2

4
+5VS
@ PR413
0_0402_5%
2
1

TP
BOOT1

ISEN1

PR386
10K_0402_1%

3
2
1

ISL6208BCRZ-T_QFN8_2X2

+3VS

49

BOOT1

PGOOD

24

23

FB

COMP
22

FB2
20

VSEN

ISUMN

RTN
19

ISEN2

+CPU_CORE_NB

3

PC404
2200P_0402_50V7K
2
1

27

2
PR365
4.7_1206_5%

PC405
0.01U_0402_25V7K
2
1

LGATE1

LGATE_NB2

PC386
0.01U_0402_25V7K
2
1

2
28

PWROK

2

PWM_Y

1

VDD

ENABLE

SVT

1

PR376
2
1
1_0603_5%

2

30
29

5

LGATE

C

PR414
0_0603_5%

PC381
1U_0603_16V6K

VDDP

GND
TP

2

LGATE2

ISL6277HRTZ-T_TQFN48_6X6

VDDIO

4
9

PL35
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
4

PC384
10U_1206_25V6M
2
1

31

LGATE2

+5VALW

PC379
0.22U_0603_25V7K

PHASE_NB2

PC403
10U_1206_25V6M
2
1

PHASE2

8

1

UGATE2

1

0_0603_5%

2

33

1

2

PWM PHASE

3
2
1

BOOT2

PC378
1U_0603_16V6K
2
1

34

BOOT_NB2

3

PQ99
MDU1516URH_POWERDFN56-8-5

5

37

38
PHASEX

UGATEX

LGATEX

PWM2_NB

FCCM_NB

PGOOD_NB

FB_NB

COMP_NB

VSEN_NB

ISUMN_NB

35

PWM_NB

ISEN2_NB

CPU_B+

PC385
10U_1206_25V6M
2
1

PWM_NB
40

39

42

41

43

44

46

45

47

48
ISEN1_NB

ISUMP_NB

VIN
BOOT2

PR364

1
2

ISEN3

2
1
@PR384
@
PR384
10_0402_5%

2

36

UGATE

FCCM BOOT

VCC

FCCM_NB 7

2

PH5
470K_0402_5%_TSM0B474J4702RE
2
1

BOOT_NB1

BOOTX

32

13

PR383
0_0402_5%
2
1

CPU_B+

PHASE2

SVD

PR359
0_0603_5%
2
1UGATE3-1 4
PR360
PC376
2.2_0603_1% 0.22U_0603_25V7K
2
1 2
1

UGATE_NB2
PU28

UGATE2

+5VS

PR382 27.4K_0402_1%
2
1

+5VS

VR_HOT_L

ISEN3

12

UGATE_NB1

SVC

18

4
1 SVC
0_0402_5%
5
1
0_0402_5%
SVD
6
1
0_0402_5%
VDDIO
7
1
0_0402_5%
8
1 SVT
0_0402_5%
1 ENABLE 9
0_0402_5%
1 PWROK 10
0_0402_5%
11

17

PC383
1000P_0402_25V6
1
2

IMON_NB

ISUMP

<8,25> APU_PWRGD

NTC_NB

3

ISEN1

<37> VR_ON

2

16

<8> APU_SVT

+1.5VS
PR380
110K_0402_1%
1
2

ISEN2_NB

15

1

+1.5VS

1

2

PR352
10K_0402_1%

@

PHASE_NB1

6

ISEN2

2
<8> APU_SVD
@PR372
@
PR372
100K_0402_5%

2
PR366
2
PR367
2
PR371
2
PR374
2
PR375
2
PR377
2
PR378

1
2
PR395
11K_0402_1%

1
1
2

<8> APU_SVC

<8,25,37,44> EC_THERM#

PU27

@ PR362
10_0402_5%
2
1

+5VS

PH4
470K_0402_5%_TSM0B474J4702RE
2
1
PR368
10K_0402_1%

C

27.4K_0402_1%
2
1

1

PR363

PC377
1000P_0402_25V6

14

2

2

PC375
0.22U_0402_10V6K
2
1 ISEN2_NB

1

5

LGATE_NB1

PR351
10K_0402_1%
2
1

PR356
1_0402_1%
VSUMN_NB 2
1

2
1
PR357
42.2K_0603_1%

FCCM_NB

D

+CPU_CORE_NB

3

PR354
3.65K_0402_1%
VSUMP_NB 2
1

PC367
680P_0603_50V7K

2

PQ98
MDU1511RH_POWERDFN56-8-5
PR355
422_0402_1%
2
1

PC370
0.22U_0402_10V6K
2
1 ISEN1_NB

PR361
110K_0402_1%

4

B+

PC374
2200P_0402_50V7K
2
1

LGATE_NB1

21

2

ISEN1_NB

@ PC369
@ PR358
100_0402_1% 220P_0402_50V7K
2
1
2
1

PC368
0.1U_0603_50V7K

2
PR349
4.7_1206_5%

1
1 2

PC366
0.22U_0402_10V6K

2
1

PC365
0.022U_0402_16V7K
1
2

1
2
PR353
11K_0402_1%

PH3
10K_0402_5%_ERTJ0ER103J
2
12
1
PR350
2.61K_0402_1%

BOOT_NB1
2

1

VSUMN_NB

PR348
PC363
2.2_0603_1% 0.22U_0603_25V7K
2
1 2
1

PC373
0.01U_0402_25V7K
2
1

PC364
1000P_0402_50V7K

VSUMP_NB

PL34
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
4

PHASE_NB1

PC372
10U_1206_25V6M
2
1

PC362
100P_0402_50V8J
2
1

1

PR346
PC361
PR347
0_0402_5% 1000P_0402_50V7K 301_0402_1%
2
1
2
1
2
1

+
2

PC382
1U_0603_16V6K

+CPU_CORE_NB

PQ97
MDU1516URH_POWERDFN56-8-5

1

3
2
1

PR342
10_0402_5%
2
1

D

UGATE_NB1

5

PR343
3.01K_0402_1%
2
1

PR341
0_0603_5%
2
1UGATE_NB1-1 4

PL33
FBMA-L18-453215-900LMA90T_1812
2
1

PC349
2200P_0402_50V7K
2
1

PC360
PR344
@ PR345
137K_0402_1% 390P_0402_50V7K 32.4K_0402_1%
2
1
2
1
2
1

PC353
0.01U_0402_25V7K
2
1

PC348
PR340
330P_0402_50V7K 2K_0402_1%
2
1
2
1
<8> APU_VDDNB_SEN

PC352
10U_1206_25V6M
2
1

5

PC351
10U_1206_25V6M
2
1

CPU_B+

PC371
10U_1206_25V6M
2
1

4

PC387
2200P_0402_50V7K
2
1

5

2011/07/08

Deciphered Date

2015/07/08

Title

Compal Electronics, Inc.
SCHEMATIC,MB A8331

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019H2

Date:

5

4

3

2

Wednesday, February 29, 2012
1

Sheet

50

of

52

5

4

3

2

Version change list (P.I.R. List)
Item

D

Fixed Issue

Reason for change

Rev.

PG#

Modify List

1

Page 1 of 2
for PWR

Date

Phase

1

D

2

3
4
5
C

C

6

7

8
9
10
B

B

11
12
13
14
15
A

A

16

2011/07/08

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2015/07/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

SCHEMATIC,MB A8331
Rev
B

4019H2

Wednesday, February 29, 2012

Sheet
1

51

of

52

5

4

3

2

1

Version change list (P.I.R. List)
EVT Stage (0.1~0.2)

DVT Stage (0.2~0.3)

D

0817 Pop C1025 180p for VDDIO (SCL v1.02)
Change D16,D17 to SCS00000Z00
0818 Change Q50 from BSH138 to BSH111
Unpop R1100 for +1.1VALW
Add D26 BOM Structure for 930@
unpop D4 for USB issue
0903 1.Change Card Reader Controller to RTS5209
2.Change LAN to Atheros AR8151
3.Removed D17
0904 Add Mini2 Debug Port
0905 1.Add Fresco FL1009 USB3.0 Controller
C

P20. BACO BIFVDDC update
P25. remove Q25 APU power ok
0915 1.Remove EC X2
0916 1.Add C1361/C1362 10pF for EMI
2.Change D27/D29 footprint to AZ5125
3.Add R402 10k for reserved
4.Add R469/R527 for VGA Internal Thermal Senser
0926 1.Change D4 to SC300001G00 for ESD request
2.Change D33/D34/D37/D40/D41 to SCA00001A00 for ESD request

B

PVT Stage
D

1.Unpop C954, C955 for Mini2 reserved.
2.Remove R587, R588, Q11 for no need level shift.
3.Pop R469, R527
Unpop U9, R391, C352, C324
for VGA Internal Thermal Interface.
4.Unpop C374 330uF for Use discrete +1.5VSG circuit.
5.Add R1169 1k for RTS2132 Vender suggestion.
6.Reserved R1177 for option EEPROM.
7.Add R1178 for RTS2132 discrete +1.2VS power.
8.Reserved SMBUS(TL_CLK/TL_DATA) to EC for EEEPROM option.
9.Reserved BACO circuit and pop C1105.
10.Change D4, D6 to AZC099 for ESD reserved.
11.Change D20, D21 to AZC199-02SPR7G for ESD reserved.
12.Remove D44, D45 for no need.
13.Change C1211, R837 BOM to TL@.
14.Change JTP1 to 6P/8P co-lay footprint for WIN8.
15.Add SMBUS(FCH_SCLK1/FCH_SDATA1) for JTP1.
16.Reserved GPIO166 for future used.
17.Add H29 for ME update.
18.Add C1719, C1720 10pF for RTD5209 EMI request.
19.Change L1801 footprint.
20.Pop D42 and change to SCA00001A00 for ESD.
21.Change C1537 to 10pF 2KV for EMI/ESD.
22.Unpop C1336, C1337, C1338, C1333, C1334, C1335
for MINI2 Reserved.
23.Modify C1911 always pop for noise reduce.
24.Modify R60 to M3@.
25.Change Board ID to "02" for DVT.
26.Add Q30 for EC_THERM reverse for EC common code.
27.Change 9012_PH2 netname to 9012_VCIN for VC function.
28.Unpop R65 for External OTP.
29.Change L68 +5VS to +VDDA.
30.Chnage R1124 to 200k, R1130 to 10k for VGA Power Sequence.
31.Pop R997 for W/L BT combo card BT ON/OFF
32.Change U28 SPI ROM from MXIC to EON

C

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/07/08

Deciphered Date

2015/07/08

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

SCHEMATIC,MB A8331
Document Number

Rev
B

4019H2
Wednesday, February 29, 2012

Sheet
1

52

of

52

www.s-manuals.com



---

Source Exif Data:

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Create Date                     : 2013:04:13 02:38:36-04:00
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Modify Date                     : 2014:04:25 23:06:21+03:00
Metadata Date                   : 2014:04:25 23:06:21+03:00
Producer                        : iText® 5.4.0b ©2000-2012 1T3XT BVBA (ONLINE PDF SERVICES (ONLINE PDF SERVICES; licensed version)
Format                          : application/pdf
Title                           : Compal LA-8331P - Schematics. www.s-manuals.com.
Creator                         : 
Subject                         : Compal LA-8331P - Schematics. www.s-manuals.com.
Document ID                     : uuid:ada88d72-1500-4bbe-a4b3-14ec7149118e
Instance ID                     : uuid:4415dcee-cdfc-42ae-9428-9e74c2021961
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Keywords                        : Compal, LA-8331P, -, Schematics., www.s-manuals.com.
Warning                         : [Minor] Ignored duplicate Info dictionary

EXIF Metadata provided by EXIF.tools