Compal LA 8661P Schematics. Www.s Manuals.com. R0.1 Schematics

User Manual: Motherboard Compal LA-8661P Lotus - Schematics. Free.

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Compal Confidential

2

2

Lotus M/B Schematics Document
14": Elise; 15.6" Exige

Intel Ivy Bridge ULV Processor with DDRIII + Panther Point

Date : 2011/10/27
Version 0.1

3

3

4

4

2011/06/29

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/06/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

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Title

Block Diagrams
Size Document Number
Custom

Rev
0.1

LA-8551P

Date:

Friday, March 02, 2012

Sheet
E

1

of

55

A

B

C

D

E

Compal Confidential
Model Name : Lotus
1

128Mx16

2011/11/01

PEG 3.0 x16
(2 x8)

AMD

VRAMx8pcs

128Bit

DDRIII
P28, P29

DDR3 1333/1600MHz 1.5V
DDR3L 1333MHz 1.35V

Intel
IVY Bridge

File Name : LA8661P

BANK 0, 1, 2, 3

P12, P13

Dual Channel

ULV Processor
FCBGA 1023

Thames-XT
25W

1

DDR3-SO-DIMM X 2

31mm*24mm

P22~ P29

P5~ P11

FDI x8
HDMI Conn.

LVDS Conn.

DDPB port
P30

DMI x4

100MHz

100MHz

2.7GT/s

5GT/s

port1,3 port0,2 P35

2

100MHz

X1

X1

X1

port1

P34

JMINI1
WLAN&BT
(mini card)

port1

P31

port5

port9
X1

RJ45

3

2

3.3V 24MHz

port8

HD webcam
SPI

D-MIC(daul)

HDA Codec
LPC BUS

SATA HDD

IDT 92HD91

BIOS SPI ROM,
4MB +2 MB

P38

P14

33MHz

P33

X1

3.3V 48MHz

HD Audio

P14~ P21

port0

JMINI2
m-SATA
(mini card)

X2

X1

25mm*25mm

(GEN1 1.5Gb/S
GEN2 3Gb/S
GEN3 6Gb/S)
port0

USB 2.0 x4

PCH
989pin BGA

100MHz

SATAx2

X2

USB 3.0 x2

Intel
Panther Point

PCI-Express x 8 (PCIE2.0 5GT/s)

X1

USB2.0 x1 port1
USB charger

USB3.0 x2

P32

LVDS(1Ch/2ch)
HDMI

Card Reader
/LAN controller
RTL8411

Daughter board

P33

SPK conn

X1

P41

USB 2.0 x2

SD socket

Sub Woofer
Amp
P39

HP Amp

Sub Woofer
conn P39

HP&MIC
jack S/B

P40
3

P34

TPM1.2
SLB9635/9656

Daughter board

Accelerometer
HP3DC2 P42

P42

Daughter board

FAN conn.
P37

Touch pad daughter board

ENE KB932
P36

4

PS2

LED

P37

RTC CKT.

P14

Power On/Off CKT.

Lid switch
S/B

Touch Pad
P37

SPI

Int.KBD
P37

EC ROM,
256kB P36

FAN/LED
P37
4

P37

SM_BUS
(PCH)

DC/DC interface CKT.P43

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/29

2011/06/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Block Diagrams
Size Document Number
Custom

Rev
0.1

LA-8551P

Date:

Sheet

Friday, March 02, 2012
E

2

of

55

A

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QAU30/50 (LA-8661P Ver:0.1)

2

S1

Description

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

BATT+

Battery power supply (12.6V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

ON

OFF

OFF

+VGFX_CORE

Core voltage for UMA graphic

ON

OFF

OFF

+0.75VS

+0.75VP to +0.75VS switched power rail for DDR terminator

ON

OFF

OFF

+1.05VS_VCCP

+V1.05SP to +1.05VS_VCCP switched power rail for CPU

ON

OFF

OFF

+VCCP (1.05V ) power for PCH

ON

OFF

OFF

+VCCP

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

+1.5V

+1.5VP to +1.5V power rail for DDRIII (1.35V OR 1.5V)

ON

ON

OFF

+1.5VS

+1.5VS switched power rail

ON

OFF

OFF

E

+VALW

+V

+VS

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

Full ON

Power Plane

1

SIGNAL

STATE

Voltage Rails

D

Clock
ON

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

Power Plane

Description

S1

S3

S5

+VGA_CORE

GPU power

PX

OFF

OFF

+3VGS

GPU power

PX

OFF

OFF

+1.8VGS

GPU power

PX

OFF

OFF

+1.5VGS

GPU power

PX

OFF

OFF

+1.0VGS

GPU power

PX

OFF

OFF

+1.8VS

(+5VALW ) to 1.8V switched power rail to PCH

ON

OFF

OFF

+3VALW

+3VALW always on power rail

ON

ON

ON*

+3VALW_EC

+3VALW always to KBC

ON

ON

ON*

+LAN_IO

+3VALW to +LAN_IO power rail for LAN

ON

ON

+3V_PCH

+3VALW to +3V_PCH power rail for PCH (Short Jumper)

ON

ON

ON*

+3VS

+3VALW to +3VS power rail

ON

OFF

OFF

+5VALW

+5VALWP to +5VALW power rail

ON

ON

ON*

Device

+5V_PCH

+5VALW to +5V_PCH power rail for PCH (Short resister)

ON

ON

ON*

Smart Battery

+5VS

+5VALW to +5VS switched power rail

ON

OFF

OFF

G-sensor

+VSB

B+ to +VSB always on power rail for sequence control

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

1

ON*

EC SM Bus1 address
EC SM Bus2 address

Address

Address

Device

0x50/0x52

PCH (Reserve)
2

PCH SM Bus address
Device

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Address

DDR DIMM0
DDR DIMM1

CLKOUT DESTINATION

Mini Card1
Mini Card2
TP module

PCI0

PCH_LPBACK

PCI1

PCI_LPC

SMBUS Control Table

SOURCE

3

EC_SMB_CK1
EC_SMB_DA1

KB930

EC_SMB_CK2
EC_SMB_DA2

KB930

PCH_SMBCLK
PCH_SMBDATA

PCH

PCH_SML0CLK
PCH_SML0DATA

PCH

PCH_SML1CLK
PCH_SML1DATA

PCH

BATT

WLAN
MIINI1

V

BATT
Charger

TP

EC_SMB_CK2

SODIMM

EC_SMB_DA2

PCH_SML1CLK
PCH_SML1DATA

G-Sensor

HP AMP

V

V
V
V

@

GPU

V

V

None

PCI4

None

USB Port Table

V
DESTINATION

CLKOUT_PCIE0

PCIE LAN
CARD READER

FLEX CLOCKS

DESTINATION

CLKOUTFLEX0

None

CLKOUTFLEX1

None

CLKOUTFLEX2

None

TPM

9656@

CPUUMA1@
CPUUMA2@
CPUDIS@
VRAM

X76@

None

CLKOUT_PCIE4

None

CLKOUT_PCIE5

None

UHCI1
EHCI1

SATA2

None

SATA3

None

UHCI3

SATA4

None

UHCI4

SATA5

None

UHCI2

H2G@
S2G@

EHCI2

DGPU_PRSNT#

UHCI5
UHCI6

Option










CLKOUT_PCIE3

CLKOUTFLEX3










None

UHCI0

USB30@

PX@

UMA

@
X

CONN@
X

V

X

UMA@
V

DIS@
X

X

DIS

X

X

V

V

X

V

V

THA@

USB 3.0

CLKOUT_PCIE6

None

CLKOUT_PCIE7

None

CLKOUT_PEG_B

None

Project ID

30UMA@

30DIS@

50UMA@

LA-8661P
PX@

A

B

Camera
Mini Card(WLAN& BT)

None
None
None
None
2 External
USB Port
USB3.0 (left Side)

LA-8662P

Issued Date

None
Compal Electronics, Inc.

Compal Secret Data
2011/06/29

Deciphered Date

2011/06/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

UMA@
C

D

4

None
USB3.0 (left Side)

4

50DIS@

3

None
None
None
None
None

1
2
3

Security Classification

PCB

0
1
2
3
4
5
6
7
8
9
10
11
12
13
Port








CLKOUT_PCIE2

3 External
USB Port
USB2.0 (left Side)
USB2.0 (right Side)
USB2.0 (left Side)

USB 2.0 USB 1.1 Port

SATA1 m-SATA,JMINI2

9635@

CPU

mini WLAN

DESTINATION

SATA0 SATA, JHDD1

M2G@

4

PCI3

V

BY SKU

CLK

None

SATA

DIFFERENTIAL

CLKOUT_PCIE1

PCI2

Title

Notes List
Size
C
Date:

Document Number

Rev
0.1

LA-8661P
Friday, March 02, 2012

Sheet
E

3

of

55

5

4

3

2

1

D

D

C

C

B

B

A

A

Compal Secret Data

Security Classification
Issued Date

2011/06/29

Deciphered Date

2011/06/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

PROCESSOR(1/7) DMI,FDI,PEG
Size
B
Date:

Document Number
Friday, March 02, 2012

Rev
0.1
Sheet
1

4

of

55

5

4

3

2

UCPU1 CPUDIS01@
i5-2467M CPU
SA00004X000

PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms

Sandy Bridge:
Intel Core i5-2467M: SA00004X000 (4619HY32L01)
UCPU1 CPUDIS02@
i5-2367M CPU
SA000051H20
UCPU1 CPUUMA3@
i5-2367M CPU
SA000051H20

UCPU1 CPUUMA1@
17W 1.5GHz GT2 ES2 QBP8
SA00005AZ10

UCPU1 CPUUMA4@
17W 1.7GHz GT2 ES2 QBP7
SA00005B010

UCPU1 CPUUMA2@
17W 1.5GHz no cnfg ES2 QBTP
SA00005AZ20

Ivy Bridge:
1.5GHz GT2 ES2 QBP8: SA00005AZ10 (4619HZ32L01)
1.5GHz ES2 QBTP: SA00005AZ20(4619HZ32L02)

1

+VCCP

D

1

D

UCPU1 CPUDIS04@
i5-3317U CPU
SA00005K600

M2
P6
P1
P10

<16> DMI_CRX_PTX_P0
<16> DMI_CRX_PTX_P1
<16> DMI_CRX_PTX_P2
<16> DMI_CRX_PTX_P3

N3
P7
P3
P11

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

K1
M8
N4
R2

<16>
<16>
<16>
<16>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

K3
M7
P4
T3

<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

U7
W11
W1
AA6
W6
V4
Y2
AC9

<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

U6
W10
W3
AA7
W7
T4
AA3
AC8
AA11
AC12

<16> FDI_FSYNC0
<16> FDI_FSYNC1

U11

1

2

<16> FDI_INT

B

RC2
24.9_0402_1%

AA10
AG8

<16> FDI_LSYNC0
<16> FDI_LSYNC1

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC

eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms

EDP_COMP

AF3
AD2
AG11
AG4
AF4
AC3
AC4
AE11
AE7
AC1
AA4
AE10
AE6

eDP_AUX#
eDP_AUX
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

eDP

NOTE:eDP_COMPIO and eDP_ICOMPO
should not be left floating even if Internal
Graphic is disabled since they are shared
with other interfaces

eDP_COMPIO
eDP_ICOMPO
eDP_HPD#

2

PEG_COMP

2

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

2

1

RC88 @
10K_0402_5%

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

G3
G1
G4

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

Intel(R) FDI

+VCCP

<16>
<16>
<16>
<16>

1

@

DMI

C

UCPU1A

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

<16>
<16>
<16>
<16>

UCPU1 CPUUMA5@
17W 1.7GHz no cnfg ES2 QBTQ
SA00005B020

RC1
24.9_0402_1%

PCI EXPRESS -- GRAPHICS

UCPU1 CPUDIS03@
i5-2367M CPU
SA000051H20

CU65
0.1U_0402_16V4Z

Add CU65 0.1U as EMI request.
12.19



K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

C

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]



F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

B

10/05 Change to 0.22uF.

IVY-BRIDGE_BGA1023

Typ- suggest 220nF. The change in AC capacitor
value from 180nF to 265nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)

A

A

Compal Secret Data

Security Classification
Issued Date

2011/06/29

2011/06/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number
Custom

Rev
0.1

LA-8661P

Date:

Sheet

Friday, March 02, 2012
1

5

of

58

4

3

2

Buffered reset to CPU

+3VS

+VCCP
CC1
0.1U_0402_16V4Z

5

2

NC

4

Y

PLT_RST# 2

G

A

2
BUFO_CPU_RST#

2

1 BUF_CPU_RST#
43_0402_1%

SN74LVC1G07DCKR_SC70-5

D

RC6 @
750_0402_1%
2

3

<17,22,31,34,36,42> PLT_RST#

Reset# signal is driven by the PCH to multiple agents on the platform.
PCH Reset# output DC levels are 0-V and 3.3 V,
processor Reset input DC levels are 0V and 1.0 V.
Processor high-voltage level is lower than PCH high voltage level,
therefore a voltage level shifter is required on the Reset# signal.
In order for Reset# to meet the signal quality requirement at the input to
the processor OD buffer must be placed on the motherboard between
the PCH and the processor.

RC4

P

1
D

RC3
75_0402_5%

UC1

1

1

1

1

5

R375 @
0_0402_5%
1
2

Requires a series resistor of 43±5% between processor and PCH.
It also a needs an Rtt of 75±5% to VCCP after the OD
buffer and before the series resistor.

2
C57
10K_0201_5%

PAD

+VCCP

PROC_DETECT#

T5 @

C49

H_PROCHOT#

A48

<18,36> H_PECI

H_PROCHOT# 1
RC10

<36,46> H_PROCHOT#

1

<18> H_THRMTRIP#

C

PECI

2 H_PROCHOT#_R C45
56_0402_5%

1 10K_0201_5% H_CPUPWRGD_R

2

2

THERMAL

1 62_0402_5%

2

BCLK
BCLK#

PROCHOT#

H_THEMTRIP#_R D45

SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

THERMTRIP#



UNCOREPWRGOOD:
PM_SYS_PWRGD_BUF 1
RC18

PM_SYNC

B46

UNCOREPWRGOOD




RC16 0_0201_5%
1
2 H_CPUPWRGD_R

H_CPUPWRGD

CORE

OK

2 PM_DRAM_PWRGD_R BE45
130_0402_5%

SM_DRAMPWROK

SM_DRAMPWROK:DRAM power ok
BUF_CPU_RST#

D44

RESET#

TCK
TMS
TRST#

JTAG & BPM

<16> H_PM_SYNC

SI2 change to 0201
<18>
12.19

C48

PWR MANAGEMENT

SI2 change to 0201
12.19
H_PM_SYNC_R
2
0_0201_5%

RC85
RC84

AG3
AG1

1 1K_0402_5%
1 1K_0402_5%

2
2

+3VS
2

1 1K_0201_5%

+VCCP

SI2 change to 0201
12.19

PRDY#
PREQ#

1
RC13

100MHz

CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>

XDP_DBRESET# RC5
DPLL_REF_CLK
DPLL_REF_CLK#

RC12 0_0402_5%

SI2 change to 0201
12.19

J3
H2

CATERR#

Processor Pullups

RC8

RC11

1
@ RC7

SI2 change to 0201
12.19

DDR3
MISC

PROC_DETECT (Processor Detect): pulled to
ground on the processor package. There is no
connection to the processor silicon for this
signal. System board designers may use this
signal to determine if the processor is present

PROC_SELECT#

MISC

F49

<18> H_SNB_IVB#

CLOCKS

UCPU1B @
This pin is for compability with future
platforms. A pull up resistor to VCCIO is
required if connected to the DF_TVS strap
on the PCH.

TDI
TDO

DBR#

AT30 H_DRAMRST#
BF44
BE43
BG43

H_DRAMRST# <7>

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

PAD
T35
PAD @
T39
N53 @
N55
L56
L55
J58

C

XDP_TCK
XDP_TMS
XDP_TRST#

M60 XDP_TDI
L59 XDP_TDO

K58

XDP_DBRESET#_R 1 RC17

2 0_0201_5%

XDP_DBRESET#

XDP_DBRESET# <16>

12/16:Change to 0201 for SI2
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

G58
E55
E59
G55
G59
H60
J59
J61

XDP_BPM#4_R
XDP_BPM#5_R
XDP_BPM#6_R
XDP_BPM#7_R

T60
T61
T62
T63

@ PAD
@ PAD
@ PAD
@ PAD

2011.10.18 delete all reserved XDP conponent.
Just reserve test point for XDP.

IVY-BRIDGE_BGA1023
+3VS
+3V_PCH
2

DDR3 Compensation Signals

1

CC2
0.1U_0402_16V4Z

2

RC25
200_0402_5%

UC2
74AHC1G09GW_TSSOP5

1
2

<16> PM_DRAM_PWRGD

B

O
A

4

1
3

1

@
RC29
39_0402_5%

2

<43,52>

SUSP

SUSP

1 2

Part Number = SA00003Y000

D

3

200_0402_5%

11.06 Change to +3V_PCH

1 140_0402_1%

2

1 25.5_0402_1%

SM_RCOMP2 RC26

2

1 200_0402_1%

PU/PD for JTAG signals

PM_SYS_PWRGD_BUF

RC28
+3V_PCH

2

SM_RCOMP1 RC24

2

5

@ RC27
0_0402_5%
1
2

SM_RCOMP0 RC23

P

<16> SYS_PWROK

+1.5V_CPU_VDDQ

1

1

RC81
10K_0402_5%

G

B

S

2
G

@
QC1
2N7002_SOT23

XDP_TMS

T40 @ PAD

XDP_TDI

T41 @ PAD

XDP_TDO

T42 @ PAD

XDP_TCK

T43 @ PAD

XDP_TRST#

T46 @ PAD

SI2 change to 0201
12.19
C263
XDP_TRST#
1
C264
PLT_RST#
1
C265 @
PM_SYS_PWRGD_BUF1
C266
BUF_CPU_RST#
1

0.1U_0201_16V4Z
2
220P_0402_50V7K
2
100P_0402_50V8J
2
220P_0402_50V7K
2

XDP_DBRESET#_R

CC4

2

1 0.1U_0201_16V4Z

H_CPUPWRGD_R

C118 1

2 220P_0402_50V7K

B

SI2 change to 0201
12.19
6/27 Add ESD solution

2011.10.18 delete all reserved XDP conponent.
Just reserve test point for XDP.

A

A

Compal Secret Data

Security Classification
Issued Date

2011/06/29

Deciphered Date

2011/06/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Compal Electronics, Inc.

Title

PROCESSOR(2/7) PM,XDP,CLK
Size
C
Date:

Document Number

Rev
0.1

LA-8041P
Friday, March 02, 2012

Sheet
1

6

of

58

5

4

3

2

1

UCPU1C @
UCPU1D @

<12> DDR_A_D[0..63]

C

B

<12> DDR_A_BS0
<12> DDR_A_BS1
<12> DDR_A_BS2

BD37
BF36
BA28

<12> DDR_A_CAS#
<12> DDR_A_RAS#
<12> DDR_A_WE#

BE39
BD39
AT41

<13> DDR_B_D[0..63]

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

AU36
AV36
AY26

M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>

AT40
AU40
BB26

M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>

BB40
BC41

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

AY40
BA41

M_ODT0 <12>
M_ODT1 <12>

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

<12>
<12>

<12>

<12>

<12>

AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60

<13> DDR_B_BS0
<13> DDR_B_BS1
<13> DDR_B_BS2

BG39
BD42
AT22

<13> DDR_B_CAS#
<13> DDR_B_RAS#
<13> DDR_B_WE#

AV43
BF40
BD45

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

BA34
AY34
AR22

M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE0_DIMMB <13>
D

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

DDR SYSTEM MEMORY B

D

AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

DDR SYSTEM MEMORY A

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

BA36
BB36
BF27

M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE1_DIMMB <13>

BE41
BE47

DDR_CS0_DIMMB#
DDR_CS1_DIMMB#

AT43
BG47

M_ODT2 <13>
M_ODT3 <13>

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_DQS#[0..7]

<13>
<13>

<13>

C

DDR_B_DQS[0..7]

<13>

DDR_B_MA[0..15]

<13>

B

IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023

@ RC35
0_0402_5%
1
2

H_DRAMRST#

3

reset

RC36
1K_0402_5%
RC37
1K_0402_5%
2

2

DIMM

1

!



+1.5V

CPU

D

S

DDR3_DRAMRST#_R
1
QC2
BSS138_NL_SOT23-3

2

<6> H_DRAMRST#

RC39
0_0402_5%
1
2

<10,15,36> DRAMRST_CNTRL_PCH

DDR3_DRAMRST#

<12,13>

S0
DRAMRST_CNTRL_PCH hgih ,MOS ON
9/7 Folllow PAJ80 BOM by Light H_DRAMRST# HIGH,DDR3_DRAMRST# HIGH
del: SB501380020
Dimm not reset
add: SB00000QO00
S3
DRAMRST_CNTRL_PCH Low ,MOS OFF
H_DRAMRST# lo,DDR3_DRAMRST# HIGH
Dimm not reset
S4,5
1
DRAMRST_CNTRL_PCH Low ,MOS OFF
H_DRAMRST# lo,DDR3_DRAMRST# low
CC3
Dimm reset
0.047U_0402_16V4Z

2

1

A

G

RC38
4.99K_0402_1%

1

DRAMRST_CNTRL

A

Compal Secret Data

Security Classification
Issued Date

2011/06/29

2011/06/29

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Compal Electronics, Inc.
PROCESSOR(3/7) DDRIII

2

Size Document Number
Custom

Rev
0.1

LA-8041P

Date:

Sheet

Friday, March 02, 2012
1

7

of

58

5

4

3

2

1

CFG Straps for Processor

1

PEG bus is reversed, need to PD.
11.01
CFG2
RC40 SI2 change to 0201
12.19

2

RC40
1K_0201_1%
D

D

Change to part G.
PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane #
socket pin map definition

*

CFG2

definition matches

0:Lane Reversed

1

CFG4

RC41 @
1K_0201_1%

+CPU_CORE

RC44

1
2
RC45

+VGFX_CORE

VCC_VAL_SENSEH43
249.9_0402_1%
VSS_VAL_SENSE K43
1
49.9_0402_1%

2 49.9_0402_1% VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
1
49.9_0402_1%

H45
K45
F48

RC47 @
1K_0201_1%

2

2

@ RC46
1K_0201_1%
B

H48
K48

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_DIE_SENSE

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

N42
L42
L45
L47

*

CFG4

C

1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

M13
M14
U14
W14
P13

CFG6

RSVD39
RSVD40

AT49
K24

RSVD41
RSVD42
RSVD43
RSVD44

CFG5

AH2
AG13
AM14
AM15

RC48 @
1K_0201_1%

RSVD45

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1

RC48, RC49 SI2 change to 0201
12.19
RC49 @
1K_0201_1%

Change CFG[6:5] to 11 = 1 x 16 PCI Express
because AMD driver can't install issue
11.21

N50

PCIE Port Bifurcation Straps

A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1

00
01
10
11

CFG[6:5]

=
=
=
=

1 x 8, 2 x 4 PCI Express
reserved
2 x 8 PCI Express
1 x 16 PCI Express

B

*
12/16:Change to 0201 for SI2 because standoff PAD
CFG7

RC50 @
1K_0201_1%

2

12/16:Change to 0201 for SI2 because standoff PAD

BA19
AV19
AT21
BB21
BB19
AY21
BA22
AY22
AU19
AU21
BD21
BD22
BD25
BD26
BG22
BE22
BG26
BE26
BF23
BE24

CLK_RES_ITP <15>
CLK_RES_ITP# <15>

Display Port Presence Strap
RSVD30
RSVD31
RSVD32
RSVD33

RSVD6
RSVD7

1

1

CPU_RSVD6
CPU_RSVD7

VCC_VAL_SENSE
VSS_VAL_SENSE

N59
N58

1

1
2
RC43

BCLK_ITP
BCLK_ITP#

1

RC42

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

2

2011.10.18 delete XDP resistor
just reserve test point for XDP.

T7
T8
T14
T15
T16
T47
T48
T58
T59
T17
T18

B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53

2

C

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

RC41 SI2 change to 0201
12.19

1

T11

RESERVED

T9
T6

2

UCPU1E @

Delete T12, T13, T10
12.21

IVY-BRIDGE_BGA1023

PEG DEFER TRAINING

CFG7

*

1: (Default) PEG Train immediately following
xxRESETB de assertion
0: PEG Wait for BIOS for training

A

Compal Secret Data

Security Classification
Issued Date

2011/06/29

2011/06/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

A

Compal Electronics, Inc.
PROCESSOR(4/7) RSVD,CFG

Size Document Number
Custom
Date:

Rev
0.1

LA-8661P
Sheet

Friday, March 02, 2012
1

8

of

58

5

4

3

UCPU1F

2

1

POWER
+VCCP

+CPU_CORE

PEG IO AND DDR IO

D

AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

C

+VCCP
+VCCP
RC51

W16
W17

1

1

VCCIO50
VCCIO51

2

RC52 @
75_0402_5%

0_0805_5%

VCCIO_SEL

BC22

VCCP_PWRCTRL_R

110K_0402_5%
2
@ RC53

choose low or high

CPU EDS descript as follow:
For Chief River platforms this pin
should not be used.

+VCCP
+1.05VS_VCCPQ

VCCPQE[1]
VCCPQE[2]

B

+VCCP

RC54

AM25
AN22

1
2
0_0805_5%

RC56
75_0402_5%

2
1U_0402_6.3V6K

SVID

2

1
CC73

1

B

AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48

2

C

VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]

QUIET
RAILS

D

VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]
VCC[26]
VCC[27]
VCC[28]
VCC[29]
VCC[30]
VCC[31]
VCC[32]
VCC[33]
VCC[34]
VCC[35]
VCC[36]
VCC[37]
VCC[38]
VCC[39]
VCC[40]
VCC[41]
VCC[42]
VCC[43]
VCC[44]
VCC[45]
VCC[46]
VCC[47]
VCC[48]
VCC[49]
VCC[50]
VCC[51]
VCC[52]
VCC[53]
VCC[54]
VCC[55]
VCC[56]
VCC[57]
VCC[58]
VCC[59]
VCC[60]
VCC[61]
VCC[62]
VCC[63]
VCC[64]
VCC[66]
VCC[67]
VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]

CORE SUPPLY

A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38

VCCIO[1]
VCCIO[3]
VCCIO[4]
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]

VIDALERT#
VIDSCLK
VIDSOUT

A44
B43
C44

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

RC57 1
RC58 1
RC59 1

2
2
2

43_0402_1%
0_0402_5%
0_0402_5%

VR_SVID_ALRT# <54>
VR_SVID_CLK <54>
VR_SVID_DAT <54>

+CPU_CORE

0_0402_5%
0_0402_5%

VCCSENSE <54>
VSSSENSE <54>

2
10_0402_1%

+VCCP

AN16 VCCIO_SENSE_R
AN17 VSS_SENSE_VCCIO

2

2011/06/29

2011/06/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

Place the PU
resistors close to VR
A

10/05 mount.
(follow check list)

Compal Secret Data

Security Classification

RC64
100_0402_1%

VCCIO_SENSE <51>
VSS_SENSE_VCCIO <51>
RC66
10_0402_1%

IVY-BRIDGE_BGA1023

Issued Date

1

2
2

Place the PU
resistors close to CPU

1

RC61 1
RC62 1
RC63

VCCIO_SENSE
VSS_SENSE_VCCIO

A

F43 VCCSENSE_R
G43 VSSSENSE_R

2
100_0402_1%

2

VCC_SENSE
VSS_SENSE

1

SENSE LINES

1
RC60

2

Title

Compal Electronics, Inc.
PROCESSOR(5/7) PWR,BYPASS

Size Document Number
Custom

Rev
0.1

LA-8661P

Date:

Sheet

Friday, March 02, 2012
1

9

of

58

5

4

+1.5V

2

1 0.1U_0402_10V7K

CC75

2

1 0.1U_0402_10V7K

1

"

Can connect to GND if motherboard only
supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
VAXG can be left floating in a common
motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed
UCPU1G

+1.5V_CPU_VDDQ

POWER

RC67
0_0402_5%
2
1

+V_SM_VREF should
have 20 mil trace width

+VGFX_CORE

1

CC74

2

"

+1.5V_CPU_VDDQ

3

RC68
1K_0402_1%

2

1

2

A

2

1

2

1U_0402_6.3V6K
CC133

2

1

1U_0402_6.3V6K
CC132

2

1

1U_0402_6.3V6K
CC131

1

1U_0402_6.3V6K
CC130

2

1U_0402_6.3V6K
CC129

1

1

2

2

1

2

2

1

+3VALW

1

2

1

2

+1.5V_CPU_VDDQ

1
2
3

5

4

2

1

C

QC4
AON6718L_DFN8-5

RC70
100K_0402_5%

3

RUN_ON_CPU1.5VS3

@

1

2
RUN_ON_CPU1.5VS3# 5

4

6

<36,43,49,50,51> SUSP#

@ RC75
0_0402_5%
1
2

+1.5V_CPU_VDDQ Source

2N7002DWH_SOT363-6
QC5B
RC73
330K_0402_5%

RC71
470_0603_5%
R78

1
CC118
2 0.1U_0402_25V6

2

2N7002DWH_SOT363-6
QC5A

2

RUN_ON_CPU1.5VS3#

Q10A
2N7002DWH_SOT363-6

1

<36> CPU1.5V_S3_GATE

RC74
0_0402_5%
1
2

1
2

1

2

1

1

2

6

1

1

2

20K_0402_5%
2
1

1

1

SI# BOM Change CC118 0.1u 25V form 0.1u 16V

VCCDQ[1]
VCCDQ[2]

Follow DG 0.71 page 6

AM28
AN26

B

1U_0402_6.3V6K

1

2

CC119

VDDQ_SENSE
VSS_SENSE_VDDQ

BC43
BA43

VCCSA_SENSE <53>

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

U10 VCCSA_SENSE

D48
D49

1
@ RC78

VCCSA_VID0
VCCSA_VID1

2
0_0402_5%
VID[0]
0
0
1
1

VCCSA_VID0 <53>
VCCSA_VID1 <53>

VID[1]
0
1
0
1

0.90 V
0.80 V
0.725 V
0.675 V

2011
Yes
Yes
No
No

2012
Yes
Yes
Yes
Yes
A

IVY-BRIDGE_BGA1023

Compal Secret Data

Security Classification
Issued Date

Delete CC25 330U cap 10.19
(after check with power)
5

2

+1.5V

2

QUIET RAILS

SENSE
LINES

VCCSA[1]
VCCSA[2]
VCCSA[3]
VCCSA[4]
VCCSA[5]
VCCSA[6]
VCCSA[7]
VCCSA[8]
VCCSA[9]
VCCSA[10]
VCCSA[11]
VCCSA[12]
VCCSA[13]
VCCSA[14]
VCCSA[15]
VCCSA[16]

SENSE LINES

10U_0603_6.3V6M
CC24

2

10U_0603_6.3V6M
CC21

10U_0603_6.3V6M
CC22

10U_0603_6.3V6M
CC20

10U_0603_6.3V6M
CC23

2

1

L17
L21
N16
N20
N22
P17
P20
R16
R18
R21
U15
V16
V17
V18
V21
W20

VCCPLL[1]
VCCPLL[2]
VCCPLL[3]

VCCSA VID
lines

2

BB3
BC1
BC4

1.8V RAIL

1

+VCCSA

2

1

+VSB

+1.5V_CPU_VDDQ

SA RAIL

2

CC122
1U_0402_6.3V6K

1

2

CC121
1U_0402_6.3V6K

10U_0603_6.3V6M
CC26

1

1

VAXG_SENSE
VSSAXG_SENSE

2
10_0402_1%

+1.8VS_VCCPLL

1

2

2

VREF
- 1.5V RAILS

3
1
3

F45
G45

RC77
0_0805_5%
2

1

1

RC72
100K_0402_5%

2 10_0402_1%

1
RC87

+VCCSA

2

CC99
10U_0603_6.3V6M

RC86 1

1

1

RC76
0_0603_5%

<54> VCC_AXG_SENSE
<54> VSS_AXG_SENSE

+1.8VS

2

QC4 Change to SA0000JA00 for small package
1016

+VGFX_CORE

B

1

CC98
10U_0603_6.3V6M

2

+1.5V_CPU_VDDQ

CC97
10U_0603_6.3V6M

1

CC96
10U_0603_6.3V6M

2

CC95
10U_0603_6.3V6M

1

CC94
10U_0603_6.3V6M
CC93
10U_0603_6.3V6M

2

1U_0402_6.3V6K
CC92

10/03 add +V_DDR_REFB

1

D

RC69
1K_0402_1%

1
RUN_ON_CPU1.5VS3

Check with Power Team
CC100 (330UF) can be taken off.
10.31

AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

1U_0402_6.3V6K
CC91

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]
VDDQ[9]
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]

+V_SM_VREF

3

@ QC3
AP2302GN-HF_SOT23-3

1

2

1U_0402_6.3V6K
CC90

For Chief River only

CC79
0.1U_0402_16V4Z

1U_0402_6.3V6K
CC89

+V_DDR_REFB_R

1 RC83
2
@
1K_0402_1%

+V_DDR_REFA_R
+V_DDR_REFB_R

10/03 add +V_DDR_REFB

1U_0402_6.3V6K
CC88

S
RC82
1
2
@ 0_0402_5%

2

1U_0402_6.3V6K
CC87

SB000002X00
BSS138W-7-F_SOT323-3
2 DRAMRST_CNTRL_PCH
G

BE7
BG7

+V_SM_VREF_CNT

1U_0402_6.3V6K
CC86

D

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

AY43

1U_0402_6.3V6K
CC85

+V_DDR_REFA_R

1 RC14
2
@
1K_0402_1%

QC8

+V_DDR_REFB

<7,15,36>

S
RC15
1
2
@ 0_0402_5%

C

DRAMRST_CNTRL_PCH

SM_VREF

DDR3

+V_DDR_REFA

SB000002X00
BSS138W-7-F_SOT323-3
2 DRAMRST_CNTRL_PCH
G

VAXG[1]
VAXG[2]
VAXG[3]
VAXG[4]
VAXG[5]
VAXG[6]
VAXG[7]
VAXG[8]
VAXG[9]
VAXG[10]
VAXG[11]
VAXG[12]
VAXG[13]
VAXG[14]
VAXG[15]
VAXG[16]
VAXG[17]
VAXG[18]
VAXG[19]
VAXG[20]
VAXG[21]
VAXG[22]
VAXG[23]
VAXG[24]
VAXG[25]
VAXG[26]
VAXG[27]
VAXG[28]
VAXG[29]
VAXG[30]
VAXG[31]
VAXG[32]
VAXG[33]
VAXG[34]
VAXG[35]
VAXG[36]
VAXG[37]
VAXG[38]
VAXG[39]
VAXG[40]
VAXG[41]
VAXG[42]
VAXG[43]
VAXG[44]
VAXG[45]
VAXG[46]
VAXG[47]
VAXG[48]
VAXG[49]
VAXG[50]
VAXG[51]
VAXG[52]
VAXG[53]
VAXG[54]
VAXG[55]
VAXG[56]

GRAPHICS

1

QC7
D

AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46
N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59
W50
W51
W52
W53
W55
W56
W61
Y48
Y61

2

D

4

2011/06/29

2011/06/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title

Compal Electronics, Inc.
PROCESSOR(6/7) PWR

Size Document Number
Custom

Rev
0.1

LA-8661P

Date:

Sheet

Friday, March 02, 2012
1

10

of

58

5

4

3

2

1

UCPU1H

D

C

B

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]

VSS

VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

UCPU1I
D

BG17
BG21
BG24
BG28
BG37
BG41
BG45
BG49
BG53
BG9
C29
C35
C40
D10
D14
D18
D22
D26
D29
D35
D4
D40
D43
D46
D50
D54
D58
D6
E25
E29
E3
E35
E40
F13
F15
F19
F29
F35
F40
F55
G51
G6
G61
H10
H14
H17
H21
H4
H53
H58
J1
J49
J55
K11
K21
K51
K8
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61
M11
M15

VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]

VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]

VSS

NCTF

A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53
A9
AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56
AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46
AC6
AD17
AD20
AD4
AD61
AE13
AE8
AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61
AG7
AH4
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AJ7
AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
AM34

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59
G48

C

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

B

IVY-BRIDGE_BGA1023

IVY-BRIDGE_BGA1023

A

A

Compal Secret Data

Security Classification
Issued Date

2011/06/29

2011/06/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PROCESSOR(7/7) VSS

Size Document Number
Custom

Rev
0.1

LA-8041P

Date:

Sheet

Friday, March 02, 2012
1

11

of

58

5

4

3

2

1

DDR3 SO-DIMM A
+V_DDR_REFA

+1.5V

+1.5V

3.56A@+1.5V
JDDRL1
+V_DDR_REFA

1

<7> DDR_A_DQS[0..7]
<7> DDR_A_DQS#[0..7]

2

<7> DDR_A_MA[0..15]

1

2

CD2
2.2U_0603_6.3V6K

<7> DDR_A_D[0..63]

CD1
0.1U_0402_16V7K

All VREF traces should
have 20 mil trace width

D

DDR_A_D0
DDR_A_D1

DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17

+1.5V
1

DDR_A_DQS#2
DDR_A_DQS2

RD1
1K_0402_1%

DDR_A_D18
DDR_A_D19

+V_DDR_REFA

1

2

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

D

DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR3_DRAMRST#

DDR3_DRAMRST#

<7,13>

DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21

DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31

2

RD2
1K_0402_1%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

C

C

DDR_A_MA3
DDR_A_MA1

Layout Note:
Place near JDIMM1.203 & JDIMM1.204

+0.75VS

1

<7> DDR_A_WE#
<7> DDR_A_CAS#

DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#

<7> DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35

B

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

Layout Note:
Place near JDIMM1

DDR_A_D48
DDR_A_D49

Layout Note: Place these 4 Caps near Command
and Control signals of DIMMA

DDR_A_DQS#6
DDR_A_DQS6

+1.5V

1
+

CD22
330U_B2_2.5VM_R15M
DDR_A_D58
DDR_A_D59

2
RD51

2

RD6
10K_0402_5%

2

1

CD24
0.1U_0402_16V7K

DDR3 SO-DIMM A

1

CD23
2.2U_0603_6.3V6K

+3VS
SGA00004400

2 10K_0402_5%

1

2

DDR_A_D56
DDR_A_D57

2

2

1

CD21
0.1U_0402_16V7K

2

1

CD20
0.1U_0402_16V7K

2

1

CD19
0.1U_0402_16V7K

2

1

CD18
0.1U_0402_16V7K

2

1

CD17
10U_0603_6.3V6M

2

1

CD16
10U_0603_6.3V6M

2

1

CD15
10U_0603_6.3V6M

2

1

CD14
10U_0603_6.3V6M

1

CD13
10U_0603_6.3V6M

2

CD12
10U_0603_6.3V6M

1

DDR_A_D50
DDR_A_D51

205

G1

G2

DDR_CKE1_DIMMA

206

0.6A@+0.75VS

DDR_CKE1_DIMMA

<7>

DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

DDR_A_BS1
DDR_A_RAS#

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDR_CS0_DIMMA#
M_ODT0

DDR_CS0_DIMMA#
M_ODT0 <7>

M_ODT1

M_ODT1

+1.5V

<7>

RD3
1K_0402_1%

+VREF_CA

<7>

+VREF_CA
DDR_A_D36
DDR_A_D37
1
DDR_A_D38
DDR_A_D39

2

DDR_A_D44
DDR_A_D45

1

2

CD11
2.2U_0603_6.3V6K

2

<7> DDR_A_BS0

DDR_A_MA10
DDR_A_BS0

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

CD10
0.1U_0402_16V7K

10U_0603_6.3V6M

2

CD9

1

10U_0603_6.3V6M

2

CD8

1

10U_0603_6.3V6M

2

1U_0402_6.3V6K

1

CD7

2

1U_0402_6.3V6K

1

CD6

2

CD5

1

1U_0402_6.3V6K

CD4

2

1U_0402_6.3V6K

CD3

1

M_CLK_DDR0
M_CLK_DDR#0

<7> M_CLK_DDR0
<7> M_CLK_DDR#0

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

1

DDR_A_MA8
DDR_A_MA5

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

2

DDR_A_MA12
DDR_A_MA9

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

1

DDR_A_BS2

<7> DDR_A_BS2

RD4
1K_0402_1%
2

DDR_CKE0_DIMMA

<7> DDR_CKE0_DIMMA

B

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PCH_SMBDATA
PCH_SMBCLK

PCH_SMBDATA <13,15,31>
PCH_SMBCLK <13,15,31>
+0.75VS

LCN_DAN06-K4406-0102

+1.5V
A

A

1
@

2

1
@

2

CD25
0.1U_0402_16V7K

2

CD28
0.1U_0402_16V7K

1
@

CD27
0.1U_0402_16V7K

2

CD26
0.1U_0402_16V7K

1
@

Standard

LA-8043P

Compal Secret Data

Security Classification
Issued Date

SI# 8/16 Reserve 4 pcs 0.1uF for EMI noise issue
5

4

2011/06/29

Deciphered Date

2011/06/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title

DDRIII DIMM
Size
C
Date:

Document Number

Rev
0.1

LA-8661P
Friday, March 02, 2012

Sheet
1

12

of

58

5

4

3

2

1

DDR3 SO-DIMM B

10/03 change to +V_DDR_REFB
+V_DDR_REFB

+1.5V

+1.5V

3.56A@+1.5V
JDDRL2
+V_DDR_REFB

<7> DDR_B_DQS[0..7]
D

<7> DDR_B_DQS#[0..7]

2

<7> DDR_B_MA[0..15]

1

2

CD29
2.2U_0603_6.3V6K

1

CD50
0.1U_0402_16V7K

All VREF traces should
have 20 mil trace width
<7> DDR_B_D[0..63]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDR_B_D0
DDR_B_D1

DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9

Delete DDR_B_DM[0..7]

DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17

+1.5V
1

DDR_B_DQS#2
DDR_B_DQS2

RD12
1K_0402_1%

DDR_B_D18
DDR_B_D19

10/03 change to +V_DDR_REFB

DDR_B_D24
DDR_B_D25

1

2

+V_DDR_REFB

DDR_B_D26
DDR_B_D27

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0

D

DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#

DDR3_DRAMRST#

<7,12>

DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21

DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31

2

RD11
1K_0402_1%

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

Layout Note:
Place near JDIMM1.203 & JDIMM1.204

+0.75VS

1

<7> DDR_B_WE#
<7> DDR_B_CAS#

DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS1_DIMMB#

<7> DDR_CS1_DIMMB#

DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41

B

DDR_B_D42
DDR_B_D43

Layout Note:
Place near JDIMM1

DDR_B_D48
DDR_B_D49

Layout Note: Place these 4 Caps near Command
and Control signals of DIMMA

DDR_B_DQS#6
DDR_B_DQS6

+1.5V

2

1
+

CD57
47U 6.3V M B1 ESR70M
DDR_B_D58
DDR_B_D59

2
RD7 1

2

1

2

+3VS

RD9
10K_0402_5%

DDR3 SO-DIMM B

CD31
2.2U_0603_6.3V6K

1

CD38
0.1U_0402_16V7K

+3VS

2 10K_0402_5%

1

+

DDR_B_D56
DDR_B_D57

2

2

1

CD36
47U 6.3V M B1 ESR70M

2

1

CD39
0.1U_0402_16V7K

2

1

CD47
0.1U_0402_16V7K

2

1

CD43
0.1U_0402_16V7K

2

1

CD44
0.1U_0402_16V7K

2

1

CD56
10U_0603_6.3V6M

2

1

CD42
10U_0603_6.3V6M

2

1

CD40
10U_0603_6.3V6M

2

1

CD45
10U_0603_6.3V6M

1

CD46
10U_0603_6.3V6M

2

CD37
10U_0603_6.3V6M

1

DDR_B_D50
DDR_B_D51

205

G1

G2

DDR_CKE1_DIMMB

206

0.6A@+0.75VS

DDR_CKE1_DIMMB

<7>

DDR_B_MA15
DDR_B_MA14
C

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_BS1
DDR_B_RAS#

DDR_B_BS1 <7>
DDR_B_RAS# <7>

DDR_CS0_DIMMB#
M_ODT2

DDR_CS0_DIMMB#
M_ODT2 <7>

M_ODT3

M_ODT3

+1.5V

<7>
+VREF_CB

<7>

RD8
1K_0402_1%

+VREF_CB

10/03 change to +VREF_CB

DDR_B_D36
DDR_B_D37
1
DDR_B_D38
DDR_B_D39

2

DDR_B_D44
DDR_B_D45

1

2

CD30
2.2U_0603_6.3V6K

2

<7> DDR_B_BS0

DDR_B_MA10
DDR_B_BS0

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

CD55
0.1U_0402_16V7K

10U_0603_6.3V6M

2

CD49

1

10U_0603_6.3V6M

2

CD52

1

10U_0603_6.3V6M

2

1U_0402_6.3V6K

1

CD53

2

1U_0402_6.3V6K

1

CD48

2

CD54

1

1U_0402_6.3V6K

CD51

2

1U_0402_6.3V6K

CD41

1

M_CLK_DDR2
M_CLK_DDR#2

<7> M_CLK_DDR2
<7> M_CLK_DDR#2

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

1

DDR_B_MA12
DDR_B_MA9

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

2

C

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

1

DDR_B_BS2

<7> DDR_B_BS2

RD10
1K_0402_1%
2

DDR_CKE0_DIMMB

<7> DDR_CKE0_DIMMB

DDR_B_DQS#5
DDR_B_DQS5
B

DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PCH_SMBDATA
PCH_SMBCLK

PCH_SMBDATA <12,15,31>
PCH_SMBCLK <12,15,31>
+0.75VS

LCN_DAN06-K4406-0102

+1.5V

2

@

2

1
@

2

10/05 change to PH.

CD32
0.1U_0402_16V7K

@

1

CD35
0.1U_0402_16V7K

2

1

CD34
0.1U_0402_16V7K

@

CD33
0.1U_0402_16V7K

1
A

Standard


Compal Secret Data

Security Classification

SI# 8/16 Reserve 4 pcs 0.1uF for EMI noise issue

Issued Date

A

2010/05/27

Deciphered Date

2011/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
DDRIII-DDRH

Size

Document Number

Rev
0.1

LA-8661P
Date:

Sheet

Friday, March 02, 2012
1

13

of

58

5

4

3

2

1

PCH_RTCX1

1

2

CH3
18P_0201_50V8J

This is needed to reduce leakage from
Coin Cell Battery in G3 state

+RTCVCC
RH116 1

2
1M_0402_5%

9/7 SMT memo:Follow PM requirement change R1 p/n into
R1: SA00004EES0
R3: SA00004QOB0

<38>

3

HDA_SPKR

HDA_SPKR

T10

HDA_RST#

K34

<38> HDA_SDIN0

HDA_SDIN0

E34
G34

RH122

1

2
0_0402_5%

@

C34

SI add 1M pull down

9/7 SMT memo:Follow intel ME update requirement
add: RH123
<36>
HDA_SDO

RH123

<38> HDA_SDOUT_AUDIO

RH125

A34
1

HDA_SDOUT
2
0_0402_5%

1

HDA_SDOUT
2
33_0402_5%

HDA_SDOUT

A36
C36

SI2 delete RH128& RH127 200 ohm for CPU screw PAD
12.19
+3V_PCH

PCH_JTAG_TCK

J3

1

N32

PCH_JTAG_TMS

H7

PCH_JTAG_TDI

K5

PCH_JTAG_TDO

H1

INTVRMEN

LDRQ0#
LDRQ1# / GPIO23
SERIRQ

HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#
HDA_SDIN0

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDO
HDA_DOCK_EN# / GPIO33

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

HDA_DOCK_RST# / GPIO13

JTAG_TCK

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

JTAG_TMS

SATAICOMPO

JTAG_TDI
JTAG_TDO

SATAICOMPI

SATA3COMPI

2

PCH_SPI_CLK

T3

PCH_SPI_CS0#

Y14

PCH_SPI_CS1#

T1

PCH_SPI_SI

V4

PCH_SPI_SO

U3

SATA3RBIAS

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

D36

LPC_FRAME#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

<31,36,42>
<31,36,42>
<31,36,42>
<31,36,42>

LPC_FRAME#

SERIRQ

V5

SERIRQ

SPI_MOSI

SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

<33>
<33>
<33>
<33>

SATA HDD

AM10
AM8
AP11
AP10

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

<33>
<33>
<33>
<33>

JMINI2 SSD

HDDHALT_LED#
SATA_LED#

+3VS
+RTCVCC

2

1 10K_0402_5%

RH136

2

1 10K_0402_5%

RH138

2

1 10K_0201_5%

HDA_SPKR RH139

*

2

@

PCH_INTVRMEN RH124

2

PCH_INTVRMEN RH126

2

1 330K_0402_5%
@

1 330K_0402_5%

INTVRMEN
H Integrated VRM enable
L Integrated VRM disable

*

1 1K_0402_5%

LOW=Default
HIGH=No Reboot

AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1

C

+3V_PCH

ME debug mode , this signal has a weak internal PD
HDA_SDOUT RH140

L=>security measures defined in the Flash
Descriptor will be in effect (default)

Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1

1 1K_0402_5%

RTC Battery
+1.05VS_VCC_SATA

Y11
Y10

@

2

= Disabled
*Low
High = Enabled

H=>Flash Descriptor Security will be overridden

SATA_COMP

1
RH130

+RTCBATT

2
37.4_0402_1%

AB13

SATA3_COMP

1
RH132

2
49.9_0402_1%

AH1

RBIAS_SATA3

1
RH137

2
750_0402_1%

P3

SATA_LED#

V14

HDDHALT_LED#

P1

BBS_BIT0_R

SATA_LED#

1K_0402_5%

2

W=20mils

<34>
<34>

+3VS

RH148

DH1

20mils
CH7
1U_0402_6.3V6K

HDDHALT_LED#
R60 1

HDA_SYNC

+RTCVCC

+1.05VS_SATA3

AB12

2

20mils
10mils

1

1
3

1

+3VLP

W=20mils
BAV70W 3P C/C_SOT-323


JRTC1 @

1
2

1
2

3
4

This signal has a weak internal pull-down
On Die PLL VR is supplied by
1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom

GND
GND

+3V_PCH

ACES_50271-0020N-001

HDA_SYNC

RH149

2

1 1K_0402_5%

Place CH95 close to PCH.

2 10K_0201_5%

SI2 change to 0201
12.19

PCH_JTAG_TCK

SPI BIOS Pinout
(1)CS#
(2)DO
(3)WP#
(4)GND

Delete RH151& CH1 for EMI reserve.
01.18

RH131

+3VS

AM3
AM1
AP7
AP5

2

SPI_MISO

SERIRQ

<36,42>

SPI_CS0#
SPI_CS1#

SI2 change to 0201
12.19

EC,TPM and Debug card.

<31,36,42>

E36
K36

PANTHER-POINT_FCBGA989

B

1
RH150

SPI_CLK

SPI

RH135
100_0402_1%

2

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA3RCOMPO

SI2 change to RH133 0201
12.19
51_0402_5%

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

C38
A38
B37
C37

))

INTRUDER#

PCH_JTAG_TDI

RH134
100_0402_1%

2

2

RH133
100_0201_1%

SRTCRST#

1

1

1

2

@ RH129
@RH129
200_0402_5%
PCH_JTAG_TMS

FWH4 / LFRAME#

D

S

7/12

L34

HDA_SYNC

1

SB000002X00
BSS138W-7-F_SOT323-3

2 RH158

1
1M_0402_5%

N34

HDA_SYNC

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

#
$
&%
'
$
(

2 HDA_SYNC_R
33_0402_5%

HDA_BIT_CLK

RTCRST#

IHDA

RH121

K22
C17

RTCX2

SATA

HDA_RST#
2
33_0402_5%

Prevent back drive issue.

G

RH120

+5VS

G22

SM_INTRUDER#
CLRP2
SHORT PADS
PCH_INTVRMEN
ME CMOS
CLP1 & CLP2 place near DIMM

QH1

1

<38> HDA_SYNC_AUDIO

D20

RTCX1

JTAG

1

<38> HDA_RST_AUDIO#

HDA_BIT_CLK
2
33_0402_5%

RH119

PCH_RTCRST#

1

1

2

1

C20

PCH_SRTCRST#

2

<38> HDA_BITCLK_AUDIO

A20

PCH_RTCX2

LPC

2

1
2
RH117 20K_0402_5%
1
2
RH118 20K_0402_5%
CH5
1U_0402_6.3V6K

PCH_RTCX1

SATA 6G

2

CMOS
CLRP1
SHORT PADS

RTC

1

1

CH4
1U_0402_6.3V6K

PCH_JTAG_TDO

PV BOM

UH1A
+RTCVCC

C

D

SM_INTRUDER#

2

4
OSC

OSC

NC

NC
2

YH1

3

2

32.768K 12.5PF Q13MC1462001700

CH2
1
18P_0201_50V8J

D

PCH_RTCX2

2
10M_0402_5%

1

1
RH115

B

SPI BIOS Pinout

(5)DIO
(6)CLK
(7)HOLD#
(8)VCC

(1)CS#
(2)DO
(3)WP#
(4)GND

W25X32

(5)DIO
(6)CLK
(7)HOLD#
(8)VCC

W25X32

Change BIOS ROM power rail to +3VS
2012.01.08

SPI ROM FOR ME ( 4MByte )
+3VS

2

SI stuff RH142, RH175, RH176, RH235
11.22

RH141
3.3K_0402_5%

1

@

PCH_SPI_CS0#
PCH_SPI_SO

1
RH145

+3VS

SPI ROM FOR Win8

1
2
3
4

8
CS#
VCC
7
SO/SIO1
HOLD#
6
WP#
SCLK
5
GND
SI/SIO0
MX25L3206EM2I-12G_SO8

PCH_SPI_HOLD#
PCH_SPI_CLK_RIC
PCH_SPI_SI_RIC

1 RH144
2 RH176
2 RH235

2
1
1

3.3K_0402_5%
33_0402_5% PCH_SPI_CLK
33_0402_5% PCH_SPI_SI

1

2

CH6
0.1U_0201_16V4Z

(2MByte )

A

+3VS

SI stuff RH315, RH323, RH312, RH321
11.22

2
@

RH304
3.3K_0402_5%

1

A

+3VS

UH2

RH142 1
2 0_0402_5% PCH_SPI_CS0#_R
RH175 1
2 33_0402_5% PCH_SPI_SO_RIC
PCH_SPI_WP#
2
3.3K_0402_5%

PCH_SPI_CS1#
PCH_SPI_SO
+3VS

1
RH302

8
7
6
5

CS#
VCC
SO
HOLD#
WP#
SCLK
GND
SI
MX25L1606EM2I-12G_SO8

5

+3VS

UH5

RH315 1
2 0_0402_5% PCH_SPI_CS1#_R 1
RH323 1
2 33_0402_5% PCH_SPI_SO_LIC 2
PCH_SPI_WP#
2
3
3.3K_0402_5%
4

1 RH301
2 RH312
2 RH321

2
1
1

3.3K_0402_5%
33_0402_5% PCH_SPI_CLK
33_0402_5% PCH_SPI_SI

20mils
4

1

2

Issued Date
CH8
0.1U_0201_16V4Z

Compal Electronics, Inc.

Compal Secret Data

Security Classification
PCH_SPI_HOLD#
PCH_SPI_CLK_LIC
PCH_SPI_SI_LIC

2011/06/29

Deciphered Date

2011/06/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title

PCH (1/8) SATA,HDA,SPI, LPC
Size

Document Number

Rev
0.1

LA-8043P
Date:

Sheet

Friday, March 02, 2012
1

14

of

58

5

4

3

2

1

PV# 9/13 change power rail form +3VALW->+3V_PCH

10/03 change to PCIE port1.

+3V_PCH

SMBDATA

1
RH152
1
RH153
1
RH156
1
RH157
1
RH159
1
RH160

UH1B
SMBCLK

+3V_PCH
<34> LAN_CLKREQ#

MiniWLAN

PCIECLKREQ0#

RH178
RH179

2
2

1 0_0402_5%
1 0_0402_5%

PCIE_MINI1#
PCIE_MINI1

RH181
+3VS
MINI1_CLKREQ#

2

1 10K_0201_5%

MINI1_CLKREQ#

<31> CLK_PCIE_MINI1#
<31> CLK_PCIE_MINI1

SI2 change to 0201
<31>
12.19

PCIE_LAN# Y40
PCIE_LAN Y39

2 10K_0201_5%

J2
AB49
AB47
M1
AA48
AA47

+3VS

RH182 1

2 10K_0402_5%

V10
Y37
Y36

+3V_PCH

SI2 change to 0201
12.19

RH180

1 10K_0402_5%

2

A8
Y43
Y45

+3V_PCH

RH177

1 10K_0201_5%

2

L12
V45
V46

+3V_PCH

SI2 change to 0201
12.19

RH274 2

1 10K_0402_5%

L14
AB42
AB40

+3V_PCH

RH183

2 10K_0201_5%

1

E6

Change WL_OFF# to GPIO45 (pull-high) +3V_PCH
2012.01.04
<31>
B

+3V_PCH

RH185

V40
V42

WL_OFF#

2 10K_0402_5%

1

WL_OFF# T13

XTAL25_IN

YH2

1

3
GND

GND

2

4

+3V_PCH
<8> CLK_RES_ITP#
<8> CLK_RES_ITP

3

RH189 1
RH190
RH191

2
2

2 10K_0402_5%
@
@

1 0_0402_5%
1 0_0402_5%

K12
CLK_BCLK_ITP#
CLK_BCLK_ITP

AK14
AK13

SML1DATA / GPIO75

PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8

CL_CLK1
CL_DATA1
CL_RST1#

PEG_A_CLKRQ# / GPIO47

CLKOUT_PCIE1N
CLKOUT_PCIE1P

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P

PCIECLKRQ1# / GPIO18
CLKOUT_DP_N
CLKOUT_DP_P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
CLKIN_DMI_P

PCIECLKRQ2# / GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P

CLKIN_GND1_N
CLKIN_GND1_P

PCIECLKRQ3# / GPIO25
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
CLKIN_SATA_N
CLKIN_SATA_P

PCIECLKRQ4# / GPIO26
CLKOUT_PCIE5N
CLKOUT_PCIE5P

REFCLK14IN

PCIECLKRQ5# / GPIO44

CLKIN_PCILOOPBACK

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

XTAL25_IN
XTAL25_OUT

C13 GPIO74

CLKIN_DMI2#
CLKIN_DMI2
CLKIN_DMI#
CLKIN_DMI
CLKIN_DOT96#
CLKIN_DOT96
CLKIN_SATA#
CLKIN_SATA
CLK_PCH_14M

E14 SML1CLK
M16 SML1DATA

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

+3V_PCH

P10

M10

PEG_CLKREQ#_R
0_0402_5%

2

1

AB37
AB38

CLK_VGA# 0_0402_5%
CLK_VGA 0_0402_5%

2
2

1
1

AV22 CLK_CPU_DMI#_PCH
AU22 CLK_CPU_DMI_PCH

RH172
RH173

1
1

VGA_CLKREQ#

RH412
RH410
RH411

<23>

CLK_PCIE_VGA# <22>
CLK_PCIE_VGA <22>

2 0_0402_5%
2 0_0402_5%

100MHz
100MHz

CLK_CPU_DMI#
CLK_CPU_DMI

CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>

C

AM12
AM13
BF18 CLKIN_DMI#
BE18 CLKIN_DMI
BJ30 CLKIN_DMI2#
BG30 CLKIN_DMI2
G24 CLKIN_DOT96#
E24 CLKIN_DOT96

+3VS

+3VS

AK7 CLKIN_SATA#
AK5 CLKIN_SATA
K45 CLK_PCH_14M
H45 CLK_PCI_LPBACK

CLK_PCI_LPBACK

RH186
2.2K_0402_5%

<17>

V47 XTAL25_IN
V49 XTAL25_OUT

2N7002DWH_SOT363-6

Y47

XCLK_RCOMP

SMBCLK

1
RH184

2
90.9_0402_1%

6

+1.05VS_VCCDIFFCLKN

RH188
2.2K_0402_5%

1

PCH_SMBCLK

RH192 @
1
2
0_0402_5%

+3VS

PCIECLKRQ6# / GPIO45
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67

K43

UMA@

F47
H47
K49

SMBDATA

<12,13,31>

B

3

4

RH318
10K_0402_5%

2N7002DWH_SOT363-6
QH2B
RH194
1
2
0_0402_5%
@

RH319
10K_0402_5%

+3VS

DGPU_PRSNT#

PX@

PCH_SMBDATA

<12,13,31>

1

+3VS

CH13
18P_0201_50V8J
CLK_PCH_14M

@
RH193
2
1
33_0402_5%

@

2

CH14

1

2

2

2
2
2
2
2
2
2
2
2

If use extenal CLK gen, please place close to CLK gen
else, please place close to PCH

T11

1
CH12
18P_0201_50V8J

1
1
1
1
1
1
1
1
1

M7

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

RH162
RH163
RH164
RH165
RH166
RH167
RH168
RH169
RH170

QH2A

XCLK_RCOMP

PCIECLKRQ7# / GPIO46

D

2
1K_0201_5%

12/16:Change to 0201 for SI2

PEG_B_CLKRQ# / GPIO56

CLKOUT_PCIE7N
CLKOUT_PCIE7P

2 10K_0402_5%

1
RH161

RH8
10K_0402_5%

CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0# / GPIO73

G12 SML0DATA

PANTHER-POINT_FCBGA989

1

2

XTAL25_OUT

2
1
1M_0402_5%
RH187
25MHZ_20PF_7V25000016

1

V38
V37

SML1CLK / GPIO58

1 RH263

DRAMRST_CNTRL_PCH

RH291
2.2K_0402_5%

22P_0201_25V8

CLK_PCI_LPBACK2
1
33_0402_5%

2

SML1CLK

CH15

1

@

1

2N7002DWH_SOT363-6
@
RH195

RH311
2.2K_0402_5%

2

Reserve for EMI please close to UH1

SI2 YH2 change to SJ10000DJ00
12.19

2

C

1 0_0402_5%
1 0_0402_5%

2
2

SML1ALERT# / PCHHOT# / GPIO74

GPIO74

SML0CLK

2

RH171
1

SML0DATA

C8

<7,10,36>

2

RH4
RH5

<34> CLK_PCIE_LAN#
<34> CLK_PCIE_LAN

SML1DATA

DRAMRST_CNTRL_PCH

1

PCIE LAN/Card Reader

SML0CLK

A12 DRAMRST_CNTRL_PCH

1

SI2 change to 0201
12.19

SML0ALERT# / GPIO60

+3V_PCH

5

BE38
BC38
AW38
AY38

PERN4
PERP4
PETN4
PETP4

PERN6
PERP6
PETN6
PETP6

SML1CLK

2

BG40
BJ40
AY40
BB40

SML0DATA

<37>

SMBDATA <37>

2

BJ38
BG38
AU36
AV36

SMBCLK

SMBDATA

REV:06 0203

PERN3
PERP3
PETN3
PETP3

PERN5
PERP5
PETN5
PETP5

C9

1

BG37
BH37
AY36
BB36

H14 SMBCLK

2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%

2

BF36
BE36
AY34
BB34

E12 SMBALERT#

SML0CLK

10K_0402_5%
2

1

D

SMBDATA

RH155
1

2

BG36
BJ36
AV34
AU34

PERN2
PERP2
PETN2
PETP2

SMBUS

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

SMBCLK

Link

CH10 1
CH11 1

BE34
BF34
BB32
AY32

SMBALERT# / GPIO11

Controller

Mini card WLAN

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

PERN1
PERP1
PETN1
PETP1

FLEX CLOCKS

<31> PCIE_PRX_DTX_N2
<31> PCIE_PRX_DTX_P2
<31> PCIE_PTX_C_DRX_N2
<31> PCIE_PTX_C_DRX_P2

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

1
1

PCI-E*

CH85
CH84

BG34
BJ34
AV32
AU32

CLOCKS

<34> PCIE_PRX_DTX_N1
<34> PCIE_PRX_DTX_P1
<34> PCIE_PTX_C_DRX_N1
<34> PCIE_PTX_C_DRX_P1

PCIE LAN/Card Reader

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

6

1

EC_SMB_CK2 <23,36,40>

QH6A

1

5

Reserve for EMI please 22P_0201_25V8
close to
UH1
SML1DATA

3

4

EC_SMB_DA2 <23,36,40>

2N7002DWH_SOT363-6
QH6B

A

SI# 8/8

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/29

Deciphered Date

2011/06/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

A

Add SML1CLK/SML1DATA for EC detect Thermal

Title

PCH (2/8) PCIE, SMBUS, CLK
Size

Document Number

Rev
0.1

LA-8043P
Date:

Sheet

Friday, March 02, 2012
1

15

of

58

5

4

3

2

1

UH1C

<5>
<5>
<5>
<5>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

BE24
BC20
BJ18
BJ20

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

AW24
AW20
BB18
AV18

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

AY24
AY20
AY18
AU18

<5> DMI_CRX_PTX_N0
<5> DMI_CRX_PTX_N1
<5> DMI_CRX_PTX_N2
<5> DMI_CRX_PTX_N3

D

<5>
<5>
<5>
<5>

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT

+VCCP
To VccIO.

BJ24
DMI_IRCOMP
2
49.9_0402_1%
RBIAS_CPY
2
750_0402_1%

1
RH196
1
RH197

BG25
BH21

DMI_ZCOMP

FDI_FSYNC0

DMI_IRCOMP

FDI_FSYNC1

DMI2RBIAS

FDI_LSYNC0

4mil width and place
within 500mil of the PCH
@

2 SUSACK#_R
0_0201_5%

1
RH200

SYS_PWROK

<6> SYS_PWROK

1

2

PCH_PWROK1
RH203

2

K3
P12

RH202

<36> PCH_PWROK

0_0402_5%
PM_PWROK_R
0_0402_5%

1

2

RH204

0_0402_5%

PCH_RSMRST#
1
RH206

<36> PCH_RSMRST#

SI2 change to 0201
<36> SUSWARN#
12.19

E20

1

2 ACIN_R
H20
CH751H-40PT_SOD323-2

GPIO72

E10
RI#

B

SYS_PWROK
PWROK
APWROK
DRAMPWROK

SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63

A10

+3V_PCH

SLP_S4#
SLP_S3#
SLP_A#

ACPRESENT / GPIO31

SLP_SUS#

BATLOW# / GPIO72

PMSYNCH

RI#

SLP_LAN# / GPIO29

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

AW16

FDI_INT

AV12

FDI_FSYNC0

BC10

FDI_FSYNC1

AV14

FDI_LSYNC0

BB10

FDI_LSYNC1

2 10K_0402_5%

GPIO72

RH210 1

2 10K_0201_5%

RI#

RH211 1

2 10K_0201_5%

RH212 1

2 10K_0402_5%

DSWODVREN RH213

RH214 1

2100K_0402_5%

DSWODVREN

<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>

D

FDI_INT <5>
FDI_FSYNC0

1 RH199

E22 PCH_DPWROK
B9

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

<5>

FDI_FSYNC1

<5>

FDI_LSYNC0

<5>

FDI_LSYNC1

<5>

DSWODVREN

A18

WAKE#

1

PCH_RSMRST#
2 0_0402_5%
PCH_DPWROK <36>

2
RH201

G8

SUS_STAT#

N14

SUSCLK

D10

<31,34>

ENBKL

<36>
ENBKL
<32> PCH_ENVDD

PM_CLKRUN# <42>

2
RH205

1
0_0402_5%

PM_SLP_S5#
PM_SLP_S4#

F4

PM_SLP_S3#

G10

SLP_A#

G16

PM_SLP_SUS#

AP14

H_PM_SYNC

J47
M45
P45

<32> DPST_PWM
PCH_LCD_CLK
PCH_LCD_DATA

<32> PCH_LCD_CLK
SUS_STAT# <42>
<32> PCH_LCD_DATA
LPCPD# pin of LPC devices may
be connected to PCH SUS_STAT# pin.

H4

K14

UH1D

PCH_PCIE_WAKE#

0_0402_5%

PM_CLKRUN#

N3

CTRL_CLK
CTRL_DATA

SUSCLK_R <36>
PM_SLP_S5# <36>

PAD~D

PM_SLP_S4# <36>

1
RH207

PM_SLP_S3# <36>

2 LVD_VREF
0_0402_5%

<32> PCH_TXCLK<32> PCH_TXCLK+

SLP_A# <36>

<32> PCH_TXOUT0<32> PCH_TXOUT1<32> PCH_TXOUT2<32> PCH_TXOUT0+
<32> PCH_TXOUT1+
<32> PCH_TXOUT2+

<6>

PCH_TXCLKPCH_TXCLK+

AK39
AK40

PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

AN48
AM47
AK47
AJ48

PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+

AN47
AM49
AK49
AJ47

PCH_GPIO29

AF40
AF39
AH45
AH47
AF49
AF45

12/16:RH210& RH211 Change to 0201 for SI2
+RTCVCC

RH215

AH43
AH49
AF47
AF43

1 330K_0402_5%

2

T45
P39

AE48
AE47

PM_SLP_SUS# <36>

H_PM_SYNC

T40
K47

LVDS_IBG AF37
AF36

T37

GPIO29 PU to follow Intel request.
11.04

PANTHER-POINT_FCBGA989

RH331 1

ACIN_R

CLKRUN# / GPIO32

PWRBTN#

PCH_GPIO29

WAKE#

WAKE#

SUSWARN#/SUSPWRDNACK/GPIO30

K16

GPIO29 PU to follow Intel request.
11.04

SYS_RESET#

DPWROK

RSMRST#

2 PBTN_OUT#_R
0_0402_5%

DH2

SUSACK#

2 PCH_RSMRST#_R C21
0_0402_5%
2 SUSWARN#_R
0_0201_5%

RH209

ACIN

B13

1

1
RH208

<36> PBTN_OUT#

L22
L10

PM_DRAM_PWRGD

<6> PM_DRAM_PWRGD

<23,36,47>

DSWVRMEN
C12

XDP_DBRESET#

<6> XDP_DBRESET#

C

2 SUSACK#_R
0_0201_5%

1
RH198

System Power Management

SUSWARN#

SI2 change to 0201
12.19 <36> SUSACK#

FDI_LSYNC1

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

1 330K_0402_5%

2

L_BKLTEN
L_VDD_EN

SDVO_TVCLKINN
SDVO_TVCLKINP

L_BKLTCTL

SDVO_STALLN
SDVO_STALLP

L_DDC_CLK
L_DDC_DATA

SDVO_INTN
SDVO_INTP

LVD_IBG
LVD_VBG

SDVO_CTRLCLK
SDVO_CTRLDATA

LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

@

1

2 10K_0201_5%

RH217 1

2 10K_0402_5%

DSWODVREN - On Die DSW VR Enable
H Enable
L Disable

*

PCH_PWROK

SI2 change to 0201
12.19
CH268
PCH_PWROK

1

<46,48> SPOK

SI# 8/16 Reserve C268 100pF
by ESD request

@

2

2
DH30

1
CH751H-40PT_SOD323-2

1
DH29

2
CH751H-40PT_SOD323-2

N48
P49
T49

PCH_RSMRST#

T39
M40

+3VS

M47
M49

VGATE

CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA

RH221

1

2 2.2K_0402_5% CTRL_DATA

IN2

UH3

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

mDP

DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P

DMC DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

OUT

4

1 10K_0402_5%

SYS_PWROK

1
RH224

NOTE:It is recommended that SYS_PWROK
be asserted after both PWROK assertion and
CPU core VR powergood assertion. This needed
to ensure a safe platform design which meets
the timing requirements for this signal.

5

<30>

HDMI

<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>

P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

B

M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

RH220
1K_0402_0.5%

A

@

MC74VHC1G08DFT2G_SC70-5

1
2

PCH_DDPB_HPD
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N3
PCH_DPB_P3

PANTHER-POINT_FCBGA989

RH308
10K_0402_5%

SYS_PWROK

RH222
RH223

DAC_IREF
CRT_IRTN

PCH_DDPB_CLK <30>
PCH_DDPB_DAT <30>

2

VCC

IN1

T43
T42

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

DDPD_CTRLCLK
DDPD_CTRLDATA

CRT_HSYNC
CRT_VSYNC

P38
M39

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP
DDPC_HPD

1

2 2.2K_0402_5% CTRL_CLK

EC Request
on 20110309

PM_CLKRUN#

1

1

PM_CLKRUN#

2

<54>

RH219

3

A

2

2 8.2K_0402_5%

GND

PCH_PWROK 1

1

5

CRT_IREF
RH218

C

AP39
AP40

AT49
AT47
AT40

DDPC_CTRLCLK
DDPC_CTRLDATA

100P_0201_50V8J

+3VS

AM42
AM40

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

HDMI

CRT

PCH_RSMRST#

RH216

**

SUSWARN#

AP43
AP45

L_CTRL_CLK
L_CTRL_DATA

LVDS

BC24
BE20
BG18
BG20

Digital Display Interface

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

FDI

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI

<5>
<5>
<5>
<5>

1
RH225

2
2.37K_0402_1%
2
100K_0402_5%
2
100K_0402_5%

LVDS_IBG
PCH_ENVDD
ENBKL

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/29

2011/06/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

Title

PCH (3/8) DMI,FDI,PM,GFX,DP
Size

Document Number

Rev
0.1

LA-8043P
Date:

Friday, March 02, 2012

Sheet
1

16

of

58

5

4

3

2

1

UH1E

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

<35> USB3_RX1_N
<35> USB3_RX3_N
<35> USB3_RX1_P

USB3.0 x2

<35> USB3_RX3_P
<35> USB3_TX1_N
<35> USB3_TX3_N
<35> USB3_TX1_P

C

<35> USB3_TX3_P

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

DGPU_HOLD_RST# C46
DGPU_SELECT#
C44
E40
PXS_PWREN
GPIO51
D47
GPIO53
E42
GPIO55
F46

<22> DGPU_HOLD_RST#
PAD~D T38 @
<24,56> PXS_PWREN

Exchange GPIO2& 5 for HP request
<42> ACCEL_INT#
2012.01.04
Change back the same as DB phase.
2012.01.30

ACCEL_INT#
ODD_DA#
DP_CBL_DET
PIRQH#

AOAC_PME#

<36> AOAC_PME#
<6,22,31,34,36,42>
B

CLK_PCI_LPBACK
CLK_PCI_LPC
CLK_PCI_DEBUG

<15> CLK_PCI_LPBACK
<36,42> CLK_PCI_LPC
<31> CLK_PCI_DEBUG

RH230
RH231
RH242

K40
K38
H38
G38

PLT_RST#

2
1
1

PLT_RST#

1 22_0402_5%
2 22_0402_5%
2 22_0402_5%

CLK_PCI0
CLK_PCI1

G42
G40
C42
D44
K10
C6
H49
H43
J48
K42
H40

TP21
TP22
TP23
TP24

RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

USB3Rn1
USB3Rn2
USB3Rn3
USB3Rn4
USB3Rp1
USB3Rp2
USB3Rp3
USB3Rp4
USB3Tn1
USB3Tn2
USB3Tn3
USB3Tn4
USB3Tp1
USB3Tp2
USB3Tp3
USB3Tp4

PIRQA#
PIRQB#
PIRQC#
PIRQD#

RSVD28
RSVD29

REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

USB

B21
M20
AY16
BG46

RSVD1
RSVD2
RSVD3
RSVD4

RSVD

D

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

PCI

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS

AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

D

AV5
AV10
AT8
AY5
BA2

USB2.0 and sleep charger
(Port 1)

AT12
BF3

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

C33

USBRBIAS

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

<35>
<35>
<35>
<35>
<35>
<35>
C

To USB3.0 connector
(Port 0& 2)
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10

USB20_N8 <32>
USB20_P8 <32>
USB20_N9 <31>
USB20_P9 <31>
USB20_N10 <32>
USB20_P10 <32>

Camera
mPCIE-WLAN/BT
Touch Screen

Add touch screen 12.07

+3V_PCH
RPH1

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

USB_OC0#

<35>

USB_OC4#

Within 500 mils
1
RH229

2
22.6_0402_1%

B33

PME#
PLTRST#

<35>

A14
K20
B17
C16
L16
A16
D14
C14

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

4
3
2
1

5
6
7
8

USB_OC6#
USB_OC4#
USB_OC7#
USB_OC5#

4
3
2
1

10K_0804_8P4R_5%
RPH2
5
6
7
8
B

10K_0804_8P4R_5%

+3VS
PANTHER-POINT_FCBGA989
RPH3
ACCEL_INT#
PCI_PIRQD#
PCI_PIRQB#
PCI_PIRQC#

1
2
3
4

GPIO51
PIRQH#
GPIO53
DP_CBL_DET

1
2
3
4

8
7
6
5
8.2K_0804_8P4R_5%
+3VS

@
RH233
10K_0402_5%

@

UH4

P

RH7

2
0_0402_5%
+3VS

1

8.2K_0804_8P4R_5%

1
RH232

2

8
7
6
5

5

RPH4

ODD_DA#

1 RH6

2 8.2K_0402_5%

GPIO55

1 RH320

2 10K_0402_5%

DGPU_SELECT#

1 RH236

2 10K_0402_5%

PXS_PWREN

1 RH237

2 10K_0402_5%

DGPU_HOLD_RST# @1 RH334

2 10K_0402_5%

4

<31> PLT_RST_BUF#

IN1

O

1

PLT_RST#

2
IN2
SN74AHC1G08DCKR_SC70-5

G

2 8.2K_0402_5%

3

1

1

PCI_PIRQA#

RH234 @
100K_0402_5%

A

2

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Follow Powell reserve PU 10K

2011/06/29

Deciphered Date

2011/06/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

PCH (4/8) PCI, USB, NVRAM
Size

Document Number

Rev
0.1

LA-8043P
Date:

Friday, March 02, 2012

Sheet
1

17

of

58

5

4

3

2

1

2

+3VS

UH1F

H36
E38
C10

<36>

EC_SMI#

EC_SMI#
DMC_DET#

C4

EC_LID_OUT#_R
1
0_0201_5%

G2

PCH_GPIO16

1
RH267

2 SLP_ME_CSW_DEV#
10K_0402_5%

1
RH241

2 SLP_ME_CSW_DEV#
1K_0402_5%

<52>

DDR3L_EN

U2

VGA_PWRGD

D40

PCH_GPIO22

T5

DDR3L_EN

E8

PCH_GPIO27
<36> SLP_ME_CSW_DEV#

@
<31> BT_ON#

Refer Powell change
BT_ON to GPIO34
10.21

PCH_GPIO37

FDI TERMINATION VOLTAGE OVERRIDE
C

*

LOW - Tx, Rx terminated
to same voltage
(DC Coupling Mode)

+3VS

<33> HDD_DETECT#

RH245

2

RH246

2

@

1 1K_0402_5%

PCH_GPIO37

1

PCH_GPIO37

E16

SLP_ME_CSW_DEV#
BT_ON#

P8
K1

PCH_GPIO35

K4

GPIO36

V8

PCH_GPIO37

M5

GPIO38

N2

PCH_GPIO39

M3

PCH_GPIO48

V13

GPIO49

V3

HDD_DETECT#

D6

A4
A44
A45
A46
A5

GPIO27

A6

PCH_GPIO27 (Have internal Pull-High)
VCCVRM VR Enable
*High:
Low: VCCVRM VR Disable
@ RH250

1

2

GPIO15

A20GATE
PECI

SATA4GP / GPIO16
TACH0 / GPIO17
SCLOCK / GPIO22
GPIO24
GPIO27
GPIO28

PROCPWRGD
THRMTRIP#
INIT3_3V#
DF_TVS
TS_VSS1

STP_PCI# / GPIO34
TS_VSS2
GPIO35
TS_VSS3
SATA2GP / GPIO36

B3
B47

PCH_GPIO27
10K_0402_5%

BD1
BD49
BE1
BE49

B

BF1
BF49

DB# 10/20 Reserve GPIO 36 pull up resistor
and add pull down resistor

D

TS_VSS4

P4

GATEA20

AU16

PCH_PECI_R

P5

EC_KBRST#

@
1
2
0_0402_5%
RH239

AY11
AY10

10K_0402_5%

2
@ RH322

2

RH255

1

1

<36>

H_PECI <6,36>
+1.8VS

EC_KBRST# <36>
H_CPUPWRGD

H_THERMTRIP#_C 1
390_0402_5%

2
RH240

<6>

H_THRMTRIP#

H_THRMTRIP#

RH226
2.2K_0402_5%

<6>

T14
AY1

NV_CLE
RH227

2

1

H_SNB_IVB#

1K_0402_5%

<6>

Layout note: CLOSE TO THE BRANCHING POINT

AH8
AK11
AH10

SLOAD / GPIO38

NC_1

AK10
P37

SDATAOUT0 / GPIO39

C

SDATAOUT1 / GPIO48

VSS_NCTF_15

SATA5GP / GPIO49 / TEMP_ALERT#

VSS_NCTF_16

GPIO57

VSS_NCTF_17

VSS_NCTF_1

VSS_NCTF_19

VSS_NCTF_2

VSS_NCTF_20

VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5

VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23

VSS_NCTF_6

VSS_NCTF_24

VSS_NCTF_7

VSS_NCTF_25

VSS_NCTF_8

VSS_NCTF_26

VSS_NCTF_9

VSS_NCTF_27

VSS_NCTF_10

VSS_NCTF_28

VSS_NCTF_11

VSS_NCTF_29

VSS_NCTF_12

VSS_NCTF_30

VSS_NCTF_13

VSS_NCTF_31

VSS_NCTF_14

VSS_NCTF_32

+3VS

BG2
BG48

GPIO68

1 RH310

2 10K_0402_5%

BH3

GPIO6

1 RH243

2 10K_0402_5%

BH47

GPIO1

1 RH244

2 10K_0402_5%

BJ4

EC_KBRST#

1 RH295

2 10K_0402_5%

1 RH273

2 10K_0402_5%

PCH_GPIO16

1 RH247

2 10K_0201_5%

C2

DDR3L_EN

2 10K_0402_5%

C48

HDD_DETECT#

D1

DMC_DET#

D49

EC_LID_OUT#_R

1
@ RH248
1
RH249
1
RH251
1
RH252

BJ44
BJ45

SI2 change to 0201
12.19

BJ46
BJ5

+3V_PCH

BJ6

SI2 change to 0201
12.19

2 10K_0201_5%
2 10K_0402_5%
2 1K_0201_5%

E1
E49

B

12/20:Delete RH253 for SI2

F1
F49

+3VS

PANTHER-POINT_FCBGA989

+3VS

10K_0402_5%

This signal should be connected to
the processor's UNCOREPWRGD
input to indicate when the processor power is valid.

SATA3GP / GPIO37

VSS_NCTF_18

100K_0402_5%

+3VS

A40

RH238
10K_0402_5%

RCIN#
<55> VGA_PWRGD

C41

LAN_PHY_PWR_CTRL / GPIO12

12/16:Change to 0201 for SI2

+3V_PCH

B41

GPIO8

CPU/MISC

On-Die PLL Voltage Regulator disable

TACH7 / GPIO71

GPIO

L

2
RH154

<36> EC_LID_OUT#

TACH3 / GPIO7

NCTF

On-Die voltage regulator enable

++

H

TACH6 / GPIO70

1

This signal has a weak internal pull up

TACH5 / GPIO69

TACH2 / GPIO6

1

EC_SCI#

On-Die PLL Voltage Regulator

*

A42

GPIO6
<36>

TACH4 / GPIO68

TACH1 / GPIO1

GPIO 69 follow Intel's request PU.
11.04

2

GPIO28

GPIO1

EC_SCI#

BMBUSY# / GPIO0

RH330
10K_0402_5%

GPIO68

C40

2

D

GPIO0

T7

1

<36>

GPIO0

GPIO0

1

GPIO38

1

GPIO36
PCH_GPIO48

Refer Powell change
BT_ON to GPIO34
10.21

GPIO36

1

BT_ON#

1

PCH_GPIO39

SI# 8/8 change PCH_WAN_RADIO_OFF#
to PCH_GPIO35

1

PCH_GPIO22

PCH_GPIO35
GPIO49

1
1
1

RH254
RH256
RH257
RH258
RH259
RH260
RH261
RH262

2 10K_0402_5%
2 10K_0201_5%
2 10K_0402_5%
2 10K_0402_5%
2 10K_0201_5%
2 10K_0402_5%

SI2 change to 0201
12.19

2 10K_0402_5%
2 10K_0201_5%

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/29

Deciphered Date

2011/06/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

PCH (5/8) GPIO, CPU, MISC
Size

Document Number

Rev
0.1

LA-8043P
Date:

Sheet

Saturday, March 03, 2012
1

18

of

58

5

4

3

2

1

+VCCP

PCH Power Rail Table

POWER

+3VS

Voltage Rail

2
+VCCP

AN16
AN17
AN21

+3VS

2

1

2

1

2

1

2

CH31
1U_0402_6.3V6K

2

1

CH30
1U_0402_6.3V6K

1

AN27
CH29
1U_0402_6.3V6K

SI# 8/8 Add RH297 for
power break down

CH32
1U_0402_6.3V6K

+1.05VS_VCC_EXP
CH28
10U_0603_6.3V6M

AP21
AP23
AP24
AP26

1

AT24
AN33

2

RH268
0_0805_5%

+VCCP

AN34

+3VS_VCCA3GBG

BH29

1

2

CH35
0.1U_0201_16V4Z

+VCCAFDI_VRM

Place CH53 Near AP13,AP15 pin
2
RH270

+1.05VS_VCCAPLL_FDI

1
0_0603_5%

AP16
BG6

CH21

1

2

VCCIO[16]
VCCIO[17]

AK37

AP36

2

AP37

1

2

CH24
0.01U_0201_16V7

1

AM38

RH265
1
2
0_0805_5%

V33 +3VS_VCC3_3_6

0.1UH_MLF1608DR10KT_10%_1608
LH2
2
1

Near AP43

+VCCTX_LVDS

AM37

1

2

9/8 SI build BOT limit 0.8, CH25
del:SE000008L80
add: SE000001120

+3VS

CH26
0.1U_0201_16V4Z

V34
2

VCCIO[18]
VCCIO[19]

2925mA

VCCVRM[3]

VCCIO[23]
VCCIO[24]

AT16

VCCDMI[1]

AT20 +VCCP_VCCDMI
1
RH314

VCCCLKDMI

AB36 +1.05VS_VCC_DMI_CCI

1

1

2
VCCIO[25]
VCCIO[26]

VCCDFTERM[1]

VCC3_3[3]

VCCVRM[2]
VccAFDIPLL

VCCDFTERM[2]
VCCDFTERM[3]
190mA
VCCDFTERM[4]

5

0.001

Vcc3_3

3.3

0.266

VccADAC

3.3

0.001

VccADPLLA

1.05

0.08

VccADPLLB

1.05

0.08

VccCore

1.05

1.3

VccDMI

1.05

0.042

VccIO

1.05

2.925

VccASW

1.05

1.01

VccSPI

3.3

0.02

VccDSW

3.3

0.003

VccpNAND

1.8

0.19

VccRTC

3.3

6 uA

VccSus3_3

3.3

0.119

+VCCP_VCCDMI
+VCCP

RH266

VCCIO[21]
VCCIO[22]

+VCCAFDI_VRM

20mA

VCCIO[20]

0.001

V5REF_Sus

0.1uH inductor, 200mA

1
VCC3_3[7]

0.001

5

D

+1.8VS

VCCAPLLEXP
VCCIO[15]

1.05

AK36

VCCIO[28]

VCC3_3[6]

S0 Iccmax
Current (A)

V5REF

V_PROC_IO

CH22
10U_0603_6.3V6M

CH25
22U_0603_6.3V6M

VCCTX_LVDS[4]

0.1U_0201_16V4Z

CH20
0.01U_0201_16V7

CRT
60mA

AG16

2

+VCCP

0_0805_5%

2

1

2

C

0_0805_5%

SI# 8/8 Change 10uH to 0805 0 ohm
to follow compal common design

VccSusHDA

3.3 / 1.5

0.01

VccVRM

1.8 / 1.5

0.16

+VCCPNAND

AG17

1
RH269

AJ16

1

AJ17

2

2
+1.8VS
0_0805_5%

VccCLKDMI

1.05

0.02

VccSSC

1.05

0.095

VccDIFFCLKN

1.05

0.055

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.06

RH271

@
+VCCP

1
2+1.05VS_VCCDPLL_FDIAP17
0_0805_5%
+VCCP_VCCDMI

B

AU20

VCCIO[27]
VCCDMI[2]

FDI

C

BJ22

AN26

RH297

1
2
0_0805_5%

VCCTX_LVDS[2]

2

2
1
BLM18PG181SN1D_2P

CH33
1U_0402_6.3V6K

Place CH35 Near AP19 pin

1

VSSALVDS
VCCTX_LVDS[1]

1

CH34
1U_0402_6.3V6K

+VCCAPLLEXP

1
0_0603_5%
@

VCCALVDS

Voltage

LH1

CH36
0.1U_0402_10V7K

AN19

@ CH37
10U_0603_6.3V6M

2
RH264

1mA

VCCTX_LVDS[3]

+VCCP

1
U47
2

HVCMOS

+VCCP

+VCCADAC

U48

+3VS

LVDS

2011.10.18 change all cap to small size:
22u& 10u to 0603
4.7u to 0402
1u, 0.1u, 0.01u to 0201

VCCADAC
VSSADAC

DMI

2

DFT / SPI

2

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

1mA

VCC CORE

2

1

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

VCCIO

2

D

1

CH18
1U_0402_6.3V6K

1

CH16
1U_0402_6.3V6K

1
CH17
10U_0603_6.3V6M

CH19
1U_0402_6.3V6K

1300mA

CH23
0.01U_0201_16V7

UH1G

20mA

VCCSPI

V1

RH272
1
2
0_0805_5%

+3V_VCCPSPI

+3VS

1
CH38
1U_0402_6.3V6K

PANTHER-POINT_FCBGA989

Change BIOS ROM power rail to +3VS
2012.01.08

2

B

Change +1.5VS to +1.5V_PCIE
10/21
+VCCAFDI_VRM

+1.5V_PCIE

2

RH275
1
0_0603_5%

+VCCAFDI_VRM

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/29

2011/06/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

PCH (6/8) PWR
Size

Document Number

Rev
0.1

LA-8043P
Date:

Sheet

Friday, March 02, 2012
1

19

of

58

5

4

3

2

1

VCC3_3 = 266mA detal waiting for newest spec

+VCCP

VCCDMI = 42mA detal waiting for newest spec

+VCCSUS1

AL24

+1.05VM_VCCSUS

1
0_0603_5%
1

1

2

2 @

1

2

CH51
22U_0805_6.3V6M

@

CH50
22U_0805_6.3V6M

2

AA21

9/8 SI build BOT limit 0.8
del: SE000001120
add: SE000001120

CH262
1U_0402_6.3V6K

RH407

AA24
AA26
AA27
AA29
AA31

2

SI# 7/29 Add RH307 for break
down PCH VCCASW power

1

2

1

2

AC26

CH55
1U_0402_6.3V6K

1

0_0805_5%

CH54
1U_0402_6.3V6K

+VCCP

C

+VCCP_VCCASW

1

CH53
1U_0402_6.3V6K

RH307

2

AC27
AC29
AC31

+3VS

AD29
RH313

2

SI# 8/8 Add RH313 for follow
compal common design

1

AD31
W21

0_0805_5%

1

2

10UH_LB2012T100MR_20%
CH59
@

W23

+3VS_VCC_CLKF33
1
1

10U_0603_6.3V6M 2

2

CH61
1U_0402_6.3V6K

LH4

119mA

VCCSUS3_3[7]

VCCAPLLDMI2
VCCSUS3_3[8]
VCCIO[14]
VCCSUS3_3[9]

DCPSUS[3]

VCCSUS3_3[10]
VCCSUS3_3[6]

AA19

W24
W26
W29
W31
W33

VCCASW[1]

1

CH64

VCCIO[34]

1010mA
1mA

VCCASW[3]
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
VCCASW[15]

V5REF_SUS
DCPSUS[4]
VCCSUS3_3[1]

0.1U_0201_16V4Z

1mA

V5REF

VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCC3_3[1]
VCC3_3[8]

VCCASW[16]

VCC3_3[4]

+VCCP

2
RH300

VCCASW[19]

VCC3_3[2]

VCCASW[20]
DCPRTC
VCCVRM[4]

VCCIO[13]

BD47

+1.05VS_VCCA_B_DPL

BF47

VCCIO[6]
VCCADPLLA80mA
VCCADPLLB80mA

AF17
AF33
AF34
AG34

CH67
1U_0402_6.3V6K
+1.05VS_SSCVCC

1

1

CH69
1U_0402_6.3V6K

2

AG33
+VCCSST

V16

CH70
+1.05VM_VCCSUS

0.1U_0201_16V4Z

VCCIO[2]

VCCSSC95mA

2
RH286

M26

1

1
0_0603_5%
2
RH287

AN24

1

+3V_VCCPSUS_1

P34 +PCH_V5REF_RUN

1

N22
P20

T17
V19

2

2

1

2

CH81
1U_0402_6.3V6K

2

1

CH80
22U_0603_6.3V6M

1

CH79
1U_0402_6.3V6K

2

CH78
22U_0603_6.3V6M

+1.05VS_VCCA_B_DPL

1

VCCIO[4]

DCPSUS[1]
DCPSUS[2]

VCCASW[22]

2

1

2

VCCRTC

PANTHER-POINT_FCBGA989

9/8 SI build BOT limit 0.8, CH78, CH80
del:SE000008L80
add: SE000001120

7/8 CH78, CH80 220uF change to 22uF.
4

CPU

1mA
V_PROC_IO

RTC

1

CH76
0.1U_0201_16V4Z

A22
1

CH75
0.1U_0201_16V4Z

2

BJ8

+1.05VS_VCCA_A_DPL

1
2
LH7
10UH_LB2012T100MR_20%

1
0_0603_5%

2

+3V_PCH

DH3

RH284
100_0402_5%

0.1U_0201_16V4Z

+3V_PCH

+3VS

CH751H-40PT_SOD323-2
+PCH_V5REF_RUN

+3VS

+3VS_VCCPCORE
1
CH58

AA16

0.1U_0201_16V4Z

W16

2
RH290

1

1
0_0805_5%

+3VS

2
RH292
CH60

1

+VCC3_3_2

2
1

AF13

1

1
0_0603_5%

0.1U_0201_16V4Z
2
+1.05VS_SATA3
RH294

0_0603_5%
CH62

2
1

0.1U_0201_16V4Z

AH13

1

+VCCP

CH63
0_0805_5%
1U_0402_6.3V6K

2

+1.05VS_SATA3

AH14

CH57
1U_0402_6.3V6K

2

2

+3VS_VCCPPCI

T34

C

DH4

2

P22

2

RH288
100_0402_5%

+3V_PCH

CH56
1U_0402_6.3V6K

CH751H-40PT_SOD323-2
+PCH_V5REF_SUS
1

CH49

+5VS

RH289
0_0603_5%
2
1

+3V_VCCPSUS

N20

AJ2

@

+VCCP

+PCH_V5REF_SUS

AN23 +VCCA_USBSUS

LH5
10UH_LB2012T100MR_20%
1
2
@

AF14
+VCCSATAPLL
+VCCAFDI_VRM

AK1
AF11

CH66 @

+1.05VS_VCC_SATA
+1.05VS_VCC_SATA

AC16

VCCASW[23]
VCCASW[21]

10mA

VCCSUSHDA

AC17

Place CH73 Near AK1 pin

RH299

2
1

AD17

1

+VCCP

2 10U_0603_6.3V6M

0_0805_5%

+VCCP

SI# 8/8 Delet the RH301,RH302,RH304 for follow
compal common design

T21
V21
T19

+VCCSUSHDA

P32
CH77
0.1U_0201_16V4Z

1

2

@

2
RH305

1
0_0603_5%

+3V_PCH

A

All the CODEC I/O Voltages need to be at
the same level either 3.3 V or 1.5 V.

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

2011/06/29

2011/06/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

B

+VCCP

1

+VCCAFDI_VRM

DCPSST

+RTCVCC

CH74
0.1U_0201_16V4Z

2

1

CH73
0.1U_0201_16V4Z

1
CH71
4.7U_0402_16V4Z

CH72
0.1U_0201_16V4Z

+V_CPU_IO

1

LH6
10UH_LB2012T100MR_20%
1
2

5

VCCVRM[1]

VCCIO[3]

2

2

+VCCP

VCCAPLLSATA

VCCIO[7]
VCCDIFFCLKN[1]
55mA
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]

+VCCP

A

+1.05VS_VCCAUPLL

+5V_PCH

+VCCA_USBSUS

2

1
0_0603_5%

2
0_0603_5%

T26

2

2

SATA

+1.05VS_VCCA_A_DPL

+1.05VS_VCCDIFFCLKN

2

1
RH303

P24

1

+3VS

+1.05VS_VCCDIFFCLKN

1
0_0603_5% 1

2

V24

D

RH279
20K_0402_5%

2

CH65
1U_0402_6.3V6K

2
RH298

2

1
+3V_PCH
0_0603_5%
2
1
+3V_PCH
RH282
0_0603_5%

RH293

+VCCDIFFCLK

2

+VCCP

Y49

1

V23

VCCASW[18]

MISC

1
0_0603_5% 1

T24

2
RH281
+3V_VCCAUBG

VCCASW[17]

HDA

2
RH296

1

<43> PCH_PWR_EN#
+3V_VCCPUSB

T23

2

VCCIO[12]
+VCCAFDI_VRM

+VCCP
B

N16

T29

VCCASW[2]

VCCIO[5]
+VCCRTCEXT

2

T27

+5V_PCH

1

2

AL29

CH40
1U_0402_6.3V6K

3

1

BH23

+VCCDPLL_CPY

2 @

+VCCP

VCCIO[33]

2 RH278 1
0_0603_5%

2

+VCCAPLL_CPY_PCH

P28

QH3
AO3413_SOT23

+5VALW

+VCCP

VCC3_3[5]

2

2
0_0603_5%

1

T38

VCCIO[32]

1
0_0603_5%

1

1
RH283

+3VS_VCC_CLKF33

DCPSUSBYP

USB

CH42

CH45
1U_0402_6.3V6K

2

V12

PCI/GPIO/LPC

@

0.1U_0201_16V4Z

+VCCP

@ CH43
10U_0603_6.3V6M

+PCH_VCCDSW

1

Clock and Miscellaneous

LH3
10UH_LB2012T100MR_20%
1
2
@
1

2
RH285

G

VCCIO[31]
+VCCP

1

1

VCCDSW3_33mA

P26

2

T16

+1.05VS_VCCUSBCORE

N26

1

+VCCPDSW

2

VCCIO[30]

2

0.1U_0201_16V4Z

VCCIO[29]

1

D

@

VCCACLK

2

G

2
<36> PCH_VREG_EN#

AD49

1

CH39

CH48
1U_0402_6.3V6K

2
0_0603_5%

D

2
0_0603_5%

1
RH309

S

1
RH277

CH68
1U_0402_6.3V6K

+3V_DSW

RH306
150_0402_1%
2
1

D

1

S

3

2

POWER

UH1J

CH41
0.1U_0201_16V4Z

+VCCACLK
1
0_0603_5%

CH47
0.1U_0201_16V4Z

@

2
RH276

+3V_PCH

CH52
0.1U_0201_16V4Z

+3V_DSW

CH44
0.1U_0201_16V4Z

@
QH4
AO3413L_SOT23-3

+3VALW

2

Title

PCH (7/8) PWR
Size

Document Number

Rev
0.1

LA-8043P
Date:

Sheet

Friday, March 02, 2012
1

20

of

58

5

4

3

2

1

UH1I

D

AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

UH1H

H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

C

B

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

PANTHER-POINT_FCBGA989

A

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

D

C

B

A

PANTHER-POINT_FCBGA989

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/29

2011/06/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

PCH (8/8) VSS
Size

Document Number

Rev
0.1

LA-8043P
Date:

Sheet

Friday, March 02, 2012
1

21

of

58

5

4

3

2

1

D

D

C

C

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/30

Deciphered Date

2013/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

ATI_SeymourXT_M2_PCIE/LVDS
Size
C
Date:

Document Number

Rev
0.1

LA7691P
Friday, March 02, 2012

Sheet
1

22

of

58

5

4

3

2

1

D

D

C

C

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/30

Deciphered Date

2013/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

ATI_SeymourXT_M2_Main_MSIC
Size
C
Date:

Document Number

Rev
0.1

LA7691P
Friday, March 02, 2012

Sheet
1

23

of

58

5

4

3

2

1

D

D

C

C

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/30

Deciphered Date

2013/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

ATI_SeymourXT_M2_BACO POWER
Size
C
Date:

Document Number

Rev
0.1

LA7691P
Friday, March 02, 2012

Sheet
1

24

of

58

5

4

3

2

1

D

D

C

C

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/30

Deciphered Date

2013/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

ATI_SetmourXT_M2_PWR_GND
Size
C
Date:

Document Number

Rev
0.1

LA7691P
Friday, March 02, 2012

Sheet
1

25

of

58

5

4

3

2

1

D

D

C

C

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/30

Deciphered Date

2013/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

ATI_SeymourXT_M2_Power
Size
C
Date:

Document Number

Rev
0.1

LA7691P
Friday, March 02, 2012

Sheet
1

26

of

58

5

4

3

2

1

D

D

C

C

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/30

Deciphered Date

2013/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

ATI_SeymourXT_M2_MEM IF
Size
C
Date:

Document Number

Rev
0.1

LA7691P
Friday, March 02, 2012

Sheet
1

27

of

58

5

4

3

2

1

D

D

C

C

B

B

A

A

Compal Secret Data

Security Classification
Issued Date

2011/06/30

Deciphered Date

2013/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
ATI_SeymourXT_M2_VRAM_A

Size
C
Date:

Document Number

Rev
0.1

LA7691P
Sheet

Friday, March 02, 2012
1

28

of

58

5

4

3

2

1

D

D

C

C

B

B

A

A

Compal Secret Data

Security Classification
Issued Date

2011/06/30

Deciphered Date

2013/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
ATI_SeymourXT_M2_VRAM_B

Size
C
Date:

Document Number

Rev
0.1

LA7691P
Sheet

Friday, March 02, 2012
1

29

of

58

5

3

1
1

2
2

C272
C273

PCH_DPB_P2
PCH_DPB_N2

PCH_DPB_P2 <16>
PCH_DPB_N2 <16>

0.1U_0402_16V7K
0.1U_0402_16V7K

1
1

2
2

C274
C275

PCH_DPB_P1
PCH_DPB_N1

PCH_DPB_P1 <16>
PCH_DPB_N1 <16>

PCH_DPB_P0_C
PCH_DPB_N0_C

0.1U_0402_16V7K
0.1U_0402_16V7K

1
1

2
2

C276
C277

PCH_DPB_P0
PCH_DPB_N0

PCH_DPB_P0 <16>
PCH_DPB_N0 <16>

+HDMI_5V_OUT
D57
+5VS

D

F1
1 +HDMI_5V

2

5

1

2

1.1A_6V_SMD1812P110TF
C279

1

0.1U_0402_16V4Z 2

2

R386

R385
100K_0402_5%

2.2K_0402_5%
2

2

> == 3, -,.
3
-?@ 645 /A 78 1320
9: .
2
1<2;

1

1

R387

+3VS

HDMI

1
0_0402_5%

5

2

2

2

2

2

2

2

2

R383680_0402_5%

R382680_0402_5%

R381680_0402_5%

R380680_0402_5%

R379680_0402_5%

R378680_0402_5%

R377680_0402_5%

R384
1

+3VS

1M_0402_5%

Q147B
4

L28
MBK1608221YZF_2P
HP_DETECT
1
2

<16> PCH_DDPB_CLK

1
1

D56
BAV99-7-F_SOT23-3
@

C278
220P_0402_50V7K

1
R390

2
2.2K_0402_5%
1

<16> PCH_DDPB_DAT

@
R392 1

WCM-2012-900T_0805
L29
1

0_0402_5%

2

4

3

1

2

HDMI_R_CK+

@1
@
C509

5V PULL UP IN CONNECTER SIDE

2
33P_0402_50V8J

3

C

+HDMI_5V_OUT

PCH_DPB_N3_C

R394 1

PCH_DPB_P0_C

R397 1

2

2

0_0402_5%

HDMI_R_CK-

@1
@
C510

2
33P_0402_50V8J

2

0_0402_5%

HDMI_R_D0+

@1
@
C511

2
33P_0402_50V8J

@

R395

2
3

@
1
C280

3
0_0402_5%

2

HDMI_R_D0-

@
PCH_DPB_P1_C

R399 1
4
WCM-2012-900T_0805
L31
1

@

0_0402_5%

2

4

3

1

2

PCH_DPB_N1_C

R400

1

PCH_DPB_P2_C

R401

1

HDMI_R_D1+

@1
C512

2
33P_0402_50V8J

@1
@
C513

2
33P_0402_50V8J

2

JHDMI1
HP_DETECT

+HDMI_5V_OUT
HDMI_SDATA
HDMI_SCLK

@
1

2

10P_0402_50V8J

4

R398 1

R396
2.2K_0402_5%

2
10P_0402_50V8J

L30
WCM-2012-900T_0805
4
PCH_DPB_N0_C

1

2

@

1

HDMI_SDATA

1

4

2.2K_0402_5%
2
1

PCH_DPB_P3_C

6

2N7002DWH_SOT363-6
SB00000AR10 Q147A

+3VS

SM070001310 400ma 90ohm@100mhz DCR 0.3

C

HDMI_SCLK

3

2

3

2N7002DWH_SOT363-6
SB00000AR10
+3VS

1

R389

2

5V Level

2

Q47A
2N7002KDW_SOT363-6

20K_0402_5%

HDMI_DETECT

6

2

2

2

Place closed to JHDMI1

1

<16> PCH_DDPB_HPD

1

Del HDMI Repeater PS8271

W=40mils
2N7002KDW_SOT363-6
Q47B
4

3

CH491DPT_SOT23-3

+3VS

2

1

0.1U_0402_16V7K
0.1U_0402_16V7K

PCH_DPB_P1_C
PCH_DPB_N1_C

1

PCH_DPB_P2_C
PCH_DPB_N2_C

1

PCH_DPB_P3 <16>
PCH_DPB_N3 <16>

1

PCH_DPB_P3
PCH_DPB_N3

1

C270
C271

1

2
2

1

1
1

1

0.1U_0402_16V7K
0.1U_0402_16V7K

R376680_0402_5%

D

4

PCH_DPB_P3_C
PCH_DPB_N3_C

C281

HDMI_R_CKHDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1-

3

HDMI_R_D1+
HDMI_R_D2-

2

2

0_0402_5%

HDMI_R_D1-

@1
C514

2
33P_0402_50V8J

2

0_0402_5%

HDMI_R_D2+

@1
@
C515

2
33P_0402_50V8J

HDMI_R_D2-

@1
C516

2
33P_0402_50V8J

@

HDMI_R_D2+

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

10/13 change conn to
DC232001000

20
21
22
23

HONGL_13-13201904CP

4
WCM-2012-900T_0805
L32
1
PCH_DPB_N2_C

@

4

3

1

2

R402 1

2
@

B

3
2
0_0402_5%

B

Follow EMI request add 33pF cap to GND.
11.02

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/29

Deciphered Date

2011/06/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HDMI Conn
Size

Document Number

Rev
0.1

LA-8042P
Date:

Friday, March 02, 2012

Sheet
1

30

of

58

5

4

3

2

1

+3V_AOAC

2
4
6
8
10
12
14
16

1
3

S

R91
PLT_RST#
0_0402_5%
17
CLK_PCI_DEBUG 1
2CLK_PCI_DEBUG_L 19
21
23
<15> PCIE_PRX_DTX_N2
25
<15> PCIE_PRX_DTX_P2
27
29
31
<15> PCIE_PTX_C_DRX_N2
33
<15> PCIE_PTX_C_DRX_P2
35
37
39
41
43
R58
45
0_0402_5%
47
E51TXD_P80DATA 1
2 E51TXD_P80DATA2_R
49
E51RXD_P80CLK_R
1
2
51
53
0_0402_5%
R57

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
G1

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
G2

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54

<15> CLK_PCIE_MINI1#
<15> CLK_PCIE_MINI1

BT_ON#

2
G
Q26
2N7002_SOT23-3

<6,17,22,34,36,42> PLT_RST#
<17> CLK_PCI_DEBUG

C

LPC_FRAME# <14,36,42>
LPC_AD3 <14,36,42>
LPC_AD2 <14,36,42>
LPC_AD1 <14,36,42>
LPC_AD0 <14,36,42>

W L_OFF#
PLT_RST_BUF#
R85

1

MINI1_SMBCLK
MINI1_SMBDATA

R86
R87

1
1

USB20_N9_R
USB20_P9_R

R88
R89

W L_OFF# <15>
PLT_RST_BUF# <17>
+3V_AOAC

2 0_0603_5%
@
@

2 0_0402_5%
2 0_0402_5%

1
1

2 0_0402_5%
2 0_0402_5%

R90 1
R101 1

2 0_0402_5%
2 0_0402_5%

PCH_SMBCLK
PCH_SMBDATA

PCH_SMBCLK <12,13,15>
PCH_SMBDATA <12,13,15>
USB20_N9 <17>
USB20_P9 <17>

MINI1_LED#

MINI1_LED# <36>
C

R92
4.7K_0402_5%

1

<36> E51TXD_P80DATA
<36> E51RXD_P80CLK

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

1

2
4
6
8
10
12
14
16

BT_ON_L

D

WL_OFF# Change from PCH GPIO55 to GPIO46.
(pull-high change from +3VS to +3V_PCH)
12.07

CONN@

1
3
5
7
9
11
13
15

<15> MINI1_CLKREQ#

BT_ON#

JMINI1

1
3
5
7
9
11
13
15

<16,34> PCH_PCIE_W AKE#

<18>

+1.5VS_W LAN
+3V_AOAC

(9~16mA)

BELLW _80003-2021

2

@ R84
0_0402_5%
1
2
R93
1
2
0_0402_5%

BT_ON

D

WLAN

R73
10K_0402_5%
+3V_AOAC

2

R100
0_0402_5%
1
2

<36> EC_PCIE_W AKE#

D

1

R73 pull high, and stuff R100
12.07

R70

2

+3V_AOAC
100K_0402_5%
BT_ON

For Wireless LAN
+3VS

2
1
1K_0402_5%
R326

E51RXD_P80CLK_R

+3V_AOAC
R83 @
0_1206_5%
2
1

+1.5V_PCIE

60mil
1

C86

1

R82
1

C87

+1.5VS_W LAN
0_0603_5%
2

1

4.7U_0603_6.3V6K 0.1U_0402_16V4Z
2
2

2

1

C82
4.7U_0603_6.3V6K

1

C83
0.1U_0402_16V4Z

2

C84
0.1U_0402_16V4Z

2

Mini Card Power Rating
Power

Primary Power (mA)

B

Auxiliary Power (mA)
B

Normal

Peak

Normal

+3VS

1000

750

+3V

330

250

250 (wake enable)

+1.5VS

500

375

5 (Not wake enable)

1

AOAC_PW _ON <37>
R370
1K_0402_5%

1

2

2

+3V_AOAC

0.047U_0402_16V7K

G

0.1U_0402_16V4Z

1

C69

2

+3V_AOAC

D

1

3

+3VALW

S

C85

2
Q11
AO3413L_SOT23-3
R95 @
0_1206_5%
2
1

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/29

Issued Date

Deciphered Date

2011/06/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

MiniCard & WLan
Size

Document Number

Rev
0.1

LA-8042P
Date:

Friday, March 02, 2012

Sheet
1

31

of

58

5

4

3

2

1

5

4

3

2

1

SI# 8/15 R62 change to +3VALW, R61change to 10 ohm, R63 change to 200K ohm
+LCDVDD

1

LCD POWER CIRCUIT
+3VS

+3VALW

R62
100K_0402_5%

1

2

2
3

R63
200K_0402_5%
2
1

S

2

C61
0.047U_0402_16V7K

1

C55

1

4.7U_0603_6.3V6K

2

1

C56
0.1U_0402_16V4Z

3
Q6B
DMN66D0LDW-7_SOT363-6

C59
680P_0402_50V7K

0.1U_0402_16V4Z

1

1

2

2

1

1

C60
68P_0402_50V8J

SM010014520 3000ma
220ohm@100mhz
DCR 0.04

D

LCD/LED PANEL Conn.

+LCDVDD

+3VS

W=60mils

R64

1

R65

1

C63
0.1U_0402_16V4Z

C62

2
4.7U_0603_6.3V6K

4

<16> PCH_ENVDD

2

C58

Q7
AO3413L_SOT23-3

W=60mils

2

5

10U_0603_6.3V6M

D

2

PCH_ENVDD

2

1

C57

G

1

2

6

D

Q6A
DMN66D0LDW-7_SOT363-6

9/8 SI build BOT limit 0.8, CH55
del: SE053475Z80
add: SE107475K80

1

2

1

INVPWR_B+
B+
L7
FBMA-L11-201209-221LMA30T_0805
2
1

+3VS

W=60mils

R61
100_0603_5%

W=60mils

Place closed to JLVDS1

+LCDVDD

C66

2

1 220P_0402_50V7K INVTPWM

C67

2

1 220P_0402_50V7K DISPOFF#

2 2.2K_0402_5%

W=60mils

LCD_CLK

2 2.2K_0402_5% LCD_DATA
1
1
@ C64
@ C65
10P_0402_50V8J
10P_0402_50V8J
2

2

9/8 SI build BOT limit 0.8, C62
del: SE053475Z80
add: SE107475K80

+3VS& +5VS for touch screen (choose one when getting spec) 12.09

C

R156

Change to smaller package
01.16

@
1

+LCDVDD

+5VS
C

2 0_0402_5%

L11
<17> USB20_P8

1

<17> USB20_N8

2

1

4

2

3

USB20_P8_R

4
3

JLVDS1

Part Number = SM070002900
USB20_N8_R
<16> PCH_LCD_CLK
<16> PCH_LCD_DATA

WCM-1210HS-900T_4P

1 R229

Delete

PCH_LCD_CLK

R193 2
R194 2

1 0_0402_5%
1 0_0402_5%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

LCD_CLK
LCD_DATA

USB20_P10_R
USB20_N10_R

2 0_0402_5%

INVT_PWM because EC pin 25 need to connect to BATT_TEMPA
@
@
1

2 0_0402_5%
<36>

L12
<16>

DPST_PWM

1 R197

2 0_0402_5%

INVTPWM

<17> USB20_P10

1

<17> USB20_N10

4

1

2

4

3

2

USB20_P10_R

3

USB20_N10_R

BKOFF#

BKOFF#

R74
10K_0402_5%

1 R230

2 0_0402_5%

<16> PCH_TXCLK+
<16> PCH_TXCLK-

1

@

@

Port 10 for touch screen
12.07

For easier layout routing
change the pin order 12.08

2

R72
10K_0402_5%

<16> PCH_TXOUT0<16> PCH_TXOUT0+
<16> PCH_TXOUT2+
<16> PCH_TXOUT2-

2

WCM-2012-900T_4P
B

<16> PCH_TXOUT1<16> PCH_TXOUT1+

1

R157

INVPWR_B+

+3VS
<38> D_MIC_CLK
<38> D_MIC_DATA

INVTPWM
BKOFF#

USB20_N8_R
USB20_P8_R
D_MIC_CLK
D_MIC_DATA

D8
D_MIC_CLK

2

D_MIC_DATA

3

1

Change to SCA00001W00
01.16

TVNST52302AB0_SOT523-3
@

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
41
36
G1
42
37
G2
43
38
G3
44
39
G4
45
40
G5
STARC_111H40-100000-G4-R

B

@

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/29

2011/06/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

LVDS Connector
Size

Document Number

Rev
0.1

LA-8042P
Date:

Sheet

Friday, March 02, 2012
1

32

of

58

5

4

3

2

1

D

D

mSATA Conn.
+3VS_MSATA

1

2

1

C44
4.7U_0603_6.3V6K

2

JMINI2

+3VS_MSATA

C45
0.1U_0402_16V4Z

1

1
3
5
7
9
11
13
15

C43
0.1U_0402_16V4Z

2

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53

C

<14> SATA_PRX_DTX_P1
<14> SATA_PRX_DTX_N1

C290 1
C291 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PRX_C_DTX_P1
SATA_PRX_C_DTX_N1

<14> SATA_PTX_DRX_N1
<14> SATA_PTX_DRX_P1

C292 1
C293 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_C_DRX_N1
SATA_PTX_C_DRX_P1

+3VS_MSATA

<18> HDD_DETECT#

HDD_DETECT#

1

2

0_0402_5%
R59 @

CONN@

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
G1

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
G2

R52
+3VS_MSATA

2
4
6
8
10
12
14
16

2
R53

+1.5VS_MSATA

2

0_0805_5%
1
0_0805_5%
1

+3VS
+1.5V_PCIE

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54

C

BELLW_80003-2021

Exchange port 0 & port 1 for SI as customer request
11.30

Change footprint to Starconn (PAD is bigger)
11.30
JHDD1

+5VS_HDD1

<14> SATA_PTX_DRX_P0
<14> SATA_PTX_DRX_N0

B

<14> SATA_PRX_DTX_N0
<14> SATA_PRX_DTX_P0

C286 1
C287 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

C288 1
C289 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0

1
2
3
4
5
6
7
8
9
10
11
12

CONN@

1
2
3
4
5
6
7
8
9
10
GND
GND

B

ACES_50208-00801-003

STARC_111D10-000000-G4-R
10
9

SATA connector

+5VS_HDD1

100mils
+5VS

+5VS_HDD1

2

1

2

1

2

C285
1000P_0402_50V7K

2

1

C284
0.1U_0402_16V4Z

1

C283
1U_0402_6.3V4Z

2
0_0805_5%

C282
10U_0603_6.3V6M

1
R403

SATA_PTX_C_DRX_P0 R20 @
@1
SATA_PTX_C_DRX_N0 R21 @1
@

2 0_0201_5%
2 0_0201_5%

SATA_PTX_C_DRX_P0_R
SATA_PTX_C_DRX_N0_R

SATA_PRX_C_DTX_N0 R22 @
@1
SATA_PRX_C_DTX_P0 R23 @1
@

2 0_0201_5%
2 0_0201_5%

SATA_PRX_C_DTX_N0_R
SATA_PRX_C_DTX_P0_R

8
7
6
5
4
3
2
1

GND
GND
8
7
6
5
4
3
2
1
JHDD2

CONN@

Co-layout for wire type connector
01.16
Change connector to ACES_50376
01.31
Change connector to ACES_50208 because current limit issue
02.06

Chagne 0805 to 0603
12.08
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

2011/06/29

Deciphered Date

2011/06/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

A

2

Title

mSATA Connector
Size
C
Date:

Document Number

Rev
0.1

LA-8042P
Friday, March 02, 2012

Sheet
1

33

of

58

5

4

3

@
R404 0_1206_5%
1
2

W=60mils
+3VALW
Q148

1

1.5K_0402_5%
SDA
2

EEPROM(TWSI)
44
42

SDA
SCL/LED_CR

1
2
4
5
6
7
9
10

XTLI
XTLO

59
60

+LAN_SROUT1.0V
ENSWREG

48
45

+LAN_VDDREG

46
47

1
Y9

62
LAN_LED0
LAN_LED1

51
49
43

C311

DVDD10
DVDD10
Clock

AVDD10
AVDD10
AVDD10

REGOUT
ENSWREG_H

EVDD10
Card_3V3

VDDREG
VDDREG

VDD33/18
VDD33/18

RSET

SI2 Y9 change to SJ10000DJ00
12.19

GND
GND
GND9(Exposed Pad)

LEDs

+LAN_VDD_1V0
R427
1

3.3V : Enable Switching Regulator
(Default,For Power Efficiency)
0V
: Enable LDO Regulator

C321

Switching Regulator Circuit

+LAN_VDDREG

C317
4.7U_0603_6.3V6K

1

1
C318

2

2

Close to Pin46,47

0.1U_0402_16V7K

2

2
+LAN_VDD_1V0

W=60mils

1

R423

2

2 LAN_ACTIVITY#

1

2

C328 1

@
2

1
3

0.1U_0402_16V7K

Stuff D58 as EMI request 11.22

13

1
+VDD33/18

33
53

2

24
32
65

VDD33/18 for SD UHS Mode Power
+VDD33/18

1

2

C313
1
@

2

1

2

Correct footprint
02.13

C316
1

2

JLAN1
@

Close to Pin53

+LAN_VDD_1V0

1
C322
2

1
C323
2

2

C508
1

LAN_MDIP0

1

LAN_MDIN0

2

+V_DAC

3

+V_DAC

4

LAN_MDIP1

5

LAN_MDIN1

6

LAN_MDIP2

7

LAN_MDIN2

8

+V_DAC

9

+V_DAC

10

1
C324

1

C325

2

2

1
C326

1

C327

2

2

RJ45_TX3-

8

RJ45_TX3+

7

RJ45_RX1-

6

RJ45_TX2-

5

RJ45_TX2+

4

RJ45_RX1+

3

RJ45_TX0-

2

RJ45_TX0+

1

GND
PR4GND

12
11

PR4+
PR2PR3PR3+
PR2+

B

PR1GND
PR1+
GND
SANTA_130460-3

TD1+

TX1+

TD1-

TX1-

TDCT1

TXCT1

TDCT2

TXCT2

TD2+

TX2+

TD2-

TX2-

TD3+

TX3+

TD3-

TX3-

TDCT3

TXCT3

TDCT4

TXCT4

24

RJ45_TX0+

23

RJ45_TX0R430
R431
R432
R433

22
21
20

RJ45_RX1+

19

RJ45_RX1-

18

RJ45_TX2+

17

RJ45_TX2-

1
1
1
1

10
9

@

2 75_0402_5%
2 75_0402_5%
2 75_0402_5%
2 75_0402_5%

2

1

C329
SE167100J80
10P_1808_3KV
1

16

C330

11

LAN_MDIN3

12

TD4+

TX4+

TD4-

TX4-

0.1U_0402_16V4Z
D59
2
L34
TVNST52302AB0_SOT523-3

15
14

RJ45_TX3+

13

RJ45_TX3-

1

350UH_NA0069RLF
SP050006Y00

2

C331
4.7U_0603_6.3V6K
A

2

LAN_MDIP3

TS1 change from SP050006X00
to SP050006Y00& SP050006P00
10/12

100UH_SSC0301101MCF_0.18A_20%

Change P/N from SCA00000T00 to SCA00001L00
11.01
Stuff D59 as EMI request 11.22

3

2

Add LAN LED White& Amber on M/B
10.12
Change power rail to +LAN_VDD_3V3
02.03
5

2

LINK_100_1000#

+CR_VDD_3V3
+LAN_EVDD10

29

3

+LAN_VDD_3V3

1

2 470P_0402_50V8J

TVNST52302AB0_SOT523-3

3
8
61

0.01U_0402_16V7K

LED9
LINK_100_1000#

C309 1

TS1

+LAN_VDD_3V3

White

33_0603_1%
LTW-110DC5-C_WHITE

2 470P_0402_50V8J

LAN_ACTIVITY#

Close to Pin29

A

2

C308 1

C320
0.1U_0402_16V7K

330_0603_5%

1

2

C

LINK_100_1000#

+LAN_VDD_1V0

41
52

0.1U_0402_16V7K

R429

1

2

LED10

1

2

D58

4.7U_0603_6.3V6K

HT-110UD_1204

LAN_LED1

0.1U_0402_16V7K

+LAN_VDD_3V3

11
58
63
64

Change from SHI0000F400 to SH00000RK00
Z-high issue.
3/8

LAN_LED0

1

Place each cap. to Pin 3, 8 , 41 , 52 ,61
1

C319

Amber

2

1

R428
1
0_0603_5%

12
39

+LAN_EVDD10

2

1

SH00000RK00
L33
+LAN_SROUT1.0V
1
2
2.2UH +-5% NLC252018T-2R2J-N
DELTA_1008HC-472EJFS-A_2P

1

R419 0_0402_5%
@
1
2

GPO

Close to Pin33

0_0603_5%

+LAN_VDD_3V3

D

EMI-ESD

Reserved for LAN PHY Disable Application

RTL8411-CG_QFN64_9X9

R424 0_0402_5%
2
1
@

2

2

ENSWREG

LED0
LED1
LED3

1

1

R426 0_0402_5%
2
1

+LAN_VDD_3V3

B

AVDD33
AVDD33
AVDD33
AVDD33

2.49K_0402_1%
XTLO

2

4.7U_0603_6.3V6K

2

1
C305 @
5P_0402_50V8C

4.7U_0603_6.3V6K

R425
1

GPO

DVDD33
DVDD33

Regulator and Reference

25MHZ_20PF_7V25000016

2

LAN_ACTIVITY#
Pin

MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3
CKXTAL1
CKXTAL2

GPO

1
SD_CLK
SD_CMD
SD_WP
SD_CD#

C314
0.1U_0402_10V7K

LAN_MDIP0
LAN_MDIN0
LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
LAN_MDIP3
LAN_MDIN3

50

SD_CLK

C315
0.1U_0402_10V7K

27P_0402_50V8J

HSOP
HSON
HSIP
HSIN

GPO
PN : SA00005B400

1

2

Add +5VS& more pin for +CR_VDD_3V3
2012.01.10

@ C507
5P_0402_50V8C

30
31
25
26

SD_CMD

3

R418
Strapping
1
+LAN_VDD_3V3

Delete 0 ohm
11.05

22
24
26

GND
GND
GND

@ C506
5P_0402_50V8C

PCIE_PRX_C_DTX_P1
PCIE_PRX_C_DTX_N1
PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1

Transceiver Interface

GND

GND
GND
GND

+CR_VDD_3V3

0_0402_5%
SD_D0_R
2
0_0402_5%
SD_D1_R
2
0_0402_5%
SD_D2_R
2
0_0402_5%
SD_D3_R
2
0_0402_5%
SD_CMD_R
2
0_0402_5%
SD_CLK_R
2
@ C504
5P_0402_50V8C

LAN_CLKREQ#_R

PERSTB
CLKREQB

SD_D3

R407
1
R409
1
R411
1
R413
1
R415
1
R416
1

@ C503
5P_0402_50V8C

37
36

REFCLK_P
REFCLK_N

SD_D0
SD_D1
SD_D2
SD_D3

0.1U_0402_16V7K

2 0.1U_0402_16V7K

27
28

19
18
23
22
17
16
15
14
20
21
35
54
34
55
56
57

1U_0402_6.3V6K

C307 1

1
1

Card Reader
SD_D0/MS_D7/xD_D5
SD_D1/MS_CLK/xD_D6
SD_D2/xD_D7
SD_D3/MS_D2/xD_D2
SD_D4/xD_WE#
SD_D5/xD_CE#
SD_D6/MS_INS#/xD_RE#
SD_D7/xD_RDY
SD_CLK/MS_D3/xD_D4
SD_CMD/MS_D6/xD_D3
SD_WP/MS_D1/xD_WP#
SD_CD#/MS_D5/xD_ALE
MS_BS/xD_CLE
MS_D4/xD_D0
MS_D0/xD_D1
XD_CD#

0.1U_0402_16V7K

2 0.1U_0402_16V7K

ISOLATEB

SD_D2

ISOLATEB
LANWAKEB
PCI-Express

CLK_PCIE_LAN
CLK_PCIE_LAN#

SD_D1

C312
0.1U_0402_10V7K

GND

21
23
25

0.1U_0402_16V7K

38
40

3

2

2

0.1U_0402_16V7K

ISOLATEB
LANWAKEB

2 0_0402_5%

XTLI

3

1

SD_D0
U70
Power Manahement/Isolation

1 R414
2 @
10K_0402_5%

C310
2

4

0.1U_0402_16V7K

2 10K_0402_5%

R421
15K_0402_5%

27P_0402_50V8J
1

2

SATA_LED# <14>
HDDHALT_LED# <14>
PWR_LED# <36,37>
TP_ON_OFF_LED# <36>

C302
0.1U_0603_25V7K

2 0_0402_5%

C306 1

2
1K_0402_5%

1
C300

SATA_LED#
HDDHALT_LED#
PWR_LED#
TP_ON_OFF_LED#

2

R417
<15> CLK_PCIE_LAN
0_0402_5%
<15> CLK_PCIE_LAN#
LAN_CLKREQ# 2
1 LAN_CLKREQ#_R
<6,17,22,31,36,42> PLT_RST#

1
R420

2

0.1U_0402_16V7K

1
+3VS

1
C299

2
4
6
8
10
12
14
16
18
20

2
4
6
8
10
12
14
16
18
20

PANAS_AXK7L20213G

2

C

@

R412 1

<15> PCIE_PRX_DTX_N1
<15> PCIE_PTX_C_DRX_P1
<15> PCIE_PTX_C_DRX_N1

2

0.1U_0402_16V7K

2
Q149
R406
SSM3K7002FU_SC70-3

R408 1

<15> PCIE_PRX_DTX_P1

1
C298

Note:
1. C38: Close to Pin12(DVDD33) for avoiding voltage drop when inserting card.
2. The rise time of +LAN_VDD_3V3 must >1ms and <100ms for the internal LDO.

1.5M_0402_5%

3

S

+LAN_VDD_3V3

<15> LAN_CLKREQ#

2

+3VS

1
3
5
7
9
11
13
15
17
19

@ C505
5P_0402_50V8C

1
1

D

R410 1

<16,31> PCH_PCIE_WAKE#

1
C297

1
3
5
7
9
11
13
15
17
19

SD_D3_R
SD_CMD_R
SD_CLK_R
SD_D0_R
SD_D1_R
SD_D2_R
SD_WP
SD_CD#

EN_WOL

2
G

+LAN_VDD_3V3

2

0.1U_0402_16V7K

1
C296

D

<36> EC_PME#

0.1U_0402_16V7K

2

2

0.1U_0402_16V7K

C295

R405
470K_0402_5%

<36> WOL_EN

These caps close to U1: Pin 11,12,39,58,63,64

D
2

2
+VSB

+5VALW

JP10

1.5A

C301
10U_0603_6.3V6M

1

G

S

1
AO3413L_SOT23-3

1

Pin2 change to +5VALW cause
power LED is on S/B
11.30

+5VS

+LAN_VDD_3V3

3

1

C294
1U_0402_6.3V6K

2

W=60mils

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/29

2011/0/03

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title
Size
Date:

LAN&CardReader Realtek RTL8411

Document Number

Rev
0.1

Thursday, March 08, 2012

Sheet
1

34

of

58

A

B

+5VALW

2

1

1
+

G547I2P81U_MSOP8

C90
2

W=80mils

1
C91
2

1
C92
2

R94
1

USB_ON#

<36> USB_ON#

E

0.1U_0402_16V4Z

8
7
6
5

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

1000P_0402_50V7K

1
C89

0.1U_0402_16V4Z

2

1
2
3
4

1000P_0402_50V7K

1
C88

D

U3

W=80mils

150U_B2_6.3VM_R45M

USB3.0

C

USB3.0 need support 2.5A
change USB PWR SW SA00003TV00
low active
+USB_AS

2

USB_OC0#

1

USB_OC0# <17>

0_0402_5%
@

SI# 8/8 change USB_OC0# to USB30_OC#

D10
TVNST52302AB0_SOT523-3

R227
1

2

USB3_TX1_N

<17> USB3_TX1_N

@

0_0402_5%
2

USB3RXDN1_C

1
USB3_TX1_P

<17> USB3_TX1_P

USB3_RX1_N

<17> USB3_RX1_N

3

4

3

1
L21

2
2
USB30@

1
R228
R231
1

2
0_0402_5%
0_0402_5%
2

@
@

4

1 C96
1 C95

2
2

USB3TXDN3_C_R
USB3TXDP3_C_R

R141
1

USB3_TX3_N

USB3RXDN1_C

10 9

USB3RXDP1_C

2 2

9 8

USB3RXDP1_C

USB3TXDN1_C_R

4 4

7 7

USB3TXDN1_C_R

USB3TXDP1_C_R

5 5

6 6

USB3TXDP1_C_R

4

1

8

<17> USB3_RX3_N

USB3RXDN1_C

USB3_RX3_N

IP4292CZ10-TB

<17> USB3_RX1_P

<17>

1
R232

1
Part Number = SC300002500

R233
1

USB20_N0

USB20_N0

D12
USB3RXDP1_C

2
@ 0_0402_5%
@

0_0402_5%
2

USB20_N0_C

WCM-2012-900T_4P
4
1

<17>

USB20_P0

USB20_P0

4

3

1
L23

2

USB3RXDN3_C

1 1

10 9

USB3RXDN3_C

USB3RXDP3_C

2 2

9 8

USB3RXDP3_C

USB3TXDN3_C_R

4 4

7 7

USB3TXDN3_C_R

USB3TXDP3_C_R

5 5

6 6

USB3TXDP3_C_R

<17> USB3_RX3_P

<17>

USB20_N2

3 3
8
USB20_P0_C

2

4

3

2
3

USB30@

1

2

4

3

2
3

@

0_0402_5%
2

USB20_N2_C

L26
1

2

2

R236
1

USB20_N2

3

2
@ 0_0402_5%

USB3TXDN3_C

USB30@

1

WCM-2012-900T_4P
USB3RXDP3_C
1
2
R224 @
0_0402_5%

USB3_RX3_P

4

6/27 Add ESD solution

<17>

Part Number = SC300002500

USB20_P2

1

2

4

3

2
3

WCM-2012-900T_4P
1
2
R235
@ 0_0402_5%

IP4292CZ10-TB

1
R234

@ 0_0402_5%
2

L25

6/27 Add ESD solution

2
2
USB30@

1
L22

10
11
12
13

WCM-2012-900T_4P
USB3TXDP3_C
1
2
R142 @
0_0402_5%
@
R2231
2 0_0402_5% USB3RXDN3_C

USB3_TX3_P

<17> USB3_TX3_P

4

USB3_RX1_P

GND
GND
GND
GND

L24
1

3 3

3

3

0.1U_0402_10V7K
0.1U_0402_10V7K

<17> USB3_TX3_N

1 1

USB3TXDP1_C

WCM-2012-900T_4P
4

USB3TXDN3_C
USB3TXDP3_C

VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+

SANTA_373070-1

D9

USB3TXDN1_C

WCM-2012-900T_4P
4

USB3RXDN3_C
USB3RXDP3_C
D11
TVNST52302AB0_SOT523-3

1

SANTA_373070-1

1
2
3
4
5
6
7
8
9

USB20_N2_C
USB20_P2_C

3

10
11
12
13

GND
GND
GND
GND

JUSB4 @

USB20_N2_C
USB20_P2_C
2

1 C93
1 C94

USB20_N0_C
USB20_P0_C

Change conn to SANTA-373070
10/18

1

USB3TXDN1_C_R
USB3TXDP1_C_R

@

VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+

3

USB3RXDN1_C
USB3RXDP1_C

Change P/N from SCA00000T00 to SCA00001L00
11.01
Change P/N to SCA00001W00 for smaller size, 10*10 choke
02.13

2

JUSB1
1
2
3
4
5
6
7
8
9

USB20_N0_C
USB20_P0_C

USB3TXDN1_C 0.1U_0402_10V7K 2
USB3TXDP1_C 0.1U_0402_10V7K 2

+USB_AS

Change conn to SANTA-373070
10/18

+USB_AS

USB20_P2

USB20_P2_C

3

3

VL

+2543PWR

+USB_VCCB

USB charger footprint need change to TPS2543

RH336

Delete C336 (150UF), and put it on S/B
12.08

2

USB_CTL2_R

2
USB_CHARGE_EN_R

B

O

2

A

3

1

2 0_0402_5%

13

USB20_N1
USB20_P1

2
3

USB20_N1
USB20_P1

ILIM_SEL
USB_CHARGE_EN#
USB_CTL1
USB_CTL2
+3VL

R2602
0_0402_5%
0_0402_5%1
R2603
0_0402_5%
0_0402_5%1
R2601 10K_0402_5%
10K_0402_5%1

2
2
2

USB_CTL1_R
USB_CTL2_R
USB_CTL3_R

6
7
8

CTL1
CTL2
CTL3

ILIM1
ILIM0

1

11
10
15
16

R2499
R437

2
2

USB_IN_STATUS#

USB_IN_STATUS#

2
1
1 19.1K_0402_1%
19.1K_0402_1%

0_0402_5%
2

U2D_DN1_C

WCM-2012-900T_4P

14
17

4

3

2

1
U2D_DP1

1
L27
1
R237

2

W=80mils
1

10mil
+VSB

10mil

2
1
R187
20K_0402_5%

2

3
USB_IN_STATUS#

TPS2543RTER_QFN16_3X3

Fixed to high
01.16

R238 @
1

U2D_DN1

4
GND
GPAD

<48>

5

1
C186
0.1U_0603_25V7K
QH9B
2N7002DWH_SOT363-6
2

1

2

USB_CHARGE_EN_R
1
2N7002KTB_SOT523-3

Modify 0301
U2D_DP1_C

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/29

Deciphered Date

2011/06/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

4

Q12

3

<36> USB_CHARGE_EN

2

2
@ 0_0402_5%

Follow EMI request add choke
11.08

A

+3VALW

D

USB_CTL1
USB_CTL2

ILIM_SEL
EN

R2604 2
0_0402_5%
U2D_DN1
U2D_DP1

9

+2543PWR

SI7326DN-T1-E3_PAK1212-8
U4
1
2
3
5

W=80mils

S

<36>
<36>

4
5

NC

DM_OUT DM_IN
DP_OUT DP_IN

1

G

4

FAULT#

1

C97
0.1U_0402_16V4Z

<17>
<17>

12

4

R434 1

USB_OC4#

OUT

17
18

17
18

ACES_85201-1605

C518
10U_0603_6.3V6M

<17>

IN

2

3

+5VALW
U27
1

U2D_DN1_C
U2D_DP1_C
1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

4

1

ILIM_SEL

C99
0.1U_0402_16V4Z

2

10K_0402_5%

C98
1000P_0402_50V7K

2
R436

4 USB_CHARGE_EN#
Part Number = SA00003Y000

R145
1M_0402_5%

Delete C338 (10UF) for test point (placement issue)
02.14

+USB_VCCB

P

1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

HP_L
HP_DET#
MIC1_L
MIC1_R
MIC_SENSE

C345
1U_0402_6.3V6K

1

C337
0.1U_0402_16V4Z

+3VL

RH337
100K_0402_5%

U7
74AHC1G09GW_TSSOP5

5

R143
100K_0402_5%

HP_R

HP_R

<40>
HP_L
<38> HP_DET#
<41> MIC1_L
<41> MIC1_R
<38> MIC_SENSE

G

2

USB_CTL1_R
R139
100K_0402_5%

2

2

2

1

1

2

1

2
1

1

C341
1U_0402_6.3V6K

2

C340
1U_0402_6.3V6K

1

R24
0_0201_5%

C339
1000P_0402_50V7K

TPS2543 : SA000059H00 pin 9 (Status); 2540 pin9 (NC)

<40>
1

100K_0402_5%

VL

JIO1 @

2

USB2.0 & charger

VL

1

Delete pull-high resistors
01.16

C

D

Title

USB Con & Daughter Con
Size
C
Date:

Document Number

Rev
0.1

Monday, March 05, 2012

Sheet
E

35

of

58

5

4

3

2

1

+3VALW_EC

1

2
1

R99

2

R107

1

2

4.7K_0402_5%

BKOFF#

R109
@

+3VALW_EC
D

R137
56K_0402_5%

R112
100K_0402_5%
2
1

1

2 47K_0402_5%

1

2 2.2K_0402_5%

EC_SMB_DA1

1

2 2.2K_0402_5%

EC_SMB_CK1

KSO2

1

2 1K_0402_5%

EC_SCI#

M2
L2
M3
K4
N3
M4
K5
N4

CLK_PCI_LPC
PLT_RST#
EC_RST#
EC_SCI#
NMI_DBG#

N5
M5
K13
N6
M6

<37> KSI[0..7]

+3VALW
EC_SMI#
<37> KSO[0..15]
R439

C222

2

1

2

33_0402_5%

22P_0402_50V8J

R440

C221

CLK_PCI_LPC 1

2

1

33_0402_5%

2
22P_0402_50V8J

6/27 add 33 ohm and 22p by EMI request

R120

<18> SLP_ME_CSW_DEV#
<16>
SLP_A#

2 10K_0402_5% EC_SCI#

1

1 R195
1 R196

EC_SMB_CK1
EC_SMB_DA1
R121 1
2 0_0402_5%
R122 1
2 0_0402_5%

<42,46,47> EC_SMB_CK1
<42,46,47> EC_SMB_DA1
<15,23,40> EC_SMB_CK2
<15,23,40> EC_SMB_DA2

D9
E12
E13
D12
D13
C12
C13
D10
J13
J12
H12
H13
H10
H9
G9
G10
G13
G12
F13
F12
F10
F9
E10
E9
E8
D8
A8
A7
B8
A6

AVCC
INVT_PWM/PWM0/GPIO0F
BEEP#/PWM1/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

AD

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PS2 Interface

SPI Flash ROM

GPIO

2 GPIO0

GPIO0

<18>

<18>
EC_SMI#
<43> PCH_PWR_EN

CH751H-40PT_SOD323-2

Change to BATT_TEMPA in SI
X1
EC_XCLK1 1

2

2

<45>
<16>
<46>
<37>

AC_LED#
SUSWARN#
BATT_TEMPA
FAN_SPEED1

<31> E51TXD_P80DATA
<31> E51RXD_P80CLK
<38>
EAPD

2EC_XCLK0

32.768KHZ_12.5PF_Q13FC1350000
1
1
@

PCH_PWR_EN

<35> USB_CTL1
<35> USB_CTL2

C112 @
15P_0402_50V8J

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

GPI

Reserve USB_CTL 11.03
<16>

R124
1

SUSCLK_R

1
C71
220P_0402_50V7K

2

EC_XCLK1
EC_XCLK0
0_0402_5%

J1
K1

R66
100K_0402_5%

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

XCLKI
XCLKO

V18R

KB930BF A1 LFBGA 128P

2

2

ADP_I

<46,47>

PM_SLP_SUS# <16>
+3VALW_EC

R118
0_0402_5%
2
1

VR_HOT#

VR_HOT#

EC_PCIE_WAKE# <31>

Reserve EC_PCIE_WAKE#
11.03
H_PROCHOT#_EC

<46> H_PROCHOT#_EC

0_0402_5%
R200 2
1

H_PROCHOT#

<6,46>

2N7002DWH_SOT363-6
Q10B

5

Pin76 PU follow EC request
(Common code to DM3, DM6)
PCH_VREG_EN# <20>11.03

Delete DA output for FAN change to PWM

D6
E6
E5
D5
A5
B5

TP_ON_OFF_LED#
USB_ON#
WLAN_OFF_LED
PCH_PWROK
TP_CLK
TP_DATA

B1
A1
C1
C2

AOAC_PW_ON#
WOL_EN
HDA_SDO
EC_PME#

K2
J2
M1
N2

EC_SI_SPI_SO
EC_SO_SPI_SI
EC_SPICLK_L
EC_SPICS#/FSEL#

TP_ON_OFF_LED# <34>
USB_ON# <35>
WLAN_OFF_LED# <37>
PCH_PWROK <16>
TP_CLK <37>
TP_DATA <37>

C

+3VALW_EC

R144

1

2

0_0402_5%

20mils

AOAC_PW_ON# <37>
WOL_EN <34>
HDA_SDO <14>
EC_PME# <34>

1

2
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO07
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

GND
GND
GND
GND
GND

D14
1

BOARD_ID
ADP_I
PROJECT_ID
PM_SLP_SUS#
R123 1
2 10K_0402_5%

B10
A9
A10
B9

<54>

1 100P_0402_50V8J ECAGND
EC_PCIE_WAKE#

SPI Device Interface

J8
J10
J9
N13
G2

NMI_DBG#

PM_SLP_S3#
J5
PM_SLP_S5#
N9
EC_SMI#
L13
R199 2 43_0402_1%K6
1
N7
AC_LED#
M7
SUSWARN#
N8
BATT_TEMPA
K8
FAN_SPEED1
M11
N11
E51TXD_P80DATA
K10
E51RXD_P80CLK
K9
EAPD
N12
USB_CTL1
M13
USB_CTL2
L12

B13
A13
B12
A12
E7
D7

KB_BKL_LED# <37>
MINI1_LED# <31>
KBL_OFF# <37>

MINI1_LED#
KBL_OFF#
1 0_0402_5%
FAN_PWM <37>

<16,23,47>

U6

SM Bus

1

2

B

<16> PM_SLP_S3#
<16> PM_SLP_S5#

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

R443
10K_0402_5%

For PCI SERR

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

DA Output

KB_BKL_LED#
M9
M8
M10 R191 2
FAN_PWM
N10
C108 2

PWM Output

1

+3VALW_EC

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
2 0_0402_5%
2 0_0402_5%

GA20/GPIO00
KBRST#/GPIO01
SERIRQ
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

ACIN

1 100P_0402_50V8J

2

3

GATEA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

C

1

C109

4

<18>

R111

R110

CH751H-40PT_SOD323-2
1

2

D5

^
_`
a
b
c
B
C
D
E
F

KSO1

R105

R113

EC_ACIN

1. Delete 2543PWR_ON#, 01.30
2. KB_BKL_LED# change to GPIO0F, 01.16

AGND

2 47K_0402_5%

1

2 10K_0402_5%

1

R114
R115
R116
R117

2
2
2
2

0_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%

B7
B4
A4
B3
A3
A2
B2
H5
N1

EC_PECI R119 1
243_0402_1% H_PECI
AOAC_PME#
AOAC_PME# <17>
R217 1 0_0402_5%
2
BAT_CHG_LED <45>
CAP_LOCK#
CAP_LOCK# <37>
PWR_LED#
PWR_LED# <34,37>
R218 2
1 0_0402_5%
WLAN_ON_LED# <37>
SYSON
SYSON
<43,51,52>
VR_ON
VR_ON
<54>
PM_SLP_S4#
PM_SLP_S4# <16>

D4
D1
D2
E2
E4
E1
F4
F2
F1

7

EC_SPICS#/FSEL#_R 1

ENBKL <16>
H_PECI <6,18>

PCH_RSMRST#
PCH_RSMRST# <16>
0_0402_5% R212
EC_LID_OUT# <18>
PCH_DPWROK
2
1
PCH_DPWROK <16>
H_PROCHOT#_EC
SUSACK#
SUSACK# <16>
BKOFF#
BKOFF#
<32>
CPU1.5V_S3_GATE
CPU1.5V_S3_GATE <10>
USB_CHARGE_EN
USB_CHARGE_EN <35>
SA_PGOOD
SA_PGOOD <53>

3

0.1U_0402_16V4Z

EC_SI_SPI_SO_R
EC_SO_SPI_SI_R
EC_SPICLK_L_R
EC_SPICS#/FSEL#_R

Delete PX_MODE bcuz PX5.0 is ready.
ENBKL
R134 1 0_0402_5%
B6 10.20
2

EC_SPICLK_L_R

6

EC_SO_SPI_SI_R

5

VCC

VSS

4

W
HOLD
S
C
D

Q

EC_SI_SPI_SO_R

2

MX25L2006EM1I-12G SOP 8P

C114
EC_SPICLK_L_R

1

22P_0402_50V8J
2
B

Delete EMI reserve R129& C119.
01.18

EC_ACIN
R136
F5
EC_ON
G1
2
1
+3VALW_EC
EC_ON
<37>
ON/OFF#
47K_0402_5%
G5
ON/OFF# <37>
LID_SW#
H1
LID_SW# <37>
SUSP#
G4
SUSP#
<10,43,49,50,51>
PBTN_OUT#
H4
PBTN_OUT# <16>
H2 2
1 DRAMRST_CNTRL_PCH
DRAMRST_CNTRL_PCH <7,10,15>
R221 @
0_0402_5%
+V18R
L1
1
C113

2

20mil

1
1
1
1

8

SPIPIN3

C110

HGI
II
I
KJL
II
GM
KON
LP
QR
QS
JT
LIP
I
HT
QK
UL
VJ
WXG

<17,42> CLK_PCI_LPC
<6,17,22,31,34,42> PLT_RST#

10/1 ENE Recommand
R104

15P_0402_50V8J

TP_DATA

Y
[XZZ
\]

<18>
GATEA20
<18> EC_KBRST#
<14,42> SERIRQ
<14,31,42> LPC_FRAME#
<14,31,42> LPC_AD3
<14,31,42> LPC_AD2
<14,31,42> LPC_AD1
<14,31,42> LPC_AD0

0.1U_0402_16V4Z

1

+3VALW_EC

@ C111

4.7K_0402_5%

EC_RST#

A11

1 47K_0402_5%

C107 2

+3VS

2

1
B11

J7
K7
K12
M12
J6
J4
VCC
VCC
VCC
VCC
VCC
VCC

R106 2

SUSACK#

1

+3VS

BOARD_ID

2

U5

+3VALW_EC

R102

R125
100K_0402_5%

C106
0.1U_0402_16V4Z

Follow EC request, PV2 phase
use 56K resistor.
02.13

R155 30UMA@
33K_0402_5%

TP_CLK

1

1
1
D

1

2

C105
1000P_0402_50V7K

2

2

C104
1000P_0402_50V7K

R155
50DIS@
200K_0402_5%

2

1

C103
0.1U_0402_16V4Z

PROJECT_ID

2

1

C102
0.1U_0402_16V4Z

2

1

C101
0.1U_0402_16V4Z

R155
50UMA@
100K_0402_5%

C100
0.1U_0402_16V4Z

1

R154
100K_0402_5%

+3VALW_EC

+3VALW_EC

L9
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA

+3VALW_EC

2

R98
0_0805_5%
2

ECAGND

2

1

2

+3VALW

R155
30DIS@
56K_0402_5%

0_0402_5%
1

+3VALW_EC

4.7U_0603_6.3V6K

L10

ECAGND 2
1
FBMA-L11-160808-800LMT_0603

JFW1

A

KSO2
KSO3
KSI5
KSI4
KSI6
KSI7
E51TXD_P80DATA

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
GND
GND

R126
1
R127
1
R128
1
R130
1

A

100K_0402_5%
2 PLT_RST#
10K_0402_5%
2 PCH_DPWROK
10K_0402_5%
2 PCH_PWROK
10K_0402_5%
2 VR_ON

Compal Secret Data

Security Classification

ACES_50521-00841-001
@

Issued Date

2011/06/29

2011/06/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
EC ENE-KB930 & 9012

Size Document Number
Custom
Date:

Rev
0.1

LA-8041P
Sheet

Friday, March 02, 2012
1

36

of

58

i
j
k
l
m
n
o
p
nq
r
ps
tu
tr
vu
q

<36>

+3VALW_EC

R131
100K_0402_5%

1

1

1

2/3 add R462/R463 for PWM

2

2

6/27 add 33 ohm and 22p by EMI request

1

2

<36> FAN_SPEED1
<36> FAN_PWM

1 R50
2
0_0603_5%

<38>

1
2
3
4

FAN_PWM_R

1 GND
2 GND
3
4

5
6
+3VALW

+5VALW

MUTE_LED

<36> CAP_LOCK#

R372 1

<36> KB_BKL_LED#

R374 1

ACES_50271-0040N-001

+3VS

2 360_0402_5%
+5VS
2 360_0402_5%

11.01 change K/B symbol
Amber

2
3

5

WLAN_ON_LED#

+5VS_KBL

<36>

R369
2

G
@

G1
G2

1
2
3
4

1

ACES_50504-0040N-001

2

Change the connector to ZIF type
12.02

U28

MRDLY
VCC
GND
RESET
CD
MR

TP/B TO M/B

6
5
4

KBC_HANGUP_RESET#

+3VALW_EC

<48>

6/27 Add ESD solution

Q3 @
SSM3K7002FU_SC70-3

2
G
1

<36>
<36>

C116

2

2

Change the connector to ZIF type
12.02

H19
H_3P3

HOLEA

H20
H_3P3

HOLEA

H24
H_4P4

HOLEA

H23
H_3P3

HOLEA

HOLEA

H28
H_3P3

H29
H_3P3

H30
H_3P3

HOLEA

HOLEA

HOLEA

HOLEA

H31
H_3P3

@

H33
H_3P3

@

1

@

HOLEA
@

@

@

1

H26
H25
H_3P1X2P8 H_3P3

HOLEA

1

H27
H_2P8

HOLEA

1

H22
H_3P1X2P8

<15>

SMBDATA

SMBCLK

R190
2

0_0201_5%
SMBCLK_#
1

SMBDATA

2R210

SMBDATA#
0_0201_5%
1

REV:06 0203

1

@

SMBCLK

Reduce R190 and R210 0Ohm

H32
H_3P3
HOLEA
@

PCB
PX@

1

@

1

@

1

@

1

@

1

1

1

1

@

<15>

UMA@

ZZZ3

ZZZ3

LA-8661P

LA-8662P

DA80000SE00

DA60000SK00

H34
H_2P1N

0.1U_0402_16V4Z
HOLEA

1
2
3
4
5
6

1
2
3
4
5 G1
6 G2

@

@

HOLEA
@

HOLEA
@

12/15:Add NPTH H34
7
8

E-T_6916K-Q06N-00L

FD1

Change the connector to ZIF type
12.02

FD2
@

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FD4
@

FIDUCIAL_C40M80

2011/06/29

Deciphered Date

@

FIDUCIAL_C40M80

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

FD3
@

1

JPWR1
+5VALW
+3VALW_EC
LID_SW#
ON/OFFBTN#
PWR_LED#

1

<34,36> PWR_LED#

2

1

<36> LID_SW#

2

G2
G1
6
5
4
3
2
1
ACES_50578-0060N-001

1

0.1U_0402_16V4Z

C48

@

1

2

Add C47, C48 as EMI request.
12.05

1

H18
H_3P3

HOLEA

1

@

C47

H13
H_2P8

HOLEA

1

+5VALW

@

1

+3VALW_EC

H11
H_3P3

REV:06 0203 Remove R373,Q12,R758,

1

2
1

<36> AOAC_PW_ON#

Q49A

0.1U_0402_16V4Z

2N7002KDW_SOT363-6

2

1

2

1
2

1

H21
H_2P8
HOLEA

<31> AOAC_PW_ON
6

C49

2 0.1U_0402_16V7K

100P_0402_50V8J
R75
100K_0402_5%

+3VS

Add C49 as EMI request.
12.05

+3V_TP

1

100P_0402_50V8J

1

C220

8
7
6
5
4
3
2
1

SMBCLK_#
SMBDATA#

+5VALW

+5VALW

1

JTP1@

TP_CLK
TP_DATA

TP_CLK
TP_DATA

1M_0402_5%
@

Delete Q13
12.08

S

R512

1
0_0603_5%

1

2 10U_0805_25V6K

1

3

BATT+

@

D

2

C349

D7
PESD5V0U2BT
@

Change reset IC to vendor GMT
12.21

2 10U_0805_25V6K

1

1

VIN

@

C117

C350

1

51ON#

KBL_OFF# <36>

+3V_TP

R445
2

1

1
D62

1
2
3

5

3

ON/OFFBTN#

R520
0_0402_5% 1
2
+3VS
N_3_5V_001_R
1
2
R514
20K_0402_5%
1
G677L308A31U_ADFN6_1P5x1P5
C502
0.1U_0402_16V4Z
2
2 ON/OFF#
1
2
CH751H-40PT_SOD323-2
D60
CH751H-40PT_SOD323-2

2 0.1U_0402_25V6

3

C517 1

1
1K_0402_5%

AO3413L_SOT23-3

C68
0.047U_0402_16V7K

5
6

2

D

JP14
1
2
3
4

R80
100K_0402_5%

Q9
S

4

1

+5VALW

Q49B

2N7002KDW_SOT363-6

6
2

<36> WLAN_OFF_LED#

+5VS

WL_WHIT

Q48B

Q48A

Follow thermal (FAN) design guide, pull-high 10K
12.05

2N7002KDW_SOT363-6

WLAN_AMBER

ACES_51503-03241-001

Keyboard backlight Conn

R371
360_0402_5%

2

R367
360_0402_5%

33
34

1

1

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 GND
28 GND
29
30
31
32

2

1

2
2
2
2
2
2
2
2

KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

3

2

1
1
1
1
1
1
1
1

KSO[0..15]

JFAN1

2

FAN_PWR
RPM@ C171
1000P_0402_50V7K

1

+5VS

PWM@
R48 1
0_0603_5%

C243
C242
C245
C244
C248
C246
C249
C250

JKB1 @
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
WL_WHIT
WLAN_AMBER

R463 @
10K_0402_5%

PWM@ C168
0.1U_0402_16V4Z

R132
10K_0402_5%

+5VS

C167
10U_0603_6.3V6M

6
1

2

2

2N7002KDW_SOT363-6

Q42A

EC_ON

EC_ON

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

<36>

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

4

<45>

D6
CHN202UPT_SC70-3

KSI[0..7]

2N7002KDW_SOT363-6

51ON#

3
C269
0.1U_0402_16V7K

<36>

51ON#

1

2

1

<36>

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

3

ON/OFFBTN#

ON/OFF#

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

1

2

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

de
f
hg

10K_0402_5%

C226
C227
C229
C228
C231
C230
C233
C232
C235
C234
C237
C236
C240
C238
C241
C239

1

@
R170

KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

1

2

2

+3VLP

2011/06/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

KB/TP/LED/FAN/Screw/Gsensor
Size Document Number
Custom
Date:

Saturday, March 03, 2012

Rev
0.1

LA-8041P
Sheet

37

of

58

5

4

3

2

1

Notes:
Keep PVDD supply and speaker traces routed on the DGND plane.
Keep away from AGND and other analog signals

DVDD_IO should match
with HDA Bus level(optional for 3.3V signaling or 1.5V signaling)
Place AVDD ,PVDD,and DVDD capacitor close to Codec
+3VS_DVDD
RA3
BLM18BD601SN1D_0603
1
2

<14> HDA_SDOUT_AUDIO

HDA_SDOUT_AUDIO

HDA_SDIN0
2
33_0402_5%
HDA_RST_AUDIO#

<14> HDA_SDIN0
<14> HDA_RST_AUDIO#
C

<36>

EAPD
DH6 1
CH751H-40PT_SOD323-2

EAPD

100_0402_5%
D_MIC_CLK 2
D_MIC_DATA

<32> D_MIC_CLK
<32> D_MIC_DATA

6
5

HDA_SYNC_AUDIO

<14> HDA_SYNC_AUDIO

EAPD_L

2

1

10
1
RA11

SDIN_CODEC

8
11

2
1
DH7
CH751H-40PT_SOD323-2

RA13
LA19
D_MIC_CLK_L1
1
LA20

DVDD

SENSE_A
SENSE_B

CA508 @
33P_0402_50V8J

1

HP0_PORTA_L
HP0_PORTA_R
VREFOUT_A
HDA_BITCLK
HP1_PORTB_L
HP1_PORTB_R

HDA_SDO
HDA_SYNC

PORTC_L
PORTC_R
VREFOUT_C/GPIO4

HDA_SDI
HDA_RST#

PORTE_L
PORTE_R

EAPD_AMP <39>

47
FBMA-L10-160808-301LMT_2P
D_MIC_CLK_L_C
2
2
D_MIC_DATA_C
2
4
FBMA-L10-160808-301LMT_2P
48
MUTE_LED_L
46

PORTF_L
PORTF_R
EAPD
SPK_PORTD_+L
SPK_PORTD_-L

DMIC_CLK/GPIO1
DMIC0/GPIO2

SPK_PORTD_+R
SPK_PORTD_-R

SPDIFOUT0/GPIO3
DMIC1/GPIO0/SPDIFOUT1

MONO_OUT
36
2
+3VS_DVDD

1

+3VS_DVDD

Place C208 close to Codec
1

1

42

RA17
10K_0402_5%

49

2

CA1

2

1

SENSE_B

RA10

2

CA11

PLACE CLOSE TO U1 PIN 14

2 20K_0402_1%
1

2 1000P_0402_50V7K

1

2 1000P_0402_50V7K

+AVDD_CODEC
HP_DET#

2 10K_0402_1%

1

@

D

HP_DET# <35>

+AVDD_CODEC

If Sense_B is un-used, then pull high
Sense_B to AVDD by 10Kohm resistor

28
29
23
31
32

HP_OUT_L
HP_OUT_R

19
20
24

MIC_EXTL
MIC_EXTR
VREFOUT_EXT_MIC

HP_OUT_L <40>
HP_OUT_R <40>

HP Jack

MIC_EXTL <41>
MIC_EXTR <41>

Ext MIC

VREFOUT_EXT_MIC

15
16

C

17
18
40
41

SPKL+
SPKL-

44
43

SPKR+
SPKR-

25
12

SPKL+
SPKL-

<41>
<41>

SPKR+
SPKR-

<41>
<41>

Internal SPKR(front stereo speaker)

MUTE_LED <37>

SUB_OUT <39>
MONO_INR
CA96

MONO_IN
1
0.1U_0402_25V6

2

R368
270_0402_1%

21
22
34
37

2
AVSS1
AVSS2
AVSS3

PAD

1

SENSE_A
SENSE_B

DVSS
PVSS

SENSE_A

26
30
33

1

2

1

1

2

1
QA1B

2

MUTE_LED_L

5
2N7002KDW_SOT363-6

Place C209,C210,CA87,CA89 close to Codec

EAPD_L

10K_0402_5%
RA18

B

1

HDA_RST_AUDIO#

VREFFILT
CAP2
VVREG(+2.5V)

1

92HD91B2X5NLGXYAX8_QFN48_7X7

2

2
B

PCBEEP

CA12
4.7U_0603_6.3V6K
35
CAP-

7
RA14
4.7K_0402_5%

CAP+

2 2.49K_0402_1%

1

PVDD

45
39
13
14

1

RA7

MIC_SENSE <35>

1

HDA_BITCLK_AUDIO

PVDD1
PVDD2

RA9

MIC_SENSE

2

<14> HDA_BITCLK_AUDIO

2

DVDD_IO

2 10K_0402_1%

3

9

Correct CA508 circuitry.
12.05

AVDD1
AVDD2

2

1

4

3

DVDD_CORE

1

RA8

2

Follow EMI request, reserve cap.
11.03

2

27
38

2
1
0_0805_5%

CA10
10U_0603_6.3V6M

UA5

1

RA6

@

CA9
0.1U_0402_25V6

1

CA5
10U_0603_6.3V

2

1
0_0805_5%

CA8
0.1U_0402_25V6

2

1

2

CA16
10U_0603_6.3V6M

2

RA5

CA14
4.7U_0603_6.3V6K
0.1U_0402_25V6
CA15

CA2

1

1

+AVDD_CODEC

CA7
1U_0402_6.3V6K

1

CA4
0.1U_0402_25V6

2

CA3
1U_0402_6.3V6K

0.1U_0402_25V6

+5VS

CA13
4.7U_0603_6.3V6K

1 0_0805_5%

2

D

If Sense_A total length is greater than
6 inches, chagne C12 to 0.1uF

PLACE CLOSE TO U1 PIN 13

+3VS

CA6
0.1U_0402_25V6

RA2

+VDDA_CODEC

RA1
FBMA-L11-201209-221LMA30T_0805
2
1

DVDD_IO

+3VS

1

2

CA18
0.1U_0402_25V6

RA55
10K_0402_5%

1

Follow EMI request, reserve cap.
11.03

CA93@1

2 0.1U_0402_25V6

CA92@1

2 0.1U_0402_25V6

RA53 1

A

+VDDA_CODEC

<14>

HDA_SPKR

SB Beep

HDA_SPKR

S

UA1
2N7002H_SOT23-3

2
G

1

RA54
10K_0402_5%

2

CA99
0.01U_0402_16V7K

1

2
RA16
10K_0402_5%

1

2 0_0805_5%

GND

UA2

W=40Mil

1

2 0.1U_0402_25V6

9/27 LDO TPS793475DBVR for audio power

MONO_IN

2

2

2 0.1U_0402_25V6

CA98 @1

1

2 0.1U_0402_25V6

CA101 @1

1

100K_0402_5%
+5VS

D

3

CA102 @1

RA56

CA97
2

0.1U_0402_25V6

2

GNDA
Security Classification
Issued Date

1
3

VOUT

5

VIN
BYPASS

4

EN

1

2
GND
TPS793475DBVR_SOT23-5

CA100
0.1U_0402_25V6

2

CA20
0.1U_0402_25V6

CA17
0.01U_0402_16V7K

2

2

1

1

+AVDD_CODEC

2

1

CA19
10U_0805_10V6K
A

Change UA2 P/N to SA00005J000 just for HP project.
02.06
Compal Secret Data
2011/06/29

Deciphered Date

2011/06/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Compal Electronics, Inc.
Title

Audio IDT 92HD91
Size Document Number
Custom
Date:

Rev
0.1
Sheet

Friday, March 02, 2012
1

38

of

58

5

4

3

1

+5V_SUBAMP

+5VS

1
RA12
BLM18BD601SN1D_0603
1
2

D

2

2

CA21
10U_0603_6.3V

Add 10U cap as vendor suggestion
01.18
D

UA3

SUB+

2
RA139

1
A1
47K_0402_5%

IN+

2

SUB-

2
RA138

1
C1
47K_0402_5%

IN-

<38>

C2

EAPD_AMP

LA1

1

2 FBM-11-160808-601-T_0603

SUBWOOFER+ <41>

A3

LA2

1

2 FBM-11-160808-601-T_0603

SUBWOOFER- <41>

PVDD
PGND

B3

VDD
EN

GND

A2

TPA2011D1YFFR_DSBGA9

C

2011.10.28
2011.12.19

1

B1

OUT-

C3

CA30
680P_0603_50V7K

2

B2

OUT+

1

CA27 1
0.033U_0603_16V7

<38> SUB_OUT

2

2

CA29 1
0.033U_0603_16V7

CA31
680P_0603_50V7K

Change Sub-woofer Amp to TPA2011D1
Change P/N from SA00004Z700 to SA00005FR00 for HP.

C

+5V_SUBAMP

2

+5V_SUBAMP

1

RA4
47K_0402_5%

6

2

2

1

RA19
10K_0402_5%

RA21
47K_0402_5%

QH9A
2N7002DWH_SOT363-6
1

2

B

6

1

B

RA15
1

2

2
1

Part B is used on USB20 portion
01.18

QH10A
2N7002DWH_SOT363-6

100K_0402_5%
3

SUB+
QH10B
2N7002DWH_SOT363-6

RA20

Add circuitry for de-pop
01.18

2
100K_0402_5%

5
4

1

QH10 must change to BJT before SMT
(Footprint is compatible from BJT& MOTFET)
01.18
BJT P/N: SB00000VH00

SUB-

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/29

Deciphered Date

2011/06/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Audio Woofer Amplifier
Size
B
Date:

Document Number
Friday, March 02, 2012

Rev
0.1
Sheet
1

39

of

58

5

4

3

2

1

Headphone amplifier
HP_5V

LA14

5
4

HP_OUT_L

CA64
1

1U_0402_6.3V6K
2
1
LA12

2
0_0603_5%

1
2
6
7

PCH_SMB_DA1_AMP
PCH_SMB_CK1_AMP

8
20
18

1

1

CA66
1U_0402_6.3V6K

1
CA90
2

1U_0402_6.3V6K

CA65
1U_0402_6.3V6K

0.1U_0402_25V6

21

RIGHTINM
RIGHTINP
LEFTINM
LEFTINP

VDD_12

SCL
VDD_20

11
14

30_0603_1%
2
2

1
1
RA39

GND_3
GND_9
GND_10
GND_13
GND_19

SD#
SDA

12
RA40

HPRIGHT
HPLEFT

CPVSS_15
CPVSS_16

CPP

CPN

3
9
10
13
19

HP_R
HP_L

HP_R
HP_L

<35>
<35>

30_0603_1%

#DB 0930 need apply 30_0603 ohm P/N

15
16
17

GND
HPA00929

1
CA80
2
CA79
1

1U_0402_6.3V6K
2

1

2

2

1

CA95

2
0_0603_5%

CA94

1U_0402_6.3V6K
2
1
LA18

0.1U_0402_25V6

CA57
1

2

D

2

UA6

HP_OUT_R

2

1

FBM-11-160808-601-T_0603

CA54
1U_0402_6.3V6K

<38> HP_OUT_L

RA38

2.2U_0402_6.3V6M

<38> HP_OUT_R

+5VS

HP_5V

10K_0402_1%

D

1

2

C

C

+3VS

HP_5V

2

RH332
2.2K_0402_5%
2N7002DWH_SOT363-6

RH333
2.2K_0402_5%
1

1

2

2

Add level shift 11.06

<15,23,36> EC_SMB_CK2

1

6

PCH_SMB_CK1_AMP

5

QH8A

<15,23,36> EC_SMB_DA2

4

PCH_SMB_DA1_AMP

3

2N7002DWH_SOT363-6
QH8B

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/29

Deciphered Date

2011/06/29

Title

Audio SPK/HP Amplifier

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

Size Document Number
Custom
Date:
2

Wednesday, March 07, 2012

Rev
0.1
Sheet
1

40

of

58

A

B

C

D

E

Front Speaker Connector 1
JSPKR1
SPKR+
SPKRSPKL+
SPKL-

1
2
3
4

1

GND1
GND2

<38> MIC_EXTR

1U_0603_25V6

2

CA55
1

1U_0603_25V6

2

1
CA56

4.7K_0402_5%
1
2
RA57

VREFOUT_EXT_MIC
MIC1_L
MIC1_R

RA58
1
2
4.7K_0402_5%

2

3

2

3

<35>

CA58
1U_0402_6.3V4Z

1

1

<35>

MIC1_R

1

DA2 @
TVNST52302AB0_SOT523-3

DA1 @
TVNST52302AB0_SOT523-3

1

MIC1_L

VREFOUT_EXT_MIC

2

RA43

RA42

<38> MIC_EXTL

E&T_3806-F04N-02R
CONN@

CA47

2

1

CA46

5
6

Ext. Mic

1
2
3
4

2

CA45
RA41

1

2

2

CA44

1
RA37

1

3.3_0402_5%

3.3_0402_5%

3.3_0402_5%

3.3_0402_5%

2

2

2200P_0402_50V7K

1

2200P_0402_50V7K

2

2200P_0402_50V7K

2200P_0402_50V7K

1

1

SPKR+
SPKRSPKL+
SPKL-

2

1

<38>
<38>
<38>
<38>

2

2

Need place rear Audio Codec (UA5)
JSW1 @

1
2

<39> SUBWOOFER+
<39> SUBWOOFER-

3
4

1
2
G1
G2
E&T_3806K-F02N-03R

Change 4pins to 2 pins
12.08

3

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/04/07

2012/10/21

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Audio SPK Conn/Jack/MIC

Size Document Number
Custom
Date:

Rev
0.1

PAV10

Friday, March 02, 2012

Sheet
E

41

of

58

5

4

3

+3VS

2

R450

+3VALW

2

+3VS

C124

R171

1

2 0_0402_5%

+3V_GSEN

G-sensor Power Rail Change to +3VALW
(Note: Need to add D13 to prevent power leakage)
01.05
+3V_GSEN

2

2

1

G-sensor Address: 0x50/0x52
11.01

D13

1

2

ACCEL_INT# <17>

CH751H-40PT_SOD323-2

U25

1

0.1U_0402_16V4Z

XTALO
XTALI

14
13

TPM_XTALO
TPM_XTALI
PAD
T44
@

1
EC_SMB_CK1_G_SEN
EC_SMB_DA1_G_SEN

@
4.7K_0402_5%

2

1
10K_0402_5%

2
3

R167
0_0402_5%

INT2
INT1
VDD

SCL/SPC
SDA/SDI/SDO
SDO/SA0
CS

GND
GND
RES
RES
RES
RES

NC
NC

9
11
14

ACCEL_INT#_D

5
12
10
13
15
16

C218
0.1U_0402_16V7K

HP3DC2

2

1

1

2

2

C219
10U_0603_6.3V6M

T45

1

@
PAD

1
3
12

R166

Vdd_IO

2

9635@
4.7K_0402_5%

2
6

+3V_GSEN

R504

2

1

R502

4
6
7
8

1

LPC_PD#_TPM
BADD

2

28
9
8

1

LPCPD#
TESTB1/BADD
TEST1

+3V_GSEN

R168
0_0402_5%

S IC SLB9635TT1.2 TSSOP 28P TPM

@

2

0_0402_5%

2 0_0402_5%

R503
4.7K_0402_5%
9635@

TPM
SLB 9635 TT 1.1
LCLK
LFRAME#
GPIO2
LRESET#
GPIO
SERIRQ
CLKRUN#
PP
NC
NC
NC

21
22
16
27
15
7

1

CLK_PCI_LPC
LPC_FRAME#
PLT_RST#
SERIRQ
PM_CLKRUN#
1
2
R449
@ 4.7K_0402_5%

LAD0
LAD1
LAD2
LAD3

1

2

+3VS

R507
0_0402_5%
9635@

26
23
20
17

2

GND
GND
GND
GND

CLK_PCI_LPC
LPC_FRAME#
PLT_RST#
SERIRQ

1

<17,36>
<14,31,36>
<6,17,22,31,34,36>
<14,36>
<16> PM_CLKRUN#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

R510
0_0402_5%
9635@

1

4
11
18
25

<14,31,36>
<14,31,36>
<14,31,36>
<14,31,36>

@

D

VDD
VDD
VDD

U69

R509
0_0402_5%
9656@

5

2
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

R169

1

1

+3VS

VSB

2

D

C342

24
19
10

1

1

+3VALW

+3VS

R508 9656@
0_0402_5%
0.1U_0402_16V4Z
1
1
C343
C344

2

+3VS

R511 2

9656@
1

0_0402_5%

NC

2

OSC

C

3
2

RH228
2.2K_0402_5%

2
SUS_STAT# <16>

12.5PF Q13MC1462001700
TPM_XTALO
C347 132.768K
2
10M_0402_5% 9635@
18P_0402_50V8J

2N7002DWH_SOT363-6

RH280
2.2K_0402_5%

1

0_0402_5% SUS_STAT#

NC

1

1

9635@

OSC

6

<36,46,47> EC_SMB_CK1

BADD

1

EC_SMB_CK1_G_SEN

QH5A

5

PLT_RST#

1

@
R505 2

4

2

2

R451
9635@

+3V_GSEN

2

R506
4.7K_0402_5%
9635@
LPC_PD#_TPM

Y8

1

1

C

+3V_GSEN

Change gate power rail to +3V_GSEN
The same as EC
01.19

9635@ 18P_0402_50V8J
C346 1
2

TPM_XTALI

3

<36,46,47> EC_SMB_DA1

4

EC_SMB_DA1_G_SEN

2N7002DWH_SOT363-6
QH5B

B

B

A

A

Compal Secret Data

Security Classification
2006/09/25

Issued Date

Deciphered Date

2006/09/25

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
TCG/BIOS ROM/PS2/LED/SW

Size

Document Number

Rev
0.1

LA3262P_DIS__M64
Date:

Sheet

Wednesday, March 07, 2012
1

42

of

58

C

D

2
100P_0402_50V8J

10.21 Change to PAK type

3

1

C179
0.1U_0603_25V7K

SUSP

Q14A
DMN66D0LDW-7_SOT363-6

+VSB

2

1

3

2

1
3

3

1
2

1

U14
2N7002H_SOT23-3

R178
10K_0402_5%

2

PCH_PWR_EN#

Q43A
DMN66D0LDW-7_SOT363-6

5
+0.75VS
+1.8VS

+VCCP

+1.5V

1

Q43B
DMN66D0LDW-7_SOT363-6

4

PCH_PWR_EN#

S

2
G

<10,36,49,50,51> SUSP#

R179
470_0603_5%

1 200K_0402_5% 3V_GATE

C180
0.1U_0603_25V7K

1

D

2

1

1

1
1

10mil
R181 2

S

2
2

2

4

Q14B
DMN66D0LDW-7_SOT363-6

1

1

20mil

2

5

SUSP

SUSP

2

2

U13
2N7002H_SOT23-3

2

5VS_GATE

<6,52>
D

2
G

R177
100K_0402_5%

4

C176
10U_0603_6.3V6M

40mil

SI7326DN-T1-E3_PAK1212-8
U15
1
2
5
3

SYSON

1

R176
470_0603_5%

SYSON#

SYSON#
<36,51,52> SYSON

R175
100K_0402_5%

6

2
2

1

4

1

+3V_PCH

C178
1U_0603_25V6

SUSP

2

Delete J1
01.12

C177
10U_0603_6.3V6M

10mil

2
1
R180
20K_0402_5%

+VSB

1

C173
1U_0603_25V6

2

+3VALW

+5VS
C172
10U_0603_6.3V6M

20mil

1

C175
10U_0603_6.3V6M

2

C174
10U_0603_6.3V6M

1

SI7326DN-T1-E3_PAK1212-8
U12
1
2
5
3

6

1

R174
100K_0402_5%

Short J1 for PCH VCCSUS3.3

SI Change to PAK type

1

7/12

+5VALW

+3VALW TO +3VALW(PCH AUX Power)

+5VALW TO +5VS
+5VALW

+5VALW

2

C267 @
SYSON
1

E

1

B

2

A

2

2

2

R182
22_0603_5%

R183
470_0603_5%

R184
470_0603_5%

@ R185
470_0603_5%

6 1

6 1

6

3 1

2

6/24 U16 and U17 to Q16 change to Dule mos package

@

Q15A
DMN66D0LDW-7_SOT363-6

SUSP

2

Q15B
DMN66D0LDW-7_SOT363-6

SUSP

2

Q17A
DMN66D0LDW-7_SOT363-6

1

5

1

SUSP

4

1

2

SYSON#

Q18A
DMN66D0LDW-7_SOT363-6

+3VALW TO +3VS
+3VALW

2
C191
0.1U_0603_25V7K

2

+5VALW

SUSP

Q20A
DMN66D0LDW-7_SOT363-6

2

2

R189
100K_0402_5%
PCH_PWR_EN#

3

<20> PCH_PWR_EN#

1

1

4

Q20B
DMN66D0LDW-7_SOT363-6

3

6

3VS_GATE

5

R186
470_0603_5%

1

SUSP

2

1

4

10mil

3

+VSB

R188
47K_0402_5%
2
1

2

1

C184
1U_0603_25V6

20mil

2

1

C183
10U_0603_6.3V6M

3

1

C182
10U_0603_6.3V6M

2

C181
10U_0603_6.3V6M

1

+3VS
SI7326DN-T1-E3_PAK1212-8
U18
1
2
5
3

Q17B

5

<36> PCH_PWR_EN

1

6/24 Q20 and Q21 to Q20 change to Dule mos package

4

DMN66D0LDW-7_SOT363-6

2

R192
100K_0402_5%

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/29

2011/06/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

DC Interface
Size Document Number
Custom
Date:

Rev
0.1

LA-8661P
Sheet

Friday, March 02, 2012
E

43

of

58

5

4

3

2

1

D

D

C

C

B

B

2

A

A

Compal Secret Data

Security Classification
Issued Date

2011/06/29

2011/06/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
Strap pin table

Size Document Number
Custom
Date:

Rev
0.1

LA-8041P
Sheet

Friday, March 02, 2012
1

44

of

58

5

4

3

2

1

D

D

PL1
HCB1608KF-121T30_0603
1
2

ADPIN

1
2

1

3

2
C

KBC output
AC_LED#

2

3

ACES_59012-06001-002

PL2
HCB1608KF-121T30_0603
1
2

PC4
1000P_0402_50V7K

ADPIN

2

ACIN_LED

6

PC3
100P_0402_50V8J

4

PC52
0.1U_0402_25V6
2
1

6

PC51
0.1U_0402_25V6
2
1

5

1

4

2

5

ADPIN

2

2

3

PC2
1000P_0402_50V7K
2
1

3

PC1
100P_0402_50V8J

PJP1 @
1
1
Charge_LED

VIN

PL4
HCB1608KF-121T30_0603
1
2

PD1
PJSOT24CW_SOT323

for EMI solution

1

1

PD4
PJSOT24CW_SOT323

Input to Battery

BAT_CHG_LED ACIN_LED Charge_LED

LED Status

0

0

1

0

White LED light

0

1

0

1

Amber LED light

1

0

0

0

X (don’t care)

1

1

0

0

X (don’t care)

C

ESD diode : SCA00001G00

+3VLP

+3VALW

2

2

AC_LED#

2

1

32.8
TP0610K-T1-GE3 1P SOT23-3
PQ5

5

2

B

1

3
B

Y

1

AC_LED#

PR23 @
0_0402_5%

1

PU3
74LVC1G86GW_SOT353-5

2
2

A

BAT_CHG_LED

PR24
0_0402_5%
2
1

5
P
4

AC_LED#

PR30 @
0_0402_5%

PR32
0_0402_5%
2
1

Charge_LED

@

2

1

2

1

PC5
0.22U_0603_25V7K

2

A

G

51ON#

PU2
74LVC1G02GW_SOT353-5

1

B

O

@

PR31
0_0402_5%
2
1

3

37

PR5
22K_0402_1%
1
2

2

1

3
PR4
100K_0402_5%

BATT+

PD3
LL4148_LL34-2
2
1

4

P

VS
PQ1
TP0610K-T1-GE3 1P SOT23-3

G

B

PR25
249_0402_1%
ACIN_LED 1
2

1
PR28
10K_0402_5%
2
1
PR29
10K_0402_5%

36

1
PR26
10K_0402_5%
2
1
PR27
10K_0402_5%

3

+3VALW

BAT_CHG_LED 36

A

A

Compal Secret Data

Security Classification
Issued Date

2011/10/03

2014/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR- DCIN / Vin Detector

Size Document Number
Custom

Rev
0.1

LA-8551P

Date:

Sheet

Saturday, March 03, 2012
1

45

of

59

5

4

3

2

1

For KB930 --> Keep PU1 circuit
(Vth = 0.825V)

D

BATT++

PC7
1000P_0402_50V7K

PC8
0.01U_0402_25V7K

Rset = 3 * Rtmh
Rhyst = (Rset* Rtml) / (3*Rtml - Rset)
Rtmh at 90C = 7.8K, Rtml at 56C = 26.1K
Rset = 3 * 7.8K = 23.4K ==> 23.7K
Rhyst = (23.4K * 26.1K) / (3 * 26.1K - 23.4K) = 11.12K ==> 11.3K

2
PR10
100_0402_5%
1
2

EC_SMB_DA1 36,42,47

PR11
100_0402_5%
1
2

EC_SMB_CK1 36,42,47

PR8
6.49K_0402_1%
1
2

1

+3VLP
+3VALW

Place clsoe to EC pin
PC10
.1U_0402_16V7K

PR12
23.7K_0402_1%

2

PR9
1K_0402_5%
1
2

2

BATT_TEMPA 36

PR13
11.3K_0402_1%

PU1

MAINPWON

MAINPWON

3

+3VS

4

OT1 TMSNS2
OT2 RHYST2

6
5

1

G718TM1U_SOT23-8

B

1

PR22
0_0402_5%
2

D

S

ADP_I 36,47

PR17
10K_0402_1%

1

B

1

+VSB

D

2
G

1
2

1

1

3

S

PC12 @
0.1U_0603_25V7K

PQ3
SSM3K7002FU_SC70-3

2
PR18 @
0_0402_5%

H_PROCHOT#_EC

36

Active point = 71.52W
Recovery point = 62.62W

PQ4
SSM3K7002FU_SC70-3

2
G

2

PC13 @
.1U_0402_16V7K

1

SPOK

1

16,48

3

1

PR20
100K_0402_1%

2

PR15
5.9K_0402_1%

2

PR21
22K_0402_1%
1
2

2
1
PR19
100K_0402_1%

2

+5VALW

1

1

2

6,36 H_PROCHOT#
3

2

PR14
26.1K_0402_1%

BIT3161
SA00004KC00

PR16
100K_0402_1%

PQ2
TP0610K-T1-GE3 1P SOT23-3

PH1
100K_0402_1%_NCP15WF104F03RC

7

2

48

GND RHYST1

8

2

2

VCC TMSNS1

1

1

B+

C

1

1

12
11
10
9
8
7
6
5
4
3
2
1

PH1 under CPU botten side :
CPU thermal protection at 90 +-3 degree C
Recovery at 56 +-3 degree C

BATT+

2

C

BATT++

2

12
11
10
9
8
7
6
5
4
3
2
1

BATT+

PL3
SMB3025500YA_2P
2
1

1

ACES_88107-12001-H01-CP
14
PJPB1 @
GND
13
GND

1

Part Number = SP02000I400

D

A

A

Compal Secret Data

Security Classification
Issued Date

2011/10/03

2014/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR- BATTERY CONN

Size Document Number
Custom

Rev
0.1

LA-8551P

Date:

Sheet

Saturday, March 03, 2012
1

46

of

59

A

B

C

D

1

for reverse input protection
D
PQ101
SSM3K7002FU_SC70-3
3

2
G
S

1

1

B+

BATT+

ILIM

4

Min.
L-->H 17.45V
H-->L 16.89V

Typ.
17.92V
17.52V

1
2

PC122
0.01U_0402_50V7K

1
2

PC121
2200P_0402_50V7K

1
2

PC119
10U_0805_25V6K

1

PC118
10U_0805_25V6K

2

1

3

1

PC124
0.01U_0402_25V7K

2

PR120
100K_0402_1%

1
2

1
2
PR119
365K +-1% 0402

PR125

14 13 12 11 10

9

8

7

6

5

4

EC_SMB_CK1 36,42,46

0x3F

Icp

-

-

0

1

1

0

0

1

-

-

-

3.2A

0x14

Icharge

-

-

0

1

0

0

1

1

1

-

-

2.496A

0x15

Vcharge

1

0

0

0

0

0

1

0

0

0

1

16.8V

EC_SMB_DA1 36,42,46

2

1

ADP_I

36,46

PC126
100P 25V K NPO 0402

Max.
18.42V
18.16V

4

ILIM and external DPM
3.54A

Compal Secret Data

Security Classification
Issued Date

2011/10/03

Deciphered Date

2014/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

1 CSON1

for charger demage solution
SCS00005800

+3VALW

1

1

PR126
42.2K +-1% 0402

2

1

PC125
.047U 16V K X7R 0402

2

Vin Dectector

@

2

MDV1527URH
SB00000V100

10

SCL

SDA

9

8

2
PR123
@

1

PR122
@

2 CSON1
PR115
PC123
0_0603_5%
0.1U_0603_25V7K
BQ24738_BATDRV

RB551V-30_SOD323-2

SRN 1

11

2

0_0402_5%

1
2

PR124
270K +-1% 0402

2

0_0402_5%

7

VIN

for EMI solution

12

PR114
0_0603_5%
2 CSOP1

PD103

1

IOUT

ACDET
6

2 PR118 @
0_0402_5%

SRN
BATDRV

0_0402_5%

1
2

PC131
0.1U_0402_25V6

1
2

PC130
0.1U_0402_25V6

ACOK

SRP 1

2

ACDRV

5

13

3
PC117
0.1U_0402_25V6

4

14

SRP

2

BQ24738_ACDRV

GND

3
2
1

CMSRC

1

ACP

3

2

1

4

2

2

1 CSOP1

DL_CHG

15

2

PC120
680P_0402_50V7K

LODRV

2

PQ106
AON7406L_DFN8-5

PR112
0.01_1206_1%
1
4

PC116
0.1U_0402_25V6

1

5

16

ACN

PL102
10UH_FDSD0630-H-100M-P3_3.8A_20%
BQ24738_LX
1
2 CHG
PR113
4.7_1206_5%

PC115
1
2

REGN

17

18

BTST

PHASE

HIDRV

19

20
VCC

PAD

BQ24738_CMSRC

PR116
10K_0402_1%
1
2

1

1

4

3
2
1

2

2

PR111
DH_CHG 1
2
PD102
2.2_0402_1%
RB751V-40_SOD323-2

BQ24725ARGRR QFN 20P CHARGER

ACIN

2

5
2

PQ105
AON7408L_DFN8-5
1

PR110
2.2_0402_1%

PC114
1U_0603_25V6K

1

16,23,36

PR105
0_0402_5%

1

4

1
2

PC108
2200P_0402_50V7K
2
1

PC107
0.1U_0402_25V6

PC106
10U_0805_25V6K
2
1

2

2

BQ24738_ACN

1

21

3

@

2

PR106
4.12K_0603_1%

1U_0603_25V6K

+3VALW

MDV1526URH
SB00000TZ00

2

3

PC105
10U_0805_25V6K
2
1

BQ24738_BATDRV 1

PC113 0.047U_0402_25V7K
1

PU101

B+

1
2
3

5

PD101
BAT54CW_SOT323-3

BQ24738_BST
1

2
1
2

1
2

PC111
0.1U_0402_25V6

PC109
0.1U_0402_25V6
1
2

VIN

PR109
10_1206_1%
2
1

2

1

4

MDV1526URH
SB00000TZ00

PC104
10U_0805_25V6K
2
1

@

DH_CHG

3

PQ104
AON7702L_DFN8-5

2

2

PL101
1.2UH +-30% 1231AS-H-1R2N=P3 2.9A
1
2

1

4

1

5

1

BQ24738_ACP

2

1
2
3

PR108
4.12K_0603_1%

1
2

1

@

2

1
2

PR104
0_0402_5%

1
2
3

5

for EMI solution
PR103
0.02_1206_1%

PC110
0.01U_0402_50V7K

P2
PQ103
AON7702L_DFN8-5

BQ24738_LX

P1

PC102
0.1U_0402_25V6

PQ102
TPCA8057-H_PPAK56-8-5

4

PC101
2200P_0402_50V7K
2
1

VIN

2

PR102
3M_0402_5%

PC103
10U_0805_25V6K

1

PC112
0.1U_0402_25V6

2

PR101
1M_0402_5%

PR107
4.12K_0603_1%

1

B

C

Title

Compal Electronics, Inc.
PWR- CHARGER

Size

Document Number

Rev
0.1

LA-8551P
Date:

Saturday, March 03, 2012
D

Sheet

47

of

59

C

D

PR321
0_0201_1%
1
2

@

19

LG_5V

5

2.2_0402_5%

PL303
2.2UH_MMD-06CZ-2R2M-V1_8A_20%
1
2

1

PQ304

4
MDU1512RH_POWERDFN56-8-5

1

2

VL
PC317
4.7U_0805_10V6K

+5VALWP
1
+

2

2

1
2

PC315
1U_0603_10V6K

1
2

B++

1SNUB_5V 2

NC

RT8205LZQW(2) WQFN 24P PWM

PC313
150U_D2_6.3VY_R15M

LX_5V

SH00000F600

PR310
4.7_1206_5%

UG_5V

20

2

2.2UH

PC316
680P_0603_50V7K

21

PR308

3
2
1

BST_5V 1

PC311
0.22U_0603_16V7K
2BST1_5V1
2

5

2

1
ENTRIP1

22

AON7518
SB00000U300
PQ302
AON7518 1N DFN

4

23

18

PR312 @
0_0402_5%
1
2

PC318
0.1U_0603_25V7K

ENTRIP2

3

3

LGATE1

2
ENTRIP1

REF

LGATE2
VREG5

PHASE1

PR311
499K_0402_1%
1
2

AON7406L_DFN8-5

6

FB1

FB_3V

4

5

TONSEL

FB2

6

UGATE1

PHASE2

VIN

12

UGATE2

SPOK

24

3
2
1

MAINPWON

LG_3V

BOOT1

17

4

11

PGOOD

BOOT2

13

B+

LX_3V

VREG3

EN

1
2
3
5

PD302
RLZ5.1B_LL34
1
2

PR313
200K_0402_1%

2

2

PQ303

1
2
3

1

+3.3VALWP
TDC=3.5A
Peak Current=5A
OCP current=6A
Rtrip=105K
F=375KHz

1SNUB_3V2

+ PC312
150U_B2_6.3VM_R35M

PC314
680P_0603_50V7K

1

PR309
4.7_1206_5%

PL302
3.3UH +-20% PCMB053T-3R3MS 5A
1
2

+3VALWP

16,46
VO1

16

PC310
PR307
1
2BST1_3V 1
2BST_3V 9
2.2_0402_5%
UG_3V
0.22U_0603_16V7K
10

3.3uH SH00000QQ00

B++

PR306
62K_0402_1%
1
2

VO2

GND

8

1

2

P PAD

SKIPSEL

7

4

15

25

14

2

PU301

ENTRIP2

1
5
PQ301
AON7408L_DFN8-5

PC309
10U_0805_6.3V6M

PR305
105K_0402_1%
1
2

PC308
4.7U_0805_25V6-K

PC307
2200P_0402_50V7K
2
1

1
2

ENTRIP2

+3VLP

PL301
HCB2012KF-121T50_0805
1
2

ENTRIP1

PR304
20K_0402_1%
1
2

FB_5V

PR303
20K_0402_1%
1
2

B++

PC301
0.1U_0402_25V6
2
1

PR302
30.9K_0402_1%
1
2

PC306
10U_0805_25V6K
2
1

PR301
13.7K_0402_1%
1
2

B+

1

PC305
4.7U_0805_25V6-K
2
1

+3VLP

1

1

PR320
0_0201_1%
2

2

1

PC302
1U_0603_16V6K

2VREF_8205

E

PC304
2200P_0402_50V7K
2
1

B

PC303
0.1U_0402_25V6
2
1

A

2VREF_8205

3

3

PQ305A
SSM6N7002FU-2N_SOT363-6

N_3_5V_001

2

PQ305

SB00000PC00

PQ305B
SSM6N7002FU-2N_SOT363-6

5

PJP303

4

1

2

2

1

1

@ JUMP_43X118

+5VALWP DIS
TDC=8.54A
Ipeak=12.2A
Rtrip=62K, OCP=14.64A
F=300KHz
Total Capacitor 1440uF,
ESR 3.07mohm

PJP304

35 USB_IN_STATUS#
37 KBC_HANGUP_RESET#

1

2

PR314
100K_0402_5%

PR315 @ 0_0402_5%
1
2

VL

+5VALWP

2

2

1

1

+5VALW

@ JUMP_43X118

PJP301

+3VALWP
MAINPWON

PR316 @
1

2

0_0402_5%
2

2

1

+3VALW

1

@ JUMP_43X118

1

46

MAINPWON

PJP302
PD301
PR317
1M_0402_1%
LL4148_LL34-2
2
1 1
2

VS

+3VLP

2

2

1

+3VL

1

@ JUMP_43X39

4

3

1

PC319
4.7U_0603_6.3V6K

PR319
316K_0402_1%
2
1

2

4

2
2
1
PR318
402K_0402_1%

VIN

PQ306
LTC015EUBFS8TL NPN UMT3F

Compal Secret Data

Security Classification
2011/10/03

Issued Date

2014/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Compal Electronics, Inc.
PWR- 3VALWP/5VALWP

Size Document Number
Custom
Date:

Rev
0.1

LA-8551P

Saturday, March 03, 2012

Sheet
E

48

of

59

B

C

2

A

PC602
680P_0402_50V7K

1

2

SNUB_1.8VSP

1

1

D

PR602
4.7_0402_1%

SH00000MW00

1

PL602
1UH_SIG4018-1R0_3A_20%
1
2

2

1
2

2

+1.8VSP

2

1

+1.8VS

1

@ JUMP_43X39

+1.8VS
TDC=2.63A
Peak Current=3.762A

PC605
22U_0805_6.3V6M

1

2

1

2
1

NC

NC
PU601
SY8033BDBC_DFN10_3X3

PR605
10K_0402_1%

PC606 @
0.1U_0402_10V7K

1.8VSP_FB

PC604
22U_0805_6.3V6M

6

FB
EN

2

SVIN

PC603
22P_0402_50V8J

1

3

LX

PJP601

+1.8VSP
PR603
20K_0402_1%

4
PG

1.8VSP_LX

1

1
2

1
2

5

2

LX

PVIN

TP

8

PVIN

7

9

EN_1.8VSP

@

2

10

11

1
PR601
0_0402_5%
SUSP# 1
2

PC601
22U_0805_6.3V6M

PR604
47K_0402_5%

10,36,43,50,51 SUSP#

1.8VSP_VIN

2

+5VALW

PL601
HCB1608KF-121T30_0603
1
2

2

3

3

4

4

Compal Secret Data

Security Classification
Issued Date

2011/10/03

Deciphered Date

2014/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Title

Compal Electronics, Inc.
PWR- 1.8VS

Size

Document Number

Rev
0.1

LA-8551P
Date:

Saturday, March 03, 2012

Sheet
D

49

of

59

A

B

C

D

1

1

PL1001

2

1

1
PC1002
10U_0805_25V6K

1
2

PC1003
2200P_0402_50V7K

1
2

5

PQ1001

PC1004
0.1U_0402_25V6

+1.5V_PCIE_B+

2

B+

HCB2012KF-121T50_0805

4
PR1005
PC1005
2.2_0402_5% 0.22U_0402_16V7K
1
2
1
2
3
2
1

AON7408L_DFN8-5

PU1001

2

EN_1.5V_PCIE

3

FB_1.5V_PCIE

4

RF_1.5V_PCIE

5

TRIP
EN
VFB
RF

DRVH
SW
V5IN
DRVL

10

BST_1.5V_PCIE

9

UG_1.5V_PCIE

8

SW_1.5V_PCIE

7

+1.5V_PCIE_5V

6

LG_1.5V_PCIE

PL1002
1UH_KJ0730-1R0M_11A_20%
1
2

+5VALW

2

2

4

1

AON7406L_DFN8-5

3
2
1

1

PC1007
1U_0603_6.3V6M

+ PC1009
150U_B2_6.3VM_R35M
PR1008
4.7_1206_5%

11
2

TP

TPS51212DSCR_SON10_3X3

+1.5V_PCIEP
1

PQ1002

1

10,36,43,49,51 SUSP#

2
PR1001 174K_0402_1%

VBST

1

1

PR1002
0_0402_5%
1
2

PGOOD

5

1
TRIP_1.5V_PCIE

PR1003
470K_0402_1%

2

PC1008

2

680P_0603_50V7K

2

2

PC1006
.1U_0402_16V7K

1

2

PJP1001

+1.5V_PCIEP

2

2

1

1

+1.5V_PCIE

JUMP_43X118

DIS
+1.5V_PCIE
TDC=6A
Peak Current=8A

1

PR1006
115K_0402_1%
1
2

UMA
+1.5V_PCIE
TDC=0.46A
Peak Current=0.66A

PR1007
100K_0402_1%
3

2

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/10/03

Deciphered Date

2014/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Title

PWR- VGA_VDDC
Size
C
Date:

Document Number

Rev
0.1

LA-8551P
Saturday, March 03, 2012
D

Sheet

50

of

59

5

4

3

2

1

D

D

PL501
HCB2012KF-121T50_0805
1
2

1
2

PC512
0.1U_0402_25V6

2

1

PC511
0.1U_0402_25V6

2

1

PC501
4.7U_0805_25V6-K

1
2

PC504
4.7U_0805_25V6-K

1
2

PC503
2200P_0402_50V7K

1
2

B+

DRVL

6

3

1

4
D1

D1

D1

S2

S2

+1.05VSP_5V

+5VALW

LG_+1.05VSP

PL502
1UH_KJ0730-1R0M_11A_20%
1
2

11
TP
TPS51212DSCR_SON10_3X3

2

1
2
1

2

VSS_SENSE_VCCIO

PC510
680P_0603_50V7K

9

PR508
10_0402_5%

2

C

+ PC506
220U_B2_2.5VM_R15M

PR505
4.7_1206_5%
PC507
1U_0603_6.3V6M

1

1

PR507
470K_0402_1%

2

PC508 @
.1U_0402_16V7K

+VCCP
1

1

RF

7

D1

PR509
5.11K_0402_1%
2
1

PC509
0.1U_0402_25V6

V5IN

D2/S1

1

VFB

SW_+1.05VSP

5

SW

UG_+1.05VSP

8

2

5

EN

9

2

PR506 @
0_0402_5%
1
2

36,43,52 SYSON

FDMS3668S
SB00000U900
10

1

RF_+1.05VSP

DRVH

6

4

VBST

TRIP

S2

FB_+1.05VSP

PGOOD

G2

3

9

7

2

EN_+1.05VSP

BST_+1.05VSP

2

SUSP#

TRIP_+1.05VSP

10

8

PR504
0_0402_5%
1
2

C

10,36,43,49,50

2 PR503
54.9K_0402_1%

PQ501
AON6920_DFN5X6A-8-10~D

PU501

1

53 VTTPWRGOOD

1

PC505
0.22U_0603_16V7K
1
2

G1

PR502
2.2_0603_5%
1
2

2

PR501
10K_0402_5%

2

1

+3VS

PC502
0.1U_0402_25V6

+V1.05SP_B+

VCCIO_SENSE

9

2

PR510
100_0402_5%
1
2

SANYO
SGA00004I00

B

B

PR511
10K_0402_1%

1

+VCCP
TDC=9.85A
Peak Current=14.07A
OCP current=16.88A
Rtrip = 54.9K

A

A

Compal Secret Data

Security Classification
Issued Date

2011/10/03

Deciphered Date

2014/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR- VCCP

Size
Document Number
Custom
Date:

Rev
0.1

LA-8551P

Saturday, March 03, 2012

Sheet
1

51

of

59

5

4

3

2

1

DDR3L_EN
D

1.5VP

L

DDR3

1.5V

H

DDR3L

1.35V

D

PU401

PC408
22U_0805_6.3VAM

1
@

18

2

DDR3L_EN
PR407
10K_0402_5%

1

1

2

1

3

PQ401
SSM3K7002FU_SC70-3

PR408
100K_0402_1%

C

PR406
5.1K_0402_1%
1
2
PC411
.1U_0402_16V7K

2
G
S

2

PC407
22U_0805_6.3VAM
2
1

2
PR405
10K_0402_1%
2

2

2
D

+3VS

1

1

PC402
680P_0402_50V7K

SNUB_+1.5VP

C

1

8

PR403
750K_0402_5%

FB

PC409 @
SY8809DFC_DFN8_2X2
0.1U_0402_10V7K

1

EN

+1.5VP

7

1

PG

LX_1.5V

6

2

IN

PL402
1UH_KJ0730-1R0M_11A_20%
1
2

5

PC410
22P_0402_50V8J

1

LX

2

1

1

EN_1.5V

2

PR401
0_0402_5%

2

1
2

1

36,43,51 SYSON
PC404
22U_0805_6.3VAM

GND

LX

PR404
150K_0402_1%
1
2

2
PC403
22U_0805_6.3VAM

1
2

+3VALW

PL403
HCB2012KF-121T50_0805
1
2

1.5V_IN
PC401
2200P_0402_50V7K

+5VALW

GND

3

PR402
4.7_0402_1%
2
1

4
@ PL401
HCB2012KF-121T50_0805
1
2

PJP451

1

PJP401

1

+0.75VS

+1.5VP

2

1

1

+1.5V

@ JUMP_43X118

1

APL5336 HF
SA00002XR10

2

VIN

VCNTL

GND

NC

VREF

NC

VOUT

NC

6

+3VALW

5

2

3
PR452
1K_0402_1%

8
2

4

7

1

1

1

2
PC452
4.7U_0805_6.3V6K

PC453
1U_0603_10V6K

+0.75VSP
TDC=1.4A
Peak Current=2A

2

9
TP
APL5336KAI-TRL SOP

VREF_APL5336

A

1

1

1

2

PC455
10U_0805_6.3V6M

A

Compal Secret Data

Security Classification
Issued Date

2011/10/03

Deciphered Date

2014/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

+1.5V
Ipeak=8A
Imax=6A
Total Capacitor 1050uF,
ESR 4.43mohm
HW side:
C106 330uF 17m
C218 390uF 10m
VGA@ CV122 390uF 10m
@ C189 330uF 15m

+0.75VSP
2

S

.1U_0402_16V7K

2

0.1U_0402_10V7K

PR453
1K_0402_1%

2

1
0.75VS_N_002 2
G
PC451 @

3

SUSP

1

6,43

D

PQ451
SSM3K7002FU_SC70-3

PC454
PR451
0_0402_5%
2
1

2

PU451

1

B

PC406
22U_0805_6.3VAM

+1.5V

2

@ JUMP_43X39

PC405
22U_0805_6.3VAM
2
1

2

+0.75VSP

B

4

3

2

Title

Compal Electronics, Inc.
PWR- 1.5VP/0.75VSP

Size
Document Number
Custom
Date:

Rev
0.1

LA-8551P

Saturday, March 03, 2012

Sheet
1

52

of

59

4

3

2

1

2

5

1

PC652
680P_0402_50V7K

SNUB_+VCCSA

The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.

VOUT
VID1

PG

PR651
1K_0402_5%
1
2
C

EN
VID0

4
5

+3VS

+VCCSA_EN

1

2

PR654
0_0402_5%

6

SY8037CDCC_DFN12_3X3

+VCCSA

@

51

PC657
22U_0805_6.3V6M
1
2

FB

SA_PGOOD 36

PR653
100K_0402_5%
2
1

3

PC656
22U_0805_6.3V6M
1
2

7

2

PC655
22U_0805_6.3V6M
1
2

8

LX

1

9

LX

SVIN

2

1

LX

PVIN

+VCCSA_PHASE

PC661
0.1U_0402_10V7K

+VCCSAP_FB
2

PVIN

13

1
2

PC660
22U_0805_6.3VAM

1
2

PC659
22U_0805_6.3VAM

1
2

PC658
0.1U_0603_25V7K

1

PC651
2200P_0402_50V7K

2

10

1

PR655
1K_0402_5%
1
2

11
PC653
68P_0402_50V8J

GND

+5VALW

12

4x4
PL652
1UH_PCMB042T-1R0MS_4.5A_20%
1
2

PU651
+VCCSA_PWR_SRC

PC654
22U_0805_6.3V6M
1
2

PU651 SY8037DDCC SA00005O000
PL651
HCB1608KF-121T30_0603
1
2

D

PR652
4.7_0402_1%
1
2

D

+VCCSA
Itdc=3A
Imax=4A

PR656
100_0402_5%
2
1

VTTPWRGOOD

PR657 @ 0_0402_5%
1
2

VCCSA_VID0

10

VCCSA_VID1

10

VCCSA_SENSE 10

C

B

B

A

A

Compal Secret Data

Security Classification
Issued Date

2011/10/03

Deciphered Date

2014/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR- VCCSA

Size
C
Date:

Document Number

Rev
0.1

LA-8551P
Saturday, March 03, 2012

Sheet
1

QCL70

53

of

59

A

B

C

D

E

F

G

H

1

1

+CPU_CORE

@PC229
@
PC229
0.1U_0402_25V6
1

2

VCCSENSE 9
1

VSSSENSE
1

PR205 @
0_0402_5%

PHASE_GFX

34

UG_GFX

33

BOOT_GFX

32

EN_GFX

VR_ON
PR240 @
0_0402_5%
1
2
1

PR243
49.9K_0402_1%
2

1

PR244
2.2_0402_1%
2

1

2

ISENAP

ISENAN

COMPA

PR249
2.2_0402_1%
1
2

PC201
150U_D2_6.3VY_R15M

1

2

PC207
0.1U_0402_25V6

2

AON7514
SB00000VA00
PR252
4.7_0402_1%
2 1
2

PQ204
FDMS0308AS 1N POWER56-8

1

VGATE

PR265 @
0_0402_5%

RNTCAN

2

PR254
1.13K_0402_1%
@PR259
@
PR259
2K_0402_1%
1
2

1

PC222
680P_0402_50V7K

1

@

0_0402_5%

2

PR262

2

+GFX_CORE
TDC=21.5A
Ipeak=33A
OCP=39.6A
F=700KHz
Total Capacitor 470uF
ESR 4.5mohm

1

RNTCAP

3

PC225
0.1U_0402_25V6
1
2

PC226
0.1U_0402_25V6

2

9 VR_SVID_CLK

3
2
1

1

1
16.2K_0402_1%
2

PH206
1
10K_0402_1%_ERTJ0EG103FA
2
1

9 VR_SVID_DAT

PC223
560P_0402_50V7K

1

1
2
1
PR264
PR261
3.3K_0402_1% 3.3K_0402_1%

2

54.9_0402_1%

+VGFX_CORE
PL204
0.12UH FDUE0630-H-R12M=P3 32.5A
1
2

5

VGATE

9 VR_SVID_ALRT#

PC227
220P_0402_50V8J

4

1

2

VCC_AXG_SENSE 10

PC228 @
0.1U_0402_25V6
@ PR268
100_0402_5%

2

@ PR267
100_0402_5%

1

1

10 VSS_AXG_SENSE

2

2

PR266 @
0_0402_5%

2

16

1

PQ203
AON7518 1N DFN
PC220
0.22U_0603_10V7K
1
2
4

2

FBA

RGNDA

VCLK

VDIO

ALERT

PC221
0.1U_0402_25V6

2.2_0402_5%
1
2

1

VR_HOT# 36

PR247

3
2
1

VR_HOT#

2
PR258

1

+CPU_5V
+GFX_5V

1

31

36

2

1

1
@PC224
@
PC224

2

1

PVCC

PC219
0.1U_0402_25V6

LG_GFX

35

2
PR235 @
0_0402_5%

2

36

+5VALW
1

1

37

LG_CPU
PR238 @ 0_0402_5%
1
2

1

38

PC215

2

PHASE_CPU

PC218
22U_0805_6.3VAM

UG_CPU

39

1

40

4

0.1U_0402_25V6

PC206
22U_0805_6.3VAM

2
PR223
4.7_0402_1%
2 1
2

5
1
2

1
2

+CPU_CORE
TDC Nom=16A
Ipeak=33A
OCP=39.6A
F=700KHz
Total Capacitor 470uF,
ESR 4.5mohm

2

2

1
BOOT1

3
ISEN1P

TONSET

PC211
0.1U_0402_25V6

PC216
0.1U_0402_25V6

PR255

4

3
2
1

BOOT_CPU
1
2
4
ISEN1N

5

6
FB

COMP

8

7
RGND

9

TONSETA

VR_SVID_ALRT#
VR_SVID_DAT
VR_SVID_CLK

1

PC212
0.1U_0402_25V6
1
2

41

2

130_0402_1%
2

EN

VRHOT

30

PR253

IBIAS

29

150_0402_1%
2

BOOTA

28

+VCCP

@ PR251
1

UGATEA

OCSETA

27

10K_0402_1%
2

PHASEA

TSENA

VCC

FB_GFX

PR250
1

OCSET

26

+3VS

PVCC
LGATEA
RT8167BGQW WQFN 40P PWM

25

75_0402_1%
2

ICCMAXA

24

PR248
1

LGATE1

23

+VCCP

ICCMAX

VRA_READY

2

PR246

20

PHASE1

VR_READY

1

19
PR245

UGATE1

TMPMAX

TSEN

2
PR231 @
10K_0402_1%

PR232
10K_0402_1%

PU201

SETINI

22

3

@PR229
@
PR229
1.69K_0402_1%
1
2

2

1

1

OCSETA

2

PR224
1.58K_0402_1%

PC210
680P_0402_50V7K

2

18

53.6K_0402_1%

1

SANYO
330U 6.3V M D2E ESR25M TPE H1.8

+CPU_CORE

PC217
22U_0805_6.3VAM

17

@ 10K_0402_1%_ERTJ0EG103FA

+5VALW
1
2
PL203
HCB2012KF-121T50_0805

PL202
0.12UH FDUE0630-H-R12M=P3 32.5A
1
2

5

16

PH205

2

AON7514
SB00000VA00

PQ202
FDMS0308AS 1N POWER56-8

2.2U_0603_10V6K

15

PR242
6.65K_0402_1%
1
2

+

PQ201
AON7518 1N DFN
4

4

FB_CPU
13

10K_0402_1%
2
1

PR241 @
0_0402_5%
1
2

GFXPS2

10

OCSET

PR239

VCC

VCC

SETINIA
12

14

@ 10K_0402_1%_ERTJ0EG103FA

PC209
390P_0402_50V7K

GND
11

2

2

PR216
2.2_0402_1%
1
2

3
2
1

2
1
2.4K_0402_1%

PR234

21

1

2
1
432_0402_1%

PH202
10K_0402_1%_ERTJ0EG103FA
1
2
2

2

432_0402_1%

1
2

PC213

0.1U_0402_25V6

PR226
2.4K_0402_1%
2
1

PH203
10K_0402_1%_ERTJ0EG103FA
1
2
1

PH204
1

PC208
0.22U_0603_10V7K
1
2

1

PR228

10K_0402_1%
2
1

VCC

PR233

1

0.1U_0402_25V6

PC214

PR236
@ 0_0402_5%
1
2

1

2
1
16.9K_0402_1%
2

PR222

VCC

PR237
13.3K_0402_1%

PR215
2.2_0402_5%
1
2

PR221

10K_0402_1%
2

PR219

2

PC204
0.1U_0402_25V6

1

33K_0402_1%
2
1

10K_0402_1%
2
1

10K_0402_1%
2
1

ICCMAXA
PR218

1

PR214
3.3K_0402_1%

ICCMAX

PR217

PC202
390P_0402_50V7K

5

RNTC1P

PL201
HCB2012KF-121T50_0805
1
2

+CPU_5V

PR201
2.2_0402_1%
1
2

PC205
22U_0805_6.3VAM

1

PR213
49.9K_0402_1%
1
2

PR210
3.3K_0402_1%

1

2

10K_0402_1%
2

SETINIA
TEMPMAX

RNTC1N

2

PC203
2.2U_0603_10V6K

@ PR212
@PR212

1

1

2

VCC

1

1

1

1

PR209
51K_0402_1%
2

PR208
66.5K_0402_1%
2

1
66.5K_0402_1%
2

PR207

PH201
10K_0402_1%_ERTJ0EG103FA
2
1

2

PR206
2.2_0402_1%
VCC

2

1

2

1

PR204 @
0_0402_5%

2

9
+5VALW

2

PR203 @
100_0402_5%

2

@PR202
@
PR202
100_0402_5%

+VGFX_CORE

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/10/03

Deciphered Date

2014/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PWR- CPU GFX CORE
Size
A2
Date:

Document Number

Rev
0.1

LA-8551P

Saturday, March 03, 2012

Sheet

54

of

59

ev
0.1

1

2

3

4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

E

F

Date:
G

Saturday, March 03, 2012

Sheet
H

54

of

59

5

4

3

2

1

D

D

DRVL

7

+VGA CORE_5V

6

LG_VGA CORE

+5VALW

1
2

DIS@ PC801
10U_0805_25V6K

1
2

DIS@ PC804
10U_0805_25V6K

1
2

DIS@ PC803
2200P_0402_50V7K

1
2

1

2
1

3
2
1

2

2

1
+

DIS@ PR817
5.1K_0402_1% 23
1
2

2

GPU_VID0

@ PR818
3K_0402_5%

Rtrip = 84.5K, OCP = 40A

GPU VID1

L

L

1

L

H

0.9

H

L

0.94

H

H

0.875

A

Issued Date

2011/10/03

Deciphered Date

2014/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

GPU VID0

Compal Secret Data

Security Classification

3

B

Rrf = 470K, FSW = 290KHz

1

S

26

+VGA_CORE
TDC=23.4A
Peak Current=33.8A
OCP current=40A
Rtrip=84.5K

DIS@ PR816
10K_0402_1%

DIS@ PC818
.1U_0402_16V7K

2
2
G
1

DIS@ PR814
3K_0402_5%

1

D

DIS@ PQ806
SSM3K7002FU_SC70-3

2

1
1

GPU_VID1

2

VCCSENSE_VGA

1

2

1

2

+3VGS

2

DIS@ PR813
23
5.1K_0402_1%

1

2

1 1

@ PR812
10K_0402_1%

3

DIS@ PR811
16K_0402_1%
2

+3VGS

2
G
3

680P_0603_50V7K

1

+

2

DIS@ PQ805
SSM3K7002FU_SC70-3

DIS@ PR808
4.22K_0402_1%
1
2

DIS@ PC810

DIS@ PR810
10K_0402_1%

5

1

DIS@ PR809
100_0402_5%
1
2

D

S

4

2

2
B

DIS@ PQ804
MDU1512RH_POWERDFN56-8-5

VSSSENSE_VGA 26

3
2
1

2
2

DIS@ PR807
10_0402_5%

DIS@ PC817
.1U_0402_16V7K

1

1

1

4

DIS@ PQ803
MDU1512RH_POWERDFN56-8-5

DIS@ PC807
1U_0603_6.3V6M

DIS@
DIS@ PR806
470K_0402_1%

2

DIS@ PR805
4.7_1206_5%

+VGA_CORE
C

+

11

TPS51212DSCR_SON10_3X3

@ PC808
.1U_0402_16V7K

DIS@ PC802
0.1U_0402_25V6

5

0.36UH +-20% SH00000R500

DIS@ PL802
0.36UH_MMD-12CE-R36M-M1L_34A_20%
1
2

DIS@ PR815
9.1K_0402_1%
1 1
2

TP

B+

DIS@

RF

SW_VGA CORE

DIS@ PC815
470U_D2_2VM_R4.5M

5

V5IN

UG_VGA CORE

8

DIS@ PC814
470U_D2_2VM_R4.5M

RF_VGA CORE

VFB

SW

BST_VGA CORE

9

PC813
470U_D2_2VM_R4.5M

4

EN

10

2

FB_VGA CORE

DRVH

DIS@ PC809
0.1U_0402_25V6

3

VBST

TRIP

1

EN_VGA CORE

PGOOD

1

24 PXS_PWREN_R

DIS@ PR804
0_0402_5%
1
2

2

5

C

TRIP_VGA CORE

2

HCB2012KF-121T50_0805

4

5

2
84.5K_0402_1%

DIS@ PL801
1

3
2
1

PU801

1
1
DIS@ PR803

DIS@ PQ802
MDU1516URH_POWERDFN56-8-5

EE Modify

4

3
2
1

DIS@ PR802
DIS@ PC805
2.2_0603_5% 0.22U_0603_16V7K
1
2
1
2

5

DIS@ PQ801
MDU1516URH_POWERDFN56-8-5

+VGA CORE_B+

2

Title

Thames XT/Thames Pro

A

Compal Electronics, Inc.
PWR- VGA_VDDC

Size
Document Number
Custom
Date:

Rev
0.1

LA-8551P

Wednesday, March 07, 2012

Sheet
1

55

of

59

5

4

3

2

1

D

DIS@ PC1052
680P_0402_50V7K

SNUB_1.0VGSP

1

2

D

C

2

C

DIS@ PR1052
4.7_0402_1%

PJP1051

2

1
2

1

1

+1.0VGSP

DIS@ PC1055
22U_0805_6.3V6M

1

2

NC

NC

DIS@ PC1054
22U_0805_6.3V6M

1.0VGSP_FB

2

6

2

FB
EN

+1.0VGSP
DIS@ PC1053
22P_0402_50V8J

1

3

DIS@ PR1053
20K_0402_1%

4
PG

2

DIS@ PR1055
28.7K_0402_1%

PC1056 @
0.1U_0402_10V7K

LX

SVIN

TP

5

1
2

PR1054
47K_0402_5%

2

@

LX

PVIN

11

EN_1.0VGSP

2

DIS@ PR1051
0_0402_5%

PVIN

DIS@ PL1052
1UH_SIG4018-1R0_3A_20%
1.0VGSP_LX
1
2

1

9
8

1

1

10

7

1.0VGSP_VIN

DIS@ PC1051
22U_0805_6.3V6M

2

1

+5VALW

1

SH00000MW00
DIS@ PU1051
SY8033BDBC_DFN10_3X3

DIS@ PL1051
HCB1608KF-121T30_0603
1
2

2

2

1

1

@ JUMP_43X39

+1.0VGS

+1.0VSP
TDC=1.54A
Peak Current=2.2A

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/10/03

Deciphered Date

2014/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

PWR- VGA 1.0VGSP
Size
C
Date:

Document Number

Rev
0.1

LA-8551P
Monday, March 05, 2012

Sheet
1

56

of

59

A

1

5

1

2

1

4

1

1

2

1

Security Classification

Issued Date
2011/10/03

3

2

1

Deciphered Date

2

1

2

1

2

1

2014/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Title

Size

Date:

2

1

1

PC1134
10U_0603_6.3V6M

PC1135
10U_0603_6.3V6M

2

PC1153
1U_0402_6.3V6K

2

1

PC1165
1U_0402_6.3V6K

1

PC1133
10U_0603_6.3V6M

2

1

2

PC1152
1U_0402_6.3V6K

PC1132
10U_0603_6.3V6M

1

2

PC1164
1U_0402_6.3V6K

1

PC1131
10U_0603_6.3V6M

2

PC1151
1U_0402_6.3V6K

2

PC1150
1U_0402_6.3V6K

1

1

PC1163
1U_0402_6.3V6K

1

2

2

2

1

1

PC1162
1U_0402_6.3V6K

2

2

PC1130
10U_0603_6.3V6M

2

PC1149
1U_0402_6.3V6K

PC1129
10U_0603_6.3V6M

1

PC1161
1U_0402_6.3V6K

1
PC1148
1U_0402_6.3V6K

2

PC1147
1U_0402_6.3V6K

PC1128
10U_0603_6.3V6M

PC1116
330U_D2_2V_Y

PC1117
330U_D2_2V_Y

1

1

1

1
PC1112
22U_0805_6.3V6M

2

PC1111
22U_0805_6.3V6M

2

PC1110
22U_0805_6.3V6M

2

PC1109
22U_0805_6.3V6M

2

PC1108
22U_0805_6.3V6M

PC1113
22U_0805_6.3V6M

1
PC1115
22U_0805_6.3V6M

2

PC1114
22U_0805_6.3V6M

3

PC1177
1U_0402_6.3V6K

1

1

2

PC1160
1U_0402_6.3V6K

2

PC1159
1U_0402_6.3V6K

2

1

PC1176
1U_0402_6.3V6K

1

1

1

2

2

2

2

PC1146
1U_0402_6.3V6K

1

PC1175
1U_0402_6.3V6K

1

1

2

2

2

1

PC1158
1U_0402_6.3V6K

2

PC1127
10U_0603_6.3V6M

1

PC1174
1U_0402_6.3V6K

PC1126
10U_0603_6.3V6M

2

PC1145
1U_0402_6.3V6K

1

1

PC1157
1U_0402_6.3V6K

1

2

PC1125
2.2U_0402_6.3V6M

+

PC1173
1U_0402_6.3V6K

2

2

1

1

2

1

1

1

2

PC1144
1U_0402_6.3V6K

2

2

PC1143
2.2U_0402_6.3V6M

2

PC1124
2.2U_0402_6.3V6M

+

1

1

1

1

PC1123
2.2U_0402_6.3V6M

2

1

2

2

2
PC1142
2.2U_0402_6.3V6M

1

PC1107
22U_0805_6.3V6M

2

PC1156
1U_0402_6.3V6K

1

PC1141
2.2U_0402_6.3V6M

2

2
PC1122
2.2U_0402_6.3V6M

PC1106
22U_0805_6.3V6M

4

PC1172
1U_0402_6.3V6K

1

1

PC1121
2.2U_0402_6.3V6M

2

PC1105
22U_0805_6.3V6M

1

PC1194
1U_0402_6.3V6K

1

2
PC1140
2.2U_0402_6.3V6M

1

PC1120
2.2U_0402_6.3V6M

2

2

2

1

PC1139
2.2U_0402_6.3V6M

2

1

1

PC1193
1U_0402_6.3V6K

2

PC1192
1U_0402_6.3V6K

PC1171
22U_0805_6.3V6M

1

PC1138
2.2U_0402_6.3V6M

2

2
PC1119
2.2U_0402_6.3V6M

+

PC1101
470U_D2_2VM_R4.5M

5

2

PC1191
1U_0402_6.3V6K

2
PC1183
10U_0603_6.3V6M

1

2

2
2

PC1190
1U_0402_6.3V6K

1
1

PC1189
1U_0402_6.3V6K

PC1170
22U_0805_6.3V6M

2

PC1182
10U_0603_6.3V6M

1

1

2

2

2

1

1

PC1169
22U_0805_6.3V6M

2

PC1181
10U_0603_6.3V6M

1

2

2
2

1

PC1188
1U_0402_6.3V6K

1
1

PC1187
1U_0402_6.3V6K

PC1168
22U_0805_6.3V6M

2

PC1180
10U_0603_6.3V6M

1

1

1

1

PC1104
22U_0805_6.3V6M

2

2

2

2
PC1137
2.2U_0402_6.3V6M

1

PC1118
2.2U_0402_6.3V6M

2

1

PC1186
1U_0402_6.3V6K

PC1167
22U_0805_6.3V6M

2

1

1

1

2

2

1

PC1136
2.2U_0402_6.3V6M

2

2

PC1179
10U_0603_10V6M

2

2

1
PC1154
470U_D2_2VM_R4.5M

2

PC1166
22U_0805_6.3V6M

1
1

PC1185
1U_0402_6.3V6K

1

+

PC1178
10U_0603_10V6M

2

C

PC1184
1U_0402_6.3V6K

1

D

2

+CPU_CORE

2
1

+CPU_CORE

1

2
D

+VCCP

+VCCP

C

+VGFX_CORE

+VGFX_CORE

B
B

A

PWR - PROCESSOR DECOUPLING

Compal Electronics, Inc.

Document Number

LA-8551P

Saturday, March 03, 2012

Rev
0.1

1

Sheet
57
of
59

5

4

3

2

Version Change List ( P. I. R. List )
Item Page#

Title

Date

Request
Owner

1

Page 1

Issue Description

Solution Description

Rev.

D

C

D

1

47

change PC111 to 0402

2011/11/28

For layout space

2

47

remove PR121

2011/11/28

0ohm, not needed

3

47

change PR124 to 270K, PR126 to 42.2K

2011/11/28

change Vin detector setting

4

47

change PC125 to 0.047uF

2011/11/28

5

47

change PR125 to 0ohm, PC126 to 100pF

2011/11/28

FAE review recommand

6

47

change PR119 to 365K

2011/11/28

modify charge Ilimit to 3.54A

7

47

change PR111 to 0ohm

2011/11/28

8

47

add PL101

2011/11/28

9

46

delete PD5, PD6

2011/11/28

10

46

SMC, SMD exchange

2011/11/28

11

46
47

delete pin8 and pin5,
add battery temp sense at pin5.
change PQ302 to AON7518

2011/11/28

12
13

50, 52

change PU1001, PU401 from SY8036HDBC to SY8036LDBC
2011/11/28

14

53

change PU651 from SY8037DCC to SY8037ADCC

2011/11/28

15

52

add PQ401, PR406, PR407, PC411

2011/11/28

16

56

change PR1055 to 28.7K

2011/11/28

17

54

change PL202, PL204 to SH00000PP00, 0.12uH

2011/11/28

18

54

change PU201 to RT8167, SA00005AU00

2011/11/28

19

54

change PQ201, PQ203 to AON7518, SB00000U300

2011/11/28

20

54

change PQ202, PQ204 to FDMS0308AS, SB00000U400

2011/11/28

21

55

change PL802 to 0.36uH, SH00000HD00

2011/11/28

22

52

change PU401 to SY8809DFC

2011/11/29

23

45, 48

change PD2, PD301 DIO CD4148WN-1 1206

2011/11/29

24

51

add PC511, PC512

2011/12/11

25

54

change PL201 to 0805, and add PL203

2011/12/11

26

48

add PR320

2011/12/11

27

55

change PC813, PC814, PC815, PC816 tp 330uF 9m

2011/12/11

28

47

change PQ101 to SB000009610

2011/12/11

29

54

change PR210, PR214, PR261, PR264 to 3.3K;
PR222 to 15.8K; PR255 to 10.5K;
PC202, PC209 to 270p; PC223 to 220p;
PC227 to 560p; PR224, PR254 to 1.82K;
PR207 to 127K

2011/12/11

B

imbedded battery, ESD diode is not needed

EC request to need one detect pin if SMB communication fail.

2011/11/28

C

for correct 1.0V voltage

For cost and layout space

tune frequency

Fine tune CPU, GFX transient
B

30

47, 54

change PR111, PR110, PR216, PR249 to 2.2 ohm

2011/12/12

31

53, 56

change PL602, PL1052 to SH00000MW00

2011/12/12

For EMI solution
For crack issue

32

55

change PL802 to SH00000HQ00

2011/12/12

For thermal solution

33

48

change PL303 to SH00000ON00

2011/12/12

For thermal solution

34

47

change PR114, PR115 to 0 ohm

2011/12/14

Prevent charger damaged by negative output voltage
For GFX GT2 current limit

35

54

change PR207 to 66.5K

2011/12/14

36

54

change PR237 to

2011/12/23

37

54

change PR241 to 1/16W 0 +-5% 0402

38

54

change PR242 to

39

47

change PQ103, PQ104 to SB00000TZ00

40

47, 48

change PQ106, PQ303 to SB00000H700

2011/12/23

41

54

change PR210,PR261,PR264

2011/12/23

42

53

change PL651 to SY8037CDCC

2012/1/11

For latch mode

43

57

change PC1180, PC1181, PC1182, PC1183
to SE000005T80

2012/1/11

For height limit

44

46

Delete PC11

2012/1/12

For ME request

A

23.7K +-1% 0402

23.7K +-1% 0402

to

3.3K +-1% 0402

2011/12/23
2011/12/23
2011/12/23

A

Compal Secret Data

Security Classification
2011/10/03

Issued Date

2014/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR - PIR

Size

Document Number

Rev
0.1

LA-8551P
Date:

Saturday, March 03, 2012

Sheet
1

58

of

59

5

4

3

2

Version Change List ( P. I. R. List )
Item Page#

Title

Date

Request
Owner

1

Page 2

Issue Description

Solution Description

Rev.

D

D

45

47

change PR114 to 10, PR115 to 6.8ohm, add PD103

2012/1/30

For Charger issue

46

47

Add PC130, PC131, PC104, PC107

2012/1/30

For EMI solution

47

48

Add PR321

2012/1/30

Choose working frequency to improve efficiency and thermal

48

50

change 1.5VPCIE Circuit

2012/1/30

Change input voltage form 5V to 19V to slove thermal issue

49

52

Add PL403

2012/1/30

Choose input voltage to slove thermal issue

50

54

Change PR224 to1.58Kohm, PC209 to 220PF,
PC202 to 390PF, PR222 to 16.9Kohm,
PR237 to 21.5K

2012/1/30

Base on SI layout, FAE review recommand value

51

48

change PL303 to SH00000F600

2012/1/30

For thermal issue

52

45

Delete PD2, PR2, PR3, PC6

2012/1/30

For Layout space

Change PQ302, PQ201, PQ203 to AON7514

2012/1/30

For efficiency

2012/1/30

For Layout space

53

C

B

47, 48,
54

54

51

Delete PJP501

55

55

Change PC813, PC814, PC815 to 470uF, delete PC816 2012/1/30
Change PL802 0.36uF to 13*13*3.5 size

For thermal issue

56

55

Add PC820, PC821, PC822

2012/1/30

For VGA transient voltage

57

57

2012/1/30

For ME request

58

47

Change PC1180, PC1181, PC1182, PC1183 to
SE000005T80
change PQ102 to TPCA8057

59

54

change PC223 to 560pF, PC227 to 220pF

2012/2/17

60

48

change PQ302 to AON7518

2012/2/17

For efficiency

61

55

change PL802 to 13*13*3 size

2012/2/17

For thermal solution

C

2012/1/30
For FAE suggesstion

62

47

For HP and soucer request

54

change PR114, PR115 to 0 ohm, PD103 to
SCS00005800
change PC201 to 330uF

2012/2/17

63

2012/2/17

For acoustic solution

64

45

change LED circuit

2012/2/23

65

48

change PL303 to 3.3uH 10*10*3H, PC313
to 150U_B2_6.3VM_R35M, remove 5V output jumper

2012/2/23

For thermal solution

66

53

change PU651 to SY8037DDCC

2012/2/23

For ULV CPU and latch mode

67

55

change PR812 and PR816 power to +3VGS

2012/2/23

For leakage issue

68

45

change LED circuit

2012/2/29

69

54

change PC209 to 390pF, PR237 to 13.3Kohm,
PR254 to 1.13Kohm, PR255 to 16.2Kohm,
PR242 to 6.65Kohm

2012/2/29

Base on PV layout

70

45

change PL1, PL2 to 0603 size, add PL4

2012/2/29

EMI request

B

A

A

Compal Secret Data

Security Classification
2011/10/03

Issued Date

2014/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR - PIR

Size

Document Number

Rev
0.1

LA-8551P
Date:

Saturday, March 03, 2012

Sheet
1

59

of

59

5

4

3

2

1

B+
PXS_PWREN_R
+VGA_CORE

TPS51212DSCR
SUSP#,SYSON

+VCCP

TPS51212DSCR

BATT+

BQ24725ARGRR

+3VALW
D

RT8205LZQW

D

SUSP
+3VS

SI7326DN
PCH_PWR_EN#

+3V_PCH

SI7326DN
+5VALW
VR_ON

+CPU_CORE

RT8165BGQW

+VGFX_CORE

PXS_PWREN
+1.0VGS

SY8033BDBC
VCCSA_EN

+VCCSA

SY8037DCC
SUSP#

+1.5V_PCIE

SY8036DBC
SUSP#
C

+1.5VS

SY8033BDBC

C

SUSP
+5VS

SI7326DN
PCH_PWR_EN#

+5V_PCH

AO3413L
SYSON

+1.5V

SY8036DBC
SUSP
SI4800

+1.5VS

SUSP
APL5336KAI

+0.75VS

B

B

Title