Compal LA 9241P Schematics. Www.s Manuals.com. R0.5 Schematics
User Manual: Motherboard Compal LA-9241P Viper MXM - Schematics. Free.
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A B C D E 1 1 Compal Confidential 2 2 Intel Haswell rPGA Processor with Lynx Point-H Viper MXM Date : 2012/12/20 Version 0.5 3 3 4 4 2011/06/29 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/29 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Cover Page Rev 0.5 LA-9241P Date: A B C D Thursday, December 20, 2012 Sheet E 1 of 56 A B C D E Compal Confidential Model Name : File Name : 1 1 DDR3-SO-DIMM2, 4 LVDS Panel Conn. eDP to LVDS RTD 2136 eDP DeMUX PS8321 Page eDP Panel Conn. Page 22 DP Conn DP MUX PS8338 Page Page 39 DPC 36 Dock Conn DPD DPE Page 33 ThunderBolt Cactus Ridge Mini DP Conn. Dock Conn CRT VGA Conn CRT Page 33 Page 39 Intel Haswell eDPF MXM3.0 Conn AMD: nVidia: PEGx16 FDI x2 VGA Switch 2 to 2 MAX14885EETL 100MHz 2.7GT/s 5GT/s Port 7 Port 1 100MHz Port 2 Page 39 Page 25 Port 6 Port 13 ODD Conn. Page 23 mSATA Conn. Page 23 SATA HDD Conn. Page 23 33 Smart card Controller Page 37 AU9540A51 WWANPage 25 HD Audio HDA Codec IDT 92HD91 Page 26 2 SIM Card Page 25 FPR Validity VFM471 Page 28 Page 22 Port 0 20mm*20mm Page 13,14,15,16,17,18,19,20,21 USB 2.0 Bus SD/MMC Slot X1 USB3.0 x3 Dock x1 Page Digital MIC SPI WLAN (MINI card) X1 USB 2.0 x 11 Combo Jack X1 Webcam X1 USB2.0 Page 22 Page 39 SPK conn Page 27 X1 BIOS SPI ROM x1, 16 MB Page 30 X1 33MHz Page 29 3 Expresscard X1 PCH 695pin BGA LPC BUS GLAN Intel Clarkville Page 39 X4 X4 Intel Lynx Point (GEN1 1.5Gb/S GEN2 3Gb/S GEN3 6Gb/S) Card Reader Controller Page 11 USB 3.0 x4 CRT SATAx4 Port 5 BANK 0, 1, 2, 3 DMI x4 100MHz Page 36 PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) Port 6 Ch A 37.5mm*37.5mm Page 4,5,6,7,8,9,10 X4 Port 8 DDR3-SO-DIMM1, 3 DDR3L 1333MHz 1.35V rPGA Processor rPGA947 Page 35 Page 36 Page 12 eDP 36 CRT 2 BANK 0, 1, 2, 3 Ch B Page 39 WLAN Page Dock 25 Page 33 3 RJ45 Conn. Page 29 Accelerometer ST HP3DC2 Page Super I/O SMSC LPC47N217 Page 32 28 TPM1.2 Infineon SLB9656/9635 Page 30 KBC SMSC KBC1126 Page 28 CPU FAN1 conn. EC ROM 2MB Page 30 PS2 Page 24 Touch pad daughter board SMBus (PCH) Touch Pad Page 38 RTC CKT. SPI(PCH) Docking connector: RJ45 USB30*1 USB20*1 DP*2 Parallel port Serial port PS2 Line in/Line out SATAx2 VGA Int.KBD Page 38 Page 13 4 4 Power On/Off CKT. DC/DC interface CKT. Page 34 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 Deciphered Date 2011/06/29 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D Block Diagrams Rev 0.5 LA-9241P Thursday, December 20, 2012 E Sheet 2 of 56 5 4 3 2 1 D D C C B B A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 2011/06/29 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 SMBus block diagram_DSC Rev 0.5 LA-9241P Sheet Thursday, December 20, 2012 1 3 of 56 5 4 3 2 1 +VCCIOA_OUT PEG_COMP 24.9_0402_1% D 2 1 D RC1 CAD Note: Trace width=12 mils ,Spacing=15mil Max length= 400 mils. Haswell rPGA EDS JCPU1A [14] [14] [14] [14] DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 [14] [14] [14] [14] DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 [14] [14] [14] [14] DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 FDI_CSYNC FDI_INT D21 C21 B21 A21 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 D20 C20 B20 A20 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 D18 C17 B17 A17 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 FDI_CSYNC FDI_INT D17 C18 B18 A18 H29 J29 DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 FDI_CSYNC DISP_INT FDI [14] [14] DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 PEG DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI C [14] [14] [14] [14] B INTEL_HASWELL_HASWELL PEG_RCOMP PEG_RXN_0 PEG_RXN_1 PEG_RXN_2 PEG_RXN_3 PEG_RXN_4 PEG_RXN_5 PEG_RXN_6 PEG_RXN_7 PEG_RXN_8 PEG_RXN_9 PEG_RXN_10 PEG_RXN_11 PEG_RXN_12 PEG_RXN_13 PEG_RXN_14 PEG_RXN_15 PEG_RXP_0 PEG_RXP_1 PEG_RXP_2 PEG_RXP_3 PEG_RXP_4 PEG_RXP_5 PEG_RXP_6 PEG_RXP_7 PEG_RXP_8 PEG_RXP_9 PEG_RXP_10 PEG_RXP_11 PEG_RXP_12 PEG_RXP_13 PEG_RXP_14 PEG_RXP_15 PEG_TXN_0 PEG_TXN_1 PEG_TXN_2 PEG_TXN_3 PEG_TXN_4 PEG_TXN_5 PEG_TXN_6 PEG_TXN_7 PEG_TXN_8 PEG_TXN_9 PEG_TXN_10 PEG_TXN_11 PEG_TXN_12 PEG_TXN_13 PEG_TXN_14 PEG_TXN_15 PEG_TXP_0 PEG_TXP_1 PEG_TXP_2 PEG_TXP_3 PEG_TXP_4 PEG_TXP_5 PEG_TXP_6 PEG_TXP_7 PEG_TXP_8 PEG_TXP_9 PEG_TXP_10 PEG_TXP_11 PEG_TXP_12 PEG_TXP_13 PEG_TXP_14 PEG_TXP_15 E23 M29 K28 M31 L30 M33 L32 M35 L34 E29 D28 E31 D30 E35 D34 E33 E32 L29 L28 L31 K30 L33 K32 L35 K34 F29 E28 F31 E30 F35 E34 F33 D32 H35 H34 J33 H32 J31 G30 C33 B32 B31 A30 B29 A28 B27 A26 B25 A24 J35 G34 H33 G32 H31 H30 B33 A32 C31 B30 C29 B28 C27 B26 C25 B24 PEG_COMP PEG_CRX_GTX_N0 PEG_CRX_GTX_N1 PEG_CRX_GTX_N2 PEG_CRX_GTX_N3 PEG_CRX_GTX_N4 PEG_CRX_GTX_N5 PEG_CRX_GTX_N6 PEG_CRX_GTX_N7 PEG_CRX_GTX_N8 PEG_CRX_GTX_N9 PEG_CRX_GTX_N10 PEG_CRX_GTX_N11 PEG_CRX_GTX_N12 PEG_CRX_GTX_N13 PEG_CRX_GTX_N14 PEG_CRX_GTX_N15 PEG_CRX_GTX_P0 PEG_CRX_GTX_P1 PEG_CRX_GTX_P2 PEG_CRX_GTX_P3 PEG_CRX_GTX_P4 PEG_CRX_GTX_P5 PEG_CRX_GTX_P6 PEG_CRX_GTX_P7 PEG_CRX_GTX_P8 PEG_CRX_GTX_P9 PEG_CRX_GTX_P10 PEG_CRX_GTX_P11 PEG_CRX_GTX_P12 PEG_CRX_GTX_P13 PEG_CRX_GTX_P14 PEG_CRX_GTX_P15 PEG_CTX_GRX_C_N0 PEG_CTX_GRX_C_N1 PEG_CTX_GRX_C_N2 PEG_CTX_GRX_C_N3 PEG_CTX_GRX_C_N4 PEG_CTX_GRX_C_N5 PEG_CTX_GRX_C_N6 PEG_CTX_GRX_C_N7 PEG_CTX_GRX_C_N8 PEG_CTX_GRX_C_N9 PEG_CTX_GRX_C_N10 PEG_CTX_GRX_C_N11 PEG_CTX_GRX_C_N12 PEG_CTX_GRX_C_N13 PEG_CTX_GRX_C_N14 PEG_CTX_GRX_C_N15 PEG_CTX_GRX_C_P0 PEG_CTX_GRX_C_P1 PEG_CTX_GRX_C_P2 PEG_CTX_GRX_C_P3 PEG_CTX_GRX_C_P4 PEG_CTX_GRX_C_P5 PEG_CTX_GRX_C_P6 PEG_CTX_GRX_C_P7 PEG_CTX_GRX_C_P8 PEG_CTX_GRX_C_P9 PEG_CTX_GRX_C_P10 PEG_CTX_GRX_C_P11 PEG_CTX_GRX_C_P12 PEG_CTX_GRX_C_P13 PEG_CTX_GRX_C_P14 PEG_CTX_GRX_C_P15 PEG_CRX_GTX_N[0..15] [35] PEG_CTX_GRX_P[0..15] PEG_CTX_GRX_N[0..15] PEG_CRX_GTX_P[0..15] [35] PEG_CTX_GRX_P[0..15] [35] PEG_CTX_GRX_N[0..15] [35] PEG_CTX_GRX_C_P0 PEG_CTX_GRX_C_N0 CC1 CC2 2 2 1 0.22U_0402_6.3V6K 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P0 PEG_CTX_GRX_N0 PEG_CTX_GRX_C_P1 PEG_CTX_GRX_C_N1 CC3 CC4 2 2 1 0.22U_0402_6.3V6K 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P1 PEG_CTX_GRX_N1 PEG_CTX_GRX_C_P2 PEG_CTX_GRX_C_N2 CC5 CC6 2 2 1 0.22U_0402_6.3V6K 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P2 PEG_CTX_GRX_N2 PEG_CTX_GRX_C_P3 PEG_CTX_GRX_C_N3 CC7 CC8 2 2 1 0.22U_0402_6.3V6K 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P3 PEG_CTX_GRX_N3 PEG_CTX_GRX_C_P4 PEG_CTX_GRX_C_N4 CC9 2 CC10 2 1 0.22U_0402_6.3V6K 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P4 PEG_CTX_GRX_N4 PEG_CTX_GRX_C_P5 PEG_CTX_GRX_C_N5 CC11 2 CC12 2 1 0.22U_0402_6.3V6K 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P5 PEG_CTX_GRX_N5 PEG_CTX_GRX_C_P6 PEG_CTX_GRX_C_N6 CC13 2 CC14 2 1 0.22U_0402_6.3V6K 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P6 PEG_CTX_GRX_N6 PEG_CTX_GRX_C_P7 PEG_CTX_GRX_C_N7 CC15 2 CC16 2 1 0.22U_0402_6.3V6K 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P7 PEG_CTX_GRX_N7 PEG_CTX_GRX_C_P8 PEG_CTX_GRX_C_N8 CC17 1 CC18 1 2 0.22U_0402_6.3V6K 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P8 PEG_CTX_GRX_N8 PEG_CTX_GRX_C_P9 PEG_CTX_GRX_C_N9 CC19 1 CC20 1 2 0.22U_0402_6.3V6K 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P9 PEG_CTX_GRX_N9 PEG_CTX_GRX_C_P10 CC21 1 PEG_CTX_GRX_C_N10 CC22 1 2 0.22U_0402_6.3V6K 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P10 PEG_CTX_GRX_N10 PEG_CTX_GRX_C_P11 CC23 1 PEG_CTX_GRX_C_N11 CC24 1 2 0.22U_0402_6.3V6K 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P11 PEG_CTX_GRX_N11 PEG_CTX_GRX_C_P12 CC25 1 PEG_CTX_GRX_C_N12 CC26 1 2 0.22U_0402_6.3V6K 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P12 PEG_CTX_GRX_N12 PEG_CTX_GRX_C_P13 CC27 1 PEG_CTX_GRX_C_N13 CC28 1 2 0.22U_0402_6.3V6K 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P13 PEG_CTX_GRX_N13 PEG_CTX_GRX_C_P14 CC29 1 PEG_CTX_GRX_C_N14 CC30 1 2 0.22U_0402_6.3V6K 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P14 PEG_CTX_GRX_N14 PEG_CTX_GRX_C_P15 CC31 1 PEG_CTX_GRX_C_N15 CC32 1 2 0.22U_0402_6.3V6K 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P15 PEG_CTX_GRX_N15 C B 1 OF 9 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 2011/06/29 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 DMI,PEG Rev 0.5 LA-9241P Thursday, December 20, 2012 Sheet 1 4 of 56 5 4 3 2 1 +VCCIO_OUT 2 1 CC35 1 2 2 PM_DRAM_PWRGD 1 RC9 A 2 O 4 PM_DRAM_PWRGD_CPU 74AHC1G09GW_TSSOP5 Part Number = SA00003Y000 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 XDP_PREQ# XDP_PRDY# Place near JXDP1 5 B [8] [8] CFG0 CFG1 [8] [8] CFG2 CFG3 CFG0 CFG1 CFG2 CFG3 XDP_OBS0 XDP_OBS1 RC10 3.3K_0402_1% RC5 need to close to JCPU1 RC13 1 H_CPUPWRGD 07/30 Non Install QC1 10/18 Delete QC1 and RC12 [14,30] ON/OFFBTN# [9] [14,30] CPU_PWR_DEBUG PM_PWROK [11,12,13,16,28,38] [11,12,13,16,28,38] [8] [8] CFG4 CFG5 [8] [8] CFG6 CFG7 CFG4 CFG5 2 1K_0402_1% CFG6 CFG7 H_CPUPWRGD_XDP 2 0_0402_5% RC107 1 09/23 Change netname to VGATE 09/26 Change netname to PM_PWROK. Add RC107 DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK +VCCIO_OUT JXDP1 2 +3VS 2 100K_0402_1% 3 [14] +VCCIO_OUT 1 1 PWR_GD D P [30,31,47] UC1 2 RC5 1.8K_0402_1% 0.1U_0402_10V6K G 08/10 Add RC106 and change UC1.1 connection to VR_ON 9/11 Delete RC106 09/23 Change netname to PWR_GD 1 CC34 0.1U_0402_16V4Z 1 +1.35VS +5VDS CC33 0.1U_0402_16V4Z SM_DRAMPWROK with DDR Power Gating Topology XDP_TCLK GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 SAMTE_BSH-030-01-L-D-A [24,47] 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 CFG17 CFG16 CFG17 CFG16 CFG8 CFG9 CFG8 CFG9 CFG10 CFG11 CFG19 CFG18 CFG12 CFG13 CFG14 CFG15 CFG10 CFG11 [8] [8] CFG19 CFG18 [8] [8] CFG12 CFG13 [8] [8] CFG14 CFG15 [8] [8] 2 XDP_RST#_R XDP_DBRESET# [8] [8] [8] [8] D 1 PLT_RST# 1K_0402_1% RC16 PLT_RST# [13,14,25,28,29,30,35,37,39] XDP_TDO XDP_TRST# XDP_TDI XDP_TMS 2 1 CFG3 1K_0402_1% RC105 CONN@ KBC_PROC_HOT_R KBC_PROC_HOT_R +VCCIO_OUT 07/25 Delete RC24 Haswell rPGA EDS 1 JCPU1B PM_SYNC PWRGOOD SM_DRAMPWROK PLTRSTIN 09/11 Connect CPU.AT26 pin to CPU_PLTRST# G28 H28 F27 E27 D26 E26 [15] CLK_CPU_DPLL# [15] CLK_CPU_DPLL CLK_CPU_SSC_DPLL# CLK_CPU_SSC_DPLL [15] CLK_CPU_DMI# [15] CLK_CPU_DMI DPLL_REF_CLKN DPLL_REF_CLKP SSC_DPLL_REF_CLKN SSC_DPLL_REF_CLKP BCLKN BCLKP INTEL_HASWELL_HASWELL CLOCK [15] [15] BPM_N_0 BPM_N_1 BPM_N_2 BPM_N_3 BPM_N_4 BPM_N_5 BPM_N_6 BPM_N_7 2 OF 9 XDP_OBS0 XDP_OBS1 XDP_OBS2_R XDP_OBS3_R XDP_OBS4_R XDP_OBS5_R XDP_OBS6_R XDP_OBS7_R XDP_DBRESET# 1 [14] CPU_DRAM_RST# [11] 2 AR30 AN31 AN29 AP31 AP30 AN28 AP29 AP28 QC2 3 DDR3_DRAMRST#_CPU 1 XDP_PRDY# XDP_PREQ# XDP_TCLK XDP_TMS XDP_TRST# XDP_TDI XDP_TDO XDP_DBRESET# C RC25 1 2 3.3K_0402_5% DDR_RST_EN [16] 1 CPU_PLTRST# AR29 AT29 AM34 AN33 AM33 AM31 AL33 AP33 0_0402_5% BSS138W-7-F_SOT323-3 T144 T145 T146 T147 T148 T149 @ @ @ @ @ @ PAD PAD PAD PAD PAD PAD [30,45] KBC_DS3_EN 1 [18] AT28 AL34 AC10 AT26 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 DDR3_DRAMRST#_CPU D 3 3 S H_PM_SYNC H_CPUPWRGD PM_DRAM_PWRGD_CPU CPU_PLTRST# PWR [14] H_PM_SYNC [18] H_CPUPWRGD JTAG 1 09/11 Delete RC27 and connect CPU.AM35 pin to PCH_THERMTRIP#_R 2 G PRDY PREQ TCK TMS TRST TDI TDO DBR AP3 AR3 AP2 AN3 G D PCH_THERMTRIP#_R CATERR PECI FC_AK31 PROCHOT THERMTRIP SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 SM_DRAMRST D KBC_PROC_HOT# [18,24,35] Q59 AN32 AR27 AK31 AM30 AM35 MISC RC28 4.99K_0402_1% [24,30] 2N7002KW_SOT323-3 T118 @ SKTOCC S C 1 H_CATERR# H_PECI H_PECI PAD T1 @ 2 56_0402_5% KBC_PROC_HOT_R PCH_THERMTRIP#_R PAD [30] RC26 CPU_DETECT# AP32 THERMAL #4/9 change by HP requirement T120 @ 2 PAD KBC_PROC_HOT 2 @ RC22 62_0402_5% S 2 G For ESD concern, please put near CPU RC108 10K_0402_1% @ QC3 2N7002_SOT23 2 #4/92 change by HP requirement DDR3 1 RC23 10/18 Uninstall QC3 10/12 Reserve RC108 10/18 Change RC108 to 10k ohms, and install RC108 09/11 Noninstall RC36, RC38, RC40, RC43, RC45, RC47 11/07 Delete RC36, RC38, RC40, RC43, RC45, RC47 by ESD request. Add T144, T145, T146, T147, T148, T149 PU/PD for JTAG signals +3VS XDP_DBRESET# RC52 2 1 1K_0402_1% 09/11 Change RC55.1 connection to H_CPUPWRGD +1.05VS 1 H_CPUPWRGD RC55 10K_0402_1% B DDR3 COMPENSATION SIGNALS 2 B CAD Note: Avoid stub in the PWRGD path while placing resistors RC25 & RC130 09/11 Delete RC66 XDP_TDO RC57 2 1 51_0402_1% SM_RCOMP0 RC59 1 2 100_0402_1% XDP_TCLK RC60 2 1 51_0402_1% SM_RCOMP1 RC61 1 2 75_0402_1% XDP_TRST# RC62 2 1 51_0402_1% SM_RCOMP2 RC65 1 2 100_0402_1% CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 Deciphered Date 2011/06/29 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 PM,XDP,CLK Rev 0.5 LA-9241P Thursday, December 20, 2012 1 Sheet 5 of 56 5 4 3 2 1 D D Haswell rPGA EDS JCPU1C [11] DDR_A_D[0..63] AR15 AT14 AM14 AN14 AT15 AR14 AN15 AM15 AM9 AN9 AM8 AN8 AR9 AT9 AR8 AT8 AJ9 AK9 AJ6 AK6 AJ10 AK10 AJ7 AK7 AF4 AF5 AF1 AF2 AG4 AG5 AG1 AG2 J1 J2 J5 H5 H2 H1 J4 H4 F2 F1 D2 D3 D1 F3 C3 B3 B5 E6 A5 D6 D5 E5 B6 A6 E12 D12 B11 A11 E11 D11 B12 A12 AM3 F16 F13 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 C B +SM_VREF_CA +DIMM01_VREF_DQ +DIMM23_VREF_DQ SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SM_VREF SA_DIMM_VREFDQ SB_DIMM_VREFDQ Haswell rPGA EDS RSVD SA_CK_N_0 SA_CK_P_0 SA_CKE_0 SA_CK_N_1 SA_CK_P_1 SA_CKE_1 SA_CK_N_2 SA_CK_P_2 SA_CKE_2 SA_CK_N_3 SA_CK_P_3 SA_CKE_3 SA_CS_N_0 SA_CS_N_1 SA_CS_N_2 SA_CS_N_3 SA_ODT_0 SA_ODT_1 SA_ODT_2 SA_ODT_3 SA_BS_0 SA_BS_1 SA_BS_2 VSS SA_RAS SA_WE SA_CAS SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15 SA_DQS_N_0 SA_DQS_N_1 SA_DQS_N_2 SA_DQS_N_3 SA_DQS_N_4 SA_DQS_N_5 SA_DQS_N_6 SA_DQS_N_7 SA_DQS_P_0 SA_DQS_P_1 SA_DQS_P_2 SA_DQS_P_3 SA_DQS_P_4 SA_DQS_P_5 SA_DQS_P_6 SA_DQS_P_7 [12] AC7 U4 V4 AD9 U3 V3 AC9 U2 V2 AD8 U1 V1 AC8 M_CLK_A_DDR#0 M_CLK_A_DDR0 DDR_CKE0_DIMMA M_CLK_A_DDR#1 M_CLK_A_DDR1 DDR_CKE1_DIMMA M_CLK_A_DDR#2 M_CLK_A_DDR2 DDR_CKE2_DIMMA M_CLK_A_DDR#3 M_CLK_A_DDR3 DDR_CKE3_DIMMA M7 L9 M9 M10 M8 L7 L8 L10 V5 U5 AD1 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMA# DDR_CS3_DIMMA# M_A_ODT0 M_A_ODT1 M_A_ODT2 M_A_ODT3 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 V10 U6 DDR_A_RAS# U7 DDR_A_WE# U8 DDR_A_CAS# V8 AC6 V9 U9 AC5 AC4 AD6 AC3 AD5 AC2 V6 AC1 AD4 V7 AD3 AD2 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 AP15 AP8 AJ8 AF3 J3 E2 C5 C11 AP14 AP9 AK8 AG3 H3 E3 C6 C12 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 M_CLK_A_DDR#0 M_CLK_A_DDR0 DDR_CKE0_DIMMA M_CLK_A_DDR#1 M_CLK_A_DDR1 DDR_CKE1_DIMMA M_CLK_A_DDR#2 M_CLK_A_DDR2 DDR_CKE2_DIMMA M_CLK_A_DDR#3 M_CLK_A_DDR3 DDR_CKE3_DIMMA DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] [11] DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMA# DDR_CS3_DIMMA# M_A_ODT0 [11] M_A_ODT1 [11] M_A_ODT2 [11] M_A_ODT3 [11] DDR_A_BS0 [11] DDR_A_BS1 [11] DDR_A_BS2 [11] [11] [11] [11] [11] DDR_A_RAS# [11] DDR_A_WE# [11] DDR_A_CAS# [11] DDR_A_MA[0..15] DDR_A_DQS#[0..7] DDR_A_DQS[0..7] JCPU1D DDR_B_D[0..63] [11] [11] [11] AR18 AT18 AM17 AM18 AR17 AT17 AN17 AN18 AT12 AR12 AN12 AM11 AT11 AR11 AM12 AN11 AR5 AR6 AM5 AM6 AT5 AT6 AN5 AN6 AJ4 AK4 AJ1 AJ2 AM1 AN1 AK2 AK1 L2 M2 L4 M4 L1 M1 L5 M5 G7 J8 G8 G9 J7 J9 G10 J10 A8 B8 A9 B9 D8 E8 D9 E9 E15 D15 A15 B15 E14 D14 A14 B14 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 RSVD SB_CKN0 SB_CK0 SB_CKE_0 SB_CKN1 SB_CK1 SB_CKE_1 SB_CKN2 SB_CK2 SB_CKE_2 SB_CKN3 SB_CK3 SB_CKE_3 SB_CS_N_0 SB_CS_N_1 SB_CS_N_2 SB_CS_N_3 SB_ODT_0 SB_ODT_1 SB_ODT_2 SB_ODT_3 SB_BS_0 SB_BS_1 SB_BS_2 VSS SB_RAS SB_WE SB_CAS SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15 SB_DQS_N_0 SB_DQS_N_1 SB_DQS_N_2 SB_DQS_N_3 SB_DQS_N_4 SB_DQS_N_5 SB_DQS_N_6 SB_DQS_N_7 SB_DQS_P_0 SB_DQS_P_1 SB_DQS_P_2 SB_DQS_P_3 SB_DQS_P_4 SB_DQS_P_5 SB_DQS_P_6 SB_DQS_P_7 AG8 @ T3 Y4 M_CLK_B_DDR#0 AA4 M_CLK_B_DDR0 AF10 DDR_CKE0_DIMMB Y3 M_CLK_B_DDR#1 AA3 M_CLK_B_DDR1 AG10 DDR_CKE1_DIMMB Y2 M_CLK_B_DDR#2 AA2 M_CLK_B_DDR2 AG9 DDR_CKE2_DIMMB Y1 M_CLK_B_DDR#3 AA1 M_CLK_B_DDR3 AF9 DDR_CKE3_DIMMB P4 R2 P3 P1 DDR_CS0_DIMMB# DDR_CS1_DIMMB# DDR_CS2_DIMMB# DDR_CS3_DIMMB# R4 R3 R1 P2 R7 P8 AA9 M_B_ODT0 M_B_ODT1 M_B_ODT2 M_B_ODT3 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 R10 R6 DDR_B_RAS# P6 DDR_B_WE# P7 DDR_B_CAS# R8 Y5 Y10 AA5 Y7 AA6 Y6 AA7 Y8 AA10 R9 Y9 AF7 P9 AA8 AG7 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 AP18 AP11 AP5 AJ3 L3 H9 C8 C14 AP17 AP12 AP6 AK3 M3 H8 C9 C15 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 PAD~D M_CLK_B_DDR#0 M_CLK_B_DDR0 DDR_CKE0_DIMMB M_CLK_B_DDR#1 M_CLK_B_DDR1 DDR_CKE1_DIMMB M_CLK_B_DDR#2 M_CLK_B_DDR2 DDR_CKE2_DIMMB M_CLK_B_DDR#3 M_CLK_B_DDR3 DDR_CKE3_DIMMB [12] [12] [12] [12] [12] [12] [12] [12] [12] [12] [12] [12] DDR_CS0_DIMMB# DDR_CS1_DIMMB# DDR_CS2_DIMMB# DDR_CS3_DIMMB# [12] [12] [12] [12] M_B_ODT0 M_B_ODT1 M_B_ODT2 M_B_ODT3 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 [12] [12] [12] [12] [12] [12] [12] C DDR_B_RAS# [12] DDR_B_WE# [12] DDR_B_CAS# [12] DDR_B_MA[0..15] [12] DDR_B_DQS#[0..7] DDR_B_DQS[0..7] [12] [12] B 07/10 Change by HP request CC84 CC85 CC86 INTEL_HASWELL_HASWELL INTEL_HASWELL_HASWELL 2 1 2 4 OF 9 3 OF 9 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1 07/10 Delete by HP request 08/03 Add CC84, CC85, CC86 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 2011/06/29 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 DDRIII Rev 0.5 LA-9241P Sheet Thursday, December 20, 2012 1 6 of 56 5 4 3 2 1 D D COMPENSATION PU FOR eDP +VCCIOA_OUT 2 EDP_COMP 24.9_0402_1% 1 RC77 CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils. Haswell rPGA EDS JCPU1H T28 U28 T30 U30 U29 V29 U31 V31 C T34 U34 U35 V35 U32 T32 U33 V33 P29 R29 N28 P28 P31 R31 N30 P30 DDIB_TXBN_0 DDIB_TXBP_0 DDIB_TXBN_1 DDIB_TXBP_1 DDIB_TXBN_2 DDIB_TXBP_2 DDIB_TXBN_3 DDIB_TXBP_3 eDP EDP_AUXN EDP_AUXP EDP_HPD EDP_RCOMP EDP_DISP_UT IL EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1 FDI_TXN_0 FDI_TXP_0 FDI_TXN_1 FDI_TXP_1 DDIC_TXCN_0 DDIC_TXCP_0 DDIC_TXCN_1 DDIC_TXCP_1 DDIC_TXCN_2 DDIC_TXCP_2 DDIC_TXCN_3 DDIC_TXCP_3 DDID_TXDN_0 DDID_TXDP_0 DDID_TXDN_1 DDID_TXDP_1 DDID_TXDN_2 DDID_TXDP_2 DDID_TXDN_3 DDID_TXDP_3 M27 N27 P27 E24 R27 EDP_CPU_C_AUX# EDP_CPU_C_AUX EDP_HPD EDP_COMP T119@ C126 1 C127 1 P35 R35 N34 P34 P33 R33 N32 P32 EDP_CPU_C_LANE_N0 EDP_CPU_C_LANE_P0 EDP_CPU_C_LANE_N1 EDP_CPU_C_LANE_P1 2 0.1U_0402_25V6 2 0.1U_0402_25V6 EDP_CPU_AUX# EDP_CPU_AUX [36] [36] C PAD C128 C129 C130 C131 1 1 1 1 2 2 2 2 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6 FDI_CTX_PRX_N0 FDI_CTX_PRX_P0 FDI_CTX_PRX_N1 FDI_CTX_PRX_P1 EDP_CPU_LANE_N0 EDP_CPU_LANE_P0 EDP_CPU_LANE_N1 EDP_CPU_LANE_P1 FDI_CTX_PRX_N0 FDI_CTX_PRX_P0 FDI_CTX_PRX_N1 FDI_CTX_PRX_P1 [36] [36] [36] [36] [14] [14] [14] [14] DDI +VCCIO_OUT 8 OF 9 1 INTEL_HASWELL_HASWELL HPD INVERSION FOR EDP 10K_0402_5% RC78 08/07 Change RC78 to 10K 2 B B 1 S 2 G CPU_EDP_HPD# 2 RC79 100K_0402_5% 1 [36] 3 EDP_HPD D QH1 BSS138W-7-F_SOT323-3 SB000002X00 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 2011/06/29 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 CPU-FDI,eDP,DDI Rev 0.5 LA-9241P Thursday, December 20, 2012 Sheet 1 7 of 56 5 4 3 2 1 CFG STRAPS for CPU D 2 D @ RC80 1K_0402_1% 1 CFG2 PEG Static Lane Reversal - CFG2 is for the 16x 1:(Default) Normal Operation; Lane # definition matches socket pin map definition CFG2 0:Lane Reversed Haswell rPGA EDS JCPU1I CFG4 C35 B35 AL25 @ T26 PAD~D @ T28 PAD~D H_CPU_TESTLO 1 2 RSVD_TP RSVD_TP TESTLO RSVD CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 RSVD RSVD NC RSVD RSVD_TP RSVD_TP RSVD_TP VSS VSS VSS VSS CFG_RCOMP CFG16 CFG18 CFG17 CFG19 CFG16 CFG18 CFG17 CFG19 [5] [5] [5] [5] Display Port Presence Strap AR33 G6 AM27 AM26 F5 AM2 K6 CFG4 E18 U10 P10 CFG6 CFG5 B1 A2 AR1 E21 E20 AP27 AR26 AL31 AL32 9 OF 9 2 1 H_CPU_TESTLO 49.9_0402_1% 1 CFG_RCOMP 49.9_0402_1% 1 H_CPU_RSVD 49.9_0402_1% RC84 B 2 RC85 2 RC86 INTEL_HASWELL_HASWELL C 1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port @ RC83 1K_0402_1% CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 AT20 AR20 AP20 AP22 AT22 AN22 AT25 AN23 AR24 AT23 AN20 AP24 AP26 AN25 AN26 AP25 RSVD_TP RSVD FC_G6 RSVD RSVD RSVD RSVD RSVD AT31 AR21 AR23 AP21 AP23 @ RC82 1K_0402_1% [5] [5] [5] [5] [5] [5] [5] [5] [5] [5] [5] [5] [5] [5] [5] [5] CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 W30 W31 W34 RSVD_TP RSVD_TP CFG_RCOMP CFG_16 CFG_18 CFG_17 CFG_19 1 +VCC_CORE RSVD_TP RSVD_TP TESTLO_G26 VSS RSVD RSVD VCC 2 C RSVD_TP RSVD_TP C23 B23 D24 D23 1 @ T16 PAD~D @ T17 PAD~D W29 W28 H_CPU_RSVD G26 W33 AL30 AL29 F25 RSVD_TP RSVD_TP RSVD_TP RSVD_TP 2 A34 A35 @ T15 PAD~D @ T12 PAD~D RSVD_TP RSVD_TP RSVD RC81 1K_0402_1% AT1 AT2 AD10 07/10 Delete RC106 and RC107 CFG[6:5] PCIE Port Bifurcation Straps 11: (Default) x16 - Device 1 functions 1 and 2 disabled 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled B CFG7 2 1 2 @ RC106 1K_0402_1% @ RC87 1K_0402_1% 1 CFG9 PEG DEFER TRAINING 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training 09/21 Reserve CFG9 PD RC106 CFG7 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 2011/06/29 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 CPU-RSVD,CFG Rev 0.5 LA-9241P Thursday, December 20, 2012 Sheet 1 8 of 56 5 4 3 +1.35VS Source 2 1 J4 2 2 2 1 4 2 RUN_ON_CPU1.5VS3 2 6 1 2N7002DWH_SOT363-6 QC5A @ RC92 330K_0402_5% 2 2 SLP_S3 1 [34,49] R6 @ D @ 11/06 Change QC5A.2 and QC5B.5 connection to SLP_S3 +VCC_CORE Haswell rPGA EDS JCPU1E 20K_0402_5% RC88 100K_0402_5% +1.35VS @ K27 L27 T27 V27 RC89 470_0603_5% 1 @ CC39 2 0.1U_0402_25V6 CC38 2 1 0.1U_0402_10V6K @5 CC40 2 1 0.1U_0402_10V6K SLP_S3 AB11 AB2 AB5 AB8 AE11 AE2 AE5 AE8 AH11 K11 N11 N8 T11 T2 T5 T8 W11 W2 W5 W8 09/11 Delete RC93 and connect SLP_S3# to QC5.5 RUN_ON_CPU1.5VS3 RSVD RSVD RSVD RSVD +1.35VS QC5B 2N7002DWH_SOT363-6 4 1 B+ 1 1 JUMP_43X79 SI7326DN-T1-E3_PAK1212-8 QC4 @ 1 2 5 3 3 1 +1.35V [11,12] 10/18 Delete Q80, R461, Q2, RC90. Modify +1.35VS power circuit 12/12 Uninstall QC4,RC92,CC39,RC89,QC5 and RC88. Add J4. 12/13 Install RC88 10/16 Add Q80 N26 K26 AL27 AK27 +VCC_CORE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ RSVD VCC RSVD RSVD 09/11 Change netname to VCCSENSE C VCCSENSE AL35 E17 AN35 A23 F22 W32 AL16 J27 AL13 VR_SVID_ALRT# VR_SVID_CLK VR_SVID_DAT AM28 AM29 AL28 +VCCIO_OUT @ T54 PAD~D +VCCIOA_OUT 07/25 Delete RC96 [47] [47] [47] 2 [5] RC98 150_0402_1% 1 +1.05VS VR_SVID_ALRT# VR_SVID_CLK VR_SVID_DAT AP35 H27 AP34 AT35 AR35 AR32 AL26 AT34 AL22 AT33 AM21 AM25 AM22 AM20 AM24 AL19 AM23 AT32 CPU_PWR_DEBUG @ T50 @ T51 @ T52 @ T53 PAD~D PAD~D PAD~D PAD~D CPU_PWR_DEBUG +VCC_CORE 1 2 [47] VCCSENSE RC101 100_0402_1% B VCC_SENSE +1.35VS VDDQ DECOUPLING VCCSENSE 1 RC104 100_0402_1% 2 2 CC41 + 2 1 @ + 2 CC87 330U_D2_2V_Y 2 1 330U_D2_2V_Y 2 1 CC51 10U_0603_6.3V6M 2 1 CC50 10U_0603_6.3V6M 2 1 CC49 10U_0603_6.3V6M 2 1 CC48 10U_0603_6.3V6M 2 1 CC47 10U_0603_6.3V6M 2 1 CC46 10U_0603_6.3V6M 2 1 CC45 10U_0603_6.3V6M 2 09/11 Delete RC102 and RC103 1 CC44 10U_0603_6.3V6M VSSSENSE 1 CC43 10U_0603_6.3V6M 1 CC42 10U_0603_6.3V6M VSSSENSE VIDALERT VIDSCLK VIDSOUT VSS PWR_DEBUG VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP VSS VSS VSS VSS VSS # 04/02 change Pin name by Intel update VSS VSS VSS VSS VSS VSS +VCC_CORE CAD Note: RC101 SHOULD BE PLACED CLOSE TO CPU CAD Note: RC104 SHOULD BE PLACED CLOSE TO CPU [10,47] VCC_SENSE RSVD VCCIO_OUT FC_A23 VCOMP_OUT RSVD # 04/02 change Pin name RSVD by Intel update RSVD RSVD Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC INTEL_HASWELL_HASWELL AA26 AA28 AA34 AA30 AA32 AB26 AB29 AB25 AB27 AB28 AB30 AB31 AB33 AB34 AB32 AC26 AB35 AC28 AD25 AC30 AD28 AC32 AD31 AC34 AD34 AD26 AD27 AD29 AD30 AD32 AD33 AD35 AE26 AE32 AE28 AE30 AG28 AG34 AE34 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AG26 AH26 AH29 AG30 AG32 AH32 AH35 AH25 AH27 AH28 AH30 AH31 AH33 AH34 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 G25 H25 J25 K25 L25 M25 N25 P25 R25 T25 D C B U25 U26 V25 V26 W26 W27 5 OF 9 08/06 Reserve CC87 2 1 2 1 2 1 2 1 2 1 2 CH11 22U_0805_6.3V6M 1 CH10 22U_0805_6.3V6M 2 CH9 22U_0805_6.3V6M 1 CH8 22U_0805_6.3V6M 2 CH7 22U_0805_6.3V6M 1 CH6 22U_0805_6.3V6M 2 CH5 22U_0805_6.3V6M 1 CH4 22U_0805_6.3V6M 2 CH3 22U_0805_6.3V6M 1 CH2 22U_0805_6.3V6M 2 CH1 22U_0805_6.3V6M 1 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 2011/06/29 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 CPU- PWR Rev 0.5 LA-9241P Sheet Thursday, December 20, 2012 1 9 of 56 5 4 3 Haswell rPGA EDS 2 1 Haswell rPGA EDS JCPU1F JCPU1G D D A10 A13 A16 A19 A22 A25 A27 A29 A3 A31 A33 A4 A7 AA11 AA25 AA27 AA31 AA29 AB1 AB10 AA33 AA35 AB3 AC25 AC27 AB4 AB6 AB7 AB9 AC11 AD11 AC29 AC31 AC33 AC35 AD7 AE1 AE10 AE25 AE29 AE3 AE27 AE35 AE4 AE6 AE7 AE9 AF11 AF6 AF8 AG11 AG25 AE31 AG31 AE33 AG6 AH1 AH10 AH2 AG27 AG29 AH3 AG33 AG35 AH4 AH5 AH6 AH7 AH8 AH9 AJ11 AJ5 AK11 AK25 AK26 AK28 AK29 AK30 AK32 E19 C B VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS INTEL_HASWELL_HASWELL AK34 AK5 AL1 AL10 AL11 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 E22 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AM10 AM13 AM16 AM19 E25 AM32 AM4 AM7 AN10 AN13 AN16 AN19 AN2 AN21 AN24 AN27 AN30 AN34 AN4 AN7 AP1 AP10 AP13 AP16 AP19 AP4 AP7 W25 AR10 AR13 AR16 AR19 AR2 AR22 AR25 AR28 AR31 AR34 AR4 AR7 AT10 AT13 AT16 AT19 AT21 AT24 AT27 AT3 AT30 AT4 AT7 B10 B13 B16 B19 B2 B22 B34 B4 B7 C1 C10 C13 C16 C19 C2 C22 C24 C26 C28 C30 C32 C34 C4 C7 D10 D13 D16 D19 D22 D25 D27 D29 D31 D33 D35 D4 D7 E1 E10 E13 E16 E4 E7 F10 F11 F12 F14 F15 F17 F18 F20 F21 F23 F24 F26 F28 F30 F32 F34 F4 F6 F7 F8 F9 G1 G11 G2 G27 G29 G3 G31 G33 G35 G4 G5 H10 H26 H6 H7 J11 J26 J28 J30 J32 J34 J6 K1 6 OF 9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_SENSE RSVD K10 K2 K29 K3 K31 K33 K35 K4 K5 K7 K8 K9 L11 L26 L6 M11 M26 M28 M30 M32 M34 M6 N1 N10 N2 N29 N3 N31 N33 N35 N4 N5 N6 N7 N9 P11 P26 P5 R11 R26 R28 R30 R32 R34 R5 T1 T10 T29 T3 T31 T33 T35 T4 T6 T7 T9 U11 U27 V11 V28 V30 V32 V34 W1 W10 W3 W35 W4 W6 W7 W9 Y11 H11 AL24 F19 T26 AK35 AK33 C B VSSSENSE [47,9] 09/11 Change netname to VSSSENSE INTEL_HASWELL_HASWELL 7 OF 9 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 2011/06/29 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 CPU-VSS Rev 0.5 LA-9241P Thursday, December 20, 2012 Sheet 1 10 of 56 5 4 JDIMM1 H=4mm TOP +1.35V +1.35V 07/17 Rename JP3 to JDIMM1 2 2 1 2 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 Layout Note: Place near JDIMM1 DDR_A_D24 DDR_A_D25 +1.35V 1 2 1 2 DDR_CKE0_DIMMA [6] DDR_A_BS2 DDR_A_BS2 DDR_A_MA3 DDR_A_MA1 +1.35V 1 2 1 2 1 @ 2 CD15 10U_0603_6.3V6M 2 CD14 10U_0603_6.3V6M 1 CD13 10U_0603_6.3V6M 2 CD12 10U_0603_6.3V6M 1 CD11 10U_0603_6.3V6M 2 CD10 10U_0603_6.3V6M CD9 10U_0603_6.3V6M 1 M_CLK_A_DDR0 M_CLK_A_DDR#0 [6] DDR_A_BS0 DDR_A_MA10 DDR_A_BS0 [6] [6] DDR_A_WE# DDR_A_CAS# DDR_A_WE# DDR_A_CAS# 1 + M_CLK_A_DDR0 M_CLK_A_DDR#0 [6] [6] CD16 330U_B2_2.5VM_R15M 2 DDR_A_MA13 DDR_CS1_DIMMA# DDR_A_D40 DDR_A_D41 Layout Note: Place near JDIMM1.203,204 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 +0.675VS DDR_A_DQS#6 DDR_A_DQS6 2 CD24 1U_0402_6.3V6K 2 CD23 1U_0402_6.3V6K CD22 1U_0402_6.3V6K CD21 1U_0402_6.3V6K 2 1 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 +3VS DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 DDR3_DRAMRST#_R DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D20 DDR_A_D21 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D26 DDR_A_D27 205 G1 G2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 DDR_A_D30 DDR_A_D31 DDR_CKE1_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMA DDR_CKE2_DIMMA DDR_A_BS2 [6] DDR_A_MA15 DDR_A_MA14 DDR_A_MA12 DDR_A_MA9 DDR_A_MA11 DDR_A_MA7 DDR_A_MA8 DDR_A_MA5 DDR_A_MA6 DDR_A_MA4 DDR_A_MA3 DDR_A_MA1 DDR_A_MA2 DDR_A_MA0 [6] [6] M_CLK_A_DDR1 M_CLK_A_DDR#1 M_CLK_A_DDR1 M_CLK_A_DDR#1 DDR_A_BS1 DDR_A_RAS# DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_A_ODT0 DDR_CS0_DIMMA# M_A_ODT0 [6] M_A_ODT1 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 M_A_ODT1 2 M_CLK_A_DDR2 M_CLK_A_DDR#2 DDR_A_MA10 DDR_A_BS0 [6] [6] DDR_A_WE# DDR_A_CAS# [6] [6] [6] 1 M_CLK_A_DDR2 M_CLK_A_DDR#2 [6] [6] DDR_CS3_DIMMA# DDR_A_MA13 DDR_CS3_DIMMA# +DIMM_VREF_CA 1 2 1 RD26 DDR_A_D32 DDR_A_D33 2 +1.35V 1K_0402_1% DDR_A_DQS#4 DDR_A_DQS4 1 3 +SM_VREF_CA DDR_A_D34 DDR_A_D35 QD2 2N7002KW_SOT323-3 DDR_A_D40 DDR_A_D41 RUN_ON_CPU1.5VS3 DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D42 DDR_A_D43 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D52 DDR_A_D53 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D58 DDR_A_D59 +3VS DDR_A_D62 DDR_A_D63 DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK 1 [12,13,16,28,38,5] [12,13,16,28,38,5] +0.675VS 2 206 FOX_AS0A626-U4RN-7F CONN@ 08/07 Change JDIMM1 footprint 1 2 CD26 2.2U_0402_6.3V6M +0.675VS CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 CD25 0.1U_0402_16V4Z 2 CD28 2.2U_0402_6.3V6M 2 CD27 0.1U_0402_16V4Z 1 1 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 2 DDR_A_D12 DDR_A_D13 CD20 0.1U_0402_16V4Z DDR_A_D34 DDR_A_D35 B 2 2 DDR_A_D6 DDR_A_D7 CD19 2.2U_0402_6.3V6M DDR_A_DQS#4 DDR_A_DQS4 1 [5] 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 +0.675VS 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 205 G1 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 G2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 DDR3_DRAMRST#_R DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 DDR_CKE3_DIMMA [6] C DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_A_DDR3 M_CLK_A_DDR#3 M_CLK_A_DDR3 M_CLK_A_DDR#3 [6] [6] DDR_A_BS1 DDR_A_RAS# DDR_CS2_DIMMA# M_A_ODT2 DDR_CS2_DIMMA# M_A_ODT2 [6] M_A_ODT3 M_A_ODT3 DDR_A_D36 DDR_A_D37 1 DDR_A_D38 DDR_A_D39 2 [6] +DIMM_VREF_CA [6] 1 2 DDR_A_D44 DDR_A_D45 B DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK +0.675VS 206 Standard Reverse Issued Date A Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 Deciphered Date 2011/06/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 DDR_CKE3_DIMMA DDR_A_MA15 DDR_A_MA14 LCN_DAN06-K4406-0102 CONN@ A 5 D DDR_A_DQS#0 DDR_A_DQS0 CD18 0.1U_0402_16V4Z DDR_CS1_DIMMA# DDR_A_D32 DDR_A_D33 1 CPU_DRAM_RST# 1 DDR_A_D0 DDR_A_D1 CD17 2.2U_0402_6.3V6M [6] SGA00004400 1 2 33_0402_5% 1 All VREF traces should have 10 mil trace width 08/03 Change RD6 to 33 ohms RD25 1K_0402_1% 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDR_CKE0_DIMMA DDR_A_MA8 DDR_A_MA5 2 1 +1.35V JDIMM3 [6] [6] DDR_A_MA12 DDR_A_MA9 1 RD6 DDR3_DRAMRST#_R S 2 CD8 1U_0402_6.3V6K 1 CD7 1U_0402_6.3V6K 2 CD6 1U_0402_6.3V6K 1 CD5 1U_0402_6.3V6K C DDR_A_D26 DDR_A_D27 [12] D DDR_A_MA[0..15] DDR_A_DQS#0 DDR_A_DQS0 2 G DDR_A_DQS#[0..7] [6] DDR_A_D4 DDR_A_D5 1 [6] VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 DDR_A_DQS[0..7] VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 2 CD4 0.1U_0402_16V4Z 2 CD3 2.2U_0402_6.3V6M 1 RD23 1K_0402_1% 1 +1.35V DDR_A_D8 DDR_A_D9 DDR_A_D[0..63] +1.35V 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 CD2 0.1U_0402_16V4Z D +1.35V 2 1K_0402_1% All VREF traces should have 10 mil trace width [6] 1 +DIMM_A_DQ JDIMM1 1 RD24 CD1 2.2U_0402_6.3V6M 1 RD2 1K_0402_5% QD1 2N7002KW_SOT323-3 3 S D +DIMM_A_DQ 07/10 Change by HP request G +DIMM01_VREF_DQ 1 07/10 Change by HP request RUN_ON_CPU1.5VS3 07/10 Change by HP request [6] 2 JDIMM1 H=5.2mm BOT Populate RD1, De-Populate RD7 for Intel DDR3 VREFDQ multiple methods M1 Populate RD7, De-Populate RD1 for Intel DDR3 VREFDQ multiple methods M3 [12,9] 3 3 2 Title DDRIII DIMM1&2 Size Document Number Custom Date: 1 Rev 0.5 LA-9241P Thursday, December 20, 2012 Sheet 11 of 56 4 JDIMM2 H=9.2mm TOP 07/10 Change by HP request [11,9] QD3 2N7002KW_SOT323-3 +1.35V +1.35V +1.35V 2 1K_0402_1% DDR_B_D8 DDR_B_D9 [6] DDR_B_D[0..63] [6] DDR_B_DQS[0..7] [6] [6] DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11 DDR_B_DQS#[0..7] DDR_B_MA[0..15] DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 Layout Note: Place near JDIMM2 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 +1.35V 2 1 @ 2 [6] DDR_CKE0_DIMMB [6] DDR_B_BS2 DDR_B_BS2 DDR_B_MA8 DDR_B_MA5 11/06 Add C511 by rf request DDR_B_MA3 DDR_B_MA1 M_CLK_B_DDR0 M_CLK_B_DDR#0 [6] DDR_B_BS0 DDR_B_MA10 DDR_B_BS0 [6] [6] DDR_B_WE# DDR_B_CAS# DDR_B_WE# DDR_B_CAS# 1 + 2 CD44 330U_B2_2.5VM_R15M [6] M_CLK_B_DDR0 M_CLK_B_DDR#0 [6] [6] DDR_CS1_DIMMB# DDR_B_MA13 DDR_CS1_DIMMB# DDR_B_D34 DDR_B_D35 Layout Note: Place near JDIMM2.203,204 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49 +0.675VS 2 1 2 DDR_B_DQS#6 DDR_B_DQS6 CD52 1U_0402_6.3V6K 1 CD51 1U_0402_6.3V6K 2 CD50 1U_0402_6.3V6K CD49 1U_0402_6.3V6K 2 1 1 DDR_B_D6 DDR_B_D7 2 1 2 DDR_B_D12 DDR_B_D13 DDR3_DRAMRST#_R DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 DDR3_DRAMRST#_R DDR_B_D10 DDR_B_D11 [11] DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D20 DDR_B_D21 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D26 DDR_B_D27 DDR_B_D30 DDR_B_D31 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 2 +0.675VS 205 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 G1 G2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 [6] DDR_CKE1_DIMMB DDR_CKE1_DIMMB DDR_CKE2_DIMMB [6] DDR_CKE2_DIMMB DDR_B_MA12 DDR_B_MA9 DDR_B_MA15 DDR_B_MA14 DDR_B_MA8 DDR_B_MA5 DDR_B_MA11 DDR_B_MA7 DDR_B_MA3 DDR_B_MA1 DDR_B_MA6 DDR_B_MA4 [6] [6] DDR_B_MA2 DDR_B_MA0 M_CLK_B_DDR1 M_CLK_B_DDR#1 M_CLK_B_DDR1 M_CLK_B_DDR#1 DDR_B_BS1 DDR_B_RAS# DDR_B_BS1 DDR_B_RAS# DDR_CS0_DIMMB# M_B_ODT0 DDR_CS0_DIMMB# M_B_ODT0 [6] M_B_ODT1 M_B_ODT1 DDR_B_D36 DDR_B_D37 1 DDR_B_D38 DDR_B_D39 2 [6] [6] DDR_B_WE# DDR_B_CAS# [6] [6] [6] [6] DDR_CS3_DIMMB# +DIMM_VREF_CA [6] 1 2 M_CLK_B_DDR2 M_CLK_B_DDR#2 DDR_B_MA10 DDR_B_BS0 DDR_B_MA13 DDR_CS3_DIMMB# DDR_B_D32 DDR_B_D33 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35 DDR_B_D40 DDR_B_D41 DDR_B_D44 DDR_B_D45 DDR_B_D42 DDR_B_D43 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D48 DDR_B_D49 DDR_B_D46 DDR_B_D47 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D52 DDR_B_D53 DDR_B_D50 DDR_B_D51 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D58 DDR_B_D59 +3VS DDR_B_D62 DDR_B_D63 1 DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK [11,13,16,28,38,5] [11,13,16,28,38,5] +0.675VS 2 206 TYCO_2-2013311-4 CONN@ 1 2 +0.675VS 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT GND1 BOSS1 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT GND2 BOSS2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDR_B_D4 DDR_B_D5 DDR_B_DQS#0 DDR_B_DQS0 D DDR_B_D6 DDR_B_D7 DDR_B_D12 DDR_B_D13 DDR3_DRAMRST#_R DDR_B_D14 DDR_B_D15 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_CKE3_DIMMB DDR_CKE3_DIMMB [6] DDR_B_MA15 DDR_B_MA14 C DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_B_DDR3 M_CLK_B_DDR#3 M_CLK_B_DDR3 M_CLK_B_DDR#3 [6] [6] DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB# M_B_ODT2 DDR_CS2_DIMMB# M_B_ODT2 [6] M_B_ODT3 M_B_ODT3 DDR_B_D36 DDR_B_D37 1 DDR_B_D38 DDR_B_D39 2 [6] +DIMM_VREF_CA [6] 1 2 DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 B DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK +0.675VS 206 208 LCN_DAN06-K4406-0103 CONN@ Reverse 08/07 Change JDIMM2 footprint A M_CLK_B_DDR2 M_CLK_B_DDR#2 CD54 2.2U_0402_6.3V6M 1 CD56 2.2U_0402_6.3V6M 2 CD55 0.1U_0402_16V4Z 1 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 CD53 0.1U_0402_16V4Z DDR_B_D58 DDR_B_D59 +3VS 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 CD48 0.1U_0402_16V4Z DDR_B_DQS#4 DDR_B_DQS4 1 All VREF traces should have 10 mil trace width CD47 2.2U_0402_6.3V6M DDR_B_D32 DDR_B_D33 B DDR_B_DQS#0 DDR_B_DQS0 RD28 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS CD46 0.1U_0402_16V4Z 2 DDR_B_D4 DDR_B_D5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 CD45 2.2U_0402_6.3V6M 2 1 @ CD43 10U_0603_6.3V6M 2 1 CD42 10U_0603_6.3V6M 2 1 CD41 10U_0603_6.3V6M 2 1 CD40 10U_0603_6.3V6M 2 1 CD39 10U_0603_6.3V6M 1 CD38 10U_0603_6.3V6M CD37 10U_0603_6.3V6M 2 DDR_CKE0_DIMMB DDR_B_MA12 DDR_B_MA9 +1.35V 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDR_B_D0 DDR_B_D1 DDR_B_BS2 C511 100P_0402_50V8J 2 1 CD36 1U_0402_6.3V6K 2 1 CD35 1U_0402_6.3V6K 2 1 CD34 1U_0402_6.3V6K 1 CD33 1U_0402_6.3V6K C VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 CD30 0.1U_0402_16V4Z 2 DDR_B_D2 DDR_B_D3 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 1K_0402_1% 2 1 CD32 0.1U_0402_16V4Z All VREF traces should have 10 mil trace width CD31 2.2U_0402_6.3V6M 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 DDR_B_D0 DDR_B_D1 +1.35V JDIMM4 1 RD27 JDIMM2 D 4/16 change by HP requirement +DIMM_B_DQ D S +DIMM23_VREF_DQ 1 1 JDIMM4 H=5.2mm BOT 07/10 Change by HP request 3 +DIMM_B_DQ +1.35V 2 RUN_ON_CPU1.5VS3 G Populate RD4, De-Populate RD8 for Intel DDR3 VREFDQ multiple methods M1 Populate RD8, De-Populate RD4 for Intel DDR3 VREFDQ multiple methods M3 3 2 5 A Reverse Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 Deciphered Date 2011/06/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title DDRIII DIMM3&4 Size Document Number Custom Date: 1 Rev 0.5 LA-9241P Thursday, December 20, 2012 Sheet 12 of 56 5 4 3 2 1 2 RH6 330K_0402_5% 1 +RTCVCC 07/09 Delete by HP request. 07/09 Delete by HP request. PCH_INTVRMEN D D INTVRMEN - INTEGRATED SUS 1.05V VRM ENABLE High - Enable Internal VRs Low - Enable External VRs 1 RH28 QH11B 1 1 1 CH13 2 2 2 CH14 18P_0402_50V8J +3VS 2 C LPT_PCH_M_EDS UH1A REV = 5 11/01 Change YH1 to small package RH34 1 2 20K_0402_5% RH35 1 2 1M_0402_5% [25] RH36 1 CMOS_CLR1 Clear CMOS Open Keep CMOS 2 TPM setting Clear ME RTC Registers Open Keep ME RTC Registers 1 1 CH15 SHORT PADS 2 1U_0402_6.3V6K A8 2 G10 0_0402_5% PCH_RTCRST# 1 @ CMOS1 1 CH16 B9 PCH_INTVRMEN PCH_RTCRST# SHORT PADS 2 1U_0402_6.3V6K HDA_SPKR [26] HDA_SDI0 D9 B25 HDA_BIT_CLK 2 [26] @ ME1 Shunt 2 SRTCRST# HDA_SYNC A22 HDA_SPKR AL10 HDA_RST# C24 HDA_SDI0 L22 K22 CMOS place near DIMM G22 F22 [39] +3V_PCH HDA_SYNC Isolation Circuit HDD_HALTLED [33,36] +5VS A24 HDA_SDOUT 07/06 Follow HP's GPIO table B ISO_PREP# HDD_HALTLED B17 ISO_PREP# C22 SATA_RXN_0 SATA_RXP_0 RTCX1 RTCX2 SATA_TXN_0 SATA_TXP_0 SRTCRST# SATA_RXN_1 SATA_RXP_1 INTRUDER# INTVRMEN SATA_TXN_1 SATA_TXP_1 RTCRST# SATA_RXN_2 SATA_RXP_2 HDA_BCLK SATA_TXN_2 SATA_TXP_2 HDA_SYNC SPKR SATA_RXN_3 SATA_RXP_3 HDA_RST# SATA_TXN_3 SATA_TXP_3 AZALIA ME_CLR1 1 2 2 20K_0402_5% [14] 1 B4 INTRUDER# 1 RH230 WWAN_DET# CMOS setting Shunt B5 PCH_RTCX2 RTC +RTCVCC PCH_RTCX1 SATA 08/03 RH33.1 connection to GND HDA_SDI0 HDA_SDI1 SATA_RXN4/PERN1 SATA_RXP4/PERP1 HDA_SDI2 HDA_SDI3 SATA_TXN4/PETN1 SATA_TXP4/PETP1 HDA_SDO SATA_RXN5/PERN2 SATA_RXP5/PERP2 DOCKEN#/GPIO33 HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2 SATA_TXP5/PETP2 G 2 SATA_RCOMP QH2 3 HDA_SYNC_R 1 SATALED# HDA_SYNC D S RH43 1M_0402_5% RH39 2 @ 1 51_0402_1% PCH_JTAG_TCK AB3 RH40 1 @ PCH_JTAG_TMS AD1 RH41 1 @ PCH_JTAG_TDI AE2 RH44 1 @ 2 200_0402_5% 2 200_0402_5% 2 200_0402_5% PCH_JTAG_TDO AD3 1 1 1 2 RH45 PCH_TP25 0_0402_5% F8 C26 AB6 SATA0GP/GPIO21 JTAG_TMS SATA1GP/GPIO19 JTAG_TDI JTAG_TDO TP9 TP25 TP8 +3VDS [26] 1 RH233 3 W=20mils +BATT_D 1 1 HDA_SYNC_AUDIO 2 RH51 DAN202U_SC70 W=20mils 1K_0402_5% W=20mils 1 2 3 4 [26] HDA_SDOUT_AUDIO [26] HDA_RST_AUDIO# [26] HDA_BITCLK_AUDIO 1 2 G1 G2 ACES_50271-00201-001 CONN@ 08/07 Change JBATT1 footprint 1 2 @ CH17 27P_0402_50V8J 1U_0603_10V4Z 2 Place near PCH 4 3 2 1 JBATT1 2 W=20mils CH102 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 AV10 AW10 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 BB9 BD9 SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 AY13 AW13 SATA_PTX_DRX_N2 SATA_PTX_DRX_P2 BC12 BE12 SATA_PRX_DTX_N3 SATA_PRX_DTX_P3 AR13 AT13 SATA_PTX_DRX_N3 SATA_PTX_DRX_P3 [23] [23] SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 [23] [23] SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 [23] [23] SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 [23] [23] SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 [33] [33] SATA_PTX_DRX_N2 SATA_PTX_DRX_P2 [33] [33] SATA_PRX_DTX_N3 SATA_PRX_DTX_P3 [33] [33] SATA_PTX_DRX_N3 SATA_PTX_DRX_P3 [33] [33] SATA_PRX_DTX_N5 SATA_PRX_DTX_P5 [23] [23] ODD DOCK_SATA5 DOCK_SATA3 BD13 BB13 AV15 AW15 B BC14 BE14 SATA_PRX_DTX_N5 SATA_PRX_DTX_P5 AP15 AR15 SATA_PTX_DRX_N5 SATA_PTX_DRX_P5 AY5 SATA_COMP AP3 SATA_ACT# AT1 SG_IN AU2 FN9 BD4 SATA_IREF SATA_PTX_DRX_N5 SATA_PTX_DRX_P5 R463 1 mSATA +3VS [23] [23] 2 10K_0402_5% 10K_0402_5% R7 +3VS SATA_ACT# [33,39] SG_IN [22] 1 RH42 PAD~D T72 @ 2 +1.5VS 0_0402_5% UMA@ BA2 BB2 RP6 2 10K_0402_5% TP20 [14,25,28,29,30,35,37,39,5] 1 OF 11 S Q70 2N7002KW_SOT323-3 +1.5VS HDA_SYNC_R 33_0402_5% HDA_SDOUT HDA_RST# HDA_BIT_CLK 1 2 RH49 A CAD note: Place the resistor within 500 mils of the PCH. Avoid routing next to clock pins. 33_8P4R_5% 10/25 Delete RH50, RH52, RH53. Add RP6 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 Deciphered Date 2011/06/29 Title Date: 4 D 2 G PLT_RST# SATA Impedance Compensation SATA_COMP 7.5K_0402_1% 5 6 7 8 10K_0402_5% R8 RH237 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 HDD +BATT1.1 2 1 BC10 BE10 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 +3VS D40 A SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 TP22 LYNXPOINT_BGA695 +RTCVCC SATA_IREF SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 AW8 AY8 2 2 2 @ RH48 100_0402_1% @ RH47 100_0402_1% @ RH46 100_0402_1% 1 1 09/21 Non-install RH39, RH40, RH41, RH44, RH48, RH47, RH46 JTAG_TCK JTAG 2 SB000002X00 BSS138W-7-F_SOT323-3 BC8 BE8 1 HDD_HALTLED 100K_0402_5% 2 32.768KHZ_12.5PF_Q13FC1350000500 2 2 @ LOW = DESABLED (DEFAULT) HIGH = ENABLED RH38 10K_0402_5% 1 1 RH33 RH37 10K_0402_5% 2 18P_0402_50V8J FLASH DESCRIPTOR SECURITY OVERRIDE C PCH_RTCX2 YH1 D S D S 2 1 1 6 4 3 HDA_SDOUT 2.2K_0402_5% MESS84DW-G_SC88-6 MESS84DW-G_SC88-6 09/03 Instal RH31 09/19 Change QH11 to P MOS, change RH30 to 2.2K ohms RH30 DISABLED WHEN LOW (DEFAULT) ENABLED WHEN HIGH 2 10M_0402_5% 1 G G QH11A 3 +3V_PCH NO REBOOT STRAP 1 HDA_SPKR 10K_0402_5% DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK PCH_RTCX1 5 2 @ [11,12,16,28,38,5] [11,12,16,28,38,5] 07/09 Change by HP request. 10/26 Swap QH11A.2 and QH11B.5 connection PLT_RST# BAT_GRNLED# 2 1 RH29 [30,39] 1 +3VS 3 2 PCH-RTC,HDA,SATA,XDP Rev 0.5 LA-9241P Thursday, December 20, 2012 1 Sheet 13 of 56 5 4 3 2 1 +3VDS 07/23 Connection RH55.2 to +RTCVCC JME1 2 RH64 1 RH72 1 RH75 [5] SUS_PWR_ACK 10K_0402_5% PCH_PCIE_WAKE# 10K_0402_5% 2 PCH_RI# 10K_0402_5% 1 XDP_DBRESET# 2 RH54 SYS_RESET# 0_0402_5% PCH_DPWROK 1 RH67 2 [13] PM_RSMRST# 0_0402_5% PCH_RTCRST# PCH_RTCRST# ON/OFFBTN# 2 BATLOW# 10K_0402_5% 10/26 change RH75.2 connection to BATLOW# SYS_RESET# 07/20 Add ME debug circuit 1 2 RH78 RP7 16 15 DSWODVREN 08/10 Add RH245 10/12 Delete RH245. Add UH6, CH116 10/12 Delete VCC1_PWRGD connection to UH6.1 and 2. Then add R613 between +3VDS and UH6 pin 1,2. change UH6.5 pin connection to +3VDS 10/18 install R613, CH116 and UH6. Uninstall RH67 10/18 Uninstall R613, CH116 and UH6. Install RH68 12/12 Delete UH6, R613 and CH116 AP17 AV20 DGPU_PWR_EN DGPU_HOLD_RST# ODD_DA# 10/25 Delete RH66, RH69, RH71. Add RP8 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 [4] [4] DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 [4] [4] DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 AY22 AP20 [4] [4] DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 AR17 AW20 [4] [4] DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 BD21 BE20 [4] [4] DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 BD17 BE18 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 BB21 BC20 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 BB17 BC18 DMI_IREF 0_0402_5% BE16 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 +1.5VS 1 2 RH88 AW17 +1.5VS 1 2 RH90 AY17 DMI_RCOMP 7.5K_0402_1% 10/16 Delete R230 [31] SUSACK# [30,31] B [5] AD7 F10 PCH_PWROK_R AB7 PM_APWROK H3 PM_DRAM_PWRGD [30] [30] [30,35] [30] J2 PM_RSMRST# SUS_PWR_ACK [30,5] ON/OFFBTN# AC_PRES_OUT BATLOW# R6 AM1 PM_PWROK PCH_PWROK_R 1 RH97 ON/OFFBTN# 2 ME_SUS_PWR_ACK_R 0_0402_5% J4 K1 E6 AC_PRES_OUT BATLOW# 10/26 change PCH.K7 connection to BATLOW# PCH_RI# @ T90 11/06 Change PCH.D2 pin connection to DDR3_SET DDR3_SET [45] DDR3_SET K7 N4 AB10 PAD~D FDI_RXN_1 FDI_RXP_0 FDI FDI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI TP16 DMI_TXN_0 DMI_TXN_1 TP5 TP15 DMI_TXN_2 DMI_TXN_3 TP10 DMI_TXP_0 DMI_TXP_1 FDI_CSYNC FDI_INT DMI_TXP_2 DMI_TXP_3 FDI_IREF DMI_IREF TP17 TP12 TP13 TP7 FDI_RCOMP AJ35 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 [7] AL35 FDI_CTX_PRX_N1 FDI_CTX_PRX_N1 [7] D RH62 8 7 6 5 AJ36 FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 [7] AL36 FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 [7] AY45 AV45 AW44 FDI_CSYNC AL40 FDI_INT AT45 FDI_CSYNC FDI_INT 1 FDI_IREF RH86 2 [4] [4] [36] PCH_CRT_BLU [36] PCH_CRT_GRN [36] PCH_CRT_RED [36] PCH_CRT_DDC_CLK [36] PCH_CRT_DDC_DAT [36] PCH_CRT_HSYNC [36] PCH_CRT_VSYNC D2 PCH_CRT_BLU T45 PCH_CRT_GRN U44 PCH_CRT_RED V45 PCH_CRT_DDC_CLK M43 SYS_RESET# DSWVRMEN System Power Management DPWROK SYS_PWROK WAKE# PWROK CLKRUN# APWROK SUS_STAT#/GPIO61 DRAMPWROK SUSCLK/GPIO62 RSMRST# SLP_S5#/GPIO63 SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# PWRBTN# SLP_S3# ACPRESENT/GPIO31 SLP_A# BATLOW#/GPIO72 SLP_SUS# RI# PMSYNCH TP21 SLP_LAN# M45 PCH_CRT_DDC_DAT 1 2 N42 1 2 N44 HSYNC 20_0402_1% VSYNC 20_0402_1% 2 CRT_IREF 649_0402_1% RH84 RH85 1 +1.5VS 0_0402_5% RH87 U40 AU42 U39 AR44 2 FDI_RCOMP 7.5K_0402_1% 1 RH89 C8 DSWODVREN L13 PCH_DPWROK K3 PCH_PCIE_WAKE# BKL_PWM_PCH N36 [35] BKL_PWM_PCH [35] PANEL_BKEN_PCH +1.5VS AN7 PM_CLKRUN# U7 BT_OFF Y6 SUSCLK_KBC PCH_PCIE_WAKE# K36 Y7 SLP_S5# T85 SLP_S4# T86 PAD~D @ SLP_S4# [45] H1 SLP_S3# F3 SIO_SLP_A# F1 SIO_SLP_SUS# AY3 H_PM_SYNC G5 SLP_LAN#_R RH247 SLP_WLAN#/GPIO29 PAD~D@ SLP_S3# 1 [35] [30] C6 SLP_LAN# DGPU_HOLD_RST# [35,36] DGPU_SELECT# [15,35] DGPU_PWR_EN +3VS RH147 09/20 Change to +3VS [22] Camera_ON [30,31,34,45] SIO_SLP_A# [30,31,46] T88 PAD~D @ SIO_SLP_SUS# T89 PAD~D @ H_PM_SYNC [5] 2 SLP_LAN# 10K_0402_5% 10/25 Add R247 ENVDD_PCH [25] PM_CLKRUN# [28,30,32] 10/26 change PCH.U7 connection to BT_OFF BT_OFF [25] SUSCLK_KBC 1 2 2 1 2 1 2 1 2 1 2 1 TBT_RR_GPIO# 10K_0402_5% 2 1 RH74 RH76 RH77 RH80 RH82 RH83 RH244 [39] ENVDD_PCH G36 PCI_PIRQA# H20 PCI_PIRQB# L20 PCI_PIRQC# K17 PCI_PIRQD# M20 DGPU_HOLD_RST# A12 DGPU_SELECT# B13 C12 DGPU_PWR_EN 1 2 C10 PCH_GPIO51 100K_0402_5% Camera_ON A10 TBT_RR_GPIO# TBT_RR_GPIO# 07/18 Delete PCH_GPIO55 PD RH186. 07/23 Add CR_SX_WARN# off page symbol 10/23 Change net name to TBT_RR_GPIO# AL6 REV = 5 VGA_BLUE DDPB_CTRLCLK VGA_GREEN DDPB_CTRLDATA VGA_RED DDPC_CTRLCLK VGA_DDC_CLK DDPC_CTRLDATA VGA_DDC_DATA DDPD_CTRLCLK VGA_HSYNC DDPD_CTRLDATA VGA_VSYNC DDPB_AUXN DAC_IREF DDPC_AUXN VGA_IRTN AU44 DMI_RCOMP SUSACK# LPT_PCH_M_EV UH1E AV43 AL39 LOW = A16 SWAP OVERRIDE HIGH = DEFAULT NMI_SMI_DBG# 100K_0402_5% PCH_CRT_DDC_CLK 2.2K_0402_5% PCH_CRT_DDC_DAT 2.2K_0402_5% DGPU_SELECT# 10K_0402_5% Camera_ON 10K_0402_5% ACCEL_INT_R# 8.2K_0402_5% 07/23 Add CR_SX_WARN# PU RH244 10/23 Change netname to TBT_RR_GPIO# [35] SYS_RESET# 09/11 Delete RH92, RH93, RH221, RH94, RH95 [30,5] FDI_RXN_0 DMI_RXN_2 DMI_RXN_3 STP_A16OVR EDP_BKLTCTL EDP_BKLTEN DDPD_AUXN DDPB_AUXP LVDS AV17 HIGH = ENABLED (DEFAULT) LOW = DISABLED REV = 5 DMI_RXN_0 DMI_RXN_1 DMI_RXP_0 DMI_RXP_1 A16 SWAP OVERRIDE STRAP CRT [4] [4] LPT_PCH_M_EDS DSWODVREN - ON DIE DSW VR ENABLE DISPLAY AW22 AR20 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 1 RP8 1 2 3 4 10K_8P4R_5% UH1B [4] [4] 2 PM_CLKRUN# 8.2K_0402_5% 1 2 SLP_LAN# RH70 200K_0402_5% 10/25 Change RH70 to 200K [4] [4] 1 2 3 4 8.2K_8P4R_5% 09/20 Change RH74 to 100k C 8 7 6 5 PCI_PIRQC# PCI_PIRQA# PCI_PIRQB# PCI_PIRQD# PWRSV_SEL# 07/31 Correct netname 10K_0402_5% FCI_10051922-1410ELF CONN@ +3VS +3VS 10/25 Delete RH56, RH57, RH59, RH60. Add RP7 +RTCVCC 2 2 1 SLP_S5# SLP_S4# SIO_SLP_A# 1 2 3 4 5 6 7 G2 8 G1 9 10 11 12 13 14 RH55 330K_0402_5% 1 RH63 D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SLP_S3# 1 +3V_PCH DDPC_AUXP EDP_VDDEN DDPD_AUXP DDPB_HPD PIRQA# DDPC_HPD PIRQB# DDPD_HPD R40 R39 C R35 R36 N40 N38 H45 K43 J42 H43 K45 J44 K40 K38 H39 07/06 Correct netname to follow GPIO table PIRQC# PIRQD# PCI PIRQE#/GPIO2 GPIO50 PIRQF#/GPIO3 GPIO52 PIRQG#/GPIO4 GPIO54 PIRQH#/GPIO5 GPIO51 PME# GPIO53 PLTRST# G17 PWRSV_SEL# PWRSV_SEL# F17 ODD_DA# ODD_DA# L15 NMI_SMI_DBG# NMI_SMI_DBG# 2 M15 ACCEL_INT_R# 0_0402_5% AD10 @ T87 [37] [23] 1 B [30] ACCEL_INT# RH96 [28] PAD~D Y11 PLTRST# GPIO55 LYNXPOINT_BGA695 08/10 Change UH3.5 connection to +3V_PCH power rail 5 OF 11 +3V_PCH [29,30] CH20 1 2 0.1U_0402_16V4Z 4 OF 11 2 Boot BIOS Strap PCH_GPIO51 08/10 Change UH7.5 connection to +3V_PCH power rail SATA1GP/ GPIO19 0 0 0 1 1 07/18 Add QH12 to invertion PCH_GPIO55 signal 07/23 Move QH12 to S/B. Boot BIOS Location LPC 10/25 Delete RH98, RH99, RP9 8 1 7 2 6 3 5 4 IN1 IN2 RH100. Add RP9 MC74VHC1G08DFT2G_SC70-5 GND Change R614.1 connection to +3V_PCH Change R614 to 10K ohms, and connection R614.1 to PM_RSMRST# Uninstall Q79, R614 Delete Q79, R615 UH3 OUT 4PLT_RST# Reserved (NAND) 1 08/10 Change RH235 to 0ohms RH101 1 0 PCI 1 1 SPI 2 Issued Date 07/16 Add for ESD's request A ENVDD_PCH 100K_0402_5% Compal Electronics, Inc. Compal Secret Data Security Classification 9/13 Delete UH7, RH235. Move RH236, CH106 to page 31 2 2012/03/23 Deciphered Date 2011/06/29 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 [13,25,28,29,30,35,37,39,5] @ CH107 22P_0402_50V8J PCH_CRT_BLU PCH_CRT_GRN PCH_CRT_RED 150_1206_8P4R_1% A PLT_RST# 1 3 PLTRST# 10/17 10/18 10/23 12/12 VCC 5 LYNXPOINT_BGA695 2 PCH -DMI,FDI,PM,DP,CRT Rev 0.5 LA-9241P Thursday, December 20, 2012 1 Sheet 14 of 56 5 4 3 2 1 1 RH106 10K_0402_5% 2 +3V_PCH GFX_CLK_REQ# D D 07/23 Delete FN14 and FN15 off page symbol [39] CLK_PCIE_CR# CLK_PCIE_CR +3VS CR_CLK_REQ# [39] CLK_TB_REFCLK# [39] CLK_TB_REFCLK [39] +3VS TB_CLKREQ# 2 1 10K_0402_5% AB1 AA44 AA42 RH105 2 1 10K_0402_5% AF1 AB43 AB45 RH113 2 1 10K_0402_5% AF3 1 10K_0402_5% AD43 AD45 T3 AF43 AF45 V3 C +3V_PCH +3V_PCH [39] [39] [39] [29] CLK_PCIE_EXP# CLK_PCIE_EXP CLKREQ_EXP# +3V_PCH [29] CLK_PCIE_LAN# [29] CLK_PCIE_LAN CLK_PCIE_LAN_REQ1# +3V_PCH [25] CLK_PCIE_MINI1# [25] [25] CLK_PCIE_MINI1 +3V_PCH MINI1_CLKREQ# RH118 2 RH121 2 1 10K_0402_5% RH125 2 1 10K_0402_5% CLKREQ_EXP# AE44 AE42 AA2 AB40 AB39 CLK_PCIE_LAN_REQ1# AE4 RH128 2 1 10K_0402_5% AJ44 AJ42 RH131 2 1 10K_0402_5% MINI1_CLKREQ# Y3 AH43 AH45 [30] [32] RH135 RH137 CLK_PCI_KBC CLK_PCI_SIO CLK_PCI_LOOPBACK RH138 2 2 1 10_0402_5% 1 10_0402_5% 2 1 22_0402_5% CLK_PCI0 D44 PCI_LOOPBACKOUT E44 1 2 3 4 B42 CLK_PCI4 A40 F41 22_1206_8P4R_5% CLKOUT_PEG_A_P PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47 CLKOUT_PCIE_N_1 CLKOUT_PCIE_P_1 CLKOUT_PEG_B CLKOUT_PEG_B_P PCIECLKRQ1#/GPIO18 PEGB_CLKRQ#/GPIO56 CLKOUT_PCIE_N_2 CLKOUT_DMI CLKOUT_PCIE_P_2 CLKOUT_DMI_P PCIECLKRQ2#/GPIO20/SMI# CLKOUT_DP CLKOUT_DP_P CLKOUT_PCIE_N_3 CLKOUT_PCIE_P_3 PCIECLKRQ3#/GPIO25 CLKOUT_DPNS CLKOUT_DPNS_P CLKOUT_PCIE_N_4 CLKOUT_PCIE_P_4 PCIECLKRQ4#/GPIO26 CLKIN_DMI CLKIN_DMI_P CLKOUT_PCIE_N5 CLKOUT_PCIE_P_5 PCIECLKRQ5#/GPIO44 CLKIN_GND CLKIN_GND_P CLKIN_DOT96N CLKIN_DOT96P CLKOUT_PCIE_N_6 CLKOUT_PCIE_P_6 PCIECLKRQ6#/GPIO45 CLKIN_SATA CLKIN_SATA_P CLKOUT_PCIE_N_7 REFCLK14IN CLKIN_33MHZLOOPBACK CLKOUT_PCIE_P_7 PCIECLKRQ7#/GPIO46 XTAL25_IN XTAL25_OUT CLKOUT_ITPXDP CLKOUTFLEX0/GPIO64 CLKOUT_ITPXDP_P CLKOUTFLEX1/GPIO65 CLKOUT_33MHZ0 CLKOUTFLEX2/GPIO66 CLKOUT_33MHZ1 CLKOUTFLEX3/GPIO67 CLKOUT_33MHZ2 ICLK_IREF CLKOUT_33MHZ3 TP19 TP18 CLKOUT_33MHZ4 DIFFCLK_BIASREF CLOCK SIGNAL AB35 CLK_PCIE_VGA# AB36 CLK_PCIE_VGA AF6 GFX_CLK_REQ# CLK_PCIE_VGA# [35] CLK_PCIE_VGA [35] DGPU_PWR_EN Y39 Y38 U4 2N7002KW_SOT323-3 3 PEG_CLK_REQ# 1 RH109 2 1 10K_0402_5% WLAN_TRAMSIT_OFF# AF39 CLK_CPU_DMI# AF40 CLK_CPU_DMI AJ40 AJ39 CLK_CPU_SSC_DPLL# CLK_CPU_SSC_DPLL AF35 AF36 CLK_CPU_DPLL# CLK_CPU_DPLL AY24 AW24 CLK_BUF_DMI# CLK_BUF_DMI AR24 AT24 CLK_BUF_BCLK# CLK_BUF_BCLK H33 G33 CLK_BUF_DOT96# CLK_BUF_DOT96 BE6 BC6 CLK_BUF_CKSSCD# CLK_BUF_CKSSCD +3V_PCH WLAN_TRAMSIT_OFF# CLK_CPU_DMI# [5] CLK_CPU_DMI [5] CLK_CPU_SSC_DPLL# CLK_CPU_SSC_DPLL CLK_CPU_DPLL# CLK_CPU_DPLL F45 D17 CLK_PCH_14M CLK_PCI_LOOPBACK AM43 AL44 08/06 Change ball name [14,35] [35] Q55 [25] 07/06 Follow HP's GPIO table [5] [5] C [5] [5] XTAL25_IN XTAL25_OUT 1 RH132 2 1M_0402_5% C40 F38 SIO_14M PAD~D T91 @ 1 22_0402_5% RH136 2 YH2 CLK_SIO_14M PAD~D 3 [32] F36 T92 @ F39 AM45 OUT NC IN NC 1 2 25MHZ_20PF_5YEA2500020BIF50Q3 1 ICLK_IREF 2 0_0402_5% RH140 +1.5VS AD39 AD38 AN44 4 11/01 Change YH2 to small package 1 PCH_CLK_BIASREF 7.5K_0402_1% 2 RH142 +1.5VS 1 18P_0402_50V8J [28] CLK_PCI_TPM [30] CLK_PCI_DEBUG_KBC [25] CLK_PCI_DEBUG 8 7 6 5 CLKOUT_PEG_A CLKOUT_PCIE_P_0 18P_0402_50V8J CLK_PCI2 RP10 B CLKOUT_PCIE_N_0 2 G +3V_PCH [39] [39] RH104 Y45 S Y43 09/11 Delete RH107, RH103, RH203, RH114, RH116, RH205, RH122, RH124, RH126, RH127, RH128, RH130 REV = 5 D LPT_PCH_M_EDS UH1C CH21 2 1 B CH22 2 10/25 Delete RH141, RH234, RH139. Add RP10. LYNXPOINT_BGA695 2 OF 11 PCIECLK REQ Pull UP Power Rail: SUS Rail : 0 3 4 5 6 7 Core Rail: 1 2 10/25 Delete RH108, RH110, RH111, RH112. Add RP11 RP11 1 2 3 4 CLK_BUF_DMI CLK_BUF_DMI# CLK_BUF_BCLK CLK_BUF_BCLK# 8 7 6 5 10K_8P4R_5% RH1151 RH1171 2 10K_0402_5% 2 10K_0402_5% CLK_BUF_CKSSCD# RH1191 CLK_BUF_CKSSCD RH1201 2 10K_0402_5% 2 10K_0402_5% RH1231 2 10K_0402_5% CLK_BUF_DOT96# CLK_BUF_DOT96 CLK_PCH_14M A A CLOCK TERMINATION for FCIM and need close to PCH Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 2011/06/29 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 PCH- CLK Rev 0.5 LA-9241P Thursday, December 20, 2012 Sheet 1 15 of 56 5 4 3 2 1 +3V_PCH FPR_OFF 10K_0402_5% MEM_SMBCLK 2.2K_0402_5% MEM_SMBDATA 08/07 Install RH148 and 2.2K_0402_5% change value to 2.2K DDR_RST_EN 10/18 Uninstall RH148 2.2K_0402_5% 07/06 Add for NFC function NFC_RST# 10K_0402_5% SML1_SMBCLK 2.2K_0402_5% SML1_SMBDATA 2.2K_0402_5% 2N7002DWH_SOT363-6 6 5 MEM_SMBCLK 2 +3VS 1 DDR_XDP_WAN_SMBCLK [11,12,13,28,38,5] QH3A D 3 MEM_SMBDATA 4 DDR_XDP_WAN_SMBDAT [11,12,13,28,38,5] 1 RH143 2 1 RH144 2 1 RH146 2 1 @ RH148 2 1 1 2 1 2 RH149 RH150 D RH151 2N7002DWH_SOT363-6 QH3B SIRQ 10K_0402_5% LPT_PCH_M_EDS [25,28,30,32] LPC_LAD3 [25,28,30,32] LPC_LFRAME# [32] A18 LPC_LAD3 C18 LPC_LFRAME# B21 D21 LPC_LDRQ0# G20 [28,30,32] SIRQ SIRQ AL11 SMBCLK LAD_1 LAD_2 SMBDATA SML0ALERT#/GPIO60 LAD_3 SML0CLK LFRAME# SML0DATA LDRQ0# SML1ALERT#/PCHHOT#/GPIO74 LDRQ1#/GPIO23 SML1CLK/GPIO58 SERIRQ SML1DATA/GPIO75 N7 FPR_OFF R10 MEM_SMBCLK U11 MEM_SMBDATA N8 DDR_RST_EN FPR_OFF [28] +3VS [30] PCH_SPI_CS0# RH154 1 PCH_SPI_CS0# 2 RH155 PCH_SPI_CLK_R AJ11 5_0402_1% PCH_SPI_CS0#_R AJ7 5_0402_1% AL7 AJ10 [30] PCH_SPI_SI [30] PCH_SPI_SO [30] PCH_SPI_WP# PCH_SPI_HOLD# 2 1 2 1 PCH_SPI_WP# 1 2 RH242 PCH_SPI_HOLD# RH243 1 2 PCH_SPI_SI RH156 PCH_SPI_SO RH157 AH1 PCH_SPI_SI_R 5_0402_1% AH3 PCH_SPI_SO_R 5_0402_1% PCH_SPI_WP#_R AJ4 15_0402_5% PCH_SPI_HOLD#_RAJ2 15_0402_5% SPI_CLK CL_CLK C-Link CL_DATA SPI_CS0# CL_RST# U8 LAN_SMBCLK R7 LAN_SMBDATA H6 NFC_RST# K6 SML1_SMBCLK N11 SML1_SMBDATA AF11 CL_CLK1 AF10 CL_DATA1 AF7 CL_RST1# DDR_RST_EN [5] LAN_SMBCLK [29] LAN_SMBDATA NFC_RST# @ 2N7002DWH_SOT363-6 [29] 6 @ LAN_SMBCLK [39] 07/06 Add for NFC function TP1 SPI_MOSI Thermal TP2 SPI_MISO TP4 SPI_IO2 TP3 SPI_IO3 TD_IREF 3 @ LAN_SMBDATA CL_CLK1 +3VS CL_DATA1 [25] CL_RST1# [25] 1 RH238 @ RH239 NFC_3S_SMBCLK [39] 4 NFC_3S_SMBDAT [39] C 2N7002DWH_SOT363-6 QH10B [25] BA45 2N7002DWH_SOT363-6 QH9A 6 1 SML1_SMBCLK PCH_KBC_I2CLK [30,35] BC45 BE43 QH9B 4 SML1_SMBDATA +3V_PCH 3 PCH_KBC_I2CDAT BE44 [30,35] 2N7002DWH_SOT363-6 AY43 07/19 Add RH242 and RH243 07/26 Install RH242 and RH244 LYNXPOINT_BGA695 RH153 QH10A SPI_CS1# SPI_CS2# RH152 PCH_TD_IREF 1 RH158 2 +3V_PCH 5 PCH_SPI_CLK 2 SPI [30] 1 1 07/06 Add for NFC function C PCH_SPI_CLK +3VS 2 1 LPC_LAD2 SMBus 1 2 LPC_LAD2 SMBALERT#/GPIO11 LAD_0 +3VM_LAN 2 2.2K_0402_5% [25,28,30,32] C20 2.2K_0402_5% LPC_LAD1 A20 LPC_LAD1 LPC [25,28,30,32] LPC_LAD0 1 LPC_LAD0 REV = 5 2 UH1D [25,28,30,32] 10/09 Change to RH152, RH153 to 499ohms 11/09 Change RH152, RH153 to 2.2K ohms LAN_SMBCLK 2.2K_0402_5% LAN_SMBDATA 2.2K_0402_5% 2 2 5 1 RH145 2 +3VS [30] 2 8.2K_0402_1% 3 OF 11 PCH_SPI_CLK 1 @ 2 CH113 22P_0402_50V8J B B 07/30 Add CH113 by RF request. H1 H_3P0 H2 H_3P3 H6 H_3P8 H7 H_3P8 H8 H_3P0 H9 H_3P8 H19 H_4P8X3P8 H20 H_4P3 H21 H_3P8 H22 H_4P8X3P8 H24 H_3P3 H25 H_2P8 H26 H_3P3 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA H10 H_3P8 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA @ @ @ @ @ @ @ @ @ @ @ @ @ @ ZZZ1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 07/09 Delete by HP request. PCB MB HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ 07/20 07/23 08/06 09/12 09/21 2012/03/23 @ Title Date: 4 3 A @ Compal Electronics, Inc. 2011/06/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 @ Modify screw hole Modify screw hole Delete H23 Delete H4, H32, H34, H41. Add H42, H43, H44, H45, H46 Add H47, H48 Compal Secret Data Security Classification Issued Date @ FD4 FIDUCIAL_C40M80 1 @ FD3 FIDUCIAL_C40M80 1 @ FD2 FIDUCIAL_C40M80 1 @ FD1 FIDUCIAL_C40M80 1 HOLEA 1 H50 H_3P0 HOLEA 1 H49 H_3P3 HOLEA 1 H48 H_3P0N HOLEA 1 H47 H_3P0N HOLEA 1 A H46 H_3P8 1 HOLEA @ 1 HOLEA 1 H43 H44 H45 H_2P8 H_2P4X3P9N H_3P8X4P8N 1 H42 H_2P8 1 H40 H_3P0 1 H38 H_3P8 1 H37 H_3P0 1 H35 H_3P8 1 H33 H_3P1N 1 H31 H_3P8 1 H30 H_3P0 1 H29 H_3P3 1 H28 H_3P3 1 H27 H_3P3 2 PCH - SPI, SMBUS,LPC Rev 0.5 LA-9241P Thursday, December 20, 2012 Sheet 1 16 of 56 5 4 3 2 1 D D [39] [39] [39] [39] [39] [39] [39] [39] [39] [39] C [39] [39] [39] [39] Card Reader PCIE_PTX_C_DRX_N3 PCIE_PTX_C_DRX_P3 [39] [39] AT31 AR31 1 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2 2 0.1U_0402_10V7K PCIE_PTX_DRX_P2 BD33 BB33 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 AW33 AY33 CH27 CH28 1 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N3 2 0.1U_0402_10V7K PCIE_PTX_DRX_P3 BE34 BC34 PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 AT33 AR33 2 0.1U_0402_10V7K PCIE_PTX_DRX_N4 2 0.1U_0402_10V7K PCIE_PTX_DRX_P4 BE36 BC36 PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_C_DRX_N4 PCIE_PTX_C_DRX_P4 PCIE_PRX_EXPTX_N5 PCIE_PRX_EXPTX_P5 [25] [25] PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 CH110 CH111 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_EXPRX_N5 PCIE_PTX_EXPRX_P5 [25] [25] WLAN PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 [39] [39] [29] [29] BE32 BC32 CH29 1 CH30 1 PCIE_PRX_EXPTX_N5 PCIE_PRX_EXPTX_P5 CH1001 CH99 1 2 0.1U_0402_10V7K PCIE_PTX_EXPRX_N5_C 2 0.1U_0402_10V7K PCIE_PTX_EXPRX_P5_C AY38 AW38 2 0.1U_0402_10V7K PCIE_PTX_DRX_N6 2 0.1U_0402_10V7K PCIE_PTX_DRX_P6 BC38 BE38 PCIE_PRX_DTX_N7 PCIE_PRX_DTX_P7 AT40 AT39 1 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N7 2 0.1U_0402_10V7K PCIE_PTX_DRX_P7 BE40 BC40 PCIE_PRX_DTX_N8 PCIE_PRX_DTX_P8 AN38 AN39 CH35 1 CH36 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N8 2 0.1U_0402_10V7K PCIE_PTX_DRX_P8 BD42 BD41 CH31 1 CH32 1 PCIE_PRX_DTX_N7 PCIE_PRX_DTX_P7 PCIE_PTX_C_DRX_N7 PCIE_PTX_C_DRX_P7 CH33 CH34 PCIE_PRX_DTX_N8 PCIE_PRX_DTX_P8 PCIE_PTX_C_DRX_N8 PCIE_PTX_C_DRX_P8 BD37 BB37 PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PTX_C_DRX_N6 PCIE_PTX_C_DRX_P6 AW36 AV36 +1.5VS 1 2 RH160 PCH_PCIE_IREF 0_0402_5% BE30 BC30 B BB29 +1.5VS 1 2 RH164 PCH_PCIE_RCOMP BD29 7.5K_0402_1% USB2N0 USB2P0 USB2N1 USB2P1 USB2N2 USB2P2 USB2N3 USB2P3 USB2N4 USB2P4 USB2N5 USB2P5 USB2N6 USB2P6 USB2N7 USB2P7 USB2N8 USB2P8 USB2N9 USB2P9 USB2N10 USB2P10 USB2N11 USB2P11 USB2N12 USB2P12 USB2N13 USB2P13 PETN1/USB3TN3 PETP1/USB3TP3 PERN2/USB3RN4 PERP2/USB3RP4 PETN2/USB3TN4 PETP2/USB3TP4 PERN_3 PERP_3 PETN_3 PETP_3 PERN_4 PERP_4 PETN_4 PETP_4 PERN_5 PERP_5 PETN_5 PETP_5 USB3RN1 USB3RP1 USB3TN1 USB3TP1 USB3RN2 USB3RP2 USB3TN2 USB3TP2 USB3RN5 USB3RP5 USB3TN5 USB3TP5 USB3RN6 USB3RP6 USB3TN6 USB3TP6 PERN_6 PERP_6 PETN_6 PETP_6 PERN_7 PERP_7 PETN_7 PETP_7 PERN_8 PERP_8 PETN_8 PETP_8 USBRBIAS# USBRBIAS PCIE_IREF TP24 TP23 TP11 OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14 TP6 PCIE_RCOMP LYNXPOINT_BGA695 B37 D37 A38 C38 A36 C36 A34 C34 B33 D33 F31 G31 K31 L31 G29 H29 A32 C32 A30 C30 B29 D29 A28 C28 G26 F26 F24 G24 USBP0USBP0+ USBP1USBP1+ AR26 AP26 BE24 BD23 AW26 AV26 BD25 BC24 AW29 AV29 BE26 BC26 AR29 AP29 BD27 BE28 USB3RN1 USB3RP1 USB3TN1 USB3TP1 USB3RN2 USB3RP2 USB3TN2 USB3TP2 USB3RN5 USB3RP5 USB3TN5 USB3TP5 USB3RN6 USB3RP6 USB3TN6 USB3TP6 K24 K26 USBRBIAS M33 L33 USBP0[33] USBP0+ [33] USBP1[40] USBP1+ [40] USBP4USBP4+ USBP5USBP5+ USBP6USBP6+ USBP7USBP7+ USBP8USBP8+ USBP9USBP9+ USBP10USBP10+ USBP11USBP11+ USBP12USBP12+ USBP13USBP13+ [39] [39] [39] [39] [39] [39] [37] [37] [28] [28] [39] [39] [22] [22] [33] [33] [25] [25] [25] [25] USB3RN1 USB3RP1 USB3TN1 USB3TP1 USB3RN2 USB3RP2 USB3TN2 USB3TP2 USB3RN5 USB3RP5 USB3TN5 USB3TP5 USB3RN6 USB3RP6 USB3TN6 USB3TP6 [33] [33] [33] [33] [40] [40] [40] [40] [39] [39] [39] [39] [39] [39] [39] [39] C ----->BT/WLAN Combo USBRBIAS ----->Docking USB 3.0 ----->USB 3.0 Walkup port 2 ----->USB 3.0 Walkup port 3 ----->USB 3.0 Walkup port 4 CAD NOTE: Route single-end 50-ohms and max 500-mils length. Avoid routing next to clock pins or under stitching capacitors. Recommended minimum spacing to other signal traces is 15 mils. 10/26 Change PCH.P3 and RPH2.4 connection to WWAN_DET#_PCH P3 WWAN_DET#_PCH V1 USB_OC1#_R U2 USB_OC2# P1 USB_OC3# M3 USB_OC4#_R T1 dGPU_HPD_INTR N2 M1 9 OF 11 USBP4USBP4+ USBP5USBP5+ USBP6USBP6+ USBP7USBP7+ USBP8USBP8+ USBP9USBP9+ USBP10USBP10+ USBP11USBP11+ USBP12USBP12+ USBP13USBP13+ ----->Docking USB 3.0 ----->USB 3.0 Walkup port 2 ----->NA ----->NA ----->USB 3.0 Walkup port 3 ----->USB 3.0 Walkup port 4 ----->Express card slot ----->Smart card reader ----->Finger Print Reader ----->Walkup USB 2.0 port ----->USB Camera ----->Docking USB 2.0 port ----->WWAN RH159 22.6_0402_1% GIGA LAN 2 0.1U_0402_10V7K PCIE_PTX_DRX_N1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1 PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 [39] [39] [29] [29] 1 1 REV = 5 PERN1/USB3RN3 PERP1/USB3RP3 PCIe Express card slot PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 CH108 CH109 LPT_PCH_M_EDS 1 [39] [39] PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 AW31 AY31 2 [39] [39] UH1I PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 USB 07/17 Add by HP request. WWAN_DET#_PCH [25] 07/23 Delete off page symbol dGPU_HPD_INTR [35] LED_LINK_LAN#_R [29] TB_HOT_PLUG# [39] 07/18 Change net name to TB_HOT_PLUG# follow HP request. 09/11 Delete RH165 +3V_PCH 09/11 Change RPH1.3 connection to TB_HOT_PLUG# B RPH1 USB_OC4#_R TB_HOT_PLUG# LED_LINK_LAN#_R USB_OC3# 4 3 2 1 5 6 7 8 10K_1206_8P4R_5% RPH2 WWAN_DET#_PCH 4 dGPU_HPD_INTR 3 2 USB_OC2# 1 USB_OC1#_R 5 6 7 8 10K_1206_8P4R_5% 07/23 Modify pin define for layout smooth A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 2011/06/29 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 PCH-PCIE,USB Rev 0.5 LA-9241P Thursday, December 20, 2012 Sheet 1 17 of 56 2N7002KW_SOT323-3 +3VS [30] 2 1 2 1 2 1 1 2 RH167 RH169 RH171 RH175 1 2 1 2 1 2 1 2 1 2 1 2 RH177 D RH172 RH173 RH178 RH240 RH241 PCH_GPIO0 10K_0402_5% OCP_OC# 100K_0402_5% ODD_EN 10K_0402_5% DGPU_PWROK 8.2K_0402_5% 1 4 D 3 5 S 3 +3VS [30] EC_SCI# PCH_GPIO8 [29] LAN_DIS# [38] [35] KBL_DET# DGPU_PWROK WWAN_TRANSMIT_OFF# RH183 2 07/23 07/23 08/01 10/26 1 2 @ RH184 2 RH185 2 PCH_GPIO24 10K_0402_5% 1 PCH_GPIO8 10K_0402_5% 1 LAN_DIS# 10K_0402_5% 1 NFC_INT 10K_0402_5% 07/06 Change for NFC 07/23 Follow VBK10. 10/24 Install RH185 1 RH176 Delete Delete Change Change EC_SCI# A14 THERM_SCI# G15 PCH_GPIO8 LAN_DIS# FPR_LOCK# 10K_0402_5% 10/24 Change RH176.2 connection to GND. Install RH176 [28] FPR_LOCK# [35] DGPU_PRSNT# 07/06 Change for NFC [39] NFC_INT 07/06 Follow HP's GPIO table [23] ODD_EN C 1 LANWAKE# RH248 100K_0402_5% 10/25 Add LANWAKE# PU RH248 to +3VDS D3E_WAKE# [30,32] [25] +3V_PCH KBC_SIO_RST# GPS_XMIT_OFF# Y1 K13 AB11 KBL_DET# AN2 DGPU_PWROK C14 WWAN_TRANSMIT_OFF# BB4 LANWAKE# LANWAKE# PCH_GPIO24 off page symbol FN_CLK2 off page symbol net name to mSATA_DET# net name to PCH_GPIO_35 10/26 Change net name to PCH_GPIO_36 08/01 Change net name to Sec_HDD_DET 07/23 Delete PCH_GPIO37 off page symbol +3VDS 2 F13 Y10 R11 PCH_GPIO28 AD11 PCH_GPIO34 AN6 PCH_GPIO_35 AP1 PCH_GPIO_36 AT3 PCH_GPIO37 AK1 DOCK_ID0 AT7 DOCK_ID1 AM3 FPR_LOCK# AN4 DGPU_PRSNT# AK3 NFC_INT U12 ODD_EN C16 D3E_WAKE# D13 KBC_SIO_RST# G13 GPS_XMIT_OFF# H15 2 1 BMBUSY#/GPIO0 2 1 RH166 2 1 RH168 TACH1/GPIO1 TACH2/GPIO6 CPU/Misc TACH3/GPIO7 GPIO8 D 10/26 Delete A20GATE off page symbol LAN_PHY_PWR_CTRL/GPIO12 TP14 GPIO15 PECI SATA4GP/GPIO16 RCIN# GPIO TACH0/GPIO17 PROCPWRGD SCLOCK/GPIO22 THRMTRIP# GPIO24 PLTRST_PROC# GPIO27 VSS AN10 A20GATE AY1 PAD~D AT6 RCIN# AV3 H_CPUPWRGD AV1 PCH_THERMTRIP#_R T104 @ RCIN# H_CPUPWRGD 10/29 Change RH179 to 100ohms +1.05VS [5] 2 RH179 AU4 CPU_PLTRST# CPU_PLTRST# N10 [5] 1 GPIO28 2 GPIO34 1 100_0402_5% PCH_THERMTRIP#_R PCH_THERMTRIP#_R [24,35,5] GPIO35/NMI# SATA2GP/GPIO36 SATA3GP/GPIO37 SLOAD/GPIO38 SDATAOUT0/GPIO39 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SDATAOUT1/GPIO48 SATA5GP/GPIO49 GPIO57 TACH4/GPIO68 TACH5/GPIO69 TACH6/GPIO70 TACH7/GPIO71 VSS VSS VSS VSS NCTF LYNXPOINT_BGA695 A2 A41 A43 A44 B1 B2 B44 B45 BA1 BC1 BD1 BD2 BD44 BD45 BE2 BE3 D1 E1 E45 A4 C 6 OF 11 PCH_GPIO28 2 1 @RH194 @ RH194 1K_0402_1% 1 RH193 4.7K_0402_5% BE41 BE5 C45 A5 A20GATE 10K_0402_5% RCIN# 10K_0402_5% REV = 5 CH37 0.1U_0402_16V4Z [29] RH182 AT8 OCP_OC# PCH_GPIO24 +3V_PCH 2 PCH_GPIO0 PCH_GPIO15 [25] LPT_PCH_M_EDS UH1F 07/23 Correct Net name DOCK_ID0 10K_0402_5% DOCK_ID1 10K_0402_5% KBC_SIO_RST# 10K_0402_5% EC_SCI# 10K_0402_5% THERM_SCI# 10K_0402_5% WWAN_TRANSMIT_OFF# 10K_0402_5% 07/06 Add PU resistor 1 Q58 2 G OCP_PWM_OUT 2 2 PCH_GPIO15 1K_0402_1% 2 PCH_GPIO_35 100K_0402_5% 2 PCH_GPIO34 100K_0402_5% RH181 +3VS 1 RH180 1 RH170 08/01 Change net name to mSATA_DET# 10/26 Change RH180.2 connection to PCH_GPIO_35. Change RH180.1 connection to +3VS 08/01 Change net name to Sec_HDD_DET 10/26 Change netname to PCH_GPIO_36 PLL ON DIE VR ENABLE ENABLED - HIGH(DEFAULT) DISABLED - LOW 2 1 2 1 RH198 RH200 PCH_GPIO_36 10K_0402_5% PCH_GPIO37 10K_0402_5% B B +3VS 1 2 2 1 RH197 RH199 Config KBL_DET# 10K_0402_5% DGPU_PRSNT# 10K_0402_5% GPIO16,49 USB X4,PCIEX8,SATAX6 11 USB X6,PCIEX8,SATAX4 01 SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK. WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER PLRST_N DE-ASSERTS). NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED. 08/03 Delete RH201, RH202 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 2011/06/29 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 PCH -GPIO,MISC,NTFC Rev 0.5 LA-9241P Sheet Thursday, December 20, 2012 1 18 of 56 5 4 3 2 1 D D LH1 2 1 BLM18PG181SN1D_2P +VCCADAC LPT_PCH_M_EDS +1.5VS CRT DAC VCCVRM FDI VCCIO HVCMOS Core VCCIO VCCVRM VCCIO Y12 1 +PCH_USB_DCPSUS1 1 T141 @ PAD AJ30 AJ32 AJ26 AJ28 AK20 AK26 AK28 2 +PCH_USB_DCPSUS3 T142 @ PAD 2 @ C +1.5VS +1.5VS 1 BE22 AK18 2 +1.05VS +1.5VS +1.05VS 1 AN11 AK22 1 +1.05VS AM18 AM20 AM22 AP22 AR22 AT22 2 2 7 OF 11 1 2 1 2 1 2 1 2 CH59 10U_0603_6.3V6M 1 CH58 1U_0402_6.3V6K +PCH_VCCDSW_R R30 R32 CH57 1U_0402_6.3V6K 2 +3V_PCH CH56 1U_0402_6.3V6K 1 RH204 2 AN35 CH55 1U_0402_6.3V6K LYNXPOINT_BGA695 VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO AN34 CH54 10U_0603_6.3V6M SATA VCCMPHY B VCCVRM +3VS 1 @ 2 @ 2 CH52 10U_0603_6.3V6M 2 PCIe/DMI 1 BB44 CH53 10U_0603_6.3V6M 2 1 CH51 1U_0402_6.3V6K 1 CH50 1U_0402_6.3V6K 2 CH49 22U_0805_6.3V6M 1 DCPSUS3 DCPSUS3 VCCIO VCCVRM VCCVRM +3VS CH48 0.1U_0402_16V4Z DCPSUS1 VCCSUS3_3 VCCSUS3_3 USB3 DCPSUSBYP VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCC3_3_R30 VCC3_3_R32 +1.05VS M31 CH47 0.1U_0402_16V4Z VCCIO +1.05VM +PCH_VCCDSW U14 AA18 U18 U20 U22 U24 V18 V20 V22 V24 Y18 Y20 Y22 VSS VCCADACBG3_3 P43 CH45 10U_0603_6.3V6M 2 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC P45 CH46 1U_0402_6.3V6K 2 1 CH44 1U_0402_6.3V6K 2 1 CH43 1U_0402_6.3V6K 2 1 CH39 1U_0402_6.3V6K C CH38 10U_0603_6.3V6M 1 2 +1.5VS REV = 5 VCCADAC1_5 AA24 AA26 AD20 AD22 AD24 AD26 AD28 AE18 AE20 AE22 AE24 AE26 AG18 AG20 AG22 AG24 Y26 2 1 CH42 10U_0603_6.3V6M UH1G +1.05VS 1 CH41 0.1U_0402_16V4Z 2 CH40 0.01U_0402_16V7K 1 @ B +PCH_VCCDSW 5.11_0402_1%~D 07/20 Delete CH60, CH62, CH63 2 CH61 1U_0402_6.3V6K 1 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 2011/06/29 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 PCH- Power Rev 0.5 LA-9241P Thursday, December 20, 2012 Sheet 1 19 of 56 5 4 3 2 1 D D +3V_PCH LPT_PCH_M_EDS UH1H +1.05VS M24 U35 L24 Y35 AF34 07/19 Non Install CH101 07/20 Delete CH102 +1.05VS_VCC AP45 Y32 +1.05VS AD34 +1.05VS AD35 +1.05VS_VCC LH2 1 2 4.7UH_LQM18FN4R7M00D_20% AG30 AG32 +1.05VS_VCC AD36 2 AE30 AE32 1 +1.05VS 2 +3V_PCH Azalia DCPSUS2 VCCSUSHDA A26 1 VCCVRM VCC VCCSUS3_3 VCCCLK VCCRTC RTC VCCCLK3_3 DCPRTC DCPRTC VCCCLK3_3 VCCCLK3_3 VCCCLK3_3 V_PROC_IO V_PROC_IO CPU +RTCVCC K8 P14 P16 +PCH_DCPRTC CH74 1 +1.05VS CH105 1 CH83 1 CH84 1 AJ12 AJ14 2 0.1U_0402_10V7K~D 1 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 1U_0402_6.3V6K 2 07/25 Change power rail VCCCLK3_3 VCCCLK3_3 VCCSPI SPI 1 A6 AD12 1 2 1 2 2 2 C +3V_PCH 09/11 Delete RH226 VCCCLK VCC VCC VCCCLK VCCCLK VCCASW Fuse VCCCLK VCCASW VCCCLK VCCCLK P18 P20 +3VS L17 +1.05VM 1 R18 2 VCCVRM VCCCLK VCC3_3 Thermal VCCCLK VCCCLK VCC3_3 AW40 +1.5VS 1 2 +3VS AK30 AK32 1 LYNXPOINT_BGA695 8 OF 11 2 CH85 0.1U_0402_10V6K B 1 CH81 1U_0402_6.3V6K 2 CH80 10U_0603_6.3V6M 1 +3V_PCH U36 CH92 1U_0402_6.3V6K AA30 AA32 +3VS AE14 AF12 AG14 CH79 1U_0402_6.3V6K +1.05VS VCCIO ICC U32 V32 VCCIO VCCIO VCCIO VCCIO +PCH_VCCSST CH66 2 0.1U_0402_10V6K CH77 1U_0402_6.3V6K L26 M26 VCC3_3 VCC3_3 VCC3_3 1 +3VDS 10/18 Install RH209. Uninstall RH208 10/23 Install RH208. Uninstall RH209 CH76 0.1U_0402_10V6K L29 DCPSST 2 0.1U_0402_10V6K +PCH_VCCDSW3_3 A16 AA14 1 RH209 CH75 0.1U_0402_10V6K M29 +3VS 09/24 Change netname 1 RH208 @ CH73 1U_0402_6.3V6K 1 2 C S2 PAD @ T143 CH72 10U_0603_6.3V6M 2 +1.5VS VCCDSW3_3 VSS VCC3_3 2 CH71 0.1U_0402_10V7K~D 1 CH70 0.1U_0402_10V6K 2 U30 V28 V30 Y30 +1.05VS VCCSUS3_3 VCCSUS3_3 1 CH104 1 2 GPIO/LPC VCCUSBPLL 2 0_0402_5% CH69 0.01U_0402_16V7K_X7R 1 CH68 0.1U_0402_10V6K 2 +3VS VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 USB 1 CH67 0.1U_0402_10V6K 2 CH65 0.1U_0402_10V6K 1 +3V_PCH R20 R22 CH64 0.1U_0402_10V6K +3V_PCH R24 R26 R28 U26 0_0402_5% REV = 5 B +1.05VS 2 Place near pin Y32,AA30,AA32 1 2 Place near pin AD34 Place near pin AD35,AD36 1 2 CH91 1U_0402_6.3V6K Place near pin AP45 2 1 CH90 1U_0402_6.3V6K 2 1 CH89 1U_0402_6.3V6K 1 CH88 1U_0402_6.3V6K @ CH87 1U_0402_6.3V6K 2 CH86 10U_0603_6.3V6M 1 09/24 Delete RH213, RH216, and change netname. Place near pin AG30,AG32,AE30,AE32 +3VS Place near pin M29 Place near pin L29 1 2 Place near pin L26,M26 1 2 CH96 1U_0402_6.3V6K 2 CH95 1U_0402_6.3V6K A 1 CH94 1U_0402_6.3V6K 2 CH93 1U_0402_6.3V6K 1 A Place near pin U32,V32 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 2011/06/29 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 PCH - Power Rev 0.5 LA-9241P Sheet Thursday, December 20, 2012 1 20 of 56 5 4 3 2 1 D D UH1J LPT_PCH_M_EDS AL34 AL38 AL8 AM14 AM24 AM26 AM28 AM30 AM32 AM16 AN36 AN40 AN42 AN8 AP13 AP24 AP31 AP43 AR2 AK16 AT10 AT15 AT17 AT20 AT26 AT29 AT36 AT38 D42 AV13 AV22 AV24 AV31 AV33 BB25 AV40 AV6 AW2 F43 AY10 AY15 AY20 AY26 AY29 AY7 B11 B15 C VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REV = 5 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS UH1K K39 L2 L44 M17 M22 N12 N35 N39 N6 P22 P24 P26 P28 P30 P32 R12 R14 R16 R2 R34 R38 R44 R8 T43 U10 U16 U28 U34 U38 U42 U6 V14 V16 V26 V43 W2 W44 Y14 Y16 Y24 Y28 Y34 Y36 Y40 Y8 AA16 AA20 AA22 AA28 AA4 AB12 AB34 AB38 AB8 AC2 AC44 AD14 AD16 AD18 AD30 AD32 AD40 AD6 AD8 AE16 AE28 AF38 AF8 AG16 AG2 AG26 AG28 AG44 AJ16 AJ18 AJ20 AJ22 AJ24 AJ34 AJ38 AJ6 AJ8 AK14 AK24 AK43 AK45 AL12 AL2 BC22 BB42 LPT_PCH_M_EDS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS LYNXPOINT_BGA695 B LYNXPOINT_BGA695 REV = 5 B19 B23 B27 B31 B35 B39 B7 BA40 BD11 BD15 BD19 AY36 AT43 BD31 BD35 BD39 BD7 D25 AV7 F15 F20 F29 F33 BC16 D4 G2 G38 G44 G8 H10 H13 H17 H22 H24 H26 H31 H36 H40 H7 K10 K15 K20 K29 K33 BC28 C 11 OF 11 B 10 OF 11 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 2011/06/29 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 PCH - GND Rev 0.5 LA-9241P Thursday, December 20, 2012 Sheet 1 21 of 56 5 4 3 2 1 LCD POWER CIRCUIT INVPWR_B+ U47 6 1 07/23 Add C392 and C394 by RF request D 2 VIN VIN VOUT VOUT VBIAS CT GND GND W=60mils 7 1 +LCDVDD 8 C499 1 2 5 9 C498 TPS22965DSGR_SON8_2X2 4700P_0402_16V7K C394 1 @ 2 2 1 C2 10U_0603_6.3V6M 2 C3 0.1U_0402_16V4Z 18P_0402_50V8J 4 +5VDS C449 ON 0.1U_0402_16V4Z 2 4.7U_0603_6.3V6K 2 18P_0402_50V8J @ 2 1 C497 C4 @ 680P_0402_50V7K 1 C393 82P 50V J NPO 0402 1 +3VDS 1 3 ENAVDD 09/26 Change C497 to 4.7u. Install R490 ENAVDD 2 [35] 1 100K_0402_5% W=60mils Place closed to JLVDS1 +LCDVDD R490 2 L1 FBMA-L11-201209-221LMA30T_0805 2 1 L2 FBMA-L11-201209-221LMA30T_0805 2 1 B+ C5 1 1 2 2 SM010014520 3000ma 220ohm@100mhz DCR 0.04 68P_0402_50V8J 08/08 Reserve C449 by RF request eDP PANEL Conn. W=60mils W=60mils 07/23 Add C392 and C394 by RF request D 09/25 Change LCDVDD power rail solution. Delete R9, R10, R11, Q12, Q20, C1, C7, C8 Add U47, C497, C498, C499 Uninstall R494 11/06 Change C498 to 4700pF 07/06 Change for eDP MUX ENABLT ENABLT 1 2 2K_0402_5% R12 EDP_SW_D3N EDP_SW_D3P [36] [36] EDP_SW_D2N EDP_SW_D2P [36] [36] EDP_SW_D1N EDP_SW_D1P [36] [36] EDP_SW_D0N EDP_SW_D0P [36] [36] EDC_SW_AUX EDC_SW_AUX# JEDP1 1 [35] [36] [36] 2 R13 100K_0402_5% 2 1 +3VS +LCDVDD 1 2 R178 100K_0402_5% R179 100K_0402_5% [13] SG_IN EDP_SW_HPD [36] D3 [30,38,39] 1 LID_SW# 2 [35] ENABLT_R INV_PWM INV_PWM 1 @ 1 Camera_ON +5VS 2 2 R15 [14] D_MIC_CLK D_MIC_DATA 2 0_0402_5% USB20_P10_R USB20_N10_R L3 [17] USBP10- [17] USBP10+ 1 1 2 4 3 2 USB20_N10_R 3 USB20_P10_R INVPWR_B+ C 4 C22 2 1 680P_0402_50V7K 07/31 Delete +5VS_R_LOGO_KBL signal INV_PWM +5VS 1 2 G1 G2 G3 G4 G5 1 2 1U_0402_6.3V6K 1 C83 0.1U_0402_16V4Z D_MIC_CLK D_MIC_DATA C84 R491 100K_0402_5% 07/31 Delete Q21,Q22,R454,R14. [26] [26] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 C81 4.7U_0603_6.3V6K RB751V-40_SOD323-2 9/20 Change to commond part. EDP_SW_HPD ENABLT_R +3VS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 11/01 Delete C23, C80, C82, C111 C ACES_50398-04071-001 WCM-2012-900T_4P CONN@ 1 2 @ R16 0_0402_5% 08/03 Swap pin define for layout smooth D_MIC_CLK D_MIC_DATA C500 2 @ 1 2 10P_0402_25V8K 1 10P_0402_25V8K @ 09/12 Modify JEDP1 symbol and footprint. 09/13 Modify JEDP1 symbol and footprint. 09/20 Correct circuit short issue, Modify pin define. C501 09/12 Modify JEDP1 symbol and footprint. 09/25 Reserve C500, C501 for ESD request B B A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/29 2011/06/29 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title eDP/LVDS CONN & Camera Size Document Number Rev 0.5 LA-9241P Date: Thursday, December 20, 2012 Sheet 1 22 of 56 5 4 3 2 1 SATA HDD CONN. GND A+ AGND BB+ GND D SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0 0.01U_0402_16V7K_X7R 1 0.01U_0402_16V7K_X7R 1 SATA_PRX_C_DTX_N0 SATA_PRX_C_DTX_P0 0.01U_0402_16V7K_X7R 1 0.01U_0402_16V7K_X7R 1 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2 C41 2 C42 2 C43 2 C44 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 [13] [13] SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 [13] [13] D +5VS 100mils +5VS 1 2 1 2 1 2 C48 68P_0402_50V8J 2 C47 0.1U_0402_16V4Z 1 C46 1U_0402_6.3V4Z GND GND V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12 1 2 3 4 5 6 7 C45 10U_0805_10V4Z 23 24 Place caps. near HDD CONN. CONN@ JHDD1 SANTA_199201-1 07/30 Modify JHHD1 footprint. 11/07 Change C48 to 68pF Placea caps. near HDD CONN. +5VS SATA ODD CONN. +5V_ODD Place caps. near ODD CONN. JODD1 1 R55 @ 2 R57 100K_0402_5% 2 Q24 SI2305CDS-T1-GE3_SOT23-3 2 1 0.01U_0402_16V7K_X7R 1 0.01U_0402_16V7K_X7R 1 2 C49 2 C50 SATA_PRX_C_DTX_N1 SATA_PRX_C_DTX_P1 0.01U_0402_16V7K_X7R 1 0.01U_0402_16V7K_X7R 1 2 C51 2 C52 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 [13] [13] SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 8 9 10 11 12 13 R56 DP +5V GND +5V GND MD GND GND GND GND SANTA_203801-1 CONN@ 1 [13] [13] 2 @ 0_0402_5% C 1 +5V_ODD 2 C53 @ 0.1U_0402_10V6K ODD_DA# [14] 2 07/30 Modify JODD1 footprint. 08/03 Modify JODD1 footprint. 08/03 Change JODD1 pin 16 and 17 to NC. 10/31 Modify JODD1 footprint. 1 2 1 2 1 2 C58 68P_0402_50V8J 2 C57 0.1U_0402_10V6K 1 07/06 Correct Net name to follow HP GPIO table C56 0.1U_0402_10V6K 1 +5V_ODD C55 10U_0805_10V4K 07/12 Delete C54 and add R539 by HP request S 2N7002_SOT23-3 2 G 14 15 16 17 100K_0402_5% D 3 ODD_EN ODD_EN SATA_PTX_C_DRX_P1 SATA_PTX_C_DRX_N1 R539 ODD_EN# Q25 [18] G 1 1 1 2 3 4 5 6 7 D +5VS CC52 1U_0402_6.3V6K C GND A+ AGND BB+ GND 1 S 3 2 0_0805_5% 11/07 Change C58 to 68pF Placea caps. near ODD CONN. B B mSATA Conn. +3VS JMINI1 08/01 Modify SATA bus from port 2 to port 5 [13] [13] [13] [13] SATA_PRX_DTX_P5 SATA_PRX_DTX_N5 SATA_PTX_DRX_N5 SATA_PTX_DRX_P5 C61 C62 1 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P5 SATA_PRX_C_DTX_N5 C63 C64 1 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N5 SATA_PTX_C_DRX_P5 +3VS [32] mSATA_DET# mSATA_DET# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 08/01 Delete Q48 and add R565 10/26 Delete R565 +3VS 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND1 GND2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 +3VS 1 2 1 C59 4.7U_0603_6.3V6K 2 C60 0.1U_0402_16V4Z 54 BELLW_80003-1023 CONN@ R1316 1 2 10K_0402_5% 07/06 Change value to 10K A A 2012/03/23 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2010/03/31 Title IBEX-M(1/6)-HDA/JTAG/SATA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.5 LA-9241P Date: 5 4 3 2 Thursday, December 20, 2012 1 Sheet 23 of 56 5 4 PWM Fan Control circuit 3 2 1 +5VS 07/12 Change U3 to TC7SET00 by HP request 2 KBC_PROC_HOT# D 1 RB751V-40_SOD323-2 R133 4.7K_0402_5% +VCCIO_OUT 1 2 2K_0402_5% [47,5] O 4 INA C65 2 1 TC7SET00FU _SSOP5 @ 0.1U_0402_10V6K R166 C 2 B 3 R17 INB 1 2 3 4 5 6 1 2 3 4 G5 G6 D ACES_50273-0040N-001 CONN@ 1 2 #5/7 change by HP requirement 2 JFAN1 22_0402_5% 1 2 R60 P 5 D4 +5VS TACH_FAN_IN U3 G [30,5] [30] 1 FAN_PWM 3 [30] change by HP requirement 1 #4/11 E Q65 MMBT3904_SOT23-3 1 07/12 Swap JFAN1 pin1 and pin 2 2 +5VS 47K_0402_5% Notes: KBC_PROC_HOT_R Place Q65 close CPU side C 28K_0402_1% +3VS 1 2 5 4 150_0402_1% HYST GMT G708T1U C66 1 GND OT# 2 0.1U_0402_16V4Z SET VCC C R1315 U38 R61 1 1 2 2 3 R492 1 2 0_0402_5% PCH_THERMTRIP#_R [18,35,5] 10/18 Install R492 and change R492.2 connection to PCH_THERMTRIP#_R 08/01 Change netname to KBC_PWR_ON 08/01 Change netname to KBC_PWR_ON B B A A Compal Secret Data Security Classification Issued Date 2012/03/23 Deciphered Date 2011/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Thermal/FAN Size Document Number Custom Date: Rev 0.5 LA-9241P Thursday, December 20, 2012 1 Sheet 24 of 56 B 2 +3VS GPS_XMIT_OFF# [18] 2 WLAN&BT Combo module circuits BT on module BT on module Enable Disable BT_CRTL HI LO BT_ON# LO HI #4/13 2 C74 1 1 2 4.7U_0805_10V4Z 2 C73 C72 1 [29,30] [15] MINI1_CLKREQ# 1 3 [15] [15] [17] [17] SIM_DET CLK_PCIE_MINI1# CLK_PCIE_MINI1 PCIE_PRX_DTX_N7 PCIE_PRX_DTX_P7 PCIE_PTX_C_DRX_N7 PCIE_PTX_C_DRX_P7 +3V_AOAC +3V_WWAN 09/10 Add R599 and R600 LOTES_APCI0018-P002A WWAN_FULL_PWR R599 1 2 10K_0402_5% WWAN_RSVD2 R600 1 2 10K_0402_5% [16] [16] [16] 10/24 Add R619, R620, R621 R619 1 2 0_0402_5% 2 0_0402_5% R620 1 R621 1 2 0_0402_5% CL_CLK1 CL_DATA1 CL_RST1# +3V_AOAC 6 5 2 1 2 @ C78 1 1 2 0.1U_0402_10V6K 2 R81 PLT_RST# USBP13USBP13+ [13,14,28,29,30,35,37,39,5] [17] [17] WL_LED# WLAN_TRAMSIT_OFF# 2 1 54 07/16 Add for ESD's request BT_ON D S Mini Card Power Rating R84 [30] 1 WWAN_DISABLE @ C375 22P_0402_50V8J 2 Power 2 2 Q27 SI2305CDS-T1-GE3_SOT23-3 220K_0402_1% HB_5680629-SICR11 For Wireless LAN Primary Power (mA) Auxiliary Power (mA) Normal Peak Normal +3VS 1000 750 +3V 330 250 250 (wake enable) +1.5VS 500 375 5 (Not wake enable) +3V_WWAN 1 09/12 Modify JSIM1 symbol and footprint. UIM_PWR BT_OFF Q28 2N7002_SOT23-3 2 G 10K_0402_5% C77 9 8 R83 @ 47K_0402_5% 3 [14] 2 DAN217T146_SC59-3 4.7U_0805_10V4Z GND GND +3VDS @ 3 07/25 JSIM1.7 connection to SUM_DET 1 LPC_LFRAME# LPC_LFRAME# [16,28,30,32] LPC_LAD3 LPC_LAD3 [16,28,30,32] LPC_LAD2 LPC_LAD2 [16,28,30,32] LPC_LAD1 LPC_LAD1 [16,28,30,32] LPC_LAD0 LPC_LAD0 [16,28,30,32] D10 RB751V-40_SOD323-2 2 1 WLAN_TRAMSIT_OFF# [15] 2 VCC RST CLK 2 M_WXMIT_OFF# RB751V-40_SOD323-2 1 UIM_PWR UIM_RST UIM_CLK 18P_0402_50V8J GND VPP I/O NC 1 WWAN_TRANSMIT_OFF# 1 UIM_VPP UIM_DATA SIM_DET [18] 3 1 2 3 C76 UIM_VPP D9 CONN@ JSIM1 [39] +3V_WWAN 2 D8 CH2 CH3 @ S DIO(BR) NUP4301MR6T1 TSOP-6 5 6 7 4 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 R85 10K_0402_5% +3V_WWAN 4 1 Vp 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 +3VDS D Vn 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 GND1 GND2 BELLW_80003-1023 CONN@ 3 CH1 CH4 3 G 2 S 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 1 U5 +3V_AOAC JMINI2 WLAN_WAKE# PLT_RST# CLK_PCI_DEBUG CLK_PCI_DEBUG [17] [17] 68 69 WLAN 2 0_0402_5% @ R67 1 2 @ 0_0402_5% PCH_PCIE_WAKE# Q69 2N7002KW_SOT323-3 [15] R568 1 KBC_WAKE# [14] change by HP requirement 1 08/07 Add JMINI2.1 net name. Add R568 and connection R586.1 to KBC_DS3_EN 10/16 Change R568.1 connection to KBC_WAKE#. Delete R64 +3VS +3V_WWAN UIM_RST UIM_CLK UIM_DATA UIM_PWR E WLAN 2 G R65 1 2 1 D S 10K_0402_5% 2 1 0.1U_0402_10V6K 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 GND1 GND2 2 T128 @ PAD 09/10 Delet T128 AUDIO0 AUDIO1 AUDIO2 AUDIO3 IUM_RFU UIM_RESET UIM_CLK UIM_DATA UIM_PWR NC GNSS0 GNSS1 GNSS2 GNSS3 GNSS4 NC NC NC NC NC COEX3 COEX2 COEX1 SIM_DET SUSCLK 3P3VAUX 3P3VAUX 3P3VAUX GND_WWAN RESERVED RESERVED GND USB3_TXUSB3_TX+ GND USB3RXUSB3RX+ GND NC NC GND NC NC GND NC NC GND ANTCTL0 ANTCTL1 ANTCTL2 ANTCTL3 RESET# PEDET GND GND OC_USB3 1 0.01U_0402_16V7K WWAN_DET#_PCH 13 15 WLAN_WAKE# 17 WWAN_RSVD2 19 09/10 Delet T126 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 PLT_RST# 61 NGFF_WWAN_PEDET @T134 PAD @ T134 63 11/06 Change JMINI3.65 connection to GND. 65 67 NGFF_WWAN_USB3_OC @T135 PAD @ T135 WWAN_DET#_PCH 11/06 Change JMINI3.13 connection to signal WWAN_DET#_PCH WWAN_FULL_PWR M_WXMIT_OFF# WW_LED# @ 39P_0402_50V8J 08/07 Add R567 and connection R567.1 to WLAN_WKAE# 10/16 Install R567 10/24 Delete R567 [17] 2 4 6 8 10 C71 @ 39P_0402_50V8J USBP12+ USBP12- CONN@ GND 3P3VAUX GND 3P3VAUX GND FULL_CARD_PWR_OFF# USB_D+ W_DISABLE1# USB_DLED1# GND C69 [17] [17] 1 1 3 5 7 9 11 WWAN_DET# C70 @ 39P_0402_50V8J 07/06 Change to NFCC connector 07/24 Modify JMINI3 pin define. 07/25 Modify JMINI3 pin define. 08/03 Modify JMINI3 footprint +3V_WWAN JMINI3 [13] C +3V_WWAN D A WWAN 3 R457 1 7W 07/19 Delete C79 200K_0402_5% 2 R458 1 0_0402_5% 2 WLAN_DISABLE [30] 11/06 Change R458 to 0ohm 1 07/19 Change power rail to +3VDS 10/25 Delete R89 08/01 Q68 and R459 uninstall 11/06 Delete Q68, R459 R90 1K_0402_5% 2 07/31 modify Q4A circuit. 08/03 Q4.2 connection to BT_ON 07/31 Install Q29 and Q31 D 1 1 3 1 10/24 Add PD R618 10/25 Delete R618 +3VDS Q30 AO3413L_SOT23-3 2 Q4B 2N7002DW T/R7_SOT-363-6 5 1 4 WL_LED C86 3 S 1 0.1U_0402_16V4Z Q4A 2N7002DW T/R7_SOT-363-6 2 BT_ON 07/19 Delete C85 +3V_AOAC [39] 6 WL/BT_LED# G 3 WL/BT_LED# 47K Q29 DTA114YKAGZT146_SOT23-3 2 WL_LED# 10K 2 +3VS 4 4 2 WW_LED# 10K WL_LED R94 1 2 100K_0402_5% 3 47K Q31 DTA114YKAGZT146_SOT23-3 Compal Secret Data Security Classification +3VS Issued Date 2012/03/23 Deciphered Date 2010/03/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D Compal Electronics, Inc. WWAN/NAND mini Document Number Rev 0.5 LA-9241P Thursday, December 20, 2012 E Sheet 25 of 56 5 4 3 2 1 Notes: Keep PVDD supply and speaker traces routed on the DGND plane. Keep away from AGND and other analog signals +AVDD_CODEC +3VS +3VS If Sense_A total length is greater than 6 inches, chagne C12 to 0.1uF PLACE CLOSE TO U1 PIN 13 Place AVDD ,PVDD,and DVDD capacitor close to Codec +5VS RA3 1 2 2.49K_0402_1% +AVDD_CODEC D D 1 RA9 HDA_BITCLK_AUDIO @ [13] [13] HDA_BITCLK_AUDIO 6 HDA_SDOUT_AUDIO HDA_SDOUT_AUDIO 5 [13] [13] [22] [22] 2 HDA_SDI0 33_0402_5% HDA_RST_AUDIO# HDA_SDI0 HDA_RST_AUDIO# [30] 10 HDA_SYNC_AUDIO HDA_SYNC_AUDIO 1 RA11 SDIN_CODEC 8 11 2 EAPD_L DH1 RB751V-40_SOD323-2 9/20 Change to commond part. 2 10K_0402_5% RA27 1 +3VS 47 1 100_0402_5% D_MIC_CLK D_MIC_CLK_L_C RA12 2 1 0_0402_5% D_MIC_DATA RA14 2 D_MIC_DATA_C 10/11 Change RA14 to 0 ohm. REC_MUTE_LED_CTRL MUTE_LED_CNTR MUTE_LED_CNTR DVDD SENSE_A SENSE_B HP0_PORTA_L HP0_PORTA_R VREFOUT_A HDA_BITCLK HP1_PORTB_L HP1_PORTB_R HDA_SDO HDA_SYNC PORTC_L PORTC_R VREFOUT_C/GPIO4 HDA_SDI HDA_RST# PORTE_L PORTE_R 2 4 48 46 PORTF_L PORTF_R EAPD SPK_PORTD_+L SPK_PORTD_-L DMIC_CLK/GPIO1 DMIC0/GPIO2 SPK_PORTD_+R SPK_PORTD_-R SPDIFOUT0/GPIO3 DMIC1/GPIO0/SPDIFOUT1 MONO_OUT 1 2 [39] PVDD1 PVDD2 1 EC_MUTE# D_MIC_CLK D_MIC_DATA DVDD_IO @ 33_0402_5% HDA_BITCLK_AUDIO [13] C 9 CA8 22P_0402_50V8J 1 2 2 AVDD1 AVDD2 10K_0402_5% RA16 CA15 4.7U_0603_6.3V6K 36 1 2 35 Place close to Codec 7 42 49 CAP+ PCBEEP VREFFILT CAP2 VVREG(+2.5V) CAP- 2 27 38 AVSS1 AVSS2 AVSS3 PAD 1 45 39 2 13 14 1 2 1 2 SENSE_A SENSE_B 28 29 23 DOCK_HP_L_CODEC DOCK_HP_R_CODEC 31 32 1 2 SENSE_A CA1 SENSE_B RA4 CA13 PLACE CLOSE TO U1 PIN 14 SENSE_A SENSE_B 1 2 1000P_0402_50V7K 1 2 2.49K_0402_1% 1 +AVDD_CODEC 2 1000P_0402_50V7K If Sense_B is un-used, then pull high Sense_B to AVDD by 10Kohm resistor @ [27] [27] [27] [27] External MIC Combo Jack HP_OUT_L HP_OUT_R HP_OUT_L HP_OUT_R 19 20 24 EXT_MIC_L [27] EXT_MIC_JACK [27] VREFOUT_MIC_JACK [39] [39] 07/06 Delete MIC_SENSE# circuit Headphone [27] 15 16 C 17 18 DOCK_LI_L_CODEC DOCK_LI_R_CODEC 40 41 SPKL+ SPKL- 44 43 SPKR+ SPKR- DOCK_LI_L_CODEC DOCK_LI_R_CODEC SPKL+ SPKL- [27] [27] SPKR+ SPKR- [27] [27] [27] [27] Internal SPKR(front stereo speaker) 25 12 2 MONO_INR 1 MONO_IN 0.1U_0402_25V6 CA14 21 22 34 37 07/06 Delete MUTE LED circuit DVSS PVSS 2 CA12 10U_0603_6.3V6M 3 DVDD_CORE 26 30 33 92HD91B2X5NLGXWCX8_QFN48_7X7 09/20 Delete RA13, CA20 1 2 1 2 1 2 CA19 10U_0603_6.3V6M 1 1 CA11 10U_0603_6.3V6M UA1 CA10 0.1U_0402_25V6 1 CA5 10U_0603_6.3V CA9 0.1U_0402_25V6 2 1U_0402_6.3V6K CA18 2 CA21 4.7U_0603_6.3V6K 2 1 CA7 1U_0402_6.3V6K CA2 1 1 CA6 0.1U_0402_25V6 1 CA16 4.7U_0603_6.3V6K 2 CA3 1U_0402_6.3V6K 0.1U_0402_25V6 CA4 0.1U_0402_25V6 07/23 Delete RA7 CA8,CA10 near UA5 PIN45 CA9,CA21 near UA5 PIN39 1 2 09/03 Change UA1 P/N B B Place C209,C210,CA87,CA89 close to Codec 1 +AVDD_CODEC +5VS 2 1 @ 2 0.1U_0402_25V6 HDA_SPKR SB Beep HDA_SPKR 2 QA1A DMN66D0LDW-7_SOT363-6 1 RA19 10K_0402_5% 2 CA26 0.01U_0402_16V7K 1 2 0_0805_5% 3 VIN C88 680P_0603_50V7K 07/20 HP's request. GND 1 2 HPA01085DBVR SOT23 5P 1 2 4 BYPASS EN 10K_0402_5% 1 [13] 2 RA20 CA31 0.1U_0402_25V6 2 2 1 1 1 C87 CA29 10U_0805_10V6K 2 100K_0402_5% 5 VOUT 6 Q75 RA28 10K_0402_5% 1 @ 2 0.1U_0402_25V6 UA2 W=40Mil 680P_0603_50V7K MONO_IN 1 1 @ 2 0.1U_0402_25V6 RA21 1 2 2 CA30 1 2 CA27 +AVDD_CODEC RA18 CA22 2 0.1U_0402_25V6 S 1 CA25 1 1 1 @ 2 0.1U_0402_25V6 3 1 @ 2 0.1U_0402_25V6 CA24 2N7002KW_SOT323-3 REC_MUTE_LED_CTRL 2 G 2 CA23 D RA17 10K_0402_5% [38] CA28 0.1U_0402_25V6 1 REC_MUTE_CTRL_KB A A GND GNDA RA53 need under or near UA5 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 Deciphered Date 2011/06/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Audio IDT 92HD91 Size Document Number Custom Date: Rev 0.5 LA-XXXXP Thursday, December 20, 2012 1 Sheet 26 of 56 5 4 3 2 RA22 Speaker Connector [26] VREFOUT_MIC_JACK JSPKR1 C89 07/16 Delete DA1 for ESD's request 2 2 EXT_MIC_L2 EXT_MIC_L2 [39] 1 CA36 220P_0402_50V7K 2 2 3 2 3 2 3 2 D 3 DA2 @ 1 1 1 RA24 @ DA3 YSDA0502C C/A SOT-23 1 2 1 BK1608HS601-T_2P CA35 CA34 EXT_MIC_JACK 1 ACES_50273-0040N-001 CONN@ 1 RA26 LA3 [26] 1 2 CA33 RA23 1 2 CA32 1 2 2 3.3_0402_5% 3.3_0402_5% 3.3_0402_5% 3.3_0402_5% RA25 1 2 1 2200P_0402_50V7K 1 2200P_0402_50V7K 2 2200P_0402_50V7K 2200P_0402_50V7K D 1 2.2K_0402_5% G6 G5 4 3 2 1 1U_0402_6.3V6K 6 5 4 3 2 1 SPKR+ SPKRSPKL+ SPKL- SPKR+ SPKRSPKL+ SPKL- 2 [26] [26] [26] [26] 1 07/16 Change P/N for ESD's request 07/20 Change P/N for ESD's request YSDA0502C C/A SOT-23 7/13 Move to small board Need place near Audio Codec (UA5) DOCK Audio +AVDD_CODEC C 8 C DLINE_OUT_R [33] G 1 CA39 220P_0402_50V7K 2 C93 1100K_0402_5% 2 BK1608HS601-T_2P 1 1 2 CA40 220P_0402_50V7K 2 15P_0402_50V8J U6B 5 10/11 Change C95 to 0.47U X5R 100K_0402_5% CC55 R105 2.2U_0402_6.3V6M C95 CC53 1 2 DOCK_LI_L_CODEC 6.2K_0402_1% 1 2 2.2U_0402_6.3V6M B 6.2K_0402_1% 1 2 2.2U_0402_6.3V6M [33] DOCK_LINE_IN_R [33] 2 2 1 BK1608HS601-T_2P 1 R99 OUT 2 1 0.1U_0402_16V7K C97 1 2 7 +VREF_EQ TLV2462CDR_SO8 IN- 0.47U_0603_16V7X 1 DOCK_LINE_IN_R 2 10K_0402_5% + 6 B C96 68P_0402_50V8J 2 2 @ R107 2K_0402_5% 2 R106 @ 2K_0402_5% 1 LA8 R104 1 DOCK_LI_R_CODEC DOCK_LINE_IN_L R102 CC54 1 2 1 [26] EXT_MIC_JACK DOCK_LINE_IN_L 2 10/11 Change R102 and R104 to 1% [26] +AVDD_CODEC 100K_0402_5% R103 2 20K_0402_1% R101 2 20K_0402_1% R100 +AVDD_CODEC R96 1 8 2 1 1 2 R98 30_0402_1% 150U_B2_6.3VM_R45M IN- P 1 1 [33] [26] 1 DOCK_HP_R_CODEC + [26] 2 DLINE_OUT_L EXT_MIC_L TLV2462CDR_SO8 BK1608HS601-T_2P LA7 C94 1 1 1 1U_0603_16V7 G 2 2 MIC_OUT 4 1 2 R97 30_0402_1% 1 1 2 150U_B2_6.3VM_R45M C92 0.01U_0402_16V7K LA6 C90 OUT - 2 1 DOCK_HP_L_CODEC + [26] + 4 10/11 Change R97 and R98 to 1% C91 2 2 P U6A 3 +VREF_EQ 07/06 Change C91 and C94 to 2.2uF as spec 10/11 Change C91 and C94 to 150u 10/11 Non install R106 and R107 R167 SENSE_B 1 2 20K_0402_1% SENSE_A R108 39.2K_0402_1% 3 2 20K_0402_1% R109 6 2 07/23 Combine with QA1B 11/05 Delete R174, QA1B. HP_SENSE# connection to R167.1 [26] [26] 1 HP_SENSE# 1 [39] Q6A 10/11 Change to AGND 2 2N7002DW-T/R7_SOT363-6 [33] 5 LINE_IN_SENSE 4 1 1 DOCK_HPS# 1 [33] 2N7002DW-T/R7_SOT363-6 Q6B 2 100K_0402_5% R111 2 100K_0402_5% R110 A A 10/11 Change to AGND 10/11 Change to AGND Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 Deciphered Date 2012/10/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 5 4 3 2 Audio SPK Conn/Jack/MIC Document Number Rev 0.5 LA-9241P Thursday, December 20, 2012 1 Sheet 27 of 56 4 3 R123 NC NC NC TPM_XTALO TPM_XTALI 1 @ 1 3 12 T108 PAD @ T109 PAD @ 1 2 [11,12,13,16,38,5] [11,12,13,16,38,5] 1 R120 @ 2 R118 2 C102 22P_0402_50V8J 1 2 33_0402_5% 4 6 7 8 DDR_XDP_WAN_SMBCLK DDR_XDP_WAN_SMBDAT +3VS CLK_PCI_TPM ACCEL_INT# 1 10K_0402_5% 2 3 R121 0_0402_5% Vdd_IO INT2 INT1 VDD SCL/SPC SDA/SDI/SDO SDO/SA0 CS GND GND RES RES RES RES NC NC +3VS 9 11 14 5 12 10 13 15 16 C103 0.1U_0402_16V7K HP3DC2 @ [14] 10/24 change ACCEL_INT# connection to U9.11 U9 R116 4.7K_0402_5% R117 9635@ 4.7K_0402_5% 2 6 D ACCEL_INT# +3VS 2 1 1 14 13 LPC_PD#_TPM BADD 1 NC GPIO 1 1 2 2 C104 10U_0603_6.3V6M SLB9656TT1.2_TSSOP28 07/26 Change U11 symbol and P/N to SLB9656. 0_0402_5% R124 @ 0_0402_5% 2 2 2 2 4.7K_0402_5% R122 9635@ 0_0402_5% NC NC 28 9 8 2 1 R119 @ SLB9656TT1.2 RH219 10K_0402_5% R115 9635@ 4.7K_0402_5% NC TESTB1/LRESET# TEST1 LCLK LFRAME# LRESET# SERIRQ TEST PP 1 1 +3VS PLT_RST# +3VS 1 CLK_PCI_TPM [16,25,30,32] LPC_LFRAME# [13,14,25,29,30,35,37,39,5] PLT_RST# [16,30,32] SIRQ Base I/O Address 0 = 02Eh * 1 = 04Eh 0.1U_0402_16V4Z 2 21 22 16 27 PM_CLKRUN#_TPM 15 2 7 [15] LAD0 LAD1 LAD2 LAD3 GND GND GND GND LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 4 11 18 25 [16,25,30,32] [16,25,30,32] [16,25,30,32] [16,25,30,32] 26 23 20 17 LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 2 C101 VDD VDD VDD VDD U11 D +3VS 2 1 2 1 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 1 ACCELEROMETER R114 0_0402_5% 9635@ 5 C98 2 R113 0_0402_5% 9656@ 0_0402_5% 9656@ R112 24 19 10 1 0.1U_0402_16V4Z 1 1 C99 C100 2 +3VDS 1 TPM1.2 +3VS 1 +3VS 1 5 9635@ 18P_0402_50V8J 2 C105 1 2 1 1 TPM_XTALI 2 +3VS R127 2 C Y1 9635@ 32.768KHZ_12.5PF_FC-135 TPM_XTALO C106 1 10M_0402_5% LPC_PD#_TPM 07/06 Delete LED1 1 @ 2 R126 9635@ 4.7K_0402_5% C 2 9635@ 18P_0402_50V8J PLT_RST# 9656@ 1 R129 2 0_0402_5% BADD R177 [14,30,32] PM_CLKRUN# 1 2 PM_CLKRUN#_TPM Finger printer 0_0402_5% 9635@ #4/15 Correct Net name. +3VS 1 C107 0.1U_0402_16V4Z 2 12/12 Add Q85 +5VS JFP1 1 3 [18] FPR_LOCK# R131 2 R130 2 1 0_0402_5% 1 0_0402_5% 1 3 5 7 9 11 USB20_N8_R USB20_P8_R FPR_LOCK# FPR_OFF_C 12/13 Change netname to FPR_OFF_C Q85 2N7002KW_SOT323-3 1 3 5 7 9 11 2 4 6 8 10 12 2 4 6 8 10 12 B ACES_85203-0602N-10 CONN@ 3 FPR_OFF S [16] D B USBP8USBP8+ 2 2 G [17] [17] D11 7/24 Modify pin define. 9/12 Modify JFP1 footprint 9/18 Modify JFP1 pin define 9/26 Modify JFP1 pin define to follow ME request. SCA00000U10 07/16 Change P/N for ESD's request 1 YSLC05CH_SOT23-3 A A Compal Secret Data Security Classification 2012/03/23 Issued Date Deciphered Date 2006/09/25 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Compal Electronics, Inc. TPM/Gsensor Document Number Rev 0.5 LA-9241P Thursday, December 20, 2012 Sheet 1 28 of 56 1 2 3 4 5 W=60mils +3VM_LAN +3VDS 2 R376 10K_0402_5% 2 2 2 1 C110 22U_0603_6.3V6K 1 C109 0.1U_0402_16V4Z 1 C108 1U_0402_6.3V6K 1 10/26 Change R376 to 10k. Change R376.1 connection to +3VDS [34] SLP_LAN SLP_LAN A 6 A 07/20 Change C110 to 22UF 2 SLP_LAN# 1 [14,30] AMT@ Q7A 2N7002DWH_SOT363-6 07/20 Change location to Q7A 07/23 Change R128 to 4.7K ohms Q63 LAN_ACT# +3VM_LAN R154 1 R155 1 2 10K_0402_5% 2 10K_0402_5% @ @ C 2 3 LED_LINK_LAN# LAN_ACT# 26 27 25 T110 T111 LAN_JTAG_TMS LAN_JTAG_TCK 32 34 33 35 XTAL2 XTAL1 9 10 R158 1 2 1K_0402_5% 30 R159 1 2 3.01K_0402_1% 12 SMB_CLK SMB_DATA VDD3P3_IN LAN_DISABLE_N VDD3P3_4 VDD3P3_15 VDD3P3_19 VDD3P3_29 LED0 LED1 LED2 VDD0P9_8 VDD0P9_11 VDD0P9_16 LANWAKE_N VDD0P9_22 JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TCK VDD0P9_37 VDD0P9_40 VDD0P9_43 VDD0P9_46 VDD0P9_47 XTAL_OUT XTAL_IN TEST_EN CTRL_0P9 LAN_MDIP3 LAN_MDIN3 6 +3VM_LAN 1 2 47K_0402_5% R145 1 5 +3VM_LAN 8 11 16 2 C114 R144 1 2 10K_0402_5% R150 1 LED_LINK_LAN# 1 @ 680P_0402_50V7K 4 15 19 29 MDO3MDO3+ MDO2+ MDO2MDO1+ MDO1MDO0+ MDO0- 07/11 Delete R140, R142 by HP request 2 300_0603_5% 2 C118 1 2 3 4 5 6 7 G2 8 G1 9 10 11 12 13 14 B 16 15 ACES_87212-14G0 CONN@ C117 1 2 1000P_0402_50V7K D12 @ C505 1 2 10U_0603_6.3V6M SCA00000U10 YSLC05CH_SOT23-3 11/02 Add C505 22 07/16 Change P/N for ESD's request 37 40 43 46 47 7 +1.05VM_LAN [17] SHI00004C00 L15 1 2 4.7UH +-5% 1008HC-472EJFS-A DELTA_1008HC-472EJFS-A_2P 49 C504 1 LED_LINK_LAN#_R LED_LINK_LAN#_R 3 LED_LINK_LAN# Q34 2N7002_SOT23-3 1 2 2 @ 07/06 Add by HP request 1 C350 47U_0805_4V6M CLARKVILLE 1 C373 0.1U_0402_16V4Z CTRL_0P9 23 24 1 @ 680P_0402_50V7K 10U_0603_6.3V6M RBIAS LAN_MDIP2 LAN_MDIN2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2 300_0603_5% 2 RSVD1_VCC3P3 20 21 JP4 R138 1 LAN_ACT# 3 MMBT3904_SOT23-3 3LANWAKE#_R 10/26 Delete R153 [33] SVR_EN_N 28 31 LAN_MDIP1 LAN_MDIN1 1 2 0_0402_5% @ MDI_PLUS3 MDI_MINUS3 2 4.7K_0402_5% 1 R569 1 PERp PERn 17 18 +3VM_LAN S R128 1 MDI_PLUS2 MDI_MINUS2 LAN_MDIP0 LAN_MDIN0 D 41 42 PETp PETn 13 14 RJ-45 CONN. R625 1 2 0_0402_5% LED_LINK_LAN_DOCK# 2 [33] C 2 G LANWAKE# KBC_WAKE# LAN_DIS# 38 39 LAN_SMBCLK LAN_SMBDATA +3VM_LAN Delete R151, R152 by HP request Add R569 and connection R569.1 to KBC_DS3_EN Change R569.1 connection to KBC_WAKE# Add Q63 [18] [25,30] [18] PCIE_PRX_DTX_P6_C PCIE_PRX_DTX_N6_C MDI PCIE_PTX_C_DRX_P6 PCIE_PTX_C_DRX_N6 [16] LAN_SMBCLK [16] LAN_SMBDATA 2 0.1U_0402_10V7K 2 0.1U_0402_10V7K MDI_PLUS1 MDI_MINUS1 PCIE [17] [17] C115 1 C116 1 PE_CLKP PE_CLKN SMBUS PCIE_PRX_DTX_P6 PCIE_PRX_DTX_N6 MDI_PLUS0 MDI_MINUS0 LED [17] [17] CLK_REQ_N PE_RST_N JTAG CLK_PCIE_LAN CLK_PCIE_LAN# 2 B 07/11 08/07 10/16 10/25 44 45 [15] [15] E B 48 36 07/11 Delete R135 by HP request 07/11 Delete R139 by HP request CLK_PCIE_LAN_REQ1# PLT_RST# C [15] [13,14,25,28,30,35,37,39,5] 2 U10 R136 10K_0402_5% 1 +3VM_LAN LAN_DIS# 10/26 Connect Q34.3 to LED_LINK_LAN_DOCK# with R625, and delete LED_LINK_LAN_DOCK# connection to Q34.1. Delete R157 and connect Q34.1 and signal LED_LINK_LAN#_R. 11/02 Reserve C504. Change C350 to 47u. TS1 2 0.1U_0402_16V4Z C390 1 2 0.1U_0402_16V4Z MDO0MDO1+ MDO1- 9/27 Change Y2 to 3225 package. MDO2+ MDO2MDO3+ MDO3- 2 0.1U_0402_16V4Z C392 1 2 1U_0402_6.3V4Z 07/23 Add C389, C390, C391, C392. MDO0+ [33] MDO0- [33] MDO1+ [33] MDO1- [33] MDO2+ [33] MDO2- [33] 4 LAN_MDIP1 5 LAN_MDIN1 6 LAN_MDIP2 7 LAN_MDIN2 8 +V_DAC 9 +V_DAC 10 LAN_MDIP3 11 LAN_MDIN3 12 TX1- TDCT1 TDCT2 TXCT1 TXCT2 TD2+ TX2+ TD2- TX2- TD3+ TD3- TX3+ TX3- TDCT3 TXCT3 TDCT4 TXCT4 TD4+ TX4+ TD4- TX4- 24 MDO0+ 23 MDO0- 10/25 Delete R160, R161, R162, R163. Add RP12 RP12 5 6 7 8 22 21 20 MDO1+ 19 MDO1- 18 MDO2+ 17 MDO2- 4 3 2 1 07/23 Change C121 to 1000pF 75_1206_8P4R_5% 2 1 1 16 15 14 MDO3+ 13 MDO3- L16 D13 @ [33] MDO3- [33] 2 1 C122 0.1U_0402_16V4Z 2 C123 4.7U_0603_6.3V6K D YSLC05CH_SOT23-3 350UH_NA0069RLF SP050006Y00 100UH_SSC0301101MCF_0.18A_20% 07/16 Change P/N for ESD's request Compal Secret Data Security Classification MDO3+ 2 SCA00000U10 Issued Date 2012/03/23 Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 C121 SE120102K90 1000P_1808_3KV 2 1 IN NC OUT NC MDO0+ 2 C391 1 3 +V_DAC TX1+ TD1- 1 D C125 33P_0402_50V8J 4 2 25MHZ 18PF +-20PPM CRG3202518 C124 33P_0402_50V8J 1 2 Y2 1 3 XTAL2 +V_DAC TD1+ 1 C389 1 XTAL1 2 2 2 0.01U_0402_16V7K 1 LAN_MDIN0 3 C120 1 LAN_MDIP0 3 4 Title Compal Electronics, Inc. Intel 82566 Nineveh Size Document Number Rev 0.5 LA-9241P Date: Thursday, December 20, 2012 5 Sheet 29 of 56 2 2 09/10 Delete R216 07/18 R216 non install by HP request. A PVT_MISO PCH_SPI_CS0# [16] PCH_SPI_SO [38] PCH_SPI_CS0# PCH_SPI_SO KSO[0..13] KSO4 KSO5 T121 @ T122 @ +3VS +3VS 4.7K_0804_8P4R_5% 1 2 3 4 8 7 6 5 [38] D44 TP_CLK TP_DATA SP_CLK SP_DATA 3 KSI[0..7] PS2_CLK 1 2 PS2_DATA RP3 BAT54CW_SOT323-3 4.7K_0804_8P4R_5% 1 2 3 4 8 7 6 5 PS2_CLK PS2_DATA KBD_DATA KBD_CLK D45 3 KBD_DATA 1 RP4 2 KBD_CLK TP_CLK [38] [38] [33] [33] SP_CLK SP_DATA PS2_CLK PS2_DATA KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 29 28 27 26 25 24 23 22 TP_CLK 35 SP_CLK SP_DATA PS2_CLK PS2_DATA 61 62 66 67 PM_CLKRUN# SIRQ CLK_PCI_KBC EC_SCI# 55 57 54 76 58 84 106 14 37 119 68 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 *KSO12/GPIO5 *KSO13/GPIO6 100mA KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 *IMCLK/GPIO51 *GPIO50/KCLK *GPIO65/KDAT *GPIO46/EMCLK *GPIO47/EMDAT 07/20 Add D44 and D45 [14,28,32] [16,28,32] [15] [18] 7/13 Delete R244 PM_CLKRUN# SIRQ CLK_PCI_KBC EC_SCI# [16,25,28,32] [16,25,28,32] [16,25,28,32] [16,25,28,32] B 1 [16,25,28,32] [18,32] C188 1U_0402_6.3V6K LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0 LPC_LFRAME# KBC_SIO_RST# LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0 51 50 48 46 LPC_LFRAME# 52 KBC_SIO_RST# 53 2mA 70 LAD[3] LAD[2] LAD[1] LAD[0] LPC Bus LFRAME# LRESET# *VSS_VBAT *XTAL1 [31,47,5] S 1 2 3 4 5 6 [13,14,25,28,29,35,37,39,5] PLT_RST# 7 NMI_SMI_DBG# 8 LPC_LAD0 9 10/16 Remove current VCC1_PWRGD connection to LPC_LAD1 JP6.16. Then add a 4.7 K resistor between JP6.16 10 LPC_LAD2 and new signal VCC1_PWRGD_SUS#. 11 LPC_LAD3 12 13 07/18 change net name TX_STBY_LED# 14 07/25 change net name 8051RX_CAPLED# 08/07 Change net name 8051_RECOVER#/_NUM_LOCK_LED# 15 16 VCC1_PWRGD_SUS#12/12 Remove R611. Connect JP6.16 to VCC1_PWRGD_SUS# 17 1 2 15_0402_5% KSO0 R237 1 2 15_0402_5% 18 KSO1 R235 1 2 15_0402_5% 19 KSO3 R234 1 2 15_0402_5% 20 KSO2 R233 1 2 15_0402_5% 21 JTAG_RST# R231 22 +3VDS 23 09/25 Install R237, R235, R234, R233, R231 24 25 26 *GPIO53/PS2CLK *GPIO152/PS2DAT *GPIO11/KSO16 *GPIO130 *I2C0_DATA0 *I2C0_CLK0 *GPIO12/KSO17 *ADC_TO_PWM_OUT/GPIO41 *GPIO13 *nRESET_OUT#/GPIO121 *GPIO141/PWM3 VCC1_RST# *ADC4/GPIO62 *XTAL2 15 C187 1 LPC_LFRAME# SIRQ 2 4.7U_0805_10V4Z 93 SIO_SLP_A# 98 2 0_0402_5% N27271225 R222 1 99 100 KBC_PWR_ON 126 10/16 Change U7.125 connection to CHRG_RST, 125 U7.126 connection to KBC_WAKE# 10/23 Add R617 12/12 Delete R617, R227 124 10/17 Change R227 to 10K 09/20 Change R227 to 3K 123 10/16 Connect D21.2 to PM_APWROK. Install D21. 122 2 RB751V-40_SOD323-2 KBRST# D21 1 121 09/24 Non-install D21 FAN_PWM 120 118 KBD_PWM_LED 107 79 80 81 83 85 86 87 88 89 90 91 92 101 102 103 105 4 74 7/13 Delete R236 R238 1 H_PECI_R TACH_FAN_IN 07/18 Install R242 2 100K_0402_5% R615 1 10/18 Change R615 to 470K ohms KBD_CLK KBD_DATA 12/12 Change R615 to 100K ohms ON/OFFBTN# I2C_MAIN_DAT I2C_MAIN_CLK 109 110 I2C_BAY_DAT I2C_BAY_CLK 73 69 2 43_0402_1% SIO_SLP_A# [14,31,46] SUS_PWR_ACK [14] AC_PRES_OUT [14,35] KBC_PWR_ON [34,44] KBC_WAKE# [25,29] CHRG_RST [43] FET_A [51] PM_APWROK [14,31] FAN_PWM [24] BAT_GRNLED# [13,39] KBD_PWM_LED [38] ON/OFFBTN_KBC# [42] CHRG_ADP_DET [42] PCH_KBC_I2CDAT PCH_KBC_I2CLK ON/OFFBTN_KBC# [33,38] LID_SW# KSO17 [39] MAIN_BAT_DET# OCP_PWM_OUT [18] TRAVEL_BAT_DET# KBC_DS3_EN [45,5] TACH_FAN_IN PM_PWROK [14,5] 08/10 Change R253.2 connection to VR_ON 10/16 Change U17 pin 77 connection to VCC1_PWRGD_SUS# ON/OFFBTN# ADP_ID_CHK [50] 07/19 Delete R254, Add R549 EN_P1V5 [33,39,40,44,45] 8051_RECOVER#/_NUM_LOCK_LED# I2C_BAY_DAT I2C_BAY_CLK ON/OFFBTN_KBC# 09/12 Delete R249, R251 OCP_PWM_OUT KBC_DS3_EN 09/10 Delete R253 and R549 ADP_ID_CHK 07/18 Non install R253 and install R254. VCC1_PWRGD_SUS# 09/12 Delete R256 07/18 Non install R258 and install R500 2 0_0402_5% SUSCLK_KBC KBC_XTAL2 R624 1 SUSCLK_KBC [14] 10/15 Reserve R624 and connection to SUSCLK_KBC 09/10 Delete R258, R500 and change pin69 netname to KBC_XTAL2 12/12 Install R624 FET_B [51] AMBER_BATLED# [39] TX_STBY_LED# 07/18 R436 change to 1K 09/21 R436 change to8051RX_CAPLED# 100K PD 2 100K_0402_5% R436 1 1 2 300_0402_5% TRAVEL_BAT_DET# +3VDS LID_SW# 09/10 Delete R271 [38] PVT_CS# 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% B R295 1 2 100K_0402_5% R493 1 2 100K_0402_5% R546 1 2 100K_0402_5% 07/18 Add R546 by HP request. 07/25 Change net name 08/07 Change net name 09/07 Delete TX_STBY_LED# offpage symbol +3VDS 4.7K_0804_8P4R_5% 1 8 I2C_MAIN_CLK 2 7 I2C_MAIN_DAT 3 6 I2C_BAY_CLK 4 5 I2C_BAY_DAT iSCT_LED# [39] 10/16 change R436.2 connection to +3VDS ADP_A_ID [50] TRAVEL_BAT_DET# [42] LID_SW# [22,38,39] ADP_EN [43] RP5 +3VDS AVSS 116 *GPIO163 113 *nBAT_LED#/GPIO154 115 *nPWR_LED#/GPIO156 114 10/16*GPIO155 Change EC pin 41 and R436.1 joint point connection to iSCT_LED# 41 iSCT_LED# *GPIO206 42 N27271143 R270 *ADC2/GPIO60 65 GPIO33 64 *GPIO27 63 GPIO35 40 AVCC R268 R439 R440 R441 R442 R443 R444 R445 10/12 Change R276.1 connection netname to RSMRST#_EC 07/18 Install R277 08/10 Change R277.1 connection to VR_ON 09/12 Delete R278 09/23 Change netname to PWR_GD 2 2200P_0402_50V7K C190 1 C192 1 A CPPWR_EN [39] ACES_50238-02471-002 +1.05VS CONN@ H_PECI [5] 08/07 Change JP6 footprint SLP_S3# [14,31,34,45] 8051_RECOVER#/_NUM_LOCK_LED# [38] 10/18 Change R610 to 470 ohms 7/13 Reserve R541 and R542 for NFC function PM_RSMRST# [14]7/19 Install R541, R542 NFC_RX [39] 7/26 Add R561, R562. Non install R541, R542 NFC_TX [39] 9/03 Non install R561, R562. install R541, R543 9/12 Delete R561, R562. PCH_KBC_I2CDAT [16,35] PCH_KBC_I2CLK [16,35] KBC_PROC_HOT# [24,5] EC_MUTE# [26] +3VDS 09/10 Delete R241 and connect EC_MUTE# to KBC.91 directly. MAIN_BAT_DET# [42] Delete R242 and connect MAIN_BAT_DET# to KBC.92 directly. TACH_FAN_IN [24] 10/16 Change R245.1 connection to KBC_WAKE# PLT_DET 2 100K_0402_5% KBC_WAKE# R245 1 10/16 Add a 680K PD for U7.102. Change U7.102 connection to PLT_DET. 2 10K_0402_5% ADP_EN R246 1 KBD_CLK [33] 10/16 Delete R247 12/12 Change R248 to 100k ohms KBD_DATA [33] 2 100K_0402_5% VCC1_PWRGD_SUS# R248 1 ON/OFFBTN# [14,5] 07/25 Change net name 10/16 Change R248 to 200k ohms. Change ADP_PRES [50] R248.1 connection to VCC1_PWRGD_SUS# 08/07 Change net name 08/10 Add VCC1_PWRGD off page symbol 10/26 Delete VCC1_PWRGD off page symbol 2 100K_0402_5% TX_STBY_LED# R255 1 2 100K_0402_5% 8051RX_CAPLED# R257 1 2 10K_0402_5% KBD_PWM_LED R259 1 I2C_MAIN_DAT [42,43] 2 100K_0402_5% KBC_PWR_ON R263 1 I2C_MAIN_CLK [42,43] PWR_GD PWR_GD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 G1 G2 8051_RECOVER#/_NUM_LOCK_LED# 10/12 Add R610. Change U17.85 connection netname to RSMRST#_EC 2 470_0402_5% RSMRST#_EC R610 1 2 0_0402_5% R541 1 2 0_0402_5% R542 1 2 10K_0402_5% R252 1 10/16 Delete R239, R240 PCH_KBC_I2CDAT PCH_KBC_I2CLK KBC_PROC_HOT# 111 112 108 59 75 60 78 77 38 CLK_PCI_DEBUG_KBC 45 VSS VSS VSS VSS VSS VSS VSS 11 47 56 104 82 117 36 7/13 Delete R269 *ADC3/GPIO61 *GPIO36 *PVT_SCLK/GPIO153 *SHD_SCLK/GPIO122 *GPIO31 *GPIO127 *IMDAT/GPIO52 GPIO147 GPIO151 *ADC1/GPIO57 *ADC0/ADC_TO_PWM_IN/GPIO56 MEC1322-NU VTQFP 128P *PWRGD PCH_SPI_CLK *GPIO23/I2C1_DAT0 *GPIO22/I2C1_CLK0 *GPIO21/I2C2_DAT0 *GPIO20/I2C2_CLK0 *GPIO105/FAN_TACH1 *GPIO140/TACH2PWM_IN *GPIO45/A20M/PVT_CS#1 *GPIO110 72 [16] OUT1/RSMRST# *GPIO162/RXD *GPIO165/TXD/HSD_CS1# Power Mgmt/SIRQ 07/18 Non install R266 09/10 Delete R266, netname MAIN_BAT_DET# PVT_SCLK *GPIO30 VREF_PCEI *GPIO131/PECI_DATA *GPIO7/KSO14 *GPIO10/KSO15 *I2C0_DATA1 *I2C0_CLK1 09/10 Delete R262, R264. Change pin 71 netname to KBC_XTAL1 71 12/12 Delete R605 KBC_XTAL1 07/18 Non install R264 and install R262 09/25 Reserve R605 2 2200P_0402_50V7K C189 1 A_GND 1 2 N27271393 39 [43] VOLTAGE_ADC 1 R267 300_0402_5% [51] LATCHED_ALARM 08/03 Change R437 to 33 ohms 07/24 Change net name 2 2 33_0402_5% PCH_SPI_CLK_EC 3 PCH_SPI_CLK R437 1 30 WLAN_DISABLE [25] WLAN_DISABLE 31 [43] CHRG_ADP_DET 32 TP_DATA [38] TP_DATA 33 WWAN_DISABLE [25] WWAN_DISABLE 34 SLP_LAN# [14,29] SLP_LAN# 43 1 2 N27271121 [43] CURRENT_ADC 2300_0402_5%N27271128 44 R272 1 [50] OCP_A_IN R273 300_0402_5% *GPIO44 *GPIO135/KBRST *GPIO34/TACH2PWM_OUT *GPIO133/PWM0 *GPIO136/PWM2 Access Bus Interface CLKRUN# SER_IRQ PCI_CLK EC_SCI# JP6 [14] [14] Layout note: 2vias to GND CAP *GPIO145 *GPIO157/BC_CLK *GPIO160/BC_DAT *GPIO161/BC_INT# *GPIO24/I2C3_CLK0 *GPIO25/I2C3_DAT0 *GPIO66 BAT54CW_SOT323-3 +RTCVCC 2 [38] 21 20 19 18 17 16 13 12 10 9 8 7 6 5 NMI_SMI_DBG# [15] 7/13 Add R543 9/12 Delete R543 Miscellaneous PAD PAD KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 FLDATAOUT *PVT_MOSI/GPIO54 FLCS0# *PVT_CS0#/GPIO146 FLDATAIN *PVT_MISO/GPIO164 Keyboard/Mouse Interface 7/13 Delete R496,R497,R498,R499 128 127 97 96 95 94 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 [16] 7/13 Delete R224 and R460, beacuse no QW LED and CALC LED 7/13 Delete R220, R223 and short to make layout easier PCH_SPI_SI PCH_SPI_SI SMSC_1322-NU_TQFP-128P PVT_CS# U17 [16] 3 BATLOW# *VBAT 10/16 Delete R218 07/18 Non install R219 and install R218 09/10 Delete R219 B+ Q84 2N7002KW_SOT323-3 1 +RTCVCC 5 LPC Debug Port 10/16 Delete C186 7/13 Change by HP request PVT_MOSI 100K_0804_8P4R_5% 09/12 Change RP1 and RP2 to 100K ohms. 4 Add by HP request. Change R537 to 10K Change R540 to 4.7K Delete R540, Q74 Add Q84 +3VS D 2 49 1 *JTAG_RST# 2 General Purpose I/O Interface 1 07/09 07/10 08/03 10/16 12/12 10/16 Change R215.2 to GND 07/18 R215 install by HP request. 1 2 JTAG_RST# R215 100K_0402_5% 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1 Layout note: Close to PIN119 C185 2 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1 Layout note: Close to PIN106 C184 KSI7 KSI6 KSI5 KSI4 2 Layout note: Close to PIN84 C183 8 7 6 5 1 Layout note: Close to PIN58 C182 RP2 2 0.1U_0402_16V4Z 100K_0804_8P4R_5% 1 2 3 4 1 Layout note: Close to PIN37 C181 KSI0 KSI1 KSI2 KSI3 3 +3VDS Layout note: Close to PIN14 C180 1 2 3 4 C179 RP1 8 7 6 5 0.1U_0402_16V4Z Layout note: Close to PIN68 07/20 Rearrange pin define for layout smooth. G 1 7/13 Change by HP request +RTCVCC +3VDS 07/23 Change C322 to 100pF 10/16 Delete C322 A_GND C191 1 2 2200P_0402_50V7K 1 R281 1 1 1 1 1 1 1 1 1 CPPWR_EN PM_PWROK RSMRST#_EC ADP_ID_CHK FET_A FET_B KBC_PROC_HOT# OCP_PWM_OUT KBC_DS3_EN R274 R275 R276 R278 R279 R280 R446 R447 R265 CHRG_RST R243 1 2 2 2 2 2 2 2 2 2 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 10K_0402_5% 100K_0402_5% 2 100K_0402_5% 2 2200P_0402_50V7K 10/16 Change R243 to 100K. Change R243.1 connection to CHRG_RST. Change R243.2 connection to GND 2 0_0402_5% C487 1 @ 2 10P_0402_25V8K KBC_XTAL1 2 Layout note: ADC nets are spaced at least 20mils from any high speed switching signals to prevent cross talk that could add noise Y4 32.768KHZ_12.5PF_FC-135 1 @ C488 1 @ 2 10P_0402_25V8K KBC_XTAL2 09/10 Add C487, C488, and Y4 11/01 Uninstall Y4, C487, C488 C C PCH_SPI_CLK_EC 1 SPI ROM (16MByte ) 2 C419 33P_0402_50V8J @ PVT ROM (IN) 09/03 Change R282 to 10K +3VDS +3VDS 07/24 Add C419 for EMI request +3VDS 2 @ CH98 22P_0402_50V8J 1 2 3 PCH_SPI_HOLD# 7 08/03 Add CH114 PCH_SPI_CS0# 1 PCH_SPI_CLK 6 PCH_SPI_SI 5 R282 U18 HOLD 128M W 25Q128FVSIG SOIC8P S C Q 2 PCH_SPI_SO_R_1 2 R283 1 1 2 8 3 1 R438 2 10K_0402_5% PVT_CS# 2 PVT_SCLK 1 R616 10/16 Add R616 15_0402_5% PVT_MOSI 1 PCH_SPI_SO 5_0402_1% 128M W25Q128FVSIG SOIC8P CONN@ 08/09 Correct UH5 and &UH1 SPI ROM size 08/09 Change UH5 footprint R555 0_0402_5% 10K_0402_5% 20mils W D 2 4 7 1 6 5 VCC CONN@ VSS 4 2MB &UH2 45@ W HOLD 16M W 25Q16CVSSIG SOIC 8P S C D Q 2 PVT_MISO 16M W25Q16CVSSIG SOIC 8P 07/18 Install U18 07/25 Change U18 to scoket and add &UH2 08/09 Correct U18 and &UH2 SPI ROM size 2 1 PCH_SPI_WP# PCH_SPI_HOLD# &UH1 45@ VSS C193 CH114 @ 22P_0402_50V8J 2 CH97 0.1U_0402_16V4Z PCH_SPI_WP# [16] 07/19 Add off page symbol PCH_SPI_WP# and PCH_SPI_HOLD# 07/09 Delete 16 pin SPI ROM socket 20mils 1 [16] VCC 0.1U_0402_16V4Z 7/13 Change power rail from +3V_SPI to +3VDS 12/12 Change RH222, RH223, RH224 to 100K 2 PCH_SPI_CS0# RH222 1 @ 100K_0402_5% 2 PCH_SPI_WP# RH223 1 100K_0402_5% 2 PCH_SPI_HOLD# RH224 1 100K_0402_5% +3VDS +3VDS +3VDS 1 UH5 8 1 @ 2 +3VDS CH112 22P_0402_50V8J +3VDS 1 7/13 Delete RH220 7/13 Change power rail from +3V_SPI to +3VDS 07/23 Add CH112 for RF request 07/24 Add R555 for EMI request 2 1 R560 100K_0402_5% R559 100K_0402_5% [33,38,39] 6 8051TX_STBYLED# 2 Q77A 2N7002KDW_SOT363-6 3 1 2 D D Q77B 2N7002KDW_SOT363-6 08/07 Change net name 5 4 TX_STBY_LED# 07/25 Add Q77 and R559 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 Deciphered Date 2011/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 1 2 3 4 KBC1322 5 Rev 0.5 LA-9241P Thursday, December 20, 2012 Sheet 30 of 56 +3VS 09/03 Non install R284 2 R550 2 8 1 31.6K_0402_1% R292 2 3.3K_0402_5% 1 2 1 SLP_S3# 2 - 1 PWR_GD PWR_GD [30,47,5] 09/23 Change netname to PWR_GD LM393DR2G_SO8 C195 1000P_0402_50V7K 2 R552 1 PM_APWROK + O 2 09/11 Delete R287. Connect joint point of R286.1 and U18.1 to VR_ON 1 D41 R551 3 3.3K_0402_5% DAP202UGT106_SC70-3 R294 1 2 1M_0402_5% +1.05VS 2 30.9K_0402_1% 1 2 24.3K_0402_1% R553 R296 5 6 + P 1 R293 2 10K_0402_5% 1.75VREF - U19B O 4 +1.35VS 1 7 LM393DR2G_SO8 1 +3VS 2 76.8K_0402_1% G 8 +5VDS 1 R297 C196 3300P_0402_25V7K 1 R299 73.2K_0402_1% 2 2 07/20 Follow VBK10 PWR_GD circuit R304 1 +5VL 2 88.7K_0402_1% 1 2 R309 1 2 2 3.3K_0402_5% O 7 1 PM_APWROK [14,30] R312 1 09/23 Change netname to VGATE [47] 8 R307 1K_0402_5% 3300P_0402_25V7K 3 VGATE 2 1 3 1 R301 CH115 0.22U_0402_6.3V6K 2 1M_0402_5% C198 1 2 DAP202UGT106_SC70-3 2 1M_0402_5% +5VDS LM393DR2G_SO8 1 + P SIO_SLP_A# C199 - 2 [14,30,46] 2 U20B + - G 19.1K_0402_1% R313 D43 6 U20A O 4 1 R548 5 2 10K_0402_5% P 1 G 3.3K_0402_5% 4 1.05VM_PG 2 1 [46] 2 20.5K_0402_1% R547 1 8 R311 R310 1 RH246 4.7K_0402_5% 2 +5VDS +3VM_LAN +3V_PCH R175 3.3K_0402_5% 1 2 1M_0402_5% 1 2 1 C197 35.7K_0402_1% R306 2 1 1000P_0402_50V7K +3VDS 11/01 Change R304.1 connection to +5VL. Change R304 to 88.7k +-1% 2 [14,30,34,45] 3 P 1.5VS_PG 1 2 10K_0402_5% 1 2 1.75VREF R291 105K_0402_1% 10/31 Change R291.1 connection to +5VL. Change R291 to 105K_1% R290 +5VL 2 3.3K_0402_5% G [49] 1 U19A 4 +0.675VS 07/23 Change R286 to 10K R286 10K_0402_5% +5VDS 1 1 2 R288 76.8K_0402_1% 09/03 Change R289 to 11.5K 1 2 11.5K_0402_1% R289 +5VS 1 2 1M_0402_5% R284 @ 40.2K_0402_1% 2 2 C194 3300P_0402_25V7K R285 1 1 1 PCH_PWROK_R [14] LM393DR2G_SO8 2 0.068U_0402_10V6K 12/12 Change CH115 to 0.22uF 9/13 Modify power ok circuit 07/18 HP request Compal Secret Data Security Classification Issued Date 2012/03/23 Deciphered Date 2010/03/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Compal Electronics, Inc. POK CKT Size Document Number Rev 0.5 LA-9241P Date: Thursday, December 20, 2012 Sheet 31 of 56 1 2 Parallel Port 4 5 +5VS 10/25 Delete R318, R319, R321, R322. Add RP17 2 TO LPC47N217N +3VS RP17 D27 RB751V-40_SOD323-2 1 +5VS_PRN DSR#1 CTS#1 RI#1 DCD#1 RP13 8 7 6 5 LPTACK# LPTERR# LPTAFD# LPTSTB# 10/25 Delete R465, R466, R467, R472. Add RP14 8 7 6 5 1 2 3 4 4.7K_0804_8P4R_5% 1 2 3 4 A RXD1 R323 1 2 1K_0402_5% U22 4.7K_0804_8P4R_5% LAD0 LAD1 LAD2 LAD3 10/25 Delete R469, R470, R471, R479. Add RP16 1 2 3 4 4.7K_0804_8P4R_5% RP16 8 7 6 5 LPTSLCTIN# LPD0 LPD1 LPD2 1 2 3 4 4.7K_0804_8P4R_5% R476 1 LPTINIT# 2 4.7K_0402_5% B [33] [33] [33] [33] [33] [33] [33] [33] [33] [33] [33] [33] [33] [33] [33] [33] [33] LPTINIT# LPTSLCTIN# LPD0 LPD1 LPD2 LPD3 LPD4 LPD5 LPD6 LPD7 LPTSLCT LPTPE LPTBUSY LPTACK# LPTERR# LPTAFD# LPTSTB# LPTINIT# LPTSLCTIN# LPD0 LPD1 LPD2 LPD3 LPD4 LPD5 LPD6 LPD7 LPTSLCT LPTPE LPTBUSY LPTACK# LPTERR# LPTAFD# LPTSTB# 7 10 23 38 46 +3VS 2 1 2 4.7U_0805_10V4Z 4.7K_0804_8P4R_5% 2 1 0.1U_0402_16V4Z 10/25 Delete R484, R485, R486. Add RP18 SIO_IRQ SIO_GPIO12 SIO_GPIO10 1 0.1U_0402_16V4Z 1 2 3 4 RP18 8 7 6 5 0.1U_0402_16V4Z 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% C204 @ SIO_GPIO23 SIO_GPIO41 SIO_GPIO42 SIO_GPIO44 2 2 2 2 C203 1 1 1 1 +3VS C202 R328 R329 R330 R554 SIO_GPIO46 C201 2 4.7K_0402_5% R480 1 10/26 Delete R481 35 36 37 39 40 41 42 43 44 45 47 48 49 50 51 52 53 INIT# SLCTIN# PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 SLCT PE BUSY ACK# ERROR# ALF# STROBE# LFRAME# LDRQ# PCI_RESET# LPCPD# CLKRUN# PCI_CLK SER_IRQ IO_PME# CLOCK CLK14 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO10 GPIO11/SYSOPT GPIO12/IO_SMI# GPIO13/IRQIN1 GPIO14/IRQIN2 GPIO23 9 11 12 13 LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 14 15 LPC_LFRAME# LPC_LDRQ0# 16 17 KBC_SIO_RST# LPCPD#_SIO 18 19 20 6 PM_CLKRUN# CLK_PCI_SIO SIRQ SIO_PME# 8 CLK_SIO_14M 21 22 24 25 26 27 28 29 30 31 32 33 34 SIO_GPIO41 SIO_GPIO42 SIO_GPIO43 SIO_GPIO44 mSATA_DET# SIO_GPIO46 SER_SHD_GPIO47 SIO_GPIO10 SYSOPT SIO_GPIO12 SIO_IRQ LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 [16,25,28,30] [16,25,28,30] [16,25,28,30] [16,25,28,30] LPC_LFRAME# LPC_LDRQ0# [16,25,28,30] [16] KBC_SIO_RST# 1 2 10K_0402_5% R324 [18,30] PM_CLKRUN# [14,28,30] CLK_PCI_SIO [15] SIRQ [16,28,30] +3VS CLK_SIO_14M +3VS LPCPD#_SIO R325 1 2 4.7K_0402_5% [15] 10/26 Connect U22.26 pin to signal mSATA_DET# mSATA_DET# [23] B R327 10K_0402_5% SIO_GPIO23 2 RP15 8 7 6 5 LPD3 LPD4 LPD5 LPD6 RXD1 TXD1 DSR1# RTS1# CTS1# DTR1# RI1# DCD1# GPIO 4.7K_0804_8P4R_5% RXD1 TXD1 DSR#1 RTS#1 CTS#1 DTR#1 RI#1 DCD#1 54 55 56 1 2 3 4 5 LPC I/F [33] [33] [33] [33] [33] [33] [33] [33] RXD1 TXD1 DSR#1 RTS#1 CTS#1 DTR#1 RI#1 DCD#1 PARALLEL I/F 10/25 Delete R473, R474, R475, R468. Add RP15 1 2 3 4 SERIAL I/F RP14 8 7 6 5 LPD7 LPTSLCT LPTPE LPTBUSY 1 10/25 Delete R320, R477, R478, R464. Add RP13 A 3 VTR VCC VCC VCC VCC POWER EPAD 57 LPC47N217N-ABZJ_QFN56_8X8 1 2 07/19 Change R483.1 and R482.1 connection to +3VS. Change R330.1, R329.1, and R328.1 connection to GND 07/20 Reserve SIO_GPIO44 PD R554, and modify R328, R329, R330 value to 4.7K. Modify R482, R483 value to 10K +3VS R482 1 R483 1 C 2 10K_0402_5% 2 10K_0402_5% SIO_GPIO44 SIO_GPIO43 2 4.7K_0402_5% R601 1 @ SIO_GPIO42 09/11 Add R601 4.7K PU to +3VS on signal SIO_GPIO42. Noninstall R601 R331 1 2 10K_0402_5% C SYSOPT Base I/O Address 0 = 02Eh 1 = 04Eh CLK_SIO_14M 1 1 CLK_PCI_SIO R333 @ 10_0402_5% 2 2 R332 33_0402_5% 1 2 1 C205 82P 50V J NPO 0402 2 C206 @ 10P_0402_25V8K 11/07 Change R332 to 33 ohms, C205 to 82pF and install R332 and C205 D D Compal Secret Data Security Classification Issued Date 2012/03/23 Deciphered Date 2009/09/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Title Compal Electronics, Inc. SUPER I/O LPC47N217N-ABZJ Size Document Number Rev 0.5 LA-9241P Date: Thursday, December 20, 2012 5 Sheet 32 of 56 1 2 VA +5VS +5VS VIN D42 L30ESD24VC3-2_SOT23-3 1 2 2 1 2 1 2 P1 09/11 Delete R351 and connect EN_P1V5 to JDOCK1.140 189 2 3 DPB_HPD EN_P1V5 ADP_SIGNAL DPB_AUX DPB_AUX# R168 1 2 100K_0402_5% DPB_HPD ADP_SIGNAL 09/27 Delete R339, R341 MDO3+ MDO3- [29] [29] MDO2+ MDO2- 188 187 186 185 184 183 182 DETECT +5VS B [36] [36] DPB_TXP0 DPB_TXN0 [36] [36] DPB_TXP1 DPB_TXN1 [36] DPB_TXP2 DPB_TXN2 [36] [36] DPB_TXP3 DPB_TXN3 [36] [36] DPB_AUX DPB_AUX# Quick SW [36] DPB_AUX DPB_AUX# 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 188 187 186 185 184 183 182 1 2 3 4 5 6 7 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 MDO1+ MDO1- [29] [29] MDO0+ MDO0- [29] [29] LED_LINK_LAN_DOCK# LAN_ACT# [29] [32] [32] [32] [32] [32] [32] [32] [32] [32] [32] [32] [32] [32] [32] [32] [32] [32] LPTSTB# LPTAFD# LPTERR# LPTACK# LPTBUSY LPTPE LPTSLCT LPD7 LPD6 LPD5 LPD4 LPD3 LPD2 LPD1 LPD0 LPTSLCTIN# LPTINIT# [13,39] [36] [13,36] SATA_ACT# DOCK_ID ISO_PREP# [29] +5VS USB3TN1 USB3TP1 USB3TN1 USB3TP1 USB3RN1 USB3RP1 USB3RN1 USB3RP1 USBP0USBP0+ MXM_DCK_AUX MXM_DCK_AUX# [17] [17] [17] [17] [17] [17] MXM_DCK_LANE_P0 MXM_DCK_LANE_N0 [35] [35] MXM_DCK_LANE_P1 MXM_DCK_LANE_N1 [35] [35] MXM_DCK_LANE_P2 MXM_DCK_LANE_N2 [35] [35] MXM_DCK_LANE_P3 MXM_DCK_LANE_N3 [35] [35] MXM_DCK_AUX MXM_DCK_AUX# C208 0.1U_0402_16V4Z ON/OFFBTN_KBC# [30,38] A JDOCK1B [36] [30,39,40,44,45] G1 2 C299 0.01U_0402_16V7K_X7R 1 JDOCK1A 190 ON/OFFBTN_KBC# 2 10/11 Non-install D42 07/16 Add by ESD's request 12A R335 1K_0402_5% 09/11 Change C299 to 0.01uF. Delete R336 and connect C299.1 to ON/OFFBTN_KBC#. Connect ON/OFFBTN_KBC# to JDOCK1.49 0.1U_0402_16V4Z C213 0.1U_0603_50V4Z L28 HCB2012KF-121T50_0805 1 2 0.1U_0402_16V4Z C212 0.1U_0603_50V4Z 1 5A @ 1 2 10K_0402_5% 2 10K_0402_5% VA L27 HCB2012KF-121T50_0805 1 2 VA [29] [29] +3V_PCH VA_ON# R334 1 R337 1 DOCK_ID ISO_PREP# 0.1U_0402_16V4Z C211 2 DOCKING CONNECT 10U_0805_10V4Z C210 2 5 1 1 4 2 1 1 C209 PCI Express x1 channels PS/2 Interfaces USB 2.channels SATA Channels Display Port Channels Serial Port Parallel Port Line In Line Out RJ45 (10/100/1000) VGA 2 LAN indicator LED's Power Button I2C interface DOCK CONN. 184PIN C207 A (1) (2) (2) (2) (2) (1) (1) (1) (1) (1) (1) (1) (1) (1) 3 GPU [13] [13] SATA_PTX_DRX_P3 SATA_PTX_DRX_N3 [13] [13] SATA_PRX_DTX_P3 SATA_PRX_DTX_N3 [17] [17] USBP11USBP11+ [13] [13] SATA_PTX_DRX_P2 SATA_PTX_DRX_N2 [13] [13] LPTSTB# LPTAFD# LPTERR# LPTACK# LPTBUSY LPTPE LPTSLCT LPD7 LPD6 LPD5 LPD4 LPD3 LPD2 LPD1 LPD0 LPTSLCTIN# LPTINIT# STB_LED#_R SATA_ACT# DOCK_ID ISO_PREP# USBP11USBP11+ SATA_PRX_DTX_P2 SATA_PRX_DTX_N2 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 08/01 Modify SATA bus from port 5 to port 2 192 194 196 198 200 [35] [35] FOX_QL0094L-D26601-8H CONN@ 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 G2 G4 G6 G8 G10 G1 G3 G5 G7 G9 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 DCK1_HPD ON/OFFBTN_KBC# VA_ON# DCK1_HPD [35] MXM_DCK_AUX MXM_DCK_AUX# 09/27 Delete R340, R342 D_DDCDATA D_DDCCLK D_DDCDATA [36] D_DDCCLK [36] D_VSYNC [36] D_HSYNC [36] R_DOCK_RED R_DOCK_RED R_DOCK_GRN R_DOCK_BLU [36] R_DOCK_GRN R_DOCK_BLU DCD#1 RI#1 DTR#1 CTS#1 RTS#1 DSR#1 TXD1 RXD1 [36] [36] DCD#1 [32] RI#1 [32] DTR#1 [32] CTS#1 [32] RTS#1 [32] DSR#1 [32] TXD1 [32] RXD1 [32] KBD_DATA KBD_CLK PS2_DATA PS2_CLK B KBD_DATA [30] KBD_CLK [30] PS2_DATA [30] PS2_CLK [30] LINE_IN_SENSE [27] DOCK_HPS# [27] DOCK_HPS# DOCK_LINE_IN_L DOCK_LINE_IN_R DLINE_OUT_L DLINE_OUT_R DLINE_OUT_L DLINE_OUT_R [27] [27] [27] [27] DETECT 191 193 195 197 199 FOX_QL0094L-D26601-8H CONN@ C C R_DOCK_RED R_DOCK_GRN R_DOCK_BLU R343 1 R344 1 R345 1 R_DOCK_RED R_DOCK_GRN R_DOCK_BLU C214 1 C215 1 C216 1 2 150_0402_1% 2 150_0402_1% 2 150_0402_1% 1 +5VDS 2 R346 10K_0402_5% 07/18 change by HP request 8051TX_STBYLED# 1 8051TX_STBYLED# 3 [30,38,39] STB_LED#_R D S 2 G 2 @ 0.1U_0402_16V4Z 2 @ 0.1U_0402_16V4Z 2 @ 0.1U_0402_16V4Z Q35 2N7002_SOT23-3 D D IN 1 2 NC<-->COM NO<-->COM L ON OFF H OFF ON Compal Secret Data Security Classification Issued Date 2012/03/23 Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 4 Title Compal Electronics, Inc. DOCK CONN Size Document Number Custom LA-9241P Date: Rev 0.5 Thursday, December 20, 2012 5 Sheet 33 of 56 A B C +3VALW TO +3VALW(PCH AUX Power) +5VDS to +5VS Transfer Short J1 for PCH VCCSUS3.3 +3VDS @ J1 1 1 +3V_PCH C490 1 @ 2 0.01U_0402_16V7K +5VDS 2 2 SLP_S3# R603 1 2 0_0402_5% 3 1 40mil Q40 AO3413L_SOT23-3 3 1 2 2 S 3 1 G 2 1 2 08/10 Reserve C455 for RF KBC_PWR_ON# 4 Q18B DMN66D0LDW-7_SOT363-6 4 +5VDS C491 1 2 4700P_0402_16V7K6 VBIAS GND GND CT 5 9 TPS22965DSGR_SON8_2X2 2 @ 2 1 C506 @ 2 1 C507 @ 2 1 @ 2 2 08/10 Reserve C453 and C454 for RF 9/25 Change +5VS power rail soultion. Delete U24, C226, C221, C222. Add U45, R603, C489, C490, C491, C492 9/26 Change C489, C492 to 10u. Change C490 to 0.01u 11/06 Add C506, C507, C508, C509 by RF reqeust 11/06 Change C491 to 4700pF 4 +5VDS C495 1 2 4700P_0402_16V7K6 VOUT VIN VOUT VBIAS GND GND CT 6.5A 7 8 C496 1 2 5 9 TPS22965DSGR_SON8_2X2 09/25 Change +3VS power rail solution. Delete U25, C218, C223, C219, C227, R354, R356, R357, Q9. Add U46, R604, C493, C494, C495, C496 09/26 Change C494, C496 to 10u. Change C493 to 0.01u 11/06 Change C495 to 4700pF 2 100K_0402_5% @ 2 1 C457 2 1 2 C458 1 @ 68P_0402_50V8J 1 @ 68P_0402_50V8J 2 DMN66D0LDW-7_SOT363-6 Q18A 68P_0402_50V8J 6 2 C456 @ 10/25 Change R455 to 200k. Add PD R622. 10/26 Change R455.2 connection to B+ 2 KBC_PWR_ON @ C510 1 08/10 Reserve C452, C456, C457, C458 for RF 11/06 Reserve C510 by RF request 1 [30,44] C452 1 +3VDS 200K_0402_5% R622 1 2 1 VIN 100P_0402_50V8J 2 C454 C494 1 +3VS ON 68P_0402_50V8J 2 C453 U46 3 10U_0603_6.3V6M @ C492 1 10U_0603_6.3V6M 2 8 100P_0402_50V8J 2 R455 @ VOUT 2 0_0402_5% 1 100P_0402_50V8J 1 KBC_PWR_ON# KBC_PWR_ON# 2 VIN R604 1 4.5A 7 68P_0402_50V8J 5 B+ [46] @ SLP_S3# VOUT 68P_0402_50V8J R355 470_0603_5% C489 1 10U_0603_6.3V6M 2 C455 1 68P_0402_50V8J 1 @ C508 1 100P_0402_50V8J 2 R489 1K_0402_5% 1 100P_0402_50V8J 2 C220 1U_0603_25V6 1 C225 10U_0603_6.3V6M C224 10U_0603_6.3V6M 1 C493 1 @ 2 0.01U_0402_16V7K +3VDS ON 10U_0603_6.3V6M D C509 1 +5VS VIN E +3VDS to +3VS Transfer U45 JUMP_43X79 07/06 Swap Drain and Source to aviod leakage issue D Discharge circuit-2 for V-M Change Delete Change Delete R455 to 47K. Add Q18A, C504, R609. Modify circuit C504, R609, R456, Q67B. Add R612. Modify circuit. R612 to 4.7k ohms. Delete Q67A R612 +3VM_LAN 1 10/12 10/16 10/18 10/23 +3VDS 07/20 Delete C231 1 3 4 1 R373 470_0402_5% D S SLP_S3 2 G Q43 2N7002_SOT23-3 @ 1 2 @ 2 1 Q42A 2N7002DW T/R7_SOT-363-6 2 @ 3 6 2 SLP_S3 R370 220_0402_5% @ D 3 1 + 2 +5VS S SLP_S3 2 G Q44 2N7002_SOT23-3 @ 1 4 3 1 330U_B2_2VM_R15M 9/25 Uninstall R370, R373, Q43, Q44 3 09/26 Change Q42 to Dual channel 09/28 Add C503 Q42B 2N7002DW T/R7_SOT-363-6 5 4 SLP_S3 2 C232 2 220K_0402_5% 2 10U_0805_10V4Z R375 1 3300P_0402_25V7K B+ 1 C503 1 3 R369 470_0402_5% 6A 1 2 3 C235 2 0.1U_0402_16V4Z C234 10U_0805_10V4Z C233 1 Q39 2N7002KW_SOT323-3 1 +3VS +1.05VS 2 S R368 100K_0402_5% Discharge circuit-1 Q41 AO4430L_SO8 1 D 2 Q7B 2N7002DWH_SOT363-6 5 2 G SLP_S3# 1 [14,30,31,45] 07/23 Remove Q37, R366, R361 +1.05VS 8 7 6 5 SLP_LAN 2 2 +1.05VM to +1.05VS Transfer +1.05VM SLP_S3 SLP_S3 2 1 2 C230 SLP_LAN SLP_LAN [49,9] 1.5A 1 AMT@ R488 1K_0402_5% [29] +3VM_LAN 0.1U_0402_16V4Z 2 1U_0402_6.3V4Z C229 1 AMT@ G S AMT@ Q36 AO3413L_SOT23-3 3 1 2 10/26 Change Q36 to AO3413 +3VDS 3 +3VALW to +3VM_LAN Transfer D 2 2 1 R360 470_0402_5% R363 4.7K_0402_5% 07/10 Change R363 to 4.7K 09/26 Change netname to SLP_S3# 09/26 Change +1.05VS power circuit. 4 4 Compal Secret Data Security Classification Issued Date 2012/03/23 Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Size Compal Electronics, Inc. DC/DC Circuits Document Number Rev 0.5 LA-9241P Date: Thursday, December 20, 2012 E Sheet 34 of 56 5 [4] PEG_CTX_GRX_P[0..15] [4] PEG_CTX_GRX_N[0..15] [4] PEG_CRX_GTX_P[0..15] [4] PEG_CRX_GTX_N[0..15] 4 3 2 1 #4/6 change by HP requirement PEG_CTX_GRX_P[0..15] PEG_CTX_GRX_N[0..15] PCH_THERMTRIP#_R PCH_THERMTRIP#_R AC_PRES_OUT AC_PRES_OUT PEG_CRX_GTX_P[0..15] PEG_CRX_GTX_N[0..15] B+ [18,24,5] [14,30] B+ PEX_RST 5/28 change by HP requirement 2 CV9 2 CV10 PEG_CRX_GTX_C_N15 PEG_CRX_GTX_C_P15 PEG_CRX_GTX_N14 PEG_CRX_GTX_P14 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 1 1 2 CV11 2 CV12 PEG_CRX_GTX_C_N14 PEG_CRX_GTX_C_P14 PEG_CRX_GTX_N13 PEG_CRX_GTX_P13 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 1 1 2 CV13 2 CV14 PEG_CRX_GTX_C_N13 PEG_CRX_GTX_C_P13 PEG_CRX_GTX_N12 PEG_CRX_GTX_P12 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 1 1 2 CV15 2 CV16 PEG_CRX_GTX_C_N12 PEG_CRX_GTX_C_P12 PEG_CRX_GTX_N11 PEG_CRX_GTX_P11 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 1 1 2 CV17 2 CV18 PEG_CRX_GTX_C_N11 PEG_CRX_GTX_C_P11 PEG_CRX_GTX_N10 PEG_CRX_GTX_P10 1 1 2 CV19 2 CV20 PEG_CRX_GTX_C_N10 PEG_CRX_GTX_C_P10 PEG_CRX_GTX_N9 PEG_CRX_GTX_P9 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 1 1 2 CV21 2 CV22 PEG_CRX_GTX_C_N9 PEG_CRX_GTX_C_P9 PEG_CRX_GTX_N8 PEG_CRX_GTX_P8 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 1 1 2 CV23 2 CV24 PEG_CRX_GTX_C_N8 PEG_CRX_GTX_C_P8 PEG_CRX_GTX_N7 PEG_CRX_GTX_P7 PEG_CRX_GTX_N6 PEG_CRX_GTX_P6 B 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 1 1 1 1 2 CV25 2 CV26 2 CV27 2 CV28 PEG_CRX_GTX_C_N7 PEG_CRX_GTX_C_P7 PEG_CRX_GTX_C_N6 PEG_CRX_GTX_C_P6 PEG_CRX_GTX_N5 PEG_CRX_GTX_P5 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 1 1 2 CV29 2 CV30 PEG_CRX_GTX_C_N5 PEG_CRX_GTX_C_P5 PEG_CRX_GTX_N4 PEG_CRX_GTX_P4 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 1 1 2 CV31 2 CV32 PEG_CRX_GTX_C_N4 PEG_CRX_GTX_C_P4 PEG_CRX_GTX_C_N0 PEG_CRX_GTX_C_P0 [15] [15] +3VS DGPU_PRSNT# DGPU_PWROK DGPU_PWR_EN DGPU_PRSNT# [18] DGPU_PWROK DGPU_PWR_EN [18] [14,15] R607 1 R608 1 CLK_PCIE_VGA# CLK_PCIE_VGA 2 10K_0402_5% 2 300_0402_5% 10/25 Change R607 and R608 to 10K 10/29 Change R608 to 300 ohms. 09/27 Add R606, R607, R608 10/18 Change R606,R607 and R608 to 4.7K R606 1 2 4.7K_0402_5% +3VS DGPU_PWROK Q60A MXM_PCH_KBC_I2CDAT MXM_PCH_KBC_I2CLK 1 6 PCH_KBC_I2CDAT 2N7002DW T/R7_SOT-363-6 Q60B 4 3 PCH_KBC_I2CLK [16,30] [16,30] 2N7002DW T/R7_SOT-363-6 PEG_CTX_GRX_N15 PEG_CTX_GRX_P15 EDP PEG_CTX_GRX_N14 PEG_CTX_GRX_P14 PEG_CTX_GRX_N13 PEG_CTX_GRX_P13 PEG_CTX_GRX_N12 PEG_CTX_GRX_P12 [36] [36] MXM_eDP_LANE_N0 MXM_eDP_LANE_P0 [36] [36] MXM_eDP_LANE_N1 MXM_eDP_LANE_P1 [36] [36] MXM_eDP_LANE_N2 MXM_eDP_LANE_P2 [36] [36] MXM_eDP_LANE_N3 MXM_eDP_LANE_P3 [36] [36] GPU_AUX# GPU_AUX 0.1U_0402_10V7K 0.1U_0402_10V7K 2 2 1 1 C24 MXM_eDP_C_LANE_N0 C25 MXM_eDP_C_LANE_P0 0.1U_0402_10V7K 0.1U_0402_10V7K 2 2 1 1 C26 MXM_eDP_C_LANE_N1 C27 MXM_eDP_C_LANE_P1 0.1U_0402_10V7K 0.1U_0402_10V7K 2 2 1 1 C28 MXM_eDP_C_LANE_N2 C29 MXM_eDP_C_LANE_P2 0.1U_0402_10V7K 0.1U_0402_10V7K 2 2 1 1 C30 MXM_eDP_C_LANE_N3 C31 MXM_eDP_C_LANE_P3 0.1U_0402_10V7K 0.1U_0402_10V7K 2 2 1 1 C32 GPU_C_AUX# C33 GPU_C_AUX 07/09 Change by easy layout 10/11 Change DP port C to eDP PEG_CTX_GRX_N11 PEG_CTX_GRX_P11 PEG_CTX_GRX_N10 PEG_CTX_GRX_P10 PEG_CTX_GRX_N9 PEG_CTX_GRX_P9 07/09 Change by easy layout 10/11 Change DP port A to Thunder bolt PEG_CTX_GRX_N8 PEG_CTX_GRX_P8 PEG_CTX_GRX_N7 PEG_CTX_GRX_P7 PEG_CTX_GRX_N6 PEG_CTX_GRX_P6 PEG_CTX_GRX_N5 PEG_CTX_GRX_P5 Thunder Bolt PEG_CTX_GRX_N4 PEG_CTX_GRX_P4 [39] [39] MXM_TB_LANE_N0 MXM_TB_LANE_P0 [39] [39] MXM_TB_LANE_N1 MXM_TB_LANE_P1 [39] [39] MXM_TB_LANE_N2 MXM_TB_LANE_P2 [39] [39] MXM_TB_LANE_N3 MXM_TB_LANE_P3 2 2 1 C34 MXM_TB_C_LANE_N0 1 C35 MXM_TB_C_LANE_P0 0.1U_0402_10V7K 0.1U_0402_10V7K 2 2 1 C36 MXM_TB_C_LANE_N1 1 C37 MXM_TB_C_LANE_P1 0.1U_0402_10V7K 0.1U_0402_10V7K 2 2 1 C38 MXM_TB_C_LANE_N2 1 C39 MXM_TB_C_LANE_P2 0.1U_0402_10V7K 0.1U_0402_10V7K 2 2 1 C40 MXM_TB_C_LANE_N3 1 C67 MXM_TB_C_LANE_P3 MXM_TB_AUX# MXM_TB_AUX 1 CONN@ R93 R92 R91 150_0402_1% 150_0402_1%150_0402_1% @ @ @ CRT +3VS 4 OUT U37 IN1 IN2 1 2 DGPU_HOLD_RST# PLT_RST# [14] [13,14,25,28,29,30,37,39,5] MC74VHC1G08DFT2G_SC70-5 12/20 Uninstall R91, R92, R93. C 10/11 Change DP port D to SWITCH R450 1 2 10K_0402_5% MXM_SYS_LANE_N0 MXM_SYS_LANE_P0 [36] [36] MXM_SYS_LANE_N1 MXM_SYS_LANE_P1 [36] [36] MXM_SYS_LANE_N2 MXM_SYS_LANE_P2 [36] [36] MXM_SYS_LANE_N3 MXM_SYS_LANE_P3 [36] [36] MXM_SYS_AUX# MXM_SYS_AUX GPU_HPD [36] DCK1_SYS_HPD DCK1_SYS_HPD SWITCH [36] [36] 07/09 Change by easy layout [36] 10/11 Change DP port B to DOCK R448 1 R449 1 1 FOX_AS0B826-S43B1-7H 100K_0402_5% 2 08/09 Modify JMXM1 footprint 2 R169 2 10K_0402_5% 2 10K_0402_5% MXM_DCK_LANE_N0 MXM_DCK_LANE_P0 [33] [33] MXM_DCK_LANE_N1 MXM_DCK_LANE_P1 [33] [33] MXM_DCK_LANE_N2 MXM_DCK_LANE_P2 [33] [33] MXM_DCK_LANE_N3 MXM_DCK_LANE_P3 [33] [33] Dock MXM_DCK_AUX# [33] MXM_DCK_AUX [33] DCK1_HPD [33] TB_HPD [39] DCK1_HPD TB_HPD B +3VS C347 315 317 C348 1 2 C349 1 2 0.1U_0402_16V4Z 08/09 Modify JMXM1 footprint GND GND [36] [36] [36] [36] RED_R [36] GREEN_R [36] BLUE_R [36] 0.1U_0402_16V4Z CONN@ [15] GPU_VGA_DDC_DAT GPU_VGA_DDC_CLK GPU_VGA_VSYNC GPU_VGA_HSYNC 10U_0603_6.3V6M FOX_AS0B826-S43B1-7H PEG_CLK_REQ# @ C450 C451 82P 50V J NPO 0402 MXM_TB_AUX# MXM_TB_AUX 07/06 Swap PEG TX and RX 6/2 change to fix MXM no function issue. PEG_CTX_GRX_N0 PEG_CTX_GRX_P0 PEX_RST 82P 50V J NPO 0402 [39] [39] 0.1U_0402_10V7K 0.1U_0402_10V7K PEG_CTX_GRX_N1 PEG_CTX_GRX_P1 5 PEG_CRX_GTX_C_N1 PEG_CRX_GTX_C_P1 1 0.22U_0402_6.3V6K 1 0.22U_0402_6.3V6K VCC 1 0.22U_0402_6.3V6K 1 0.22U_0402_6.3V6K 2 2 D PEG_CRX_GTX_N3 PEG_CRX_GTX_P3 GND 2 2 CV7 CV8 1 0.22U_0402_6.3V6K 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N2 PEG_CTX_GRX_P2 3 CV5 CV6 PEG_CRX_GTX_N0 PEG_CRX_GTX_P0 CV1 2 CV2 2 PEG_CRX_GTX_C_N3 PEG_CRX_GTX_C_P3 2 PEG_CRX_GTX_N1 PEG_CRX_GTX_P1 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231 233 235 237 239 241 243 245 247 249 251 253 255 257 259 261 263 265 267 269 271 273 275 277 279 281 283 285 287 289 291 293 295 297 299 301 303 305 307 309 311 313 2 PEG_CRX_GTX_C_N2 PEG_CRX_GTX_C_P2 1 1 0.22U_0402_6.3V6K 1 0.22U_0402_6.3V6K 2 PCH_THERMTRIP#_R 2 2 1 2 2 1 MMBT3904_SOT23-3 Q83 10/25 Change Q61 and Q62 to dual channel 7002 11/08 Delete D52. Add Q83, R627 CV3 CV4 1 1 1 3 MXM_THERMTRIP# PEG_CRX_GTX_N2 PEG_CRX_GTX_P2 GND PEX_RX3# PEX_RX3 GND GND PEX_TX2# PEX_TX2 GND PEX_TX1# PEX_TX1 GND PEX_TX0# PEX_TX0 GND PEX_CLK_REQ# PEX_RST# VGA_DDC_DAT VGA_DDC_CLK VGA_VSYNC VGA_HSYNC GND VGA_RED VGA_GREEN VGA_BLUE GND LVDS_LCLK# LVDS_LCLK GND LVDS_LTX3# LVDS_LTX3 GND LVDS_LTX2# LVDS_LTX2 GND LVDS_LTX1# LVDS_LTX1 GND LVDS_LTX0# LVDS_LTX0# GND DP_D_L0# DP_D_L0 GND DP_D_L1# DP_D_L1 GND DP_D_L2# DP_D_L2 GND DP_D_L3# DP_D_L3 GND DP_D_AUX# DP_D_AUX DP_C_HPD DP_D_HPD RSVD RSVD RSVD RSVD DP_B_L0# DP_B_L0 GND DP_B_L1# DP_B_L1 GND DP_B_L2# DP_B_L2 GND DP_B_L3# DP_B_L3 GND DP_B_AUX# DP_B_AUX DP_B_HPD DP_A_HPD 3V3 3V3 @ 2 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 10/18 change R137 to 4.7K 10/29 Delete R137, Q82.B. Add D52 GND PEX_TX3# PEX_TX3 GND GND PEX_RX2# PEX_RX2 GND PEX_RX1# PEX_RX1 GND PEX_RX0# PEX_RX0 GND PEX_REFCLK# PEX_REFCLK GND RSVD RSVD RSVD RSVD RSVD LVDS_UCLK# LVDS_UCLK GND LVDS_UTX3# LVDS_UTX3 GND LVDS_UTX2# LVDS_UTX2 GND LVDS_UTX1# LVDS_UTX1 GND LVDS_UTX0# LVDS_UTX0 GND DP_C_L0# DP_C_L0 GND DP_C_L1# DP_C_L1 GND DP_C_L2# DP_C_L2 GND DP_C_L3# DP_C_L3 GND DP_C_AUX# DP_C_AUX RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GND DP_A_L0# DP_A_L0 GND DP_A_L1# DP_A_L1 GND DP_A_L2# DP_A_L2 GND DP_A_L3# DP_A_L3 GND DP_A_AUX# DP_A_AUX PRSNT_L# GND GND 1 PEG_CRX_GTX_N15 PEG_CRX_GTX_P15 AC_PRES_OUT 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262 264 266 268 270 272 274 276 278 280 282 284 286 288 290 292 294 296 298 300 302 304 306 308 310 312 314 316 318 2 1 100K_0402_5% 6 PEG_CTX_GRX_N3 PEG_CTX_GRX_P3 5 2 R63 +3VS C 1 R627 4.7K_0402_5% C 2 4.7K_0402_5% ENAVDD_G BL_EN_G BL_PWM_G @ Q82A 2N7002KDW_SOT363-6 E R487 1 DGPU_PWR_EN PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC GND GND GND GND GND GND GND GND GND GND PRSNT_R# WAKE# PWR_GOOD PWR_EN RSVD RSVD RSVD RSVD PWR_LEVEL TH_OVERT# TH_ALERT# TH_PWM GPIO0 GPIO1 GPIO2 SMB_DAT SMB_CLK GND OEM OEM OEM OEM GND PEX_TX15# PEX_TX15 GND PEX_TX14# PEX_TX14 GND PEX_TX13# PEX_TX13 GND PEX_TX12# PEX_TX12 GND PEX_TX11# PEX_TX11 GND PEX_TX10# PEX_TX10 GND PEX_TX9# PEX_TX9 GND PEX_TX8# PEX_TX8 GND PEX_TX7# PEX_TX7 GND PEX_TX6# PEX_TX6 GND PEX_TX5# PEX_TX5 GND PEX_TX4# PEX_TX4 B +5VS JMXM1B 07/06 Swap PEG TX and RX PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC GND GND GND GND GND GND GND GND GND GND 5V 5V 5V 5V 5V GND GND GND GND PEX_STD_SW# VGA_DISABLE# PNL_PWR_EN PNL_BL_EN PNL_BL_PWM HDMI_CEC DVI_HPD LVDS_DDC_DAT LVDS_DDC_CLK GND OEM OEM OEM OEM GND PEX_RX15# PEX_RX15 GND PEX_RX14# PEX_RX14 GND PEX_RX13# PEX_RX13 GND PEX_RX12# PEX_RX12 GND PEX_RX11# PEX_RX11 GND PEX_RX10# PEX_RX10 GND PEX_RX9# PEX_RX9 GND PEX_RX8# PEX_RX8 GND PEX_RX7# PEX_RX7 GND PEX_RX6# PEX_RX6 GND PEX_RX5# PEX_RX5 GND PEX_RX4# PEX_RX4 2 D 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 1 JMXM1A 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 07/09 Change by easy layout 5/17 change by HP agree +3VS [17] U34 3 1 6 ENAVDD_G [14] ENVDD_PCH [14,36] DGPU_SELECT# Y0 Y1 S VCC Z GND 5 4 2 ENAVDD dGPU_HPD_INTR dGPU_HPD_INTR 08/08 Reserve C450, C451 by RF request [22] DGPU_SELECT# Y0 Y1 S VCC Z GND 5 4 2 ENABLT [22] 2 PANEL_BKEN_PCH 2N7002KW_SOT323-3 1 D 2 DCK1_HPD D 2N7002KW_SOT323-3 2 G S R453 Q53 100K_0402_5% 3 G S R452 Q52 100K_0402_5% 3 2 3 U35 3 1 6 BL_EN_G [14] 1 1 TB_HPD 1 2N7002KW_SOT323-3 S R451 Q51 100K_0402_5% 2 D DCK1_SYS_HPD 2 G +3VS 1 1 74LVC1G3157GW_SC-88-6 74LVC1G3157GW_SC-88-6 S Z LO Y0 HI Y1 A A +3VS U36 3 1 6 BL_PWM_G [14] BKL_PWM_PCH DGPU_SELECT# Y0 Y1 S VCC Z GND 5 4 2 INV_PWM [22] 74LVC1G3157GW_SC-88-6 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 12/12 Change U34, U35, U36 to small package for material shortage issue. 2012/03/23 Deciphered Date 2009/09/09 Title MXM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.5 LA-9241P Date: 5 4 3 2 Thursday, December 20, 2012 1 Sheet 35 of 56 1 2 07/17 Modify eDP MUX solution to PI3VDP12413 3 4 DP MUX eDP MUX +3VS 1 CC72 2 1 2 07/23 Modify net name GPU_SEL D0D0+ D1D1+ D2D2+ D3D3+ D0-B D0+B D1-B D1+B D2-B D2+B D3-B D3+B AUX-B AUX+B HPD_B AUXAUX+ AUX_HPD_SEL HPD GND GND GND 25 OE HGND PI3VDP12412ZHEX_TQFN42_9X3P5 2 3 4 6 7 8 9 10 11 13 14 5 18 2 A U26 12 21 34 VDD VDD VDD D0-A D0+A D1-A D1+A D2-A D2+A D3-A D3+A AUX-A AUX+A HPD_A 07/23 Modify net name SEL_eDP_MUX SEL_DP_MUX EDP_SW_D0N EDP_SW_D0P EDP_SW_D1N EDP_SW_D1P EDP_SW_D2N EDP_SW_D2P EDP_SW_D3N EDP_SW_D3P [22] [22] [22] [22] [22] [22] [22] [22] EDC_SW_AUX# EDC_SW_AUX SEL_eDP_MUX [22] [22] EDP_SW_HPD 1 17 22 43 1 [22] [35] [35] [35] [35] [35] [35] [35] [35] MXM_SYS_LANE_N0 MXM_SYS_LANE_P0 MXM_SYS_LANE_N1 MXM_SYS_LANE_P1 MXM_SYS_LANE_N2 MXM_SYS_LANE_P2 MXM_SYS_LANE_N3 MXM_SYS_LANE_P3 [35] [35] MXM_SYS_AUX# MXM_SYS_AUX [35] SEL_DP_MUX DCK1_SYS_HPD 2 3 4 6 7 8 9 10 11 13 14 5 18 1 17 22 43 07/19 Delete CC70, CC71, CC75, CC76, CC77, CC78, CC79, CC80, CC81, CC82 GPU_SEL D0D0+ D1D1+ D2D2+ D3D3+ D0-B D0+B D1-B D1+B D2-B D2+B D3-B D3+B AUX-B AUX+B HPD_B AUXAUX+ AUX_HPD_SEL HPD GND GND GND HGND OE PI3VDP12412ZHEX_TQFN42_9X3P5 42 41 40 39 38 37 36 35 24 23 16 DPA_TXN0 DPA_TXP0 DPA_TXN1 DPA_TXP1 DPA_TXN2 DPA_TXP2 DPA_TXN3 DPA_TXP3 C382 C381 C386 C383 C385 C384 C388 C387 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K MB_DPA_TXN0 MB_DPA_TXP0 MB_DPA_TXN1 MB_DPA_TXP1 MB_DPA_TXN2 MB_DPA_TXP2 MB_DPA_TXN3 MB_DPA_TXP3 MB_DPA_AUX# MB_DPA_AUX MB_DP_HPD 33 32 31 30 29 28 27 26 19 20 15 DPB_TXN0 DPB_TXP0 DPB_TXN1 DPB_TXP1 DPB_TXN2 DPB_TXP2 DPB_TXN3 DPB_TXP3 DPB_AUX# DPB_AUX DPB_HPD 25 R544 1 2 10K_0402_5% [39] [39] [39] [39] [39] [39] [39] [39] [39] [39] [39] [33] [33] [33] [33] [33] [33] [33] [33] [33] [33] [33] M/B DP Docking +3VS 1 10K_0402_5% 1 0.1U_0402_16V4Z R505 2 C367 +3VS 2 1 0.1U_0402_16V4Z 33 32 31 30 29 28 27 26 19 20 15 2 C370 MXM_eDP_LANE_N0 MXM_eDP_LANE_P0 MXM_eDP_LANE_N1 MXM_eDP_LANE_P1 MXM_eDP_LANE_N2 MXM_eDP_LANE_P2 MXM_eDP_LANE_N3 MXM_eDP_LANE_P3 GPU_AUX# GPU_AUX GPU_HPD 1 0.1U_0402_16V4Z MXM_eDP_LANE_N0 MXM_eDP_LANE_P0 MXM_eDP_LANE_N1 MXM_eDP_LANE_P1 MXM_eDP_LANE_N2 MXM_eDP_LANE_P2 MXM_eDP_LANE_N3 MXM_eDP_LANE_P3 [35] GPU_AUX# [35] GPU_AUX [35] GPU_HPD 2 C369 [35] [35] [35] [35] [35] [35] [35] [35] From GPU EDP_CPU_AUX# EDP_CPU_AUX CPU_EDP_HPD# 2 1U_0402_6.3V4Z [7] [7] [7] 2 200K_0402_5% VDD VDD VDD 2 1 C368 EDP_CPU_AUX# EDP_CPU_AUX CPU_EDP_HPD# R564 1 D0-A D0+A D1-A D1+A D2-A D2+A D3-A D3+A AUX-A AUX+A HPD_A 2 1 CC83 CC74 1U_0402_6.3V6K From CPU EDP_CPU_LANE_N0 EDP_CPU_LANE_P0 EDP_CPU_LANE_N1 EDP_CPU_LANE_P1 12 21 34 1 0.1U_0402_16V4Z +3VS U42 42 41 40 39 38 37 36 35 24 23 16 EDP_CPU_LANE_N0 EDP_CPU_LANE_P0 EDP_CPU_LANE_N1 EDP_CPU_LANE_P1 1 CC73 0.1U_0402_16V4Z 0.1U_0402_16V4Z R563 200K_0402_5% A [7] [7] [7] [7] 07/17 Modify DP MUX solution to PI3VDP12412 +3VS +3VS 07/27 Add R563, R564 5 2 100K_0402_5% R504 +3VS +3VS B 2 07/23 Delete R516 and CC84 1 B R462 10K_0402_5% R535 10K_0402_5% 07/23 Delete R545 and C371 1 6 2 ISO_PREP# [13,33] 1 3 4 SEL_DP_MUX Q76A 2N7002KDW_SOT363-6 5 DGPU_SELECT# 07/23 Change to dual channel MOS Q76 Q76B 2N7002KDW_SOT363-6 [14,35] 2 07/23 Modify net name SEL_eDP_MUX 07/23 Change dual channel MOS Q76 +5VS F1 1.1A_8VDC_FUSE 1 2 +RCRT_VCC +CRTVDD D46 2 1 C468 3 1 1 1 1 RB491D_SOT23-3 1 9/21 Correct netname. C CC60 CC61 CC62 CC63 CC64 CC65 2 2 2 2 2 2 +3VS 10U_0603_6.3V6M 10U_0603_6.3V6M 0.1U_0402_16V4Z 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z U28 6 16 R350 1 +5VS +5VS R348 1 2 10K_0402_5% [14] [35] PCH_CRT_HSYNC GPU_VGA_HSYNC 3 13 [14] [35] PCH_CRT_VSYNC GPU_VGA_VSYNC 4 14 2 10K_0402_5% R349 1 2 10K_0402_5% 1 40 39 38 SDAA SDAB Q78B 2N7002KDW_SOT363-6 [33] DOCK_ID 5 30 20 10 41 4 D 2 1 DGPU_SELECT# 3 Q78A 2N7002KDW_SOT363-6 GRN1 GRN2 EN BLU1 BLU2 SHA SHB SCL1 SCL2 SVA SVB SDA1 SDA2 S00 S01 S10 S11 SH1 SH2 6 +5VS 2 SCLA SCLB GND GND GND SV1 SV2 NC L33 1 2 39NH_CS0805-39NJ-S_5% DAC_GR L30 1 2 110NH_CS0805-R11J-S_5% DAC_GRN R574 1 2 0_0805_5% VGA_GR R577 1 2 0_0805_5% VGA_G L34 1 2 39NH_CS0805-39NJ-S_5% DAC_BL L31 1 2 110NH_CS0805-R11J-S_5% DAC_BLU R575 1 2 0_0805_5% VGA_BL R578 1 2 0_0805_5% VGA_B VGA_RED R_DOCK_RED 32 23 VGA_GRN R_DOCK_GRN 31 22 VGA_BLU R_DOCK_BLU 09/07 Delete VGA_RED, VGA_GRN, VGA_BLU, VGA_DDCCLK, VGA_DDCDATA, CRT_HSYNC, and CRT_VSYNC off page symbol R_DOCK_RED [33] R_DOCK_GRN [33] R_DOCK_BLU RP19 150_0804_8P4R_5% VGA_DDCCLK D_DDCCLK 34 25 VGA_DDCDATA D_DDCDATA 37 28 R_CRT_HSYNC R_D_HSYNC R385 1 R386 1 2 33_0402_1% 2 33_0402_1% CRT_HSYNC 36 27 R_CRT_VSYNC R_D_VSYNC R387 1 R388 1 2 33_0402_1% 2 33_0402_1% CRT_VSYNC D_DDCDATA 1 2 10/25 Delete R570, R571, R572. Add RP19 12/20 Change RP19 to 150ohms [33] 35 26 D_DDCCLK 1 2 3 4 33 24 1 2 1 2 1 2 1 2 1 2 [33] [33] 1 @ 2 1 @ 2 G G C-H_13-12201572CP CONN@ 09/12 Modify JVGA2 footprint 10/31 Modify JVGA2 footprint CRT_HSYNC R579 1 2 0_0402_5% CRT_HSYNC_R CRT_VSYNC R580 1 2 0_0402_5% CRT_VSYNC_R D_VSYNC [33] D47 @ VGA_R 2 VGA_G 3 D48 VGA_B MAX14885EETL+T_TQFN40_5X5~D @ D49 @ 2 1 +3VS CRT_HSYNC 2 CRT_VSYNC 3 1 1 3 YSLC05CH_SOT23-3 YSLC05CH_SOT23-3 D YSLC05CH_SOT23-3 2 10K_0402_5% 2 10K_0402_5% 07/25 Combine Q56 and Q57 to Q79 Compal Secret Data Security Classification Issued Date 2012/03/23 Deciphered Date 2009/12/31 Title Compal Electronics, Inc. Switch/MUX/VGA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom LA-9241P DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 1 2 C VGA_DDCDATA [33] GPAD R501 1 R502 1 2 2 16 17 VGA_DDCCLK D_HSYNC 12 VGA_DDCCLK VGA_DDCDATA 1 @ 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 VGA_R VGA_BLU 8 7 6 5 5 15 PCH_CRT_DDC_DAT GPU_VGA_DDC_DAT RED1 RED2 2 0_0805_5% C467 10P_0402_50V8J PCH_CRT_DDC_CLK GPU_VGA_DDC_CLK [14] [35] 2 BLUA BLUB R576 1 VGA_GRN 1 CC66 0.1U_0402_16V4Z VGA_RE C466 10P_0402_50V8J [14] [35] VL 21 11 2 0_0805_5% C465 10P_0402_50V8J 9 19 29 JVGA2 R573 1 DAC_RED C464 18P_0402_50V8J PCH_CRT_BLU [35] BLUE_R VCC VCC GRNA GRNB 2 110NH_CS0805-R11J-S_5% C463 18P_0402_50V8J [14] MAX14885E REDA REDB L29 1 C462 18P_0402_50V8J 8 18 DAC_RE C461 18P_0402_50V8J 7 17 PCH_CRT_GRN [35] GREEN_R 2 39NH_CS0805-39NJ-S_5% C460 18P_0402_50V8J PCH_CRT_RED [35] RED_R [14] L32 1 VGA_RED C459 18P_0402_50V8J [14] 1 0.1U_0402_10V6K W=40mils 09/07 Add JVGA2 circuit +5VS 1 3 4 Rev 0.5 Thursday, December 20, 2012 5 Sheet 36 of 56 5 4 3 2 1 1 +VCC_SM R391 4.7K_0402_5% 09/03 Change U30 P/N 11/01 Change U30 to AU9560-GBS-GR 2 D U30 +5VS SCardRst SCardclk R395 2 SCardData R396 1 1 C252 0.1U_0402_16V7K [17] [17] 1 0_0402_5% 2 470_0402_5% USBP7USBP7+ +3VS_SM 2 +VCC_SM C253 2 +5VS 2 +3VS_SM CC69 C257 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 XTAL_OUT XTAL_IN PWRSV_SEL# [14] PLT_RST# SSDA T93 PAD~D @ SSCL T94 PAD~D @ +3VS_SM EEPWP T95 PAD~D @ ICCInsertN [13,14,25,28,29,30,35,39,5] 09/20 Delete R393, CC67, and connector U30.23 to PLT_RST# +1.8VS_SM AU9560-GBS-GR_SSOP28 07/20 Vendor's suggestion PWRSV_SEL# 07/06 Correct netname to follow GPIO table C255 1 2 2 C254 1 2 1 C256 0.1U_0402_16V7K 2 C259 1 D XO XI PWRSV_SEL LEDCRD LEDPWR RESET EEPDATA EEPCLK P1(6) ICCInsertN VDDH VDDP VDD V18OUT 1U_0402_6.3V6K 2 C258 1 0.1U_0402_16V7K 1 1U_0402_6.3V6K 2 1U_0402_6.3V6K 1 1 0.1U_0402_16V7K 1U_0402_6.3V6K 0.1U_0402_16V7K CC68 1 SCard0C8 SCard0C6 SCard0Fcb SMIO_5VPWR SCard0Rst SCard0Clk SCard0Data DM DP AV33 SCPWR0 5VGND 5VInput V33OUT 0.1U_0402_16V7K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCardC8 SCardC6 SCardFcb 07/20 Vendor's suggestion 07/20 Vendor's suggestion 11/05 Uninstall Y3, CV33, CV34 C CV33 18P_0402_50V8J @ @ +VCC_SM SCardC6 SCardData SCardC8 ICCInsertN C264 11/01 Change Y3 to small package 2 @ 2 C260 1 2 C261 1 @ 2 @ CV34 XTAL_IN 18P_0402_50V8J C263 1 @ 2 0.1U_0402_16V7K @ C265 1 0.1U_0402_16V7K 1 0.1U_0402_16V7K ACES_51524-0100N-001 CONN@ 07/10 Modify J3 footprint 09/12 Modify J3 pin define Y3 @ 12MHZ_12PF_5YEA12000122IFA2Q3 RH225 1M_0402_5% 4 1 SCardRst SCardclk SCardFcb 0.1U_0402_16V7K 10 9 8 7 6 5 4 3 2 1 0.1U_0402_16V7K 10 9 8 7 6 5 4 3 2 1 12 11 2 GND GND 3 2 XTAL_OUT 1 J3 C 07/12 Modify J3 pin define 07/16 Modify J3 pin define B B A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 Deciphered Date 2011/06/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Smart Card Size C Date: 5 4 3 2 Document Number Rev 0.5 Thursday, December 20, 2012 1 Sheet 37 of 56 5 4 3 2 1 Power Board Conn 11/01 Add R626 +3VDS [26] [30] +5VDS JPWR1 ON/OFFBTN_KBC# D 1 1 3 5 8051TX_STBYLED# 7 ON/OFFBTN_KBC# 9 11 +5VDS +3VDS 2 [22,30,39] LID_SW# LID_SW# [30,33,39] [30,33] C270 0.1U_0402_16V7K 8051TX_STBYLED# ON/OFFBTN_KBC# 1 3 5 7 9 11 2 4 6 8 10 12 2 4 6 8 10 12 [30] [30] KSI[0..7] KSI7 KSI6 KSI5 KSI4 KSI3 KSI2 KSI1 KSI0 ACES_85203-0602N-10 CONN@ 09/12 Modify JPWR1 connector pin define. 09/12 Modify JPWR1 connector footprint and pin define. 10/26 Modify JPWR1 connector footprint and pin define. [30] REC_MUTE_CTRL_KB 8051RX_CAPLED# +3VDS 8051_RECOVER#/_NUM_LOCK_LED# KSO[0..13] KSO13 KSO12 KSO11 KSO10 KSO9 KSO8 KSO7 KSO6 KSO5 KSO4 KSO3 KSO2 KSO1 KSO0 TP/B Conn 09/12 Modify JTP1 pin define and footprint 07/12 07/20 08/07 09/12 09/13 10/31 11/05 JTP1 C [11,12,13,16,28,5] [11,12,13,16,28,5] [30] [30] 1 3 5 7 9 11 13 15 17 19 SP_LEFT SP_MID SP_RIGHT DDR_XDP_WAN_SMBCLK DDR_XDP_WAN_SMBDAT TP_DATA TP_CLK DDR_XDP_WAN_SMBCLK DDR_XDP_WAN_SMBDAT TP_DATA TP_CLK +3VS D33 KSI0 KSI_D_0 3 KSI_D_8 KSI_D_0 [39] 3 2 3 2 07/16 Change P/N for ESD's request 07/20 Change P/N for ESD's request 10/11 Install D32 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 GND GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 KSO12 KSI_D_9 KSI_D_13 KSI_D_6 C420 C421 C422 C423 1 1 1 1 @ @ @ @ 2 2 2 2 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J KSO1 KSO6 KSO4 KSO3 C424 C425 C426 C427 1 1 1 1 @ @ @ @ 2 2 2 2 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J KSI_D_1 KSI_D_4 KSI_D_10 KSI_D_8 C428 C429 C430 C431 1 1 1 1 @ @ @ @ 2 2 2 2 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J KSO13 KSO9 KSI_D_11 KSI7 C432 C433 C434 C435 1 1 1 1 @ @ @ @ 2 2 2 2 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J KSI_D_5 KSO10 KSO7 KSO8 C436 C437 C438 C439 1 1 1 1 @ @ @ @ 2 2 2 2 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J KSI_D_3 KSI_D_2 KSI_D_0 KSI_D_12 C440 C441 C442 C443 1 1 1 1 @ @ @ @ 2 2 2 2 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J KSI_D_14 KSO2 KSO11 KSO0 KSO5 C444 C445 C446 C447 C448 1 1 1 1 1 @ @ @ @ @ 2 2 2 2 2 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J D 69 D39 2 KSI_D_3 3 KSI_D_11 KSI6 1 KSI3 D34 2 KSI_D_6 3 KSI_D_14 D37 2 KSI_D_1 3 KSI_D_9 KSI_D_1 [39] 2 KSI_D_4 3 KSI_D_12 C 1 DAP202UGT106_SOT323-3 DAP202UGT106_SOT323-3 1 +3VS YSDA0502C C/A SOT-23 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 D36 2 1 07/09 Change by follow spec 08/10 Modify JTP1 pin define. KSI1 D32 KSO13 KSO12 KSO9 KSI_D_9 KSI_D_11 KSI_D_13 KSI7 KSI_D_6 KSI_D_5 KSO1 KSO10 KSO6 KSO7 KSO4 KSO8 KSO3 KSI_D_3 KSI_D_1 KSI_D_2 KSI_D_4 KSI_D_0 KSI_D_10 KSI_D_12 KB connector pin define. KSI_D_8 KB connector pin define. KSI_D_14 JKB1 footprint KSO5 JKB1 footprint KSO2 JKB1 pin define, KSO0 JKB1 footprint and pin define, KSO11 JKB1 pin define to follow ME request. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 HB_A823461-SBVR02 CONN@ DAP202UGT106_SOT323-3 2 2 360_0402_5% 2 0_0402_5% 70 1 1 100P_0402_50V8J 100P_0402_50V8J 2 2 4 6 8 10 12 14 16 18 20 E-T_6900K-Q10N-00R CONN@ C298 1 2 4 6 8 10 12 14 16 18 20 1 KSI4 07/24 Add for EMI request 1 C297 1 3 5 7 9 11 13 15 17 19 Modify Modify Change Change Change Change Modify JKB1 R400 1 R626 1 1 KSI2 C296 2 0.1U_0402_16V7K DAP202UGT106_SOT323-3 DAP202UGT106_SOT323-3 D35 D38 2 KSI_D_2 3 KSI_D_10 1 2 KSI_D_5 3 KSI_D_13 1 KSI5 DAP202UGT106_SOT323-3 DAP202UGT106_SOT323-3 +5VDS 1 +5VS R408 1 2 200K_0402_5% 8 7 6 5 4 3 2 1 ACES_50611-0040N-001 CONN@ 8 6 AO3413L_SOT23-3 1 @ 2 4 2 B 6 09/27 Change R408 to 200k D 7 5 3 1 2N7002KDW_SOT363-6 SP_LEFT SP_MID SP_RIGHT 8 7 6 5 4 3 2 1 2 G JP9 8 6 4 2 Q10A SP_DATA SP_CLK 8 7 6 5 4 3 2 1 12 11 10 9 C295 0.047U_0402_16V7K [30] [30] G4 G3 G2 G1 1 +5VS S 2 B R407 100K_0402_5% Q47 +5VS_KBL 2 KBD_PWM_LED [30] 1 KB backlight Conn JP13 3 Stick Point CONN 09/26 Modify JP9 pin define to follow ME request KBL_DET# CONN@ ACES_50554-0080N-001 [18] 07/09 Change by follow spec 09/12 Delete JTP2 connector A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/03/23 Deciphered Date 2011/11/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title KB/TP/LED Size Document Number Custom Date: Rev 0.5 Thursday, December 20, 2012 1 Sheet 38 of 56 5 4 3 2 1 VGA+Function Board Thunderbolt +5VDS +5VDS JTB1 [17] [17] D 9/07 Remove JVGA1 BTB connector USB3TN6 USB3TP6 [17] [17] USB3RN6 USB3RP6 MB_DPA_TXP3 MB_DPA_TXN3 [36] [36] MB_DPA_TXP2 MB_DPA_TXN2 [36] [36] MB_DPA_TXP1 MB_DPA_TXN1 [36] [36] Function Board PCIE_PTX_EXPRX_N5 PCIE_PTX_EXPRX_P5 [17] [17] PCIE_PRX_EXPTX_N5 PCIE_PRX_EXPTX_P5 [15] [15] [15] [17] [17] [38] [38] [30] [26] [25] [22,30,38] KSI_D_0 KSI_D_1 KSO17 MUTE_LED_CNTR WL/BT_LED# LID_SW# KSI_D_0 KSI_D_1 KSO17 MUTE_LED_CNTR WL/BT_LED# LID_SW# 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 19 17 15 13 11 9 7 5 3 1 +1.5VS +1.5VS [36] [36] [36] 10/23 Add Q80 for iSCT_LED# circuit. 1 R623 2 3 WL/BT_LED# 1K_0402_5% Q81 BSS138W-7-F_SOT323-3 iSCT_LED# 10/24 Change Q80 to single MOS, Add R623, Q81 [13,14,25,28,29,30,35,37,5] PLT_RST# [30,33,38] 8051TX_STBYLED# [30] AMBER_BATLED# [13,30] BAT_GRNLED# 10/16 Change JTB1.91 net [14] TBT_RR_GPIO# name to iSCT_LED# TB_HOT_PLUG# 10/23 Change netname [17] +3VDS to TBT_RR_GPIO# 07/18 Add PWR_GD signal +3VDS 07/31 Change JTB1.95 to +3VDS EN_P1V5 E-T_6900K-Q10N-00R CONN@ ACES_50611-0120N-001 CONN@ MB_DPA_AUX# MB_DPA_AUX MB_DP_HPD 1 2 JFUN1 20 18 16 14 12 10 8 6 4 2 G 2 4 6 8 10 12 14 16 18 20 22 24 CLK_PCIE_EXP# CLK_PCIE_EXP CLKREQ_EXP# USBP6USBP6+ D USBP9USBP9+ D [17] [17] 2 4 6 8 10 12 14 16 18 20 22 24 S EN_P1V5 SATA_ACT# 1 MB_DPA_TXP0 MB_DPA_TXN0 [17] [17] +5VS JUB1 1 3 5 7 9 11 13 15 17 19 21 23 Q80 2N7002KW_SOT323-3 3 S [13,33] 1 3 5 7 9 11 13 15 17 19 21 23 C iSCT_LED# G USB20 2 [30] +5VDS USBP5USBP5+ [17] [17] [36] [36] 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 9/07 Add JFUN1 connector 9/12 Modify JFUN1 pin define and footprint 09/26 Modify JFUN1 pin define to follow ME request 07/10 Modify JUB1 footprint and pin define. 07/24 Modify JUB1 pin define. 1 C339 0.01U_0402_16V7K_X7R 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 GND1 GND2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 CLK_TB_REFCLK# CLK_TB_REFCLK [15] [15] MXM_TB_LANE_N3 MXM_TB_LANE_P3 [35] [35] MXM_TB_LANE_N2 MXM_TB_LANE_P2 [35] [35] MXM_TB_LANE_N1 MXM_TB_LANE_P1 [35] [35] MXM_TB_LANE_N0 MXM_TB_LANE_P0 [35] [35] PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 D [17] [17] PCIE_PTX_C_DRX_N4 PCIE_PTX_C_DRX_P4 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 [17] [17] [17] [17] PCIE_PTX_C_DRX_N3 PCIE_PTX_C_DRX_P3 PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 [17] [17] [17] [17] PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 [17] [17] [17] [17] PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 [17] [17] C MXM_TB_AUX# [35] MXM_TB_AUX [35] TB_HPD [35] EN_P1V5 [30,33,40,44,45] CPPWR_EN [30] TB_CLKREQ# [15] HDD_HALTLED [13] +3VDS 07/18 Remove B+ and change to HDD_HALTLED 102 ACES_50019-10001-001 CONN@ 2 07/10 Modify JTB1 footprint and pin define. 07/17 Modify JTB1 pin define. 09/13 Modify JTB1 footprint B B Card Reader Board USB3TN5 USB3TP5 08/10 Change JCR1.21 connection to +3VS +3VS 08/10 Change JCR1.21 connection to +3VDS +3VS 07/19 Modify pin define for better return path A 08/01 JCR1.35 connection to PCH_PCIE_WAKE# 10/16 Delete R602, connection JCR1.5 to +5VDS +5VDS EN_P1V5 [27] HP_SENSE# 09/19 Add R602, and noninstall. 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 07/19 Modify pin define for better return path NFC CONN +3VS JNFC1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 ACES_50103-04071-001 CONN@ CLK_PCIE_CR CLK_PCIE_CR# 16 14 [15] [15] PCIE_PRX_DTX_P8 PCIE_PRX_DTX_N8 [17] [17] PCIE_PTX_C_DRX_P8 PCIE_PTX_C_DRX_N8 [17] [17] [16] [18] [25] [30] NFC_3S_SMBDAT NFC_INT UIM_VPP NFC_TX 1 R558 @ 2 NFC_SW 0_0402_5% PLT_RST# CR_CLK_REQ# R538 100K_0402_5% [15] EXT_MIC_L2 [27] HP_OUT_R [26] HP_OUT_L [26] 12 10 8 6 4 2 GND GND 12 10 8 6 4 2 11 9 7 5 3 1 15 13 11 9 7 5 3 1 Add NFC connector Modify Pin define Modify Pin define. Modify JNFC1 footprint and pin define Modify JNFC1 pin define Delete R557, Non-install R358, C374 +3VS +3V_PCH @ R358 10K_0402_5% NFC_SEL_R NFC_RST# [16] NFC_3S_SMBCLK 1 [16] NFC_SEL_R C374 @ NFC_RX [30] 2 0.1U_0402_16V4Z ACES_50559-01201-001 CONN@ @ R556 10K_0402_5% A 7/13 Modify pin net name Compal Secret Data Security Classification Issued Date 07/30 Modify JCR1 pin define and footprint. 08/07 Change JCR1 footprint 08/08 Change JCR1 pin define 5 GND GND 07/06 07/09 07/30 08/07 08/08 09/21 1 +3VS 2 USB3RN5 USB3RP5 [17] [17] 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 46 44 42 1 [17] [17] 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 GND GND GND 2 USBP4USBP4+ GND GND GND 1 [17] [17] JCR1 45 43 41 2 +5VDS 4 2012/03/23 Deciphered Date 2010/03/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 Title Compal Electronics, Inc. I/O CONN Size Document Number Rev 0.5 LA-9241P Date: Thursday, December 20, 2012 Sheet 1 39 of 56 A B C D E 09/24 Change power rail to +3VS 9/07 Add USB3.0 repeater and connector USB Power Switch +USB_CS U43 2 2 1 2 C480 1 1 C484 2 R590 1 @ 2 4.7K_0402_5% A_DE1 R591 1 @ 2 4.7K_0402_5% A_EQ0 R596 1 @ 2 4.7K_0402_5% R595 1 Equalizer control and program for channel B 3.3V tolerant. Internally pulled down at ~150K [B_EQ1, B_EQ0] == LL: adaptive EQ enable LH: program EQ at 3.5dB HL: program EQ at 6dB HH: program EQ at 10dB 次 +3VS Equalizer control and program for channel A 3.3V tolerant. Internally pulled down at ~150K [A_EQ1, A_EQ0] == LL: adaptive EQ enable LH: program EQ at 3.5dB HL: program EQ at 6dB HH: program EQ at 10dB 次 2 4.7K_0402_5% @ B_EQ0 R594 1 @ 2 4.7K_0402_5% B_EQ1 R589 1 @ 2 4.7K_0402_5% B_DE0 R593 1 @ 2 4.7K_0402_5% B_DE1 R597 1 @ 2 4.7K_0402_5% 次 1 Programmable output pre-emphasis level setting for channel B 3.3V tolerant. Internally pulled down at ~150K [B_EQ1, B_EQ0] == LL: 3.5dB de-emphasis LH: No de-emphasis HL: 5dB de-emphasis HH: Reserved 09/24 Change power rail to +3VS +3VS +3VS 1 2 C502 C482 10U_0603_6.3V6M 09/26 Add C502 1 2 2 1 USB3.0 Repeater C469 0.1U_0402_25V6K change power switch to high active parts 20120803 0.01U_0402_50V7K 1 2 + G547I1P81U_MSOP8 C475 A_DE0 A_EQ1 680P_0603_50V7K 2 EN_P1V5 0.1U_0402_16V4Z 2 1000P_0402_50V7K 680P_0603_50V7K 1 [30,33,39,44,45] C483 1 C479 1 1000P_0402_50V7K C476 8 7 6 5 150U_B2_6.3VM_R45M C481 EN_P1V5 GND VOUT VIN VOUT VIN VOUT EN FLG W=100mils 0.1U_0402_16V4Z 1 1 2 3 4 Programmable output pre-emphasis level setting for channel A 3.3V tolerant. Internally pulled down at ~150K [A_EQ1, A_EQ0] == LL: 3.5dB de-emphasis LH: No de-emphasis HL: 5dB de-emphasis HH: Reserved +3VS +5VDS W=100mils 次 09/24 Change power rail to +3VS VDD : 1.5V for PS8713A VDD : 3.3V for PS8713B U44 1 13 +3VS 09/24 Change power rail to +3VS 2 FORM CPU [17] [17] USB3TP2 USB3TN2 C473 1 C471 1 15 16 17 18 A_EQ1 A_DE0 A_EQ0 A_DE1 2 0.1U_0402_25V6K 2 0.1U_0402_25V6K 19 20 USB3_C_TP2 USB3_C_TN2 FORM USB CONNECTOR 9 8 USB3_RP2_RE USB3_RN2_RE 09/24 Delete Q79, Q80, C475, C477, C478, R588, R587. 5 7 14 24 1 R592 2 4.7K_0402_5% +3VS @ B_EQ1/I2C_ADDR1 B_DE0/I2C_ADDR0 B_EQ0/NC B_DE1/NC A_INp A_INn A_OUTp A_OUTn B_INp B_INn B_OUTp B_OUTn PD# REXT TEST I2C_EN 4 3 2 6 B_EQ1 B_DE0 B_EQ0 B_DE1 12 11 USB3_C_TP2_RE USB3_C_TN2_RE C470 1 C474 1 2 0.1U_0402_25V6K 2 0.1U_0402_25V6K 22 23 USB3_C_RP2 USB3_C_RN2 C486 1 C472 1 2 0.1U_0402_25V6K 2 0.1U_0402_25V6K 2 USB3_TP2_RE USB3_TN2_RE TO USB CONNECTOR USB3RP2 USB3RN2 [17] [17] TO CPU 10 21 25 GND GND GPAD 4.99K_0402_1% PS8713BTQFN24GTR2_TQFN24_4X4 Chip test mode enable. 3.3V tolerant. Internally pulled down at ~150K . TEST == L: Normal operation (default) H: Test mode enable 次 Add DC to DC interface 2012/8/3 TEST R598 A_EQ1/SDA_CTL A_DE0/SCL_CTL A_EQ0/NC A_DE1/NC 2 TEST 1 09/24 Change power rail to +3VS VDD VDD Folow ESD team recommeend change ESD diode D5 D6 20120713 D50 3 3 USB3RXDN2_R 1 9 USB3RXDN2_R USB3RXDP2_R 2 8 USB3RXDP2_R USB3TXDN2_R 4 7 USB3TXDN2_R USB3TXDP2_R 5 6 USB3TXDP2_R USB3.0 Connector 9/17 Swap L35, L36, L37 for layout smoothly USB3_TN2_RE @ 0_0402_5% 2 USB3TXDN2_R 1 4 3 1 2 3 TO USB connector TX USB3_RN2_RE TVWDF1004AD0_DFN9 JUSB1 2 WCM-2012-900T_4P 1 2 R586 @ 0_0402_5% R584 @ 0_0402_5% 1 2 USB3_TP2_RE 1 4 3 1 2 USB3TXDP2_R USB20_N1_R USB20_P1_R 3 TO USB connector RX 2 @ 0_0402_5% 2 @ D51 YSLC05CH_SOT23-3 10 11 12 13 GND GND GND GND LOTES_AUSB0041-P002A CONN@ 9/13 Modify JUSB1 footprint and pin define 4 1 R585 1 USBP1- USB3TXDN2_R USB3TXDP2_R VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+ USB3RXDP2_R 4 [17] USB3RXDN2_R USB3RXDP2_R USB3RXDN2_R 3 WCM-2012-900T_4P 1 2 R582 @ 0_0402_5% USB3_RP2_RE 1 2 3 4 5 6 7 8 9 USB20_N1_R USB20_P1_R L37 4 +USB_CS 2.5A 3 L36 4 2 R583 1 USB20_N1_R L35 4 1 [17] A USBP1+ 4 3 1 2 3 B Issued Date USB20_P1_R Compal Electronics, Inc. Compal Secret Data Security Classification 2 WCM-2012-900T_4P 1 2 R581 @ 0_0402_5% 2012/05/11 Deciphered Date 2013/05/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C D Title USB3.0 CONN/Repeater Size Document Number Custom Date: Rev 0.5 LA-9241P Thursday, December 20, 2012 E Sheet 40 of 56 5 4 ADP_EN DC IN 3 2 1 ACDRV ACFET RBFET +3VS B+ D D RT8243AZQW +3VDSP +5VDSP Main BATT B++ Jumper SY8032 +3VDS +1.5VSP +1.5VS Jumper +5VDS +3VS EN EN ACDRV Battery Selector BATT RBFET RT8207M 2nd BATT Charger EN_P1V5 SLP_S3# +1.35VP +1.5VP +0.675VSP +0.75VSP Jumper +1.35V +1.5V Jumper +0.675VS +0.75VS EN 7/19 BQ24736 C C TPS51212 SIO_SLP_A# +1.05VMP Jumper +1.05VM EN TPS51631 +CPU_CORE B B VR_ON EN A A 5 4 3 2 1 5 4 3 2 +3VDS PJP2 Zero force Footprint: FOX_BP0208C-B24B1-9HQ_8P-T 5 6 V BUS Ground V I/O V I/O PD10 L30ESD24VC3-2_SOT23-3 2 1 2 3 1 1 ADP_SIGNAL 1 PD11 AZC099-04S.R7G SOT23 ESD 4 3 V I/O V I/O 1 PR5 100_0402_5% 2 1 2 PC9 100P_0402_50V8J 2 1 1 2 2 1 1 PR4 100_0402_5% 2 1 2 PC10 100P_0402_50V8J MAIN_BAT_DET# I2C_MAIN_DAT [30,43] I2C_MAIN_CLK [30,43] 1 PR11 10K_0402_5% 2 1 PR12 30K_0402_5% 2 +3VDS 4 PD13 AZC099-04S.R7G SOT23 ESD 3 V I/O V I/O 5 6 1 1 V I/O PJP3 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 VMB_B I2C_BAY_DAT-1 I2C_BAY_CLK-1 2 SD028300080 B PC11 0.1U_0603_50V7K PL6 HCB2012KF-121T50_0805 1 2 1 2 PL7 HCB2012KF-121T50_0805 PC12 1000P_0402_50V7K BATT_B 1 7/11 2 1 2 V I/O 1 3 2 PC13 0.01U_0402_50V7K 5 PR9 100_0402_5% 2 1 1 2 PC15 100P_0402_50V8J 1 PR8 100_0402_5% 2 1 2 2 1 3 6 PC16 100P_0402_50V8J PR16 100K_0402_5% 1 1 2 2 A PQ2A ME2N7002DKW-G 2N SOT363-6 SB00000SA00 ME2N7002DKW-G 2N SOT363-6 PQ2B PR7 1K_0402_5% 2 1 FOX_BR0208C-Z71H1-9H CONN@ 5 PC14 100P_0402_50V8J 4 PR15 300_0402_5% +3VDS B V BUS Ground PD12 L30ESD24VC3-2_SOT23-3 2 2 2 1 1 2 6 SB00000SA00 PC3 1000P_0402_50V7K +3VDS 1 PQ1A D PC7 0.01U_0402_50V7K SD028680380 5 ME2N7002DKW-G 2N SOT363-6 ME2N7002DKW-G 2N SOT363-6 4 PQ1B 1 2 PL5 HCB2012KF-121T50_0805 C PR10 680K_0402_5% 1 PR13 3.9K_0402_5% 2 300K_0402_5% 2 BATT_A PL4 HCB2012KF-121T50_0805 1 2 VIN 3 PR14 1 [30] PC8 100P_0402_50V8J 1 PD1 L30ESD24VC3-2_SOT23-3 VIN C PR3 1K_0402_5% 2 1 @ ACES_59012-0100N-002 @ PR1 15K_0402_5% VMB_A PC2 0.1U_0603_50V7K 7/11 2 10 1 10 8 PJP2 @ FOXCONN BP0208C-B24B1-9H 8P BATT 1 1 2 2 3 I2C_MAIN_DAT-1 3 4 I2C_MAIN_CLK-1 4 5 5 6 6 7 7 8 8 2 9 6 1 8 ADPIN PC4 1000P_0402_50V7K 6 7 4 2 5 2 2 9 4 1 7 2 3 PC1 100P_0402_50V8J 5 1 3 3 2 1 D VIN PC6 1000P_0402_50V7K 2 1 PJP1 PC5 100P_0402_50V8J 2 1 PL1 HCB2012KF-121T50_0805 1 2 PL2 HCB2012KF-121T50_0805 1 2 PL3 HCB2012KF-121T50_0805 1 2 [30] I2C_BAY_CLK [30] A [30] TRAVEL_BAT_DET# Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/03 Issued Date Deciphered Date 2014/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 I2C_BAY_DAT 3 2 Title DC Conn/BATT Conn Size Document Number Rev 0.3 15W Date: Thursday, December 20, 2012 Sheet 1 42 of 52 5 4 VIN P1 PC138 82P 50V J NPO 0402 PC108 68P_0402_50V8J 2 1 PC107 2200P_0402_50V7K 2 1 PC106 0.1U_0402_25V6 2 1 4 3 2 1 PC155 1U_0603_25V6K 1 PC154 2 1 PC118 0.01U_0402_50V7K 1 PC117 2 1 2200P_0402_50V7K PC116 2 10U_0805_25V6K 1 2 10U_0805_25V6K PC115 2 1 1 PD102 RB551V-30_SOD323-2 1 2 PC121 680P_0402_50V7K 3 2 1 2 2 PC120 1U_0603_25V6K 2 5 1 4 CSON1 REGN_CHG 3 1 16 2 PC114 0.1U_0402_25V6 17 PR112 PC112 2.2_0402_1% 0.047U_0402_25V7K 2BST_CHG-1 1 2 BST_CHG 1 4 PC113 0.1U_0402_25V6 DH_CHG C 1 CSOP1 18 PR111 4.7_1206_5% LX_CHG 1 19 PD103 RB751V-40_SOD323-2 2 1 DL_CHG BATT PR110 0.02_1206_1% PL102 4.7U 20% VMPI0703AR-4R7M-Z01 5.5A 1 2 CHG PQ106 AON7406L_DFN8-5 1 SNB_CHG 2 LODRV REGN 15 GND 14 SRP SRN PC105 10U_0805_25V6K 2 1 P1 4 0.1U_0402_25V6 2 8 7 6 5 2 PR108 2 VCC_CHG @ @ 1 B PR121 0_0402_5% 1 2 PC124 0.1U_0603_25V7K [30] 1 CURRENT_ADC 2 1 2 PC125 100P_0402_50V8J 2N7002KW 1N SOT323-3 PQ105 AO4409L 1P SO8 1 2 3 2.2_0402_1% PC111 1U_0603_25V6K 1 2 2 1 21 20 2 1 2 13 1 1 S P2 PR120 0_0402_5% 1 2 PR122 0_0402_5% 1 2 PQ108 3 [30] PR117 10K_0402_5% 1 2 V_3.9K D 2 G CHRG_RST [50] 2 1 2 PR119 20K_0402_1% 2 1 1 2 PR116 1M_0402_5% 2 PR118 10K_0402_1% B [30] 4/12 PC122 100P_0402_50V8J 1 1 PR115 127K_0402_1% PD104 LL4148_LL34-2 2 1 1 2 PR114 18.2K_0402_1% CHRG_ADP_DET ILIM SRP_CHG VIN 2 PR113 22K_0402_1% BTST DLIM SRSET 4/11 SCL PC119 0.01U_0402_50V7K 1 [50] 9 10 2 +5VS 1 2 PR128 10_0402_1% 4/12 HIDRV 12 I2C_MAIN_CLK SDA 11 [30,42] +3VDS 8 @ 5 1 1 PR109 10_1206_1% VCC PHASE SRN_CHG I2C_MAIN_DAT @ PQ104 AON7408L_DFN8-5 IOUT PC123 0.01U_0402_50V7K [30,42] 7 PC104 10U_0805_25V6K 2 1 2 1 2 PC110 0.1U_0402_25V6 B+ C ICS PR127 10_0402_1% 1 2 @ D for RF request, 8/6 PAD 2 ACP ACN 2 1 PC109 0.1U_0402_25V6 3 5 ACDET CMSRC 6 ACDRV [30] 4 PU102 BQ24736RGRR_QFN20_3P5X3P5 ACPRES 1 1 1 4 2 1 PR105 4.12K_0603_1% 1 2 PR104 4.12K_0603_1% 2 1 PD101 BAT54WS-7-F_SOD323-2~D @ PR107 100K_0402_5% 2 3 PL101 1UH_PCMB053T-1R0MS_7A_20% 1 2 ACN_CHG 3 2 ACP_CHG PQ103B ME2N7002DKW-G 2N SOT363-6 PR102 0.005_1206_1% 4 PC102 0.1U_0402_25V6 1 2 SB00000SA00 ADP_EN 1 CMSRC_CHG 4 5 ACDRV_CHG 5 B+ CHRG_ADP_DET +3VDS 1 2 3 4 1 2 PR103 220K_0402_5% 2 1 PC101 0.1U_0402_25V6 1 PR101 220K_0402_5% 2 6 PQ103A ME2N7002DKW -G 2N SOT363-6 1 PQ102 MDU1512RH 1N POW ERDFN56-8 AO4423L 1P SO8 8 7 6 5 ACFET_CHG 2 P2 2 PC103 10U_0805_25V6K 2 1 PQ101 1 2 3 D 3 PC126 @ 0.22U_0402_6.3V6K Remove 6 *2200pF MLCC for RF request, 11/6 2 PR126 49.9K_0402_1% @ @ PC153 82P 50V J NPO 0402 1 2 @ PC152 6.8P_0402_50V8C 2 1 PC151 0.1U_0402_25V6 PC149 82P 50V J NPO 0402 2 1 1 PC148 6.8P_0402_50V8C 2 1 @ @ PC128 0.22U_0402_6.3V6K for RF request, 8/6 2012/04/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2014/12/31 Deciphered Date Title CHARGER THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 @ 2 @ PC147 0.1U_0402_25V6 @ PC145 82P 50V J NPO 0402 2 1 1 PC144 6.8P_0402_50V8C 2 1 @ 2 @ PC143 0.1U_0402_25V6 @ PC141 82P 50V J NPO 0402 2 1 1 PC137 6.8P_0402_50V8C 2 1 @ 2 @ PC136 0.1U_0402_25V6 @ PC140 82P 50V J NPO 0402 2 1 1 PC134 6.8P_0402_50V8C 2 1 @ 2 @ PC133 0.1U_0402_25V6 1 PC139 82P 50V J NPO 0402 2 1 @ 1 @ PC131 6.8P_0402_50V8C 2 1 [30] 1 VOLTAGE_ADC 2 1 SD034576380 2 1 2 A PR125 576K_0402_1% 1 2 PC127 100P_0402_50V8J PR124 49.9K_0402_1% 1 2 2 VIN PC130 0.1U_0402_25V6 B+ 4 3 2 Document Number Rev 0.3 15W Sheet Thursday, December 20, 2012 1 43 of 52 A 4 3 PQ306 2N7002KW 1N SOT323-3 +5VLP PJP306 JUMP_43X39 1 2 1 2 1 1 2 PC325 100P_0402_50V8J PC323 68P_0402_50V8J 1 PC309 0.1U_0402_25V6 2 1 2 1 1 PC308 2200P_0402_50V7K 2 @ PC332 6.8P_0402_50V8C 2 1 1 2 PC331 2200P_0402_50V7K 2 1 1 PC302 4.7U_0805_10V6K + @ @ for RF request, 8/6 +5VLP Typ: 225mA 1 2 PC316 1U_0402_10V6K 2 1 2 ENLDO_3V_5V 1 B++ Typ: 175mA 1 2 +3VLP 2 4 1 2 PQ304 +5VDSP PC330 0.1U_0402_25V6 2 1 LG_5V PC315 220U_6.3V_M 16 PL302 2.2UH +-20% ETQP3W 2R2W FN 8.5A 1 2 1 LX_5V PR315 4.7_1206_5% UG_5V PC312 680P_0402_50V7K 18 17 SIS412DN-T1-GE3_POW ERPAK8-5 PC333 100P_0402_50V8J 19 AON7406L_DFN8-5 PR321 499K_0402_1% 1 2 PC307 10U_0805_25V6K C for RF request, 8/6 3 2 1 FB1 LDO3 LDO5 ENM LGATE1 @ 4 PR312 PC311 2.2_0603_5% 0.1U_0603_25V7K 2 BST_5V-1 1 2 BST_5V 1 15 14 12 11 13 LGATE2 VIN 10 @ 21 MDV1526URH_PDFN33-8-5 2 ENTRIP1 3 PHASE2 @ 20 5 9 PQ302 2 1 2 5 1 FB_5V PC321 1U_0402_10V6K 2 LX_3V UGATE2 B++ For RF request, 11/5 PC306 10U_0805_25V6K PR309 115K_0402_1% 1 ENTRIP1 2 FB_3V 4 5 BOOT2 5 PR314 4.7_1206_5% 2 1 PJP303 JUMP_43X118 1 2 1 2 8 4 PC319 0.1U_0603_25V7K 2 1 +3VDSP UG_3V LG_3V PQ303 B PJP302 JUMP_43X118 1 2 1 2 PAD BYP1 PHASE1 for RF request, 8/6 +5VDSP 7 PGOOD UGATE1 1 2 3 2 PC313 680P_0402_50V7K 2 1 + PC314 220U_6.3V_M @ PC329 100P_0402_50V8J @ PC328 6.8P_0402_50V8C 2 1 PC327 2200P_0402_50V7K 2 1 1 PC326 0.1U_0402_25V6 2 1 2 @ 1 PR307 20K_0402_1% 1 2 RT8243AZQW W QFN 20P BOOT1 PL303 4.7U 20% VMPI0703AR-4R7M-Z01 5.5A 1 2 +3VDSP 6 TON PG_3V_5V PC310 PR313 0.1U_0603_25V7K 2.2_0603_5% 2 1BST_3V-1 1 2 BST_3V PR325 100K_0402_1% 2 1 SH00000PH00 3VDS_PG PU301 (Vin=6.5 ~ 12v) (Vin=12 ~ 25v) +5VDSP 3 2 1 1 2 3 for RF request, 8/6 @ PR311 0_0402_5% 1 2 ENTRIP2 4 For RF request, 11/5 C For HP request, 11/5 FB2 PQ301 SIS412DN-T1-GE3_POWERPAK8-5 5 PC334 10U_0805_25V6K 1 PC303 10U_0805_25V6K 2 1 @ PR310 1 PR306 20K_0402_1% 2 1 2 1 PC304 0.1U_0402_25V6 @ 2 1 PC305 2200P_0402_50V7K 2 1 2 PC322 68P_0402_50V8J 1 2 @ <1>5V=283KHz 3V=330KHz <2>5V=321KHz 3V=375KHz (By Rton= 68K ohm) PR305 30K_0402_1% 2 1 68K_0603_5% 2 PR304 13.7K_0402_1% 1 2 2 @ PJP301 PAD-OPEN 1x3m PC324 100P_0402_50V8J 1 +3VDSP PC320 100P_0402_50V8J 2 2 +3VLP 10K_0402_1% PR324 B++ 1 ENLDO B+ SB00000SA00 D PR308 124K_0402_1% 1 ENTRIP2 2 1 ME2N7002DKW-G 2N SOT363-6 KBC_PWR_ON PR316 @ 0_0402_5% [30,33,39,40,45] 1 2 EN_P1V5 3 6 2 3 4 [30,34] 1 PQ305A PQ305B 5 2 S ME2N7002DKW-G 2N SOT363-6 1 2 PR326 100K_0402_1% D D 2 G +5VLP +3VDS 1 5 B PC317 4.7U_0805_10V6K +5VDS +3VDS +5VL A A Compal Secret Data Security Classification 2011/06/13 Issued Date 2014/12/31 Deciphered Date Title Compal Electronics, Inc. 3VDSP/5VDSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Thursday, December 20, 2012 Date: Rev 0.3 15W 5 4 3 2 Sheet 1 44 of 52 5 3 For RF request, 11/5 PC406 4.7U_0805_25V6-K PR402 0_0402_5% 1 2 +1.35VP 1 2 PC408 10U_0805_6.3V6K 1 21 PC407 10U_0805_6.3V6K +0.675VSP 20 2 +1.35VP 19 VTT BST_1.35V 18 VLDOIN DH_1.35V BOOT PAD VDDP 1 3 4 VTTREF_0.675V 5 +1.35VP FB 1 +1.35VP 6 7 PC413 0.033U_0402_16V7K S3_1.35V FB_1.35V C 1.35V_PG 7/11 2 2 PR419 @ 100K_0402_5% 1 2 TON_1.35V +3VS S3 PC412 1U_0603_10V6K 10 PC411 1U_0603_10V6K VDDQ S5 VDD VTTREF 8 11 GND RT8207MZQW _W QFN20_3X3 1 VDD_1.35V CS VTTSNS TON +5VDS 1 MDV1526URH_PDFN33-8-5 2 1 2 3 PC410 680P_0603_50V7K C +5VDS PR405 5.1_0603_5% 1 2 13 12 2 2 1SNB_1.35V 4 2 2 PU401 VTTGND PGND PGOOD PR404 4.7_1206_5% 330U_2.5V_M PC409 + LGATE 9 14 PR403 15.8K_0402_1% 1 2 CS_1.35V PQ402 1 15 UGATE DL_1.35V D 2 1 +1.35VP SIS412DN-T1-GE3_POW ERPAK8-5 5 1 1 2 3 PL402 2.2UH_VMPI0703AR-2R2M-Z01_8A_20% PHASE 4 LX_1.35V PQ401 for RF request, 8/6 16 +0.675VSP 5 D 1 PR418 2.2_0603_5% 1 2 17 @ PC405 10U_0805_25V6K 2 1 @ PC404 2200P_0402_50V7K 2 1 @ PC403 0.1U_0402_25V6 2 1 PC401 68P_0402_50V8J 2 1 1 2 @ 2 PC402 0.22U_0402_10V6K 1 2 B+_1.35V PC419 82P 50V J NPO 0402 2 1 B+ 4 PL401 HCB1608KF-121T30_0603 1 2 PR406 10.2K_0402_1% 1 2 +1.35VP PR407 887K_0402_1% 2 B+_1.35V1 1 PR408 42.2K_0402_1% 1 2 2 PC415 .1U_0402_16V7K 2 1 D [30,5] +0.675VSP A PJP401 JUMP_43X118 1 2 PJP402 JUMP_43X39 1 2 1 2 +1.35V +0.675VS A Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/03 Issued Date Deciphered Date 2014/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 1 2 KBC_DS3_EN +1.35VP 5 PR415 10K_0402_5% 2 PR420 42.2K_0402_1% 3 2 SLP_S4# B [14] 3 1 1 2 @ PC417 0.1U_0402_10V7K 1 @ PC416 0.1U_0402_10V7K 8/1 DDR3_SET S PD401 BAT54CW _SOT323-3 [14] PQ403 2N7002KW 1N SOT323-3 2 G 1 2 PR412 0_0402_5% 1 2 SLP_S3# 2 1 2 2 PR416 4.7K_0402_5% [14,30,31,34] PC418 0.22U_0402_16V7K PR411 10.2K_0402_1% 1 B PR417 100_0402_5% 1 EN_P1V5 1 [30,33,39,40,44] 3 2 Title DDR Power Size Document Number Rev 0.3 15W Date: Thursday, December 20, 2012 Sheet 1 45 of 52 5 4 3 2 1 PL501 @ 1 2 1 PC512 68P_0402_50V8J @ 2 2 1 PC503 2200P_0402_50V7K 1 PC502 0.1U_0402_25V6 2 1 PC505 4.7U_0805_25V6-K 2 1 2 @ B+ D 5 +3VS PC504 4.7U_0805_25V6-K D PC513 100P_0402_50V8J HCB2012KF-121T50_0805 1 2 B+_1.05V 1 PQ501 for RF request, 8/6 @ PR511 100K_0402_5% 1.05VM_PG 4 2 [31] PR502 PC506 2.2_0603_5% 0.22U_0603_16V7K 1 2BST_1.05V-1 1 2 7/17 RF DRVL 1 TP @ PL502 2.2UH +-20% ETQP3W 2R2W FN 8.5A 1 2 7 6 +5VDS 4/11 DL_1.05V 11 TPS51212DSCR_SON10_3X3 PR506 470K_0402_1% 3 2 1 LX_1.05V +1.05VMP 1 V5IN 8 SIS412DN-T1-GE3_POW ERPAK8-5 PC507 1U_0603_6.3V6M PR505 4.7_1206_5% PQ502 4 C 1 2 5 VFB DH_1.05V + PC510 330U_2.5V_M 1SNB_1.05V RF_1.05V SW BST_1.05V 9 2 4 EN 10 AON7406L_DFN8-5 FB_1.05V DRVH 5 3 VBST TRIP 1 EN_1.05V PGOOD 2 2 3 2 1 2 1 C TRIP_1.05V 2 SIO_SLP_A# PR504 100_0402_5% 1 2 PC508 .1U_0402_16V7K ,30,31] PU501 1 PR503 86.6K_0402_1% 1 2 2 PC511 680P_0603_50V7K PR508 5.11K_0402_1% 2 1 1 2 PQ503 2N7002KW 1N SOT323-3 D PR510 10K_0402_1% 2 G S 1 KBC_PWR_ON# 3 34] PJP501 B 2 +1.05VMP 2 1 1 B +1.05VM @ JUMP_43X79 4/11 A A Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/03 Issued Date Deciphered Date 2014/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title 1.05VMP Size Document Number Rev 0.3 15W Date: Thursday, December 20, 2012 Sheet 1 46 of 52 5 PWM2 1 2 PR217 0_0402_5% SKIP EMI Part (47.1) PJP201 1 +5VDS CPU_B+ 1 2 1 2 @EMI@ PL201 FBMA-L11-453215-800LMA90T_1812 Acoustic (37.2) BOOT VDD PWM SKIP# 2 3 1 4 0.15UH +-20% ETQP4LR15AFM 29A PL204 2 1 1 2 PR233 0_0402_5% SKIP KBC_PROC_HOT_R PC213 2 1 0.15U_0402_10V6K 3 PR245 2.2_0402_5% 1 2 1 SDIO PC261 PWM2 ALERT# 5 6 2 7 .1U_0402_16V7K 8 VIN PGND2 VSW BOOT_R PGND1 BOOT PWM VDD SKIP# 4 2 3 1 4 0.15U_0402_10V6K PC217 2 1 PH204 PR239 3.01K_0402_1% 2 1 2 EMI@ PC263 EMI@ PR249 470P_0402_50V7K 4.7_1206_5% 1 2 1 2 9 10U_0805_25V6K PC205 2 1 10U_0805_25V6K @RF@ PC269 82P 50V J NPO 0402 PC204 2 1 @RF@ PC266 68P_0402_50V8J 2 1 EMI@ PC208 2200P_0402_50V7K 2 1 2 PC256 .1U_0402_16V7K EMI@ PC207 0.1U_0402_25V6 2 1 1 2 PR232 100_0402_5% 1 2 PR231 100_0402_5% 1 2 2 PR228 0_0402_5% PR235 63.4K_0402_1% 2 1 EMI Part (47.1) CPU_B+ 10K_0402_1%_TSM0A103F34D1RZ PR250 2.1K_0402_1% 2 1 CSP2 CSN2 +VCC_CORE 3 0.15UH +-20% ETQP4LR15AFM 29A PL202 2 1 1 PU203 CSD97374CQ4M_SON8_3P5X4P5 2 PR247 0_0402_5% SKIP SCLK 4 PC262 1U_0402_6.3V6K 2 1 VR_HOT# +5VDS Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 2011/06/24 Deciphered Date 2014/12/31 Title PWR-CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.3 Date: A CSN1 +5VDS 2 1 @ PC206 47P_0402_50V8J CSP1 RF Part (47.3) PC216 1U_0402_6.3V6K 2 1 2 [24,5] VR_SVID_CLK + 2 +VCC_CORE 3 1 BOOT_R PGND1 4 2 VSW 1 [9] 1 @RF@ PC258 220P_0402_25V8K 2 7 .1U_0402_16V7K 8 PGND2 1 1 1 6 VIN 2 5 PH203 1 9 PC212 2 1 EMI@ PC259 EMI@ PR240 470P_0402_50V7K 4.7_1206_5% 1 2 1 2 10U_0805_25V6K @RF@ PC267 82P 50V J NPO 0402 PC211 2 1 @RF@ PC264 68P_0402_50V8J 2 1 1 2 +3VS EMI@ PC215 2200P_0402_50V7K 2 1 CPU_B+ PR229 3.01K_0402_1% 2 1 2 PR225 63.4K_0402_1% 2 1 EMI Part (47.1) EMI Part (47.1)RF Part (47.3) EMI@ PC214 0.1U_0402_25V6 2 1 1 PR253 47K_0402_1% 2 PAD PC250 1U_0603_10V6K PR252 10_0402_1% 1 2 2.1K_0402_1% 2 1 SDIO 10K_0402_1%_TSM0A103F34D1RZ PR241 [31] 2 1 1 4 + 2 @RF@ PC257 68P_0402_50V8J VGATE PC253 PR230 100_0402_5% 1 2 VR_SVID_ALRT# 1 2 3 PWM1 1 1 [9] 2 PR236 22_0402_5% 1 2 PR237 22_0402_5% 1 2 PR238 22_0402_5% 1 B+ PWM3 EMI Part (47.1) RF Part (47.3) VR_SVID_DAT 2 PAD-OPEN 1x3m @ 4 +VCCIO_OUT [9] 0.15U_0402_10V6K PC209 2 1 10K_0402_1%_TSM0A103F34D1RZ PR214 63.4K_0402_1% 2 1 PH202 1 1 [30,31,5] PR223 2.2_0402_5% 1 2 PC254 1U_0603_10V6K PR216 3.01K_0402_1% 2 1 2 PC230 2 1 10U_0805_25V6K 9 2 SKIP# PR226 10_0603_1% 1 2 +5VDS +VCC_CORE 0.15UH +-20% ETQP4LR15AFM 29A PL203 PU202 CSD97374CQ4M_SON8_3P5X4P5 3 1 PC235 100U_25V_M PWM1 CSN3 PC234 100U_25V_M 6 PWR_GD 4 CSP3 3 VDD PWM 3 1 + 1 F-IMAX BOOT 2 PC233 100U_25V_M SKIP 2 PC203 0.33U_0402_10V6K 4 VSW BOOT_R PGND1 2 7 .1U_0402_16V7K 8 CPU_VREF PR215 PC245 10K_0402_1% 330P_0402_50V7K 1 2 1 2 PGND2 9 7 2 PR219 2.94K_0402_1% 1 2 6 10U_0805_25V6K B-RAM 10 11 B-RAMP 12 OCP-I 15 13 IMON O-USR VDIO 33 25 PR220 10K_0402_1% 1 2 ALERT# 2 VDD VCLK VFB PR224 0_0402_5% PC246 @ 2.2P_0402_50V8C 1 2 14 GFB 32 24 8 PR227 0_0402_5% 1 2 ALERT# 1 23 VFB SCLK VCCSENSE GFB PW M3 PGOOD VR_HOT# [9] PR221 0_0402_5% 1 2 CSN3 VR_HOT# 22 31 CSN3 PW M2 TPS51631RSMR_QFN32_4X4 CSP3 VIN PC210 1U_0402_6.3V6K 2 1 VR_ON CSP2 30 21 GND 20 5 PU204 CSD97374CQ4M_SON8_3P5X4P5 PW M1 29 VSSSENSE 1 PC248 CSN2 V5A CSP2 CSP3 EMI@ PR243 EMI@ PC260 470P_0402_50V7K 4.7_1206_5% 1 2 1 2 PR218 2.2_0402_5% 2 1 PWM3 SKIP# 28 19 2 [10,9] 10U_0805_25V6K @RF@ PC268 82P 50V J NPO 0402 PC229 2 1 @RF@ PC265 68P_0402_50V8J 2 1 EMI@ PC238 2200P_0402_50V7K 2 1 2 1 PR211 2 20K_0402_1% 1 2 PR209 150K_0402_1% 1 PR207 2 PR205 2 100K_0402_1% 1 1 CPU_B+ F-IMAX CSN1 VREF CSN2 CSP1 27 18 THERM 16 VBAT +3VS 17 CSN1 COMP @ PR242 0_0402_5% 1 2 CSP1 DROOP 37W pop, 47W up unpop SLEWA PU201 PR244 2.1K_0402_1% 2 1 EMI Part (47.1) EMI Part (47.1) RF Part (47.3) O-USR 26 CPU_B+ OCP-I SLEWA PR212 10K_0402_1% 2 1 D phase3 37W pop, 47W up unpop EMI@ PC232 0.1U_0402_25V6 2 1 1 PR210 2 36.5K_0402_1% 2 PR208 1 255K_0402_1% @ PR206 2 1 100K_0402_1% 2 PR204 1 88.7K_0402_1% 1 PC201 2 C 2 2 PR202 39K_0402_1% 39K_0402_1% 1 PR203 1 1 .1U_0402_16V7K 2 2 @ PR201 10K_0402_1% PH201 1 1 CPU_VREF 4700P_0402_16V7K B 10K_0402_1% 100K_0402_1%_TSM0B104F4251RZ PC202 2 1 A B C Sheet D 47 of 52 5 4 +VCC_CORE 3 2 1 2 X 470u/4m 30 X 22u/0805 +VCC_CORE 1 PC2012 22U_0805_6.3V6M 2 1 PC2023 22U_0805_6.3V6M 2 1 2 PC2034 22U_0805_6.3V6M 1 PC2011 22U_0805_6.3V6M 2 1 PC2022 22U_0805_6.3V6M 2 1 2 PC2033 22U_0805_6.3V6M 1 PC2010 22U_0805_6.3V6M 2 1 PC2021 22U_0805_6.3V6M PC2009 22U_0805_6.3V6M PC2020 22U_0805_6.3V6M 2 1 2 PC2032 22U_0805_6.3V6M 1 2 1 2 PC2031 22U_0805_6.3V6M PC2008 22U_0805_6.3V6M 1 2 2 1 2 1 2 PC2019 22U_0805_6.3V6M PC2007 22U_0805_6.3V6M 1 PC2030 22U_0805_6.3V6M 1 2 1 PC2018 22U_0805_6.3V6M PC2006 22U_0805_6.3V6M 2 2 2 1 2 1 PC2029 22U_0805_6.3V6M 1 PC2017 22U_0805_6.3V6M 2 PC2028 22U_0805_6.3V6M 1 PC2005 22U_0805_6.3V6M 2 2 1 2 1 PC2016 22U_0805_6.3V6M 1 PC2027 22U_0805_6.3V6M 2 1 2 PC2015 22U_0805_6.3V6M 1 PC2026 22U_0805_6.3V6M 1 2 PC2014 22U_0805_6.3V6M 1 PC2025 22U_0805_6.3V6M 2 2 1 2 1 2 C 1 + PC2013 22U_0805_6.3V6M 2 PC2024 22U_0805_6.3V6M 1 + @ PC2002 470U_D2_2VM_R4.5M D PC2001 470U_D2_2VM_R4.5M D C B B A A Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/03 Issued Date Deciphered Date 2014/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PROCESSOR DECOUPLING Size Document Number Rev 0.3 LA-9371P Date: Thursday, December 20, 2012 Sheet 1 48 of 52 A B C D 1 2 1 2 1 +1.5VS 1 1 2 1 PC606 22U_0805_6.3VAM +1.5V_PCIEP TDC=0.46A Peak Current=0.66A 2 1 2 +3VS @ PC603 0.1U_0402_10V7K PC605 22U_0805_6.3VAM EN_1.5V 1 1 2 +1.5VSP @ JUMP_43X39 2 EN PR602 10K_0402_5% 1 2 PC604 22P_0402_50V8J FB 2 PJP601 +1.5VSP 1 GND LX_1.5V 1 PG 3 2 1 2 PC601 22U_0805_6.3VAM 6 LX 2 5 IN 4X4 PL602 0.47UH +-20% PCMC042T-R47MN 6A 1 2 PR603 150K_0402_1% 4 2 PR601 4.7_0402_1% 1 2 1 1 PU601 SY8032ABC_SOT23-6 2 2 PJP602 JUMP_43X39 @ SNUB_+1.5V 7/17 PC602 680P_0402_50V7K 1 +3VS [31] PR604 100K_0402_1% 2 1 1.5VS_PG 7/17 @ PR605 100K_0402_5% 2 1 PQ601 2N7002KW 1N SOT323-3 D 2 G SLP_S3 3 [34,9] +3VS S 3 3 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/03 Deciphered Date 2014/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title 1.5VSP Size Document Number Rev 0.3 15W Date: Thursday, December 20, 2012 D Sheet 49 of 52 5 4 3 2 1 D D 3 1 [43] 1 2 PR1110 8.06K_0402_1% 2 2 B PR1112 100K_0402_5% 1 2 2 B E VIN 3 OCP_A_IN [30] 1 +3VDS 3 1 PC1103 3900P_0402_50V7K 2 PQ1104 MMBT3906H_SOT23-3 1 PD1102 @ GLZ4.7B_LL34-2 PR1119 3.24K_0402_1% 2 2 2 2 2 PR1118 130K_0402_1% PR1117 45.3K_0402_1% 2 1 1 1 3 S PR1116 @ 3.9K_0402_5% B [30] C B 1 2 2 1 ADP_A_ID 2 G ADP_ID_CHK PR1115 619_0402_1% 2 PR1114 220K_0402_5% C PQ1103 MMBT3904W H_SOT323-3 E 30] [43] E 1 1 1 C 3 1 PQ1102 MMBT3906H_SOT23-3 PR1113 8.66K_0402_1% PQ504 2N7002KW 1N SOT323-3 D SRSET C 2 PR1125 13K_0402_1% C PR1109 100K_0402_5% V_3.9K 2 G +3VDS 1 1 1 D S ADP_SIGNAL +3VDS PQ1101 NDS0610_NL_SOT23-3 PR1108 100_0402_5% 1 2 PR1120 470K_0402_1% 1 2 P1 B 1 1 +3VDS +5VL PR1122 47K_0402_5% 2 - 4 O 1 2 + ADP_PRES [30] PU1102A LM393DR2G SO8 PR1124 47K_0402_5% @ PC1104 0.01U_0402_16V7K 2 2 PR1126 100K_0402_1% 2 1 1 1 2 PR1123 86.6K_0402_1% P 1 3 G 2 8 PR1121 200K_0402_1% +5VL A A Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/03 Issued Date Deciphered Date 2014/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title ADP_OCP Size Document Number Rev 0.3 15W Date: Thursday, December 20, 2012 Sheet 1 50 of 52 4 3 2 1 1 5 2 MFET_B 1 3 PD1201 BAV99W T1G_SC70-3 PR1202 10K_0402_5% 1 2 PR1201 10K_0402_5% 2 BATT_A D 1 1 PQ1203 AO4409L 1P SO8 PQ1205 AO4409L_SO8 8 7 6 5 BATT_A 1 2 3 [30] 2 6 FET_A SB00000SA00 BATT_B C 1 2 4 PR1208 220K_0402_5% 2 4 PR1207 470K_0402_5% 3 2 1 2 PQ1204 AO4409L 1P SO8 PQ1206 AO4409L 1P SO8 8 7 6 5 1 1 2 3 C 5 6 7 8 2 4 4 5 6 7 8 3 2 1 BATT PR1206 220K_0402_5% 1 2 PR1205 470K_0402_5% 5 +3VDS PQ1202A ME2N7002DKW-G 2N SOT363-6 2 1 LATCHED_ALARM PR1204 470K_0402_5% 1 2 SX34H_SMA2 6 PR1203 10K_0402_5% MFET_A PQ1201A ME2N7002DKW-G 2N SOT363-6 2 PQ1201B ME2N7002DKW-G 2N SOT363-6 4 3 SB00000SA00 1 PD1202 1 1 D PD1203 1 2 PR1209 10K_0402_5% MFET_B 2 SX34H_SMA2 1 PR1213 1M_0402_5% 1 2 [30] 2 2 +3VDS 3 PD1204 BAV99W T1G_SC70-3 B PR1211 470K_0402_5% 5 4 5 PQ1207A ME2N7002DKW-G 2N SOT363-6 1 6 LATCHED_ALARM PQ1207B ME2N7002DKW-G 2N SOT363-6 3 SB00000SA00 4 2 10K_0402_5% PR1212 3 2 2 FET_B ME2N7002DKW-G 2N SOT363-6 PQ1202B PR1210 10K_0402_5% 1 MFET_A 1 1 BATT_B SB00000SA00 B +3VDS +5VL 4/11 +3VDS 4/11 4/11 1 1 1 BATT 2 + - O 1 PR1217 64.9K_0402_1% 4 1 6 P 2 5 G PR1216 200K_0402_1% PC1201 0.1U_0603_25V7M PR1215 100K_0402_5% 2 8 2 1 PR1214 10K_0402_5% 7 LATCHED_ALARM LATCHED_ALARM [30] PU1102B LM393DR2G SO8 1 2 PR1218 137K_0402_1% D 2 A 3 S A 2 G PQ1209 2N7002KW 1N SOT323-3 Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/03 Issued Date Deciphered Date 2014/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Battery selector Size Document Number Rev 0.3 15W Date: Thursday, December 20, 2012 Sheet 1 51 of 52 5 4 3 2 V ersion Change L ist ( P. I. R . L ist ) Item Page# Title D ate R equest O w ner 1 Page 1 Issue D escription Solution D escription R ev. D D 2012/08/06 C 1 43 2 44 Reserve PC324,322,323,325326,327,328,329,330,331,332,333 2012/08/06 RF solution 3 44 Add PC305,304,308,309 2012/08/06 RF solution 4 45 Reserve PC419,401 2012/08/06 RF solution 5 45 Add PC403,404,405 2012/08/06 RF solution 6 46 Reserve PC512,513 2012/08/06 RF solution Reserve PC130,129,131,139,133,132,134,140,136,135,137,141,143,142,144,145,146,147,148,149,151,150,152,153,138 RF solution 7 46 Add PC502,503 2012/08/06 RF solution 8 48 Reserve PC264,267,266,269,265,268 2012/08/06 RF solution 9 48 Add PC214,215,207,203,232,236 2012/08/06 10 48 Change PC233,234 from SF000001280 to SF000004M00 2012/08/09 11 47 Change PR234 from 19.1K to 62K 2012/08/10 HP suggestion 12 48 Change PQ203,204,211 from SB00000K300 to SB00000U300 2012/09/11 Design change 13 48 Change PQ201,205,209 from SB00000SJ00 to SB00000WX00 2012/09/13 Design change 14 44 Change PQ301,302 from SB00000JM00 to SB00000IA00 2012/09/17 Design change 15 44 Change PQ303 from SB00000CT00 to SB00000H700 2012/09/17 Design change 16 44 Change PQ304 from SB00000N800 to SB00000TZ00 2012/09/17 Design change 17 45 Change PQ401 from SB00000H800 to SB00000IA00 2012/09/17 Design change 18 45 Change PQ402 from SB00000N800 to SB00000TZ00 2012/09/17 Design change 19 46 Change PQ501 from SB00000H800 to SB00000IA00 2012/09/17 Design change 20 46 Change PQ502 from SB00000N800 to SB00000H700 2012/09/17 21 51 Reserve PR1101,1102,1103,1104,1105,1106,1107,PC1101,1102,PU1101,PD1101 2012/09/25 HP suggestion 22 45 Change PD401 from SC600000D00 to SCS00006400 2012/10/2 HP suggestion 23 45 Change PR416 from SD034100380 to SD028470180 2012/10/2 HP suggestion 24 43 Change PL101 from SH00000MR00 to SH00000NW00 2012/10/2 Design change 25 23 Change PR240,243,249 from SD001470B80 to SD000010280 2012/10/2 Design change 26 23 Reserve PL201 2012/10/2 Design change 27 25 Reserve PL301 2012/10/2 Design change RF solution Change the hieght to 6mm C Design change B B A A Compal Secret Data Security Classification 2011/10/03 Issued Date 2014/12/31 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Compal Electronics, Inc. PWR - PIR Document Number Rev 0.3 LA-9241P Thursday, December 20, 2012 Sheet 1 52 of 52 5 4 VBL20 from DB0 to DB1 LA-9241P REV:0.1 -> 0.2 Modify <2012.07.04.~2012.08.07. > Rev. Item Date Impact Page Change Cause D C 3 2 Modify Description 0.2 1 7/6 CKT 13 -Follow HP GPIO table -Change UH1.B17 to HDD_HALTLED 0.2 2 7/6 CKT 14,37 -Follow HP GPIO table -Change UH1.G17 and U30.26 to PWRSV_SEL#. 0.2 3 7/6 CKT 15 -Follow HP GPIO table -Change UH1.U4 to WLAN_TRAMSIT_OFF# 0.2 4 7/6 CKT, LAYOUT 16 -For NFC function -Change UH1.H6 to NFC_RST#, and add QH10, RH238, RH239 for NFC SMBUS level shift 0.2 5 7/6 CKT, LAYOUT 18,23 -Follow HP GPIO table -Change UH1.C16 to ODD_EN. Change Q25.1 netname to ODD_EN and Q25.2 netname to ODD_EN# 0.2 6 7/6 CKT, LAYOUT 18 -Follow HP GPIO table -Change UH1.U12 and RH185.1 to NFC_INT 0.2 7 7/6 CKT, LAYOUT 19 -Add PU resistor to avoid issue. -Add RH240 and RH241PU resistor of THERM_SCI# and WWAN_TRANSMIT_OFF# 0.2 8 7/6 CKT, LAYOUT 22 -eDP MUX -Modify eDP connector signal source from eDP MUX. 0.2 9 7/6 CKT 23 -Power driving -Change R1316 from 100K to 10K ohms D 0.2 10 7/6 CKT, LAYOUT 25 -Change WWAN connector to NFCC -Modify JMINI3 connector type and pin define 0.2 11 7/6 CKT, LAYOUT 26 -Move Mute circuit to S/B -Move QA2 and R95 to S/B 0.2 12 7/6 CKT, LAYOUT 26 -Audio Combo Jack -Delete MIC_SENSE# circuit. 0.2 13 7/6 CKT, LAYOUT 27 -Follow reference design -Change C91 and C94 to 2.2uF as spec 0.2 14 7/6 CKT, LAYOUT 28 -No ACCELEROMETER LED -Delete LED1 0.2 15 7/6 CKT, LAYOUT 29 -NIC yellow ban issue -Add C350 and C373 to +1.05VM_LAN 0.2 16 7/6 CKT, LAYOUT 30 -Follow HP KBC pin define. -Modify U17 pin define. 0.2 17 7/6 CKT, LAYOUT 34 -Avoid leakage issue 0.2 18 7/6 CKT, LAYOUT 35 -MXM no display out issue -Swap JMXM1 PEG TX and RX bus 0.2 19 7/6 CKT, LAYOUT 36 -Avoid eDP signal quality fail issue -Change U42 to PS8321 which had include repeater function 0.2 20 7/6 CKT, LAYOUT 36 -To support DP1.2a -Change U26 to PS8338 to support DP1.2a spec. 0.2 21 7/6 CKT, LAYOUT 39 -Add NFC function -Add JNFC1 circuit. 0.2 22 7/9 CKT, LAYOUT 13 -HP request -Delete PCH XDP circuit 0.2 23 7/9 CKT, LAYOUT 13 -HP request -Add QH11 0.2 24 7/9 CKT, LAYOUT 16 -HP request -Delete U39, U40, RH232 0.2 25 7/9 CKT, LAYOUT 30 -HP request -Delete 16pin SPI ROM socket 0.2 26 7/9 CKT, LAYOUT 30 -HP request -Add R537,Q73 0.2 27 7/9 CKT, LAYOUT 35 -HP request -Swap MXM port A and port C for layout smoothly 0.2 28 7/9 CKT, LAYOUT 38 -Follow spec pin define -Modify JTP1 and JTP2 pin define 0.2 29 7/9 CKT, LAYOUT 39 -Follow spec pin define -Modify JNFC1 pin define 0.2 30 7/10 CKT, LAYOUT 6,11,12 -Following Intel CRB by HP request -Modify JCPU1 pin AM3,F16,F13 netname. Delete RC73,RC76,C13,C75. Add QD3,RD27,RD28 0.2 31 7/10 CKT, LAYOUT 8 -HP request -Delete RC106, RC107 0.2 32 7/10 CKT, LAYOUT 30 -HP request -Modify R537 to 10K ohms 0.2 33 7/10 CKT, LAYOUT 34 -HP request -Modify R363 to 4.7K ohms 0.2 34 7/11 CKT, LAYOUT 36 -Follow vendor request -Add CC75,CC76,CC77,CC78,CC79,CC80,CC81,CC82. Modify U26 circuit 0.2 35 7/11 CKT, LAYOUT 29 -HP request -Delete R135, R139, R151, R152, R140, R142 for layout. 0.2 36 7/12 CKT, LAYOUT 22 -HP request -Delete C6 0.2 37 7/12 CKT, LAYOUT 23 -HP request -Delete C54. Add R539. 0.2 38 7/12 CKT, LAYOUT 24 -HP request -Change U3 to TC7SET00 0.2 39 7/12 CKT, LAYOUT 24 -FAN module pin define wrong. -Modify JFAN1 pin define by follow latest spec. 0.2 40 7/12 CKT, LAYOUT 37 -Follow latest Smart card module pin define. -Modify J3 pin define. 0.2 41 7/12 CKT, LAYOUT 38 -Follow latest KB connector pin 1 location. -Modify JKB1 pin define. 0.2 42 7/13 CKT, LAYOUT 27,39 -Reduce layout spacing -Move R494,R495,LA5,LA9,CA37,CA38,DA4 to sub board 0.2 43 7/13 CKT, LAYOUT 30 -Correct KBC circuit -Change U17.68, C179.1, C188.1 to +RTCVCC. -Delete R224, R460, R220, R223, R496, R497, R498, R499, R244, R269, R236, RH220. -Change RH222.1, RH223.1, RH224.1, CH97.1, CH98.1, UH5.8 to +3VDS -Reserve R541, R542 for NFC TX/RX 0.2 44 7/13 CKT, LAYOUT 39 -Follow ME connector list -Modify JVGA1 footprint and pin define. 0.2 45 7/13 CKT, LAYOUT 39 -Follow ME connector list -Modify JTB1 pin define, add WL/BT_LED# signal. 0.2 46 7/16 CKT, LAYOUT 14 -ESD request -Reserve CH107 -Swap Q40 drain and source B C 0.2 47 7/16 CKT, LAYOUT 25 -ESD request -Reserve C375 0.2 48 7/16 CKT, LAYOUT 27 -ESD request -Change DA2 and DA3 P/N. 0.2 49 7/16 CKT, LAYOUT 27 -ESD request -Delete DA1 0.2 50 7/16 CKT, LAYOUT 28 -ESD request -Change D11 P/N 51 7/16 CKT, LAYOUT 29 0.2 1 -ESD request B -Change D12 and D13 P/N 0.2 52 7/16 CKT, LAYOUT 33 -ESD request -Add D42 0.2 53 7/16 CKT, LAYOUT 37 -Follow HP latest generation smart card connector pin define. -Modify J3 pin define. 0.2 54 7/16 CKT, LAYOUT 38 -ESD request -Change D32 P/N. 0.2 55 7/17 CKT 11 -Correct connector name -Change JP3 to JDIMM1 0.2 56 7/17 CKT, LAYOUT 36 -Change DP and eDP MUX to passive solution -Modify U26 and U42 to PI3VDP12412ZHEX and releate circuit. 0.2 57 7/17 CKT, LAYOUT 17,39 -Follow HP request -Modify JTB1 pin define. Add CH108, CH109, CH110, CH111. Connect PCIE port 1 and port 2 to JTB1. 0.2 58 7/18 CKT, LAYOUT 14 -Follow HP request -Delete RH186, and add QH12 to invertion PCH_GPIO56 signal for CR_SX_WARN# 0.2 59 7/18 CKT, LAYOUT 17 -Follow HP request -Change RH165.2 net name to TB_HOT_PLUG# for TBT function. 0.2 60 7/18 CKT, LAYOUT 30,32 -Follow HP request -Change JP6.13 connection to 8051TX_STBYLED# (instead of 8051TX_STBLED#) -Change Q35.2 connection to 8051TX_STBYLED# (instead of 8051TX_STBLED#) -Add a 100K pullup resistor between signal PVT_CS# and +3VDS power rail. -Make these resistors as non-install (from Install): R219,R266,R258,R253,R216,R264 -Make R215 install -Change R436 to 1K (from 10 ohm) -Make these resistors as install (from un-install): R242,R254,R500,R277,R269,R262,R218 -Make U18 as install. A Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date A 2011/11/5 Deciphered Date 2010/12/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title HW_PIR1 Size C Date: 5 4 3 2 Document Number Rev 0.5 LA-9241P Thursday, December 20, 2012 1 Sheet 53 of 56 5 4 VBL20 from DB0 to DB1 LA-9241P REV:0.1 -> 0.2 Modify <2012.07.04.~2012.08.07. > Rev. Item Date Impact Page Change Cause D C B 2 1 Modify Description 0.2 61 7/18 CKT, LAYOUT 31 -Follow HP request -Modify PM_APWROK circuit 0.2 62 7/18 CKT, LAYOUT 39 -Follow HP request -Modify JTB1 connector pin define. Add HDD_HALTLED and PWR_GD 0.2 63 7/19 CKT, LAYOUT 16,30 -Follow HP request -Reserve RH242 and RH243. Add off page symbol of PCH_SPI_WP# and PCH_SPI_HOLD# 0.2 64 7/19 CKT 20 -Follow Intel reference schematic V1.2 -Non-install CH101 0.2 65 7/19 CKT,LAYOUT 25 -Follow HP request -Delete C79 and C85. Change R457.1 power rail to +3VDS 0.2 66 7/19 CKT,LAYOUT 30 -Follow HP request -Delete R254 0.2 67 7/19 CKT,LAYOUT 32 -Follow HP request -Change R483.1 and R482.1 connection to +3VS. Change R330.1, R329.1, and R328.1 connection to GND 0.2 68 7/19 CKT,LAYOUT 36 -Follow HP request -Delete CC70, CC71, CC75, CC76, CC77, CC78, CC79, CC80, CC81, CC82 0.2 69 7/19 CKT,LAYOUT 39 -Follow HP request -Modify pin define JVGA1 and JCR1 pin define for better return path 0.2 70 7/19 CKT,LAYOUT 40 -Follow HP request - Connect signal ADP_ID_CHK to pin 78 of KBC via a 0 ohm resistor (install this resistor). - Connect NFC_RX to pin 86 of KBC directly, and then move R541 (install) between ADP_ID_CHK and pin 86 of KBC. - Connect NFC_TX to pin 87 of KBC directly, and then move R542 (install) between pin 87 of KBC and signal PLT_SEL. 0.2 71 7/20 CKT,LAYOUT 14 -Follow HP request -Add ME debug connector JME1 0.2 72 7/20 CKT,LAYOUT 16 -Follow latest ME drawing. -Correct screw hole size. 0.2 73 7/20 CKT,LAYOUT 19,20 -Follow HP request. -Delete CH60, CH62, CH63, CH102 0.2 74 7/20 CKT,LAYOUT 19,21,38 -Follow HP request. -Add RA28 and Q75 for REC_MUTE_CTRL_KB signal. Modify JKB1 pin define. 0.2 75 7/20 CKT 27,38 -Follow ESD request. -Change DA2, DA3, D32 P/N 0.2 76 7/20 CKT,LAYOUT 29,34 -Follow HP request. -Change C110 to 22uF, Delete C231. Change Q170A lcation to Q7A 0.2 77 7/20 CKT,LAYOUT 30 -Layout smooth -Modify RP1 pin define. 0.2 78 7/20 CKT,LAYOUT 30 -Follow HP request. -Add D44 and D45 0.2 79 7/20 CKT,LAYOUT 31 -Follow HP request. -Modify PWR_GD circuit. 0.2 80 7/20 CKT 37 -Vendor's suggestion -Change C258 and C255 to 1uF. Non install RH225. 0.2 81 7/20 CKT 38 -Modify for 2 DIMM and 4 DIMM SKU. -Reserve SIO_GPIO44 PD R554, and modify R328, R329, R330 value to 4.7K. Modify R482, R483 value to 10K 0.2 82 7/23 CKT,LAYOUT 14 -Schematic wrong. -Connection RH55.2 to power rail +RTCVCC 0.2 83 7/23 CKT,LAYOUT 14 -Follow HP request. -Move QH12 to sub board. Add CR_SX_WARN# PU 10K ohms RH244 0.2 84 7/23 CKT,LAYOUT 15,17,18 -No connection to other page. -Delete FN14, FN15, USB_OC0#_R, USB_OC1#_R, USB_OC2#, USB_OC3#, USB_OC4#_R, PCH_GPIO24, FN_CLK2, PCH_GPIO37 off page symbol. 0.2 85 7/23 CKT,LAYOUT 16 -Follow latest ME drawing. -Modify screw hole size. 0.2 86 7/23 CKT,LAYOUT 17 -Correct net name -Change RH171.1 connection to ODD_EN C 0.2 87 7/23 CKT,LAYOUT 88 7/23 CKT,LAYOUT 22,30 -Follow RF request. -Reserve C393, C394, CH112 0.2 89 7/23 CKT,LAYOUT 26 -MIC_SENSE circuit had been removed. -Delete RA7. 0.2 90 7/23 CKT,LAYOUT 27 -Reduce layout spacing -Combine QA2B with QA1A. 0.2 91 7/23 CKT,LAYOUT 31 -Follow HP request. -Change R286 to 10K 0.2 92 7/23 CKT,LAYOUT 36 -Follow HP request. 0.2 93 7/23 CKT,LAYOUT 36 -Modify netname to more clear. -Change SEL to SEL_eDP_MUX. Change SEL_DP to SEL_DP_MUX 0.2 94 7/23 CKT,LAYOUT 17 -Layout smooth -Modify RPH1 and RPH2 pin define 0.2 95 7/24 CKT,LAYOUT 25 -Follow latest NGFF pin define. -Modify JMINI3 pin define. 0.2 96 7/24 CKT,LAYOUT 28 -Follow latest FP spec. -Modify JFP1 pin define. 0.2 97 7/24 CKT,LAYOUT 30,38 -Follow EMI request -Add C420, C421, C422, C422, C423, C424, C425, C426, C427, C428, C429, C430, C431, C432, C433, C434, C435, C436, C437, C438, C439, C440, C441, C442, C443, C444, C445, C446, C447, C448, R555 and C419. Change R437.2 netname to PCH_SPI_CLK_EC. 0.2 98 7/24 CKT,LAYOUT 39 -Follow HP request -Modify JUB1 pin define. 0.2 99 7/25 CKT,LAYOUT 5,9,20 -Follow HP request -Delete RC24, RC96. Change UH1 pin AJ12 and AJ14 connection to +1.05VS 0.2 100 7/25 CKT,LAYOUT 30 -Follow HP request -Change U18 to socket and add &UH2 for KBC ROM 0.2 101 7/25 CKT,LAYOUT 30 -Follow HP request -Connect JP6.13, U17.115, and R255.1 to TX_STBY_LED. Add R559, R560, and Q77 0.2 102 7/25 CKT,LAYOUT 36 -Reduce layout spacing -Combine Q56 and Q57 to dual channel Q79 0.2 103 7/25 CKT,LAYOUT 25 -Follow latest NGFF spec -Modify JMINI3 and JSIM1 pin define. 0.2 104 7/26 CKT,LAYOUT 16,30 -Follow HP request -Install RH242, RH244. Add R561, R562. Noninstall R541, R542 0.2 105 7/26 CKT,LAYOUT 28 -Follow RFQ spec -Change U11 to SLB9656 0.2 106 7/27 CKT,LAYOUT 36 -Follow HP request -Add R563, R564 0.2 107 7/30 CKT,LAYOUT 5 -Follow Intel reference schematic -Non install QC1 0.2 108 7/30 CKT,LAYOUT 16 -Follow RF request -PCH_SPI_CLK reserve CH113 to GND 109 7/30 CKT,LAYOUT 18,29,30,34 -Follow VBK10 D 0.2 0.2 A 3 22,39 -Non install RH184 and RH185. Add C389, C390, C391, C392. Change C121 to 1000pF. Change C322 to 100pF. Delete Q37, R366, R361. -Combine Q63 and Q72 to Dual channel Q76. Delete R516, R545, CC84, C371. -Follow HP request B -Change R10.1 to +5VDS and Q20.3 to +3VDS for layout easy. Modify JVGA1 and JCR1 pin define. 0.2 110 7/30 CKT,LAYOUT 23 -Follow latest connector list -Modify JHDD1, JODD1 and JCR1 footprint. 0.2 111 7/30 CKT,LAYOUT 39 -Correct JNFC1 pin define -Modify JNFC1 pin define. 0.2 112 7/31 CKT,LAYOUT 25,39 -Follow HP request -Modify Q4A circuit. Change JTB1.95 connection to +3VDS. 0.2 113 7/31 CKT 25 -Wireless LED fail issue. -Install Q29 and Q31 0.2 114 7/31 CKT,LAYOUT 26 -No LOGO KBL function -Delete Q21,Q22,R454,R14. Delete JEDP1.35 signal 0.2 115 7/31 CKT,LAYOUT 14 -Correct netname -Change RH62.2 netname to PWRSV_SEL# 0.2 116 8/01 CKT,LAYOUT 23,33,39 -HP request -Swap SATA bus port 2 and port 5. JCR1.35 connection to PCH_PCIE_WAKE# 0.2 117 8/01 CKT,LAYOUT 18,23,25 -HP request -Uninstall Q68, R459. Change PCH.AT3 and RH198.2 netname to Sec_HDD_DET. Change PCH.AP1 and RH180.2 to mSATA_DET#. Delete Q48. Add R565. 0.2 118 8/01 CKT,LAYOUT 24 -PWR request -Change R492.2 connection to KBC_PWR_ON 0.2 119 8/01 CKT -Follow RFQ spec -Change KBC symbol to SMC1322 0.2 120 8/03 CKT,LAYOUT -HP request -Add CC84, CC85, CC86. Change RD6 to 33ohms. RH33.1 connection to GND. Delete RH201, RH202. Q4.2 connection to BT_ON 0.2 121 8/03 CKT,LAYOUT 22 -Layout smooth -Swap L3 pin define for layout smooth 0.2 122 8/03 LAYOUT 23 -Follow ME connector list -Modify JODD1, JMINI3 footprint 0.2 123 8/03 CKT,LAYOUT 25,30,39 -HP request -Q4.2 connection to BT_ON. Change R437 to 33 ohms. Change R540 to 4.7K. Change JVGA1 pin 39 and 40 connection to +3VDS 0.2 124 8/03 CKT,LAYOUT 30 -RF request -Add CH114 0.2 125 8/06 CKT,LAYOUT 9,15 -HP request -Reserve CC87. Change JCPU1 pin AM43 and pin AL44 ball name 30 6,11,13,18 A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/11/5 Deciphered Date 2010/12/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title HW_PIR2 Size C Date: 5 4 3 2 Document Number Rev 0.5 LA-9241P Thursday, December 20, 2012 1 Sheet 54 of 56 5 4 VBL20 from DB0 to DB1 LA-9241P REV:0.1 -> 0.2 Modify <2012.07.04.~2012.08.14. > Rev. Item Date Impact Page Change Cause D 7,16,25,29 3 2 1 Modify Description 0.2 126 8/07 CKT, LAYOUT -Follow HP request -Change RC78 to 10Kohms. Install RH148 and change to 2.2Kohms. Add R567, R568 and R569. 0.2 127 8/07 CKT, LAYOUT 30 -Correct netname -Change TX_STBY_LED net name to TX_STBY_LED# 0.2 128 8/07 CKT, LAYOUT 11,12,13, 30,38,39 -Follow latest ME connector list -Modify JDIMM1, JDIMM2, JBATT1, JKB1, JCR1, JNFC1, JP6 connector footprint 0.2 129 8/08 CKT, LAYOUT 22,35 -RF request -Reserve C449, C450, C451 0.2 130 8/08 CKT, LAYOUT 39 -Follow latest ME connector list -Modify JCR1 and JNFC1 pin define. 0.2 131 8/09 CKT 39 -Follow latest ME connector list -Modify JMXM1 footprint 0.2 132 8/10 CKT, LAYOUT 5,14,30 -Follow HP request -Add RC106 and change UC1.1 connection to VR_ON. Change UH7.5 and UH3.5 connection to +3V_PCH power rail. Change RH235 to 0ohms. Add RH245 and connection to VCC1_PWRGD. Change R277.1 and R253.2 connection to VR_ON 0.2 133 8/10 CKT 39 -Add +3VDS power rail for USB repeater -Change JCR1.21 connection to +3VDS 0.2 134 8/10 CKT 38 -Follow TP module pin define -Modify JTP1 pin define. 0.2 135 8/10 CKT, LAYOUT 34 -RF request -Reserve C452, C453, C454, C455, C456, C457, C458 0.2 136 8/14 CKT -Material EOL 0.2 137 8/14 CKT 24,25,30,32 -Material EOL D -Change Q59, Q70, Q55, Q58, Q68, Q75, Q39, Q61, Q51, Q52, Q53 to SB000009Q80 (S TR 2N7002KW 1N SOT323-3 ) -Change D4, D8, D10, D21, D27 to SCS00000Z00 (S SCH DIO RB751V-40 SOD-323) VBL20 from DB1 to DB2 LA-9241P REV:0.2 -> 0.3 Modify <2012.09.03.~ 2012.09.28 > Rev. Item Date Page Change Cause Modify Description 0.3 1 9/03 CKT 26 -Chang UA1 to HP P/N -Change UA1 P/N to 92HD91B2X5NLGXWCX8 0.3 2 9/03 CKT Impact 30,31 -Follow HP request -Install R451, R452. Noninstall R561, R562, R284. Change R282 to 10K ohms. Change R289 to 11.5k ohms 0.3 3 9/07 CKT 30,36 -No used -Delete TX_STBY_LED#, VGA_RED, VGA_GRN, VGA_BLU, VGA_DDCCLK, VGA_DDCDATA, CRT_HSYNC, and CRT_VSYNC off page symbol 0.3 4 9/07 CKT, LAYOUT 36,39,40 -Follow latest ME drawing -Add VGA circuit and connector. Remove JVGA1 BTB connector. Add JFUN1 connector. Add USB3.0 repeater and connector 0.3 5 9/10 CKT, LAYOUT 25 -Follow HP request -Add WWAN_FULL_PWR and WWAN_RSVD2 PU R599 and R600 to +3V_WWAN. Delete T126 and T128 0.3 6 9/10 CKT, LAYOUT 30 -Follow HP request -Delete R219, R258, R500, R262, R264, R266, R216, R241, R242, R253, R549, R271. Change U17 pin69 to KBC_XTA2, pin 71 to KBC_XTAL1. Add C487, C488, Y4 Connect EC_MUTE# to KBC.91. MAIN_BAT_DET# to KBC.92. pin 70 of KBC to GND. ADP_ID_CHK signal to KBC.78. A\DP_EN signal to KBC.63 0.3 7 9/11 CKT, LAYOUT 5,9,10,14, 15,17,20, 31,32, 33 -Follow HP request -Delete RC102 and RC103. Connect CPU.AL35 pin to VCCSENSE. Connect CPU.AK35 pin to VSSSENSE. Delete RH165 and connect PCH.M1 to TB_HOT_PLUG# directly. Connect RPH1.3 to TB_HOT_PLUG# directly. Delete RH226 and connect pin AD12 of PCH to +3V_PCH power rail. Delete RC106 and connect UC1.1 to VR_ON. Noninstall RC36,RC38,RC40,RC43,RC45,RC47. Delete RC66. Connect CPU.AT26 pin to CPU_PLTRST#. Delete RC30. Connect CPU.AL34 pin to H_CPUPWRGD. Change RC55.1 connection to H_CPUPWRGD. Delete RC27. Connect CPU.AM35 pin to PCH_THERMTRIP#_R. Delete RC93 and connect SLP_S3# to QC5.5. Delete R351. Connect EN_P1V5 to JDOCK1.140. Change C299 to 0.01uF. Delete R336 and connect C299.1 to ON/OFFBTN_KBC# . Connect ON/OFFBTN_KBC# to JDOCK1.49. Delete R287. Connect joint point of R286.1 and U18.1 to VR_ON. Add R601 4.7K PU to +3VS on signal SIO_GPIO42. Noninstall R601. Delete RH92, RH93, RH221, RH94, RH95, RH107, RH103, RH203, RH114, RH116, RH205, RH122, RH124, RH126, RH127, RH128, RH130 30 -Follow HP request -Delete R543, R561, R562. Delete signal ADP_ID_CHK connection to KBC.86 pin. Delete R249 and connect signal OCP_PWM_OUT to KBC.59 pin. Delete R251 and connect signal PM_PWROK to KBC.60 pin. Delete R256 and connect signal EN_P1V5 to KBC.38 pin. Delete R277 and connect signal VR_ON to KBC.72. Change RP1 and RP2 to 100K. C B A 0.3 8 9/12 CKT, LAYOUT 0.3 9 9/12 CKT, LAYOUT 38, -ME move LID SW from Power board to Function baord. -Modify JPWR1 and JFUNC1 connector pin defein. 0.3 10 9/12 CKT, LAYOUT 37 -ME rotate Smart connector 90 degree. -Modify J3 pin define. 0.3 11 9/13 CKT, LAYOUT 16 -Follow latest ME drawing 0.3 12 9/14 CKT, LAYOUT 14,31 -Follow HP request 0.3 13 9/14 CKT, LAYOUT 0.3 14 9/17 CKT, LAYOUT 40 -Layout request 0.3 15 9/17 CKT, LAYOUT 38 -Follow ME connector list -Change JPWR1 footprint and pin define. 0.3 16 9/17 CKT, LAYOUT 38 -Follow Keyboard spec -Modify JKB1 pin define. 0.3 17 9/18 CKT, LAYOUT 28 -Follow ME drawing -Modify JFP1 pin define. 0.3 18 9/19 CKT, LAYOUT 13,39 -Follow HP request -Add a 0ohm resistor between JCR1.5 and signal PCH_PCIE_WAKE#. Then make this resistor open. Change QH11 to P MOS. Change RH30 to 2.2K ohms 0.3 19 9/19 CKT, LAYOUT 34 -Layout smooth -Delete J2 C -Delete H4, H32, H34, H41, JP2. Add H42, H43, H44, H45, H46. Modify JEDP1, JSIM1, JFP1, JVGA2, J3, JKB1, JTP1. JFUN1 pin define and footprint. -Delete UH7, RH235. Move RH236, CH106 to page 31. Modify POWER OK circuit 22,30,38,39,40 -Follow ME and DFX request -Modify JEDP1, UH5, JTB1, JUSB1 and JKB1 pin define and footprint. -Swap L35, L36, L37 for layout smoothly. 0.3 20 9/20 CKT, LAYOUT 14,26,30,37 -Follow HP request -Change RH74 to 100K. Change RH147.1 power rail to +3VS. Delete RA13, CA20. Change R227 to 3K. Delete R393, CC67, and connector U30.23 to PLT_RST#. 0.3 21 9/20 CKT, LAYOUT 22 -Correct circuit short issue -Modify JEDP1 connector circuit. Add one more +3VS power pin for power consumption 0.3 22 9/20 CKT, LAYOUT 22,26 -Change to common part. -Change D3 and DH1 to RB751V-40_SOD323-2 0.3 23 9/21 CKT, LAYOUT 8,13,30,39 -Follow HP request -Reserve CFG9 PD resistance RC106. Non-install RH39, RH40, RH41, RH44, RH48, RH47, RH46. Change R436 to 100K and connection R436.2 to GND. Delete R557, Non-install R358, C374 0.3 24 9/21 CKT, LAYOUT 36 -Netname issue. -Change L29.2 netname to DAC_RED. L30.2 netname to DAC_GRN. L31.2 netname to DAC_BLU 0.3 25 9/23 CKT, LAYOUT 5,30,31,47 -Follow HP request -Change netname VR_ON to PWR_GD, change netname PWR_GOOD_3 to VGATE 0.3 26 9/24 CKT, LAYOUT 20,30 -Follow HP request -Non install D21. Delete RH213, RH216, and change netname 0.3 27 9/24 CKT, LAYOUT 40 -No need another DC/DC circuit to provide +3VDS_P to U44. -Delete Q79, Q80, C475, C477, C478, R588, R587. Change +3VDS_P power rail to +3VS. 0.3 28 9/25 CKT, LAYOUT 22 -Change +3VS, +5VS and +LCDVDD power rail soultion 0.3 29 9/25 CKT, LAYOUT 30 -Follow HP request -Delete R9, R10, R11, Q12, Q20, C1, C7, C8, U24, C226, C221, C222, U25, C218, C223, C219, C227, R354, R356, R357, Q9. Add U47, C497, C498, C499, U45, R603, C489, C490, C491, C492, U46, R604, C493, C494, C495, C496, Uninstall R370, R373, Q43, Q44, R490 -Install R237, R235, R234, R233, R231 0.3 30 9/25 CKT, LAYOUT 31 -Reserve for EC CLK issue -Reserve R605 and connect R605.1 to SUSCLK_KBC 0.3 31 9/26 CKT, LAYOUT 5,22,34,40 -Follow HP request 0.3 32 9/26 CKT, LAYOUT 34 -Correct Netname -Change JXDP1.47 connection to PM_PWROK via a 0ohm resistor. Add a C502 (10uF cap) for +3VS decoupling. Change C489 and C492 value to 10uF or 4.7uF. Change C494 and C496 to 10uF or 4.7uF. Change C499 value to 4.7uF and make R480 as install. Change C493 and C490 to 0.01uF -Change R375.1 connection netname to SLP_S3# 0.3 33 9/26 CKT, LAYOUT 38,39 -Follow ME request -Modify JP9 and JFUN1 pin define. 0.3 34 9/26 CKT, LAYOUT 34 -Follow HP request. -Modify +1.05VS power circuit. 0.3 35 9/27 CKT, LAYOUT 33,35,38 -Follow HP request. -Delete R339, R340, R341, R342. Add R606, R607, R608 PU to +3VS. Change R408 to 200K ohms. Uninstall C295. 0.3 36 9/27 CKT, LAYOUT 29 -Material shortage issue -Change Y2 to smaller (32x25 mm) package. 0.3 37 9/28 CKT, LAYOUT 34 -Follow HP request. -Add C503 0.3 38 10/09 ckT 16 -Follow HP request. -Change RH152, RH153 to 499ohms. A Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date B 2011/11/5 Deciphered Date 2010/12/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title HW_PIR3 Size C Date: 5 4 3 2 Document Number Rev 0.5 LA-9241P Thursday, December 20, 2012 1 Sheet 55 of 56 5 4 VBL20 from DB1R to SI1 LA-9241P REV:0.3 -> 0.4 Modify <2012.10.11.~ 2012.11.09> Rev. Item Date Impact Page Change Cause 3 2 1 Modify Description 0.4 1 10/11 CKT, LAYOUT 26,27 -Follow IDT request 0.4 2 10/11 CKT, 33 -Follow ESD request. -Change RA14 to 0 ohm. Change C91, C94 to 150u. Change R97, R98, R102, R104 to 1%. Non-install R106, R107. Change C95 to 0.47u X5R. Change QA1.4, R110.2, Q6.1, R111.2, Q6.4 to AGND. -Non-install D42. Install D32. -Re-arrange MXM DP port. Port A for Thunder Bolt. Port B for Dock. Port C for EDP. Port D for SWITCH 0.4 3 10/11 CKT, LAYOUT 35 -Follow HP request 0.4 4 10/12 CKT, LAYOUT 5,14,30,34 -Follow HP request -Reserve RC108, UH6, CH116, R610. Change U17.85 and R276.1 connection netname to RSMRST#_EC. Change R455 to 47K. Add Q18A, C504, R609. Modify +3V_PCH power circuit 0.4 5 10/16 CKT, LAYOUT 9,14,25,29, 30,34,39 -Follow HP request -Install R567, D21. Add R612, R616, Q80, R614, Q79. Delete R602, C504, R609, R456, Q67B, R218, R239, R240, R540, Q74, R247, C322, C186, R230, R64. Change R568.1, R569.1 and R245.1 connection to KBC_WAKE#. Remove current VCC1_PWRGD connection to JP6.16. Then add a 4.7 K resistor between JP6.16 and new signal VCC1_PWRGD_SUS#. Change R215.2 to GND. Change R227 to 3.3K. Add a R615 PD for U7.102. Change U7.102 connection to PLT_DET. Change R248 to 200k ohms. Change R248.1, U17.77 connection to VCC1_PWRGD_SUS#. Change R243.1 and U7.125 connection to CHRG_RST. Change R243 to 100K. Change R243.2 connection to GND. change R436.2 connection to +3VDS. Change JTB1.91, U17.41 and R436.1 connection to iSCT_LED#. Change D21.2 connection to PM_APWROK. Modify +3V_PCH power circuit. Change JCR1.5 connection to +5VDS. -Change R614.1 connection to +3V_PCH. Correct R227 to 10K. D 0.4 6 10/17 CKT, LAYOUT 14,30 -Follow HP request 0.4 7 10/18 CKT, LAYOUT 5,9,14,16 20,24,25 30,34,35 -Follow HP request -Change R615 to 470K, R610 to 470 ohm, R614 to 10K ohms, R612, R137, R606, R607 and R608 to 4.7K ohms, RC108 to 10K ohms . Delete Q67A, QC1, RC12, Q80, R461, Q2, RC90. Install RH209, R492, RC108, R613, CH116 and UH6. Uninstall QC3, RH148, RH67, RH208. Change R492.2 connection to PCH_THERMTRIP#_R Connection R614.1 to PM_RSMRST#. Modify +1.35VS power circuit 14,20,30 34,39 18,25,28 -Follow HP request 0.4 8 10/23 CKT, LAYOUT 0.4 9 10/24 CKT, LAYOUT 14,18,25 29,34,35 30 -Follow HP request -Delete R612. Reserve R616 between KBC. 124 pin and signal SIO_SLP_SUS#. Uninstall RH209, Q79, R614, R613, CH116 and UH6. Install RH67, RH208. Change PCH.AL6, JTB1.91 and RH244.2 connection to TBT_RR_GPIO#. Add Q80 for iSCT_LED# circuit -Add R618, R619, R620, R621. Delete R567, and connect JMINI3.15 to WLAN_WAKE# directly. Change ACCEL_INT# connection to U9.11. Change RH176.2 connection to GND and make RH176 install. Change RH185 as install -Add R247, Q63. Change RH70 to 200k ohms. Add LANWAKE# PU RH248 to +3VDS. Delete R618, R89. Change R455 to 200k. Add PD R622. Change Q61 and Q62 to dual channel 7002 0.4 10 10/25 CKT, LAYOUT 0.4 11 10/25 CKT, LAYOUT 0.4 12 10/26 -Solve KBC external crystal can not work issue. -Reserve R624 and connection to SUSCLK_KBC CKT, LAYOUT 13,14,15 29,32,36 -Follow Compal HW request -Delete RH56, RH57, RH59, RH60, RH66, RH69, RH71, RH98, RH99, RH100, RH141, RH234, RH139, RH108, RH110, RH111, RH112, R160, R161, R162, R163, R320, R477, R478, R464, R465, R466, R467, R472, R473, R474, R475, R468, R469, R470, R471, R479, R484, R485, R486, R318, R319, R321, R322, R570, R571, R572. Add RP7, RP8, RP9, RP10, RP11, RP12, RP13, RP14, RP15, RP16, RP17, RP18, RP19. 0.4 13 0.4 14 10/26 CKT, LAYOUT -Rearrange RP11, RP8, RP17, RP13, RP14, RP15, RP16, RP12, RP10, RP7 pin assignment for layout smoothly. CKT, LAYOUT 13,14,15 29,32,36 38 -For layout smoothly. 10/26 -Move LID switch to PWR board by ME reqesut. 0.4 -Change JPWR1 to 6 pin, and modify the JPWR1 pin define. 15 10/26 CKT, LAYOUT 13,14,17 18,23,29 30,32,34 38, -Follow HP request. -Delete R153, R481, R565. Swap QH11A.2 and QH11B.5 connection. Change RH75.2 and PCH.K7 connect to BATLOW#. Change PCH.U7 connect to BT_OFF. Change PCH.P3 and RPH2.4 connect to WWAN_DET#_PCH. Delete A20GATE and VCC1_PWRGD_SUS# off page symbol. Change RH180.2 and UH1.AP1 connect to PCH_GPIO_35. Change RH198.1 and UH1.AT3 connect to PCH_GPIO_36. Change R376 to 10k. Change R376.1 connect to +3VDS. Connect Q34.3 to LED_LINK_LAN_DOCK# with R625, and delete LED_LINK_LAN_DOCK# connection to Q34.1. Delete R157 and connect Q34.1 and signal LED_LINK_LAN#_R. Connect U22.26 pin to signal mSATA_DET#. Change R455.2 connection to B+. Change Q36 to AO3413. 0.4 16 10/29 CKT, LAYOUT 18,35 -Follow HP request. -Change RH179 to 100ohms. Delete R137, Q82.B. Add D52 0.4 17 10/31 CKT, LAYOUT 18,36 -Follow ME request. -Change JODD1, JVGA2, JKB1 footprint 0.4 18 10/31 CKT, LAYOUT 18,37 -Follow HP request. -Change R291.1 connection to +5VL. Change R291 to 105K_1% 0.4 19 11/01 CKT, LAYOUT 31 -Follow HP request. -Change R304.1 connection to +5VL. Change R304 to 88.7k +-1%. Uninstall R306. 0.4 20 11/01 CKT, LAYOUT 13,15,37 -Material shortage issue -Change Y3, YH1, YH2 to small package 0.4 21 11/01 CKT, LAYOUT 22,30,37,38 -Follow HW request -Uninstall Y4, C487, C488. Delete C23, C80, C82, C111. Change U30 to AU9560-GBS-GR. Add R626 0.4 22 11/02 CKT, LAYOUT 29 -Follow HP request. -Reserve C504. Add C505 -Follow HP request C B D C 0.4 23 11/05 CKT, LAYOUT 27 -Audio Jack change to normal open type -Delete R174, QA1B. HP_SENSE# connection to R167.1 0.4 24 11/05 CKT, LAYOUT 38 -Follow ME request -Modify JKB1 pin define to follow ME request. 0.4 25 11/05 CKT, LAYOUT 39 -Smart Card Reader AU9560-GBS-GR no need external crystal -Uninstall Y3, CV33, CV34 0.4 26 11/06 CKT, LAYOUT 9,14,22, 25 -Follow HP request 0.4 27 11/06 CKT, LAYOUT 12 -Follow RF request -Change QC5A.2 and QC5B.5 connection to SLP_S3. Change PCH.D2 pin connection to DDR3_SET. Delete Q68, R459. Change R458 to 0ohm. Change JMINI3.13 connection to signal WWAN_DET#_PCH. Change JMINI3.65 connection to GND. Change C498 to 4700pF -Add C506, C507, C508, C509, C510, C511 0.4 28 11/07 CKT, LAYOUT 5 -Follow ESD request -Delete RC36, RC38, RC40, RC43, RC45, RC47 by ESD request. Add T144, T145, T146, T147, T148, T149 0.4 29 11/07 CKT, LAYOUT 23,32 -Follow RF request -Change C48 and C58 to 68pF. Change R332 to 33 ohms, C205 to 82pF and install R332 and C205 0.4 30 11/08 CKT, LAYOUT 23,33 -Follow HP request -Delete D52. Add Q83, R627 0.4 31 11/09 CKT 16,34,35 -Follow HP request -Change RH152 and RH153 value to 2.2K. Change C491 and C495 to 4700pF. Change R627 to 4.7K. VBL20 from SI1 to SI2 LA-9241P REV:0.4 -> 0.5 Modify <2012.12.12.~ > Rev. Item Date Impact Page B Change Cause Modify Description -Follow HP request 0.5 1 12/12 CKT, LAYOUT 0.5 2 12/12 CKT, LAYOUT 9,14,28,30 31 35 -Material shortage issue. -Uninstall QC4, RC92, CC39, RC89, QC5 and RC88. Add J4, Q84, Q85. Delete Q79, R615, UH6, R613, R617, R227 , CH116, R605. Change RH222, RH223, RH224, R615, R248 to 100K. Remove R611. Connect JP6.16 to VCC1_PWRGD_SUS#. Install R624. Change CH115 to 0.22uF -Change U34, U35, U36 to small package 0.5 3 12/13 CKT 9,28 -Follow HP request -Install RC88. Change JFP1.11 netname to FPR_OFF_C 0.5 4 12/20 CKT 35,36 -Solve CRT switch issue -Uninstall R91,R92,R93. Change RP19 to150 ohms A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/11/5 Deciphered Date 2010/12/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title HW_PIR3 Size C Date: 5 4 3 2 Document Number Rev 0.5 LA-9241P Thursday, December 20, 2012 1 Sheet 56 of 56 www.s-manuals.com
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