Compal LA 9262P Schematics. Www.s Manuals.com. R1.0 Schematics

User Manual: Motherboard Compal LA-9262P VAZA0 - Schematics. Free.

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A

B

C

D

E

MODEL NAME : VAZA0
PCB NO : LA-9262P ( DAB0000I010 )
BOM P/N :
1

1

Dell/Compal Confidential
2

2

ZZZ
MB_PCB

Schematic Document
Murcielgo MLK (Haswell ULT)

3

3

2013-04-19
Rev: 1.0
Highlight the short pad for 0 ohm

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P01-Cover Page
Size

A

B

C

D

Document Number

Rev
1.0

LA-9262P
Date:

Friday, April 19, 2013

Sheet
E

1

of

45

A

1

eDP Panel
Conn x 2.

B

C

D

eDP 1.3

P.17

E

Channel A
DDR3L-RS 4Gb or 8Gb (x16) * 4

Memory Bus (DDR3L-RS)

P.12, 14

Dual Channel
1.35V DDR3L-RS 1600 MHz

miniDP
Conn.

Channel B
DDR3L-RS 4Gb or 8Gb (x16) * 4

DP 1.2

P.19

1

P.13, 14

Intel
Haswell ULT

USB3.0/USB2.0

USB 3.0 Conn.

15W TDP
SPI

USB3.0/USB2.0

P.23

( USB Charger Port )

Digital Camera

SPI ROM
8M

P.17

USB2.0

SDIO

I2C

UART
USB2.0

P.20

Pressure Sensor
APS331APTR

I2C

Sensor HUB P.20
STM32F103RC

USB2.0

NFC Module
Conn
P.22

SMLink

P.21

3

I2C

P.27

P.20

HDA
Page 5, 6, 7, 8, 9, 10, 11

Audio DSP
ALC5505 P.18

HDA

LPC Bus

TPM
P.20
AT97SC3204

Digital MIC

SMBus

FAN conn.

PCM

I2C

Daughter Board

Touch Pad

ALS+CLS
TCS3472
P.20
Intel used Capella

PCIE *2

IOL BTB Conn

Gyro Sensor
TX3GD20TR

2

NFGG Slot A-SD
WLAN
BT
WiGig

P.17

e-Compass +
Accelerometer
DE303DLHCTR P.20

P.07

USB2.0

Touch Screnn

3

P.22

P.23

USB 3.0 Conn.

2

Mini Card (Full)
# mSATA

SATA3.0

BGA 1168 Balls

P.17

Headphone Jack

( iPhone & Nokia compatible)

Audio AMP
APA2605

Int. Speaker

P.18

ENE KB9012BF
Intel used Renesas

Audio Codec
ALC3661

P.28

P.27

Int.KBD
4

RTC conn.

P.26

P.26

4

DC/DC Interface CKT.
P.25

Issued Date

P.29 ~ 39

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Power Circuit DC/DC

2011/02/23

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P02-Block Diagram
Size

A

B

C

D

Document Number

Rev
1.0

LA-9262P
Date:

Friday, April 19, 2013

Sheet
E

2

of

45

A

B

C

D

E

Compal Confidential
Project Code : VAZA0
File Name : LA-9262P

1

1

LS-9261P
Volume Up/Down, PWR, Rotation Button

LS-8822P
Win8 Button
Hall Sensor

FPC
36 pin

Audio Jack
2

2

Camera

LA-9262P M/B
Keyboard

eDP Cable x 2
Coaxial and Wire

LCD Panel
Touch Panel Control Baord

FPC (main frame)

30 pin

Keyboard Backlight

FFC
4 pin

FFC

3

6 pin

Touch Pad

FPC

CABLE
9 pin

3

16 pin to 15 pin

Battery Pack

NFC Module

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size

Date:
A

B

C

D

P03-DaughterB block diagram
Document Number
LA-9262P
Friday, April 19, 2013

Sheet
E

3

of

Rev
1.0
45

A

Board ID Table for AD channel
Vcc
Ra
Board ID
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

3.3V +/- 5%
100K +/- 1%
Rb
0
12K +/- 1%
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
56K +/- 1%
75K +/- 1%
100K +/- 1%
130K +/- 1%
160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%
330K +/- 1%
430K +/- 1%
560K +/- 1%
750K +/- 1%
NC

USB PORT#

BOARD ID Table
V AD_BID min

V AD_BID typ

V AD_BID max

Board ID
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

EC AD3

PCB Revision
CS 0.1
CS 0.2
CS 0.3
CS 0.4
CS 0.5
CS 1.0

PCH
USB
Port
Mapping

Non-CS 0.1
Non-CS 0.2
Non-CS 0.3
Non-CS 0.4
Non-CS 1.0

DESTINATION

0

External USB3

1

External USB3

2

NGFF CARD WLAN

3

Touch Panel

4

Camera

5

Sensors HUB

6
7

SMBUS Control Table
SOURCE

1

EC_SMB_CK1
EC_SMB_DA1

KB9012

EC_SMB_CK2
EC_SMB_DA2

KB9012

PCH_SML0CLK
PCH_SML0DATA

PCH

PCH_SML1CLK
PCH_SML1DATA

PCH

MEM_SMBCLK
MEM_SMBDATA

PCH

NGFF

BATT

V

Charger

NFC

DDR3 SPD

ALS

Touch Pad

V
V

V

V

DESTINATION

PCH
DDI
Port
Mapping

Link

V

DIFFERENTIAL

V

FLEX CLOCKS

V

DESTINATION

DDI PORT#

DESTINATION

B

mini-DP
1

C

SATA

DESTINATION

PCI EXPRESS

m-SATA

Lane 1

DESTINATION

CLKOUT_PCIE0

CLKOUT_LPC_0

EC LPC

SATA0

CLKOUT_PCIE1

CLKOUT_LPC_1

TPM

SATA1

Lane 2

SATA2

Lane 3

NGFF CARD WLAN

SATA3

Lane 4

NGFF CARD WLAN

CLKOUT_PCIE2

CLK

XDP

CLKOUT_PCIE3

NGFF CARD WLAN

CLKOUT_PCIE4

Lane 5

CLKOUT_PCIE5

Lane 6

Symbol Note :
: means Digital Ground

: means Analog Ground

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P04-Notes List
Size

A

Document Number

Rev
1.0

LA-9262P
Date:

Friday, April 19, 2013

Sheet

4

of

45

5

4

3

DP
D

19

PCH_INV_PWM

@ RC147

1

RC146

2

2 0_0402_5%

EDP_BKLCTL

1 0_0402_5%

EDP_DISP

C54
C55
B58
C58
B55
A55
A57
B57

PCH_DP_N0
PCH_DP_P0
PCH_DP_N1
PCH_DP_P1
PCH_DP_N2
PCH_DP_P2
PCH_DP_N3
PCH_DP_P3

DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3

C51
C50
C53
B54
C49
B50
A53
B53

1

HSW_ULT_DDR3L

UCPU1A

21
21
21
21
21
21
21
21

2

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

DDI

EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3

EDP

DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3

EDP_AUXN
EDP_AUXP
EDP_RCOMP
EDP_DISP_UTIL

C45
B46
A47
B47

eDP_TXN_P0
eDP_TXP_P0
eDP_TXN_P1
eDP_TXP_P1

19
19
19
19

C47
C46
A49
B49

D

A45
B45

eDP_AUXN
eDP_AUXP

D20 +EDP_COM
A43 EDP_DISP

RC36
@ RC158

+VCCIOA_OUT

19
19

1
2

2 24.9_0402_1%
1 0_0402_5%

Width 20 mils, Spacing 25 mils,
Length < 100 mil

@
@ RH123

1

2 100K_0402_5%

ENBKL

@ RH158

1

2 100K_0402_5%

PCH_ENVDD

RH300

1

2 1M_0402_5%

PCH_DP_HPD

1 OF 19
@

HSW_ULT_DDR3L

UCPU1I

23

MPCIE_RST#

TP_INT#

MPCIE_RST#
TPM_IRQ#
PCI_PIRQC#
PCI_PIRQD#

U6
P4
N4
N2
AD4

@ T123
C

1
2
3
4

8 10K_8P4R_5%
7
6
5

PCI_PIRQC#
PCI_PIRQD#

@ RH396
@ RH397

1
1

2 10K_0402_5%
2 10K_0402_5%

AUDIO_IRQ#
NGFF_WAKE#

@ RH381

1

2 100K_0402_5%

MPCIE_RST#

RH452

1

2 10K_0402_5%

Sensor_RST#

RP2

TP_INT#

29 TP_INT#
19 TS_RST#
23 NGFF_WAKE#
22 Sensor_RST#

TPM_IRQ#

NGFF_WAKE#
Sensor_RST#
AUDIO_IRQ#

PCH_DP_CLK
PCH_DP_DAT

21
21

+5VS

PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME

U7
L1
L3
R5
L4

DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP

DISPLAY
PCIE

GPIO55
GPIO52
GPIO54
GPIO51
GPIO53

DDPB_HPD
DDPC_HPD
EDP_HPD

C5
B6
B5
A6

PCH_DP_AUXN

21

PCH_DP_AUXP

21

3

1

@ QC5
DII-DMN65D8LW-7
@ RC148

C8
A8
D6

PCH_DP_HPD

PCH_DP_HPD

2

CPU_eDP_HPD#

21

CPU_eDP_HPD#

C

1

eDP_HPD

0_0402_5%

@
RC138
100K_0402_5%

RC160
100K_0402_5%
9 OF 19

19

2

2 100K_0402_5%

PCH_DP_CLK
PCH_DP_DAT

B9
PCH_DP_CLK
C9 PCH_DP_DAT
D9
D11

2

1

DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA

eDP SIDEBAND

2

@ RH380

EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN

D

2 2.2K_0402_5%
2 2.2K_0402_5%

B8
A9
C6

S

1
1

EDP_BKLCTL
ENBKL
PCH_ENVDD

G

RH281
RH282

ENBKL
PCH_ENVDD

1

19
19,35

1

+3VS

@

+1.05VS_VCCST
HSW_ULT_DDR3L

2

UCPU1B

@ T2

1

RC43
62_0402_5%

30,32

1
RC44

2

30

1

H_PROCHOT#

H_PROCHOT#

H_CATERR#

H_PECI

2

RC41

D61
K61
N62

H_PROCHOT#_R
56_0402_5%

K63

H_CPUPWRGD_R

C61

H_CPUPWRGD_R
10K_0402_5%

PROC_DETECT
CATERR
PECI

PU/PD for JTAG signals

MISC

PRDY
PREQ
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO

JTAG

PROCHOT

PROCPWRGD

THERMAL

2
2
2

200_0402_1%
121_0402_1%
100_0402_1%

Avoid stub in the PWRGD path
while placing resistors RC44 & RC53

1 RC55
1 RC58
1 RC60

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
H_DRAMRST#
DDR_PG_CNTL

DDR3 Compensation Signals

AU60
AV60
AU61
AV15
AV61

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1

XDP_PRDY#
XDP_PREQ#
CPU_XDP_TCK
CPU_XDP_TMS
CPU_XDP_TRST#
CPU_XDP_TDI
CPU_XDP_TDO

XDP_PRDY#
18
XDP_PREQ#
18
CPU_XDP_TCK
18
CPU_XDP_TMS
18
CPU_XDP_TRST#
18
CPU_XDP_TDI
18
CPU_XDP_TDO
18

+1.05VS_VCCST

PWR

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

Width 15 mils, Spacing 25 mils, Length < 500 mil
B

J62
K62
E60
E61
E59
F63
F62

DDR3L

J60
H60
H61
H62
K59
H63
K60
J61

@ T226
@ T227
@ T228
@ T229
@ T230
@ T231

XDP_BPM0#
XDP_BPM1#

1

2 RC45 @

51_0402_5% 1

2 RC46 @

CPU_XDP_TDO

51_0402_5% 1

2 RC48

2 0.1U_0402_10V7K

R1d

Stuffed : Dual TCK
unstuffed : Singel TCK
B

Stuffed : Single & Dual TCK
CPU_XDP_TCK

51_0402_5% 1

2 RC52

CPU_XDP_TRST#

51_0402_5% 1

2 RC54 @

closed MCP 1000 mils

+1.35V_DDR

@ CC240 1

51_0402_5% 1

CPU_XDP_TDI

18
18

2 OF 19
@

+3VS

CPU_XDP_TMS

XDP_PRDY#
XDP_PREQ#

@ T263
@ T264

CPU_XDP_TCK
CPU_XDP_TMS
CPU_XDP_TRST#
CPU_XDP_TDI
CPU_XDP_TDO

@ T265
@ T266
@ T267
@ T268
@ T269

R2
R9

UC1

2

RC159
220K_0402_5%
39

5
4

SM_PG_CTRL

VCC

1

NC

2

A
Y

1

DDR_PG_CNTL

3

GND

74AUP1G07GW_TSSOP5

2

@
RC161
2M_0402_5%

+1.35V_DDR

A

1

A

RC75
470_0402_5%

2

02-0320
H_DRAMRST#

@ RC162

1

2 0_0402_5%

DDR3_DRAMRST#

12,13,14,15

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P05-MCP(1/7) DDI,EDP,PM,XDP
Size

5

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

Friday, April 19, 2013

Sheet
1

5

of

45

5

4

3

2

1

D

D

UCPU1C
12,13

C

B

HSW_ULT_DDR3L

HSW_ULT_DDR3L

UCPU1D

DDR_A_D[0..63]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

DDR CHANNEL A

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1

14,15

AU37
AV37
AW36
AY36

M_CLK_A_DDR#0
M_CLK_A_DDR0

AU43
AW43
AY42
AY43
AP33
AR32

DDR_B_D[0..63]

12,13,16
12,13,16

DDR_A_CKE0
DDR_A_CKE1

12,13,16
12,13,16

DDR_A_CS0#
DDR_A_CS1#

12,13,16
12,13,16

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AP32
AY34
AW34
AU34

DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#

AU35
AV35
AY41
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

AP49
AR51
AP51

12,13,16
12,13,16
12,13,16

DDR_A_BS0
12,13,16
DDR_A_BS1
12,13,16
DDR_A_BS2
12,13,16
DDR_A_MA[0..15]

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

V_DDR_REF_CA
V_DDR_REFA_R
V_DDR_REFB_R

12,13,16

12,13

12,13

16
16
16

10 mil trace width

AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

DDR CHANNEL B

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

AM38
AN38
AK38
AL38

M_CLK_B_DDR#0
M_CLK_B_DDR0

AY49
AU50
AW49
AV50
AM32
AK32

14,15,16
14,15,16

DDR_B_CKE0
DDR_B_CKE1

14,15,16
14,15,16

DDR_B_CS0#
DDR_B_CS1#

14,15,16
14,15,16

DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#

14,15,16
14,15,16
14,15,16

AL32
AM35
AK35
AM33
AL35
AM36
AU49

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

14,15,16
14,15,16
14,15,16
DDR_B_MA[0..15]

14,15,16

DDR_B_DQS#[0..7]

C

14,15

DDR_B_DQS[0..7]

14,15

B

3 OF 19

4 OF 19

@

@

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P06-MCP(2/7) DDRIII
Size

5

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

Friday, April 19, 2013

Sheet
1

6

of

45

5

2

1 15P_0402_50V8J

3

PCH_RTCX1

1

RH2
10M_0402_5%

RH11 1

+RTCVCC

2 1M_0402_5%

2

2

YH1
32.768KHZ_12.5PF_9H03200031

18
CH3

2

1

PCH_RTCX2

PCH_RTCRST#

15P_0402_50V8J
far away hot spot

20
20
20
20

1
2
3
4

HDA_BITCLK_AUDIO
HDA_RST_AUDIO#
HDA_SYNC_AUDIO
HDA_SDOUT_AUDIO

8
7
6
5

1

2
2

@T273
@T275
@T276
@T277
@T278

PCH_SRTCRST#

20K_0402_5%

CH5
1U_0402_6.3V6K

1

2

1

RH23

2

20K_0402_5%

1

@
CLRP2
SHORT PADS
ME CMOS

18

1

PCH_JTAG_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_JTAG_JTAGX

PCH_JTAG_JTAGX

2

PCH_INTVRMEN
330K_0402_5%

2

PCH_TRST
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
RSVD
RSVD
JTAGX
RSVD

R1341
1M_0402_5%

D

closed MCP 2000 mils

F5
E5
C17
D17

SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0

EC_SMI#
PCH_GPIO35
PCH_GPIO36
mSATA_DET#

V1
U1
V6
AC1

EC_SMI#
PCH_GPIO35
PCH_GPIO36
mSATA_DET#

A12
L11
K10
C12
U3

SATA_IREF
RSVD
RSVD
SATA_RCOMP
SATALED

JTAG

Reserve for RF please close to UH1

mSATA

EC_SMI#

1
1
1

@ RH390
@ RH391
RH392

2 10K_0402_5%
2 200K_0402_5%
2 100K_0402_5%

HDA_SDO

30

mSATA_DET#

SATA_RCOMP RH43 1
2
PCH_SATALED#
RH35

PCH_GPIO35
PCH_GPIO36
mSATA_DET#

@ T270
@ T271
@ T272
@ T274

ME debug mode , this signal has a weak internal PD
+V1.05S_ASATA3PLL

24

2 3K_0402_1%
1
10K_0402_5%

L=>security measures defined in the Flash
Descriptor will be in effect (default)
H=>Flash Descriptor Security will be overridden

+3VS

+1.5VS_3.3VS_AUDIO

Width = 15 mil, Spacing = 12 mil
Close PCH within 500 mil

@ RH42 1

2 1K_0402_5%

HDA_SDOUT

= Disabled
*Low
High = Enabled

5 OF 19
@

1

330K_0402_5%

HDA_SDOUT
10P_0402_50V8J

+3VS

J6
H6
B14
C15

SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37

AU62
AE62
AD61
AE61
AD62
AL11
AC4
AE63
AV2

PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

24
24
24
24

J8
H8
A17
B17

SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1

SATA

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

2

+5VA

@ RH34

PCH_JTAG_JTAGX
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_TCK
PCH_JTAG_TDI

18
18
18
18
18

+RTCVCC

RH31

HDA_SDIN0

HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_RST/I2S_MCLK
AUDIO
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_SDO/I2S0_TXD
HDA_DOCK_EN/I2S1_TXD
HDA_DOCK_RST/I2S1_SFRM
I2S1_SCLK

closed MCP 1000 mils

CLP1 & CLP2 place near DIMM

1

AW8
AV11
AU8
AY10
AU12
AU11
AW10
AV10
AY8

HDA_SDOUT

CMOS
@
CLRP1
SHORT PADS
PCH_RTCRST#

2

RH25

1

CH4
1U_0402_6.3V6K

2

20

1

RTC

HDA_BIT_CLK
HDA_RST#
HDA_SYNC
HDA_SDOUT
HDA_BIT_CLK
HDA_SYNC
HDA_RST#

1

@ MC103

J5
H5
B15
A15

SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2

33_8P4R_5%

1

2

RTCX1
RTCX2
INTRUDER
INTVRMEN
SRTCRST
RTCRST

RP3

D

+RTCVCC

AW5
AY5
AU6
AV7
AV6
AU7

PCH_RTCX1
PCH_RTCX2
SM_INTRUDER#
PCH_INTVRMEN
PCH_SRTCRST#
PCH_RTCRST#

2

HSW_ULT_DDR3L

UCPU1E

1

CH2

4

2

From EC, for enable
ME code programing

C

Q351

+1.5VS_3.3VS_AUDIO

G

HDA_SDO

1

3
S

30

D

*

INTVRMEN
H：Integrated VRM enable
L：Integrated VRM disable

RH24 1

2 1K_0402_5%

HDA_SDOUT

XTAL24_IN

C43
C42
U2

+1.05VA

R3d
R5
R8
R6

Stuffed : Single & Dual TCK
RH40 1

C

DII-DMN65D8LW-7

PCH JTAG
R4

HSW_ULT_DDR3L

UCPU1F

2 51_0402_5%

+3VS

@ RH91

+3VS

@ RH95

1

2 10K_0402_5%

PCH_GPIO18

1

2 10K_0402_5%

PCH_GPIO19

B41
A41
Y5

1

2 10K_0402_5%

PCH_GPIO20

C41
B42
AD1

PCH_JTAG_TDI

RH445 1

2 51_0402_5%

PCH_JTAG_TDO

RH39 1

2 51_0402_5%

PCH_JTAG_TMS

@ RH375 1

2 1K_0402_5%

PCH_JTAG_JTAGX

@ RH53 1

2 51_0402_5%

PCH_JTAG_TCK

23
23

WLAN

CLK_PCIE2#
CLK_PCIE2
+3VS

RH100

@ RH103

+3VS

@ RH107

+3VS

@ RH110

+3VS

1

1

1

2 10K_0402_5%

2 10K_0402_5%

PCH_GPIO22

A39
B39
U5

PCH_GPIO23

B37
A37
T2

XTAL24_IN
XTAL24_OUT
RSVD
RSVD
DIFFCLK_BIASREF

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19

SIGNALS

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21

CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22

A25
B25

XTAL24_IN
XTAL24_OUT

K21
M21
C26

XCLK_BIASREF

C35
C34
AK8
AL8

1

RH113

RH117

2 3K_0402_1%

+V1.05S_AXCK_LCPLL

1
2
1
1
1

RH428
RH360
RH386

CLKOUT_LPC0
CLKOUT_LPC1

2 22_0402_5%
2 22_0402_5%
2 30_0402_5%

2
1M_0402_5%

YH2
24MHZ_12PF_7V24000020

TESTLOW1
TESTLOW2
TESTLOW3
TESTLOW4

AN15
AP15

1

XTAL24_OUT

XCLK_BIASREF <100 MILS

3
4

1

CLK_PCI_TPM
22
CLK_PCI_LPC
30
CLK_LPC_DEBUG
18

2

B35
A35

1
CH24
15P_0402_50V8J

2

CH23
15P_0402_50V8J

LPC CLOCK CAN FEED ONLY 1 LOAD AT A TIME

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23

TESTLOW1
TESTLOW2
TESTLOW3
TESTLOW4

@ RH410

1

TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8

CLOCK

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20

B38
C37
N1

PCH_GPIO21

2 10K_0402_5%

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18

1
1
1
1

RH76
RH77
RH78
RH79

2
2
2
2

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

6 OF 19

2

@

0_0402_5%
DII-DMN65D8LW-7
D

S

23

3

CLK_REQ2#

B

1

PCH_GPIO20

Q346

UCPU1G

B

HSW_ULT_DDR3L

2

G

1

+3VS_NGFF

AU14
AW12
AY12
AW11
AV12

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

LAD0
LAD1
LAD2
LAD3
LFRAME

LPC
SMBUS

2

R1197
100K_0402_5%

18,22,30
18,22,30
18,22,30
18,22,30
18,22,30

AA3
Y7
Y4
AC2
AA2
AA4
Y6
AF1

PCH_SPI_CLK
PCH_SPI_CS#

PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_IO2
PCH_SPI_IO3

+3VS

SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3

SPI

SMBALERT/GPIO11
SMBCLK
SMBDATA
SML0ALERT/GPIO60
SML0CLK
SML0DATA
SML1ALERT/PCHHOT/GPIO73
SML1CLK/GPIO75
SML1DATA/GPIO74
CL_CLK
CL_DATA
CL_RST

C-LINK

AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3

SMBALERT#
SMBCLK
SMBDATA
SML0ALERT#
SML0CLK
SML0DATA

SMBALERT#

22

SML0CLK 24
SML0DATA 24
SML1ALERT# 22

SML1CLK
SML1DATA

Connect NFC

PU to +3VNS_PWR on Sensor HUB side

AF2
AD2
AF4

CL_CK 23
CL_DAT 23
CL_RST# 23
+3VS

+3V_PCH

+3VS

RP7

@ MC118
RH56 1

2 1K_0402_5%

SPI_IO3_ROM

1

2

12P_0402_50V8J

7 OF 19
@

+3VS

PCH_SPI_SO
PCH_SPI_IO2
PCH_SPI_SI
PCH_SPI_IO3

RP4

1
2
3
4

SPI_SO_ROM
SPI_IO2_ROM
SPI_SI_ROM
SPI_IO3_ROM

6

SMBCLK

6

SML1CLK

1

PCH_SMLCLK

19,26,30

2

8
7
6
5

QH3A

RH99
10K_0402_5%

1

PCH_SMBCLK

15_0804_8P4R_5%

@ RH453

A

SPI ROM FOR ME ( 8MByte )
ROM is Quad SPI

1

QH4A

1

2

0_0402_5%

Connect EC, ALS
4

@ RH105

0_0402_5%

PCH_SMLDATA

+3VS

1

RH72

1

QH3B

3

4

PCH_SMBDATA

2

1

0_0402_5%

@ RH111

2 499_0402_1%
2 499_0402_1%

1
2
3
4

SMBALERT#
SML0ALERT#
EC_SMI#

12,14,18,19

DMN66D0LDW-7_SOT363-6

QH4B

1
@ RH454

RH70

SML0DATA

RP19

19,26,30

DMN66D0LDW-7_SOT363-6

SML0CLK

Connect DDR SPD, XDP

2

SMBDATA

3

SML1DATA

12,14,18,19

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

5

PCH_SPI_CLK

2

2 15_0402_5%

5

1

2

RH255

8
7
6
5

2.2K_0804_8P4R_5%
RH98
10K_0402_5%

Closed to UCPU1
SPI_CLK_ROM

1
2
3
4

SMBCLK
SMBDATA
SML1CLK
SML1DATA

PCH_SPI_CLK

1

SPI_IO2_ROM

1

2 1K_0402_5%

2

RH54 1

8
7
6
5

A

+3VS

10K_8P4R_5%

2
0_0402_5%

U48
PCH_SPI_CS#
SPI_SO_ROM
SPI_IO2_ROM

1
2
3
4

/CS
DO(IO1)
/WP(IO2)
GND

VCC
/HOLD(IO3)
CLK
DI(IO0)

W25Q64FVSSIQ_SO8

8
7
6
5

SPI_IO3_ROM
SPI_CLK_ROM
SPI_SI_ROM

1

CH6
.1U_0402_16V7K

@ MC94

@ MR256

2

1

1

22P_0402_50V8J

2

SPI_CLK_ROM

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2

33_0402_5%

2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Reserve for EMI please close to U48

Title

P07-MCP(3/7) SATA,HDA,CLK,SPI
Size

5

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

Sheet

Friday, April 19, 2013
1

7

of

45

5

4

3

2

1

+3V_PCH

+3VS

PM_CLKRUN#

2

RH248

1 8.2K_0402_5%

30
18
18,29
29

02-0320

Non Deep S3 (Pop RH429)
Deep S3 (Pop RH430)

SUSACK#
PM_SYS_RESET#
SYS_PWROK
PCH_PWROK

+3V_PCH_DSW

2 3K_0402_5%

@ R1312

SUS_PWR_DN

Deep S3 support, connect to EC

1

PBTN_OUT#_R

@ RH429
@ RH430
@ RH450

2
2
2

1 0_0402_5%
1 0_0402_5%
1 0_0402_5%

@ RH131

2

1 0_0402_5%

+3V_PCH
HSW_ULT_DDR3L

UCPU1H

WAKE#

30
30
30
30

18,30,36,38
+3V_PCH_DSW

SLP_WLAN#

1

@ RH402

2
2
2
2

1
1
1
1

@ RH463

2

1 0_0402_5%

PM_SLP_S0#

18,29,30

2

@ RH438

1.05VS_PG

18,20,29,30

8
7
6
5

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

PCH_RSMRST#_R
SUS_PWR_DN
PBTN_OUT#_R
AC_PRESENT_R
PCH_GPIO72
SLP_S0#
SLP_WLAN#

1 0_0402_5%

2

@ RH439

PBTN_SW#

AK2
AC3
AG2
AY7
AB5
AG7

SUSACK
SYS_RESET
SYS_PWROK
PCH_PWROK
APWROK
PLTRST

DSWVRMEN
DPWROK
WAKE
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63

AW6
AV4
AL7
AJ8
AN4
AF3
AM5

RSMRST
SUSWARN/SUSPWRDNACK/GPIO30
PWRBTN
ACPRESENT/GPIO31
BATLOW/GPIO72
SLP_S0
SLP_WLAN/GPIO29

SLP_S4
SLP_S3
SLP_A
SLP_SUS
SLP_LAN

AW7 DSWODVREN
AV5 PCH_DPWROK
AJ5 WAKE#
V5
PM_CLKRUN#
AG4 SUS_STAT#
AE6 SUSCLK
@ RH132
AP5
AJ6
AT4
AL5
AP4
AJ7

WAKE#

1

PBTN_OUT#_R

PBTN_OUT#_R

2

2

PM_CLKRUN#
22,30
SUS_STAT# 22
SUSCLK_R
23,30
PM_SLP_S5# 18,30

1 0_0402_5%

PM_SLP_S4#
PM_SLP_S3#
@ RH313

2
0_0402_5%

2

SUSCLK

2

1

1

2

+RTCVCC

DSWODVREN

RH147

2

1 330K_0402_5%

DSWODVREN

@ RH151

2

1 330K_0402_5%

+3V_PCH

1

2 10K_0402_5%

RH394

1

2 100K_0402_5%

4

PLT_RST#

IN1

O

*

2

IN2

RH171
100K_0402_5%

UH5
SN74AHC1G08DCKR_SC70-5

@
RH183
10K_0402_5%

2

18,22,23,30

2

@ RH272

PCH_PWROK

PM_SLP_S5#

@ RH426

1

2 1K_0402_5%

PM_SLP_S4#

@ RH415

1

2 1K_0402_5%

PM_SLP_S3#

@ RH416

1

2 1K_0402_5%

1
+3V_PCH

1 1K_0402_5%

PCH_GPIO15

+3V_PCH

3

closed MCP 2000 mils
@ T279
@ T280
@ T281
@ T282
@ T283
@ T284
@ T285
@ T286
@ T287
@ T288

2

1 0_0402_5%

@ RH128

2

1 0_0402_5%

2

AUDIO_PWREN
SENSOR_HUB_I2C_WAKE
PCH_GPIO17
KB_DET#
EC_RUNTIME_SCI#
KB_BL_DET
SENSOR_INT#
MEM_CONFIG0
MEM_CONFIG1
UART_WAKE#

1 0_0402_5%

2

1 100K_0402_5%

BT_RADIO_DIS#

@ RH294

2

1 10K_0402_5%

NFC_IRQ

RH383

2

1 100K_0402_5%

UART_WAKE#

@ RH400

2

1 100K_0402_5%

USB0_PWR_EN

@ RH295

2

1 10K_0402_5%

SENSOR_INT#

RH398

1

2 10K_0402_5%

EC_RUNTIME_SCI#

@ RH395

1

2 10K_0402_5%

PCH_GPIO17

20,27,35

AUDIO_PWREN
28 KB_BL_DET

28

24 NFC_RST#
24 NFC_IRQ
22
23

TPM_RST#
BT_CS_NOTICE
22 SLATE_MODE

SENSOR_DFU_EN#

+3VS
22

2

1 1M_0402_5%

NFC_DET#

SENSOR_HUB_I2C_WAKE
19 TS_INT#
27 MPHY_PWREN
25 USB0_PWR_EN
22 SENSOR_INT#
27 EN_CAM

RH457

2

1 49.9K_0402_1%

UART1_RXD

RH458

2

1 49.9K_0402_1%

UART1_TXD

RH459

2

1 49.9K_0402_1%

UART1_RTS#

RH460

2

1 49.9K_0402_1%

UART1_CTS#

30

@ RH384

2

1 100K_0402_5%

TS_INT#

22

22,27

NC

VCC

GND

OUT Y

SSD_PWREN#

RH423

2

H_THERMTRIP#

1

RC149

4

SSD_PWREN

35

R1185

1

2 100K_0402_5%

KB_DET#

RH302

1

2 100K_0402_5%

NGFF_PWREN

R1163

1

2 100K_0402_5%

SERIRQ

RH29

1

2 10K_0402_5%

KB_RST#

RH196

1

1

2 10K_0402_5%

DDR_CHA_EN

RH440

1

2 100K_0402_5%

DDR_CHB_EN

RH441

1

DDR_CHA_EN

@ RH442

1

2 SHORT PADS

DDR_CHB_EN

@ RH443

1

2 SHORT PADS

RC156

1

2 49.9_0402_1%

1

2 1K_0402_5%

2 100K_0402_5%

HSW_ULT_DDR3L

UCPU1J

P1
AU2
AM7
AD6
Y1
T3
AD5
AN5
AD7
AN3

AUDIO_PWREN
KB_BL_DET
PCH_GPIO15
KB_DET#
PCH_GPIO17

NFC_IRQ

MEM_CONFIG0
MEM_CONFIG2
MEM_CONFIG1
SENSOR_HUB_I2C_WAKE
TS_INT#
MPHY_PWREN
USB0_PWR_EN
SENSOR_INT#
TPM_DET

UART_WAKE#
EC_RUNTIME_SCI#

NFC_DET#
HDA_SPKR

AG6
AP1
AL4
AT5
AK4
AB6
U4
Y3
P3
Y2
AT3
AH4
AM4
AG5
AG3
AM3
AM2
P2
C4
L2
N5
V2

BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46

CPU/
MISC

THRMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD

D60
V4
T4
AW15
AF20
AB21

H_THERMTRIP#_R 1
KB_RST# @ RC49
SERIRQ
PCH_OPIRCOMP

H_THERMTRIP#
0_0402_5%

GPIO

SERIAL IO

GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81

R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2

PCH_GPIO86

PCH_GPIO86
BT_RADIO_DIS#

SSD_PWREN#
DDR_CHA_EN
DDR_CHB_EN

SDIO_D0

B

BT_RADIO_DIS#
23
PCH_GPIO88
30
TOUCH_EN
27

1

2 10K_0402_5%

RH337

2

1 100K_0402_5%

TPM_DET

1

2 2.2K_0402_5%

I2C0_SDA

@ RH424

1

2 2.2K_0402_5%

I2C0_SCK @ RH462

1

2 2.2K_0402_5%

I2C0_SCK

@ RH425

1

2 2.2K_0402_5%

@ RH435

1

2 1K_0402_5%

*01

= Enable
= Disable

DDR Memory Configuratino Type Strap pin
+3V_PCH
@ RH271

2

1 10K_0402_5%

MEM_CONFIG2

@ RH314

2

1 10K_0402_5%

@ RH303

2

1 10K_0402_5%

MEM_CONFIG0

@ RH316

2

1 10K_0402_5%

@ RH180

2

1 10K_0402_5%

MEM_CONFIG1

@ RH315

2

1 10K_0402_5%

Pin Name

Micron 4G
SA00005TH0L

Micron 8G
SA00006FB0L

Hynix 4G
SA00006JF0L

Hynix 8G
TBD

Samsung 4G
SA00006J30L

Samsung 8G
SA00006J80L

PCH_GPIO59

MEM_CONFIG0

0

1

0

1

0

1

PCH_GPIO48

MEM_CONFIG1

0

0

1

1

0

0

PCH_GPIO47

MEM_CONFIG2

0

0

0

0

1

1

A

TPM_DET

TPM BOM Optional

Audio DSP

TPM_DET
Sensor HUB

20

I2C0_SDA_DSP

20

I2C0_SCK_DSP

22

I2C0_SDA_SNR

22

I2C0_SCK_SNR

@ RA7

1

2 0_0402_5%

I2C0_SDA

@ RA8

1

2 0_0402_5%

I2C0_SCK

@ R1225

2

1 0_0402_5%

@ R1224

2

1 0_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

0 = W/O TPM

2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P08-MCP(4/7) PM,GPIO,LPIO,MISC
Size

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

5

1 1K_0402_5%

Top-Block Swap Override mode

UART1_RXD
23
UART1_TXD 23
UART1_RTS#
23
UART1_CTS#
23
I2C0_SDA
30
I2C0_SCK
30
I2C1_SDA
19
I2C1_SCK
19
SDIO_CLK
23
SDIO_CMD
23
SDIO_D0
23
SDIO_D1
23
SDIO_D2
23
SDIO_D3
23

GPIO Pin

NTPM@

1 = W/TPM

2

+3VS

I2C0_SDA @ RH461

A

TPM

@ RH434

GPIO66 have internal pull down

19

TPM@
RH274

SPI
+VS_LPSS_SDIO

SDIO_D0

LCD_DBC
UART1_RXD
UART1_TXD
UART1_RTS#
UART1_CTS#
I2C0_SDA
I2C0_SCK

Boot BIOS Location

0

NGFF_PWREN
23,27
TPM_PWREN
27

+3VS

+3VNS_PWR

GPIO86 have internal pull down

Width = 15 mil, Spacing = 12 mil
Close PCH within 500 mil

NGFF_PWREN

@ RH32

Boot BIOS Strap

HDA_SPKR

+3V_PCH

PCH_GPIO86

KB_RST# 30
SERIRQ
22,30

*
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69

2 100K_0402_5%

2

10 OF 19

*LOW=Default
HIGH=No Reboot

+3VS

MPHY_PWREN

@

2 1K_0402_5%

2 1K_0402_5%

1 0_0402_5%

+3VS

@ RH37 1

C

IN A

@ RH431

SENSOR_EN

23 UART_WAKE#
EC_RUNTIME_SCI#
24 DEVSLP0
SENSOR_STANDBY#
23 WL_OFF#
24 NFC_DET#
20 HDA_SPKR

30

SN74AUP1G04DCKR_SOT23-5

PCH_GPIO27

Deep S3 support,
PCH_GPIO27 connect from EC PCH_WAKE#

22

KB_DET#

EC_WAKE_SCI#

30

+1.05VS_VCCST

PCH_OPIRCOMP
@ RH188

WAKE_PCH#

5
+3VS

2

SSD_PWREN#

TLS Confidentiality
Low - Intel ME Crypto Transport Layer Security (TLS)
cipher suite with no confidentiality
High - Intel ME Crypto Transport Layer Security (TLS)
cipher suite with confidentiality

@ RH310

WAKE#

PCH_GPIO27 @ RH427

For Power on only, after solder MCP need remove.

+3VS

PCH_GPIO27

U682

PCH_GPIO15

RH465

Non Deep S3

10P_0402_50V8J

5
SYS_PWROK

P

1 100K_0402_5%

1

+3VS

30,34

PCH_RSMRST#_R

Reserve for RF please close to UH1

DSWODVREN - On Die DSW VR Enable
H：Enable
L：Disable

PCH_PLTRST#

C

B

08-0328 Deep S3 Support
5VA_EN

1

@ MC102

PCH Strap PIN

1

G

2

3

RH159

2

@ RH309
0_0402_5%

02-0320
PCH_DPWROK

02-0320

D

@ RH126
0_0402_5%

1

1 1K_0402_5%

@ RH270

2 100K_0402_5%

PCH DPWROK Option for Deep S3

PM_SLP_S4# 18,30,39
PM_SLP_S3# 18,27,30,37,38
PM_SLP_A# 18
PM_SLP_SUS#
27,29,30,34,38

1 0_0402_5%

Deep S3 Support
Non Deep S3 (De-pop RH313)

18

+3VS

2

*

1

2 1M_0402_5%

@ RH186

PCH_RSMRST#

PCH_DPWROK @ RH401
23

8 OF 19

APWROK_R

1 0_0402_5%

@ RH168

PCH_GPIO27

2 1M_0402_5%

SYSTEM POWER MANAGEMENT

SUSACK#_R
SYS_RESET#
SYS_PWROK
PCH_PWROK
APWROK_R
PCH_PLTRST#

+3VS

10K_8P4R_5%
RH12 1

AC_PRESENT

1

@

RP20

1
2
3
4

PCH_GPIO27
PCH_GPIO72

PCH_RSMRST# @ RH133
@ RH297
@ RH293
AC_PRESENT @ RH137

RH154

2 10K_0402_5%

Deep S3 support, connect to DSW power rail
SYS_RESET#

PCH_RSMRST#
PCH_SUSWARN#
PBTN_OUT#
AC_PRESENT

2 1K_0402_5%
SUS_PWR_DN

D

NON-Deep S3 Support

1

RH146

Friday, April 19, 2013

Sheet
1

8

of

45

5

4

3

C23
C22

D

F8
E8
B23
A23
H10
G10
B21
C21
E6
F6
B22
A21

NGFF

23
23

PCIE_PRX_WLANTX_N3
PCIE_PRX_WLANTX_P3

23
23

PCIE_PTX_WLANRX_N3
PCIE_PTX_WLANRX_P3

23
23

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4

23
23

PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

G11
F11
CH11
CH16

1
1

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

PCIE_PTX_WLANRX_N3_C
PCIE_PTX_WLANRX_P3_C

2 0.1U_0402_10V7K
2 0.1U_0402_10V7K

PCIE_PTX_DRX_N4_C
PCIE_PTX_DRX_P4_C

USB2N1
USB2P1

PERN5_L1
PERP5_L1

USB2N2
USB2P2

PETN5_L1
PETP5_L1

USB2N3
USB2P3

PERN5_L2
PERP5_L2

USB2N4
USB2P4

PETN5_L2
PETP5_L2

USB2N5
USB2P5

PERN5_L3
PERP5_L3

USB2N6
USB2P6

PETN5_L3
PETP5_L3

USB2N7
USB2P7
USB3RN1
USB3RP1
PCIE

USB

USB3TN1
USB3TP1

PERN4
PERP4

B29
A29

USB3RN2
USB3RP2

PETN4
PETP4

G17
F17

USB3TN2
USB3TP2

USBRBIAS
USBRBIAS
RSVD
RSVD

PERN2/USB3RN4
PERP2/USB3RP4

B31
A31

2 3K_0402_1%

PCIE_RCOMP

25
25

USB3.0 (Power Share)

USB20_N1
USB20_P1

25
25

USB3.0 (Power Share)

USB20_N2
USB20_P2

23
23

NGFF (WLAN)

AR10
AT10

USB20_N3
USB20_P3

19
19

Touch Panel

AM15
AL15

USB20_N4
USB20_P4

19
19

Camera

AM13
AN13

USB20_N5
USB20_P5

22
22

Sensors HUB

AR8
AP8

E15
E13
A27
B27

OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43

RSVD
RSVD
PCIE_RCOMP
PCIE_IREF

Width = 15 mil, Spacing = 15 mil
Close PCH within 500 mil

DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62

AR13
AP13
G20
H20

USB3RN0
USB3RP0

25
25

C33
B34

USB3TN0
USB3TP0

25
25

USB3RN1
USB3RP1

25
25

USB3TN1
USB3TP1

25
25

E18
F18
B33
A33

AJ10
AJ11
AN10
AM10

1

USBRBIAS

DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63

B

DC_TEST_C1_C2

2

Net USB_BIAS route impedacnes should be 50-ohm
and length less than 450-mil spacing is 15-mil.

RH163
22.6_0402_1%

AL3
AT1
AH2
AV3

USB_OC0#
USB_OC1#
USB_OC2#
USB1_PWR_EN

C

USB_OC0#
USB_OC1#

RP11

25
25

USB1_PWR_EN

USB_OC2#
USB_OC0#
USB_OC1#
USB1_PWR_EN

25

USB_OC0#
USB_OC1#
USB_OC2#
USB1_PWR_EN

1
2
3
4

8
7
6
5

10K_8P4R_5%

closed MCP 2000 mils
11 OF 19

AY2
AY3
AY60
AY61
AY62
B2
B3
B61
B62
B63
C1
C2

D

AP11
AN11

@

UCPU1Q

Debug Port

+3V_PCH

PETN2/USB3TN4
PETP2/USB3TP4

+V1.05S_AUSB3PLL

1

USB20_N0
USB20_P0

AR7
AT7

Within 450 mils

PETN1/USB3TN3
PETP1/USB3TP3

F15
G15

RH338

AN8
AM8

PERN1/USB3RN3
PERP1/USB3RP3

C30
C31
C

USB2N0
USB2P0

PETN5_L0
PETP5_L0

PETN3
PETP3

F13
G13
CH1237 1
CH1238 1

PERN5_L0
PERP5_L0

PERN3
PERP3

C29
B30

1

HSW_ULT_DDR3L

UCPU1K

F10
E10

2

@ T289
@ T290
@ T291
@ T292

HSW_ULT_DDR3L

DAISY_CHAIN_NCTF_AY2
DAISY_CHAIN_NCTF_AY3
DAISY_CHAIN_NCTF_AY60
DAISY_CHAIN_NCTF_AY61
DAISY_CHAIN_NCTF_AY62
DAISY_CHAIN_NCTF_B2
DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_B61
DAISY_CHAIN_NCTF_B62
DAISY_CHAIN_NCTF_B63
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2

A3
A4

DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4

17 OF 19

A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63

DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63

DC_TEST_A3_B3

DC_TEST_A61_B61
B

DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62

@

UCPU1R

AT2
AU44
AV44
D15
F22
H22
J21

HSW_ULT_DDR3L

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD

N23
R23
T23
U10
AL1
AM11
AP7
AU10
AU15
AW14
AY14

18 OF 19
@
A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P09-MCP(5/7) PCIE,USB
Size

5

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

Friday, April 19, 2013

Sheet
1

9

of

45

5

4

3

2

1

+1.35V_DDR
+1.35V_DDR

2

4.2A

1

1

VR_ON

R1211
1M_0402_5%

29,40

L59
J58
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50

@
R1241
1K_0402_5%

IMVP_VR_PG

IMVP_VR_PG

D

+VCC_CORE

2

1

2

CC234
2.2U_0402_6.3V6M

1

CC239
2.2U_0402_6.3V6M

CC238
2.2U_0402_6.3V6M

2

CC233
2.2U_0402_6.3V6M

1

1

2

+VCCIO_OUT

+VCC_CORE

1

2

40

VCCSENSE

18,29

2 100_0402_1%
2 0_0402_5%

RC94 1
@ RC92 1
@ RC96 1
@ RC150 1
VR_ON
@ RC151 1
IMVP_VR_PG @ RC152 1

VR_SVID_ALRT#
40 VR_SVID_CLK
40 VR_SVID_DAT
1.05VS_VCCST_PG
30,40 VR_ON

2
2
2
2
2
2

18

SIP

+1.05VS
RC93 2

1 75_0402_5%

H_CPU_SVIDALRT#

RC95 1

2 130_0402_1%

H_CPU_SVIDDAT

VIDSOUT:
Requires a pull-up to VCCIO through a pull-up resistor of 110 ±5% close to the processor, and a pull-up
to VCCIO through a pull-up resistor of 110 ±5% close to Intel MVP 7.
VIDSCLK:
Required pull-up to VCCIO through 55 ±5% close to Intel IMVP 7.
C

43_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
VCCSTPG_MCP
VR_ON_MCP
VRPG_MCP

+1.05VS_VCCST

2

0_0805_5%

1

02-0320

2

CH1204
22U_0603_6.3V6M

2

R1179

1

1
CH1205
1U_0402_6.3V6K

2

FIVE_EN

150_0402_5%

AC22
AE22
AE23

+1.05VS_VCCST

AB57
AD57
AG57
C24
C28
C32

+VCC_CORE
+1.05VDX_MODPHY

2 0_1206_5%

2

1

2

CH41
1U_0402_6.3V6K

+V1.05VS_VCCHSIO

1

CH40
1U_0402_6.3V6K

R1240 1

+V1.05S_AUSB3PLL

B

2

2

K9
L10
M9
N8
P9
B18
B11

+V1.05VS_VCCHSIO

CH85
1U_0402_6.3V6K

1

1
CH1209
22U_0805_6.3V6M

+1.05VS

1

2

CH1208
22U_0805_6.3V6M

CH39
1U_0402_6.3V6K

+V1.05S_AUSB3PLL
+V1.05S_ASATA3PLL

2

2

Y20
AA21
W21

+V1.05S_APLLOPI

+1.05VS
LH12

1

+V1.05S_APLLOPI

1

2.2UH_LQM2MPN2R2NG0L_30%
CH1212 +
100U_A_6.3V_R70M

2

2

2

J13

+V1.05A_DCPSUS

1@

CH1239
10U_0603_6.3V6M

2

AH14

+1.5VS_3.3VS_AUDIO

2

+V1.05S_ASATA3PLL

AH13

1

LH11

1

2

CH1220
22U_0603_6.3V6M

2.2UH_LQM21PN2R2MC0D_20%
1
CH1210
22U_0805_6.3V6M

1
CH1211
22U_0805_6.3V6M

2

+3V_PCH_DSW

1

2
CH1225
22U_0603_6.3V6M

VCCSUS3_3
VCCRTC
DCPRTC

SPI

RSVD
VCCAPLL
VCCAPLL

VCCSPI

OPI

+V1.05S_AXCK_DCB
+V1.05S_AXCK_LCPLL

+1.05VS

1

@ RH348

1

2

CH1234
1U_0402_6.3V6K

0_0402_5%
@ RH351

1

+3V_PCH

2

0_0603_5%
A

Non Deep S3

1
CH1235
1U_0402_6.3V6K

2

AH11
AG10
AE7

CH1206 1

2 0.1U_0402_10V7K

Y8

+3VS

1

AG14
AG13

+1.05VS

VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1

HDA

VCCHDA
VRM

DCPSUS2

CORE

VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3

2

+3V_PCH_DSW

J18
K19
A20
J17
R21
T21
K18
M20
V21
AE20
AE21

GPIO/LPC

VCCTS1_5
VCC3_3
VCC3_3

B

+1.05VS

closed to VCC1P05
1

review feedback change to 0 ohm
@ RH346
+PCH_VCCDSW

1

CH1218

2

1

CH1215
1U_0402_6.3V6K

1
CH1216
1U_0402_6.3V6K

1

VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3

SERIAL IO

VCCSDIO
VCCSDIO

0_0402_5%

+V1.05S_AXCK_DCB_L

1

1

2.2UH_LQM2MPN2R2NG0L_30%

1

+
CH1228
100U_A_6.3V_R70M

1

+V1.05S_AXCK_DCB

2

CH1229
1U_0402_6.3V6K

+RTCVCC

+V1.05A_DCPSUS

1

+1.5VS

2

1
CH1222
1U_0402_6.3V6K

2

1

@
CH1223
22U_0603_6.3V6M

CH84
1U_0402_6.3V6K

U8
T9

+VS_LPSS_SDIO

2

LPT LP POWER
SUS OSCILLATOR

DCPSUS4
RSVD
VCC1_05
VCC1_05

USB2

AB8

2

1
CH82
0.1U_0402_10V7K

2

2

+RTC_VCCSUS

1
+1.05VS

1

2

2

1

2

+3V_PCH

@ RH354

1

+VS_LPSS_SDIO

2

1

0_0402_5%
CH1207
1U_0402_6.3V6K

2

CH1227
1U_0402_6.3V6K

@
L63

1

+V1.05A_AOSCSUS

1
1

@
CH1232
1U_0402_6.3V6K

+

2

+3VS

0_0603_5%

1

CH1233
1U_0402_6.3V6K

+1.8VS

0_0603_5%

+VS_LPSS_SDIO

@ RH341

+V1.05A_AOSCSUS

AC20
AG16
AG17

@ RH350

02-0320

CH1226
0.1U_0402_10V7K

+1.05VA

@ RH406

2

+V1.05A_AOSCSUS_L

1

2.2UH_LQM2MPN2R2NG0L_30%
CH1240
100U_A_6.3V_R70M
@

2

A

0_0603_5%

L62

2

0_0402_5%

+V1.05S_AXCK_LCPLL_L

1

2

2.2UH_LQM2MPN2R2NG0L_30%
CH1230
100U_1206_6.3V6M

2

+V1.05S_AXCK_LCPLL

1

2

1
CH1231
1U_0402_6.3V6K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

Title

P10-MCP(6/7) PWR,VCC

2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

5

2

1
CH83
0.1U_0402_10V7K

+3VS

2

+1.05VS
@ RH356

2

2

closed to VCCRTC

SIP

13 OF 19

L61

2

1
CH1217
10U_0603_6.3V6M

1U_0402_6.3V6K

DCPSUS can be NC, if INTVRMEN pull up
to enable Integrated VRM
+1.05VS
@ RH355

2

+1.05VS
0_0402_5%

J15
K14
K16

2

2

1

@

2

@
CH47
0.1U_0402_10V7K

2
J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8

1

CH1224
1U_0402_6.3V6K

C

+RTC_VCCSUS

USB3

DCPSUS3

THERMAL SENSOR

+V1.05S_AXCK_LCPLL

+3VALW

VCC
VCC
VCC
VCC
VCC
VCC

2

2

02-0320

AC9
AA9
AH10
V8
W9

+3VS

+1.05VS

Deep S3 Support

VCCST
VCCST
VCCST

RTC

+3V_PCH

+1.05VDX_MODPHY

HSW ULT POWER

VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VCCASW
VCCASW

0_0603_5%
CH1214
1U_0402_6.3V6K

1@

1
CH1213
1U_0402_6.3V6K

VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY

+RTCVCC
HSIO

@ RH405

2

VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD

HSW_ULT_DDR3L

VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL

+1.05VA

1

VCC
RSVD
RSVD

D

+1.5VS_3.3VS_AUDIO

LH10
2.2UH_LQM21PN2R2MC0D_20%
1

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

12 OF 19

UCPU1M

1

RSVD
RSVD

C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57

@

+1.5VS_3.3VS_AUDIO
+1.05VDX_MODPHY

L62
N63
L63
B59
F60
C59
D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59

FIVE_EN

FIVE_EN

+1.05VS_VCCST

@ RH340

1

E63
AB23
A59
E20
AD23
AA23
AE59

VCCSENSE_R

+VCCIO_OUT
+VCCIOA_OUT

close to CPU

+1.05VS_VCCST

F59
N58
AC58

RC97 & RC98 close to PCH

RC97 1
@ RC98 1

CH1241
0.1U_0402_10V7K

40

+VCC_CORE
HSW_ULT_DDR3L

UCPU1L

+1.05VS_VCCST

2

2

1

2

2

1

CC165
10U_0603_6.3V6M

2

1

CC164
10U_0603_6.3V6M

2

1

CC163
10U_0603_6.3V6M

1

CC162
10U_0603_6.3V6M

CC161
10U_0603_6.3V6M

2

CC160
10U_0603_6.3V6M

1

Friday, April 19, 2013

Sheet
1

10

of

45

5

4

3

2

1

closed MCP 1000 mils
@ T293

CFG3
HSW_ULT_DDR3L

UCPU1S

D

1K_0402_5%

2

1 RC81

CFG4

eDP Strap

1 : Disabled; No Physical Display Port
attached to Embedded Display Port
CFG4

* 0 : Enabled; An external Display
Port device is connected to the
Embedded Display Port

18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

18
18
18
18

CFG16
CFG18
CFG17
CFG19

AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60

CFG3
CFG4

AA62
U63
AA61
U62
CFG_RCOMP

V63
A5

49.9_0402_1%

2

1

RC153

CFG_RCOMP

49.9_0402_1%

2

1

RC154

PROC_OPI_COMP

2

1 RC155

8.2K_0402_1%

TD_IREF

TD_IREF

Width = 15 mil, Spacing = 15 mil
Close PCH within 500 mil

E1
D1
J20
H18
B12

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

RSVD_TP
RSVD_TP

AV63
AU63
D

RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RESERVED

RSVD
RSVD
RSVD
PROC_OPI_RCOMP

CFG16
CFG18
CFG17
CFG19

RSVD
RSVD

CFG_RCOMP

VSS
VSS

RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
TD_IREF

C63
C62
B43
A51
B51
L60
N60
W23
Y22
AY15

PROC_OPI_COMP

AV62
D58
P22
N21
P20
R20

19 OF 19

@

C

C

UCPU1N

HSW_ULT_DDR3L

UCPU1O

HSW_ULT_DDR3L

UCPU1P

A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29

B

A

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20

AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

15 OF 19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31

D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

HSW_ULT_DDR3L

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
VSS
16 OF 19

H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63

B

V58
AH46
V23
E62
AH16

RC99 & RC100 close to PCH
VSSSENSE_R

@ RC99
RC100

1
1

2 0_0402_5%
2 100_0402_1%

VSSSENSE

40

@

A

@
14 OF 19
@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P11-MCP(7/7) PWR,VSS,CFG
Size

5

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

Friday, April 19, 2013

Sheet
1

11

of

45

5

4

3

2

1

follow INTEL PDG
CD1

2

1 .047U_0402_16V7K

CD2

2

1 .047U_0402_16V7K

CD3

1

2 .047U_0402_16V7K

CD4

1

2 .047U_0402_16V7K

+VREFCA

+VREFDQ_A

D

D

PLACE THESE CAPS
NEAR TO RESPECTIVE DIMM PINS

UD1 @

M8
H1

+VREFCA
+VREFDQ_A
6,13

DDR_A_DQS#[0..7]

6,13

DDR_A_DQS[0..7]

6,13

DDR_A_D[0..63]

6,13,16

DDR_A_MA[0..15]

All VREF traces should
have 10 mil trace width

C

6,13,16
6,13,16
6,13,16

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

6,13,16
6,13,16

M_CLK_A_DDR0
M_CLK_A_DDR#0

6,13,16
6,13,16
13,16

DDR_A_CKE0
DDR_A_CKE1
M_ODT0

6,13,16
6,13,16

DDR_A_CS0#
DDR_A_CS1#

6,13,16
6,13,16
6,13,16

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

M2
N8
M3

M_CLK_A_DDR0
M_CLK_A_DDR#0

J7
K7

DDR_A_CKE0
DDR_A_CKE1
M_ODT0
DDR_A_CS0#
DDR_A_CS1#

K9
J9
K1
J1
L2
L1

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

J3
K3
L3

DDR_A_DQS0
DDR_A_DQS1

F3
C7

DDR_A_DQS#0
DDR_A_DQS#1

G3
B7

1

CKE0
CKE1/NC
ODT0
ODT1/NC
CS0#
CS1#/NC

DQSL#
DQSU#

2

1 240_0402_1%

L8

RD79 2

1 240_0402_1%

L9

RD1

DML
DMU

RESET#

ZQ1/NC

@

DDR_A_D13
DDR_A_D15
DDR_A_D12
DDR_A_D14
DDR_A_D8
DDR_A_D11
DDR_A_D9
DDR_A_D10

+1.35V_DDR

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

M2
N8
M3

M_CLK_A_DDR0
M_CLK_A_DDR#0

J7
K7

DDR_A_CKE0
DDR_A_CKE1
M_ODT0
DDR_A_CS0#
DDR_A_CS1#

K9
J9
K1
J1
L2
L1

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

J3
K3
L3

DDR_A_DQS2
DDR_A_DQS3

F3
C7

DDR_A_DQS#2
DDR_A_DQS#3

G3
B7

2

1 240_0402_1%

L8

RD80 2

1 240_0402_1%

L9

RD2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15/NC

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK#
CKE0
CKE1/NC
ODT0
ODT1/NC
CS0#
CS1#/NC

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

RAS#
CAS#
WE#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU
DQSL#
DQSU#
DML
DMU

T2

DDR3_DRAMRST#

96-BALL
SDRAM DDR3L
MT41K256M16HA-125M:E_FBGA96

CAD NOTE:
PLACE THE CAP NEAR TO
SDRAM RESET PIN

VREFCA
VREFDQ

E7
D3

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

ZQ0

D7
C3
C8
C2
A7
A2
B8
A3

M8
H1

+VREFCA
+VREFDQ_A

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

DDR_A_D6
DDR_A_D0
DDR_A_D2
DDR_A_D5
DDR_A_D3
DDR_A_D4
DDR_A_D7
DDR_A_D1

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

RAS#
CAS#
WE#

E3
F7
F2
F8
H3
H8
G2
H7

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK#

CD5

2 0.1U_0402_25V6

B

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

T2

DDR3_DRAMRST#

DDR3_DRAMRST#

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15/NC

E7
D3

5,13,14,15

UD2 @

VREFCA
VREFDQ

RESET#

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

ZQ0
ZQ1/NC

E3
F7
F2
F8
H3
H8
G2
H7

DDR_A_D18
DDR_A_D16
DDR_A_D22
DDR_A_D21
DDR_A_D19
DDR_A_D20
DDR_A_D23
DDR_A_D17

D7
C3
C8
C2
A7
A2
B8
A3

DDR_A_D29
DDR_A_D27
DDR_A_D28
DDR_A_D26
DDR_A_D24
DDR_A_D31
DDR_A_D25
DDR_A_D30

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.35V_DDR

C

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9

B

96-BALL
SDRAM DDR3L
MT41K256M16HA-125M:E_FBGA96

1
2

1
2

1
2

2

Memory Channel A SPD EEPROM
CD114

CD113

10U_0603_6.3V6M

2

CD112

1

10U_0603_6.3V6M

2

CD111

1

1U_0402_6.3V6K

CD21

1U_0402_6.3V6K

CD20

10U_0603_6.3V6M

2

CD19

1

10U_0603_6.3V6M

2

CD18

1

1U_0402_6.3V6K

2

CD17

1

1U_0402_6.3V6K

2

CD16

1

1U_0402_6.3V6K

2

CD15

1

1U_0402_6.3V6K

CD14

2

1U_0402_6.3V6K

1U_0402_6.3V6K

A

1

1

+1.35V_DDR

1
+

@
CD22
330U_B2_2VM_R15M

+3VS
+3VS

UD3 @

2
7,14,18,19
7,14,18,19

PCH_SMBCLK
PCH_SMBDATA

8
7
6
5

VCC
WP
SCL
SDA

A0
A1
A2
GND

1
2
3
4

@ RD3
@ RD4

2
2

1 1K_0402_5%
1 1K_0402_5%

1

2

AT24C02C-XHM-T_TSSOP8

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P12-DDRIII Channel_A Lower
Size

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

5

A

@
CD23
0.1U_0402_10V7K

Friday, April 19, 2013

Sheet
1

12

of

45

5

4

3

2

1

follow INTEL PDG

D

CD24 2

1 .047U_0402_16V7K

CD25 2

1 .047U_0402_16V7K

CD26 1

2 .047U_0402_16V7K

CD27 1

2 .047U_0402_16V7K

+VREFCA

D

+VREFDQ_A

PLACE THESE CAPS
NEAR TO RESPECTIVE DIMM PINS

UD4 @

M8
H1

+VREFCA
+VREFDQ_A

6,12

DDR_A_DQS#[0..7]

6,12

DDR_A_DQS[0..7]

6,12

DDR_A_D[0..63]

6,12,16

DDR_A_MA[0..15]

All VREF traces should
have 10 mil trace width
6,12,16
6,12,16
6,12,16

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

6,12,16
6,12,16

M_CLK_A_DDR0
M_CLK_A_DDR#0

6,12,16
6,12,16
12,16

DDR_A_CKE0
DDR_A_CKE1
M_ODT0

6,12,16
6,12,16

DDR_A_CS0#
DDR_A_CS1#

6,12,16
6,12,16
6,12,16

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

M2
N8
M3

M_CLK_A_DDR0
M_CLK_A_DDR#0

J7
K7

DDR_A_CKE0
DDR_A_CKE1
M_ODT0
DDR_A_CS0#
DDR_A_CS1#

K9
J9
K1
J1
L2
L1

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

J3
K3
L3

UD5 @

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15/NC

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK#

C

DDR_A_DQS4
DDR_A_DQS5

F3
C7

DDR_A_DQS#4
DDR_A_DQS#5

G3
B7
E7
D3

5,12,14,15

1

2

B

T2

DDR3_DRAMRST#

DDR3_DRAMRST#

2

1 240_0402_1%

L8

RD81 2

1 240_0402_1%

L9

RD5

@
CD28
0.1U_0402_25V6

CKE0
CKE1/NC
ODT0
ODT1/NC
CS0#
CS1#/NC

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

RAS#
CAS#
WE#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU
DQSL#
DQSU#
DML
DMU

RESET#

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

ZQ0
ZQ1/NC

E3
F7
F2
F8
H3
H8
G2
H7

DDR_A_D39
DDR_A_D37
DDR_A_D34
DDR_A_D32
DDR_A_D35
DDR_A_D33
DDR_A_D38
DDR_A_D36

D7
C3
C8
C2
A7
A2
B8
A3

DDR_A_D44
DDR_A_D47
DDR_A_D45
DDR_A_D46
DDR_A_D41
DDR_A_D42
DDR_A_D40
DDR_A_D43

B2
D9
G7
K2
K8
N1
N9
R1
R9

M8
H1

+VREFCA
+VREFDQ_A

+1.35V_DDR

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

M2
N8
M3

M_CLK_A_DDR0
M_CLK_A_DDR#0

J7
K7

DDR_A_CKE0
DDR_A_CKE1
M_ODT0
DDR_A_CS0#
DDR_A_CS1#

K9
J9
K1
J1
L2
L1

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

J3
K3
L3

DDR_A_DQS6
DDR_A_DQS7

F3
C7

DDR_A_DQS#6
DDR_A_DQS#7

G3
B7
E7
D3

B1
B9
D1
D8
E2
E8
F9
G1
G9

DDR3_DRAMRST#

2

1 240_0402_1%

L8

RD82 2

1 240_0402_1%

L9

RD6

96-BALL
SDRAM DDR3L
MT41K256M16HA-125M:E_FBGA96

CAD NOTE:
PLACE THE CAP NEAR TO
SDRAM RESET PIN

T2

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15/NC

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK#
CKE0
CKE1/NC
ODT0
ODT1/NC
CS0#
CS1#/NC

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

RAS#
CAS#
WE#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU
DQSL#
DQSU#
DML
DMU

RESET#

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

ZQ0
ZQ1/NC

E3
F7
F2
F8
H3
H8
G2
H7

DDR_A_D55
DDR_A_D53
DDR_A_D54
DDR_A_D51
DDR_A_D49
DDR_A_D52
DDR_A_D48
DDR_A_D50

D7
C3
C8
C2
A7
A2
B8
A3

DDR_A_D62
DDR_A_D57
DDR_A_D63
DDR_A_D56
DDR_A_D59
DDR_A_D61
DDR_A_D58
DDR_A_D60

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.35V_DDR

C

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9

96-BALL
SDRAM DDR3L
MT41K256M16HA-125M:E_FBGA96

B

1
2

1
2

1
2

2

CD118

CD117

10U_0603_6.3V6M

2

CD116

1

10U_0603_6.3V6M

2

CD115

1

1U_0402_6.3V6K

CD44

1U_0402_6.3V6K

CD43

10U_0603_6.3V6M

2

CD42

1

10U_0603_6.3V6M

2

CD41

1

1U_0402_6.3V6K

2

CD40

1

1U_0402_6.3V6K

2

CD39

1

1U_0402_6.3V6K

2

CD38

1

1U_0402_6.3V6K

CD37

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

+1.35V_DDR

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P13-DDRIII Channel_A Upper
Size

5

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

Friday, April 19, 2013

Sheet
1

13

of

45

5

4

3

2

1

follow INTEL PDG

D

CD45 2

1 .047U_0402_16V7K

CD46 2

1 .047U_0402_16V7K

CD47 1

2 .047U_0402_16V7K

CD48 1

2 .047U_0402_16V7K

+VREFCA

D

+VREFDQ_B
UD6 @

PLACE THESE CAPS
NEAR TO RESPECTIVE DIMM PINS

6,15

DDR_B_DQS#[0..7]

6,15

DDR_B_DQS[0..7]

6,15

DDR_B_D[0..63]

6,15,16

M8
H1

+VREFCA
+VREFDQ_B

DDR_B_MA[0..15]

All VREF traces should
have 10 mil trace width

C

6,15,16
6,15,16
6,15,16

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

6,15,16
6,15,16

M_CLK_B_DDR0
M_CLK_B_DDR#0

6,15,16
6,15,16
15,16

DDR_B_CKE0
DDR_B_CKE1
M_ODT2

6,15,16
6,15,16

DDR_B_CS0#
DDR_B_CS1#

6,15,16
6,15,16
6,15,16

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

M2
N8
M3

M_CLK_B_DDR0
M_CLK_B_DDR#0

J7
K7

DDR_B_CKE0
DDR_B_CKE1
M_ODT2
DDR_B_CS0#
DDR_B_CS1#

K9
J9
K1
J1
L2
L1

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

J3
K3
L3

DDR_B_DQS2
DDR_B_DQS3

F3
C7

DDR_B_DQS#2
DDR_B_DQS#3

G3
B7
E7
D3

5,12,13,15

T2

DDR3_DRAMRST#

DDR3_DRAMRST#

1

2

1 240_0402_1%

L8

RD83 2

1 240_0402_1%

L9

RD7
CD49

2

0.1U_0402_25V6

UD7 @

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15/NC

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK#
CKE0
CKE1/NC
ODT0
ODT1/NC
CS0#
CS1#/NC

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

RAS#
CAS#
WE#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU
DQSL#
DQSU#
DML
DMU

RESET#

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

ZQ0
ZQ1/NC

@

DDR_B_D22
DDR_B_D21
DDR_B_D18
DDR_B_D17
DDR_B_D23
DDR_B_D16
DDR_B_D19
DDR_B_D20

D7
C3
C8
C2
A7
A2
B8
A3

DDR_B_D30
DDR_B_D26
DDR_B_D29
DDR_B_D27
DDR_B_D25
DDR_B_D28
DDR_B_D24
DDR_B_D31

B2
D9
G7
K2
K8
N1
N9
R1
R9

M8
H1

+VREFCA
+VREFDQ_B

+1.35V_DDR

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

M2
N8
M3

M_CLK_B_DDR0
M_CLK_B_DDR#0

J7
K7

DDR_B_CKE0
DDR_B_CKE1
M_ODT2
DDR_B_CS0#
DDR_B_CS1#

K9
J9
K1
J1
L2
L1

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

J3
K3
L3

DDR_B_DQS0
DDR_B_DQS1

F3
C7

DDR_B_DQS#0
DDR_B_DQS#1

G3
B7
E7
D3

B1
B9
D1
D8
E2
E8
F9
G1
G9

T2

DDR3_DRAMRST#

2

1 240_0402_1%

L8

RD84 2

1 240_0402_1%

L9

RD8

96-BALL
SDRAM DDR3L
MT41K256M16HA-125M:E_FBGA96

CAD NOTE:
PLACE THE CAP NEAR TO
SDRAM RESET PIN

B

E3
F7
F2
F8
H3
H8
G2
H7

VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15/NC
BA0
BA1
BA2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK#
CKE0
CKE1/NC
ODT0
ODT1/NC
CS0#
CS1#/NC
RAS#
CAS#
WE#
DQSL
DQSU
DQSL#
DQSU#
DML
DMU

RESET#

ZQ0
ZQ1/NC

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

E3
F7
F2
F8
H3
H8
G2
H7

DDR_B_D7
DDR_B_D1
DDR_B_D3
DDR_B_D5
DDR_B_D6
DDR_B_D4
DDR_B_D2
DDR_B_D0

D7
C3
C8
C2
A7
A2
B8
A3

DDR_B_D8
DDR_B_D12
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D10
DDR_B_D9
DDR_B_D11

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.35V_DDR

A1
A8
C1
C9
D2
E9
F1
H2
H9

C

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9

96-BALL
SDRAM DDR3L
MT41K256M16HA-125M:E_FBGA96
B

1
2

1
2

1
2

2

Memory Channel B SPD EEPROM
1
CD122

CD121

10U_0603_6.3V6M

2

CD120

1

10U_0603_6.3V6M

2

CD119

1

1U_0402_6.3V6K

CD65

1U_0402_6.3V6K

CD64

10U_0603_6.3V6M

2

CD63

1

10U_0603_6.3V6M

2

CD62

1

1U_0402_6.3V6K

2

CD61

1

1U_0402_6.3V6K

2

CD60

1

1U_0402_6.3V6K

2

CD59

1

1U_0402_6.3V6K

CD58

2

1U_0402_6.3V6K

1U_0402_6.3V6K

A

1

1

+1.35V_DDR

+

@
CD66
330U_B2_2VM_R15M

+3VS

+3VS
+3VS

UD8 @

2
7,12,18,19
7,12,18,19

PCH_SMBCLK
PCH_SMBDATA

8
7
6
5

VCC
WP
SCL
SDA

A0
A1
A2
GND

1
2
3
4

@ RD9 2
@ RD10 2

1 1K_0402_5%
1 1K_0402_5%

1

2

AT24C02C-XHM-T_TSSOP8

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P14-DDRIII Channel_B Lower
Size

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

5

A

@
CD67
0.1U_0402_10V7K

Friday, April 19, 2013

Sheet
1

14

of

45

5

4

3

2

1

follow INTEL PDG

D

CD68 2

1 .047U_0402_16V7K

CD69 2

1 .047U_0402_16V7K

CD70 1

2 .047U_0402_16V7K

CD71 1

2 .047U_0402_16V7K

+VREFCA

D

+VREFDQ_B

PLACE THESE CAPS
NEAR TO RESPECTIVE DIMM PINS

UD9 @

M8
H1

+VREFCA
+VREFDQ_B

6,14

DDR_B_DQS#[0..7]

6,14

DDR_B_DQS[0..7]

6,14

DDR_B_D[0..63]

6,14,16

DDR_B_MA[0..15]

All VREF traces should
have 10 mil trace width

6,14,16
6,14,16
6,14,16

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

6,14,16
6,14,16

M_CLK_B_DDR0
M_CLK_B_DDR#0

6,14,16
6,14,16
14,16

DDR_B_CKE0
DDR_B_CKE1
M_ODT2

6,14,16
6,14,16

DDR_B_CS0#
DDR_B_CS1#

6,14,16
6,14,16
6,14,16

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

M2
N8
M3

M_CLK_B_DDR0
M_CLK_B_DDR#0

J7
K7

DDR_B_CKE0
DDR_B_CKE1
M_ODT2
DDR_B_CS0#
DDR_B_CS1#

K9
J9
K1
J1
L2
L1

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

J3
K3
L3

UD10

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15/NC

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK#

C

DDR_B_DQS4
DDR_B_DQS5

F3
C7

DDR_B_DQS#4
DDR_B_DQS#5

G3
B7
E7
D3

5,12,13,14

1

2

B

T2

DDR3_DRAMRST#

DDR3_DRAMRST#

@
CD72
0.1U_0402_25V6

RD11 2

1 240_0402_1%

L8

RD85 2

1 240_0402_1%

L9

CKE0
CKE1/NC
ODT0
ODT1/NC
CS0#
CS1#/NC

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

RAS#
CAS#
WE#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU
DQSL#
DQSU#
DML
DMU

RESET#

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

ZQ0
ZQ1/NC

E3
F7
F2
F8
H3
H8
G2
H7

DDR_B_D39
DDR_B_D33
DDR_B_D38
DDR_B_D37
DDR_B_D34
DDR_B_D32
DDR_B_D35
DDR_B_D36

D7
C3
C8
C2
A7
A2
B8
A3

DDR_B_D45
DDR_B_D47
DDR_B_D44
DDR_B_D42
DDR_B_D40
DDR_B_D46
DDR_B_D41
DDR_B_D43

B2
D9
G7
K2
K8
N1
N9
R1
R9

M8
H1

+VREFCA
+VREFDQ_B

+1.35V_DDR

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

M2
N8
M3

M_CLK_B_DDR0
M_CLK_B_DDR#0

J7
K7

DDR_B_CKE0
DDR_B_CKE1
M_ODT2
DDR_B_CS0#
DDR_B_CS1#

K9
J9
K1
J1
L2
L1

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

J3
K3
L3

DDR_B_DQS6
DDR_B_DQS7

F3
C7

DDR_B_DQS#6
DDR_B_DQS#7

G3
B7
E7
D3

B1
B9
D1
D8
E2
E8
F9
G1
G9

DDR3_DRAMRST#

RD12 2

1 240_0402_1%

L8

RD86 2

1 240_0402_1%

L9

96-BALL
SDRAM DDR3L
MT41K256M16HA-125M:E_FBGA96

CAD NOTE:
PLACE THE CAP NEAR TO
SDRAM RESET PIN

T2

@

VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15/NC
BA0
BA1
BA2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK#
CKE0
CKE1/NC
ODT0
ODT1/NC
CS0#
CS1#/NC
RAS#
CAS#
WE#

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU
DQSL#
DQSU#
DML
DMU

RESET#

ZQ0
ZQ1/NC

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

E3
F7
F2
F8
H3
H8
G2
H7

DDR_B_D48
DDR_B_D52
DDR_B_D50
DDR_B_D55
DDR_B_D53
DDR_B_D51
DDR_B_D54
DDR_B_D49

D7
C3
C8
C2
A7
A2
B8
A3

DDR_B_D60
DDR_B_D62
DDR_B_D61
DDR_B_D63
DDR_B_D57
DDR_B_D58
DDR_B_D56
DDR_B_D59

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.35V_DDR

C

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9

96-BALL
SDRAM DDR3L
MT41K256M16HA-125M:E_FBGA96

B

1
2

1
2

1
2

2

CD126

CD125

10U_0603_6.3V6M

2

CD124

1

10U_0603_6.3V6M

2

CD123

1

1U_0402_6.3V6K

CD88

1U_0402_6.3V6K

CD87

10U_0603_6.3V6M

2

CD86

1

10U_0603_6.3V6M

2

CD85

1

1U_0402_6.3V6K

2

CD84

1

1U_0402_6.3V6K

2

CD83

1

1U_0402_6.3V6K

2

CD82

1

1U_0402_6.3V6K

A

CD81

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

+1.35V_DDR

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P15-DDRIII Channel_B Upper
Size

5

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

Friday, April 19, 2013

Sheet
1

15

of

45

5

4

3

2

1

+1.35V_DDR

1

M3

M1

+VREFCA

2

.1U_0402_16V7K

RD13
1.8K_0402_1%
RD14

D

1

V_DDR_REF_CA

1

2

+VREFCA

2.7_0402_1%

2
1

RD15
1.8K_0402_1%

2

2

RD16
24.9_0402_1%

All VREF traces should
have 10 mil trace width

D

2

1

CD89
0.022U_0402_16V7K

1
CD90

6

+1.35V_DDR

M3

RD19

RD20
+VREFDQ_A

6

1

V_DDR_REFB_R

CD91
0.022U_0402_16V7K

2

CD92
0.022U_0402_16V7K

1

RD22
1.8K_0402_1%

1

RD24
24.9_0402_1%

C

2

2

RD23
24.9_0402_1%

+VREFDQ_B

2

RD21
1.8K_0402_1%

C

2

4.99_0402_1%

1

1

2

4.99_0402_1%

1

2

1

V_DDR_REFA_R

1

6

M1

2

RD18
1.8K_0402_1%

2

RD17
1.8K_0402_1%

+1.35V_DDR

M1

1

1

M3

2

+0.675VS

6,12,13

DDR_A_MA[0..15]

6,14,15

DDR_B_MA[0..15]

+0.675VS

2

2

CD101

1

CD98

2

10U_0603_6.3V6M

1

CD97

2

1U_0402_6.3V6K

1

CD96

2

1U_0402_6.3V6K

1

CD95

2

1U_0402_6.3V6K

CD94

1

1U_0402_6.3V6K

2

1U_0402_6.3V6K

CD93

1U_0402_6.3V6K

1

1

B

+0.675VS

DDR_A_MA12
DDR_A_MA15
DDR_A_MA0
DDR_A_MA10

RD25
RD27
RD29
RD31

1
1
1
1

2
2
2
2

34.8_0402_1%
34.8_0402_1%
34.8_0402_1%
34.8_0402_1%

DDR_B_MA12
DDR_B_MA15
DDR_B_MA0
DDR_B_MA10

RD26
RD28
RD30
RD32

1
1
1
1

2
2
2
2

34.8_0402_1%
34.8_0402_1%
34.8_0402_1%
34.8_0402_1%

DDR_A_MA4
DDR_A_MA2
DDR_A_MA1
DDR_A_MA6

RD33
RD35
RD37
RD39

1
1
1
1

2
2
2
2

34.8_0402_1%
34.8_0402_1%
34.8_0402_1%
34.8_0402_1%

DDR_B_MA14
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2

RD34
RD36
RD38
RD40

1
1
1
1

2
2
2
2

34.8_0402_1%
34.8_0402_1%
34.8_0402_1%
34.8_0402_1%

DDR_A_MA3
DDR_A_MA9
DDR_A_MA11
DDR_A_MA5

RD41
RD43
RD45
RD47

1
1
1
1

2
2
2
2

34.8_0402_1%
34.8_0402_1%
34.8_0402_1%
34.8_0402_1%

DDR_B_MA8
DDR_B_MA1
DDR_B_MA13
DDR_B_MA7

RD42
RD44
RD46
RD48

1
1
1
1

2
2
2
2

34.8_0402_1%
34.8_0402_1%
34.8_0402_1%
34.8_0402_1%

DDR_A_MA14
DDR_A_MA7
DDR_A_MA8
DDR_A_MA13

RD49
RD51
RD53
RD55

1
1
1
1

2
2
2
2

34.8_0402_1%
34.8_0402_1%
34.8_0402_1%
34.8_0402_1%

DDR_B_MA3
DDR_B_MA9
DDR_B_MA11
DDR_B_MA5

RD50
RD52
RD54
RD56

1
1
1
1

2
2
2
2

34.8_0402_1%
34.8_0402_1%
34.8_0402_1%
34.8_0402_1%

6,12,13
6,12,13
6,12,13
6,12,13

DDR_A_CKE0
DDR_A_RAS#
DDR_A_CS0#
DDR_A_CAS#

RD57
RD59
RD61
RD63

1
1
1
1

2
2
2
2

34.8_0402_1%
34.8_0402_1%
34.8_0402_1%
34.8_0402_1%

6,14,15
6,14,15
6,14,15
6,14,15

DDR_B_CKE0
DDR_B_CS0#
DDR_B_CAS#
DDR_B_RAS#

RD58
RD60
RD62
RD64

1
1
1
1

2
2
2
2

34.8_0402_1%
34.8_0402_1%
34.8_0402_1%
34.8_0402_1%

6,12,13
6,12,13
6,12,13
6,12,13

DDR_A_WE#
DDR_A_BS0
DDR_A_BS2
DDR_A_BS1

RD65
RD67
RD69
RD71

1
1
1
1

2
2
2
2

34.8_0402_1%
34.8_0402_1%
34.8_0402_1%
34.8_0402_1%

6,14,15
6,14,15
6,14,15
6,14,15

DDR_B_BS1
DDR_B_BS2
DDR_B_BS0
DDR_B_WE#

RD66
RD68
RD70
RD72

1
1
1
1

2
2
2
2

34.8_0402_1%
34.8_0402_1%
34.8_0402_1%
34.8_0402_1%

6,12,13
6,12,13

DDR_A_CKE1
DDR_A_CS1#

RD87
RD88

1
1

2 34.8_0402_1%
2 34.8_0402_1%

6,14,15
6,14,15

DDR_B_CKE1
DDR_B_CS1#

RD89
RD90

1
1

2 34.8_0402_1%
2 34.8_0402_1%

M_ODT0

RD73

1

2 30_0402_1%

2 26.1_0402_1%

6,14,15

2 26.1_0402_1%

6,14,15

B

+1.35V_DDR

2

CD110

2

CD107

1

10U_0603_6.3V6M

2

CD106

1

1U_0402_6.3V6K

2

CD105

1

1U_0402_6.3V6K

2

CD104

1

1U_0402_6.3V6K

2

CD103

1

1U_0402_6.3V6K

CD102

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

+0.675VS

12,13

+1.35V_DDR

14,15

RD74

1

2 30_0402_1%

M_CLK_B_DDR0

RD76

1

2 26.1_0402_1%

M_CLK_B_DDR#0

RD78

1

2 26.1_0402_1%

M_ODT2

+0.675VS

A

6,12,13

M_CLK_A_DDR0

RD75

1

6,12,13

M_CLK_A_DDR#0

RD77

1

2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P16-DDRIII Vref & Termination
Size

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

5

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

+0.675VS

Friday, April 19, 2013

Sheet
1

16

of

45

5

4

UCPU1

CPU_1.7G_GT3@

UCPU1

CPU_1.8G_GT2@

3

UCPU1

CPU_1.6G_GT2@

UCPU1

2

1

CPU_1.7G_GT2@

SA00006SS1L

SA00006SL1L

SA00006SM2L

SA00006SX1L

I7-4650U

I7-4500U

I5-4200U

I3-4010U

D

D

MEM_CONFIG2
UD1

Micron_4G@

SA00005TH0L

X768G

X7641131L61

Micron_4G@

Micron_4G@

Micron_4G@

Micron_4G@

Micron_4G@

UD9

UD10 Micron_4G@

MEM_CONFIG1
RH315

Micron_4G@

MEM_CONFIG0
RH316

Micron_4G@

SD028100280

SD028100280

SD028100280

MT41K256M16HA-125M:E

MT41K256M16HA-125M:E

10K_0402_5%

10K_0402_5%

10K_0402_5%

UD1

UD2

UD4

UD5

UD6

UD7

UD9

UD10 Micron_8G@

RH314

RH315

RH303

SD028100280

SD028100280

SD028100280

MT41K512M16TNA-125M:E

MT41K512M16TNA-125M:E

MT41K512M16TNA-125M:E

MT41K512M16TNA-125M:E

10K_0402_5%

10K_0402_5%

10K_0402_5%

X764G

UD1

UD2

UD4

UD5

UD6

UD7

UD9

UD10 Hynix_4G@

RH314

RH180

RH316

SA00006JF0L

X76_4G@

SD028100280

SD028100280

SD028100280

H5TC4G63AFR-PBR

H5TC4G63AFR-PBR

10K_0402_5%

10K_0402_5%

10K_0402_5%

UD1

UD2

UD4

UD5

UD6

UD7

UD9

UD10 Hynix_8G@

RH314

RH180

RH303

SD028100280

SD028100280

SD028100280

H5TC8G63AMR-PBR

H5TC8G63AMR-PBR

H5TC8G63AMR-PBR

H5TC8G63AMR-PBR

10K_0402_5%

10K_0402_5%

10K_0402_5%

UD1

UD2

UD4

UD5

UD6

UD7

UD9

UD10 Samsung_4G@

RH271

RH315

RH316

SA00006J30L

SD028100280

SD028100280

SD028100280

K4B4G1646B-HKK0

K4B4G1646B-HKK0

10K_0402_5%

10K_0402_5%

10K_0402_5%

UD1

UD2

UD4

UD5

UD6

UD7

UD9

UD10 Samsung_8G@

RH271

RH315

RH303

SA00006J80L

SA00006J80L

K4B8G1646B-MKK0

SA00006J80L

K4B8G1646B-MKK0

SA00006J80L

K4B8G1646B-MKK0

SA00006J80L

K4B8G1646B-MKK0

Samsung_8G@

SA00006J80L

Samsung_8G@

SA00006J80L

K4B8G1646B-MKK0

K4B8G1646B-MKK0

SA00006J30L

Samsung_4G@

K4B4G1646B-HKK0

K4B8G1646B-MKK0

SA00006J30L

Samsung_4G@

K4B4G1646B-HKK0

Samsung_8G@

SA00006J30L

Samsung_4G@

K4B4G1646B-HKK0

Samsung_8G@

SA00006J30L

Samsung_4G@

K4B4G1646B-HKK0

Samsung_8G@

SA00006J30L

Samsung_4G@

SA00006Q90L

K4B4G1646B-HKK0

Samsung_8G@

SA00006J30L

SA00006Q90L

K4B4G1646B-HKK0

Samsung_8G@

SA00006J30L

Samsung_4G@

SA00006Q90L

SA00006J80L

K4B8G1646B-MKK0

Samsung_8G@

Samsung_8G@

C

Hynix_8G@

H5TC8G63AMR-PBR

Samsung_4G@

SA00006Q90L

Hynix_8G@

H5TC8G63AMR-PBR

Samsung_4G@

SA00006Q90L

Hynix_8G@

H5TC8G63AMR-PBR

Samsung_4G@

SA00006Q90L

Hynix_8G@

H5TC8G63AMR-PBR

Samsung_4G@

SA00006Q90L

Hynix_8G@

SA00006JF0L

Hynix_4G@

H5TC4G63AFR-PBR

SA00006Q90L

SA00006JF0L

Hynix_4G@

H5TC4G63AFR-PBR

Hynix_8G@

SA00006JF0L

Hynix_4G@

H5TC4G63AFR-PBR

Hynix_8G@

SA00006JF0L

Hynix_4G@

H5TC4G63AFR-PBR

Hynix_8G@

SA00006JF0L

Hynix_4G@

SA00006FB0L

H5TC4G63AFR-PBR

Hynix_8G@

SA00006JF0L

SA00006FB0L

H5TC4G63AFR-PBR

Hynix_8G@

SA00006JF0L

Hynix_4G@

SA00006FB0L

Micron_8G@

MT41K512M16TNA-125M:E

Hynix_4G@

SA00006FB0L

Micron_8G@

MT41K512M16TNA-125M:E

Hynix_4G@

SA00006FB0L

Micron_8G@

MT41K512M16TNA-125M:E

Hynix_4G@

SA00006FB0L

Micron_8G@

MT41K512M16TNA-125M:E

Hynix_4G@

SA00006FB0L

Micron_8G@

SA00005TH0L

Micron_4G@

MT41K256M16HA-125M:E

SA00006FB0L

SA00005TH0L

RH314

MT41K256M16HA-125M:E

Micron_8G@

SA00005TH0L

Micron_4G@

MT41K256M16HA-125M:E

Micron_8G@

SA00005TH0L

UD7

MT41K256M16HA-125M:E

Micron_8G@

SA00005TH0L

UD6

MT41K256M16HA-125M:E

Micron_8G@

SA00005TH0L

UD5

MT41K256M16HA-125M:E

Micron_8G@

SA00005TH0L

UD4

X76_8G@

X7641131L57
C

UD2

Samsung_8G@

SD028100280

SD028100280

SD028100280

10K_0402_5%

10K_0402_5%

10K_0402_5%

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P17-BOM
Size

5

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

Friday, April 19, 2013

Sheet
1

17

of

45

5

4

3

2

1

U663 200ps of XDP
+3V_PCH
U663@

2

CPU_PATH_EN_G
5

CPU_XDP_TRST#

3

CPU_XDP_TRST#

5

D

5

CPU_XDP_TDO

5

CPU_XDP_TDI

6
12

03-0320

11
15

5

14

CPU_XDP_TMS

1OE

VCC

1A

1B

4

1

XDP_TRST#

2OE

2

2A

2B

7

XDP_TDO

10

XDP_TDI_SWITCH

13

XDP_TMS

@
CH1236
0.1U_0402_25V6K

D

3OE
3A

3B

4OE
4A

4B
NC

8

16

GND

NC

1
9

74CBTLV3126DS_SSOP16
+3V_PCH

@
U697

5
@ R1324

1

2 10K_0402_5%

@ R1325

1

2 10K_0402_5%

CPU_PATH_EN

P

1

1.05VS_PG

IN1

4

O

2

CPU_PATH_EN_G

IN2

G

8,29,30

3

+3V_PCH

SN74AHC1G08DCKR_SC70-5

7

RS5

@ RH446

1

2 0_0402_5% XDP_TCK0

@ RH370

1

2 0_0402_5% CPU_XDP_TRST#

PCH_JTAG_TDI

@ RH371

1

2 0_0402_5% XDP_TDI

PCH_JTAG_TMS

@ RH372

1

2 0_0402_5% XDP_TMS

J1D

@ RH373

1

2 0_0402_5% XDP_TCK1

Stuffed : Dual TCK

J1S

@ RH411

1

2 0_0402_5% XDP_TCK0

Stuffed : Singel TCK

J2D

@ RH374

1

2 0_0402_5% XDP_TCK0

J2S

@ RH412

1

2 0_0402_5% XDP_TDO

J3D

@ RH369

1

2 0_0402_5% XDP_TDO

J3S

@ RH413

1

2 0_0402_5% XDP_TDI_SWITCH

J4D

@ RH414

1

2 0_0402_5% XDP_TDI_SWITCH

5
7

CPU_XDP_TCK

CPU_XDP_TCK

PCH_JTAG_TRST#

C

C

Topolog

Description

Be st Use for

Default Setting: Dual
TCK S can Chains
(also known as
"Shared JTAG" in
other docum ent)

In this topology, the
CPU JTAG chain will be
controlled by TCK0 and
TCK1 will control
the PCH JTAG chain.

- Run control oper.
- ME/Sx debug

Resistors
Stuffed

Resistors
ufStuffed

R1, R2,
J1d, J2d,
J3d, J4d,
R3, R4, R5

J1s, J2s,
J3s

7

7

PCH_JTAG_TCK

J1D, J1S
<200ps of the XDP
Stub<200ps
7

Single TCK scan chain
(also known as "Com m on
JTAG" in other docum
ent)

In th is topolog y, PCH
TDI- TDO and CPU TDI-TDO
will be chained to form
one JTAG scan chain
controlled by TCK0

-B oundary Scan/
Manufacturing est

J1s , J2s ,
J3s ,
R2, R3, R4,
R5

PCH_JTAG_JTAGX

J2D, J2S
<200ps of the XDP
Stub <200ps

R1, J1d, J2d,
J3d , J4d

7

PCH_JTAG_TDO

PCH_JTAG_TDO

J3D, J3S, R3
<200ps of the XDP
Stub <200ps
+1.05VA

B

1
2
3
4
5
6
7
8
9
10
11
12

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PLT_RST#
CLK_LPC_DEBUG
+3VS

30
30

EC_TX
EC_RX

1
2
3
4
5
6
7
8
9
10
11
12

8,27,30,37,38

PM_SLP_S3#

8,30
8,30,39
8

7

PM_SLP_S5#
PM_SLP_S4#
PM_SLP_A#
+3V_PCH
PCH_RTCRST#

8,18,20,29,30
8,18
A

PBTN_SW#
PM_SYS_RESET#

8,30,36,38

PM_SLP_S0#

+3V_PCH

XDP_TDO

51_0402_5%

2

1

RH38

+3VS
XDP_DBRESET#

@ RH367

1

2 1K_0402_5%

SYS_PWROK_XDP

@ R1311

1

2 3K_0402_5%

13
14

@ RH51

1
1
@ CH1
0.1U_0402_25V6K

JXDP

2

+1.05VS_XDP
5
5

0_0402_5%

2

5
5

GND
GND
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

10,29 1.05VS_VCCST_PG
8,18,20,29,30 PBTN_SW#
8 PBTN_OUT#_R
10 FIVE_EN
8,29 SYS_PWROK

XDP_PREQ#
XDP_PRDY#
11
11

CFG0
CFG1

11
11

CFG2
CFG3

XDP_BPM0#
XDP_BPM1#
11
11

CFG4
CFG5

11
11

CFG6
CFG7

@ R1180 1
@ RH21 1
@ RH444 1

2 1K_0402_5%
2 0_0402_5%
2 0_0402_5%

XDP_PWRGD
PCH_PWRBTN#_XDP

@ R1309 1

2 0_0402_5%

SYS_PWROK_XDP

7,12,14,19
7,12,14,19

PCH_SMBDATA
PCH_SMBCLK

XDP_TCK1
XDP_TCK0

SYS_PWROK_XDP

1

E-T_6705K-Y18N-00L
CONN@

2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

+1.05VS_XDP
PLTRST1#_XDP
XDP_DBRESET#

@
C1282
0.1U_0402_10V7K

11
11

CFG8
CFG9

11
11

CFG10
CFG11

11
11

CFG19
CFG18

11
11

CFG12
CFG13

11
11

CFG14
CFG15

11
11

@ RH363 1
@ RH451 1

1

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PIN60

A

Title

P18-XDP,APS,Debug CONN
Size

Document Number

Rev
1.0

LA-9262P
Date:

2

CFG3

Compal Electronics, Inc.
2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

1K_0402_5%

Compal Secret Data
Deciphered Date

PLT_RST# 8,18,22,23,30
PM_SYS_RESET#
8,18

@
R1198

1

TCK0, TCK1 and TMS stub <200ps

2011/06/02

2 1K_0402_5%
2 0_0402_5%

@
C1237
0.1U_0402_10V7K

2

XDP_PIN60

Issued Date

4

CFG17
CFG16

SAMTE_BSH-030-01-L-D-A
CONN@

Security Classification

5

B

+1.05VS

GND
GND

JAPS

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

J4D
<200ps of the XDP

@

ACES_50281-0120N-001
CONN@

+3VALW

XDP_TDI

R7

JDebug
7,22,30
7,22,30
7,22,30
7,22,30
7,22,30
8,18,22,23,30
7

Friday, April 19, 2013

Sheet
1

18

of

45

3

2

MD90

6
+3VDX

2 0_0805_5%

GND

V BUS Ground
V I/O

@
C1231
10U_0603_6.3V6M

V I/O

2

@ R1004 1

2

2

ML55

D93
5,19,35

2 0_0402_5%

3

EN

9

USB20_P4

9

USB20_N4

1

1

2

4

3

2

USB20_P4_CONN

3

USB20_N4_CONN

8

+3VS_CAM

DMIC_DAT
R1342 1
ALS_SMBCLK
ALS_SMBDATA
ALS_INT#

DMIC_CLK

1

2 100_0402_5%

1

@ R1279

LCD_DBC

LCD_DBC

1

ENVDD

4

+3VS

DMIC_CLK_R

2 0_0402_5%

+LCDVDD
30

LCD_TEST

2

PCH_ENVDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

USB20_P4_CONN
USB20_N4_CONN

I2C1_SDA_TS

1

APL3512ABI-TRG_SOT23-5

D

3

JLVDS2

eDP Conn

+LCDVDD

2

IP4223CZ6_SO6-6

1
2

SS

2200P_0402_25V7K

V I/O

1

C1143
10U_0603_6.3V6M

4

1

1

@ R1322

4

VIN

C1230

2

1

VOUT

+LCDVDD

V I/O

I2C1_SCK_TS

C1145
.1U_0402_16V7K

5

+LCDVDD

02-0320

U721

5

+3VS_TOUCH

1

+3VALW
20,30

TABLET_MODE

Win8_BTN_SW#_C

WCM2012F2S-900T04_0805
19,30,35

3

EC_ENVDD

@ R1005 1

2 0_0402_5%

DMIC_DAT

BAT54CW-7-F_SOT323-3
R1026

2

1

1 220K_0402_5%

ENVDD
@ R1006 1

2

2 0_0402_5%

DMIC_CLK_R

1

@
MC1210
10P_0402_50V8J

2

MC1133
10P_0402_50V8J

eDP BackLight Power

5

eDP_TXN_P1

C1061 1

eDP_TXP_P1

0.1U_0402_10V7K
2
C1063 1

+INV_PWR_SRC

B+
@ R531 1

2

SP010016L00

4

eDP_TXN_P1_C

3

1

eDP_TXP_P1_C

0.1U_0402_10V7K

JLVDS1

eDP_TXN_P1_CONN

2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

TS_INT#_R
eDP_TXN_P1_CONN
eDP_TXP_P1_CONN

eDP_TXP_P1_CONN

DLW21SN670HQ2L_4P

2 0_0603_5%

eDP_TXN_P0_CONN
eDP_TXP_P0_CONN

@ R1007 1

2 0_0402_5%

@ R1008 1

2 0_0402_5%

eDP_AUXP_CONN
eDP_AUXN_CONN

D

3

R535
1M_0402_5%

C613
0.1U_0402_25V6

5

C1060 1

eDP_TXN_P0

5

Vgs(th) = -1 ~ -3, max 20V

2

eDP_TXP_P0

D105

2
+LCDVDD_R

2
3

3

2
eDP_AUXN

0.1U_0402_10V7K
2
C1065 1

S

0.1U_0402_10V7K

2 0_0402_5%

@ R1010 1

2 0_0402_5%

5

TS_RST#

eDP_AUXP_C

4

3

eDP_AUXP_CONN

eDP_AUXN_C

1

2

eDP_AUXN_CONN

@
R1034
100K_0402_5%

@ R1139

2

1 100K_0402_5%

LCD_DBC

@ R1376

2

1 100K_0402_5%

TS_RST#

@ R1011 1

2 0_0402_5%
TS_RST#

VCC

5
MD50

1

IN A
GND

OUT Y

4

D

2

@ Q305
DII-DMN65D8LW-7

G

3

3

TS_INT#_R

DMIC_CLK

6

+3VS

5

DMIC_DAT

4

V I/O

V I/O

V BUS Ground
V I/O

S

V I/O

USB20_N4_CONN

R1385
100K_0402_5%

2
3

USB20_P4_CONN

@ Q363

IP4223CZ6_SO6-6

8

1

TS_INT#

D

SN74AUP1G04DCKR_SOT23-5

1

1

NC

2 0_0402_5%

2

2

@ R1389 1

+3VS_TOUCH

2

1
+LCDVDD_R

SP010016L00

DLW21SN670HQ2L_4P

@
R541
820_0805_1%

@

C

ACES_50406-02071-001
CONN@
SP010016L00

1
1

+LCDVDD
U708

I2C1_SCK_TS
I2C1_SDA_TS
TS_RST#

@ ML58

+INV_PWR_SRC

BAT54CW-7-F_SOT323-3

@ R1009 1

2

EC_ENVDD

eDP_AUXP

5

Discharge Circuit

Q71
DII-DMN65D8LW-7

G
19,30,35

5

eDP_TXP_P0_CONN

G

1

D

2

2

+INV_PWR_SRC
+3VS_TOUCH

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
G1
G2
G3
G4

3

TS_INT#_R

S

PCH_ENVDD

1

5,19,35

C1064 1

@
R1033
100K_0402_5%

1

R536
100K_0402_5%

2

+LCDVDD_R

DISPOFF#
INV_PWM_R

eDP_TXN_P0_CONN

DLW21SN670HQ2L_4P

+3VS

MLK IC :
113m ohm
550m A

1

1 220K_0402_5%

2

2

3

1

eDP_TXP_P0_C

0.1U_0402_10V7K
C612
0.1U_0402_25V6

PWR_SRC_ON

R1161

4

eDP_TXN_P0_C

0.1U_0402_10V7K
2
C1062 1

1

2
C

eDP_HPD

@ ML57

60mil

2

2

6
5
2
1

G

1

4

1

5

Q70
SI3457CDV-T1-GE3_TSOP6
S

60mil

D

ACES_50406-02071-001
CONN@
SP010016L00

@ ML56
5

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
G1
G2
G3
G4

Right Hinge

4

Left Hinge

5

DII-DMN65D8LW-7

+3VALW

R1384

1
2

BackLight PWM Control
D72

B

2

ENBKL

1
30

DISPOFF#
30

1

3

BKOFF#

2

Win8_BTN_SW#

R540
220K_0402_5%

1

2

BAT54CW-7-F_SOT323-3

B

1

5

2

1

+3VS_TOUCH

Win8_BTN_SW#_C

R978
1K_0402_5%
C1142
0.01U_0402_16V7K

D73
SDMK0340L-7-F_SOD323-2

PCH_INV_PWM

1

2

1

RH364

1

2 2.2K_0402_5%

I2C1_SDA

RH365

1

2 2.2K_0402_5%

7,12,14,18

PCH_SMBCLK

7,12,14,18

PCH_SMBDATA

INV_PWM_R

R545
220K_0402_5%

2

D92
SDMK0340L-7-F_SOD323-2

I2C1_SCK

1

2

@
MC1151
680P_0402_50V7K

2 0_0402_5%

A

DMIC_DAT

@ RA10 1

2 0_0402_5%

1

2 0_0402_5%

@ RA5
@ RA6

1

2 0_0402_5%

DMIC_CLK_CODEC

20

1

2 0_0402_5%

8

I2C1_SDA

I2C1_SDA

@ R1258

1

2 0_0402_5%

@ R1152

1

2 0_0402_5%

I2C1_SCK_TS
I2C1_SDA_TS

@ R1153

1

2 0_0402_5%

9

USB20_N3

@ R1218

1

2 0_0402_5%

9

USB20_P3

@ R1219

1

2 0_0402_5%

DMIC_CLK_DSP

20

DMIC_DAT_DSP

20

To EC

ALC5505
To Sensor HUB

2011/06/02

Deciphered Date

ALS_INT#_EC

22

ALS_INT#_HUB

3

2

29

Touch PAD

Touch Panel

1 0_0402_5%

@ R1116 2

1 0_0402_5%
2 0_0402_5%

ALS_SMBCLK

7,26,30

PCH_SMLCLK

@ R983

7,26,30

PCH_SMLDATA

@ R984

ALS_INT#

1

2 0_0402_5%

ALS_SMBDATA

1 0_0402_5%

02-0320

1 0_0402_5%

22

Sensor_I2C_SCL

@ R985 2

22

Sensor_I2C_SDA

@ R986 2

A

Compal Electronics, Inc.
2013/10/28

Title

P17-eDP/ Camera CONN
Size

Document Number

Rev
1.0

LA-9262P
Date:

4

29

I2C1_SDA_TP

@ R1115 2

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

I2C1_SCK_TP

Default control from EC connect to PCH<->EC SMBus
30

Compal Secret Data

Security Classification
Issued Date

ALC3661

20

DMIC_DAT_CODEC

2 0_0402_5%

@ R1257

For ALS Sensor
1

2 0_0402_5%

1

I2C1_SCK

Closed to JLVDS2
@ RA9

1

@ R1378

I2C1_SCK

02-0320

DMIC_CLK

@ R1377

8

1

5

2

2

0_0402_5%

@
R977
100K_0402_5%

Friday, April 19, 2013

Sheet
1

19

of

45

5

4

+5VS_AUDIO

2

1

+3VALW

2
C1146
.1U_0402_16V7K

1

3

+3VS_AUDIO

2
C1099
.1U_0402_16V7K

1

+5VA

2
C1100
.1U_0402_16V7K

1

+1.5VS_3.3VS_AUDIO

2
C1101
.1U_0402_16V7K

1

2

Pull-up resistor is on EC page (100K)

2

1

VOLUME_UP_SW#_C

1
C1098
.1U_0402_16V7K

1

C1279
0.1U_0402_10V7K

2

R953
1K_0402_5%

VOLUME_UP_SW#

VOLUME_UP_SW#

30

1

2

C1123
0.01U_0402_16V7K

Pull-up resistor is on EC page (100K)

D

JIOL1

38

19
19
8

36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

DMIC_DAT_CODEC
DMIC_CLK_CODEC
HDA_SPKR

HDA_SDIN0_DSP
HDA_SDOUT_DSP
HDA_RST_DSP#
HDA_SYNC_DSP

ML9

1

HDA_BITCLK_DSP

2

HDA_BITCLK_AUDIO_C

0_0603_5%

1

@ MC1297
0.01U_0402_16V7K

+RTCVCC
+3VS_AUDIO
+1.5VS_3.3VS_AUDIO
+5VS_AUDIO

2

GND

1

VOLUME_DOWN_SW#_C

GND

36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

2

D

VOLUME_DOWN_SW#

VOLUME_DOWN_SW#

37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

R955
1K_0402_5%

VOLUME_UP_SW#_C
VOLUME_DOWN_SW#_C
ROTATION_LOCK_SW#_C

1

2

PBTN_SW#
8,18,29,30
LID_SW_IN#
30
BATT_LED_COLOR_W
30
BATT_LED_CTRL# 30

30

C1124
0.01U_0402_16V7K

Pull-up resistor is on PCH (10K)

EAPD# 30
AUD_MUTE#
BEEP# 30

30
ROTATION_LOCK_SW#_C

1

2

R957
1K_0402_5%

+3VALW
+5VA

ROTATION_LOCK_SW#

2

+5VS_AUDIO

30

1
C1125
0.01U_0402_16V7K

E-T_1001K-F36E-03L
CONN@
DC031201160

SP01000Q510

+1.2VS_DVDD
+3VS_AUDIO

Closed to UA1 Pin 16
1

15-0411

1

2

1

2

DVDD-12-I
DVDD-12-I
DVDD-12-I

+1.2VS_DVDD

DVDD-12-SWR

15
13

DVDD_25
DDR_VREF

43
40

HDA_BITCLK_AUDIO
HDA_SDOUT_AUDIO
HDA_SDIN0_AUDIO
HDA_SYNC_AUDIO
HDA_RST_AUDIO#

6
5
8
10
11

DVDD-33-SWR

16

DVDD-33-SWR-C

DVDD-IO
FB-SWR
DVDD-12-SWR

ALC5505

DVDD-25-LDO-O
DDR-VERF

32
29
30
31

MCLKO
I2SCLKO
I2SCLRCKO
I2SSDO0

38
39
41

I2SCLKI
I2SLRCKI
I2SSDI0
DSP-PD#

1.2_PGND

7
7
7
7
7

DVDD_25

2

1

2 33_0402_5%

45
46

CA13
0.1U_0402_10V7K

closed to pin 40

1
2

R1186
20K_0402_1%

DDR_VREF

19
19

1
R1187
20K_0402_1%

2

@ RA11 2
@ RA12 2
@ RA13 2

1 0_0402_5%
1 0_0402_5%
1 0_0402_5%

23
23

R1261
10K_0402_5%

I2S_SDI_IN
DSP_PD#_R
HDA_BITCLK_DSP_B
HDA_SDOUT_DSP_B
HDA_SDIN0_DSP
HDA_SYNC_DSP
HDA_RST_DSP#

23
@ R1262 2

1 0_0402_5%

TABLET_MODE_R

@ R1375 2

1 0_0402_5%

VOLUME_DOWN_SW#_DSP
VOLUME_UP_SW#_DSP

@ R1263 2
@ R1264 2

1 0_0402_5%
1 0_0402_5%

DSP_PD#

TABLET_MODE

30

19,30

VOLUME_DOWN_SW#_C
VOLUME_UP_SW#_C
B

I2C0_SCK_DSP
I2C0_SDA_DSP

33
34
35
36

CS-L
SCK
SI
SO

DVSS-SWR
DVSS
DGND

AUDIO_XTAL24_OUT

I2S_SFRM_OUT
I2S_SDO_OUT
I2S_CLK_IN
I2S_SFRM_IN

17

26
27

I2C-MASTER-SCL/I2C-SLAVE-SCL
I2C-MASTER-SDA/I2C-SLAVE-SDA

XTAL-IN
XTAL-OUT

12
44
49

I2S_BCLK_OUT

23
24
21
19
18
7
28
4
20
22

VGPIO0/TRST#
VGPIO2/TMS
VGPIO3/VOL-DN/TDI
VGPIO4/VOL-UP/TCLK
VGPIO5/VOL-MUTE/TDO

VDIMC-CLK1
VDMIC-DAT1

2
3

AUDIO_XTAL24_IN
AUDIO_XTAL24_OUT

BITCLK-V/MCLKI-2
SDATA-OUT-V/I2SSDO1
VGPIO1/SDATA-IN-V/I2SSDI3
SYNC-V/I2SSDO2
RESETB-V/I2SSDO3

VDMIC-CLK2/I2SSDI1
VDMIC-DAT2/I2SSDI2

47
48

DMIC_CLK_DSP
DMIC_DAT_DSP

CA15
0.1U_0402_10V7K

2

2

RA1

BITCLK/I2SCLKI-2
SDTA-OUT/I2SSDO0-2
SDATA-IN/I2SSDI0-2
SYNC/I2SLRCLKI-2
RESETB

1

1

1

CA14
0.1U_0402_10V7K

2
B

CA21
10U_0603_6.3V6M

1

HDA_BITCLK_AUDIO
HDA_SDOUT_AUDIO
HDA_SDIN0
HDA_SYNC_AUDIO
HDA_RST_AUDIO#

+3VS_AUDIO

1.2_PGND

42

DVDD-33-LDO-I

9

2

14

1

1
25
37

+1.5VS_3.3VS_AUDIO

CA20
10U_0603_6.3V6M

1

CA19
4.7U_0603_6.3V6K

2

2

CA18
0.1U_0402_10V7K

1

CA12
0.1U_0402_10V7K

2

CA11
0.1U_0402_10V7K

2

CA9
10U_0603_6.3V6M

CA7
10U_0603_6.3V6M

2

1

2

+3VS_AUDIO
UA1

LA1
1
2
DVDD-12-SWR
4.7UH_PG031B-4R7MS_1.1A_20%

1
1

+1.2VS_DVDD

Closed to UA1 Pin 13

+3VS_AUDIO

1

CA22
10U_0603_6.3V6M

C

2

2
+1.2VS_DVDD

1

CA10
0.1U_0402_10V7K

2

CA8
10U_0603_6.3V6M

2

1

CA6
0.1U_0402_10V7K

2

1

CA5
0.1U_0402_10V7K

2

1

CA4
0.1U_0402_10V7K

2

1

CA3
4.7U_0603_6.3V6K

2

1

CA2
4.7U_0603_6.3V6K

1

CA1
4.7U_0603_6.3V6K

C

+1.5VS_3.3VS_AUDIO

09-0328

8
8

+3VS_AUDIO
R1265
R1266

VOLUME_DOWN_SW#_DSP
VOLUME_UP_SW#_DSP

2
2

1 10K_0402_5%
1 10K_0402_5%

1.2_PGND
YA1
24MHZ_12PF_7V24000020

1
2

ALC5505_QFN48_7X7

3
4

1.2_PGND

AUDIO_XTAL24_IN

1

1

CA16
2 18P_0402_50V8J

2 18P_0402_50V8J

HDA_BITCLK_AUDIO
HDA_SDOUT_AUDIO
HDA_SDIN0_AUDIO
HDA_SYNC_AUDIO
HDA_RST_AUDIO#

CA17

02-0320

+3VS_AUDIO

U664
+3VDX

+5VA
8,27,35

1
A

2

AUDIO_PWREN

AUDIO_PWREN
+5VA

C1213
0.1U_0402_10V7K

1
2
3
4
5

+5VA
+3VS

6
7

VIN1
VIN1

VOUT1
VOUT1

ON1

CT1

VBIAS
ON2
VIN2
VIN2

GND
CT2
VOUT2
VOUT2
GPAD

14
13

@ R1318 1

2 0_0603_5%

MLK IC :
20m ohm
230m A
Intel :
165m ohm
200m A

@ RA16
@ RA17
@ RA18
@ RA19
@ RA20

2
2
2
2
2

1
1
1
1
1

HDA_BITCLK_DSP_B

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

02-0320

HDA_BITCLK_DSP_B
HDA_SDOUT_DSP_B
HDA_SDIN0_DSP
HDA_SYNC_DSP
HDA_RST_DSP#

@ RA14 1

I2S_BCLK_OUT
I2S_CLK_IN
I2S_SFRM_IN

2 0_0402_5%

HDA_BITCLK_DSP

@ R1372 2
@ R1373 2
@ R1374 2

HDA_SDOUT_DSP_B

1 0_0402_5%
1 0_0402_5%
1 0_0402_5%

@ RA15 1

I2S_CLK

2 0_0402_5%

+1.5VS_3.3VS_AUDIO

12

C1212 1

2 2200P_0402_25V7K

C1214 1

2 2200P_0402_25V7K

1
+5VS_AUDIO

10
9
8

@ R1125 1

15

2 0_0603_5%

02-0320

MLK IC :
20m ohm
570m A
Intel :
33m ohm
1500m A

2
3

NC

HDA_SDOUT_DSP

+1.5VS_3.3VS_AUDIO

UA2 @

11

23

UA3 @

VCC

5

1
2

A
Y

4
3

GND

74AUP1G34GW_TSSOP5

NC

VCC

5
A

A
Y

4

GND

74AUP1G34GW_TSSOP5

TPS22966DPUR_SON14_2X3
R1182

2

1 100K_0402_5%~D

AUDIO_PWREN

@ R1140

2

1 1K_0402_5%

AUDIO_PWREN

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P18-Audio DSP, IOL Conn
Size

5

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

Friday, April 19, 2013

Sheet
1

20

of

45

5

4

3

2

Mini DP CONN

1

Co-lay

D113

2

+3VS

DPF1

1

1

2

3
@ RV1

D

2

1 0_1206_5%

1

2

1

2

CV2
.1U_0402_16V7K

BAT1000-7-F_SOT23-3

CV1

10U_0603_6.3V6M

1.5A_6V_1206L150PR

D

+3VS
JMDP1
DISP_DAT_AUXN_CONN

RV2

1

2

100K_0402_5%

DISP_CLK_AUXP_CONN

RV3

1

2

100K_0402_5%

+5VS
PCH_DP_P0

.1U_0402_16V7K

2

1

CV3

PCH_DP_N0

.1U_0402_16V7K

2

1

CV4

DISP_HPD_SINK
PCH_DP_P0_C
CAB_DET_SINK
PCH_DP_N0_C

5
5
5
5

PCH_DP_P1
PCH_DP_P3
PCH_DP_N1
PCH_DP_N3

.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K

2
2
2
2

1
1
1
1

CV5
CV6
CV7
CV9

PCH_DP_P1_C
PCH_DP_P3_C
PCH_DP_N1_C
PCH_DP_N3_C

5

PCH_DP_P2

.1U_0402_16V7K

2

1

CV11

5

PCH_DP_N2

.1U_0402_16V7K

2

1

CV12

PCH_DP_P2_C
DISP_CLK_AUXP_CONN
PCH_DP_N2_C
DISP_DAT_AUXN_CONN

5
5

DISP_CEC

1
@ CV13
0.1U_0402_10V6K

2

UV1

16
5
5
5
5

PCH_DP_AUXP
PCH_DP_CLK
PCH_DP_AUXN
PCH_DP_DAT

0.1U_0402_10V7K

2

1 CV8

PCH_DP_AUXP_C

0.1U_0402_10V7K

2

1 CV10

PCH_DP_AUXN_C

2
3
5
6
11
10
14
13

Vcc
1B1
1B2
2B1
2B2
3B1
3B2
4B1
4B2

1A
2A
3A
4A
OE#
S
GND

4
7
9
12
15
1
8

SN74CBT3257CPWR_TSSOP16

DISP_CLK_AUXP_CONN
DISP_DAT_AUXN_CONN

DP_CBL_DET

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1 : HDMI/DVI/VGA Dongle
0 : DP Port

1

2

2

21
22
23
24

0.1U_0402_10V7K

22U_0805_6.3V6M

LTCX0044A00

C

C

5.1M_0402_5%

2

1

CV15

1

GND1
GND2
GND3
GND4

ACON_MAR2B-20K1200
CONN@
SP061204160

RV4

CV14

S = L, A port = B1 port
S = H, A port = B2 port

GND
HPD
LANE0_P
CONFIG1
LANE0_N
CONFIG2
GND
GND
LANE1_P
LANE3_P
LANE1_N
LANE3_N
GND
GND
LANE2_P
AUX_CH_P
LANE2_N
AUX_CH_N
GND
DP_PWR

G

2

+5VS

3

1

DISP_HPD_SINK

1

D

PCH_DP_HPD

S

5

QV2

@
RV10
100K_0402_5%

2

BSS138-G_SOT23-3

B

B

@ RV8

2

0_0402_5%

CAB_DET_SINK

1

1

DP_CBL_DET

2

RV9
1M_0402_5%

DP Signal ESD
@ MD1
PCH_DP_P0_C

1 1

10 9

PCH_DP_P0_C

PCH_DP_N0_C

2 2

9

8

PCH_DP_N0_C

PCH_DP_P1_C

4 4

7

7

PCH_DP_P1_C

PCH_DP_N1_C

5 5

6

6

PCH_DP_N1_C

3 3
8
RCLAMP0524PATCT_SLP2510P8-10-9

Place close JDP1
@ MD2
PCH_DP_P3_C

1 1

10 9

PCH_DP_N3_C

2 2

9

8 PCH_DP_N3_C

PCH_DP_P2_C

4 4

7

7

PCH_DP_N2_C

5 5

6

6 PCH_DP_N2_C

PCH_DP_P3_C

A

A

PCH_DP_P2_C

3 3
8
RCLAMP0524PATCT_SLP2510P8-10-9

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P19-Mini DP CONN
Size
C
Date:

5

4

3

2

Document Number

Rev
1.0

LA-9262P
Friday, April 19, 2013

Sheet
1

21

of

45

3

2

Sensor Fussion

Gyro

+3VNS_PWR

2 100K_0402_5%
2 100K_0402_5%

1

R1099

2 10K_0402_5%

JTCK

1

4

GYRO_I2C_ADD_SEL

5

7

GYRO_INT#

8

2 0_0402_5%
8 SENSOR_DFU_EN#
SENSOR_HUB_WAKE#

I2C0_SCK_SNR
I2C0_SDA_SNR
SENSOR_HUB_I2C_WAKE_R
PB13
SENSOR_DFU_EN#

HUB_OSC_IN

1
B

2

2

HUB_OSC_OUT

8MHZ_12PF_7A08000006

1

C1204
18P_0402_50V8J

1
C1205
18P_0402_50V8J

2

1

2

+3VNS_PWR

2

C970
0.1U_0402_10V7K

2

ATMEL TPM

PRESSURE_INT2#

9

PRESSURE_INT1#
D

NC
NC
GND
GND

Reserved
GND
GND

10
16
13

Need change to DELL P/N

+3VNS_PWR

1

@
R1205
0_0402_5%

Place close to U638 Pin 1,15,16

24

11

LPS331APTR_HCLGA16_3X3

1
C969
10U_0603_6.3V6M

INT1

Pressure 0xBA

GYRO_I2C_ADD_SEL

2

+3VNS_PWR

@
C1148
10U_0603_6.3V6M

2

@
R1206
0_0402_5%

PC0
SBD_WAKE#
PC2
Sensor_ALERT#

A3

SPARE2

R1090
0_0402_5%

@

@ T252

2

G6
A8
A1
H1
G8
VDD_4
VDD_3
VDD_2
VDD_1
VDDA

E8
F8
D6
H6
H5
E1
E2
E3
D1
A2
B3
C4
C8
B8
B7

C7
A6
F7
C6

NRST
BOOT0
Vref+
Vbat

D8
D7

OSC_IN
OSC_OUT

1

2

@
R1003
100K_0402_5%

Sensor_RST#

1

@
C1149
0.1U_0402_10V7K

2

+3VNS_PWR

2

SPARE1

C1152
0.1U_0402_10V7K

2

C

e-Compass + Accelerometer

+3VNS_PWR

SOSCI
SOSCO

+3VNS_PWR

RESET#

+3VNS_PWR
+3VALW

C964 2

@
R819
0_0402_5%

@ R1141

2

1 100K_0402_5%

@ R1253

2

1 100K_0402_5%

2

C968
4.7U_0603_6.3V6K
2
MAG_DRDY

+3VNS_PWR
JSNRDG

RESET#
SENSOR_HUB_I2C_WAKE_R

Place close to U636
1
C977
0.1U_0402_10V7K

1 0.22U_0402_10V6K

1

HUB_OSC_IN
HUB_OSC_OUT

1

1
6

C964 Should be low ESR (220mOhm) ceramic type

BOOT0

C976
0.1U_0402_10V7K

+3VNS_PWR
U637

@
R1092
0_0402_5%

1
CH1203
18P_0402_50V8J

Place close to U653 Pin 1, 14

1

STM32F103RCY6TRC23_WLCSP64

1
CH1202
18P_0402_50V8J

RESET#

PC0
PC1
PC2
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15

Y1
32.768KHZ_12.5PF_9H03200031
2
1
SOSCI
SOSCO

Y2

1

2

PD2

DFU_ENA : uC DFU mode enable (Active Low)

Connect to HSW GP27 via EC

+3VNS_PWR

INT2

SA0

C978
1U_0402_6.3V6K

2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND1
GND2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

Vdd_IO
C1

Vdd
SDA

12
13

SETP
SETC

SCL

14
3

Sensor_I2C_SDA

2

Sensor_I2C_SCL

5

ACCEL_INT1

4

ACCEL_INT2

LSM303DLHCTR_LGA14

8
9
10
11

RESET#
JTMS
JNTRST
JTCK
JTDI
JTDO
Sensor_I2C_SCL
Sensor_I2C_SDA
SPARE1
SPARE2

Reserved
DRDY
Reserved
Reserved

INT1
INT2

7

GND
LSM303DLHCTR_LGA14_3X5

Magnetic 0x3C
Acceleration 0x32

SENSOR_HUB_I2C_WAKE_R
CONSOLE_RX
CONSOLE_TX
SENSOR_EN

SENSOR_DFU_EN#
I2C0_SCK_SNR
I2C0_SDA_SNR

8,27

+3VNS_PWR

1

Sensor_I2C_SCL
Sensor_I2C_SDA
8 SLATE_MODE

@ R1252 1

30

JTDO
JNTRST
PB5
Sensor_I2C_SCL
Sensor_I2C_SDA

24 JTDO
JNTRST

PA0-WKUP
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15

F5
A7
B1
H2
E7

To HSW GP58
8 I2C0_SCK_SNR
8 I2C0_SDA_SNR
SENSOR_HUB_I2C_WAKE

7

1

BOOT1
24

8

SML1ALERT#

0.1U_0402_10V7K

2
PRESSURE_INT1#
MAG_DRDY
GYRO_DRDY
PRESSURE_INT2#
ACCEL_INT2
CONSOLE_TX
CONSOLE_RX
PA11
PA12
JTMS
JTCK
JTDI

24 JTMS
24 JTCK
24 JTDI

Connect to mSATA card for
Debug/Programing used

F6
E6
H8
G7
H7
E5
G5
G4
E4
D2
D3
C1
C2
D4
B2
C3
H4
F4
H3
A4
B4
A5
B5
C5
D5
B6
G3
F3
G2
G1
F2
F1

ALS_INT#_HUB
GYRO_INT#

ALS_INT#_HUB

@ T260
@ T261

19
19

16

2
3
5
12

C974
0.01U_0402_16V7K

SDA

2

R537
1M_0402_5%

VSS_4
VSS_3
BYPASS/VSS_2
VSS_1
VSSA

19

SENSOR_HUB_I2C_WAKE - Asserted by host
Transition ST32 out of stop mode

SML1ALERT#

2

U636

C

15

14
15

CS

+3VNS_PWR

C979

1

1

D94
SDMK0340L-7-F_SOD323-2

8

To HSW GP14

SENSOR_INT#
8
SMBALERT# 7

2 0_0402_5%

1
2

7

1

1
+3VNS_PWR

ACCEL_INT1

VDD

14

VDD
Reserved

SCL

Gyroscope 0xD2

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
@ R1158 1

Sensor_ALERT#

RES_0

VDD_IO

1

2

SENSOR_STANDBY#

PA11
PA12

RES_6

6

L3GD20TR_LGA16_4X4

Exit Standby on rising edge of
ACCEL_INT1 or SENSOR_STANDBY#

D74
SDMK0340L-7-F_SOD323-2

From HSW GP70
8

2 0_0402_5%
2 0_0402_5%

INT1

Sensor_I2C_SDA
100K_0402_5%

2

@ R1221 1
@ R1222 1

USB20_N5
USB20_P5

RES_5

@
R1175

1

9
9

PB13 @ R1367 1
PC0 @ R1135 1
PC2 @ R1136 1

PB5

5

DRDY/INT2

12
13

4

2

2 1.5K_0402_5%

Sensor_RST#

GND

Sensor_I2C_SCL

1

R1223 1

PA12

Sensor_RST#

RES_4

11

2

2 1.5K_0402_5%

SDO/SA0

1
+3VNS_PWR

10

R1207
100K_0402_5%

2 10K_0402_5%

RES_3

9

2

PA12

SDA/SDI/SDO

+3VNS_PWR

@

R1088
100K_0402_5%

R1227 1
@ R1251 1

SML1ALERT#

RES_2

CS

6

GYRO_DRDY

RES_1

SCL/SPC

1

1

3

VDD_IO

1

@ R1143 1

ALS_INT#_HUB

Sensor_I2C_SDA

U653

1

@ R1220 1

2

2

SENSOR_DFU_EN#

D

@
R1176

10K_8P4R_5%

Sensor_I2C_SCL

2

+3VNS_PWR

JNTRST
JTDO
JTMS
JTDI

R1091

2 2.2K_0402_5%
2 2.2K_0402_5%

8
7
6
5

100K_0402_5%

1
1

R854
R855

1
2
3
4

100K_0402_5%

Sensor_I2C_SCL
Sensor_I2C_SDA

1

+3VNS_PWR
RP12

Pressure

+3VNS_PWR

U638

+3VNS_PWR
+3VNS_PWR

1

2

4

2

5

Place close to U637 Pin1, 14

1

1
C965
10U_0603_6.3V6M

2

2

C966
0.1U_0402_10V7K

B

ACES_50506-02041-P01
CONN@

+3VS_TPM

+3VS_TPM

O

TPM_RESET#

2

1
3

TPM@
R1310
220K_0402_5%

+3VS_TPM
U652

2

5

28

2

LPCPD#
7,18,30
7,18,30
7,18,30
7,18,30

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

7
7,18,30

CLK_PCI_TPM
LPC_FRAME#

8,30
8,30

SERIRQ
PM_CLKRUN#

TPM@

TPM@

26
23
20
17

SB3V

LPCPD#
LAD0
LAD1
LAD2
LAD3

1

CLK_PCI_TPM
TPM_RESET#

21
22
16
27
15

LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#

TESTBI
TESTI

ATEST_1
ATEST_2
ATEST_3

GND_4
GND_11
GND_18
GND_25

2

@ MR976
33_0402_5%

V_BAT
NBO_13
NBO_14

GPIO6

CLK_PCI_TPM
A

VCC_0
VCC_1
VCC_2

2

@ MC1141
27P_0402_50V8J

1

2

12
13
14

TPM@

1

2

TPM@

TPM@

1

2

1

2

TPM@

6
9
8

A

+3VS_TPM
@ R975

NC_7
1
2
3

1

10
19
24

7
4
11
18
25

PP

1

2

4.7K_0402_5%

Issued Date

SUS_STAT#
+3V_PCH

5

@

R1238

1

2 0_0402_5%

TPM@

R1239

1

2 10K_0402_5%

Compal Electronics, Inc.

Compal Secret Data

Security Classification

AT97SC3204-X2A1D-AB _TSSOP28

02-0320
8

C1140
0.1U_0402_10V7K

SN74AHC1G08DCKR_SC70-5

1

C1139
2200P_0402_25V7K

IN2

G

2

4

C1138
2200P_0402_25V7K

TPM_RST#

1
TPM@

P

5

TPM@
U698

IN1

C1137
2200P_0402_25V7K

8

1

C1136
4700P_0402_25V7K

PLT_RST#

C1135
0.1U_0402_10V7K

8,18,23,30

2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LPCPD#

Title

P20-Sensor Fussion / TPM
Size

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

Friday, April 19, 2013

Sheet
1

22

of

45

A

B

C

Wireless LAN

D

closed to pin 2, 4

+1.8VS

+3VS_NGFF

2 49.9K_0402_1%

SDIO_CMD

R1362 1

2 150K_0402_5%

SDIO_D0

R1363 1

2 49.9K_0402_1%

SDIO_D1

R1364 1

2 49.9K_0402_1%

SDIO_D2

1

2

R1365 1

2 49.9K_0402_1%

SDIO_D3

@ R1327 1

2 100K_0402_5%

SDIO_WAKE#_Q

@ R1328 1

2 10K_0402_5%

SDIO_RST#

2 49.9K_0402_1%

SDIO_CLK

1

2

1

2

1

2

C713
0.1U_0402_10V7K

R1361 1

+3VS_NGFF

11-0328
C716
22U_0603_6.3V6M

SDIO_CLK

C715
0.1U_0402_10V7K

2 49.9K_0402_1%

C712
22U_0603_6.3V6M

@ R1360 1

E

closed to pin 64, 66

1

1

+3VS
+1.8VS

1

2

@
C1283
0.1U_0402_10V7K

1

2
+3VS

R1395 1

@
C1284
0.1U_0402_10V7K

8,18,22,30
5

PLT_RST#
MPCIE_RST#

@ R1313

1

2 0_0402_5%

MPCIE_RST# @ R1314

1

2 0_0402_5%

PLT_RST#

VCCB

A2
A1

SDIO_RST#_R

VCCA

B1

B1

A1

SDIO_CLK
SDIO_CMD
8 SDIO_D0
8 SDIO_D1
8 SDIO_D2
8 SDIO_D3

B2

A2

GND

OE

C1
D2

SDIO_WAKE#_Q

D1

@ R1199 1

2 0_0402_5%

SDIO_WAKE#

@ R1216 1

2 0_0402_5%

NGFF_WAKE#_R

69

@ R1131 1

2 0_0402_5%
9
9

TXS0102YZPR_DSBGA8

+3VS_NGFF

R942 1

2

2 100K_0402_5%

PCIE_WAKE#

02-0320
Pop for SDIO Interface NGFF
5

NGFF_WAKE#

GND
USB_D+
USB_DGND
SIDO_CLK
SDIO_CMD
SDO_DAT0
SDO_DAT1
SDO_DAT2
SDO_DAT3
SDIO_WAKE#
SDIO_RESET#

3.3VAUX
3.3VAUX
LED1#
PCM_CLK
PCM_SYNC
PCM_IN
PCM_OUT
LED2#
GND
UART_WAKE#
UART_RX

2
4
6
8
10
12
14
16
18
20
22

BT_PCMCLK
BT_PCMFR1
BT_PCMIN
BT_PCMOUT

UART_WAKE#

UART1_RXD_NGFF

8

+1.8VS

SDIO_RST#

25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67

02-0320

C2

SDIO_CLK
SDIO_CMD
SDIO_D0
SDIO_D1
SDIO_D2
SDIO_D3
SDIO_WAKE#_Q
SDIO_RST#

8
8

+1.8VS

SDIO_WAKE#

JNGFF1

1
3
5
7
9
11
13
15
17
19
21
23

USB20_P2_R
USB20_N2_R

U679

B2

+3VS_NGFF

11-0328

PCIE_PTX_WLANRX_P3
PCIE_PTX_WLANRX_N3

9
9

PCIE_PRX_WLANTX_P3
PCIE_PRX_WLANTX_N3

7
7

CLK_PCIE2
CLK_PCIE2#

7

CLK_REQ2#

9
9

PCIE_PTX_DRX_P4
PCIE_PTX_DRX_N4

9
9

PCIE_PRX_DTX_P4
PCIE_PRX_DTX_N4

PCIE_WAKE#

UART_TX
UART_CTS
UART_RTS
RESERVED
RESERVED
RESERVED
COEX3
COEX2
COEX1
SUSCLK
PERST0#
W_DISABLE2#
W_DISABLE1#
I2C_DATA
I2C_CLK
ALERT
RESERVED
RESERVED
RESERVED
RESERVED
3.3VAUX
3.3VAUX

GND
PETP0
PETN0
GND
PERP0
PERN0
GND
REFCLKP0
REFCLKN0
GND
CLKEQ0#
PEWAKE0#
GND
RSRVD/PETP1
RSRVD/PETN1
GND
RSRVD/PERP1
RSRVD/PERN1
GND
RESERVED
RESERVED
GND
MTG77

MTG76

24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66

For Bluetooth CS notify

UART1_TXD_NGFF
UART1_CTS#_NGFF
UART1_RTS#_NGFF

1
1

@ R1210
@ R1212

1

2 0_0402_5%

@ R1208 1

2 0_0402_5%

@ R1200

2 0_0402_5%
2 0_0402_5%

@ R1255 1
NGFF_RST#

CL_DAT 7
CL_CK 7

2 0_0402_5%
BT_RADIO_DIS#

WL_OFF#_R

SUSCLK_R
8

2

@ R1209

1

2 0_0402_5%

BT_CS_NOTICE

+3VS_NGFF

68

+3VS_NGFF

1

2

USB20_P2_R

2

USB20_N2_R

@ R742 1

+3VS

R1137
10K_0402_5%

2

1

3

2 0_0402_5%

Q344
DII-DMN65D8LW-7

G

USB20_N2

3

1

3
S

9

4

D

4

1

USB20_P2

2

9

WL_OFF#_R

WL_OFF#

+3VS

8
+1.8VS

1

Prevent Backdriver from +3VS_WLAN to +3VS
3

+1.8VS

1@
@ R1215

1

2 0_0402_5%

@ R1214

1

2 0_0402_5%
+3VS

U709

1
1
1
1

2
2
2
2

49.9K_0402_1%
49.9K_0402_1%
49.9K_0402_1%
49.9K_0402_1%

UART1_TXD_NGFF
UART1_RXD_NGFF
UART1_RTS#_NGFF
UART1_CTS#_NGFF

UART1_TXD_NGFF
UART1_RXD_NGFF
UART1_RTS#_NGFF
UART1_CTS#_NGFF

2
3
4
5
6
7

05-0326

5

@ Q347
1
NGFF_WAKE#_R

3

C

5

VCC

@
C1285
0.1U_0402_10V7K

3

VCCA

VCCB

A1
A2
A3
A4
NC

B1
B2
B3
B4
NC

GND

OE

14
13
12
11
10
9

UART1_TXD
8
UART1_RXD
8
UART1_RTS#
8
UART1_CTS#
8

8 @ R1188 1

+1.8VS

2 0_0402_5%

TXB0104PWR_TSSOP14

PCIE_WAKE#

O

4

NGFF_RST#

2

Pop for PCIe Interface NGFF

IN A

MMBT3904_SOT23-3

IN2

1
3

3

OUT Y

4

@ R1202 1

+3VS
+1.8VS

2 10K_0402_5%

1
1

SN74AUP1G04DCKR_SOT23-5

2

R1203
100K_0402_5%

GND

B

IN1

2

E

P

2

NC

G

PLT_RST#

1

1

@

SN74AHC1G08DCKR_SC70-5
U675

2
U671

2
@ R1368
@ R1369
@ R1370
@ R1371

Pop for SDIO Interface NGFF

+3VS

C1286
0.1U_0402_10V7K

+1.8VS

+3VS

1

8,30

13-0402

2 0_0402_5%

@ ML49
WCM2012F2S-900T04_0805

MPCIE_RST#

8

02-0320

CONN@

@ R741 1

NGFF_PWREN

7

BT_CS_NOTICE

LOTES_APCI0019-P001A01

Pop for PCIe Interface NGFF

8,27

CL_RST#
BT_CS_NOTICE

+5VA

2

@
C1246
0.1U_0402_10V7K

1

2

U676

WAKE#

1

8

1
2
3

OE
A
GND

VCC
B

5
4

@
C1288
0.1U_0402_10V7K

+1.8VS

2

2
3
4
5
6

SN74CBTD1G125DCKR_SC70-5

7
R1338
100K_0402_5%

@
C1287
0.1U_0402_10V7K

U677

1
BT_PCMCLK
BT_PCMFR1
BT_PCMOUT
BT_PCMIN

PCIE_WAKE#

+3VS

VCCA

VCCB

A1
A2
A3
A4
NC

B1
B2
B3
B4
NC

GND

OE

14
13
12
11
10
9

I2S_CLK 20
I2S_SFRM_OUT
20 +1.8VS
I2S_SDO_OUT
20
I2S_SDI_IN
20

8 @ R1204 1

2 0_0402_5%

2

TXB0104PWR_TSSOP14

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P21-WLAN / WiGig / BT
Size

A

B

C

D

Document Number

Rev
1.0

LA-9262P
Date:

Friday, April 19, 2013

Sheet
E

23

of

45

5

4

3

2

1

mSATA Card
+3.3VDX_SSD
JSATA1

D

7
7

7
7

SATA_PRX_DTX_P0
SATA_PRX_DTX_N0

CS54 1
CS53 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PRX_DTX_P0_C
SATA_PRX_DTX_N0_C

SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

CS43 1
CS42 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_DRX_N0_C
SATA_PTX_DRX_P0_C

+3.3VDX_SSD
@ T244
@ T245
@ T246

RXRX+

GND1

Connect to Sensor HUB uC JTAG for
Debug/Programing used

@ T242
@ T243

DEVSLP0

DEVSLP0

+3.3VDX_SSD

8

1

54

GND2

D

RESET# 22
+3VNS_PWR

2
TYCO_2041119-1
CONN@

1

2

1

2

1

2

C722
47P_0402_50V8J

53

TX+
TX-

JTMS 22
JTDO 22
JTDI 22
JTCK 22
JNTRST
22

C721
0.01U_0402_16V7K

mSATA_DET#

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

C720
.1U_0402_16V7K

7

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

C719
4.7U_0603_6.3V6K

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

@

+3.3VDX_SSD

@ R1366 1

2 10K_0402_5%

DEVSLP0

C

C

B

B

ME Decide using 16 pin conn
MB 16 <-------> 15 pin NFC (Reserved Connection)
The I2C address set on the module is 28h

+3V_NFC

1

2
+3V_NFC

02-0320
+3V_PCH

2

1 100K_0402_5%

NFC_RST#

8

NFC_RST#

7
7

SML0CLK
SML0DATA

8
8

NFC_IRQ
NFC_DET#

JNFC1

2 0_0603_5%

NFC_RST#

NFC_VDD_SIM
NFC_DET#

2

@ R1142

@ R1242 1

1

R1100
100K_0402_5%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

15. MOD_GND
14. VDD_IO
13. MOD_VDD
12. SWP_PWR
11. NC/Float
10. Reset/WakeUp
9. MOD_GND
8. I2C_SCL
7. I2C_SDA
6. VDD_SIM
5. IRQ
4. MOD_GND
3. SWP
2. MOD_GND
1. MOD_VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GND
GND
HB_A531515-SCHR21
CONN@

+3V_NFC

A

C1134
0.1U_0402_10V7K

A

@
NFC_VDD_SIM

R973 2
@ R974 1

1 10K_0402_5%
2 0_0402_5%

NFC_DET#

@ R1228 1

2 0_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P22-mSATA / NFC Conn
Size
C
Date:

5

4

3

2

Document Number

Rev
1.0

LA-9262P
Friday, April 19, 2013

Sheet
1

24

of

45

A

B

C

D

E

USB CONN

+5V_USB_P1

close to JUSB1
JUSB1

@ R262 1

USB3TN1_RC_CON
USB20_P1_CONN

2 0_0402_5%

USB20_N1_CONN
USB3RP1_RC_CON

ML40
SW_USB20_P1

4

SW_USB20_N1

1

4

3

1

2

3

USB20_P1_CONN

2

USB20_N1_CONN

USB3RN1_RC_CON

1

WCM2012F2S-900T04_0805
@ R222 1

2 0_0402_5%

@ R556 1

2 0_0402_5%

30

USB1_DET#

USB3TP1

+5V_USB_P1

GND
GND
GND
GND

2.0A

11
12
13
14

TAIWI_USB014-107CRL-TW
CONN@
DC231201090

L40 close to JUSB1

1
C303

2

1

1

C265

2

LTCX0044E00

ML45
9

SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRXPlug_DET

.1U_0402_16V7K

USB IO Port

47U_1206_6.3V6M

9
1
8
3
7
2
6
4
5
10

USB3TP1_RC_CON

C623 1

2 0.1U_0402_10V7K

USB3TP1_C

1

2

USB3TP1_RC_CON

C621 1

2 0.1U_0402_10V7K

USB3TN1_C

4

3

USB3TN1_RC_CON

+5V_USB_P1

For ESD request
MD74

9

USB3TN1

USB3RN1_RC_CON
USB3RP1_RC_CON
USB3TN1_RC_CON
USB3TP1_RC_CON

DLW21SN670HQ2L_4P
@ R555 1

2 0_0402_5%

@ R560 1

2 0_0402_5%

1
2
3
4

RR+
TT+

8
7
6
5

VCC
GND
DD+

USB20_P1_CONN
USB20_N1_CONN

+5VDX_WALKPORT

AZ1065-06Q.RDG_MSOP8
+5VDX_WALKPORT
@ R1167 2

1 100K_0402_5%

R1164 2

1 100K_0402_5%

C962
10U_0603_6.3V6M
USB_ILIM_SEL

USB_ILIM_SEL

ML46

3

USB3RN1_RC_CON

1

2

USB3RP1_RC_CON

USB1_PWR_EN_EC

2

SN74AHC1G32DCKR_SC70-5

2

9
9
9

P

1

INA

O

4

USB_EN

USB_EN

IN

2
3

34

4
5

R1165

2

USB_PS_CTL1

6
7
8

1 100K_0402_5%

MODE

FAULT#

STATUS#

DM_OUT
DP_OUT

DM_IN
DP_IN

ILIM_SEL
EN

ILIM_LO
ILIM_HI

CTL1
CTL2
CTL3

GND
GPAD

12
9
11
10

SW_USB20_N1
SW_USB20_P1

14
17

2

1

1

0

DCP_Auto

0

1

1

1

DCP_Auto

+5VDX_WALKPORT
30

1

1

1

0

SDP

1

1

1

1

CDP

USB1_CTL1

R1213

2

1 100K_0402_5%

@ R1166

2

1 0_0402_5%

2

15
16

TPS2543RTER_QFN16_3X3

0

C963
.1U_0402_16V7K

R1118
48.7K_0402_1%

USB_ILIM_SEL
USB_EN

OUT

R1117
22.1K_0402_1%

ILIM_SEL

13

USB20_N1
USB20_P1

INB

+5VDX_WALKPORT

CTL3

USB_OC1#

G

30

USB1_PWR_EN

0.1U_0402_10V7K

3

9

5

1
U699

CTL2

2

+5V_USB_P1

1
@ C1289

2 0_0402_5%

2

CTL1

2

US1

+3VALW

DLW21SN670HQ2L_4P
@ R565 1

1

2.1A / Channel
+5VDX_WALKPORT

1

4

USB3RP1

2

USB3RN1

9

1

9

30

1

USB_PS_CTL1

+5VDX_WALKPORT

2A / Channel
@ R888 1

2 0_0402_5%

C1172
10U_0603_6.3V6M
+5VDX_WALKPORT

ML52

3

9

9

USB20_N0

1

USB20_P0

4

1

2

4

3

2

1

2

2

C1173
.1U_0402_16V7K

+5V_USB_P0

USB20_N0_CONN

3

1

3

US2

1
2
3
4

USB20_P0_CONN
8

WCM2012F2S-900T04_0805

USB0_PWR_EN

USB0_PWR_EN

GND VOUT
VIN VOUT
VIN VOUT
EN
OC

8
7
6
5

USB_OC0#

9

G547I1P81U_MSOP8
@ R889 1

2 0_0402_5%

@ R891 1

2 0_0402_5%

C1108
0.1U_0402_10V7K

9

USB3TN0

USB3TP0

1

USB3TN0

1

2
2

USB0_PWR_EN

USB CONN

ML53

1

USB3TP0_C

2

4

USB3TN0_C

3

USB3TP0_RC_CON

+5V_USB_P0

USB3TN0_RC_CON
JUSB2

C1107
0.1U_0402_10V7K

1
2
3
4
5
6
7
8
9

DLW21SN670HQ2L_4P
USB20_N0_CONN
USB20_P0_CONN
@ R890 1

2 0_0402_5%
USB3RN0_RC_CON
USB3RP0_RC_CON

@ R893 1

2 0_0402_5%
USB3TN0_RC_CON
USB3TP0_RC_CON

ML54
9

USB3RN0

USB3RN0

4

3

USB3RN0_RC_CON

9

USB3RP0

USB3RP0

1

2

USB3RP0_RC_CON

VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+

close to JUSB2
10
11
12
13

GND
GND
GND
GND

+5V_USB_P0

2.0A

ACON_TARAG-9R1391
CONN@
SP061204161

For ESD request

DLW21SN670HQ2L_4P

+5V_USB_P0

4

@ R892 1

2 0_0402_5%

1
C1109

2

MD82
USB3RN0_RC_CON
USB3RP0_RC_CON
USB3TN0_RC_CON
USB3TP0_RC_CON

1
2
3
4

RR+
TT+

VCC
GND
DD+

8
7
6
5

.1U_0402_16V7K

USB3TP0

2 100K_0402_5%

47U_1206_6.3V6M

9

R1217 1

1
C1110

2
4

USB20_P0_CONN
USB20_N0_CONN

AZ1065-06Q.RDG_MSOP8

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P23-USB 3.0 IO CONN
Size

A

B

C

D

Document Number

Rev
1.0

LA-9262P
Date:

Sheet

Friday, April 19, 2013
E

25

of

45

A

B

C

D

E

F

G

H

SW1
EVQP3S01K_4P

2

1

2

3

4

Batman 2
+3VS

LED1

1

C1122
.1U_0402_16V7K

BATT_LED_LV1

R910

2

1 820_0402_5%

2

1

27-11-T1D-CP1Q1RY-3C_WHITE
LED2
@ Q359A
BATT_LED_LV2

R911

2

1 820_0402_5%

2

1

1

6

BATMAN_CLK
27-11-T1D-CP1Q1RY-3C_WHITE
LED3
+3VALW

+5VA

BATT_LED_LV3

Q354
AO3419L_SOT23-3
D

S

3

1

R912

2

1 820_0402_5%

BATT_LED_LV4

6

PCH_SMLCLK

2
0_0402_5%
@ Q359B 3

BATMAN_DATA

4

R913

2

1 820_0402_5%

2

1

BATT_LED_LV5

R916

2

1 820_0402_5%

2

1

2

@ R1351

0_0402_5%

+3V_BATMAN

1

27-11-T1D-CP1Q1RY-3C_WHITE
+3V_BATMAN

+5VA
+3VALW

+3V_BATMAN

RP14

+5VA

1
2
3
4

Q355
AO3419L_SOT23-3
D

S

3

1

8
7
6
5

BATT_LED#_LV1_Q
BATT_LED#_LV2_Q
BATT_LED#_LV3_Q
BATT_LED#_LV4_Q

+3VLP
+RTCVCC

BATT_LED_LV2

@ R1349

2

1 0_0402_5%

@ R1348

2

1 0_0402_5%

1

2

@
C1294
0.1U_0402_10V7K

BATMAN_CLK

@ R1347 1

2 2.2K_0402_5%

BATMAN_DATA

@ R1346 1

2 2.2K_0402_5%

+3V_BATMAN
U714

11

5

100K_0804_8P4R_5%

2

BATT_LED#_LV2

4

2

G

30

2

3

10

BATT_LED#_LV2_Q
BATMAN_DATA

Q316B
DMN66D0LDW-7_SOT363-6

6

@ Y3
BATMAN_X1

1

2

BATMAN_X2

BATMAN_CLK

32.768KHZ_7PF_Q13FC1350000200

1
+3VALW

+5VA

Q356
AO3419L_SOT23-3
D

S

1

2

1

@
C1295
7P_0402_50V8C

2

@
C1296
7P_0402_50V8C

7

BATMAN_X1

14

BATMAN_X2

15

@

VCC
INTA

NC
NC
NC
NC
NC
NC
NC
NC

SQW/INTB
SDA
SCL
X1

GND
GND

X2

12
1
4
5
8
9
13
16

2

3
17

1337GNLGI8_QFN16_3X3

BATT_LED_LV3

2

3

7,19,30

DMN66D0LDW-7_SOT363-6

27-11-T1D-CP1Q1RY-3C_WHITE
LED5

BATT_LED#_LV1_Q

Q316A
DMN66D0LDW-7_SOT363-6

1

7,19,30

PCH_SMLDATA

BATT_LED_LV1

2

1

1
@ R1350

2
BATT_LED#_LV1

1

27-11-T1D-CP1Q1RY-3C_WHITE
LED4

G

30

2

1

DMN66D0LDW-7_SOT363-6

5

BATBTN#

2

30

BATT_LED#_LV3

1

6

2

G

30

BATT_LED#_LV3_Q

Q318A
DMN66D0LDW-7_SOT363-6

+3VALW

+5VA

Q357
AO3419L_SOT23-3

3

3

D

S

1

BATT_LED_LV4

5

3

BATT_LED#_LV4

4

3

2

G

30

BATT_LED#_LV4_Q

Q318B
DMN66D0LDW-7_SOT363-6

+5VA

+5VA

Q358
AO3419L_SOT23-3

2

+3VALW

2

6

1

2

1

BATT_LED_LV5

G

BATT_LED#_LV5

1

D

30

3

S

R920
100K_0402_5%

Q320A
DMN66D0LDW-7_SOT363-6
4

4

2011/06/02

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2013/10/28

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size

Date:
A

B

C

D

E

F

G

P24-BAT LED

Document Number

LA-9262P

Friday, April 19, 2013

Rev
1.0
Sheet

26
H

of

45

A

B

C

D

E

MLK IC :
20m ohm
500m A
Intel :
532m ohm
62m A

+5VA

+3VS_TPM

3

TPM_PWREN

1 100K_0402_5%

CT

VBIAS

GND
GND

+3VS_TPM

02-0320

7
8

@ R1392 1

6

2 0_0603_5%

@ C1297 1

1

2 2200P_0402_25V7K

5
9

2

+3V_PCH
@
C1298
0.1U_0402_10V7K

@ C1300

2

1 0.01U_0402_16V7K

+3VALW

04-0326
8,29,30,34,38

+3VS

1

PM_SLP_SUS# R1183

PM_SLP_SUS#

2 10K_0402_5%

PM_SLP_SUS#_R

+3VS_TPM

+3VALW

+3VALW
@ R1393 1

2 0_0603_5%

8

@ R1382 1

TOUCH_EN

2 0_0402_5%

TOUCH_EN_R

1

2

+3VALW
C1199
1U_0402_6.3V6K

2

R1160

1 100K_0402_5%

2

1 100K_0402_5%

+5VS

5VS_EN

MLK IC :
20m ohm
600m A

U717

1
2

+5VA

8,18,27,30,37,38

1

@ R1146

PM_SLP_S3#

2 0_0402_5%

4

+5VA

+5VA
8,20,35

1

SIP

2

3

5VS_EN

C1161
0.1U_0402_10V7K

+3VS
+1.5VS

@ R1306
@ R1305

1
1

C1280

1

5

AUDIO_PWREN

6
7

2 0.01_0603_1%
2 0_0603_5%

VIN1
VIN1

VOUT1
VOUT1

ON1

CT1

VBIAS

GND

ON2

CT2

VIN2
VIN2

VOUT2
VOUT2

2 0.1U_0402_10V7K

GPAD

14
13
12

4
5
6
7

2 2200P_0402_25V7K

C1281 1

2 2200P_0402_25V7K

2

9
8

+1.5VS_3.3VS_AUDIO

2

15

2

+1.05VA

1

2

2 0_1206_5%

@ R1247 1

PM_SLP_S3#

2

R1250

+1.05VS

C1243
0.1U_0402_10V7K

3

VCC

2

15
17

@ R1190 1
@ C1244 1

16

EN

GND

1

6
7
8

BLEED
SR

1

Delay

2 0_0402_5%

3

+5VA

4

SENSOR_EN

SENSOR_EN

1 100K_0402_5%

2 2200P_0402_25V7K

15

1

5
6
7

VIN1
VIN1
ON1

2 0_0402_5%

PM_SLP_S3#

R1388

8,18,27,30,37,38

2

1 220K_0402_5%

WLAN_EN

2

+1.05VA

+1.05VDX_MODPHY
Q360
SiSA12DN-T1-GE3_POWERPAK8-5

+1.05VA

8,23

ON2

CT2

VIN2
VIN2

VOUT2
VOUT2

5

4

2

2

30

3
1

R1379

1

2 330_0402_5%

C1257

1

2 2200P_0402_25V7K

10

C1248

1

2 2200P_0402_25V7K

9
8

@ R1319 1

C1219
0.1U_0402_10V7K

6

R1380

1

2 330_0402_5%

+3VALW

1
2

3

EN_WLANPWR

WLAN_EN

3

+5VA

4

EN_CAM

5

+5VA
8

+3VALW

EN_CAM

1

+3VALW

C1209
10U_0603_6.3V6M

2

C1203
0.1U_0402_10V7K

1
C617
0.1U_0402_10V7K

6
7

VIN1
VIN1

VOUT1
VOUT1

ON1

CT1

VBIAS

1

ON2

CT2

VIN2
VIN2

VOUT2
VOUT2

2

DII-DMN65D8LW-7

@ R1226 1

12

C1202

1

2 2200P_0402_25V7K

10

C1292

1

2 2200P_0402_25V7K

9
8

@ R1128 1

+3VS_CAM

1 100K_0402_5%

2

1

MLK IC :
20m ohm
300m A
Intel :
41m ohm
800m A

TPS22966DPUR_SON14_2X3

1 100K_0402_5%

EN_CAM

C1227
0.01U_0402_16V7K

+1.05VDX_MODPHY

1

3

PM_SLP_SUS

GND

OUT Y

4

RUN_ON#
MPHY_PWREN#

D

2
G

3

SN74AUP1G04DCKR_SOT23-5

2
D

2
G

S

@ Q4
RUN_ON#

S

2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

C

D

G

@ Q5
PM_SLP_SUS

D

S

2
G

3

S

4

Title

P25-DC/DC Interface
Size

Document Number

Rev
1.0

LA-9262P
Date:

A

D

2

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

@ Q34
RUN_ON#

DII-DMN65D8LW-7

4

2

@ R298
470_0402_5%

+3V_D

OUT Y

DII-DMN65D8LW-7

@ Q39

GND

SN74AUP1G04DCKR_SOT23-5

+VCCP_D

5

DII-DMN65D8LW-7

VCC

IN A

1

@

DII-DMN65D8LW-7

2

PM_SLP_S3#

NC

+1.5VS_D

1

4

3

1

+3V_PCH

@ R297
470_0402_5%

2

@ R296
470_0402_5%

3

U710

5

1

@

IN A

2

+1.05VS

+1.5VS

2
+3VALW

+1.05VDX_MODPHY_D

2

02-0320

MPHY_PWREN

@ R300
470_0402_5%

PM_SLP_SUS#

+3VS_CAM

2 0_0603_5%

15

GPAD

C1215
0.1U_0402_10V7K

2 0_0603_5%

1

2

R1162

2

14
13

3

3

S

VCC

1

+3VS_NGFF

11

GND

2

+3VS_NGFF

02-0320

1

1

2

+3VALW

NC

2 0_0603_5%

MLK IC :
20m ohm
7m A
Intel :
2570m ohm
7m A
U718

Discharge

U713

MLK IC :
20m ohm
160m A
Intel :
73m ohm
550m A

+3VNS_PWR

02-0320

2

NGFF_PWREN

2

SI1553CDL-T1-GE3_SC70-6

@ R1169

1

C1256
1U_0402_6.3V6K

15

GPAD

BAT54CW-7-F_SOT323-3

1

5

Q362

1

C1159
10U_0603_6.3V6M

C1228
0.1U_0402_10V7K

2
G

+3VS

11

GND

MPHY_PWREN#

MPHY_PWREN

C1200
1U_0402_6.3V6K

2

C1158
.1U_0402_16V7K

Q361

1
2
3

MLK IC :
5m ohm
1840m A
Intel :
6m ohm
1840m A

4

1

1

2

8

1

MLK IC :
20m ohm
20m A
Intel :
73m ohm
?m A

D115

B+

D

+3VS_TOUCH

2

12

CT1

VBIAS

SENSOR_EN

1

MPHY_PWREN

+3VS_TOUCH

MLK IC :
20m ohm
??m A
Intel :
106m ohm
310m A

14
13

VOUT1
VOUT1

1

2 0.01U_0402_16V7K

B+

1

2 0_0603_5%

02-0320

+3VALW

Change circuits design for meet Intel timing, ramp time = 10uS for rising and falling

R1381
10K_0402_5%

1

@ R1320 1

2 0_0402_5%
2 1000P_0402_25V8J

@ R1191 1
@ C1242

C1240
10U_0603_6.3V6M

MLK IC :
5m ohm
3414m A
Intel :
5m ohm
3414m A

NCP4545IMNTWG_QFN18_3X3

3

C1278

TPS22966DPUR_SON14_2X3

2

VOUT
VOUT
VOUT

10
9
8

C352
1U_0402_6.3V6K

2

+3VS

1
2

+3VALW

@

VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN

VOUT2
VOUT2

2 2200P_0402_25V7K

U716
+3VALW

+5VA
U673

VIN2
VIN2

GPAD

+5VA

4
5
9
10
11
12
13
14
18
19

CT2

1

11

GND

ON2

C355

C1254
0.1U_0402_10V7K

8,22

1

VBIAS

12

2 0_0603_5%

1

+1.05VS

R1355

CT1

@ R1326 1

+5VA

MLK IC :
20m ohm
30m A

2

@
C1241
0.1U_0402_10V7K

ON1

1

14
13

C1162
10U_0603_6.3V6M

8,18,27,30,37,38

1

VOUT1
VOUT1

1

C1163 1

11
10

+1.05VA

3

VIN1
VIN1

TPS22966DPUR_SON14_2X3

TPS22966DPUR_SON14_2X3

02-0320

1
2

TOUCH_EN_R

+5VS
@ R1027

02-0320

U719

06-0328

TPS22965DSGR_SON8_2X2

TPM_PWREN

+3V_PCH

PM_SLP_SUS#_R

1

2

@ R1394

1

ON

4

+5VA

VOUT
VOUT

2

TPM_PWREN

VIN
VIN

1

8

U722 @

1
2

3

2

PM_SLP_SUS# : Deep Sx Indication
When asserted (low), this signal indicates PCH
is in Deep Sx state where internal Sus power is
shut off for enhanced power saving.
When deasserted (high), this signal indicates exit from
Deep Sx state and Sus power can be applied to PCH

10-0328

+3VALW
@
C1299
0.1U_0402_10V7K

1

1

Friday, April 19, 2013

Sheet
E

27

of

45

A

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FD5

@

FIDUCIAL_C40M80

FIDUCIAL_C40M80

1

C

D

E

FD6

@

1

1

FIDUCIAL_C40M80

FD4

@

1

FD3

@

1

FD2

@

1

1

FD1

B

@

FIDUCIAL_C40M80

8

KB_DET#

KSI[0..7]

PCB Screw Hole

@ C1174
@ C1175
@ C1176
@ C1177

1
1
1
1

2
2
2
2

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

KSO10
KSO11
KSO9
KSO14

@ C1178
@ C1179
@ C1180
@ C1181

1
1
1
1

2
2
2
2

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

KSO6
KSO7
KSO4
KSO5

@ C1182
@ C1183
@ C1184
@ C1185

1
1
1
1

2
2
2
2

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

1

KSI[0..7]

KSO[0..16]

H17
H_2P0N
@

30

KSO[0..16]

30

INT_KBD Conn.

H8

1

H_2P3
@

1

H3
H_4P0
@

H16
H_2P0X2P5N
@

1

H14 NUT
H_3P2
CONN@

1

1

H6
H_2P3
@

1

H5
H_2P3
@

1

H1
H_2P3
@

KSO13
KSO15
KSO16
KSO12

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10
CAPS_LED

1

@

JKB1

1 : Diagnotisc

H26
H_3P3

30 : Diagnotisc

1
1
1
1

KSI2
KSI4
KSI6
KSI7

@ C1186
@ C1187
@ C1188
@ C1189

KSI0
KSI3
KSI1
KSI5

@ C1190 1
@ C1191 1
@ C1192 1
@ C1193 1

2
2
2
2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1

GND
GND

31
32

ACES_50699-03041-001
CONN@
DC011112270

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

LTCX0044300

2

2

PCB Screw Hole for CPU (NUT)
H10

+3VS

+5VS

30

3

CAPS_LED#

1
DII-DMN65D8LW-7
Q326

@ C1078 1

KSO0

1

2

CAPS_LED

R943
820_0402_5%

100K_0402_5%

2

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

1

2

1

1

2
2
2
2

G

1
1
1
1

D

@ C1194
@ C1195
@ C1196
@ C1197

D

KSO2
KSO1
KSO3
KSO8

S

H_3P2
CONN@

G

H_3P2
CONN@

H12

1

S

3

R989
H11

Q329
AO3419L_SOT23-3

+5VS

2

1

H_3P2
CONN@

1

H9
H_3P2
CONN@

2 100P_0402_50V8J
2 100P_0402_50V8J
2 100P_0402_50V8J
2 100P_0402_50V8J

1

2 100P_0402_50V8J

2

PCB Screw Hole for mSATA

@ C1160
0.1U_0402_10V7K

1

H13
H_4P5N
CONN@

+5VS

+5VS_KBL

20mil

3

2

JBL1

1
2
3
4

KB_LED_PWM#

1

8

F1
0.75A_24V_1812L075-24DR~OK

R944 1

KB_BL_DET

2 47K_0402_5%

2

+5VS_KBL

5
6

R945

2

100K_0402_5%

30

D

S

2

KB_LED_PWM

LED Maximum Current is 300mA

3

GND1
GND2

HB_A810420-SBHR22
CONN@

1

C1059
10U_0603_6.3V6M

1

2

1
C1153
1U_0603_10V6K

3

1

1
2
3
4

Q311
DII-DMN65D8LW-7

G

RTC Battery
+RTCBATT

Intel recommend for EMI

Intel recommend for EMI

Intel recommend for EMI

+RTCBATT
+0.675VS

2
1

1
2
G1
G2

1

2

1
MC1267
0.1U_0402_10V7K

2

ACES_50271-00201-001
CONN@

W=20mils
3

W=20mils

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

B+

B+

1

1

B+

JBT1

1
2
3
4

RTCR1
1K_0402_5%

+3VLP

+0.675VS

1
MC1268
0.1U_0402_10V7K

1
MC1269
0.1U_0402_10V7K

2

2

1
MC1270
0.1U_0402_10V7K

2

1
MC1271
0.1U_0402_10V7K

2

MC1272
0.1U_0402_10V7K

2

MC1273
0.1U_0402_16V7K

2

1
MC1274
0.1U_0402_16V7K

2

MC1275
0.1U_0402_16V7K

2

RTCD1
BAT54CW-7-F_SOT323-3

1

+RTCVCC

W=20mils

2

+RTCVCC

Intel recommend for EMI

4

12-0328
+3VS

CH95
1U_0402_6.3V6K

1

1

2

4

@
CLRP3
SHORT PADS

+3VS

1

1
MC1276
0.1U_0402_10V7K

2

MC1277
0.1U_0402_10V7K

2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P26-SCREWH/KB/RTC
Size

A

B

C

D

Document Number

Rev
1.0

LA-9262P
Date:

Sheet

Friday, April 19, 2013
E

28

of

45

5

4

3

2

1

1

+3VALW

2

@
R1281
1K_0402_5%

6

+3VALW
+3VALW

1

2

PBTN_SW#

GND

OUT Y

4

U688

1

2

@
R1282
100K_0402_5%

+3VALW

IN A
@ R1283

3

+3VALW

1
2
3

2

10K_0402_5%
SN74AHC1G04DCKR_SOT23-5

2

8,18,20,30

1

5

@

CP
GND
D

@ U689

6
5
4

C
VCC
Q

30,32,33

1

ACIN

2

SHUTDWN#

NC7SZ175P6X_SC70-6
STARTUP_LATCH_SET

1

VR_A_ENABLE

2

PM_SLP_SUS#

8,27,30,34,38

0_0402_5%

1
+3V_PCH

C1260
@
0.01U_0402_16V7K

@
Q349B
DMN66D0LDW-7_SOT363-6

2
1

5

2

@ R1286

1

EC_SHUTDOWN

4

@
R1285
0_0402_5%

30

4

O
INB

3

@ T262

@ R1284

INA

3

SN74AHC1G32DCKR_SC70-5

D

@
C1259
0.1U_0402_10V7K

5

2

PBTN_SW

VCC

P

@

NC

1

U687

1

@
Q349A
DMN66D0LDW-7_SOT363-6

G

+3VALW
D

2

SMC_SHDN

1

3.3K_0402_5%

2

@
R1287
100K_0402_5%

C

C

+3VS

+3V_PCH

1

1
+3V_PCH

@
C1261
0.1U_0402_10V7K

O

1

2 0_0402_5%

+3V_PCH

4

DELAY_VR_AND_ALL_SYS

@ C1262

1

IN2

SN74AHC1G08DCKR_SC70-5

5

2

HWPG

@ R1290

@
U690

IN1

@

1

@ R1292

IN1

4

O

2

PCH_PWROK_EC

1

ALL_SYS_PCH_PWROK_EC

IN2

2

SYS_PWROK

+1.05VS_VCCST

8,18

1K_0402_5%

1.05VS_PG

SN74AHC1G08DCKR_SC70-5

8,18,30
+3V_PCH

1

3

30

2

0.1U_0402_10V7K

U691

P

1

2 0_0402_5%

3

30

1

G

@ R1291

IMVP_VR_PG

G

10,40

P

5

2

2

1

@ R1289
10K_0402_5%

@
R1293
0_0402_5%

U672

1

2

30

1.05VS_PG_EC

1

2 0_0402_5%

2

A
Y

3
@ R1294

1

VCC

R1132
10K_0402_5%

5
2

@ R1353

NC

4

1.05VS_VCCST_PG

10,18

GND

2 0_0402_5%

74AUP1G07GW_TSSOP5
@ R1295

1

2 0_0402_5%

@ R1296

1

2 0_0402_5%

PCH_PWROK

8

B

B

Touchpad CONN
+3VS_TOUCH

2

1
1

R886
10K_0402_5%

2

JFAN1

4
3
2
1

2

D81
SDMK0340L-7-F_SOD323-2

2

3

1

4
3
2
1

G2
G1

6
5

CVILU_CI4304M2HR0-NH
CONN@
SP02000Y500

TP_INT#_R

A

S

1

TP_INT#

D

5

30 SYSTEM_FAN_PWM
30 SYSTEM_FAN_FB

R1299
100K_0402_5%
G

@ Q364

A

2

1

1

+3VS_TOUCH

2

ACES_51524-00801-001
CONN@

C1102
0.1U_0402_25V6K

+5VS

+3VS

@ DE1
PESD5V0U2BT_SOT23-3

1

@ DE2
PESD5V0U2BT_SOT23-3

C1225
1U_0402_6.3V6K

2

1

2

3

2

3

TP_DATA
TP_CLK

1

R1103
10K_0402_5%

TP_INT#_R
30
30

1
2
3
4
5
6
7
8
GND
GND

2

1
2
3
4
5
6
7
8
9
10

I2C1_SDA_TP
I2C1_SCK_TP

R884
10K_0402_5%

JTP1
19
19

1

+3VS_TOUCH

DII-DMN65D8LW-7
R1387

1

2
0_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P27-TP / FAN/PWERGD
Size

5

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

Friday, April 19, 2013

Sheet
1

29

of

45

4

8,18,22,23

1 100K_0402_5%
1

I2C0_SCK

PLT_RST#

8

C

@ Q352B 3

PCH_SMLDATA

4

I2C0_SDA

8

DMN66D0LDW-7_SOT363-6

1

2

@ R1308

D9
E12
E13
D12
D13
C12
C13
D10
J13
J12
H12
H13
H10
H9
G9
G10
G13
G12
F13
F12
F10
F9
E10
E9
E8
D8

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16

5

2
0_0402_5%

N5
M5
K13
N6
M6

PLT_RST#
EC_RST#

DMN66D0LDW-7_SOT363-6

1

0_0402_5%

+3VS

8

M2
L2
M3
K4
N3
M4
K5
N4

EC_SLP_S0#

8 EC_RUNTIME_SCI#
8,22 PM_CLKRUN#

.1U_0402_16V7K

1

@ R1307

PCH_SUSWARN#

RP15

1
2
3
4

8
7
6
5

PCH_SMLCLK
PCH_SMLDATA
TP_CLK
TP_DATA

32,33
32,33
7,19,26
7,19,26

A8
A7
B8
A6

EC_SMB_CK1
EC_SMB_DA1
PCH_SMLCLK
PCH_SMLDATA

EC_SMB_CK1
EC_SMB_DA1
PCH_SMLCLK
PCH_SMLDATA

4.7K_8P4R_5%

1 10K_0402_5%

WAKE_PCH#

20

ROTATION_LOCK_SW#

25
29
20

AUD_MUTE# : Internal PU on Codec Chip (+3VS)

+3VALW_EC

Deep S3 support
Default (No Function)

B

R229 2
R230 2

1 10K_0402_5%
1 10K_0402_5%

R1386 2

EC_SMB_CK1
EC_SMB_DA1

1 10K_0402_5%

2

1

2 0_0402_5%

1

@ R1297

1

Pin J6 is VCC_0 :
Power supply for 51ON power management

Rb

R225
270K_0402_1%

01-0320

20
8
8

EC_SMI#
PS_ID
8 EC_WAKE_SCI#
ROTATION_LOCK_SW#
26 BATT_LED#_LV5
USB_ILIM_SEL
SYSTEM_FAN_FB
VOLUME_UP_SW#
18 EC_TX
18 EC_RX
AUD_MUTE#
SUSACK#
WAKE_PCH#

20 VOLUME_DOWN_SW#
8,23 SUSCLK_R

1

ROTATION_LOCK_SW#

VOLUME_UP_SW#

WAKE_PCH#

J5
N9
L13
K6
N7
M7
N8
K8
M11
N11
K10
K9
N12
M13
L12

J1
K1

VOLUME_DOWN_SW#
EC_CRY2

2

@ R253
0_0402_5%

INVT_PWM/PWM0/GPIO0F
BEEP#/PWM1/GPIO10
FANPWM0/GPIO12
ACOFF/FANPWM1/GPIO13

PWM Output
MISC

1

R607
100K_0402_5%

2

MC654
20P_0402_50V8

BATT_TEMP/AD0/GPI38
BATT_OVP/AD1/GPI39
ADP_I/AD2/GPI3A
AD3/GPI3B
AD4/GPI42
SELIO2#/AD5/GPI43

DAC_BRIG/DA0/GPO3C
EN_DFAN1/DA1/GPO3D
DA Output
IREF/DA2/GPO3E
KSI0/GPIO30
DA3/GPO3F
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
PSCLK1/GPIO4A
KSI4/GPIO34
PSDAT1/GPIO4B
KSI5/GPIO35
PSCLK2/GPIO4C
PS2 Interface
KSI6/GPIO36
PSDAT2/GPIO4D
KSI7/GPIO37
TP_CLK/PSCLK3/GPIO4E
KSO0/GPIO20
TP_DATA/PSDAT3/GPIO4F
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
SDICS#/GPXIOA00
KSO4/GPIO24
SDICLK/GPXIOA01
KSO5/GPIO25 Int. K/B
SDIDO/GPXIOA02
KSO6/GPIO26 Matrix
SDIDI/GPXIOD00
SPI Device Interface
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
GPIO5C MOSI
GPIO5B MISO
KSO10/GPIO2A
SPI Flash ROM SPICLK/GPIO58
KSO11/GPIO2B
GPIO5A SPICS#
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
CIR_RX/GPIO40
KSO16/GPIO48
CIR_RLC_TX/GPIO41
KSO17/GPIO49
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO BATT_LOW_LED#/GPIO54
SCL0/GPIO44
SDA0/GPIO45
SUSP_LED#/GPIO55
SM Bus
SCL1/GPIO46
SYSON/GPIO56
SDA1/GPIO47
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB0/GPIO14
FANFB1/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
EC_ON/GPXIOA05
EC_SWI#/GPXIOA06
ICH_PWROK/GPXIOA07
GPO
BKOFF#/GPXIOA08
WL_OFF#/GPXIOA09
GPXIOA10
GPXIOA11

GPI

XCLKI GPIO5D
XCLKO GPIO5E

1

EC_SLP_S5#

AD Input

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

2

2 10K_0402_5%

2 0_0402_5%
EC_SLP_S5#

7
32

R1354 2

1

@ R249

PM_SLP_S3#

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &

KB9012BF-A3_LFBGA128

PM_SLP_S4#/GPXIOD01
ENBKL/GPXIOD02
GPXIOD03
GPXIOD04
GPXIOD05
GPXIOD06
GPXIOD07
V18R

GND
GND
GND
GND
GND

8,18,27,37,38
+3VALW_EC

@ R604 1

2 0_0402_5%

2

C283
0.1U_0402_10V7K
D

M9
M8
M10 SENSOR_HUB_WAKE#
N10
B13
A13
B12
A12
E7
D7

ADP_I

AD_BID0
ALS_INT#_EC
AOAC_THERMAL

B10
A9
A10
B9

32,33

ALS_INT#_EC

19

@ R228 2

EAPD_R#

EAPD#

VCIN0_PH_R

J2
K2
M1
N2

USB1_PWR_EN_EC
PCH_PWR_EN

EAPD#

2 10K_0402_5%

@ R980 1

2 10K_0402_5%

CAPS_LED#

@ R990 1

2 100K_0402_5%

VCOUT0_PH#

@ R922 1

2 10K_0402_5%

1
2
3
4

8
7
6
5

+3VLP

10K_8P4R_5%

20

ECAGND
100P_0402_50V8J

1.05VS_PG_EC
29
HDA_SDO
7
1 0_0402_5%

4
3
2
1

LID_SW_IN#
VOLUME_DOWN_SW#
USB1_PWR_EN_EC
TABLET_MODE

1

EC_BATT_PRS#
@ R925 2

@ R241 1

TABLET_MODE

RP21

2

C286

B1
A1
C1
C2

EAPD_R#

Win8_BTN_SW#
SENSOR_HUB_WAKE#
BATBTN#
PBTN_SW#

1 0_0402_5%
PCH_PWROK_EC
29
AC_PRESENT
8
EC_SHUTDOWN
29
TP_CLK 29
TP_DATA 29

TP_CLK
TP_DATA

+3VALW_EC

RP16

BATT_LED#_LV1 26
ACOFF 33
EC_ENVDD
19,35
BATT_LED#_LV2 26

ACOFF

D6
E6
E5
D5
A5
B5

Analog Board ID definition,
Please see page 4.

KB_LED_PWM
28
BEEP# 20
SENSOR_HUB_WAKE#
22
SYSTEM_FAN_PWM
29

32,33

5
6
7
8

+3VALW_EC

100K_0804_8P4R_5%
VCIN0_PH

32
C

2

1

R1249

B6
B7
B4
A4
B3
A3
A2
B2
H5
N1

RP22

BATT_LED#_LV4 26
BATT_LED#_LV3 26
USB1_PWR_EN_EC
25
43.2K_0402_1%

PM_SLP_SUS#

VOLUME_UP_SW#
EC_ON_CTRL#
ALS_INT#_EC
ACOFF

8,27,29,34,38

4
3
2
1

5
6
7
8

+3VALW_EC
+3VLP
+3VALW_EC

100K_0804_8P4R_5%
TABLET_MODE

TABLET_MODE 19,20
USB1_CTL1
25
BATT_LED_COLOR_W
CAPS_LED#
28
BATT_LED_CTRL# 20
LCD_TEST 19
5VA_EN 8,34
DSP_PD#
20
PM_SLP_S4# 8,18,39

CAPS_LED#

D4
D1
D2
E2
E4
E1
F4
F2
F1

20

@ R924 2

ACIN

EC_ON

HWPG

PCH_RSMRST#
8
USB1_DET_EC#
@ R926 2
1 0_0402_5%
VCIN1_PH_R
H_PROCHOT_EC
H_PROCHOT_EC
32
VCOUT0_PH#
VCOUT0_PH#
36
BKOFF# 19
EN_WLANPWR
27
LID_SW_IN#
LID_SW_IN#
20
HWPG

VCIN1_PH

1 100K_0402_5%

C1116

2

1

100P_0402_50V8J

C1117

1

2

.1U_0402_16V7K

@ R1154 2

1 0_0402_5%

VR_ON

10,40

32

+3VALW_EC

AOAC Thermal

1

6

1

F5
G1
G5
H1
G4
H4
H2

ACIN
EC_ON
EC_ON_CTRL#
Win8_BTN_SW#
BATBTN#

AC_IN
ALW_PWR_EN
ON/OFFBTN#

ACIN
29,32,33
EC_ON 36
Win8_BTN_SW#
PBTN_OUT#

EC_PECI

8

AOAC_THERMAL

1

2

R240

L1

R927
13.7K_0402_1%

VCC_0 power plane

19

H_PECI

43_0402_5%

5

+V18R

B

R928
100K_0402_1%_TSM0B104F4251RZ

1

2

2

1 33_0402_5%

2

@ Q352A

R219
100K_0402_1%

Ra

+3VALW_EC

@ R921

1

2

2 0_0402_5%
2 0_0402_5%
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

+3VNS_PWR

PCH_SMLCLK

+3VALW_EC

32

2

R221 2

2

ECAGND

1
8
8,22
7,18,22
7,18,22
7,18,22
7,18,22
7,18,22

CLK_PCI_LPC

C285

ECAGND

AD_BID0

J8
J9
N13
J10
G2

1 @ MR226

1
1

@ R1390
@ R1391

PCH_GPIO88
PM_SLP_S0#

@ MC284

+3VALW_EC

2 .1U_0402_16V7K

+3VLP

02-0320

22P_0402_50V8J
7

Board ID
C282 1

02-0320

U34

8
8,18,36,38

2

1

AVCC

KSO3

2

AGND

2 10K_0402_5%

1

A11

@ R1032 1

1

@

VCC
VCC
VCC
VCC
VCC
VCC

PLT_RST#

2

@

C281
1000P_0402_50V7K

2 10K_0402_5%

2

2

C280
1000P_0402_50V7K

@ R929 1

2

2

C279
.1U_0402_16V7K

2

2

0_0603_5%

1

C278
.1U_0402_16V7K

@ R811

1
KSO[0..16]

1

C276
.1U_0402_16V7K

KSO[0..16]

1

C277
.1U_0402_16V7K

D

KSI[0..7]

28

+3VALW_EC

1

0_0603_5%

KSI[0..7]

28

2

L43
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA

2

02-0320

@ R216

1
+3V_PCH

3

+3VALW_EC

J7
K12
M12
K7
J4
J6

+3VALW

B11

5

C293
4.7U_0603_6.3V6K

Only for Debug using

Acordding M13_EE_Implementation_Requirements
Thermistor need place around CPU

SW2 @

20mil

L44
1
ECAGND 2
FBMA-L11-160808-800LMT_0603

3

1

4

2

PBTN_SW#
+3VS

SKQGCBE010_4P
8,18

2 0_0402_5%

HW PWR GOOD

EC_SLP_S5#

1

@ R250 1

PM_SLP_S5#

R930
10K_0402_5%

D114

2
@ D109
DB2J31400L_SOD323-2

SDMK0340L-7-F_SOD323-2
8,18,29
38
+3VLP

39

H_PROCHOT# Control citcuits need place close to CPU and VR
1

+3VLP
R1156

+3VS

U712

1

NC

VCC

1.2V_DDR_PWROK

37

1.8VS_PWROK

37

1.5VS_PWROK

U635
SN74LVC1G06DCKR_SC70-5

25

USB1_DET#

1

3
@ R941
150K_0402_1%

2 0_0402_5%

@ R1133

1

2 0_0402_5%

@ R934

1

2 0_0402_5%

@ R982

1

2 0_0402_5%

2

A

2

H_PROCHOT_EC

29

26

OUT Y

4

USBCHG_DET_D

BATBTN#

1

BATBTN#

2

EC_ON_CTRL#

SN74AUP1G04DCKR_SOT23-5

D85
SDMK0340L-7-F_SOD323-2
8,18,20,29

BAT54CW-7-F_SOT323-3

A

1

36

PBTN_SW#

1

PBTN_SW#

2

C1118
0.01U_0402_16V7K

2

3

1

2

G

Y

NC

4

H_PROCHOT#

HWPG

D84
SDMK0340L-7-F_SOD323-2

IN A
GND

HWPG

1

5

P

5

1

2

3

2

2
@
R265
0_0402_5%

A

2

USBCHG_DET_PWR_EN#
D104
@ C655
.1U_0402_16V7K

2

@ R931

USB1_DET_EC#

1

R608
100K_0402_5%

1

2

C656
47P_0402_50V8J

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

Title

P28-EC ENE-KB9012

1

5,32

1.05VA_PG

2

VR_HOT#

R939
100K_0402_5%

2

1

40

100K_0402_5%

1

+3VALW_EC

1

1.05VS_PG

2

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size

5

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

Friday, April 19, 2013

Sheet
1

30

of

45

5

4

3

B+

NVDC
CHARGER
BQ24715

DC IN
D

2

1

+3VLP

+3VLP
G920

D

Page 36

Page 33

+5VA

+5VA: TDC:1106mA
TPS62130
Page 34

Battery
(2S3P)

+5VDX_WALKPORT: TDC:2.1A
TPS62130

+5VDX_WALKPORT

Page 34

+3VDX

+3VDX: TDC:393.6mA
TPS62130
Page 35

C

+3.3VDX_SSD: TDC:637mA
TPS62130

C

+3.3VDX_SSD

Page 35

+3VALW

+3VALW: TDC:1161mA
TPS62130
Page 36

+1.05VA: TDC:3754mA
TPS51362

B

+1.05VA
Page 38

+1.35V_DDR: TDC:3883mA
+0.675VS: TDC:700mA
RT8207M
Page 39

+1.5VS: TDC:20.3mA
TPS62150

B

+1.2V_DDR
+0.6VS

+1.5VS
Page 37

+1.8V_DDR

+1.8VS: TDC:11.9mA
TPS62140
Page 35

+VCC_CORE
TDC: 10A
TPS51622

A

+VCC_CORE

A

Page 37 38
Security Classification
Issued Date

Compal Electronics, Inc.

Compal Secret Data
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P29-PWR_Block_Diagram
Size

5

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

Friday, April 19, 2013

Sheet
1

31

of

45

C

JDCIN1

+3VALW

PSID Part (39.1)

PSID

DCIN_GND

VIN

PL101
HCB2012KF-121T50_0805

1

ADPIN

2

S
G

2

1

1
2

1

30

1

2

1

2

+3VALW
+5VA

PR104
10K_0402_1%
PQ102
MMST3904-7-F_SOT323

3

E

1

PR106
15K_0402_1%

PS_ID

Erp lot6 Circuit

asserts H_PROCHOT# when adaptor is
unplugged, keep low for 10ms
till SW PROCHOT# is issued by EC

keep DNP in BOM since Dell 45W
adaptor has no hiccup mode
VIN
1

H_PROCHOT#

1

2

3 2

2

@

1

4

2

6

2

@

@
PR121

1

@ PC113
0.1U_0402_25V6

1

4

5

@ PR119
200K_0402_1%

1
PR124

2

6

2
1

1M_0402_1%

2

PR115
0_0402_5%

30,33

PQ105A
2N7002KDWH_SOT363-6

1U_0603_10V6K

PR125

EC_BATT_PRS#

PD104
SM24_SOT23

5

PQ103A
2N7002KDWH_SOT363-6

+3VALW

2

2

1

1

2
PR112
100_0402_5%

1

3

1

2

1

3

PC115

1
PR113
100K_0402_1%

2

2

CLK_SMB
DAT_SMB
BATT_PRS
SYS_PRS

PR120

1M_0402_1%
PQ105B
2N7002KDWH_SOT363-6

PR111
100_0402_5%

1

+3VALW
PR126
10K_0402_1%

100K_0402_1%

30,33

2

2

@

ACIN

1

EC_SMB_DA1

VIN
1M_0402_1%

11
10

30,33

PR123

1

JBATT1

EC_SMB_CK1

2

PR109
100_0402_5%

1

2

3

29,30,33

1M_0402_1%

PQ103B
2N7002KDWH_SOT363-6

5,30,32

2

PD103
SM24_SOT23

PR122
3.3K_1206_5%~D

Battery protection:

1

1

1

PC108
100P_0402_50V8J

2

2

1

BATT++
PC107
1000P_0402_50V7K

BATT+

1

2

PC106
0.01U_0402_25V7K

2

1

PC105
100P_0402_50V8J

2

1

EMI Part (35.33)

9
8
7
6
5
4
3
2
1

B

2

@ PR107
10K_0402_1%

PL103
FBMA-L11-453215-800LMA90T_1812

2

9
8
7
6
5
4
3
2
1

C

2

1

PSID-3

PSID-2

PSID-1

BATT++

2

PQ101
FDV301N_NL_SOT23-3

EMI Part (35.33)
BATT+

3

D

1

PR105
100K_0402_1%

1
2

1
2

PR103
33_0402_5%

1

PC104
100P_0402_50V8J

2

PC103
1000P_0402_50V7K

1

PC102
100P_0402_50V8J

2

1

PC101
1000P_0402_50V7K

2

1
2

2

HCB2012KF-121T50_0805

PL104

1

EMI solution for adaptor
without ferrite bead
20120507

PC109
0.1U_0402_25V6

PL102
BLM18BD102SN1D_0603
1

GND
GND

PR102
2.2K_0402_5%

1
2
3
4
5
6
7

2

1
2
3
4
5
GND1
GND2

D

2

B

1

A

@

JBATT battery connector

Delay adaptor OC H_PROCHOT#
2ms while hybrid power
transition

Adaptor protection:

Adaptor protection:

if battery removed, adaptor only,
then trigger the H_PROCHOT#,
keep DNP in BOM since battery can not
be removed by end user

if CP and IPCC failed, adaptor output
=rating 100% and over load 20W
then trigger the H_PROCHOT# by EC
30,33

@

S

30

@

VCIN0_PH

1

VCIN1_PH

2

30

PR118
110K_0402_1%

PH101
100K_0402_1%_TSM0B104F4251RZ

1

1

1U_0603_10V6K

3

G

1

D

2

1

1

PR117
13.7K_0402_1%

2

2

PC112
0.1U_0402_25V6

1

PQ104
2N7002KW_SOT323-3

1

@ PC114

2

2

H_PROCHOT_EC

PC116
0.01U_0402_25V7K

1

160K_0402_1%

100K_0402_1%

G

2

5,30,32

PR116
10K_0402_1%

PR108

S

2

PQ106
2N7002KW_SOT323-3

1

D

3

PR110

30

+3VALW_EC

H_PROCHOT#
H_PROCHOT#

2

Recovery at 80+-3 degree C

ADP_I

EC_BATT_PRS#

1

3

2

5,30,32

PH101 under CPU bottom side :
CPU thermal protection
@88+-3 degree C

2

3

SMART
Battery:
1.GND
2.GND
3.BAT_ALERT
4.SYS_PRES
5.BATT_PRS
6.DAT_SMB
7.CLK_SMB
8.BATT++
9.BATT++

@
ECAGND

30

4

4

Compal Secret Data

Security Classification
Issued Date

2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size

Date:
A

B

C

Compal Electronics, Inc.
P30-PWR_DCIN/BATT CONN/OTP

Document Number

Rev
1.0

LA-9262P
Friday, April 19, 2013

Sheet
D

32

of

45

5

4

3

2

PQ201

1
2

PC205
10U_0805_25V6K

1
2

PC204
10U_0805_25V6K

PC202
0.1U_0402_25V6
2
1

PC203
2200P_0402_50V7K
2
1

PC206
2200P_0402_50V7K
2
1

CSSN_1

CSSP_1

1

D

PC213
1
2

VCC

REGN

2

16

PR211
3

CMSRC

CMSRC

BTST

17

BTST 1

1U_0603_10V6K
PD202
BAT54HT1G_SOD323-2
5

20

VCC

2

PU201

1

1
PC214

2

2
PD201

RB751V-40_SOD323-2

1

2

PQ203

C

B+

2.2_0603_5%
4

ACDRV

HIDRV

18

PC217
10U_0805_25V6K
1
2

4

CHG_UGATE
1

ACDRV

@

6

ACDET

keep DNP in BOM since Dell 45W
adaptor has no hiccup mode

30,32

EC_SMB_DA1

30,32

EC_SMB_CK1

EC_SMB_DA1

8

EC_SMB_CK1

9

ACDET

PHASE

SDA

LODRV

SCL

GND

19

15

B+=6V-8.4V

0.047U_0603_25V7M
3
2
1

PC218
2

1
2
PC216
2
1

PC212
0.1U_0402_25V6K
1
2

2

1000P_0402_50V7K

1

105K_0402_1%

S

PC211
0.1U_0402_25V6K
1
2

PR210
10_1206_5%

PR213

ACOFF

PC210
0.1U_0402_25V6K
1
2

1

2N7002KW_SOT323-3

PQ202
1

D

2
G
3

30

ACDRV

@

C

PL202
HCB2012KF-121T50_0805
1
2

VIN

1U_0805_25V4Z

2

for DT mode,
adaptor loading recovery

2

@

CMSRC

PR208
499K_0402_1%

1

PR209
3.3K_1206_5%~D

2

PR206

PR203
2

2
1

PC209

1

2

PR202

2

1

4.7_0603_5%

0.022U_0402_25V7K
2

1

CSD87312Q3E_SON8-4
PC208

1

3
4

4.02K_0402_1%

S

0.1U_0402_25V6K

G

4.02K_0402_1%

2

4
3

REGN

D2

PL201
HCB2012KF-121T50_0805
1
2

1

D1

ACN

1

D

ACP

VIN

EMI Part (35.33)

P1

PR201
0.01_1206_1%

1

CHG_LX

PC219
10U_0805_25V6K
1
2

SIR472DP-T1-GE3_POWERPAK8-5

Near PL203

CHG_LGATE

REGN
14

1

PL203
2.2UH_PCMB063T-2R2MS_8A_20%
2

21
2

30,32

3

2

4

/BATDRV

BQ24715RGRR_QFN20_3P5X3P5~D

ADP_I

1
2

11

2

PR220 @
4.7_1206_5%~D

SNUB_CHG
PC221 @
1000P_0603_50V7K~D
PC227
0.1U_0402_25V6K
1
2

PC228
1

PC225
10U_0805_25V6K

/BATDRV

+VCHGR
1

PC224
10U_0805_25V6K
2
1

CELL

PR226
120K_0402_1%

3
2
1

PAD

10

PR216
0.01_1206_1%
4

PC223
10U_0805_25V6K
2
1

SRN

100P_0402_50V8J

1

IOUT

12

1

SRP

2

2

ACIN

7

1

29,30,32

ACOK

PQ205
PC220
1
2

1

13
SI7716ADN-T1-GE3_POWERPAK8-5

5

5

PR223
100K_0402_1%

2

0.1U_0603_25V7K

B

B

close to IC
1

@ PR224
2

+3VALW

100K_0402_1%

EMI Part (35.33)

PD204

2
PR225

@

2
SX34H_SMA2

PQ206
AO4407A_SO8

+VCHGR
1
2
3

8
7
6
5

@

BATT+

4

S

2
G

0.01U_0402_25V7K~D

for LEARN mode disable
(pulse)

1

1

PQ204
2N7002KW_SOT323-3

2

1

EC_BATT_PRS#

100K_0402_1%

30,32

D

3

1
@ PC229

battery = 2S3P -->
2130mAh*3= 6390mAh
---->6390mAh*0.8C=5.112A for express charge
Design charger current around 6A for worst case
max discharge current setting @ 7.7A (around 1.2C)

PR230
/BATDRV 1

2

4.02K_0402_1%

A

A

Security Classification
Issued Date

Compal Electronics, Inc.

Compal Secret Data
2011/06/02

Deciphered Date

2013/10/28

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

P31-PWR_NVDC_CHARGER
Document Number

Rev
1.0

LA-9262P

Friday, April 19, 2013

Sheet

1

33

of

45

5

4

3

2

1

PD307
8,27,29,30,34,38

3

PM_SLP_SUS#

1
8,30

EN_+V5A

2

5VA_EN

16

17

2

C

1
2

1

PC306
22U_0805_6.3V6M

1SNUB_+V5A

2

2
680P_0603_50V7K

2

@

@

FSW_+V5A

PR307
154K_0402_1%

PC307

PR308

1

FB_+V5A

FSW_+V5A

+5VA
TDC 1106mA
Peak Current 1580mA
OCP setting @ 3A

1M_0402_1%

2

FB
5

6

FSW
7

DEF

1

AGND

PG

8

 VFB=0.8V
Vo=VFB*(1+PR305/PR307)=0.8*(1+806K/154K)=5V

SS/TR

1

1

FB_+V5A

4

2

PC308
180P_0402_50V8J

+V5A_SS/TR 9

PC305
22U_0805_6.3V6M

@

+5VA

2

2

1

1
PR305
806K_0402_1%

2

SW

TPS62130RGTR_QFN16_3X3~D

3

100K_0402_1%

AVIN

2

1

JUMP_43X79

PR306

10

SW

2

PVIN

1

+V5AP

1

1

2

+V5A_LX

1

2

11

PJP302

2.2UH_PCME051E-2R2MS_3.3A_20%

SW

PR304
4.7_1206_5%

1

PC303
10U_0805_25V6K

2

1

PC302
10U_0805_25V6K

2

EMI Part (35.33)

PVIN

PL301

PC304
22P_0402_50V8J

12

+V5A_VIN

D

PADGND

2

BLM18SG700TN1D_2P

PGND

VOS

PL302

1

B+

PGND

14

13
EN

PU301

15

BAT54CW-7-F_SOT323-3
D

EMI Part (35.33)

C

+3VALW

4

EN_+5VDX

17

PL303
2.2UH_PCME051E-2R2MS_3.3A_20%

2

1M_0402_1%

2
1

PR318

2

1

B

PC314
22U_0805_6.3V6M

1

2

FSW_+5VDX

2

PR317
154K_0402_1%
PC315
680P_0603_50V7K

 VFB=0.8V
Vo=VFB*(1+PR315/PR317)=0.8*(1+806K/154K)=5V

1

1SNUB_+5VDX

FB

4

5
FB_+5VDX

FSW_+5VDX 7

6

FSW

AGND

PG
DEF

SS/TR

8

1

9

2

PC316
180P_0402_50V8J

+5VDX_SS/TR

2

FB_+5VDX

PC313
22U_0805_6.3V6M

@

1

3

2

SW

2

+5VDX_WALKPORT

1

TPS62130RGTR_QFN16_3X3~D

PR315
806K_0402_1%

100K_0402_1%

AVIN

2

1

JUMP_43X79

PR316

SW

1

+5VDXP

2

10

PVIN

PR314
4.7_1206_5%

11

PJP304

2

2

1

PC312
22P_0402_50V8J

+5VDX_LX

1

1

SW

1

PADGND

16

15

PVIN

2

1

PC311
10U_0805_25V6K

2

2

BLM18SG700TN1D_2P

EMI Part (35.33)

12

+5VDX_VIN

1

B

2

PC310
10U_0805_25V6K

B+

1

PGND

PL304

PGND

EN

PU302

14

SN74AHC1G32DCKR_SC70-5

O
INB

VOS

2

USB_EN

13

25

PU307

INA

G

1

PM_SLP_SUS#

3

8,27,29,30,34,38

P

5

+3VALW

@

@

EMI Part (35.33)
+3VALW

A

+5VDX_WALKPORT
TDC 2.1A
Peak Current 3A
OCP setting @ 3A

A

Compal Secret Data

Security Classification
2011/06/02

Issued Date

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size

Date:
5

4

3

2

Compal Electronics, Inc.
P32-PWR_+5V_VR

Document Number

LA-9262P
Friday, April 19, 2013

Sheet
1

Rev
1.0
34

of

45

5

4

3

2

1

PD305
SDMK0340L-7-F_SOD323-2
8,20,27

2

AUDIO_PWREN

1

EN_+3VDX

PD306
5,19

PCH_ENVDD

2

EC_ENVDD

3

1

1

2

1

2

1

2

PC322
22U_0805_6.3V6M

1

1SNUB_+3VDX
2
PR328

1M_0402_1%

FB_+3VDX

FSW_+3VDX

PR327
100K_0402_1%

PC323
680P_0603_50V7K

FB
5

6

7
FSW_+3VDX

@

@

C

EMI Part (35.33)

17

2.2UH_PCME051E-2R2MS_3.3A_20%
+3.3VDX_SSDP

1

1

1

1

PC330
22U_0805_6.3V6M

FSW_+3.3VDX_SSD

1
2

1SNUB_+3.3VDX_SSD
2

1M_0402_1%

2
PR338

1

PR337
100K_0402_1%

PC331
680P_0603_50V7K

FB

4

5
FB_+3.3VDX_SSD

6

7
FSW_+3.3VDX_SSD

8

+3.3VDX_SSD
TDC 637mA
Peak Current 910mA
OCP setting @ 3A

AGND

PG
FSW

SS/TR
DEF

9

1
2

 VFB=0.8V
Vo=VFB*(1+PR335/PR337)=0.8*(1+316K/100K)=3.3V

PC332
180P_0402_50V8J

+3.3VDX_SSD_SS/TR

2

FB_+3.3VDX_SSD

PC329
22U_0805_6.3V6M

@

2

1

3

2

SW

2

+3.3VDX_SSD

1

TPS62130RGTR_QFN16_3X3~D

PR335
316K_0402_1%

100K_0402_1%

AVIN

2

2

JUMP_43X79

PR336

SW

2

10

PVIN

PR334
4.7_1206_5%

11

PJP308

2

1

1

2

+3.3VDX_SSD_LX

1

1

SW

PC328
22P_0402_50V8J

PADGND

16

PVIN

B

PL307

2

1

PC327
10U_0805_25V6K

2

EMI Part (35.33)

2

1

PC326
10U_0805_25V6K

BLM18SG700TN1D_2P

PGND

12

+3.3VDX_SSD_VIN

PGND

2

VOS

PL308

1

15

13
EN

PU304

@

@

EMI Part (35.33)

A

+3VALW

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Issued Date

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
Date:

5

+3VDX

1

SSD_PWREN

B

A

1

+3VALW

8

B+

AGND

FSW

DEF

1

+3VDX
TDC 393.6mA
Peak Current 562.3mA
OCP setting @ 3A

14

C

PG

8

 VFB=0.8V
Vo=VFB*(1+PR325/PR327)=0.8*(1+316K/100K)=3.3V

SS/TR

2

FB_+3VDX

4

2

PC324
180P_0402_50V8J

+3VDX_SS/TR

9

1

@

PC321
22U_0805_6.3V6M

3

2

SW

1

TPS62130RGTR_QFN16_3X3~D

PR325
316K_0402_1%

100K_0402_1%

AVIN

2

2

JUMP_43X79

PR326

SW

2

+3VDXP

2

10

PVIN

PR324
4.7_1206_5%

11

PJP306

2
1

1

2

+3VDX_LX
1

1

PC320
22P_0402_50V8J

16

17

PL305
2.2UH_PCME051E-2R2MS_3.3A_20%

SW

2

1
2

2

EMI Part (35.33)

PC319
10U_0805_25V6K

1

BLM18SG700TN1D_2P

PVIN

PADGND

12

+3VDX_VIN
PC318
10U_0805_25V6K

B+

2

PGND

PL306

1

PGND

14

EN

PU303

15

D

BAT54CW-7-F_SOT323-3

VOS

19,30

13

D

4

3

2

P33-PWR_+3.3V_VR(1/2)

Document Number

LA-9262P
Friday, April 19, 2013

Sheet

1

35

Rev
1.0
of

45

5

4

3

2

1

D

D

PL309

2

1M_0402_1%

1

@

PR348

FB_+3VALW

FSW_+3VALW

+3VALW
TDC 1611mA
Peak Current 2301mA
OCP setting @ 3A

1

1

+3VALW

1

PC338
22U_0805_6.3V6M

C

2

2

1

FSW_+3VALW

PR347
91K_0402_1%

PC337
22U_0805_6.3V6M

2

2
1

100K_0402_1%

2

@

1

2

JUMP_43X79

PR346

2

FB_+3VALW

2

1

5

6

7

8

08-0328

PR345
294K_0402_1%

PJP310
+3VALWP

PR301
6.65K_0402_1%

@

2

2

PC340
4700P_0402_25V7K

PR344
4.7_1206_5%

1

3VALW_PG

1SNUB_+V3.3A_DSW

4

2

PG

3

PC339
680P_0603_50V7K

SS/TR

SW

EMI Part (35.33)

TPS62130RGTR_QFN16_3X3~D

1

16-0419

9

AVIN

2

FB

+3VALW_DSW_SS/TR

 VFB=0.8V
Vo=VFB*(1+PR345/PR347)=0.8*(1+316K/100K)=3.3V

2.2UH_PCME051E-2R2MS_3.3A_20%
1
2

+3VALW_LX

1

1

SW

SW

AGND

10

PVIN

FSW

11

DEF

1
2

2

EMI Part (35.33)

PC335
10U_0805_25V6K

1

BLM18SG700TN1D_2P

PVIN

PC336
22P_0402_50V8J
2
1

12

+3VALW_VIN
PC334
10U_0805_25V6K

B+

C

2

1

PL310
1

D

S

3

EN

PU305

17

2 DB2J31400L_SOD323-2

PADGND

1

VCOUT0_PH#

16

PD303

30

EN_+3VALW

PGND

1 DB2J31400L_SOD323-2

15

2
PD302
2.2K_0402_5%

EC_ON

PGND

1
PR341

2

30

VOS

1 DB2J31400L_SOD323-2

13

2

USBCHG_DET_D

2
PD301
2.2K_0402_5%

14

30

1
PR342

2
G
PQ300
DII-DMN65D8LW-7

PM_SLP_S0#

8,18,30,38

+3VALW

B

+3VLP

B

B+
PU306

GND
G920AT24U_SOT89-3
1

IN

2
1

OUT

PC342
2

PC341
2
1

10U_0805_25V6K

3

1U_0805_25V4Z

A

A

2011/06/02

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P34-PWR_+3.3V_VR(2/2)
Size

4

3

2

Rev
1.0

LA-9262P
Date:

5

Document Number
Friday, April 19, 2013

Sheet

1

36

of

45

A

B

8,18,27,30,37,38

C

D

 VFB=0.8V
Vo=VFB*(1+PR407/PR408)=0.6*(1+105K/120K)=1.5V

PM_SLP_S3#

+1.5VS
TDC 20.3mA
Peak Current 30.5mA
OCP setting @ 1A

PJP401

2

PL401

2

B+

1
2

1
+1.5VS_FSW

1
PR408
120K_0402_1%

PC405
22U_0805_6.3V6M

2
PR411

1
2

100K_0402_1%

2
1.5VSP_FB

2

5

6

7

FB

AGND

DEF
8

1

1.5VS_PWROK

@
30
+1.5VS_FSW

8,18,27,30,37,38

4

PG

@

2

PC408
180P_0402_50V8J

2

SS/TR
FSW

9

+1.5VS_SS/TR

PR406
4.7_1206_5%

3

SW
TPS62150RGTR_QFN16_3X3~D

PR407
105K_0402_1%

+1.5VS

2
43x39

2

AVIN

2

2

SW

1SNUB_1.5VSP

10

PVIN

+1.5VSP 1
PC404
22P_0402_50V8J

1

PC407
680P_0603_50V7K

11

1

PJP402

1UH +-20% PHI25201B-1R0MS 1.8A

+1.5VSP_LX

1

SW

1

PVIN

1

PADGND

PGND

PGND

16

14

EN

12

15

1
2

PU401

VOS

43x39

1

17

+1.5VSP_VIN

13

1

PC403
10U_0805_25V6K

B+

1.5VS_PWROK

2

EMI Part (35.33)

1.5VSP_FB

PM_SLP_S3#

PJP403

1

2

17

PL402

PJP404

1UH +-20% PHI25201B-1R0MS 1.8A

2

2

1

PC414
22U_0805_6.3V6M

2

PC413
22U_0805_6.3V6M

1
2

2
FSW_+1.8VS

PR420
324K_0402_1%

FB_+1.8VSP

1.8VS_PWROK

 VFB=0.8V
Vo=VFB*(1+PR419/PR420)=0.8*(1+402K/324K)=1.8V
+1.8VS
TDC 11.9mA
Peak Current 17mA
OCP setting @ 2A

@
30

+1.8VS

1

1

FB_+1.8VSP

PR424

@

100K_0402_1%

1.8VS_PWROK

FB

4

5

AGND
6

FSW
7

DEF

PG

8

1

SS/TR

FSW_+1.8VS

4

9

2

PC415
180P_0402_50V8J

+1.8VS_SS/TR

2

2

3

1

SW
TPS62140RGTR_QFN16_3X3~D

PR419
402K_0402_1%

2
43x39

2

AVIN

PR418
4.7_1206_5%

SW

1SNUB_1.8VSP

10

PVIN

2

PC416
680P_0603_50V7K

11

1

+1.8VP

2

1

+1.8VSP_LX

PC412
22P_0402_50V8J

1

1

SW

1

PVIN

PADGND

16

15

VOS

PGND

12

PGND

14

13

PU402

EN

1
2

1
2

PC411
10U_0805_25V6K

3

43x39

PC410
10U_0805_25V6K

3

EMI Part (35.33)

Compal Secret Data

Security Classification
Issued Date

4

2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size

Date:
A

B

C

Compal Electronics, Inc.
P35-PWR_+1.5VS/+1.8V_DDR

Document Number

LA-9262P

Friday, April 19, 2013

Sheet
D

37

of

Rev
1.0
45

5

4

3

2

1

@ PR501

1
8,27,29,30,34

2

EN_+1.05VS

PM_SLP_SUS#
0_0402_5%

D

D

PR503

1
8,18,27,30,37

2

PM_SLP_S3#

23
22

29
TP

EN

RA

VREF

28

27

26

REFIN

BST

PC503
PR506

19

17

SW

VIN

SW

VIN

SW

VIN

SW

6

BST_+1.05VS 1

2

5.1_0603_5%
SW_+1.05VS

1

+1.05VA

2
PL502
0.68UH_PCMC063T-R68MN_15.5A_20%

.1U_0603_25V7K

1

PJP501

2

7
8

2

SNUB_+1.05V

1

PGND

9

2

1

1

JUMP_43X118
@ PR507
4.7_1206_5%

@ PC509
1000P_0402_50V7K

@

@

2

TPS51362RVER_QFN28_4P5X3P5
PU501

10

PGND
11

PGND
12

PGND
13

PGND

15

14

1
2

0.1U_0402_25V6
PC512

1
2

2200P_0402_50V7K
PC511

1

PC510
10U_0805_25V6K

2

1
2

PC513
10U_0805_25V6K

EMI Part (35.33)

@

2

+1.05VSP

2

16

V5

5

1

0_0402_5%

2

+1.05VS_B+

GND

4

PC508
22U_0805_6.3V6M

2

NC

C

8,18,30,36

1

1

TRIP

3

2

18

HCB2012KF-121T50_0805
PL501

MODE

PM_SLP_S0#

0_0402_5%
PR509

2

B+

PC504
1 1U_0603_10V6K

SLEW

30

2

PC507
22U_0805_6.3V6M

2

@ PR505

20

1

1

+5VA

21

LP#

2

1

0_0402_5%
2
TRIP

LP#

1.05VA_PG

2

PC506
22U_0805_6.3V6M

1

VSNS

1

1

PR508

PGOOD

1

PC502
1000P_0402_50V7K
2
1
SLEW

GSNS

PC505
22U_0805_6.3V6M

C

REFIN2

24

25

1.05V_VREF 1

PC501

2

0.1U_0402_25V6

0_0402_5%

B

B

EMI Part (35.33)

+1.05VA
TDC 3754mA
Peak Current 3942mA
OCP setting @ 8A

A

A

Security Classification
Issued Date

Compal Electronics, Inc.

Compal Secret Data
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P36-PWR_+1.05VS
Size

4

3

2

Rev
1.0

LA-9262P
Date:

5

Document Number

Friday, April 19, 2013

Sheet

1

38

of

45

5

4

3

2

1

+0.675VS
TDC 700mA
Peak Current 1000mA
OCP setting @ 1200mA

EMI Part (35.33)
D

D

PL601

1

B+

2

+1.2V_B+
PJP604

HCB2012KF-121T50_0805

1

PC605
0.22U_0603_10V7K

2

1

2

PR601
2.2_0603_5%

1

1

+1.35V_DDR

43x39

2

BOOT_+1.2V
PJP603

2

1

PC604
2200P_0402_50V7K

@

2

1
2

PC602
10U_0805_25V6K

B+=6V-8.4V

PC603
0.1U_0402_25V6

VLDOIN_+1.2V

DH_+1.2V

1

+0.6VSP

2
43x39

+0.675VS

1

PC607
10U_0805_25V6K

2

1

1

PC606
10U_0805_25V6K

VTT

2

20

19
VLDOIN

18
BOOT

17

2
C

PC609
0.033U_0402_16V7K

4

VTTREF_+1.2V

5

6

10

PC612
1U_0603_10V6K

3

FB

VDDQ
S3

VDD

7

11

VTTREF

S5

VDD_+1.2V

GND

RT8207MZQW_WQFN20_3X3

VDDP

8

12

TON

+5VA

UGATE

PHASE

16

1

CS

9

PQ602
AON7516_DFN8-5

2

VTTSNS

1
2
3

15P_0603_50V
4.7_1206_5%~D
PC613
PR605
2
1SNUB_+1.2V
2
1

+5VA
PR608

1

+1.2V_B+

1

B

1
8,18,30

2

S5_+1.2V

PM_SLP_S4#
0_0402_5%

PC616
@ 0.1U_0402_16V7K~D

S3_+1.2V

MAX
7.8mohm

2

1.35V for DDR3L
VFB = 0.75V
Vo=0.75(1+PR608/PR610)=0.75(1+ 8.2/10) = 1.35V

2

PC615
@ 0.1U_0402_16V7K~D

PR613

AON7212L
TYP
Rds(on) :6.2mohm ,

2

PR611
1M_0402_1%

2

MAX
23.5mohm

2

PC614
100P_0402_50V8J
10K_0402_1%

1

1

1.2V_DDR_PWROK

AON7406L
TYP
Rds(on) :19mohm ,

2

8.2K_0402_1%

PR610

30

1

+1.2V_FB

+1.2V_TON

PC611
330U_B_2.5VM_R9M

+

2

1
4

PGND

1

+1.35V_DDR
TDC 3884mA
Peak Current 5548mA
OCP setting @ 7A

PC608
1U_0603_10V6K

2

VTTGND

21

CS_+1.2V

13
PR606
5.1_0603_5%

PAD

+1.2VP

B

PC610
330U_B_2.5VM_R9M

+

2

1

2

2

JUMP_43X118

1

14

PR604
3.6K_0402_1%

1

PU601

LGATE

1

1

1

+1.2VP

5

2

1

15

PGOOD

PL602
2.2UH_PCMB063T-2R2MS_8A_20%

PJP602

2

4

2

+1.35V_DDR

DL_+1.2V

1
2
3

C

PQ601
AON7408L_DFN8-5

5

SW_+1.2V

PR615

1
5

2

SM_PG_CTRL
0_0402_5%

A

A

Security Classification
Issued Date

Compal Electronics, Inc.

Compal Secret Data
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P37-PWR_+1.35V_DDR/+0.675VS
Size

4

3

2

Rev
1.0

LA-9262P
Date:

5

Document Number

Friday, April 19, 2013

Sheet
1

39

of

45

5

4

3

2

PJP701

2

1
+

2

100K_0402_1%_NCP15WF104F03RC

PWM1

PU702
CSD97374CQ4M_SON8_3P5X4P5

SW_PHASE_1

1
2

@
PR720
75_0402_1%

@ PR721

4

1

2

3

IMVP_VR_PG

10,29

+5VS

2
@ PR723

2

+3VS

2

1

VR_SVID_DAT

2

1.91K_0402_1%~D

CSP2

PH703

SKIP#

1

2

2
1

+1.05VS_VCCST

PU703
CSD97374CQ4M_SON8_3P5X4P5

9
8
7

PC719
0.1U_0402_25V6

PC720
1U_0603_10V6K

0_0402_5%
10_0603_1%

1

2

2

6
5

1

PR730
0_0603_5%

PGND2
PWM
BOOT
VSW
PGND1
BOOT_R VDD
VIN
SKIP#

4
3
2
1

SW_PHASE_2

VR_SVID_DAT

PC722

@
PR738
75_0402_1%

3

1

4

B

0.24UH_FDUE0630J-H-R24M-P3_22A_20%

2

+5VS

1

2

from processor

+VCC_CORE

2

SNUB_phase2
PC718
1000P_0402_50V7K

1

VR_SVID_ALRT#

VR_SVID_DAT

2

1

0.1U_0402_25V6K

2

1

PC721

VR_SVID_CLK

VR_SVID_CLK
VR_SVID_ALRT#

10

2

1
2

PR737
130_0402_1%

1
2

PR736
75_0402_1%

1

PR735
56_0402_1%

2
10

@

1

PL702

SKIP#2

10

2

2

SKIP#2

1

1

PR731

2

+5VA

PR734

1500P_0402_7K

1

1
2

1

CSN2

CPU_B+
PR733

10K_0402_1%
B

close to IC

4.7_1206_5%~D

2

1

1

2

PC724

2

30

PC716
0.12U_0402_10V6K

15P_0603_50V

PR744

1

VR_HOT#

PR728
10.2K_0402_1%

PWM2

2

10K_0402_1%

VR_SVID_CLK

+3VS

PC715
1U_0603_10V6K

1

2

PC717

VREF

PR727

1

PR726
2.49K_0402_1%

0.33U_0603_10V7K

VR_SVID_ALRT#
100P_0402_50V8J~D

1

1_0603_5%

2

2

2

10K_0402_1%_TSM0A103F34D1RZ
PR729
3.01K_0402_1%

2
COMP
@ PC714

1

2

1

PR724
2.49K_0402_1%

TPS51622RSM_QFN32_4X4

DROOP

2

1

close to choke

PC713
2.2U_0603_10V7K

PR725

1

1

C

2

75_0402_1%

1

0_0402_5%

PWM2

PC712

PWM1

5

4

SNUB_phase1
PC710
1000P_0402_50V7K

2

6

SKIP#1

1

0.24UH_FDUE0630J-H-R24M-P3_22A_20%

15P_0603_50V

2

2

1

1

SKIP#

1

SKIP#1

1
PR718

7

3

1

PAD

VDIO

8

+VCC_CORE

2

33

ALERT#

VCLK
31

25

+3VS

VDD

32

VFB

GND

GFB

10,30

4
3
2
1

1

10

PGOOD
VR_HOT#

N/C

6
5

1

PL701

PR719

2

PGND2
PWM
BOOT
VSW
PGND1
BOOT_R VDD
VIN
SKIP#

4.7_1206_5%~D

9
8
7

PR715
0_0603_5%

9
O-USR

F-IMAX

11
B-RAMP

IMON

OCP-I

12

13

14

15
SLEWA

N/C

V5A

24

PU3

30

VFB

23

PWM2

29

GFB

PWM1

CSP2

28

22

CSN2

VREF

@

1

PR746

0_0402_5%

2

21

SKIP#

COMP

20

VR_ON

CSN1

27

19
CSP2

CSP1

26

C

THERM

16
VBAT

18

DROOP

17

2

2
2
1

1

CSN1

close to IC
CSN1

2

VR_ON

PC708
0.12U_0402_10V6K

CPU_B+

2

CSP1

PR708
3.01K_0402_1%

1
1

PR713
150K_0402_1%

2

O-USR

1

PR712
150K_0402_1%

2
1

PR711
100K_0402_1%

F-IMAX

D

2

2

PR706
169K_0402_1%

PR705
1M_0402_1%

1

2
1

PR704
75_0402_1%

2

PR703
205K_0402_1%

1

B-RAMP

2

PR710
39K_0402_1%

OCP-I

PR717
10K_0402_1%
PU701

PH702
10K_0402_1%_TSM0A103F34D1RZ

PC711
0.1U_0402_25V6

CSN2

CSP1

PR707

CPU_B+
1

1

10.2K_0402_1%

1

2
1

PC707

4700P_0603_50V7K

PC709
0.1U_0402_25V6K

2

1
2
2

1
2

2

@

2

PR702
2.49K_0402_1%

EMI Part (35.33)

1

PR714
39K_0402_1%

SLEWA

1

PR709
10K_0402_1%

1

@

PR701
75_0402_1%

2

PH701

IMON

close to choke

1

1
2

PC703
0.1U_0402_25V6

1
2

PC702
10U_0805_25V6K

VREF

1

2

2

PC701
10U_0805_25V6K

1

HCB2012KF-121T50_0805
@ PL703

CPU_B+
PC705
100U_D2_16VM_R50M

2

1

1

JUMP_43X79

2

1

B+

PC704
2200P_0402_50V7K

DC load line: 2m-OHM
TDC: 10A
IccMax: 32A
OCP: 42A
PH701 B value: 4250K 1%
PH702, PH703 B value: 3435K 1%

D

1

A

VFB
10

VCCSENSE

11

VSSSENSE

PC723
2.2U_0603_10V7K

VCCSENSE and VSSSENSE
have been already pull-high to +VCC_CORE and GND
by 100-OHM in HW side, P10 and P11

A

GFB

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

2013/10/28

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

P38-PWR_CPU_CORE

Document Number

Rev
1.0

LA-9262P
Friday, April 19, 2013

Sheet

1

40

of

45

5

4

3

2

1

D

D

for VCORE:2 phase ---> reserved 30pcs, 15-pcs is OK after fine-tune

@

@

@

@

@

1
2

PC810

@

1

PC820

2

PC819

22U_0805_6.3V6M

1

@

2

22U_0805_6.3V6M

1

PC818

2

22U_0805_6.3V6M

1

PC817

22U_0805_6.3V6M

1
2

PC809

@

2

22U_0805_6.3V6M

1

PC816

22U_0805_6.3V6M

1

PC808

2

22U_0805_6.3V6M

1
2

PC807

@

2

22U_0805_6.3V6M

1

PC815

22U_0805_6.3V6M

1
2

PC806

@

2

22U_0805_6.3V6M

1

PC814

22U_0805_6.3V6M

1
2

PC805

@

2

22U_0805_6.3V6M

1

PC813

22U_0805_6.3V6M

1
2

PC804

@

2

22U_0805_6.3V6M

1

PC812

22U_0805_6.3V6M

1
2

PC803

@

2

22U_0805_6.3V6M

1

PC811

2

22U_0805_6.3V6M

@

22U_0805_6.3V6M

1

PC802

2

22U_0805_6.3V6M

1

PC801

2

22U_0805_6.3V6M

+VCC_CORE

@

1

PC830

2

PC829

22U_0805_6.3V6M

1
2

PC828

22U_0805_6.3V6M

1
2

PC827

22U_0805_6.3V6M

1
2

PC826

22U_0805_6.3V6M

1
2

PC825

22U_0805_6.3V6M

1
2

PC824

22U_0805_6.3V6M

1
2

PC823

22U_0805_6.3V6M

1
2

PC822

22U_0805_6.3V6M

1
2

PC821

22U_0805_6.3V6M

2

1

C

22U_0805_6.3V6M

C

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P39-PWR_PROCESSOR_DECOUPLING
Size

5

4

3

2

Document Number

Rev
1.0

LA-9262P
Date:

Sheet

Friday, April 19, 2013

1

41

of

45

5

4

3

2

Version Change List ( P. I. R. List )
Item Page#
X

Title

XX

XXX

Date
XX'XX/XX

Request
Owner
Compal_XX

1

Page 1

Issue Description

Solution Description

XXXXX

Rev.

Change PRXX from Xohm to XXKohm.

D

D

36

20121008

Compal_Power

34

20121012

Compal_HW

34

create one more input cap for TPS51362 Vin

add PC513_10U_0805_16V6K for TPS51362's input

create one more resistor for TPS62130 enable pin

add PR342_2.2K_0402_5%

design change, delete PU301~PU305, TPS62130 and related components,
create PU301, TPS51225 for 3.3V and 5V power rails

35

20121018

Compal_Power

20121018

Compal_Power

design change, delete PU401, PU402, TPS62140 and TPS62150
and related components,
create PU401and PU402, SY8003D for 1.5V and 1.8V power rails

20121023

dell

reject power design change of 3.3V, 5V, 1.8V and 1.5V

20121203

Compal_EMI

change PL501 for EMI and layout routing

36
36

34
35

C

36

C

38

change from SUPPRE_ FBMA-L11-453215-800LMA90T_1812 to HCB2012KF-121T50_0805

39

20121203

Compal_EMI

change PL601 for EMI and layout routing

change from SUPPRE_ FBMA-L11-453215-800LMA90T_1812 to HCB2012KF-121T50_0805

40

20121203

Compal_EMI

add PL703 for EMI

add PL701 HCB2012KF-121T50_0805

38

20121203

Compal_Power

create PR509 0_0402_5% for debug

add PR509 0_0402_5%

32

20121205

Compal_HW

create PR5107 10K_0402_1% for test

add PR107 10K_0402_1%

40

20121213

Compal_Power

fine tune VR transient

de-pop PC714, change PR711 from 150K to be 100K

40

20130122

Compal_Power

follow Intel's recommendation

change PR737 from 110 OHM to be 130 OHM

33

20130131

Compal_RF

reserved a MLCC for RF consideration

create PC206 2200P_0402_50V7K

40

20130221

Compal_RF

for RF noise reducing

pop PC703, PR719 and PC712, PR734 and PC722 for VCORE

39

20130221

Compal_RF

for RF noise reducing

pop PR605 and PC613 for DDR

B

B

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Issued Date

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P40-PWR_PIR-1
Size
Date:

5

4

3

2

Document Number

LA-9262P

Friday, April 19, 2013

Rev
1.0
Sheet
1

42

of

45

5

4

3

2

Version Change List ( P. I. R. List )
Item Page#

Title

Date

Request
Owner

1

Page 2

Issue Description

Solution Description

Rev.

D

D

X

XX

XXX

XX'XX/XX

Compal_XX

XXXXX

Change PRXX from Xohm to XXKohm.

C

C

B

B

A

A

2011/06/02

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P41-PWR_PIR-2
Size

4

3

2

Rev
1.0

LA-9262P
Date:

5

Document Number
Friday, April 19, 2013

Sheet

1

43

of

45

A

B

C

D

+3V_PCH

2.2K

SMBUS Address [0x9a]

1

+3VS

2.2K

@0-ohm

10K

+3VS

AP2

SMBCLK

AH1

SMBDATA

E

10K

PCH_SMBCLK

DMN66D0

PCH_SMBDATA

DIMM Channel A SPD ROM

[0xA0]

1

DMN66D0

+3V_PCH

@0-ohm

DIMM Channel B SPD ROM

6/15-Change pull high resistor from 1k to 499
ohms
499

PCH

AN1

SML0CLK

AK1

SML0DATA

499

XDP

NFC

[0x28]

+3VS

+3V_PCH
2.2K

[0xA4]

2.2K

4.7K

4.7K

+3VNS_PWR

6/15-add o ohm
@0-ohm
SML1CLK

SML1DATA

PCH_SMLCLK

PCH_SMLDATA
0-ohm

+3VS

AU3

2

2.2K

DMN66D0

AH3

ALS

DMN66D0

0-ohm

@0-ohm
6/15-NC mos

@

2.2K

@0-ohm

@0-ohm
DMN66D0
DMN66D0

+3VNS_PWR

@0-ohm

@

+3VNS_PWR
10K

10K

@ 10K

+3VS

2

[0x29]

@0-ohm

I2C0_SCK_SNR

G3

I2C0_SDA_SNR

F3

Magnetic 0x3C
Acceleration 0x32

B5

e-Compass +
Accelerometer

C5

Sensor HUB

@ 10K
Pressure Sensor

I2C
F3
F2

I2C0_SCK

0-ohm

[0xBA]

I2C0_SDA

3

Gyro Sensor

+3VNS_PWR

0-ohm

3

B8

A6

[0xD2]
0-ohm
I2C0_SCK_DSP 27

+3VS_TOUCH

I2C0_SDA_DSP 26

+3VS

ALS 5505

0-ohm
1K

1K

@ 1K

+3VALW_EC

@ 1K

PCH
F1
G4

I2C1_SCK

0-ohm

I2C1_SDA

I2C1_SCK_TP
I2C1_SDA_TP

I2C1_SCK_TS
I2C1_SDA_TS

4

9

10K

8

Touch Pad

0-ohm
0-ohm

10K

KBC

A8

EC_SMB_CK1

A7

EC_SMB_DA1

100-ohm

Charger

[0x12]

BATTERY
CONN

[0x16]

7
6

100-ohm

Touch Panel

4

0-ohm

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/02

Deciphered Date

2013/10/28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P42-SMBus Block Diagram
Size

Date:
A

B

C

D

Document Number

Rev
1.0

Friday, April 19, 2013

Sheet
E

44

of

45

5

4

[AC in]
Vin

B+

Tb

+3VLP

EC Input

Td

EC_ON

EC Output

Te

+3VALW (+3V_PCH_DSW)
EC Output

5VA_EN (PCH_DPWROK)

1ns < Th < 4s

PBTN_SW#

EC_ON

Td

+3VALW (+3V_PCH_DSW)

Tf
EC Output

Tg

+5VA
EC Input

Tc

+3VLP

Tc

Te

5VA_EN (PCH_DPWROK)

Tf

+5VA

Tg

T1

+1.05VA

T2

+3V_PCH
T4
+5VDX_WALKPORT

T5

EC Output PCH_RSMRST#
T7
PCH Output PCH_SUS_PWR_DN

0 mS

T8 < 90ms

EC Output AC_PRESENT

20 mS
16ms < T9 < 4s

110 mS EC Output PBTN_OUT#
C

Minimum duration of PWRBTN # assertion = 16mS after SUSCLK stable

T10
PCH Output SUSCLK

T11

PCH Output PM_SLP_S5#

30us < T12

PCH Output PM_SLP_S4#
T14
+1.35V_DDR

T15

1.2V_DDR_PWROK

T18

30us < T

PCH Output PM_SLP_S3#
T20
+5VS

T21

+3VDX

T22

+3VS

T23

+1.8VS

T24

1.8VS_PWROK

T25

+1.5VS
B

[AC in]

[Battery only, AC absent]

ITEM
Ta
Tb
Tc
Td
Te
Tf
Tg
Th

+3VLP

ITEM
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
T35
T36
T37
T38
T39
T40
T41
T42

Measure Point
To +1.05VA
To +3V_PCH
To
PM_SLP_SUS#
To +5VDX_WALKPORT
PM_SLP_SUS#
To PCH_RSMRST#
To
PCH_RSMRST#
To PCH_SUS_PWR_DN
PCH_RSMRST#
To AC_PRESENT
PBTN_OUT#
To Low pluse width
PCH_RSMRST#
To SUSCLK
SUSCLK
To PM_SLP_S5#
PM_SLP_S5#
To PM_SLP_S4#
To
PM_SLP_S4#
To +1.35V_DDR
+1.35V_DDR
To 1.2V_DDR_PWROK
To
To
PM_SLP_S4#
To PM_SLP_S3#
To
PM_SLP_S3#
To +5VS
PM_SLP_S3#
To +3VDX
PM_SLP_S3#
To +3VS
PM_SLP_S3#
To +1.8VS
+1.8VS
To ALL_VS_PG
PM_SLP_S3#
To +1.5VS
+1.5VS
To 1.5VS_PWROK
PM_SLP_S3#
To +1.05VS
+1.05VS
To 1.05VS_PG
PM_SLP_S3#
To MPHY_PWREN
MPHY_PWREN
To +1.05VDX_MODPHY
ALL_VS_PG
To HWPG
HWPG
To PCH_PWROK
1.05VS_PG
To 1.05VS_VCCST_PG
1.05VS_VCCST_PG
To VR_ON
VR_ON
To +VCC_CORE
+VCC_CORE
To IMVP_VR_PG
PCH_PWROK
To SM_PG_CTRL
SM_PG_CTRL
To +0.6VS
HWPG
To PCH_PWROK_EC
PCH_PWROK_EC
To SYS_PWROK
SYS_PWROK
To PCH_PLTRST#
HWPG
To PCH_PLTRST#

VIN
VIN
B+
EC_ON
+3VALW
5VA_EN

Measure Point
To ACIN
To B+
To +3VLP
To EC_ON
To +3VALW
To PCH_DPWROK
To +5VA

PBTN_SW#

Time

ITEM

Tc
Th
Td
Te
Tf
Tg

Low pluse width

B+

Measure Point
To
To
To +3VLP

PBTN_SW#
PBTN_SW#
EC_ON
+3VALW
5VA_EN

Time

Low pluse width

To
To
To
To

EC_ON
+3VALW
PCH_DPWROK

D

+5VA

1ns < Th < 4s

PBTN_SW#

PCH Output PM_SLP_SUS#

20 mS

1

Discrete Power On Sequence
EC pay attention timing

B+

D

2

Ta

ACIN

EC Output

3

[Battery only, AC absent]

T26

1.5VS_PWROK

Time

PM_SLP_SUS#

PM_SLP_SUS#

>10ms
<200ms
0~90ms
>100ms
<30us

<10ms
C

<30us

>1ms

>5ms
<0.1us
<2.5ms
<7.5ms
<35us
5~99ms
>1.06ms
>5~99ms
B

T27

+1.05VS

T28

1.05VS_PG
T29
PCH Output MPHY_PWREN

T30

+1.05VDX_MODPHY
T31
EC Input HWPG

T32 0ms < T

PCH Input PCH_PWROK
T33
PCH Input 1.05VS_VCCST_PG

T34

PCH Output VR_ON

T35

+VCC_CORE

T36

IMVP_VR_PG
PCH Output SM_PG_CTRL

T37

+0.6VS

T38

80 mS after HWPG
EC Output PCH_PWROK_EC

T39 5~99ms
T40 0ms < T

PCH Input SYS_PWROK

T41

PCH Output PCH_PLTRST#

T42

5~99ms < T

PCH Output PCH_PLTRST#
A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Clas s ification
2011/08/25

Deciphered Date

2012/07/25

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

T itle

P44-Power Sequence
Size

Date:
5

4

3

2

Docum ent Num ber

Friday, April 19, 2013
1

Rev
1.0
Sheet

45

of

45

www.s-manuals.com



---

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