Compal LA 9531P Schematics. Www.s Manuals.com. R0.1 Schematics

User Manual: Motherboard Compal LA-9531P V5WE2, V5WC2, V5WT2 - Schematics. Free.

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A

B

C

D

E

Compal Confidential
Model Name : V5WE2/T2 (EA/EG50_HW)
File Name : LA-9531P
1

1

Compal Confidential
2

2

EA50_HW M/B Schematics Document
Intel Shark Bay ULT (Hasswell + Lynx Point-LP)
AMD SUN

2012-09-24

3

3

REV:0.1

4

4

ZZZ

Part Number
DA60000XL00
V5WE2_PCB

2012/07/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Description
PCB 0VR LA-9531P REV0 M/B

2013/07/10

Deciphered Date

Title

Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Tuesday, September 25, 2012

Sheet
E

1

of

50

Rev
0.1

A

B

C

D

E

CRT Conn.

Fan Control

page 27

1

page 36

DP to VGA
ITE IT6511FN

HDMI Conn.

eDP Conn.

page 25

1

page 24

page 26

eDP

DP x 2 lanes

HDMI x 4 lanes

2.7GT/s

2.97GT/s

204pin DDR3L-SO-DIMM X1

Intel Haswell ULT

DDI

page 15

BANK 0, 1, 2, 3

Memory BUS
Dual Channel

Haswell ULT

204pin DDR3L-SO-DIMM X1

1.35V DDR3L 1333/1600

Processor

page 16

BANK 4, 5, 6, 7

MINI Card
WLAN
USB port 8 page 30

2

OPI

AMD SUN
with DDR3 x4
page 17~23

PCIe 2.0
5GT/s

PCIe 2.0 x4
5GT/s

port 4

port 5

Flexible IO

Lynx Point - LP
PCH

PCIe 2.0
5GT/s

USBx8

port 3

SATA3.0

SATA3.0

6.0 Gb/s

6.0 Gb/s

port 0

LAN(GbE)
Boardcom
57786Xpage

3

SATA HDD
Conn.

port 2

page 04~14

LPC BUS

2 in 1
(SD/MMC)

USB port 0
page 32

USB/B (port 1,2)
page 32

USB port 5
page 24

3.3V 24MHz

HDA Codec
ALC3225
page 35

SPI

3

Int. Speaker

page 7

ENE
KB9012/KB932
page 33

2

48MHz

SPI ROM x2

CLK=24MHz

page 29

Int. MIC

page 35

Combo Jack

page 35

page 35

Sub Board
page 6

Touch Pad
LS-5931P

Power On/Off CKT.

page 37

page 34

page 32

LS-5932P
DC/DC Interface CKT.

Int.KBD

page 34

PWR/B

page 34

4

CMOS
Camera

1168pin BGA

page 31

Card Reader

RTC CKT.

USB 2.0
conn x2

HD Audio

SATA CDROM
Conn.

page 31

38

USB 3.0
conn x1

USB/B

EC ROM x1
(KB932)
page 33

(port 1,2)
page 32

4

2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

page 38~38
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Power Circuit DC/DC
B

C

D

Title

Block Diagrams

Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
E

2

of

50

Rev
0.1

A

B

C

D

SIGNAL

STATE

Voltage Rails

1

2

Description

S1

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

BATT+

Battery power supply (12.6V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

+VGA_CORE

Core voltage for GPU

ON

OFF

OFF

HIGH

HIGH

ON

ON

ON

ON

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

1

Board ID / SKU ID Table for AD channel

OFF

OFF

ON

OFF

OFF

+0.95VSDGPU

+0.95VSDGPUP to +0.95VSDGPU switched power rail for CPU

ON

OFF

OFF

Vcc
Ra/Rc/Re

+1.35V

+1.35VP to +1.35V power rail for DDRIIIL

ON

ON

OFF

Board ID

+1.5VS

+1.5V to +1.5VS switched power rail

ON

OFF

OFF

+1.5VSDGPU

+1.5VSDGPUP to +1.5VSDGPU switched power rail for GPU

ON

OFF

OFF

+1.8VS

+3VS to 1.8V switched power rail to CPU

ON

OFF

OFF

+1.8VSDGPU

+1.8VS to +1.8VSDGPU switched power rail for GPU

ON

OFF

OFF

+3VALW

+3VALW always on power rail

ON

ON

ON*

+3VLP

B+ to +3VLP power rail for suspend power

ON

ON

ON

+3VS

+3VALW to +3VS power rail

ON

OFF

OFF

+3VSDGPU

+3VS to +3VSDGPU switched power rail for GPU

ON

OFF

OFF

0
1
2
3
4
5
6
7

ON

ON

ON*

ON

OFF

OFF

+VSB

+VSBP to +VSB always on power rail for sequence control

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

EC SM Bus1 address
Device

Address

Smart Battery

0001 011X

Device

Address
0100 110x

VGA Internal Thermal Senser 0100 000x
G Senser

USB 2.0

1001 000x

JDIMM1

ChannelB

DIMM1

1001 010x

JDIMM2

3 External
USB Port

0
1
2
3
4
5
6
7

EHCI1

USB Port(Left 3.0)
USB Port(Right 2.0)
USB Port(Right 2.0)

2012/07/10

Issued Date

AMD GPU
Mars component
VRAM Selection
VRAM x 8pcs

VGA@

TPM Module
G-Sensor
KB Backlight

TPM@
GSEN@
BL@

Camera

XDP (Debug Port)
Debug Only

XDP@
DEG@

MARS@

X76@
128@

3

USB Port(Left 3.0)
4

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2

BOM Structure
@
CONN@
932@
9012@
CHR@
NCHR@
AMIC@
DMIC@

Mini Card (WLAN+BT)

USB 3.0 Port
0
1
XHCI
2
3

4

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

BTO Item
Unpop
Connector
EC 932
EC 9012
W/Charger
WO/Charger
Analog MIC
Digital MIC

PCB Revision
0.1
0.2
0.3
1.0

Port

Address
DIMM0

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

USB Port Table

0011 000x

PCH SM Bus address
ChannelA

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

BTO Option Table

Board ID
0
1
2
3
4
5
6
7

EC SM Bus2 address
On Board Thermal Senser

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

BOARD ID Table

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

3

HIGH

ON

+5VALW to +5VS switched power rail

Clock

HIGH

+0.675VSP to +0.675VS switched power rail for DDR terminator

+5VALWP to +5VALW power rail

+VS

LOW

+1.0VSDGPU switched power rail for GPU

+5VALW

+V

HIGH

+0.675VS

+5VS

+VALW

S1(Power On Suspend)

+1.05VSDGPU

Device

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Full ON

Power Plane

E

2013/07/10

Deciphered Date

Title

Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Tuesday, September 25, 2012

Sheet
E

3

of

50

Rev
0.1

5

4

3

2

26
26
26
26

DP to CRT

C54
C55
B58
C58
B55
A55
A57
B57

CPU_DP1_N0
CPU_DP1_P0
CPU_DP1_N1
CPU_DP1_P1

D

25
25
25
25
25
25
25
25

HDMI

C51
C50
C53
B54
C49
B50
A53
B53

CPU_DP2_N0
CPU_DP2_P0
CPU_DP2_N1
CPU_DP2_P1
CPU_DP2_N2
CPU_DP2_P2
CPU_DP2_N3
CPU_DP2_P3

1

HASWELL_MCP_E

U1A

DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

DDI

EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3

EDP

DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3

EDP_AUXN
EDP_AUXP
EDP_RCOMP
EDP_DISP_UTIL

C45
B46
A47
B47

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

24
24
24
24

C47
C46
A49
B49

D

A45
B45

EDP_AUXN 24
EDP_AUXP 24

D20
A43

EDP_COMP R1 1

2 24.9_0402_1%

+VCCIOA_OUT

Trace width=20 mils,Spacing=25mil,Max length=100mils
EDP_DISP_UTIL 24

Rev1p2

1 OF 19

Reserved for ESD
Reserved for ESD
C94

@1

2 6.8P_0402_50V8C
T20
T2

2

+1.05VS_VTT

1
R68
62_0402_5%

1

33,38,39 H_PROCHOT#
C

D61
K61
N62

@
@

33 H_PECI

+1.35V

XDP_PRDY#_R
XDP_PREQ#_R
XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R

HASWELL_MCP_E

U1B

C95

@1

R6

1

C60

@1

R8
56_0402_5%
1
2 H_PROCHOT#_R K63

PROC_DETECT
CATERR
PECI

PRDY
PREQ
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO

JTAG

PROCHOT

THERMAL

2 6.8P_0402_50V8C

2

2 10K_0402_5% H_CPUPW RGD

C61

PROCPWRGD

DIMM_DRAMRST# 15,16

R11
R13
R41

1
1
1

2 200_0402_1% SM_RCOMP0
AU60
2 120_0402_1% SM_RCOMP1
AV60
AU61
2 100_0402_1% SM_RCOMP2
DIMM_DRAMRST# AV15
AV61
DDR_PG_CTRL
15 DDR_PG_CTRL

R27
R28
R29
R30
R31
R20
R21

1
1
1
1
1
1
1

2
2
2
2
2

6.8P_0402_50V8C
6.8P_0402_50V8C
6.8P_0402_50V8C
6.8P_0402_50V8C
6.8P_0402_50V8C

J62
K62
E60
E61
E59
F63
F62

XDP_PRDY#_R
XDP_PREQ#_R
XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R
XDP_TDI_R
XDP_TDO_R

XDP@
XDP@
XDP@
XDP@
XDP@
XDP@
XDP@

2
2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

XDP_PRDY#
XDP_PREQ#
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO

2 0_0402_5%
2 0_0402_5%

XDP_OBS0
XDP_OBS1

C

PWR

2 6.8P_0402_50V8C

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

Reserved for ESD
DIMM_DRAMRST#

@1
@1
@1
@1
@1

MISC

Reserved for ESD

R184
470_0603_5%

C63
C64
C96
C97
C98

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1

DDR3

DDR3 Compensation Signals

J60
H60
H61
H62
K59
H63
K60
J61

XDP_BPM#0_R
R22
XDP_BPM#1_R
R23
@
T148
@
T149
@
T150
@
T151
@
T152
@
T153

1 XDP@
1 XDP@

Rev1p2

2 OF 19

+1.05VS_VTT

+1.05VS_VTT

Reserved for ESD

PU/PD for JTAG signals

JXDP1
6.8P_0402_50V8C
6.8P_0402_50V8C

+3VS
B

@

2 1K_0402_5%
+1.05VS_VTT

XDP_TMS

R86

1

XDP_TDI

R87

1 XDP@

2 51_0402_5%

XDP_PREQ#

R88

1

2 51_0402_5%

XDP_TDO

R89

1 XDP@

@

+3VALW _PCH

R4
1K_0402_5%
@
SYS_PW ROK_XDP

@

2 51_0402_5%

XDP_TCK

R90

1 XDP@

2 51_0402_5%

XDP_TRST#

R91

1

2 51_0402_5%

@

C92
C93

14 CFG0
14 CFG1
14 CFG2
14 CFG3

2 51_0402_5%

1@
1@

XDP_PREQ#
XDP_PRDY#
CFG0
CFG1

R25

1

1

2

XDP_DBRESET# R3

2
2

CFG2
1 XDP@ 2
CFG3_R
1K_0402_1%
XDP_OBS0
XDP_OBS1
CFG4
CFG5

14 CFG4
14 CFG5

CFG6
CFG7

14 CFG6
14 CFG7

H_CPUPW RGD 1K_0402_5%
0_0402_5%
8 PBTN_OUT#_R

1 XDP@
1 XDP@

2 R5 H_CPUPW RGD_XDP
2 R14 CFD_PW RBTN#_XDP

0_0402_5%
0_0402_5%

1 XDP@
1 XDP@

2 R15 CPU_PW R_DEBUG_R
2 R16 SYS_PW ROK_XDP

11 CPU_PW R_DEBUG
8 SYS_PW ROK

30,7 PCH_SMBDATA
30,7 PCH_SMBCLK

T3

@

XDP_TCK

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

CONN@

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

CFG17
CFG16

CFG17 14
CFG16 14

CFG8
CFG9

B

CFG8 14
CFG9 14

CFG10
CFG11

CFG10 14
CFG11 14

CFG19
CFG18

CFG19 14
CFG18 14

CFG12
CFG13

CFG12 14
CFG13 14

CFG14
CFG15

CFG14 14
CFG15 14
CLK_CPU_ITP 7
CLK_CPU_ITP# 7

XDP_RST#_R
R7
XDP_DBRESET#_R R19

1 XDP@
1 XDP@

2 1K_0402_5%
2 0_0402_5%

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
CFG3_R

PLT_RST# 33,34,8
XDP_DBRESET# 31,8

C35
@
6.8P_0402_50V8C
1
2

XDP_DBRESET#_R

SAMTE_BSH-030-01-L-D-A

Reserved for ESD

A

A

U1

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

CPU_QDA7

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SA000067H00

5

4

3

2

Title

HSW MCP(1/11) DDI,MSIC,XDP

Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
1

4

of

50

Rev
0.1

5

4

U1C

3

2

HASWELL_MCP_E

U1D

D

C

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

1

SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2

DDR CHANNEL A

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1

AU37
AV37
AW36
AY36

SA_CLK_DDR#0
SA_CLK_DDR0
SA_CLK_DDR#1
SA_CLK_DDR1

AU43
AW43
AY42
AY43

AP32 DDRA_ODT0

AU35
AV35
AY41

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDRA_CKE0_DIMMA 15
DDRA_CKE1_DIMMA 15

AP33
AR32

AY34
AW34
AU34

15
15
15
15

DDRA_CS0_DIMMA# 15
DDRA_CS1_DIMMA# 15
@

T4
DDR_A_RAS# 15
DDR_A_W E# 15
DDR_A_CAS# 15
DDR_A_BS0 15
DDR_A_BS1 15
DDR_A_BS2 15

AU36 DDR_A_MA0
AY37 DDR_A_MA1
AR38 DDR_A_MA2
AP36 DDR_A_MA3
AU39 DDR_A_MA4
AR36 DDR_A_MA5
AV40 DDR_A_MA6
AW39DDR_A_MA7
AY39 DDR_A_MA8
AU40 DDR_A_MA9
AP35 DDR_A_MA10
AW41DDR_A_MA11
AU41 DDR_A_MA12
AR35 DDR_A_MA13
AV42 DDR_A_MA14
AU42 DDR_A_MA15
AJ61 DDR_A_DQS#0
AN62 DDR_A_DQS#1
AM58 DDR_A_DQS#2
AM55 DDR_A_DQS#3
AV57 DDR_A_DQS#4
AV53 DDR_A_DQS#5
AL43 DDR_A_DQS#6
AL48 DDR_A_DQS#7
AJ62 DDR_A_DQS0
AN61 DDR_A_DQS1
AN58 DDR_A_DQS2
AN55 DDR_A_DQS3
AW57DDR_A_DQS4
AW53DDR_A_DQS5
AL42 DDR_A_DQS6
AL49 DDR_A_DQS7
AP49
AR51
AP51

15 DDR_A_D[0..63]
15 DDR_A_MA[0..15]
15 DDR_A_DQS#[0..7]
15 DDR_A_DQS[0..7]

SM_DIMM_VREFCA 15,16
SA_DIMM_VREFDQ 15
SB_DIMM_VREFDQ 16

AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18

HASWELL_MCP_E

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

DDR CHANNEL B

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

AM38
AN38
AK38
AL38

SB_CLK_DDR#0
SB_CLK_DDR0
SB_CLK_DDR#1
SB_CLK_DDR1

AY49
AU50
AW49
AV50

16
16
16
16

DDRB_CKE0_DIMMB 16
DDRB_CKE1_DIMMB 16

AM32
AK32

D

DDRB_CS0_DIMMB# 16
DDRB_CS1_DIMMB# 16

AL32 DDRB_ODT0
AM35
AK35
AM33

@

T5
DDR_B_RAS# 16
DDR_B_W E# 16
DDR_B_CAS# 16

AL35
AM36
AU49

DDR_B_BS0 16
DDR_B_BS1 16
DDR_B_BS2 16

AP40 DDR_B_MA0
AR40 DDR_B_MA1
AP42 DDR_B_MA2
AR42 DDR_B_MA3
AR45 DDR_B_MA4
AP45 DDR_B_MA5
AW46DDR_B_MA6
AY46 DDR_B_MA7
AY47 DDR_B_MA8
AU46 DDR_B_MA9
AK36 DDR_B_MA10
AV47 DDR_B_MA11
AU47 DDR_B_MA12
AK33 DDR_B_MA13
AR46 DDR_B_MA14
AP46 DDR_B_MA15

C

AW30DDR_B_DQS#0
AV26 DDR_B_DQS#1
AN28 DDR_B_DQS#2
AN25 DDR_B_DQS#3
AW22DDR_B_DQS#4
AV18 DDR_B_DQS#5
AN21 DDR_B_DQS#6
AN18 DDR_B_DQS#7
AV30 DDR_B_DQS0
AW26DDR_B_DQS1
AM28 DDR_B_DQS2
AM25 DDR_B_DQS3
AV22 DDR_B_DQS4
AW18DDR_B_DQS5
AM21 DDR_B_DQS6
AM18 DDR_B_DQS7

16 DDR_B_D[0..63]
16 DDR_B_MA[0..15]
16 DDR_B_DQS#[0..7]

B

B

16 DDR_B_DQS[0..7]

Rev1p2

3 OF 19

Rev1p2

4 OF 19

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HSW MCP(2/11) DDRIII

Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
1

5

of

50

Rev
0.1

5

4

3

2

1

PCH_RTCX1

2
10M_0402_5%

PCH_RTCX2

1
D

1

C153
18P_0402_50V8J

2

R69
20K_0402_1%
1
2
1
2
R70
20K_0402_1%
C150
1U_0402_10V6K

C154
18P_0402_50V8J

2

ME CMOS

2

R72

1
@

2

PCH_RTCX1
PCH_RTCX2
2 1M_0402_5% SM_INTRUDER#
PCH_INTVRMEN
PCH_SRTCRST#
PCH_RTCRST#

1

PCH_INTVRMEN

1
1

R73
R74

* HL：
：Integrated
Integrated

@

AW5
AY5
AU6
AV7
AV6
AU7

RTCX1
RTCX2
INTRUDER
INTVRMEN
SRTCRST
RTCRST

SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3

RTC

SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2

R71
0_0603_5%
CMOS

35 HDA_SDIN0
+RTCVCC

HASWELL_MCP_E

U1E

+RTCVCC

1

1

+RTCVCC

Y1
32.768KHZ_12.5PF_FC-135
2
1

C149
1U_0402_10V6K

2

1
R101

RTCRST close RAM door

T6
T7
T8
T9

HDA_BIT_CLK
HDA_SYNC
HDA_RST#
HDA_SDIN0
@
HDA_SDOUT
@
@
@

AW8
AV11
AU8
AY10
AU12
AU11
AW10
AV10
AY8

2 330K_0402_5%
2 330K_0402_5%

HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_RST/I2S_MCLK
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_SDO/I2S0_TXD
HDA_DOCK_EN/I2S1_TXD
HDA_DOCK_RST/I2S1_SFRM
I2S1_SCLK

AUDIO

SATA

SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37

INTVRMEN

VRM enable
VRM disable
T95
51_0402_5% 1

@

2 R97
T21
T19
T15
T10
T11
T22
T12

HDA for AUDIO

@
PCH_JTAG_RST#
PCH_JTAG_TCK
@ PCH_JTAG_TDI
@ PCH_JTAG_TDO
@ PCH_JTAG_TMS
@
@
@ PCH_TCK_JTAGX
@

AU62
AE62
AD61
AE61
AD62
AL11
AC4
AE63
AV2

RP14

C

1
2
3
4

35 HDA_BITCLK_AUDIO
35 HDA_SYNC_AUDIO
35 HDA_RST_AUDIO#
35 HDA_SDOUT_AUDIO

8
7
6
5

SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1

PCH_TRST
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
RSVD
RSVD
JTAGX
RSVD

SATA_IREF
RSVD
RSVD
SATA_RCOMP
SATALED

JTAG

J5
H5
B15
A15

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

31
31
31
31

HDD

J8
H8
A17
B17

D

J6
H6
B14
C15

SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2

31
31
31
31

ODD

F5
E5
C17
D17

PU at Page09
V1
U1
V6
AC1

PCH_GPIO34
PCH_GPIO35
PCH_GPIO36
PCH_GPIO37

A12
L11 @
K10 @
C12
U3

PCH_GPIO34
PCH_GPIO35
PCH_GPIO36
PCH_GPIO37

SATA_IREF
T13
T14
SATA_RCOMP
PCH_SATALED#
R10 1
10K_0402_5%

2

R75

1

9
9
9
9

+1.05VS_ASATA3PLL

2 0_0603_5%

within 500 mils

R2

1

2 3.01K_0402_1%

PCH_SATALED# 34
+3VS
C

HDA_BIT_CLK
HDA_SYNC
HDA_RST#
HDA_SDOUT

Rev1p2

5 OF 19

33_0804_8P4R_5%
R163 1 9012@ 2 0_0402_5%

33 HDA_SDO

R161 1 932@

31,33,7 SPI_WP1#_R

2 4.7K_0402_5%

ME Debug

B

B

W=20mils

trace width 10mil

+RTCBATT

+CHGRTC

W=20mils
+RTCVCC

D22
R445
1K_0402_5%
2
1

2
1

A

A

3
BAS40-04_SOT23-3

1

C151
0.1U_0402_16V4Z

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2

2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HSW MCP(3/11) RTC,SATA,XDP

Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
1

6

of

50

Rev
0.1

5

4

3

2

HASWELL_MCP_E

U1F

PCH_GPIO18

C43
C42
U2

PCH_GPIO19

B41
A41
Y5

XTAL24_IN

1
R48

XTAL24_OUT

9 PCH_GPIO18

Y2
24MHZ_12PF_7A24000134
1
2

9 PCH_GPIO19

2

2

28 CLK_PCIE_LAN#
28 CLK_PCIE_LAN
+3VS
28 LAN_CLKREQ#
30 CLK_PCIE_MINI1#
30 CLK_PCIE_MINI1
30,8 MINI1_CLKREQ#

PCIE LAN

1
C2
12P_0402_50V8J

C3
12P_0402_50V8J

WLAN

C41
B42
AD1

CLK_PCIE_MINI1#
CLK_PCIE_MINI1
MINI1_CLKREQ#

B38
C37
N1

1

+3VS

9 PCH_GPIO23

R216
10K_0402_5%
@

2

VGA_CLKREQ#

A39
B39
U5

PCH_GPIO23

B37
A37
T2

CLK_PEG_VGA#
CLK_PEG_VGA

17 CLK_PEG_VGA#
17 CLK_PEG_VGA

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20

CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22

K21 @
M21 @
C26
C35
C34
AK8
AL8

T16
T17
XCLK_BIASREF

1
1
1
1

R140
R141
R142
R148

AN15
AP15

2
2
2
2

CLKOUT_LPC0
CLKOUT_LPC1

B35
A35

R78

1

1
2

33,34 LPC_AD0
33,34 LPC_AD1
33,34 LPC_AD2
33,34 LPC_AD3
33,34 LPC_FRAME#

1
1
1
1
1

DEG@
DEG@
DEG@
DEG@
DEG@

2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

LAD0
LAD1
LAD2
LAD3
LFRAME

AA3
Y7
Y4
AC2
AA2
AA4
Y6
AF1

R390
R395

CLK_BCLK_ITP#
CLK_BCLK_ITP

R66
R67

2
2 TPM@

1 22_0402_5%
1 22_0402_5%

1 XDP@
1 XDP@

2 0_0402_5%
2 0_0402_5%

SPI

C-LINK

CL_CLK
CL_DATA
CL_RST

AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3

SMB_ALERT#
PCH_SMBCLK
PCH_SMBDATA
PCH_GPIO60
SML0CLK
SML0DATA
PCH_GPIO73
SML1CLK
SML1DATA

CLK_PCI_LPC 33
CLK_PCI_TPM 34
CLK_CPU_ITP# 4
CLK_CPU_ITP 4

AF2
AD2
AF4

@
@
@

SMB_ALERT# 33,9
PCH_SMBCLK 30,4
PCH_SMBDATA 30,4
PCH_GPIO60 9

+3VALW _PCH
T23
T24
T25

SML0CLK
RP8
SML0DATA
PCH_SMBDATA
PCH_SMBCLK
SML1CLK
SML1DATA

D29

1

C66

1

2 932@ RB751V40_SC76-2
2

Q7A
DMN66D0LDW -7_SOT363-6

33_0402_5% 2

1 R108

PCH_SMBDATA

CS#
VCC
DO(IO1) HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)

8
7
6
5

6

2
1

RP19
PCH_SPI_IO3_1
PCH_SPI_CLK_1
PCH_SPI_MOSI_1

1
2
3
4

PCH_SPI_MOSI_1
PCH_SPI_CLK_1
PCH_SPI_IO3_1
PCH_SPI_MISO_1

EN25QH16-104HIP_SO8
9012@

8
7
6
5

PCH_SPI_MOSI
PCH_SPI_CLK
PCH_SPI_HOLD1#
PCH_SPI_MISO

D_CK_SDATA

3

PCH_SMBCLK

B

D_CK_SDATA 15,16,34

4

D_CK_SCLK

D_CK_SCLK 15,16,34

Reserve for EMI(Near SPI ROM)

C152
10P_0402_50V8J
1
2
2
@
R104

SPI ROM ( 4MByte )

1
@

+3VS

PCH_SPI_CLK_1
33_0402_5%

2

1
2 3.3K_0402_5% PCH_SPI_HOLD1#
R103
1 9012@ 2 3.3K_0402_5%
R102
PCH_SPI_W P1#
R564 1 932@ 2 1K_0402_5%

+3VS

Q8A
DMN66D0LDW -7_SOT363-6

PU 2.2K at EC side (+3VS)
C67

1

2 0.1U_0402_16V7K

SML1CLK

6

1

33_0402_5% 2 9012@ 1 R109

SPI ROM ( 8MByte for Chrome)

PCH_SPI_CS1#
PCH_SPI_MISO_2
PCH_SPI_IO2_2

1
2
3
4

CS#
DO
WP#
GND

VCC
HOLD#
CLK
DI

8
7
6
5

RP20
PCH_SPI_IO3_2
PCH_SPI_CLK_2
PCH_SPI_MOSI_2

PCH_SPI_MOSI_2
PCH_SPI_CLK_2
PCH_SPI_IO3_2
PCH_SPI_MISO_2

EN25QH32-104HIP_SO8
9012@

1
2
3
4

EC_SMB_CK2 18,33,36

5

U7

U6

R119
4.7K_0402_5%

Q7B
DMN66D0LDW -7_SOT363-6

33_8P4R_5%

+BIOS_SPI

PCH_SPI_W P1#

2 2.2K_0402_5%
2 2.2K_0402_5%

5

1
2
3
4

PCH_SPI_CS0#
PCH_SPI_MISO_1
PCH_SPI_IO2_1

R116
4.7K_0402_5%

0.1U_0402_16V7K

U6
PCH_SPI_W P1#

R114 1
R113 1

+3VS

2

SPI ROM ( 2MByte )

8 2.2K_0804_8P4R_5%
7
6
5

+3VS
+3VS

B

1
2
3
4

Rev1p2

7 OF 19

D29 design for Debug
board flash SPI ROM
(can be short after MP)

C

PCH_GPIO73 9

R305 1 9012@ 2 0_0402_5%

8
7
6
5

PCH_SPI_MOSI
PCH_SPI_CLK
PCH_SPI_HOLD1#
PCH_SPI_MISO

3

SML1DATA

4

EC_SMB_DA2 18,33,36

Q8B
DMN66D0LDW -7_SOT363-6

33_8P4R_5%
9012@

A

Reserve for EMI(Near SPI ROM)

C453
10P_0402_50V8J
1
2
2
R402
@

1
@

PCH_SPI_CLK_2
33_0402_5%

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

MX25L6406EM2I-12G_SO8
932@

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SA00004G600

5

D

Rev1p2

SMBALERT/GPIO11
SMBCLK
SMBDATA
SML0ALERT/GPIO60
SMBUS
SML0CLK
SML0DATA
SML1ALERT/PCHHOT/GPIO73
SML1CLK/GPIO75
SML1DATA/GPIO74

LPC

SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3

PCH_SPI_CLK_1
PCH_SPI_CS0#
PCH_SPI_MOSI_1
PCH_SPI_MISO_1
PCH_SPI_HOLD1#

+BIOS_SPI

A

+1.05VS_AXCK_LCPLL

HASWELL_MCP_E

U1G

PCH_SPI_MOSI
PCH_SPI_MISO
PCH_SPI_W P1#
PCH_SPI_HOLD1#

31,33,6 SPI_W P1#_R

2 3.01K_0402_1%

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23

AU14
LPC_AD0
AW12
LPC_AD1
AY12
LPC_AD2
AW11
LPC_AD3
LPC_FRAME# AV12

PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#

R572
R599
R603
R602
R604

SIGNALS

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21

6 OF 19

C

PCH_SPI_CLK_1_R
PCH_SPI_CS0#_1_R
PCH_SPI_MOSI_1_R
PCH_SPI_MISO_1_R
31 SPI_HOLD1#_R

TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8

CLOCK

XTAL24_IN
XTAL24_OUT

VGA_CLKREQ#
R221
10K_0402_5%

31
31
31
31

RSVD
RSVD
DIFFCLK_BIASREF

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19

A25
B25

2

1

CLK_PCIE_LAN#
CLK_PCIE_LAN
2 10K_0402_5%
R52 1

XTAL24_IN
XTAL24_OUT

1

D

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18

1

2
1M_0402_5%

1

4

3

2

Title

HSW MCP(4/11) CLK,SPI,SMBUS

Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
1

7

of

50

Rev
0.1

5

4

3

2

1

1

+3VS

Reserved for ESD

R59

31,4 XDP_DBRESET#

1 DEG@ 2 0_0402_5%

2

R227
10K_0402_5%
SYS_RESET#

* LH：
：Enable(DEFAULT)
Disable

DSWODVREN - On Die DSW VR Enable

C39
@
6.8P_0402_50V8C
1
2

PU at Page 4 (double PU)

R124 1
R125 1

D

PM_APW ROK

R64

1

2 0_0402_5%

PCH_PW ROK_R

33 PBTN_OUT#

2

PBTN_OUT#_R

R117 1

PCH_RSMRST#

R61
R62
R63

4 SYS_PW ROK
33 PCH_PW ROK
11,33 VCCST_PG_EC

4 PBTN_OUT#_R

1
R110
0_0402_5%

SUSW ARN#

R79

33 PCH_RSMRST#

2 10K_0402_5%

1

AK2
AC3
AG2
AY7
AB5
AG7

1

AW6
AV4
AL7
AJ8
AN4
AF3
AM5

2 0_0402_5% PCH_RSMRST#_R
SUSW ARN#
PBTN_OUT#_R
PCH_ACIN
2 8.2K_0402_5% PCH_BATLOW #
T31
@

9 SUSW ARN#
+3VALW _PCH

R156 1

2 330K_0402_5%
2 330K_0402_5%

@

D

SYSTEM POWER MANAGEMENT

R206
2 0_0402_5%

SUSACK#
SYS_RESET#
1
2 0_0402_5% SYS_PW ROK_R
1
2 0_0402_5%
PCH_PW ROK_R
1
2 0_0402_5%
@
PM_APW ROK
PLT_RST#
33,34,4 PLT_RST#

@

+RTCVCC

HASWELL_MCP_E

U1H

SUSACK
SYS_RESET
SYS_PWROK
PCH_PWROK
APWROK
PLTRST

AW7
AV5
AJ5

DSWVRMEN
DPWROK
WAKE
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63

RSMRST
SUSWARN/SUSPWRDNACK/GPIO30
PWRBTN
ACPRESENT/GPIO31
BATLOW/GPIO72
SLP_S0
SLP_WLAN/GPIO29

V5
AG4
AE6
AP5

DSW ODVREN
PCH_RSMRST#_R
PCH_PCIE_W AKE#
1
1K_0402_5%
1
8.2K_0402_5%
CLKRUN#
LPCPD#
SUSCLK
PM_SLP_S5#

AJ6
AT4
AL5
AP4
AJ7

PM_SLP_S4#
PM_SLP_S3#
@
@
PM_SLP_LAN#

@
@

SLP_S4
SLP_S3
SLP_A
SLP_SUS
SLP_LAN

+3VALW_PCH

PCH_PCIE_W AKE# 28
+3VALW _PCH
+3VS
CLKRUN# 34
LPCPD# 34
SUSCLK 33
PM_SLP_S5# 33

2 R120
2 R157

T27
T28

@

T29
PM_SLP_S4# 33
PM_SLP_S3# 33

T30
T96
R118 1
@
10K_0402_5%

2

+3VALW _PCH

1

not support Deep S4,S5 can NC
Rev1p2

8 OF 19

R245
100K_0402_5%

DDPB_CTRLDATA: Port B Detected
C

2

D21

1

33,38,40,41 ACIN

2

DDPC_CTRLDATA: Port C Detected

PCH_ACIN

C

RB751V40_SC76-2

*

B

Y

1

(Have internal PD)

R207
10K_0402_5%

B

11,45 VGATE

A
Y

3

EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN

DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA

eDP SIDEBAND

2
VCC

5
4

EC_SMI#
VGA_ON
DGPU_HOLD_RST#
TP_INT#
T26

33 EC_SMI#
37,42,43,44,46,9 VGA_ON
9 DGPU_HOLD_RST#
34 TP_INT#

R310
10K_0402_5%
VGATE_3V

9 PCH_GPIO55
9 PCH_GPIO51

2

U17

NC

B8
A9
C6

1

+1.05VS_VTT

2

+3VS

24 PCH_INV_PW M
33 ENBKL
24 PCH_ENVDD

+3VALW _PCH

1

HASWELL_MCP_E

U1I
PCH_PW ROK

G

U43
MC74VHC1G08DFT2G_SC70-5

2

R208
10K_0402_5%

A

R65
0_0402_5%
1
2
@

SYS_PW ROK

3

1

VGATE_3V

4

0: Port B or C is not detected

1

2

PCH_PW ROK

P

5

+3VS

1: Port B or C is detected

VGATE_3V 33

U6
P4
N4
N2
AD4

@

U7
L1
L3
R5
L4

PCH_GPIO55
PCH_GPIO52
Project_ID1
PCH_GPIO51
Project_ID0

PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME

DISPLAY

GPIO

GPIO55
GPIO52
GPIO54
GPIO51
GPIO53

DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP

DDPB_HPD
DDPC_HPD
EDP_HPD

B9
C9
2 2.2K_0402_5%
R271 1
D9 DDI2_CTRL_CK
DDI2_CTRL_CK 25
D11 DDI2_CTRL_DATA
DDI2_CTRL_DATA 25

C5
B6
B5
A6

DDI1_AUX_DN

DDI1_AUX_DN 26

DDI1_AUX_DP

DDI1_AUX_DP 26

C8
A8
D6

CPU_DP_HPD 26
CPU_HDMI_HPD 25
CPU_EDP_HPD 24

B

GND
74AUP1G07GW _TSSOP5
9 OF 19

Rev1p2

+3VS
R403
0_0402_5%
2
1
@

+3VS
MINI1_CLKREQ# 30,7
DEVSLP0 31,9

+3VS

R391
100K_0402_5%
VGA@

IN1
IN2

OUT

4

PLT_RST_BUF# 28,30

1

2

R416
100K_0402_5%

1

2

U30
MC74VHC1G08DFT2G_SC70-5

2

R214
10K_0402_5%

R215
10K_0402_5%

1

2

Project_ID0

5

Project_ID1 Project_ID0
GPIO54 GPIO53
V5WE2/T2 UMA
0
0
*V5WE2/T2 DIS
0
1
V5WV2
1
0
x
1
1

A

Project ID

2

Project_ID1

R204
10K_0402_5%
@

2

R205
10K_0402_5%
@

1

A

U37
MC74VHC1G08DFT2G_SC70-5
VGA@

+3VS

1

+3VS

1

PLT_RST#

PLTRST_VGA# 17

2

4

VCC

OUT

GND

IN2

3

IN1

1

2

GND

1

DGPU_HOLD_RST#

3

PLT_RST#

VCC

5

8
PCH_GPIO52
7
TP_INT#
6
MINI1_CLKREQ#
5
DEVSLP0
10K_0804_8P4R_5%

5

RP27 1
2
3
4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title

HSW MCP(5/11) PM,GPIO,DDI

Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
1

8

of

50

Rev
0.1

5

4

3

2

1

+3VS
+3VS

8
PCH_GPIO51
7
PCH_GPIO83
6
PCH_GPIO55
5
SERIRQ
10K_0804_8P4R_5%
8
EC_IN_RW
7
PCH_GPIO69
6
PCH_GPIO4
5
PCH_GPIO7
10K_0804_8P4R_5%
8
PCH_GPIO5
7
PCH_GPIO1
6
PCH_GPIO94
5
PCH_GPIO93
10K_0804_8P4R_5%
8
PCH_GPIO2
7
PCH_GPIO91
6
PCH_GPIO90
5
PCH_GPIO38
10K_0804_8P4R_5%
8
PCH_GPIO19
7
PCH_GPIO36
6
VGA_ON
5
EC_KBRST#
10K_0804_8P4R_5%
8
PCH_GPIO18
7
PCH_GPIO35
6
PCH_GPIO48
5
PCH_GPIO34
10K_0804_8P4R_5%
8
PCH_GPIO71
7
PCH_GPIO49
6
PCH_GPIO16
5
PCH_GPIO37
10K_0804_8P4R_5%

D

RP25 1
2
3
4
RP26 1
2
3
4
RP16 1
2
3
4
RP28 1
2
3
4
RP29 1
2
3
4
RP30 8
7
6
5

C

RP31 8
7
6
5
RP32 8
7
6
5
R311 1
10K_0402_5%

PCH_GPIO55 8

RP36

1
2
3
4

8
7
6
5

PCH_GPIO88
PCH_GPIO92
PCH_GPIO85
PCH_GPIO39
10K_0804_8P4R_5%

+1.05VS_VTT

1

RP24 1
2
3
4

PCH_GPIO51 8

HASWELL_MCP_E

U1J

R144
1K_0402_5%
D

33 EC_LID_OUT#

PCH_GPIO19 7
PCH_GPIO36 6
VGA_ON 37,42,43,44,46,8

PCH_GPIO56
PCH_GPIO57
PCH_GPIO58
PCH_GPIO59
PCH_GPIO44
PCH_GPIO47
PCH_GPIO48
PCH_GPIO49
PCH_GPIO50
PCH_GPIO71
PCH_GPIO13
PCH_GPIO14
PCH_GPIO25
PCH_GPIO45
PCH_GPIO46

PCH_GPIO18 7
PCH_GPIO35 6
PCH_GPIO34 6

PCH_GPIO37 6

1
PCH_GPIO67
2
PCH_GPIO65
3
PCH_GPIO6
4
PCH_GPIO64
10K_0804_8P4R_5%
1
PCH_GPIO84
2
PCH_GPIO0
3
PCH_GPIO3
4
PCH_GPIO89
10K_0804_8P4R_5%
1
PCH_GPIO17
2
PCH_GPIO23
3
PCH_GPIO76
4
PCH_GPIO50
10K_0804_8P4R_5%
2
PCH_GPIO70

P1
PCH_GPIO76
AU2
PCH_GPIO8
AM7
EC_LID_OUT# AD6
Y1
PCH_GPIO16
T3
PCH_GPIO17
PCH_GPIO24 AD5
PCH_GPIO27 AN5
PCH_GPIO28 AD7
PCH_GPIO26 AN3

33 EC_SCI#
31,8 DEVSLP0

35 PCH_SPKR

AG6
AP1
AL4
AT5
AK4
AB6
U4
Y3
P3
Y2
AT3
AH4
AM4
AG5
AG3

PCH_GPIO9 AM3
AM2
EC_SCI#
P2
DEVSLP0
C4
PCH_GPIO70
L2
PCH_GPIO38
N5
PCH_GPIO39
V2
PCH_SPKR

BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46

CPU/
MISC

GPIO

LPIO

GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81

PCH_GPIO23 7

THERMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD

GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69

D60
H_THERMTRIP#
V4
T4
SERIRQ
AW15
PCH_OPIRCOMP
AF20 @
T106
AB21 @
T32

R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2

PCH_GPIO83
PCH_GPIO84
PCH_GPIO85
PCH_GPIO86
DGPU_PRSNT#
PCH_GPIO88
PCH_GPIO89
PCH_GPIO90
PCH_GPIO91
PCH_GPIO92
PCH_GPIO93
PCH_GPIO94
PCH_GPIO0
PCH_GPIO1
PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PCH_GPIO5
PCH_GPIO6
PCH_GPIO7
PCH_GPIO64
PCH_GPIO65
PCH_GPIO66
PCH_GPIO67
EC_IN_RW
PCH_GPIO69

2

RP23 1
2
3
4

1

EC_KBRST# 33
SERIRQ 33,34

2 R145
49.9_0402_1%

C

EC_IN_RW 34

Rev1p2

10 OF 19

+3VALW _PCH

B

+3VS

RP37 1
2
3
4
RP38 1
2
3
4
RP39 1
2
3
4
RP40 1
2
3
4
R248 1
10K_0402_5%

SMB_ALERT# 33,7
SUSW ARN# 8
TP_W AKE# 10,34

+3VALW _PCH
+3VALW _PCH

USB_OC1# 10
R301
10K_0402_5%
PCH_GPIO56

+3VS

1

RP35 8
7
6
5

EC_SCI#
SMB_ALERT#
SUSW ARN#
TP_W AKE#
10K_0804_8P4R_5%
1
PCH_GPIO8
2
USB_OC1#
3
PCH_GPIO13
4
PCH_GPIO26
10K_0804_8P4R_5%
8
PCH_GPIO45
7
PCH_GPIO14
6
PCH_GPIO44
5
PCH_GPIO46
10K_0804_8P4R_5%
8
DGPU_HOLD_RST#
7
PCH_GPIO47
6
PCH_GPIO24
5
PCH_GPIO28
10K_0804_8P4R_5%
8
PCH_GPIO58
7
PCH_GPIO59
6
PCH_GPIO27
5
PCH_GPIO25
10K_0804_8P4R_5%
8
USB_OC2#
7
PCH_GPIO60
6
USB_OC0#
5
PCH_GPIO9
10K_0804_8P4R_5%
2
PCH_GPIO73

R269 1

R303
10K_0402_5%

2

8
7
6
5

1

1
2
3
4

2

RP34

@

2 1K_0402_1%

PCH_SPKR

B

PCH_GPIO57

SPKR / GPIO81 :

NO

REBOOT

DGPU_HOLD_RST# 8

1: ENABLED

*
USB_OC2# 10
PCH_GPIO60 7
USB_OC0# 10,32

0: DISABLED (Have internal PD)

+3VS

+3VALW _PCH

PCH_GPIO66
PCH_GPIO86
R247 1

PCH_GPIO73 7

2 10K_0402_5%

EC_LID_OUT#

GPIO15 : TLS Confidentiality

R272 1
R273 1

R270 1

@

2 1K_0402_1%

2 1K_0402_1%
2 1K_0402_5%

@

GSPI0_MOSI / GPIO86 : Boot BIOS Strap

SDIO_D0 / GPIO66 : Top-Block Swap Override

1

+3VS

R306
10K_0402_5%
@

1: Intel ME TLS with confidentiality

1: ENABLED

0: Intel ME TLS with no confidentiality

0: SPI ROM (Have internal PD)

(Have internal PD)

*

*

1: ENABLED (Have internal PU)
0: DISABLED

A

2

*
GPIO87

DGPU_PRSNT#

2

DGPU_PRSNT#

R219
10K_0402_5%
VGA@

DIS,Optimus
UMA
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

0
1

2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

A

4

3

2

Title

HSW MCP(6/11) GPIO,LPIO

Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
1

9

of

50

Rev
0.1

5

4

3

2

HASWELL_MCP_E

U1K
C76
C77

1
1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_GTX_C_HRX_N0 F10
PEG_GTX_C_HRX_P0 E10

PEG_HTX_C_GRX_N0 C78
PEG_HTX_C_GRX_P0 C79

1
1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_HTX_GRX_N0
PEG_HTX_GRX_P0

PEG_GTX_HRX_N1
PEG_GTX_HRX_P1

C80
C81

1
1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_GTX_C_HRX_N1 F8
PEG_GTX_C_HRX_P1 E8

PEG_HTX_C_GRX_N1 C82
PEG_HTX_C_GRX_P1 C83

1
1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_HTX_GRX_N1
PEG_HTX_GRX_P1

PEG_GTX_HRX_N2
PEG_GTX_HRX_P2

C84
C85

1
1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_GTX_C_HRX_N2 H10
PEG_GTX_C_HRX_P2 G10

PEG_HTX_C_GRX_N2 C86
PEG_HTX_C_GRX_P2 C87

1
1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_HTX_GRX_N2
PEG_HTX_GRX_P2

PEG_GTX_HRX_N3
PEG_GTX_HRX_P3

C88
C89

1
1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_GTX_C_HRX_N3 E6
PEG_GTX_C_HRX_P3 F6

PEG_HTX_C_GRX_N3 C90
PEG_HTX_C_GRX_P3 C91

1
1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_HTX_GRX_N3
PEG_HTX_GRX_P3

B22
A21

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3

G11
F11

PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

C29
B30

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4

F13
G13

PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

B29
A29

PEG_GTX_HRX_N0
PEG_GTX_HRX_P0

PEG_GTX_HRX_N[0..3] 17
PEG_GTX_HRX_P[0..3] 17
D

PEG_HTX_C_GRX_N[0..3] 17
PEG_HTX_C_GRX_P[0..3] 17

PCIE LAN

28 PCIE_PRX_DTX_N3
28 PCIE_PRX_DTX_P3
C155
C160

28 PCIE_PTX_C_DRX_N3
28 PCIE_PTX_C_DRX_P3

WLAN

1
1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

30 PCIE_PRX_DTX_N4
30 PCIE_PRX_DTX_P4
C156
C157

30 PCIE_PTX_C_DRX_N4
30 PCIE_PTX_C_DRX_P4

1
1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

C23
C22

B23
A23

B21
C21

G17
F17
C

C30
C31
F15
G15
B31
A31

PERN5_L0
PERP5_L0

USB2N0
USB2P0

PETN5_L0
PETP5_L0

USB2N1
USB2P1

PERN5_L1
PERP5_L1

USB2N2
USB2P2

PETN5_L1
PETP5_L1

USB2N3
USB2P3

PERN5_L2
PERP5_L2

USB2N4
USB2P4

PETN5_L2
PETP5_L2

USB2N5
USB2P5

PERN5_L3
PERP5_L3

USB2N6
USB2P6

PETN5_L3
PETP5_L3

USB2N7
USB2P7

PERN3
PERP3
USB3.0 P1

PETN3
PETP3

USB

PCIe

USB3.0 P2

PETN4
PETP4

R232
R155

1
1

2 3.01K_0402_1%
2 0_0603_5%

@ E15
@ E13
A27
B27

USB3RN1
USB3RP1
USB3TN1
USB3TP1

PERN4
PERP4

USB3RN2
USB3RP2
USB3TN2
USB3TP2

AN8
AM8

USB20_N0
USB20_P0

AR7
AT7

USB20_N1
USB20_P1

AR8
AP8

USB20_N2
USB20_P2

USB20_N0 32
USB20_P0 32

USB2 Port 0 (USB3.0 P0)

USB20_N1 32
USB20_P1 32

USB2 Port 1

USB20_N2 32
USB20_P2 32

USB2 Port 2

AR10
AT10

D

AM15
AL15

USB20_N4
USB20_P4

USB20_N4 30
USB20_P4 30

Mini Card(WLAN+BT)

USB20_N7 24
USB20_P7 24

Camera

AM13
AN13
AP11
AN11
AR13
AP13

USB20_N7
USB20_P7

G20
H20

PCH_USB3_RX0_N 32
PCH_USB3_RX0_P 32

C33
B34

USB3 Port 0

PCH_USB3_TX0_N 32
PCH_USB3_TX0_P 32

E18
F18
B33
A33

PERN1/USB3RN3
PERP1/USB3RP3

C

USB3.0 P3 / PCIE P1

PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4

USB3.0 P4 / PCIE P2

USBRBIAS
USBRBIAS
RSVD
RSVD

PETN2/USB3TN4
PETP2/USB3TP4
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43

+1.05VS_AUSB3PLL
T33
T34
PCIE_RCOMP
PCIE_IREF

1

RSVD
RSVD
PCIE_RCOMP
PCIE_IREF

AJ10
USBRBIAS
AJ11
AN10 @
T35
AM10 @
T36

AL3
AT1
AH2
AV3

R154 1

2 22.6_0402_1%

USB_OC0#
USB_OC1#
USB_OC2#
TP_W AKE#

USB_OC0#
USB_OC1#
USB_OC2#
TP_W AKE#

1

2
11 OF 19

CAD note:
Route single-end 50-ohms and max 450-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils
32,9
9
9
34,9

C612
0.1U_0402_16V4Z
@

Rev1p2

B

B

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HSW MCP(7/11) PCIE,USB

Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
1

10

of

50

Rev
0.1

5

4

3

2

1

Shark Bay ULT have internal gate for VDDQ
+1.35V_CPU
T37
T38

+1.35V_CPU

@ J2

1

@
@

AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50

Q5
@
AO4304L_SO8

8
7
6
5

1
2
3
+CPU_CORE

4

D

1

@

2

R182
0_0402_5%

1

2

T39
T40

@
@

VCC_SENSE_R
T41

@

T42
T43
T44

@
@
@

+VCCIO_OUT
C5
0.1U_0603_25V7K
@

2

45 VR_SVID_CLK

R164
1 0_1206_5%

@

1

2 R165

2
C

2

33,8 VCCST_PG_EC

3

NC

VCC

A
Y

0_0402_5%
0_0402_5%

1
1

2 R167
2 R168
@ C167
2 0.1U_0402_16V7K

1

R309
10K_0402_5%

5
4

45 VR_ON
45,8 VGATE

1

+3VALW _PCH
U16

VCCST_PG_EC_R

4 CPU_PW R_DEBUG

2

1

+1.05VS_VTT

R166
0_0402_5%
1
2
@

T45
T46
T47
T48
T98
T142
T143
T144
T141
T140
T147
T145
T146

VCCST_PWRGD 33,44

74AUP1G07GW _TSSOP5

2

+1.05VS_VTT

AC22
AE22
AE23

1

CPU_PW R_DEBUG

AB57
AD57
AG57
C24
C28
C32

R170
10K_0402_5%
@

RSVD
RSVD

H_CPU_SVIDALRT#

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY

HSW ULT POWER

VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC

1

R172
43_0402_1%
2
1

@
@
@
@
@
@
@
@
@
@
@
@
@

2

1
2
45 VR_ALERT#

D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59

+CPU_CORE

Place the PU
resistors close to CPU
R171
75_0402_1%

B

+1.05VS_VTT
R169
150_0402_1%

+1.05VS_VTT

L62
N63
L63
B59
F60
C59

Reserved Only

GND

SVID ALERT

E63
AB23
A59
E20
AD23
AA23
AE59

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
VIDSOUT
VCCST_PG_EC_R
PCH_VR_EN
VR_READY

0_0402_5%

+3VS

1

F59
N58
AC58

+1.05VS_VTT

+VCCIOA_OUT

R422
100K_0402_5%
@

L59
J58

2

JUMP_43X118

37 3VS_GATE

+CPU_CORE

HASWELL_MCP_E

U1L
+1.35V

C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57

D

C

Rev1p2

12 OF 19

+1.35V_CPU

SVID DATA

B

VDDQ DECOUPLING
+1.05VS_VTT

1
2

2

@

1

2

1

2

1

2

1

2

C17
10U_0603_6.3V6M

1

C16
10U_0603_6.3V6M

2

@

C15
10U_0603_6.3V6M

2

1

C14
10U_0603_6.3V6M

2

1

C13
10U_0603_6.3V6M

+1.05VS_VTT

VIDSOUT

2

1

C12
10U_0603_6.3V6M

2

1

C11
2.2U_0402_6.3V6M

45 VR_SVID_DATA

1

C10
2.2U_0402_6.3V6M

R174
0_0402_5%
2
1

@

C9
2.2U_0402_6.3V6M

R173
130_0402_1%

C8
2.2U_0402_6.3V6M

Place the PU
resistors close to CPU

1
+

C18
330U_2.5V_M

2

+CPU_CORE

C6
22U_0805_6.3V6M

1
2

VCC_SENSE_R

Note: 0 ohm PLACED CLOSE TO CPU
2

1 R178
0_0402_5%

VCC_SENSE 45

1

2

C7
1U_0402_6.3V6K

@

R177
100_0402_1%

1

2

@

+1.35V : 470UF/2V/7343 *2
10UF/6.3V/0603 * 6
2.2UF/6.3V/0402 * 4

A

A

2

1 R235
0_0402_5%

VSS_SENSE 45

1

13 VSS_SENSE_R

2012/07/10

Issued Date
2

Compal Electronics, Inc.

Compal Secret Data

Security Classification

R233
100_0402_1%

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HSW MCP(8/11) Power

Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
1

11

of

50

Rev
0.1

4

3

Near K9

+1.05VS_VTT

2

1
+1.05VS_AUSB3PLL
+1.05VS_ASATA3PLL

C31
1U_0402_6.3V6K
2
@

T99
+1.05VS_APLLOPI

Near L10 Near M9

HDA --> 3.3V or 1.5V
I2C --> 1.8V

+1.05VS_AUSB3PLL

+3VALW _PCH
T105

@ Y20
AA21
W21

C30
mPHY

VCCSUS3_3
VCCRTC
DCPRTC

RTC

SPI

RSVD
VCCAPLL
VCCAPLL

VCCSPI

OPI

VCCASW
VCCASW
@

J13

1
1

2 1U_0402_6.3V6K
2 100U_1206_6.3V6M

2

1 C38
1U_0402_6.3V6K
T116

+1.05VS_ASATA3PLL

Near B11
C46
1
2
L2
C61
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%

1
1

2 1U_0402_6.3V6K
2 100U_1206_6.3V6M

+1.05VS_APLLOPI
R210
0_0805_5%
1
2
1
C47
2
L3 @1
C22
@1
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%

Near AC9

2

Near AH10

2

Near V8

2

VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1

+3VALW _PCH
C28
AC9
1 22U_0805_6.3V6M
AA9
C59 @
1 0.1U_0402_16V7K
AH10
V8
C29
1 22U_0805_6.3V6M
W9

DCPSUS2

VRM/USB2/AZALIA
CORE

VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3

GPIO/LCC

THERMAL SENSOR

+3VS

2 1U_0402_6.3V6K
2 100U_1206_6.3V6M

+1.05VS_AXCK_DCB
+1.05VS_AXCK_LCPLL

C

2

Near J17

+1.05VS_AXCK_DCB

2

Near R21
Near J18
C48
1
2
L4
C23
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%

@ AH13

AXALIA/HDA

VCCHDA

Near AA21

+1.05VS_VTT
+1.05VS_VTT

AH14

1
1

2 1U_0402_6.3V6K
2 100U_1206_6.3V6M

C57
1 1U_0402_6.3V6K
C56
1 1U_0402_6.3V6K

T100
T101
T102

+3VALW _PCH

J18
K19
A20
J17
R21
T21
@ K18
@ M20
@ V21
AE20
AE21

VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3

2 1U_0402_6.3V6K

AH11
AG10
AE7 +VCCRTCEXT 1
C54
+3VS

2

Y8

1 0.1U_0402_16V7K

C58

SDIO/PLSS

VCCTS1_5
VCC3_3
VCC3_3

VCCSDIO
VCCSDIO

+RTCVCC
0.1U_0402_16V7K

2
@

AG14
AG13

1

2

@

1

2

@

1

2
D

+1.05VS_VTT
+1.05VS_VTT

USB3

DCPSUS3

Near B18
C42
1
2
L1
C32
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%

+RTCVCC

1

0.1U_0402_16V7K
C50

2

1

+3VALW _PCH

VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL

0.1U_0402_16V7K
C51

D

1

K9
L10
M9
N8
P9
B18
B11

1

HASWELL_MCP_E

U1M

C20
1U_0402_6.3V6K

C21
1U_0402_6.3V6K

+1.05VS_VTT

2

1U_0402_6.3V6K
C52

5

J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
J15
K14
K16

U8
T9

C27
C33
C40

1
1
1

2 10U_0603_6.3V6M
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
C41
1U_0402_6.3V6K
2+PCH_VCCDSW _R 1
2
0_0402_5%

+PCH_VCCDSW 1
R209
C36 1
C37 1
C43 @1

C55

1

2 22U_0805_6.3V6M
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K

2 0.1U_0402_16V7K

C44 1

2

1U_0402_6.3V6K

+1.05VS_VTT

+1.5VS
+3VS

+3VS
C

LPT LP POWER
SUS OSCILLATOR

USB2

DCPSUS4
RSVD
VCC1_05
VCC1_05

AB8
AC20
AG16
AG17

C53 @1
C25 @1
@

2 1U_0402_6.3V6K
2 100U_1206_6.3V6M
T103

+1.05VS_VTT
C45 1

2

1U_0402_6.3V6K

+1.05VS_AXCK_LCPLL

Near A20
C49
1
2
L5
C24
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%

1
1

13 OF 19

Rev1p2

2 1U_0402_6.3V6K
2 100U_1206_6.3V6M

+3VALW TO +3VALW(PCH AUX Power)
Short J5 for PCH VCCSUS3.3
+3VALW_PCH

+5VALW
B

2

J5 @
JUMP_43X39
2
1
2

R561
100K_0402_5%
@

40mil
D

S

R77
0_0402_5%
1
2
@

33 PCH_PWR_EN

D

S

2
G

Q33
2N7002K_SOT23-3
@

R563
100K_0402_5%
@

PCH_PWR_EN

2

PCH_PWR_EN#

PCH_PWR_EN#

1

2

20mil

1

@
C591
1U_0402_6.3V6K

1

C590
4.7U_0603_6.3V6K

C589
4.7U_0603_6.3V6K
@

1

2@

G

Q10
DMG2301U-7_SOT23-3
@

1

1

2

3
2

1

1

3

+3VALW
B

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HSW MCP(9/11) Power

Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
1

12

of

50

Rev
0.1

5

U1N
D

C

B

A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29

4

3

HASWELL_MCP_E

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U1O

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

14 OF 19

AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20

AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

2

HASWELL_MCP_E

U1P

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
15 OF 19 Rev1p2 VSS

AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31

D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

1

HASWELL_MCP_E

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
16 OF 19 Rev1p2 VSS

H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63

D

C

V58
AH46
V23
E62
AH16

VSS_SENSE_R 11

B

Rev1p2

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HSW MCP(10/11) GND

Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
1

13

of

50

Rev
0.1

5

4

U1Q

T49
T50

D

AY2
DC_TEST_AY2_AW 2
AY3
DC_TEST_AY3_AW 3
AY60
@
DC_TEST_AY61_AW 61 AY61
DC_TEST_AY62_AW 62 AY62
B2
@
B3
DC_TEST_A3_B3
B61
DC_TEST_A61_B61
B62
DC_TEST_B62_B63
B63
C1
DC_TEST_C1_C2
C2

DAISY_CHAIN_NCTF_AY2
DAISY_CHAIN_NCTF_AY3
DAISY_CHAIN_NCTF_AY60
DAISY_CHAIN_NCTF_AY61
DAISY_CHAIN_NCTF_AY62
DAISY_CHAIN_NCTF_B2
DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_B61
DAISY_CHAIN_NCTF_B62
DAISY_CHAIN_NCTF_B63
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2

3

2

HASWELL_MCP_E

1

HASWELL_MCP_E

U1R

DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
17 OF 19 Rev1p2DAISY_CHAIN_NCTF_AW63

A3
A4
A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63

DC_TEST_A3_B3
@
@
DC_TEST_A61_B61
@
@
@
DC_TEST_AY2_AW 2
DC_TEST_AY3_AW 3
DC_TEST_AY61_AW 61
DC_TEST_AY62_AW 62
@

T58
T59
T60
T61
T62

T51
T52
T53
T54

@
@
@
@

AT2
AU44
AV44
D15

T55
T56
T57

@
@
@

F22
H22
J21

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

T63

AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60

4
4
4
4

CFG16
CFG18
CFG17
CFG19

CFG16
CFG18
CFG17
CFG19

AA62
U63
AA61
U62
V63

CFG_RCOMP
T90

@

A5

T91
T92
T93
T94
TD_IREF

@
@
@
@

E1
D1
J20
H18
B12

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

@
@
@
@
@
@
@

T68
T69
T70
T71
T72
T73
T74

D

HASWELL_MCP_E

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP

RESERVED

RSVD
RSVD
RSVD
PROC_OPI_RCOMP

CFG16
CFG18
CFG17
CFG19

RSVD
RSVD

CFG_RCOMP

VSS
VSS

RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
TD_IREF

AV63
AU63

@
@

T75
T76

C63
C62
B43

@
@
@

T77
T78
T79

A51
B51

@
@

T80
T81

L60

@

T82

N60

@

T83

W23
Y22
AY15

@
@

T84
T85
OPI_COMP

AV62
D58

@
@

T86
T87

@
@

T88
T89

CFG Straps for Processor
C

CFG3

1

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

AL1
AM11
AP7
AU10
AU15
AW14
AY14

R224
1K_0402_1%
@

2

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

T64
T65
T66
T67

Physical Debug Enable

P22
N21
P20
R20

(DFX Privacy)

1: DISABLED

CFG3

0: ENABLED; SET DFX ENABLED BIT
IN DEBUG INTERFACE MSR
CFG4

1

C

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

@
@
@
@

Rev1p2

18 OF 19

U1S

N23
R23
T23
U10

Rev1p2

19 OF 19

R225
1K_0402_5%

B

2

B

2

1
CFG_RCOMP
49.9_0402_1%
1
OPI_COMP
49.9_0402_1%
1
TD_IREF
8.2K_0402_5%

R222

2
R223

2
R226

Display Port Presence Strap

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

CFG4

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HSW MCP(11/11) RSVD

Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
1

14

of

50

Rev
0.1

A

B

C

D

E

+1.35V
+1.35V

DDR_A_D44
DDR_A_D41
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D47

+1.35V

All VREF traces should
have 10 mil trace width

Layout Note:
Place near JDIMM1

DDR_A_D51
DDR_A_D50

DDR_A_D49
DDR_A_D48

1

2

1

2

C110
1U_0402_6.3V6K

2

@

C109
1U_0402_6.3V6K

2

1

C108
1U_0402_6.3V6K

1

C107
1U_0402_6.3V6K

@

DDRA_CKE0_DIMMA

5 DDRA_CKE0_DIMMA

DDR_A_BS2

5 DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

2

+1.35V

2

1

2

DDR_A_MA3
DDR_A_MA1

C114
10U_0603_6.3V6M

2

1

C113
10U_0603_6.3V6M

1

C112
10U_0603_6.3V6M

2

C111
10U_0603_6.3V6M

1

DDR_A_MA8
DDR_A_MA5

5 SA_CLK_DDR0
5 SA_CLK_DDR#0

+1.35V

5 DDR_A_BS0

DDR_A_MA10
DDR_A_BS0

5 DDR_A_WE#
5 DDR_A_CAS#

DDR_A_WE#
DDR_A_CAS#

5 DDRA_CS1_DIMMA#

DDR_A_MA13
DDRA_CS1_DIMMA#

1
+

2

C118
330U_2.5V_M

DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D6

SF000002Z00
330U 2.5V H4.2
17mohm OSCON

DDR_A_D21
DDR_A_D20

3

DDR_A_D17
DDR_A_D16

+0.675VS

DDR_A_D36
DDR_A_D33

2

1

2

1

2

C124
1U_0402_6.3V6K

1

C123
1U_0402_6.3V6K

2

@

C122
1U_0402_6.3V6K

1

C121
1U_0402_6.3V6K

@

DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D38
DDR_A_D62
DDR_A_D58

DDR_A_D60
DDR_A_D61

Layout Note:
Place near JDIMM1.203,204
+3VS

2
1

1

2

205
R212
0_0402_5%

1

R211
0_0402_5%

4

@

C126
2.2U_0402_6.3V6M

2

C125
0.1U_0402_16V7K

1

2

+0.675VS

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

G1

G2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

+5VALW

3

DIMM_DRAMRST# 16,4

VCC

A
Y

SA_ODT0

+1.35V
R186
R188 1
66.5_0402_1%
100K_0402_5%
Q18
LBSS138LT1G_SOT-23-3
D
R189 1
2
66.5_0402_1%
G
S
R190 1
M_A_B_DIMM_ODT
66.5_0402_1%

2

SA_ODT1

2

SB_ODT0

2

SB_ODT1

2
5
4

GND
74AUP1G07GW_TSSOP5

DDR_A_D27
DDR_A_D26

2

2

1

2

4 DDR_PG_CTRL
DIMM_DRAMRST#

NC

R187 1
66.5_0402_1%

1

1

U45

1

DDR_A_D25
DDR_A_D24

DDR_A_D45
DDR_A_D40

DDR_VTT_PG_CTRL

DDR_A_D42
DDR_A_D46

DDR_A_DQS#[0..7]

5

DDR_A_DQS[0..7]

5

DDR_A_D[0..63]

DDR_A_D52
DDR_A_D53

SB_ODT0 16

1

SB_ODT1 16

42

5

DDR_A_MA[0..15]

5

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D55

DDRA_CKE1_DIMMA

DDRA_CKE1_DIMMA

5

DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7

2

DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
SA_CLK_DDR1
SA_CLK_DDR#1

SA_CLK_DDR1 5
SA_CLK_DDR#1 5

DDR_A_BS1
DDR_A_RAS#

DDR_A_BS1 5
DDR_A_RAS# 5

DDRA_CS0_DIMMA#
SA_ODT0

DDRA_CS0_DIMMA#

+1.35V
5

R56
1.8K_0402_1%

SA_ODT1
+VREF_CA
DDR_A_D5
DDR_A_D4
@
DDR_A_D3
DDR_A_D7
DDR_A_D18
DDR_A_D19

1

2

1

2

C120
0.1U_0402_16V7K

DDR_A_D0
DDR_A_D1

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_A_D15
DDR_A_D11

C119
2.2U_0402_6.3V6M

2

1
@
2

C117
10U_0603_6.3V6M

1

C116
10U_0603_6.3V6M

2

C115
10U_0603_6.3V6M

1

SA_CLK_DDR0
SA_CLK_DDR#0

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

@

DDR_A_DQS#1
DDR_A_DQS1

3

DDR_A_D30
DDR_A_D31

DDR_A_D9
DDR_A_D12

R296
1
2
2_0402_1%
R295
1.8K_0402_1%

SM_DIMM_VREFCA 16,5

1

2

C162
0.022U_0402_25V7K

1

DDR_A_DQS#3
DDR_A_DQS3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

R294
24.9_0402_1%

2

DDR_A_D29
DDR_A_D28

2

R176
24.9_0402_1%

2

DDR_A_D14
DDR_A_D10

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

1

2

1

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

2

2

1
1

1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

1

2
@
R185
1.8K_0402_1%

2

C106
0.1U_0402_16V7K

C158
0.022U_0402_25V7K

1

1

DDR_A_D13
DDR_A_D8

2

1

JDIMM1
+V_DDR_REFA
R54
1.8K_0402_1%
C105
2.2U_0402_6.3V6M

5 SA_DIMM_VREFDQ

+1.35V

C34
0.1U_0402_16V7K

R293
2_0402_1%
1
2

+1.35V

DDR_A_DQS#2
DDR_A_DQS2

3

DDR_A_D22
DDR_A_D23

+VREF_CA 16

DDR_A_D37
DDR_A_D32

DDR_A_D35
DDR_A_D39
DDR_A_D63
DDR_A_D59
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D56
DDR_A_D57
D_CK_SDATA
D_CK_SCLK

D_CK_SDATA 16,34,7
D_CK_SCLK 16,34,7

+0.675VS

206

TYCO_2-2013022-1
CONN@

Channel A

SP07000JN10
4



DIMM_1 STD H:4mm
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

2013/07/10

Deciphered Date

Title

DDRIII DIMMA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Tuesday, September 25, 2012

Sheet
E

15

of

50

Rev
0.1

A

B

C

D

E

+1.35V

DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3

2

2

DDR_B_D26
DDR_B_D27
DDR_B_D40
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D42

+1.35V

All VREF traces should
have 10 mil trace width

Layout Note:
Place near JDIMM1

DDR_B_D56
DDR_B_D57

DDR_B_D59
DDR_B_D58

1

2

1

2

C132
1U_0402_6.3V6K

2

@

C131
1U_0402_6.3V6K

2

1

C130
1U_0402_6.3V6K

1

C129
1U_0402_6.3V6K

@

DDRB_CKE0_DIMMB

5 DDRB_CKE0_DIMMB

DDR_B_BS2

5 DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

2

+1.35V

2

1

2

DDR_B_MA3
DDR_B_MA1

C136
10U_0603_6.3V6M

2

1

C135
10U_0603_6.3V6M

1

C134
10U_0603_6.3V6M

2

C133
10U_0603_6.3V6M

1

DDR_B_MA8
DDR_B_MA5

5 SB_CLK_DDR0
5 SB_CLK_DDR#0

+1.35V

5 DDR_B_WE#
5 DDR_B_CAS#

DDR_B_WE#
DDR_B_CAS#

5 DDRB_CS1_DIMMB#

DDR_B_MA13
DDRB_CS1_DIMMB#

DDR_B_D4
DDR_B_D1

DDR_B_D3
DDR_B_D7
DDR_B_D21
DDR_B_D20

3

DDR_B_D22
DDR_B_D23

+0.675VS

DDR_B_D36
DDR_B_D33

2

@

1

2

DDR_B_D35
DDR_B_D39
DDR_B_D52
DDR_B_D49

+3VS

2

2

1

C146
1U_0402_6.3V6K

1

C145
1U_0402_6.3V6K

@

C144
1U_0402_6.3V6K

2

C143
1U_0402_6.3V6K

1

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D48
DDR_B_D53

1

Layout Note:
Place near JDIMM1.203,204

R229
10K_0402_5%

+3VS
+0.675VS

2

205

2
1

1

R231
0_0402_5%

4

@

C148
2.2U_0402_6.3V6M

2

C147
0.1U_0402_16V7K

1

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

G1

G2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_DQS#[0..7]

5

DDR_B_DQS[0..7]

5

DDR_B_D[0..63]

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_MA[0..15]

5
5

DDR_B_D13
DDR_B_D15
DDR_B_D25
DDR_B_D24
1

DIMM_DRAMRST#

DIMM_DRAMRST# 15,4

DDR_B_D30
DDR_B_D31
DDR_B_D45
DDR_B_D44

DDR_B_D47
DDR_B_D43
DDR_B_D61
DDR_B_D60
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D63
DDR_B_D62

DDRB_CKE1_DIMMB

DDRB_CKE1_DIMMB

5

DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7

2

DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
SB_CLK_DDR1
SB_CLK_DDR#1

SB_CLK_DDR1 5
SB_CLK_DDR#1 5

DDR_B_BS1
DDR_B_RAS#

DDR_B_BS1 5
DDR_B_RAS# 5

DDRB_CS0_DIMMB#
SB_ODT0

DDRB_CS0_DIMMB#
SB_ODT0 15

SB_ODT1

SB_ODT1 15

+1.35V
5

+VREF_CB
DDR_B_D5
DDR_B_D0
@
DDR_B_D2
DDR_B_D6
DDR_B_D16
DDR_B_D17

1

2

1

2

C142
0.1U_0402_16V7K

DDR_B_DQS#0
DDR_B_DQS0

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_B_D12
DDR_B_D9

C141
2.2U_0402_6.3V6M

2

1
@
2

5 DDR_B_BS0

DDR_B_MA10
DDR_B_BS0

C139
10U_0603_6.3V6M

1

C138
10U_0603_6.3V6M

2

C137
10U_0603_6.3V6M

1

SB_CLK_DDR0
SB_CLK_DDR#0

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

R58
1.8K_0402_1%
@
R300
0_0402_5%
1
2
@

R298
1.8K_0402_1%
@

1

2

@

R302
0_0402_5%
2
1

DDR_B_DQS#2
DDR_B_DQS2

SM_DIMM_VREFCA 15,5
@

C163
0.022U_0402_25V7K

1

2

R179
24.9_0402_1%

DDR_B_D10
DDR_B_D11

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

1

2

1
1

1

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

2

R213
1.8K_0402_1%

2

1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

1

1

@

C128
0.1U_0402_16V7K

C159
0.022U_0402_25V7K

C127
2.2U_0402_6.3V6M

1

R297
2_0402_1%
2

DDR_B_D8
DDR_B_D14

2

1

JDIMM2
+V_DDR_REFB
R57
1.8K_0402_1%

2

1

5 SB_DIMM_VREFDQ

+1.35V

R299
24.9_0402_1%

2

+1.35V

DDR_B_D19
DDR_B_D18

3

+VREF_CA 15

DDR_B_D37
DDR_B_D32

DDR_B_D34
DDR_B_D38
DDR_B_D51
DDR_B_D55
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D50
D_CK_SDATA
D_CK_SCLK

D_CK_SDATA 15,34,7
D_CK_SCLK 15,34,7

+0.675VS

206

TYCO_2-2013022-1
CONN@

Channel B

SP07000JN10
4



DIMM_2 STD H:4mm
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

2013/07/10

Deciphered Date

Title

DDRIII DIMMB

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Tuesday, September 25, 2012

Sheet
E

16

of

50

Rev
0.1

A

B

C

D

E

GFX PCIE LANE REVERSAL
U51A
PEG_HTX_C_GRX_P[0..3]

10 PEG_HTX_C_GRX_P[0..3]

PEG_GTX_HRX_P[0..3]

PART 1 0F 9

PEG_HTX_C_GRX_N[0..3]

10 PEG_HTX_C_GRX_N[0..3]

PEG_GTX_HRX_N[0..3]

PEG_GTX_HRX_P[0..3] 10
PEG_GTX_HRX_N[0..3] 10
U51G

PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0

AA38
Y37

PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_N1

Y35
W36

PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_N2

W38
V37

PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_N3

V35
U36
U38
T37
T35
R36
R38
P37
P35
N36

2

N38
M37

L38
K37
K35
J36
J38
H37
H35
G36
G38
F37

PCIE_TX0P
PCIE_TX0N

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

NC#N38
NC#M37
NC#M35
NC#L36
NC#L38
NC#K37

NC#N33
NC#N32
PCI EXPRESS INTERFACE

M35
L36

PCIE_RX0P
PCIE_RX0N

NC#N30
NC#N29
NC#L33
NC#L32

NC#K35
NC#J36

NC#L30
NC#L29

NC#J38
NC#H37

NC#K33
NC#K32

NC#H35
NC#G36

NC#J33
NC#J32

NC#G38
NC#F37

NC#K30
NC#K29

NC#F35
NC#E37

NC#H33
NC#H32

Y33
Y32

PEG_GTX_HRX_P0
PEG_GTX_HRX_N0

W33
W32

PEG_GTX_HRX_P1
PEG_GTX_HRX_N1

U33
U32

PEG_GTX_HRX_P2
PEG_GTX_HRX_N2

U30
U29

PEG_GTX_HRX_P3
PEG_GTX_HRX_N3

PART 7 0F 9

1

RSVD/VARY_BL
RSVD/DIGON

AK27
AJ27

LVDS CONTROL

TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N
TX4P_DPB1P
TX4M_DPB1N

T33
T32

TX5P_DPB0P
TX5M_DPB0N

T30
T29

LVTMDP

1

P33
P32

NC#AF35
NC#AG36

TXCAP_DPA3P
TXCAM_DPA3N

P30
P29

TX0P_DPA2P
TX0M_DPA2N

N33
N32

TX1P_DPA1P
TX1M_DPA1N

N30
N29

TX2P_DPA0P
TX2M_DPA0N
NC#AN36
NC#AP37

L33
L32
L30
L29

AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37
AF35
AG36

AP34
AR34
AW37
AU35

2

AR37
AU39
AP35
AR35
AN36
AP37

2160842006A0MARSXT_FCBGA962
MARS@

K33
K32
J33
J32
K30
K29

3

3

F35
E37

AB35
AA36

7 CLK_PEG_VGA
7 CLK_PEG_VGA#

H33
H32

CLOCK

PCIE_REFCLKP
PCIE_REFCLKN
CALIBRATION

PCIE_CALR_TX
2 VGA@ 1
AH16
R795
1K_0402_5%

3.3-V tolerant
PLTRST_VGA#

8 PLTRST_VGA#

AA30

TEST_PG

PCIE_CALR_RX

Y30
Y29

VGA_PCIE_CALRP
VGA_PCIE_CALRN

R794 1 MARS@ 2 1.69K_0402_1%

+0.95VSDGPU

R796 1 MARS@ 2 1K_0402_1%

+0.95VSDGPU

PERSTB
2160842006A0MARSXT_FCBGA962
MARS@

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

MARS-Pro_PCIE

Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
E

17

of

50

Rev
0.1

A

B

C

D

U51B

External VGA Thermal Sensor

GPU_DPRSLPVR

+3VSDGPU

1

@

GPU_VID_5

2

@

46 GPU_VID_2

(GPIO1, 2, 7, 11, 12, 13, 18, 21

GPIO_19_CTF
GPU_VID_2

is NC at SUN)

R810 1 MARS@ 2 499_0402_1%

+1.8VSDGPU

AK24

20mil

R811 1 MARS@ 2 249_0402_1%

R
AVSSN

GENERAL PURPOSE I/O

GPIO_0
GPIO_1
GPIO_2

G
AVSSN

GPIO_5_AC_BATT
GPIO_6_TACH
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21
GPIO_22_ROMCSB
CLKREQB

2 0.1U_0402_16V4Z

AH13
(SUN NC)

DAC1

XTALOUT

X2
VGA@
Crystal

3
4

VGA@
C848
10P_0402_50V8J

GND

GND

IN

4

2
8
7
6
5

(SUN NC)

V13
U13
AF33
AF32
AA29
AG21
AC32

NC#V13
NC#U13
NC#AF33
NC#AF32
NC#AA29
NC#AG21
NC#AC32

HPD1

MLPS
100mA

27MHZ_10PF_X3G027000BA1H-U

DBG_VREFG

PS_2

PX_EN

Crystals must have a max ESR of 80 ohm

+1.8VSDGPU

DEBUG

DDC/AUX

AM23
AN23
AK23
AL24
AM24

@

GPU_THERM_D+
GPU_THERM_D-

10U_0603_6.3V6M 2
1U_0402_6.3V6K 2
0.1U_0402_16V4Z 2

13mA
1 @
1 VGA@
1 @

10mil
C844
C845
C846

1

2

AM34

PS_0

AD31

PS_1

AG31

PS_2

AD33

PS_3

2

2

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO

MLPS_EN#

AF29
AG29
AK32

+TSVDD

AJ32
AJ33

DPLUS
DMINUS

AM27
AL27
AM19
AL19

DDC2CLK
DDC2DATA

AN20
AM20

AUX2P
AUX2N

AL30
AM30

NC#AL29
NC#AM29

1

PS0_[1]=1
PS0_[2]=0
PS0_[3]=0
PS0_[4]=1
PS0_[5]=1

R808
8.45K_0402_1%
VGA@
PS_0

L68
BLM18AG121SN1D_2P
1
+1.8VSDGPU
MARS@

R809
2K_0402_1%
VGA@

:
:
:
:
:

B

2.00k

4.53k

2.00k

xx011

6.98k

4.99k

xx100

4.53k

4.99k

xx101

3.24k

5.62k

xx110

3.40k

10.0k

xx111

4.75k

NC

2

00xxx

680nF

01xxx

82nF

10xxx

10nF

11xxx

NC

same as GPIO_11
Since the frame buffer size is 512 MB
same as GPIO_12
the aperture size is set to 256 MB.
same as GPIO_13
Reserved for internal use only. Must be 1
AUD_PORT_CONN_PINSTRAP[0]

100
101
101
101
101
100
101

1
@

2

-

512Kbit
1Mbit
2Mbit
4Mbit
8Mbit
512Kbit
1Mbit

M25P05A
M25P10A
M25P20
M25P40
M25P80
Pm25LV512
Pm25LV010

(ST)
(ST)
(ST)
(ST)
(ST)
(Chingis)
(Chingis)

3

+VDDC_CT

Differential for testing
X76@ and DNI component
for normal operation.
R812
10K_0402_5%

@
R816
10K_0402_5%
PS_1

X76@
R815
10K_0402_5%

1

R818
4.75K_0402_1%
VGA@

@

2

PS_1[1]
PS_1[2]
PS_1[3]
PS_1[4]
PS_1[5]

1

=
=
=
=
=

0
0
0
1
1

:
:
:
:
:

PCIeR GEN3 is not supported.
Reserved for internal use only
Reserved for internal use only
TX_PWRS_ENB: Full Tx output swing.
TX_DEEMPH_EN: Tx deemphasis enabled.

@

2

+VDDC_CT

PS_3[1]
PS_3[2]
PS_3[3]
PS_3[4]
PS_3[5]

=
=
=
=
=

x
x
x
1
1

:
:
VRAM ID
:
: AUD_PORT_CONN_PINSTRAP[1]
: AUD_PORT_CONN_PINSTRAP[2]

PS_2

=======
001

VRAM ID for Mars

=======

Micron MT41K256M16HA-107G:E

PS_2[1]
PS_2[2]
PS_2[3]
PS_2[4]
PS_2[5]

@
R821
10K_0402_5%

=
=
=
=
=

0
0
0
0
1

:
:
:
:
:

Reserved.
Reserved.
BIOS_ROM_EN :Disable the external BIOS ROM device.
VGA_DIS : 0=VGA controller capacity enabled.
Reserved.

R823
4.75K_0402_1%
VGA@

1
VGA@

4

2

AK30
AK29

NC#AK30
NC#AK29

AJ30
AJ31

DDCVGACLK
DDCVGADATA

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

Title

MARS-Pro_STRAP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2160842006A0MARSXT_FCBGA962
MARS@

Rev
0.1

V5WE2 M/B LA-9531P Schematic

Date:

A

8.45k

xx010

+VDDC_CT

AN21
AM21

NC#AN21
NC#AM21

TSVDD
TSVSS

xx001

MARS@
BLM18AG121SN1D_2P

AL29
AM29

GPIO_28_FDO
TS_A

4.75k

+1.8VSDGPU

1 MARS@1 MARS@

AM26
AN26

DDC1CLK
DDC1DATA
TESTEN
AUX1P
AUX1N

AL31
L69
VGA@
0_0603_5%
2
1

@

2

NC

70mA

+VDDC_CT

2

PS_3

THERMAL

1
2
@
R819
10K_0402_5%
1 VGA@ 2
R820
10K_0402_5%

2

PS_3

BACO

NC#AL30
NC#AM30
+3VSDGPU

2

PD(1%) Cap

xx000

1
PS_1

2mA

1
VGA@
C849
10P_0402_50V8J

10mil

1 MARS@

117mA

AC31
AD30
AD32

NC_SVI2#AC31
NC_SVI2#AD30
NC_SVI2#AD32

2

1
@

1

100mA

CEC_1

1

AD28

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS

10K_0804_8P4R_5%
T18

L67

2

2

Bits[5:1] PU(1%)

10mil

R805 1 MARS@ 2 499_0402_1%

(SUN NC)
+AVDD
(SUN NC) MARS@
1
AC33 +VDD1DI
AC34

VDD1DI
VSS1DI

@

2

Mars MLPS configuration

2 10K_0402_5%
2 10K_0402_5%

AD34
AE34

AVDD
AVSSQ

2

C847
0.01U_0402_16V7K

2

OUT

AL21

2 VGA@ 1
TESTEN
R817
1K_0402_5%
1
2
3
4

R803 1 @
R804 1
@

AB34

RSET

RP21
XTALIN

T155
AUD_1
AUD_0

1

2

AUD[1:0]:
00 - No audio function

C842
0.1U_0402_16V4Z

+3VSDGPU

VGA@
R822
1M_0402_5%
2
1

T156

AC36
AC38

HSYNC
VSYNC

GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

R813
0_0402_5%
@

R814
+3VSDGPU 5.11K_0402_1%
2 @
1

AE36
AD35
AF37
AE38

B
AVSSN

GPIO_29
GPIO_30

Place VREFG divider and cap close to ASIC

Pull high @ VGA side

T154

1

+VGA_VREF

AD39
AD37

@

C843
0.1U_0402_16V4Z

1
C841
MARS@

1

I2C

PS_0
AC30

@

AT23
AR22

NC#AT23
NC#AR22

C839
10U_0603_6.3V6M

VREFG:Use a voltage divider to set
VREFG = 1.80 V / 3 (or 0.60-V nominal).

2160842006A0MARSXT_FCBGA962
MARS@

AU22
AV21

NC#AU22
NC#AV21

1

2

AT21
AR20

C838
1U_0402_6.3V6K

3

T137
T138
@

C837
0.1U_0402_16V4Z

AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

NC_XTAL_PVDD
NC_XTAL_PVSS

AK10
AL10

C840
0.1U_0402_16V4Z

AG32
AG33

CLKTESTA
CLKTESTB

AU20
AT19

NC#AU20
NC#AT19

C836
10U_0603_6.3V6M

10K_0402_5% 1

AF30
AF31

C835
0.1U_0402_16V4Z

GPU_VID_1
GPU_VID_3
THM_ALERT#

46 GPU_VID_1
46 GPU_VID_3

NC#AT17
NC#AR16

DPD

SCL
SDA

SPLL_PVSS

AT17
AR16

1 VGA@ 1 VGA@ 1

SPLL_PVSS

AU16
AV15

NC#AU16
NC#AV15

SMBCLK SMBus
SMBDATA

@

C834
1U_0402_6.3V6K

AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13

GPU_VID_4

R806

AH20
AH18
AN16

R409
2 100K_0402_5%

GPU VID need check
46 GPU_VID_5

DPC

XO_IN2

L66
BLM18AG121SN1D_2P
1
+0.95VSDGPU
VGA@

2

+SPLL_VDDC

SPLL_VDDC

AN10

SPLL_PVSS

2

1
AW35 XO_IN2 2
@
0_0402_5% R802

2

AK26
AJ26

2

33 GPU_ACIN
46 GPU_VID_4

AT15
AR14

NC#AT15
NC#AR14

100mA

2

1

C833
10U_0603_6.3V6M

AJ23
AH23

Slave ID: 0x41

46 GPU_DPRSLPVR

NC#AU14
NC#AV13

+SPLL_VDDC AN9

2
XO_IN 1
@
0_0402_5% R799

C832
1U_0402_6.3V6K

@
@

AU14
AV13

AW34

C891
R841
0.1U_0402_16V4Z 51.1_0402_1%

VGA_SMB_CK2
VGA_SMB_DA2

SPLL_PVDD

AT33
AU32

NC#AT33
NC#AU32

NC#AT21
NC#AR20

0_0402_5%
2VGA_SMB_CK2_R
2VGA_SMB_DA2_R
0_0402_5%

XO_IN
+SPLL_PVDD AM10

C892
R904
0.1U_0402_16V4Z 51.1_0402_1%

R898
1
1
R899

2

AR32
AT31

NC#AR32
NC#AT31

1 VGA@ 1 VGA@ 1

C831
0.1U_0402_16V4Z

EC_SMB_DA2 33,36,7

MPLL_PVDD
MPLL_PVDD

2

EC_SMB_CK2 33,36,7

NC#AV31
NC#AU30

H7
H8

+MPLL_PVDD

1

EC_SMB_CK2

@

AV31
AU30

2

5
2

1

VGA_SMB_DA2

3

Q54A
VGA@
DMN66D0LDW-7_SOT363-6
6
EC_SMB_DA2

DPB

XTALOUT

AR30
AT29

NC#AR30
NC#AT29

L65
BLM18AG121SN1D_2P
1
+1.8VSDGPU
VGA@

2

+SPLL_PVDD

1

2

2
1

1

4

Q54B
VGA@
DMN66D0LDW-7_SOT363-6

75mA

2

SM010030010 200ma
120ohm@100mhz DCR 0.2

C830
10U_0603_6.3V6M

R801
4.7K_0402_5%
VGA@

XTALOUT

AT27
AR26

NC#AT27
NC#AR26

2

C829
1U_0402_6.3V6K

VGA_SMB_CK2

T112
T113
T114
T115
T118
T117
T119
T121
T120
T122
T124
T123
T125
T127
T126
T128
T130
T129
T131
T133
T132
T134
T136
T135

AU34

2

C828
0.1U_0402_16V4Z

+3VSDGPU

NC#AR8
NC#AU8
DBG_CNTL0
NC#AW8
NC#AR3
NC#AR1
DBG_DATA0
DBG_DATA1
DBG_DATA2
DBG_DATA3
DBG_DATA4
DBG_DATA5
DBG_DATA6
DBG_DATA7
DBG_DATA8
DBG_DATA9
DBG_DATA10
DBG_DATA11
DBG_DATA12
DBG_DATA13
DBG_DATA14
DBG_DATA15
DBG_DATA16
DBG_DATA17
DBG_DATA18
DBG_DATA19
DBG_DATA20
DBG_DATA21
DBG_DATA22
DBG_DATA23

XTALIN

AU26
AV25

PLLS/XTAL

AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

T111

+3VSDGPU

R800
4.7K_0402_5%
VGA@

DPA

NC#AU26
NC#AV25

ADM1032ARMZ-2REEL_MSOP8

R03 modify BOM

SWAPLOCKA
SWAPLOCKB

2

+3VSDGPU

XTALIN

2

VGA@2
4.7K_0402_5%

AV33

1

1
R798

1 VGA@ 1 VGA@ 1

@

AT25
AR24

NC#AT25
NC#AR24

2

5

AJ21
AK21

1

GND

THM_ALERT#

AU24
AV23

NC#AU24
NC#AV23

2

ALERT#

THERM#

VGA_SMB_DA2

6

+MPLL_PVDD
PART 9 0F 9

MUTI GFX

GENLK_CLK
GENLK_VSYNC

1

D-

7

AD29
AC29

T109
T110

2

4

SDATA

VGA_SMB_CK2

C826
10U_0603_6.3V6M

GPU_THERM_D-

D+

3

8

C825
1U_0402_6.3V6K

2

SCLK

C824
0.1U_0402_16V4Z

1

C823
0.1U_0402_16V4Z

2

GPU_THERM_D+
2200P_0402_50V7K
2 VGA@
C827 1

VDD

1

U52 VGA@

1
1 VGA@

L64
BLM18AG121SN1D_2P
2
1
+1.8VSDGPU
VGA@

130mA

2

+3VSDGPU

E

U51I
PART 2 0F 9

C

D

Tuesday, September 25, 2012
E

Sheet

18

of

50

A

B

C

D

E

MAA[0..15]

U51D

MAA[0..15] 22

U51C
PART 4 0F 9

1

2

R828

1

2

40.2_0402_1%
MARS@

2

100_0402_1%
MARS@

1 MARS@

2

C852
1U_0402_6.3V6K

R830

15mil
MVREFSA

3

L18
L20
L27
N12
AG12

R835 1 VGA@

2 120_0402_1% M27

CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1

MVREFDA
MVREFSA

CKEA0
CKEA1

NC#L27
NC#N12
NC#AG12

W EA0B
W EA1B

MEM_CALRP0
NC#M12
NC#AH12

MAA0_8/MAA_13
MAA1_8/MAA_14
MAA0_9/MAA_15
MAA1_9/RSVD

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

J21
G19

ODTA0
ODTA1

H27
G27

CLKA0
CLKA0#

J14
H14

CLKA1
CLKA1#

K23
K19

RASA0#
RASA1#

K20
K17

CASA0#
CASA1#

K24
K27

CSA0#

M13
K16

CSA1#

K21
J20

CKEA0
CKEA1

K26
L15

WEA0#
WEA1#

H23
J19
M21
M20

MAA13
MAA14
MAA15

DQMA#[0..7] 22

ODTA0 22
ODTA1 22
CLKA0 22
CLKA0# 22
CLKA1 22
CLKA1# 22
RASA0# 22
RASA1# 22
CASA0# 22
CASA1# 22
CSA0# 22
CSA1# 22

MVREFDB Y12
MVREFSB AA12

CKEA0 22
CKEA1 22

DDBIB0_0/QSB_0B
DDBIB0_1/QSB_1B
DDBIB0_2/QSB_2B
DDBIB0_3/QSB_3B
DDBIB1_0/QSB_4B
DDBIB1_1/QSB_5B
DDBIB1_2/QSB_6B
DDBIB1_3/QSB_7B
ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1

MVREFDB
MVREFSB

W EB0B
W EB1B

WEA0# 22
WEA1# 22

MAB0_8/MAB_13
MAB1_8/MAB_14
MAB0_9/MAB_15
MAB1_9/RSVD
DRAM_RST

H3
H1
T3
T5
AE4
AF5
AK6
AK5

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

T7
W7

ODTB0
ODTB1

L9
L8

CLKB0
CLKB0#

AD8
AD7

CLKB1
CLKB1#

T10
Y10

RASB0#
RASB1#
CASB0#
CASB1#
CSB0#

AD10
AC10

CSB1#

U10
AA11

CKEB0
CKEB1

N10
AB11

WEB0#
WEB1#

T8
W8
U12
V12

MAB13
MAB14
MAB15

2160842006A0MARSXT_FCBGA962
MARS@

1

QSA#[0..7] 22

MAB[0..15]

MAB[0..15] 23
1

DQMB#[0..7]

DQMB#[0..7] 23

QSB[0..7]

QSB[0..7] 23

QSB#[0..7]

B_BA2 23
B_BA0 23
B_BA1 23

QSB#[0..7] 23

+1.5VSDGPU

VGA@

W 10
AA10

2160842006A0MARSXT_FCBGA962
MARS@

QSA[0..7] 22

QSA#[0..7]

R824

P10
L10

AH11

QSA[0..7]

1

A34
E30
E26
C20
C16
C12
J11
F8

EDCB0_0/QSB_0
EDCB0_1/QSB_1
EDCB0_2/QSB_2
EDCB0_3/QSB_3
EDCB1_0/QSB_4
EDCB1_1/QSB_5
EDCB1_2/QSB_6
EDCB1_3/QSB_7

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

40.2_0402_1%

15mil

2

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

W CKB0_0/DQMB_0
W CKB0B_0/DQMB_1
W CKB0_1/DQMB_2
W CKB0B_1/DQMB_3
W CKB1_0/DQMB_4
W CKB1B_0/DQMB_5
W CKB1_1/DQMB_6
W CKB1B_1/DQMB_7

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

2

M12
AH12

ADBIA0/ODTA0
ADBIA1/ODTA1

C34
D29
D25
E20
E16
E12
J10
D7

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

MVREFDB

1 VGA@

R827 VGA@
100_0402_1%

ODTB0 23
ODTB1 23

2

2

+1.5VSDGPU

CLKB0 23
CLKB0# 23
CLKB1 23
CLKB1# 23

R829
VGA@

RASB0# 23
RASB1# 23

40.2_0402_1%

15mil

CASB0# 23
CASB1# 23

MVREFSB

1 VGA@

R831

C853
1U_0402_6.3V6K

MVREFDA
MVREFSA

DDBIA0_0/QSA_0B
DDBIA0_1/QSA_1B
DDBIA0_2/QSA_2B
DDBIA0_3/QSA_3B
DDBIA1_0/QSA_4B
DDBIA1_1/QSA_5B
DDBIA1_2/QSA_6B
DDBIA1_3/QSA_7B

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

GDDR5/DDR3

DQB0_0
DQB0_1
DQB0_2
DQB0_3
DQB0_4
DQB0_5
DQB0_6
DQB0_7
DQB0_8
DQB0_9
DQB0_10
DQB0_11
DQB0_12
DQB0_13
DQB0_14
DQB0_15
DQB0_16
DQB0_17
DQB0_18
DQB0_19
DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31
DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8
DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31

C851
1U_0402_6.3V6K

+1.5VSDGPU

EDCA0_0/QSA_0
EDCA0_1/QSA_1
EDCA0_2/QSA_2
EDCA0_3/QSA_3
EDCA1_0/QSA_4
EDCA1_1/QSA_5
EDCA1_2/QSA_6
EDCA1_3/QSA_7

A32
C32
D23
E22
C14
A14
E10
D9

A_BA2 22
A_BA0 22
A_BA1 22

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

1

2

W CKA0_0/DQMA_0
W CKA0B_0/DQMA_1
W CKA0_1/DQMA_2
W CKA0B_1/DQMA_3
W CKA1_0/DQMA_4
W CKA1B_0/DQMA_5
W CKA1_1/DQMA_6
W CKA1B_1/DQMA_7

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

2

2
1
2

100_0402_1%
MARS@

1 MARS@
C850
1U_0402_6.3V6K

R826

15mil
MVREFDA

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_BA2
MAA1_6/MAA_BA0
MAA1_7/MAA_BA1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1

1

R825
40.2_0402_1%
MARS@

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

2

1

+1.5VSDGPU

GDDR5/DDR3

1

1

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

MEMORY INTERFACE A

(SUN 64 bin on at Channel B)

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

DQMA#[0..7]

MDB[0..63]

VGA@

CSB0# 23

100_0402_1%

2

2

MDA[0..63]

22 MDA[0..63]

23 MDB[0..63]

MEMORY INTERFACE B

PART 3 0F 9

CSB1# 23
CKEB0 23
CKEB1 23

3

WEB0# 23
WEB1# 23

1
2
1
2
VGA@
VGA@
R838
R839
10_0402_5% 1 VGA@ 51.1_0402_1%
VGA@
C854
R840
120P_0402_50V8
4.99K_0402_1%
2

VRAM_RST# 22,23

Place all these components very close
to GPU (Within 25mm) and
keep all component close to
each Other (within5mm) except Rser2
The suggested components are tested on the AMD
reference board only. Customers must measure the slew
on each memory part to ensure that the slew rate meets
the DRAM specification.

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

4

2013/07/10

Title

MARS-Pro_MEMORY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Sheet

Tuesday, September 25, 2012
E

19

of

50

Rev
0.1

A

B

C

D

E

U51E
PART 5 0F 9

+1.5VSDGPU

VGA@

@

300mA

20mil
+VDDR4
1
@
2

AF23
AF24
AG23
AG24
AD12
AF11
AF12
AF13
AF15
AG11
AG13
AG15

I/O

VDDR3
VDDR3
VDDR3
VDDR3
DVP

VDDR4
VDDR4
VDDR4
VDDR4

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

VDDR4
VDDR4
VDDR4
VDDR4

(SUN NC)

1
2

2

2

+0.95VSDGPU

@
1

30A (TBD)

2

2

+0.95VSDGPU

VGA@
1

2

Must always be connected to PCIE_VDDC.
0.95 V for "Mars" and
"Heathrow"/"Chelsea" on both BACO and
non-BACO designs.
2

AH22
AH27
AH28
M26
N24
R18
R21
R23
R26
T17
T20
T22
T24
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

3

360mil
+VGA_CORE

3.5A (DDR3)
1
@
2

1
@
2

1
@
2

1
@
2

1
@
2

1
@
2

1
@
2

C923
10U_0603_6.3V6M

@
R842
0_0402_5%

VGA@
1

C922
1U_0402_6.3V6K

FB_GND

1

VGA@
1

C921
1U_0402_6.3V6K

FB_VDDCI

2

C920
1U_0402_6.3V6K

46 VSS_GPU_SENSE

AG28

2

C919
0.1U_0402_16V4Z

T139

VSS_GPU_SENSE AH29

FB_VDDC

VGA@
1
+VGA_CORE

C918
0.1U_0402_16V4Z

VCC_GPU_SENSE AF28

VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI

2

@
1

1.4A 60mil

C917
0.1U_0402_16V4Z

VOLTAGE
SENESE

10mil
46 VCC_GPU_SENSE

ISOLATED
CORE I/O

3

2

@
1

C876
10U_0603_6.3V6M

2

VGA@
1

2

25mA

+VDDR3

C899
0.1U_0402_16V4Z

2

C908
1U_0402_6.3V6K

SM010014520 3000ma
220ohm@100mhz
DCR 0.04

C907
10U_0603_6.3V6M

L72
FBMA-L11-201209-221LMA30T_0805
2
1
+1.8VSDGPU
MARS@
MARS@ MARS@
1
1

2

10mil

C898
0.1U_0402_16V4Z

2

VGA@
1

C897
1U_0402_6.3V6K

@
1

VGA@

C896
1U_0402_6.3V6K

2
1
L71
BLM18AG121SN1D_2P

2

VDD_CT
VDD_CT
VDD_CT
VDD_CT

2

@
1

C875
1U_0402_6.3V6K

+3VSDGPU

1
@

LEVEL
TRANSLATION

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18

2

@
1

2

+1.8VSDGPU

C888
10U_0603_6.3V6M

2

13mA

+VDDC_CT AF26
AF27
AG26
AG27

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

N27
T27

100mil

@
1

C889
1U_0402_6.3V6K

2

VGA@
2

C887
0.1U_0402_16V4Z

VGA@
1

C886
1U_0402_6.3V6K

VGA@
1

C885
10U_0603_6.3V6M

1
L70
BLM18AG121SN1D_2P

20mil

2

CORE

BIF_VDDC
BIF_VDDC

2.5A

VGA@
1

C890
1U_0402_6.3V6K

+VDDC_CT
+1.8VSDGPU

BACO

2

@
1

C874
1U_0402_6.3V6K

2

2

C873
1U_0402_6.3V6K

2

@
1

C872
1U_0402_6.3V6K

2

VGA@
1

100mA

C871
1U_0402_6.3V6K

2

VGA@
1

C884
2.2U_0402_6.3V6M

2

VGA@
1

C883
2.2U_0402_6.3V6M

2

VGA@
1

C882
2.2U_0402_6.3V6M

2

@
1

C881
2.2U_0402_6.3V6M

2

C880
2.2U_0402_6.3V6M

@
1

C879
10U_0603_6.3V6M

VGA@
1

C878
10U_0603_6.3V6M

VGA@
1

C877
10U_0603_6.3V6M

VGA@
1

2

NC For Mars

C870
1U_0402_6.3V6K

2

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

20mil

C869
1U_0402_6.3V6K

2

VGA@
1

C868
0.1U_0402_16V4Z

@
1

C867
0.1U_0402_16V4Z

2

VGA@
1

C866
0.1U_0402_16V4Z

2

C865
0.1U_0402_16V4Z

@
1

C864
0.1U_0402_16V4Z

VGA@
1

AA31
AA32
AA33
AA34
W30
Y31
V28
W29
AB37

C863
10U_0603_6.3V6M

1

NC#AA31
NC#AA32
NC#AA33
NC#AA34
NC#W30
NC#Y31
NC_BIF_VDDC
NC_BIF_VDDC
PCIE_PVDD

C862
1U_0402_6.3V6K

2

MEM I/O

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

C861
1U_0402_6.3V6K

2

VGA@
1

C860
0.01U_0402_16V7K

2

@
1

C859
0.01U_0402_16V7K

2

VGA@
1

C858
0.01U_0402_16V7K

1

C857
0.01U_0402_16V7K

2

C856
0.01U_0402_16V7K

1

AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

PCIE

1.5A

2160842006A0MARSXT_FCBGA962
MARS@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

MARS-Pro_PWR/GND

Size Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Tuesday, September 25, 2012
E

Sheet

20

of

50

Rev
0.1

A

B

C

D

E

U51F
PART 6 0F 9

1

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

NC#AG22

AP20
AP21
AP22
AP23
AU18
AV19

AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20

237mA
+1.8VSDGPU

AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

@
1

2

VGA@
1

VGA@
1

2

2

AH34
AJ34
AF34
AG34
AM37
AL38
AM32

DP_VDDC

DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC

NC#AN24
NC#AP24
NC#AP25
NC#AP26
NC#AU28
NC#AV29
NC#AP20
NC#AP21
NC#AP22
NC#AP23
NC#AU18
NC#AV19

NC#AP13
NC#AT13
NC#AP14
NC#AP15

DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR

CALIBRATION

AW28

AW18
R845
150_0402_1%
2 MARS@ 1 AM39

AP31
AP32
AN33
AP33
AL33
AM33
AK33
AK34
AN31

20mil
+0.95VSDGPU

280mA

1 VGA@ 1 VGA@ 1 VGA@

2

AP13
AT13
AP14
AP15

2

2

2

DP GND

DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR

C938
0.1U_0402_16V4Z

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

AN24
AP24
AP25
AP26
AU28
AV29

C937
1U_0402_6.3V6K

4

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

PART 8 0F 9
DP_VDDR

C936
10U_0603_6.3V6M

3

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

U51H

C929
10U_0603_6.3V6M

2

1

C928
1U_0402_6.3V6K

GND

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20

C927
0.1U_0402_16V4Z

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

NC#AW28

NC#AW18

DP_CALR

AN27
AP27
AP28
AW24
AW26
AN29
AP29
AP30
AW30
AW32
AN17
AP16
AP17
AW14
AW16
AN19
AP18
AP19
AW20
AW22
AN34
AP39
AR39
AU37
AF39
AH39
AK39
AL34
AV27
AR28
AV17
AR18
AN38
AM35
AN32

3

2160842006A0MARSXT_FCBGA962
MARS@

AG22

4

VSS_MECH
VSS_MECH
VSS_MECH

A39
AW1
AW39

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

2013/07/10

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2160842006A0MARSXT_FCBGA962
MARS@

V5WE2 M/B LA-9531P Schematic

Date:

A

MARS-Pro_PWR/GND

B

C

D

Tuesday, September 25, 2012

Sheet
E

21

of

50

Rev
0.1

B

C

M2
N8
M3

19 A_BA0
19 A_BA1
19 A_BA2

CLKA0
CLKA0#
19 CKEA0
19 ODTA0
19 CSA0#
19 RASA0#
19 CASA0#
19 WEA0#

ODTA0

J7
K7
K9
K1
L2
J3
K3
L3

QSA2
QSA0

F3
C7

DQMA#2
DQMA#0

E7
D3

QSA#2
QSA#0

G3
B7

2

VRAM_RST#

19,23 VRAM_RST#

T2

1

L8

D7
C3
C8
C2
A7
A2
B8
A3

MDA0
MDA5
MDA1
MDA7
MDA3
MDA4
MDA2
MDA6

VREFDA_Q1
VREFCA_A1
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

+1.5VSDGPU

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

R846
243_0402_1%
128@

J1
L1
J9
L9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDA23
MDA19
MDA22
MDA18
MDA21
MDA16
MDA20
MDA17

B2
D9
G7
K2
K8
N1
N9
R1
R9

M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A_BA0
A_BA1
A_BA2

M2
N8
M3

CLKA0
CLKA0#
CKEA0

J7
K7
K9

+1.5VSDGPU
A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTA0
CSA0#
RASA0#
CASA0#
WEA0#

K1
L2
J3
K3
L3

QSA3
QSA1

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#3
DQMA#1

E7
D3

QSA#3
QSA#1

G3
B7

VRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

R847
243_0402_1%
128@

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@
+1.5VSDGPU

MDA25
MDA30
MDA24
MDA29
MDA26
MDA31
MDA27
MDA28

D7
C3
C8
C2
A7
A2
B8
A3

MDA14
MDA11
MDA12
MDA10
MDA13
MDA9
MDA15
MDA8

VREFCA_A3
VREFDA_Q3

+1.5VSDGPU

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9

A_BA0
A_BA1
A_BA2

M2
N8
M3

CLKA1
CLKA1#

J7
K7
K9

19 CKEA1

+1.5VSDGPU

19 ODTA1
19 CSA1#
19 RASA1#
19 CASA1#
19 WEA1#

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

ODTA1

K1
L2
J3
K3
L3

QSA4
QSA5

F3
C7

DQMA#4
DQMA#5

E7
D3

QSA#4
QSA#5

G3
B7

VRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R848
243_0402_1%
128@

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@

J1
L1
J9
L9

VREFCA
VREFDQ

R850
4.99K_0402_1% 128@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA35
MDA32
MDA38
MDA34
MDA37
MDA36
MDA39
MDA33

D7
C3
C8
C2
A7
A2
B8
A3

MDA43
MDA44
MDA40
MDA45
MDA42
MDA46
MDA41
MDA47

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A_BA0
A_BA1
A_BA2

M2
N8
M3

CLKA1
CLKA1#
CKEA1

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTA1
CSA1#
RASA1#
CASA1#
WEA1#

K1
L2
J3
K3
L3

QSA6
QSA7

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#6
DQMA#7

E7
D3

QSA#6
QSA#7

G3
B7

+1.5VSDGPU

VRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R849
243_0402_1%
128@

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@
+1.5VSDGPU

R851
4.99K_0402_1% 128@

VREFDA_Q3
VREFCA_A3

+1.5VSDGPU

BA0
BA1
BA2

1

+1.5VSDGPU

1

E3
F7
F2
F8
H3
H8
G2
H7

1

QSA#[0..7]

19 QSA#[0..7]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

J1
L1
J9
L9

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA48
MDA51
MDA55
MDA54
MDA50
MDA52
MDA49
MDA53

D7
C3
C8
C2
A7
A2
B8
A3

MDA63
MDA58
MDA60
MDA59
MDA61
MDA56
MDA62
MDA57

X76
ZZZ1
X7601@

X76402BOL01
4Gbx8 Micron 256M16
1

+1.5VSDGPU

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

QSA[0..7]

19 QSA[0..7]

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

U57

B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VSDGPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

2

B1
B9
D1
D8
E2
E8
F9
G1
G9

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@

+1.5VSDGPU

1

DQMA#[0..7]

19 DQMA#[0..7]

VREFCA
VREFDQ

1

MDA[0..63]

19 MDA[0..63]

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

1

MAA[0..15]

19 MAA[0..15]
1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

E

U56

2

VREFCA_A1 M8
VREFDA_Q1 H1

D

U55

2

U54

1

A

R854
4.99K_0402_1% 128@

R855
4.99K_0402_1%
128@

3

3

2
1

VREFDA_Q3

1

+1.5VSDGPU

128@

+1.5VSDGPU

2

R863
C944
4.99K_0402_1%
128@
2

2

1

C943

2

2

2

C940
128@

R862
4.99K_0402_1%
128@

1

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

R859
4.99K_0402_1%
128@

0.1U_0402_16V4Z

128@

0.1U_0402_16V4Z

1

C939

15mil

VREFCA_A3

1

VREFDA_Q1

1

VREFCA_A1
R858
4.99K_0402_1%
128@

15mil

2

15mil

2

2

15mil

128@

2

+1.5VSDGPU
+1.5VSDGPU

2

2

2

2

2

2

2

2

2

2

1

1

2

2

2

C406
0.01U_0402_16V7K
2
128@

128@
1

128@
1

2

2

2

2

2

2

2

2

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

128@
1

2

C975
10U_0603_6.3V6M

2
40.2_0402_1%

128@
1

C974
10U_0603_6.3V6M

2

128@

128@
1
C971
10U_0603_6.3V6M

1
R869

128@
1
C970
10U_0603_6.3V6M

19 CLKA1#

2
40.2_0402_1%

128@
1
C969
10U_0603_6.3V6M

1
R868

C968
10U_0603_6.3V6M

128@
19 CLKA1

128@
1

C973
10U_0603_6.3V6M

4

+1.5VSDGPU

+1.5VSDGPU

C972
10U_0603_6.3V6M

C395
0.01U_0402_16V7K
2
128@

128@
1

2012/07/10

C966
1U_0402_6.3V6K

2

128@
1

C965
1U_0402_6.3V6K

2

128@
1

C964
1U_0402_6.3V6K

2

128@
1

C963
1U_0402_6.3V6K

2

2
40.2_0402_1%

128@
1

C962
1U_0402_6.3V6K

2

128@

C961
1U_0402_6.3V6K

128@
1

C960
1U_0402_6.3V6K

128@
1

C959
1U_0402_6.3V6K

128@
1

C958
1U_0402_6.3V6K

128@
1

C957
1U_0402_6.3V6K

128@
1

C956
1U_0402_6.3V6K

128@
1

C955
1U_0402_6.3V6K

128@
1

C954
1U_0402_6.3V6K

128@
1

C953
1U_0402_6.3V6K

128@
1

C952
1U_0402_6.3V6K

128@
1

C951
1U_0402_6.3V6K

128@
1

C950
1U_0402_6.3V6K

1
R867

128@
1

C949
1U_0402_6.3V6K

19 CLKA0#

2
40.2_0402_1%

128@
1

C948
1U_0402_6.3V6K

1
R866

128@
1

C947
1U_0402_6.3V6K

128@
19 CLKA0

128@
1

2013/07/10

Deciphered Date

Title

VRAM_DDR3 / Channel A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Tuesday, September 25, 2012

Sheet
E

22

of

50

Rev
0.1

B

C

19 QSB[0..7]
19 QSB#[0..7]

DQMB#[0..7]
QSB[0..7]
QSB#[0..7]

M2
N8
M3

19 B_BA0
19 B_BA1
19 B_BA2

CLKB0
CLKB0#
19 CKEB0
19 ODTB0
19 CSB0#
19 RASB0#
19 CASB0#
19 WEB0#

ODTB0

J7
K7
K9
K1
L2
J3
K3
L3

QSB3
QSB1

F3
C7

DQMB#3
DQMB#1

E7
D3

QSB#3
QSB#1

G3
B7

2

VRAM_RST#

19,22 VRAM_RST#

T2

1

L8

R870
243_0402_1%

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDB31
MDB26
MDB25
MDB29
MDB28
MDB30
MDB24
MDB27

D7
C3
C8
C2
A7
A2
B8
A3

MDB12
MDB11
MDB15
MDB9
MDB13
MDB8
MDB14
MDB10

VREFDB_Q1 M8
VREFCB_A1 H1
N3
MAB0
P7
MAB1
P3
MAB2
N2
MAB3
P8
MAB4
P2
MAB5
R8
MAB6
R2
MAB7
T8
MAB8
R3
MAB9
MAB10 L7
MAB11 R7
MAB12 N7
MAB13 T3
MAB14 T7
MAB15 M7

+1.5VSDGPU

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

VGA@

J1
L1
J9
L9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

B2
D9
G7
K2
K8
N1
N9
R1
R9

B_BA0
B_BA1
B_BA2

M2
N8
M3

CLKB0
CLKB0#
CKEB0

J7
K7
K9

+1.5VSDGPU
A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTB0
CSB0#
RASB0#
CASB0#
WEB0#

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

K1
L2
J3
K3
L3

QSB2
QSB0

F3
C7

DQMB#2
DQMB#0

E7
D3

QSB#2
QSB#0

G3
B7

VRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R871
243_0402_1%

J1
L1
J9
L9

VGA@

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@
+1.5VSDGPU

E3
F7
F2
F8
H3
H8
G2
H7

MDB23
MDB16
MDB22
MDB18
MDB21
MDB19
MDB20
MDB17

D7
C3
C8
C2
A7
A2
B8
A3

MDB2
MDB4
MDB0
MDB6
MDB3
MDB7
MDB1
MDB5

VREFCB_A3 M8
VREFDB_Q3 H1
N3
MAB0
P7
MAB1
P3
MAB2
N2
MAB3
P8
MAB4
P2
MAB5
R8
MAB6
R2
MAB7
T8
MAB8
R3
MAB9
MAB10 L7
MAB11 R7
MAB12 N7
MAB13 T3
MAB14 T7
MAB15 M7

+1.5VSDGPU

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

B_BA0
B_BA1
B_BA2

M2
N8
M3

CLKB1
CLKB1#

J7
K7
K9

19 CKEB1

+1.5VSDGPU
A1
A8
C1
C9
D2
E9
F1
H2
H9

19 ODTB1
19 CSB1#
19 RASB1#
19 CASB1#
19 WEB1#

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

ODTB1

K1
L2
J3
K3
L3

QSB4
QSB5

F3
C7

DQMB#4
DQMB#5

E7
D3

QSB#4
QSB#5

G3
B7

VRAM_RST#

T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R872
243_0402_1%

VGA@

J1
L1
J9
L9

U61

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@

E3
F7
F2
F8
H3
H8
G2
H7

MDB35
MDB37
MDB34
MDB39
MDB33
MDB38
MDB32
MDB36

D7
C3
C8
C2
A7
A2
B8
A3

MDB46
MDB43
MDB47
MDB41
MDB44
MDB42
MDB45
MDB40

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMB#6
DQMB#7

E7
D3

QSB#6
QSB#7

G3
B7

B1
B9
D1
D8
E2
E8
F9
G1
G9

R873
243_0402_1%

VGA@

1

DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VSDGPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

2

B1
B9
D1
D8
E2
E8
F9
G1
G9

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@

1

3

VGA@
2

2

2

1

VREFDB_Q3

1

1

1

2

R887
4.99K_0402_1%

C982
VGA@
VGA@
2

2

2

2

C981
VGA@
VGA@

1

2

2

1

2

2

2

2

2

VGA@
C1013
10U_0603_6.3V6M

2

1
VGA@ VGA@

2

2012/07/10

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

1

C1012
10U_0603_6.3V6M

2

VGA@

VGA@
1

C1005
1U_0402_6.3V6K

1

VGA@
1

C1004
1U_0402_6.3V6K

+1.5VSDGPU

VGA@
1

C1003
1U_0402_6.3V6K

2

VGA@
1

C1002
1U_0402_6.3V6K

2

C1011
10U_0603_6.3V6M

2

2

C1010
10U_0603_6.3V6M

2

2

2

C1008
10U_0603_6.3V6M

2

C1007
10U_0603_6.3V6M

1 VGA@

2

VGA@
1

C1001
1U_0402_6.3V6K

2

VGA@
1

C1000
1U_0402_6.3V6K

2

VGA@
1

C999
1U_0402_6.3V6K

2

VGA@
1

C998
1U_0402_6.3V6K

2

VGA@
1

C997
1U_0402_6.3V6K

2

1 VGA@ 1 VGA@ 1 VGA@
C1006
10U_0603_6.3V6M

C410
0.01U_0402_16V7K
VGA@

+1.5VSDGPU

+1.5VSDGPU

VGA@
1

C996
1U_0402_6.3V6K

2

VGA@
1

C995
1U_0402_6.3V6K

2

VGA@
1

C994
1U_0402_6.3V6K

2

VGA@
1

C993
1U_0402_6.3V6K

2

VGA@
1

C992
1U_0402_6.3V6K

2

VGA@
1

C991
1U_0402_6.3V6K

VGA@
1

1

2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

J1
L1
J9
L9

MDB59
MDB62
MDB58
MDB63
MDB56
MDB61
MDB57
MDB60

0.1U_0402_16V4Z

R886
4.99K_0402_1%

C1009
10U_0603_6.3V6M

R892
40.2_0402_1%
1
2
VGA@
R893
40.2_0402_1%
1
2
VGA@

C409
0.01U_0402_16V7K
VGA@

ODT/ODT0
CS/CS0
RAS
CAS
WE

T2

D7
C3
C8
C2
A7
A2
B8
A3

+1.5VSDGPU
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

L8

R879
4.99K_0402_1%

VGA@

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

19 CLKB1#

1

C985
1U_0402_6.3V6K

VGA@
1

C990
1U_0402_6.3V6K

VGA@
1

C989
1U_0402_6.3V6K

4

F3
C7

MDB55
MDB49
MDB52
MDB50
MDB53
MDB48
MDB54
MDB51

+1.5VSDGPU

+1.5VSDGPU

C988
1U_0402_6.3V6K

2

K1
L2
J3
K3
L3

QSB6
QSB7

+1.5VSDGPU

VGA@

ODTB1
CSB1#
RASB1#
CASB1#
WEB1#

VRAM_RST#

VREFCB_A3
C978
VGA@
VGA@

VGA@
1

1

19 CLKB1

2

0.1U_0402_16V4Z

1

J7
K7
K9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

+1.5VSDGPU

1

1
2
1

VREFDB_Q1

R883
4.99K_0402_1%

VGA@
1

C987
1U_0402_6.3V6K

19 CLKB0#

1

+1.5VSDGPU

40.2_0402_1%
2

CLKB1
CLKB1#
CKEB1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

1

R878
4.99K_0402_1%

VGA@

VREFCB_A1

R891

M2
N8
M3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

+1.5VSDGPU

R875
4.99K_0402_1%

R882
C977
4.99K_0402_1% VGA@
VGA@

R890 40.2_0402_1%
2
VGA@

B_BA0
B_BA1
B_BA2

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@

3

1

VREFCA
VREFDQ

N3
MAB0
P7
MAB1
P3
MAB2
N2
MAB3
P8
MAB4
P2
MAB5
R8
MAB6
R2
MAB7
T8
MAB8
R3
MAB9
MAB10 L7
MAB11 R7
MAB12 N7
MAB13 T3
MAB14 T7
MAB15 M7

+1.5VSDGPU

BA0
BA1
BA2

+1.5VSDGPU
R874
4.99K_0402_1% VGA@

19 CLKB0

VREFDB_Q3 M8
VREFCB_A3 H1

1

1

MDB[0..63]

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

1

19 MDB[0..63]
19 DQMB#[0..7]

MAB[0..15]

VREFCA
VREFDQ

1

19 MAB[0..15]

N3
MAB0
P7
MAB1
P3
MAB2
N2
MAB3
P8
MAB4
P2
MAB5
R8
MAB6
R2
MAB7
T8
MAB8
R3
MAB9
MAB10 L7
MAB11 R7
MAB12 N7
MAB13 T3
MAB14 T7
MAB15 M7

E

U60

2

VREFCB_A1 M8
VREFDB_Q1 H1

D

U59

2

U58

2

A

2013/07/10

Deciphered Date

Title

VRAM_DDR3 / Channel B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Tuesday, September 25, 2012

Sheet
E

23

of

50

Rev
0.1

A

B

C

D

E

Place closed to JLVDS1
+LCDVDD
+3VS

LCD POWER CIRCUIT

1
+3VS

+LCDVDD
U8

1

VOUT

5

GND

4
1

2
2

2

1

2

1

SS

1
@

1

VIN

EN

+INVPWR_B+

C368
0.1U_0402_16V4Z

2
C367 2
4.7U_0603_6.3V6K

3

L11
FBMA-L11-201209-221LMA30T_0805
2
1

APL3512ABI-TRG_SOT23-5
C164
2200P_0402_50V7K
@

8 PCH_ENVDD

1

2

@

0.1U_0402_16V4Z

1

2

C419
0.1U_0402_16V4Z

1
@C365
@
C365
68P_0402_50V8J
2

W=60mils

LCD/ LED PANEL Conn.

SM010014520 3000ma
220ohm@100mhz
DCR 0.04

W=60mils
+INVPWR_B+

W=60mils
+LCDVDD

+3VS

2

@

33 BKOFF#

R401
1K_0402_5%
@

IN A

BKOFF#

@
C549 1
@
C528 1
R280 1

INVTPWM
BKOFF#

2 220P_0402_50V7K
2 220P_0402_50V7K
2 10K_0402_5%

For Camera

2

2

INVTPWM
1

1
R362

+3VS
U20 @
M74VHC1GT125DF2G_SC70-5
2
1
5
Vcc
100K_0402_5% OE

GND OUT Y

1
R363
1
@
R404

8 PCH_INV_PWM
4 EDP_DISP_UTIL

4

INVTPWM

2
0_0402_5%
2
0_0402_5%

2
R393
@ 10K_0402_5%

USB20_P7

REF1 REF2

3

I/O2

I/O3

5
4

USB20_P7
USB20_N7

10 USB20_P7
10 USB20_N7
+3VS

D6
AZC099-04S_SOT23
@
1
6
I/O1
I/O4
1

3

EDP_HPD
EDP_AUXN_C
EDP_AUXP_C

+3VS
USB20_N7

2

EDP_TXP0_C
EDP_TXN0_C
EDP_TXP1_C
EDP_TXN1_C

eDP
3

4 EDP_TXN0
4 EDP_TXP0
4 EDP_TXN1
4 EDP_TXP1

C372 1
C371 1

2 0.1U_0402_16V7K EDP_TXN0_C
2 0.1U_0402_16V7K EDP_TXP0_C

C374 1
C373 1

2 0.1U_0402_16V7K EDP_TXN1_C
2 0.1U_0402_16V7K EDP_TXP1_C

1

B+

W=60mils

C364
1000P_0402_50V7K

C140
1U_0402_6.3V6K

R405
0_0402_5%
1
2
@

W=60mils

C375

JLVDS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

G1
G2
G3
G4
G5
G6

41
42
43
44
45
46

2

3

ACES_50203-04001-001
CONN@

SP010014B00
+3VS
C369 1
C370 1

4 EDP_AUXN
4 EDP_AUXP

2 0.1U_0402_16V7K EDP_AUXN_C R613 2
2 0.1U_0402_16V7K EDP_AUXP_C R614 2

1 100K_0402_1%
1 100K_0402_1%

@
@

+3VS

2

2

3

2

EDP_HPD

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

R364
100K_0402_5%

2012/07/10

Deciphered Date

2013/07/10

Title

eDP Connector

2

1
R406
0_0402_5%

4

D

S

8 CPU_EDP_HPD

G

4

Q13
L2N7002LT1G_SOT23-3
@
1

1

1

+5VS

R383
10K_0402_5%
@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Tuesday, September 25, 2012

Sheet
E

24

of

50

R367
0_0603_5%
1
2
@

W=40mils
+HDMI_5V_OUT
F1

1

+HDMI_5V

1

2

3
1.1A_6V_SMD1812P110TF
1

D7
RB491D-YS_SOT23-3

1

2

C378
0.1U_0402_16V4Z

D

4
4
4
4

CPU_DP2_N1
CPU_DP2_P1
CPU_DP2_N0
CPU_DP2_P0

C381
C382
C379
C380

2
2
2
2

1
1
1
1

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

HDMI_TX1HDMI_TX1+
HDMI_TX2HDMI_TX2+

4
3
2
1

4
4
4
4

CPU_DP2_N2
CPU_DP2_P2
CPU_DP2_N3
CPU_DP2_P3

C383
C384
C385
C386

2
2
2
2

1
1
1
1

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

HDMI_TX0HDMI_TX0+
HDMI_CLKHDMI_CLK+

4
3
2
1

RP17
680_8P4R_5%
5
6
7
8

5
+3VS
Q14B
DMN66D0LDW-7_SOT363-6

1
L13
WCM-2012-900T_0805
@4

R370 1

2

0_0402_5%

HDMI_R_D0-

2

1
2
+HDMI_5V_OUT
+3VS

3

2
1
D8
RB751V40_SC76-2

2

4

3

HDMI_TX0+

R371 1

2

HDMI_TX1-

R372 1

2

1

2

4

3

2
3
0_0402_5%

HDMI_R_D0+

0_0402_5%

HDMI_R_D1-

2
3

HDMI_TX1+

R373

1

2

0_0402_5%

HDMI_R_D1+

HDMI_TX2-

R374

1

2

0_0402_5%

HDMI_R_D2-

2

1
C387
220P_0402_50V7K
@

L16
WCM-2012-900T_0805
@4

1

2

4

3

R375 1

HDMI_TX2+

1
2
3
4

1

1

HDMI_HPD

R121
100K_0402_5%

D19
RB751V40_SC76-2
2
1

3

HDMI_TX0-

1

2

3

HDMI_R_CK+

L15
WCM-2012-900T_0805
@4

6

4

0_0402_5%

1
2

1

2

HDMI_R_CK-

2

2

+3VS

8 CPU_HDMI_HPD

1

0_0402_5%

R369 1

1

Q14A
DMN66D0LDW-7_SOT363-6

2

HDMI_CLK+

1
L14
WCM-2012-900T_0805
@4

+3VS

R376
1M_0402_5%

R368 1

HDMI_CLK-

5
6
7
8
RP18
680_8P4R_5%

E

SM070001310 400ma 90ohm@100mhz DCR 0.3

HDMI_GND

2

C

3

+5VS

B

4

A

RP15
2.2K_0804_8P4R_5%
8
HDMI_SCLK
7
HDMI_SDATA
6 DDI2_CTRL_CK
5 DDI2_CTRL_DATA

2

2
2

3
0_0402_5%

HDMI_R_D2+

HDMI connector

3

JHDMI1
HDMI_HPD

31 HDMI_HPD
+HDMI_5V_OUT

HDMI_SDATA
HDMI_SCLK

2
1

6

4

HDMI_R_CK-

Q15A
DMN66D0LDW-7_SOT363-6

HDMI_R_CK+
HDMI_R_D0-

HDMI_SCLK

3
HDMI_SDATA
Q15B
DMN66D0LDW-7_SOT363-6

HDMI_R_D0+
HDMI_R_D1-

D2
@

YSLC05CH_SOT23-3

5

1

8 DDI2_CTRL_CK
8 DDI2_CTRL_DATA

2

3

+3VS

+3VS

HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+

Place closed to JHDMI1

Reserved for ESD

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKCK_shield
CK+
D0D0_shield
D0+
D1D1_shield
D1+
GND
D2GND
D2_shield GND
D2+
GND

20
21
22
23

ACON_HMR2U-AK120C
CONN@

ZZZ

DC232002700

4

Issued Date

RO0000003HM
45@

Compal Electronics, Inc.

Compal Secret Data

Security Classification

HDMI_ROYALTY
ROYALTY HDMI W/LOGO+HDCP

2012/07/10

Deciphered Date

4

2013/07/10

Title

HDMI Conn

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Tuesday, September 25, 2012

Sheet
E

25

of

50

Rev
0.1

2

2

+1.8VS_6511

2
2

1 0.1U_0402_16V7K CPU_DP1_C_P0
1 0.1U_0402_16V7K CPU_DP1_C_N0

30
31

C70
C71

2
2

1 0.1U_0402_16V7K CPU_DP1_C_P1
1 0.1U_0402_16V7K CPU_DP1_C_N1

33
34

C72
0.1U_0402_16V7K
1
DDI1_AUX_C_DP
1
DDI1_AUX_C_DN
C73
0.1U_0402_16V7K
DDI1_AUX_DP_R
DDI1_AUX_DN_R

2
2

1 100K_0402_5%
1 1M_0402_5%

@

1

2

C581
0.1U_0402_16V4Z

@

2

C580
0.1U_0402_16V4Z

@

@

C474
0.1U_0402_16V4Z

+CRT_VCC

2

2

R230
4.7K_0402_5%

MCUVDD

RX1P
RX1N

MCURSTN

VGADDCCLK
VGADDCSDA

DCAUXP
DCAUXN

VSYNC
HSYNC

1

C477
2 0.1U_0402_16V4Z

1

C496 1
2 0.1U_0402_16V4Z
1
2
1
2
R133
4.7K_0402_5%
C614
MCURSTN
0.1U_0402_16V4Z

50
53
32

@

19
20

1
1
1
1

T97
ISPSCL_R
ISPSDA_R

27
25

R413
R412
R411
R410

4

22_0402_5%
22_0402_5%
22_0402_5%
22_0402_5%

1 22_0402_5%
1 22_0402_5%

ISPSCL 27
ISPSDA 27

1
2

CRT_CLK_1
CRT_DATA_1

+1.8VS_RXVDD

28
37
36

DVDD18
DVDD18
DVSS18

IORN
IORP
VGADETECT

+1.8VS_RXVCC

RSET

39

6511_PWR_EN

2

37.4_0402_1%

1

2

37.4_0402_1%

7
6

R147 1

CRT_B

1

CRT_B 27

CRT_G

2

CRT_G 27

37.4_0402_1%
CRT_R

18

CRT_R 27

VGADETECT 27

3

R196 1

2 100_0402_1%

42

INT#
COMP

48
47

PCSDA
PCSCL
XTALIN
XTALOUT

43

SYSRSTN

IT6511FN_QFN56_7X7

5

+1.8VS_DAC

4

1

41
40

2 C500
0.1U_0402_16V4Z

XTALIN_6511
XTALOUT_6511

B

+3VS

2

2 10K_0402_5%
2 10K_0402_5%

1

R76

GND

2 10K_0402_5%

R53

10
9

@
R584
100K_0402_5%

R419
1M_0402_5%

57

R193 1
R194 1

@

13
12

C411
0.1U_0402_16V7K

ASPVCC
VDDA

R134 1

Q25
DMG2301U-7_SOT23-3

2

1

IOGN
IOGP

R396
1K_0402_5%
2
1

+1.8VS_DAC

1

IOBN
IOBP

+3VS_6511

1

1

8
11
14

2

IT6511FN

PVCC
PVCC

3

45

2

26
38

VDDC
VDDC
VDDC

R80
0_0603_5%
1
2
@

+3VS

CRT_CLK_1 27
CRT_DATA_1 27

VSYNC 27
HSYNC 27

1

AVCC
AVCC

CRT_CLK 27

Q27B
DMN66D0LDW-7_SOT363-6

2

+1.8VS_RXVCC

35
29

CRT_DATA 27

C

2
2

R397
R398

2
2
2
2

@
@

CRT_CLK_1

6
Q27A
DMN66D0LDW-7_SOT363-6
3

5

51

R197
75_0402_1%
R199
75_0402_1%
R201
75_0402_1%

+1.8VS_RXVCC

R123
2.2K_0402_5%

2

1

+3VS

R127
2.2K_0402_5%
2
1

+3VS

2
17
15
49
52
IVDD
IVDD
IVDD
IVDD

RX0P
RX0N

RXAUXP
RXAUXN

22
21

2

CRT_DATA_1

MCUVDDH

ISPSCL
ISPSDA

24
23

2

1

6511_PWR_EN#

+3VS

1

+3VS

URDBG

1 1M_0402_5%
1 100K_0402_5%

1

1

2

+1.8VS_RXVDD

OSCOUT

B

2

D

R234
4.7K_0402_5%

OVDD
OVDD
OVDD

HPD

DDCSCL
DDCSDA

44

C68
C69

2 0_0402_5%
2 0_0402_5%
@
@

1

G

R420 2
R51 2

2

D

+3VS

1

S

R400 1
R415 1

8 DDI1_AUX_DP
8 DDI1_AUX_DN

2

XTALOUT_6511

XTALIN_6511

2

GND

IN

2
G
Q52
L2N7002LT1G_SOT23-3
@

1
C74

2

D

S

6511_PWR_EN

44 6511_PWR_EN

1
18P_0402_50V8J

1
C65

18P_0402_50V8J

2

6511_PWR_EN#

37 6511_PWR_EN#

X4
27MHZ_10PF_X3G027000BA1H-U
Crystal
3
4
OUT
GND

1

@
@

1

1

C

R50 2
R421 2

2

3

+3VS

1

2

4 CPU_DP1_P1
4 CPU_DP1_N1

2

C498
0.1U_0402_16V4Z

@
+3VS_6511

1

2

U42
DP_HPD

4 CPU_DP1_P0
4 CPU_DP1_N0

1

1
2
L48
BLM18PG600SN1_2P
Rated current 500mA, DC 0.1ohm

+1.8VS_RXVCC

2
L47
BLM18PG600SN1_2P
Rated current 500mA, DC 0.1ohm

16
46
54

R418
100K_0402_5%

R408
22_0402_5%

1
1
Q24
L2N7002LT1G_SOT23-3
@

R240
4.7K_0402_5%
1
@
2
1
2
@
R241
4.7K_0402_5%

2
2

D

+3VS

1

S

DP_HPD

55
56

G

2

R407 @ @
22_0402_5%

1

2

+1.8VS_DAC

1

ISPSCL_R
ISPSDA_R

3

1

C497 @
0.1U_0402_16V4Z

2 0_0402_5%
+5VS

8 CPU_DP_HPD

2

1

2

C519
4.7U_0603_6.3V6K

R399 1

1

C457
0.1U_0402_16V4Z

2

D

@

1

C456
0.1U_0402_16V4Z

@

C455
10U_0603_6.3V6M

1

C637 @
0.1U_0402_16V4Z

2
0_0603_5%

L30

C473 @
0.1U_0402_16V4Z

1

+3VS_6511

1

+1.8VS_6511

C472
0.1U_0402_16V4Z

+1.8VS_RXVDD

C579
0.1U_0402_16V4Z

3

+1.8VS_6511

C75
1U_0402_6.3V6K

4

C476
4.7U_0603_6.3V6K

5

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

ITE IT6511FN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Tuesday, September 25, 2012

Sheet
1

26

of

50

Rev
0.1

A

B

C

D

+5VS

E

W=40mils

1
2
3

W=40mils

+R_CRT_VCC

D17

I/O1

I/O4

REF1 REF2
I/O2

I/O3

6

+CRT_VCC

VGADETECT

2
5

F2

1

+CRT_VCC

1

2

3

4

1.1A_6V_SMD1812P110TF 1
D31
@ C450
0.1U_0402_16V4Z
RB491D-YS_SOT23-3
2

AZC099-04S_SOT23
@
1

1

CRB1.0 use 47ohm@100Mhz Bead

26 CRT_R
26 CRT_G
26 CRT_B

JCRT1

CRT_B_2

2

1

2

1

2

C616
10P_0402_50V8J

1

1

2
1

R175
2 33_0603_5%

1

R180
2 33_0603_5%

2

+CRT_VCC
U24

1
R439
0_0402_5%
2
1

26 HSYNC

2

CRT_HSYNC

3

OE

Vcc

5

0.1U_0402_16V4Z

2

@
1 C447

4

CRT_HSYNC_1

C606
100P_0402_50V8J
@

1

@

2

16
17

DC060006E00

2

VGADETECT 26
CRT_DATA 26

CRT_VSYNC_2
1

2

G
G

C-H_13-12201560CP
CONN@

CRT_HSYNC_2

@
C448
10P_0402_50V8J

IN A
GND OUT Y

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

CRT_G_2

C618
10P_0402_50V8J

2

CRT_R_2

C647
10P_0402_50V8J

2

1

C611
10P_0402_50V8J

1

C615
10P_0402_50V8J

2

C648
10P_0402_50V8J

1

CRT Connector

26 ISPSDA
26 ISPSCL

L42
BLM18BA470SN1D_2P
1
2
L45
BLM18BA470SN1D_2P
1
2
L46
BLM18BA470SN1D_2P
1
2

C449
10P_0402_50V8J

@

1

CRT_CLK 26

C646 2
68P_0402_50V8J 1
@

2

M74VHC1GT125DF2G_SC70-5

C607
68P_0402_50V8J

+CRT_VCC
U23
10K_0402_5% 1

2 R239

2
R441
0_0402_5%

26 VSYNC

1

1
2

CRT_VSYNC

3

OE

Vcc

5

IN A
GND OUT Y

4

CRT_VSYNC_1
D18
CRT_HSYNC_2

1

I/O1

M74VHC1GT125DF2G_SC70-5

2

3

CRT_DATA

I/O4

REF1 REF2

3

I/O2

I/O3

6
5
4

CRT_VSYNC_2
+CRT_VCC

3

CRT_CLK

AZC099-04S_SOT23
@

@
2
2
@

C451
0.1U_0402_16V4Z
C452
0.1U_0402_16V4Z

VCC_SYNC
VCC_VIDEO
VCC_DDC

U10

+CRT_VCC
+3VS

1
2
7

1
1

CRT_CLK_1
CRT_DATA_1

10
11

1
2
C454
0.1U_0402_16V4Z
@

4

For contact

8

discharge ESD +/-8kV

SYNC_IN1
SYNC_IN2
DDC_IN1
DDC_IN2

VIDEO_1
VIDEO_2
VIDEO_3

SYNC_OUT1
SYNC_OUT2
DDC_OUT1
DDC_OUT2

BYP
GND

13
15

6

26 CRT_CLK_1
26 CRT_DATA_1

HSYNC
VSYNC

3
4
5

CRT_R_2
CRT_G_2
CRT_B_2

14
16

CRT_HSYNC_1
CRT_VSYNC_1

9
12

CRT_CLK
CRT_DATA

4

DDC_CLK/DAT reserved PU Resistor

CM2009-00QR_QSOP16
@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

CRT Connector
Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
E

27

of

50

Rev
0.1

5

4

3

2

1

+1.2V_LAN
+VDDO_CR

AVDDH
AVDDH

+3V_LAN

D

VDDO
VDDO
VDDO

TRD2_N
TRD2_P
39
45
51

R02 modify

for ESD

+LAN_GPHYPLLVDDL

36

+LAN_PCIEPLLVDD

32

AVDDL
AVDDL
AVDDL

TRD1_N
TRD1_P
TRD0_N
TRD0_P

GPHY_PLLVDDL

2 0.1U_0402_16V4Z PLT_RST_BUF#

SO_LINKLED#

1
1

0.1U_0402_16V7K
0.1U_0402_16V7K

33 EC_PME#
+3V_LAN

C

R764 1

2 4.7K_0402_5%
2 0_0402_5%

@

PCIE_TXD_P
PCIE_TXD_N
PCIE_RXD_P
PCIE_RXD_N

TRAFFICLED#_SERIALDI
GPIO1_LR_OUT
GPIO_0

2 0_0402_5%

R766 1

30,8 PLT_RST_BUF#
7 CLK_PCIE_LAN
7 CLK_PCIE_LAN#

PCIE_PRX_C_DTX_P3 28
PCIE_PRX_C_DTX_N3 27
33
34

R763 1

R765 1

8 PCH_PCIE_WAKE#

2 C788
2 C791

SI_EEDATA
CS#_EECLK

3

LAN_PME#

2 0_0402_5%

PREST#
PCIE_REFCLK_P
PCIE_REFCLK_N
SD_DETECT/XD_WE#

29
29
29
29

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3

5
6
7
8

CR_DATA0_R
CR_DATA1_R
CR_DATA2_R
CR_DATA3_R

33_8P4R_5%

SR_DISABLE/XD_DETECT#

25
24
23
22
52
53
54
55

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7

MS_INS#/XD_CE#
GPIO2_MEDIA_SENSE/XD_RE#
CR_WP#/XD_WP#
CR_LED_CR_BUS_PWR/XD_ALE
CR_CLK/XD_RY_BY#

+3VS
R776 1

2 1K_0402_5% 58

R777 1

2 4.7K_0402_5% 6

LAN_MIDI3LAN_MIDI3+

47
46

LAN_MIDI2LAN_MIDI2+

43
44

LAN_MIDI1LAN_MIDI1+

41
40

LAN_MIDI0LAN_MIDI0+

LAN_MIDI3- 29
LAN_MIDI3+ 29

1

2

CR_CMD_XD_CLE

+LAN_XTALVDDH
C785

LAN_MIDI0- 29
LAN_MIDI0+ 29

20mil

65
66

10

TEST2
SR_LX
LOW_PWR

19
18

SR_VFB

15mil38

2 LAN_RDAC
1.24K_0402_1%

1

RB751V40_SC76-2
2
1

R760 2

1

8

67
+VDDO_CR_R

R761 1

2 0_0603_5%

5

5IN1_LED_R#

R762 2

1

64
63

SPROM_DOUT
SPROM_CLK

1

CR_XD_WE#_SD_DETECT_R

R767 2

1

0_0402_5%

CR_XD_WE#_SD_DETECT

0_0402_5%

R896
0_0402_5%

@

CR_WP#_XD_WP#_R

R772 2

1

0_0402_5%

CR_WP#_XD_WP#

CR_PWR_EN_R

R773 2

1

0_0402_5%

CR_PWR_EN

21

CR_CLK_XD_RY_BY#_R

R774 1

2 10_0402_5%

26

CR_CMD_XD_CLE_R

1

2 22_0402_5%

16

R775

40mil

L59
2
+1.2V_LAN_OUT 1
4.7UH_PG031B-4R7MS_1.1A_20%

13

1
2
BLM18AG601SN1D_2P

2

2

0.1U_0402_16V4Z

CR_XD_WE#_SD_DETECT 29,31

CR_WP#_XD_WP# 29

CLK_REQ#

SR_VDDP
SR_VDD

CR_CMD_XD_CLE 29

1

1

+1.2V_LAN
1

2

2

EMI Request...2010/07/27

C794
10U_0603_6.3V6M

B

1

2

2

SM010005500 500ma 600ohm@100mhz DCR 0.38

20mil
+3V_LAN

1 0.1U_0402_16V4Z
C795

C792
0.01U_0402_16V7K
@

40mil
1

40mil

15
14

For EMI request

CR_PWR_EN 29
CR_CLK_XD_RY_BY# 29

R02 Modify

L60
1
2
BLM18AG601SN1D_2P

+LAN_PCIEPLLVDD

4.7U_0603_6.3V6K
C796

C797
0.1U_0402_16V4Z

1

1

2

2

+1.2V_LAN

C798
4.7U_0603_6.3V6K

PLACE NEXT P14
R781
10K_0402_5%

20mil

+3V_LAN

1
2
R783
1K_0402_5%

2
R782
1K_0402_5%
1
2

3 LAN_XTALO
1

SPROM_CLK
(EECLK)

SPROM_DOUT
(EEDATA)

On chip

1

0

AT24C02

1

1

C800
15P_0402_50V8J

C803 1
@

L61
1
2
BLM18AG601SN1D_2P

2 0.1U_0402_16V4Z
C801
0.1U_0402_16V4Z

1

1

2

2

1

1

2

2

+1.2V_LAN

C802
4.7U_0603_6.3V6K

U49 @
8
7
6
5

VCC
WP
SCL
SDA

A0
A1
A2
GND

1
2
3
4

20mil

L62
1
2
BLM18AG601SN1D_2P

+LAN_AVDDL

AT24C04BN-SH-T_SO8
SA00004QG00

C804
0.1U_0402_16V4Z

@

+1.2V_LAN

C805
4.7U_0603_6.3V6K

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

2
R785
1K_0402_5%

SPROM_CLK
SPROM_DOUT

R779
200_0402_1%

2

C790

1

5IN1_LED# 34

57

LAN_XTALI
LAN_XTALO_R

4

1

1

2
C799
15P_0402_50V8J
2

GND

1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z

+VDDO_CR

60

1

3
GND

L57

9

R784
1K_0402_5%

1
1

+3V_LAN

59

2
1
1

D

C

@

A

2

L58

+LAN_GPHYPLLVDDL

Y6
25MHZ 10PF X3G025000DA1H-X

2

68

BCM57786XA1KMLG_QFN68_8X8
2

1

@

2

C789
@
0.1U_0402_16V4Z

LAN_ACTIVITY# 29
+VDDO_CR

0_0402_5%

C793
0.1U_0402_16V4Z

RDAC

12

+3V_LAN

1

+LAN_AVDDH

XTALO
XTALI
GND PLANE

7 LAN_CLKREQ#

D23

1

L56
1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z

2

20mil

2

69

@
2

1

LAN_LINK# 29

2

Reserved for leakage current
1
R780

@

20mil

LAN_MIDI1- 29
LAN_MIDI1+ 29

TEST1

4.7K_0402_5%

LAN_XTALO_R
LAN_XTALI

2

LAN_PWR_EN# 33

VMAIN_PRSNT

4
B

2

60mil

LAN_MIDI2- 29
LAN_MIDI2+ 29

+3V_LAN

R778

2

@

1

WAKE#

11
31
30

RP22
4
3
2
1

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3

49
50

2

@

1

C787

SCLK_SPD1000LED#

PCIE_PRX_DTX_P3
PCIE_PRX_DTX_N3
PCIE_PTX_C_DRX_P3
PCIE_PTX_C_DRX_N3

1

@

1

+LAN_BIASVDDH

PCIE_PLLVDDL

SPD100LED#_SERIALDO
10
10
10
10

3

+LAN_AVDDH

+3V_LAN
1

PCIE_PLLVDDL

29
C786 1

48
42

Q6
DMG2301U-7_SOT23-3
TRD3_N
TRD3_P

+LAN_AVDDL

+LAN_XTALVDDH

G

7
56
62

17

C784
0.1U_0402_16V4Z

XTALVDDH

C783
4.7U_0603_6.3V6K

VDDC
VDDC

+3V_LAN

2

@

C782
0.1U_0402_16V4Z

2

35
61

1

C781
0.1U_0402_16V4Z

2

R759
0_0805_5%

+3VALW

+LAN_BIASVDDH

C780
0.1U_0402_16V4Z

2

1

+1.2V_LAN

37

VDDO_CR

C779
4.7U_0603_6.3V6K

2

@

BIASVDDH

20

1

2

2

@

1

C777
4.7U_0603_6.3V6K

@

1

C778
0.1U_0402_16V4Z

1

C776
0.1U_0402_16V4Z

@

C775
0.1U_0402_16V4Z

2

C774
0.1U_0402_16V4Z

C773
0.1U_0402_16V4Z

2

@

1

D

C772
0.1U_0402_16V4Z

2

1

S

C771
4.7U_0603_6.3V6K

U48
1

2013/07/10

Deciphered Date

Title

Broadcom BCM57786X

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Sheet

Tuesday, September 25, 2012
1

28

of

50

Rev
0.1

5

4

3

2

1

10
11
12

2

1

2

1

2

MCT3
MX3+
MX3-

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

RJ45_MIDI2RJ45_MIDI2+

18
17
16

RJ45_MIDI1+
RJ45_MIDI1-

15
14
13

RJ45_MIDI0RJ45_MIDI0+

R787
1K_0402_5%
D

C806 1
@
C807 1
@

JRJ45

GST5009-E
SP050006B10

1

2

1

TCT3
TD3+
TD3-

21
20
19

R786
1K_0402_5%

LAN Connector

2

28 LAN_MIDI028 LAN_MIDI0+

LAN_MIDI0LAN_MIDI0+

MCT2
MX2+
MX2-

RJ45_MIDI3+
RJ45_MIDI3-

2

7
8
9

TCT2
TD2+
TD2-

24
23
22

2

2

CARD READER_2in1 SP07000TF00

RJ45_MIDI0+

R790
75_0402_1%
1
R791
75_0402_1%

LAN_MIDI1+
LAN_MIDI1-

MCT1
MX1+
MX1-

1

RJ45_MIDI0-

2

RJ45_MIDI1+

3

RJ45_MIDI2+

4

RJ45_MIDI2-

5

RJ45_MIDI1-

6

RJ45_MIDI3+

7

RJ45_MIDI3-

8

PR1+
LED_YELLOW_A1
PR1LED_YELLOW_A2

9

LED_GREEN_B1
PR3LED_GREEN_B2

C808 1
@

11

LAN_LINK#

12

C809 1
@

PR2PR4+

GND
GND

2 220P_0402_50V7K

LAN_ACTIVITY#

10

PR2+
PR3+

2 220P_0402_50V7K

LAN_ACTIVITY# 28

2 68P_0402_50V8J

LAN_LINK# 28

2 68P_0402_50V8J

13
14

40mil

PR4SANTA_130451-F
CONN@

DC234005300

2

28 LAN_MIDI1+
28 LAN_MIDI1-

TCT1
TD1+
TD1-

1
R788
75_0402_1%
2
1
R789
75_0402_1%
1

4
5
6

C813
0.1U_0402_16V4Z

28 LAN_MIDI228 LAN_MIDI2+

LAN_MIDI2LAN_MIDI2+

C812
0.1U_0402_16V4Z

LAN_MIDI3+
LAN_MIDI3-

C811
0.1U_0402_16V4Z

28 LAN_MIDI3+
28 LAN_MIDI3-

C810
0.1U_0402_16V4Z

D

1

T1

1
2
3

1

+3V_LAN

RJ45_GND
LAN_ACTIVITY#
LAN_LINK#

2

BOTHHAND: S X'FORM_ GST5009-E LF LAN, SP050006B10
TIMAG:S X'FORM_ IH-160 LAN , SP050006F00

C

3

Place close to TCT pin

C

@ JP1
B88069X9231T203_4P5X3P2-2
2
1

D38
L30ESDL5V0C3-2
@

C814 1

LANGND

@

JREAD1

3

WP SW
CD SW
GND SW
GND SW

R793
10K_0402_5%

2

22_0402_5%

@
1

1

C26

3

@ R26

Q9
DMG2301U-7_SOT23-3

Q23
L2N7002LT1G_SOT23-3 D
2
28 CR_PW R_EN
G
S

SP07000TF00

1

1

2
6.8P_0402_50V8C

A

@

2012/07/10

Issued Date

Deciphered Date

40mil

3

1

2

@

1

2

@

1

2

2

A

Compal Electronics, Inc.
2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

1

Compal Secret Data

Security Classification

5

2
@
R792
0_0805_5%

2

T-SOL_156-1000302601_NR
CONN@

CR_CLK

1

G

10
11
12
13

+XDPW R_SDPW R_MSPW R
+3VALW
D

CR_W P#_XD_W P#
CR_XD_W E#_SD_DETECT

+VDDO_CR

DAT0
DAT1
DAT2
CD/DAT3

S

28 CR_W P#_XD_W P#
28,31 CR_XD_W E#_SD_DETECT

8
9
1
2

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3

C819
0.1U_0402_16V4Z

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3

B

C818
0.1U_0402_16V4Z

28
28
28
28

CMD
VSS
VDD
CLK
VSS

C817
4.7U_0603_6.3V6K

28 CR_CLK_XD_RY_BY#

CR_CLK

2

1
R897 2
0_0402_5%

3
4
5
6
7

C822
0.1U_0402_16V4Z

CR_CMD_XD_CLE

1

28 CR_CMD_XD_CLE

B

B88069X9231T203_4P5X3P2-2

1
JP2

3

2
1

+XDPW R_SDPW R_MSPW R

2

2

J15
JUMP_43X118
@

D39
L30ESDL5V0C3-2

1
2

40mil

Card Reader Connector

2

10P_0402_50V8J

1

1

RJ45_GND

2

Title

LAN Magnetic & RJ45
Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
1

29

of

50

Rev
0.1

A

B

C

D

E

For Wireless LAN
60mil

+3VS

+1.5VS
+3VS_W LAN

1

@ J3

1

2
1

JUMP_43X118
@ J4

1
1

@

1

@

1

C459

+1.5VS_W LAN

@

C460
0.1U_0402_16V4Z
4.7U_0603_6.3V6K 0.1U_0402_16V4Z
2
2
2

+3VALW

C458

J13
JUMP_43X39
2
1
2

1

2

C461

@

4.7U_0603_6.3V6K

1

C462
@
0.1U_0402_16V4Z

2

1

C463
0.1U_0402_16V4Z

2

2

JUMP_43X118

1

+3VS_W LAN

Mini Card Power Rating
+3VS_W LAN

+1.5VS_W LAN
R429 1

2 4.7K_0402_5%
JMINI1

W LAN_PME#
R423
0_0402_5%
1
2

33 WLAN_PME#
+3VS_W LAN

7,8 MINI1_CLKREQ#

+3VALW
U9

5
C165
1U_0402_6.3V6K

@

R414
0_0402_5%
1
2
@

4

1
@

1

2
2

VOUT

1

W=60mils

7 CLK_PCIE_MINI1#
7 CLK_PCIE_MINI1

VIN
GND

2

SS
EN

10 PCIE_PRX_DTX_N4
10 PCIE_PRX_DTX_P4

3

C166
APL3512ABI-TRG_SOT23-5
2200P_0402_50V7K

10 PCIE_PTX_C_DRX_N4
10 PCIE_PTX_C_DRX_P4

33 W LAN_ON
+3VS_W LAN
R435
0_0402_5%
1
2
1
2

2

1

1

33 E51TXD_P80DATA
33 E51RXD_P80CLK

R436
0_0402_5%
R438
1K_0402_5%

53

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GNDGND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

W L_OFF#
PLT_RST_BUF#

W L_OFF# 33
PLT_RST_BUF# 28,8

MINI1_SMBCLK
R432 1
MINI1_SMBDATA R434 1

@
@

2 0_0402_5%
2 0_0402_5%

PCH_SMBCLK 4,7
PCH_SMBDATA 4,7

USB20_N4 10
USB20_P4 10
R443 1

2 100K_0402_5%

+3VS_W LAN
MINI1_LED# 33

2

54

BELLW _80053-1021
CONN@

1

2

DC040009P00
D

3

2

R437
100K_0402_5%

33 BT_ON#

E51TXD_P80DATA_R
E51RXD_P80CLK_R

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

S

2
G

Q20
L2N7002LT1G_SOT23-3

3

3

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

MINI CARD (WLAN)
Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
E

30

of

50

Rev
0.1

A

B

C

D

E

SATA HDD1 Conn.
JHDD1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0

2 0_0805_5%

+3VS_HDD

+5VS_HDD

+5VS

2

2

1
@
2

C398
1000P_0402_50V7K

2

1

C397
0.1U_0402_16V4Z

1
@

C161
1U_0402_10V6K

C420
10U_0603_6.3V6M

2

C390
0.1U_0402_16V4Z

1

1

100mils

6 SATA_PRX_DTX_N2
6 SATA_PRX_DTX_P2

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

+5VS

C401 1
C402 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2

C403 1
C405 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2

R593
0_0805_5%
1
2

80mils

GND
GND

1

2

1
2
3
4
5
6
7
8
9
10
11
12
13

+5VS_ODD
1
@

2

C408
1000P_0402_50V7K

+3VS

1

R49

+5VS

@

2

6 SATA_PTX_DRX_P2
6 SATA_PTX_DRX_N2

C407
0.1U_0402_16V4Z

R307 1

8,9 DEVSLP0

R308 1
0_0402_5%
2 0_0402_5%

JODD1

C404
10U_0603_6.3V6M

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

SATA ODD Conn.

GND
A+
AGND
BB+
GND

1

C391 1
C394 1

6 SATA_PRX_DTX_N0
6 SATA_PRX_DTX_P0

1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

2

C392 1
C393 1

6 SATA_PTX_DRX_P0
6 SATA_PTX_DRX_N0

1
2
3
4
5
6
7

GND
A+
AGND
BB+
GND
DP
+5V
+5V
MD
GND
GND

1

GND
GND

14
15

TYCO_1759838-1
CONN@

24
23

SP01000WZ00

SANTA_192901-1
CONN@

DC010005I00

2

2

Debug Board
JDB1

28,29 CR_XD_W E#_SD_DETECT

33 EC UART_TXD
25 HDMI_HPD
4,8 XDP_DBRESET#
33,34 KSI0
33,34 KSO2

51

+EC_SPI

R587
10K_0402_5%
@
R596
0_0402_5%
1
2

ON/OFFBTN# 32,34

R595
10K_0402_5%
@

R569 1 932@
1K_0402_1%

REC_MODE_L 33
EC UART_RXD 33

2

SPI_W P1#_R 33,6,7
S

2
G

+3VALW _EC

3

2

EC_SPICS#/FSEL#_R 33
EC_SI_SPI_SO_R1 33
EC_RST# 33,34

1

+3VS

Kill SW

1

G2

PCH_SPI_CLK_1_R 7
PCH_SPI_MOSI_1_R 7
+BIOS_SPI

2

G1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

3

+EC_SPI

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

2 1

3

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

D

Q34
AO3419L_SOT23-3
@
R597
0_0402_5%
@

SPI_W P1#_R 33,6,7
LID_SW # 32,33
KSI2 33,34
KSO3 33,34
KSO4 33,34

1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

7 PCH_SPI_CS0#_1_R
7 PCH_SPI_MISO_1_R
7 SPI_HOLD1#_R
33 EC_SPICLK
33 EC_SO_SPI_SI_R1

R562
0_0402_5%
1
2

+3VALW

52

JP5

1
2

1
2

CONN@
3
4

G1
G2

ACES_87212-02G0

E&T_1001K-F50C-05R
CONN@

Ctrl (L, 58)
Ctrl (R, 64)
D (33)
F3 (114)
Enter (43)
Space (61)

4

C03,
C01,
C01,
C03,
C01,
C03,

R04
R04
R03
R03
R05
R05

(KSI2,
(KSI0,
(KSI0,
(KSI2,
(KSI0,
(KSI2,

KSO3)
KSO3)
KSO2)
KSO2)
KSO4)
KSO4)

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

HDD/ODD/Debug Board
Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
E

31

of

50

Rev
0.1

A

10 PCH_USB3_TX0_P
10 PCH_USB3_TX0_N

B

2
C484

1 PCH_USB3_TX0_P_C
0.1U_0402_16V7K

2
C482

R453 1
R455 1
L24
2

1 PCH_USB3_TX0_N_C
0.1U_0402_16V7K

@
@

C

2 0_0402_5%
2 0_0402_5%
1

3

U3TXDP0

4

D

E

+5VALW

For ESD request
U3RXDN0

D15
1 1

10 9

U3RXDN0

U3RXDP0

2 2

9 8

U3RXDP0

4 4

7 7

U3TXDN0

U3TXDP0

5 5

6 6

U3TXDP0

U25

C483
0.01U_0402_16V7K
1
2
@

U3TXDN0
U3TXDN0

+USB3_VCCA

1
2
3
4

33 USB_CHARGE_2A#

OCE2012120YZF_4P

1

PCH_USB3_RX0_P

10 PCH_USB3_RX0_P

R456 1
R457 1
L25
2

U3RXDP0

4

U3RXDN0

1
2

2

1

4

U2DP0_L

3

U2DP0_L

1

U2DN0_L

I/O1

I/O4

REF1 REF2
I/O2

I/O3

6
5
4

1
+USB3_VCCA

C486
220U_6.3V_M

1

U2DN0_L
U2DP0_L

R472 1 NCHR@ 2 0_0402_5%
R469 1 NCHR@ 2 0_0402_5%

U2DN0
U2DP0

R459
10K_0402_5%
CHR@

1
R462
0_0402_5%

2

2 10K_0402_5%
2

C635
0.1U_0402_16V4Z
CHR@

1

2

8
7
6
5

CB
CEN
TDM
DM
TDP
DP
VDD
SELCDP
Thermal Pad

1
2
3
4
9

USB_CEN
U2DN0
U2DP0

U3TXDN0
U3TXDP0

USB_CEN 33

1
2
@
R463 10K_0402_5%
1 CHR@ 2
R464 10K_0402_5%

SLG55584AVTR_TDFN8_2X2
CHR@

U3RXDN0
U3RXDP0

2

R460 1 CHR@

1
2

+3VALW

U46
33 USB_CHARGE_CB0
10 USB20_N0
10 USB20_P0
+5VALW

2
@

+

U2DN0_L

AZC099-04S_SOT23
@

W CM2012F2SF-670T04_0805
@

USB20_N0
USB20_P0

USB_OC0# 10,9

+USB3_VCCA

W=100mils
C487
1000P_0402_50V7K

2

U2DN0

R454
0_0402_5%
2
@

1

For USB2.0 ESD request

2 0_0402_5%
2 0_0402_5%
4

1

8
@
L05ESDL5V0NA-4 SLP2510P8

D16

U2DP0

W=60mils

3 3

1

OCE2012120YZF_4P
R458 1
R461 1
L26
3
3

8
7
6
5

OUT
OUT
OUT
OCB

SY6288DCAC_MSOP8

2 0_0402_5%
2 0_0402_5%

3

PCH_USB3_RX0_N

10 PCH_USB3_RX0_N

@
@

GND
IN
IN
EN/ENB

SF000002Y00
220U 6.3V OSCON
ESR 17mohm@100Khz

USB3.0 Conn.
JUSB1

1
2
3
4
5
6
7
8
9

VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+

GND
GND
GND
GND

10
11
12
13

OCTEK_USB-09EAEB
CONN@

SELCDP 33

2

DC233008O00
+5VALW

USB Host Charger
CB

SELCDP

0

X

DCP(Dedicated Charging Port)
autodetect with mouse/keyboard wakeup

1

0

S0 charging with SDP(Standard Downstream Port) only

1

1

S0 charging with CDP(Charging Downstream Port) or
SDP only

3

3

USB/B
(USB Port 1, Port2)
+5VALW

PWR/B

JUSB2

Reverse Stand-off Voltage :24V

JPW R1

GND
GND

ON/OFFBTN#
33 USB_EN#
10 USB20_N1
10 USB20_P1

2

LID_SW#
PWR_LED#
ON/OFFBTN#

+3VALW
+3VLP
LID_SW# 31,33
PWR_LED# 34
ON/OFFBTN# 31,34

3

1
2
3
4
5
6

1
2
3
4
5
6
7
8

D4
@

1

ACES_88514-00601-071
CONN@

10 USB20_N2
10 USB20_P2

USB_EN#
USB20_N1
USB20_P1
USB20_N2
USB20_P2

PJSOT24C_SOT23

1
2
3
4
5
6
7
8
9
10
11
12
13
14

SP010014M00

1
2
3
4
5
6
7
8
9
10
11
12
13
14
ACES_88514-01201-071
CONN@

SP01001BF00
4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

USB3.0 Conn/USB_B/PWR_B
Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
E

32

of

50

Rev
0.1

9 EC_SCI#
30 WLAN_ON

CLK_PCI_LPC
PLT_RST#
EC_RST#_R
EC_SCI#
WLAN_ON

12
13
37
20
38

ECAGND

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0

2.2K_0804_8P4R_5%

R488
R492

1
1

@
@

1

C511

2 10K_0402_5%
2 10K_0402_5%

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
PCH_PWR_EN

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

EC_SMI#
EC_SCI#

2 0.01U_0402_16V7K
@

PLT_RST#

ESD request

KSI[0..7]

31,34 KSI[0..7]

2

X1 @
32.768KHZ_12.5PF_FC-135
1 EC_XCLK0
EC_XCLK1 2

1
@

2

KSO[0..17]

31,34 KSO[0..17]

1
C513
15P_0402_50V8J

C514
15P_0402_50V8J

2

@

39,40
39,40
18,36,7
18,36,7

R605 1 DEG@ 2 E51TXD_P80DATA
0_0402_5%
R606 1 DEG@ 2 E51RXD_P80CLK
0_0402_5%

31 EC UART_TXD
31 EC UART_RXD

3

31 REC_MODE_L

R565
0_0402_5%

2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

8 PM_SLP_S3#
8 PM_SLP_S5#
8 EC_SMI#
12 PCH_PWR_EN
11,8 VCCST_PG_EC
30 WL_OFF#
39 EC_SPOK
1 36 FAN_SPEED1
30 E51TXD_P80DATA
30 E51RXD_P80CLK
34 PWR_SUSP_LED#
36 G_SEN_INT

8 SUSCLK

VCCST_PG_EC
WL_OFF#
EC_SPOK
FAN_SPEED1
REC_MODE_L_R
E51TXD_P80DATA
E51RXD_P80CLK
9012_PCH_PWROK
PWR_SUSP_LED#
G_SEN_INT

EC_XCLK1
1
2
EC_XCLK0
R502
0_0402_5%
2 932@ 1
R504
100K_0402_5%
C516 1
932@

2 20P_0402_50V8

122
123

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PW M/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PW ROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

XCLKI/GPIO5D
XCLKO/GPIO5E

9012@

EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F

PS2 Interface

CPU1.5V_S3_GATE/GPXIOA00
W OL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00

BT_ON#
BEEP#
USB_EN#

63
64
65
66
75
76

BATT_TEMP

2
1

ADP_I
AD_BID0

2

R478
R479

1
1

@
@

2
2

4.7K_0402_5%
4.7K_0402_5%

+3VS

EC_MUTE#

R481

1

@

2 10K_0402_5%

R588

1

2 10K_0402_5%

@

R482
0_0402_5%
2
1

45 VR_HOT#

H_PROCHOT# 38,39,4

DMN66D0LDW-7_SOT363-6
Q50B

Latest design guide suggest change to
74LVC1G06.

EN_DFAN1 36
SELCDP 32
USB_CHARGE_CB0 32

R491 2
R493 2

EC_MUTE# 35
LAN_PWR_EN# 28
WLAN_PME# 30
EC_ENTERING_RW 34
TP_CLK 34
TP_DATA 34

1 200K_0402_5%
1 200K_0402_5%

@
@

R509 1

+3VLP
+3VALW_EC

2 0_0402_5%

@ D20

97
98
99
109

VGATE_3V
USB_CHARGE_2A#
HDA_SDO
VCIN0_PH_R

SPI Flash ROM

GPIO
Bus

GPIO

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

119
120
126
128

1
EC_SI_SPI_SO
R158 2 932@ 49.9_0402_1% EC_SI_SPI_SO_R
1
EC_SO_SPI_SI
R159 2 932@ 49.9_0402_1% EC_SO_SPI_SI_R
1 R160
2 932@ 49.9_0402_1%
EC_SPICLK_R
EC_SPICLK
1 R146
2 49.9_0402_1% EC_SPICS#/FSEL#_R
EC_SPICS#/FSEL#
932@
1 100K_0402_5%
R691 2
ENBKL
ENBKL 8
930_PECI
FSTCHG
FSTCHG 40
BATT_BLUE_LED#
BATT_BLUE_LED#
34
EC_WLAN_LED#
EC_WLAN_LED# 34
PWR_LED
PWR_LED 34
BATT_AMB_LED#
BATT_AMB_LED# 34
SYSON
SYSON 37,42

ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PW R_LED#/GPIO54
BATT_LOW _LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APW ROK/GPXIOA10
SA_PGOOD/GPXIOA11

GPI

AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW #/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
V18R

73
74
89
90
91
92
93
95
121
127

PM_SLP_S4#

VGATE_3V 8
USB_CHARGE_2A# 32
HDA_SDO 6

1

ACIN 38,40,41,8

RB751V40_SC76-2
2
1 100P_0402_50V8J
C512

EC_ACIN

2

KB930&9012 Co-Layout Item
EC_SPICLK 31

PCH_RSMRST#
EC_LID_OUT#
VCIN1_PROCHOT_R
H_PROCHOT#_EC
GPXIOA07
BKOFF#
PBTN_OUT#
GPU_ACIN
MINI1_LED#

110
112
114
115
116
117
118

EC_ACIN
EC_ON
ON/OFF
LID_SW#
SUSP#
VCCST_PWRGD
9012_PECI

Pin 111 is a power source for HW operation of KB9012.
So, power plan will be different between KB930 and KB9012.
930_PECI

R496 1 932@

9012_PECI

R497 1 9012@ 2 43_0402_1%

H_PECI 4

9012_PCH_PWROK 2 9012@ 1
R498
0_0402_5%
2 932@ 1
GPXIOA07
R499
0_0402_5%
2
1
@
R500
0_0402_5%

+3VALW_EC

C515
4.7U_0603_6.3V6K

@

R501 1
R505 1

VCIN0_PH_R
VCIN1_PROCHOT_R
R590 1

@

1 932@
R601
1K_0402_5%

R507 2 932@

1 47K_0402_5%

KSO2

R508 2 932@

1 47K_0402_5%

+EC_SPI
KB932 use 256KB ROM
KB9012 Embedded 128KB ROM
D28

EC_SPICS#/FSEL#_R
1 DEG@ 2 EC_SI_SPI_SO_R
R598
0_0402_5%
R510
1
2 4.7K_0402_5% SPI_WP#
@

2

U29

1
2
3
4

/CS
VCC
DO_IO1 /HOLD
/W P
CLK
GND
DIO_IO0

8
7
6
5

W25X20BVSNIG_SO8
SA00003GM10
932@

+3VALW_EC

1

2 932@ RB751V40_SC76-2

2 932@ 0.1U_0402_16V4Z
C518 1
R511
1 932@ 2 4.7K_0402_5%
SPI_HOLD#
+EC_SPI
EC_SPICLK
1 DEG@ 2
EC_SO_SPI_SI_R
EC_SO_SPI_SI_R1 31
R600
0_0402_5%
2
R513

@

1
0_0402_5%

@
C520

4

33P_0402_50V8K

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

VCIN0_PH 39
VCIN1_PROCHOT 39

+3VALW_EC

KSO1

EC_SPICLK

Security Classification

2 0_0402_5%
2 0_0402_5%

2 10K_0402_5% H_PROCHOT#_EC

PU will disable PH function

KB932&9012 Co-Layout Item

2013/07/10

Deciphered Date

Title

EC ENE-KB9012

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

3

R696
10K_0402_5%

D28 design for Debug board flash SPI ROM
(can be short after MP)

U28

PCH_PWROK 8
MAINPWON 39,41

Pin104 This co-layouted circuit is for power fail function of
KB930 and KB9012.At KB930, PCH_PWROK will be connected to pin 104.
At KB9012,PCH_PWROK will be connected to pin 32,
and VCOUT0_PH will be connected to pin 104.

20mil

Issued Date

2 43_0402_1%

BKOFF# 24
PBTN_OUT# 8
GPU_ACIN 18
MINI1_LED# 30

R697
10K_0402_5%

+EC_SPI

KB932QF-A0_LQFP128
932@

+3VLP

0_0402_5%

Pin74(KB930),Pin118(KB9012) are with different PECI pin location,
so HW must co-layout for it.
Please make sure which EC pin will be connected to PECI circuit.

EC_ON 34,41
ON/OFF 34
LID_SW# 31,32
SUSP# 37,40,42,43,44
VCCST_PWRGD 11,44

31 EC_SPICS#/FSEL#_R
31 EC_SI_SPI_SO_R1

C517
0.1U_0402_16V4Z
@

2

R495

PCH_RSMRST# 8
EC_LID_OUT# 9

1

2

+3VALW

0_0402_5%

1

+V18R

KB9012QF-A3_LQFP128_14X14

2

@

R494

@

124

1

+EC_VCC

PM_SLP_S4# 8

100
101
102
103
104
105
106
107
108

2
ECAGND 1
L32
BLM18AG121SN1D_2P

SA000055I00

1

EC_PME# 28

31,6,7 SPI_WP1#_R

2

TP_CLK
TP_DATA

H_PROCHOT#_EC 5
EC_PME#

EC_MUTE#
LAN_PWR_EN#
WLAN_PME#
EC_ENTERING_RW
TP_CLK
TP_DATA

Analog Board ID definition,
Please see page 3.

1

+5VS

1 100P_0402_50V8J ECAGND

1
R506
0_0402_5%

Rb

4.7K_0402_5%
4.7K_0402_5%

BATT_TEMP 38,39

83
84
85
86
87
88

Board ID

AD_BID0

2
2

USB_CEN 32
ADP_I 39,40

EN_DFAN1
SELCDP
USB_CHARGE_CB0

+3VALW_EC

R503
100K_0402_5%
@

1
1

EC_ENTERING_RW

BT_ON# 30
BEEP# 35
USB_EN# 32

68
70
71
72

SM010030010 200ma 120ohm@100mhz DCR 0.2

Ra

R485
R483

SMB_ALERT#_R 34

SPI Device Interface

Follow KB930 checking List

4

1

2

GND/GND
GND/GND
GND/GND
GND/GND
GND0

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

DA Output

11
24
35
94
113

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

+3VS

67

AD Input

21
23
26
27

C510 2

BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43

2 100K_0402_5%

Q50A
DMN66D0LDW-7_SOT363-6

ECAGND 39

PWM Output

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

6

7,9 SMB_ALERT#

GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13

1

4

7 CLK_PCI_LPC
34,4,8 PLT_RST#

EC_SMB_DA1
EC_SMB_CK1
EC_SMB_CK2
EC_SMB_DA2

1
2
3
4
5
7
8
10

C508
0.1U_0402_16V4Z

2

+3VS

8
7
6
5

KBL_EN#
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

+3VALW_EC
R476

LID_SW#

+3VS

+EC_VCCA

2

RP12

1
2
3
4

U28

1

2

E

1

PU at LAN side

+3VALW_EC

1

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

34 KBL_EN#
9 EC_KBRST#
34,9 SERIRQ
34,7 LPC_FRAME#
34,7 LPC_AD3
34,7 LPC_AD2
34,7 LPC_AD1
34,7 LPC_AD0

2 100K_0402_5% EC_PME#

@

2

+EC_VCC

D

200ma 120ohm@100mhz DCR 0.2

1

1

2

2
DEG@ 0_0402_5%

+3VALW_EC

R484

2

2
@

C507
1000P_0402_50V7K

R591

1

2

R236
0_0805_5%

2
@

C506
1000P_0402_50V7K

1

31,34 EC_RST#

EC_RST#_R

0.1U_0402_16V4Z

1
@

C505
0.1U_0402_16V4Z

1

1
@

C504
0.1U_0402_16V4Z

1 47K_0402_5%

C509 2

1

C503
0.1U_0402_16V4Z

R480 2

2

C502
0.1U_0402_16V4Z

1
1

+3VALW_EC

EC_VDD/AVCC

+3VLP

AGND/AGND

1
CLK_PCI_LPC
33_0402_5%

69

@

L31
SM010030010
BLM18AG121SN1D_2P
1
2 +EC_VCCA
1

9
22
33
96
111
125

2
R477

C

+3VALW_EC
R24
0_0805_5%
1
2
@

3

B

+3VALW

2

A

C501
22P_0402_50V8J
2
1
@

Tuesday, September 25, 2012

Sheet
E

33

of

50

B

2Y1
2Y0
2S

GND
PAD

10
7
8

KSI0
F3_BTN
ON/OFF

D25
@

ON/OFF

3

GND

6

EC_ENT_RW

BTN_A

EC_ENTERING_RW
R586 1 932@
0_0402_5%
R589 1 932@
0_0402_5%

7

EC_IN_RW

BTN_B

1
2
3
4
5
6

5

8

EC_RST#

9

PAD

2
2

33

EC_IN_RW 9
EC_RST# 31,33

GND
GND

F3 + Power BTN --> Reset EC

R693 2

9
10

G1
G2

1

ACES_51524-0080N-001
CONN@

1

D36
932@
RB751V40_SC76-2

C551
100P_0402_50V8J

+3VS_TP

LEFT_BTN#

RIGHT_BTN#
LEFT_BTN#

7
8

SP01001A900

932@ 1 10K_0402_5%

3

SW4
AE1G-A120T_4P
1

4

D34
PJDLC05C_SOT23-3
@

3

RIGHT_BTN#

2

SW5
AE1G-A120T_4P
1

4

2

100g for Press

100g for Press

2

1

KB BackLight Conn.
+5VS
JBL1
D

3

+5VALW

1

4
3
2
1

+5VS_BL

2

G

BL@
R451
Q44
100K_0402_5% DMG2301U-7_SOT23-3
1
BL@ 2 KBL_EN_R

2
G
Q26
L2N7002LT1G_SOT23-3
@

33 KBL_EN#

4
3
2
1

G2
G1

6
5

D

PW R_LED# 32

Q17
L2N7002LT1G_SOT23-3

2
G

33 PWR_LED

SP01000Z300
D

LED

PW R_LED#

ACES_50504-0040N-001
CONN@

2
1

1
R592
0_0402_5%

S

S

2

33 BATT_AMB_LED#

BATT_AMB_LED#

3

B

A

2

1
R699

2
51_0402_5%

4

1
R698

2
390_0402_5%

2

1
R700

2
51_0402_5%

4

1
R701

2
390_0402_5%

LTST-C295TBKF-CA_AMBER-BLUE
LED7

33 PWR_SUSP_LED#

PW R_LED#

1

PWR_SUSP_LED#

3

B

A

+3VS

2

LTST-C295TBKF-CA_AMBER-BLUE

HDD LED

+3VS

4

2
ON/OFFBTN#

R534
100K_0402_5%
9012@

1
51ON#

3

1

1
3
5
7
9
11
13
15
FOX_QT510166-L010-7H
CONN@

LPC_AD3
LPC_AD2
CLK_PCI_TPM
LPC_FRAME#
LPC_AD1
LPC_AD0
LPCPD#_R
SERIRQ

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

LPC_AD3 33,7
LPC_AD2 33,7
CLK_PCI_TPM 7
LPC_FRAME# 33,7
LPC_AD1 33,7
LPC_AD0 33,7

+3VS

R392

2 TPM@

1

SERIRQ 33,9
R444
1
2
@
0_0402_5%

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

Issued Date

B

2
4
6
8
10
12
14
16

8 LPCPD#

SP020011OA0
Security Classification

31,32 ON/OFFBTN#

2
4
6
8
10
12
14
16

10K_0402_5%

12/9 modify pin define

Q39
S
L2N7002LT1G_SOT23-3
932@

3

2
R624
10K_0402_5%
932@

2
390_0402_5%

JTPM1

1
3
5
7
9
11
13
15

CLKRUN#
PLT_RST#

D

2
G

1

4
@

EC_ON

1
R702

LTST-C191KFKT-2CA_ORANGE

+3VALW
+3VS

6
5
2

1

8 CLKRUN#
33,4,8 PLT_RST#

BAV70W _SOT323-3

33,41 EC_ON

2

A

MC74VHC1G08DFT2G_SC70-5

51ON# 38

4

SW 3
AE1G-A120T_4P
1
3

PCH_SATALED# 6

TPM Board

ON/OFF 33

3
2

1

1

1

D24

LED8

1

EC_W LAN_LED#

33 EC_WLAN_LED#

5IN1_LED# 28

+3VLP

R522
100K_0402_5%
932@
SW 1
AE1G-A120T_4P
1
3

A

Y

+3VS

2

2

+3VALW _EC

P

MEDIA_LED#

U39
2
B

G

1

3

@
R632
10K_0402_5%

5

A

LTST-C191TBKT-CA_BLUE

6
5

33 BATT_BLUE_LED#

1

C524
0.1U_0603_25V7K
@

+3VS

A

+3VALW

LED6

BATT_BLUE_LED#

1

27
28

G1
G2

ON/OFF BTN

TOP

2

8 TP_INT#

TP_DATA 33
TP_CLK 33

SP010014M00

R740
LED4
51_0402_5%
1
2 2

4

33 SMB_ALERT#_R
10,9 TP_WAKE#

2 0_0402_5%
2 0_0402_5%

0.1U_0402_16V4Z
2
C663 1

1
2
3
4
5
6

ACES_88514-00601-071
CONN@

SLG4N059VTR_TDFN8_2X2

SP01000IJ00

Bottom

R608 1
@
R607 1 932@

1
2
3
4
5
6
7
8

+5VS

E-T_6905-E26N-01R
CONN@

Test Only

D_CK_SDATA
D_CK_SCLK

15,16,7 D_CK_SDATA
15,16,7 D_CK_SCLK

To TP/B Conn.
JTP2

PWR_BTN#

4

JTP1

1
2
3
4
5
6
7
8

5
6

F3_BTN

1 C552
932@

5
6

2

2

TP_CLK
TP_DATA

2

ON/OFF

TP Conn.

2 0_0402_5%
@
932@ 2 0_0402_5%

0.1U_0402_16V4Z

(For Wake Up and Interrupt)

+3VALW _EC
C523
932@
0.1U_0603_25V7K
U44
932@
2
1
1
VDD

27
28

2

R609 1
R610 1

+3VS
+3VALW _PCH

AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3

NX3L4684TK_MO-229-10_3X3
932@

G1
G2

@

2

1

D30
@

1

KSO5

1

3

6
11

2
5
4

1

1Y1
1Y0
1S

1Z
2Z

S

3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

VCC

3
9

KSO5_SW
KSI0_SW

KB Conn.
JKB2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

@

U41

1

+3VS_TP

C553
100P_0402_50V8J

C522 932@
0.1U_0603_25V7K
2
1

SP01000IJ00

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5_SW
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0_SW
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KSI0
KSO5

+3VALW _EC

E-T_6905-E26N-01R
CONN@

2

0_0402_5%
0_0402_5%

3

1 9012@ 2
1 9012@ 2

R577
R585

2

KSI0_SW
KSO5_SW

1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

KSO[0..17] 31,33

3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

E

D_CK_SDATA
D_CK_SCLK
TP_CLK
TP_DATA

KSI[0..7] 31,33

KSO[0..17]

3

1

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5_SW
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0_SW
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

D

3

KSI[0..7]

KB Conn.
JKB1

C

2

A

D

Title

KB & TP & TPM Connector & LED
Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
E

34

of

50

Rev
0.1

4

A

B

C

D

E

Int. Speaker Conn.
+VDDA

4.75V

2

0.1U_0402_16V4Z
2
@

+VDDA

@

2

GND

HP_PLUG#

3

C444

2

1
2

R238 1

2 47_0603_1%

HP_RIGHT R237 1

2 47_0603_1%

29

10mil
30

GND

C583 1
R546 2

68mA 600mA

SPK_OUT_L+

2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
1 20K_0402_1%

10mil31
10mil27
39
7
15

MIC2_R

SPK_OUT_L-

LINE1_L

SPK_OUT_R+

LINE1_R
SPK_OUT_RMIC1_L
HPOUT_L
MIC1_R
HPOUT_R
CBN
SDATA_OUT

MIC2_VREFO

SYNC
RESETB

MIC1_VREFO_R
BCLK

2
2

@

1
1

43

SPKL-

45

SPKR+

44

SPKR-

32

HP_LEFT

8

C575 1

2 2.2U_0402_6.3V6M

39.2K_0402_1%
20K_0402_1%

CPVEE

SENSE_A

34

10mil13
14
48

5

GPIO1/DMIC_CLK
JDREF

CPVEE

PCBEEP

SENSE A
SENSE B

MONO_OUT
AVSS2

HDA_SDIN0

6

VREF

HDA_RST_AUDIO#

HDA_RST_AUDIO#

HDA_BITCLK_AUDIO

2
1
@
0_0402_5%

HDA_RST_AUDIO#

6

For EMI
C573

3

DMIC_CLK

47

12

2

16
38
28

GND

1

BEEP#_R

C555
1U_0402_6.3V6K

@

2

1

2

1

1

1
1

3

1

@

1

2

1

2

GNDA Place next pin27

2

2

1
2
3
4

1
2
5
3 G1 6
4 G2
ACES_88266-04001
CONN@

SP02000K200

GND

GND

3

+INTMIC_VREFO

GND

SM010004010 300ma 70ohm@100mhz DCR 0.3

R417
AMIC@
10K_0402_5%
INT_MIC_R

BEEP# 33

2

R529
47K_0402_5%

CODEC_VREF

10mil
25

2

2

EC_MUTE# 33

MONO_IN

1

1

15mil

100P_0402_50V8J
C556

J12
JUMP_43X39
1
2
2
@ 1

+3VS_DMIC
DMIC_CLK_R
DMIC_DATA_R

D26
PJDLC05C_SOT23-3
@

GND

4.7K_0402_5%
R531

J11
JUMP_43X39
1
2
2
@ 1

2 0_0603_5%
2 0_0603_5%
2 0_0603_5%

C719
R671
1000P_0402_50V7K10K_0402_5%

22P_0402_50V8J

DMIC_DATA

C578
10U_0603_6.3V6M

J14
JUMP_43X39
1
2
2
@ 1

R162 1
DMIC@ 1
DMIC@ 1

2

GND

+3VS

C572
@
0.1U_0402_16V7K

6

2

@

AVSS1

GND
J7
JUMP_43X39
1
2
2
@ 1

2

R143
R668

R544
4.7K_0402_5%
@

6
6

2

SPDIFO
DVSS

1

3

HDA_SYNC_AUDIO

6

ALC3225-CG_MQFN48_6X6

GND

HDA_SDOUT_AUDIO

10
11

reseve for EMI

C577
2.2U_0402_6.3V6M

49

GNDA

HP_RIGHT

C576
0.1U_0402_16V4Z

4

GND

JMIC1
DMIC_CLK
DMIC_DATA

2
HDA_SDIN0_AUDIO 1 R547
33_0402_5%

LDO1_CAP

LDO3_CAP

Int. MIC
A+D

GND

@

33

1
R548
GPIO0/DMIC_DATA

GNDA

1

MIC2JD

4

R543
22K_0402_5%

+3VS

@

LDO2_CAP

2

COM_MIC

2

GNDA

2

R545
R549

SPKL+

MIC1_VREFO_L

PD#

HP_PLUG#_1
MIC2JD_1

42

GNDA

1

1

36

9

DVDD

35mA

MIC2_L

CBP

1

DC230009K00

D1
AZ5125-02S.R7G_SOT23-3

2

LINE2_R

46

41

40

26

LINE2_L

C571

R542
22K_0402_5%
1
2

7

1

37

+INTMIC_VREFO

C574 1

Q28
@
LBSS138LT1G_SOT-23-3
2
MIC2JD
G

GNDA

SDATA_IN

C570
2.2U_0402_6.3V6M

3

GNDA

D

10U_0603_6.3V6M
2

2
0.1U_0402_16V4Z

R539
2.2K_0402_5%

MIC2JD_1

6
SINGA_2SJ3053-100111F
CONN@

HP_PLUG#

1

18

35

+MIC2_VREFO

GND

2
5

COM_MIC

2

17

20
1

C584 1

1
C564

10U_0603_6.3V6M

DVDD_IO

23

19

Place near
codec

1

HPOUT_R_2

+MIC2_VREFO
+3VS

GND Place near Pin1, 9

CPVDD

24

PVDD2

LINE2_C_L
4.7U_0603_6.3V6K
2
LINE2_C_R
4.7U_0603_6.3V6K
2
MIC2_C_L
4.7U_0603_6.3V6K
2
MIC2_C_R
4.7U_0603_6.3V6K

PVDD1

2

AVDD2

U34

21

GNDA

2

S

GNDA

22

GNDA

HPOUT_L_2

2

2

C562
@

2
0.1U_0402_16V4Z

2

1
C636

1

C561

1
INT_MIC
C770 1
1K_0402_5%
2
C769 1
1000P_0402_50V7K
C568 1
1 COM_MIC_R
1K_0402_5%
C569 1

L52 1
0_0603_5%

1

2
R540

1
@ C582

AVDD1

1
2

20mil

0.1U_0402_16V4Z
1

SM010030010 200ma 120ohm@100mhz DCR 0.2

20mil
+3VS_DVDD 0.1U_0402_16V4Z

1

GNDA

C567
10U_0603_6.3V6M

GNDA

COM_MIC

C62

Combo MIC

2
R726
1

4
3

2

2

Headphone Out
COM_MIC

GNDA
HP_PLUG#

Place near Pin25, 38

INT_MIC_R

1

1
2
HPOUT_R_1
L38
BLM18AG121SN1D_2P

1

C605
10U_0603_6.3V6M

HD Audio Codec

1

+AVDD1_HDA

Internal MIC

GND

GNDA
C445

330P_0402_50V7K
1

L36
BLM18AG121SN1D_2P
1
2
HPOUT_L_1

Place near Pin46

Place near Pin40

+VDDA

2

+3VS_VDDA

SM010030010 200ma 120ohm@100mhz DCR 0.2

2

2

JHP1
330P_0402_50V7K

HP_LEFT

2

GND

S

GND

0.1U_0402_16V4Z
C604

1

2
G

Q31
L2N7002LT1G_SOT23-3

GNDA

1

L54 1
0_0603_5%

1

1

0.1U_0402_16V4Z
1
C559

Place near Pin41

L55 2
0_0603_5%

+3VS

GND

SP02000K200

D37
AZ5125-02S.R7G_SOT23-3
@

D

0.1U_0402_16V4Z
1
C558

2

C608
10U_0603_6.3V6M

1

D27
AZ5125-02S.R7G_SOT23-3
@

1
+PVDD_HDA

40mil
1
L33 2
FBMA-L11-201209-221LMA30T_0805

5
6

2

SM010014520 3000ma 220ohm@100mhz DCR 0.04

G1
G2

R523
100K_0402_5%

HP_PLUG#_1

+VDDA

1
2
3
4

ACES_88266-04001
CONN@

1

(output = 300 mA)

GND

1

JSPK1

1
2
3
4

SPK_R+
SPK_RSPK_L+
SPK_L-

3

JUMP_43X118
@

40mil

40mil

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

2

2

2
2
2
2

2

C554

1

1
1
1
1

3

40mil
1

R527
R528
R532
R533

SPKR+
SPKRSPKL+
SPKL-

2

J6

3

+5VS

For EMI
L51
1
2
FBMA-L11-160808-800LMT_0603
AMIC@

C550
AMIC@
220P_0402_50V7K

15milDMIC_CLK_R
DMIC_DATA_R

R181
1 AMIC@ 2 0_0603_5%

PCH_SPKR 9

R530
47K_0402_5%

GNDA

GNDA
4

GNDA

GNDA
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

2013/07/10

Deciphered Date

Title

HD Audio Codec ALC3225

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Tuesday, September 25, 2012

Sheet
E

35

of

50

Rev
0.1

FAN1 Conn

AP2113AMTR-G1_SO8

1

1

1

1

1

1

1

1

@

@

@

@

JFAN1
1
2
3

33 FAN_SPEED1
C630
1000P_0402_50V7K
@

1

1

@

@

@

@

@

@

1
2 GND
3 GND

@

@

H22
H_2P5N

SP020020710

H23
H_2P5X3P5N
@

1

@

1

+3VS

+3VS

2

R518
10K_0402_5%
GSEN@
U2

18,33,7 EC_SMB_CK2
18,33,7 EC_SMB_DA2
+3VS

1

FD3

FD4

1

4
5

ACES_88231-03041
CONN@

2 10K_0402_5%
R519 1
@
R520 1 GSEN@ 2 10K_0402_5%

8
4
6
7
16
15
13
2
3

Vdd_IO
CS
SCLSPC
SDA/SDI/SDO
SDO/SA0

Vdd
INT1
INT2

ADC1
ADC2
ADC3

RES

NC
NC

GND
GND

1

C633 1

14

C628 1

11
9

G_SEN_INT

GSEN@
2 10U_0603_6.3V6M
GSEN@
2 0.1U_0402_16V4Z

G_SEN_INT 33

10
5
12

LIS3DHTR_LGA16_3X3
GSEN@

@

Issued Date

Deciphered Date

J10
JUMP_43X39
1
2
2
@ 1

J20
JUMP_43X39
1
2
2
@ 1

J17
JUMP_43X39
1
2
2
@ 1
J16
JUMP_43X39
1
2
2
@ 1

J21
JUMP_43X39
1
2
2
@ 1
J19
JUMP_43X39
1
2
2
@ 1

J18
JUMP_43X39
1
2
2
@ 1

J22
JUMP_43X39
1
2
2
@ 1

J24
JUMP_43X39
1
2
2
@ 1
J25
JUMP_43X39
1
2
2
@ 1

J28
JUMP_43X39
1
2
2
@ 1
J29
JUMP_43X39
1
2
2
@ 1

J23
JUMP_43X39
1
2
2
@ 1

J27
JUMP_43X39
1
2
2
@ 1

J26
JUMP_43X39
1
2
2
@ 1

J30
JUMP_43X39
1
2
2
@ 1

J31
JUMP_43X39
1
2
2
@ 1

J33
JUMP_43X39
1
2
2
@ 1

J32
JUMP_43X39
1
2
2
@ 1

J34
JUMP_43X39
1
2
2
@ 1

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

@

FIDUCIAL_C40M80

J35
JUMP_43X39
1
2
2
@ 1

LIS3DH
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)
Security Classification

@

FIDUCIAL_C40M80

For TP ESD soultion

H27
H_3P7

1

1
2

40mil

2

@

H21
H_2P5

@ C631
1000P_0402_50V7K
1
2

+VCC_FAN1

1

@

FIDUCIAL_C40M80

C627
4.7U_0603_10V6K
1
2

R516
10K_0402_5%

@

FD2

FIDUCIAL_C40M80

H13
H14
H15
H16
H20
H24
H_4P0 H_4P0 H_4P0 H_4P0 H_4P0 H_4P0

C626
0.1U_0402_16V4Z
@

+3VS

@

1

2

@

1

1

@

1

R515
0_0402_5%

GND
GND
GND
GND

1

1

EN
VIN
VOUT
VSET

1

33 EN_DFAN1

+VCC_FAN1
2

8
7
6
5

1

U31
1
2
3
4

FD1

1

H3
H4
H5
H6
H9
H10
H11
H12
H17
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

1

C632
4.7U_0603_10V6K
1
2

1

+5VS

2013/07/10

Title

FAN & Screw Hole & G-Sensor

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

V5WE2 M/B LA-9531P Schematic

Date:

Tuesday, September 25, 2012

Sheet

36

of

50

A

B

C

D

E

Normall Platform (Not support M-STATE and Deep Sleep)
+5VALW TO +5VS

2
Q30B
DMN66D0LDW -7_SOT363-6
@

4

+5VALW

6
7

+5VALW

GND

ON2

CT2

VIN2
VIN2

VOUT2
VOUT2
GPAD

12

2

C976
1 330P_0402_50V7K

2

1

11
330P_0402_50V7K
C967

9
8

2

2

2

1

2
SUSP
G
Q37
L2N7002LT1G_SOT23-3
@

S

3

3

S

+1.35V

2
6511_PW R_EN# 26
G
Q38
L2N7002LT1G_SOT23-3
@

+5VALW

R554
100K_0402_5%
@

1

R573
470_0603_5%
@

SYSON#

6

3

+1.35V_R
3VS_GATE 11

+1.8VS_6511_R
D

1

1
3

SUSP

Q32A
DMN66D0LDW -7_SOT363-6
@

1
+1.05VS_VTT_R

2

3

2

5

Q32B
DMN66D0LDW -7_SOT363-6
@

C598
0.1U_0603_25V7K
@

1

2
2

2
1

R568
470_0603_5%
@

D

2
SUSP
G
Q36
L2N7002LT1G_SOT23-3
@

S
+3VS_R

3VS_GATE

R559
150K_0402_1%
SUSP

+0.675VS_R

2

1

2

6 1

4

10mil
@

S

+1.8VS_6511

R567
470_0603_5%
@

D

R558
470_0603_5%
@

1

2

+VSB

1

1

4

20mil

@

@

C597
1U_0402_6.3V6K

1

2

C596
4.7U_0603_6.3V6K

2

+1.05VS_VTT

R566
470_0603_5%
@

+3VS
U35
DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5

C595
4.7U_0603_6.3V6K

C594
4.7U_0603_6.3V6K

1

@

1

D

2
G

R555
10K_0402_5%

15

1

+3VALW TO +3VS
+3VALW

2

33,40,42,43,44 SUSP#

+5VS

TPS22966DPUR_SON14_2X3

Reserved

SUSP

Q29
L2N7002LT1G_SOT23-3

10

+0.675VS

2

42 SUSP

1

CT1

VBIAS

5

5VS_ON

ON1

1

C592
0.1U_0603_25V7K
@

SUSP

3

3VS_ON

+3VS

1

+5VS_R

47K_0402_5%
2 R927
1
C980
1
2
0.1U_0402_16V4Z
2 R926
1
20K_0402_1%
C979
1
2
0.1U_0402_16V4Z

14
13

1

2
1

SUSP#

VOUT1
VOUT1

2

1

2

Q30A
DMN66D0LDW -7_SOT363-6
@

R551
470_0603_5%
@

5

2

SUSP

2

5VS_GATE

6

2

1

3

4

10mil

2

@

VIN1
VIN1

1

R553 1 @
100K_0402_5%

+VSB

1

1
2

+3VALW

4

2

@

C588
1U_0402_10V6K

20mil

1

R552
100K_0402_5%

U11
C587
4.7U_0603_10V6K

2

@

U33
DMN3030LSS-13_SOP8L-8
1
2
3

8
7
6
5

C586
4.7U_0603_10V6K

1

C585
4.7U_0603_10V6K

1

+5VALW

+5VS

3

+5VALW

5
SYSON
Q40B
DMN66D0LDW -7_SOT363-6
@

SYSON#

1

4

2
Q40A
DMN66D0LDW -7_SOT363-6
@

SYSON 33,42

3

3

+3VS to +3VSDGPU for GPU

4

2
@

100mil(1.5A)

GND
EN

3

2
C621
VGA@
1 4.7U_0603_6.3V6K

VGA_ON# 2

APL3512ABI-TRG_SOT23-5

1
2

+1.8VSDGPU_R

3

+1.5VSDGPU_R

2

SS

1

1

1

VIN

1

C620
4.7U_0603_6.3V6K
VGA@

VOUT

R571
470_0603_5%
@

C169
2200P_0402_50V7K

Q45A
DMN66D0LDW -7_SOT363-6
@

4

5
R424
0_0402_5%
1
2
@

R570
470_0603_5%
@

+3VSDGPU

VGA@

1

U12

6

+3VS

2

+1.8VSDGPU

2

+1.5VSDGPU

5 VGA_ON#
Q45B
DMN66D0LDW -7_SOT363-6
@

42,43,44,46,8,9 VGA_ON
4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

DC Interface
Size
Document Number
Custom

V5WE2 M/B LA-9531P Schematic

Date:

Sheet

Tuesday, September 25, 2012
E

37

of

50

Rev
0.1

A

B

PL102
HCB2012KF-121T50_0805
1
2

+5VS
1

PL101
HCB2012KF-121T50_0805
1
2

@PR102
@
PR102
47K_0402_1%

3

BATT_TEMP 33,39

2

1
1

@ PR104
@PR104
1.5M_0402_5%
@ PC106
100P_0402_50V8J

@ PR101
@PR101
100K_0402_1%

1

2

2

2

-

2

1

1
1

@PD102
@
PD102
LL4148_LL34-2

+

O

@ PU102A
@PU102A
LM393DR_SO8

S

2

8
1

P

2
G

@ PQ101A
DMN66D0LDW-7_SOT363-6

G

6

@ PC105
0.022U_0402_16V7K
2
1

D

@ PR103
@PR103
10K_0402_1%

4

33,39,4 H_PROCHOT#

2

PC104
1000P_0603_50V7K

1

1

1
PC103
100P_0603_50V8

2

PC102
100P_0603_50V8

2

2

PC101
1000P_0603_50V7K

+3VALW

1

1

1

DC_IN_S1

2

1
2
3
4
GND
GND

D

VIN

1

CONN@ PJP101
ACES_50305-00441-001_4P

C

@ PR106
47K_0402_1%

3

@ PD101
LL4148_LL34-2

3

2

-

5
6

ACIN 33,40,41,8

4

4

@ PR108
@PR108
68_1206_5%

930@ PQ102
TP0610K-T1-E3_SOT23-3

2

2

@ PR107
@PR107
1.5M_0402_5%

@ PR109
@PR109
68_1206_5%

1

VS

3

34 51ON#

1

@ PC109
@PC109
0.1U_0603_25V7K

2

2

930@ PC108
0.22U_0603_25V7K

2

930@ PR111
22K_0402_1%
1
2

2

930@ PR110
100K_0402_1%

1

1

N1

@ PD103
@PD103
LL4148_LL34-2

1

2

JUMP_43X39

+

O

2

1

2

1

BATT+

@PJ101
@
PJ101
1

7

S

1

930@ PD104
LL4148_LL34-2
2
1

1

@ PQ101B
DMN66D0LDW-7_SOT363-6

1

2

5
G

8

@PC107
@
PC107
0.022U_0402_16V7K
2
1

D

2

@ PU102B
@PU102B
LM393DR_SO8

P

VIN

G

H_PROCHOT#

2

2

3

@PR105
@
PR105
0_0402_5%
1
2

+3VLP

-

PBJ101 @
2

+
1

PR113
560_0603_5%
1
2

PR112
560_0603_5%
1
2

+CHGRTC

+RTCBATT

ML1220T13RE
4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

Title

DCIN
V5WE2 M/B LA-9531P Schematic

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

Tuesday, September 25, 2012
D

Sheet

38

of

50

Rev
0.1

A

C

D

+3VLP

PL202
HCB2012KF-121T50_0805
1
2

1

1

1
2

1

1

@ PC209
0.1U_0603_25V7K

1

@ PR230
10K_0402_1%

1

BATT_TEMP 33,38

@ PU204

1

@ PR231
100K_0402_1%

EC_SMB_CK1 33,40

2
MAINPWON

2

EC_SMB_DA1 33,40

3
4

8

VCC TMSNS1

7

GND RHYST1

2

6

OT1 TMSNS2

1

@ PR232
47K_0402_1%

1

2

2

@ PR229
10K_0402_1%

2

PC201
0.01U_0402_25V7K

2

PR203
1K_0402_1%

PR208
1K_0402_1%
1
2

PC202
1000P_0402_50V7K

2

PR201
100_0402_1%

BATT+ <45,47>

2

PR202
100_0402_1%

+3VLP

2

1

2
1
PR206
6.49K_0402_1%

1

PL201
HCB2012KF-121T50_0805
1
2

1

1

CONN@ PJP201
SUYIN_200275GR008G13GZR
10
GND 9
GND 8
BATT_S1
8 7
7 6
BI
6 5
TH
5 4
EC_SMCK
4 3
EC_SMDA
3 2
2 1
1

B

5

OT2 RHYST2

@ PH202
100K_0402_1%_NCP15WF104F03RC

2

G718TM1U_SOT23-8

2

2

PH201 under CPU botten side :
CPU thermal protection at 90 degree C ( shutdown )
Recovery at 56 degree C

PQ202
TP0610K-T1-E3_SOT23-3

+3VLP

1

3

MAINPWON

2

1

@ PQ204
2N7002KW_SOT323-3

@ PR221
1_0402_1%

2

4

G

GND RHYST1
~OT1 TMSNS2
~OT2 RHYST2

7
6
5

1

1

2

@
PR222
10.5K_0402_1%

B value:4250K±1%
+VSB

PR225
10K_0402_1%

2

+VSBP

VCIN1_PROCHOT 33

2

@
PR222
16.2K_0402_1%

PH201
100K_0402_1%_NCP15WF104F03RC

2

1

1

2

VCIN0_PH 33

G718TM1U_SOT23-8

@ PJ201

1

90W@ PR218
8.87K_0402_1%

2
1
@ PR220
9.53K_0402_1%

1

3

S

VCC TMSNS1

8

65W@ PR218
3.92K_0402_1%

2

1

2

2

PU201

PR228
21K_0402_1%

1

3

1

33,41 MAINPWON

D

S

2

@ PC208
1U_0402_6.3V6K

@

1

2

1

33,38,4 H_PROCHOT#

PQ203
2N7002KW_SOT323-3

G

@ PR214
21K_0402_1%

@ PR217
100K_0402_1%

@ PR216
100K_0402_1%

D

2

@ PC207
0.1U_0603_25V7K

2

1
1

2

1
2

41 SPOK

1

PR227
1_0402_1%

@

4

@

2

For 65W adapter==>action 70W , Recovery 54W
For 90W adapter==>action 97W , Recovery 75W

2

4

PR226
0_0402_5%

1

2

JUMP_43X39

33 ECAGND

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

Title

BATTERY CONN / OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

3

ADP_I 33,40

@ PR213
100K_0402_1%
@ PR219
1K_0402_1%
1
2

ADP_I >1.28V ,
CPU will throttling

+EC_VCCA

1

2

1

+VSBP

2

2

@

1
PC206
0.1U_0603_25V7K

VL

2

PR212
22K_0402_1%
2
1

1

1
PR211
100K_0402_1%

33 EC_SPOK
3

PC205
0.22U_0603_25V7K

3

B+

B

C

Tuesday, September 25, 2012
D

Sheet

39

of

50

Rev
0.1

A

B

C

D

1

D

3

for reverse input protection

S

2
G

1 2

1
2

2

1

1

PR305
1_0402_1%

2

1

PC318
10U_0805_25V6K

2

1

PC315
10U_0805_25V6K

2

1 CSON1

PC317
0.1U_0402_25V6

2

2

1 CSOP1

1

PR313
4.7_1206_5%

2
1
2

PC314
0.1U_0402_25V6

Min.
17.852V
17.476V

Typ
18.063V
17.687V

Max.
18.275V
17.898V

ILIM and external DPM
Min.
3.906A

Close EC

Typ
Max.
4.006A 4.108A

ADP_I 33,39
@ PC325
0.1U_0402_16V7K

4

2

S

PQ306
SIS412DN-T1-GE3_POWERPAK8-5

3
2
1
PC321
0.1U_0603_25V7K

1

1
2

1

@

EC_SMB_DA1 33,39
@ PR325
0_0402_5%
1
2

Vin Dectector
L-->H
H-->L

EC_SMB_CK1 33,39

PC324
100P_0402_50V8J

4

3

for Voltage level drop
close to charger

PR324
64.9K_0402_1%

3

1

D

@

+3VALW

@

1

33,37,42,43,44 SUSP#

@ PQ308
2N7002KW_SOT323-3
2
G

PC326
1000P_0402_50V7K

2
2

33 FSTCHG

PC308
0.01U_0402_50V7K

1

2

PR322
402K_0402_1%

ACDET
@ PQ307
PDTC115EU_SOT323-3

@ PR323
100K_0402_1%
1
2

BATT+

3

3

PR317
316K_0402_1%
2
1

PR327
2.2K_0402_5%
2
1

1

2

2
1
@PR321
@
PR321
2M_0402_1%

2 CSON1
PR315
6.8_0603_5%
BQ24725_BATDRV

PC322
0.01U_0402_25V7K

VIN

@ PR318
@PR318
2M_0402_1%

SRN 1

PR314
10_0603_5%
2 CSOP1

@

2

ILIM
1

1

ACDET

PR320
100K_0402_1%

6

33,38,41,8 ACIN

3

12
11

BATDRV
SCL

ACOK

SRP 1

2

SRN

9

5

ACDRV

13

10

ACOK

SRP

SDA

2
PR316
100K_0402_1%

CMSRC

4

DL_CHG

14

GND

8

1

5

REGN

ACP

IOUT

4

2

PL302
PR312
10UH_FDSD0630-H-100M-P3_3.8A_20%
0.01_1206_1%
2
4
BQ24725_LX 1
CHG 1

PC316
680P_0402_50V7K

3
2
1

2

2

15

LODRV

7

BQ24725_ACDRV

2
5

1
PR310
0_0603_5%
1
BQ24725_BST 2

ACN

ACDET

+3VLP

3

PQ305
SIS412DN-T1-GE3_POWERPAK8-5

4

DH_CHG-1

PC313
1U_0603_25V6K

16

17

18
HIDRV

1

BQ24735RGRR_QFN20_3P5X3P5
BQ24725_CMSRC

PR306
4.12K_0603_1%

PD303
RB751V-40_SOD323-2

BTST

DH_CHG

BQ24725_LX

19
PHASE

PAD

PR311
0_0603_5%
2
DH_CHG 1

PR326
2.2K_0402_5%

2

VCC

PU301

1

PC307
2200P_0402_50V7K

2
2

3
1
1
2

PC312
1U_0603_25V6K

21

@

2

PC310
0.047U_0402_25V7K
1
2

2
1

@

BQ24725_BATDRV 1

1

PD302
BAS40CW_SOT323-3

PR309
10_1206_1%

1

1
2

BQ24725_ACP

BQ24725_ACN

2

PC305
0.1U_0402_25V6
2
1

1
VIN

1

4x4x2

PC304
10U_0805_25V6K
2
1

3

2

2

PL301
1.2UH_PNS40201R2YAF_3A_30%
1
2

1

4

2

1

4

CHG_B+

PR303
0.02_1206_1%

PC306
0.1U_0402_25V6
1
2

PR308
4.12K_0603_1%

1

PR307
4.12K_0603_1%
2
1

2

B+

2

1

PC302
0.1U_0402_25V6

2

1

4

2

@

P2

PC303
10U_0805_25V6K

PQ303
SIS412DN-T1-GE3_POWERPAK8-5
1
2
3
5

1
2
3

5
PC301
2200P_0402_50V7K
2
1

100ppm

P1

PQ302
AON6414AL_DFN8-5

PR304
1_0402_1%

VIN

PR301
3M_0402_5%

PC311
0.1U_0603_25V7K

PR302
1M_0402_5%

1

PQ304
SIS412DN-T1-GE3_POWERPAK8-5
1
2
5
3

2

20

1

PC309
0.1U_0402_25V6

2

4

1

PQ301
2N7002KW_SOT323-3

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHARGER

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

Tuesday, September 25, 2012
D

Sheet

40

of

50

Rev
0.1

5

4

3

2

ENTRIPx adjustment range: 0.5V~3V,
floating or over 4.5V will shutdown channel.

Low

Low

ENTRIP1
(V)

ENTRIP2
(V)

LDO5

LDO3

+5VALW

+3VALW

X

X

Off

Off

Off

Off

Low
">2.3V"
=>High
">2.3V"
=>High
">2.3V"
=>High
">2.3V"
=>High

X

X

On

On

Off

Off

Off

Off

On

On

Off

Off

Off

On

On

On

Off

On

On

On

On

On

On

On

On

Off

On

On

On

Off

D

PR404
20K_0402_1%
1
2

9

1
FB1

5

PC404
10U_0805_25V6K
2
1

PR405

PR423
ENTRIP1 1
2

3
TON

ENTRIP1

19

PR407 PC410
2.2_0603_5% 0.1U_0603_25V7K
2 1
2
BST_5V 1
UG_5V
LX_5V

16

LG_5V

PL403
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
1
2
+5VALWP

1

2

+3VLP

Rds(on):13.5mΩ~16.5mΩ
3
2
1

1

ENM

PQ404
SI7716ADN-T1-GE3_POW ERPAK8-5

1
+

PC413
220U_6.3V_M

2

@

2

PC402
4.7U_0805_10V6K

@

1

2

4

Typ: 175mA

2

15

14

@PJ403
@
PJ403

@ PJ401

Typ: 225mA
VL

+3VALWP

1

1

2

2

+3VALW

JUMP_43X118
PC417
4.7U_0805_10V6K

B

@ PJ402

+5VALWP

1

1

2

2

+5VALW

JUMP_43X118

ENLDO threshold ON: 1.2min 1.6typ 2max
OFF: 0.9min 0.95typ 1max

5V=321KHz 3V=375KHz
(By Rton= 68K ohm)

(Vin=12

~ 25v)

+3.3VALWP Ipeak=6.16A ; Imax=4.31A
Delta I=1.578=>1/2Delta I=0.789A (F=375K Hz)
Rds(on)=16.5m ohm(max) ; Rds(on)=13.5m ohm(typical)
Ilimit_min=(107K*10uA)/(10*16.5m*1.2)=6.6049A
Ilimit_max=(107K*10uA)/(10*13.5m)=7.0712A
Iocp=Ilimit-1/2Delta I=7.3939~7.8602A

+5VALWP Ipeak=7A ; Imax=4.9A
Delta I=2.516=>1/2Delta I=1.2583A (F=321K Hz)
Rds(on)=16.5m ohm(max) ; Rds(on)=13.5m ohm(typical)
Ilimit_min=(118K*10uA)/(10*16.5m*1.2)=7.284A
Ilimit_max=(118K*10uA)/(10*13.5m)=7.7982A
Iocp=Ilimit+1/2Delta I=8.5423~9.0565 A

@

9012@ PR412
2.2K_0402_5%
1
2

13

2

LDO3

LDO5

1

18
17

JUMP_43X79

1

PR421
499K_0402_1%
1
2
PR422
150K_0402_1%
2
1

B

12

11
1

RT8243A_B+

C

7X7X3
Isat:6.6A
DCR: 40mΩ(Max)

2

Rds(on):13.5mΩ~16.5mΩ

B+

33,34 EC_ON

LGATE1

1

2

@

PQ403
SI7716ADN-T1-GE3_POW ERPAK8-5

PC416
0.1U_0603_25V7K

2

4

ENM

LGATE2

ENLDO

10

VIN

LG_3V

1
2
3

PC412
220U_6.3V_M

PC414
680P_0402_50V7K
2
1

+

PR406
1

ENTRIP2 1

PHASE1

@
1

ENTRIP2

PHASE2

PQ402
SIS412DN-T1-GE3_POW ERPAK8-5

4
20

PR410
4.7_1206_5%

8

LX_3V

BOOT1
PU401
RT8243AZQW _W QFN20_3X3
UGATE2
UGATE1

21

PC415
680P_0402_50V7K

UG_3V

BOOT2

5

+3VALWP

PR409
4.7_1206_5%
2
1

PL402
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
2
1

7

PAD
BYP1

3
2
1

PC411
0.1U_0603_25V7K

PGOOD

FB=1.98V(Min)
2.006V(Typ)
2.03V(Max)

5

2

6
PR408
2.2_0603_5%
1 2
1 BST_3V

4

5

39 SPOK

PC419
1U_0603_10V6K
2
1

7X7X3
Isat:6.6A
DCR: 40mΩ(Max)

1
2
3

4

FB=1.98V(Min)
2.006V(Typ)
2.03V(Max)

FB2

C

PQ401
SIS412DN-T1-GE3_POWERPAK8-5

5

PC405
2200P_0402_50V7K
2
1

@

PC403
10U_0805_25V6K
2
1

RT8243A_B+

PC401
0.1U_0402_25V6
2
1

B+

68K_0402_1%
2

PL401
HCB2012KF-121T50_0805
1
2

118K_0402_1%

2

PR403
20K_0402_1%
2
1

RT8243A_B+

ENM (V)

PR402
30K_0402_1%
2
1
107K_0402_1%
2

@ PL404
HCB2012KF-121T50_0805
1
2

ENLDO (V)

">1.6V"
=>High
">1.6V"
=>High
">1.6V"
=>High
">1.6V"
=>High
">1.6V"
=>High

D

PR401
13.3K_0402_1%
1
2

1

930@ PD401 930@ PR416
LL4148_LL34-2 1M_0402_1%
2
1
1
2

6

1

VL

D

2
G

VS

1
2

For EC use +3VALW,
mark "@" if use +3VLP

℃℃
℃

℃
℃
℃

TDC:4.31A Fsw:375KHz
H-MOS PD:0.3736W ∆T:12
L-MOS PD:0.2713W ∆T:7.9
Choke PD:1.5158W ∆T:24
OVP margin for Vos:8%

TDC:4.9A Fsw:321KHz
H-MOS PD:0.4173W ∆T:13.4
L-MOS PD:0.3442W ∆T:10
Choke PD:1.9613W ∆T:30
OVP margin for Vos:9%

A

D

5
G
930@ PQ405
S 930@ PQ406A
PDTC115EUA_SC70-3 DMN66D0LDW -7_SOT363-6

930@ PQ406B
DMN66D0LDW -7_SOT363-6
4

1

2

1
@ PR417
402K_0402_1%

930@ PR419
1M_0402_1%
1
2

2

VS

A

ENM

930@ PR418
316K_0402_1%
1
2
3 2
1
930@ PR420
10K_0402_1%

ACIN

VIN

33,38,40,8

PR414
P
R414
0_0402_5%
1
2

PC418
4.7U_0603_6.3V6K

33,39 MAINPWON

Compal Secret Data

Security Classification
2012/07/10

Issued Date

S

2013/07/10

Deciphered Date

Title

Compal Electronics, Inc.
3VALW/5VALW

3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Tuesday, September 25, 2012
Date:

Rev
0.1

V5WE2 M/B LA-9531P Schematic

5

4

3

2

Sheet
1

41

of

50

A

3
2
1

12
2

1

1

1
2

PGOOD_1.35V

VGA@ PC530
0.1U_0402_16V7K

VGA@ PR532
0_0402_5%
1
2

2

+0.675VS

1

1

2

2

+0.95VSDGPU

VGA@ PC531
0.22U_0603_10V7K
2
1

On
Off
(Hi-Z)

2012/07/10

VGA@ PC538
22U_0805_6.3V6M

VGA@ PC537
22U_0805_6.3V6M
2
1

VGA@ PC536
22U_0805_6.3V6M
2
1

1
2

+0.95VSDGPUP
Ipeak=4.28A ; 1.2Ipeak=5.136A ;Imax=2.996A
F=131904/(PR534^0.9492)=1000KHz, PR534=169KΩ

Compal Electronics, Inc.

Compal Secret Data

Security Classification

VGA@ PC535
22U_0805_6.3V6M
2
1

1
VGA@ PR536
100K_0402_1%

VGA@ PC540
22P_0402_50V8J

2

FB=0.799V

VGA@ PR535
19.1K_0402_1%
2
1

10
9

@ PC539
680P_0402_50V7K

@ PR533
4.7_0402_1%
2
1

+0.95VSDGPUP
11

1

SS/TR

VGA@ PL506
1UH_PCMB063T-1R0MS_12A_20%
1
2

LX_0.95V

2

RT/CLK

GND

COMP

PH

12

VGA@ PC542
2200P_0402_50V7K

BOOT

13

14

PH

VGA@ PU504
TPS54618

GND

PW RPD

PH

1

VIN

PWRGD

15

VIN

VSENSE

2

EN

16
VIN
1

AGND

VGA@ PC534
22U_0805_6.3V6M

1
2

@

Issued Date

Note: S3 - sleep ; S5 - power off

1

2

0.95V_VIN
PC533
22U_0805_6.3V6M

VGA@ PL505
HCB2012KF-121T50_0805
1
2

0.675VSP

Off
Off
Off
(Discharge) (Discharge) (Discharge)

2

VGA@ PR531
100K_0402_1%

1

Lo

1

2

Lo

2

JUMP_43X118

6
VGA@ PC541
VGA@ PR537
3300P_0402_50V7K 18K_0402_1%
7
2
1 2
1
VGA@ PR534
169K_0402_1%
2
1
8

S4/S5

2

@ PJ511

5

On

1

+0.95VSDGPUP

EN_0.95V

2

1

VGA@ PR530
1K_0402_1%
1
2

37,43,44,46,8,9 VGA_ON

2

On

On

1

JUMP_43X79

1

On

Hi

+1.35V

@ PJ506

2

Hi

Lo

2

JUMP_43X118

+0.675VSP

2

PR510
10K_0402_1%

2

@ PJ505

1

@

FB=0.75V
To GND = 1.5V
To VDD = 1.8V

1

JUMP_43X118
PC510
1U_0603_10V6K

SNUB_0.95V

Hi

S3

1

@ PJ504

1

+1.35VP

17

S0

PC506
330U_2.5V_M

1

1

PC511
0.1U_0402_16V7K

VTT_REFP

2

+

+5VALW

PR505
5.1_0603_5%

+3VALW

4

1.35VP

1

2

Rds=4.2mΩ(Typ)
5.0mΩ(Max)

11

3

S5

2

@ PC507
680P_0402_50V7K

PR509
8.06K_0402_1%
2
1

+3VALW

S3

PC503
2200P_0402_50V7K

2
1

1

2

@ PR503
4.7_1206_5%

2

PR504
8.45K_0402_1%
2
1

+1.35VP

DCR:8.5mΩ

PR508
887K_0402_1%
2
1 1.35V_B+

S

STATE

PC502
10U_0805_25V6K

1
13

@

6.6x7.3x3.8 TAI-TECH

PQ503
S TR MDU1512RH 1N POWERDFN56-8

5
14

PC509
1U_0603_10V6K
2
1

PGOOD
10

S5

TON
9

FB

VDD

4

LG_1.35V

PR506
10K_0402_1%
2
1

PHASE

16

17

VDDP

15

B+

PL501
S COIL 1.5UH 20% TMPB0604M-1R5MN-Z01 11A
1
2

1

2

1

D

UGATE

18
BOOT

19
VLDOIN

20

RT8207MZQW_WQFN20_3X3

VDDQ

2

PC512
0.1U_0402_16V7K

1

PQ501
2N7002KW_SOT323-3
2
SUSP
G

CS

VTTREF

6

1
2

PC508
0.033U_0402_16V7K

GND

PGND

PR507
1_0402_1%
1
2

3

37 SUSP

+1.35VP

LGATE

VTTSNS

@ PR501
680K_0402_1%
1
2

33,37 SYSON

1

5

VTTGND

S5_1.35V 8

4

+VTT_REFP

PAD

S3

1

3

15 DDR_VTT_PG_CTRL

PC504
0.1U_0603_25V7K
1
BST_1.35V-1 2

LX_1.35V

VTT

PU501

21

2

PR513
1_0402_1%
1
2

PQ502
MDV1525URH_PDFN33-8-5

5
3
2
1

1

JUMP_43X39

靠靠Output Cap PAD

S3_1.35V 7

1

PC505
10U_0805_25V6K

2

1

PC501
10U_0805_25V6K

+0.675VSP

33,37,40,43,44 SUSP#

PR502
2.2_0603_5%
1
BST_1.35V 2

120%

2

115%

4

UG_1.35V

2

@

2

PJ503

1

+1.35VP

2012/9/6

OVP=110%

PL507
HCB2012KF-121T50_0805
2
1

1.35V_B+

PC521
0.1U_0402_25V6

+1.35VP
Ipeak = max{ 0.7*Ibudget, 1st +2nd max loading}
Ipeak = max{ 12.34*0.7 ,
4.2+8.14
}
Ipeak=12.34A ; 1.2Ipeak=14.808A ;Imax=8.638A
1/2Delta I=0.7353A (F=300K Hz)
PR504=(1.2Ipeak-1/2Delta I) *Rds(on)(max)*1.2/9uA=8.45Kohm
choose PR504=8.45Kohm (for safety >1.2Ipeak)
Rds(on)=5.0m ohm(max) ; Rds(on)=4.2m ohm(typical)
Ilimit_min=(8.366K*9uA)/(5.0m*1.2)=15.058A
Ilimit_max=(8.535K*11uA)/(4.2m*1.2)=22.352A
Iocp=Ilimit+1/2Delta I=15.79A~23.09A
Iocp(min)>1.2Ipeak

Deciphered Date

2013/07/10

Title

1.35VP/0.675VSP/0.95VSDGPUP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V5WE2 M/B LA-9531P Schematic

Date:

A

Tuesday, September 25, 2012

Sheet

42

of

50

Rev
0.1

4

3

2

1

VFB= 0.704V
Vo=VFB*(1+11.5K/10K)= 1.5V
Freq=290KHz(typ)

VGA@ PL504
HCB2012KF-121T50_0805
2
1

DRVL
TP

C

VGA@ PR514
470K_0402_1%

Frequency(KHz)

470
200
100
39

290
340
380
430

7

+5VALW

6

DL_1.5VSG

11

TPS51212DSCR_SON10_3X3

4

VGA@ PC515
1U_0603_10V6K

Rds=13.5mΩ(Typ)
16.5mΩ(Max)

VGA@ PR515
11.5K_0402_1%
2
1

1
2

1
2

1
2

1

@ PC518
10U_0805_25V6K

+1.5VSDGPUP

1
+

@ PR518
4.7_1206_5%

VGA@ PC523
330U_2.5V_M

2
@ PC522
680P_0402_50V7K

C

1

FB=0.704V

2

VGA@ PL502
4.7UH_PCMB063T-4R7MS_5.5A_20%
1
2

2

Resistance(KΩ)

SW _1.5VSG

1

V5IN

TST

DH_1.5VSG

8

2

VFB

9

1

5

SW

D

2

4

DRVH

EN

VGA@ PC514
0.1U_0603_25V7K
1
2

B+

5

FB_1.5VSG
RF_1.5VSG

TRIP

BST_1.5VSG

3
2
1

3

10

1

2

EN_1.5VSG

VBST

1

VGA@ PC513
0.1U_0402_16V7K

TRIP_1.5VSG

PGOOD

2

1

VGA@ PR511
1K_0402_1%
1
2

2

37,42,44,46,8,9 VGA_ON

1

3
2
1

VGA@ PR517
2.2_0603_1%
1
2

VGA@ PU502
VGA@ PR512
56.2K_0402_1%
2
1

VGA@ PC517
10U_0805_25V6K

4

VGA@ PC516
2200P_0402_50V7K

5

Cesr= 15m ohm
Ipeak= 4.7A Imax= 3.29A Iocp=5.64A
Iocp= 5.72A~6.43A

VGA@ PQ505
SI7716ADN-T1-GE3_POWERPAK8-5

D

VGA@ PQ504
SIS412DN-T1-GE3_POWERPAK8-5

1.5VSG_B+

@ PC519
0.1U_0402_25V6

5

+3VS
1

2

VGA@ PR516
10K_0402_1%

2

PC526
1U_0402_6.3V6K

2

+1.5VSDGPU

1

1
2

@

PC524
22U_0805_6.3V6M

1
@ PR522
22K_0402_5%

PC527
0.1U_0402_16V7K

PC525
22U_0805_6.3V6M

FB_1.5VSP

PR521
22.6K_0402_1%

2

2

FB=0.8V

2

1

PR519
20K_0402_1%

B

+1.5VSP

2

1
1

1

2

@ PJ509

+1.5VSDGPUP

2

+1.5VSP_ON

1

33,37,40,42,44 SUSP#

PR523
1_0402_1%
1
2

FB

2

EN
POK

GND

1

8
7

2

PC528
4.7U_0603_6.3V6K

1

PU503
APL5930KAI-TRG_SO8
6
5 VCNTL
3
VOUT 4
9 VIN
VIN
VOUT

B

PC529
0.022U_0402_16V7K
2
1

Note:Iload(max)=3A

JUMP_43X118
@ PJ510

1

1

2

2

JUMP_43X118

Ien=10uA, Vth=0.3V, notice
the res. and pull high
voltage from HW

@ PJ508

A

+1.5VSP

1

1

2

2

+1.5VS

A

JUMP_43X39

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

+1.5VSP/+1.5VSDGPUP
Size
Document Number
Custom

Rev
0.1

V5WE2 M/B LA-9531P Schematic

Date:

Tuesday, September 25, 2012

Sheet
1

43

of

50

5

4

3

2

1

+1.05VSP Ipeak=5.36A ; Imax=3.752A ; 1.2Ipeak=6.432
Delta I=0.xxxxA=>1/2Delta I=0.xxxxA,F= 800K Hz(typ)

PR603
330K_0402_1%
2
1

D

D

SUSP# 33,37,40,42,43

PR607
1M_0402_1%
1
2

2

1

PC629
22U_0805_6.3V6M

1
2

1
2

PC628
22U_0805_6.3V6M

@

@ PC607
680P_0402_50V7K

2

PC608
4.7U_0603_6.3V6M

1

PC601
4.7U_0603_6.3V6M
2
1

+3VS

2

PR618
10K_0402_1%
2
1

C

@ PR604
4.7_0805_5%

PC627
22U_0805_6.3V6M

+3VALW

5

1

LDO

FB_+1.05VSP

8

2

PG

4

1

BYP

+1.05VSP

9

2

FB

ILMT

PL601
0.68UH_PCMC063T-R68MN_15.5A_20%
1
2

1

GND

SW_+1.05VSP

2

@ PC614
0.1U_0402_16V7K

LX

BST_+1.05VSP

12

PC626
22U_0805_6.3V6M

1

2
PR619
1M_0402_1%

GND

6

PC625
22U_0805_6.3V6M

3

LX

2

13

BS

GND

PC624
22U_0805_6.3V6M

10

IN

PC606
0.1U_0402_16V7K
1
2

PR602
PC605
0_0603_5% 0.1U_0603_25V7K
1
2
1
2

1

7

PU601
SY8208DQKC_QFN14_3X3
1
EN_+1.05VSP
IN
EN

1 2

PC623
10U_0805_25V6K
2
1

PC604
10U_0805_25V6K
2
1

14

1

1
2
@ PR613
10K_0402_1%

+3VS

11

2

@ PC602
0.1U_0402_25V6
2
1

PC603
2200P_0402_50V7K
2
1

B+

C

PR605
100K_0402_1%
2
1

@ PJ602

1

+1.05VSP

VFB=0.6V

1

2

2

+1.05VS_VTT

JUMP_43X118
@ PJ603
1
2
1
2

1

11,33 VCCST_PWRGD

JUMP_43X118
PR608
133K_0402_1%

1

2

+3VS

2

PC615
1U_0402_6.3V6K

+3VS

Note:Iload(max)=3A
1
2
1

1

@

1

VGA@ PR616
15.8K_0402_1%

2

@ PR617
22K_0402_5%

2

Ien=10uA, Vth=0.3V, notice
the res. and pull high
voltage from HW

PC622
22U_0805_6.3V6M

1

+1.8VSDGPU_ON

2

VGA@ PC619
0.1U_0402_16V7K

1
FB_1.8VSDGPU

2

VGA@ PR615
1_0402_1%
1
2

2

1

2

2

37,42,43,46,8,9 VGA_ON

VGA@ PR614
20K_0402_1%

FB=0.8V

1

2

+1.8VSDGPU
VGA@ PC621
22U_0805_6.3V6M

FB

VGA@ PC620
0.022U_0402_16V7K
2
1

EN
POK

2

8
7

GND

1

VGA@ PU603
APL5930KAI-TRG_SO8
6
5 VCNTL
3
VOUT 4
9 VIN
VIN
VOUT
VGA@ PC618
4.7U_0603_6.3V6K

PR611
15.8K_0402_1%

PR612
22K_0402_5%

B

Note:Iload(max)=3A

PC612
22U_0805_6.3V6M

1
2

@

VGA@ PC617
1U_0402_6.3V6K

2

1

1

1

+1.8VS_6511_ON

2

PC616
0.1U_0402_16V7K

1
2

FB_1.8VS_6511

+1.8VS_6511
PC613
22U_0805_6.3V6M

PR609
20K_0402_1%

FB=0.8V

PC611
0.022U_0402_16V7K
2
1

1

2

1

PR610
1_0402_1%
1
2

26 6511_PWR_EN

FB

2

EN
POK

2

8
7

GND

PC610
4.7U_0603_6.3V6K

B

1

PU602
APL5930KAI-TRG_SO8
6
5 VCNTL
3
VOUT 4
9 VIN
VIN
VOUT

A

A

Ien=10uA, Vth=0.3V, notice
the res. and pull high
voltage from HW

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

2013/07/10

Deciphered Date

Title

+1.05VSP/+1.8VSDGPU/+1.8VS_6511

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Tuesday, September 25, 2012

Sheet
1

44

of

50

5

4

3

2

1

6

PWM1

2

1

PC705
0.1U_0402_25V6

PC706
68U_25V_M_R0.36

3

DCR:0.82mΩ±5%

PR716
24.9K_0402_1%
1
2
PH702
PR717
10K_0402_1%_TSM0A103F34D1RZ
3.01K_0402_1%
1
2
1
2
PC711
0.1U_0402_16V7K
1
2

Close choke.

B value:3435K

PC712
0.068U_0402_16V7K
1
2

2

4

C

CSN1
CSP1

3

VGATE 11,8
2

PC746
1U_0402_6.3V6K

Use X7R is better or far away inductor.

Maximum current: 32A

@ PR725
2K_0402_1%

33

PAD

1

+3VS

2

1
PR724
1_0402_1%

VDD

1

1

2

2

1

PC741
0.1U_0402_16V7K

1
PR731
130_0402_1%

1

PR730
75_0402_1%

@

2

2

2

1
PR729
54.9_0402_1%

+1.05VS_VTT

51622_VREF

COMP
PR727
3.48K_0402_1%
2
1

PR734
10K_0402_1%

5

Close to PWR IC

VR_SVID_DATA 11
VR_ALERT# 11
VR_SVID_CLK 11

1

PR726
10K_0402_1%
2
1

@

CSP1-1 2
PR715
2.21K_0402_1%
2
1

1
1 2
2

SKIP#

1

VR_ON 11

7

2

ALERT#
32

VCLK
31

VDIO

8

DROOP
PC742
100P_0402_50V8J
2
1

1

CPU_PHASE1
PC740
1U_0603_10V6K

9
O-USR

11

10
F-IMAX

12
OCP-I

14

13
IMON

THERM

B-RAMP

VDD

VR_HOT#

GND

VFB

30

24

N/C
PGOOD

GFB

29

VFB

N/C

V5A

23

PWM2

TPS51622RSM_QFN32_4X4~D

PU3

VREF

GFB

PWM1
PU701

CSP2

28

0_0402_5%
2
0_0402_5%
2

CSN2

27

PR721
1
PR722
1

SKIP#

25

11 VCC_SENSE

@

15

16
22
@
11 VSS_SENSE

SLEWA

VBAT
21

+3VS

2

+CPU_CORE

@
VR_ON

CSN1

COMP

@
C

CSP1

DROOP

@

D

PL702
0.22UH_PCMB104T-R22MS_35A_20%
1
4

+5VS

PC714
PR714
680P_0402_50V7K 4.7_1206_5%

PU702
CSD97374CQ4M_SON8_3P5X4P5
5
1 SKIP#
SKIP# 2
6 VIN
BOOT_R VDD 3
PGND1 4
7
BOOT
VSW
8
9 PWM
PGND2

1

2.2_0603_5%
1CPU_BOOT1
0.1U_0603_25V7K
2CPU_BOOT1-1
PWM1

2

PR701
2
PC701
1

26

17

2

@

B+

1
PC749
1000P_0402_50V7K

F-IMAX

PR713
10K_0402_1%
1
2 VBAT

18
CSN1
PR718 0_0402_5%
2
1
19
PR719 0_0402_5%
1
2
20

+

2

B-RAMP

O-USR

CSP1

PC704
2200P_0402_50V7K

1
2

1
2

1

PC709
10U_0805_25V6K

@

1

OCP-I

PR712
39K_0402_1%
2
1

CPU_B+

PC703
10U_0805_25V6K

@ PR711
10K_0402_1%
1
2 SLEWA

PL701
HCB2012KF-121T50_0805
2
1

2

PR709
PR710
392K_0402_1% 56K_0402_1%
1
2
1
2

PL703
HCB2012KF-121T50_0805
2
1
CPU_B+

PC702
10U_0805_25V6K

THERM

PC747
0.1U_0402_25V6
2
1

D

@

PR707
PR704
150K_0402_1% 8.87K_0402_1%
2
1
2
1

Close MOS.
PC748
4700P_0402_25V7K
1
2

2

PR708
10K_0402_1%
2
1

PR705
PR702
150K_0402_1% 100K_0402_1%
2
1
2
1

1

B value:4250K

PR706
PR703
39K_0402_1% 274K_0402_1%
2
1
2
1

51622_VREF
PH705
100K_0402_1%_TSM0B104F4251RZ

PC743
PR728
PC744
1500P_0402_50V7K 10K_0402_1% 0.33U_0402_10V6K
2
1 1
2

2

VR_HOT# 33

1

V5A

2

B

2

1

+5VS

PR732
10_0603_5%
PC745
1U_0402_6.3V6K

B

Consider use 0603 for inrush power.

VIN

12V-20V

MAX current

32A

Thermal current

10A

Dynamic current

27A

Over current level

45A

Switching frequency

600KHz

Boot voltage

1.7V

DC Load- line

2m Ohm

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

2013/07/10

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+CPU_CORE

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Tuesday, September 25, 2012

Sheet
1

45

of

50

Rev
0.1

VID0

1

0

1

0

0

0
5
4

VGA@ PR802
2.2_0603_5%
2
1

BOOT2_VGA

VGA@ PC806
0.22U_0603_10V7K
1
2
BOOT2_2_VGA
UGATE2_VGA

VGA@ PR848
0_0603_5%
1
2

3
2
1

2
1
@ PR837
10K_0402_1%

UGATE2-1_VGA

VGA@ PL804
S COIL 0.22UH 20% FDUE0640-H-R22M=P3 25A
1
2

@ PR805
4.7_1206_5%

1
2

1
2
1
2

3
2
1

2
1
VGA@ PR838
10K_0402_1%

2
1
VGA@ PR840
10K_0402_1%

2
1
@ PR842
10K_0402_1%

2
1
VGA@ PR844
10K_0402_1%

2
1
@ PR846
10K_0402_1%
GPU_VID_5
GPU_VID_4
GPU_VID_3
GPU_VID_2
GPU_VID_1

30
29
28
27
26
25
24
23
22
21

+VGA_CORE

DCR: 0.97mΩ±5%

VGA@ PR808
1_0402_5%

7x7x4
VGA@ PR809
10K_0402_1%
1
2V1N_VGA

VSUM+_VGA

VSUM-_VGA
ISEN2_VGA

@ PC807
680P_0402_50V7K

C

@ PR812
0_0402_5%
2
1

@ PR813
0_0402_5%
2
1

1

ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1

+5VS

VGA_CORE
Freq.=400KHz
Imax=27.00A
Ipeak=40.50A
Iocp=49.00A
LL= disable
Cesr= xx mOHM

VGA@ PC810
1U_0603_10V6K

11
12
13
14
15
16
17
18
19
20

2

AGND

ISL62883CHRTZ-T_TQFN40_5X5

2
@ PR817
0_0402_5%
2
1
@ PR819
0_0402_5%
2
1

Layout Note:
Place near Phase1 Choke

1
2

VGA@ PC820
10U_0805_25V6K
2
1

+VGA_CORE

1

DCR: 0.97mΩ±5%

7x7x4

2

VGA@ PR833
10K_0402_1%
1
2V2N_VGA

VGA@ PR832
1_0402_5%

2

PR829
4.7_1206_5%

VGA@ PR830
3.65K_0402_1%
2
1

2

@

1

1

V1N_VGA

1

3
2
1
2

VGA@ PL802
S COIL 0.22UH 20% FDUE0640-H-R22M=P3 25A
1
2

VSUM-_VGA

VSUM+_VGA
@

5
4

LGATE1_VGA
VGA@ PH801
10K_0402_1%_TSM0A103F34D1RZ

VGA@ PR836
953_0402_1%
1
2

VGA@ PC819
10U_0805_25V6K

4

VGA@ PR831
10K_0402_1%

VGA@ PR826
2.61K_0402_1%
2
1

UGATE1-1_VGA

VGA@ PC821
0.22U_0603_10V7K
1
2

PHASE1_VGA

1

VGA@ PR828
11K_0402_1%
2
1

@ PC824
0.1U_0603_25V7K
2
1

VGA@ PC823
0.22U_0603_16V7K
2
1

2
1

VGA@ PR824
2.2_0603_5%
2
1 BOOT1_1_VGA

2

VGA@ PR835
10_0402_5%
1
2

2

2
1

VGA@ PC826
1000P_0402_50V7K
20 VSS_GPU_SENSE

@ PC825
330P_0402_50V7K
2
1

VGA@
PC822
330P_0402_50V7K

2

1

1

20 VCC_GPU_SENSE

@ PR827
82.5_0402_5%

VSUM+_VGA

@ PC827
0.01U_0402_25V7K

+VGA_CORE

VGA@ PR847
0_0603_5%
1
2

UGATE1_VGA

VGA@ PR823
10_0402_5%
1
2

B

VGA@ PQ801
MDU1516URH_POWERDFN56-8-5

VGA@ PC818
0.22U_0603_25V7K

1
2

VGA@ PC817
1U_0603_10V6K
2
1

1

VSUM-_VGA

+VGA_B+

+5VS

BOOT1_VGA

B

2

1

VGA@ PR820
324K_0402_1%

+VGA_B+

VGA@ PR821
1_0402_5%
2
1

ISEN1_VGA

VGA@ PQ802
MDU1511RH_POWERDFN56-8-5

ISEN2_VGA

2

+5VS

5

1
2
VGA@ PR818
3.57K_0402_1%

3
2
1

VGA@ PC812
470P_0402_50V7K

VGA@ PC816
0.22U_0402_10V4Z

1

41

VGA@ PR816
499_0402_1%
1
2
1

2

VGA@ PC814
150P_0402_50V8J

2

2

BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1

PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2

VGA@ PC815
0.22U_0402_10V4Z

1
2

2

1

1
2
3
4
5
6
7
8
9
10

@ PC809
33P_0402_50V8J

VGA@ PC813
47P_0402_50V8J
1
2

1

VGA@ PR810
100K_0402_5%
1
2

+3VS

VGA@ PC811
1000P_0402_50V7K

VGA@ PR815
5.9K_0402_1%
1

VGA@ PR811
47K_0402_1%
2
1

D

V2N_VGA

4

LGATE2_VGA

B+

VGA@ PC808
1U_0603_10V6K
1
2

CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0

VGA@ PU801

40
39
38
37
36
35
34
33
32
31

C

VGA@ PL803
HCB2012KF-121T50_0805
2
1

PHASE2_VGA
5

2
1
@ PR839
10K_0402_1%

2
1
VGA@ PR841
10K_0402_1%

2

2
1
VGA@ PR804
10K_0402_1%

2
1
VGA@ PR845
10K_0402_1%

@ PR803
1_0402_1%
1
2
18 GPU_DPRSLPVR

1
@ PR843
10K_0402_1%

2

@ PC805
0.1U_0402_16V7K

VGA@ PL801
HCB2012KF-121T50_0805
2
1

@

VGA@ PQ803
MDU1516URH_POWERDFN56-8-5

+3VSDGPU

+VGA_B+

1

VID1

2

VID2

VGA@ PC804
10U_0805_25V6K
2
1

VID3

VGA@ PQ804
MDU1511RH_POWERDFN56-8-5

VGA_ON

1

37,42,43,44,8,9

PR801
P
R801
0_0402_5%
1
2

VID4

18
18
18
18
18

GPU_VID_5
GPU_VID_4
GPU_VID_3
GPU_VID_2
GPU_VID_1

@

D

1.0V 0

VID5

VGA@ PR806
3.65K_0402_1%
2
1

AMD
MARS XT

VID6

1

VGA@ PR807
10K_0402_1%

Default
Voltage

VGA Chipset

2

VGA@ PC803
10U_0805_25V6K
2
1

3

VGA@ PC802
2200P_0402_50V7K
2
1

4

PC801
0.1U_0603_25V7K
2
1

5

PC828
680P_0402_50V7K

ISEN1_VGA

VSUM-_VGA

A

VGA@
PC829
0.1U_0402_16V7K

2

1

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

+GPU_COREP
Size
C
Date:

5

4

3

2

Document Number

V5WE2 M/B LA-9531P Schematic
Tuesday, September 25, 2012
1

Sheet

46

of

50

Rev
0.1

4

3

2

PWR Rule
CPU DCLL=1.5m ohm dedign 330uF/9m *0, 22uF *30

1

1
2
1
2

1
2
1
2

1
2
1
2

1
2
1
2

1
2
1

2
1
2

2

1

1
2
1

2
1

D

For BOT side

PC927
22U_0805_6.3V6M

PC926
22U_0805_6.3V6M

PC925
22U_0805_6.3V6M

PC924
22U_0805_6.3V6M

PC923
22U_0805_6.3V6M

PC922
22U_0805_6.3V6M

PC921
22U_0805_6.3V6M

PC920
22U_0805_6.3V6M

2

PC909
22U_0805_6.3V6M

PC908
22U_0805_6.3V6M

PC907
22U_0805_6.3V6M

PC906
22U_0805_6.3V6M

PC905
22U_0805_6.3V6M

PC904
22U_0805_6.3V6M

D

PC903
22U_0805_6.3V6M

PC902
22U_0805_6.3V6M

1

+CPU_CORE

2

5

+CPU_CORE

2

1

2

PC941
22U_0805_6.3V6M

2

1

PC940
22U_0805_6.3V6M

2

1

PC939
22U_0805_6.3V6M

2

1

PC938
22U_0805_6.3V6M

2

1

PC937
22U_0805_6.3V6M

2

1

PC936
22U_0805_6.3V6M

22u *26, @*6

C

1

PC935
22U_0805_6.3V6M

2

PC934
22U_0805_6.3V6M

1

@

For TOP side
C

1

2

1

@

2

@

1

2

PC956
22U_0805_6.3V6M

2

@

PC955
22U_0805_6.3V6M

1

PC954
22U_0805_6.3V6M

2

@

PC953
22U_0805_6.3V6M

2

1

PC952
22U_0805_6.3V6M

2

1

PC951
22U_0805_6.3V6M

1

PC950
22U_0805_6.3V6M

2

PC949
22U_0805_6.3V6M

1

@

B

B

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

CPU_CORE_CAP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

V5WE2 M/B LA-9531P Schematic

5

4

3

2

Date:

Tuesday, September 25, 2012

1

Sheet

47

of

50

5

4

3

2

1
+

VGA@ PC1018
2.2U_0402_6.3V6M

D

PC1027
330U_D2_2.5VY_R9M

+

VGA@ PC1017
2.2U_0402_6.3V6M
2
1

VGA@ PC1008
10U_0402_6.3V6M

1

VGA@ PC1026
560U_2.5V_M

2

VGA@ PC1016
2.2U_0402_6.3V6M
2
1

VGA@ PC1007
10U_0402_6.3V6M
2
1
+

VGA@ PC1025
560U_2.5V_M

VGA@ PC1015
2.2U_0402_6.3V6M
2
1

VGA@ PC1006
10U_0402_6.3V6M
2
1
VGA@ PC1014
2.2U_0402_6.3V6M
2
1
VGA@ PC1024
2.2U_0402_6.3V6M

VGA@ PC1005
10U_0402_6.3V6M
2
1
VGA@ PC1013
2.2U_0402_6.3V6M
2
1
VGA@ PC1023
2.2U_0402_6.3V6M
2
1

VGA@ PC1004
10U_0402_6.3V6M
2
1
VGA@ PC1012
2.2U_0402_6.3V6M
2
1
VGA@ PC1022
2.2U_0402_6.3V6M
2
1

VGA@ PC1003
10U_0402_6.3V6M
2
1
VGA@ PC1011
2.2U_0402_6.3V6M
2
1
VGA@ PC1021
2.2U_0402_6.3V6M
2
1

VGA@ PC1002
10U_0402_6.3V6M
2
1
VGA@ PC1010
2.2U_0402_6.3V6M
2
1
VGA@ PC1020
2.2U_0402_6.3V6M
2
1

1

VGA@ PC1001
10U_0402_6.3V6M
2
1

2
1
2

VGA@ PC1009
2.2U_0402_6.3V6M
2
1

1
2

VGA@ PC1019
2.2U_0402_6.3V6M
2
1

C

1

1

AMD MARS
GPU_CORE
560uF*2+330uF*2
10uF*8+2.2uF*16

+VGA_CORE

D

2

2@

C

AMD MARS
VDDCI
330uF*1+2.2uF*1

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

VGA_CORE CAP
Size Document Number
Custom

Rev
0.1

V5WE2 M/B LA-9531P Schematic

Date:

Tuesday, September 25, 2012

Sheet
1

48

of

50

A

B

C

D

E

1

1

2

2

3

3

4

4

2012/07/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2013/07/10

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PIR-HW

V5WE2 M/B LA-9531P Schematic

Date:

A

B

C

D

Sheet

Tuesday, September 25, 2012
E

49

of

50

Rev
0.1

5

4

3

2

Version change list (P.I.R. List)
Item

D

1

Fixed Issue

Page 1 of 2
for PWR
Reason for change

VGA boot voltage

1

Vboot Voltage can not allow
to boot to 1.1V

Rev.

PG#

Modify List

VGA

Date

take off the PR212

11/22

Phase

EVT2

D

2
3
4
5
6
C

C

7
8

9
10
11
B

B

12
13
14

15
16

A

17

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

2013/07/10

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PIR (PWR)

V5WE2 M/B LA-9531P Schematic

Date:

5

4

3

2

Tuesday, September 25, 2012

Sheet
1

50

of

50

Rev
0.1

www.s-manuals.com



---

Source Exif Data:

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File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.4
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39
Create Date                     : 2012:09:25 19:44:15Z
Creator Tool                    : PScript5.dll Version 5.2.2
Modify Date                     : 2015:04:06 01:37:47+03:00
Metadata Date                   : 2015:04:06 01:37:47+03:00
Format                          : application/pdf
Creator                         : 
Title                           : Compal LA-9531P - Schematics. www.s-manuals.com.
Subject                         : Compal LA-9531P - Schematics. www.s-manuals.com.
Producer                        : GPL Ghostscript 8.15
Document ID                     : uuid:207ff047-2984-4f05-821c-f413d477a12a
Instance ID                     : uuid:e25589c4-7c15-4b10-8d86-61090537dbaf
Page Count                      : 51
Keywords                        : Compal, LA-9531P, -, Schematics., www.s-manuals.com.
Warning                         : [Minor] Ignored duplicate Info dictionary

EXIF Metadata provided by EXIF.tools