Compal LA 9868P Schematics. Www.s Manuals.com. R1.0 Schematics

User Manual: Motherboard Compal LA-9868P VNKAE Rosetta 10AN/10ANG - Schematics. Free.

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A

B

C

D

E

1

1

VNKAE
Rosetta 10AN/10ANG

2

2

LA-9868P REV 1.0 Schematic
AMD KABINI Quad Core 25W only for UMA
AMD KABINI Quad Core 15W for DIS&UMA
2013-03-18 Rev 1.0

3

3

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Issued Date

Deciphered Date

2015/09/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Cover Page
Document Number

Rev
1.0

LA-9868P
Sheet

Thursday, May 16, 2013
E

1

of

42

A

1

B

AMD GPU
AMD Sun Pro M2, 64bit with 1GB DDR3(2Gbit)
AMD Sun Pro M2, 64bit with 2GB DDR3(4Gbit)

C

D

Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2

PCIe Gen2 X4

Single Channel

5Gbps

page 12-19

USB 2.0 Left

Jaguar Core

DP0 X4

USB port 0
page 25
page 20

Integrated Yangtze FCH
USB 2.0

USB Right1

5V 480Mbps

HDMI Conn
(1.4b & 3D)

BANK 0, 1, 2, 3

page 10,11

TouchScreen

Cardreader

1

1.5V DDRIII 1333/1600 MT/s
APU SMBUS

AMD FT3 APU

LVDS/eDP Conn

E

USB2.0 port 8
page 24

USB port 4
page 20

USB Right2

USB port 2
page 28

PCIeMini Card
For BT

Int. Camera

USB2.0 port 9
page 24

USB port 1
page 23

USB port 3
page 20

DP1 X4

BGA 769-balls

page 21

USB Right1
USB3.0 port 0
page 24

USB 3.0

2

5V 5Gbps

CRT Conn

USB Right2
USB3.0 port 1
page 24

2

DAC

page 22

SATA port 0
5V 6Gbps

SATA HDD
SATA port 0
page 23

PCIe Gen1 X1
APU SMBUS

PCIeMini Card For WLAN

2.5bps

PCIe port 2
page 23

SATA port 1
5V 6Gbps

SATA ODD
SATA port 1
page 23

SPK Conn
page 27

PCIe Gen1 X1

RTL8106E 10/100M

2.5bps

PCIe port 1
page 25

HD Audio

HDA Codec

3.3V 24MHz

JPIO
(HP & MIC)

ALC259

page 27

page 26

3

3

page 5-9

SPI BUS
3.3V 33HZ

LPC Bus
3.3V 33 MHz

SPI ROM
(4MB) page

APU SMBus

ENE KB9012

7

Touch Screen Control/B

page 29

EC SMBus

page 20

DC/DC Interface CKT.
4

Touch Pad

page 31

page 30

Power Circuit DC/DC

USB2.0&LAN/B

page 32~41

page 25

Int.KBD

page 30

page 30

page 25

RTC CKT.

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Issued Date

Power On/Off CKT & Power/B

G-Sensor

Deciphered Date

2015/09/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

page 9

Date:

A

B

C

D

Block Diagram
Document Number

Rev
1.0

LA-9868P
Sheet

Thursday, May 16, 2013
E

2

of

42

5

4

3

DESIGN CURRENT 0.15A
DESIGN CURRENT 0A

2

1

+3VL
+5VL

B+
Ipeak=12A, Imax=8.4A, Iocp min=14A

+5VALW

D

D

SUSP#
DESIGN CURRENT 4A

N-CHANNEL
TPS22966

+5VS

ODD_PWR

N-CHANNEL

DESIGN CURRENT 2A

+5VS_ODD

TPS22966

RT8243A
Ipeak=8A, Imax=5.6A, Iocp min=10A

+3VALW
3VALW_APU_PWREN

P-CHANNEL
AO-3413

DESIGN CURRENT 330mA

+3V_LAN

1.8_0.95VALW_PWREN
DESIGN CURRENT 2.5A

SY8032
C

+3VALW_APU

+1.8VALW

SUSP#

C

N-CHANNEL

+1.8VS

TPS22966
VGA_PWRGD

N-CHANNEL

+1.8VGS

TPS22966
SUSP#
DESIGN CURRENT 4A

N-CHANNEL

+3VS

LCD_ENVDD

TPS22966

P-CHANNEL
AO-3413

DESIGN CURRENT 1.5A

+LCD_VDD

DESIGN CURRENT 60mA

+3VS_DGPU

DGPU_PWR_EN

P-CHANNEL
AO-3413

DESIGN CURRENT 2A

+3V_WLAN

SYSON

B

B

Ipeak=12A, Imax=8.4A, Iocp min=13.8A

RT8207M

+1.5V

VGA_PWRGD

N-CHANNEL

DESIGN CURRENT 2A

+1.5VGS

DESIGN CURRENT 1.5A

+0.75VS

TPS22966
SUSP#
1.8_0.95VALW_PWREN

+0.95VALW

Ipeak=2.5A, Imax=1.75A, Iocp min=16A

SY8208D

0.95VS_PWREN#

N-CHANNEL

DESIGN CURRENT 2A

+0.95VS

FDS6676

VR_ON

RT8880A

A

Ipeak=15A, Imax=10.5A, Iocp min=30A

APU_CORE

Ipeak=13A, Imax=9.1A, Iocp min=30A

APU_CORE_NB

Ipeak=21A, Imax=14.7A, Iocp min=40A

VGA_CORE

A

GPU_DPRSLPVR

ISL62881
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Deciphered Date

2015/09/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Power Tree
Size

4

3

2

Rev
1.0

LA-9868P
Date:

5

Document Number
Thursday, May 16, 2013

Sheet
1

3

of

42

A

Voltage Rails

B

( O MEANS ON

+RTCVCC

B+

+5VL
+3VL

D

E

UMA

X MEANS OFF )

+5VALW

+1.5V

+3VALW

BTO Option Table

+5VS
+3VS

Function

+0.95VS

+1.8VALW

power
plane

1

C

+1.8VS

+0.95VALW

description

+1.5VS

+VSB

1

explain

+0.75VS
+APU_CORE

BTO

+APU_CORE_NB
SIGNAL

STATE
State

HIGH

HIGH

S1(Power On Suspend)

HIGH

HIGH

S3 (Suspend to RAM)

LOW

HIGH

S4 (Suspend to Disk)

LOW

HIGH

S0

O

O

O

O

O

O

S5 (Soft OFF)

LOW

LOW

S1

O

O

O

O

O

O

G3

LOW

LOW

S3

O

O

O

O

O

X

S5 S4/AC

O

O

O

O

X

X

S5 S4/ Battery only

O

O

O

X

X

X

S5 S4/AC & Battery
don't exist

O

X

X

X

X

X

2

APU SM Bus Address (SCL0/SDA0)
3

SLP_S3# SLP_S5#

Full ON

Power
Device
+3VS
DDR SO-DIMM A
+3VS
DDR SO-DIMM B
+3VS
WLAN

2

APU POWER SEQUENCE

HEX Address
A0H 1010 0000 b
A2H 1010 0010 b

+RTC

G-A

3

3VALW_APU_PWREN
+3VALW_APU

G-B

1.8_0.95VALW_PWREN
+1.8VALW
+0.95VALW
SYSON

EC SM Bus1 Address
Device
Power
HEX
+3VL
Smart Battery 16H
+3VL
Charger
12H

EC SM Bus2 Address

Device
Address
Power
G-Sensor
0001 0110 b +3VS
VGA thermal
0001 0010 b +3VS
+3VS
APU thermal

HEX
40H
82H
98H

+1.5V

G-C

SUSP#
+3VS

G-D

Address
0100 0000 b
1000 0010 b
1001 1000 b

+1.8VS
+1.5VS
+0.95VS
VR_ON
+APU_CORE

G-E

+APU_CORE_NB

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Issued Date

Deciphered Date

2015/09/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Notes List
Rev
1.0

LA-9868P

Date:

A

B

C

D

Sheet

Thursday, May 16, 2013
E

4

of

42

5

4

3

2

1

<10,11> DDR_AB_DQS[0..7]
<10,11> DDR_AB_DQS#[0..7]

DDR_AB_D[0..63]
MEMORY

AJ38
AG35
N34

M_DATA0

M_ADD1

M_DATA1

M_ADD2

M_DATA2

M_ADD3

M_DATA3

M_ADD4

M_DATA4

M_ADD5

M_DATA5

M_ADD6

M_DATA6

M_ADD7

M_DATA7

M_ADD9

M_DATA8

M_ADD10

M_DATA9

M_ADD11

M_DATA10

M_ADD12

M_DATA11

M_ADD13

M_DATA12

M_ADD14

M_DATA13

M_ADD15

M_DATA14

B32
B38
G40
N41
AG40
AN41
AY40
AY34
Y40

DDR_AB_DQS0
DDR_AB_DQS#0
DDR_AB_DQS1
DDR_AB_DQS#1
DDR_AB_DQS2
DDR_AB_DQS#2
DDR_AB_DQS3
DDR_AB_DQS#3
DDR_AB_DQS4
DDR_AB_DQS#4
DDR_AB_DQS5
DDR_AB_DQS#5
DDR_AB_DQS6
DDR_AB_DQS#6
DDR_AB_DQS7
DDR_AB_DQS#7

B33
A33
B40
A40
H41
H40
P41
P40
AH41
AH40
AP41
AP40
BA40
AY41
AY33
BA34
AA40
Y41

M_BANK1

M_DATA16

M_BANK2

M_DATA17

DDR_A_CLK0
DDR_A_CLK0#
DDR_A_CLK1
DDR_A_CLK1#
DDR_B_CLK0
DDR_B_CLK0#
DDR_B_CLK1
DDR_B_CLK1#

AC35
AC34
AA34
AA32
AE38
AE37
AA37
AA38

M_DM0

M_DATA19

M_DM1

M_DATA20

M_DM2

M_DATA21

M_DM3

M_DATA22

M_DM4

M_DATA23

M_DM6

M_DATA24

M_DM7

M_DATA25

M_DM8

M_DATA26

DDR_A_CLK0
DDR_A_CLK0#
DDR_A_CLK1
DDR_A_CLK1#
DDR_B_CLK0
DDR_B_CLK0#
DDR_B_CLK1
DDR_B_CLK1#

<10>
<10>
<11>
<11>

DDR_A_ODT0
DDR_A_ODT1
DDR_B_ODT0
DDR_B_ODT1

<10>
<10>
<11>
<11>

DDR_A_SCS0#
DDR_A_SCS1#
DDR_B_SCS0#
DDR_B_SCS1#

M_DATA30

M_DQS_L1
M_DQS_H2
M_DQS_L2
M_DQS_H3
M_DQS_L3
M_DQS_H4
M_DQS_L4
M_DQS_H5
M_DQS_L5
M_DQS_H6
M_DQS_L6
M_DQS_H7
M_DQS_L7
M_DQS_H8
M_DQS_L8
M_CLK_H0

M_DATA31
M_DATA32
M_DATA33
M_DATA34
M_DATA35
M_DATA36
M_DATA37
M_DATA38
M_DATA39

L34
J38
J37
J34

DDR_A_ODT0
DDR_A_ODT1
DDR_B_ODT0
DDR_B_ODT1

AN38
AU38
AN37
AR37

DDR_A_SCS0#
DDR_A_SCS1#
DDR_B_SCS0#
DDR_B_SCS1#

AJ34
AR38
AL38
AN35

M_DATA41
M_DATA42
M_DATA43
M_DATA44
M_DATA45

M_CLK_L0

M_DATA46

M_CLK_H1

DDR_AB_RAS#
DDR_AB_CAS#
DDR_AB_WE#

AJ37
AL34
AL35

+MEM_VREF

AD40
AC38

M41
N40
T41
U40
L40
M40
R40
T40

DDR_AB_D24
DDR_AB_D25
DDR_AB_D26
DDR_AB_D27
DDR_AB_D28
DDR_AB_D29
DDR_AB_D30
DDR_AB_D31

R10
R8
<25> PCIE_LANTX_ARX_P1
<25> PCIE_LANTX_ARX_N1

LAN

<23> PCIE_WLANTX_ARX_P2
<23> PCIE_WLANTX_ARX_N2

WLAN

+0.95VS_APU_GFX

AF40
AF41
AK40
AK41
AE40
AE41
AJ40
AJ41

DDR_AB_D32
DDR_AB_D33
DDR_AB_D34
DDR_AB_D35
DDR_AB_D36
DDR_AB_D37
DDR_AB_D38
DDR_AB_D39

1
RC1

P_GPP_RXP0

P_GPP_TXP0

P_GPP_RXN0

P_GPP_TXN0

R5
R4

P_GPP_RXP1

P_GPP_TXP1

P_GPP_RXN1

P_GPP_TXN1

N5
N4

P_GPP_RXP2

N10
N8

P_GPP_RXP3

2 P_TX_ZVDD W 8
1.69K_0402_1%
L5
L4

<12> PCIE_GTX_C_ARX_P0
<12> PCIE_GTX_C_ARX_N0
<12> PCIE_GTX_C_ARX_P1
<12> PCIE_GTX_C_ARX_N1

VGA<12>

PCIE_GTX_C_ARX_P2
<12> PCIE_GTX_C_ARX_N2

P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3

P_GPP_RXN3

P_GFX_RXP0
P_GFX_RXN0
P_GFX_RXP1

G5
G4

P_GFX_RXP2

M_DATA47

P_GFX_TXP0

P_GFX_RXN1

P_GFX_RXN2
P_GFX_RXP3
P_GFX_RXN3

P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3

M_CLK_H2

M_DATA48

M_CLK_L2

M_DATA49

M_CLK_H3

M_DATA50

M_CLK_L3

M_DATA51

M_RESET_L

M_DATA53

M_EVENT_L

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

J2 PCIE_ATX_WLANRX_P2 CC11
J1 PCIE_ATX_WLANRX_N2 CC21

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

P_RX_ZVDD

2
RC2

M_DATA54

M0_CKE1

M_DATA56

M1_CKE0

M_DATA57

M1_CKE1

M_DATA58

M0_ODT0

M_DATA60

M0_ODT1

M_DATA61

M1_ODT0

M_DATA62
M_DATA63

M1_ODT1
M0_CS_L0

M_CHECK0

M0_CS_L1

M_CHECK1

M1_CS_L0

M_CHECK2

M1_CS_L1

M_CHECK3

M_RAS_L

M_CHECK5

M_CAS_L

M_CHECK6

M_WE_L

M_CHECK7

1
1K_0402_1%

+0.95VS_APU_GFX

1
1

2 VGA@
2 VGA@

0.1U_0402_16V7K
0.1U_0402_16V7K

F2 PCIE_ATX_GRX_P1 CC7
F1 PCIE_ATX_GRX_N1 CC8

1
1

2 VGA@
2 VGA@

0.1U_0402_16V7K
0.1U_0402_16V7K

E2 PCIE_ATX_GRX_P2 CC9 1
E1 PCIE_ATX_GRX_N2 CC10 1

2 VGA@
2 VGA@

0.1U_0402_16V7K
0.1U_0402_16V7K

D2 PCIE_ATX_GRX_P3 CC11 1
D1 PCIE_ATX_GRX_N3 CC12 1

2 VGA@
2 VGA@

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_ATX_C_GRX_P0 <12>
PCIE_ATX_C_GRX_N0 <12>
PCIE_ATX_C_GRX_P1 <12>
PCIE_ATX_C_GRX_N1 <12>

VGA

PCIE_ATX_C_GRX_P2 <12>
PCIE_ATX_C_GRX_N2 <12>

C

PCIE_ATX_C_GRX_P3 <12>
PCIE_ATX_C_GRX_N3 <12>

FT3 REV 0.51

@

AV41 DDR_AB_D48
AW 40DDR_AB_D49
BA38 DDR_AB_D50
AY37 DDR_AB_D51
AU41 DDR_AB_D52
AV40 DDR_AB_D53
AY39 DDR_AB_D54
AY38 DDR_AB_D55
BA36 DDR_AB_D56
AY35 DDR_AB_D57
BA32 DDR_AB_D58
AY31 DDR_AB_D59
BA37 DDR_AB_D60
AY36 DDR_AB_D61
BA33 DDR_AB_D62
AY32 DDR_AB_D63

B

V41
W 40
AB40
AC40
U41
V40
AA41
AB41

FAN Control Circuit

+5VS

+3VS

1A

1

@

2
+FAN1
0_0603_5%

JFAN

R1
10K_0402_5%

6
5
4
3
2
1

M_VREF
M_ZVDDIO_MEM_S

M_VREFDQ

FT3_BGA769

AD41

M_ZVDDIO 1
39.2_0402_1%

2
RC4

+1.5V

<29> FANPWM
<29> FAN_SPEED1

@

MEMORY Reference Voltage (Cap follower checklist 1.02)

1

+FAN1
C1
0.01U_0402_25V7K
@

1

2

1
C3

D1

+1.5V

BAS16_SOT23-3

15mil
RC7

1

2 1K_0402_5%

2
10U_0603_6.3V6M

A

MEM_MAB_EVENT#

2

+MEM_VREF

@

GND
GND
4
3
2
1

ACES_50273-0040N-001

EVENT# pull high

RC6
1K_0402_1%

1

WLAN

G2 PCIE_ATX_GRX_P0 CC5
G1 PCIE_ATX_GRX_N0 CC6

2

A

LAN

PCIE_ATX_C_WLANRX_P2 <23>
PCIE_ATX_C_WLANRX_N2 <23>

H2
H1

close to APU
+1.5V

PCIE_ATX_C_LANRX_P1 <25>
PCIE_ATX_C_LANRX_N1 <25>

M0_CKE0

FT3 REV 0.51

remove from CRB_ver0C
Check List 1.02

CC31
CC41

AM41 DDR_AB_D40
AN40 DDR_AB_D41
AT41 DDR_AB_D42
AU40 DDR_AB_D43
AL40 DDR_AB_D44
AM40 DDR_AB_D45
AR40 DDR_AB_D46
AT40 DDR_AB_D47

R2

2 ESD@
MEM_MAB_RST#
180P_0402_50V8J

K2 PCIE_ATX_LANRX_P1
K1 PCIE_ATX_LANRX_N1

P_RX_ZVDD_095 W7

P_TX_ZVDD_095

J5
J4

D7
E7

<12> PCIE_GTX_C_ARX_P3
<12> PCIE_GTX_C_ARX_N3

P_GPP_RXN2

L2
L1

M_CLK_L1

M_CHECK4

<10,11> DDR_AB_RAS#
<10,11> DDR_AB_CAS#
<10,11> DDR_AB_WE#

DDR_AB_D16
DDR_AB_D17
DDR_AB_D18
DDR_AB_D19
DDR_AB_D20
DDR_AB_D21
DDR_AB_D22
DDR_AB_D23

PCIE

FT3_BGA769
M_DATA40

M_DATA59

B

1
CC94

M_DATA29

M_DQS_H1

M_DATA55

DDR_A_CKE0
DDR_A_CKE1
DDR_B_CKE0
DDR_B_CKE1

F40
F41
K40
K41
E40
E41
J40
J41

D

UC1B

2

DDR_A_CKE0
DDR_A_CKE1
DDR_B_CKE0
DDR_B_CKE1

M_DQS_L0

M_DATA52

G38
MEM_MAB_RST#
MEM_MAB_EVENT# AE34

<10,11> MEM_MAB_RST#
<10,11> MEM_MAB_EVENT#
<10>
<10>
<11>
<11>

M_DATA28

M_DQS_H0

MEMORY

<10>
<10>
<10>
<10>
<11>
<11>
<11>
<11>

DDR_AB_D8
DDR_AB_D9
DDR_AB_D10
DDR_AB_D11
DDR_AB_D12
DDR_AB_D13
DDR_AB_D14
DDR_AB_D15

M_DM5

M_DATA27

C

B37
A38
D40
D41
B36
A37
B41
C40

M_BANK0

M_DATA18

DDR_AB_DM0
DDR_AB_DM1
DDR_AB_DM2
DDR_AB_DM3
DDR_AB_DM4
DDR_AB_DM5
DDR_AB_DM6
DDR_AB_DM7

DDR_AB_D0
DDR_AB_D1
DDR_AB_D2
DDR_AB_D3
DDR_AB_D4
DDR_AB_D5
DDR_AB_D6
DDR_AB_D7

M_ADD8

M_DATA15

DDR_AB_BS0
DDR_AB_BS1
DDR_AB_BS2
DDR_AB_DM[0..7]

B30
A32
B35
A36
B29
A30
A34
B34

2

DDR_AB_BS0
DDR_AB_BS1
DDR_AB_BS2

M_ADD0

1

AG38
W 35
W 38
W 34
U38
U37
U34
R35
R38
N38
AG34
R34
N37
AN34
L38
L35

GPP

DDR_AB_MA0
DDR_AB_MA1
DDR_AB_MA2
DDR_AB_MA3
DDR_AB_MA4
DDR_AB_MA5
DDR_AB_MA6
DDR_AB_MA7
DDR_AB_MA8
DDR_AB_MA9
DDR_AB_MA10
DDR_AB_MA11
DDR_AB_MA12
DDR_AB_MA13
DDR_AB_MA14
DDR_AB_MA15

GRAPHICS

D

<10,11>
<10,11>
<10,11>
<10,11>

<10,11>

UC1A

<10,11> DDR_AB_MA[0..15]

2

2

RC8
1K_0402_1%

1

CC18

Compal Secret Data

Security Classification

0.1U_0402_16V7K

2012/09/27

Issued Date

1

1

CC17
1U_0402_6.3V6K

2015/09/27

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Close to APU AD40

Date:

5

4

3

2

FT3 DISP/MISC/HDT
Document Number

Rev
1.0

LA-9868P
Thursday, May 16, 2013

Sheet
1

5

of

42

5

4

3

2 0.1U_0402_16V7K
EDP_LCD_TXOUT0+_R 1
CC109 EDP@
2 0.1U_0402_16V7K
EDP_LCD_TXOUT0-_R 1
CC110 EDP@

2

1

EDP_LCD_TXOUT2+
EDP_LCD_TXOUT2+3VS

LCD_ENBKL : APU to EC to LCD
LVDS_CLK&LVDS_DATA layout follow EDP AUX route 85 ohm

UC1C
DISPLAY/SVI2/JTAG/TEST

A9
B9

<21> APU_HDMI_TX2+
<21> APU_HDMI_TX2-

A10
B10

<21> APU_HDMI_TX1+
<21> APU_HDMI_TX1-

A11
B11

<21> APU_HDMI_TX0+
<21> APU_HDMI_TX0-

EDP/LVDS
CC108
CC107
EDP@
EDP@
0.1U_0402_16V7K 0.1U_0402_16V7K

DP_2K_ZVSS

TDP1_TXP1

DP_DIGON
DP_VARY_BL

TDP1_TXN1

<20> EDP_LCD_TXOUT2+_R
<20> EDP_LCD_TXOUT2-_R

RC75
RC76

1 LVDS@ 2 0_0402_5%
1 LVDS@ 2 0_0402_5%

EDP_LCD_TXOUT2+ A4
EDP_LCD_TXOUT2- B4

<20> EDP_LCD_TXOUT1+_R
<20> EDP_LCD_TXOUT1-_R

CC107
CC108

1 LVDS@ 2 0_0402_5%
1 LVDS@ 2 0_0402_5%

EDP_LCD_TXOUT1+ A5
EDP_LCD_TXOUT1- B5

<20> EDP_LCD_TXOUT0+_R
<20> EDP_LCD_TXOUT0-_R

RC77
RC78

1 LVDS@ 2 0_0402_5%
1 LVDS@ 2 0_0402_5%

EDP_LCD_TXOUT0+ A6
EDP_LCD_TXOUT0- B6
LCD_TXCLK+
LCD_TXCLK-

<20> LCD_TXCLK+
<20> LCD_TXCLK-

A7
B7

TDP1_AUXP

TDP1_TXN2
TDP1_TXP3
TDP1_TXN3
LTDP0_TXP0
LTDP0_TXN0
LTDP0_TXP1
LTDP0_TXN1

TDP1_HPD
LTDP0_AUXP
LTDP0_AUXN
LTDP0_HPD

K15
H15

C

+3VS

B22
B21

<13,25,29> EC_SMB_CK2
<13,25,29> EC_SMB_DA2
RC26 2

1 1K_0402_5%

APU_PROCHOT#

+1.8VS
<38> APU_PWRGD
RC32

1

2 300_0402_5%

APU_RST#

RC34

1

2 300_0402_5%

APU_PWRGD

APU_RST#

B20
A20

APU_PWRGD

B19
A19

APU_PROCHOT#
APU_ALERT#

A22
B18

LTDP0_TXP3

DAC_BLUE

B15 APU_CRT_B

DAC_VSYNC

DISP_CLKIN_H

DAC_SDA
DAC_ZVSS
THERMDA

SIC
SID
APU_RST_L
LDT_RST_L
APU_PWROK

THERMDC
DIECRACKMON
BP0
BP1
BP2
BP3
PLLTEST1

LDT_PWROK
PROCHOT_L

BYPASSCLK_H

ALERT_L

BYPASSCLK_L

RPC2

APU_TDI
APU_TCK
APU_TMS
APU_TRST#

1
APU_DBREQ#
1K_0402_5%

T15

<38> APU_VDD_SEN_L
T18
T19

B

TDO
TCK

M_TEST

TMS
TRST_L
DBRDY
DBREQ_L

FREE_2

1
2 ESD@
APU_RST#
CC99 1000P_0402_50V7K
1
2 ESD@
APU_PWRGD
CC93 180P_0402_50V8J

D23
G23
VDDMEM_SENSE E25
E23
VDD095_FB_H AV33
VDD095_FB_L AU33

VDDCR_NB_SENSE

USB_ATEST1

VDDCR_CPU_SENSE

M_ANALOGIN
M_ANALOGOUT

VDDIO_MEM_S_SENSE
VSS_SENSE
VDD_095_FB_H
VDD_095_FB_L

TMON_CAL

2 499_0402_1%

TEST4
TEST5

T1
T2

TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST31

T3
T4
T5
T6
T34
T35

HDMI_EN/DP_STEREOSYNCE21

TEST36
TEST37
TEST42
TEST43
TEST39
TEST40
TEST41

1 4.7K_0402_5%

APU_CRT_HSYNC

RC18 1

EDP_LVDS_HPD

RC45 2

2 1K_0402_5%
@

1 100K_0402_5%

EDP_LVDS_HPD

RC44 2

EDP@ 1 100K_0402_5%

LCD_ENBKL

RC19 2

1 100K_0402_5%

LCD_INT_PWM

RC20 2

1 100K_0402_5%

APU_CRT_R

RC22 1

2 150_0402_1%

APU_CRT_G

RC24 1

2 150_0402_1%

APU_CRT_B

RC27 1

2 150_0402_1%

APU_CRT_HSYNC

RC30 1

@

C

2 1K_0402_5%

route TEST25_H/L AND TEST28_H/L differentially
T7
T8
T9

A29

AJ10
AJ8
R32
N32
AP29

<22>
<22>

APU_CRT_CLK <22>
APU_CRT_DATA <22>

A16 DAC_ZVSS RC21 1

GIO_TSTDTM0_CLKINIT H25

1 4.7K_0402_5%

RC12 2

CRT
APU_CRT_HSYNC
APU_CRT_VSYNC

D19 APU_CRT_CLK
D21 APU_CRT_DATA

GIO_TSTDTM0_SERIALCLKH21

USB_ATEST0

<38> APU_VDDNB_SEN_H
<38> APU_VDD_SEN_H

1K_8P4R_5%

2
RC28

T32
T37

PLLCHRZ_L

TDI

MISC

8
7
6
5

1
2
3
4

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

RC17 2

APU_CRT_CLK

CC101
CC103
EDP@
EDP@
0.1U_0402_16V7K 0.1U_0402_16V7K

APU_CRT_B <22>

G19 APU_CRT_HSYNC
E19

H27
H29
D25
A27
B27
A26
B26
B28
A28
B24
A24
AV35
AU35
E33

APU_CRT_DATA

EDP/LVDS
EDP Cap co-lay

APU_CRT_G <22>

SVC
SVD

EDP_LVDS_CLK <20>
EDP_LVDS_DATA <20>

APU_CRT_R <22>

DISP_CLKIN_L
SVT

HDMI

EDP_LVDS_HPD <20>

LTDP0_TXN3

TEST

T28

+1.8VS

H17 EDP_LVDS_HPD

D

EDP_LVDS_DATA_R RC15 1 LVDS@ 2 4.7K_0402_5%

HDMI DDC PU RES move
to HDMI page

APU_HDMI_CLK <21>
APU_HDMI_DATA <21>

D15 EDP_LVDS_CLK_R CC1011 LVDS@ 2 0_0402_5%
E15 EDP_LVDS_DATA_RCC1031 LVDS@ 2 0_0402_5%

A14 APU_CRT_G

PLLCHRZ_H

D29
D31
D35
D33
G27
B25
A25

EDP/LVDS

HDMI_HPD <21,8>

B14 APU_CRT_R

PLLTEST0

<29,38> APU_PROCHOT#

EDP_LVDS_CLK_R RC14 1 LVDS@ 2 4.7K_0402_5%
LCD_ENBKL <20,29>
LCD_ENVDD <20>
LCD_INT_PWM <20>

H19

DAC_RED

MISC

<38> APU_SVT
<38> APU_SVC
<38> APU_SVD

2 150_0402_1%
2 2K_0402_1%

D17 APU_HDMI_CLK
E17 APU_HDMI_DATA

DAC_GREEN

DAC_SCL

G31
D27
E29

DP_150_ZVSS RC13 1
DP_2K_ZVSS RC9 1
LCD_ENBKL
LCD_ENVDD
LCD_INT_PWM

LTDP0_TXN2

LTDP0_TXP2

DAC_HSYNC

SVT,SVC,SVD, APU_PWRGD is 1.8V Output
PROCHOT is 3.3V Input

B16
A21
B17
A17
A18

TDP1_TXP2
TDP1_AUXN

A12
B12

<21> APU_HDMI_CLK+
<21> APU_HDMI_CLK-

EDP use 2 Lane for FHD
EDP Cap co-lay

DP_150_ZVSS

TDP1_TXN0

DISPLAY

HDMI

TDP1_TXP0

DP_BLON

D

+1.8VS

NOTE: DP_STEREOSYNC & APU_HSYNC PU FOR
INTERNAL(HDMI enable), DP_STEREOSYNC &
APU_HSYNC PD FOR CUSTOMER(HDMI disable)

T12
T13
T14
T16
T17

TEST25_L
TEST36
TEST37

RC35 1
RC37 1
RC39 1

@
@

DP_STEREOSYNC

RC36 1

@

TEST36
TEST37

RC41 1
RC46 1

@
@

TEST25_H

RC43 1

2 510_0402_1%
2 1K_0402_5%
2 1K_0402_5%
2 1K_0402_5%
2 1K_0402_5%
2 1K_0402_5%
2 510_0402_1%

DP_STEREOSYNC

DP_STEREOSYNC
Used to align shutter glasses with the interleaved video frame

+3VS

B

RPC4

FT3 REV 0.51

FT3_BGA769

APU_ALERT#
DP_STEREOSYNC
TEST19
TEST18

@

1
2
3
4

8
7
6
5

close to APU

+1.8VS

1K_8P4R_5%

DC1

2
@ESD@
SCV00001K00

1 APU_PROCHOT#

close to APU

A

A

Compal Secret Data

Security Classification
2012/09/27

Issued Date

2015/09/27

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

FT3 DISP/MISC/HDT
Document Number

Rev
1.0

LA-9868P
Thursday, May 16, 2013

Sheet
1

6

of

42

5

4

3

2

1

UC1E
CLK/SATA/USB/SPI/LPC

SATA ODD

USB_ZVSS

SATA_RX0N

AY19
BA19

SATA_TX1P

AY17
BA17

SATA_RX1N

1 1K_0402_1%SATA_ZVSS
AR19
1 1K_0402_1%SATA_ZVSS_095 AP19

SATA_ZVSS

USB_HSD0P

SATA_RX0P

USB_HSD0N

<23> SATA_ATX_DRX_P1
<23> SATA_ATX_DRX_N1

USB_HSD1P

SATA_TX1N

USB_HSD1N

<23> SATA_DTX_C_ARX_N1
<23> SATA_DTX_C_ARX_P1
+0.95VS

SATA_TX0N

BA16
AY16

<23> SATA_DTX_C_ARX_N0
<23> SATA_DTX_C_ARX_P0

D

W4
USBCLK/14M_25M_48M_OSC

SATA_TX0P

RC58 2
RC59 2

T20

SATA_ACT

SATA_RX1P

SATA_ZVDD_095

BA30

SATA_ACT_L/GPIO67

AY12

SATA_X1

SATA

SATA HDD

BA14
AY14

<23> SATA_ATX_DRX_P0
<23> SATA_ATX_DRX_N0

USB_HSD2P
USB_HSD2N
USB_HSD3P
USB_HSD3N
USB_HSD4P
USB_HSD4N
USB_HSD5P

BA12

LAN
WLAN

<12> CLK_PCIE_VGA
<12> CLK_PCIE_VGA#

<25> CLK_LAN
<25> CLK_LAN#
<23> CLK_WLAN
<23> CLK_WLAN#

SATA_X2

GFX_CLKP

USB_HSD6P
USB_HSD6N
USB_HSD7P

GFX_CLKN

USB_HSD7N

AC8
AC10

GPP_CLK0P

USB_HSD8P

GPP_CLK0N

USB_HSD8N

AE4
AE5

GPP_CLK1P

USB_HSD9P

GPP_CLK1N

USB_HSD9N

AC4
AC5

GPP_CLK2P

AA5
AA4

GPP_CLK3P

USB_SS_0TXP

GPP_CLK3N

USB_SS_0TXN

X14M_25M_48M_OSC

USB_SS_0RXP

CLK

VGA

U4
U5

USB

USB_HSD5N

GPP_CLK2N

USB_SS_ZVSS

AG4 USB_ZVSS

RC57 1

2 11.8K_0402_1%

AL4
AL5

USB20_P1 <23>
USB20_N1 <23>

AG7
AG8

USB20_P2 <28>
USB20_N2 <28>

AG1
AG2

USB20_P3 <20>
USB20_N3 <20>

AF1
AF2

USB20_P4 <20>
USB20_N4 <20>

AD1
AD2
AC1
AC2
AB1
AB2
AA1
AA2
AE10

AE8
USB_SS_ZVDD_095_USB3_DUAL

RC60 1
RC61 1

USBSS_ZVSS
USBSS_ZVDD

T2
T1

EC

RC62 1
RC63 1

EMI@
@EMI@

<29> LPC_AD0
<29> LPC_AD1
<29> LPC_AD2
<29> LPC_AD3
<29,8> LPC_FRAME#
<29> SERIRQ

2 22_0402_5%LPC_CLK0 AY2
2 0_0402_5% LPC_CLK1 AW 2

AT2
AT1
AR2
AR1
AP2
AP1
AV29
AP25
AV2

USB3.0-Right1

USB30_RX0P <24>
USB30_RX0N <24>

R1
R2

USB30_TX1P <24>
USB30_TX1N <24>

W1
USB_SS_1RXN W 2
USB_SS_1RXP

X48M_X2

USB30_RX1P <24>
USB30_RX1N <24>

C

USB3.0-Right2

LPCCLK0
SPI_CLK/GPIO162

LPCCLK1
LAD0
LAD1
LAD2
LAD3

SPI

<29,8> CLK_PCI_EC
<8> CLK_PCI_DDR

N1

LPC

48M_X2

+0.95VALW
USB30_TX0P <24>
USB30_TX0N <24>

X48M_X1
USB_SS_1TXN

USB2.0-Right2

2 1K_0402_1%
2 1K_0402_1%

V2
USB_SS_0RXN V1
USB_SS_1TXP

USB2.0-Right1

USB20_P9 <24>
USB20_N9 <24>

SPI_CS2_L/GPIO166 AR4
SPI_DO/GPIO163
SPI_DI/GPIO164

AR11
AR7

APU_SPI_CLK
APU_SPI_CS1#
APU_SPI_CS2#
APU_SPI_MOSI
APU_SPI_MISO

1
RC130
T21

APU_SPI_WP#

T22

@

2
0_0402_5%

APU_SPI_CLK_R

RC10
10_0402_5%
@EMI@

SPI_HOLD_L/GEVENT9_LAU11
SPI_WP_L/GPIO161

LFRAME_L

AU7

SPI_CS1_L/GPIO165 AW 9

1

N2

USB20_P8 <24>
USB20_N8 <24>

AU9

2

48M_X1

D

Touch Screen

AE1
AE2

C

AP13

USB2.0-Left1 (Debug Port)
WLAN (BT)
Cardreader
Int. Camera

USB20_P0 <24>
USB20_N0 <24>

AJ4
AJ5

LDRQ0_L

CC13
10P_0402_50V8J
@EMI@

SERIRQ/GPIO48
LPC_CLKRUN_L
LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L

2

1

FT3 REV 0.51

FT3_BGA769

@

B

B

48KMHz CRYSTAL
48M_X2

SPI ROM
48M_X1
RC64

2

2

1

RC1011
RC1021
RC1211
RC1241

<29> EC_SPIDO
<29> EC_SPIDI
<29> EC_SPICLK
<29> EC_SPICS#

1M_0402_5%

1

885@
885@
885@
885@

2
2
2
2

33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%

4M Byte
UC5

3

1

2

3

4

5

APU_SPI_CLK_R

6

4
RC66 1

YC1
48MHZ_8PF_X3S048000D81H-W
1
CC22
4.7P_0402_50V8J

APU_SPI_MOSI

2

2 10K_0402_5%

1

APU_SPI_CS1#

7

+3VALW_APU

3

CC23
4.7P_0402_50V8J

Socket: SP07000F500/SP07000H900
Please place UC5 close to UC1 APU,

8
2

4MB ROM P/N:
SA00004LI00

A

1

SI

SO

2

APU_SPI_MISO

SCLK
CS
HOLD
WP
VCC

GND

4

MX25L3205DM2I-12G SO8
CC25
0.1U_0402_16V4Z

A

SW said ROM can change to 4MB
Compal Secret Data

Security Classification
2012/09/27

Issued Date

2015/09/27

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

FT3-SATA/CLK/USB/SPI/LPC
Document Number

Rev
1.0

LA-9868P
Thursday, May 16, 2013

Sheet
1

7

of

42

4

<25> APU_PCIE_WAKE#

SLP_S3#
SLP_S5#

<29> SLP_S3#
<29> SLP_S5#
T25

TEST1/TMS

TEST0/2
<29>
<29>
<29>
<29>

SYS_PWRGD

AU13
AY10
AY6
AR23
AR31
AN5
AL7

KB_RST#
GATEA20
EC_SCI#
EC_SMI#

PWR_GOOD
SYS_RESET_L/GEVENT19_L
WAKE_L/GEVENT8_L
SLP_S3_L
SLP_S5_L
TEST0
TEST1/TMS
TEST2

SD_WP/GPIO76

SLP_S3#, SLP_S5# PU reserve

BA22
AY21
AY24
SD_DATA3/GPIO80 BA24
SD_LED/GPIO45
SCL0/GPIO43

AU25
AV25

APU_SCLK0
APU_SDATA0

AY11
BA11

APU_SCLK1
APU_SDATA1

KBRST_L

SCL1/GPIO227

GA20IN/GEVENT0_L

SDA1/GPIO228
GPIO49

LPC_SMI_L/GEVENT23_L

<23> CLKREQ_WLAN#

+3VALW_APU
RPC5

<27> SPK_DET
<25> CLKREQ_LAN#
<13> CLKREQ_PEG#

USB_OC#0
USB_OC#2
USB_CHG_OC#
ODD_PLUGIN#

<24,29> USB_OC#0
<24,29> USB_CHG_OC#
<23> ODD_PLUGIN#
<24,29> USB_OC#2
EMI@
2 33_0402_5%
RC92 1
2 33_0402_5%
RC93 1

100K_8P4R_5%
C

10K_0402_5%
2
1 APU_PCIE_WAKE#
2
1 APU_GPIO174
10K_0402_5%

RC96 1
RC97 1

EMI@
2 10P_0402_50V8J

@
@

2 10K_0402_5%
2 10K_0402_5%

RC98 1
RC1001

<26> AZ_SYNC_HD
<26> AZ_RST_HD#

AZ_BITCLK_HD

2 33_0402_5%
2 33_0402_5%

HDA_SYNC
HDA_RST#

AN2
AN1
AK2
AK1
AM1
AL2
AM2
AL1

GPIO55
GPIO57
GPIO58

IR_RX1/GEVENT20_L

GPIO59

IR_LED_L/LLB_L/GPIO184

GPIO64

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60
CLK_REQ1_L/GPIO61
CLK_REQ2_L/GPIO62
CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63
CLK_REQG_L/GPIO65/OSCIN
USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L
USB_OC1_L/TDI/GEVENT13_L
USB_OC2_L/TCK/GEVENT14_L

SPKR/GPIO66
GPIO68
GPIO69
GPIO70
GPIO71
GPIO174

2 10P_0402_50V8J

32K_X1

AJ2

AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST_L

32K_X2

AJ1

1

APU SMBus0 for S0 , SMBus1 for S5
If APU_SMBUS no use pull high 10K

2
@

GENINT1_L/GPIO32
GENINT2_L/GPIO33
FANOUT0/GPIO52

+3VS

GEVENT2

RTC CLK
X32K_X2

GEVENT2

VGA_PWRGD <15,39>

AV31
AU31

SPI ROM

DEFAULT

DEFAULT

CLKGEN
DISABLED

RTCCLK

AV11

RTC_CLK

RTC_CLK <29>

LPC ROM

eDP
panel

LVDS
panel

1
2
3
4

PXS_PWREN
PXS_EN#
Board_ID0
Board_ID1

FAST POWER
UP/RESET TIMING
FOR SIMULATION

+3VS
+3VALW_APU

HDMI_HPD <21,6>

Place at GPU
QC3A
2N7002KDWH_SOT363-6
1
6
VGA@
QC3B
2N7002KDWH_SOT363-6
4
3
PXS_EN#
VGA@

RC110
10K_0402_5%

A

Onkyo
0

RC99
1K_0402_5%
NTOUCH@

5

EC_PXCONTROL

ODD DA#

+3VS

+3VS

EC_PXCONTROL <29>

1

2

RC105
10K_0402_5%

1
CC48
ODD_DA#_APU 1
CC104
PXS_RST#

2 @ESD@
180P_0402_50V8J
2 ESD@
180P_0402_50V8J

No Brand
1

1

ODD_DA#_APU 6
CC32
0.1U_0402_16V4Z
@

1

ODD_DA# <23>

QC1A
2N7002KDWH_SOT363-6

2

A

RC114
2K_0402_5%

@
RC115
2K_0402_5%

Compal Secret Data

Security Classification
2012/09/27

Issued Date

2015/09/27

Deciphered Date

Title

2

2

2
2

@
RC111
2K_0402_5%

2

@
RC113
2K_0402_5%

1

1

1

1

1

close to APU

RC112
2K_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

B

PXS_PWREN

Board Conf. Board_ID0 Board_ID1
0
0
PX5
0
1
Reserved
1
0
DIS
1
1
UMA

SPK_DET

GEVENT2
RTC_CLK

TOUCH_SEL
RC126
10K_0402_5%
LVDS@

For DIS
L
H
Sleep&
SM_EN PlayMusic ALC259
(ALC269)

RC95
10K_0402_5%
TOUCH@

RC125
10K_0402_5%
EDP@

PANEL_SEL

Non Touch
Touch
Panel
Panel (turn off EHCI)

TOUCH_SEL

+3VS

+3VS

L

2

2

<29,7> CLK_PCI_EC
<7> CLK_PCI_DDR
<29,7> LPC_FRAME#

@
RC109
10K_0402_5%

2

RC106
10K_0402_5%

1

1

1

1

1

2

RC108
10K_0402_5%

8
7
6
5
10K_8P4R_5%
VGA@

+3VALW_APU

@
RC107
10K_0402_5%

3

2

L

DEFAULT

DEFAULT

QC2
2N7002KW_SOT323-3

1

RPC6

NORMAL POWR
UP/RESET TIMING

3.3V SPI ROM

2 10K_0402_5%

VRAM_SEL
Control by X76

RTC_CLK

1.8V SPI ROM

DEFAULT

2

+3VALW_APU
RC94 1

EC_LID_OUT#

2

PULL
LOW

CLKGEN
ENABLE

1K_0402_5%

2

LPC_FRAME#

1K_0402_5%

1

2

CLK_PCI_DDR

BOOT FAIL TIMER
DISABLED

C

EC_LID_OUT# <29>

BA29
AP23

32K_X2

PANEL_SEL

BOOT FAIL TIMER

RC1331 VGA@ 2
1
2
RC136
259@

@

H
PULL
HIGH

PXS_RST#
SM_DET

SW request

ODD_DA#_APU
EC_LID_OUT#

2

32.768KHZ_7PF_Q13MC1461000100

269@ 2 10K_0402_5%
UMA@ 2 10K_0402_5%
UMA@ 2 10K_0402_5%

HDMI_HPD_N

HDMI_HPD_N

STRAP PINS
CLK_PCI_EC

RC1351
RC1371
RC1381

FT3 REV 0.51

H

B

SM_DET
Board_ID0
Board_ID1

+3VS

FT3_BGA769

8P_0402_50V8D

+3VS
+3VALW_APU

2.2K_8P4R_5%

X32K_X1

3

1
2

8
7
6
5

GPIO174 PD CHK1.03

APU_GPIO174

RC104
20M_0402_5%
CC31 1

1
2
3
4

APU_SDATA0
APU_SCLK0
APU_SCLK1
APU_SDATA1

PXS_RST# <12>
APU_SPKR <26>
PXS_PWREN <14,39>

PXS_PWREN
TOUCH_SEL
SM_DET

AV17
BA4
AR15
AP17
GEVENT11_L AP11
GEVENT17_L AN8
BLINK/GEVENT18_L AU17
GEVENT22_L BA6

RPC1

ODD_PWR <31>

Board_ID0
Board_ID1
PXS_RST#

GEVENT7_L

AZ_SDIN0/GPIO167
AZ_SDIN2/GPIO169

1
JPW

GEVENT4_L

AZ_SDOUT
AZ_SDIN1/GPIO168

2

APU_SCLK1 <30>
APU_SDATA1 <30>

PANEL_SEL

GEVENT2_L

AZ_BITCLK

32K_X1
YC2

4

PW_CLEAR#

GEVENT10_L

USB_OC3_L/TDO/GEVENT15_L

FANIN0/GPIO56

HDA_BITCLK
AZ_SDIN0_HD
CC30 1

HDA_BITCLK
HDA_SDOUT
AZ_SDIN0_HD

AY8
AW 1
AV1
AY1

IR_TX1/GEVENT6_L

D

LPC_RST# <29>

RC74
100K_0402_5%
@

G

CC15 1

<26> AZ_BITCLK_HD
<26> AZ_SDOUT_HD
<26> AZ_SDIN0_HD

USB_OC#0
USB_CHG_OC#
ODD_PLUGIN#
USB_OC#2

IR_TX0/GEVENT21_L

AP27
AY28
BA28
AV23
AP21
BA26
AV19
AY27
BA27
AU21
AY26
AV21
AM21
BA3

150P_0402_50V8J

APU_SCLK0 <10,11,23>
APU_SDATA0 <10,11,23>

1

21

8
7
6
5

1
2
3
4

RC23
RC25

AU29
AW 29
AR27
AV27
AY29

AC_PRES/IR_RX0/GEVENT16_L

2 33_0402_5%

RC73 1

CC27

LPC_PME_L/GEVENT3_L

GPIO

<24> SLP_CHG_CB1
<25> LAN_EN

LPC_RST#_R

AY25

SDA0/GPIO47

MSIC

AP15
AV13
BA9
BA10
AV15

<24> SLP_CHG_CB0

A_RST# is for LPC devices

SD_DATA2/GPIO79

GPIO51

SLP_S3#
SLP_S5#

2

SD_DATA1/GPIO78

HDA

2 2.2K_0402_5%
2 2.2K_0402_5%

@
@

150P_0402_50V8J

AY23
AY20
BA20

SD_DATA0/GPIO77

IR

RC128 1
RC129 1

1

2

AMD G3-S5 clock issue

AY3
BA5

PWR_BTN_L

APU_PCIE_RST# <12,23,25>

RC72
@
100K_0402_5%

2
SD_CMD/GPIO74

RSMRST_L

CC28

21

SYS_PWRGD
T23
APU_PCIE_WAKE#

BA8
AM19
AY7
AW 11

GPIO50

+3VALW_APU

2 33_0402_5%

1

1U_0402_6.3V6K

CC29

2 10K_0402_5%

RC68 1

BA23
AY22

2

<29> PBTN_OUT#
<29> SYS_PWRGD

+1.8VALW
RC127 1

AY5

SD_CLK/GPIO73

PCIE_RST_L

SD_CD/GPIO75

RSMRST#

1

APU_PCIE_RST#_R
SD_PWR_CTRL

LPC_RST_L

S

RSMRST#

AY4
AY9

2

close to APU

CH751H-40PT_SOD323-2
D

UC1D

LPC_RST#_R
APU_PCIE_RST#_R

1

2 ESD@
SYS_PWRGD
180P_0402_50V8J

ACPI/SD/AZ/GPIO/RTC/MISC

2

2

1

PCIE_RST# is for PCIE devices on APU

SD

<29> EC_RSMRST#

2

Sequence

RC71 2

47K_0402_5%

1

DC2

1

1
CC97

3

1

+1.8VALW

D

5

Follow check list & ORB_0C
design 10 ms RC delay circuit
on +1.8-V S5 power rail.

2

FT3 GPIO/AZ/MISC
Document Number

Rev
1.0

LA-9868P
Thursday, May 16, 2013

Sheet
1

8

of

42

5

4

3

AMD CKL v1.01 10uF

1.5V OF APU

VDDIO_MEM_S

0.1uF

2

8

+1.5V

+1.5V

1

2

1

1@
CC14

2

2

1

47U_0805_6.3V6M

1

2

0.1U_0402_16V7K CC37

2

0.1U_0402_16V7K CC43

1

0.1U_0402_16V7K CC42

1

2

0.1U_0402_16V7K CC36

1

2

0.1U_0402_16V7K CC35

1

2

0.1U_0402_16V7K CC41

2

2

0.1U_0402_16V7K CC34

2

0.1U_0402_16V7K CC33

D

10U_0603_6.3V6M CC40

10U_0603_6.3V6M CC39

3A
1

AMD CKL v1.01 10uF 4.7uF 1uF 180pF

1.8VALW & 1.8VS OF APU

VDD_18

1

7
1

VDD_18_ALW

2
0_0603_5%

VDDCR_CPU_3 L25

VDDIO_MEM_S_4
VDDIO_MEM_S_5
VDDIO_MEM_S_6
VDDIO_MEM_S_7
VDDIO_MEM_S_8
VDDIO_MEM_S_9
VDDIO_MEM_S_10
VDDIO_MEM_S_11
VDDIO_MEM_S_12
VDDIO_MEM_S_13
VDDIO_MEM_S_14
VDDIO_MEM_S_15
VDDIO_MEM_S_16
VDDIO_MEM_S_17
VDDIO_MEM_S_18
VDDIO_MEM_S_19
VDDIO_MEM_S_20
VDDIO_MEM_S_21
VDDIO_MEM_S_22
VDDIO_MEM_S_23

VDDCR_NB_3 N11
VDDCR_NB_4 N13
VDDCR_NB_5 N17

2

1

2

1

2

1U_0402_6.3V6K CC64

2

1

1U_0402_6.3V6K CC63

2

1

1U_0402_6.3V6K CC61

2

1

1U_0402_6.3V6K CC62

2

1

1U_0402_6.3V6K CC60

2

1

1U_0402_6.3V6K CC59

2

1

1U_0402_6.3V6K CC58

2

1

VDDCR_NB_7 R13

1

VDDCR_NB_8 R17
VDDCR_NB_9 U13
VDDCR_NB_10 U17
VDDCR_NB_11 W 13
VDDCR_NB_12 W 17
VDDCR_NB_13 AA13
VDDCR_NB_14 AA17
VDDCR_NB_15 AC13
VDDCR_NB_16 AC17
VDDCR_NB_17 AE15
VDDCR_NB_18 AE17
VDDCR_NB_19 AE19
VDDCR_NB_20 AG17
VDDCR_NB_21 AG21

2

AL10
AL11

0.5A

3.3VALW & 3.3VS OF APU

B1
B2

+1.8VALW_APU

VDDIO_AZ_ALW_1
VDDIO_AZ_ALW_2
VDD_18_ALW_1

VDD_18_1

VDD_18_ALW_2

VDD_18_2
VDD_18_3
VDD_18_4

1A

2

1

2

1

2

1

2

1U_0402_6.3V6K CC70

2

2

1

1U_0402_6.3V6K CC69

1

1

CC66

0.2A

0.1A

AR5
AU4
AV7
AW 5

+0.95VALW_APU_USB3
1U_0402_6.3V6K CC67

2
0_0603_5%

for VDDIO_AZ_ALW

0.2A
1U_0402_6.3V6K CC71

1U_0402_6.3V6K CC75

1U_0402_6.3V6K CC74

for VDDIO_33_ALW

@

AL13
AM13

+3VALW_APU

4.7U_0603_6.3V6K

1
RC117

0.2A

+1.5VS

+3VS_APU

+3VS

1U_0402_6.3V6K CC72

+3VALW_APU

2

+APU_CORE_NB

VDDCR_NB_2 L17

+1.5VS

B

13A/17A

VDDCR_NB_1 L13

0.1A

1

A8
A13
A23
A31
A35
A39
B8
B13
B23
B31
B39
C1
C2
C5
C7
C9
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C33
C35
C37
C39
C41
D9
D11
D13
E3
E4
E9
E11
E13
E27
E31
E35
E38
E39
G3
G7
G11
G13
G15
G17
G21
G25
G29
G35
G37
G39
G41
H11
H13
H23
H31

VDDCR_CPU_4 L27
VDDCR_CPU_5 L29
VDDCR_CPU_6 N21
VDDCR_CPU_7 N23
VDDCR_CPU_8 N27
VDDCR_CPU_9 R21
VDDCR_CPU_10 R23
VDDCR_CPU_11 R27
VDDCR_CPU_12 U21
VDDCR_CPU_13 U23
VDDCR_CPU_14 U27
VDDCR_CPU_15 W 21
VDDCR_CPU_16 W 23
VDDCR_CPU_17 W 27
VDDCR_CPU_18 AA21
VDDCR_CPU_19 AA23
VDDCR_CPU_20 AA27
VDDCR_CPU_21 AC21
VDDCR_CPU_22 AC23
VDDCR_CPU_23 AC27
VDDCR_CPU_24 AE21
VDDCR_CPU_25 AE23
VDDCR_CPU_26 AE27

1.5A
10U_0603_6.3V6M CC57

2

1

1U_0402_6.3V6K CC55

2

1

1U_0402_6.3V6K CC54

2

1

1U_0402_6.3V6K CC53

2

1

1U_0402_6.3V6K CC52

1

1U_0402_6.3V6K CC51

4.7U_0603_6.3V6K

C

VDDIO_MEM_S_3

1

0.5A

VDD_33_2

VDD_33_ALW_2
VDD_095_USB3_DUAL_1

VDD_095_1

VDD_095_USB3_DUAL_2

VDD_095_2

VDD_095_USB3_DUAL_3

VDD_095_3

VDD_095_USB3_DUAL_4

VDD_095_4
VDD_095_5

AE11
AE13
AJ11
AJ13

+0.95VALW_APU

2

VDD_33_1

VDD_33_ALW_1

VDD_095_ALW_1

VDD_095_6

VDD_095_ALW_2

VDD_095_7
VDD_095_8

VDD_095_ALW_3

VDD_095_9

VDD_095_ALW_4

1.5A

A2
A3
B3
C3

+1.8VS

0.2A

AM15
AM17

+3VS_APU

5A

AG23
AG27
AJ21
AJ27
AL21
AL23
AL27
AM23
AM25

+0.95VS_APU

AN4

VSS_63

VSS_2

VSS_64

VSS_3

VSS_65

VSS_4

VSS_66

VSS_5

VSS_67

VSS_6

VSS_68

VSS_7

VSS_69

VSS_8

VSS_70

VSS_9

VSS_71

VSS_10

VSS_72

VSS_11

VSS_73

VSS_12

VSS_74

VSS_13

VSS_75

VSS_14

VSS_76

VSS_15

VSS_77

VSS_16

VSS_78

VSS_17

VSS_79

VSS_18

VSS_80

VSS_19

VSS_81

VSS_20

VSS_82

VSS_21

VSS_83

VSS_22

VSS_84

VSS_23

VSS_85

VSS_24

VSS_86

VSS_25

VSS_87

VSS_26

VSS_88

VSS_27

VSS_89

VSS_28

VSS_90

VSS_29

VSS_91

VSS_30

VSS_92

VSS_31

VSS_93

VSS_32

VSS_94

VSS_33

VSS_95

VSS_34

VSS_96

VSS_35

VSS_97

VSS_36

VSS_98

VSS_37

VSS_99

VSS_38

VSS_100

VSS_39

VSS_101

VSS_40

VSS_102

VSS_41

VSS_103

VSS_42

VSS_104

VSS_43

VSS_105

VSS_44

VSS_106

VSS_45

VSS_107

VSS_46

VSS_108

VSS_47

VSS_109

VSS_48

VSS_110

VSS_49

VSS_111

VSS_50

VSS_112

VSS_51

VSS_113

VSS_52

VSS_114

VSS_53

VSS_115

VSS_54

VSS_116

VSS_55

VSS_117

VSS_56

VSS_118

VSS_57

VSS_119

VSS_58

VSS_120

VSS_59

VSS_121

VSS_60

VSS_122

VSS_61

VSS_123
VSS_124

VSS_62

VSS_187

VSS_126

VSS_188

VSS_127

VSS_189

VSS_128

VSS_190

VSS_129

VSS_191

VSS_130

VSS_192

VSS_131

VSS_193

VSS_132

VSS_194

VSS_133

VSS_195

VSS_134

VSS_196

VSS_135

VSS_197

VSS_136

VSS_198

VSS_137

VSS_199

VSS_138

VSS_200

VSS_139

VSS_201

VSS_140

VSS_202

VSS_141

VSS_203

VSS_142

VSS_204

VSS_143

VSS_205

VSS_144

VSS_206

VSS_145

VSS_207

VSS_146

VSS_208

VSS_147

VSS_209

VSS_148

VSS_210

VSS_149

VSS_211

VSS_150

VSS_212

VSS_151

VSS_213

VSS_152

VSS_214

VSS_153

VSS_215

VSS_154

VSS_216

VSS_155

VSS_217

VSS_156

VSS_218

VSS_157

VSS_219

VSS_158

VSS_220

VSS_159

VSS_221

VSS_160

VSS_222

VSS_161

VSS_223

VSS_162

VSS_224

VSS_163

VSS_225

VSS_164

VSS_226

VSS_165

VSS_227

VSS_166

VSS_228

VSS_167

VSS_229

VSS_168

VSS_230

VSS_169

VSS_231

VSS_170

VSS_232

VSS_171

VSS_233

VSS_172

VSS_234

VSS_173

VSS_235

VSS_174

VSS_236

VSS_175

VSS_237

VSS_176

VSS_238

VSS_177

VSS_239

VSS_178

VSS_240
VSS_241

VSS_179
VSS_180

VSS_242

VSS_181

VSSBG_DAC

VSS_182

VBURN

VSS_183

PSEN

AL39
AL41
AM11
AM27
AM31
AN3
AN7
AN39
AP31
AR3
AR13
AR17
AR21
AR25
AR29
AR39
AR41
AU1
AU2
AU3
AU15
AU19
AU23
AU27
AU39
AV9
AW 3
AW 7
AW 13
AW 15
AW 17
AW 19
AW 21
AW 23
AW 25
AW 27
AW 31
AW 33
AW 35
AW 37
AW 39
AW 41
AY13
AY15
AY18
AY30
BA2
BA7
BA13
BA15
BA18
BA21
BA25
BA31
BA35
BA39
A15
AL31
AM29

D

C

VSS_184
VSS_185
VSS_186
FT3 REV 0.51

@

0.6A
+0.95VS_APU_GFX

AMD CKL v1.01

@

Place on TOP

B

10uF 1uF 180pF

VDD_095_USB3_DUAL 2
VDD_095
2
VDD_095_ALW
VDD_095_GFX
1

FT3 REV 0.51

FT3_BGA769

VSS_125

FT3_BGA769

@

VDD_095_GFX_3 AA10

VDDBT_RTC_G

W 29
W 39
W 41
Y1
Y2
AA3
AA7
AA8
AA11
AA15
AA19
AA25
AA29
AA39
AC3
AC7
AC11
AC15
AC19
AC25
AC29
AC31
AC39
AC41
AE3
AE7
AE25
AE29
AE32
AE39
AG3
AG5
AG10
AG11
AG13
AG15
AG19
AG25
AG29
AG31
AG39
AG41
AH1
AH2
AJ3
AJ7
AJ15
AJ17
AJ19
AJ23
AJ25
AJ29
AJ31
AJ32
AJ39
AL3
AL8
AL15
AL17
AL19
AL25
AL29

J3
J7
J8
J39
K11
K13
K17
K19
K21
K23
K25
K27
K29
K31
L3
L7
L8
L10
L11
L15
L19
L31
L39
L41
M1
M2
N3
N7
N15
N19
N25
N29
N31
N39
P1
P2
R3
R7
R15
R19
R25
R29
R39
R41
U1
U2
U3
U7
U8
U11
U15
U19
U25
U29
U31
U39
W3
W5
W 11
W 15
W 19
W 25

FT3 REV 0.51

VDD_095_GFX_2 W 10

4.5uA

GND

VSS_1

FT3_BGA769

VDD_095_GFX_1 U10

+RTC_APU

UC1H
GND

+APU_CORE

VDDCR_NB_6 R11

1U_0402_6.3V6K CC50

@

VDDCR_CPU_2 L23

1

0.5A
CC49

1
RC116

VDDCR_CPU_1 L21

VDDIO_MEM_S_2

+1.8VS

+1.8VALW_APU

+1.8VALW

VDDIO_MEM_S_1

UC1G

15A/21A

POWER

J35
L32
L37
N35
R31
R37
U32
U35
W 31
W 32
W 37
AA31
AA35
AC32
AC37
AE31
AE35
AG32
AG37
AJ35
AL32
AL37
AR35

1

6

1

UC1F

4

3A

1

2

180pF

3
5
4
1

1
1

+0.95VS

2

2

1

2

1

2

route to 20mil
@
JCMOS

2

1

2

1

2

1

2

2

2

Compal Secret Data

Security Classification
2012/09/27

Issued Date

2015/09/27

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

1

10U_0603_6.3V6M CC95

1

1U_0402_6.3V6K CC92

2

1U_0402_6.3V6K CC96

1
2

1

1U_0402_6.3V6K CC91

2

1

1U_0402_6.3V6K CC90

2

1

1U_0402_6.3V6K CC89

2

1

1U_0402_6.3V6K CC88

1

2

1

+0.95VS_APU_GFX
LC1
0.6A
1
2
FBMA-L11-201209-300LMA30T
1
1

RC123
120_0402_5%

1 2

1

RC122
1
2
10K_0402_5%

2

DC5

2

CH751H-40PT_SOD323-2

1

0.22U_0402_16V7K

+RTC

CC98

+3VL

2

1

+0.95VS_APU

5A
10U_0603_6.3V6M CC86

4.5uA
A

2

1

0.5A

2
0_0603_5%

PJ2
JUMP_43X79
@

10U_0603_6.3V6M CC87

+RTC_APU_R

1

@

1U_0402_6.3V6K CC85

1

+RTC_APU

1
RC120

1U_0402_6.3V6K CC83

2

2
0_0603_5%

1U_0402_6.3V6K CC84

VDDIO_33

@

+0.95VALW_APU

+0.95VALW

1U_0402_6.3V6K CC82

2

1
RC119

1U_0402_6.3V6K CC80

VDDIO_33_ALW

1

1U_0402_6.3V6K CC78

3

1A

1U_0402_6.3V6K CC79

RTC OF APU

1

180pF

10U_0603_6.3V6M CC77

VDDIO_AZ_ALW

1uF

1

+0.95VALW_APU_USB3

+0.95VALW

AMD CKL v1.01 4.7uF

2

2

0.95VALW & 0.95VS OF APU

4

3

2

FT3 PWR/GND
Document Number

Rev
1.0

LA-9868P
Thursday, May 16, 2013

Sheet
1

9

of

42

A

3

D

DDR_AB_DQS#1
DDR_AB_DQS1

DDR_AB_DQS#2
DDR_AB_DQS2
DDR_AB_D18
DDR_AB_D19
DDR_AB_D24
DDR_AB_D25
DDR_AB_DM3
DDR_AB_D26
DDR_AB_D27

DDR_A_CKE0

<5> DDR_A_CKE0

DDR_AB_BS2

<11,5> DDR_AB_BS2

C

DDR_AB_MA12
DDR_AB_MA9
DDR_AB_MA8
DDR_AB_MA5
DDR_AB_MA3
DDR_AB_MA1
DDR_A_CLK0
DDR_A_CLK0#

<5> DDR_A_CLK0
<5> DDR_A_CLK0#

DDR_AB_MA10
DDR_AB_BS0

<11,5> DDR_AB_BS0

DDR_AB_WE#
DDR_AB_CAS#

<11,5> DDR_AB_WE#
<11,5> DDR_AB_CAS#

DDR_AB_MA13
DDR_A_SCS1#

<5> DDR_A_SCS1#

DDR_AB_D32
DDR_AB_D33
DDR_AB_DQS#4
DDR_AB_DQS4
B

DDR_AB_D34
DDR_AB_D35
DDR_AB_D40
DDR_AB_D41
DDR_AB_DM5
DDR_AB_D42
DDR_AB_D43
DDR_AB_D48
DDR_AB_D49
DDR_AB_DQS#6
DDR_AB_DQS6
DDR_AB_D50
DDR_AB_D51
DDR_AB_D56
DDR_AB_D57
DDR_AB_DM7
DDR_AB_D58
DDR_AB_D59

+3VS

2

1

+0.75VS
CD20

0.1U_0402_16V4Z

A

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
W E#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
GND1
BOSS1

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
BOSS2

SO-DIMM VREF
+1.5V

DDR_AB_DQS#[0..7]
DDR_AB_D[0..63]

1
RD1
1K_0402_1%

<11,5>

DDR_AB_DM[0..7]
DDR_AB_MA[0..15]

<11,5>

+VREF_DQA

+VREF_CAA

<11,5>

D

2

MEM_MAB_RST# <11,5>

CD1

DDR_AB_D14
DDR_AB_D15

1

DDR_AB_D20
DDR_AB_D21
DDR_AB_DM2
DDR_AB_D22
DDR_AB_D23
DDR_AB_D28
DDR_AB_D29

1 @
CD2
2

1 @
CD4

2

RD3
1K_0402_1%

CD3

1

Close to JDDR3L.1

2

RD4
1K_0402_1%

Close to JDDR3L.126

DDR_AB_DQS#3
DDR_AB_DQS3
DDR_AB_D30
DDR_AB_D31

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_A_CKE1

DDR_A_CKE1 <5>

DDR_AB_MA15
DDR_AB_MA14
C

DDR_AB_MA11
DDR_AB_MA7
DDR_AB_MA6
DDR_AB_MA4
DDR_AB_MA2
DDR_AB_MA0
DDR_A_CLK1
DDR_A_CLK1#
DDR_AB_BS1
DDR_AB_RAS#
DDR_A_SCS0#
DDR_A_ODT0
DDR_A_ODT1

DDR_A_CLK1 <5>
DDR_A_CLK1# <5>
DDR_AB_BS1 <11,5>
DDR_AB_RAS# <11,5>
DDR_A_SCS0# <5>
DDR_A_ODT0 <5>
DDR_A_ODT1 <5>

+VREF_CAA
DDR_AB_D36
DDR_AB_D37

Layout Note: Place these 4 Caps near
Command and Control signals of DIMMA

Layout Note:
Place near JDDR3L

DDR_AB_DM4
DDR_AB_D38
DDR_AB_D39

B

Layout Note:
Place near JDDR3L.203 and 204

+1.5V

DDR_AB_D44
DDR_AB_D45
DDR_AB_DQS#5
DDR_AB_DQS5
DDR_AB_D46
DDR_AB_D47

CD43 1

2 47U_0805_6.3V6M

CD10 1

2 10U_0603_6.3V6M
+1.5V

DDR_AB_D52
DDR_AB_D53
DDR_AB_DM6
DDR_AB_D54
DDR_AB_D55

CD11 1

2 10U_0603_6.3V6M

CD13 1

2 10U_0603_6.3V6M

CD5

1

2 0.1U_0402_16V4Z

CD14 1

2 10U_0603_6.3V6M

CD6

1

2 0.1U_0402_16V4Z

CD16 1

2 10U_0603_6.3V6M

CD7

1

2 0.1U_0402_16V4Z

CD18 1

2 10U_0603_6.3V6M

CD8

1

2 0.1U_0402_16V4Z

+0.75VS

2

1 1U_0402_6.3V6K

CD12 2

1 1U_0402_6.3V6K

CD9

DDR_AB_D60
DDR_AB_D61
DDR_AB_DQS#7
DDR_AB_DQS7
DDR_AB_D62
DDR_AB_D63
MEM_MAB_EVENT#
APU_SDATA0
APU_SCLK0

MEM_MAB_EVENT# <11,5>
APU_SDATA0 <11,23,8>
APU_SCLK0 <11,23,8>

A

+0.75VS

206
208

Compal Electronics, Inc.

Compal Secret Data

Security Classification

LCN_DAN06-K4406-0103
@

2012/09/27

Issued Date

Deciphered Date

2015/09/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

RD2
1K_0402_1%

<11,5>

2

DDR_AB_D12
DDR_AB_D13
DDR_AB_DM1
MEM_MAB_RST#

<11,5>

DDR_AB_DQS[0..7]

DDR_AB_D6
DDR_AB_D7

+1.5V

1

DDR_AB_DQS#0
DDR_AB_DQS0

2.2U_0402_6.3V6M

DDR_AB_D16
DDR_AB_D17

DDR_AB_D4
DDR_AB_D5

2.2U_0402_6.3V6M

DDR_AB_D10
DDR_AB_D11

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

1

DDR_AB_D8
DDR_AB_D9

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

0.1U_0402_16V7K

DDR_AB_D2
DDR_AB_D3

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

2

DDR_AB_DM0

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

1

1

+VREF_DQA
DDR_AB_D0
DDR_AB_D1

2

DDR3 SO-DIMM A
Reverse Type

2

+1.5V
JDDR3L

2

4

+1.5V

0.1U_0402_16V7K

5

4

3

2

DDRIII-SODIMMA
Document Number

Rev
1.0

LA-9868P
Sheet

Thursday, May 16, 2013
1

10

of

42

4

3

D

DDR_AB_DQS#1
DDR_AB_DQS1

DDR_AB_DQS#2
DDR_AB_DQS2
DDR_AB_D18
DDR_AB_D19
DDR_AB_D24
DDR_AB_D25
DDR_AB_DM3
DDR_AB_D26
DDR_AB_D27

DDR_B_CKE0

<5> DDR_B_CKE0
C

DDR_AB_BS2

<10,5> DDR_AB_BS2

DDR_AB_MA12
DDR_AB_MA9
DDR_AB_MA8
DDR_AB_MA5
DDR_AB_MA3
DDR_AB_MA1
DDR_B_CLK0
DDR_B_CLK0#

<5> DDR_B_CLK0
<5> DDR_B_CLK0#

DDR_AB_MA10
DDR_AB_BS0

<10,5> DDR_AB_BS0

DDR_AB_WE#
DDR_AB_CAS#

<10,5> DDR_AB_WE#
<10,5> DDR_AB_CAS#

DDR_AB_MA13
DDR_B_SCS1#

<5> DDR_B_SCS1#

DDR_AB_D32
DDR_AB_D33
DDR_AB_DQS#4
DDR_AB_DQS4

B

DDR_AB_D34
DDR_AB_D35
DDR_AB_D40
DDR_AB_D41
DDR_AB_DM5
DDR_AB_D42
DDR_AB_D43
DDR_AB_D48
DDR_AB_D49
DDR_AB_DQS#6
DDR_AB_DQS6
DDR_AB_D50
DDR_AB_D51
DDR_AB_D56
DDR_AB_D57
DDR_AB_DM7
DDR_AB_D58
DDR_AB_D59
A

2
10K_0402_5%

2

1

+0.75VS
CD40

1
RD9
0.1U_0402_16V4Z

+3VS

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
W E#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
GND1
BOSS1

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
BOSS2

DDR_AB_MA[0..15]

1

1
DDR_AB_DM[0..7]

<10,5>

2

DDR_AB_D[0..63]

DDR_AB_D12
DDR_AB_D13

+VREF_DQB

<10,5>

+VREF_CAB
D

<10,5>

2
CD21

MEM_MAB_RST# <10,5>

1

DDR_AB_D14
DDR_AB_D15
DDR_AB_D20
DDR_AB_D21
DDR_AB_DM2
DDR_AB_D22
DDR_AB_D23

1 @
CD22
2

CD23

1

Close to JDDR3H.1

2

RD7
1K_0402_1%

Close to JDDR3H.126

DDR_AB_D28
DDR_AB_D29
DDR_AB_DQS#3
DDR_AB_DQS3
DDR_AB_D30
DDR_AB_D31

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_CKE1

DDR_B_CKE1 <5>

DDR_AB_MA15
DDR_AB_MA14

C

DDR_AB_MA11
DDR_AB_MA7
DDR_AB_MA6
DDR_AB_MA4
DDR_AB_MA2
DDR_AB_MA0
DDR_B_CLK1
DDR_B_CLK1#
DDR_AB_BS1
DDR_AB_RAS#
DDR_B_SCS0#
DDR_B_ODT0
DDR_B_ODT1

DDR_B_CLK1 <5>
DDR_B_CLK1# <5>
DDR_AB_BS1 <10,5>
DDR_AB_RAS# <10,5>
DDR_B_SCS0# <5>
DDR_B_ODT0 <5>
DDR_B_ODT1 <5>

+VREF_CAB

Layout Note:
Place near JDDR3H

DDR_AB_D36
DDR_AB_D37

Layout Note: Place these 4 Caps near
Command and Control signals of DIMMB

DDR_AB_DM4

Layout Note:
Place near JDDRH.203 and 204

DDR_AB_D38
DDR_AB_D39

B

DDR_AB_D44
DDR_AB_D45
DDR_AB_DQS#5
DDR_AB_DQS5

+1.5V

DDR_AB_D46
DDR_AB_D47
DDR_AB_D52
DDR_AB_D53

CD30 1

2 10U_0603_6.3V6M

CD31 1

2 10U_0603_6.3V6M

CD33 1

2 10U_0603_6.3V6M

CD34 1

2 10U_0603_6.3V6M

CD36 1

2 10U_0603_6.3V6M

CD38 1

2 10U_0603_6.3V6M

DDR_AB_DM6
DDR_AB_D54
DDR_AB_D55
DDR_AB_D60
DDR_AB_D61

+0.75VS

+1.5V

CD25 2

1 0.1U_0402_16V4Z

CD26 2

1 0.1U_0402_16V4Z

CD27 2

1 0.1U_0402_16V4Z

CD28 2

1 0.1U_0402_16V4Z

CD29 2

1 1U_0402_6.3V6K

CD32 2

1 1U_0402_6.3V6K

DDR_AB_DQS#7
DDR_AB_DQS7
DDR_AB_D62
DDR_AB_D63
A

MEM_MAB_EVENT#
APU_SDATA0
APU_SCLK0

MEM_MAB_EVENT# <10,5>
APU_SDATA0 <10,23,8>
APU_SCLK0 <10,23,8>

+0.75VS

206
208

2012/09/27

Issued Date

LCN_DAN06-K4806-0103
@

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2015/09/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

1 @
CD24

2
RD5
1K_0402_1%

2.2U_0402_6.3V6M

DDR_AB_D16
DDR_AB_D17

DDR_AB_D6
DDR_AB_D7

RD8
1K_0402_1%

RD6
1K_0402_1%

<10,5>

DDR_AB_DQS#[0..7]

2.2U_0402_6.3V6M

DDR_AB_D10
DDR_AB_D11

<10,5>

DDR_AB_DQS[0..7]

DDR_AB_DQS#0
DDR_AB_DQS0

DDR_AB_DM1
MEM_MAB_RST#

+1.5V

+1.5V

1

DDR_AB_D8
DDR_AB_D9

DDR_AB_D4
DDR_AB_D5

SO-DIMM VREF

DDR3 SO-DIMM B
Reverse Type

2

DDR_AB_D2
DDR_AB_D3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

0.1U_0402_16V7K

DDR_AB_DM0

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

2

DDR_AB_D0
DDR_AB_D1

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

1

JDDR3H

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

1

2

+1.5V

+1.5V

+VREF_DQB

2

0.1U_0402_16V7K

5

4

3

2

DDRIII-SODIMMB
Document Number

Rev
1.0

LA-9868P
Sheet

Thursday, May 16, 2013
1

11

of

42

A

B

<5> PCIE_ATX_C_GRX_P[3..0]
<5> PCIE_ATX_C_GRX_N[3..0]

PCIE_ATX_C_GRX_P[3..0]

C

UV1A

PCIE_ATX_C_GRX_N[3..0]

PCIE_GTX_C_ARX_P[3..0]
PART 1 0F 9

D

E

PCIE_GTX_C_ARX_P[3..0] <5>

PCIE_GTX_C_ARX_N[3..0]

LVDS Interface

PCIE_GTX_C_ARX_N[3..0] <5>

UV1D
1

AA38
Y37

PCIE_ATX_C_GRX_P1
PCIE_ATX_C_GRX_N1

Y35
W36

PCIE_ATX_C_GRX_P2
PCIE_ATX_C_GRX_N2

W38
V37

PCIE_ATX_C_GRX_P3
PCIE_ATX_C_GRX_N3

V35
U36
U38
T37
T35
R36
R38
P37
P35
N36

PCIE_RX0P
PCIE_RX0N

PCIE_TX0P
PCIE_TX0N

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

1

PCIE_GTX_ARX_P0 .1U_0402_16V7K CV1
PCIE_GTX_ARX_N0
CV2
.1U_0402_16V7K

1
1

2 VGA@
2 VGA@

PCIE_GTX_C_ARX_P0
PCIE_GTX_C_ARX_N0

.1U_0402_16V7K CV3
CV4
.1U_0402_16V7K

1
1

2 VGA@
2 VGA@

PCIE_GTX_C_ARX_P1
PCIE_GTX_C_ARX_N1

U33 PCIE_GTX_ARX_P2 .1U_0402_16V7K CV5
U32 PCIE_GTX_ARX_N2
CV6
.1U_0402_16V7K

1
1

2 VGA@
2 VGA@

PCIE_GTX_C_ARX_P2
PCIE_GTX_C_ARX_N2

1
1

2 VGA@
2 VGA@

PCIE_GTX_C_ARX_P3
PCIE_GTX_C_ARX_N3

Y33
Y32

W33 PCIE_GTX_ARX_P1
W32 PCIE_GTX_ARX_N1

U30 PCIE_GTX_ARX_P3
U29 PCIE_GTX_ARX_N3

.1U_0402_16V7K

CV7
CV8

PART 7 0F 9
RSVD/VARY_BL
RSVD/DIGON

TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N

.1U_0402_16V7K

TX4P_DPB1P
TX4M_DPB1N

T33
T32

TX5P_DPB0P
TX5M_DPB0N

T30
T29

NC#AF35
NC#AG36

P33
P32

TXCAP_DPA3P
TXCAM_DPA3N

P30
P29

TX0P_DPA2P
TX0M_DPA2N

2

M35
L36
L38
K37
K35
J36
J38
H37
H35
G36
G38
F37
F35
E37

NC
NC

NC
NC

PCI EXPRESS INTERFACE

N38
M37

NC
NC
NC
NC

NC
NC
NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC
NC
NC

NC
NC

N33
N32
N30
N29

AB35
AA36

TX2P_DPA0P
TX2M_DPA0N
NC
NC

L33
L32
L30
L29

VGA@

AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37
AF35
AG36

AP34
AR34
AW37
AU35
2

AR37
AU39
AP35
AR35
AN36
AP37

SUN-PRO M2_FCBGA962

K33
K32
J33
J32
K30
K29

For MEMCLK 1GHz

H33
H32

Brand

Description

Comment

skHynix

H5TQ2G63DFR-N0C

1.5V/1GHz

000

NC

4750

Samsung

K4W2G1646E-BC1A

1.5V/1GHz

111

4750

NC

PS_3[3:1] R_pu(ohm) R_pd(ohm)

gDDR3-2Gbit

CLOCK
CLK_PCIE_VGA
CLK_PCIE_VGA#

TX1P_DPA1P
TX1M_DPA1N

AC Coupling Capacitor
PCIeR Gen1 and Gen2 only: Recommended value is 100 nF 10%.
PCIeR Gen3: Recommended value is 220 nF 10%.

3

<7> CLK_PCIE_VGA
<7> CLK_PCIE_VGA#

AK27
AJ27

LVDS CONTROL

LVTMDP

PCIE_ATX_C_GRX_P0
PCIE_ATX_C_GRX_N0

3

PCIE_REFCLKP
PCIE_REFCLKN
CALIBRATION
PCIE_CALR_TX

AH16
2 VGA@ 1
RV2
1K_0402_5%

Y30

VGA_PCIE_CALRP

RV1

1 VGA@ 2 1.69K_0402_1%

+0.95VGS

Y29

VGA_PCIE_CALRN

RV3

1 VGA@ 2 1K_0402_1%

+0.95VGS

PERSTB

1

3.3-V tolerant

AA30

GPU_RST#

PCIE_CALR_RX

TEST_PG

VGA@

SUN-PRO M2_FCBGA962

For MEMCLK 900MHz

Brand

Description

Comment

skHynix

H5TQ2G63DFR-11C

1.5V/900MHz

000

1.35V/900MHz
1.5V/900MHz
1.5V/900MHz

PS_3[3:1]R_pu(ohm) R_pd(ohm)

2

VGA@
RV212
100K_0402_5%

gDDR3-2Gbit
+3VS

Micron
Samsung

MT41K128M16JT-107G:K
K4W2G1646E-BC11

NC

4750

001

8450

2000

111

4750

NC

<23,25,8> APU_PCIE_RST#

2
1

B

UV13
Y

A

4

4

GPU_RST#

G

<8> PXS_RST#

3

4

P

5

VGA@

MC74VHC1G08DFT2G SC70 5P

2012/09/27

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2015/09/27

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

PCIE/LVDS
Rev
1.0

LA-9868P

Thursday, May 16, 2013

Sheet
E

12

of

42

A

B

C

D

PART 2 0F 9

NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

1
RV11
<29> GPU_DOWN#
<39> GPU_VID5

VGA@

2
10K_0402_5%

<39> GPU_VID1
@

RV8 1

<39> GPU_VID2

TV4
TV5

<8> CLKREQ_PEG#
VGA@
2 10K_0402_5%
1

DPD

NC
NC
NC
NC

AK26
AJ26

SCL
SDA

AH20
AH18
AN16

GENERAL PURPOSE I/O
GPIO_0
GPIO_1
GPIO_2

AH17
AJ17
GPU_VID5
AK17
AJ13
GPU_GPIO8
AH15
GPU_GPIO9
AJ16
GPU_GPIO10
AK16
AL16
AM16
AM14
AM13
GPU_VID1
AK14
GPIO_16
AG30
AN14
2 10K_0402_5% AM17
AL13
GPU_VID2
AJ14
GPU_GPIO21
AK13
GPU_GPIO22
CLKREQ_PEG# AN13

TV1
TV2
TV3

2

SMBCLK
SMBus
SMBDATA

GPU_VID3
GPU_VID4

GENERIC_X
Stereo-sync signal.
Indicates left/right frame, or top/bottom field.
Can be left unconnected if not used.

PX_EN :
High (3.3 V) switches the regulators
off (enter BACO mode).
Low (0 V) switches the regulators
on. (Default)

+3VGS

Enable JTAG access

TV9

2

PX_EN

AG32
AG33
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

GPIO_5_AC_BATT
GPIO_6_TACH
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21
GPIO_22_ROMCSB
CLKREQB

R
AVSSN
G
AVSSN
B
AVSSN
DAC1

HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
NC
NC
NC
NC
NC
NC
NC

GPIO_29
GPIO_30

AC30

CEC_1

AK24

HPD1

4.53k

2.00k

xx011

6.98k

4.99k

xx100

4.53k

4.99k

xx101

3.24k

5.62k

xx110

3.40k

10.0k

AH13

xx111

4.75k

NC
680nF

01xxx

82nF

10xxx

10nF

11xxx

TV7

GPIO_28_FDO
H

Disable

L

Enable

PX_EN

+TSVDD

CV19

1

2

PS_1[3]

N/A

GENLK_CLK

Reserved for internal use only. Must be 0 at reset.

0

PS_1[4]

TX_PWRS_ENB

GPIO_0

Transmitter (Tx) power savings enable.
0 = 50% Tx output swing.
1 = Full Tx output swing.

1

PS_1[5]

TX_DEEMPH_EN

GPIO_1

PCI EXPRESS transmitter, deemphasis enable.
0 = Tx deemphasis disabled.
1 = Tx deemphasis enabled.

1

PS_2[1]

N/A

N/A

Reserved.

0

PS_2[2]

N/A

N/A

Reserved.

0

PS_2[3]

BIOS_ROM_EN

GPIO_22

To enable the external BIOS ROM device.
0 = Disable the external BIOS ROM device.
1 = Enable the external BIOS ROM device.

0

PS_2[4]

BIF_VGA_DIS

GPIO_9

VGA disable determines whether or not the card will be recognized as the
system's VGA controller.
0 = VGA controller capacity enabled.
1 = The device will not be recognized as the system’s VGA controller.

0

PS_2[5]

N/A

N/A

Reserved.

PS_3[1]
PS_3[2]
PS_3[3]

BOARD_CONFIG[0]
BOARD_CONFIG[1]
BOARD_CONFIG[2]

PS_0[5]
PS_3[4]
PS_3[5]

AUD_PORT_CONN_
PINSTRAP[0]

1 GB

Not supported

2 GB

Not supported

4 GB

Not supported

NC

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO

DPLUS
DMINUS

AK32

GPIO_28_FDO

AL31

TS_A

AJ32
AJ33

TSVDD
TSVSS

AE36
AD35
AF37
AE38
AC36
AC38
AB34
AD34
AE34
AC33
AC34

Pin Name
V13
U13
AF33
AF32
AA29
AG21
AC32

GPIO_0

Type
I/O
3.3 V
(VDDR3)

PD/PU

Description

PD-reset

Power-state indicator.
Permits the voltage regulator to activate power-saving
features.
IF VR Suport PSI# and DPRSLPVR PU 10K to +3VGS.
PSI# :Low load current flag
DPRSLPVR : Deeper sleep enable flag

AC31
AD30
AD32

AG31

PS_2

GPIO_15_PWRCNTL_0

AD33

PS_3

I/O
3.3 V
(VDDR3)

PD-reset

(Optional) An input which allows the system to
request a fastpower reduction by setting
GPIO_5_AC_BATT to low (0 V). The resulting state
transition may disturb the display momentarily.
Power reductions that are less time critical
should use the standard software methods in order
to prevent display disturbances.

PD-reset

Voltage control signals for the core (VDDC and VDDCI).
At reset, these signals will be inputs with weak
internal pulldown resistors.
The VBIOS can define all voltage-control signals to be
either 3.3-V or open-drain outputs (all signals must
be the same type).
The output states (high/low) of these pins are
programmable for each AMD PowerPlay state when they
are used as voltage control signals.
Note: GPIO_29 and GPIO_30 are only available on 28-nm
ASICs, and are NC on earlier generation ASICs.

I/O
3.3 V
(VDDR3)

GPIO_29

DDC1CLK
DDC1DATA

N/A

AUD_PORT_CONN_
PINSTRAP[1]

0

Board configuration related strapping (such as memory ID).

Together with PS_0[5] form the three-bit strap option to indicate the number of
audio-capable display outputs. In a given ASIC there are as many endpoints as
there are digital display outputs, though not all outputs are audio capable.
111 = No usable endpoints.
110 = One usable endpoint.
101 = Two usable endpoints.
100 = Three usable endpoints.
011 = Four usable endpoints.
010 = Five usable endpoints.
001 = Six usable endpoints.
000 = All endpoints are usable.

N/A

AUD_PORT_CONN_
PINSTRAP[2]

2

Base on
VRAM ID

111

DDC2CLK
DDC2DATA
AUX2P
AUX2N

NC
NC

NC
NC
DDCVGACLK
DDCVGADATA

AM26
AN26
AM27
AL27

GPIO_8_ROMSO

I
3.3 V
(VDDR3)

PD-reset

AN20
AM20
AL30
AM30
AL29
AM29

Serial-ROM input to ROM.
General purpose I/O or open-drain output.

GPIO_9_ROMSI
GPIO_10_ROMSCK

O
3.3 V
(VDDR3)

Bits[5:4]

Bits[3:1]

R_pu

R_pd

PS_0[5:1]

11

001

NC

8.45K

2K

PS_1[5:1]

11

001

NC

8.45K

2K

PS_2[5:1]

00

000

680 nF

NC

4.75K

PD-reset

Thermal monitor interrupt.
An input from an external temperature sensor (ALERTb).

PS_3[5:1]

11

XXX

NC

PD-reset

Critical temperature fault (CTF) (active high) will
output 3.3 V if the on-die temperature sensor exceeds
a critical temperature so that the motherboard can
protect the ASIC from damage by removing power.
The CTF setpoint is 109
by default, and is
programmed during ASIC initialization. See the
advisory for AMD PowerPlay states for more details.

PD-reset

(Optional) Voltage control signal for the
memory-voltage regulator.
Note: This signal must be low (0 V) at reset
(failure to do so will prevent booting).

PD-reset

Disable MLPS: PU 10K ohm to 3.3V.
(Do not install for Mars)
Enable MLPS: PD 10K ohm to GND.
(Install for Mars)

GPIO_22_ROMCSB

GPIO_17_THERMAL_INT

AJ30
AJ31

SUN-PRO M2_FCBGA962

GPIO_19_CTF

I/O
3.3 V
(VDDR3)

O
3.3 V
(VDDR3)

GPIO_21

I/O
3.3 V
(VDDR3)

GPIO_28_FDO

I/O
3.3 V
(VDDR3)

MLPS Strap

Serial-ROM clock to ROM.
General purpose I/O or open-drain output.
BIOS-ROM chip select.
Used to enable the ROM for ROM read and program
operations.
Design: No use external VGA ROM, so use the test
points.

PD-reset

AN21
AM21
AK30
AK29

Serial-ROM output from ROM.
General purpose I/O or open-drain output.
Design: No use external VGA ROM, so use the test point.

AM19
AL19

Capacitor

X

@
RV20
8.45K_0402_1%

PS_0
PS_1
PS_2
PS_3

PX_EN

B

O

On/off regulator switch in AMD PowerXpress? (switchable
graphics) BACO mode.
High (3.3 V) switches the regulators off (enter BACO
mode).
Low (0 V) switches the regulators on. (Default)
PX_EN is tri-state before internal TEST_PG is asserted
and PERSTb is deasserted.

PD

C

2

2

@
CV23

1

@
RV27
2K_0402_1%
2

2

1

0.01U_0402_16V7K

Supports the CLKREQB feature for saving power to turn
on/off the REFCLK clock on the ASIC.

1 VGA@ 1 @
CV21
CV22
0.68U_0402_10V6K

O

@
CV20

0.01U_0402_16V7K

CLKREQB

X

+1.8VGS

Mapping to VRAM type please refer to page 6

℃

0.01U_0402_16V7K

4

A

0

3

DDC/AUX

NC
NC

VGA@

Determines whether or not the PCIe reference clock power
management capability is reported in the PCI configuration space
(otherwise known as CLKREQB).
0 = The CLKREQB power management capability is disabled
1 = The CLKREQB power management capability is enabled

1

0.1U_0402_16V4Z

2

1U_0402_6.3V6K

1

VGA@

CV17

CV18

10U_0603_6.3V6M

1

2
VGA@

Design
1
1
1
1

+TSVDD

GPIO_8

Not supported

AD39
AD37

PS_1

TESTEN

AF29
AG29

(1.8V@13mA TSVDD)

STRAP_BIF_
CLK_PM_EN

011

512 MB

AT23
AR22

AD31

PS_3

THERMAL

LV3
VGA@
2
1
BLM15BD121SN1D_0402

0

AU22
AV21

PS_1

NC
NC

VGA@

+1.8VGS

GPIO_2

010

AT21
AR20

PS_0

BACO

MLPS

GPIO_28_FDO

MarsCRB
1
1
1
1

AM23
AN23
AK23
AL24
AM24

PS_1[1]
64 MB

AU20
AT19

AM34

PS_2

DBG_VREFG

1
2

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO

1

AT17
AR16

PS_0

AUX1P
AUX1N

RV9
1K_0402_5%
VGA@

Reserved for internal use only. Must be 1 at reset.
Re-defined strap to indicate PCIe GEN3 capability.
1 = PCIe GEN3 supported.
0 = PCIe GEN3 not supported.

001

1

GPIO_30

AD28

GENLK_VSYNC

STRAP_BIF_
GEN3_EN_A

000

PS_1[2]

00xxx

GPIO_20_PWRCNTL_1
AL21

N/A

128 MB
256 MB

Reserved

GPIO_6

Reserved signal, for normal ASIC operation.

1

xx010

GPIO_5_AC_BATT

MLPS

DEBUG
TESTEN

TSVDD
120ohm
0.1u
1u
10u

NC_SVI2
NC_SVI2
NC_SVI2

GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

RV7
5.11K_0402_5%
@

3

2.00k

I2C

RV14

<39> GPU_VID3
<39> GPU_VID4

4.75k

8.45k

@
RV21
8.45K_0402_1%

@
RV22
8.45K_0402_1%

VGA@
RV23
8.45K_0402_1%

+3VGS

2

VGA@
RV68
4.75K_0402_1%

VGA@

1

VGA_SMB_CK2

VGA@
RV30
2K_0402_1%

6

QV1A
DMN66D0LDW-7 2N_SOT363-6
4

VGA_SMB_DA2

EC_SMB_CK2

<25,29,6>

EC_SMB_DA2

<25,29,6>

4

3

QV1B VGA@
DMN66D0LDW-7 2N_SOT363-6

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

VGA@
RV28
4.75K_0402_1%

5

GPU_DPRSLPVR

<39> GPU_DPRSLPVR

AJ23
AH23

AU16
AV15

NC

xx001

2

VGA_SMB_CK2
VGA_SMB_DA2

CHECK VR
IF VR Suport PSI# and DPRSLPVR PU 10K
to +3VGS:
PSI# :Low load current flag
DPRSLPVR : Deeper sleep enable flag

AT15
AR14

xx000

1

10K_8P4R_5%
VGA@

DPC

AU14
AV13

PS_0[4]

001

2

GPIO_16
GPIO_28_FDO
VGA_SMB_CK2
VGA_SMB_DA2

NC
NC

AT33
AU32

ROM_CONFIG [2:0]

1

+3VGS

8
7
6
5

NC
NC

AR32
AT31

Size of the Primary
Memory Apertures

PD(1%) Cap

2

RV13
1
2
3
4

NC
NC

AV31
AU30

Settings

1

10K_8P4R_5%
@

NC
NC

AR30
AT29

If BIOS_ROM_EN = 1, ROM_CONFIG[2:0] define the ROM type. If BIOS_ROM_EN = 0,
ROM_CONFIG[2:0] define the primary memory-aperture size. Refer to current
databooks for details.

2

JTAG_TRSTB
JTAG_TDI
JTAG_TMS
JTAG_TCK

NC
NC

Description

GPIO[13:11]

1

8
7
6
5

NC
NC

DPB

AT27
AR26

Legacy

2

RV12
1
2
3
4

NC
NC

Bits[5:1] PU(1%)

Strap Name
ROM_CONFIG[0]
ROM_CONFIG[1]
ROM_CONFIG[2]

1

+3VGS
1

NC
NC
DBG_CNTL0
NC
NC
NC
DBG_DATA0
DBG_DATA1
DBG_DATA2
DBG_DATA3
DBG_DATA4
DBG_DATA5
DBG_DATA6
DBG_DATA7
DBG_DATA8
DBG_DATA9
DBG_DATA10
DBG_DATA11
DBG_DATA12
DBG_DATA13
DBG_DATA14
DBG_DATA15
DBG_DATA16
DBG_DATA17
DBG_DATA18
DBG_DATA19
DBG_DATA20
DBG_DATA21
DBG_DATA22
DBG_DATA23

Mars MLPS configuration

AU26
AV25

MLPS Bit
PS_0[1]
PS_0[2]
PS_0[3]

2

AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

AT25
AR24

1

DPA

Primary Memory Aperture Size
Requested at PCI Configuration

AU24
AV23

2

SWAPLOCKA
SWAPLOCKB

NC
NC

1

AJ21
AK21

MUTI GFX
GENLK_CLK
GENLK_VSYNC

2

AD29
AC29

E

MLPS

UV1B

2012/09/27

Deciphered Date

2015/09/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D

Title

Main_MSIC
Size
Document Number
Custom
Date:

Rev
1.0

LA-9868P

Thursday, May 16, 2013
E

Sheet

13

of

42

A

B

C

D

E

UV1C

RV31 1

VGA@ 2 1M_0402_5%

PART 9 0F 9

MarsCRB
1
1
1
1

2

1

2

2
XTALOUT

2

+MPV18

H7
H8

+SPV18

AM10

1

XO_IN

AN9

+SPLL_VDDC

2

1

2

XTALOUT

2

NC

27MHZ 10PF +-20PPM X3G027000DA1H

2

1

CV25
15P_0402_50V8J
1 VGA@

1

XTALOUT

SPLL_PVDD

SPLL_VDDC

XO_IN2

AW34

AW35

AN10

SPLL_PVSS

AF30
AF31

NC_XTAL_PVDD
NC_XTAL_PVSS

Debug Only, for clock observation
As short as possible

AK10
CLKTESTA AL10
CLKTESTB

1

2

2

VGA@

SUN-PRO M2_FCBGA962

+0.95VS to +0.95VGS
+0.95VALW

OSC

2

+SPLL_VDDC
LV9 VGA@
(SPLL_VDDC:0.95V@100mA )
1
2
BLM15BD121SN1D_0402
1

3

OSC

NC

MPLL_PVDD
MPLL_PVDD

+0.95VGS

Design
1
1
1
1

2

AU34

1

XTALIN

XTALIN
CV24
15P_0402_50V8J
VGA@

(SPLL_PVDD:1.8V@75mA )

1

AV33

1

PLLS/XTAL

LV8 VGA@
1
2
BLM15BD121SN1D_0402

0.1U_0402_16V7K
CV80
VGA@

1U_0402_6.3V6K
CV79
VGA@

1

0.1U_0402_16V7K
VGA@
CV83

2.2U_0402_6.3V6M
CV78
VGA@

XTALIN

0.1U_0402_16V7K
VGA@
CV94

SPLL_VDDC
120ohm
0.1u
1u
2.2u

Design
1
1
1
1

2

1U_0402_6.3V6K
CV93
VGA@

2

MarsCRB
1
1
1
1

1

VGA@

YV1
4

(MPLL_PVDD:1.8V@130mA )

+SPV18

+1.8VGS

2.2U_0402_6.3V6M
CV81
VGA@

SPLL_PVDD
120ohm
0.1u
1u
2.2u

+MPV18
LV7 VGA@
1
2
BLM15BD121SN1D_0402

2.2U_0402_6.3V6M
VGA@
CV92

1

Design
1
1
1
1

1U_0402_6.3V6K
CV82
VGA@

+1.8VGS

MarsCRB
1
1
1
1

MPLL_PVDD
220ohm
0.1u
1u
2.2u

+3VS to +3VGS

+0.95VGS
+3VGS

3

Vgs=10V,Id=14.5A,Rds=6mohm

3

+3VS

PXS_PWREN

1

<39,8> PXS_PWREN

2

3
2

QV4
VGA@

2

1

VGA@ CV104
0.01U_0402_25V7K

VGA@
QV9A

2N7002DW-T/R7_SOT363-6

Vgs=-4.5V,Id=3A,Rds<97mohm

1

AO3413_SOT23

2
1

PXS_PWREN#

6

VGA@
QV8A

5

VGA@
RV46
47K_0402_5%
1
2

2N7002DW-T/R7_SOT363-6

3 1
5

2@
CV103
0.1U_0402_16V7K

4

PXS_PWREN#

VGA@
QV9B
2N7002DW-T/R7_SOT363-6

VGA@
QV8B
2N7002DW-T/R7_SOT363-6
4

6

2
1 RV48
B+
220K_0402_5%
VGA@
2

1

VGA@ RV49
2
1

VGA@ CV106

2

0.1U_0402_25V6

1

820K_0402_5%

QV3_GATE

FDS6676AS_SO8

VGA@
RV44
100K_0402_5%

3 1

2
RV45
VGA@

VGA@
RV43
470_0805_5%

470_0805_5%

1
2
3
4

G

S
S
S
G

D

D
D
D
D

S

8
7
6
5

2

+3VALW
VGA@
QV3

+3VGS

1

4

4

2012/09/27

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2015/09/27

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

BACO POWER
Rev
1.0

LA-9868P

Thursday, May 16, 2013

Sheet
E

14

of

42

A

B

C

D

E

+1.8VALW to +1.8VGS
+1.5V to +1.5VGS

Only for Kabini
1

1

+1.5V

VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
UV3
1
2

@

1 CV96

VGA_PWRGD

<39,8> VGA_PWRGD
+1.8VALW

VGA_PWRGD

5
6
7

VOUT1
VOUT1

ON1

CT1

VBIAS

GND

ON2

CT2

VIN2
VIN2

VOUT2
VOUT2
GPAD

14
13
12

2

1

+1.5VGS_LS
CV95 180P_0402_50V8J
1
2
VGA@

PAD-OPEN 4x4m 2
@ CV97

11
10
9
8

CV99 330P_0402_50V7K
1
2
VGA@
PJ13 @
1
+1.8VGS_LS

15

1
+1.8VGS
2

PAD-OPEN 4x4m 2
@ CV98

1

2

1U_0402_6.3V6K

2

1

CV100

0.1U_0402_10V7K

TPS22966DPUR_SON14_2X3
@

0.1U_0402_10V7K

1U_0402_6.3V6K

+5VALW

2

3
4

+1.5VGS
PJ12 @

VGA@

VIN1
VIN1

2

3

3

4

4

2012/09/27

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2015/09/27

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

BACO POWER
Rev
1.0

LA-9868P

Thursday, May 16, 2013

Sheet
E

15

of

42

A

+VDDC_CT
LV4 VGA@

(VDD_CT:1.8V@13mA )

1

2

1U_0402_6.3V6K
VGA@
CV52

10U_0603_6.3V6M
CV51
VGA@

1
2
BLM15BD121SN1D_0402

1

2

CORE

1

2
+VDDC_CT

+VDDR3
LV5
VGA@
2
1
BLM15BD121SN1D_0402
1U_0402_6.3V6K
CV42
VGA@

(VDDR3:3.3V@25mA)

1

2

1U_0402_6.3V6K
VGA@
CV54

+3VGS

1

2

1

+VDDR3

I/O
AF23
VDDR3
AF24 VDDR3
AG23
VDDR3
AG24
VDDR3
AD12
AF11
AF12
AF13

2

DVP
VDDR4
VDDR4
VDDR4
VDDR4

VOLTAGE
SENESE
AF28 FB_VDDC

AG28
TV44

<39> VSS_GPU_SENSE

AH29

ISOLATED
CORE I/O

3

<39> VCC_GPU_SENSE

FB_VDDCI
FB_GND

VGA@

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

AF15
VDDR4
AG11
VDDR4
AG13 VDDR4
AG15
VDDR4

Route as differential pair

BIF_VDDC
BIF_VDDC

VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI

N27
T27
AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18

PCIE_VDDC:
0.95 V @ 1.88 A (PCIe Gen 2.0)
0.95 V @ 2.50 A (PCIe Gen 3.0)

1

2

1

2

1

2

1

2

1

2

1

2

10U_0603_6.3V6M
CV49
VGA@

2

1

2

1

+0.95VGS

1

2

1

2

Design
2
1

PCIE_VDDC
1u
10u

MarsCRB
7
2

Design
7
2

BIF_VDDC
1u
10u

Mars check list
1
1

1

1

2

(BIF_VDDC: 0.95V@1.4A)

+0.95VGS

MarsCRB
2
1

+0.95VGS

+0.95VGS

1

PCIE_PVDD
1u
10u

2

10U_0603_6.3V6M
CV50
VGA@

LEVEL
TRANSLATION
VDD_CT
VDD_CT
VDD_CT
VDD_CT

BACO

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

2

1U_0402_6.3V6K
CV48
VGA@

AF26
AF27
AG26
AG27

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

2

1U_0402_6.3V6K
CV47
VGA@

2

10U_0603_6.3V6M
CV32
VGA@

1

Maximum Current on +1.8VGS:
"Sun": ~0.5 A

1

1U_0402_6.3V6K
VGA@
CV41

2

1U_0402_6.3V6K
CV31
VGA@

1

1

1U_0402_6.3V6K
CV46
VGA@

2

1

1U_0402_6.3V6K
CV45
VGA@

1

AA31
AA32
AA33
AA34
W30
Y31
V28
W29
AB37

10U_0603_6.3V6M
CV69
@

2

1U_0402_6.3V6K
CV30
VGA@

1

NC
NC
NC
NC
NC
NC
NC_BIF_VDDC
NC_BIF_VDDC
PCIE_PVDD

1U_0402_6.3V6K
CV44
VGA@

2

MEM I/O
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

1U_0402_6.3V6K
CV43
VGA@

1

AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

PCIE

2

Design
1
2
0
1

+1.8VGS

2

1

2.2U_0402_6.3V6M
VGA@
CV39

2

2.2U_0402_6.3V6M
CV40
VGA@

1

2.2U_0402_6.3V6M
CV37
VGA@

2

2.2U_0402_6.3V6M
CV38
VGA@

1

+1.5VGS

1U_0402_6.3V6K
@
CV68

Mars check list
1
3
1
0

(VDDR1:1.5V@1.5A)

1U_0402_6.3V6K
@
CV67

VDDR3
120ohm
1u
10u
0.1u

+1.8VGS

10U_0603_6.3V6M
CV35
VGA@

Design
1
1
1
1

E

(PCIE_PVDD: 1.80V@100mA)

+1.8VGS

PART 5 0F 9

2.2U_0402_6.3V6M
CV36
VGA@

MarsCRB
1
1
1
1

D

UV1E

+1.5VGS

0.1U_0402_16V7K
CV53
VGA@

VDD_CT
120ohm
0.1u
1u
10u

C

0.1U_0402_16V7K
VGA@
CV55

Design
0
0
5
3

10U_0603_6.3V6M
VGA@
CV34

MarsCRB
5
5
5
3

10U_0603_6.3V6M
CV33
VGA@

1

VDDR1
0.01u
0.1u
2.2u
10u

B

Design
1
1

Maximum Current on +0.95VGS:
"Sun": ~4.0 A for PCIe GEN 3.0 designs
(estimated)

2

+VGA_CORE

+VGA_CORE

2

AH22
AH27
AH28
M26
N24
R18
R21
R23
R26
T17
T20
T22
T24
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

+VGA_CORE

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

+VGA_CORE

3

SUN-PRO M2_FCBGA962

Need check all power current and decoupling capacitors
after got SUN databook and reference schematic.
4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Deciphered Date

2015/09/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Power
Size
C
Date:

A

B

C

D

Document Number

Rev
1.0

LA-9868P
Thursday, May 16, 2013

Sheet
E

16

of

42

A

B

C

D

PART 4 0F 9

PART 3 0F 9

M27
M12
AH12

H27
G27

CLKA1
CLKA1B

J14
H14

CASA0B
CASA1B

+1.5VGS

J21
G19

CLKA0
CLKA0B

RASA0B
RASA1B

Close to pin Y12 and AA12

1

ADBIA0/ODTA0
ADBIA1/ODTA1

A34
E30
E26
C20
C16
C12
J11
F8

RV72
40.2_0402_1%
VGA@

+MVREFDB_SB

K23
K19

CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1

M13
K16

MVREFDA
MVREFSA

CKEA0
CKEA1

K21
J20

NC
NC
NC

WEA0B
WEA1B

K26
L15

MAA0_8/MAA_13
MAA1_8/MAA_14
MAA0_9/MAA_15
MAA1_9/RSVD

H23
J19
M21
M20

NC
NC

2

CV159
1U_0402_6.3V6K
VGA@

+MVREFDB_SB

Y12
AA12

GDDR5/DDR3

MEMORY INTERFACE B

DQB0_0
DQB0_1
DQB0_2
DQB0_3
DQB0_4
DQB0_5
DQB0_6
DQB0_7
DQB0_8
DQB0_9
DQB0_10
DQB0_11
DQB0_12
DQB0_13
DQB0_14
DQB0_15
DQB0_16
DQB0_17
DQB0_18
DQB0_19
DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31
DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8
DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31

S1G
S1G@
X76xxxxxLx1

WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7

EDCB0_0/QSB_0
EDCB0_1/QSB_1
EDCB0_2/QSB_2
EDCB0_3/QSB_3
EDCB1_0/QSB_4
EDCB1_1/QSB_5
EDCB1_2/QSB_6
EDCB1_3/QSB_7
DDBIB0_0/QSB_0B
DDBIB0_1/QSB_1B
DDBIB0_2/QSB_2B
DDBIB0_3/QSB_3B
DDBIB1_0/QSB_4B
DDBIB1_1/QSB_5B
DDBIB1_2/QSB_6B
DDBIB1_3/QSB_7B
ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1

MVREFDB
MVREFSB

ZZZ3

H1G
H1G@
X76xxxxxLx2

ZZZ4

MAB0_8/MAB_13
MAB1_8/MAB_14
MAB0_9/MAB_15
MAB1_9/RSVD

H2G

S2G@
X76xxxxxLx3

Memory clock 900MHz
3

GPU Type
SUN PRO-M2

Memory Bus Width
64bit

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

H3
H1
T3
T5
AE4
AF5
AK6
AK5

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

T7
W7

ODTB0
ODTB1

L9
L8

CLKB0
CLKB0#

AD8
AD7

CLKB1
CLKB1#

T10
Y10

RASB0#
RASB1#

W10
AA10

CASB0#
CASB1#

P10
L10

CSB0#_0

AD10
AC10

CSB1#_0

U10
AA11

CKEB0
CKEB1

N10
AB11

WEB0#
WEB1#

T8
W8
U12
V12

MAB13
MAB14
MAB15

AH11

DRAM_RST#_R

H2G@

DRAM_RST

SUN-PRO M2_FCBGA962

SUN-PRO M2_FCBGA962

R_pu & R_pd resistor:
0402 1% resistors are required.

Manufacturer P/N

Hynix

SA00003YO70

H5TQ2G63DFR-11C
MT41K128M16JT-107G:K

SUN PRO-M2

64bit

Micron

SA00005XB00

SUN PRO-M2

64bit

Samsung

SA00005SH00

K4W2G1646E-BC11

Size per part

Configuration

X7648051L01

2Gbit

128M*16

1GB/4pcs

0

0

0

X7648051L03

2Gbit

128M*16

1GB/4pcs

0

0

1

X7648051L04

2Gbit

128M*16

1GB/4pcs

1

1

1

X76 P/N

DQMB#[0..7]

QSB[0..7]

<19>

<19>

QSB[0..7]

QSB#[0..7]

QSB#[0..7]

<19>

1

B_BA2 <19>
B_BA0 <19>
B_BA1 <19>

ODTB0 <19>
ODTB1 <19>
CLKB0 <19>
CLKB0# <19>
2

CLKB1 <19>
CLKB1# <19>
RASB0# <19>
RASB1# <19>
CASB0# <19>
CASB1# <19>
CSB0#_0 <19>
CSB1#_0 <19>
CKEB0 <19>
CKEB1 <19>
WEB0# <19>
WEB1# <19>

RV36 VGA@
1
2
10_0402_1%

VGA@
RV71
4.99K_0402_1%

Compal P/N

<19>

MAB[0..15]

DQMB#[0..7]

RV70 VGA@
1
2
51.1_0402_1%

DRAM_RST# <19>

X76xxxxxLx4

RC99 10K pull down
VRAM Vendor

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

ZZZ5

S2G

VGA@
VGA@

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

WEB0B
WEB1B
ZZZ2

MEM_CALRP0

1

RV73
100_0402_1%
VGA@

K20
K17
K24
K27

15mil

2

DDBIA0_0/QSA_0B
DDBIA0_1/QSA_1B
DDBIA0_2/QSA_2B
DDBIA0_3/QSA_3B
DDBIA1_0/QSA_4B
DDBIA1_1/QSA_5B
DDBIA1_2/QSA_6B
DDBIA1_3/QSA_7B

C34
D29
D25
E20
E16
E12
J10
D7

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

Total Memory Size/Qty PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1]

R_pu
RV20

R_pd
RV27

NC

4.75K

RV20

RV27

8.45K

RV20
4.75K

VGA@
CV158
120P_0402_50V9

1

2 120_0402_1%

EDCA0_0/QSA_0
EDCA0_1/QSA_1
EDCA0_2/QSA_2
EDCA0_3/QSA_3
EDCA1_0/QSA_4
EDCA1_1/QSA_5
EDCA1_2/QSA_6
EDCA1_3/QSA_7

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

2

RV34 1 VGA@

A32
C32
D23
E22
C14
A14
E10
D9

MAB[0..15]

MDB[0..63]

2

L27
N12
AG12

WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7

<19> MDB[0..63]

1

L18
L20

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

1

2

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_BA2
MAA1_6/MAA_BA0
MAA1_7/MAA_BA1

2

1

GDDR5/DDR3
DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

MEMORY INTERFACE A

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

E

UV1I

UV1H

3

Place all these components close to GPU (Within 25mm)
and keep all component close to each other

2K

RV27
NC

Memory clock 1GHz RC95 10K pull high

4

GPU Type

Memory Bus Width

SUN PRO-M2

64bit

SUN PRO-M2

VRAM Vendor
Hynix
Samsung

64bit

Compal P/N
SA000065300
SA000068U20

Manufacturer P/N
H5TQ2G63DFR-N0C
K4W2G1646E-BC1A

X76 P/N
X7648051L02
X7648051L05

Size per part

Configuration

2Gbit

128M*16

2Gbit

Total Memory Size/Qty PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1]
1GB/4pcs
1GB/4pcs

128M*16

0
1

1

0
0

R_pd

RV20

RV27

4.53K

2K

RV20

RV27

3.4K

10K

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

1

R_pu

2012/09/27

Deciphered Date

2015/09/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

MEM Interface
Size
C
Date:

A

B

C

D

Document Number

Rev
1.0

LA-9868P
Thursday, May 16, 2013

Sheet
E

17

of

42

A

B

C

D

E

UV1G
PART 6 0F 9
AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

1

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27

2

3

4

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

VGA@

UV1F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC

PART 8 0F 9

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20

DP_VDDR

AN24
AP24
AP25
AP26
AU28
AV29
AP20
AP21
AP22
AP23
AU18
AV19

DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC

(DP_VDDR: 1.8V@20mA)

DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR

DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR

CALIBRATION

AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20

AW28

AW18

AM39

AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

+0.95VGS

AP13
AT13
AP14
AP15

NC

NC

DP_CALR

VGA@

AN27
AP27
AP28
AW24
AW26
AN29
AP29
AP30
AW30
AW32
AN17
AP16
AP17
AW14
AW16
AN19
AP18
AP19
AW20
AW22
AN34
AP39
AR39
AU37
AF39
AH39
AK39
AL34
AV27
AR28
AV17
AR18
AN38
AM35
AN32

2

SUN-PRO M2_FCBGA962

3

AG22

4

VSS_MECH
VSS_MECH
VSS_MECH

A39
AW1
AW39

2012/09/27

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2015/09/27

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SUN-PRO M2_FCBGA962

Date:

A

1

(DP_VDDC: 0.95V@20mA)

DP GND

+1.8VGS
AH34
AJ34
AF34
AG34
AM37
AL38
AM32

AP31
AP32
AN33
AP33
AL33
AM33
AK33
AK34
AN31

B

C

D

PWR_GND
Rev
1.0

LA-9868P

Thursday, May 16, 2013

Sheet
E

18

of

42

5

4

3

2

1

CHANNEL B: 512MB/1024MB DDR3
UV6

<17> QSB[7..0]

<17> QSB#[7..0]

QSB[7..0]

<17> CLKB0
<17> CLKB0#
<17> CKEB0

QSB#[7..0]

<17>
<17>
<17>
<17>
<17>

K1
L2
J3
K3
L3

ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#

VGA@

C

J7
K7
K9

QSB3
QSB1

F3
C7

DQMB#3
DQMB#1

E7
D3

QSB#3
QSB#1

G3
B7

2
40.2_0402_1%

CLKB0 1
RV78
VGA@

<17> DRAM_RST#

2
40.2_0402_1%

T2
L8

1

VGA@
CV160
0.01U_0402_16V7K

RV80
243_0402_1%
VGA@

J1
L1
J9
L9

+1.5VGS

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2
40.2_0402_1%

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#

K1
L2
J3
K3
L3

QSB2
QSB0

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMB#2
DQMB#0

E7
D3

QSB#2
QSB#0

G3
B7

DRAM_RST# T2
L8

RV81
243_0402_1%
VGA@

J1
L1
J9
L9

UV8

UV7

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDB17
MDB19
MDB16
MDB22
MDB20
MDB21
MDB18
MDB23

D7
C3
C8
C2
A7
A2
B8
A3

MDB1
MDB7
MDB2
MDB4
MDB3
MDB5
MDB0
MDB6
+1.5VGS

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU

RESET
ZQ/ZQ0

<17>
<17>
<17>
<17>
<17>

K1
L2
J3
K3
L3

ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

QSB4
QSB7

F3
C7

DQMB#4
DQMB#7

E7
D3

QSB#4
QSB#7

G3
B7

DRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

J7
K7
K9

<17> CLKB1
<17> CLKB1#
<17> CKEB1

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M2
N8
M3

B_BA0
B_BA1
B_BA2

+1.5VGS

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

M8
H1

+VREFC_A3_B

J1
L1
J9
L9

RV82
243_0402_1%
VGA@

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

96-BALL
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
@

E3
F7
F2
F8
H3
H8
G2
H7

MDB33
MDB37
MDB35
MDB39
MDB32
MDB36
MDB34
MDB38

D7
C3
C8
C2
A7
A2
B8
A3

MDB58
MDB60
MDB56
MDB62
MDB57
MDB63
MDB59
MDB61

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15

+1.5VGS
B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

M2
N8
M3

CLKB1
CLKB1#
CKEB1

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#

K1
L2
J3
K3
L3

QSB6
QSB5

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMB#6
DQMB#5

E7
D3

QSB#6
QSB#5

G3
B7

DRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

B_BA0
B_BA1
B_BA2

+1.5VGS

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

M8
H1

+VREFC_A4_B

J1
L1
J9
L9

RV83
243_0402_1%
VGA@

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDB49
MDB53
MDB51
MDB55
MDB48
MDB54
MDB50
MDB52

D7
C3
C8
C2
A7
A2
B8
A3

MDB47
MDB43
MDB45
MDB42
MDB44
MDB40
MDB46
MDB41

D

+1.5VGS
B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

+1.5VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

C

96-BALL
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
@

96-BALL
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
@

VGA@
CV161
0.01U_0402_16V7K

2

1

2
40.2_0402_1%

CLKB0
CLKB0#
CKEB0

96-BALL
SDRAM DDR3
K4W1G1646G-BC11_FBGA96
@

VGA@

CLKB1# 1
RV85

M2
N8
M3

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

B_BA0
B_BA1
B_BA2

+1.5VGS

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DML
DMU

VGA@

CLKB1 1
RV84

MDB15
MDB10
MDB14
MDB11
MDB13
MDB9
MDB12
MDB8

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

2

2

1

CLKB0# 1
RV79

D7
C3
C8
C2
A7
A2
B8
A3

M8
H1

+VREFC_A2_B

1

DQMB#[7..0]

<17> DQMB#[7..0]

M2
N8
M3

<17> B_BA0
<17> B_BA1
<17> B_BA2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDB24
MDB26
MDB30
MDB31
MDB25
MDB27
MDB28
MDB29

2

MAB[15..0]

<17> MAB[15..0]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

1

MDB[0..63]

<17> MDB[0..63]

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

1

D

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15

VREFCA
VREFDQ

2

M8
H1

+VREFC_A1_B

2

UV5

Supported Memory Configurations: Up to 4 Gbit/part for DDR3.
+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS
B

1

VGA@
RV88
4.99K_0402_1%

15mil

2

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

close to UV7 UV8

VGA@

1

2

VGA@

1

2

VGA@

1

2

VGA@

1

2

VGA@

1

2

VGA@

CV165

2

1

2

VGA@

1

2

VGA@

1

2

VGA@

1

2

VGA@

1

2

VGA@

1U_0402_6.3V6K
CV198

2

1U_0402_6.3V6K
CV197

CV164

2
1

1U_0402_6.3V6K
CV196

2

1

1

1

1U_0402_6.3V6K
CV195

close to UV9 UV10

2

2

close to UV9 UV10

+1.5VGS

1U_0402_6.3V6K
CV194

1

1

VGA@

1U_0402_6.3V6K
CV193

2

1U_0402_6.3V6K
CV188

1

1U_0402_6.3V6K
CV187

2

1U_0402_6.3V6K
CV186

1

1U_0402_6.3V6K
CV184

2

1U_0402_6.3V6K
CV183

1

0.1U_0402_16V7K
CV173

2

0.1U_0402_16V7K
CV172

1

0.1U_0402_16V7K
CV171

2

0.1U_0402_16V7K
CV170

1

0.1U_0402_16V7K
CV169

0.1U_0402_16V7K
CV168

0.1U_0402_16V7K
CV167

0.1U_0402_16V7K
CV166

2

22U_0603_6.3V6M

VGA@

1

CV179

A

2

2

close to UV7 UV8

+1.5VGS
+1.5VGS

1

+VREFC_A4_B
VGA@
RV93
4.99K_0402_1%

1

VGA@

1U_0402_6.3V6K
CV185

VGA@

0.1U_0402_16V7K

CV163

VGA@
RV92
4.99K_0402_1%

1

2

2

CV162

+1.5VGS

0.1U_0402_16V7K

2

2

15mil

+VREFC_A3_B

1

1

1

VGA@

15mil

+VREFC_A2_B
VGA@
RV91
4.99K_0402_1%

0.1U_0402_16V7K

2

15mil
+VREFC_A1_B

VGA@
RV90
4.99K_0402_1%

VGA@
RV89
4.99K_0402_1%

2

VGA@
RV87
4.99K_0402_1%

0.1U_0402_16V7K

1

1
2

VGA@
RV86
4.99K_0402_1%

1

B

1

2

A

VGA@

VGA@

Compal Secret Data

Security Classification
Issued Date

2012/09/27

Deciphered Date

2015/09/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

VRAM Channel B
Size
C
Date:

5

4

3

2

Compal Electronics, Inc.
Document Number

Rev
1.0

LA-9868P
Thursday, May 16, 2013

Sheet
1

19

of

42

5

D

4

<6> EDP_LCD_TXOUT0+_R

EDP_LCD_TXOUT0+_R

<6> EDP_LCD_TXOUT0-_R
<6> EDP_LCD_TXOUT1+_R

EDP_LCD_TXOUT1+_R

<6> EDP_LCD_TXOUT1-_R

EDP_LCD_TXOUT1-_R

<6> EDP_LCD_TXOUT2+_R

EDP_LCD_TXOUT2+_R

<6> EDP_LCD_TXOUT2-_R

EDP_LCD_TXOUT2-_R

LCD_TXCLKEDP_LVDS_CLK

<6> EDP_LVDS_CLK

EDP_LVDS_DATA

<6> EDP_LVDS_DATA

1

Need check eDP&LVDS both 3V power rail.

If it's EPD, they're become
LCD_TXOUT2+_R = EDP_TX0+
LCD_TXOUT2-_R = EDP_TX0LCD_TXOUT1+_R = EDP_TX1+
LCD_TXOUT1-_R = EDP_TX1LVDS_CLK = EDP_AUXP
LVDS_DATA = EDP_AUXN

LCD_TXCLK+

<6> LCD_TXCLK-

2

LCD_VDD

EDP_LCD_TXOUT0-_R

<6> LCD_TXCLK+

3

D

+3VS

+LCD_VDD

W=60mils

W=60mils

U16

1.5A

5
4

+LCD_VDD_SS

VOUT

I rush=1.5A

GND

2

SS
EN

1

1

VIN

3

APL3512ABI-TRG_SOT23-5

2

C17
1500P_0402_50V7K
<6> LCD_ENVDD

2

+5VS
JLVDS

GND
GND
GND
GND
GND
B

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1 @
R390

USB20_P3_R
USB20_N3_R
+3VS_LVDS_CAM
+LCD_VDD

2
0_0603_5%

R112
100K_0402_5%

20mils
1

+5VS_LVDS_TOUCH
USB20_N4_R
USB20_P4_R
BKOFF#
INT_MIC_DATA
INT_MIC_CLK

INT_MIC_DATA <26>
INT_MIC_CLK <26>
+3VS

1
R389

@

2
0_0603_5%
+LCD_VDD

+3VS
EDP_LVDS_CLK
EDP_LVDS_DATA
EDP_LCD_TXOUT0-_R
EDP_LCD_TXOUT0+_R
EDP_LCD_TXOUT1-_R
EDP_LCD_TXOUT1+_R
EDP_LCD_TXOUT2-_R
EDP_LCD_TXOUT2+_R

C

20mils
Irush=1.5A

60mils

+3VS

LCD_INV

ESD@

D29

4

USB20_P3_R

4

3

3

USB20_N3_R

+LCD_INV

LCD_TXCLKLCD_TXCLK+

+3VS

5

Vbus

GND

2
C22

Irush=1.5A

+LCD_INV

60mils

@EMI@

31
32
33
34
35

6

INT_MIC_DATA

pin1-4 Touch function for panel
pin5-10 For Webcam with single or dual MIC
pin11-30 For LVDS or EDP panel

@
STARC_111H30-000000-G4-R

B+

1.5A

EDP_LVDS_HPD <6>

LED_PWM
BKOFF#_R

6

1

SC300001400

1

1

2

L2 2 EMI@
1
FBMA-L11-201209-221LMA30T_0805

0.1U_0402_25V6

C

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

INT_MIC_CLK

close to LVDS conn.

B

LCD Control

Carmera & Touch Screen
1

RB751V40_SC76-2

4

2

1

4

USB20_P3_R

2

1

USB20_N3_R

1
D15

BKOFF#_R

1

WCM-2012-900T_0805

<7> USB20_N4
<7> USB20_P4

2

2

1

4

USB20_N4_R

1

USB20_P4_R

2012/09/27

Issued Date

Deciphered Date

2015/09/27

Date:

4

3

2

LCD_ENBKL <29,6>
BKOFF#

BKOFF# <29>

SN74AHC1G08DCKR_SC70-5

A

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Reserve for EMI request

1

Compal Electronics, Inc.

Compal Secret Data

Security Classification

WCM-2012-900T_0805
TOUCH_EMI@
1
2
R105
0_0402_5%

5

IN1

IN2

1
2
0_0402_5%
R147
LVDS@

L4

4

EDP@

O

LVDS@

2

TOUCH_EMI@
2
1
0_0402_5%
R104

@TOUCH_EMI@
3
3

U17

2
4
RB751V40_SC76-2

R113
10K_0402_5%

Reserve for EMI request

A

2
0_0402_5%

EDP@ 1
R103

P

<7> USB20_N3

5

3

G

3

2

<7> USB20_P3

+3VS
R131
47K_0402_5%

L3

3

CAM_EMI@

Reserve for eDP panel potential issue

LED_PWM

1

D6 2

<6> LCD_INT_PWM

2

LVDS/EDP W/ CAMERA
Document Number

Rev
1.0

LA-9868P
Sheet

Thursday, May 16, 2013
1

20

of

42

5

4

3

2

1

+HDMI_5V_OUT
RPY2

RY1
2
HDMI_HPD_U 1
1K_0402_5%

2

P
A
G

2

Y

1

4

HDMI_HPD

A

Y

L

L

L

H

H

H

X

Z

74AHCT1G125GW_SOT353-5

3

+3VS

UY1

CY4
0.1U_0402_16V4Z

OE#
L

1

5

RY2
100K_0402_5%

4.7K_8P4R_5%

D

+3VS

1

D

HDMI_HPD_C

2

APU_HDMI_CLK
APU_HDMI_DATA
HDMI_SCLK
HDMI_SDATA

1

+HDMI_5V_OUT

8
7
6
5

OE#

1
2
3
4

+3VS

2

RY3
2.2K_0402_5%

2

HDMI_HPD

HDMI_HPD <6,8>

G

3

APU_HDMI_CLK

HDMI POWER CIRCUIT

D

APU_HDMI_DATA

HDMI_SCLK

QY1
BSH111_SOT23-3

G

<6> APU_HDMI_DATA

1
S

2

<6> APU_HDMI_CLK

3

1

VIN = 5V, IOUT = 0.5A , RDS(ON)
Current Limit: TYP=0.8A ; MAX=1A

HDMI_SDATA

TYP=95m

; MAX=115m

D

S

QY2
BSH111_SOT23-3

+HDMI_5V_OUT
UY2

1
CY18

2

1

3

C

0.1U_0402_10V7K

2

OUT

IN

5

+5VS

GND
FLG

EN

4

C

AP2151DWG-7_SOT25-5

SA00006H000
LY1
<6> APU_HDMI_CLK<6> APU_HDMI_CLK+

CY2

1

2 0.1U_0402_16V7K

HDMI_TXC-

1

CY1

1

2 0.1U_0402_16V7K

HDMI_TXC+

4

1
4

EMI@

2
3

2

HDMI Connector

3

JHDMI

KINGCORE WCM-2012HS-900T
HDMI_HPD_C
+HDMI_5V_OUT
HDMI_SDATA
HDMI_SCLK
LY2
<6> APU_HDMI_TX0<6> APU_HDMI_TX0+

CY5

1

2 0.1U_0402_16V7K

HDMI_TXD0-

1

CY3

1

2 0.1U_0402_16V7K

HDMI_TXD0+

4

1
4

EMI@

2
3

2

HDMI_R_CK-

3

HDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1-

KINGCORE WCM-2012HS-900T

HDMI_R_D1+
HDMI_R_D2B

HDMI_R_D2+
LY3
<6> APU_HDMI_TX1<6> APU_HDMI_TX1+

CY7

1

2 0.1U_0402_16V7K

HDMI_TXD1-

1

CY6

1

2 0.1U_0402_16V7K

HDMI_TXD1+

4

2

4

3

@

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKCK_shield
CK+
D0D0_shield
D0+
D1D1_shield
GND
D1+
GND
D2D2_shield GND
GND
D2+

23
22
21
20

B

TYCO_2041343-1~D

EMI@

1

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

2
RPY3

3

KINGCORE WCM-2012HS-900T

HDMI_R_CK+
HDMI_R_CKHDMI_R_D0+
HDMI_R_D0-

1
2
3
4

HDMI_R_D2+
HDMI_R_D2HDMI_R_D1+
HDMI_R_D1-

1
2
3
4

8
7
6
5

499_8P4R_1%
RPY4

LY4
<6> APU_HDMI_TX2<6> APU_HDMI_TX2+

CY9

1

2 0.1U_0402_16V7K

HDMI_TXD2-

1

CY8

1

2 0.1U_0402_16V7K

HDMI_TXD2+

4

EMI@

1

2

4

3

2

8
7
6
5

499_8P4R_1%

3

QY3

HDMI45@

+5VS

A

1

ZZZ

HDMI Royalty

D

3

KINGCORE WCM-2012HS-900T

S
2N7002KW_SOT323-3

2
G

RO0000003HM

A

HDMI W/Logo + HDCP

HDMI W/O Logo: RO0000001HM
HDMI W/Logo: RO0000002HM
HDMI W/Logo + HDCP: RO0000003HM

2012/09/27

Issued Date

please manually load
this virtual material to 45@ BOM

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2015/09/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

HDMI W/O CEC
Document Number

Rev
1.0

LA-9868P
Sheet

Thursday, May 16, 2013
1

21

of

42

5

4

3

2

1

D

D

<6> APU_CRT_R

APU_CRT_R

L8

1

<6> APU_CRT_G

APU_CRT_G

L9

1

<6> APU_CRT_B

APU_CRT_B

L10

1

CRT_EMI@

CRT_EMI@
CRT_EMI@

2 NBQ100505T-800Y_0402

APU_CRT_R_L

2 NBQ100505T-800Y_0402

APU_CRT_G_L

2 NBQ100505T-800Y_0402

APU_CRT_B_L
CRT@

CRT@

CRT@

2

C165

1

2

CRT@

C166

1

2

C167

1

2

2.2P_0402_50V8C

2

1

C164

2.2P_0402_50V8C

CRT@

1

2.2P_0402_50V8C

2

C163

2.2P_0402_50V8C

1

2.2P_0402_50V8C

2
R175

1

150_0402_1%

2
1 R174
CRT@

C162

2.2P_0402_50V8C

CRT@

C

150_0402_1%

1 R173

150_0402_1%

2

JCRT
APU_CRT_R_L
CRT_DDC_DAT
APU_CRT_G_L
HSYNC
APU_CRT_B_L

CRT@

CRT@

T65 PAD

+HDMI_5V_OUT

VSYNC
T66 PAD

CRT_DDC_CLK

USE HDMI POWER

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

C

G
G

16
17

C-H_13-12201513CP
@

+HDMI_5V_OUT

2

2

+3VS

7

VCC_VIDEO

VIDEO1

8
3

APU_CRT_R_L

4

APU_CRT_G_L

5

APU_CRT_B_L

2

+3VS

BYP

+HDMI_5V_OUT

CRT@
1
2
0.22U_0402_16V7K
C148

CRT@

VCC_SYNC

APU_CRT_DATA

10

APU_CRT_CLK

11

APU_CRT_VSYNC

13

VIDEO2

DDC_IN1

VIDEO3

R176
4.7K_0402_5%
CRT@

R153
4.7K_0402_5%
CRT@

1

<6> APU_CRT_DATA

VCC_DDC

2

U49

1

1

C261
0.1U_0402_10V7K
1 @
+HDMI_5V_OUT

B

B

<6> APU_CRT_CLK

<6> APU_CRT_VSYNC

DDC_IN2

DDC_OUT1

SYNC_IN1

DDC_OUT2

9

CRT_DDC_DAT

12

CRT_DDC_CLK
R62

<6> APU_CRT_HSYNC

15

APU_CRT_HSYNC

SYNC_IN2

SYNC_OUT1

14

CRT@

1

VSYNC_R
R63

6

GND

SYNC_OUT2

16

HSYNC_R

1

2 22_0402_5%
CRT@

VSYNC

2 22_0402_5%

HSYNC

TPD7S019-15DBQR_SSOP16

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Issued Date

Deciphered Date

2015/09/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

CRT
Document Number

Rev
1.0

LA-9868P
Sheet

Thursday, May 16, 2013
1

22

of

42

5

4

3

2

1

Slot 1 Half PCIe Mini Card-WLAN
+3V_WLAN

WLAN&BT Combo module circuits

JWLAN
BT_ON

1 RM1

<8> CLKREQ_WLAN#

2 BT_CTRL_R
@ 0_0402_5%

PJ11
D

2

+3V_WLAN

1

<7> CLK_WLAN#
<7> CLK_WLAN

+3VS

JUMP_43X39
@

<5> PCIE_WLANTX_ARX_N2
<5> PCIE_WLANTX_ARX_P2

2
0.1U_0402_10V7K

1

CM3

CM2

2

2

4.7U_0603_6.3V6K

0.1U_0402_10V7K
1
1
CM1

<5> PCIE_ATX_C_WLANRX_N2
<5> PCIE_ATX_C_WLANRX_P2

40 mils

+3V_WLAN

+3V_WLAN

<29> E51_TXD
<29> E51_RXD

E51_TXD
E51_RXD

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53

Debug card using

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1

GND2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

BT
on module

BT
on module

Enable

Disable

H

L

BT_ON

D

WL_OFF# <29>
APU_PCIE_RST# <12,25,8>

APU_SCLK0 <10,11,8>
APU_SDATA0 <10,11,8>
USB20_N1 <7>
USB20_P1 <7>

From EC

BT

BT_ON

<29> BT_ON

1 RM2
2 E51_RXD
1K_0402_5%

For isolate BT_CTRL and
Compal Debug Card.

54

LCN_DAN08-52406-0500
@

C

C

SATA HDD Conn.

SATA ODD Conn

+5VS_ODD
+5VS

1.1A

Place closely JHDD SATA CONN.

1.2A

1
1

C185
10U_0805_10V4Z

1

2

2

C186
0.1U_0402_10V7K

1

C187
0.1U_0402_10V7K

2

2

1

1
C189
10U_0805_10V4Z

2

C192
0.1U_0402_10V7K

2

C193
0.1U_0402_10V7K

Place components closely ODD CONN.

B

B

JHDD

23
24

GND
GND

A

Close to JHDD

@

GND
A+
AGND
BB+
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
DAS/DSS
GND
V12
V12
V12

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

SATA_ATX_C_DRX_P0
SATA_ATX_C_DRX_N0

C194 1
C195 1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

SATA_DTX_ARX_N0
SATA_DTX_ARX_P0

C196 1
C198 1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

JODD

SATA_ATX_DRX_P0 <7>
SATA_ATX_DRX_N0 <7>

@

GND
A+
AGND
BB+
GND

SATA_DTX_C_ARX_N0 <7>
SATA_DTX_C_ARX_P0 <7>

+3VS

+5VS

15
14

GND
GND

DP
+5V
+5V
MD
GND
GND

1
2
3
4
5
6
7
8
9
10
11
12
13

SATA_ATX_C_DRX_P1
SATA_ATX_C_DRX_N1

C197 1
C199 1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

SATA_DTX_ARX_N1
SATA_DTX_ARX_P1

C200 1
C201 1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

ODD_PLUGIN#

SATA_ATX_DRX_P1 <7>
SATA_ATX_DRX_N1 <7>
SATA_DTX_C_ARX_N1 <7>
SATA_DTX_C_ARX_P1 <7>

<8>

+5VS_ODD
ODD_DA#

ODD_DA# <8>

SANTA_202401-1

A

SUYIN_127043FR022G196ZR

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Issued Date

Deciphered Date

2015/09/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

WLAN/SATA HDD&ODD
Document Number

Rev
1.0

LA-9868P
Sheet

Thursday, May 16, 2013
1

23

of

42

5

4

3

2

USB Sleep & Charge

1

Right side USB 3.0 x 2/ Sleep&Charge

State table for MAX14641
CB0

Mode

CB1

0

0

STATUS

AM2

2A auto-detection charger mode for Apple device.
Resistor dividers are connected to DP/DM. Including DCP

LR1

<7> USB30_RX0N

0

1

AP1

Forced 1A charger mode for Apple devices.
Resistor dividers are connected to DP/DM.

1

0

PM

USB pass-through mode.DP/DM are connected to TDP/TDM

CM

USB pass-through mode with CDP emulation.
Auto connects DP/DM to TDP/TDM depending
on CDP detection status.

<7> USB30_RX0P

D

1

1

USB30_RX0N

4

USB30_RX0P

1

4

3

1

2

EMI@

LR2

EMI@

3

USB30_RX0N_L

<7> USB20_P8

2

USB30_RX0P_L

<7> USB20_N8

USB20_P8

4

USB20_N8

1

4

3
2

1

3

USB20_P8_L

2

USB20_N8_L
D

WCM-2012-900T_0805

KINGCORE WCM-2012HS-670T

@

JUSBR
@

RR6

14641@

UR4
<29> CHG_PWR_GATE#
RR2

<8> SLP_CHG_CB1

1
2
3
4
9

USB20_DN9
USB20_DP9
14641@
0_0402_5% CHG_CB1

CB0
TDM
TDP
VCC

CEN
DM
DP
CB1
PGND

8
7
6
5

LR3
0_0402_5%

EC_CHG_CB0

14641@
0_0402_5%
RR1
USB20_N9 <7>
USB20_P9 <7>
+5VALW

CHG_CB0
USB20_N9
USB20_P9

1

<7> USB30_TX0N

<29>

<7> USB30_TX0P

SLP_CHG_CB0 <8>

4

3

2 USB30_TX0N_C
0.1U_0402_16V7K

1
CR16

2
2 USB30_TX0P_C 1
1
2
0.1U_0402_16V7K
KINGCORE WCM-2012HS-670T

4

3

9
8
7
6
5
4
3
2
1

USB30_TX0P_C_L
USB30_TX0N_C_L

EMI@

1
CR15

USB30_TX0N_C_L

USB30_RX0P_L
USB30_RX0N_L

USB30_TX0P_C_L

USB20_P8_L
USB20_N8_L
+USB_VCCB

StdA-SSTX+
StdA-SSTXGND-DRAIN
StdA-SSRX+
StdA-SSRXGND
D+
DVBUS

CR1

13
12
11
10

GND
GND
GND
GND

LOTES_AUSB0015-P001A

CB0,CB1->VIH=1.4V

0_0402_5%

0.1U_0402_10V7K

MAX14641ETA+TGH7_TDFN-EP8_2X2
@

RR5

<29> EC_CHG_CB1

2

UR4

Address
0x35
MAX14640ETA+TGH7
14640@

Left Side USB Port

LR4

USB30_RX1N

<7> USB30_RX1N

4

4

3

EMI@

LR5

EMI@

3

USB30_RX1N_L

USB20_DN9

4

USB30_RX1P_L

USB20_DP9

1

4

3

3

USB20_N9_L

2

USB20_P9_L

C

C

EMI@

4

<7> USB20_P0

4

1

<7> USB20_N0

3

1

2

USB30_RX1P

<7> USB30_RX1P

LR7

3

1

2

2

KINGCORE WCM-2012HS-670T

USB20_P0_L <25>

2

1

Sleep & Charge Port

USB20_N0_L <25>

W=80mils
+USB_VCCC

2
3
4
1

6
OUT 7
IN
OUT 8
IN
EN/ENB OUT 5
OCB
GND
SY6288DCAC_MSOP8

1
CR17

2
USB30_TX1N_C4
0.1U_0402_16V7K

<7> USB30_TX1P

1
CR18

2
2
USB30_TX1P_C1
2
1
0.1U_0402_16V7K
KINGCORE WCM-2012HS-670T

4

3

3

USB30_TX1N_C_L
USB30_TX1P_C_L

USB20_P9_L
USB20_N9_L
+USB_VCCA

StdA-SSTX+
StdA-SSTXGND-DRAIN
StdA-SSRX+
StdA-SSRXGND
D+
DVBUS

13
12
11
10

GND
GND
GND
GND

LOTES_AUSB0015-P001A

USB_OC#2 <29,8>

1

SA00003TV00

CR14
4.7U_0805_10V4Z
2@

USB POWER SWITH

+3VALW

+3VALW
B

2
3
4
1

<29> USB_CHG_EN#

IN
IN
EN/ENB
GND

2

+USB_VCCA

OUT
OUT
OUT
OCB

RR3
4.7K_0402_5%
14640@

6
7
8
5

RR4
4.7K_0402_5%
14640@

USB_CHG_OC#

<29,8>

QR1A

SY6288DCAC_MSOP8

<29,33,34> EC_SMB_CK1

SA00006DN00

6

1

CHG_CB1

DR1
1 1

USB30_TX0N_C_L

2 2

9 8

USB30_TX0N_C_L

USB30_RX0P_L

4 4

7 7

USB30_RX0P_L

5 5

6 6

USB30_RX0N_L

USB30_RX0N_L

10 9

USB30_TX0P_C_L

5

2N7002KDWH_SOT363-6
14640@
QR1B

@ESD@

USB30_TX0P_C_L

2

2.5A
UR1

1

+5VALW

W=100mils

2

B

USB30_RX1P_L
USB30_RX1N_L

EMI@

<7> USB30_TX1N

1

<29> USB_EN#2

9
8
7
6
5
4
3
2
1

USB30_TX1P_C_L
USB30_TX1N_C_L

LR6

2.0A
UR3

@

JUSBF

WCM-2012-900T_0805

+5VALW

1
2
WCM-2012-900T_0805

<29,33,34> EC_SMB_DA1
+5VALW

W=80mils

2.0A
UR2
2
3
4
1

<29> USB_EN#0

IN
IN
EN/ENB
GND

3 3
4

CHG_CB0

8

2N7002KDWH_SOT363-6
14640@

+USB_VCCB

OUT
OUT
OUT
OCB

3

6
7
8
5

YSCLAMP0524P_SLP2510P8-10-9
SC300002800

Change ESD Diode for EMI request

USB_OC#0 <29,8>

SY6288DCAC_MSOP8

SA00003TV00

DR3
1 1

USB30_TX1N_C_L

2 2

9 8

USB30_TX1N_C_L

USB30_RX1P_L

4 4

7 7

USB30_RX1P_L

5 5

6 6

USB30_RX1N_L

USB30_RX1N_L
+USB_VCCA

W=100mils

2

CR9

2

CR11

1

2

CR3
@

2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

2015/09/27

Deciphered Date

Title

Date:

4

A

YSCLAMP0524P_SLP2510P8-10-9
SC300002800

Change ESD Diode for EMI request

CR13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

USB30_TX1P_C_L

8

1

4.7U_0805_10V4Z

@

1

0.1U_0402_10V7K

2

W=80mils

4.7U_0805_10V4Z

CR7

1

1
CR2
47U_0805_6.3V6M

2

0.1U_0402_10V7K

1

10 9

3 3

+USB_VCCB

47U_0805_6.3V6M

A

@ESD@

USB30_TX1P_C_L

3

2

LUSB/RUSB/S&C
Document Number

Rev
1.0

LA-9868P
Thursday, May 16, 2013

Sheet
1

24

of

42

5

4

Battery Reset

3

2

LAN Conn

1

+3V_LAN

1

+3VALW_APU

LL1

JLAN
+3V_LAN
<12,23,8> APU_PCIE_RST#

2

EMI@

1 10K_0402_5%

close to JLAN

+3VS

4

2

For LAN function

1

ISOLATE#

@

RL2

2
WOL_EN#
0_0402_5%

2
1

3
S

RL3
15K_0402_5%

LANCLK_REQ#

Sx Enable
Wake up
WOL_EN#

UG1

CG12
1U_0402_6.3V6K
GSENSOR@

UG3

1

2

2
3

VOUT

5

4
6
8

SELF_TEST

1
CG13
1U_0402_6.3V6K
GSENSOR@
2

GSENSOR@

VIN

2
12

+3VS_HDP

+3VS_HDP

1

Sx Disable
Wake up

LOW

HIGH

GND
BP

SHDN#

9

+3VS_HDP

4

Vdd1
Vdd2
ST
PD
FS

Rev

NC1
NC2
NC3
NC4
NC5
GND1
GND2

3
5
7

VOUTX
VOUTY
VOUTZ

1
1
1

CG1
CG2
CG3

2 GSENSOR@
2 GSENSOR@
2 GSENSOR@

R60
390_0402_5%
1
2

D24

2

1

D

12
14
16
18
20
21
22
23
24

C

BATT_FULL_LED# <29>

HT-F196BP5_WHITE
D23

2

1

HT-191UD5_AMBER_0603

1
13

1
2
R3
510_0402_5%

BATT_CHG_LOW_LED# <29>

White LED bright when both AC-adaptor is plugged in and Battery is full charged
Amber LED bright while charging battery from AC-adaptor.
Amber LED blink during Critical Low Battery

SA00004GB00

SA000022I00

8
10

BATT CHARGE /FULL LED

+5VALW

TSH352TR LGA 16P

G9191-330T1U_SOT23-5

6

ACES_50559-02001-001
@

0.033U_0402_16V7K
0.033U_0402_16V7K
0.033U_0402_16V7K

10
11
14
15
16

4

G1
G2
G3
G4

S0

GSENSOR@

Voutx
Vouty
Voutz

2

HIGH

LED

G-SENSOR
+5VS

+USB_VCCC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

W=60mils

QL1
2N7002KW_SOT323-3

C

EMI@

+USB_VCCC

D

CLKREQ_LAN#

<8> CLKREQ_LAN#

2 0_0402_5% CLK_LAN#_R
2 0_0402_5% CLK_LAN_R

<24> USB20_P0_L
<24> USB20_N0_L

WOL_EN# <29>

G

5
6

<8> LAN_EN

EMI@

<5> PCIE_ATX_C_LANRX_N1
<5> PCIE_ATX_C_LANRX_P1
<5> PCIE_LANTX_ARX_N1
<5> PCIE_LANTX_ARX_P1

1K_0402_5%
RL1
@

2
LAN_EN

RL4 1
RL5 1

<7> CLK_LAN#
<7> CLK_LAN

1

LANCLK_REQ#

D

<35> ENLDO

LANCLK_REQ#
ISOLATE#

<8> APU_PCIE_WAKE#

+3VS
RL24 2

SW6
TJG-533-V-T/R_6P
3
1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

POWER LED

+3VS_HDP
RG1

1
2
3
4

8
7
6
5

RESET#
GXOUT
GXIN
MODE

D28

2

+5VALW

4.7K_8P4R_5%
GSENSOR@

1

R61
390_0402_5%
2
1

PWR_SUSP_LED# <29>

HT-F196BP5_WHITE

B

B

UG2

1

P1_6/CLK0/SSI01

P3_5/SSCK/SCL/CMP1_2

11

HDPACT <29>

2

<13,29,6> EC_SMB_CK2

White LED bright when system is power on.
White LED blink when system is sleep mode.

2

RESET#

3

GXOUT

4
5
6

GXIN

A

<29> HDPINT

HDPINT

RG4

+3VS_HDP

7

MODE

8

2
1 1K_0402_5%
GSENSOR@

1
CG7
0.1U_0402_10V7K
GSENSOR@ 2

9

P1_5/RXD0/CNTR01/INT11#

P3_7/CNTR0#/SSO/TXD1

P1_4/TXD0

RESET#

P1_3/KI3#/AN11/TZOUT

XOUT/P4_7

P1_2/KI2#/AN10/CMP0_2

VSS/AVSS

SA00003A600
P4_2/VREF

XIN/P4_6
VCC/AVCC

P1_1/KI1#/AN9/CMP0_1

MODE

P1_0/KI0#/AN8/CMP0_0

P4_5/INT0#/RXD1

P3_3/TCIN/INT3#/SSI00/CMP1_0

10

1
P1_7/CNTR00/INT10#
CG8
GSENSOR@
0.1U_0402_10V7K
R5F211B4D34SP
2

P3_4/SCS#/SDA/CMP1_1

12
13

RG2
47K_0402_5%
GSENSOR@

WLAN/WiMAX

1

SELF_TEST

14
15

LED (AMD NO WIMAX)

HDPLOCK <29>
VOUTZ

RG3 47K_0402_5%
2
1
GSENSOR@

16

+3VS_HDP

17

VOUTX

18

VOUTY

1

2

D27
+5VS

CG6
0.1U_0402_10V7K
GSENSOR@

2

1

HT-191UD5_AMBER_0603

19

2
1
R66
510_0402_5%

WL_BT_LED# <29>

Amber LED bright while Wireless and/or WiMAX turns on.

20

GSENSOR@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Issued Date

Deciphered Date

2015/09/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

A

EC_SMB_DA2 <13,29,6>

4

3

2

LAN/G-SENSOR/LED/B_RES
Document Number

Rev
1.0

LA-9868P
Sheet

Thursday, May 16, 2013
1

25

of

42

5

4

3

2

1

35mA for 3.3V level

20 mil

40 mil

UA1
CA58
CA57

MIC1_LINE1_R_C_R
MIC1_LINE1_R_C_L

22
21
17
16
31
30
29

+MIC1_VREFO_L
+MIC1_VREFO_R
<29> EC_MUTE_INT
D

15
14
20
12

MONO_IN

@ESD@
0.01U_0402_25V7K
2
CA65 1

close to pin19

1
2

AVDD1
AVDD2

MIC1_VREFO_L
MIC1_VREFO_R
MIC2_VREFO

PVDD1
PVDD2

LINE2_R
LINE2_L

SPK_OUT_R+
SPK_OUT_R-

MONO_OUT

SPK_OUT_L+
SPK_OUT_LHPOUT_R
HPOUT_L

1
20K_0402_1%

SDATA_OUT
SDATA_IN

19
28
27
34
35
36

JDREF
LDO_CAP
VREF
CPVEE
CBN
CBP

2
3

+DVDD
+DVDD_IO

25
38

+AVDD
+AVDD

39
46

+PVDD
+PVDD

45
44

SPKR+
SPKR-

40
41
33
32

CA4
0.1U_0402_16V4Z

2

1

close to pin1

2
1

INT_MIC_CLK_R
RA42
FBMA-10-100505-301T
CAM_EMI@

CA45
0.1U_0402_16V4Z

close to pin9
75_0402_1%
RA19
RA20
75_0402_1%

6

AZ_BITCLK_HD

23
24
48

LINE1_R_C_L
LINE1_R_C_R

+DVDD_IO
1

@

1
RA1

2
0_0402_5%

+1.5VS
CA33
0.1U_0402_10V7K

close to pin39

2

AVSS1
AVSS2
PVSS1
PVSS2
DVSS

CA32
0.1U_0402_10V7K

AZ_SDOUT_HD <8>
AZ_SDIN0_HD <8>

2
1
RA23 33_0402_5%

EAPD
PD#

Thermal Pad

269@ CA9 1
269@ CA10 1

close to pin46

For P/N and footprint
Please place them to ISPD page

AGND
For EMI reserve
close to codec
EMI@

CA51
1
1
2 EMI@
RA41
10P_0402_50V8J

2
AZ_BITCLK_HD
10_0402_5%

EMI@

CA5

1

2 0.1U_0402_10V7K

EMI@

CA6

1

2 0.1U_0402_10V7K

EMI@

CA7

1

2 0.1U_0402_10V7K

1
RA38
1
RA31

@EMI@

0_0603_5%
2
0_0603_5%

MIC/LINE IN

SPKL+

1
RA7

@

2
0_0603_5%

SPK_L1 <27>

SPKL-

1
RA8

@

2
0_0603_5%

SPK_L2 <27>

MONO_IN

CA31
ESD@
SCV00001K00

0.1U_0402_10V7K

1

CA27
100P_0402_50V8J

2

1
+MIC1_VREFO_R
RA48 2.2K_0402_5%
MIC1_R <27>

2

1
+MIC1_VREFO_L
RA46 2.2K_0402_5%

MIC1_L <27>

B

MIC_SENSE
RA29 269@
100K_0402_5%

QA1A
2N7002DW-T/R7_SOT363-6
269@

2

RA37
0_0402_5%
@

1

1

SPKR+

1
RA9

@

2
0_0603_5%

SPK_R1 <27>

SPKR-

1
@
RA10

2
0_0603_5%

SPK_R2 <27>

RA35

100K_0402_5%

<29> SM_SENSE#
3

2

2

CA36
ESD@
SCV00001K00

EC

QA1B
2N7002DW-T/R7_SOT363-6
269@

5

JACK_SENSE <27>

4

1

1

SENSE A

2
1
1K_0402_5%
RA45

MIC1_LINE1_R_L

CA30
ESD@
SCV00001K00

CA34
ESD@
SCV00001K00

Codec Signals

RA47
1K_0402_5%
2
1

MIC1_LINE1_R_R

+3VL

Impedance

C

6

2

Yes

2
EMI@

For EMI reserve
close to codec

2

2

No

269@

2

CA70
1
2

259@

49

For better sound
by customer request

Sense Pin

2

Sleep and Music

Enable
Disable

RA49
4.7K_0402_5%

1

ALC269Q-VB6-CG
269@

SPK

1 RA52

CA35
1 10U_0603_6.3V6M

2
+5VALW
0_0603_5%

For S&M

DGND

47K_0402_5%

2

@

2 0.1U_0402_10V6K MIC1_LINE1_R_L
2 0.1U_0402_10V6K MIC1_LINE1_R_R

2W 4ohm =40mil
1W 8ohm =20mil

<8> APU_SPKR

2

AZ_BITCLK_HD <8>

26
37
42
43
7

Beep sound

B

D

1
RA24

+PVDD
1

HP_R <27>
HP_L <27>

Internal AMP

PCI Beep

CA50

60 mil

AZ_SDIN0_HD_R

To solve noise issue
EC_MUTE#
Hight
LOW

2
+5VALW
0_0603_5%

@

1
2
10U_0603_6.3V6M

1

<20> INT_MIC_CLK

1
RA18

HDALink is 1.5V

5
8

ALC259-VC2-CG_MQFN48_6X6
259@

RA50
4.7K_0402_5%
269@

0.1U_0402_10V7K
1

2

CA37
2

10U_0603_6.3V6M 1

C

For EMI reserve

close to pin 38

0.1U_0402_10V7K
1
CA47

CA42
CA3
2.2U_0402_6.3V6M

2
2

SPKL+
SPKLHPOUT_R
HPOUT_L

close to pin 25

UA1

LINE1_L
LINE1_R
NC

SENSE_A
SENSE_B

47
4

<29> EC_MUTE#

BCLK

GPIO0/DMIC_DATA
GPIO1/DMIC_CLK

13
18

SENSE_A
SENSE_B

1
9

RESET#

10 mil

2
1
AC_JDREF
1
2
LDO_CAP
RA30
20K_0402_1%
AC_VREF
CA60 10U_0603_6.3V6M
1
2
CPVEE
CBN
CA54 2.2U_0402_6.3V6M
1
1
2
CBP
CA53 2.2U_0402_6.3V6M
CA55
0.1U_0402_10V7K
2
<20> INT_MIC_DATA
INT_MIC_CLK_R

2 @
RA34

MIC2_R
MIC2_L

SYNC

11

close to pin 28

CA25
2.2U_0603_10V6K

DVDD
DVDD_IO

PCBEEP

10

<8> AZ_SYNC_HD

<8> AZ_RST_HD#

MIC1_R
MIC1_L

+AVDD

2

4.7U_0603_6.3V6K
4.7U_0603_6.3V6K

2
+3VS
0_0402_5%

1

MIC1_LINE1_R_R
MIC1_LINE1_R_L

@
1
RA22

+DVDD
1

650mA for 5V level

Function

39.2K

PORT-I (PIN 32, 33)

Headphone out

20K

PORT-B (PIN 21, 22)

Ext. MIC

10K

PORT-C (PIN 23, 24)

place close to chip
MIC_SENSE 2
RA32

1
20K_0402_1%

SENSE_A

A

A

5.1K

(PIN 48)
<27> NBA_PLUG

SENSE B

39.2K

PORT-E (PIN 14, 15)

20K

PORT-F (PIN 16, 17)

10K

PORT-H (PIN 20)

Compal Secret Data

Security Classification
2012/09/27

Issued Date

2015/09/27

Deciphered Date

Title

RA33

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

39.2K_0402_1%

Cover Sheet
Rev
1.0

Thursday, May 16, 2013

Sheet
1

26

of

42

5

4

3

2

1

SPK Conn.
For common design,
pull-high resistor should be placed at connector side.

<26> SPK_R1
<26> SPK_R2
<26> SPK_L1
<26> SPK_L2
<8> SPK_DET
2

D

ACES_50228-0067N-001
@
8
7 GND
GND
6
5 6
4 5
3 4
2 3
1 2
1
JSPK

DA1
ESD@
SCV00001K00

SM_DET

BIOS setup

Speaker Type

BOM

1

S&M option

Harman/Kardon

269@

Non Harman

259@

0

D

1

Non-Harman detection
0

ONKYO

1

Non-Brand

SPK_DET

HeadPhone/LINE Out JACK
C

C

JLINE @
1
2
@
RA54 0_0402_5%
1
2
@
RA53 0_0402_5%

3

HP_R_R
3

DA6

1

100P_0402_50V8J

YSDA0502C_SOT23-3
@ESD@

B

CA14

CA13
@EMI@

100P_0402_50V8J

<26> HP_R

6
1
2

HP_R_L

2

<26> HP_L

4

<26> NBA_PLUG

5

@EMI@
TYCO_2041280-1_3.6D

MIC/LINE IN JACK

B

JEXMIC @
MIC1_R_L

3

MIC1_R_R

+3VL

5

RA40
4.7K_0402_5%

TYCO_2041280-1_3.6D

2

@EMI@

RA36
0_0402_5%
@

269@

1

100P_0402_50V8J

@EMI@

4

<26> JACK_SENSE

1

YSDA0502C_SOT23-3
@ESD@

CA12

CA11
100P_0402_50V8J

DA7

3

<26> MIC1_R

2

1
2
@
RA56 0_0402_5%
2
1
@
RA55 0_0402_5%

<26> MIC1_L

6
1
2

A

A

Compal Secret Data

Security Classification
2012/09/27

Issued Date

2015/09/27

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Conn
Rev
1.0

Thursday, May 16, 2013

Sheet
1

27

of

42

5

4

3

2

1

SD_DATA0

1
CW8
0.1U_0402_16V4Z

22

For power consumption measurement
and remove it after Pre-MP phase

2
3

<7> USB20_N2
<7> USB20_P2

SD_DATA1

RSTZ
MS_INS
SD_D2/MS_D5/SB13
SD_D3/MS_D4/SB12
SD CMD/SD_CMD
SD CLK/SD_CLK
SD_CDZ
SD_D0/MS_D6/SB9
SD_D1/MS_D7/SB8
MS BS/MS_BS
SD_W P/MS_D1/SB5
SD_D4/MS_D0/SB4
SD_D5/MS_D2/SB3
SD_D6/MS_D3/SB1
SD_D7/MS_CLK/SB0

DM
DP

30mils
+3VS

1

@

2
0_0402_5%

RW1

1 CW1
2

please close the pin19 of UW1

30mils

+3VS_CR
+3VS_CR

19
23
20

+3VS_CR
+VDD18

4
18

12mils

+3VS_CR

25

1
CW5
0.1U_0402_16V4Z

1

2

1
24

DVDD
PMOS

30mils

2.2U_0402_6.3V6M

+3VS_CR

+3VS_CR
+VCC_3IN1

CW2
0.1U_0402_16V4Z

DVDD
DVDD
GPIO0
AVDD
VDD18

5
17
16
15
14
21
13
12
11
10
9
8
7
6

Thermal pad
GL834L-OGY01_QFN24_4X4

SD_DATA2
SD_DATA3
SDCMD
SDCLK
SDCD#
SD_DATA0
SD_DATA1

1

SD_DATA3

Close to connector

JCARD
@JCARD
@

2

DAT0
DAT1
DAT2
CD/DAT3
12
13

GND_SW
GND_SW

W P_SW
CD_SW

5
3
6
7
4

SDCMD_L
SDCLK_L

Close to IC

SD_DATA0_L
SD_DATA1_L
SD_DATA2_L
SD_DATA3_L

10
11

SDWP#
SDCD

SD_DATA3_L

1

CW14 EMI@
4.7P_0402_50V8J

LW5

SDCLK

2
1
BLM15BB121SN1D_0402
EMI@

SDCLK_L

2

CW15 EMI@
4.7P_0402_50V8J

LW6

SDCMD

2
1
BLM15BB121SN1D_0402
EMI@

SDCMD_L

2

C

CW10 @EMI@
4.7P_0402_50V8J

30mil
+VCC_3IN1

1
CW6
0.1U_0402_16V4Z

2

8
9
1
2

SD_DATA2_L
CW13 EMI@
4.7P_0402_50V8J

1

VDD
CMD
CLK
VSS
VSS

D

SD_DATA1_L
CW12 EMI@
4.7P_0402_50V8J

2

1

< 2 in 1 Card Reader >

+3VS_CR

2

2
1
BLM15BB121SN1D_0402
EMI@

NC (default)
10K pull down
GPIO0 Power saving mode Normal mode

2

1
CW4
0.1U_0402_16V4Z

2

SD_DATA0_L
CW11 EMI@
4.7P_0402_50V8J

LW4

CW7
4.7U_0402_6.3V6M

2

CW3
2.2U_0402_6.3V6M

LW3
2
1
BLM15BB121SN1D_0402
EMI@

1

+3VS_CR

1

2

SDWP

please close the pin4 of UW1

30mils

LW2
2
1
BLM15BB121SN1D_0402
EMI@

1
SD_DATA2

De-coupling and Bulk capacitor should place near to Cardreader chip and Combo Socket
C

2

1

UW1

2

D

LW1
2
1
BLM15BB121SN1D_0402
EMI@

T-SOL_156-2000302604

"Normal Close" type connector

CD_SW

B

WP_SW
Protect Enable

Protect disable

Card Uninsertion

Card Insertion

B

Close

Open

Close

Close

Open

Close

For normal close type connector invert circuit
+3VS_CR

1

1

+3VS_CR

SDCD#
RW3
100K_0402_5%

SDWP

D

2

QW1B
G

3

2

QW1A

SDCD

6

2

RW4
100K_0402_5%
D

5

SDWP#

G

2N7002KDWH_SOT363-6
S

1

2N7002KDWH_SOT363-6

4

S

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Issued Date

Deciphered Date

2015/09/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

CardReader GL834L
Document Number

Rev
1.0

LA-9868P
Sheet

Thursday, May 16, 2013
1

28

of

42

5

4

3

+3VL

CB4
2
0.1U_0402_10V7K

2

1

CB11
22P_0402_50V8J
@EMI@

1
2
3
4
5
7
8
10

<8> GATEA20
<8> KB_RST#
<7> SERIRQ
<7,8> LPC_FRAME#
<7> LPC_AD3
<7> LPC_AD2
<7> LPC_AD1
<7> LPC_AD0

2

D

2

<7,8> CLK_PCI_EC
<8> LPC_RST#
+3VL

RB2
47K_0402_5%
2
1
1
CB12

EC_RST#

<8> EC_SCI#
<31> 0.95VS_PWREN#

EC_RST#

2
0.1U_0402_10V7K

CHG_PWR_GATE#

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

C

KSI[0..7]

<30> KSI[0..7]

KSO[0..15]

<30> KSO[0..15]

+3VL

2 CHG_PWR_GATE#
10K_0402_5%

1
RB23

12
13
37
20
38

SMBUS1->BATT, Smart Charger
SMBUS2->G-Sensor,GPU Thermal Sensor,
APU Thermal Sensor
EC SMBus2 for S0 , SMBus1 for S5

<24> CHG_PWR_GATE#

<24,33,34>
<24,33,34>
<13,25,6>
<13,25,6>

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0

67
EC_VDD/AVCC

1

UB1

RB3
10_0402_5%
@EMI@

PWM Output
AD Input

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47

CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00

SPI Flash ROM

GPIO
Bus

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

<8> SLP_S3#
<8> SLP_S5#
<8> EC_SMI#
<24,8> USB_OC#2
<24,8> USB_CHG_OC#
<24> USB_CHG_EN#
<24> USB_EN#2
<30> KB_LED
<5> FAN_SPEED1
<23> WL_OFF#
<23> E51_TXD
<23> E51_RXD
<8> SYS_PWRGD
<23> BT_ON
<26> SM_SENSE#

2.2K_0804_8P4R_5%

B

<26> EC_MUTE_INT
<8> RTC_CLK
ESD@

2 SYS_PWRGD
0.1U_0402_10V7K
2
SUSP#
180P_0402_50V8J

@
@

P.32_SYS_PWRGD OD/L
for 1.8V PU APU

E51_TXD

122
123

2
EC_MUTE_INT_R
2 0_0402_5%
XCLKO
0_0402_5%

1

RB22
100K_0402_5%

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

XCLKI/GPIO5D
XCLKO/GPIO5E

CB16
20P_0402_50V8

WL_BT_LED# <25>
USB_EN#0 <24>
FANPWM <5>

63
64
65
66
75
76

BATT_PRES <33>
USB_OC#0 <24,8>
ADP_I <33,34>
ADP_V <34>
HDPLOCK <25>

68
70
71
72

GPIO

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
V18R

D

HDPINT <25>

885_EC_ON

+3VL
83
84
85
86
87
88

EC_MUTE# <26>

TP_CLK
TP_DATA

VGATE <38>
GPU_DOWN# <13>
POK <35>
VCIN0_PH <33>

119
120
126
128

100
101
102
103
104
105
106
107
108
110
112
114
115
116
117
118
124

2
47K_0402_5%

TP_CLK <30>
TP_DATA <30>

97
98
99
109

EC_SPIDI <7>
EC_SPIDO <7>
EC_SPICLK <7>
EC_SPICS# <7>

73
74
89
90
91
92
93
95
121
127

1
RB35

LID_SW#

VCIN0_PH connect to
power portion (9012 only)

Nuvoton EC share ROM

1
RB14

BATT_CHG_LOW_LED# <25>
SYSON <31,36>
VR_ON <38>
3VALW_APU_PWREN <31,35>

2
0_0402_5%

@

+3VS

PWR_SUSP_LED# <25>

1
VCOUT0_PH_L
RB34

EC_RSMRST# <8>
EC_LID_OUT# <8>
PROCHOT_IN <33>

H_PROCHOT_EC
VCOUT0_PH_L

C

8
7
6
5

4.7K_0804_8P4R_5%

LCD_ENBKL <20,6>
WOL_EN# <25>
HDPACT <25>
BATT_FULL_LED# <25>
CAPS_LED# <30>
SYSON
VR_ON

RPB2
1
2
3
4

VR_ON
SYSON
TP_DATA
TP_CLK

BKOFF# <20>
PBTN_OUT# <8>
1.8_0.95VALW_PWREN <37>
EC_PXCONTROL <8>

2
0_0402_5%

@

H_PROCHOT_EC
H/L, no PU/PD
PBTN_OUT#
H/L, no PU/PD

ACIN <34>

EC_ON_R

B

ON/OFFBTN# <30>
LID_SW# <30>
SUSP# <31,36>
EC_CHG_CB0 <24>
EC_CHG_CB1 <24>

LID_SW#
SUSP#

1
RB21

SUSP#

+EC_V18R

2
10K_0402_5%

1

2

KB9012QF-A3_LQFP128_14X14

CB15
4.7U_0805_10V4Z
DB1
2

1 APU_PROCHOT#

@ESD@
SCV00001K00

Close to EC

close to APU

E51_TXD
EC_ON_R

RB28
4.7K_0402_5%
1
2

1
RB36

@

2
0_0402_5%

VCIN0 pin109
VCIN1 pin102

EC_ON <35>
1

EC_MUTE_INT_R
3

D

S

1
A

1U_0402_6.3V6K
CB50
@

S

2

H_PROCHOT_EC

<1.2V

D

2N7002KW_SOT323-3
QB1

G

High Active

VCOUT0 pin104

HIGH

LOW

VCOUT1 pin103

LOW

HIGH

APU_PROCHOT# <38,6>

Low Active (+3.3V)

A

2
G

QB2
2N7002KW_SOT323-3
885@

2

>1.2V

1

Voltage Comparator Pins FOR 9012 A3
+3VL

3

APU_PROCHOT#
885@
2
1
330K_0402_5%
RB19

RB27
100K_0402_5%
1
2

VS_ON <35>

VCOUT0_PH connect to power portion (9012 only)

2

2

1
CB6

@ESD@ 1
CB14

1
RB25 1
RB20

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

GND/GND
GND/GND
GND/GND
GND/GND
GND0

8
7
6
5

21
23
26
27

SPI Device Interface

11
24
35
94
113

1
2
3
4

1

+3VS

EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F

PS2 Interface

RPB1
+3VL

BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13

AGND/AGND

CLK_PCI_EC

69

2

2

1

CB3
0.1U_0402_10V7K
1
2

9
22
33
96
111
125

For EMI

0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
1
CB2
CB5

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

1

CB1
0.1U_0402_10V7K

2

+3VL

2

885_EC_ON

1

RB24
10K_0402_5%
885@

For KB9012 EC_ON low pulse work around

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

2015/09/27

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

LPC-EC-KB9012
Document Number

Rev
1.0

LA-9868P
Thursday, May 16, 2013

Sheet
1

29

of

42

3

2

1

Touchpad Connector
JTP

ON/OFFBTN#

C24

1

ESD@

2

ON/OFFBTN# <29>

0.1U_0402_25V6

D

15
13
11
9
7
5
3
1

JPWR @

1
3
5
7

1
3
5
7

2
4
6
8

2
4
6
8

ON/OFFBTN#

@

16
14
12
10
8
6
4
2

16
14
12
10
8
6
4
2

15
13
11
9
7
5
3
1

+3VS
TP_DATA <29>
TP_CLK <29>

1

TP_SCLK1

6

APU_SCLK1 <8>

5

1

R202
100K_0402_5%

+3VS
R299
4.7K_0402_5%

2

2

R298
4.7K_0402_5%

2

+3VL

2

+3VS

1

4

1

5

Power Button

TP_SDATA1
TP_SCLK1

Q8A
DMN66D0LDW-7 2N_SOT363-6
4

TP_SDATA1

D

3

APU_SDATA1 <8>

Q8B
DMN66D0LDW-7 2N_SOT363-6

E-T_6900-G08N-00R

+5VS

ACES_50611-0040N-001

Lid SW
+5VS_LED

Q9
AO3413_SOT23

+5VS

D

1

S

3

1
2
3
4
5
6

2

+3VL

1
2
3
4
GND
GND

VDD

1

2

GND

U19
APX9132ATI-TRL_SOT23-3

JBLG @

VOUT

3

LID_SW# <29>

1

1

Keyboard LED

C218
0.1U_0402_16V4Z

C219
10P_0402_50V8J

2

ACES_50578-0040N-001

+5VS_LED

1

KBL@

C

C

FCH
H4

A

1

1

1

1

H_3P2N
@

1

1

1

1

B

PCB Fedical Mark PAD

ISPD

UC1

X4@

UC1

X4NPI@

1

@

X4R1@

UC1

DAZ0WJ00100

UC1 @
SA00006KR40
A4-5000 15W 4C

SA00006R430

SA00006R400

SA00006R410

CPU A4-5000 15W 4C

CPU A4-5000 15W 4C

CPU A4-5000 15W 4C

PCB LA-9868P

UC1

X5@

UC1

X5NPI@

X5R1@

UC1

SA00006R330

SA00006R300

SA00006R310

CPU A6-5200 25W 4C

CPU A6-5200 25W 4C

CPU A6-5200 25W 4C

A

35
36

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Issued Date

Deciphered Date

2015/09/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

4

FD4

FD3
@

1

@

ZZZ1

CVILU_CF17341U0R0-NH
@

5

FD2

FD1
@

1

KSI1
KSI6
KSI5
KSI0
KSI4
KSI3
KSI2
KSI7
KSO15
KSO12
KSO11
KSO10
KSO9
KSO8
KSO13
KSO7
KSO6
KSO14
KSO5
KSO3
KSO4
KSO0
KSO1
KSO2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GND1
GND2

H_3P2
@

H_3P0
@

1

2
1
R4 300_0402_5%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

H16

H15
H_3P0
@

H_3P2
@

H_3P0
@

JKB

H14

H18

H8

B

<29> CAPS_LED#
+3VS

H6
H_3P2x3P7
@

H_3P0
@

KSI[0..7] <29>
KSO[0..15] <29>

1

KSI[0..7]
KSO[0..15]

H_3P0
@

H_3P0
@

H9

H13

1

H_3P0
@

1

H_4P0
@

H_3P3
@

NPTH
H12

H11

1

NEW KEYBOARD CONN.

H10

1

H7

H29
H_7P0
@

1

PTH

WLAN

H21

H_3P3
@

1

H_3P3
@

H_4P2x4P6
@

1

S

H5

H3
H_4P6
@

1

G

VGA

H2
H_4P2
@

1

H1

Q10
2N7002KW_SOT323-3
KBL@

2

3

<29> KB_LED

CPU

Screw Hole

D

1

1

2

2

G

R204
10K_0402_5%
KBL@

3

2

KB/TP/LED/LID/DEBUG/ISPD
Document Number

Rev
1.0

LA-9868P
Sheet

Thursday, May 16, 2013
1

30

of

42

5

4

3

2

+5VS
+5VALW

4

+5VALW

VBIAS

5

SUSP#

6
7

+3VALW

CT1
GND

ON2

CT2

VIN2
VIN2

VOUT2
VOUT2

C5
1

180P_0402_50V8J
2

C9
1

330P_0402_50V7K
2

2
@

11
10

+3VS

PJ7

9
8

@

1

+3VS_LS

15

2
JUMP_43X118
@

2

3

<8> ODD_PWR

2

4

+5VALW

CT1
GND
CT2

ON2

6
7

+1.8VALW

ON1
VBIAS

5

SUSP#

VOUT2
VOUT2

VIN2
VIN2

GPAD

14
13

1

+5VS_ODD_LS
C12
1

12

2
JUMP_43X79

180P_0402_50V8J
2

@

11
C11
1

10

330P_0402_50V7K
2

+1.8VS
@

2

1

+1.8VS_LS

15

C15

1

PJ9

9
8

2

JUMP_43X79
@

2

D

C16

TPS22966DPUR_SON14_2X3

C8

@

1

2

1

C13
1U_0402_6.3V6K

1

+5VALW TO +5VS
+3VALW TO +3VS
Load switch

1U_0402_6.3V6K

2

C10

C7

1 C14

0.1U_0402_10V7K

1

2

1

TPS22966DPUR_SON14_2X3
@

@

JUMP_43X118

VOUT1
VOUT1

+1.8VALW TO +1.8VS
+5VS TO +5VS_ODD
Load switch

0.1U_0402_10V7K

GPAD

1

+5VS_LS

12

+5VS_ODD
@

PJ8

VIN1
VIN1

0.1U_0402_10V7K

ON1

14
13

0.1U_0402_10V7K

D

1U_0402_6.3V6K

2

3

SUSP#

VOUT1
VOUT1

1U_0402_6.3V6K

@

@

PJ6

VIN1
VIN1

1
2

+5VS

U1

1
2

VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
U2

VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

1 C6

1

+0.95VALW to +0.95VS
C

+0.75VS

+0.95VALW

+0.95VS

C

+3VALW_APU
+1.5V

2

2

Vgs=10V,Id=14.5A,Rds=6mohm

2
1

2

1

2N7002KDWH_SOT363-6

SUSP

1

2

3

SUSP

3

2
2N7002KDWH_SOT363-6

5

Q4B

1

Q5B

3VALW_APU_PWREN

5

5

SUSP#

<29,36> SUSP#

2N7002KDWH_SOT363-6

4

<29,36> SYSON

6

1
6
Q5A

Q3B

Q2B
2N7002DW-T/R7_SOT363-6

5

2

2SYSON#

R215
100K_0402_5%

Q4A

1

SYSON#

Q3A
2N7002KDWH_SOT363-6

Q2A
2
2N7002DW-T/R7_SOT363-6

R219
100K_0402_5%

1

R217
820K_0402_5%

3

2
1 R216
B+
220K_0402_5%

3 1

0.1U_0402_25V6

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

4

4

2

6

Q11_GATE

1
C250

R212
100K_0402_5%

4

FDS6676AS_SO8

R211
470_0805_5%

6 1

2
R214

470_0805_5%

1
2
3
4

1

S
S
S
G

1

D
D
D
D

2

8
7
6
5

+5VALW

R213
470_0805_5%

+5VALW

R221
470_0805_5%

1

2

+5VALW
Q11

<29> 0.95VS_PWREN#
B

B

EMI Cap.
Please check location

+1.5VS

<29,35> 3VALW_APU_PWREN

3
@

@

5

2N7002KDWH_SOT363-6

2

1

AO3413_SOT23
C252
0.01U_0402_25V7K

PJ4
JUMP_43X39
@
+3VALW_APU

Q12

4
R223
100K_0402_5%
9012@

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Issued Date

Deciphered Date

2015/09/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

@

2

2
47K_0402_5%

1

3VALW_APU_PWREN

Vgs=-4.5V,Id=3A,Rds<97mohm

0.1U_0402_10V7K

1

1
R220
QC1B

S

C251

1

2

1
1

2
R224
10K_0402_5%
885@

@ESD@

@

R218
10K_0402_5%
@

2

2

2

+3VL

3

@EMI@ @EMI@

1

1U_0402_6.3V6K

2

+3VALW

1

@EMI@

C23

1

0.1U_0402_25V6

@EMI@

2

0.1U_0402_25V6

2

1

C21

2

2

1

0.1U_0402_25V6

2
1
1

3

D

1

C253

Q6
2N7002KW_SOT323-3

G
0.1U_0402_25V6

G
AO3419L_SOT23-3

D

2

0.1U_0402_25V6

3

1

2

S
A

1

Q1

SUSP

C20

C19

G

R222
470_0805_5%

2

+3VALW

C18

D

B+

+1.5VS

+1.5V

+3VALW to +3VALW_FCH

S

+1.5V to +1.5VS

4

3

2

DC TO DC INTERFACE
Document Number

Rev
1.0

LA-9868P
Sheet

Thursday, May 16, 2013
1

31

of

42

A

B

C

D

EMI Part (47.1)
Other component (37.1)
EMI@ PL1
HCB2012KF-121T50_0805
1
2

A51 need add fuse

VIN

1

1

@PJP1
@
PJP1

PF1
1

1
2
3
4

2

DC_IN_S1

1

1
PC103 EMI@
100P_0603_50V8

PC101 EMI@
100P_0603_50V8

2

PC102 EMI@
1000P_0603_50V7K

2

2

1

ACES_50299-00401-001

1

7A_32V_S1206-H-7.0A

2

1
2
3
4

EMI@ PL3
HCB2012KF-121T50_0805
2
1

PC104 EMI@
1000P_0603_50V7K

For

RTC (38.2)

+RTC_APU_R

PU1

+
1

PR101
560_0603_5%
2+RTC_R
1
1

2

+RTC

Vin

1

+RTC

GND

AP2138N-1.5TRG1_SOT23-3

2

PBJ101 @
2

PC10

-

PR102
560_0603_5%

1U_0402_6.3V6K
2
1

For ML1220 RTC (38.2)

2

Vout

1

2

PC9
1U_0402_6.3V6K

3

2

ML1220T13RE

3

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Deciphered Date

2015/09/27

Title

DCIN/PRECHARGE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-9868P

Date:

A

B

C

Sheet
D

32

of

42

A

B

C

PL4 EMI@
HCB2012KF-121T50_0805
1
2

Other component (37.1)

EMI Part (47.1)

VMB

@
ACES_50299-01001-W01
1
BATT_S1
1 2
2 3
3 4
BATT_P4
4 5
BATT_P5
5 6
EC_SMDA
6 7
EC_SMCA
7 8
8 9
9 10
10
PJP2

PL5 EMI@
HCB2012KF-121T50_0805
1
2

PF2

1

2

BATT+

2

PR14
1K_0402_1%

1
PC7 EMI@
1000P_0402_50V7K

OTP (39.7)

PC8 EMI@
0.01U_0402_25V7K

2

1

1

10A_125V_TR2/6125FF10-R

1

2

1

D

+3VL

<29> PROCHOT_IN

PR19

2
2

EC_SMB_DA1 <24,29,34>

PR4
12.1K_0402_1%

1
1

@ PC11
0.1U_0402_10V7K

1

1

1

PR21
100_0402_1%

PR20
100_0402_1%

2

2

2

1K_0402_1%

1

BATT_PRES <29>

2

2

@ PR5
0_0402_5%
1
2

<29> VCIN0_PH

PR3
20K_0402_1%

1

PR2
@PR2
@
0_0402_5%
1
2

PH1
100K_0402_1%_TSM0B104F4251RZ

+3VL

PR1
1K_0402_1%

PR16
6.49K_0402_1%
2
1

1

2

<29,34> ADP_I

2

2

EC_SMB_CK1 <24,29,34>

3

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Deciphered Date

2015/09/27

Title

BATTERY CONN / OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-9868P

Date:

A

B

C

D

Sheet

33

of

42

A

B

C

D

for reverse input protection

1
3

Charger controller (40.1), Support component (40.2)
D

S

2
G
PR226

1
PD231
RB751V-40_SOD323-2

1

DH_CHG

BQ24725_REGN2

PQ201
AON7408L

2

4

@ PR210
0_0603_5%

2

1

2

PR247
309K_0402_1%
PR248
10K_0402_1%
1
2

ADP_V <29>

1

PR245
66.5K_0402_1%

1

EC_SMB_CK1 <24,29,33>

PR249

100P_0402_50V8J

2

EC_SMB_DA1 <24,29,33>
@ PR246
0_0402_5%
1
2

PC245
2
1

@ PC247
0.1U_0402_10V7K

2

47K_0402_1%

ADP_I <29,33>

1

1
2

1

VIN

For A51 ADP_V function

@ PC246
@PC246
0.1U_0402_10V7K

2

ILIM and external DPM
3.97A

1

Max.

PC244
0.1U_0402_25V6

Typ
17.23V
17.63V

2

Min.

2

1

CSON1

CSOP1

2
PR241
590K_0402_1%

Vin Dectector
H-->L
L--> H

PC223
10U_0805_25V6K

1

3
2
1

3

1

2

PC243
0.01U_0402_25V7K

2

1

PR242
100K_0402_1%

2

BQ24725_ACDET

PR244
422K_0402_1%

1
2

EMI Part (35.33)

+5VALW

BQ24725_ILIM

VIN

PC242
0.1U_0603_16V7K

BQ24725RGRR_QFN20_3P5X3P5

3

<29> ACIN

1

BQ24725_BATDRV

2

11

13

@

ILIM

SCL

SDA

12

PR236
10_0603_1%
2 CSOP1
SRP1
PR237
6.8_0603_5%
2 CSON1
SRN1

3

1

2 BQ24725_ACOK
10K_0402_1%

BATDRV

10

1
PR239

ACOK

6

+3VL

SRN

ACDRV

9

5

14

2

2

SRP

8

4

IOUT

3

BQ24725_ACDRV

7

BQ24725_CMSRC

ACDET

2

PR227
0.01_1206_1%
4

PC222
10U_0805_25V6K

CMSRC

AON7406L

1

PC241
0.1U_0402_25V6
2
1

GND

4

DL_CHG

1

ACP

15

2

LODRV

CHG

2

1
REGN

PQ202

ACN

2

5

16

17
BTST

HIDRV

PAD

1

1

BQ24725_LX

2

PC205
2

1

PL202
4.7UH_ETQP3W4R7WFN_5.5A_20%

PC221
10U_0805_25V6K

BATT+

3
2
1

PR229
2.2_0603_5%
1
BQ24725_BST 2

5

2

18

19
PHASE

1

1
2

PC237

DH_CHG

PR228
10_1206_1%
BQ24725_LX

2
BQ24725_VCC

1 1
21

20

PU200

2 BQ24725_BATDRV_1

1

PR233
4.12K_0603_1%

1U_0603_25V6K

VCC

1
2

PC235
0.1U_0402_25V6

PC238
0.1U_0402_25V6
2
1

1
2

PR235
4.12K_0603_1%

1
2

1U_0603_25V6K

BQ24725_ACN

BQ24725_ACP

PR234
4.12K_0603_1%

PC239
1
2

BQ24725_BATDRV

0.047U_0402_25V7K

1

PC234
0.01U_0402_50V7K

PD230
BAS40CW_SOT323-3

4

1
2

2
PC236
0.1U_0402_25V6

2

3

2

BQ24725_ACDRV_1

2

PC207 @
1U_0603_25V6K

VIN

1

1
2
3

5

PC240
0.1U_0402_25V6

3

S TR SI7716ADN
PQ207

@EMI@ PC206
@EMI@ PR206
680P_0603_50V8J
4.7_1206_5%

2

1

5

EMI@ PL201
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2

1

1

PR211
0.01_1206_1%
4

PC213
10U_0805_25V6K

1
2
3

4

1
4

2

1
2

B+

1

SI7716ADN-T1-GE3_POWERPAK8-5

1
2
3

5
PC230
2200P_0402_50V7K

P2

P1

PQ203

PC231
0.1U_0402_25V6

VIN

2

PQ205

TPCA 8057

2

EMI Part (47.1)
1

1

2

3M_0402_5%

@EMI@ PC214
2200P_0402_25V7K

1

2

1M_0402_5%

PC211
10U_0805_25V6K

PR225

1

PQ209
2N7002FU_SOT23

4

4

Please locate the RC
Near EC chip
2011-02-22
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

2015/09/27

Deciphered Date

Title

CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

Rev
1.0

LA-9868P
Sheet

34
D

of

42

A

B

C

D

PR339
0_0402_5%

3

1

@

1

1

G

D

1

PQ333
2N7002FU_SOT23
2

S

<29,31> 3VALW_APU_PWREN

2

3/5VALW controller (35.1), Support component (35.2)

PR350
30K_0402_1%
2
1

EMI Part (47.1)

LG_3V

10

BST_5V
UG_5V

5
3
2
1

LDO5

SECFB

LDO3
15

14

13

12

11

ENLDO

LGATE2
VIN

5

1

1
FB1

2

3

PHASE2

4

LGATE1

17

LX_5V

16

LG_5V

2

PL352
2.2UH_MMD-06CZ-2R2M-V1_8A_20%
2
1

PU330
RT8243AZQW_WQFN20_3X3

4

1

2

2

1

PC344
4.7U_0603_10V6K

2

PC342
1U_0603_10V6K
2
1

FDMC7692S_MLP8-5

2
1

2

@ PR332
100K_0402_5%

@ PR341
0_0402_5%
1
2

@

+5VALWP

EMI Part (47.1)
1

+

2

5V
Peak Current 12A
OCP current 14A
FSW=390kHz
Delta I=2.791A,ripple=2.791*15m=41.865mV
DCR 18~20mohm
TYP
MAX
H/S Rds(on) ::27mohm , 34mohm
L/S Rds(on) :10.8mohm ,
13.6mohm

PR340
2.2K_0402_1%
1
2

1

<29> VS_ON

PC341
4.7U_0603_10V6K

<25> ENLDO

PC343
4.7U_0805_25V6-K

3.3V
Peak Current 8A
OCP current 10A
Delta I=1.160A ,ripple=1.160 x17m=19.27mV
FSW=455kHz
DCR 35mohm +/-15%
TYP
MAX
H/S Rds(on) :27mohm , 34mohm
L/S Rds(on) :19mohm ,
23.5mohm

PQ352

VL

PR338
100K_0402_1%
2
1

1

<29> EC_ON
3

PC360
0.1U_0603_25V7K

EMI Part (35.33)

+3VLP

PR334
499K_0402_1%
2
1

3/5V_B+

3
2
1

AON7406L
PQ332

2

1
2
3

2

@EMI@ PR336
@EMI@ PC336
680P_0603_50V8J
4.7_1206_5%
1
2
1 SNUB_3V 2

PC354
150U_D2_6.3VY_R15M

1

19
18

PC355
0.1U_0402_10V7K
2
BST1_5V 1

@ P355
0_0402_5%
1
2

PC353
150U_D2_6.3VY_R15M

9

PHASE1

+

PC361
10U_0805_25V6K

2
1
PR337
210K_0402_1%
2
1
PR342
56K_0402_1%
2
1
PR357
174K_0402_1%
4

UGATE2
UGATE1

LX_3V

4

1

+3VALWP

20

1

8

BYP1

AON7408L

2
SNUB_5V

UG_3V

PGOOD
BOOT2

PQ351

21

@EMI@ PR356
@EMI@ PC356
4.7_1206_5%
680P_0603_50V8J

7

PAD

BOOT1
PL332
4.7UH_ETQP3W4R7WFN_5.5A_20%
2
1

2

PR351
19.1K_0402_1%
1
2

2

BST_3V

TON

6

ENTRIP1

@ P333
0_0402_5%
1
2

FB_5V

5

1
2
3

FB_3V

FB2

1
2

4
PC335
0.1U_0402_10V7K
2 BST1_3V
1

3/5V_B+

VL

<29> POK

5
PQ331
AON7408L

1
2

PC340
10U_0805_25V6K

PR331
20K_0402_1%
2
1

ENTRIP2

2
@EMI@ PC339
2200P_0402_50V7K
2
1

1

PR330
14K_0402_1%
1
2

3/5V_B+

5

EMI@ PL331
HCB2012KF-121T50_0805

PR335
100K_0402_1%

B+

@ PJ332

+3VLP

2

2

1

@

1

+3VL

+3VALWP

JUMP_43X39

1

1

3

PJ331

2

2

+3VALW

JUMP_43X118

(100mA,20mils ,Via NO.= 1)

(8A,160mils ,Via NO.= 16)
@

+5VALWP

1

1

PJ351
2
2

+5VALW

JUMP_43X118

(12A,240mils ,Via NO.= 24)

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Deciphered Date

2015/09/27

Title

3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

Date:

A

B

C

Sheet

D

35

of

42

A

DDR controller (35.3), Support component (35.4)
EMI@ PL151
HCB2012KF-121T50_0805

EMI Part (47.1)

1.5V_B+

@ PR163
0_0402_5%
1
2

1

1

1

2

2

PC163
0.033U_0402_16V7K

20
VTT

2

18

19
VLDOIN

1

6

7

9

8

PR160
10.2K_0402_1%
2
1

+1.5VP

2

PR161
887K_0402_1%
1
2

PR162
10K_0402_1%

1

EN_1.5V

@ PJ151

2

+1.5VP

@ PC166
0.1U_0402_10V7K

<29,31> SUSP#

PR164
@PR164
@
0_0402_5%
1
2

1

EN_0.75VSP

<29,31> SYSON

VTTREF_1.5V

5

FB_1.5V

TON_1.5V

1
2

VDDQ

4

1

VDD

PC156 EMI@
680P_0402_50V7K

1

BOOT

VTTREF

2
3

2

+5VALW

2

PC164
1U_0603_10V6K

GND

RT8207MZQW_WQFN20_3X3

VDDP

1

+5VALW

17

1

4

CS

21
1

FB

11

VDD_1.5V

VTTSNS

S3

PR159
5.1_0603_5%
1
2

12

PAD

VTTGND

PGND

S5

PC162
1U_0603_10V6K
1
2

LGATE

TON

14

PR158
17.4K_0402_1%
1
2CS_1.5V

UGATE

16
15

PU150

PC160
10U_0603_6.3V6M

PC155
0.1U_0603_25V7K
1
2

5

4

5
FDMC7692S_MLP8-5
PQ152

+0.75VSP

2
0_0603_5%

DL_1.5V

1
2
3

1
PR156 EMI@
4.7_1206_5%

2

@

2

1
PR157

13

SNUB_+1.5VP 2

PC157

+

220U_6.3V_M

1

+1.5V

BST_1.5V

SW_1.5V

1
2
3

PL152
1UH_VMPI0703AR-1R0M-Z01_11A_20%
2
1

+1.5VP

PR155
2.2_0603_5%
1
2

DH_1.5V

PQ151
AON7408L

2

1

PC154
10U_0805_25V6K

1
2

PC152@EMI@
2200P_0402_50V7K

BST_1.5V-1

PC159
10U_0603_6.3V6M

1.5V_B+

PHASE

2

PGOOD

1

10

B+

JUMP_43X118

+1.5VP

+0.75VS

2

JUMP_43X79

2

1

1

1

@ PJ152
+1.5V

JUMP_43X118

(0.5A,40mils ,Via NO.= 1)

2

2

+0.75VSP

@ PJ750
1
2
1

@ PC167
0.1U_0402_10V7K

(12A, 480mils ,Via NO.= 24)
OCP=13.8A

1.5V
Peak Current 12A
OCP current 13.82A
FSW=500kHz
DCR 8.3 ~ 10mohm
TYP
MAX
H/S Rds(on) :27mohm , 34mohm
L/S Rds(on) :10.8mohm ,
13.6mohm

STATE

S3

S5

1.5VP

S0

Hi

Hi

On

On

S3

Lo

Hi

On

On

Lo

Lo

S4/S5

VTT_REFP

0.75VSP
On
Off
(Hi-Z)

Off
Off
Off
(Discharge) (Discharge) (Discharge)

Issued Date

Note: S3 - sleep ; S5 - power off

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Deciphered Date

2015/09/27

Title

1.5VP/0.75VSP/1.8VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-9869P

Date:

A

Sheet

36

of

42

A

B

C

D

1.8V controller (35.15), Support component (35.16)
1

1

+3VALW

Need create Symbol.

1.8V
Peak Current 2.5A
OCP current 3.5A
FSW=800kHz

Note:Iload(max)=3A

1

2

FB=0.6V

+1.8_EN

1

+1.8VALWP

1

2

2

H/S Rds(on) :100mohm ,
L/S Rds(on) :80mohm ,

PR453
49.9K_0402_1%
2

2

@ PC453
0.1U_0402_16V7K

@ PJ451

1

PR451
100K_0402_1%

PC451
22U_0603_6.3V6M

1

1

2

EN

SY8032ABC_SOT23-6

+1.8VALWP

1

FB

2

PC452
22U_0603_6.3V6M

GND

PG

PC450
22P_0402_50V8J
2
1

6

IN

1

<29> 1.8_0.95VALW_PWREN

5

PL451
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2
3
LX

2

2
@ PR452
0_0402_5%
1
2

4

PC458
22U_0603_6.3V6M

1

PU450

+1.8VALW

JUMP_43X79

2

2

(2.5A,100mils ,Via NO.=5)

0.95V controller (35.5), Support component (35.6)
@ PR404
0_0402_5%
1
2

1.8_0.95VALW _PW REN

0.95V
Peak Current 11.1A
OCP current 16A
FSW=800kHz

1

2
PR405
10K_0402_1%

@ PC454
0.01U_0402_16V7K

1

2

3

3

EMI Part (47.1)
@EMI@ PR401
@EMI@PC403
4.7_1206_5%
680P_0603_50V7K
2SNB_0.95V1
1
2

PL402 EMI@

PU400

PR406
100K_0402_1%

1
2

PC412
22U_0603_6.3V6M

1
2

PC406
22U_0603_6.3V6M

1
2

1
2

PC401
22U_0603_6.3V6M

FB=0.6V

2

2

SY8208DQNC_QFN10_3X3

1

5

2

+3VALW

7

1

2

4

PC411
2.2U_0603_6.3V6K

FB
3

+3VALW

PC407
22U_0603_6.3V6M

LDO

+0.95VALWP
1

PG

PL401
1UH_PCMB063T-1R0MS_12A_20%
1
2

2

BYP

LX_0.953V

PC408
22U_0603_6.3V6M

ILMT

10

1

LX

1 2

GND

1

9

1
PC405
0.1U_0603_25V7K
2
1
6

PC409
4700P_0402_50V7K

BS

@

@ PJ1
2

+0.95VALW P

PR403
1K_0402_1%

EN

PC402
4.7U_0603_6.3V6K
2
1

1
2

IN

PR402
66.5K_0402_1%

8

B+_0.95V
10U_0805_25V6K
PC410
2
1

@EMI@

PC404

HCB2012KF-121T50_0805
2
1

2200P_0402_50V7K

B+

H/S Rds(on) :22mohm ,
L/S Rds(on) :11mohm ,

EMI Part (47.1)

2

1

1

+0.95VALW

JUMP_43X118

(11A,440mils ,Via NO.=22)
OCP=
4

2

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Deciphered Date

2015/09/27

Title

+1.8VALWP/+0.95VALWP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

Rev
1.0

LA-9868P

Thursday, May 16, 2013
D

Sheet

37

of

42

A

B

C

D

E

EMI Part (47.1)
APU_VDD_SEN_H <6>

46

BOOT1

45

LGATE_NB1

44

PHASE_NB1

43

UGATE_NB1

42

BOOT_NB1

41

VCC
1

2

PR570
2.2_0603_5%
2
1

UGATE1

PR563
124K_0402_1%
2
1

PR565
470_0402_1%
2
1

PR567
124K_0402_1%
1
2

3
2
1
3
2
1

4

2
1

ISENA1N-1
0.1U_0402_25V6

2

1

PC524
.1U_0402_16V7K

SNB_APU

ISEN1P

PR547
910_0402_1%
2

APU_core
TDC 15A(A) 13A(B)
Peak Current 21A(A) 18A(B)
OCP current > 31.5A
Load line -4mV/A
FSW=400kHz
DCR 1.4mohm +/-5%
TYP
MAX
H/S Rds(on) :11.7mohm , 14.5mohm
L/S Rds(on) :4.2mohm ,
5mohm

10_0402_5%

3

2

3
PR541
2.8K_0402_1%
2
1

1
ISEN1N

4

Compal Secret Data

Security Classification
2012/09/27

Issued Date

Title

Deciphered Date

Compal Electronics, Inc.
+CPU_CORE/VDDNBP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

PL503
0.36UH_PDME064T-R36MS_24A_20%
4
1
+APU_CORE

PC530
P
@
C530
0.1U_0402_25V6
2
1

2

PC521
0.1U_0402_25V6

PQ504
MDU1512RH 1N POWERDFN56-8

@

4

LGATE1

APU_B+

<6> APU_VDDNB_SEN_H

+5VS

SET2

PR561
53.6K_0402_1%
2
1

1

5

2

PC523
0.22U_0603_25V7K

+3VS

PR558
0_0402_5%
2

2

4

4

3
2
1

PR533
2.2_0603_5%
1
2 BOOT1-1
BOOT1 1

@ PC531
330P_0402_50V
2
1

PR559
2

+APU_CORE_NB

33U_D2_25VM_R60M @

PC507

PC515
2
1

APU_B+

39

2

@ PR557
0_0402_5%

+5VS

100U_25V_M
PC508

PC506
10U_0805_25V6K
2
1

PR527

40

2

@EMI@ PC522
2200P_0402_50V7K
2
1

UGATE1

2
PR520
10_0603_5%

5

PHASE1

47

PC502
2.2U_0603_10V7K
2
1

48

+5VS

APU_CORE_NB
@
TDC 13A(A) 12A(B)
Peak Current 17A(A) 15A(B)
OCP current > 22.5A
Load line -4mV/A
FSW=400kHz
DCR 1.4mohm +/-5%
TYP
MAX
EMI Part (47.1)
H/S Rds(on) :11.7mohm , 14.5mohm
L/S Rds(on) :4.2mohm ,
5mohm

PHASE1

1

PR555
20K_0402_5%
2
1

PR519
910_0402_1%
2

1

ISEN1N-1

1

VCC

PR518 @
0_0402_5%
2

PC520
10U_0805_25V6K
2
1

PGOOD

LGATE1
PC501
2.2U_0603_10V7K
2
1

2

1

BOOT2

UGATE2
PGOODA

ISENA1P

EN

38

37

ISENA1N

36

49

110K_0402_1%

ISENA1P

35

PVCC

1

ISENA1P

5

TONSET

3

4
TONSET

PWM3

6

5

ISEN2N
ISENA2N

ISENA2P

50

1

OFS

@PR502
@
PR502
0_0402_5%
1
2

PVCC

PR537

PR546
10K_0402_1%
2
1

PC533
0.01U_0402_50V7K

SET1

51

100K_0402_5%
PR542 VR_ON <29>
0_0402_5% @
@PR542
1
2

PR550
20K_0402_5%
1
2

OFSA

PR554
120_0402_1%
1
2

52

1

PC529
560P_0402_50V7K
1
2

PC528
68P_0402_50V8J
2
1

1

53

VGATE <29>

VCC

2

PC512
.1U_0402_16V7K

ISENA1N

RGND

PR553
6.34K_0402_1%
1
2

PWMA2

TONSETA

2

3
PR516
2.8K_0402_1%
2
1

SNB_APU_NB

1

1

PR536

<29,6> APU_PROCHOT#

ISENA1N

PR532
@PR532
@
0_0402_5%
1
2 VR_HOT

34

27

SET2

PR544
115K_0402_1%
2
1

PR548
6.34K_0402_1%
1
2

ISEN2P

ISEN1P

ISEN1N
7

8
ISEN1P

ISEN1N

10

9

ISEN3N

ISEN3P

FB

11
VSEN

BOOTA1

OFSA
SET1
VSENA

26

UGATEA1

33

SET2

@

OFS

FBA

25

PHASEA1

32

SET1

SVT

31

24

LGATEA1

FBA

OFSA

BOOT1

SVD

VSENA

23

SVC

COMPA

OFS

UGATE1

IBIAS

22

PHASE1

PWROK

100K_0402_5% COMPA 30

PR524 0_0402_5%
2
SVT

VDDIO

VCC

1

LGATE1

IMONA

28

21

PVCC

V064

29

20

PR523 0_0402_5%
2
SVD

LGATE2

IMON

VCC

PR522 0_0402_5%
2
SVC

1

GND

1

PL502
0.36UH_PDME064T-R36MS_24A_20%
4
1
+APU_CORE_NB

PU500
RT8880AGQW_QFN52_6X6

PHASE2

2 IBIAS

18

VDDIO

VSEN

COMP
17

FB

COMP

IMONA

1

1000P_0402_50V7K

1

PC517
2
1

2
2

1

PR535
18.7K_0402_1%

2
1

VREF

@

PH502
100K_0402_1%_TSM0B104F4251RZ

1000P_0402_50V7K
PC526

PR526
22K_0402_1%

2

1

PR525
35.7K_0402_1%

2
2

PR531
5.23K_0402_1%
2
1

PR534
22.6K_0402_1%

1
1
2

1
2

3

PH501
100K_0402_1%_TSM0B104F4251RZ

PR530
1.58K_0402_1%
2
1

PC525
0.47U_0402_16V4Z

1

@

<6> APU_SVT

16

19

PC518
1

@

<6> APU_SVD

VREF

PR521 0_0402_5%
2

2

@

<6> APU_SVC

15

1

1000P_0402_50V7K

@
<6> APU_PWRGD

12

13
PC516
1U_0402_6.3V6K+1.8VS
2
1

IMON

VCC

RGND

OCP_L

RGND

14

2

3
2
1

VCC VCC

VCC VCC

B+

PC519
10U_0805_25V6K
2
1

4

LGATE_NB1

2

PR540 EMI@
4.7_1206_5%

PHASE_NB1

+

2

EMI@ PC527
680P_0603_50V7K

0.22U_0603_25V7K

APU_B+

2
110K_0402_1%

PC511
68P_0402_50V8J
2
1

1

PQ503
PQ506
MDU1512RH 1N POWERDFN56-8 S TR MDU1516URH 1N POWERDFN56-8
2
1 2
1

PR501
1

PC513
560P_0402_50V7K
1
2

+
2

4.7_1206_5%

PR512
PC510
2.2_0603_5%
1
2
2 BOOT_NB1-1
BOOT_NB11

PR515
82K_0402_1%
2
1

PR513
10K_0402_1%
1
2

1

680P_0603_50V7K

PC509 @
330P_0402_50V

3
2
1

2

5

1

4

EMI@ PR517
2
1

UGATE_NB1

PR569
2.2_0603_5%
1
2

EMI@ PC514
2
1

2

2
1

1

APU_B+
PC505
10U_0805_25V6K
2
1

5

PR505

@ PR507
0_0402_5%

@ PR506
0_0402_5%

PL501 EMI@
HCB2012KF-121T50_0805

@EMI@PC534
@EMI@
PC534
2200P_0402_50V7K
2
1

1

1

PR504

+APU_CORE

PQ501
S TR MDU1516URH 1N POWERDFN56-8

10_0402_5%
1
2

2

10_0402_5%
1
2

CPU controller (36.1),Driver (36.2) Support component (36.3)

0.01U_0402_50V7K
PC503

PQ502
MDU1512RH 1N POWERDFN56-8

1

<6> APU_VDD_SEN_L

B

C

D

Rev
1.0

LA9868P

Thursday, May 16, 2013

Sheet
E

38

of

42

5

4

3

2

1

D

D

VGA controller (43.1),Driver (43.2) Support component (43.3)
EMI Part (47.1)
PL801 VGA@
HCB2012KF-121T50_0805

+VGA_CORE
TDC 21A
EDC 31.5A
OCP current ??A
FSW=??kHz
DCR 1.4m ohm +-5%
TYP
H/S Rds(on) :11.7mohm ,
L/S Rds(on) :2.7mohm ,

VGA@

2

2.61K_0402_1%

VGA@ PH7
1
2

1.15V
1.125V

B value:4250K±2%

Layout Note:
Place near Choke

1

2

VGA@ PC820
0.047U_0402_16V7K
1

0

0

1.100V

0

1

1.075V

1

0

1.050V

1

1

1.025V

0

1.000V

0

1

0.975V

1

0

0

0.950V

1

1

1

0.925V

1
1

1

0

0

0

0.900V

1

0

0

1

0.875V

1

1

0

1

0

0.850V

1

1

0

1

1

0.825V

1

1

1

0

0

0.800V

1

1

1

0

1

0.775V

Default

1
@

@

@

2
1
@ PR836
10K_0402_1%
2
1
VGA@ PR837
10K_0402_1%
2
1
@ PR838
10K_0402_1%
2
1
PR839
10K_0402_1%
2
1
VGA@ PR840
10K_0402_1%

1

@

@

<13>

1

2
0_0402_5%

1

0

PR821

0

1

@

1

1

<13>

0

GPU_ISUM-

GPU_VID1
<13>

1

GPU_VID4
<14,8>

0

GPU_VID3
<13>
GPU_VID2
<13>

1

GPU_VID5

0

0

VGA@ 1PC822 0.1U_0402_16V7K
2
0_0402_5%
PR827
1
2
<13>
0_0402_5%
PR826
1
2
0_0402_5%
PR825
1
2
0_0402_5%
PR824

0

0

0

0

1

0

1

0

VGA@ PR822
1.2K_0402_1%
GPU_ISUM+

2

1

1
1

VDDC

PXS_PWREN

1

1
1

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/27

Deciphered Date

2015/09/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

+VPU_COREP
Size
C
Date:

5

4

B

2

VGA@ PC821
0.1U_0402_16V7K

GPU_DPRSLPVR
VGA@ 47K_0402_1%
PR828
2
1

1

GPIO20
VID2

+
2

2

GPIO15
VID1
0
1

GPIO29
VID3

1

1
2
VGA@PR818
VGA@PR818
11K_0402_1%

1
A

GPIO30
VID4
1
1

2

10KB_0402_5%_ERTJ1VR103J

@

GPIO6
VID5
0
0

1

VGA@ PC900
390U_2.5V_M

PC816
680P_0603_50V7K

VGA@ PR815
2
1

VGA@ PC899
390U_2.5V_M

@ PR811
0_0402_5%

+
@EMI@

2

+VGA_CORE

1

2

1

5

3

VGA@ PR810
3.65K_0805_1%

Rds(on):2.7mΩ~3.3mΩ
+3VGS

4

2

0.1U_0402_16V7K

2

VID2

VID3

VID4

VID5

VGA@
PC817
2.2U_0603_6.3V6K

4

1

+5VALW
3
2
1

1

1

21

1
PR814
1_0603_5%

VGA@ PR718
1.8K_0402_1%
2

VGA@

4

20
2

PQ802
MDU1512RH 1N POWERDFN56-8

19

1

1

3
2
1
5

DL_GPU

@EMI@
PR808
4.7_1206_5%

2

14

2
13

12
VIN

IMON

11
VDD

9

RTN

ISUM-

BOOT

18

0.36UH_PDME064T-R36MS_24A_20%

1

8.06K_0402_1%

<15,8> VGA_PWRGD

B

17

VGA@ PL802

2

VGA@ PR817

LX_GPU

VGA@ PC823

1
VGA@
PR835
120K_0402_1%

1

VID1

DH_GPU

MAX
14mohm
3.3mohm

C

2
1
VGA@ PR823
10K_0402_1%
2
1
@ PR830
10K_0402_1%
2
1
VGA@ PR831
10K_0402_1%
2
1
VGA@ PR832
10K_0402_1%
2
1
@ PR833
10K_0402_1%

VGA@PR816
715_0402_1%
PC818
1000P_0402_50V7K

VGA@

2

VID0

CLK_EN#

4

22

2

VCCP

PGOOD

23

2 1

+3VS

LGATE

RBIAS

24

1

VGA@ PC819
56P_0402_50V8
2
1

VW

25

PC814
390P_0402_50V7K

2
1

147K for CPU
47K for GPU

VGA@

3

28

2

2 1

1

2
1
VGA@PR809
47K_0402_1%

VGA@
PC815
1000P_0402_50V7K
2
1

VGA@ PU801
ISL62881CHRTZ-T_TQFN28_4X4

15
16

1

PR813
226K_0402_1%

VSSP

VID6

VGA@
VGA@ PR812
2.37K_0402_1%
1
2

COMP

VR_ON

4

PHASE

FB

DPRSLPVR

5

UGATE

26

6

VGA@

VSEN

27

7

ISUM+

AGND

PC811
330P_0402_50V7K

1
2
VGA@ PR806
10_0402_5%

8

1

VGA@

+VGA_CORE

VGA@ PR805
VGA@PC810
VGA@
PC810
2.2_0603_5% 0.1U_0603_25V7K
2
1
2
1
BST_GPU
PR841 VGA@
0_0402_1%

PR829 0_0402_5%
2

2

1

<16> VCC_GPU_SENSE

29

C

10

VGA@ PC812
330P_0402_50V7K

2

<16> VSS_GPU_SENSE

GPU_ISUM-

5

+5VALW
GPU_ISUM+

VGA@ PC809
1000P_0402_50V7K
2
1

VGA@ PQ803
MDU1512RH 1N POWERDFN56-8

PR804
10_0402_5%
2
1

VGA@ PQ801
S TR MDU1516URH 1N POWERDFN56-8

2

2

VGA@ PC806
1U_0603_6.3V6M

VGA@

3
2
1

1 2

PR802
1_0603_5%

VGA@ PR801
1_0603_5%
2
1
1

+5VALW

VGA@ PC807
0.22U_0603_25V7K

VGA@ PC804
10U_0805_25V6K
2
1

@EMI@ PC802
2200P_0402_50V7K
2
1

VGA@ PC803
10U_0805_25V6K
2
1

1

GPU_B+

2

2

1

B+

3

2

Document Number

Rev
1.0

LA-9868P
Thursday, May 16, 2013

Sheet
1

39

of

42

+

2

5

1

+

2
1

+

2
@

4

VGA@ PC1051
1U_0402_6.3V6K
2
1
VGA@PC1052
VGA@
PC1052
1U_0402_6.3V6K
2
1

VGA@ PC1060
1U_0402_6.3V6K
2
1
VGA@ PC1068
1U_0402_6.3V6K
2
1

Security Classification

Issued Date
2012/09/27

3

VGA@ PC1049
1U_0402_6.3V6K
2
1

VGA@ PC1059
1U_0402_6.3V6K
2
1

VGA@ PC1058

VGA@ PC1067
1U_0402_6.3V6K
2
1

VGA@ PC1047
1U_0402_6.3V6K
2
1
VGA@ PC1057
1U_0402_6.3V6K
2
1

VGA@ PC1065
1U_0402_6.3V6K
2
1

1

2

1

1

1

2

1

1

1

kabini

1

2

560uF*4.5m

1U_0402_6.3V6K
PC1026

10uF
(0603)

Compal Secret Data

Deciphered Date
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size
A3
Date:

1U_0402_6.3V6K
PC1027

1u
(0402)

Thursday, May 16, 2013
Sheet

1

@

C

0.22uF

40

1U_0402_6.3V6K
PC1029

1

1U_0402_6.3V6K
PC1028

1

1

1

1

1

2

1U_0402_6.3V6K
PC1024

2

1U_0402_6.3V6K
PC1023

2

1U_0402_6.3V6K
PC1022

2

1U_0402_6.3V6K
PC1021

2

1U_0402_6.3V6K
PC1020

2

330U_D2_2V_Y

PC1033

PC1032

2

1

1
1U_0402_6.3V6K
PC1003

560U_D2_2VM_R4.5M

PC1009
10U_0603_6.3V6M

2

PC1008
10U_0603_6.3V6M

2

1

1

@

+

1

2

PC1007
10U_0603_6.3V6M
2
1

1

PC1002
10U_0603_6.3V6M

2

1

1

1
PC1005
10U_0603_6.3V6M

2

PC1036
180P_0402_50V8J
2
1

1U_0402_6.3V6K
PC1013

2

1U_0402_6.3V6K
PC1012

2

2

2

1

+

2

2

1U_0402_6.3V6K
PC1011

1

PC1001
10U_0603_6.3V6M

1

2

1

Local

2

2
1U_0402_6.3V6K
PC1010

2
PC1000
10U_0603_6.3V6M

3

1U_0402_6.3V6K
PC1025

2

1U_0402_6.3V6K
PC1018

2

1U_0402_6.3V6K
PC1017

2

1U_0402_6.3V6K
PC1016

1

+APU_CORE_NB

VGA@ PC1048
1U_0402_6.3V6K
2
1

VGA@ PC1046
1U_0402_6.3V6K
2
1

VGA@ PC1056
1U_0402_6.3V6K
2
1

VGA@PC1064
VGA@
PC1064
1U_0402_6.3V6K
2
1

2
1U_0402_6.3V6K
PC1015

2
1U_0402_6.3V6K
PC1004

+APU_CORE_NB

1U_0402_6.3V6K
2
1

VGA@ PC1079
1U_0402_6.3V6K
2
1

VGA@ PC1055
1U_0402_6.3V6K
2
1

VGA@ PC1063
1U_0402_6.3V6K
2
1

1

4

VGA@ PC1066
1U_0402_6.3V6K
2
1

VGA@ PC1045
1U_0402_6.3V6K
2
1

VGA@ PC1054
1U_0402_6.3V6K
2
1

VGA@ PC1041
10U_0603_6.3V6M
2
1

VGA@ PC1044
1U_0402_6.3V6K
2
1

VGA@ PC1062
1U_0402_6.3V6K
2
1

VGA@PC1040
10U_0603_6.3V6M
2
1

VGA@ PC1078
1U_0402_6.3V6K
2
1

VGA@ PC1053
1U_0402_6.3V6K
2
1

VGA@PC1042
10U_0603_6.3V6M
2
1

VGA@ PC1077
1U_0402_6.3V6K
2
1

+VGA_CORE

PC1061
1U_0402_6.3V6K
2
1

VGA@PC1043
VGA@
PC1043
10U_0603_6.3V6M
2
1

VGA@PC1076
VGA@
PC1076
1U_0402_6.3V6K
2
1

Local

VGA@ PC1050
1U_0402_6.3V6K
2
1

+APU_CORE

VGA@ PC1069
1U_0402_6.3V6K
2
1

2

+APU_CORE

VGA@

1
1U_0402_6.3V6K
PC1014

+APU_CORE

PC1102
330U_D2_2V_Y

B

PC1101
330U_D2_2V_Y

@

PC1019
180P_0402_50V8J
2
1

D

PC1100
560U_D2_2VM_R4.5M

PC1006
0.22U_0402_16V7K
2
1

5
1

CPU_Core output CAP (Including MLCC) 36.4
GFX output CAP (Including MLCC) 36.5
+APU_CORE_NB

+VGA_CORE
VDD
2
3
11
1

VDD_NB
1
4
9
1

of

D

180P
(0402)

Document Number

LA-9868P
42

C

+VDDC
VGA_Core output CAP (Including MLCC 43.9)

B

A
A

Compal Electronics, Inc.
PROCESSOR DECOUPLING
Rev
1.0

5

4

3

2

Version change list (P.I.R. List)
Item

1

Page 1 of 1
for PWR

Reason for change

PG#

Modify List

Date

Phase

D

D

PIR_VNKAE_DIS-UMA1226.xlsx (命令列)

C

C

B

B

A

A

2012/09/27

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2015/09/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

PIR (PWR)
Rev
1.0

VCUAA
Sheet

Thursday, May 16, 2013
1

41

of

42

5

4

3

2

1

HW PIR (Product Improve Record)
VNKAE LA-9868P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.3 TO 1.0
D

C

----------------------------------------------------------------------------------------------------------------------------------Item Page
Date
Request
Solution
----------------------------------------------------------------------------------------------------------------------------------1
2013/03/5a
Change APU to PR sample
PR sample PN SA00006R300, SKU 4519NL51L03
2
P30
2013/03/5a
PCB cut outline
Remove SW1
3
P06
2013/03/5a
co-lay eDP & LVDS
Due to common eDP cable, swap Lane0 and Lane2 to follow common design; replace CC106, CC102 with RC75, RC76; add RC77, RC78, CC109, CC110.
4
P30
2013/03/06a
no need power button
Remove SW2
5
P30
2013/03/06a
Add C24(0.1uF) to ON/OFFBTN# and set to ESD@
6
P06
2013/03/06a
Add CC99(1000pF) to APU_RST# and set to ESD@
7
2013/03/06a
Change CC93, CC94, CC97, CB6 to ESD@
8
P07
2013/03/06a
BIOS ROM
Change UC5 to always mount on 43-level
9
P07
2013/03/06a
For vendor recommand
Change CC22, CC23 from 5.6pF to 4.7pF(SE07147AC80)
10
P28
2013/03/07a
co-lay card reader for EMI request
Update card reader schematic for co-lay GL834L and RT5117
11
P09
2013/03/07b
Remove 0ohm res
Change RC116, RC117, RC119, RC120 to short pad symbol
12
P26
2013/03/07b
Remove 0ohm res
Change RA18, RA24, RA22, RA36, RA37 to short pad symbol
13
P05
2013/03/07b
Remove 0ohm res
Change R2 to short pad symbol
14
P20
2013/03/07b
Remove 0ohm res
Remove R106
15
P29
2013/03/07b
Remove 0ohm res
Change RB36 to short pad symbol
16
2013/03/11a
Update power schematic
17
P28
2013/03/12a
Remove co-lay RT5117
Update card reader schematic
18
P30
2013/03/18a
Change PCB PN
Change PCB PN to DAZ0WJ00100
19
P30
2013/03/18a
Remove DC-IN JACK PN due to BOM structure changed
20
P24
2013/03/18a
Remove 0ohm res
Change RR1, RR2 to short pad symbol
21
P08
2013/03/18a
For power consumption improve
Change VRAM_SEL to TOUCH_SEL for BTO to improve battery life.
22
P26
2013/03/25a
ESD request
Change DA1, CA30, CA31, CA34, CA36 to varistor(SCV00001K00)
23
P08
2013/03/25a
vendor recommand
Change CC31 to 8pF(SE00000DB80)
24
P24
2013/03/25a
Remove 0ohm res
Change RR1, RR2 to 0 ohm

D

C

B

B

A

A

Title
HW PIR
Size
B
Date:
5

4

3

2

Document Number
LA-9868P
Thursday, May 16, 2013

Rev
1.0
Sheet
1

42

of

42

www.s-manuals.com



---

Source Exif Data:

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Format                          : application/pdf
Creator                         : 
Title                           : Compal LA-9868P - Schematics. www.s-manuals.com.
Subject                         : Compal LA-9868P - Schematics. www.s-manuals.com.
Create Date                     : 2013:05:16 16:46:42
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