Compal LA A131P Schematics. Www.s Manuals.com. R1.0 Schematics

User Manual: Motherboard Compal LA-A131P V4DA2 - Schematics. Free.

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B

C

D

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Compal Confidential
1

Model Name : V4DA2
File Name : LA-A131P
BOM P/N:43

1

ZZZ1

LA-A131P
DAA00072010
ZZZ2

Compal Confidential

LS-A131P
DA4001PG010
ZZZ3

2

2

LS-A132P
DA600100010

V4DA2 M/B Schematics Document

ZZZ4

Haswell ULT Processor + Lynx Point - LP PCH+AMD Mars

LS-A133P
DA600101010
ZZZ5

LS-A134P
DA4001PH010
ZZZ6

2013-08-05

LS-A135P
DA600102010
3

3

ZZZ7

Rev:1.0

HDMI LOGO
RO0000003HM
45@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/20

2013/07/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Cover Page
Size Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Monday, August 05, 2013

Sheet

E

1

of

57

Rev
1.0

A

B

C

D

E

Compal Confidential

204pin DDRIII-SO-DIMM X1

AMD PX5.5
Mars M2-XT
with DDR3 * 8pcs

1

PEG 2.0x4

PEG(DIS)

Dual Channel

5GT/s PER LANE
CLK=100MHz

page18~24

eDP Conn.
page 25

page 15

BANK 0, 1, 2, 3

Memory BUS(DDRIII)

Intel Haswell ULT

DDRIII-ON BOARD 4G 256Mx16

1.35V DDR3L 1033/1333/1600

Haswell ULT

1

Processor

eDP

page 23 ,24

OPI
HDMI/DP SW.

HDMI/DP
DOCK CONN.

page 28

CRT CH2

CRT SW.

page 37

MIDI
CHC

MIDI
CHB

page 27

RJ45 Conn.

HDMI CH1
TMDS/DP

HDMI Conn.
page 28

CRT
CH1

CRT Conn.

USB port 0,1,3

WLAN
for BT

CMOS
Camera

USB port 6

USB port 5

page 35

USBx8

3.3V 24MHz

HD Audio
SPI

CLK=100MHz

3G
Card

Finger
Print

USB port 4

SATA x 6 (GEN2 3.0GT/S ,GEN3 6GT/S)

LAN SW.

page 25

page 34

3.3V 48MHz

DP x 2 lanes
2.7GT/s

PCI-Express x 8 (PCIE2.0 5GT/s)

2

USB port 2
page 37

PCH
page 26

USB 3.0
conn x3

Lynx Point - LP

page 27

DP to VGA
ITE IT6511FN

page 32

DOCK CONN.

CLK=100MHz

2

USB port 7

page 34

page 38

1168pin BGA

page 31

page 04~14

MIDI
port 2

port 4

LAN(GbE)

MINI Card

Intel I218

WLAN+BT
(Combo)

page 31

SPI ROM x2
(8M+2M)

port 6

LPC BUS

Card reader
RTS5229
Conn.

page 34

page 7

CLK=33MHz

page 38

GEN3

GEN3

port 1

port 0

mSATA
MINI Card
page 34

SATA
HDD
Conn.

page 33

SM BUS

TPM
Module

page 29

HDA Codec
ALC3225X-VB6

NFC
Module

page 38

page 30

HP
Jack

HP
MIC
LINE IN

page 33

MIC
Jack

Int.
Speaker

page 33

page 33

3

3

DOCK CONN.
LS-9581P
FUN/B

Fan

ENE KB9012

page 37

G-Sensor

page 38
page 39

page 36

page 29

LS-9582P
USB/B

page 35

Touch Pad

LS-9583P
CardReader/B

RTC CKT.

page 38

page 38

Int.KBD
page 38

page 06
4

LS-9584P
LID/B

page 38

Docking1/B page

LS-9585P
FP/B

4

LS-9586P
37

DC/DC Interface CKT.
page 40

Docking2/B

page 38

Power Circuit DC/DC
page 42~53

A

B

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

LS-9587P

2012/07/20

2013/07/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

D

Title

Block Diagrams
Size Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

E

2

of

57

Rev
1.0

A

B

Voltage Rails
Power Plane

1

AC
Description

AC

C

AC

AC

DC

DC

DC

D

SIGNAL

+VALW

+V

+VS

HIGH

HIGH

HIGH

ON

ON

ON

ON

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

HIGH

ON

OFF

OFF

OFF

ON

S5 (Soft OFF)

LOW

LOW

LOW

ON

OFF

OFF

OFF

ON

ON

ON

ON

ON

Board ID / SKU ID Table for AD channel

ON*

ON*

ON*

ON*

ON*

ON*

S0

S3

S4

S5

S3

S4

S5

+RTCVCC

RTC power

ON

ON

ON

ON

ON

ON

ON

VIN

Adapter power supply (19V)

N/A

ON

ON

ON

OFF

OFF

OFF

BATT+

Battery power supply (9V or 19V)

N/A

N/A

N/A

N/A

ON

ON

ON

B+

AC or battery power rail for power circuit.

ON

ON

ON

ON

ON

ON

ON

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

OFF

OFF

OFF

OFF

+VGA_CORE

Core voltage for GPU

ON**

OFF

OFF

OFF

OFF

OFF

OFF

+5VALW

+5VALWP to +5VALW power rail

ON

ON

ON

ON

ON

ON

+3VALW

+3VALW always on power rail

ON

ON

ON

ON

ON

+3VALW_PCH

+3VALW to +3VALW_PCH power rail for PCH

ON

ON

ON

ON

+3VM

+3VALW to +3VM power rail for PCH

ON

ON*

ON*

ON*

+1.05VM

+1.05VS_VTT to +1.05VM switched power rail for CPU & PCH

ON

ON*

ON*

ON*

+1.05VS_VTT

+1.05VSP to +1.05VS_VTT switched power rail for CPU & PCH

ON

OFF

OFF

OFF

OFF

OFF

OFF

+1.5VS

+1.5VSP to +1.5VS switched power rail

ON

OFF

OFF

OFF

OFF

OFF

OFF

+1.35V

+1.35VP to +1.35V switched power rail for DDR terminator

ON

ON

OFF

OFF

ON

OFF

OFF

+0.675VS

+0.675VSP to +0.675VS switched power rail for DDR terminator

ON

OFF

OFF

OFF

OFF

OFF

OFF

+3VS

+3VALW to +3VS power rail

ON

OFF

OFF

OFF

OFF

OFF

OFF

+5VS

+5VALW to +5VS switched power rail

ON

OFF

OFF

OFF

OFF

OFF

OFF

+3VSDGPU

+3VS to +3VSDGPU power rail

ON**

OFF

OFF

OFF

OFF

OFF

OFF

+1.5VSDGPU

+1.5V to +1.5VSDGPU switched power rail for GPU

ON**

OFF

OFF

OFF

OFF

OFF

OFF

+1.8VSDGPU

+1.8VSDGPU switched power rail for GPU

ON**

OFF

OFF

OFF

OFF

OFF

OFF
OFF

+0.95VSDGPU

+1.8VSDGPU switched power rail for GPU

ON**

OFF

OFF

OFF

OFF

OFF

+3V_LAN

LAN CHIP POWER RAIL

ON*

ON*

ON*

OFF

OFF

OFF

OFF

+3VS_WLAN

WLAN MODULE POWER RAIL

ON*

ON*

ON*

OFF

OFF

OFF

OFF

+USB3_VCCA

USB Charger PORT0 & PORT9 POWER POWER RAIL

ON

ON

ON

ON

ON*

ON*

ON*

STATE

SLP_S3# SLP_S4# SLP_S5#

E

Full ON
S0(Power On Suspend)

Vcc
Ra/Rc/Re
Board ID

0
1
2
3
4
5
6
7

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

Clock

BOARD ID Table
V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

USB 2.0

BTO Option Table
Port
0
1
2
3
4
5
6
7

Note : ON* WILL DEPEND ON SLP_A# TO TURN ON OR OFF(ME FIRMWARE CONTROL)

EHCI

Note : ON** Depend on Optimus ON/OFF.
Note : ON* Depend on LAN wake SPEC

EC SM Bus1 address
Device

Address

Smart Battery

0001 011X b

EC SM Bus2 address
Device

On Board Thermal Senser(CPU)
On Board Thermal Senser(GPU)
PCH

PCH SM Bus address
Device

DIMM0
DIMM0

A0
A4

1010 000Xb
1010 010Xb
0011 000xb

USB 3.0 Port
1
XHCI
2

PCH SM Bus0 address

Address

ChannelA
ChannelB
G-sensor

Address

1001_101xb
1001_100xb
0100_1100b
0100_1011b

On Board RAM(SPD)
JDIMM1(SPD)

Device

Address

LAN
NFC

1100_100xb
0010_100xb

BTO Item
Unpop
Connector
UMA Only
DISCRETE
CPU
CPU
CPU
DRAM ELPIDA0
DRAM HYNIXR0
NFC Function
3G Function
VPRO Function
NO VPRO Function
EMI SOLUTION
UMA Part Count
VGA Part Count
ESD SOLUTION
VRAM HYNIX0
VRAM HYNIX1

USB Port

0.8G

SA000067060 (S IC CL8064701325206 QDJB B1 0.8G BGA)

1.2G

SA00006G120 (S IC CL8064701325204 QDJ9 B1 1.2G BGA)

GPU BOM Config
MARS-XT-M2

SA000061J10 (S IC 216-0842000 A0 MARS XT M2 FCBGA 0FA)

USB port 3.0 (Left side)
DOCK USB3.0
USB Port 3.0 (I/O board)
Mini Card(3G)
Camera
Mini Card(WLAN+BT)
Finger Print

USB Port 3.0 (I/O board)
USB3 (Left side)

PCI Express Port
USB 3.0 DOCK

1
2
3
4
5-L0
5-L1
5-L2
5-L3
6-L0

CPU BOM Config
3

USB Port 3.0 (I/O board)

PCIE Table
Port

PCB Revision
0.1

Board ID
0
1
2
3
4
5
6
7

USB Port Table

2

Note : ON* WILL DEPEND ON BATTERY CAPACITY TO TURN ON OR OFF

1

USB 3.0 (I/O board)
LAN

BOM Structure
@
CONN@
UMA@
VGA@

2

ELP0@
HYNIXR0@
NFC@
3G@
VPRO@
NOVPRO@
EMI@
PC@
VGAPC@
ESD@
HYNIX0@
HYNIX1@

3

WLAN

VGA

CardReader

VRAM BOM Config
HYNIX

128*16

SA00003YO90(S IC D3 128M16 H5TQ2G63DFR-11C FBGA ABO!)

HYNIX0@

HYNIX

128*16

SA00006H430(S IC D3 128M16 H5TC2G63FFR-11C FBGA ABO! )

HYNIX1@

RAM BOM Config
ELPDIA

256*16

SA000059110(S IC D3 256M16 EDJ4216EBBG-DJ-F ABO!)

ELP0@

ELPDIA

256*16

SA00005HT50(S IC 256MX16/1600 EDJ4216EFBG-GN-F FBGA 96P ABO !)

ELP1@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/20

Deciphered Date

2013/07/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Notes List
Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic

Tuesday, July 30, 2013

Sheet

E

3

of

57

Rev
1.0

5

4

3

2

DP to CRT

<26>
<26>
<26>
<26>

C54
C55
B58
C58
B55
A55
A57
B57

CPU_DP1_N0
CPU_DP1_P0
CPU_DP1_N1
CPU_DP1_P1

D

<28>
<28>
<28>
<28>
<28>
<28>
<28>
<28>

HDMI

C51
C50
C53
B54
C49
B50
A53
B53

CPU_DP2_N0
CPU_DP2_P0
CPU_DP2_N1
CPU_DP2_P1
CPU_DP2_N2
CPU_DP2_P2
CPU_DP2_N3
CPU_DP2_P3

DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3

1

HASWELL_MCP_E

UU1A

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

DDI

EDP

DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3

EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
EDP_RCOMP
EDP_DISP_UTIL

C45
B46
A47
B47

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

<25>
<25>
<25>
<25>

C47
C46
A49
B49

D

A45
B45
D20
A43

EDP_AUXN
EDP_AUXP
EDP_COMP

RU1 1

<25>
<25>

2 24.9_0402_1%

+VCCIOA_OUT

Trace width=20 mils,Spacing=25mil,Max length=100mils
EDP_DISP_UTIL

<25>

Rev1p2

1 OF 19
HASWELL-MCP-E-ULT_BGA1168
@

Reserved for ESD

HASWELL_MCP_E

UU1B

1
CU1
@ESD@
<36>

+1.35V

RU4
470_0603_5%

2

Reserved for ESD

DIMM_DRAMRST#

<15,16,17>

CU4
6.8P_0402_50V8C
@ESD@

D61
K61
N62

@
@

1

RU2
62_0402_5%

1

2

JTAG

H_PROCHOT#_R K63

2 6.8P_0402_50V8C

1
CU3
@ESD@

2 6.8P_0402_50V8C

2 10K_0402_5% H_CPUPWRGD

1
1
1

<15>

2 200_0402_1% SM_RCOMP0
2 120_0402_1% SM_RCOMP1
2 100_0402_1% SM_RCOMP2

UU1

UU1

UU1

CPU_SR16L
SR16L@

CPU_QDJB B1
QDJB@

CPU_QDJ9 B1
QDJ9@

CPU_QEVD
QEVD@

SA00006ST80

SA000067060

SA00006G120

SA00006SL20

UU1

UU1

UU1

UU1

CPU_SR16H
SR16H@

CPU_SR1ED
SR1ED@

CPU_SR1EA
SR1EA@

CPU_SR16Z
SR16Z@

SA00006SS70

SA000072R50

SA000072S50

SA00006SLB0

UU1

UU1

UU1

UU1

CPU_SR16H
SR16H@

CPU_QEAG
QEAG@

CPU_SR170
SR170@

CPU_SR16L
SR16L@

SA00006SS70

SA000072R30

SA00006SMB0

SA00006ST80

C61

DDR_PG_CTRL

AU60
AV60
AU61
DIMM_DRAMRST# AV15
AV61
DDR_PG_CTRL

DDR3 Compensation Signals
System Memory Power Gate Control: Disables the
platform memory VTT regulator in C8 and deeper and S3.

UU1

MISC

RU3
56_0402_5%

1
CU2
@ESD@
RU5 1

RU6
RU7
RU8

Close to AV15

Reserved for ESD 1120

PROC_DETECT
CATERR
PECI

PROCHOT

PROCPWRGD

THERMAL

PRDY
PREQ
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1

J62
K62
E60
E61
E59
F63
F62

XDP_PRDY#_R
XDP_PREQ#_R
XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R
XDP_TDI_R
XDP_TDO_R

@
@
@
@
@
@
@

TU3
TU4
TU5
TU6
TU7
TU8
TU9

@
@

TU10
TU11

C

PWR

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

Reserved for ESD

2

1

2

H_PROCHOT#

1

<36>

TU1
TU2

H_PECI

+1.05VS_VTT

C

2 6.8P_0402_50V8C

DDR3

J60
H60
H61
H62
K59
H63
K60
J61

XDP_BPM#0_R
XDP_BPM#1_R

Rev1p2

2 OF 19
HASWELL-MCP-E-ULT_BGA1168
@

B

B

A

A

UU1

Security Classification

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

Issued Date

CPU_SR16Q
SR16Q@

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SA00006SX70

5

4

3

2

Title

HSW MCP(1/11) DDI,MSIC,XDP

Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Monday, August 05, 2013

Sheet

1

4

of

Rev
1.0
57

5

4

UU1C

3

2

HASWELL_MCP_E

UU1D

D

C

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

1

SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2

DDR CHANNEL A

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1

AU37
AV37
AW36
AY36

SA_CLK_DDR#0
SA_CLK_DDR0
SA_CLK_DDR#1
SA_CLK_DDR1

AU43
AW43
AY42
AY43

<16>
<16>
<17>
<17>

DDRA_CKE0_DIMMA
DDRA_CKE1_DIMMA

AP33
AR32

DDRA_CS0_DIMMA#
DDRA_CS1_DIMMA#

AP32 DDRA_ODT0

DDRA_ODT0

AY34
AW34
AU34

DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#

AU35
AV35
AY41

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

<16>
<17>

<16>
<17>

<16>
<16,17>
<16,17>
<16,17>
<16,17>
<16,17>
<16,17>

AU36 DDR_A_MA0
AY37 DDR_A_MA1
AR38 DDR_A_MA2
AP36 DDR_A_MA3
AU39 DDR_A_MA4
AR36 DDR_A_MA5
AV40 DDR_A_MA6
AW39DDR_A_MA7
AY39 DDR_A_MA8
AU40 DDR_A_MA9
AP35 DDR_A_MA10
AW41DDR_A_MA11
AU41 DDR_A_MA12
AR35 DDR_A_MA13
AV42 DDR_A_MA14
AU42 DDR_A_MA15
AJ61 DDR_A_DQS#0
AN62 DDR_A_DQS#1
AM58 DDR_A_DQS#2
AM55 DDR_A_DQS#3
AV57 DDR_A_DQS#4
AV53 DDR_A_DQS#5
AL43 DDR_A_DQS#6
AL48 DDR_A_DQS#7
AJ62 DDR_A_DQS0
AN61 DDR_A_DQS1
AN58 DDR_A_DQS2
AN55 DDR_A_DQS3
AW57DDR_A_DQS4
AW53DDR_A_DQS5
AL42 DDR_A_DQS6
AL49 DDR_A_DQS7
AP49
AR51
AP51

<16,17>

DDR_A_D[0..63]

<16,17>

DDR_A_MA[0..15]

<16,17>

DDR_A_DQS#[0..7]

<16,17>

DDR_A_DQS[0..7]

SM_DIMM_VREFCA
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

<15,16>
<16>
<15>

AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18

HASWELL_MCP_E

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

DDR CHANNEL B

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

AM38
AN38
AK38
AL38

SB_CLK_DDR#0
SB_CLK_DDR0
SB_CLK_DDR#1
SB_CLK_DDR1

AY49
AU50
AW49
AV50
AM32
AK32
AL32

@

AM35
AK35
AM33

DDRB_CKE0_DIMMB
DDRB_CKE1_DIMMB

<15>
<15>

DDRB_CS0_DIMMB#
DDRB_CS1_DIMMB#

<15>
<15>

D

TU18
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#

AL35
AM36
AU49

<15>
<15>
<15>
<15>

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

<15>
<15>
<15>
<15>
<15>
<15>

AP40 DDR_B_MA0
AR40 DDR_B_MA1
AP42 DDR_B_MA2
AR42 DDR_B_MA3
AR45 DDR_B_MA4
AP45 DDR_B_MA5
AW46DDR_B_MA6
AY46 DDR_B_MA7
AY47 DDR_B_MA8
AU46 DDR_B_MA9
AK36 DDR_B_MA10
AV47 DDR_B_MA11
AU47 DDR_B_MA12
AK33 DDR_B_MA13
AR46 DDR_B_MA14
AP46 DDR_B_MA15

C

AW30DDR_B_DQS#0
AV26 DDR_B_DQS#1
AN28 DDR_B_DQS#2
AN25 DDR_B_DQS#3
AW22DDR_B_DQS#4
AV18 DDR_B_DQS#5
AN21 DDR_B_DQS#6
AN18 DDR_B_DQS#7
AV30 DDR_B_DQS0
AW26DDR_B_DQS1
AM28 DDR_B_DQS2
AM25 DDR_B_DQS3
AV22 DDR_B_DQS4
AW18DDR_B_DQS5
AM21 DDR_B_DQS6
AM18 DDR_B_DQS7

B

<15>

DDR_B_D[0..63]

<15>

DDR_B_MA[0..15]

<15>

DDR_B_DQS#[0..7]

<15>

DDR_B_DQS[0..7]

B

Rev1p2

3 OF 19

Rev1p2

4 OF 19

HASWELL-MCP-E-ULT_BGA1168
@

HASWELL-MCP-E-ULT_BGA1168
@

A

A

Security Classification

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HSW MCP(2/11) DDRIII

Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

1

5

of

Rev
1.0
57

5

4

3

2

1

PCH_RTCX1
PCH_RTCX2
+RTCVCC

YU1
32.768KHZ_12.5PF_FC-135

2

1

CU5
1U_0402_10V6K

1
1
D

CU6
15P_0402_50V8J

2

CU7
15P_0402_50V8J

2

PCH_RTCX1
PCH_RTCX2

ME CMOS
RU10 1

2 1M_0402_5% SM_INTRUDER#
PCH_INTVRMEN
PCH_SRTCRST#
PCH_RTCRST#

2
2

RU12
20K_0402_1%

1

+RTCVCC

1

2

RU11
20K_0402_1%

1

CU8
1U_0402_10V6K

1
@

2

RU13
0_0603_5%

<8>

*

RU14 1
RU16 1

@

HDA_SDIN0
TU20

RTCRST close RAM door

TU21
TU22
TU23

HDA_BIT_CLK
HDA_SYNC
HDA_RST#
HDA_SDIN0
@
HDA_SDOUT
@
@
@

TU24
@

TU25
TU27
TU29

@
PCH_JTAG_RST#
PCH_JTAG_TCK
@ PCH_JTAG_TDI
@ PCH_JTAG_TDO
@ PCH_JTAG_TMS

TU32

@ PCH_TCK_JTAGX

2 RU17

@RF@
1 22P_0402_50V8J
C373 2

HDA for AUDIO
RPU1 EMI@

1
2
3
4

8
7
6
5

RU21 1

HDA_SDO

AW8
AV11
AU8
AY10
AU12
AU11
AW10
AV10
AY8

HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_RST/I2S_MCLK
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_SDO/I2S0_TXD
HDA_DOCK_EN/I2S1_TXD
HDA_DOCK_RST/I2S1_SFRM
I2S1_SCLK

AUDIO

SATA

AU62
AE62
AD61
AE61
AD62
AL11
AC4
AE63
AV2

V1
U1
V6
AC1
A12
L11
K10
C12
U3

SATA_IREF
RSVD
RSVD
SATA_RCOMP
SATALED

JTAG

<29>
<29>
<29>
<29>

HDD1

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

<30>
<30>
<30>
<30>

mSATA

D

CardReader Board

F5
E5
C17 PCIE_PTX_DRX_N6 CU92 1
D17 PCIE_PTX_DRX_P6 CU91 1

SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
PCH_TRST
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
RSVD
RSVD
JTAGX
RSVD

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

J6
H6
B14
C15

SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0

PCH_GPIO34
EC_SMI#
PCH_GPIO36
PCH_GPIO37

PCIE_PRX_DTX_N6
<38>
PCIE_PRX_DTX_P6
<38>
PCIE_PTX_C_DRX_N6
<38>
PCIE_PTX_C_DRX_P6
<38>

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2

EC_SCI#
<36,9>
PCH_GPIO34
<9>
EC_SMI# <36>
+1.05VS_ASATA3PLL
PCH_GPIO36
<9>
PCH_GPIO37
<9>

0_0402_5%

SATA_RCOMP
PCH_SATALED#
RU20 1
10K_0402_5%

2

within 500 mils

RU19 1

2 3.01K_0402_1%

PCH_SATALED#

<38>

+3VS
C

HDA_RST#
HDA_BIT_CLK
HDA_SYNC
HDA_SDOUT

Rev1p2

5 OF 19
HASWELL-MCP-E-ULT_BGA1168
@

33_0804_8P4R_5%
<36>

J8
H8
A17
B17

1 RU15

51_0402_5% 1

HDA_RST_AUDIO#
HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO
HDA_SDOUT_AUDIO

J5
H5
B15
A15

SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3

RTC

SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2

2 330K_0402_5%
2 330K_0402_5%

C

RTCX1
RTCX2
INTRUDER
INTVRMEN
SRTCRST
RTCRST

CMOS

INTVRMEN H: Integrated SUS 1.05V VRM Enable
L: Integrated SUS 1.05V VRM Disable

<33>
<33>
<33>
<33>

AW5
AY5
AU6
AV7
AV6
AU7

PCH_RTCRST#

<33>
+RTCVCC

PCH_INTVRMEN

HASWELL_MCP_E

UU1E

10M_0402_5%

1

RU9

2

2

1

2 0_0402_5%

ME Debug (internal pull-down)
1: Disable Flash Descriptor Security (override)

+RTCBATT

1

20mil
B

B

DU1
BAS40-04_SOT23-3

1

CU9
0.1U_0402_16V4Z

2

3

+RTCVCC

20mil

+CHGRTC

2

A

A

Security Classification

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HSW MCP(3/11) RTC,SATA,XDP

Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Thursday, August 01, 2013

Sheet

1

6

of

Rev
1.0
57

5

4

3

2

HASWELL_MCP_E

UU1F

PCH_GPIO18

C43
C42
U2

PCH_GPIO19

B41
A41
Y5

XTAL24_IN
<9>

RU24

YU2
24MHZ_12PF_X3G024000DC1H

D

CU11
10P_0402_50V8J

<34> CLK_PCIE_MINI1#
<34> CLK_PCIE_MINI1
<34,8> MINI1_CLKREQ#

WLAN

1
@

<18>
<18>

VGA

+3VS

CLK_PCIE_LAN#
CLK_PCIE_LAN

C41
B42
AD1

CLK_PCIE_MINI1#
CLK_PCIE_MINI1
MINI1_CLKREQ#

B38
C37
N1

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18

VGA_CLKREQ#

RSVD
RSVD
DIFFCLK_BIASREF
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8

CLOCK

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20

SIGNALS

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21

CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22

B37
A37
T2

CLK_PCIE_CARD#
CLK_PCIE_CARD
CARD_CLKREQ#

XTAL24_IN
XTAL24_OUT

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19

A39
B39
U5

CLK_PEG_VGA#
CLK_PEG_VGA

CLK_PEG_VGA#
CLK_PEG_VGA

<38> CLK_PCIE_CARD#
<38> CLK_PCIE_CARD
<38,9> CARD_CLKREQ#

CardReader Board

RU33
10K_0402_5%

PCH_GPIO19

<31> CLK_PCIE_LAN#
<31> CLK_PCIE_LAN
<31,9> LAN_CLKREQ#

PCIE LAN

1
CU10
10P_0402_50V8J

2

2

<9>

3
4

1

1
2

PCH_GPIO18

<36,38>
<36,38>
<36,38>
<36,38>
<36,38>

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

AU14
AW12
AY12
AW11
AV12

AA3
Y7
Y4
AC2
AA2
PCH_SPI_MOSI
PCH_SPI_MISO AA4
Y6
PCH_SPI_WP1#
PCH_SPI_HOLD1# AF1

AN15
AP15

1
1
1
1

2
2
2
2

B35
A35

1
2
3
4

/CS
DO(IO1)
/WP(IO2)
GND

CLK_BCLK_ITP#
CLK_BCLK_ITP

<36>
<38>

+3VALW_PCH

1
2
3
4

8 2.2K_0804_8P4R_5%
7
6
5
SML1DATA
SML1CLK

LAD0
LAD1
LAD2
LAD3
LFRAME

SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3

SML0CLK
SML0DATA

SMBALERT/GPIO11
SMBCLK
SMBDATA
SML0ALERT/GPIO60
SMBUS
SML0CLK
SML0DATA
SML1ALERT/PCHHOT/GPIO73
SML1CLK/GPIO75
SML1DATA/GPIO74

LPC

SPI

C-LINK

CL_CLK
CL_DATA
CL_RST

AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3

PCH_GPIO11
PCH_SMBCLK
PCH_SMBDATA
PCH_GPIO60
SML0CLK
SML0DATA
PCH_GPIO73
SML1CLK
SML1DATA

AF2
AD2
AF4

CL_CLK
CL_DATA
CL_RST

+3VM
CU12

1

8
7
6
5

PCH_SPI_MOSI_1
PCH_SPI_CLK_1
PCH_SPI_IO3_1
PCH_SPI_MISO_1

1
2
3
4

PCH_SPI_IO3_1
PCH_SPI_CLK_1
PCH_SPI_MOSI_1

<9>
C

Rev1p2

+3VS

8
7
6
5

PCH_SPI_MOSI
PCH_SPI_CLK
PCH_SPI_HOLD1#
PCH_SPI_MISO
EMI@
33_0804_8P4R_5%

+3VS
RU43
4.7K_0402_5%

QU1A
DMN66D0LDW-7_SOT363-6

@

PCH_SMBDATA

1

6

1

2

3

PCH_SMBCLK

2
RU47

D_CK_SDATA

RU44
4.7K_0402_5%

B

D_CK_SDATA

<15,29,34>

1 PCH_SPI_CLK_1
@EMI@ 33_0402_5%

4

D_CK_SCLK

D_CK_SCLK

<15,29,34>

QU1B
DMN66D0LDW-7_SOT363-6

@EMI@
CU15

SPI ROM ( 4MByte )

1

2
+3VS

0.1U_0402_16V4Z

W25Q32FVSSIQ_SO8
SA00003K820

PCH_SPI_IO3_2
PCH_SPI_CLK_2
PCH_SPI_MOSI_2

@

UU25

RPU4
PCH_SPI_MISO_2
PCH_SPI_IO3_2
PCH_SPI_CLK_2
PCH_SPI_MOSI_2

1
2
3
4

8
7
6
5

PCH_SPI_MISO
PCH_SPI_HOLD1#
PCH_SPI_CLK
PCH_SPI_MOSI
EMI@
33_0804_8P4R_5%

SML1CLK

UU25

1

SA000039A30

SA00006MK00

SA00006N100

UU26

UU26

UU26

2

2
RU49

32M EN25QH32-104HIP SOP 8P
X76EON@

32M MX25L3273EM2I-10G SOP 8P
X76MXI@

SA00006AR00

SA00006N000
4

4

EC_SMB_DA2

<16,19,36>

1 PCH_SPI_CLK_2
@EMI@ 33_0402_5%

A

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

Issued Date

SA00003K820

<16,19,36>

@EMI@

Security Classification

32M W25Q32FVSSIQ SOIC 8P
X76WIN@

EC_SMB_CK2

QU2B
DMN66D0LDW-7_SOT363-6

CU14
10P_0402_50V8J
64M MX25L6473EM2I-10G SOP 8P
X76MXI@

PU 2.2K at EC side (+3VS)

1

3

SML1DATA

Reserve for EMI(Near SPI ROM)

64M EN25QH64-104HIP SOP 8P
X76EON@

QU2A
DMN66D0LDW-7_SOT363-6

6

5

VCC
/HOLD/IO3
CLK
DI/IO0

8
7
6
5

2

UU26

/CS
DO/IO1
/WP/IO2
GND

1 499_0402_1%
1 499_0402_1%

PCH_GPIO60
<9>
SML0CLK <30,31>
SML0DATA <30,31>
PCH_GPIO73
<9>

RPU3

2

+3VM

1
2
3
4

PCH_GPIO11

RU174 2
RU175 2

CL_CLK <34>
CL_DATA <34>
CL_RST <34>

Reserve for EMI(Near SPI ROM)

5

CLK_PCI_LPC
CLK_PCI_TPM

TU36
TU37

HASWELL_MCP_E

CU13
10P_0402_50V8J

W25Q64FVSSIQ SOIC 8P
X76WIN@

@
@

1 22_0402_5%
1 22_0402_5%

Rev1p2

7 OF 19
HASWELL-MCP-E-ULT_BGA1168
@

0.1U_0402_16V4Z

VCC
/HOLD(IO3)
CLK
DI(IO0)

W25Q64FVSSIQ_SO8
SA000039A30

A

D

PCH_SPI_HOLD1#
PCH_SPI_WP1#

UU25

UU25

2 EMI@
2 EMI@

RU31
RU32

2

2 1K_0402_5%
2 1K_0402_5%

SPI ROM ( 8MByte )

PCH_SPI_WP1# 2
RU51

+1.05VS_AXCK_LCPLL

5

RU46 1
RU48 1

PCH_SPI_CS1#
PCH_SPI_MISO_2
1 PCH_SPI_IO2_2
33_0402_5%

2 3.01K_0402_1%

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

CLKOUT_LPC0
CLKOUT_LPC1

2

2

+3VM

PCH_SPI_WP1# 2
RU50

RU25 1

XCLK_BIASREF
RU26
RU27
RU28
RU30

PCH_SMBDATA
PCH_SMBCLK

UU1G
RU34
10K_0402_5%

PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#

B

C35
C34
AK8
AL8

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23

1

VGA_CLKREQ#

PCH_SPI_CS0#
PCH_SPI_MISO_1
1 PCH_SPI_IO2_1
33_0402_5%

K21
M21
C26

HASWELL-MCP-E-ULT_BGA1168
@

2

C

XTAL24_IN
XTAL24_OUT

RPU2

6 OF 19

VGA@

A25
B25

2

1M_0402_5%

XTAL24_OUT

1

1

1

2

1

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title

HSW MCP(4/11) CLK,SPI,SMBUS

Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Monday, August 05, 2013

Sheet

1

7

of

Rev
1.0
57

5

4

3

2

1

+3VS

1

CU180
2
@ESD@ 1

2

RU52
10K_0402_5%

SYS_RESET#

0.01U_0402_16V7K

SYS_RESET#

DSWODVREN - On Die DSW VR Enable

H：Enable(DEFAULT)
* L：Disable

Reserved for ESD
RU54 1
RU55 1

<46>

PM_APWROK

<36>

1
RU63
0_0402_5%

PBTN_OUT#

2

@

1

@

SYS_PWROK RU58 1
RU59 1
RU61 1

@

SUSWARN#

<36> PCH_PWROK
<11,36> VCCST_PG_EC

PBTN_OUT#_R

RU65 1

PCH_RSMRST#

PCH_PWROK_R

@

<34,36,38,8>

<36>

2 10K_0402_5%

RU64 1

PCH_RSMRST#

For Deep Sx need pull-hi to +3VALW
Note: EC is +3VL change to @
<36>

SUSACK#
SYS_RESET#
2 0_0402_5% SYS_PWROK_R
2 0_0402_5%
PCH_PWROK_R
2 0_0402_5%
PM_APWROK
PLT_RST#
PLT_RST#

AK2
AC3
AG2
AY7
AB5
AG7

2 0_0402_5% PCH_RSMRST#_R

AW6
AV4
AL7
AJ8
AN4
AF3
AM5

SUSWARN#
PBTN_OUT#_R
PCH_ACIN
2 8.2K_0402_5% PCH_BATLOW#
PM_SLP_S0#
TU45@
PM_SLP_WLAN#

SUSWARN#

RU66 1

+3VALW_PCH

For Deep Sx need pull-hi to +3VALW

2 0_0402_5%

@
<9>

PM_SLP_WLAN#

SUSACK
SYS_RESET
SYS_PWROK
PCH_PWROK
APWROK
PLTRST

AW7
AV5
AJ5

DSWVRMEN
DPWROK
WAKE

V5
AG4
AE6
AP5

CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63

RSMRST
SUSWARN/SUSPWRDNACK/GPIO30
PWRBTN
ACPRESENT/GPIO31
BATLOW/GPIO72
SLP_S0
SLP_WLAN/GPIO29

DSWODVREN
PCH_RSMRST#_R
PCH_PCIE_WAKE#
1
1K_0402_5%
1
8.2K_0402_5%
CLKRUN#
LPCPD#
SUSCLK
PM_SLP_S5#

PM_SLP_S4# <36>
PM_SLP_S3# <36>
PM_SLP_A# <40,46>
+3VALW_PCH
<36>

1

not support Deep S4,S5 can NC

DDPB_CTRLDATA: Port B Detected

Note: Deep Sx need use EC GPIO for
ACPRESENT function

PCH_ACIN

DDPC_CTRLDATA: Port C Detected
C

VPRO@

*

5

+3VS

B

Y

1

SYS_PWROK

+3VS

<25>
<36>
<25>

2
3

PCH_INV_PWM
ENBKL
PCH_ENVDD

VCC

A
Y

5
4

1

<9>

PCH_GPIO77
G_SEN_INT
DGPU_HOLD_RST#
PCH_GPIO80
TU47

<9> PCH_GPIO77
<29> G_SEN_INT
DGPU_HOLD_RST#

RU73
10K_0402_5%
@

<30,9> MSATA_DET#
<25> TOUCH_RST
<34,9>

2

UU11

VGATE

B8
A9
C6

EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN

DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA

eDP SIDEBAND

2

2

+1.05VS_VTT

NC

JAPS

VGATE_3V

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

PM_SLP_S3#
RU71
10K_0402_5%
@

+3VS

1

+3VALW_PCH

PCH_PWROK

3

UU10
MC74VHC1G08DFT2G_SC70-5
@

RU70
10K_0402_5%

HASWELL_MCP_E

UU1I

2

G

A

1

0: Port B or C is not detected

1

1

VGATE_3V

4

1: Port B or C is detected
(Have internal PD)

RU69
0_0402_5%

P

2

PCH_PWROK

<11,49>

TU43

@
TU46
2
RU67 1
@
10K_0402_5%

PM_SLP_LAN#

RB751V-40-YS_SOD323-2

B

@

PM_SLP_S4#
PM_SLP_S3#
PM_SLP_A#

Rev1p2

8 OF 19

2

2

TU41
TU42

<31,34>

pull-hi to +3VALW

HASWELL-MCP-E-ULT_BGA1168
@

DU3

1

ACIN

D

PCH_PCIE_WAKE#
+3VALW_PCH
For Deep Sx need
+3VS
CLKRUN#
<38>
LPCPD# <38>
SUSCLK <36>
PM_SLP_S5# <36>

2 RU60
2 RU62

PM_SLP_LAN#

RU68
100K_0402_5% VPRO@

<19,36,44>

@

@
@

AJ6
AT4
AL5
AP4
AJ7

SLP_S4
SLP_S3
SLP_A
SLP_SUS
SLP_LAN

+3VALW_PCH

C

2 330K_0402_5%
2 330K_0402_5%

SYSTEM POWER MANAGEMENT

RU57

2 0_0402_5%
RU56 1
NOVPRO@

PM_APWROK

+RTCVCC

HASWELL_MCP_E

UU1H
D

VGATE_3V

MINI_DET#

<36>

U6
P4
N4
N2
AD4

@

U7
L1
L3
R5
L4

MSATA_DET#
PROJECT_ID1
MINI_DET#
PROJECT_ID0

PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME

DISPLAY

GPIO

DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP

B9
C9
D9
D11

RU72 1
DDI2_CTRL_CK
DDI2_CTRL_DATA

C5
B6
B5
A6

DDI1_AUX_DN
DDI2_AUX_DN
DDI1_AUX_DP
DDI2_AUX_DP

+3VALW_PCH

2 2.2K_0402_5%
DDI2_CTRL_CK
<28>
DDI2_CTRL_DATA
<28>

+3VALW_PCH
<6>

DDI1_AUX_DN
DDI2_AUX_DN
DDI1_AUX_DP
DDI2_AUX_DP

PM_SLP_S5#
PM_SLP_S4#
PM_SLP_A#

<26>
<28>
<26>
<28>

PCH_RTCRST#

<37,38>

ON/OFFBTN#
SYS_RESET#
PM_SLP_S0#

GPIO55
GPIO52
GPIO54
GPIO51
GPIO53

DDPB_HPD
DDPC_HPD
EDP_HPD

C8
A8
D6

CPU_DP_HPD
<26>
CPU_HDMI_HPD
<28>
CPU_EDP_HPD
<25>

GND
74AUP1G07GW_TSSOP5
@

B

ACES_50506-01841-P01
CONN@

Rev1p2

9 OF 19

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND
GND

HASWELL-MCP-E-ULT_BGA1168
@
+3VS
RU99
@

1

2 0_0402_5%

8
7
6
5

2
3
4

RU74
0_0402_5%
1
@

RU75
0_0402_5%
1
@

2

TOUCH_RST

2
+3VS
MINI1_CLKREQ#
DEVSLP0 <9>

<34,7>

+3VS
PLT_RST_BUF#

2

PROJECT ID

RU80
10K_0402_5%

RU81
10K_0402_5%

1

2

PROJECT_ID0

2

PROJECT_ID1

RU76
100K_0402_5%
VGA@

OUT

PLT_RST_BUF#

<30,31,34>

1

CU187
0.1U_0402_16V4Z
@ESD@

RU77
100K_0402_5%

2

UU13
MC74VHC1G08DFT2G_SC70-5

2

PLT_RST_BUF#

1

IN2

4

GND

2

IN1

1
RU79
10K_0402_5%
@

2

RU78
10K_0402_5%
@

1

A

UU12
MC74VHC1G08DFT2G_SC70-5
VGA@

+3VS

1

+3VS

<18>

3

IN2

PLTRST_VGA#

1

VCC

2
OUT

PLT_RST#

1

2

4

3

DGPU_HOLD_RST#

IN1

GND

1

PLT_RST#

VCC

5

PCH_GPIO80
MINI1_CLKREQ#
DEVSLP0
10K_0804_8P4R_5%

5

RPU5 1

*V4DA2
Reserved
Reserved
Reserved

PROJECT_ID1 PROJECT_ID0
GPIO54
GPIO53
0
0
0
1
1
0
1
1

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

2013/07/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Size
Document Number
Custom
Date:

5

4

3

2

HSW MCP(5/11) PM,GPIO,DDI
V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

1

8

of

Rev
1.0
57

5

4

3

2

1

+1.05VS_VTT
HASWELL_MCP_E

UU1J

10K_0804_8P4R_5%
PCH_GPIO5
PCH_GPIO1
PCH_GPIO94
PCH_GPIO93
10K_0804_8P4R_5%
8
PCH_GPIO2
7
PCH_GPIO91
6
PCH_GPIO90

8
7
6
5

<25>

PCH_GPIO34
10K_0804_8P4R_5%
8
PCH_GPIO71

7
6
5

RPU148

1
2
3
4

PCH_GPIO34

PCH_GPIO16
PCH_GPIO37
10K_0804_8P4R_5%

RPU158

7
6
5
RPU168

7
6
5

<6>

<36,6>
PCH_GPIO37

PCH_GPIO67
VGA_ON
PCH_GPIO64
PCH_GPIO84
10K_0804_8P4R_5%
1
PCH_GPIO83
2
MSATA_DET#
3
PCH_GPIO3
4
SERIRQ
10K_0804_8P4R_5%
1
MINI_DET#
2
CARD_CLKREQ#
3
PCH_GPIO76

7
6
5

<7>
<8>

EC_SCI#

EC_SCI#

<6>

RU84
0_0402_5%
1
2
@

<8>

DEVSLP0

<30>

DEVSLP1

<33>

PCH_SPKR

PCH_GPIO9
PCH_GPIO10
DEVSLP0
PCH_GPIO70
DEVSLP1
PCH_GPIO39
PCH_SPKR

<30,8>

MINI_DET#
<34,8>
CARD_CLKREQ#
<38,7>

1
2
3
4

DET_SIG#_R

DET_SIG#_R

USB_OC1#
PCH_GPIO8
USB_OC3#
PCH_GPIO73
10K_0804_8P4R_5%
1
PCH_GPIO13
2
PCH_GPIO57

7
6
5

PCH_GPIO11
10K_0804_8P4R_5%
8
DET_SIG#_R_1
7
PCH_GPIO46
6
PCH_GPIO44

8
7
6
5

2
3
4
RPU211

8
7
6
5

2
3
4
RPU221

8
7
6
5

2
3
4
RU91 1
10K_0402_5%

2

0
1
0
1

+3VS

<7>

2

PCH_GPIO11

RU168
10K_0402_5%
@

5

RPU201

GPIO49

0
0
1
1

10K_0804_8P4R_5%
DGPU_HOLD_RST#
PCH_GPIO24
NFC_RST#
10K_0804_8P4R_5%
PCH_GPIO59
PCH_GPIO58
PCH_GPIO14
PCH_GPIO25
10K_0804_8P4R_5%
USB_OC2#
PCH_GPIO60
USB_OC0#
PCH_GPIO9
10K_0804_8P4R_5%
SUSWARN#

DGPU_HOLD_RST#

@
I2C1_SDA

RA38 1

I2C1_SCL

RA39 1

2 2.2K_0402_5%
2 2.2K_0402_5%
@

I2C1_SDA
I2C1_SCL
VGA_ON

<25>
<25>

<40>
C

+3VALW_PCH
+3VALW_PCH

RU86
10K_0402_5%

+3VALW_PCH

PCH_GPIO47

RU171
10K_0402_5%

<8>

@

RU87
10K_0402_5%

+3VS

RU170
10K_0402_5%

1

2
3
4

+3VS

GPIO48

0
0
0
0

SHYNIX0 4G SA00005AV50
SELP0 4G SA00005HT80

<10>

USB_OC3#
<10>
PCH_GPIO73
<7>

3
4

RPU191

GPIO47

<31,7>

1

RPU188
B

USB_OC1#

+3VS

<31,37>

PCH_GPIO70

8
7
6
5

PCH_GPIO83
PCH_GPIO84
PCH_GPIO85
PCH_GPIO86
DGPU_PRSNT#
PCH_GPIO88
PCH_GPIO89
PCH_GPIO90
PCH_GPIO91
PCH_GPIO92
PCH_GPIO93
PCH_GPIO94
PCH_GPIO0
PCH_GPIO1
PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PCH_GPIO5
I2C1_SDA
I2C1_SCL
PCH_GPIO64
VGA_ON
PCH_GPIO66
PCH_GPIO67
PCH_GPIO68
PCH_GPIO69

Rev1p2

10 OF 19

2

RPU17

D

HASWELL-MCP-E-ULT_BGA1168
@

on board ram flag
LAN_CLKREQ#

EC_KBRST# <36>
SERIRQ
<36,38>

2 RU83

RU176
10K_0402_5%
@

10K_0804_8P4R_5%

2

GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81

DET_SIG#_R_1
MSATA_DET#

4

RU85 1
10K_0402_5%
+3VALW_PCH

AM3
AM2
P2
C4
L2
N5
V2

LPIO

1

49.9_0402_1%

PCH_GPIO56

1

2
3
4

TOUCH_INT

GPIO

R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2

SERIRQ
PCH_OPIRCOMP

1

PCH_GPIO18
PCH_GPIO77

6
5

RPU131

<7>
<6>

GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69

H_THERMTRIP#

PCH_GPIO48

RU169
10K_0402_5%
X76SELP0@

PCH_GPIO10
B

+3VS
RU88 1

PCH_GPIO49

@

2 1K_0402_1%

PCH_SPKR

1

RPU121
2
3
4

2 0_0402_5% DEVSLP1

@

PCH_GPIO19
PCH_GPIO36

GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46

D60
V4
T4
AW15
AF20
AB21

2

R658 1

10K_0804_8P4R_5%
PCH_GPIO19
PCH_GPIO36
NFC_DET
EC_KBRST#
10K_0804_8P4R_5%
8
PCH_GPIO18
7
PCH_GPIO77

8
7
6
5

2
3
4

PCH_GPIO56 AG6
PCH_GPIO57 AP1
PCH_GPIO58 AL4
PCH_GPIO59 AT5
PCH_GPIO44 AK4
PCH_GPIO47 AB6
U4
PCH_GPIO48
Y3
PCH_GPIO49
P3
TOUCH_INT
Y2
PCH_GPIO71
AT3
PCH_GPIO13
PCH_GPIO14 AH4
PCH_GPIO25 AM4
DET_SIG#_R_1 AG5
PCH_GPIO46 AG3

CPU/
MISC

2

5

RPU111

LAN_PME#
NFC_RST#
NFC_IRQ

THERMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD

RU173
10K_0402_5%

RU172
10K_0402_5%
X76SHYNIX0@

SPKR / GPIO81 :

NO

REBOOT

2

2
3
4

NFC_DET

<31>
<30>
<30>

BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26

1

RPU101

<30>

P1
AU2
AM7
AD6
Y1
T3
AD5
AN5
AD7
AN3

2

2
3
4

PCH_GPIO76
PCH_GPIO8
LAN_DISABLE_N
EC_LID_OUT#
PCH_GPIO16
NFC_DET
PCH_GPIO24
LAN_PME#
NFC_RST#
NFC_IRQ

<31> LAN_DISABLE_N
<36> EC_LID_OUT#

5

RPU9 1

C

RU82
1K_0402_5%

10K_0804_8P4R_5%

1

D

PCH_GPIO88
PCH_GPIO85
PCH_GPIO89

2

2
3
4

8
7
6
5

1

RPU8 1

1
2
3
4

RPU7

1

TOUCH_INT
PCH_GPIO39
PCH_GPIO92
PCH_GPIO0
10K_0804_8P4R_5%
8
PCH_GPIO68
7
PCH_GPIO69
6
PCH_GPIO4

2

8
7
6
5

2
3
4

2

RPU6 1

1

+3VS

2

+3VS

1: ENABLED

*

For Deep Sx need pull-hi to +3VALW

SUSWARN#

+3VS

+3VALW_PCH

USB_OC2#
<10>
PCH_GPIO60
<7>
USB_OC0#
<10,35>

0: DISABLED (Have internal PD)

PCH_GPIO66
PCH_GPIO86
RU92 1

<8>

2 10K_0402_5%

EC_LID_OUT#

GPIO15 : TLS Confidentiality

RU90 1
RU93 1

RU89 1

@

2 1K_0402_1%

2 1K_0402_1%
2 1K_0402_5%

@

SDIO_D0 / GPIO66 : Top-Block Swap Override

GSPI0_MOSI / GPIO86 : Boot BIOS Strap

+3VS

1

*

RU94
10K_0402_5%
UMA@

1: Intel ME TLS with confidentiality

1: ENABLED

0: Intel ME TLS with no confidentiality

0: SPI ROM (Have internal PD)

*

1: ENABLED

*

0: DISABLED (Have internal PD)

A

2

(Have internal PD)

GPIO87

DGPU_PRSNT#

2

DGPU_PRSNT#

RU95
10K_0402_5%
VGA@

DIS,Optimus
UMA

Security Classification

0
1

5

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

A

4

3

2

Title

HSW MCP(6/11) GPIO,LPIO

Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

1

9

of

Rev
1.0
57

5

4

3

2

HASWELL_MCP_E

UU1K
CU21 1
CU16 1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_GTX_C_HRX_N0 F10
PEG_GTX_C_HRX_P0 E10

PEG_HTX_C_GRX_N0 CU17 1
PEG_HTX_C_GRX_P0 CU22 1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_HTX_GRX_N0
PEG_HTX_GRX_P0

CU23 1
CU18 1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_P1

PEG_HTX_C_GRX_N1 CU24 1
PEG_HTX_C_GRX_P1 CU19 1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_HTX_GRX_N1
PEG_HTX_GRX_P1

CU20 1
CU25 1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_GTX_C_HRX_N2 H10
PEG_GTX_C_HRX_P2 G10

PEG_HTX_C_GRX_N2 CU26 1
PEG_HTX_C_GRX_P2 CU27 1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_HTX_GRX_N2
PEG_HTX_GRX_P2

CU28 1
CU29 1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_P3

PEG_HTX_C_GRX_N3 CU30 1
PEG_HTX_C_GRX_P3 CU31 1

2 VGA@ 0.1U_0402_16V7K
2 VGA@ 0.1U_0402_16V7K

PEG_HTX_GRX_N3
PEG_HTX_GRX_P3

B22
A21

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3

G11
F11

PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

C29
B30

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4

F13
G13

PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

B29
A29

PCH_USB3_RX3_N
PCH_USB3_RX3_P

G17
F17

PCH_USB3_TX3_N
PCH_USB3_TX3_P

C30
C31

PCH_USB3_RX4_N
PCH_USB3_RX4_P

F15
G15

PCH_USB3_TX4_N
PCH_USB3_TX4_P

B31
A31

PEG_GTX_HRX_N0
PEG_GTX_HRX_P0

PEG_GTX_HRX_N[0..3]
PEG_GTX_HRX_P[0..3]
D

<18>
<18>

PEG_HTX_C_GRX_N[0..3]
PEG_HTX_C_GRX_P[0..3]

PEG_GTX_HRX_N1
PEG_GTX_HRX_P1

<18>
<18>

PEG_GTX_HRX_N2
PEG_GTX_HRX_P2

PEG_GTX_HRX_N3
PEG_GTX_HRX_P3

PCIE LAN

<31>
<31>
<31>
<31>

WLAN

C

USB 3.0

USB 3.0

DOCK

(I/O board)

<37>
<37>

CU32
CU33

PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3

<34>
<34>
<34>
<34>

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3

1
1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
CU34
CU35

PCIE_PTX_C_DRX_N4
PCIE_PTX_C_DRX_P4

1
1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCH_USB3_RX3_N
PCH_USB3_RX3_P

<37>
<37>

PCH_USB3_TX3_N
PCH_USB3_TX3_P

<35>
<35>

PCH_USB3_RX4_N
PCH_USB3_RX4_P

<35>
<35>

PCH_USB3_TX4_N
PCH_USB3_TX4_P

C23
C22
F8
E8
B23
A23

B21
C21
E6
F6

PERN5_L0
PERP5_L0

USB2N0
USB2P0

PETN5_L0
PETP5_L0

USB2N1
USB2P1

PERN5_L1
PERP5_L1

USB2N2
USB2P2

PETN5_L1
PETP5_L1

USB2N3
USB2P3

PERN5_L2
PERP5_L2

USB2N4
USB2P4

PETN5_L2
PETP5_L2

USB2N5
USB2P5

PERN5_L3
PERP5_L3

USB2N6
USB2P6

PETN5_L3
PETP5_L3

USB2N7
USB2P7

PERN3
PERP3
USB3.0 P1

PETN3
PETP3

1
RU97
1
RU98
0_0402_5%

@

2 3.01K_0402_1%
2

PCIE_RCOMP
PCIE_IREF

USB3RN1
USB3RP1

USB

PCIe

USB3TN1
USB3TP1

PERN4
PERP4
USB3.0 P2

PETN4
PETP4

USB3RN2
USB3RP2
USB3TN2
USB3TP2

AN8
AM8

USB20_N0
USB20_P0

AR7
AT7

USB20_N1
USB20_P1

AR8
AP8

USB20_N2
USB20_P2

AR10
AT10

USB20_N3
USB20_P3

AM15
AL15

USB20_N4
USB20_P4

AM13
AN13

USB20_N5
USB20_P5

AP11
AN11

USB20_N6
USB20_P6

AR13
AP13

USB20_N7
USB20_P7

G20
H20
C33
B34
E18
F18
B33
A33

USB20_N0
USB20_P0

<35>
<35>

USB20_N1
USB20_P1

<35>
<35>

USB3 (Left side)

USB20_N2
USB20_P2

<37>
<37>

USB3 (DOCK)

USB20_N3
USB20_P3

<35>
<35>

USB3 (I/O board)

USB20_N4
USB20_P4

<34>
<34>

Mini Card(3G)

USB20_N5
USB20_P5

<25>
<25>

Camera

USB20_N6
USB20_P6

<34>
<34>

Mini Card(WLAN+BT)

USB20_N7
USB20_P7

<38>
<38>

Finger Print

USB3 (I/O board)

D

PCH_USB3_RX1_N
PCH_USB3_RX1_P

<35>
<35>

PCH_USB3_TX1_N
PCH_USB3_TX1_P

<35>
<35>

PCH_USB3_RX2_N
PCH_USB3_RX2_P

<35>
<35>

PCH_USB3_TX2_N
PCH_USB3_TX2_P

<35>
<35>

USB3 (I/O Board)

USB3 (Left side)

PERN1/USB3RN3
PERP1/USB3RP3

C

USB3.0 P3 / PCIE P1

PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4

USB3.0 P4 / PCIE P2

USBRBIAS
USBRBIAS
RSVD
RSVD

PETN2/USB3TN4
PETP2/USB3TP4
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43

+1.05VS_AUSB3PLL

E15
E13
A27
B27

1

RSVD
RSVD
PCIE_RCOMP
PCIE_IREF

11 OF 19

AJ10
AJ11
AN10
AM10

AL3
AT1
AH2
AV3

USBRBIAS

RU96 1

2 22.6_0402_1%

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

CAD note:
Route single-end 50-ohms and max 450-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

<35,9>
<9>
<9>
<9>

Rev1p2

HASWELL-MCP-E-ULT_BGA1168
@

B

B

A

A

Security Classification

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HSW MCP(7/11) PCIE,USB

Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

1

10

of

Rev
1.0
57

5

4

3

2

1

L59
J58

+1.35V

+3VALW

+1.05VS_VTT

CU82

D

1

CU109

2

1

22U_0805_6.3V6M
@ESD@
CU90

1

2

22U_0805_6.3V6M
@ESD@

+CPU_CORE

2

E63
AB23
A59
E20
AD23
AA23
AE59

VCC_SENSE_R
RU100

1

2 0_0603_5%

@

+VCCIOA_OUT

VR_SVID_CLK

0_0402_5%

1

@

2 RU101 H_CPU_SVIDCLK

1

VIDSOUT
VCCST_PG_EC_R
2 RU102 PCH_VR_EN
2 RU103 VR_READY
@ CU38
2 0.1U_0402_16V7K

+3VS

1

+1.05VS_VTT

<36,8>

2

VCCST_PG_EC

3

VCC

A
Y

RU105
10K_0402_5%

5
4

1
1

Reserved Only

VCCST_PG_EC_R

RU106
0_0402_5%
1
2
@

VCCST_PWRGD

<36,47>

GND

74AUP1G07GW_TSSOP5

2

+1.05VS_VTT

+1.05VS_VTT
RU107
150_0402_1%
@

SVID ALERT

2

VR_ALERT#

1

1

AB57
AD57
AG57
C24
C28
C32

RU109
10K_0402_5%
@

RU110
43_0402_1%

HSW ULT POWER

100mA

VCC
VCC
VCC
VCC
VCC
VCC

1

2

RU108
75_0402_1%

<49>

VCCST
VCCST
VCCST

CPU_PWR_DEBUG

Place the PU
resistors close to CPU

Idle Voltage :
1.5V~1.65V
Operating Voltage :
1.6V~1.84V

VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

AC22
AE22
AE23

+CPU_CORE

2

1

+1.05VS_VTT

VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY

D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59

CPU_PWR_DEBUG

2

2

C

NC

0_0402_5%
0_0402_5%

1

+3VALW_PCH
UU14

1

<49> VR_ON
<49,8> VGATE

1.4A

VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD

L62
N63
L63
B59
F60
C59

H_CPU_SVIDALRT#
<49>

H_CPU_SVIDALRT#

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

U-Processors 15W
32A

VCC
RSVD
RSVD

+1.05VS_VTT

ESD Reserved

RU104
100K_0402_5%
@

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

F59
N58
AC58

+VCCIO_OUT

22U_0805_6.3V6M
@ESD@

RSVD
RSVD

AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50

+1.05VS_VTT

+CPU_CORE

+CPU_CORE

HASWELL_MCP_E

UU1L

C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57

D

C

Rev1p2

12 OF 19
HASWELL-MCP-E-ULT_BGA1168
@
+1.35V

B

B

VDDQ DECOUPLING

SVID DATA

ESD@

2
0_0402_5%

VCC_SENSE

CU50
22U_0805_6.3V6M

1
2

1 RU114

2

2

1

2

1

2

1

2

CU48
10U_0603_6.3V6M

@

2

1

CU47
10U_0603_6.3V6M

2

2

1

CU46
10U_0603_6.3V6M

VCC_SENSE_R

PC@

Note: 0 ohm PLACED CLOSE TO CPU

2

2

1

ESD@

CU45
10U_0603_6.3V6M

RU113
100_0402_1%

1

CU51
1U_0402_6.3V6K

+CPU_CORE

2

1

CU44
10U_0603_6.3V6M

VIDSOUT

2

1

CU43
10U_0603_6.3V6M

VR_SVID_DATA

2

1

CU42
2.2U_0402_6.3V6M

<49>

RU112
0_0402_5%
2
1
@

PC@
+1.05VS_VTT

1

CU41
2.2U_0402_6.3V6M

1

RU111
130_0402_1%

CU40
2.2U_0402_6.3V6M

Place the PU
resistors close to CPU

CU39
2.2U_0402_6.3V6M

1

+1.05VS_VTT

1
+

CU49
330U_2.5V_M

2

SF000002Z00
PC@

+1.35V : 470UF/2V/7343 *2
10UF/6.3V/0603 * 6
2.2UF/6.3V/0402 * 4

<49>

A

A

VSS_SENSE_R

@

1 RU115

VSS_SENSE

<49>

1

0_0402_5%

Security Classification

RU116
100_0402_1%

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

Issued Date
2

<13>

2

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HSW MCP(8/11) Power

Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

1

11

of

Rev
1.0
57

4

3

2

2

1

2

+1.05VS_AUSB3PLL
+1.05VS_ASATA3PLL

CU54
1U_0402_6.3V6K
@

D

Near K9

+1.05VS_VTT

+1.05VS_AUSB3PLL
CU63
CU66
CU182

2
LU1 1
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%

41mA
1
1
1

HDA --> 3.3V or 1.5V
I2C --> 1.8V

Near B18

2 1U_0402_6.3V6K
2 47U_0805_6.3V6M
2 47U_0805_6.3V6M

2

+3VALW_PCH
TU76

1 CU64

+3VALW

42mA
2
LU2 1
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%

1
1

Near AC9

2

1 22U_0805_6.3V6M

Near V8

2

1 22U_0805_6.3V6M

CU75

1

+1.05VS_APLLOPI

CU77
CU78
CU183

1
1
1

Near AH10
Near AA21

2

CU74
0.1U_0402_16V7K

2 1U_0402_6.3V6K
2 47U_0805_6.3V6M
2 47U_0805_6.3V6M

+1.05VS_AXCK_DCB

+1.05VS_VTT

C

CU80
1 1U_0402_6.3V6K
CU83
1 1U_0402_6.3V6K

Near J18

2 1U_0402_6.3V6K
2 47U_0805_6.3V6M
2 47U_0805_6.3V6M

31mA

CU87 1
CU88 1
CU185 1

2
LU5 1
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%

2

Near R21

200mA

+1.05VS_AXCK_LCPLL

2

Near J17

+1.05VS_AXCK_DCB

CU84 1
CU85 1
CU184 1

18mA

OPI

AC9
AA9
AH10
V8
W9

VCCASW

CORE

VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1

+3VALW_PCH

AXALIA/HDA

VCCHDA
VRM/USB2/AZALIA

DCPSUS2

VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3

GPIO/LCC

VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3

VCCTS1_5
VCC3_3
VCC3_3

SDIO/PLSS

VCCSDIO
VCCSDIO

+RTCVCC

2

CU56

0.1U_0402_16V7K

CU60 2
@

1 0.1U_0402_16V7K

AG14
AG13

1

2

@

1

2

@

1

2
D

+1.05VM
+1.05VS_VTT

J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
J15
K14
K16

U8
T9

CU61 1
CU62 1
CU65 1

2 10U_0603_6.3V6M
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
CU67
1U_0402_6.3V6K

+PCH_VCCDSW 1
RU117
CU68 1
CU70 1
CU72@1

CU76 1

@

2+PCH_VCCDSW_R 1

2 22U_0805_6.3V6M
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K

2 0.1U_0402_16V7K

CU79 1

2

2

0_0402_5%

1U_0402_6.3V6K

+1.05VM

+1.5VS
+3VS

+3VS
C

LPT LP POWER
SUS OSCILLATOR

DCPSUS4

USB2

13 OF 19

Near A20

2 1U_0402_6.3V6K
2 47U_0805_6.3V6M
2 47U_0805_6.3V6M

Y8

2 1U_0402_6.3V6K

USB3

DCPSUS3

THERMAL SENSOR

J18
K19
A20
J17
R21
T21
K18
M20
V21
AE20
AE21

VCCSPI

VCCASW
685mA VCCASW

+3VS

+1.05VS_AXCK_LCPLL

2
LU4 1
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%

SPI

RSVD
VCCAPLL
VCCAPLL

+RTCVCC

CU55 1
AH11
AG10
AE7 +VCCRTCEXT 1
+3VM

CU69

Near B11

@

2
LU3 1
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%

@ AH13

VCCSUS3_3
VCCRTC
DCPRTC

RTC

+3VALW_PCH

2 1U_0402_6.3V6K
2 100U_1206_6.3V6M

57mA

J13
AH14

TU77

CU71
CU73

@

1U_0402_6.3V6K

+1.05VS_ASATA3PLL

+1.05VS_VTT

Y20
AA21
W21

+1.05VS_APLLOPI

Near L10 Near M9

mPHY

0.1U_0402_16V7K
CU59

1

+3VALW_PCH

VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL

0.1U_0402_16V7K
CU58

1

K9
L10
M9
N8
P9
B18
B11

1

HASWELL_MCP_E

UU1M

VCC1_05 : 1714mA
VCCHSIO : 1838mA
CU53
1U_0402_6.3V6K

CU52
1U_0402_6.3V6K

+1.05VS_VTT

2

1U_0402_6.3V6K
CU57

5

RSVD
VCC1_05
VCC1_05

AB8

CU81 @1

AC20
AG16
AG17

2 1U_0402_6.3V6K

+1.05VS_VTT
CU86 1

2

1U_0402_6.3V6K

Rev1p2

HASWELL-MCP-E-ULT_BGA1168
@

+3VALW TO +3VALW(PCH AUX Power)
Short J5 for PCH VCCSUS3.3
+3VALW

JU2 @
JUMP_43X39

B

1

1

2

+3VALW_PCH
B

2

A

A

Security Classification

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HSW MCP(9/11) Power

Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

1

12

of

Rev
1.0
57

5

UU1N
D

C

B

A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29

4

3

HASWELL_MCP_E

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

UU1O

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20

AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

2

HASWELL_MCP_E

UU1P

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
15 OF 19 Rev1p2 VSS

AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31

D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

1

HASWELL_MCP_E

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
16 OF 19 Rev1p2 VSS

H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63

D

C

V58
AH46
V23
E62
AH16

VSS_SENSE_R

<11>

HASWELL-MCP-E-ULT_BGA1168
@

B

HASWELL-MCP-E-ULT_BGA1168
14 OF 19
HASWELL-MCP-E-ULT_BGA1168

@

Rev1p2

@

A

A

Security Classification

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HSW MCP(10/11) GND

Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

1

13

of

Rev
1.0
57

5

4

UU1Q

AY2
AY3
AY60
DC_TEST_AY61_AW61 AY61
DC_TEST_AY62_AW62 AY62
B2
B3
DC_TEST_A3_B3
B61
DC_TEST_A61_B61
B62
DC_TEST_B62_B63
B63
C1
DC_TEST_C1_C2
C2
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3

D

3

2

HASWELL_MCP_E

DAISY_CHAIN_NCTF_AY2
DAISY_CHAIN_NCTF_AY3
DAISY_CHAIN_NCTF_AY60
DAISY_CHAIN_NCTF_AY61
DAISY_CHAIN_NCTF_AY62
DAISY_CHAIN_NCTF_B2
DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_B61
DAISY_CHAIN_NCTF_B62
DAISY_CHAIN_NCTF_B63
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2

1

HASWELL_MCP_E

UU1R

DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
17 OF 19 Rev1p2

A3
A4
A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63

AT2
AU44
AV44
D15

DC_TEST_A3_B3

DC_TEST_A61_B61

F22
H22
J21

DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

HASWELL-MCP-E-ULT_BGA1168
@

N23
R23
T23
U10
D

AL1
AM11
AP7
AU10
AU15
AW14
AY14

Rev1p2

18 OF 19
HASWELL-MCP-E-ULT_BGA1168
@

C

AA62
U63
AA61
U62
CFG_RCOMP

V63
A5

TD_IREF

E1
D1
J20
H18
B12

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP

RESERVED

RSVD
RSVD
RSVD
PROC_OPI_RCOMP

CFG16
CFG18
CFG17
CFG19

RSVD
RSVD

CFG_RCOMP

VSS
VSS

RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
TD_IREF

AV63
AU63

CFG Straps for Processor

C63
C62
B43

C

CFG3

A51
B51

1

CFG3
CFG4

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

RU119
1K_0402_1%
@

L60
N60
W23
Y22
AY15

2

AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60

HASWELL_MCP_E

OPI_COMP

AV62
D58

Physical Debug Enable

P22
N21

1: DISABLED

CFG3

P20
R20

0: ENABLED; SET DFX ENABLED BIT
IN DEBUG INTERFACE MSR
CFG4

Rev1p2

19 OF 19

RU120
1K_0402_5%

HASWELL-MCP-E-ULT_BGA1168
@

B

2

B

(DFX Privacy)

1

UU1S

2

1

RU121

CFG_RCOMP

49.9_0402_1%

2

1

RU122

OPI_COMP

49.9_0402_1%

2

1

RU123

TD_IREF

Display Port Presence Strap

8.2K_0402_5%

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

CFG4

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

A

A

Security Classification

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HSW MCP(11/11) RSVD

Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

1

14

of

Rev
1.0
57

A

B

C

D

E

+1.35V
+1.35V

DDR_B_D40
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D42

+1.35V

All VREF traces should
have 10 mil trace width

Layout Note:
Place near JDIMM1

DDR_B_D56
DDR_B_D57

DDR_B_D59
DDR_B_D58

PC@

1

2

1

2

CU100
1U_0402_6.3V6K

2

CU99
1U_0402_6.3V6K

1

CU98
1U_0402_6.3V6K

2

CU97
1U_0402_6.3V6K

1
PC@

<5>

DDRB_CKE0_DIMMB

DDRB_CKE0_DIMMB
<5>

DDR_B_BS2

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

2

+1.35V

2

1

2

DDR_B_MA3
DDR_B_MA1

CU104
10U_0603_6.3V6M

2

1

CU103
10U_0603_6.3V6M

1

CU102
10U_0603_6.3V6M

2

CU101
10U_0603_6.3V6M

1

DDR_B_MA8
DDR_B_MA5

<5>
<5>

<5>

+1.35V

SB_CLK_DDR0
SB_CLK_DDR#0

SB_CLK_DDR0
SB_CLK_DDR#0

<5>

DDR_B_BS0

<5>
<5>

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDRB_CS1_DIMMB#

DDRB_CS1_DIMMB#

PC@

DDR_B_DQS#0
DDR_B_DQS0

CU186
0.1U_0402_16V4Z
1
@ESD@

DDR_B_D3
DDR_B_D7
DDR_B_D21
DDR_B_D20

3

DDR_B_D22
DDR_B_D23

+0.675VS

DDR_B_D36
DDR_B_D33

2

1

2

DDR_B_D35
DDR_B_D39

+3VS

DDR_B_D52
DDR_B_D49
1

2

1

CU115
1U_0402_6.3V6K

1

CU114
1U_0402_6.3V6K

PC@

CU113
1U_0402_6.3V6K

2

CU112
1U_0402_6.3V6K

1
PC@

DDR_B_DQS#4
DDR_B_DQS4

RU139
10K_0402_5%
2

Layout Note:
Place near JDIMM1.203,204

DDR_B_D48
DDR_B_D53

+3VS
+0.675VS
2

@
1

2

205
RU138
0_0402_5%

PC@

1

CU117
2.2U_0402_6.3V6M

2
4

CU116
0.1U_0402_16V7K

1

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

G1

G2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

<4>
DIMM_DRAMRST#

+5VS

2

2

2

DIMM_DRAMRST#

3

<16,17,4>

DDR_B_D30
DDR_B_D31

VCC

A
Y

4

GND

+1.35V
RU129
100K_0402_5%
QU4
LBSS138LT1G_SOT-23-3
D
2
G
S
M_A_B_DIMM_ODT
1

NC

1

RU128
100K_0402_5%
@

5
1

2

DDR_PG_CTRL

74AUP1G07GW_TSSOP5

DDR_B_D45
DDR_B_D44

DDR_VTT_PG_CTRL

2

SB_ODT0

RU130 1
66.5_0402_1%

2

SB_ODT1

1

<46>

DDR_B_D61
DDR_B_D60
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D63
DDR_B_D62

DDRB_CKE1_DIMMB

DDRB_CKE1_DIMMB

<5>

DDR_B_D[0..63]

<5>

DDR_B_MA[0..15]

<5>

DDR_B_DQS#[0..7]

<5>

DDR_B_DQS[0..7]

<5>

DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7

2

DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
SB_CLK_DDR1
SB_CLK_DDR#1

SB_CLK_DDR1 <5>
SB_CLK_DDR#1 <5>

DDR_B_BS1
DDR_B_RAS#

DDR_B_BS1 <5>
DDR_B_RAS#
<5>

DDRB_CS0_DIMMB#
SB_ODT0

DDRB_CS0_DIMMB#

+1.35V
<5>

RU134
1.8K_0402_1%

+VREF_CA

SB_ODT1
+VREF_CA
DDR_B_D5
DDR_B_D0

RU135
1
2
2_0402_1%

PC@
DDR_B_D2
DDR_B_D6

1

2

DDR_B_D16
DDR_B_D17

1

2

@
RU136
1.8K_0402_1%

SM_DIMM_VREFCA

1

2

<16,5>

CU107
0.022U_0402_25V7K

@

RU137
24.9_0402_1%

DDR_B_DQS#2
DDR_B_DQS2

3

DDR_B_D19
DDR_B_D18
DDR_B_D37
DDR_B_D32

DDR_B_D34
DDR_B_D38
DDR_B_D51
DDR_B_D55
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D50
D_CK_SDATA
D_CK_SCLK
+0.675VS

D_CK_SDATA <29,34,7>
D_CK_SCLK <29,34,7>

206

CONN@

4

Channel B



Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

DIMM_1 STD H:4mm

2012/07/10

2013/07/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

B

C

D

DDRIII DIMMA

Size
Document Number
Custom
Date:

A

RU126 1
66.5_0402_1%

DDR_B_D47
DDR_B_D43

CU111
0.1U_0402_16V7K

2

2

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

+5VALW
1

UU15
1

DDR_B_D25
DDR_B_D24

CU110
2.2U_0402_6.3V6M

2

1

CU108
10U_0603_6.3V6M

1

CU106
10U_0603_6.3V6M

2

CU105
10U_0603_6.3V6M

1

DDR_B_D4
DDR_B_D1

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDR_B_D13
DDR_B_D15

@

3

DDR_B_D26
DDR_B_D27

DDR_B_DQS#1
DDR_B_DQS1

1

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D12
DDR_B_D9

2

2

DDR_B_D28
DDR_B_D29

2

RU131
24.9_0402_1%
@

DDR_B_D10
DDR_B_D11

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

1

2

2

1
1

1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2

RU127
1.8K_0402_1%

2

1

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

1

PC@

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

2

1
2
1

1

CU96
0.1U_0402_16V7K

@
CU94
0.022U_0402_25V7K

DDR_B_D8
DDR_B_D14

CU93
0.1U_0402_16V7K

SB_DIMM_VREFDQ

+1.35V

JDIMM1
+V_DDR_REFA
RU124
1.8K_0402_1%
CU95
2.2U_0402_6.3V6M

<5>

RU125
2_0402_1%
1
2

+1.35V

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

E

15

of

Rev
1.0
57

5

4

3

+VREF0 +VREF1

+VREF0 +VREF1

+VREF0

D

<17,5>
<17,5>
<17,5>

BA0
BA1
BA2

J8
K8
K10

1 0_0402_5%
DDRA_ODT0_R
DDRA_CS0_DIMMA#
DDRA_CS0_DIMMA#
DDR_A_RAS#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_CAS#
DDR_A_WE#
DDR_A_WE#

ODT
CS
RAS
CAS
WE

F4
C8

<15,17,4>

1

2 RU144
240_0402_1%

RESET

L9

ZQ

J2
L2
J10
L10

NC
NC
NC
NC

M8

DDR_A_MA15

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

T3

DIMM_DRAMRST#

DIMM_DRAMRST#

DML
DMU

G4
B8

C

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

E8
D4

DDR_A_DQS#0
DDR_A_DQS#1

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE

K2
L3
J4
K4
L4

DDR_A_DQS0
DDR_A_DQS1

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC

B3
D10
G8
K3
K9
N2
N10
R2
R10

M3
N9
M4

SA_CLK_DDR0
SA_CLK_DDR#0
DDRA_CKE0_DIMMA

J8
K8
K10

DDRA_ODT0_R
DDRA_CS0_DIMMA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

K2
L3
J4
K4
L4

DDR_A_DQS2
DDR_A_DQS3

F4
C8

+1.35V

A2
A9
C2
C10
D3
E10
F2
H3
H10

E8
D4

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

DDR_A_DQS#2
DDR_A_DQS#3

DIMM_DRAMRST#
1

G4
B8

T3

2 RU141 L9
240_0402_1%
J2
L2
J10
L10

B2
B10
D2
D9
E3
E9
F10
G2
G10

DDR_A_MA15

M8

96-BALL
SDRAM DDR3L
H5TC4G63MFR-PBA_FBGA96
<17,5>

DDR_A_MA[0..15]

<17,5>

DDR_A_DQS#[0..7]

<17,5>

DDR_A_DQS[0..7]

<17,5>

DDR_A_D[0..63]

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE
ODT
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ
NC
NC
NC
NC

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC

DDR_A_D22
DDR_A_D20
DDR_A_D18
DDR_A_D21
DDR_A_D19
DDR_A_D16
DDR_A_D23
DDR_A_D17

D8
C4
C9
C3
A8
A3
B9
A4

DDR_A_D24
DDR_A_D30
DDR_A_D29
DDR_A_D31
DDR_A_D25
DDR_A_D26
DDR_A_D28
DDR_A_D27

B3
D10
G8
K3
K9
N2
N10
R2
R10

M9
H2

+1.35V

A2
A9
C2
C10
D3
E10
F2
H3
H10
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

M3
N9
M4

SA_CLK_DDR0
SA_CLK_DDR#0
DDRA_CKE0_DIMMA

J8
K8
K10

DDRA_ODT0_R
DDRA_CS0_DIMMA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

K2
L3
J4
K4
L4

DDR_A_DQS4
DDR_A_DQS5

F4
C8
E8
D4
G4
B8

DDR_A_DQS#4
DDR_A_DQS#5

T3

DIMM_DRAMRST#
1

B2
B10
D2
D9
E3
E9
F10
G2
G10

2 RU142 L9
240_0402_1%
J2
L2
J10
L10
M8

DDR_A_MA15

UU19

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE
ODT
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ
NC
NC
NC
NC

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC

E4
F8
F3
F9
H4
H9
G3
H8

DDR_A_D34
DDR_A_D33
DDR_A_D38
DDR_A_D32
DDR_A_D39
DDR_A_D37
DDR_A_D35
DDR_A_D36

D8
C4
C9
C3
A8
A3
B9
A4

DDR_A_D44
DDR_A_D46
DDR_A_D40
DDR_A_D43
DDR_A_D41
DDR_A_D47
DDR_A_D45
DDR_A_D42

B3
D10
G8
K3
K9
N2
N10
R2
R10

M9
H2
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

M3
N9
M4

SA_CLK_DDR0
SA_CLK_DDR#0
DDRA_CKE0_DIMMA

J8
K8
K10

DDRA_ODT0_R
DDRA_CS0_DIMMA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

K2
L3
J4
K4
L4

DDR_A_DQS6
DDR_A_DQS7

F4
C8

CU125

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

E4
F8
F3
F9
H4
H9
G3
H8

CU124

DDR_A_D8
DDR_A_D14
DDR_A_D12
DDR_A_D11
DDR_A_D13
DDR_A_D15
DDR_A_D9
DDR_A_D10

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

CU123

D8
C4
C9
C3
A8
A3
B9
A4

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

VREFCA
VREFDQ

CU122
0.047U_0402_25V7K
2
1

DDR_A_D7
DDR_A_D0
DDR_A_D3
DDR_A_D1
DDR_A_D6
DDR_A_D5
DDR_A_D2
DDR_A_D4

0.047U_0402_25V7K
2
1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

M9
H2

E4
F8
F3
F9
H4
H9
G3
H8

CU119

M3
N9
M4

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

CU121
0.047U_0402_25V7K
2
1

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

@

DDRA_ODT0_R

DDRA_ODT0_R

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8

SA_CLK_DDR0
SA_CLK_DDR#0
DDRA_CKE0_DIMMA

SA_CLK_DDR0
SA_CLK_DDR#0
DDRA_CKE0_DIMMA
RU1402

DDRA_ODT0
<5>
<17,5>
<17,5>
<17,5>

<16,17>

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

VREFCA
VREFDQ

0.047U_0402_25V7K
2
1

CU118

CU120

0.047U_0402_25V7K
2
1

0.047U_0402_25V7K
2
1

M9
H2

UU18

0.047U_0402_25V7K
2
1

UU17

<5>

+VREF1

+VREF1

UU16

<5>
<5>
<5>

1

0.047U_0402_25V7K
2
1

+VREF0

2

+1.35V

A2
A9
C2
C10
D3
E10
F2
H3
H10
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

E8
D4
G4
B8

DDR_A_DQS#6
DDR_A_DQS#7

DIMM_DRAMRST#
1

B2
B10
D2
D9
E3
E9
F10
G2
G10

T3

2 RU143 L9
240_0402_1%
J2
L2
J10
L10
M8

DDR_A_MA15

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE
ODT
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ
NC
NC
NC
NC

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC

E4
F8
F3
F9
H4
H9
G3
H8

DDR_A_D55
DDR_A_D53
DDR_A_D49
DDR_A_D51
DDR_A_D54
DDR_A_D52
DDR_A_D48
DDR_A_D50

D8
C4
C9
C3
A8
A3
B9
A4

DDR_A_D59
DDR_A_D61
DDR_A_D62
DDR_A_D57
DDR_A_D58
DDR_A_D56
DDR_A_D63
DDR_A_D60

B3
D10
G8
K3
K9
N2
N10
R2
R10

D

+1.35V

A2
A9
C2
C10
D3
E10
F2
H3
H10
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
B2
B10
D2
D9
E3
E9
F10
G2
G10

96-BALL
SDRAM DDR3L
H5TC4G63MFR-PBA_FBGA96

96-BALL
SDRAM DDR3L
H5TC4G63MFR-PBA_FBGA96

96-BALL
SDRAM DDR3L
H5TC4G63MFR-PBA_FBGA96

@

@

@

C

@

+0.675VS

R Value =
34.8 Ohm
+1.35V

SA_CLK_DDR0

RU150
1.8K_0402_1%

2

1

2

2

2

RU149
24.9_0402_1%

1

+1.35V
+VREF_CA

1

+VREF1

@

From CPU
<15,5>

RU118
2 0_0402_5%
@

1

RU152
1.8K_0402_1%

DDR_A_MA10
DDR_A_BS0
DDR_A_MA0
DDR_A_MA3

4
3
2
1

DDR_A_BS1
DDR_A_MA2
DDR_A_MA13
DDR_A_MA5

4
3
2
1

DDR_A_MA14
DDR_A_MA11
DDR_A_MA9
DDR_A_MA1

4
3
2
1

DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA4

4
3
2
1

2

2

2

2

SA_CLK_DDR#0
1

4
3
2
1

1

1

DDRA_CKE0_DIMMA
DDR_A_MA12
DDR_A_MA15
DDR_A_BS2

1

+0.675VS
RU148
26.1_0402_1%

RU147
26.1_0402_1%
2

1

1

B

.1U_0402_16V7K
CU131

5.11_0402_1%
2

2.2U_0603_10V6K
CU132

1
CU130
0.022U_0402_25V7K



+VREF0

1

B

2

1
2

+VREF0

2

1

CU129
1U_0402_6.3V6K

1

SA_DIMM_VREFDQ

5
6
7
8 36_0804_8P4R_5%
RPU23
5
6
7
8 36_0804_8P4R_5%
RPU24
5
6
7
8 36_0804_8P4R_5%
RPU25
5
6
7
8 36_0804_8P4R_5%
RPU26
5
6
7
8 36_0804_8P4R_5%
RPU27
5
6
7
8 36_0804_8P4R_5%
RPU28

CU128
1U_0402_6.3V6K

<5>

RU146

4
3
2
1

CU127
1U_0402_6.3V6K

RU145
1.8K_0402_1%

Frorm CPU

DDR_A_WE#
DDRA_CS0_DIMMA#
DDR_A_CAS#
DDR_A_RAS#

CU126
1U_0402_6.3V6K

DDR3L VREF

+VREF0

+1.35V

RU151
1

2

DDRA_ODT0_R

DDRA_ODT0_R

<16,17>

30_0402_1%

@ RU153
2



2.7_0402_1%
1

1

2

1

@

2

RU155
24.9_0402_1%

RU154
1.8K_0402_1%

2

External DDR Thermal Sensor
+3VS

1

CU181
0.1U_0402_16V4Z
1
2

@
2

2

@

@

2.2U_0603_10V6K
CU135

CU133
0.022U_0402_25V7K

1

.1U_0402_16V7K
CU134

@

2

1

SM_DIMM_VREFCA

+0.675VS
1
2
+1.35V
3
4

SF000002Z00

CU89
330U_2.5V_M

2

1

2

1

2

VDD

SCLK

D+

SDATA

D-

ALERT#

THERM#

GND

8
7
6
5

1
RU165

Issued Date

<19,36,7>

2
+3VS
10K_0402_5%

3

A

Compal Secret Data
2010/04/26

Deciphered Date

2012/03/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

<19,36,7>

EC_SMB_DA2

SA00003PU00
S IC W83L771AWG-2 TSSOP 8P SENSOR

V4DA2
M/B Classification
LA-9581P Schem atic
Security

5

EC_SMB_CK2

W83L771AWG-2 TSSOP8P
SA00003PU00

10U_0603_6.3V6M

+

CU148

1

1U_0402_6.3V6K

2

CU147

2

1

CU145
.1U_0402_16V7K

2

1

CU144
.1U_0402_16V7K

2

1

CU143
.1U_0402_16V7K

2

1

CU142
.1U_0402_16V7K

2

1

CU141
10U_0603_6.3V6M

2

1

CU140
10U_0603_6.3V6M

2

1

CU139
10U_0603_6.3V6M

2

1

CU138
10U_0603_6.3V6M

2

1

CU137
10U_0603_6.3V6M

A

CU136
10U_0603_6.3V6M

1

UU24

2

Title

DDRIII ON BOARD CHIPS
Size
Docum ent Num ber
Cus tom
Date:

Rev
1.0

Tues day, July 30, 2013
1

Sheet

16

of

57

5

4

3

+VREF0 +VREF1

+VREF0 +VREF1

+VREF0

D

<16,5>
<16,5>
<16,5>

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

J8
K8
K10

SA_CLK_DDR1
SA_CLK_DDR#1
DDRA_CKE1_DIMMA

SA_CLK_DDR1
SA_CLK_DDR#1
DDRA_CKE1_DIMMA

<16> DDRA_ODT0_R
<5> DDRA_CS1_DIMMA#
<16,5> DDR_A_RAS#
<16,5> DDR_A_CAS#
<16,5> DDR_A_WE#

DDRA_ODT0_R
DDRA_CS1_DIMMA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

K2
L3
J4
K4
L4

DDR_A_DQS0
DDR_A_DQS1

F4
C8
E8
D4
G4
B8

DDR_A_DQS#0
DDR_A_DQS#1

T3

DIMM_DRAMRST#

DIMM_DRAMRST#

1

2 RU160
240_0402_1%

L9

C

J2
L2
J10
L10
M8

DDR_A_MA15

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE
ODT
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ
NC
NC
NC
NC

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC

B3
D10
G8
K3
K9
N2
N10
R2
R10

DDR_A_MA[0..15]

<16,5>

DDR_A_DQS#[0..7]

<16,5>

DDR_A_DQS[0..7]

<16,5>

DDR_A_D[0..63]

SA_CLK_DDR1
SA_CLK_DDR#1
DDRA_CKE1_DIMMA

J8
K8
K10

DDRA_ODT0_R
DDRA_CS1_DIMMA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

A2
A9
C2
C10
D3
E10
F2
H3
H10

DDR_A_DQS2
DDR_A_DQS3

K2
L3
J4
K4
L4
F4
C8
E8
D4

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

DDR_A_DQS#2
DDR_A_DQS#3

DIMM_DRAMRST#
1

G4
B8

T3

2 RU157 L9
240_0402_1%
J2
L2
J10
L10

B2
B10
D2
D9
E3
E9
F10
G2
G10

DDR_A_MA15

M8

BA0
BA1
BA2

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU

RESET
ZQ
NC
NC
NC
NC
NC

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DDR_A_D20
DDR_A_D22
DDR_A_D21
DDR_A_D18
DDR_A_D16
DDR_A_D19
DDR_A_D17
DDR_A_D23

D8
C4
C9
C3
A8
A3
B9
A4

DDR_A_D30
DDR_A_D24
DDR_A_D31
DDR_A_D29
DDR_A_D26
DDR_A_D25
DDR_A_D27
DDR_A_D28

B3
D10
G8
K3
K9
N2
N10
R2
R10

+1.35V

A2
A9
C2
C10
D3
E10
F2
H3
H10

M9
H2
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

M3
N9
M4

SA_CLK_DDR1
SA_CLK_DDR#1
DDRA_CKE1_DIMMA

J8
K8
K10

DDRA_ODT0_R
DDRA_CS1_DIMMA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

F4
C8

DDR_A_DQS4
DDR_A_DQS5

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

K2
L3
J4
K4
L4

E8
D4
G4
B8

DDR_A_DQS#4
DDR_A_DQS#5

DIMM_DRAMRST#
1

B2
B10
D2
D9
E3
E9
F10
G2
G10

T3

2 RU158 L9
240_0402_1%
J2
L2
J10
L10

DDR_A_MA15

M8

VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

BA0
BA1
BA2

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU

RESET
ZQ
NC
NC
NC
NC
NC

UU23
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

E4
F8
F3
F9
H4
H9
G3
H8

DDR_A_D33
DDR_A_D34
DDR_A_D32
DDR_A_D38
DDR_A_D37
DDR_A_D39
DDR_A_D36
DDR_A_D35

D8
C4
C9
C3
A8
A3
B9
A4

DDR_A_D46
DDR_A_D44
DDR_A_D43
DDR_A_D40
DDR_A_D47
DDR_A_D41
DDR_A_D42
DDR_A_D45

B3
D10
G8
K3
K9
N2
N10
R2
R10

M9
H2

+1.35V

A2
A9
C2
C10
D3
E10
F2
H3
H10

CU155

M3
N9
M4

+1.35V

96-BALL
SDRAM DDR3L
H5TC4G63MFR-PBA_FBGA96
<16,5>

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

E4
F8
F3
F9
H4
H9
G3
H8

CU154

DDR_A_D14
DDR_A_D8
DDR_A_D11
DDR_A_D12
DDR_A_D15
DDR_A_D13
DDR_A_D10
DDR_A_D9

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

CU153

D8
C4
C9
C3
A8
A3
B9
A4

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

VREFCA
VREFDQ

CU152
0.047U_0402_25V7K
2
1

M3
N9
M4

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

DDR_A_D0
DDR_A_D7
DDR_A_D1
DDR_A_D3
DDR_A_D5
DDR_A_D6
DDR_A_D4
DDR_A_D2

0.047U_0402_25V7K
2
1

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

M9
H2

E4
F8
F3
F9
H4
H9
G3
H8

CU151

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

CU150
0.047U_0402_25V7K
2
1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

VREFCA
VREFDQ

0.047U_0402_25V7K
2
1

CU156

CU149

0.047U_0402_25V7K
2
1

0.047U_0402_25V7K
2
1

M9
H2

UU22

0.047U_0402_25V7K
2
1

UU21

<15,16,4>

+VREF1

+VREF1

UU20

<5>
<5>
<5>

1

0.047U_0402_25V7K
2
1

+VREF0

2

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

M3
N9
M4

SA_CLK_DDR1
SA_CLK_DDR#1
DDRA_CKE1_DIMMA

J8
K8
K10

DDRA_ODT0_R
DDRA_CS1_DIMMA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

1

B2
B10
D2
D9
E3
E9
F10
G2
G10

K2
L3
J4
K4
L4

ODT
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

T3

RESET

2 RU159 L9
240_0402_1%

ZQ

J2
L2
J10
L10

NC
NC
NC
NC

M8

DDR_A_MA15

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE

G4
B8

DIMM_DRAMRST#

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

E8
D4
DDR_A_DQS#6
DDR_A_DQS#7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

F4
C8

DDR_A_DQS6
DDR_A_DQS7

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

VREFCA
VREFDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC

E4
F8
F3
F9
H4
H9
G3
H8

DDR_A_D53
DDR_A_D55
DDR_A_D51
DDR_A_D49
DDR_A_D52
DDR_A_D54
DDR_A_D50
DDR_A_D48

D8
C4
C9
C3
A8
A3
B9
A4

DDR_A_D61
DDR_A_D59
DDR_A_D57
DDR_A_D62
DDR_A_D56
DDR_A_D58
DDR_A_D60
DDR_A_D63

B3
D10
G8
K3
K9
N2
N10
R2
R10

D

+1.35V

A2
A9
C2
C10
D3
E10
F2
H3
H10
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
B2
B10
D2
D9
E3
E9
F10
G2
G10

96-BALL
SDRAM DDR3L
H5TC4G63MFR-PBA_FBGA96

96-BALL
SDRAM DDR3L
H5TC4G63MFR-PBA_FBGA96

96-BALL
SDRAM DDR3L
H5TC4G63MFR-PBA_FBGA96

@

@

@

C

@

R Value =
34.8 Ohm
DDRA_CKE1_DIMMA RU166
DDRA_CS1_DIMMA# RU167

1
1

+0.675VS

2 36_0402_1%
2 36_0402_1%

UU16

UU20

X76SHYNIX0@
SA00005AV50

X76SHYNIX0@
SA00005AV50

H5TC4G63AFR-PBA ABO!
UU17

H5TC4G63AFR-PBA ABO!
UU21

X76SHYNIX0@
SA00005AV50

X76SHYNIX0@
SA00005AV50

H5TC4G63AFR-PBA ABO!
UU18

H5TC4G63AFR-PBA ABO!
UU22

X76SHYNIX0@
SA00005AV50

X76SHYNIX0@
SA00005AV50

H5TC4G63AFR-PBA ABO!
UU19

H5TC4G63AFR-PBA ABO!
UU23

X76SHYNIX0@
SA00005AV50

X76SHYNIX0@
SA00005AV50

H5TC4G63AFR-PBA ABO!

H5TC4G63AFR-PBA ABO!

SA_CLK_DDR1

B

B

1

1

SA_CLK_DDR#1
+0.675VS
RU163
26.1_0402_1%
2

RU164
26.1_0402_1%
2

UU16

UU20

X76SELP0@

X76SELP0@
SA00005HT80

SA00005HT80

EDJ4216EFBG-GNL-F FBGA 96P ABO !
UU17

EDJ4216EFBG-GNL-F FBGA 96P ABO !
UU21

X76SELP0@

X76SELP0@
SA00005HT80

SA00005HT80

EDJ4216EFBG-GNL-F FBGA 96P ABO !
UU18

EDJ4216EFBG-GNL-F FBGA 96P ABO !
UU22

X76SELP0@

X76SELP0@
SA00005HT80

+0.675VS

SA00005HT80

EDJ4216EFBG-GNL-F FBGA 96P ABO !
UU19

EDJ4216EFBG-GNL-F FBGA 96P ABO !
UU23

X76SELP0@

X76SELP0@
SA00005HT80

+1.35V

SA00005HT80

EDJ4216EFBG-GNL-F FBGA 96P ABO !

1

2

1

2

1

2

1

2

1

2

10U_0603_6.3V6M

2

CU179

1

1U_0402_6.3V6K

2

CU178

1

CU176
.1U_0402_16V7K

2

CU175
.1U_0402_16V7K

1

CU174
.1U_0402_16V7K

2

CU173
.1U_0402_16V7K

1

CU172
10U_0603_6.3V6M

2

CU171
10U_0603_6.3V6M

1

CU170
10U_0603_6.3V6M

2

CU169
10U_0603_6.3V6M

1

CU168
10U_0603_6.3V6M

2

CU167
10U_0603_6.3V6M

1
A

A

V4DA2
M/B Classification
LA-9581P Schem atic
Security

Issued Date

Compal Secret Data
2010/04/26

Deciphered Date

2012/03/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

EDJ4216EFBG-GNL-F FBGA 96P ABO !

3

2

Title

DDRIII ON BOARD CHIPS
Size
Docum ent Num ber
Cus tom
Date:

Rev
1.0

Tues day, July 30, 2013
1

Sheet

17

of

57

A

B

C

D

E

GFX PCIE LANE REVERSAL
UV6A
<10>

PEG_HTX_C_GRX_P[0..3]

<10>

PEG_HTX_C_GRX_N[0..3]

PEG_HTX_C_GRX_P[0..3]
PEG_GTX_HRX_P[0..3]

PART 1 0F 9

PEG_HTX_C_GRX_N[0..3]
PEG_GTX_HRX_N[0..3]

PEG_GTX_HRX_P[0..3]

<10>

PEG_GTX_HRX_N[0..3]

<10>
UV6G

AA38
Y37

PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_N1

Y35
W36

PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_N2

W38
V37

PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_N3

V35
U36
U38
T37
T35
R36
R38
P37
P35
N36

2

N38
M37

L38
K37
K35
J36
J38
H37
H35
G36
G38
F37

PCIE_TX0P
PCIE_TX0N

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

NC#N38
NC#M37
NC#M35
NC#L36
NC#L38
NC#K37

NC#N33
NC#N32
PCI EXPRESS INTERFACE

M35
L36

PCIE_RX0P
PCIE_RX0N

NC#N30
NC#N29
NC#L33
NC#L32

NC#K35
NC#J36

NC#L30
NC#L29

NC#J38
NC#H37

NC#K33
NC#K32

NC#H35
NC#G36

NC#J33
NC#J32

NC#G38
NC#F37

NC#K30
NC#K29

NC#F35
NC#E37

NC#H33
NC#H32

Y33
Y32

PEG_GTX_HRX_P0
PEG_GTX_HRX_N0

W33
W32

PEG_GTX_HRX_P1
PEG_GTX_HRX_N1

U33
U32

PEG_GTX_HRX_P2
PEG_GTX_HRX_N2

U30
U29

PEG_GTX_HRX_P3
PEG_GTX_HRX_N3

PART 7 0F 9

1

RSVD/VARY_BL
RSVD/DIGON

AK27
AJ27

LVDS CONTROL

TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N
TX4P_DPB1P
TX4M_DPB1N

T33
T32

TX5P_DPB0P
TX5M_DPB0N

T30
T29

LVTMDP

1

PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0

P33
P32

NC#AF35
NC#AG36

TXCAP_DPA3P
TXCAM_DPA3N

P30
P29

TX0P_DPA2P
TX0M_DPA2N

N33
N32

TX1P_DPA1P
TX1M_DPA1N

N30
N29

TX2P_DPA0P
TX2M_DPA0N
NC#AN36
NC#AP37

L33
L32
L30
L29

AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37
AF35
AG36

AP34
AR34
AW37
AU35

2

AR37
AU39
AP35
AR35
AN36
AP37

2160842006A0MARSXT_FCBGA962
@

K33
K32
J33
J32
K30
K29

3

3

F35
E37

<7>
<7>

AB35
AA36

CLK_PEG_VGA
CLK_PEG_VGA#

H33
H32

CLOCK

PCIE_REFCLKP
PCIE_REFCLKN
CALIBRATION

PCIE_CALR_TX
2 VGA@
RV151

1

3.3-V tolerant
<8>

PLTRST_VGA#

PLTRST_VGA#

AH16

1K_0402_5%

AA30

TEST_PG

PCIE_CALR_RX

Y30
Y29

VGA_PCIE_CALRP
VGA_PCIE_CALRN

RV150 1 VGA@

2 1.69K_0402_1%

+0.95VSDGPU

RV152 1

2 1K_0402_1%

+0.95VSDGPU

VGA@

PERSTB
2160842006A0MARSXT_FCBGA962
@

4

4

UV6

UV6

SUN_XT_M2_962P
SUN@

MARS_XT_M2_962P
MARS@

SA00006G600

SA000061J20

Security Classification

A

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

C

D

Title

MARS-Pro_PCIE

Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Thursday, August 01, 2013

Sheet

E

18

of

Rev
1.0
57

A

B

C

D

UV6B

External VGA Thermal Sensor

2

2

2

1

1
5

1

RV156
4.7K_0402_5%
VGA@

4

VGA_SMB_DA2

QV17A VGA@
DMN66D0LDW-7_SOT363-6

6

EC_SMB_CK2

EC_SMB_CK2

QV17B VGA@
DMN66D0LDW-7_SOT363-6
3
EC_SMB_DA2

<16,36,7>

AJ23
AH23

Slave ID: 0x41

AK26
AJ26

2

2

2

1

1

ACIN

<52>

AH20
AH18
AN16

GPU_DPRSLPVR

GPU_DPRSLPVR

DV1

VGA@
<36,44,8>

RV162
100K_0402_5%
VGA@

GPU_ACIN_D

GPU_VID_1
GPU_VID_2
THM_ALERT#
RV166 10K_0402_5% 1

2

@

(GPIO1, 2, 7, 11, 12, 13, 18, 21

DPC

NC#AT17
NC#AR16

GPIO_19_CTF
GPU_VID_3

is NC at SUN)

AG32
AG33

GPU_VID_4
GPU_VID_5

VREFG:Use a voltage divider to set
VREFG = 1.80 V / 3 (or 0.60-V nominal).

+1.8VSDGPU

RV167 1 MARS@ 2 499_0402_1%

AK24

20mil

RV168 1 MARS@ 2 249_0402_1%

SPLL_PVSS

CLKTESTA
CLKTESTB

NC_XTAL_PVDD
NC_XTAL_PVSS

AK10
AL10

2
2160842006A0MARSXT_FCBGA962
@

AU22
AV21

NC#AU22
NC#AV21

@

AT23
AR22

NC#AT23
NC#AR22
I2C

R
AVSSN

GENERAL PURPOSE I/O

GPIO_0
GPIO_1
GPIO_2
GPIO_5_AC_BATT
GPIO_6_TACH
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21
GPIO_22_ROMCSB
CLKREQB

G
AVSSN

AD39
AD37

TV30

AE36
AD35

TV31

AF37
AE38

B
AVSSN
DAC1

AC36
AC38

HSYNC
VSYNC

RV163 1 @
RV164 1
@

RV165 1 MARS@ 2 499_0402_1%
RSET
LV4
(SUN NC)
AD34
VGA@
1
+AVDD
AE34
(SUN NC)

AVDD
AVSSQ

AC33
AC34

VDD1DI
VSS1DI

+VDD1DI

(SUN NC)

V13
U13
AF33
AF32
AA29
AG21
AC32

NC#V13
NC#U13
NC#AF33
NC#AF32
NC#AA29
NC#AG21
NC#AC32

GPIO_29
GPIO_30

1

2

1

1

2

2

@

@

LV5

117mA
VGA@
1
@

AM34

PS_0

AD31

PS_1

AG31

PS_2

AD33

PS_3

2

@

2 0_0603_5%

MLPS

PS_1

1

2

1

2

100
101
101
101
101
100
101

@

1

2 0_0603_5%

+1.8VSDGPU

@

RV180

1

1
2
3
4

XTALIN

10K_0804_8P4R_5%
TV33
@

AM23
AN23
AK23
AL24
AM24

@

2

1

+3VSDGPU

AN20
AM20

AUX2P
AUX2N

1

@
RV181

AF29
AG29

2
2

MLPS_EN#

AK32

10K_0402_5%

1

@

2

13mA
0_0603_5%

10U_0603_6.3V6M
2
1U_0402_6.3V6K 2
0.1U_0402_16V4Z 2

10mil

1 VGAPC@ CV242
1 VGAPC@ CV243
1 VGA@
CV244

B

+TSVDD

AJ32
AJ33

NC#AL29
NC#AM29

GPIO_28_FDO
TS_A
TSVDD
TSVSS

0.1U_0402_16V4Z
CV111

Bits[5:1] PU(1%)
xx000

NC

PD(1%) Cap
4.75k

xx001

8.45k

2.00k

xx010

4.53k

2.00k

xx011

6.98k

4.99k

xx100

4.53k

4.99k

xx101

3.24k

5.62k

xx110

3.40k

10.0k

xx111

4.75k

NC

2

00xxx

680nF

01xxx

82nF

10xxx

10nF

11xxx

NC

-

:
:
:
:
:

same as GPIO_11
Since the frame buffer size is 512 MB
same as GPIO_12
the aperture size is set to 256 MB.
same as GPIO_13
Reserved for internal use only. Must be 1
AUD_PORT_CONN_PINSTRAP[0]

512Kbit
1Mbit
2Mbit
4Mbit
8Mbit
512Kbit
1Mbit

M25P05A
M25P10A
M25P20
M25P40
M25P80
Pm25LV512
Pm25LV010

(ST)
(ST)
(ST)
(ST)
(ST)
(Chingis)
(Chingis)

=
=
=
=
=

0
0
0
1
1

:
:
:
:
:

PCIeR GEN3 is not supported.
Reserved for internal use only
Reserved for internal use only
TX_PWRS_ENB: Full Tx output swing.
TX_DEEMPH_EN: Tx deemphasis enabled.

PS_2[1]
PS_2[2]
PS_2[3]
PS_2[4]
PS_2[5]

=
=
=
=
=

0
0
0
0
1

:
:
:
:
:

Reserved.
Reserved.
BIOS_ROM_EN :Disable the external BIOS ROM device.
VGA_DIS : 0=VGA controller capacity enabled.
Reserved.

+VDDC_CT

1

1

PS_1[1]
PS_1[2]
PS_1[3]
PS_1[4]
PS_1[5]

@
RV174
10K_0402_5%

+VDDC_CT

VGA@
RV175
8.45K_0402_1%

PS_3[1]
PS_3[2]
PS_3[3]
PS_3[4]
PS_3[5]
=======

=
=
=
=
=

x
x
x
1
1

:
:
VRAM ID
:
: AUD_PORT_CONN_PINSTRAP[1]
: AUD_PORT_CONN_PINSTRAP[2]

VRAM ID for Mars

=======

000
HYNIX0 : SA00003YO90
S IC D3 128M16 H5TQ2G63DFR-11C FBGA ABO!

AL30
AM30

1

AL29
AM29

2

AN21
AM21

NC#AN21
NC#AM21

10K_0402_5%

AL31
+1.8VSDGPU
LV6

DPLUS
DMINUS

PS_0
PS_1
PS_2
PS_3
@

NC#AL30
NC#AM30

GPU_THERM_D+
GPU_THERM_D-

RV182

Crystals must have a max ESR of 80 ohm

AM19
AL19

DDC2CLK
DDC2DATA

THERMAL

CV241
10P_0402_50V8J
VGA@

1 VGA@

A

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO

1

27MHZ_10PF_X3G027000BA1H-U

1

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS

VGA@

1

2

@

1

2

@

1

2

CV240
0.1U_0402_16V7K

IN

4

8
7
6
5

+VDDC_CT

X76VHYNIX1@
@
RV172
RV173
8.45K_0402_1% 10K_0402_5%

AM27
AL27

AUX1P
AUX1N

CV239
0.1U_0402_16V7K

GND

TESTEN

CV236
0.01U_0402_16V7K

CV237
10P_0402_50V8J
VGA@

2

GND

AD28

CV238
0.1U_0402_16V7K

2
4

OUT

1
TESTEN
1K_0402_5%

AM26
AN26

DDC1CLK
DDC1DATA

RPV1

XV1
VGA@
Crystal

3

DDC/AUX

2

RV171

+VDDC_CT
DEBUG

1

2 VGA@

+3VSDGPU

PS_3

X76VHYNIX0@
RV180
RV177
RV178
4.75K_0402_1% 4.75K_0402_1% 4.75K_0402_1%
VGA@
VGA@

2

2

XTALOUT

1

S RES 1/16W 2K +-1% 0402

PX_EN

RV169
0_0402_5%
@

RV170
5.11K_0402_1%

2 @

PS_2

BACO

1

+3VSDGPU

DBG_VREFG

1

2

Pull high @ VGA side

VGA@
RV176
1M_0402_5%

AL21

2

(SUN NC)

Place VREFG divider and cap close to ASIC

SD034200180

1

AH13

+VGA_VREF

Mars MLPS configuration

3

2

2 0.1U_0402_16V4Z

@

PS0_[1]=1
PS0_[2]=0
PS0_[3]=0
PS0_[4]=1
PS0_[5]=1

X76VHYNIX1@
CV235 1
MARS@

2

2

+1.8VSDGPU

CEC_1
HPD1

1

10mil

70mA

10mil

AC31
AD30
AD32

NC_SVI2#AC31
NC_SVI2#AD30
NC_SVI2#AD32

GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

2

2 10K_0402_5%
2 10K_0402_5%

AB34

RSET

VGA@ 1 VGA@ 1

AUD[1:0]:
00 - No audio function

TV32
AUD_1
AUD_0

@

VGA@

LV3

1
+0.95VSDGPU
BLM15AG121SN1D_L0402_2P

TV22
TV24

1

1

2
1

2

AT21
AR20

PS_0
AC30

XO_IN2

@

CV234
1U_0402_6.3V6K

3

SPLL_VDDC

AU20
AT19

NC#AU20
NC#AT19

CV233
0.1U_0402_16V4Z

AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

AF30
AF31

2

100mA
1
@
0_0402_5% RV157

SPLL_PVSS

AT17
AR16

DPD

SCL
SDA

AN10

SPLL_PVSS

2

+SPLL_VDDC

AW35 XO_IN2 2

AU16
AV15

NC#AU16
NC#AV15

SMBCLK SMBus
SMBDATA

SPLL_PVDD

2
XO_IN 1
@
0_0402_5% RV153

VGAPC@

AT15
AR14

NC#AT15
NC#AR14

CV232
0.1U_0402_16V4Z

GPU_VID_1
GPU_VID_2
GPU_VID_3
GPU_VID_4
GPU_VID_5

GPU_VID_1
GPU_VID_2
GPU_VID_3
GPU_VID_4
GPU_VID_5

NC#AU14
NC#AV13

AN9

+SPLL_VDDC

CV231
1U_0402_6.3V6K

<52>
<52>
<52>
<52>
<52>

AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13

GPU_ACIN_D

RB751V-40-YS_SOD323-2

AU14
AV13

AW34

VGA@ 1 VGA@ 1

CV230
RV161
0.1U_0402_16V4Z 51.1_0402_1%

+3VSDGPU

AT33
AU32

NC#AT33
NC#AU32

1

2
XO_IN

+SPLL_PVDD AM10

CV229
RV160
0.1U_0402_16V4Z 51.1_0402_1%

VGA_SMB_CK2
VGA_SMB_DA2

MPLL_PVDD
MPLL_PVDD

AR32
AT31

NC#AR32
NC#AT31

NC#AT21
NC#AR20

RV158
0_0402_5%
1 VGA@ 2VGA_SMB_CK2_R
1 VGA@ 2VGA_SMB_DA2_R
RV159
0_0402_5%

H7
H8

+MPLL_PVDD

VGA@

1

+1.8VSDGPU
BLM15AG121SN1D_L0402_2P

CV228
10U_0603_6.3V6M

<16,36,7>

VGAPC@

AV31
AU30

NC#AV31
NC#AU30

LV2

2

CV224
1U_0402_6.3V6K

EC_SMB_DA2

75mA
+SPLL_PVDD

XTALOUT

AR30
AT29

NC#AR30
NC#AT29

DPB

XTALOUT

2

1

+1.8VSDGPU
BLM15AG121SN1D_L0402_2P

CV223
10U_0603_6.3V6M

RV155
4.7K_0402_5%
VGA@
VGA_SMB_CK2

TV3
TV13
TV14
TV15
TV4
TV5
TV16
TV17
TV6
TV18
TV7
TV8
TV9
TV10
TV11
TV19
TV20
TV21
TV23
TV25
TV26
TV27
TV28
TV29

AU34

AT27
AR26

NC#AT27
NC#AR26

2

CV222
1U_0402_6.3V6K

+3VSDGPU

NC#AR8
NC#AU8
DBG_CNTL0
NC#AW8
NC#AR3
NC#AR1
DBG_DATA0
DBG_DATA1
DBG_DATA2
DBG_DATA3
DBG_DATA4
DBG_DATA5
DBG_DATA6
DBG_DATA7
DBG_DATA8
DBG_DATA9
DBG_DATA10
DBG_DATA11
DBG_DATA12
DBG_DATA13
DBG_DATA14
DBG_DATA15
DBG_DATA16
DBG_DATA17
DBG_DATA18
DBG_DATA19
DBG_DATA20
DBG_DATA21
DBG_DATA22
DBG_DATA23

2

0.1U_0402_16V4Z
CV112

TV2

PLLS/XTAL

AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

NCT7718W_MSOP8
SA000067P00

XTALIN

AU26
AV25

NC#AU26
NC#AV25

+3VSDGPU

R03 modify BOM

AV33

0.1U_0402_16V4Z
CV113

+3VSDGPU

XTALIN

1

VGA@ 2
4.7K_0402_5%

VGAPC@

AT25
AR24

NC#AT25
NC#AR24

DPA

2

1
RV154

SWAPLOCKA
SWAPLOCKB

1

5

AJ21
AK21

VGA@ 1 VGA@ 1

VGA@

VGA@
RV179
2K_0402_1%

001
HYNIX1 : SA00006H430
S IC D3 128MX16 H5TC2G63FFR-11C FBGA 96P ABO !
4

2

THM_ALERT#

1

GND

VGA_SMB_DA2

6

2

T_CRIT#

7

2

ALERT#

1

1

SDA

D-

AU24
AV23

NC#AU24
NC#AV23

2

4

D+

2

PART 9 0F 9

MUTI GFX

GENLK_CLK
GENLK_VSYNC

1

GPU_THERM_D-

3

AD29
AC29

TV12
TV1

2

2

VGA_SMB_CK2

CV227
10U_0603_6.3V6M

GPU_THERM_D+
2200P_0402_50V7K
2 VGA@
CV225 1

8

CV226
1U_0402_6.3V6K

1

CV221
0.1U_0402_16V4Z

2

SCL

LV1

+MPLL_PVDD

VGA@

VDD

0.1U_0402_16V4Z
CV114

UV9

1
1 VGA@

130mA

0.1U_0402_16V4Z
CV115

+3VSDGPU

E

UV6I
PART 2 0F 9

AK30
AK29

NC#AK30
NC#AK29

AJ30
AJ31

DDCVGACLK
DDCVGADATA

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2160842006A0MARSXT_FCBGA962
@
C

D

Title

MARS-Pro_STRAP

Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

E

19

of

57

Rev
1.0

B

C

D

E

MAA[0..15]

UV6D

MAA[0..15]

UV6C
PART 4 0F 9

RV186
0_0402_5%
@

1

2

+1.5VSDGPU
2

RV188

1

2

40.2_0402_1%
MARS@

1 MARS@

2

2

CV247
1U_0402_6.3V6K

RV190
100_0402_1%
MARS@

15mil
MVREFSA

3

L18
L20
L27
N12
AG12

RV193 1 VGA@
120_0402_1%

2

MEM_CALRP0 M27

CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1

MVREFDA
MVREFSA

CKEA0
CKEA1

NC#L27
NC#N12
NC#AG12

WEA0B
WEA1B

MEM_CALRP0
NC#M12
NC#AH12

MAA0_8/MAA_13
MAA1_8/MAA_14
MAA0_9/MAA_15
MAA1_9/RSVD

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

J21
G19

ODTA0
ODTA1

H27
G27
J14
H14
K23
K19
K20
K17

CLKA0
CLKA0#
CLKA1
CLKA1#
RASA0#
RASA1#
CASA0#
CASA1#

K24
K27

CSA0#

M13
K16

CSA1#

K21
J20

CKEA0
CKEA1

K26
L15

WEA0#
WEA1#

H23
J19
M21
M20

MAA13
MAA14
MAA15

ODTA0
ODTA1

<23>
<23>

CLKA0 <23>
CLKA0# <23>
CLKA1 <23>
CLKA1# <23>
RASA0#
RASA1#

<23>
<23>

CASA0#
CASA1#

<23>
<23>

CSA0#

<23>

CSA1#

<23>

CKEA0
CKEA1

<23>
<23>

WEA0#
WEA1#

<23>
<23>

MVREFDB Y12
MVREFSB AA12

DDBIB0_0/QSB_0B
DDBIB0_1/QSB_1B
DDBIB0_2/QSB_2B
DDBIB0_3/QSB_3B
DDBIB1_0/QSB_4B
DDBIB1_1/QSB_5B
DDBIB1_2/QSB_6B
DDBIB1_3/QSB_7B
ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1

MVREFDB
MVREFSB

WEB0B
WEB1B

MAB0_8/MAB_13
MAB1_8/MAB_14
MAB0_9/MAB_15
MAB1_9/RSVD
DRAM_RST

H3
H1
T3
T5
AE4
AF5
AK6
AK5

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

T7
W7

ODTB0
ODTB1

CLKB1
CLKB1#

T10
Y10

RASB0#
RASB1#

W10
AA10

CASB0#
CASB1#

P10
L10

CSB0#

AD10
AC10

CSB1#

U10
AA11

CKEB0
CKEB1

N10
AB11

WEB0#
WEB1#

T8
W8
U12
V12

MAB13
MAB14
MAB15

1

MAB[0..15]

MAB[0..15]

<24>

DQMB#[0..7]

QSB[0..7]
<24>
<24>
<24>

<23>

1

DQMB#[0..7]

B_BA2
B_BA0
B_BA1

QSA#[0..7]

QSB[0..7]

QSB#[0..7]

<24>

<24>

QSB#[0..7]

<24>

+1.5VSDGPU

VGA@

CLKB0
CLKB0#

2160842006A0MARSXT_FCBGA962
@

QSA#[0..7]

<23>
<23>

RV185

AD8
AD7

2160842006A0MARSXT_FCBGA962
@

QSA[0..7]

40.2_0402_1%

L9
L8

AH11

QSA[0..7]

1

A34
E30
E26
C20
C16
C12
J11
F8

EDCB0_0/QSB_0
EDCB0_1/QSB_1
EDCB0_2/QSB_2
EDCB0_3/QSB_3
EDCB1_0/QSB_4
EDCB1_1/QSB_5
EDCB1_2/QSB_6
EDCB1_3/QSB_7

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

2

M12
AH12

ADBIA0/ODTA0
ADBIA1/ODTA1

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

15mil
MVREFDB

RV187 VGA@
100_0402_1%

ODTB0
ODTB1

<24>
<24>

1 VGA@

2

+1.5VSDGPU

2

RV189
0_0402_5%
@

CLKB0 <24>
CLKB0# <24>
CLKB1 <24>
CLKB1# <24>
RASB0#
RASB1#

<24>
<24>

CASB0#
CASB1#

<24>
<24>

CSB0#

<24>

CSB1#

<24>

CKEB0
CKEB1

<24>
<24>

WEB0#
WEB1#

<24>
<24>

RV191
VGA@
40.2_0402_1%

15mil
MVREFSB
1 VGA@

RV192
VGA@
100_0402_1%

2

CV248
1U_0402_6.3V6K

MVREFDA
MVREFSA

DDBIA0_0/QSA_0B
DDBIA0_1/QSA_1B
DDBIA0_2/QSA_2B
DDBIA0_3/QSA_3B
DDBIA1_0/QSA_4B
DDBIA1_1/QSA_5B
DDBIA1_2/QSA_6B
DDBIA1_3/QSA_7B

C34
D29
D25
E20
E16
E12
J10
D7

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

2

2

1

2

100_0402_1%
MARS@

EDCA0_0/QSA_0
EDCA0_1/QSA_1
EDCA0_2/QSA_2
EDCA0_3/QSA_3
EDCA1_0/QSA_4
EDCA1_1/QSA_5
EDCA1_2/QSA_6
EDCA1_3/QSA_7

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

GDDR5/DDR3

DQB0_0
DQB0_1
DQB0_2
DQB0_3
DQB0_4
DQB0_5
DQB0_6
DQB0_7
DQB0_8
DQB0_9
DQB0_10
DQB0_11
DQB0_12
DQB0_13
DQB0_14
DQB0_15
DQB0_16
DQB0_17
DQB0_18
DQB0_19
DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31
DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8
DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31

2

2

1 MARS@

RV184

CV245
1U_0402_6.3V6K

1

15mil
MVREFDA

A32
C32
D23
E22
C14
A14
E10
D9

<23>
<23>
<23>

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

1

40.2_0402_1%
MARS@

WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7

A_BA2
A_BA0
A_BA1

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

2

RV183

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_BA2
MAA1_6/MAA_BA0
MAA1_7/MAA_BA1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1

1

1

+1.5VSDGPU

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

2

1

GDDR5/DDR3

<23>

DQMA#[0..7]

1

(SUN 64 bin on at Channel B)

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

DQMA#[0..7]

MDB[0..63]

CV246
1U_0402_6.3V6K

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

MDB[0..63]

2

MDA[0..63]

MDA[0..63]

MEMORY INTERFACE A

<23>

<24>

MEMORY INTERFACE B

PART 3 0F 9

1

A

3

1
2
1
2
VGA@
VGA@
RV194
RV195
10_0402_5% 1 VGA@ 51.1_0402_1%
VGA@
CV249
RV196
120P_0402_50V8
4.99K_0402_1%
2

VRAM_RST#

<23,24>

Place all these components very close
to GPU (Within 25mm) and
keep all component close to
each Other (within5mm) except Rser2
The suggested components are tested on the AMD
reference board only. Customers must measure the slew
on each memory part to ensure that the slew rate meets
the DRAM specification.

4

Security Classification

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

Issued Date

Deciphered Date

2013/07/10

Title

MARS-Pro_MEMORY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

4

D

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

E

20

of

57

Rev
1.0

A

B

C

D

E

UV6E
PART 5 0F 9

VGAPC@
VGA@

2

1

2

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

VDDR4
VDDR4
VDDR4
VDDR4

(SUN NC)

VCC_GPU_SENSE

TV34

VSS_GPU_SENSE

VSS_GPU_SENSE

AG28
AH29

FB_VDDC
FB_VDDCI
FB_GND

1

<52>

AF28

2

@
RV197
0_0402_5%

2

1

2

1

2

1

2

1

VGA@

VGA@

VGAPC@

1

1

1

2

2

2

+0.95VSDGPU

VGAPC@

1.4A

60mil

VGAPC@

1
+VGA_CORE

30A (TBD)

2

+0.95VSDGPU

VGA@

1

2

1

2

Must always be connected to PCIE_VDDC.
0.95 V for "Mars" and
"Heathrow"/"Chelsea" on both BACO and
non-BACO designs.
2

AH22
AH27
AH28
M26
N24
R18
R21
R23
R26
T17
T20
T22
T24
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

3

360mil

VGAPC@ VGAPC@ VGAPC@

+VGA_CORE

3.5A (DDR3)
1

2

1

2

1

2

CV291
0.1U_0402_16V4Z

VCC_GPU_SENSE

1

CV290
0.1U_0402_16V4Z

10mil
<52>

VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI

2

CV289
0.1U_0402_16V4Z

VOLTAGE
SENESE

ISOLATED
CORE I/O

3

1

2

+1.8VSDGPU

CV370
10U_0603_6.3V6M

1

CV287
1U_0402_6.3V6K

2

CV286
10U_0603_6.3V6M

1

+VDDR4

CV288
0.1U_0402_16V4Z

BLM15AG121SN1D_L0402_2PMARS@

VGAPC@
MARS@

DVP

VDDR4
VDDR4
VDDR4
VDDR4

2

1

CV274
10U_0603_6.3V6M

AF15
AG11
AG13
AG15

20mil

VGA@

1

AD12
AF11
AF12
AF13

1

VGAPC@
CV367
0.1U_0402_16V4Z

2

300mA

100mil

2

CV260
1U_0402_6.3V6K

1

2.5A

1

CV366
0.01U_0402_16V7K

VGA@
CV285
0.1U_0402_16V4Z

2

CV284
1U_0402_6.3V6K

CV283
1U_0402_6.3V6K

2

1

I/O

VDDR3
VDDR3
VDDR3
VDDR3

VGA@
CV259
1U_0402_6.3V6K

VGA@

AF23
AF24
AG23
AG24

2

VGAPC@

VGAPC@ VGAPC@

VGA@

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18

1

CV254
10U_0603_6.3V6M

25mA
+VDDR3

@

CV258
1U_0402_6.3V6K

10mil

VDD_CT
VDD_CT
VDD_CT
VDD_CT

@

2

VGAPC@

CV269
1U_0402_6.3V6K

2

LEVEL
TRANSLATION

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

N27
T27

2

100mA

1

CV279
10U_0603_6.3V6M

1

VGAPC@

1

+1.8VSDGPU

AF27
AG26
AG27

VGA@

1

BLM15AG121SN1D_L0402_2P

LV9

2

CV282
0.1U_0402_16V4Z

LV8

2

1

CV281
1U_0402_6.3V6K

2

CV280
10U_0603_6.3V6M

1

13mA

+VDDC_CT AF26

VGA@

CORE

BIF_VDDC
BIF_VDDC

1

CV278
1U_0402_6.3V6K

20mil
VGAPC@
VGA@

BACO

VGAPC@
VGA@

NC For Mars

CV277
1U_0402_6.3V6K

+VDDC_CT
VGA@

2

2

2

1

BLM15AG121SN1D_L0402_2P

+3VSDGPU

1

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

20mil

CV273
1U_0402_6.3V6K

2

VGA@

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

AA31
AA32
AA33
AA34
W30
Y31
V28
W29
AB37

CV268
1U_0402_6.3V6K

1

CV276
2.2U_0402_6.3V6M

2

VGA@
CV266
2.2U_0402_6.3V6M

LV7

2

+1.8VSDGPU

2

1

CV265
2.2U_0402_6.3V6M

2

VGA@

1

NC#AA31
NC#AA32
NC#AA33
NC#AA34
NC#W30
NC#Y31
NC_BIF_VDDC
NC_BIF_VDDC
PCIE_PVDD

CV257
1U_0402_6.3V6K

VGAPC@
CV264
2.2U_0402_6.3V6M

1

MEM I/O

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

CV368
1U_0402_6.3V6K

2

CV275
2.2U_0402_6.3V6M

2

CV263
10U_0603_6.3V6M

1

CV262
10U_0603_6.3V6M

VGAPC@
VGA@

1

CV261
10U_0603_6.3V6M

VGA@

1

AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

CV369
1U_0402_6.3V6K

2

1

2

VGA@
CV256
0.1U_0402_16V4Z

2

1

VGA@

2

2

CV272
0.1U_0402_16V4Z

2

1

CV255
0.1U_0402_16V4Z

1

2

1

VGAPC@
VGA@

CV271
0.1U_0402_16V4Z

2

CV270
0.1U_0402_16V4Z

1

2

VGA@

1

CV267
0.01U_0402_16V7K

VGAPC@
VGA@

1

1

CV253
0.01U_0402_16V7K

2

VGA@
CV252
0.01U_0402_16V7K

1

CV251
0.01U_0402_16V7K

2

CV250
0.01U_0402_16V7K

1

1.5A

VGAPC@

PCIE

+1.5VSDGPU

2160842006A0MARSXT_FCBGA962
@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

MARS-Pro_PWR/GND

Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

E

21

of

Rev
1.0
57

A

B

C

D

E

UV6F
PART 6 0F 9

1

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

AP20
AP21
AP22
AP23
AU18
AV19

AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20

237mA
+1.8VSDGPU

VGAPC@
1

AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

2

VGA@
1

VGA@
1

2

2

AH34
AJ34
AF34
AG34
AM37
AL38
AM32

DP_VDDC

DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC

NC#AN24
NC#AP24
NC#AP25
NC#AP26
NC#AU28
NC#AV29
NC#AP20
NC#AP21
NC#AP22
NC#AP23
NC#AU18
NC#AV19

NC#AP13
NC#AT13
NC#AP14
NC#AP15

DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR

CALIBRATION

AW28

AW18
RV198
150_0402_1%
2 MARS@ 1 AM39

AP31
AP32
AN33
AP33
AL33
AM33
AK33
AK34
AN31

20mil
280mA

VGA@

VGA@

VGA@

1

1

1

2

AP13
AT13
AP14
AP15

2

2

+0.95VSDGPU

2

DP GND

DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR

CV297
0.1U_0402_16V4Z

NC#AG22

AN24
AP24
AP25
AP26
AU28
AV29

CV296
1U_0402_6.3V6K

4

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

PART 8 0F 9
DP_VDDR

CV295
10U_0603_6.3V6M

3

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

UV6H

CV294
10U_0603_6.3V6M

2

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

1

CV293
1U_0402_6.3V6K

GND

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20

CV292
0.1U_0402_16V4Z

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

NC#AW28

NC#AW18

DP_CALR

AN27
AP27
AP28
AW24
AW26
AN29
AP29
AP30
AW30
AW32
AN17
AP16
AP17
AW14
AW16
AN19
AP18
AP19
AW20
AW22
AN34
AP39
AR39
AU37
AF39
AH39
AK39
AL34
AV27
AR28
AV17
AR18
AN38
AM35
AN32

3

2160842006A0MARSXT_FCBGA962
@

AG22

4

VSS_MECH
VSS_MECH
VSS_MECH

A39
AW1
AW39

Issued Date

2012/07/10

2013/07/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2160842006A0MARSXT_FCBGA962
@

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

B

C

D

Title

MARS-Pro_PWR/GND

Size Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

E

22

of

57

Rev
1.0

A

B

UV10
VREFCA_A1 M8
VREFDA_Q1 H1

<20>

MAA[0..15]

<20>

MDA[0..63]

<20>

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

MAA[0..15]
MDA[0..63]
DQMA#[0..7]

DQMA#[0..7]

1

QSA[0..7]

<20>

QSA[0..7]

<20>

QSA#[0..7]

QSA#[0..7]

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

C

@

UV11

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA25
MDA30
MDA26
MDA24
MDA28
MDA31
MDA27
MDA29

D7
C3
C8
C2
A7
A2
B8
A3

MDA12
MDA11
MDA15
MDA10
MDA14
MDA9
MDA13
MDA8

M8
H1

VREFDA_Q1
VREFCA_A1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

+1.5VSDGPU

@

D

UV12

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA23
MDA19
MDA20
MDA17
MDA21
MDA16
MDA22
MDA18

D7
C3
C8
C2
A7
A2
B8
A3

MDA0
MDA6
MDA1
MDA4
MDA3
MDA7
MDA2
MDA5

VREFCA_A3
VREFDA_Q3
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

+1.5VSDGPU

M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

@

UV13

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA54
MDA48
MDA51
MDA53
MDA49
MDA55
MDA52
MDA50

D7
C3
C8
C2
A7
A2
B8
A3

MDA60
MDA56
MDA63
MDA59
MDA61
MDA57
MDA62
MDA58

M8
H1

VREFDA_Q3
VREFCA_A3

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

+1.5VSDGPU

E

@

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

MDA35
MDA36
MDA37
MDA33
MDA38
MDA32
MDA39
MDA34

D7
C3
C8
C2
A7
A2
B8
A3

MDA40
MDA44
MDA41
MDA46
MDA43
MDA45
MDA42
MDA47

UV10
X76VHYNIX0@
SA00003YO90

S IC D3 128M16 H5TQ2G63DFR-11C FBGA ABO!
UV11

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

X76VHYNIX0@
SA00003YO90

S IC D3 128M16 H5TQ2G63DFR-11C FBGA ABO!

1

UV12

+1.5VSDGPU

X76VHYNIX0@
SA00003YO90

<20>
<20>
<20>

M2
N8
M3

A_BA0
A_BA1
A_BA2

CLKA0
CLKA0#
<20>

CKEA0

J7
K7
K9

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A_BA0
A_BA1
A_BA2

M2
N8
M3

CLKA0
CLKA0#
CKEA0

J7
K7
K9

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

<20>

A_BA0
A_BA1
A_BA2

M2
N8
M3

CLKA1
CLKA1#

J7
K7
K9

CKEA1

BA0
BA1
BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

+1.5VSDGPU

A_BA0
A_BA1
A_BA2

M2
N8
M3

CLKA1
CLKA1#
CKEA1

J7
K7
K9

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

B2
D9
G7
K2
K8
N1
N9
R1
R9

S IC D3 128M16 H5TQ2G63DFR-11C FBGA ABO!
UV13
X76VHYNIX0@
SA00003YO90
+1.5VSDGPU
S IC D3 128M16 H5TQ2G63DFR-11C FBGA ABO!

QSA#3
QSA#1

G3
B7

VRAM_RST#

VRAM_RST#

T2

1

L8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

RV199
243_0402_1%
VGA@

J1
L1
J9
L9

DML
DMU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9

ODTA0
CSA0#
RASA0#
CASA0#
WEA0#

K1
L2
J3
K3
L3

QSA2
QSA0

F3
C7

DQMA#2
DQMA#0

E7
D3

QSA#2
QSA#0

G3
B7

VRAM_RST#

T2
L8
J1
L1
J9
L9

RV200
243_0402_1%
VGA@

ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

96-BALL
SDRAM DDR3
S IC D3 128M16 H5TQ2G63DFR-11C FBGA

A1
A8
C1
C9
D2
E9
F1
H2
H9

<20> ODTA1
<20> CSA1#
<20> RASA1#
<20> CASA1#
<20> WEA1#

ODTA1

QSA6
QSA7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

K1
L2
J3
K3
L3
F3
C7

DQMA#6
DQMA#7

E7
D3

QSA#6
QSA#7

G3
B7

VRAM_RST#

T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

RV201
243_0402_1%
VGA@

J1
L1
J9
L9

ODT/ODT0
CS/CS0
RAS
CAS
WE

96-BALL
SDRAM DDR3
S IC D3 128M16 H5TQ2G63DFR-11C FBGA

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

K1
L2
J3
K3
L3

QSA4
QSA5

F3
C7

DQMA#4
DQMA#5

E7
D3

QSA#4
QSA#5

G3
B7

VRAM_RST#

T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

ODTA1
CSA1#
RASA1#
CASA1#
WEA1#

1

E7
D3

DQSL
DQSU

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
L1
J9
L9

RV202
243_0402_1%
VGA@

ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

DQMA#3
DQMA#1

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

1

<20,24>

2

F3
C7

ODT/ODT0
CS/CS0
RAS
CAS
WE

2

QSA3
QSA1

K1
L2
J3
K3
L3

1

ODTA0

ODTA0
<20> CSA0#
<20> RASA0#
<20> CASA0#
<20> WEA0#

2

<20>

96-BALL
SDRAM DDR3
S IC D3 128M16 H5TQ2G63DFR-11C FBGA

A1
A8
C1
C9
D2
E9
F1
H2
H9

UV10
X76VHYNIX1@
SA00006H430

S IC D3 128MX16 H5TC2G63FFR-11C FBGA 96P ABO !

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

UV11
X76VHYNIX1@
SA00006H430
S IC D3 128MX16 H5TC2G63FFR-11C FBGA 96P ABO !
UV12
X76VHYNIX1@

2

SA00006H430

B1
B9
D1
D8
E2
E8
F9
G1
G9

S IC D3 128MX16 H5TC2G63FFR-11C FBGA 96P ABO !
UV13
X76VHYNIX1@
SA00006H430

S IC D3 128MX16 H5TC2G63FFR-11C FBGA 96P ABO !

96-BALL
SDRAM DDR3
S IC D3 128M16 H5TQ2G63DFR-11C FBGA

+1.5VSDGPU
+1.5VSDGPU

+1.5VSDGPU

+1.5VSDGPU

1

1

2

2

2

1
2

2

1

1

2

2
1
2

1

2

2

2

2

1

2

1

+1.5VSDGPU

2

RV213

40.2_0402_1%

1

VGA@

1

1

VGA@

1

1

2

2

2

2

2

2

2

2

2

1

CV321
1U_0402_6.3V6K

VGA@

1

CV320
1U_0402_6.3V6K

VGA@

1

CV319
1U_0402_6.3V6K

2

2

1

2

2012/07/10

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

2

1

2

1

2

1

2

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

2

CV404
1U_0402_6.3V6K

2

1

CV458
0.1U_0402_16V4Z

1

CV457
0.1U_0402_16V4Z

2

2

VGAPC@ VGAPC@ VGAPC@
CV456
0.1U_0402_16V4Z

2

1

CV406
0.1U_0402_16V4Z

2

1

CV405
0.1U_0402_16V4Z

2

1

CV401
0.1U_0402_16V4Z

1

CV400
0.1U_0402_16V4Z

2

CV399
0.1U_0402_16V4Z

1

1

CV403
1U_0402_6.3V6K

1

4

VGAPC@ VGAPC@ VGAPC@ VGAPC@ VGAPC@

2

1

VGAPC@ VGAPC@ VGAPC@
CV402
1U_0402_6.3V6K

CV331
0.01U_0402_16V7K
VGA@

VGA@

1

CV318
1U_0402_6.3V6K

2

2

VGA@

1

CV317
1U_0402_6.3V6K

1

2

VGA@

1

CV323
10U_0603_6.3V6M

40.2_0402_1%

2

VGA@

1

CV330
10U_0603_6.3V6M

2

VGA@

1

CV329
10U_0603_6.3V6M

RV214

2

2

VGAPC@ VGAPC@ VGAPC@
VGA@
CV328
10U_0603_6.3V6M

1

CV327
10U_0603_6.3V6M

CLKA1#

CV326
10U_0603_6.3V6M

<20>

1

CV397
1U_0402_6.3V6K

VGA@

1

+1.5VSDGPU

1

CV396
1U_0402_6.3V6K

VGA@

1

2

VGAPC@ VGAPC@ VGAPC@

CV394
1U_0402_6.3V6K

VGA@

1

CV390
1U_0402_6.3V6K

CLKA1

2

CV409
1U_0402_6.3V6K

1

+1.5VSDGPU

CV325
10U_0603_6.3V6M

2

1

2
CV322
0.01U_0402_16V7K
VGA@

CV324
10U_0603_6.3V6M

2

1

1

CV389
1U_0402_6.3V6K

VGA@

CV455
0.1U_0402_16V4Z

2

1

CV454
0.1U_0402_16V4Z

2

1

1

40.2_0402_1%

2

VGAPC@ VGAPC@ VGAPC@
CV453
0.1U_0402_16V4Z

2

1

CV398
0.1U_0402_16V4Z

2

1

CV395
0.1U_0402_16V4Z

1

CV393
0.1U_0402_16V4Z

2

CV392
0.1U_0402_16V4Z

CV391
0.1U_0402_16V4Z

2

1

1

2

RV212

VGA@

1

VGA@

1

<20>

VGAPC@ VGAPC@ VGAPC@ VGAPC@ VGAPC@

VGA@

CV388
1U_0402_6.3V6K

2

VGA@

2

2
40.2_0402_1%

1

VGA@

CV407
1U_0402_6.3V6K

CLKA0#

2

VGAPC@ VGAPC@ VGAPC@
VGA@

CV412
1U_0402_6.3V6K

2

1

2

+1.5VSDGPU

CV316
1U_0402_6.3V6K

2

1

CV452
0.1U_0402_16V4Z

1

CV451
0.1U_0402_16V4Z

2

VGAPC@ VGAPC@ VGAPC@
CV450
0.1U_0402_16V4Z

2

1

CV387
0.1U_0402_16V4Z

2

1

CV386
0.1U_0402_16V4Z

2

1

CV385
0.1U_0402_16V4Z

1

CV384
0.1U_0402_16V4Z

2

CV383
0.1U_0402_16V4Z

1

2

3

VGA@
VGAPC@ VGAPC@ VGAPC@ VGAPC@ VGAPC@

1

2

+1.5VSDGPU

CV315
1U_0402_6.3V6K

<20>

1
RV211

VGA@

1

VGA@

2

CV314
1U_0402_6.3V6K

CLKA0

2

VGA@

1

CV306
1U_0402_6.3V6K

2

2

VGA@

1

CV305
1U_0402_6.3V6K

VREFDA_Q3

RV210
CV301
4.99K_0402_1%
VGA@

2

VGA@

1

CV304
1U_0402_6.3V6K

VGA@

1

2

VGA@

CV303
1U_0402_6.3V6K

CV300

VGA@
<20>

1

CV313
1U_0402_6.3V6K

2

VGA@

1

CV312
1U_0402_6.3V6K

2

1

VGA@

1

CV302
1U_0402_6.3V6K

2

RV209
4.99K_0402_1%
VGA@

0.1U_0402_16V4Z

2

1

CV449
0.1U_0402_16V4Z

1

CV448
0.1U_0402_16V4Z

2

2

CV299
VGA@

VGA@

1

2

15mil

VREFCA_A3

1

RV208
4.99K_0402_1%
VGA@

VGAPC@ VGAPC@ VGAPC@
CV447
0.1U_0402_16V4Z

2

1

CV414
0.1U_0402_16V4Z

2

1

CV413
0.1U_0402_16V4Z

2

1

CV411
0.1U_0402_16V4Z

1

CV410
0.1U_0402_16V4Z

2

CV408
0.1U_0402_16V4Z

1

VGA@

1

0.1U_0402_16V4Z

VGAPC@ VGAPC@ VGAPC@ VGAPC@ VGAPC@

CV298

0.1U_0402_16V4Z

RV207
4.99K_0402_1%
VGA@

+1.5VSDGPU

0.1U_0402_16V4Z

+1.5VSDGPU

15mil

VGA@

1

CV311
1U_0402_6.3V6K

VREFDA_Q1

VGA@

CV310
1U_0402_6.3V6K

15mil

VREFCA_A1

RV206
4.99K_0402_1%
VGA@

CV309
1U_0402_6.3V6K

15mil

RV205
4.99K_0402_1% VGA@

CV308
1U_0402_6.3V6K

RV204
4.99K_0402_1% VGA@

CV307
1U_0402_6.3V6K

RV203
4.99K_0402_1% VGA@

3

+1.5VSDGPU

1

1

+1.5VSDGPU

Title

VRAM_DDR3 / Channel A
Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

E

23

of

Rev
1.0
57

A

B

UV14
VREFCB_A1 M8
VREFDB_Q1 H1

<20>
<20>
<20>

MAB[0..15]

MAB[0..15]

MDB[0..63]

MDB[0..63]

DQMB#[0..7]

DQMB#[0..7]

<20>

QSB[0..7]

<20>

QSB#[0..7]

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15

QSB[0..7]
QSB#[0..7]

1

<20>
<20>
<20>

M2
N8
M3

B_BA0
B_BA1
B_BA2

CLKB0
CLKB0#
<20>
<20>

CKEB0

ODTB0
<20> CSB0#
<20> RASB0#
<20> CASB0#
<20> WEB0#

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

J7
K7
K9
K1
L2
J3
K3
L3

ODTB0

QSB3
QSB1

F3
C7

DQMB#3
DQMB#1

E7
D3

C

@

UV15

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDB31
MDB26
MDB25
MDB29
MDB28
MDB30
MDB24
MDB27

D7
C3
C8
C2
A7
A2
B8
A3

MDB12
MDB11
MDB15
MDB9
MDB13
MDB8
MDB14
MDB10

VREFDB_Q1
VREFCB_A1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15

+1.5VSDGPU

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

B_BA0
B_BA1
B_BA2

M2
N8
M3

CLKB0
CLKB0#
CKEB0

J7
K7
K9
K1
L2
J3
K3
L3

ODTB0
CSB0#
RASB0#
CASB0#
WEB0#

QSB2
QSB0

F3
C7

DQMB#2
DQMB#0

E7
D3

D

@

UV16

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDB23
MDB16
MDB22
MDB18
MDB21
MDB19
MDB20
MDB17

D7
C3
C8
C2
A7
A2
B8
A3

MDB2
MDB4
MDB0
MDB6
MDB3
MDB7
MDB1
MDB5

VREFCB_A3 M8
VREFDB_Q3 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15

+1.5VSDGPU

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

B2
D9
G7
K2
K8
N1
N9
R1
R9

<20>

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

<20>

B_BA0
B_BA1
B_BA2

M2
N8
M3

CLKB1
CLKB1#

J7
K7
K9

CKEB1
ODTB1

ODTB1
<20> CSB1#
<20> RASB1#
<20> CASB1#
<20> WEB1#

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

K1
L2
J3
K3
L3

QSB4
QSB5

F3
C7

DQMB#4
DQMB#5

E7
D3

E

@

UV17

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDB35
MDB37
MDB34
MDB39
MDB33
MDB38
MDB32
MDB36

D7
C3
C8
C2
A7
A2
B8
A3

MDB46
MDB43
MDB47
MDB41
MDB44
MDB42
MDB45
MDB40

VREFDB_Q3 M8
VREFCB_A3 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15

+1.5VSDGPU

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

M2
N8
M3

CLKB1
CLKB1#
CKEB1

J7
K7
K9

ODTB1
CSB1#
RASB1#
CASB1#
WEB1#

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

B_BA0
B_BA1
B_BA2

F3
C7

DQMB#6
DQMB#7

E7
D3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDB55
MDB49
MDB52
MDB50
MDB53
MDB48
MDB54
MDB51

D7
C3
C8
C2
A7
A2
B8
A3

MDB59
MDB62
MDB58
MDB63
MDB56
MDB61
MDB57
MDB60

UV14
X76VHYNIX0@
SA00003YO90

S IC D3 128M16 H5TQ2G63DFR-11C FBGA ABO!
UV15
X76VHYNIX0@
SA00003YO90
S IC D3 128M16 H5TQ2G63DFR-11C FBGA ABO!

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

B2
D9
G7
K2
K8
N1
N9
R1
R9

1

UV16
X76VHYNIX0@

+1.5VSDGPU

BA0
BA1
BA2

K1
L2
J3
K3
L3

QSB6
QSB7

@

SA00003YO90

S IC D3 128M16 H5TQ2G63DFR-11C FBGA ABO!
UV17
X76VHYNIX0@
SA00003YO90
+1.5VSDGPU

S IC D3 128M16 H5TQ2G63DFR-11C FBGA ABO!

A1
A8
C1
C9
D2
E9
F1
H2
H9

UV14
X76VHYNIX1@
SA00006H430

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

T2
L8

RV216
243_0402_1%

J1
L1
J9
L9

VGA@

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

96-BALL
SDRAM DDR3
S IC D3 128M16 H5TQ2G63DFR-11C FBGA

QSB#4
QSB#5

G3
B7

VRAM_RST#

T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

RV217
243_0402_1%

VGA@

J1
L1
J9
L9

DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

96-BALL
SDRAM DDR3
S IC D3 128M16 H5TQ2G63DFR-11C FBGA

+1.5VSDGPU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

RV218
243_0402_1%

1

1

1

CV335
VGA@
VGA@

2

2

2

1

2
VGA@

VGA@

VGA@

VGA@

1

1

1

1

1

2

2

2

1

2

2

2

1

2

2

VGA@ VGA@

2

2

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

1

1

1

1

1

2

2

2

2

2

1

2

1

2

1

2

CV422
1U_0402_6.3V6K

CV365
0.01U_0402_16V7K
VGA@

2

1

CV419
1U_0402_6.3V6K

2

1

CV339
1U_0402_6.3V6K

2

VGA@

1

CV338
1U_0402_6.3V6K

2

1

CV346
1U_0402_6.3V6K

2

2
VGA@

1

+1.5VSDGPU

1

Security Classification
Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

D

2

2

2

4

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

2

CV356
1U_0402_6.3V6K

VGA@

1

CV355
1U_0402_6.3V6K

VGA@

1

CV354
1U_0402_6.3V6K

VGA@

1

CV353
1U_0402_6.3V6K

VGA@

1

CV352
1U_0402_6.3V6K

VGA@

2

B

3

VGAPC@ VGAPC@ VGAPC@

1 VGA@

4

A

2

+1.5VSDGPU

VGA@
RV230
40.2_0402_1%

2

1

+1.5VSDGPU

1 VGA@ 1 VGA@ 1 VGA@

2

1

1

CV417
1U_0402_6.3V6K

1

+1.5VSDGPU

2

VGAPC@ VGAPC@ VGAPC@

VGA@
CV345
0.01U_0402_16V7K
VGA@

2

CV445
1U_0402_6.3V6K

40.2_0402_1%

2

1

CV442
1U_0402_6.3V6K

VGA@

2

2

CV440
1U_0402_6.3V6K

2

CV344
1U_0402_6.3V6K

VGA@

CV337
1U_0402_6.3V6K

2

2

+1.5VSDGPU

CV336
1U_0402_6.3V6K

1

2

1

VGAPC@ VGAPC@ VGAPC@

2

1

2

1

CV427
1U_0402_6.3V6K

2

1

2

2

2

RV226
4.99K_0402_1%

2

1

CV432
1U_0402_6.3V6K

2

CV364
10U_0603_6.3V6M

2

1

CV423
1U_0402_6.3V6K

2

CV334
VGA@
VGA@

CV363
10U_0603_6.3V6M

1

VGA@

1

CV431
1U_0402_6.3V6K

RV224
4.99K_0402_1%

1

CV362
10U_0603_6.3V6M

2

CLKB1#

VGA@

1

2

VREFDB_Q3

CV361
10U_0603_6.3V6M

1

<20>

VGA@

1

CV428
1U_0402_6.3V6K

2

1

CV357
10U_0603_6.3V6M

VGAPC@ VGAPC@ VGAPC@

CLKB1

VGA@

1

CV343
1U_0402_6.3V6K

1

RV229
40.2_0402_1%
<20>

VGA@

CV424
1U_0402_6.3V6K

2

VGAPC@ VGAPC@ VGAPC@
VGA@

VREFCB_A3

1

CV360
10U_0603_6.3V6M

2

SA00006H430
S IC D3 128MX16 H5TC2G63FFR-11C FBGA 96P ABO !

CV351
1U_0402_6.3V6K

VREFDB_Q1

CV333
VGA@
VGA@

CV359
10U_0603_6.3V6M

2

RV222
4.99K_0402_1%

VGA@

CV358
10U_0603_6.3V6M

1

2

1

CV470
0.1U_0402_16V4Z

2

1

CV469
0.1U_0402_16V4Z

1

2

CV468
0.1U_0402_16V4Z

2

CV438
0.1U_0402_16V4Z

1

CV436
0.1U_0402_16V4Z

2

CV437
0.1U_0402_16V4Z

1

CV434
0.1U_0402_16V4Z

2

CV435
0.1U_0402_16V4Z

1

RV221
4.99K_0402_1%

1

CV467
0.1U_0402_16V4Z

VGAPC@ VGAPC@ VGAPC@ VGAPC@ VGAPC@

1

CV466
0.1U_0402_16V4Z

2

2

RV228
CLKB0#

X76VHYNIX1@

1

1

1

1
VGA@

RV225
4.99K_0402_1%

VGAPC@ VGAPC@ VGAPC@
CV465
0.1U_0402_16V4Z

2

1

CV433
0.1U_0402_16V4Z

2

1

CV430
0.1U_0402_16V4Z

2

1

CV429
0.1U_0402_16V4Z

1

CV426
0.1U_0402_16V4Z

2

CV425
0.1U_0402_16V4Z

1

CLKB0

UV17

CV350
1U_0402_6.3V6K

<20>

SA00006H430

CV342
1U_0402_6.3V6K

2

X76VHYNIX1@

S IC D3 128MX16 H5TC2G63FFR-11C FBGA 96P ABO !

+1.5VSDGPU

RV227 40.2_0402_1%

<20>
VGAPC@ VGAPC@ VGAPC@ VGAPC@ VGAPC@

1

2

UV16

CV341
1U_0402_6.3V6K

2

1

SA00006H430
S IC D3 128MX16 H5TC2G63FFR-11C FBGA 96P ABO !

96-BALL
SDRAM DDR3
S IC D3 128M16 H5TQ2G63DFR-11C FBGA

CV340
1U_0402_6.3V6K

2

1

CV464
0.1U_0402_16V4Z

1

X76VHYNIX1@

CV349
1U_0402_6.3V6K

2

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

UV15

B1
B9
D1
D8
E2
E8
F9
G1
G9

CV348
1U_0402_6.3V6K

1

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

0.1U_0402_16V4Z

2

CV463
0.1U_0402_16V4Z

2

1

VGA@

VGAPC@ VGAPC@ VGAPC@
CV462
0.1U_0402_16V4Z

2

1

CV421
0.1U_0402_16V4Z

2

1

CV420
0.1U_0402_16V4Z

2

1

CV418
0.1U_0402_16V4Z

1

CV416
0.1U_0402_16V4Z

2

CV415
0.1U_0402_16V4Z

1

2

ZQ/ZQ0

J1
L1
J9
L9

S IC D3 128MX16 H5TC2G63FFR-11C FBGA 96P ABO !

+1.5VSDGPU

0.1U_0402_16V4Z

VGAPC@ VGAPC@ VGAPC@ VGAPC@ VGAPC@

1

RESET

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

+1.5VSDGPU

0.1U_0402_16V4Z

2

DQSL
DQSU

CV347
1U_0402_6.3V6K

2

RV220
4.99K_0402_1%

0.1U_0402_16V4Z

1

RV223
CV332
4.99K_0402_1% VGA@
VGA@

CV461
0.1U_0402_16V4Z

2

CV460
0.1U_0402_16V4Z

1

CV459
0.1U_0402_16V4Z

2

CV446
0.1U_0402_16V4Z

1

CV444
0.1U_0402_16V4Z

2

CV443
0.1U_0402_16V4Z

1

CV441
0.1U_0402_16V4Z

2

CV439
0.1U_0402_16V4Z

1

3

VGAPC@ VGAPC@ VGAPC@

T2

96-BALL
SDRAM DDR3
S IC D3 128M16 H5TQ2G63DFR-11C FBGA

VREFCB_A1

VGAPC@ VGAPC@ VGAPC@ VGAPC@ VGAPC@

VRAM_RST#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

+1.5VSDGPU

RV219
4.99K_0402_1% VGA@
+1.5VSDGPU

G3
B7

DML
DMU

L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSDGPU

+1.5VSDGPU

QSB#6
QSB#7

1

B1
B9
D1
D8
E2
E8
F9
G1
G9

VRAM_RST#

DQSL
DQSU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

2

VGA@

ZQ/ZQ0

2

RV215
243_0402_1%

J1
L1
J9
L9

G3
B7

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

1

1

L8

RESET

QSB#2
QSB#0

DML
DMU

2

2

T2

VRAM_RST#

VRAM_RST#

DQSL
DQSU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
1

<20,23>

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

2

G3
B7

QSB#3
QSB#1

DML
DMU

Title

VRAM_DDR3 / Channel B
Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

E

24

of

Rev
1.0
57

5

4

3

2

1

LCD POWER CIRCUIT
+3VS

+LCDVDD
U44

5

W=60mils
D

4

1

VIN
GND

2

C256
4.7U_0603_6.3V6K
PC@

VIN
EN

2

+LED_VOUT

1

3

PCH_ENVDD

AP2821KTR-G1_SOT23-5

<8>

W=60mils

1

W=20mils

SM010014520 3000ma
220ohm@100mhz
DCR 0.04

B+

L14
FBMA-L11-201209-221LMA30T_0805

2

2

D

1
EMI@

1

1

C815
1U_0402_10V6K

VOUT

R400

C259
0.1U_0603_50V7K~D

2

@

2

100K_0402_5%

<4>

1
R615
0_0402_5%

PCH_INV_PWM

@

1

EDP_DISP_UTIL

R617

2

INVTPWM

2
@

0_0402_5%

+5VS

1

<8>

2

C

2

1

+5VS_TOUCH

@EMI@
C800
220P_0402_50V7K

1 R632

2 1_0402_5%

C

@

W=60mils

BKOFF#

BKOFF#

1

<36>

PC@
R619
10K_0402_5%

2

R311
PC@

2

100K_0402_5%

1

eDP PANEL Conn.

C801
220P_0402_50V7K
@EMI@

CONN@
ACES_50406-03071-001
+3VS
<9>

CPU_EDP_HPD

1

<8>

R310

<8>

20_0402_5%

@

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+3VS_CAMERA

TOUCH_INT
USB20_P5_R
USB20_N5_R

TOUCH_INT

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

+5VS_TOUCH
TOUCH_RST

100K_0402_5%

+LCDVDD

2

B

1

1
C189
1
C188
I2C1_SDA
I2C1_SCL

<4> EDP_AUXP
<4> EDP_AUXN
<9> I2C1_SDA
<9> I2C1_SCL

CPU_EDP_HPD

R315

EDP_AUXP_C
EDP_AUXN_C

W=60mils
TOUCH_RST

CPU_EDP_HPD

BKOFF#
INVTPWM

W=20mils
+LCDVDD

1

2

+LED_VOUT

Place closed to JEDP1

C262
0.1U_0402_16V4Z

<4>
<4>

EDP_TXN1
EDP_TXP1

<4>
<4>

EDP_TXN0
EDP_TXP0

C247
C191

1
1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

EDP_TXN1_C
EDP_TXP1_C

C237
C190

1
1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

EDP_TXN0_C
EDP_TXP0_C

<10>

<10>

USB20_P5

USB20_N5

G5
G4
G3
G2
G1

35
34
33
32
31

B

JEDP1

Camera

A

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

3
2

TAI-TECH LPF0805F2SF-900T04_0805
SM070002J00
EMI@
4
USB20_P5_R

3

4

2

1

1

USB20_N5_R

A

L43

(EMI request)

Security Classification

Compal Electronics, Inc.

Compal Secret Data
2012/07/20

Issued Date

Deciphered Date

2013/07/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

eDP CONN.
Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

1

25

of

57

Rev
1.0

2

+1.8VS_RXVDD

@

1

2

+1.8VS_RXVDD

<4>
<4>

CPU_DP1_P1
CPU_DP1_N1
+3VS

C

<8>
<8>

DDI1_AUX_DP
DDI1_AUX_DN
+3VS

CA11
CA13

2
2

1 0.1U_0402_16V7K CPU_DP1_C_P0
1 0.1U_0402_16V7K CPU_DP1_C_N0

30
31

CA15
CA16

2
2

1 0.1U_0402_16V7K CPU_DP1_C_P1
1 0.1U_0402_16V7K CPU_DP1_C_N1

33
34

RA13 2
RA15 2

@
@

1 1M_0402_5%
1 100K_0402_5%

RA19 1
RA20 1

@
@

2 0_0402_5%
2 0_0402_5%

RA23 2
RA24 2

@
@

1 100K_0402_5%
1 1M_0402_5%

1.52mA

IVDD
IVDD
IVDD
IVDD

OVDD
OVDD
OVDD

4.2mA

MCUVDDH

100.5mA

RX0P
RX0N

MCUVDD

RX1P
RX1N

MCURSTN
URDBG

CA17
0.1U_0402_16V7K
1
DDI1_AUX_C_DP
1
DDI1_AUX_C_DN
CA18
0.1U_0402_16V7K
DDI1_AUX_DP_R
DDI1_AUX_DN_R

2
2

ISPSCL
ISPSDA

24
23

RXAUXP
RXAUXN

22
21

VGADDCCLK
VGADDCSDA

DCAUXP
DCAUXN

VSYNC
HSYNC

1

2

51
50
53
32

2 0.1U_0402_16V4Z
CA10 1
1
2
1
2
RA11
4.7K_0402_5%
CA14
MCURSTN
0.1U_0402_16V4Z
@

1
1
1
1

TA1

19
20

ISPSCL_R
ISPSDA_R

27
25

RA21 2
RA22 2

2
2
2
2

@
@

RA12
RA14
RA16
RA18

22_0402_5%
22_0402_5%
22_0402_5%
22_0402_5%

1 22_0402_5%
1 22_0402_5%

1
2

ISPSCL
ISPSDA

PCH_CRT_VSYNC_R
PCH_CRT_HSYNC_R

41.6mA

IT6511FN

VDDC
VDDC
VDDC
IOBN
IOBP
IOGN
IOGP

+1.8VS_RXVDD

28
37
36

DVDD18
DVDD18
DVSS18

47.3mA

IORN
IORP
VGADETECT

+1.8VS_RXVCC

39

ASPVCC

RSET

6.158mA
0.293mA

+3VS

B

RA33 1
RA34 1
RA35 1

@

2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%

42

COMP

48
47

PCSDA
PCSCL

Note: need external PU to 2K ~ 10K
6511_PWR_EN

6511_PWR_EN

XTALIN
XTALOUT

43

3

CRT_CLK_1 <27>
CRT_DATA_1 <27>

6511_3V_PWR_EN#

QA3
AO3419L_SOT23-3
RA25
1K_0402_5%
2
1
6511_3V_PWR_EN#

45

1

8
11
14

+1.8VS_DAC
2

13
12

RA26 1

2

37.4_0402_1%

10
9

RA27 1

2

37.4_0402_1%

7
6

RA28 1

PCH_CRT_B
PCH_CRT_G
2

18
RA32 1

+1.8VS_DAC
1

41
40

<27>

PCH_CRT_G

<27>

PCH_CRT_R

<27>

2 93.1_0402_1%

5
4

PCH_CRT_B

CA19
0.1U_0402_16V7K

37.4_0402_1%
PCH_CRT_R

3

1

2 CA20
0.1U_0402_16V4Z

XTALIN_6511
XTALOUT_6511

B

SYSRSTN
GND

<47>

VDDA

INT#

+3VS_6511

1

PVCC
PVCC

65.5mA

+3VS

<27>
<27>

1

26
38

56.95mA

<27>
<27>

C

CRT_CLK_1
CRT_DATA_1

1

+1.8VS_RXVCC

AVCC
AVCC

@

CA3 @
0.1U_0402_16V4Z

CA2
0.1U_0402_16V4Z

CA12
2 0.1U_0402_16V4Z

1

RA29
75_0402_1% 2
RA30
75_0402_1% 2
RA31
75_0402_1% 2

+1.8VS_RXVCC

2

D

<36>
OSCOUT
35
29

1

D

CPU_DP1_P0
CPU_DP1_N0

HPD

2

S

<4>
<4>

DP_HPD

DDCSCL
DDCSDA

<36>

44

1

+3VS_6511

2

UA1
DP_HPD

2

G

1

+3VS
RA10
100K_0402_5%

+3VS_6511

1

2 0_0603_5%

@

17
15
49
52

D

S

@
QA1
2N7002E_SOT23-3

RA4
4.7K_0402_5%
1
2
1
2
RA9
4.7K_0402_5%

2
2

DP_HPD

55
56

1

16
46
54

1
1
2

3

CPU_DP_HPD

1

LA3

RA2
22_0402_5%

2

+1.8VS_RXVCC

ISPSCL_R
ISPSDA_R

G

<8>

+1.8VS_6511

2 0_0402_5%

@
+5VS

RA3
22_0402_5%

1

RA1

2

1

2

2

D

1

2

CA9
0.1U_0402_16V4Z

1

CA7
0.1U_0402_16V4Z

@

CA6
10U_0603_6.3V6M

1

+1.8VS_DAC
LA2
1
2
BLM15AG121SN1D_L0402_2P

2 0_0603_5%

@

CA1
4.7U_0603_6.3V6K

1

LA1

+3VS_6511

1

+1.8VS_6511

CA5
0.1U_0402_16V4Z

3

+1.8VS_6511

CA4
1U_0402_6.3V6K

4

CA8
4.7U_0603_6.3V6K

5

RA37
1M_0402_5%

57

IT6511FN_QFN56_7X7

XTALOUT_6511

CA21
15P_0402_50V8J

1

XTALIN_6511

XA1
27MHZ_10PF_X3G027000BA1H-U
Crystal
3
4
OUT
GND
2
1
GND
IN
1

2

CA22
15P_0402_50V8J

2

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

ITE IT6511FN
Size
Document Number
Custom

V4DA2 M/B LA-A131P Schematic

Date:
5

4

3

2

Tuesday, July 30, 2013

Sheet
1

26

of

57

Rev
1.0

A

B

C

D

E

CRT Connector
+HDMI_5V_OUT

1

<26>
<26>
L6 EMI@
BLM18BA470SN1D_2P

1

1

CRT_R

L7

2

1

CRT_R_1

L8 EMI@
BLM18BA470SN1D_2P

1

CRT_G

2

1

CRT_G_1

0_0603_5%
1
2
@

CRT_B_1

L11 0_0603_5%
1
2
@

JCRT1

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

2

2

CRT_G_2

CRT_B_2

1
@EMI@

2

1
@EMI@

2

1
@EMI@

2

C246
10P_0402_50V8J

8
7
6
5

ISPSDA
ISPSCL
1

C245
10P_0402_50V8J

1
2
3
4

+HDMI_5V_OUT_CRT
0_0402_5%

CRT_R_2

C244
10P_0402_50V8J

2

1

C243
10P_0402_50V8J

2

1

C242
10P_0402_50V8J

2

1

C241
10P_0402_50V8J

2

1

2

C240
10P_0402_50V8J

@

1

C239
10P_0402_50V8J

RP2
150_0804_8P4R_5%

C238
10P_0402_50V8J

1

0_0603_5%
2
@

2

L9

L10 EMI@
BLM18BA470SN1D_2P
CRT_B

@

R328

CRB1.0 use 47ohm@100Mhz Bead

G
G

16
17

SUYIN_070546FR015S251ZR
CONN@

CRT_HSYNC_2

1
R645 2
33_0402_5%

CRT_VSYNC_2

1

R646 2
33_0402_5%

L12 EMI@
BLM18BA470SN1D_2P
1
2
CRT_HSYNC_3
L13 EMI@
BLM18BA470SN1D_2P
1
2
CRT_VSYNC_3

C249
10P_0402_50V8J

2

CRT_DATA_3
CRT_VSYNC_4

1

1

2

2

C251
10P_0402_50V8J

CRT_CLK_3
2

+3VS

+5VS

2

1
C779

2

1
C780

2

0.1U_0402_16V4Z

C782

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1
C781

Function
port 1 is chose
port 2 is chose

2

+5VS

+3VS

U11

CRT_DATA_1
CRT_CLK_1

<26>
<26>

<36>

CRT_SEL

1
2
5
6
7
9
10

CRT_SEL

30

T39

29

@

8
3
11
28
31
33

R
G
B
H_SOURCE
V_HOURCE
SDA_SOURCE
SCL_SOURCE
SEL
TEST
Reserved
GND
GND
GND
GND
GPAD

5V VDD
VDD
VDD
VDD
R1
G1
B1
H1_OUT
V1_OUT
SDA1
SCL1
R2
G2
B2
H2_OUT
V2_OUT
SDA2
SCL2

16
+HDMI_5V_OUT

4
23
32
27
25
22
20
18
12
14
26
24
21
19
17
13
15

3

CRT_B
CRT_G
CRT_R
CRT_HSYNC_2
CRT_VSYNC_2
CRT_DATA_3
CRT_CLK_3
BLUE_DOCK
GREEN_DOCK
RED_DOCK
HSYNC_DOCK
VSYNC_DOCK
CRT_DATA_DOCK
CRT_CLK_DOCK

To CRT CONN.
SEL:Low

1

2

R648
4.7K_0402_5%

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
PCH_CRT_HSYNC_R
PCH_CRT_VSYNC_R
CRT_DATA_1
CRT_CLK_1

R302
4.7K_0402_5%

BLUE_DOCK
<37>
GREEN_DOCK
<37>
RED_DOCK
<37>
HSYNC_DOCK
<37>
VSYNC_DOCK
<37>
CRT_DATA_DOCK
<37>
CRT_CLK_DOCK
<37>

R303
4.7K_0402_5%

2

1
@

<26> PCH_CRT_B
<26> PCH_CRT_G
<26> PCH_CRT_R
PCH_CRT_HSYNC_R
PCH_CRT_VSYNC_R
<26> CRT_DATA_1
<26> CRT_CLK_1

1

1
R647
4.7K_0402_5%
@

2

From PCH

2

0.1U_0402_16V4Z

1

SELx
L
H

+3VS

3

CRT_HSYNC_4

To Docking
SEL:High

PI3V713-AZLEX_TQFN32_6X3~D
SA00004R600

4

4

Security Classification

Compal Electronics, Inc.

Compal Secret Data
2012/07/20

Issued Date

Deciphered Date

2013/07/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

CRT CONN.
Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

E

27

of

57

Rev
1.0

A

B

C

D

E

+3VS
0.1U_0402_16V4Z

0.01U_0402_16V7K
HDMI_CLK+

+3VS

2

14
28
41
56

+3VS

1

1

1

@

U12
R411
4.7K_0402_5%

R474
0_0402_5%

<37>

2
R519

DP_DOCK_SEL

@

DP_CFG0
DPSW_SW
I2C_CTL_EN

1
0_0402_5%

from PCH

<8> DDI2_CTRL_CK
<8> DDI2_CTRL_DATA

44
45
38

DPB_P0
DPB_N0

3
4

DPB_P1
DPB_N1

6
7

DPB_P2
DPB_N2

9
10

DPB_P3
DPB_N3

12
13

DPB_AUXP
DPB_AUXN

52
51
50
49

DDI2_CTRL_CK
DDI2_CTRL_DATA

11
5

CPU_HDMI_HPD

VDD33
VDD33
VDD33
VDD33

DP_D0p
DP_D0n
DP_D1p
DP_D1n

DP_CFG0/SCL_CTL
SW/SDA_CTL
I2C_CTL_EN

DP_D2p
DP_D2n

IN_D0p
IN_D0n

DP_D3p
DP_D3n

IN_D1p
IN_D1n

DP_AUXp_SCL
DP_AUXn_SDA
DP_HPD

IN_D2p
IN_D2n
DP_CA_DET
IN_D3p
IN_D3n

DP_CFG1

IN_AUXp
IN_AUXn

TMDS_CH0p
TMDS_CH0n

IN_DDC_SCL
IN_DDC_SDA

TMDS_CH1p
TMDS_CH1n

IN_CA_DET

TMDS_CH2p
TMDS_CH2n

IN_HPD
TMDS_CLKp
TMDS_CLKn

1

1

2

DPSW_DDCBUF

2

DPSW_PEQ

8
27

HDMI_REXT

46

R412
+3VS

2

1

4.7K_0402_5%
R405
4.7K_0402_5%

53

CEXT

TMDS_SCL
TMDS_SDA

TMDS_DDCBUF
TMDS_HPD
PEQ
TMDS_RT
TMDS_PRE

REXT
PD

GND
GND
GND
Thermal/GND

MODE

40
39
37
36
34
33
31
30
55
54
32

HDMI_DOCK_D2+
HDMI_DOCK_D2-

<37>
<37>

HDMI_DOCK_D1+
HDMI_DOCK_D1-

<37>
<37>

HDMI_DOCK_D0+
HDMI_DOCK_D0-

<37>
<37>

HDMI_DOCK_CK+
HDMI_DOCK_CK-

<37>
<37>

HDMI2_DOCK_SCL
HDMI2_DOCK_SDA
HDMI_HPD_DOCK

42

DP_DOCK_CAD

29

DP_CFG1

19
18

HDMI_TX0+
HDMI_TX0-

22
21

HDMI_TX1+
HDMI_TX1-

25
24

HDMI_TX2+
HDMI_TX2-

16
15

HDMI_CLK+
HDMI_CLK-

48
47

HDMI_SCLK
HDMI_SDATA

1
C535

2

C536

2

1
C537

2

2

4

0.01U_0402_16V7K

Design Guide:
Place 0.1 uF, 0.01 uF decoupling capacitors
on each VDD33/VDD15 pin,
the capacitors should be placed as close to
the chip package pins as possible

<37>
<37>
<37>

4

1

2

4

3

2
3
HDMI_R_D0-

HDMI_TX1+

HDMI_R_D1+

L17

EMI@

1

2

4

3

2
3

HDMI_TX1- TAI-TECH LPF0805F2SF-900T04_0805
SM070002J00

HDMI_R_D1-

HDMI_TX2+

HDMI_R_D2+

L18

to HDMI Conn.

4

1

EMI@

HDMI_TX0- TAI-TECH LPF0805F2SF-900T04_0805
SM070002J00

1

2 R586
2 R587

3

HDMI_R_D0+

+3VS

@
@

3

L16

4

1
1

4

2

HDMI_TX0+

1

100K_0402_5%
100K_0402_5%

2

HDMI_R_CK-

<37>

HDMI2_DOCK_SDA
HDMI2_DOCK_SCL

EMI@

1

HDMI_CLK- TAI-TECH LPF0805F2SF-900T04_0805
SM070002J00

1

to Docking

HDMI_R_CK+

L15

1

EMI@

1

2

4

3

2
3

HDMI_TX2- TAI-TECH LPF0805F2SF-900T04_0805
SM070002J00

HDMI_R_D2-

+3VS
17

HDMI_HPD

23
20

TMDS_RT
TMDS_PRE

R335 1
R336 1

26
35
43
57

2 2.2K_0402_5%
2 2.2K_0402_5%

HDMI_SDATA
HDMI_SCLK

2

DDI2_CTRL_CK
DDI2_CTRL_DATA

L30ESDL5V0C3-2_SOT23-3
3
1
2
D10 @ESD@

PS8339BQFN56GTR2-A0_QFN56_7X7

SA000060T00
1

Design Guide:
Place 2.2 uF ceramic capacitor
close to CEXT pin
Place a 4.99K 1% Resistor close
to REXT pin

1

HDMI_CEXT

2

1
2

1
R41 2
4.99K_0402_1%

R387
100K_0402_5% @

2.2U_0402_6.3V6M
C538

2

<8>

1

C534

2

I2C_CTL_EN

0.1U_0402_16V4Z

I2C_CTL_EN
Low
High

Mode
Pin Control Mode
I2C Control Mode

+HDMI_5V_OUT
+5VS

U53
OUT

Control Switching Mode
SW
DP Output
HDMI Output
0
Enable
Z
1
Z
Enable

1

1

JHDMI1
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

CPU_DP2_N0

<4>

CPU_DP2_P0

<4>

CPU_DP2_N1

<4>

CPU_DP2_P1

<4>

CPU_DP2_N2

<4>

CPU_DP2_P2

<4>

CPU_DP2_N3

<4>

CPU_DP2_P3

<8>

DDI2_AUX_DN

<8>

DDI2_AUX_DP

C268 2

1 0.1U_0402_16V7K

DPB_N0

CPU_DP2_P0

C269 2

1 0.1U_0402_16V7K

DPB_P0

CPU_DP2_N1

C270 2

1 0.1U_0402_16V7K

DPB_N1

CPU_DP2_P1

C271 2

1 0.1U_0402_16V7K

DPB_P1

CPU_DP2_N2

C272 2

1 0.1U_0402_16V7K

DPB_N2

CPU_DP2_P2

C273 2

1 0.1U_0402_16V7K

DPB_P2

CPU_DP2_N3

C274 2

1 0.1U_0402_16V7K

DPB_N3

CPU_DP2_P3

C275 2

1 0.1U_0402_16V7K

DPB_P3

DDI2_AUX_DN

C283 2

1 0.1U_0402_16V7K

DPB_AUXN

DDI2_AUX_DP

C288 2

1 0.1U_0402_16V7K

DPB_AUXP

HDMI_SDATA
HDMI_SCLK
HDMI_R_CK+HDMI_5V_OUT

R337
1.5K_0402_5%
HDMI_SCLK
HDMI_SDATA

HDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1-

2

<4>

+HDMI_5V_OUT

CPU_DP2_N0

R338
1.5K_0402_5%

HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21
22
23

4

SUYIN_100042GR019M27SZL
CONN@

DC232000S00

TMDS_PRE

2

2

HDMI connector

1

R484
4.7K_0402_5%

TMDS_RT

R386
100K_0402_5%
@

2

1

+3VS

@
R478
4.7K_0402_5%

C802
0.1U_0402_16V4Z

HDMI_HPD

HDMI_HPD

2

R461
4.7K_0402_5%
@
1

1

1

R450
4.7K_0402_5%
@

2

3

R460
4.7K_0402_5%
@
DPSW_PEQ

1
2

AP2330W-7_SC59-3

2

2

2
1

DPSW_DDCBUF

3

IN
GND

Power Mode
Control port switching
Automatic port switching

2

+3VS
2

R448
4.7K_0402_5%

R467
4.7K_0402_5%
@

1

R477
4.7K_0402_5%
@

1

DP_CFG0

2

DP_CFG1

AUTOSW_EN
Low
High

+3VS

2

1

R463
4.7K_0402_5%
@

2

1

R475
4.7K_0402_5%
@

4

+3VS

2

+3VS

2

+3VS

HPD_SRC
DP_HPD
HDMI_HPD

1

3

1

W=40mils

R482
4.7K_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

1

1

R481
4.7K_0402_5%
@

2012/07/20

2013/07/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

HDMI CONN.
Size Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Monday, August 05, 2013

Sheet

E

28

of

57

Rev
1.0

A

B

C

D

E

HDD Board Conn
JHDD1
<6>
<6>

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

<6>
<6>

1

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

C279 1
C280 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

C281 1
C282 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0

+5VS

+5VS_HDD
J2
1

2

JUMP_43X118
@

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
G1
G2
G3
G4

1

+5VS_HDD

100mils

10U_0805_10V4Z

1

1

2

2

ACES_50406-02071-001
CONN@

1

2

C287
1000P_0402_50V7K

C284

C286
0.1U_0402_16V4Z

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

@

SP010016L00
2

2

APS G-Sensor

1

+3VS

+3VS

2

R523
0_0402_5%
U26
@

<15,34,7>
<15,34,7>

3

+3VS

D_CK_SCLK
D_CK_SDATA

R521 1
R522 1

@

2 10K_0402_5%
2 10K_0402_5%

8
4
6
7
16
15
13
2
3

Vdd_IO
CS
SCLSPC
SDA/SDI/SDO
SDO/SA0

Vdd

1

PC@
2 10U_0603_6.3V6M
C633 1

14

C628 1

11
9

1

2 0.1U_0402_16V4Z
3

INT1
INT2

ADC1
ADC2
ADC3

RES

NC
NC

GND
GND

R524
10

2

G_SEN_INT

G_SEN_INT

<8>

0_0402_5%
@

5
12

LIS3DHTR_LGA16_3X3
SA00004VF00

LIS3DH
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/20

Deciphered Date

Title

2013/07/20

HDD & G-Sensor

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

V4DA2 M/B LA-A131P Schematic

Tuesday, July 30, 2013

Sheet
E

29

of

57

Rev
1.0

5

4

3

2

1

+3VS_MSATA

D

<6>
<6>

SATA_PRX_DTX_P1
SATA_PRX_DTX_N1

<6>
<6>

SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

SATA_PRX_DTX_P1
SATA_PRX_DTX_N1

C381 2
C382 2

1 MSATA_PRX_C_DTX_P1 0.01U_0402_16V7K
1 MSATA_PRX_C_DTX_N1 0.01U_0402_16V7K

SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

C380 2
C379 2

1 MSATA_PTX_C_DRX_N1 0.01U_0402_16V7K
1 MSATA_PTX_C_DRX_P1 0.01U_0402_16V7K
+3VS_MSATA

R407 1
R408 1

2 1K_0402_5% E51TXD_P80DATA_R
2 1K_0402_5% E51RXD_P80CLK_R

53

1

<36> E51TXD_P80DATA
<36> E51RXD_P80CLK

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND1

GND2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

0.1U_0402_16V4Z

JMINI3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1

0.1U_0402_16V4Z

+3VS_MSATA

C378

2

1

60mil

+3VS
C377

+3VS_MSATA

J4
1

2

2

JUMP_43X118
@
D

PLT_RST_BUF#

PLT_RST_BUF#

R657 1

2 0_0402_5%

<30,31,34,8>

DEVSLP1

DEVSLP1

@

<9>

54

LOTES_AAA-PCI-092-P01-A
CONN@

2

R409
100K_0402_5%

<8,9>

MSATA_DET#

MSATA_DET#

1

R439 2
240_0402_1%

C

C

+3VS
+3VALW

+3V_NFC

SML0CLK

1

1
2
R643 0_0402_5%

<31,7>

SML0DATA

3

SML0DATA

@
R639
499_0402_1%

@
0_0603_5%

1

2 R637

0_0603_5%

1

2 R640

+3VS
SML0CLK_NFC

5

<31,7>

1

2

Q53A
DMN66D0LDW-7_SOT363-6
@
6
SML0CLK

2

@
R638
499_0402_1%

1

2

+3VS

4

SML0DATA_NFC

+3V_NFC
CONN@
HB_A511510-SCHR22

Q53B @
DMN66D0LDW-7_SOT363-6
1
R642

B

<9>

2
0_0402_5%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

NFC_DET

NFC_DET

NFC_RESET#
+3V_NFC

+3V_NFC

SML0CLK_NFC
SML0DATA_NFC
<9>

NFC_IRQ

PLT_RST_BUF#

2

IN2

U57
MC74VHC1G08DFT2G_SC70-5

OUT

3

NC

VCC

5

GND
GND
JNFC1

2

2

2

1
4
1

PLT_RST_BUF#

IN1

@ TU12

R413
100K_0402_5%

A
Y

4

B

16
17

NFC_RESET#

GND
74AUP1G07GW_TSSOP5

R641
0_0402_5%
1
2
@

R414
100K_0402_5%
2

<30,31,34,8>

1

NFC_RST#

R644
10K_0402_5%

U58

3

<9>

GND VCC

5

1

1

+3V_NFC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/20

2013/07/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

mSATA & NFC
Size Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

1

30

of

57

Rev
1.0

5

4

3

2

1

+3VALW

+3V_LAN

1

0_0603_5%

@

2 RL2

UL1
UL3

D

LAN_CLKREQ#

LAN_CLKREQ#
PLT_RST_BUF#

1

2
0_0402_5%

@

RL1

48
36
44
45

CLK_PCIE_LAN
CLK_PCIE_LAN#
0.1U_0402_10V7K 1
0.1U_0402_10V7K 1

<10>
<10>

PCIE_PRX_DTX_P3
PCIE_PRX_DTX_N3

<10>
<10>

PCIE_PTX_C_DRX_P3
PCIE_PTX_C_DRX_N3

2 CL1 PCIE_PRX_C_DTX_P3
2 CL2 PCIE_PRX_C_DTX_N3

38
39
41
42

CLK_REQ_N
PE_RST_N

MDI_PLUS0
MDI_MINUS0

PE_CLKP
PE_CLKN

MDI_PLUS1
MDI_MINUS1

PETp
PETn

MDI

<7>
<7>

PCIE

<7,9>
<30,34,8>

PERp
PERn

MDI_PLUS2
MDI_MINUS2
MDI_PLUS3
MDI_MINUS3

13
14

LAN_MIDI0+
LAN_MIDI0-

17
18

LAN_MIDI1+
LAN_MIDI1-

20
21

LAN_MIDI2+
LAN_MIDI2-

23
24

LAN_MIDI3+
LAN_MIDI3-

VOUT

5

GND

4
CL15
1U_0402_10V6K

1

VIN
2

VIN

1

EN

3

LAN_PWR_ON

D

AP2821KTR-G1_SOT23-5

2

+3V_LAN

<9>

2

@

@

2 RL6

@
@
@
@

LAN_R_ACTIVITY#

JTAG_TDI_LAN
JTAG_TDO_LAN
JTAG_TMS_LAN
JTAG_TCK_LAN

32
34
33
35

RL9

1

2 1K_0402_5%

30

RL10

1

2 3.01K_0402_1%

12

25MHZ_10PF_7V25000014
1

1

YL1 2

2

CL4
1U_0402_10V6K

15
19
29

2

2

1

47
46
37

VDD0P9_47
VDD0P9_46
VDD0P9_37

1

2

RBIAS

7

CTRL0P9

2

WGI218LM-QQJY-B0_QFN48_6X6~D
SA000066W30

1

1

2

1

2

<36>

C

@

NOTE: Total requirement Cout>=20uF. ESR<50mohm.
LAYOUT NOTE: Place LL1, CL7, CL8, CL9, and close to PHY

PD
L
L
H

SEL
L
H
X

Function
Ax to Bx; LEDAx to LEDBx
Ax to Cx; LEDAx to LEDCx
Hi-Z

0.1U_0402_16V4Z
CL10

1

1

1

CL11

LAN Switch
CL12

2 4.7K_0402_5%
0.1U_0402_16V4Z

+3V_LAN

2

2

SML0CLK

1

QL2A
DMN66D0LDW-7_SOT363-6

<30,7>

+3V_LAN

SML0DATA

3

SML0DATA

2
1

6

SML0CLK

UL2

LAN_SCLK

LAN_MIDI0+

2

LAN_MIDI0-

3

A0+

4

LAN_MIDI1+

6

LAN_MIDI1-

7

LAN_SDATA

QL2B
DMN66D0LDW-7_SOT363-6
1

2 10K_0402_5%

DET_SIG#_R

RL12

@
@1

2 10K_0402_5%

JTAG_TMS_LAN

RL11

@
@1

2 10K_0402_5%

JTAG_TCK_LAN

NOTE: Default SMBus
Address is 0xC8
<37,9>

1MHz(Defaul setting)

LAN_MIDI2+

9

LAN_MIDI2-

10

LAN_MIDI3+

11

LAN_MIDI3-

12

DET_SIG#_R

DET_SIG#_R

RL13 1

RL15 & RL16

2 0_0402_5%

LAN_LINK#
LAN_ACTIVITY#

499ohm

13

15
16
42

B1+
B1-

A1+

B2+
B2-

A1-

B3+
B3-

A2+
A2-

LEDB0
LEDB1
LEDB2

A3+

C0+
C0-

A3-

C1+
C1-

SEL

C2+
C2-

LEDA0
LEDA1
LEDA2

5

100KHz/400KHz

A0-

@

SMBUS PULL-UP OPTIONS
SMBUS SPEED

B

B0+
B0-

5

<30,7>

RL15
499_0402_1%

1

RL16
499_0402_1%

2

2 0_0402_5%

VDD
VDD
VDD
VDD
VDD
VDD
VDD

B

@

2

0.1U_0402_16V4Z
2

LAN_PME#

RL7

LAN_PWR_EN

1 LL1
+0.9V_LAN_OUT 2
4.7UH_PG031B-4R7MS_1.1A_20%

49

+3V_LAN

RL19 1

2 1K_0402_5%

TEST_EN

+3VALW

PCH_PCIE_WAKE#

1

+0.9V_PHY_CORE

40
22
16
8

VDD0P9_40
VDD0P9_22
VDD0P9_16
VDD0P9_8

Connect RBIAS through a 3.01 kΩ 1%
pull-down resistor to ground and then
place it no more than one half inch
(0.5”) away from the PHY.

<34,8>

RL14

11

VDD0P9_11

2

RL17 1

LAN_PWR_ON

43

VDD0P9_43

VSS_EPAD
CL6
10P_0402_50V8J

1

CL9
10U_0805_10V4Z

4

GND

4

VDD3P3_15
VDD3P3_19
VDD3P3_29

XTAL_OUT
XTAL_IN

*IMPORTANT NOTE: LAN_PWR_EN Controls PHY Power

5

VDD3P3_IN

CL8
0.1U_0402_16V4Z

GND

1

1

JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TCK

2 4.7K_0402_5%

CL7
22U_0805_6.3V6M

CL5
10P_0402_50V8J

3

LED0
LED1
LED2

1

39
30
21
14
8
4
1

3

C

RSVD_VCC3P3_1

VDD3P3_4
26
27
25

9
10

LAN_XTALO_R
LAN_XTALI

LANWAKE_N
LAN_DISABLE_N

RL4

CL13
0.1U_0402_16V4Z

1
RL8
0_0402_5%

1

2
3

1

CL14
22U_0805_6.3V6M

0_0402_5%

TL1
TL2
TL3
TL4

LAN_XTALO

2 LAN_DISABLE_N_R
0_0402_5%

@

RL5

LAN_LINK#
LAN_ACTIVITY#

NOTE: LAN_DISABLE_N must be connected
to PCH's GPIO12/LAN_PHY_PWR_CTRL.
This GPIO12 pin must be set as
"LAN_PHY_PC" function through FITC
tool.

1

LED

LAN_PME#
LAN_DISABLE_N

<9> LAN_PME#
LAN_DISABLE_N

6

SVR_EN_N

JTAG

NOTE: LANWAKE_N must be
connected to PCH's GPIO27.

SMB_CLK
SMB_DATA

SMBUS

28
31

LAN_SCLK
LAN_SDATA

2.2Kohm

C3+
C3LEDC0
LEDC1
LEDC2

PD

43

38
37
34
33
29
28
25
24
17
18
41

LAN_MIDI0+_DOCK
LAN_MIDI0-_DOCK

<37>
<37>

LAN_MIDI1+_DOCK
LAN_MIDI1-_DOCK

<37>
<37>

LAN_MIDI2+_DOCK
LAN_MIDI2-_DOCK

<37>
<37>

LAN_MIDI3+_DOCK
LAN_MIDI3-_DOCK

<37>
<37>

To Docking.
SEL:Low

LAN_LINK#_DOCK
<37>
LAN_ACTIVITY#_DOCK
<37>

36
35
32
31
27
26
23
22

LAN_MIDI0+_RJ45
LAN_MIDI0-_RJ45

<32>
<32>

LAN_MIDI1+_RJ45
LAN_MIDI1-_RJ45

<32>
<32>

LAN_MIDI2+_RJ45
LAN_MIDI2-_RJ45

<32>
<32>

LAN_MIDI3+_RJ45
LAN_MIDI3-_RJ45

<32>
<32>

To RJ45 conn
SEL:High

19
20
40

PAD_GND

A

A

PI3L720ZHEX_TQFN42_9X3P5~D
SA00003B200

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/20

Deciphered Date

2013/07/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

LAN Intel I218
Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic

Thursday, August 01, 2013

Sheet

1

31

of

57

Rev
1.0

5

4

3

2

1

LAN Connector

JRJ1
T36
D

<31>
<31>

<31>
<31>

<31>
<31>

<31>
<31>

LAN_MIDI0+_RJ45
LAN_MIDI0-_RJ45

LAN_MIDI1+_RJ45
LAN_MIDI1-_RJ45

LAN_MIDI2+_RJ45
LAN_MIDI2-_RJ45

LAN_MIDI3+_RJ45
LAN_MIDI3-_RJ45

LAN_MIDI0+_RJ45
LAN_MIDI0-_RJ45

1
2
3

LAN_MIDI1+_RJ45
LAN_MIDI1-_RJ45

4
5
6

LAN_MIDI2+_RJ45
LAN_MIDI2-_RJ45

7
8
9

LAN_MIDI3+_RJ45
LAN_MIDI3-_RJ45

10
11
12

TCT1
TD1+
TD1-

MCT1
MX1+
MX1-

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

24
23
22

RJ45_MIDI0+
RJ45_MIDI0-

21
20
19

RJ45_MIDI1+
RJ45_MIDI1-

18
17
16

RJ45_MIDI2+
RJ45_MIDI2-

15
14
13

RJ45_MIDI3+
RJ45_MIDI3-

RJ45_MIDI3-

8

RJ45_MIDI3+

7

RJ45_MIDI1-

6

RJ45_MIDI2-

5

RJ45_MIDI2+

4

RJ45_MIDI1+

3

RJ45_MIDI0-

2
1

RJ45_MIDI0+

GND
PR4GND
PR2PR3PR3+

40mil

PR2+
PR1GND
PR1+

2

C335

C336

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

2

C337

1

10
9

SINGA_2RJ1660-000111F

350UH_IH-160-A
SP050007E00

1

D

11

PR4+

GND

1

12

CONN@

C338

DC234007U00

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

C

C

C339
RP3

1

RJ45_GND

2

LANGND

1000P_1206_2KV7K
EMI@

RJ45_GND

3

1
2
3
4

75_0804_8P4R_1%

D31
YSLC05CH_SOT23-3

1

BOTHHAND: S X'FORM_ GST5009-D LF LAN, SP050006B00
TIMAG:S X'FORM_ IH-160 LAN , SP050006F00

2

8
7
6
5

Place close to TCT pin

L27
SCA00000U10
ESD@

100UH_SSC0301101MCF_0.18A_20%
EMI@

2

RJ45_GND

1

40mil

B

B

A

A

Security Classification

Compal Electronics, Inc.

Compal Secret Data
2012/07/20

Issued Date

Deciphered Date

2013/07/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

LAN Magnetic & RJ45
Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

1

32

of

57

Rev
1.0

60mil

R395 1
C340

+VDDA

<36>

1

4.75V

2

2

BEEP#

2 0_0603_5%
<9>

1

1
C341

BEEP#_R

R376
47K_0402_5%
2
1

PCH_SPKR

1

C342
R379
47K_0402_5%

(output = 300 mA)

2

MONO_IN
1U_0402_6.3V6K

E

40mil

SPKL+
SPKL-

100P_0402_50V8J

JSPK1
R659
R660

R380
4.7K_0402_5%

1
1

2 0_0603_5%
2 0_0603_5%

1
2

SPKL+_1
SPKL-_1

Int. Speaker Conn.

1
2

3
4

D17
AZ5125-02S.R7G_SOT23-3

2
1

0.1U_0402_16V4Z

@

D

2

60mil

C

2

+5VS

B

3

A

G1
G2
3800-F02N-00R
CONN@

@ESD@

D35

SM010014520 3000ma 220ohm@100mhz DCR 0.04

+PVDD_HDA

40mil

1

2

2

1
L34 2
FBMA-L11-201209-221LMA30T_0805

D36

2

2

1

10U_0603_6.3V6M

EC_MUTE#

RB751V-40-YS_SOD323-2

Place near Pin46

1
C356

+1.5VS_VDDA

20mil

Headphone Out

1
C363

2
0.1U_0402_16V4Z

HD Audio Codec

2

JHP1

SM010015410 300ma 80ohm@100mhz DCR 0.3
SM010028800 2000ma 120ohm@100mhz DCR 0.1
Place near Pin40

20mil

SM010028800 2000ma 120ohm@100mhz DCR 0.1

2
0.1U_0402_16V4Z

<37>
<37>
<37>
<37>

HP_DOCK_R
MIC2_DOCK_L
MIC2_DOCK_R
LINE1_LEFT
LINE1_RIGHT
MIC1_LEFT
MIC1_RIGHT

1 HP_DR_L
1K_0402_5%
1 HP_DR_R
1K_0402_5%
1 MIC2_DR_L
1K_0402_5%
1 MIC2_DR_R
1K_0402_5%
1 LINE1_R_L
1K_0402_5%
1 LINE1_R_R
1K_0402_5%
1 MIC1_R_L
1K_0402_5%
1 MIC1_R_R
1K_0402_5%

C530

1

2

C531

1

2

C552

1

2

C553

1

2

C533

1

2

C532

1

2

C529

1

2

C528

1

2

17
18
22
21
19
20

2

37

10mil

+MIC1_VREFOR

1

C364

1

C374

1

3

2

29

10mil

30

10mil

31

+MIC1_VREFOL
C358

LINE2_L
LINE2_R

2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
1 20K_0402_1%

2 2.2U_0402_6.3V6M CPVEE

27
39
7
15

AUDIO_MUTE#

34

10mil

13
14

AUDIO_MUTE#

48

SENSE_A
SENSE_B

<36>

1

2 60.4_0603_5% HPOUT_R_1

1
2
NBQ100505T-800Y-N
L45

HPOUT_L_2

6
1
2

EMI@

HPOUT_R_2

3
4
5

2

SINGA_2SJ-0960-D11
CONN@

68mA600mA

1

36

9

35mA

SPK_OUT_L+

4
49

42

SPKL+

43

SPKL-

45

SPKR+

44

SPKR-

32

HP_LEFT

33

HP_RIGHT

MIC2_L
MIC2_R

SPK_OUT_L-

LINE1_L

SPK_OUT_R+

LINE1_R
SPK_OUT_RMIC1_L
HPOUT_L
MIC1_R
HPOUT_R
CBN

CBP

SDATA_OUT

MIC2_VREFO

SYNC
RESETB

MIC1_VREFO_R
BCLK

8

HDA_SDIN0_AUDIO

SPKR+

<35>

SPKR-

<35>

HDA_SDIN0
HDA_SDOUT_AUDIO

10
11

+MIC1_VREFOR

1 R383
2
33_0402_5%

5

HDA_SYNC_AUDIO
HDA_RST_AUDIO#

6

HDA_RST_AUDIO#

HDA_BITCLK_AUDIO

MIC1_VREFO_L
1
R388

LDO1_CAP
LDO2_CAP
GPIO0/DMIC_DATA
LDO3_CAP
GPIO1/DMIC_CLK
JDREF

CPVEE

PCBEEP

SENSE A
SENSE B

MONO_OUT
AVSS2
VREF

2

DMIC_DATA

3

DMIC_CLK

47

EC_MUTE#

12

MONO_IN

R596
3K_0402_5%

AVSS1

<6>
<6>

<6>

MIC1_LEFT

R595 1

2 47_0603_5%

MIC1_RIGHT

R594 1

2 47_0603_5%

<6>

@EMI@
2
1
2 C357
0_0402_5%
22P_0402_50V8J

L47
1
2
NBQ100505T-800Y-N
2
MIC1_RIGHT_1 1
NBQ100505T-800Y-N
L46
SM01000DS00
MIC1_LEFT_1

EMI@
EMI@

JEMIC1

MIC1_LEFT_2

6
1
2

MIC1_RIGHT_2

3
4
5

MIC1_JD

SINGA_2SJ-0960-D11
CONN@

For EMI

3

EC_MUTE#

<36>

28

CODEC_VREF

10mil

C360 1

2 0.1U_0402_16V4Z

C361 1

2 2.2U_0402_6.3V6M

C362 1
@

2 10U_0603_6.3V6M

25

GND

Digital MIC CONN

SM01000II00
L31 EMI@
FCM1005KF-301T01 _2P
1
2 DMIC_CLK_R
DMIC_CLK

Place next pin28

ALC3225-CG_MQFN48_6X6

DGND

Mic In
R597
3K_0402_5%

16
38

SPDIFO
DVSS

+MIC1_VREFOL

<6>

@EMI@

PD#

C359 1

HP_RIGHT R593

EMI@

2

SDATA_IN

C354
2.2U_0402_6.3V6M

+MIC2_VREFO

R389

23

35

1

External MIC

24

46

U31

HP_DC_L
4.7U_0603_6.3V6K
HP_DC_R
4.7U_0603_6.3V6K
MIC2_DC_L
4.7U_0603_6.3V6K
MIC2_DC_R
4.7U_0603_6.3V6K
LINE1_C_L
4.7U_0603_6.3V6K
LINE1_C_R
4.7U_0603_6.3V6K
MIC1_C_L
4.7U_0603_6.3V6K
MIC1_C_R
4.7U_0603_6.3V6K

DVDD

2
R577
2
R578
2
R579
2
R580
2
R581
2
R582
2
R575
2
R576

DVDD_IO

<37>

HP_DOCK_L

CPVDD

<37>

PVDD2

Place near Pin26

2

+3VS

L44
NBQ100505T-800Y-N
1
2

Place near Pin1, 9
41

2

2 60.4_0603_5% HPOUT_L_1

1
C348

0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z

C351

40

2

1

1

C350

1
C347

R592

HP_LEFT

HP_PLUG#

1

PVDD1

C349
10U_0805_10V4Z

0.1U_0402_16V4Z
1

L29
1
2
BLM18PG121SN1D_0603

10U_0603_6.3V6M

1
C346

26

1

20mil

AVDD2

+VDDA

+3VS_DVDD

+AVDD_HDA

AVDD1

L30
1
2
BLM18PG121SN1D_0603

1

0.1U_0402_16V4Z
1
C345

Place near Pin41
SM010014520 3000ma 220ohm@100mhz DCR 0.04
+1.5VS

@
RB751V-40-YS_SOD323-2

0.1U_0402_16V4Z
1
C344

1

C343
10U_0805_10V4Z

HDA_RST_AUDIO#

2

1

1

2

1
L28 2
FBMA-L11-201209-221LMA30T_0805

+VDDA

2

POP

POP

1

<37>

SA000064R00
C371
22P_0402_50V8J
@RF@

Place near
codec

2
DMIC_DATA

L32 0_0603_5%
1
2 DMIC_DATA_R
@

1

SM010028800 2000ma 120ohm@100mhz DCR 0.1
+3VS
L33 EMI@
1
2
BLM18PG121SN1D_0603

+3VS_DMIC

JDMIC1

<37>

4

<37>
<37>

HP_PLUG#

R390

2

1

39.2K_0402_1%

MIC1_JD

R391

2

1

20K_0402_1%

R444

2

1

R464

2

1

39.2K_0402_1%

R466

2

1

20K_0402_1%

LINEIN_JD

HP_DOCK_DET
MIC2_DOCK_DET

SENSE_A

10K_0402_1%

SENSE_B

GND

J5
JUMP_43X39
1
2
2
@ 1

J7
JUMP_43X39
1
2
2
@ 1

J6
JUMP_43X39
1
2
2
@ 1

J10
JUMP_43X39
1
2
2
@ 1

J8
JUMP_43X39
1
2
2
@ 1

J9
JUMP_43X39
1
2
2
@ 1

GNDA

GND

+3VS_DMIC
DMIC_CLK_R
DMIC_DATA_R

G1
G2

5
6

4

SP02000K200
CONN@

GNDA
Issued Date

Compal Electronics, Inc.

Compal Secret Data
2012/07/20

Deciphered Date

2013/07/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

1
2
3
4

ACES_50208-0040N-001

Security Classification

A

1
2
3
4

C

D

Title

HD Audio Codec_ALC3225X
Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic

Thursday, August 01, 2013

Sheet

E

33

of

57

Rev
1.0

A

B

C

D

MINI CARD(Wireless LAN & BT)

For Wireless LAN

WLAN&BT Combo module circuits
BT
on module

BT
on module

Enable

Disable

H

L

R381

1

+3VS_WLAN
2 0_0603_5%

@

+1.5VS

+3VS_WLAN

40mil

+3VS

1

1

C365

1

C366
PC@

PC@

BT_CTRL

E

2

4.7U_0603_6.3V6K

2

1

C367
0.1U_0402_16V4Z

C368

+3VS_WLAN

@

2

2

4.7U_0603_6.3V6K

0.1U_0402_16V4Z

H

2
0_0402_5%

@

R317

+1.5VS

1

PCH_PCIE_WAKE#

+3VS_WLAN
<7,8>
1
R398

2
PCH_PCIE_WAKE#_R
10K_0402_5%

1
R316

MINI1_CLKREQ#

<7>
<7>

2

@

R397

PCH_PCIE_WAKE#_R
0_0402_5%

2
0_0402_5%

@

CLK_PCIE_MINI1#
CLK_PCIE_MINI1

+3VS_WLAN
+3VALW

<10>
<10>

U46

40mil(1A)

<10>
<10>

2

PCIE_PTX_C_DRX_N4
PCIE_PTX_C_DRX_P4

VIN
WLAN_ON

+3VS_WLAN

<36>

1

<7>
<7>
<7>

R399

2

@

CL_CLK
CL_DATA
CL_RST

CL_CLK
CL_DATA
CL_RST

53

2

2

100K_0402_5%

1

3G@ 1 10K_0402_5% WAKE_OUT_WWAN

EC_3G_WKAE#
+3VS_3G

1
1

R630
R402

@

TU149
TU150
TU151
TU152

@
@
@
@

ANT_TUNE_0_AP
ANT_TUNE_1_AP
ANT_TUNE_2_AP
ANT_TUNE_3_AP
+3VS_3G

MINI_DET#

MINI_DET#

33P_0402_50V8K
330P_0402_50V7K
330P_0402_50V7K
330P_0402_50V7K
330P_0402_50V7K
R621
R622
R623
R624
R416

13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69

3G_CONFIG0
TU156 @
2 0_0402_5% WAKE_OUT_WWAN
2 10K_0402_5% BODYSAR_DET#

3G@

3

<8,9>

USB20_P4_L
USB20_N4_L

2
2
2
2

1
1
1
1

1
@
1
@
1
@
1
@
1 3G@

C520
C445
C446
C447
C448
2
2
2
2
2

@
@
@
@
@

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
10K_0402_5%
TU153 @

ANT_TUNE_0
ANT_TUNE_1
ANT_TUNE_2
ANT_TUNE_3
3G_RESET#
3G_CONFIG1

TU154 @

3G_CONFIG2

2 R665
1
0_0402_5%

3.3V
3.3V
Power_On_Off
W_DISABLE#
LED#

CONFIG_0
Reserved
Wake_On_WWAN#
Reserved
BODYSAR_N
Reserved
Ground
GPS_DISABLE#
NC
Reserved
NC
UIM-RESET
Ground
UIM-CLK
NC
UIM-DATA
NC
UIM-PWR
Ground
NC
NC
Reserved
NC
Reserved
Ground
Reserved
NC
Reserved
NC
Reserved
Ground
NC
NC
NC
NC
NC
Ground
NC
ANTCTL0
NC
ANTCTL1
Reserved
ANTCTL2
Reserved
ANTCTL3
Reserved
Reset#
SIM_DET
CONFIG_1
NC
Ground
3.3V
Ground
3.3V
CONFIG_2
3.3V
GND
GND
BELLW_80149-3223_67P

2
4
6
8
10

R401 1 3G@

2

@

1 10K_0402_5%

USB20_N4
USB20_P4

USB20_N4
USB20_P4

1
2
3
4
5

Y+
YGND
MM+

SEL
Vdd
OE
D+
D-

10
9
8
7
6

R417

2

3G@ 1 10K_0402_5%

PI3USB102ZLEX_TQFN10_1P6X1P3

+3VALW

SP07000LL00(H:4.0mm)

+3VALW TO +3VS_3G
+3VALW

3G_OFF#

3
2
1

CLK
RST
VCC

I/O
VPP
GND

6
5
4

UIM_DATA
3G@

2

1
JAE_SF7W006S4AE1000

GPS_DISABLE#
UIM_RST
UIM_CLK
UIM_DATA
UIM_PWR

20mil

3G@
C523

UIM_CLK

B+

33P_0402_50V8K

C524

3G@

C525

UIM_PWR

C526

33P_0402_50V8K

R318
0_0402_5%
@

3G@

33P_0402_50V8K

C809 1

<36>

33P_0402_50V8K

3G_PWR_ON#

3G_PWR_ON#

5
2

Q51B
DMN66D0LDW-7_SOT363-6

3G@
2 1U_0402_10V6K

3G_PWR_ON#
3

Q51A
DMN66D0LDW-7_SOT363-6
3G@

C813
0.1U_0603_25V7K
3G@

+3VS_3G

L37
USB20_P4_D

2

+3VS_3G

EMI@

2

1

3

4

1

USB20_P4_L
3G@

3G@

3G@

3G@

CONN@
3

4

USB20_N4_L

3G_OFF#

<34,36>

+3VS

SEL

OE#

Y+

Y-

X

H

Hi-Z

Hi-Z

L

L

M+

M-

H

L

D+

D-

2

1

1

2

1

2

1
1

+

2

2

1

3G@

+
2

1

3G@

+
2

3G@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/20

2013/07/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

mini Card & 3G/SSD CONN.
Size
Document Number
Custom
Date:

A

2

1

3G@

R616
470_0603_5%
3G@

3G_PWR_ON#_R

3G@
UIM_DATA

240mil

10mil

470K_0402_5%
2 R620
1
3G@

3G@
UIM_RST

+3VS_3G
U52
DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5

JSIM1

<34,36>
UIM_CLK
UIM_RST
UIM_PWR

12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68

<15,29,7>
<15,29,7>

54

2 10K_0402_5%

3G_OFF#

D_CK_SCLK
D_CK_SDATA

<10>
<10>

2

Truth Table

USB20_N4_D
USB20_P4_D

2 0_0402_5%
2 0_0402_5%

<36>

2

<10>
<10>

1

4

@
@

USB20_N6
USB20_P6

TAI-TECH LPF0805F2SF-900T04_0805
SM070002J00
R418

R403 1
R404 1

<30,31,8>

BT_CTRL

USB20_N4_D

U59

PLT_RST_BUF#
WL_OFF#

MINI1_SMBCLK
MINI1_SMBDATA

C812
4.7U_0603_6.3V6K

<36>

2

CONFIG_3
Ground
Ground
USB_D+
USB_DGround

R664 1 @
0_0402_5%

WL_OFF#
PLT_RST#_W

3

R406

2

+3VS_3G

JMINI2
1
3
5
7
9
11

3G_CONFIG3

TU155 @

GND2

<36,38,8>

CONN@

R410
0_0402_5%

+3VS_3G

GND1

PLT_RST#

220U 4V Y D2 ESR15M
C805

3

AP2821KTR-G1_SOT23-5

1 @

RB751V-40-YS_SOD323-2

220U 4V Y D2 ESR15M
C804

GND
EN

1

1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

6 1

VOUT
VIN

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

1

4

2

D38
2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

220U 4V Y D2 ESR15M
C803

5

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2

<31,8>

S

C816
1U_0402_10V6K

+3VS_WLAN

JMINI1

Q21
2N7002E_SOT23-3

22U_0805_6.3V6M
C808

2
G

BT_ON#

3

<36>

1

WLAN_PME#

0.1U_0402_16V4Z
C807

1

<36>
D

@
R663
10K_0402_5%
1

0_0402_5%

1

2

Mini Card Power Rating

BT_CTRL

4

2

330P_0402_50V7K
C444

@

33P_0402_50V8K
@EMI@ C522

1

4

L
R394

1U_0402_10V6K
C806

BT_ON#
1

B

C

D

V4DA2 M/B LA-A131P Schematic
Sheet

Tuesday, July 30, 2013

E

34

of

57

Rev
1.0

4

A

B

<10>

C

USB20_N1

USB20_N1

+5VALW

4

2

1

4

U33

1
2
3
4

1

TAI-TECH LPF0805F2SF-900T04_0805
SM070002J00
U2DP1_L

USB20_P1

+USB3_VCCA

EMI@

3

2

<35,36,37>

USB_PWR_EN#

1
1

SM070000S80 WCM2012F2SF-670T04 67ohm
2

C395
0.1U_0402_16V4Z

USB20_P1

E

U2DN1_L
L36

3

<10>

D

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

W=40mils

8
7
6
5

USB_OC0#

+USB3_VCCA
JUSB1

<10>

PCH_USB3_RX2_N

PCH_USB3_RX2_P

2

W=80mils

1

2

1

3

4

L48

EMI@

U3RXDP2
C398

1

2

+
PCH_USB3_RX2_N

3

4

U3RXDN2

100U_B2_6.3VM_R35M

1
2

For ESD request

SM070001E00
DLW21SN900HQ2L-0805_4P

<10>

PCH_USB3_TX2_P

PCH_USB3_TX2_N

PCH_USB3_TX2_P

2
C798

PCH_USB3_TX2_N

2
C799

1

2

1

3

PCH_USB3_TX2_P_C
0.1U_0402_16V7K
PCH_USB3_TX2_N_C
0.1U_0402_16V7K

2

2

1

3

4

L49

EMI@

1

U3TXDP2

4

U3TXDN2

U2DN1_L
U3RXDP2
U3RXDN2

SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-

GND
GND
GND
GND

10
11
12
13

CONN@

D37

<10>

9
1
8
3
7
2
6
4
5

U3TXDP2
U3TXDN2
U2DP1_L

C399
470P_0402_50V7K

PCH_USB3_RX2_P

<10,35,9>

1

SM070001E00
DLW21SN900HQ2L-0805_4P
<10>

USB_OC0#

G547I2P81U_MSOP8
SA00003TV00

U3RXDN2

1 1

@ESD@
10 9

U3RXDN2

U3RXDP2

2 2

9 8

U3RXDP2

U3TXDN2

4 4

7 7

U3TXDN2

U3TXDP2

5 5

6 6

U3TXDP2

3 3
2

8
L05ESDL5V0NA-4 SLP2510P8

USB3.0 Conn.(MB)
IO Board Conn(For FFC,FPC)
+3VALW

20mil(250mA)

+3VALW

+3VS

+3V_USB

U60

5
4
C833
1U_0402_10V6K

1

VOUT

1

VIN
GND

2

@

2
C832

VIN
EN

+3V_USB
<10,35,9> USB_OC0#
<10> PCH_USB3_RX1_N
<10> PCH_USB3_RX1_P

3

<10>
<10>

1 4.7U_0603_6.3V6K

@

2 0_0402_5%

R661 1

@

2 0_0402_5%

20mil

USB20_P0
USB20_N0

USB20_P0
USB20_N0

3

<36,40,46>

SYSON

<10>
<10>

PCH_USB3_RX4_N
PCH_USB3_RX4_P

<10>
<10>

PCH_USB3_TX4_N
PCH_USB3_TX4_P
<10>
<10>

USB20_P3
USB20_N3

<36> USB_CHARGE_2A#
<35,36,37> USB_PWR_EN#
<36,37> USB_CHARGE_CB0
<36> USB_CEN
<33> SPKR<33> SPKR+
<36,37> SELCDP

JIO1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

USB_OC0#

PCH_USB3_TX1_N
PCH_USB3_TX1_P
<10>
<10>

AP2821KTR-G1_SOT23-5

2

R666 1

USB20_P3
USB20_N3

USB_PWR_EN#
USB_CEN
SPKRSPKR+
+5VALW

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

3

GND2
GND1

34
33

ACES_51547-03201-W01
CONN@

4

4

Security Classification

Compal Electronics, Inc.

Compal Secret Data
2012/07/20

Issued Date

Deciphered Date

2013/07/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

USB3.0 & SSD
Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

E

35

of

57

Rev
1.0

B

C

+3VALW

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

2.2K_0804_8P4R_5%

<7> CLK_PCI_LPC
<34,38,8>
PLT_RST#
<39> EC_RST#
<6,9> EC_SCI#
<34> WLAN_ON

CLK_PCI_LPC
PLT_RST#
EC_RST#
EC_SCI#
WLAN_ON

12
13
37
20
38

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

PM_SLP_S3#
PM_SLP_S5#
<6> EC_SMI#
<35> USB_CEN
<38> CAP_LED#
<11,8> VCCST_PG_EC
<34> WL_OFF#
<45> SPOK
<39> FAN_SPEED1
<34> EC_3G_WKAE#
<30> E51TXD_P80DATA
<30> E51RXD_P80CLK
<8> PCH_PWROK
<38> PWR_SUSP_LED#
<38> NUM_LED#

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
USB_CEN
CAP_LED#
VCCST_PG_EC
WL_OFF#
SPOK
FAN_SPEED1
EC_3G_WKAE#
E51TXD_P80DATA
E51RXD_P80CLK
PCH_PWROK
PWR_SUSP_LED#
NUM_LED#

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

<34>

3G_PWR_ON#
SUSCLK

+3VS

R486
R469

1

2 10K_0402_5%

1

@
1

C417

2 10K_0402_5%

DOCK_CRT_DET#
EC_SCI#

2 0.01U_0402_16V7K

PLT_RST#
<38>

ESD@

2

ESD request

<38>

KSI[0..7]
KSO[0..17]

<43,44>
<43,44>
<16,19,7>
<16,19,7>

KSI[0..7]
KSO[0..17]

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

<8>
<8>

3

3G_PWR_ON#
<8> SUSCLK

2
R480

2
20P_0402_50V8
PC@

GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13

AD Input

DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

XCLKI/GPIO5D
XCLKO/GPIO5E

SA00004OB30

EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F

PS2 Interface

CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00

Int. K/B
Matrix

21
23
26
27

PKEY_LED#
BEEP#
USB_PWR_EN#
FAN_PWM

63
64
65
66
75
76

BATT_TEMP
3G_OFF#
ADP_I
AD_BID0
AUDIO_MUTE#
PM_SLP_LAN#

PKEY_LED#
<38>
BEEP# <33>
USB_PWR_EN#
<35,37>
FAN_PWM
<39>
C416 2

BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43

DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

1 100P_0402_50V8J

TP_CLK

R455

1

2

4.7K_0402_5%

TP_DATA

R457

1

2

4.7K_0402_5%

SPI Flash ROM

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

GPIO
Bus

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11

GPI

AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
V18R

AUDIO_MUTE#
PM_SLP_LAN#

EC_MUTE#
LAN_PWR_EN
WLAN_PME#
COMM_LED#
TP_CLK
TP_DATA

EC_MUTE#
<33>
LAN_PWR_EN
<31>
WLAN_PME#
<34>
COMM_LED#
<38>
TP_CLK <38>
TP_DATA <38>

97
98
99
109

VGATE_3V
USB_CHARGE_2A#
HDA_SDO
VCIN0_PH

VGATE_3V <8>
USB_CHARGE_2A#
HDA_SDO
<6>
VCIN0_PH
<43>

119
120
126
128

6511_3V_PWR_EN#
USB1_CHARGE_2A#
MUTE_LED#
CRT_SEL

100
101
102
103
104
105
106
107
108

PCH_RSMRST#
EC_LID_OUT#
VCIN1_PROCHOT
H_PROCHOT#_EC
MAINPWON
BKOFF#
PBTN_OUT#
PM_SLP_WLAN#
USB2_CEN

KB9012QF-A4_LQFP128_14X14
L41
NBQ100505T-800Y
2
ECAGND 1

2

2

@

2 10K_0402_5%

R462

BT_ON# <34>
SELCDP
<35,37>
DOCK_CRT_DET#
USB1_CEN
<37>

6511_3V_PWR_EN#
USB1_CHARGE_2A#
MUTE_LED#
<38>
CRT_SEL
<27>

0_0402_5%
<49>

2

VR_HOT#

@

1

H_PROCHOT#

<4>

<37>

H_PROCHOT#_EC
R487
1

CRT_SEL

2

10K_0402_5%

D

S

2
G

Latest design guide suggest change to
74LVC1G06.

Q31
2N7002E_SOT23-3

2

<35>

<26>
<37>

ENBKL

R472
R470
@ 100K_0402_5%

ENBKL <8>
DP_HPD
<26>
BI_DET <39>
BATT_BLUE_LED#
<38>
USB_CHARGE_CB0
<35,37>
PWR_LED#
<37,38>
BATT_AMB_LED#
<38>
SYSON
SYSON
<35,40,46>
USB2_CHARGE_2A#
<37>
PM_SLP_S4# <8>
PCH_RSMRST#
<8>
EC_LID_OUT#
<9>
VCIN1_PROCHOT
<43>
H_PROCHOT#_EC
<43>
MAINPWON
<45>
BKOFF# <25>
PBTN_OUT#
<8>
PM_SLP_WLAN#
<8>
USB2_CEN
<37>

EC_ON
<45>
ON/OFF#
<38>
LID_SW#
<38>
SUSP# <37,40,47,48>
VCCST_PWRGD
<11,47>
H_PECI
<4>

1

C418

EC_ACIN

R471

+EC_VCC

R526
100K_0402_5%

110
EC_ACIN
112
EC_ON
114
ON/OFF#
115
LID_SW#
116
SUSP#
117
VCCST_PWRGD
118 R634 1
2
43_0402_1%
124
+V18R
1

1

<33>
<8>

83
84
85
86
87
88

ENBKL
DP_HPD
BI_DET
BATT_BLUE_LED#
USB_CHARGE_CB0
PWR_LED#
BATT_AMB_LED#
SYSON
USB2_CHARGE_2A#
PM_SLP_S4#

R458

EC_MUTE#

3G_OFF#
<34>
ADP_I <43,44>

BT_ON#
SELCDP
DOCK_CRT_DET#
USB1_CEN

73
74
89
90
91
92
93
95
121
127

1

<43>

@

2 0_0402_5%

2

1 100P_0402_50V8J

ACIN

<19,44,8>

1

@

2 0_0402_5%

+3VLP

Pin 111 is a power source for HW operation of KB9012.
So, power plan will be different between KB930 and KB9012.

3

ON/OFF#
1

C421
0.1U_0402_16V4Z

2
PM_SLP_S5#

C422
4.7U_0603_6.3V6K
PBTN_OUT#

@

PAD T38

C436

2
PC@

20mil

1 100P_0402_50V8J

PM_SLP_S3#

Board ID
R479
100K_0402_5%

C437

2
PC@

Analog Board ID definition,
Please see page 3.

1 100P_0402_50V8J
4

AD_BID0

1

1

4

2 100K_0402_5%

ECAGND

+3VALW_EC

Ra

1

+3VS

BATT_TEMP

68
70
71
72

SPI Device Interface

GPIO

R453

+5VS

PWM Output

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

PC@ 1
100K_0402_5%
1

C423

122
123

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0LPC & MISC

LID_SW#

1

8
7
6
5

2 10K_0402_5%

3

RP4
1
2
3
4

1
2
3
4
5
7
8
10

1

1

<38> KB_BL_EN
<9> EC_KBRST#
<38,9> SERIRQ
<38,7> LPC_FRAME#
<38,7> LPC_AD3
<38,7> LPC_AD2
<38,7> LPC_AD1
<38,7> LPC_AD0

+3VALW_EC
+3VS

KB_BL_EN
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

R465

2

1

<43>
<43>

1

0.1U_0402_16V4Z

ECAGND
+EC_VCC

USB_CEN

2

1

U36

+3VALW
C414
0.1U_0402_16V4Z
ECAGND
+EC_VCC

67

2

EC_RST#

EC_VDD/AVCC

C415

1 47K_0402_5%

PC@

2

AGND/AGND

2

PC@

2

E

1

69

R459

2
0_0603_5%

2

+3VALW_EC
1

C411
0.1U_0402_16V4Z

1
R456

2

1

C410
0.1U_0402_16V4Z

2

1

C409
0.1U_0402_16V4Z

+3VLP

@EMI@

+3VALW_EC

1

9
22
33
96
111
125

2
0_0603_5%

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

@

C408
0.1U_0402_16V4Z

@EMI@
1
CLK_PCI_LPC
33_0402_5%

2
R454

GND/GND
GND/GND
GND/GND
GND/GND
GND0

1
R452

C407
22P_0402_50V8J
2
1

D

L40
NBQ100505T-800Y
1
2 +EC_VCCA

11
24
35
94
113

A

R483
20K_0402_1%

Rb

1

C424
0.1U_0402_16V4Z

2
2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/20

2013/07/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

EC ENE-KB9012

Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Sheet

Thursday, August 01, 2013

E

36

of

57

Rev
1.0

2

1

1

+3VS

2

R127
1M_0402_5% @

<31>
<31>
<31>
<31>

LAN_MIDI1+_DOCK
LAN_MIDI1-_DOCK

LAN_MIDI1+_DOCK
LAN_MIDI1-_DOCK

LAN_MIDI2+_DOCK
LAN_MIDI2-_DOCK

<31> LAN_MIDI2+_DOCK
<31> LAN_MIDI2-_DOCK

LAN_MIDI3+_DOCK
LAN_MIDI3-_DOCK

<31> LAN_MIDI3+_DOCK
<31> LAN_MIDI3-_DOCK

B

<33>
<33>

LINEIN_JD
MIC2_DOCK_DET
HP_DOCK_DET

<33> LINEIN_JD
MIC2_DOCK_DET
HP_DOCK_DET
<33> POP

<33>
<33>

LINE1_RIGHT
LINE1_LEFT

<33>
<33>

MIC2_DOCK_R
MIC2_DOCK_L

<33>
<33>

HP_DOCK_R
HP_DOCK_L

LINE1_RIGHT
LINE1_LEFT
MIC2_DOCK_R
MIC2_DOCK_L
HP_DOCK_R
HP_DOCK_L

+MIC2_VREFO

PCH_USB3_TX3_P
PCH_USB3_TX3_N

<10>
<10>

PCH_USB3_RX3_N
PCH_USB3_RX3_P
USB20_P2_L
USB20_N2_L

<10>

USB20_N2

USB20_N2

R628 1 EMI@

2 0_0402_5%
145
146
147
148

L38
2
3
A

<10>

USB20_P2

USB20_P2

2

1

3

4

1

USB20_N2_L

4

USB20_P2_L

153
154
155
156
157
158

@EMI@
SM070002J00
TAI-TECH LPF0805F2SF-900T04_0805
2 0_0402_5%
R629 1
EMI@

GND1
PWR1
PWR1
PWR1
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G

PWR2
PWR2
PWR2
GND2
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

SYS_IN#

2

DP_DOCK_CAD

1 R547
+3V_LAN width=10 mil
LAN_ACTIVITY#_DOCK
<31>
LAN_LINK#_DOCK
<31>
DP_DOCK_CAD
<28>
DP_DOCK_SEL
<28>
USB1_CEN
<36>
USB2_CEN
<36>
USB1_CHARGE_2A#
<36>
USB2_CHARGE_2A#
<36>
DOCK_CRT_DET#
<36>

LAN_ACTIVITY#_DOCK
LAN_LINK#_DOCK
DP_DOCK_SEL

CRT_DATA_DOCK
CRT_CLK_DOCK

CRT_DATA_DOCK
CRT_CLK_DOCK

RED_DOCK

RED_DOCK

BLUE_DOCK

HSYNC_DOCK
VSYNC_DOCK
HDMI_HPD_DOCK

<27>
<27>

<27>

BLUE_DOCK

GREEN_DOCK

R124
1M_0402_5%

B

<27>

GREEN_DOCK

<27>

HSYNC_DOCK
VSYNC_DOCK

<27>
<27>

HDMI_HPD_DOCK

<28>

HDMI_DOCK_D2+_R
HDMI_DOCK_D2-_R

R649 1 EMI@
R650 1 EMI@

2 0_0402_5%
2 0_0402_5%

HDMI_DOCK_D2+_C C290 2
HDMI_DOCK_D2-_C C291 2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

HDMI_DOCK_D2+
HDMI_DOCK_D2-

HDMI_DOCK_D1+_R
HDMI_DOCK_D1-_R

R651 1 EMI@
R652 1 EMI@

2 0_0402_5%
2 0_0402_5%

HDMI_DOCK_D1+_C C292 2
HDMI_DOCK_D1-_C C293 2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

HDMI_DOCK_D1+
HDMI_DOCK_D1-

HDMI_DOCK_D0+_R
HDMI_DOCK_D0-_R

R653 1 EMI@
R654 1 EMI@

2 0_0402_5%
2 0_0402_5%

HDMI_DOCK_D0+_C C295 2
HDMI_DOCK_D0-_C C294 2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

HDMI_DOCK_D0+
HDMI_DOCK_D0-

HDMI_DOCK_CK+_R
HDMI_DOCK_CK-_R

R655 1 EMI@
R656 1 EMI@

2 0_0402_5%
2 0_0402_5%

HDMI_DOCK_CK+_C C296 2
HDMI_DOCK_CK-_C C297 2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

HDMI_DOCK_CK+
HDMI_DOCK_CK-

HDMI2_DOCK_SDA
HDMI2_DOCK_SCL

<28>
<28>

HDMI2_DOCK_SDA
HDMI2_DOCK_SCL

ON/OFFBTN#
DET_SIG#
DOCK_SPOK#
USB_PWR_EN#
SUSP#
PWR_LED#

0_0402_5%

2

@

1 R546

<28>
<28>
<28>
<28>

HDMI_DOCK_D0+
HDMI_DOCK_D0-

<28>
<28>

HDMI_DOCK_CK+
HDMI_DOCK_CK-

<28>
<28>

ON/OFFBTN#
<38,8>
DET_SIG#_R
<31,9>

DET_SIG#_R

USB_PWR_EN#
<35,36>
SUSP# <36,40,47,48>
PWR_LED#
<36,38>
USB_CHARGE_CB0
<35,36>
SELCDP <35,36>

SUSP#

1

2

149
150
151
152

HDMI_DOCK_D2+
HDMI_DOCK_D2HDMI_DOCK_D1+
HDMI_DOCK_D1-

C814
1U_0402_6.3V6K

<10>
<10>

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

2

LAN_MIDI0+_DOCK
LAN_MIDI0-_DOCK

LAN_MIDI0+_DOCK
LAN_MIDI0-_DOCK

1K_0402_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

1

JDOCK3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

MB_VIN

159
160
161
162
163
164

A

JAE_WD2F144WB5R400
CONN@

SP0300013A0

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/20

Deciphered Date

2013/07/20

Title

E Series Dcok CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Size Document Number
Custom
Date:
1

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

37

of

57

Rev
1.0

B

TPM Board
<36>

+5VALW
CONN@
FOX_QT510166-L010-7H

<7>
<36,7>

LPC_FRAME#

LPC_FRAME#

<36,7>

2 10K_0402_5%
R633 1
@
<36,9>

LPCPD#_R
2 0_0402_5%
SERIRQ

SERIRQ

CLK_PCI_TPM
33_0402_5%

+3VS

LPC_AD0

LPC_AD0

+3VS
<8> LPCPD#

+3VALW

LPC_AD1

LPC_AD1

R512 1

ACES_50565-0260N-001_26P
CONN@

CLK_PCI_TPM

CLK_PCI_TPM

<36,7>

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

CLKRUN#
LPC_AD3
PLT_RST#
LPC_AD2

<8> CLKRUN#
<36,7> LPC_AD3
<34,36,38,8>
PLT_RST#
<36,7> LPC_AD2

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

CONN@
ACES_50504-0040N-001

3

1

Q23
AO3419L_SOT23-3

4
3
2
1

+5VS_BL

4
3
2
1

6
5

G2
G1

1

JBL1

KB_BL_EN#

<36>

JTPM1

1

+5VS

R511
100K_0402_5%

D

<36>

S

KSI[0..7]
KSO[0..17]

G

KSO[0..17]

KB Backlight Conn

2

KSI[0..7]

1

KB Conn.

28
27

E

KB_BL_EN

1

1

GND2
GND1
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

D

2

JKB1

C

D

3

A

S

2

Q24
2N7002E_SOT23-3

G

22P_0402_50V8J
2
1
C547

2
@EMI@ R591

(EMI request)

@EMI@

SP01001IE00
07/26 Modify.

+3VS

Lid Switch/B
(Hall Effect Switch)

TP Conn.

2

1
PC@

C480
0.1U_0402_16V4Z

2

2

+3VS
JTP1

4
3
2
1

JLID1

<36>

1
2
3
4

LID_SW#
+3VALW

1
2
3
4

G1
G2

<36>
<36>

5
6

TP_DATA
TP_CLK

+3VLP

G2
G1

6
5

ACES_50504-0040N-001
CONN@

ACES_50504-0040N-001
CONN@

SP01000Z300

SP01000Z300

07/26 Add

07/26 Modify

2

ON/OFF BTN

4
3
2
1

R513
100K_0402_5%

SW1
SMT1-05-A_4P

1

D28

2
3

ON/OFFBTN#

FP Board

1

Test Only

ON/OFF#

1

Function Board

+3VS

<36>

3
2

4
BAV70W_SOT323-3

6
5

3

+3VALW

JFP1
<10>
<10>

@

1
2
3
4

USB20_N7
USB20_P7

USB20_N7
USB20_P7

JFUN1

1
2
3
4

G1
G2

5
6

<36,37,38>
<36>
<36>
<36>
<36>
<36>

ACES_50504-0040N-001
CONN@
D22

3

CardReader Board
<6>
<6>
<7>
<7>

CLK_PCIE_CARD
CLK_PCIE_CARD#

CLK_PCIE_CARD
CLK_PCIE_CARD#

<6>
<6>

PCIE_PRX_DTX_P6
PCIE_PRX_DTX_N6

<7,9>
<34,36,38,8>
<36,37,38>
<36>
<36>
<36>
<6>

CARD_CLKREQ#
PLT_RST#
PWR_LED#
PWR_SUSP_LED#
BATT_BLUE_LED#
BATT_AMB_LED#
PCH_SATALED#

I/O4

GND

VDD

I/O1

I/O3

6

USB20_N7

PCIE_PRX_DTX_P6
PCIE_PRX_DTX_N6
CARD_CLKREQ#
PLT_RST#

+3VALW

BATT_AMB_LED#
+3VS

4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 G1
18 G2

2

USB20_P7

1

5

KSO0
KSI3
KSI4
KSI5
ON/OFFBTN#

<36> KSO0
<36> KSI3
<36> KSI4
<36> KSI5
<37,8> ON/OFFBTN#

JREAD1
PCIE_PTX_C_DRX_P6
PCIE_PTX_C_DRX_N6

PCIE_PTX_C_DRX_P6
PCIE_PTX_C_DRX_N6

@ESD@

I/O2

PWR_LED#
MUTE_LED#
PKEY_LED#
COMM_LED#
NUM_LED#
CAP_LED#

PWR_LED#
MUTE_LED#
PKEY_LED#
COMM_LED#
NUM_LED#
CAP_LED#

+3VS

4

AZC099-04S.R7G_SOT23-6

19
20

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

C820
C821
C822
C823
C824
C825

1
1
1
1
1
1

2
2
2
2
2
2

ESD@
ESD@
ESD@
ESD@
ESD@
ESD@

PWR_LED#
MUTE_LED#
PKEY_LED#
COMM_LED#
NUM_LED#
CAP_LED#

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

C826
C827
C828
C829
C830

1
1
1
1
1

2
2
2
2
2

@
@
@
@
ESD@

KSO0
KSI3
KSI4
KSI5
ON/OFFBTN#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

3

GND
GND

ACES_51524-0160N-001
CONN@

SP01001C600
07/26 Add

4

ACES_50505-0184N-001
CONN@
BATT_AMB_LED#

1

2

C831
0.1U_0402_16V4Z
ESD@

Security Classification

Compal Electronics, Inc.

Compal Secret Data
2012/07/20

Issued Date

Deciphered Date

2013/07/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

KB/TP/LID/TPM/FUN/FP/CARD
Size
Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Thursday, August 01, 2013

Sheet

E

38

of

57

Rev
1.0

FAN Conn

3G Stand off

WIFI Stand off

H5
H_3P8

1

H4
H_3P8

1

+VCC_FAN1
R514

H3
H_3P3

1

1

@

H2
H_3P3

1

2
0_0603_5%

H1
H_3P3

C481
10U_0805_10V4Z
1
2

20mil

FAN Stand off

1

+5VS

SSD Stand off

@

@

@

@

@

+3VS

H9
H_2P5

H10
H_2P5

H11
H_2P5

H12
H_2P5

H15
H_3P0

H16
H_2P5

H17
H_2P5

1

1

1

1

1

@

@

@

@

H20
H_3P8

H21
H_3P8

H22
H_3P8

H23
H_4P0

H24
H_4P0

@

@

@

@

@

@

H26
H_3P5X3P0N

1

@

H25
H_5P0X3P0N

1

1

1

@

1

SP02000K200

H19
H_3P0N

@

1

H18
H_3P0N

1

FAN_PWM

@

1

<36>

@

1

+VCC_FAN1
FAN_SPEED1
FAN_PWM

FAN_SPEED1

1

<36>

CONN@
ACES_88266-04001_4P
4
6
3 4 G2 5
2 3 G1
1 2
1
JFAN1

1

2

R515
10K_0402_5%

1

1

H8
H_2P5

@

@

locate MB
3

BI_DET

DU2
BAV70W_SOT323-3

<36>

2

2

Debug SW

EC_RST#
R415
10K_0402_5%

6

2
<36>

+3VLP

1

+3VLP

+RTCVCC

1

R544
510K_0402_5%

DMN66D0LDW-7_SOT363-6
Q52A

1

2

SW2

0.1U_0402_16V4Z
C370

FD1

2

BI_SW
CLP1

R527
1M_0402_5%

CLP2

@

H28
2
1
2
CLIP_SHAPE8P5BC7P0-1
EC063000700
EMIST_SQ-21G_1P
CONN@

1

C369
1
0.1U_0402_16V4Z

2
SKPMAME010_2P

1

EC063000700
EMIST_SQ-21G_1P
CONN@

On H8

Issued Date

2012/07/20

Deciphered Date

@

FIDUCIAL_C40M80

FD3

FD4
@

FIDUCIAL_C40M80

@

FIDUCIAL_C40M80

Compal Electronics, Inc.

Compal Secret Data

Security Classification

@

FIDUCIAL_C40M80

1

SN200002800

FD2

2
1

S

1

1

Power ON

Q52B
DMN66D0LDW-7_SOT363-6

4

1

5

Q22
2N7002E_SOT23-3
2
G

D

5
4

3

1

Power Off

1

4

BI

1

5

<43>

6

1

R525
1K_0402_5%

3

9
G

1
G

1

2

8

BI_SW

6

G

2
@

3

SW3
MSS6-Q-T-R_6P

7

3

G

10

2

2

2013/07/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

FAN & Screw
V4DA2 M/B LA-A131P Schematic

Size
Document Number
Custom
Date:

Monday, August 05, 2013

Sheet

39

of

57

Rev
1.0

A

B

C

D

E

2

+5VALW

GND

2

2

@

3

2

0.1U_0402_16V4Z
R601 1
0_0402_5%
C789

2

NOVPRO@

1

C810
VPRO@
1 4.7U_0603_6.3V6K

VIN
EN

R635 1
0_0402_5%

+5VALW
5VS_ON

2
0.1U_0402_16V4Z

<46,8>

+5VALW

4
5
6
7

ON1

CT1

VBIAS

GND

ON2

CT2

VIN2
VIN2

VOUT2
VOUT2

@

GPAD

C786

12

1

2

2

+3VS

JUMP_43X118

2

1 330P_0402_50V7K

2

1

SUSP

1

11
10

2N7002E_SOT23-3
Q44
330P_0402_50V7K
C788

9
8

<36,37,47,48>

@ J12

1

15

1

2

2

S@

G

R603
10K_0402_5%
@

JUMP_43X118

D

2

SUSP#

+5VS

TPS22966DPUR_SON14_2X3

AP2821KTR-G1_SOT23-5

2

3

3VS_ON

1

1

2

1

VIN

1

C817
1U_0402_10V6K

1

VPRO@

VOUT

4

47K_0402_5%
2 R600
1
C787

SUSP#

14
13

3

U56

5

+3VS
+3VM

VOUT1
VOUT1

1

20mil(68mA)

+3VALW

R598
100K_0402_5%
@

@ J11

VIN1
VIN1

2

1

1
2

+3VALW

1

U48

+3VALW to +3VM for Intel AMT

PM_SLP_A#

+1.05VM

+1.05VS_VTT

1

R636 2 0_0603_5%
NOVPRO@

2

2

2

+1.05VS_VTT

1

+0.675VS

R604
470_0603_5%
@

3

1

R605
470_0603_5%
@

2

+3VS to +3VSDGPU for GPU

+1.05VS_VTT_R

3

1

1

+0.675VS_R
D
+3VSDGPU

1

1

2

C818
1U_0402_10V6K
@

VIN

1 4.7U_0603_6.3V6K

3

EN

+1.35V

AP2821KTR-G1_SOT23-5

+5VALW

1

R610
100K_0402_5%
@
SYSON#

IN2

VCC
3

C63
0.1U_0402_16V7K

VGA@ 1

4

OUT

3

6

4

VGA_ON_R

2

<52>

Q49A
DMN66D0LDW-7_SOT363-6
@

SYSON#

4

2

VGA@

1

2

IN1

GND

U55

1

VGA_ON

5

+1.35V_R

R631 1 VGA@
20K_0402_1%

5
SYSON
Q49B
DMN66D0LDW-7_SOT363-6
@

SYSON

<35,36,46>

4

MC74VHC1G08DFT2G_SC70-5

2

Security Classification

Compal Electronics, Inc.

Compal Secret Data
2012/07/10

Issued Date

Deciphered Date

2013/07/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

@

C796
VGA@

VIN

+3VS

+3VSDGPU

SUSP

G
S

R609
470_0603_5%
@

<9>

2

Q46
2N7002E_SOT23-3

2

2

GND

SUSP

G
S @

2

2

VOUT

2

Q45
2N7002E_SOT23-3

100mil(1.5A)

1

4
C797
4.7U_0603_6.3V6K
VGA@

1

2

5

VGA@

3

U50

3

+3VS

D

B

C

D

Title

DC Interface
Size
Document Number
Custom

Rev
1.0

V4DA2 M/B LA-A131P Schematic

Date:

Tuesday, July 30, 2013

Sheet
E

40

of

57

5

4

3

2

1

Power-Up/Down Sequence
1. All the ASIC supplies must reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter
ramp-up duration is preferred.
2. VDD_CT must remain powered whenever VDDR3 is powered.
3. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and VDD_CT have ramped up.
4.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to ramp-up (or vice versa).
D

5.BIF_VDDC should always be tied to PCIE_VDDC.

D

Power Sequence of Mars
From PCH GPIO65

VGA_ON

+VGA_CORE(VDDC/VDDCI)
+0.95VSDGPU(PCIE_VDDC)

←
←

←
←
←

+3VSDGPU

1.8ms

1.6ms

←

7.84ms

+1.5VSDGPU(VDDR1)

←

←

+1.8VSDGPU(VDD_CT)

3.4ms

←

←

PLTRST_VGA#

106ms

C

C

+3VS
U50
VGA_ON

U55
+3VSDGPU

APL3512ABI-TRG
SOT23-5

PU1101

MC74VHC1G08DFT2G
SC70-5

+VGA_CORE
VGA_ON_R

ISL62883CHRTZ-T
_TQFN40_5X5

VGA_PG

PU1001
B

B

VGA_PG

SY8206DQNC
QFN10_3X3

+0.95VSDGPUP

PU701
VGA_PG

SY8208DQNC
QFN10_3X3

+1.5VSDGPU

PU603
VGA_PG
A

APL5930KAI-TRG
SO8

+1.8VSDGPU
A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/07/20

2013/07/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Mars_M2 Block Diagram
Size Document Number
Custom
Date:

V4DA2 M/B LA-A131P Schematic
Tuesday, July 30, 2013

Sheet

1

41

of

57

Rev
1.0

A

B

C

D

VIN

PD101
PDS1040-13_POWERDI5-3

2
1

MB_VIN
PL101
EMI@
FBMA-L11-322513-151LMA50T_1210

1

DC_IN_S1

2

2

1

DC_IN_S2

3

ACES_87302-0401-003
PJP101

1

PD102
PDS1040-13_POWERDI5-3

2

@

1

6
5
4
3
2
1

PC101
1000P_0603_50V7K
EMI@

2

GND
GND
4
3
2
1

1

1

3

PC104
1000P_0603_50V7K
EMI@

EMI

2

2

BOM Config
UMA EMI@

DDR3L
DIS EMI@/VGA@/VGAEMI@

3

3

+3VLP
Rshort@
PR101

1

+CHGRTC

PBJ101

2
0_0402_5%

@

PR102
560_0603_5%

2

1

1

PR103
560_0603_5%

2

1

2

+RTCBATT

ML1220T13RE

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/06/19

Deciphered Date

2012/07/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

DCIN
Size
Document Number
Custom
Date:

A

B

C

Rev
1.0

V4DA2 LAA131P Schematic

Thursday, August 01, 2013
D

Sheet

42

of

56

A

B

C

D

ACES_50290-0100N

1

1

PR202
100_0402_1%

PR203
100_0402_1%

2
1

BATT+

2

PC201
EMI@
1000P_0402_50V7K

2

1

1

<40,41>

EC_SMB_DA1

<26,33>

EC_SMB_CK1

<26,33>

BATT_TEMP

<26,33>

2

PL201
EMI@
FBMA-L11-322513-151LMA50T_1210
BATT_S1

2

1

<40,41>
VMB

1

PJP201
@

EC_SMDA
EC_SMCA
TH
BI+

PC203
EMI@
0.01U_0402_25V7K

2

1

10
9
8
7
6
5
4
3
2
1

PR201
1K_0402_5%
PR211
6.49K_0402_1%

2

1

+3VLP

1

EMI

2

PR212
1K_0402_1%

BI
<26,33>

2

ENE9012

Action 70W
(throttling)

Recovery 54W

ADP_I

1.466V

1.131V

VCIN1
(EC setting)

1.2V

1.025V

2

CPU thermal protection at 92 degree C
PH203 under CPU botten side :
(92 degree = 6.99K ohm) => VCIN0_PH = 1.2V
(56 degree = 26.02k ohm) => VCIN0_PH = 2.22V
(70W/19V)*19.9*20m =1.466V
1.466*10/12.21=1.2V

+EC_VCC

ADP_I <26,33>

1

<26,33>

3

1

PR214
12.7K_0402_1%

PR217
2.21K_0402_1%

2

2

3

<26,33>

VCIN1_PROCHOT
<26,33>

VCIN0_PH
PR206
60.4K_0402_1%

H_PROCHOT#_EC
<26,33>

2

1

1

For 65W adapter==>action 70W , Recovery 54W
4

2
2

此電容要靠EC pin

PH203
100K_0402_1%_NCP15WF104F03RC

@ PC207
1000P_0402_50V7K

2

1

1

PR223
12K_0402_1%

4

ECAGND

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/06/19

Deciphered Date

2012/07/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

BATTERY CONN / OTP
Size
Document Number
Custom
Date:

A

B

C

<26,33>

Rev
1.0

V4DA2 LAA131P Schematic

Thursday, August 01, 2013
D

Sheet

43

of

56

A

B

C

D

PQ301

1

Protection for reverse input

2

3

G

Vgs = 20V
Vds = 60V
Id = 250mA

B+

S 2N7002KW_SOT323-3

PR302
1
2
3M_0402_5%

1

Rds(on) = 35mohm max
Vgs = 20V
Vds = 30V
ID = 7.7A (Ta=70C)

VIN

BATDRV

10

9

7

8

PC322
0.01U_0402_25V7K

1
2

1

PR319
100K_0402_1%

2

2
PR317
316K_0402_1%

EC_SMB_CK1

<26,32>

EC_SMB_DA1

<26,32>

ADP_I

<26,32>

1

Rshort@ PR321
0_0402_5%
1
2

1

4

Max.
18.12V
17.70V

PC325 @
100P_0402_50V8J

2

Typ
17.63V
17.22V

Close EC chip

2

BATT+

1

PC315
10U_0805_25V6K

2

1
2

PC314
10U_0805_25V6K

@EMI@ PC318
0.1U_0402_25V6

1
2

1
CSON1
1
2

PC317
0.1U_0402_25V6

CSOP1
1

PC316
0.1U_0402_25V6

2

1

PR313
4.7_1206_5%

2
1

3

@EMI@

PC320
0.1U_0603_16V7K

+3VLP

@EMI@
PC321
680P_0402_50V7K

BQ24725A_BATDRV

BQ24735RGRR_QFN20_3P5X3P5

Vin Dectector
Min.
17.16V
16.76V

PQ305
AON7408L_DFN8-5
3
2
1
5

11

13

BQ24725A_ILIM
BQ24725A_IOUT

BQ24725A_ACDET
PC324
100P_0402_50V8J
2
1

PR320
66.5K_0402_1%
1

PC323
2200P_0402_50V7K

2

VIN

BQ24735A_V2.mdd

1

BQ24735A_V1.mdd

2

1
2

12

PR314
10_0603_1%
2 CSOP1
SRP1
PR315
6.8_0603_1%
2 CSON1
SRN1

2

SRN

4

DL_CHG

14
3
2
1

ACDRV

PR318
422K_0402_1%
1
2

2

1

SRP

Support max charge 3.5A
Power loss: 0.245W
CSR rating: 1W
VSRP-VSRN spec < 81.28mV

PL302
PR312
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20% 0.01_1206_1%
1
2
4
BQ24725A_LX
CHG 1

2

CMSRC

15

2 BQ24725A_BATDRV_1

PR306
4.12K_0603_1%

PQ306
AON7408L_DFN8-5

16

1 1

GND

Module model information

L-->H
H-->L

@EMI@ PC305
0.1U_0402_25V6

1

2

PC313
1U_0603_25V6K

LODRV

1

5

1
2
BQ24725A_REGN

1

REGN

PR310
2.2_0603_5%
1
BQ24725A_BST 2
BTST

DH_CHG
18

17

HIDRV

BQ24725A_LX
19
PHASE

4

0_0402_5%

ACP

ACOK

2

ACIN

2

3

PR309
10_1206_1%

ACN

6

<26,33>

PR316

Rshort@
PR311
1

DH_CHG

ILIM

+3VLP

5

PD302
RB751V-40_SOD323-2

SCL

BQ24725A_ACDRV 4
2
BQ24725A_ACOK
100K_0402_1%

PQ304
AON6414AL_DFN8-5

BQ24725A_BATDRV

VF = 0.37V

1
2
3

5

Rds(on) = 30mohm max
Vgs = 20V
Vds = 30V
ID = 7A (Ta=70C)

PC310
0.047U_0402_25V7K
1
2

SDA

BQ24725A_CMSRC 3

PAD

IOUT

2

20

PU301

VCC

2

2

1U_0603_25V6K

1

1

BQ24725A_VCC2

1

1

PC312
1
2

21

VF = 0.5V
PD301
BAS40CW_SOT323-3

ACDET

1

PR308
4.12K_0603_1%

2

1

2

BQ24725A_ACN

2

1

PC307
0.1U_0402_25V6

BQ24725A_ACP

2

PR307
4.12K_0603_1%

PC311
0.1U_0402_25V6

BQ24725A_ACDRV_1

2

3

2

VIN

2

1

PQ303
AON6414AL_DFN8-5

@EMI@ PC306
2200P_0402_25V7K

Isat: 4A
DCR: 27mohm

1

3

PC304
10U_0805_25V6K

2

CHG_B+
EMI@ PL301
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2

2

4

4

1

PC309
0.1U_0402_25V6

1
2

PR303
0.02_1206_1%

5

PC302
0.1U_0402_25V6

1

@ PR304
0_0402_5%

4

PQ302
AON6414AL_DFN8-5

2

1
2

PC301
2200P_0402_50V7K

P2
1
2
3

PC303
10U_0805_25V6K

P1
1
2
3

5

PC308
0.01U_0402_50V7K

max Power loss 0.22W for 90W;0.12W for 65W system
CSR rating: 1W
VACP-VACN spec < 80.64mV

Need check the SOA for inrush

4

PR301
1
2
1M_0402_5%

1

D

**Design Notes**
#For 65 /90W system, 3S1P/3S2P battery
Maximum Charging current 3.5A
Battery discharge power 55W.
#Register Setting
1. 0X12 bit8 set 0 (default 1) to disable IFAULT HI if add ISN choke
2. 0X12 bit3 set 1 (default 0) to enable turbo boost function
3. Disable turbo when AC only
#Circuit Design
1. ACOK,ILIM pull high voltage need base on 3/5V enable control
2. Use 10X10 choke and 3X3 H/L side MOSFET
Charge current 3.5A
Power loss : 1.82W
Power density : 0.81 (15X15)
3. If use 4S per cell 4.35V battery, need additional circuit
for ACDET(PR218/PR220/PR222 change to 0.1%, parallel resistors
with PR222 for ACDET setting)
4. PC223 2200p is for quick response when AC plug out.
5. For hybrid design, need double check PQ202,PQ203,PQ204,PQ205 component rating
#Protect function
1. ACOVP : ACDET voltage > 3.14V
2. Charger timeout : No communication within 175s(default)
3. ACOC : 3.33 X Input current DAC setting(default)
4. CHGOCP : 3/4.5/6A based on current current setting
5. BATOVP : 103-106%
6. BATLOWV : 2.5V
7. TSHUT : 155C
8. IFAULT HI : 750mV (default)
9. IFAULT LOW : 110mV (default)

3

4

VILIM = 20*ILIM*Rsr
ILIM = 3.3*100/(100+107)/20/0.02
= 3.986 A

Compal Secret Data

Security Classification
Issued Date

2012/06/19

Deciphered Date

2012/07/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Size
Document Number
Custom

B

C

Rev
1.0

V4DA2 LAA131P Schematic

Date:
A

Compal Electronics, Inc.
CHARGER
Thursday, August 01, 2013
D

Sheet

44

of

56

5

4

3

SY8208B_V1.mdd
EN1 and EN2 dont't floating

8
PC405
10U_0805_25V6K
2
1

IN

EN1

IN

EN2
BS

1

3V5V_EN

PC425
0.01U_0402_25V7K
1
2

3
6

Rshort@ PR401
1
BST_3V

2

0_0603_5%

1

0.1U_0603_25V7K

@

PL402

PR405
4.3K_0402_5%
1
2

+3VLP

+3VALW

PC409
22U_0805_6.3VAM

2

3.3V LDO 150mA~300mA

PC408
22U_0805_6.3VAM
2
1

+3VLP
PC410
4.7U_0603_6.3V6M

PC407
22U_0805_6.3VAM
2
1

5

1

LDO

+3VALWP

2

PG

SY8208BQNC_QFN10_3X3

2

1.5UH_PCMB053T-1R5MS_6A_20%
PC406
22U_0805_6.3VAM
2
1

OUT

4

4.7_1206_5%

PR413
100K_0402_5%

1
2

GND

1

LX_3V

680P_0603_50V7K

9

10

@EMI@ PC411
@EMI@ PR404
2
13V_SN 2
1

LX

2

Check pull up resistor of SPOK at HW side

D

PR411
1K_0402_1%
1
2

PC403
2

1

@EMI@ PC401
0.1U_0402_25V6
2
1

PC404
10U_0805_25V6K
2
1

3V_VIN

<42> SPOK

C

B+

PU401
7

EMI@ PL401
HCB2012KF-121T50_0805
1
2
EMI@ PC402
2200P_0402_50V7K
2
1

B+

D

1

PR403
150K_0402_1%
2
1

ENLDO_3V5V

Module model information

2

PR402
499K_0402_1%
1
2

Vout is 3.234V~3.366V
TDC=8A

PR406
2.2K_0402_5%
1
2

<42>EC_ON

+3VALWP

@
1

PJ401
1

2

2

+3VALW

C

JUMP_43X118
Rshort@ PR407
1
2

<42> MAINPWON

0_0402_5%

B+

EMI@ PL403
HCB2012KF-121T50_0805
1
2

PC412
4.7U_0402_6.3V6M

1
2

2

1
PR408
1M_0402_1%

3V5V_EN

EN1 and EN2 dont't floating

5V_VIN

@EMI@ PC416
0.1U_0402_25V6
2
1

8

IN

EN1
EN2
BS

1

3V5V_EN

PC426
6800P_0402_25V7K
1
2

3
6

Rshort@ PR409
BST_5V 1

TDC=8A

PR412
1K_0402_1%
1
2

B

2

0_0603_5%

1

2
PC417
0.1U_0603_25V7K
PL404

5V LDO 150mA~300mA

PC422
22U_0805_6.3VAM

PC421
22U_0805_6.3VAM
2
1

PC420
22U_0805_6.3VAM
2
1

VL

1

7

2

LDO

+5VALWP
PC419
22U_0805_6.3VAM
2
1

PG

SY8208CQNC_QFN10_3X3

2

1.5UH_PCMB053T-1R5MS_6A_20%
4.7_1206_5%

OUT

1

LX_5V

4

PC424
PR410
2
15V_SN 2
1

VCC

10

+5VALWP

@
1

PJ402
1

2

2

+5VALW

JUMP_43X118

680P_0603_50V7K

LX

1

2
PC418
4.7U_0603_6.3V6M

2

1

VCC_3.3V 5

GND

PC423
4.7U_0603_6.3V6M

9

2

@

EMI@ PC415
2200P_0402_50V7K
2
1

PC414
10U_0805_25V6K
2
1

B

PC413
10U_0805_25V6K
2
1

Vout is 4.998V~5.202V
PU402

Module model information
A

A

SY8208C_V1.mdd
Security Classification

Compal Secret Data
2012/06/19

Issued Date

2012/07/31

Deciphered Date

Title

Compal Electronics, Inc.
3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Thursday, August 01, 2013
Date:

Rev
1.0

V4DA2 LAA131P Schematic

5

4

3

2

Sheet
1

45

of

56

A

C

2

BOOT_1.35V

2

1

PC507
10U_0805_6.3V6K

2

1

18

20
VTT

VLDOIN

PC511
0.033U_0402_16V7K

2

S3

FB

+1.35VP

PR506
8.2K_0402_1%

+1.35VP

2

Choke: 7x7x3
Rdc=8.3mohm(Typ), 10mohm(Max)

PR508
10K_0402_1%

2

2

@

1
Rshort@ PR510
0_0402_5%

1

<42>DDR_VTT_PG_CTRL

@ PC515
0.1U_0402_10V7K

PJ531

Lo

Hi

On

On

S4/S5

Lo

Lo

<26,33>

1

2

4
1

2

5

100K_0402_5%
PR531 Vpro@
Vpro@ PC624
.1U_0402_16V7K

IN

LX

PG

GND

FB

EN

6

Vpro@
PU531
SY8032ABC_SOT23-6

3

+1.05VMP

2
1
@EMI@ PR532
4.7_0603_5%

Vpro@ PR533
7.87K_0402_1%

2
2

Rup
FB_1.05VMP

2

@EMI@ PC536
680P_0402_50V7K

Vpro@ PR536
10K_0402_1%

Rdown
2

2

1
2

2

@Vpro@
PC535
0.1U_0402_16V7K

Vpro@ PR535
1M_0402_1%

1

+1.05VMP_ON

1

0_0402_5%

1

Rshort@
PR534

1

+1.05VM

3

Vpro@
PL531
1UH_PH041H-1R0MS_3.8A_20%
1
2
LX_1.05VMP

Note: S3 - sleep ; S5 - power off

<42> PM_SLP_A#

2

Imax= 2A, Ipeak= 3A
FB=0.6V

2

PM_APWROK

+3VALW

Off
Off
Off
(Discharge) (Discharge) (Discharge)

1

1

S3

On
Off
(Hi-Z)

2

On

@

2

Vpro@ PC534
22U_0805_6.3VAM

On

2

JUMP_43X79

1

Hi

1

JUMP_43X79

2

Hi

1

Vpro@ PC533
22U_0805_6.3VAM

S0

+0.675VS

1

@
PJ532

+3VALW

2

2

+1.05VMP

Vpro@
PC532
68P_0402_50V8J

1

0.675VSP

1

JUMP_43X39

1

VTT_REFP

2

2

PJ503

1

+0.675VSP

1

1.35VP

1

@

1

S5

+1.35V

2

2

S3

2

2

JUMP_43X118

Vpro - 1.05VM

3

1

JUMP_43X118
@
PJ502

Vpro@ PC531
22U_0805_6.3VAM

STATE

PJ501

1

+1.35VP

2

@ PC514
0.1U_0402_10V7K

Switching Frequency: 285kHz
Ipeak=10A
Iocp~13A
OVP: 110%~120%
VFB=0.75V, Vout=1.355V
MOSFET footprint: SIS412DN

Note: S3 - sleep ; S5 - power off

2

1

1

2

VTTREF_1.35V
off
on
on

VTTREF_1.35V

1

+0.675VSP
off
off
on

1

<42> SYSON

2

Level
L
L
H

2

4
5

Rshort@ PR509
0_0402_5%

L/S Rds(on): 9.9mohm(Typ), 13mohm(Max)
Idsm: 13.5A@Ta=25C, 11A@Ta=70C
Mode
S5
S3
S0

1

1.35V_B+

3

FB_1.35V

PR507
887K_0402_1%

MOSFET: 3x3 DFN
H/S Rds(on): 27mohm(Typ), 34mohm(Max)
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C

2

1

2

21
1

6

+5VALW

S5

PC512
1U_0603_10V6K

VDDQ

7

VDD

8

+5VALW

10

4

VTTREF

1

PQ502
AON7506_DFN8-5

BOOT

VDDP

11

GND

RT8207MZQW_WQFN20_3X3

1
2
3

2

12

VDD_1.35V

2

@EMI@ PC513
680P_0402_50V7K

2

VTTSNS

EN_1.35V

5
1 2

+

2

PR504
5.1_0603_5%

1

2

PC509
330U_2.5V_M

ESR=17m ohm

1

CS

PAD

VTTGND

PGND

EN_0.675VSP

2

UGATE

13

LGATE

TON

1
2
3

1

19

16
CS_1.35V
PC508
1U_0603_10V6K

PHASE

15

PGOOD

DL_1.35V

PR502
13.7K_0402_1%

2

@EMI@ PR503
4.7_1206_5%

1

17

1

1
2

5

4

PU501

PC506
10U_0805_6.3V6K

1

1

+1.35VP

+0.675VSP

SW_1.35V
PC505
0.1U_0603_25V7K

14
PL502
1UH_VMPI0703AR-1R0M-Z01_11A_20%

+1.35VP

DH_1.35V

9

1
2

PC504
10U_0805_25V6K

1
2

1

BST_1.35V

PQ501
AON7408L_DFN8-5

1

0.75Volt +/- 5%
TDC 0.7A
Peak Current 1A

PR501
2.2_0603_5%
PC503
10U_0805_25V6K

1
2

EMI@ PC502
2200P_0402_50V7K

1
2

1
2
1

1.35V_B+

TON_1.35V

2
@EMI@ PC501
0.1U_0402_25V6

1

D

Pin19 need pull separate from +1.5VP.
If you have +1.5V and +0.75V sequence question,
you can change from +1.5VP to +1.5VS.

EMI@ PL501
HCB2012KF-121T50_0805

@EMI@ PC510
22U_0805_25V6M

B+

B

4

4

Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage
Compal Secret Data

Security Classification
Issued Date

Vout=0.6V* (1+Rup/Rdown)
Vout=1.0722

2012/06/19

Deciphered Date

2012/07/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

1.35VP/0.675VSP
Size
Document Number
Custom
Date:

A

B

C

Rev
1.0

V4DA2 LAA131P Schematic

Thursday, August 01, 2013
D

Sheet

46

of

56

5

4

3

2

1

EN pin don't floating
If have pull down resistor at HW side, pls delete PR2
Rshort@
PR631

@ PC631
0.22U_0402_10V6K

D

2

1M_0402_1%
PR632

1

D

SUSP# <27>

2

0_0402_5%

2

1

1

PR633
PC632
4.7_1206_5%
680P_0603_50V7K
1
2SNB_1.05V 1
2

EMI@ PL601
HCB2012KF-121T50_0805
1
2

2

1
2

PC642
22U_0805_6.3VAM

1
2

1
2

1
2

PC641
22U_0805_6.3VAM

2

FB = 0.6V

PC640
47U_0805_6.3V6M

LDO

SY8208DQNC_QFN10_3X3

+3VALW

PC639
47U_0805_6.3V6M

PG

LDO_1.05V

1

PR639
10K_0402_5%

Rup

7
5

1

2

VCCST_PWRGD

PC610
4.7U_0603_6.3V6K

2

2

1

BYP

1

FB
ILMT

+1.05VS_VTT

@

+1.05VSP
1

0_0603_5%

PJ601
2
2

1

JUMP_43X118

PL602
1UH_VMPI0703AR-1R0M-Z01_11A_20%
1
2

4

2

C

TDC 8A

2

10 LX_1.05V

2

PC633
0.1U_0603_25V7K
1
2

PC638
330P_0402_50V7K

LX

6

Rshort@ PR634
BST_1.05V 1

1

GND

1

PC609
4.7U_0603_6.3V6K

1

PR637
0_0402_5%
Rshort@

EN

PR636
15.4K_0402_1%

10U_0805_25V6K
PC637
2
1

10U_0805_25V6K
PC636
2
1

9

ILMT_1.05V 3

+3VS

ILMT_1.05V

+1.05VSP
1

IN

BS

2

PR635 @
0_0402_5%

@EMI@ PC635
0.1U_0402_25V6
2
1

1

LDO_1.05V

8

B+_1.05V

EMI@ PC634
2200P_0402_50V7K
2
1

B+

PU601

PR638
C

Rdown

20K_0402_1%
2

36,46
VCCST_PWRGD

Pin 7 BYP is for CS.
Common NB can delete

The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high

+3VALW and PC15

VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=1.062V

+3VS

1

1

2

2

+1.8VS_6511

B

VGA@ PC615
1U_0402_6.3V6K

2

1

1

2

2

@

+1.8VSP

JUMP_43X79
PJ604
@

PJ605

PJ606

@
1

+1.8VS_DIS

2

1

PC614
1U_0402_6.3V6K

2

JUMP_43X79
PJ603
@

2

1

B

+5VALW

1

+5VALW

1

+3VS

+1.8VS_DIS

1

1

VGA@ PC619
0.01U_0402_25V7K

VGA@ PC623
22U_0805_6.3VAM

2

2

1

1

2

GND

1

2

2
4

+1.8VSDGPU

Vout=0.8V* (1+Rup/Rdown)
Vout=1.839
Ultra Low Dropout 0.23V(typical) at 3A Output Current
Issued Date

3

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/06/19

2012/07/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

2

VGA@ PR618
1.74K_0402_1%

Rdown

A

Vout=0.8V* (1+Rup/Rdown)
Vout=1.839
Ultra Low Dropout 0.23V(typical) at 3A Output Current

2

1

2
1

PR617
1.74K_0402_1%

Rdown

Rup

VGA@ PR614
2.26K_0402_1%

1
2

@VGA@ PR616
47K_0402_5%

2

PC620
22U_0805_6.3VAM

2

1

2
0_0402_5%

PU603
VGA@
APL5930KAI-TRG_SO8
6
5 VCNTL
3
VOUT 4
9 VIN
VIN
VOUT
8
7 EN
2
POK
FB

@VGA@ PC622
0.1U_0402_16V7K

1
2

Rshort@
PR612
1

PC618
0.01U_0402_25V7K

@

2

VGA_PG
<42>

1

+1.8VSP
PR611
2.26K_0402_1%

2

Rup

1

1
2

@ PR615
47K_0402_5%

PC621
0.1U_0402_16V7K

0_0402_5%

VGA@ PC617
4.7U_0805_6.3V6K

GND

2

PU602
APL5930KAI-TRG_SO8
6
5 VCNTL
3
VOUT 4
9 VIN
VIN
VOUT
8
7 EN
2
POK
FB

1

JUMP_43X79

1

Rshort@
PR609
1

1

6511_PWR_EN
<42>

2

PC616
4.7U_0805_6.3V6K

1

JUMP_43X79

2

Title

1.05VS_VTT/1.8VS_6511/1.8VS_DIS
Size
Document Number
Custom
Date:

Rev
1.0

V4DA2 LAA131P Schematic

Thursday, August 01, 2013

Sheet
1

47

of

56

5

4

3

2

EN pin don't floating
If have pull down resistor at HW side, pls delete PR2

Module model information
SY8208D_V1.mdd

Rshort@
PR701

The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high

1

1

1

1M_0402_1%

2

D

1

VGA@

VGA_PG <42>

D

@VGA@ PC701
0.22U_0402_10V6K

2

PR702

2

0_0402_5%

+1.5VS_DIS

@

1

LDO_1.5V_DIS

SY8208DQNC_QFN10_3X3

2

2

@VGA@
PR706
0_0402_5%

FB = 0.6V

PR709
VGA@
10K_0402_1%

Rdown

1
PR708
0_0402_5%
Rshort@

2

Pin 7 BYP is for CS.
Common NB can delete

1
2

2

+3VALW and PC15

+5VALW

PC715
1U_0402_6.3V6K
@
1

+1.5VSP

2

B

2

JUMP_43X79
@ PJ702

2

1

1

1

+3VS

C

VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=1.522V

2

ILMT_1.5V_DIS

+3VALW

VGA@ PC712
22U_0805_6.3VAM

5

2

LDO

+1.5VS_DIS

1

PG

7
1

BYP

2

ILMT

VGA@ PC714
4.7U_0603_6.3V6K

1

2

Rup

1

ILMT_1.5V_DIS 3

4

1

2
VGA@ PC711
22U_0805_6.3VAM

1

LX_1.5V_DIS

VGA@ PC713
4.7U_0603_6.3V6K

FB

+1.5VSDGPU

VGA@ PL702
1UH_VMPI0703AR-1R0M-Z01_11A_20%

1

10

2

TDC 8A

2

2

LX

1

VGA@ PC710
47U_0805_6.3V6M

GND

2

VGA@
PC705
0.1U_0603_25V7K

1

9

6

VGA@
PR704
0_0603_5%
1
2
BST_1.5V_DIS

1

BS

1

2

EN

VGA@ PC709
47U_0805_6.3V6M

VGA@

IN

1

8

2

VGA@ PC704
10U_0805_25V6K
2
1

VGA@ PC707
10U_0805_25V6K
2
1

B+_1.5V_DIS

PJ701

1

JUMP_43X118

VGA@ PC708
330P_0402_50V7K

PU701

2
@VGA_EMI@ PC703
0.1U_0402_25V6
2
1

LDO_1.5V_DIS
C

1

VGA@ PR705
15.4K_0402_1%

VGA_EMI@ PL701
HCB2012KF-121T50_0805
VGA_EMI@ PC706
2200P_0402_50V7K
2
1

B+

@EMI@ PR703
@EMI@ PC702
4.7_1206_5%
680P_0603_50V7K
1
2 SNB_1.5V_DIS
1
2

PJ703

1

B

2

2

+1.5VS

2

1
PC717
0.01U_0402_25V7K

1

Rup

+1.5VSP
2

FB

2

@

PR714
1.74K_0402_1%

Vout=0.8V* (1+Rup/Rdown)
Vout=1.508

2

Rdown
A

PC718
22U_0805_6.3VAM

2

2

@ PR713
47K_0402_5%

EN
POK

1

1

0_0402_5%

3
4
PR712
1.54K_0402_1%

8
7

VOUT
VOUT

1

2

VCNTL
VIN
VIN

1

1

1

SUSP#

PC719
0.1U_0402_16V7K

<42>

6
5
9

2

Rshort@
PR710

PU702
APL5930KAI-TRG_SO8

GND

2

1

JUMP_43X79
PC716
4.7U_0805_6.3V6K

Ultra Low Dropout 0.23V(typical) at 3A Output Current
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/19

Deciphered Date

2012/07/31

Title

1.5VSDGPUP/1.5VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

A

2

Rev

1.0

V4DA2 LAA131P Schematic

Thursday, August 01, 2013

Sheet
1

48

of

56

5

4

3

2

1

Follow Intel SB_ULT_PDDG 1.0
Specifications

VR_HOT#
PR806 10K ohm for 100 degree
PR806 8K ohm for 110 degree

VREF
100K_0402_1%_NCP15WF104F03RC

32A

Idyn_MAX

27A

B+

10A
2.0mV/A

Fast Slew Rate

48mV/us

4
3
2
1SKIP#-1 1

CSD97374CQ4M_SON8_3P5X4P5

If support PS4 and C10, pop PR830 and PD303,
change PR829 to 1K, PR814 to 1K.

1
2

1

PC812

2
1U_0603_10V6K

3
PL802
0.15UH_PCME064T 36A 20%

Plz notice.
Snubber R power rating on
High voltage and High FSW

2

CSP1

2.15K_0402_1%
PR822

for IC portion
for SW portion

1
2

TPS51622_V1A.mdd
TPS51622_V1B.mdd

PR825
3.01K_0402_1%

Module model information

2

1

1
@ PR824
56_0402_5%

2

+1.05VS_VTT

PR826
29.4K_0402_1%

2

B

1

4

2

1

2

PR823
10_0603_1%

2SKIP#

Rshort@ PR817
0_0402_5%

1

1

LX_CORE

B

1

VSW
PGND1
BOOT_R VDD
VIN
SKIP#

2

+3VS

6
5

PC817
0.15U_0603_16V7K

2

PR815
2.2_0603_5%

PH802
10K_0402_1%_TSM0A103F34D1RZ

0.1U_0402_25V6

1
2

4.7_1206_5%

1_0603_5%

1

33

PR816

PGND2
PWM
BOOT

CSP

BAT54HT1G_SOD323-2

1

2

VR_ALERT#

1

2

+5VALW

PC816
1U_0603_10V6K

PC814
4700P_0402_25V7K

2

PU802

9
8
7

PC809

1

680P_0603_50V7K

<26,33>
PWM1

1

VGATE

1

1

1 2

2
@ PD303

2

2

1

@EMI@ PC813 @EMI@ PR818

2

3
2

C

+CPU_CORE

+5VS
VR_SVID_CLK

0.33U_0603_10V7K
PC815

EMI@ PC808
2200P_0402_50V7K

1
@ PR830
10K_0402_1%
PR829
0_0402_5%

VREF
2

@EMI@ PC807
0.1U_0402_25V6

<42>

2

PR814
1.91K_0402_1%

5

2

2

1

VR_ON

1

6

4

4.22K_0402_1%

2

<42>

+3VS

PWM1

2

1

VR_ON

7

PAD

ALERT#
32

VCLK

GND

VR_HOT#

31

VDIO

2
SKIP#

VR_SVID_DATA

10

9
O-USR

11

OCP-I

F-IMAX

B-RAMP

IMON

13

12

30

26

PR819

+

2

1

@

1 PR820

2

V5A

VFB

10K_0402_5%

1

14

VDD

8

PC810
1U_0603_10V6K

2

100P_0402_50V8J

PR821
4.87K_0402_1%

THERM

PGOOD

GFB

PC811

1

N/C

N/C

1

VCC_SENSE

TPS51622RSM_QFN32_4X4

PU3

29

24

VCC_SENSE

PWM2

25

<42>

23

VSS_SENSE

VSS_SENSE

PWM1

CSP2

VREF

22
<42>

CSN2

COMP

21

1

VR_ON
SKIP#

28

20

2

1

Rshort@ PR813
0_0402_5%

CSN1

27

19

SLEWA

VBAT

18

+3VS
+3VS

CSP1

DROOP

17

C

15

PU801
CSN1

16

CSP1

1
+

PC806
33U_25V_M

10K_0402_5%

1

CPU_B+

2

2

PC805
33U_25V_M

1

2

1

PR812

2

1

D

EMI@
PL801
FBMA-L11-453215-121LMA90T_2

CPU_B+

CPU
Frequency = 1MHz
OCP Current 39 A
DCR: 0.66m +-7% ohm
PH601 B value: 4250k 1%
PH602 B value: 3435k 1%

Load-Line

PC804
10U_0805_25V6K

2 PR805 1
1
PR810

2

150K_0402_1%

1
PR809

2

Icc_MAX

Icc-TDC

O-USR
150K_0402_1%

1
PR808

2

150K_0402_1%

F-IMAX

8.87K_0402_1%

1
PR804

2

1M_0402_1%

1

PR803 @

75_0402_1%

2

1
PR802

422K_0402_1%

2
2 PR807 1

1
2

1
2

B-RAMP

2

39.2K_0402_1%
PR811

PC802
1000P_0402_50V7K

PR806
10K_0402_5%

1

SLEWA

OCP-I
56K_0402_1%

1

PC801

2

2
TI Alex : 0.1U => 1000P

2

@

PR801

4700P_0402_25V7K

1

PH801

IMON

75_0402_1%

1.8V
1.7V

PC803
10U_0805_25V6K

1

D

Vps0
Vboot

CSN1

VR_HOT#
<26,33>

VR_SVID_CLK

A

VR_ALERT#

<42> VR_SVID_DATA

1
2

1
2

PR828
130_0402_1%

1
2
<42>
<42>

PR827
54.9_0402_1%

+1.05VS_VTT

PC819
0.1U_0402_25V6

VR_SVID_CLK
VR_ALERT#
VR_SVID_DATA
A

Compal Secret Data

Security Classification
Issued Date

2012/06/19

Deciphered Date

2012/07/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
CPU_CORE

Size
C
Date:

Document Number

V4DA2 LAA131P Schematic
Thursday, August 01, 2013

Sheet
1

49

of

56

Rev
1.0

5

4

3

2

1

PC1016
22U_0805_6.3VAM
2
1
PC995
22U_0805_6.3VAM
2
1

@

@

@

@

PC951
22U_0805_6.3VAM
2
1

PC939
22U_0805_6.3VAM
2
1

PC1015
22U_0805_6.3VAM
2
1

D

C

@

PC967
22U_0805_6.3VAM
2
1

@

PC938
22U_0805_6.3VAM
2
1
PC950
22U_0805_6.3VAM
2
1
PC1022
22U_0805_6.3VAM
2
1

PC1019
22U_0805_6.3VAM
2
1

PC999
22U_0805_6.3VAM
2
1
PC949
22U_0805_6.3VAM
2
1
PC1021
22U_0805_6.3VAM
2
1

@

PC937
22U_0805_6.3VAM
2
1

PC1017
22U_0805_6.3VAM
2
1
PC936
22U_0805_6.3VAM
2
1
PC948
22U_0805_6.3VAM
2
1
PC1020
22U_0805_6.3VAM
2
1

PC1018
22U_0805_6.3VAM
2
1

PC997
22U_0805_6.3VAM
2
1

PC996
22U_0805_6.3VAM
2
1
PC1000
22U_0805_6.3VAM
2
1
PC935
22U_0805_6.3VAM
2
1

@

PC947
22U_0805_6.3VAM
2
1

@

PC969
22U_0805_6.3VAM
2
1

@

PC998
22U_0805_6.3VAM
2
1

@

PC934
22U_0805_6.3VAM
2
1
C

@

PC968
22U_0805_6.3VAM
2
1

D

PC946
22U_0805_6.3VAM
2
1

PC994
22U_0805_6.3VAM
2
1

+CPU_CORE

CPU LL=2m ohm dedign 22uF *18, 22uF*12(un-pop)
B

B

A

A

Security Classification

Compal Secret Data
2012/06/19

Issued Date

Deciphered Date

2012/07/31

Title

Compal Electronics, Inc.
CPU_CORE_CAP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
1.0

V4DA2 LAA131P Schematic

Thursday, August 01, 2013

Sheet
1

50

of

56

5

4

3

2

1

EN pin don't floating
If have pull down resistor at HW side, pls delete PR2

D

D

Rshort@
PR1001

VGA@

VGA_PG

1

<42>

1

2

2

JUMP_43X118

+0.95VSDGPU

@

2

2

1M_0402_1%
PR1002

2

PJ1001

0_0402_5%
@VGA@
PC1001
0.22U_0402_10V6K

1

1

1

+0.95VSDGPUP

@EMI@ PR1003
@EMI@ PC1002
4.7_1206_5%
680P_0603_50V7K
1
2SNB_0.95V 1
2

VGA@
PL1002
1UH_VMPI0703AR-1R0M-Z01_11A_20%

2

1
2

VGA@ PC1012
22U_0805_6.3VAM

1
2

VGA@ PC1011
22U_0805_6.3VAM

2

C

VGA@
PR1009
20K_0402_1%

Rdown
2

2

FB = 0.6V

1

1
SY8208DQNC_QFN10_3X3
VGA@

PR1008
0_0402_5%
Rshort@

+3VALW

1

0.95V_LDO

1

LDO

Rup

7
5

2

PG

BYP

VGA@ PC1014
4.7U_0603_6.3V6K

ILMT

1

2

ILMT_0.95V

4

VGA@ PC1013
4.7U_0603_6.3V6K

FB
ILMT_0.95V3

+0.95VSDGPUP

2

2

1

VGA@ PC1010
47U_0805_6.3V6M

2

1

1

0_0603_5%

2

6

10 LX_0.95V

VGA@
PC1005
0.1U_0603_25V7K

VGA@ PC1009
47U_0805_6.3V6M

LX

@VGA@ PR1004
1
2
BST_0.95V

1

1

BS
GND

1

2

EN

VGA@ PC1008
330P_0402_50V7K

IN

2

1
2

VGA@ PC1007
10U_0805_25V6K

1
2

1
2

8

9

1

2

B+_0.95V
VGA@ PC1006
10U_0805_25V6K

@VGA@
PR1005
0_0402_5%

PU1001

2
@VGA_EMI@ PC1003
0.1U_0402_25V6

1

0.95V_LDO

C

1

VGA_EMI@ PC1004
2200P_0402_50V7K

B+

VGA@ PR1006
12.4K_0402_1%

VGA_EMI@
PL1001
HCB2012KF-121T50_0805

Pin 7 BYP is for CS.
Common NB can delete

The current limit is set to 6A, 8A or 12A when this pin
is pull low, floating or pull high

+3VALW and PC15

VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=0.972

B

B

A

A

Security Classification

Compal Secret Data
2012/06/19

Issued Date

Deciphered Date

Vout=1.05V
2012/07/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Compal Electronics, Inc.
Title

0.95VSDGPUP
Size

Document Number

Rev

1.0

V4DA2 LAA131P Schematic
Date:

Thursday, August 01, 2013

Sheet
1

51

of

56

VID5

VID4

VID3

1.1V

0

1

0

0

VID2

VID1

0 0

VID0

+VGA_B+

0

PQ1101

1
PR1108
10K_0402_1%

VGA@ PR1105
2.2_0603_5%
2
1

UGATE2_VGA
PHASE2_VGA

40
39
38
37
36
35
34
33
32
31

@VGA_Rst@
PR1131 0_0402_5%
1
2

1

2

VGA@ PR1114
10K_0402_5%

2
1
2

1V1N_VGA
2

VGA@

PR1147
10K_0402_5%

1
2

1
1

B

PR1149 VGA@
1_0402_5%
2 V2N_VGA

0_0402_5%
ISEN1_VGA

VSUM-_VGA

EMI

Issued Date

PAD-OPEN1x1m

2012/06/19

Deciphered Date

2012/07/31

Title

VGA_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
6

5

4

3

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2

7

Rshort@
PR1150
1

VSUM+_VGA
@VGA_EMI@
PC1127
680P_0402_50V7K

+VGA_CORE

VSUM-_VGA

PJ1101
1

@VGA_EMI@
PR1145
4.7_1206_5%

2

DCR:1.4mΩ±5%
7.3x6.6x4

VGA@
PC1128
0.1U_0402_16V7K

1

@

2

Rds(on)
typ=2.7m Ω
max=3.3m Ω

2

A

PC1121
10U_0805_25V6K
2
1

1

2

Layout Note:
Place near Phase1 Choke

MDU1511RH_POWERDFN56-8-5
VGA@

4

LGATE1_VGA

C

PL1103
VGA@
0.36UH_PDME064T-R36MS1R405_24A_20%

5

PHASE1_VGA

EMI

PC1120
10U_0805_25V6K

4

3
2
1

VGA@ PH1102
10K_0402_1%_TSM0A103F34D1RZ
2
1

VGA@
PR1153
1.27K_0402_1%
1
2

PC1119
2200P_0402_50V7K
2
1

UGATE1_VGA-1
VGA@ PC1122
0.22U_0603_10V7K
1
2

VGA@

PR1143 VGA@
2.61K_0402_1%
2
1

0_0402_5%
PR1142 VGA@
2.2_0603_5%
2
1 BOOT1_1_VGA

@VGA_EMI@

UGATE1_VGA

MDU1516URH_POWERDFN56-8-5
VGA@

5

PQ1103
Rshort@
PR1156
1
2

PQ1104

VGA@ PR1148
11K_0402_1%
2
1

2

VGA@ PR1152
10_0402_5%
1
2

VGA@ PC1125
0.22U_0603_25V7K
2
1

1
2

VGA@ PC1126
0.01U_0402_50V7K

1

@VGA_Rst@
PR1151
0_0402_5%
1

2

B

1

VGA@ PR1112
3.65K_0402_1%
2
1

+VGA_B+

+5VS

2

@VGA@ PC1123
330P_0402_50V7K

8

1

D

3
2
1

VGA@ PC1116
1U_0603_10V6K
2
1

1

+5VS

VSUM+_VGA

@VGA@ PC1124
0.068U_0603_16V7K
2
1

1

E

+VGA_B+

VGA@ PR1139
1_0402_5%
1
2

2

1
2

2
@VGA_Rst@ PR1135
0_0402_5%

VSUM-_VGA
2

0_0402_5%
@VGA_Rst@
PR1144

<42> VSS_GPU_SENSE

2

PC1109 VGA@
1U_0603_10V6K

VGA@ PR1141
10_0402_5%

<42> VCC_GPU_SENSE

F

VSUM-_VGA

+5VS

C

1

VGA@
PR1117
1_0402_5%

LL Disable, Fsw = 300 kHz (typ)
Mars with turbo
I_TDC=25A
I_EDC =37.5A
I_OCP = 45A
VGA_CORE LL= disable
VGA_CORE cap = 330uF*3 (ESR 6m ohm)

BOOT1_VGA

2

PR1140 @VGA@
255K_0402_1%

2 V1N_VGA
0_0402_5%

ISEN2_VGA

2

1

ISEN1_VGA

G

+VGA_CORE

Rshort@
PR1115
1

VSUM+_VGA

ISL62883CHRTZ-T_TQFN40_5X5

@VGA_Rst@ PR1137
0_0402_5%
1
2

ISEN2_VGA

2

DCR: 1.4mΩ±5%
7.3x6.6x4

EMI

@VGA_Rst@
PR1130
0_0402_5%

VGA@ PC1117
0.22U_0603_25V7K

2

VGA@ PC1113 VGA@ PR1138
150P_0402_50V8J
324K_0402_1%

+VGA_CORE

@VGA_EMI@
PR1111
4.7_1206_5%

VGA@

CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0

470P_0402_50V7K
VGA@ PR1136
3.57K_0402_1%
1
2

1

1

AGND

11
12
13
14
15
16
17
18
19
20

1
2

2

41

VGA@ PR1134
VGA@
499_0402_1%
PC1111
1
2 1
2

VGA@ PC1112
68P_0402_50V8J
1
2

1

2

VGA@ PC1108
33P_0402_50V8J

VGA@ PC1110
1000P_0402_50V7K

@VGA@
D

VGA@ PR1133
8.06K_0402_1%
2
1

PR1132
249K_0402_1%
1
2

1

1

@VGA@
PR1128
27.4K_0402_1%

1

VGA@ PR1146
3.65K_0402_1%
2
1

1
@VGA@
PR1129
3.83K_0402_1%

30
29
28
27
26
25
24
23
22
21
1

2

2

1

BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1

PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2

VGA@ PC1115
0.22U_0402_10V4Z

2

1
2
3
4
5
6
7
8
9
10

2

@VGA@
PH1101
470K_0402_5%_ TSM0B474J4702RE
2
1

VGA@ PC1114
0.22U_0402_10V4Z

E

H

Rds(on)
typ=2.7m Ω
max=3.3m Ω

ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1

1

VGA@ PU1101
@VGA@
PR1127
10K_0402_5%

B+

EMI

PL1102
VGA@
0.36UH_PDME064T-R36MS1R405_24A_20%

@VGA_EMI@
PC1107
680P_0402_50V7K
2
1

3
2
1

1
PR1123
10K_0402_1%
VGA@

VGA@ PR1126
47K_0402_1%
2
1

+3VS

EMI

VGA_EMI@
PL1101
FBMA-L11-322513-151LMA50T_1210
2
1

5

@VGA@

4

2

1
PR1122
10K_0402_1%
VGA@

2

1
PR1121
10K_0402_1%
VGA@

2

1
PR1120
10K_0402_1%

@VGA@

VGA@

2

1
PR1119
10K_0402_1%
2

GPU_VID6
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0

VGA@ PR1125
100K_0402_5%
1
2

+3VS

2UGATE2_VGA-1
0_0402_5%

PQ1102

1

VGA_PG
<26,33>

F

Rshort@
PR1155
1

LGATE2_VGA
PR1116 VGA@
1.91K_0402_1%

2

@VGA_Rst@
PR1118
0_0402_5%
1
2

VGA@ PC1106
0.22U_0603_10V7K
1
2
BOOT2_2_VGA

3
2
1

BOOT2_VGA

2

1
PR1107
10K_0402_1%
2

1
PR1106
10K_0402_1%

1
PR1104
10K_0402_1%
2

2

@VGA@

@VGA@
PR1113
1.91K_0402_1%
1
2 CLK_ENABLE#_VGA

@VGA@

boot resistor to 1.1V

@VGA@

VGA@

2

VGA@ PR1110
10K_0402_1%
1
2

+3VSDGPU

4

1
1
PR1103
10K_0402_1%

G

@VGA@
PC1105
0.1U_0402_25V6

1

@VGA@
PR1157
10K_0402_1%
1
2

<42> GPU_DPRSLPVR

1

2

+3VSDGPU

MDU1516URH_POWERDFN56-8-5
VGA@

@VGA_Rst@
PR1102
0_0402_5%

MDU1511RH_POWERDFN56-8-5
VGA@

@VGA_Rst@
PR1101
0_0402_5%

0_0402_5%

5

VGA_ON_R

2

Rshort@
PR1154
1
2

GPU_VID_5
GPU_VID_4
GPU_VID_3
GPU_VID_2
GPU_VID_1
2

<42>

<42>
<42>
<42>
<42>
<42>

H

1

1V2N_VGA

VID6

2

1

Mars

Default
Voltage

3

2

VGA Chipset

4

VGA@ PC1104
10U_0805_25V6K
2
1

5

VGA@ PC1103
10U_0805_25V6K

6

2

7

@VGA_EMI@ PC1102
2200P_0402_50V7K
2
1

8

Size
Document Number
Custom
Date:
2

Rev

V4DA2 M/B LA-A131P
Schematic
Thursday, August 01, 2013
Sheet
52
of
56
1

5

VGA@ PC1319
1U_0402_6.3V6K
2
1
VGA@ PC1320
1U_0402_6.3V6K
2
1
VGA@ PC1321
1U_0402_6.3V6K
2
1
VGA@ PC1322
1U_0402_6.3V6K
2
1
VGA@ PC1323
1U_0402_6.3V6K
2
1
VGA@ PC1324
1U_0402_6.3V6K

VGA@ PC1333
1U_0402_6.3V6K
1
2
VGA@ PC1334
1U_0402_6.3V6K
2
1
VGA@ PC1335
1U_0402_6.3V6K
1
2
VGA@ PC1336
1U_0402_6.3V6K
1
2
VGA@ PC1337
1U_0402_6.3V6K

VGA@ PC1318
1U_0402_6.3V6K
2
1

VGA@ PC1331
1U_0402_6.3V6K
1
2
VGA@ PC1332
1U_0402_6.3V6K
1
2

VGA@ PC1317
1U_0402_6.3V6K
2
1

VGA@ PC1330
1U_0402_6.3V6K
2
1

1

VGA@ PC1316
1U_0402_6.3V6K
2
1

2

VGA@ PC1329
1U_0402_6.3V6K
2
1

1

C

VGA@ PC1315
1U_0402_6.3V6K
2
1

2

VGA@ PC1304
10U_0805_6.3V6M

VGA@ PC1308
1U_0402_6.3V6K
2
1

4

Issued Date

VGA@ PC1314
1U_0402_6.3V6K

VGA@ PC1313
1U_0402_6.3V6K
2
1

VGA@ PC1312
1U_0402_6.3V6K
2
1

VGA@ PC1311
1U_0402_6.3V6K
2
1

VGA@ PC1310
1U_0402_6.3V6K
2
1

VGA@ PC1309
1U_0402_6.3V6K
2
1

VGA@ PC1303
10U_0805_6.3V6M
2
1

VGA@ PC1307
1U_0402_6.3V6K
2
1

1

VGA@ PC1302
10U_0805_6.3V6M
2
1

2

VGA@ PC1306
1U_0402_6.3V6K
2
1

1

VGA@ PC1301
10U_0805_6.3V6M
2
1

2
VGA@ PC1305
1U_0402_6.3V6K
2
1

D

VGA@ PC1328
1U_0402_6.3V6K
2
1

1
+

2

1
+

2

Security Classification

VGA@ PC1326
330U_D2_2VM_R9M

4

1
+

2

VGA@ PC1327
330U_D2_2VM_R9M

+VGA_CORE

VGA@ PC1325
330U_D2_2VM_R9M

5
3

2012/06/19

3

2

Deciphered Date
2012/07/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

1

+VGA_CORE

D

AMD MARS
GPU_CORE
330uF*2
10uF*4+1uF*30
C

B
B

A
A

Compal Secret Data

Title

Compal Electronics, Inc.

Size
Document Number
Custom

VGA_CORE CAP

Date:

V4DA2 LAA131P Schematic

Thursday, August 01, 2013
Sheet
1

53
of
56

Rev
1.0

5

4

3

2

1

D

D

VR_ON

(PU801)
TPS51622RSM
QFN32_4X4

VGA_ON_R

(PU1101)
ISL62883CHRTZ
TQFN40_5X5

C

SYSON

ADAPTER

DDR_VTT_PG_CTRL

SUSP#

BATTERY

+CPU_CORE

Page 49

+VGA_CORE

Page 52

C

(PU501)
RT8207MZQW
WQFN20_3X3

+1.35V
Page 46

+0.675VS

(PU601)
SY8208DQKC
QFN10_3X3

+1.05VSP
Page 47

B+
VGA_PG

CHARGER

(PU701)
SY8208DQKC
QFN10_3X3

VGA_PG

B

(PU1001)
SY8208DQKC
QFN10_3X3

3V5V_EN

Page 51

SOT23-6

SO8

Page 45

SO8

Page 45

SO8

2012/06/19

2012/07/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

+1.5VS
A

Page 48

Compal Secret Data

Security Classification

5

+1.8VSDGPU

Page 47

(PU702)
APL5930KAI-TRG

SUSP#
A

Issued Date

+1.8VS_6511

Page 46

(PU603)
APL5930KAI-TRG

VGA_PG

+5VALW

2

B

+1.05VM

Page 46

(PU602)
APL5930KAI-TRG

6511_PWR_EN

+3VALW

(PU402)
SY8208CQKC
QFN10_3X3

(PU531)
SY8032ABC

PM_SLP_A#

+0.95VSDGPU

(PU401)
SY8208BQKC
QFN10_3X3

3V5V_EN

+1.5VS_DIS
Page 48

Title

Compal Electronics, Inc.
Power Tree

Size Document Number
Custom

Rev
1.0

V4DA2 LAA131P Schematic

Date:

Thursday, August 01, 2013

Sheet
1

54

of

56

5

4

3

2

Version change list (P.I.R. List)
Item

Fixed Issue

01
D

02

C

1

Page 2 of 1 for PWR
Reason for change

change Cff to 6.8nF
and 10nF if SY8208B
The 5VALW will fast
and the rising time

of SY8208C (5V)
(3V).
than 3VALW
will under 2mS.

change Cff to 6.8nF
and 10nF if SY8208B
The 5VALW will fast
and the rising time

of SY8208C (5V)
(3V).
than 3VALW
will under 2mS.

Rev.

PG#

Modify List

Date

Phase

45

Change PC425
From SE075472K80 - 4700P 25V K X7R 0402
to SE075103K80 - .01U 25V K X7R 0402

20130426

DVT

0.2

45

Change PC426
From SE075472K80 - 4700P 25V K X7R 0402
to SE075682K80 - 6800P 25V K X7R 0402

20130426

DVT

0.2

D

03

modify 1.35VP output voltage
from 1.515V modify to 1.355V

0.2

46

Change PR506
From SD028102280 - 10.2K +-1% 0402
to SD034806180 - 8.06K +-1% 0402

20130426

DVT

modify 1.05VMP output voltage
from 1.2V modify to 1.0722V

0.2

46

Change PR533
From SD034200280 - 20K +-1% 0402
to SD034787180 - 7.87K +-1% 0402

20130426

DVT

04
05

modify 1.8VSP and 1.8VS_DIS output voltage
from 1.508V modify to 1.839V

0.2

47

Change PR611, PR614
From SD034154180 - 1.54K +-1% 0402
to SD034226180 - 2.26K +-1% 0402

20130426

DVT

06

modify 1.5VSP output voltage
from 1.05V modify to 1.5V

0.2

48

Change PR709
From SD034200280 - 20K +-1% 0402
to SD034100280 - 10K +-1% 0402

20130426

DVT

51

Change PR1006
From SD034150280 - 15K +-1% 0402
to SD00000AJ80 - 12.4K +-1% 0402

20130426

DVT

20130524

DVT

20130524

DVT

modify 0.95VSDGPUP output voltage
from 1.05V modify to 0.972V

07

0.2

C

CPU_CORE choke DCR from 0.85m ohm
adjust to 0.66m ohm,
modify component to setting VREF, OCP,etc.

0.2

49

Change PR819
from SD034487100 - 4.87K +-1% 0402 to SD00000J280 - 4.32K +-1% 0402
Change PR826
from SD034200280 - 20K +-1% 0402 to SD034523280 - 52.3K +-1% 0402
Change PR822
from SD034226180 - 2.26K +-1% 0402 to D034210180 - 2.1K +-1% 0402 Change PR807
from SD034390280 - 39K +-1% 0402 to SD034560280 - 56K +-1% 0402
Change PR802
from SD034365380 - 365K +-1% 0402 to SD034442300 - 442K +-1% 0402
Change PC817, PC818 to PC817
from SE076823K80 - 0.082U 16V K X7R 0402 to SE00000OX80 0.15U 16V K X7R 0603

09

modify 1.05VSP output voltage
from 1.05V modify to 1.062V
for EA test voltage drop under 1.05V

0.2

47

Change PR636
From SD034150280 - 15K +-1% 0402
to SD034154280 - 15.4K +-1% 0402

10

modify 1.5VS_DIS output voltage
from 1.5V modify to 1.522V
for EA test voltage drop under 1.5V

0.2

48

Change PR705
From SD034150280 - 15K +-1% 0402
to SD034154280 - 15.4K +-1% 0402

20130524

DVT

0.2

48

Change PC1327
From SGA00006J00 - 560U 2V M D2 LESR4.5M SX H1.9
to SGA00006100 - 330U 2V M D2 ESR9M S H1.9

20130524

DVT

modify 1.05VS/1.5VSDGPU/0.95VSDGPU choke
from 1.5U change to 1U, for efficiency heavy load improve
0.2
1.05V => from 83.2% to 85.5%
1.5V
=> from 83.7% to 85.5%
0.95V => from 80.6% to 84.8%

47,
48,
51

Change PL602, PL702, PL1002
From SH000008800 - 1.5UH +-20% PCMC063T-1R5MN 9A
to SH00000KS00 - 1UH +-20% VMPI0703AR-1R0M-Z01 11A

20130524

DVT

Part count reduce
PR609, PR612, PR710;
PR615, PR616, PR713;
PC621, PC622, PC719
are +1.5VS/1.8VS/1.8VSDGPU enable RC.

0.3

47,
48

Change PR609, PR612, PR710 change to Rshort@
From SD028100380-S RES 1/16W 100K +-5% 0402 to SD028000080-S RES 1/16W 0 +-5% 0402
Un-pop PR615, PR616, PR713 From SD028470280 - S RES 1/16W 47K +-5% 0402 to un-pop
Un-pop PC621, PR622, PC719 From SE076104K80 - S CER CAP .1U 16V K X7R 0402 to un-pop

20130531

PVT

0.3

49

Un-pop PR824
From SD028560A80 - S RES 1/16W 56 +-5% 0402 to un-pop

20130531

PVT

08

B

B

modify VGA output capacitor
from 560U*1+330U*2 reduce to 330U*3
static Pk-Pk ripple from 32.12mV up to 35.63mV
dynamic Pk-Pk ripple from 88mV up to 94mV.

11

12

13

Part count reduce
PR824 is VR-HOT# pull high resistor, beacuse there have
a 0 ohm between VR_HOT# and H_PROCHOT#, H_PROCHOT# also
have a pull high voltage, discuss with HW, we could
un-pop PR824

A

14

A

2012/06/19

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/07/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PIR (PWR)
Size
Document Number
Custom
Date:

5

4

3

2

Rev
1.0

V4DA2 LAA131P Schematic

Thursday, August 01, 2013

Sheet
1

55

of

56

5

4

3

2

1

Version change list (P.I.R. List)
Item

Fixed Issue

Rev.

PG#

modify 1.35VP output voltage
from 1.3515V modify to 1.365V

0.3

46

16

part count reduce

0.3

45
47
51

17

part count reduce

0.3

TI suggest, If support PS4 and C10, pop PR830 and
PD303, change PR829 to 1K, PR814 to 1K.

MOS AON7702A EOL

15
D

18

PS51622 which might cause system hang
when exit C10 with PS4.
TI solution : RC filter to ignore the
~4us glitch on PGOOD.

19

Reason for change

Modify List

Date

Phase

Change PR506
From SD034806180 - 8.06K +-1% 0402
to SD000004100 - 8.2K +-1% 0402

20130606

PVT

Change PR401, PR409, PR634, PR1004
From SD013000080 - 0_0603_5% to R_short

20130606

PVT

44,46
47,48
51,52

Change PR311, PR534, PR631, PR635, PR701, PR706,
PR1001, PR1008, PR1115, PR1150, PR1154, PR1155, PR1156
From SD028000080 - 0_0402_5% to R_short

20130606

PVT

0.3

49

reserve PD303, SCS00003M00 - SCH DIO BAT54HT1G SOD323
reserve PR830, SD034100280 - 10K +-1% 0402
Add PR829, SD034100180 - 0 +-5% 0402

20130628

PVT

0.3

46

Change PQ502
from SB00000T600 - AON7702A 1N DFN
to SB000010A00 - AON7506 1N DFN

20130628

PVT

20130628

PVT

D

20

Finetune RC for CPU Transient Voltage Testing

0.3

49

Change PR819 from SD00000J280 - 4.32K +-1% 0402
to SD034422180 - 4.22K +-1% 0402
Change PR822 from SD034210180 - 2.1K +-1% 0402
to SD034215180 - 2.15K +-1% 0402
Change PR826 from SD034523280 - 52.3K +-1% 0402
to SD034294280 - 29.4K +-1% 0402
Change PR802 from SD034442300 - 442K +-1% 0402 to
SD034422380 - 422K +-1% 0402

21

part count reduce output capacitor reference
CPU Transient Voltage Testing

0.3

49

Change PC1005, PC938, PC939, PC946, PC951, PC997
from SE000008L80 - CER CAP 22U 6.3V M X6S 0805 H1.25 to un-pop

20130628

PVT

Add EMI solution Snubber at 5V and 1.05VS
PC424 680pF, PC632 680pF
PR410 4.7 ohm, PR633 4.7 ohm

20130731

PVT2/
Pre-MP

C

EMT test 5V and 1.05VS,
Main source SY8208C/D could PASS,
but 2nd source SY8206C/D fail,
EMI add snubber the both could PASS.

22

0.4

45, 47

C

23
B

B

24

25

26

27
A

A

28
2012/06/19

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/07/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PIR (PWR)
Size
Document Number
Custom
Date:

5

4

3

2

Rev
1.0

V4DA2 LAA131P Schematic

Thursday, August 01, 2013

Sheet
1

56

of

56

5

4

3

2

1

EVT-->DVT Change List

D

ESD modify
1.page37, add R649~R656

1.page36, pin 68 and pin 21 SWAP and pin 89 and pin 17
2.page30, R407,R408,change to 1K and R439 connect to JMINI3.51 and R439 change to 240 ohm
3.page28, R478, R482 change to mount
4.page39, R527 change to 1M
5.page33, R592 and R593 change to 60.4 ohm
6.page27, remove C248,C253,C404,C405,QA2,RA5,RA6,RA7,RA8,U45
update U11 and add T39
add R645 ,R646 ,L12,L13
U11.16 connect to +5VS
C782 connect to +5VS
add R647 and R648
R647 and R648 change to @
R645 ,R646 change to SD028100A80
C249 and C251 change to mount
7.page26, RA12 and RA14 mount ,RA16 and RA18 un-mount
RA2,RA3,RA4,RA9 mount
RA32 change to 93.1 ohm
CA22 and CA21 change to SE071150J80
8.page30, JNFC1.15 connect to GPIO 17
R637 change to unmount ,R640 change to mount
9.page37, add C814 and C814 change to 1UF
10.page30, JMINI3.44 connect to UU1.L2 and add R657 ,R658
11.page32, T36 change PN to SP050007E00
12.page34, R620 change to 470K

D

C

C

DVT-->PVT Change List

B

1.page36, remove JIO2
2.page27, L6,L8,L10,L12,L13 from SM01000GA00 change to SM01000FH00 for downsize of source suggest
3.page36, L40,L41,L44,L45,L46,L47 from SM010015410 to SM01000N000 for downsize of source suggest
4.page33, L31 from SM010017710 to SM01000FH00 for downsize of source suggest
5.page26, LA2 from SM010030010 to SM010028100 for downsize of source suggest
6.page19,21 LV1,LV2,LV3,LV7,LV8,LV9 from SM010030010 to SM010028100 for downsize of source suggest
7.page25, U44 from SA00003AR00 to SA00006EE00 for cost down
8.page34, U46 from SA00003AR00 to SA00006EE00 for cost down
9.page40, U50 and U56 from SA00003AR00 to SA00006EE00 for cost down
10.page31, UL3 from SA00003AR00 to SA00006EE00 for cost down
11.page37, C814 change to SE000000K80 for downsize
12.page33, add R659 and R660 for audio suggest
13.page27, R645 and R646 change to 33 ohm for CRT overshoot
14.page33, L31 change to SM01000II00 for downsize of source suggest
15.page38, update JLID1 pin define
16.page34, update C803 ,C804,C805 SN to SGA00000Y80

ESD modify
1.page38 add
2.page38 add
3.page15 add
4.page8, add

831
C820~830
CU186 (@ESD@)
CU187 (@ESD@)

B

PVT-->Per-MP Change List

A

1.page30, JNFC1 SWAP
2.page38, C480 and JTP1.4 connect to +3VS
3.page8, JAPS.11 connect to ON/OFFBTN#
4.page31,add RU176 to @
5.page9, RPU19.8 and UU1.AG5 connect to DET_SIG#_R_1
6.page9, add RU176
7.page35, JIO1.1 connect to +3VALW and reserve +3VS ,add R661 and R662
8.page27, L6,L8,L10,L12,L13 from SM01000FH00 change to SM01000GA00
9.page35, add U60 ,C833, C832 ,R666,R661
10.page34, add R664 ,D38,R663
11.page33, R659 and R660 change to 0 ohm
12.page38, C826~C829 change to @
13.page36, L40 and L41 change to SM01000DS00 (NBQ100505T-800Y)
14.page33, L44~L47 change to SM01000DS00 (NBQ100505T-800Y)
15.page36, R483 change to 20K
16.page38, SW1 to @
17.page39, SW3 to @
18.page7, add second source
19.page28, R478 un-mount ,R448 mount

A

Title
PIR(HW)
Size
A
Date:

5

4

3

Document Number
V4DA2 LAA131P Schematic
Monday, August 05, 2013
2

Rev
1.0
Sheet

57

of
1

57

www.s-manuals.com



---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.6
Linearized                      : No
Page Mode                       : UseNone
XMP Toolkit                     : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39
Create Date                     : 2013:08:05 15:08+08:00
Modify Date                     : 2015:10:28 22:03:28+02:00
Metadata Date                   : 2015:10:28 22:03:28+02:00
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Title                           : Compal LA-A131P - Schematics. www.s-manuals.com.
Creator                         : 
Subject                         : Compal LA-A131P - Schematics. www.s-manuals.com.
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Keywords                        : Compal, LA-A131P, -, Schematics., www.s-manuals.com.
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