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User Manual: Motherboard Compal LA-A913P ZAM81 - Schematics. Free.
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A
B
C
D
E
COMPAL CONFIDENTIAL
1
MODEL NAME : ZAM81
PCB NO :
LA-A913P
BOM P/N :
1
GPIO MAP: 3.1
Huston 15" DSC
2
2
Broadwell U
2013‐08‐20
REV : 0.1 (X00)
@ : Nopop Component
EMC@ : EMI, ESD and RF Component
@EMC@ : EMI, ESD and RF Nopop Component
XDP@ : XDP Component
CONN@ : Connector Component
3
3
4
4
MB PCB
Part Number
Description
DAA0007Y000
PCB 13N LA-A913P REV0 MB DSC DOCK 3
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
E
1
of
56
A
B
C
D
E
Reverse Type
Houston15 DSC Block Diagram
VRAM
DDR3
DDR3L-DIMM X2
BANK 0, 1, 2, 3
NVIDIA Graphics
N15S-GT/GM PAGE40~44
PAGE45~46
Memory BUS (DDR3L)
PCIe x 4
PAGE 18 19
1333/1600MHz
1
1
USB2.0[4]
eDP CONN
Dual Lane eDP1.3
PAGE 23
PAGE 23
USB2.0[5]
INTEL
HDMI
HDMI CONN
HDMI Level Shifter
PS8401A
PAGE 24
PAGE 24
DDI1
USB2.0[1]
BROADWELL ULT
VGA PI3V713
PAGE 26
IDT
VMM2320
VGA
VGA SW
PAGE 22
PAGE 26
DOCKING
USB2.0[3]
DDI2
PAGE 25
USB POWER SHARE
USB2.0 SW
NX3DV221GM
USB2.0&3.0 SW
USB3.0[1] PI3USB3102ZLEX
DP
PAGE 31
DP
CONN
PAGE 6~17
SD4.0
O2 Micro OZ777FJ2LN
PAGE 29
PAGE 29
USB3.0/2.0
HD Audio I/F
PCIE3
PCIE4
SATA2
HDA Codec
ALC3235
WWAN/LTE
PAGE 28
WLAN/BT/
WIGIG
PAGE 30
PAGE 30
USB2.0[7]
Transformer
On Audio/B
Trough eDP Cable
PAGE 21
PAGE 7
LID switch
SATA REPEATER
PI3EQX6741STZDEX
PAGE 39
SATA3 Conn
PAGE 20
PAGE 20
USH CONN
3
PAGE 27
PAGE 27
PAGE 35
CPU XDP Port
PAGE 9
BC BUS
Automatic Power
Switch (APS)PAGE 9
KB/TP CONN
SMSC KBC
MEC5085
PAGE 37
FAN CONN
PAGE 36
RJ45
PAGE 21
Single DMIC
Discrete TPM
AT97SC3205
USB2.0[2]
WIGIG_DP
PAGE 28
SMSC SIO
ECE5048
2
Dig. MIC
64M 4K sector
W25Q32BVSSIQ
Intel Clarkville
I218LM
PAGE 31
Universal Jack
PAGE 21
W25Q64CVSSIQ
PCIE6_0
USB3.0[2]
PAGE 31
INT.Speaker
SATA1
PCI Express BUS
USB3.0 Redriver
PS8713B PAGE 32
PAGE 21
32M 4K sector
3
SW_USB2.0[0]
SW_USB3.0[1]
SPI
DAI
LAN
SATA1
DOCK_USB2.0[0]
DOCK_USB2.0[5]
DOCK_USB3.0[3]
PCIE1
LPC
PAGE 27
USB3.0/2.0
DOCK_USB3.0[1]
Trough eDP Cable
USB3.0/2.0
PS PAGE 32
SW_USB2.0[3]
USB3.0[4]
PAGE 31
USB2.0[0]
Card reader
USB2.0[1]_PS
PAGE 32
WIGIG_DP
VGA
2
PS8338B
DP Sw
DP
Camera
PAGE 23
TPS2544
USB
VGA CONN
LCD Touch
Free Fall sensor
PAGE 20
PAGE 36
PAGE 28
DC/DC Interface
PAGE 38
4
Smart Card
RFID
Power On/Off
SW & LED PAGE 39
USH
BCM5882
TDA8034HN
DELL CONFIDENTIAL/PROPRIETARY
Fingerprint
CONN
FP_USB
PAGE 29
A
Compal Electronics, Inc.
USB2.0[6]
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
USH board
B
C
D
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
E
2
of
56
4
5
4
3
2
1
POWER STATES
Signal
SLP
S3#
SLP
S4#
SLP
S5#
SLP
A#
M
PLANE
SUS
PLANE
RUN
PLANE
S0 (Full ON) / M0
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
ON
S3 (Suspend to RAM) / M3
LOW
HIGH
HIGH
HIGH
ON
ON
ON
OFF
OFF
S4 (Suspend to DISK) / M3
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
OFF
S5 (SOFT OFF) / M3
LOW
LOW
LOW
HIGH
ON
ON
OFF
OFF
OFF
S3 (Suspend to RAM) / M-OFF
LOW
HIGH
HIGH
LOW
ON
OFF
ON
OFF
OFF
S4 (Suspend to DISK) / M-OFF
LOW
LOW
HIGH
LOW
ON
OFF
OFF
OFF
OFF
S5 (SOFT OFF) / M-OFF
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
OFF
State
D
C
ALWAYS
PLANE
PCIE
CLOCKS
USB3.0
power
plane
+3.3V_SUS
+5V_RUN
+3.3V_M
+3.3V_M
+3.3V_ALW
+1.35V_MEM
+3.3V_RUN
+1.05V_M
+1.05V_M
+3.3V_ALW_PCH
+0.675V_DDR_VTT
+3.3V_RTC_LDO
+1.05V_RUN
DESTINATION
USB3.0 1
JUSB1-->Rear left
USB3.0 2
JUSB3-->Right
PCIE 1
USB3.0 3
MMI (CARD READER)
PCIE 2
USB3.0 4
JUSB2-->Rear Right
PCIE 3
LOM
PCIE 4
WLAN
PCIE 5
GPU/WIGIG
PCIE 6
PM TABLE
+5V_ALW
SATA
(M-OFF)
SATA 3
WIGI/Express
SATA 2
mSATA/PCIE
SATA 1
HDD
SATA 0
DOCK
D
C
+VCC_CORE
DESTINATION
USB PORT#
State
B
S0
ON
ON
ON
ON
ON
S3
ON
ON
OFF
ON
OFF
S5 S4/AC
ON
OFF
OFF
ON
OFF
S5 S4/AC doesn't exist
OFF
OFF
OFF
OFF
OFF
BDW
ULT
need to update Power Status and
PM Table
USH
0
JUSB1
1
JUSB3
2
WLAN + BT
3
JUSB2
4
Touch Screen
5
CAMERA
6
USH
7
WWAN
0
BIO
1
NA
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Rev
A
4019RA
Date:
Thursday, November 14, 2013
Sheet
1
3
of
56
5
4
3
2
RUN_ON
1
MPHYP_PWR_EN
TPS22965
(UZ7)
SI3456
(QZ6)
D
D
EN_INVPWR
ADAPTER
FDC654P
(QV1)
+BL_PWR_SRC
+1.05V_RUN
A_ON
+1.05V_MODPHY
SY8208DQNC
+1.05V_M
(PU300)
+1.05V_PEX_VDD
3V3_MAIN_EN
BATTERY
+PWR_SRC
3V3_MAIN_EN
TPS22965
(UV15)
RT8813
+3.3V_RUN_GFX
+GPU_CORE
(PU600)
ALWON
TPS51285
(PU100)
+5V_ALW
C
C
CHARGER
TPS51622
(PU500)
H_VR_EN
TPS22966
(UZ3)
TPS22966
(UZ2)
APL3512
(UV24)
RUN_ON
RUN_ON
EN_LCDPWR
3.3V_WWAN_EN
SIO_SLP_LAN#
SUS_ON
AUX_EN_WOWL
TPS22966
(UZ8)
USB_PWR_SHR_EN#
USB_PWR_EN1#
TPS2544
(UI3)
TPS22966
(UZ9)
USB_PWR_EN2#
G547I2P81U
(UI1)
G547I2P81U
(UI2)
+1.35V_MEM
DGPU_PWR_ON
SI416
(QV83)
+3.3V_M
+0.675V_DDR_VTT
+3.3V_WLAN
+3.3V_ALW_PCH
A
+3.3V_LAN
+3.3V_SUS
+LCDVDD
+3.3V_WWAN
+3.3V_CAM
+3.3V_RUN
+5V_RUN
3.3V_CAM_EN#
+VCC_CORE
0.675V_DDR_VTT_ON
B
SUS_ON
B
RT8207
(PU200)
PCH_ALW_ON
A_ON
+3.3V_ALW
LP2301ALT1G
(QZ1)
+5V_USB_CHG_PWR
LP2301ALT1G
(QV8)
3.3V_TS_EN
DGPU_PWR_EN
+USB_LEFT_PWR
LP2301ALT1G
(QV86)
+USB_RIGHT_PWR
+5V_TS
+3.3V_GFX_AON
A
DELL CONFIDENTIAL/PROPRIETARY
+1.35V_MEM_GFX
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
4
of
56
5
4
3
2
1
2.2K
SMBUS Address [0x9a]
+3.3V_ALW_PCH
2.2K
AP2
MEM_SMBCLK
AH1
MEM_SMBDATA
202
2N7002
DIMMA
200
2N7002
1K
202
BDW
D
+3.3V_ALW_PCH
1K
AN1
AH3
AU3
31
LOM
53
SML1_SMBCLK
3A
28
SML0DATA
AK1
SML1_SMBDATA
A5
SML0CLK
2.2K
XDP
51
2.2K
+3.3V_ALW_PCH
B6
10K
2.2K
2.2K
4
+3.3V_ALW
6
B4
DOCK_SMB_CLK
127
A3
DOCK_SMB_DAT
129
1A
+3.3V_RUN
10K
3A
1A
D
DIMMB
200
G Sensor
DOCKING
C
C
1B
1B
2.2K
KBC
2.2K
1C
1C
A56
B59
+3.3V_ALW
3
100 ohm
PBAT_SMBCLK
PBAT_SMBDAT
BATTERY
CONN
4
100 ohm
2.2K
2.2K
A50
MEC 5085
1E
B53
1E
+3.3V_SUS
M9
USH_SMBCLK
L9
USH_SMBDAT
USH
B
B
2B
2B
10K
10K
B50
1G
A47
1G
+3.3V_ALW
11
CHARGER_SMBCLK
12
CHARGER_SMBDAT
Charger
2D
A
A
2D
2.2K
2.2K
2A
2A
5
B48
B49
DELL CONFIDENTIAL/PROPRIETARY
+3.3V_RUN
Compal Electronics, Inc.
D8
GPU_SMBDAT
D9
GPU_SMBCLK
4
GPU
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
5
of
56
5
4
3
DSC SATA port
Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the entire region of the SPI flash to be updated using FPT.
+3.3V_ALW_PCH
2
RC2
1K_0402_5%
SW1
<36>
ME_FWP_EC
ME_FWP
1
2
3
1
2
3
G2
G1
SATA1
PCB
E-Dock
HDD
H12 UMA
NA
HDD
H12 Entry
E-Dock
HDD
H14 DSC
M2 3042
SATA-Cache(no HCA)
E-Dock
HDD
H14 UMA
M2 3042
2nd PCIe Lane for PCIe Cache
NA
HDD
H14D_En
NA
NA
HDD
H14U_En
NA
E-Dock
HDD
H15 DSC
M2 3042
SATA-Cache(no HCA)
E-Dock
HDD
H15 UMA
M2 3042
2nd PCIe Lane for PCIe Cache
NA
HDD
H15D_En
NA
NA
HDD
H15U_En
NA
SATA2/PCIE6 L1 SATA3/PCIE6 L0
ME_FWP PCH has internal 20K PD.
RC1
330K_0402_5%
1
4
FLASH DESCRIPTOR SECURITY OVERRIDE
ME_FWP=LOW → ENABLE ME (DEFAULT)
‐‐> Pin1 & Pin3 short
=HIGH → DISABLE ME (ME can update) ‐‐> Pin2 & Pin3 short
PCH_INTVRMEN
1
INTVRMEN ‐ INTEGRATED SUS 1.05V VRM
ENABLE
High ‐ Enable Internal VRs
Low ‐ Enable External VRs
CC1
2
2
0_0402_5%
@ RC4
2
YC1
32.768KHZ_12.5PF_Q13FC135000040
2
1
2
1
RC9
CC2
2
NA
1
RC10 1
RC8
1
NA
SATA2/PCIE6_L1 contact to WWAN
M2 3030 WIGIG SATA3/PCIE6 L0 contact to WLAN
M2 3042
(HCA & SATA-Cache)
2
2 20K_0402_5%
20K_0402_5%
<9>
1
2
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
<21>
PCH_AZ_CODEC_SDIN0
ME_FWP
1
RC11
PCH_AZ_BITCLK
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
2
PCH_AZ_SDOUT
1K_0402_5%
CMOS place near DIMM
TPM setting
CMOS_CLR1
Shunt
Clear ME RTC Registers
Shunt
Clear CMOS
Keep ME RTC Registers
Open
Keep CMOS
+1.05V_M
1
2
1
PCH_JTAG_TDI
51_0402_5%
PCH_JTAG_TDO
51_0402_5%
1
PCH_JTAG_TMS
51_0402_5%
1
PCH_JTAG_JTAGX
1K_0402_1%
RC15
2
RC16
2
@ RC18
@
2
RC21
1
AW8
AV11
AU8
AY10
AU12
AU11
AW10
AV10
AY8
CMOS setting
Open
2
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
RTC
2
@
CMOS1 SHORT PADS~D
1
2
1U_0402_6.3V6K
RC14
RTCX1
RTCX2
INTRUDER
INTVRMEN
SRTCRST
RTCRST
PCH_RTCRST#
CC4
ME_CLR1
AW5
AY5
AU6
AV7
AV6
AU7
1U_0402_6.3V6K
1
D
contact to WWAN
M2 3030 WIGIG contact to WLAN
NA
SATA2/PCIE6_L1 contact to WWAN
M2 3030 WIGIG SATA3/PCIE6 L0 contact to WLAN
M2 3042
(HCA & SATA-Cache)
contact to WWAN
M2 3030 WIGIG contact to WLAN
contact to Express card
Express card
BDW_ULT_DDR3L
UC1E
INTRUDER#
PCH_INTVRMEN
SRTCRST#
PCH_RTCRST#
18P_0402_50V8J
2
contact to WWAN
C
PCH_RTCX2
1M_0402_5%
CC3
B
M2 3042
(HCA & SATA-Cache)
PCH_RTCX1
1
18P_0402_50V8J
1
+RTC_CELL
1
PCH_RTCX1_R
RC7
10M_0402_5%
C
M2 3042
2nd PCIe Lane for PCIe Cache
SS3-CMFTQR9_3P
+RTC_CELL
2
5
1
SATA0
1
D
2
<9>
<9>
<9>
<9>
<9>
PCH_JTAG_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
<9>
PCH_JTAG_JTAGX
PCH_JTAG_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
AU62
AE62
AD61
AE61
AD62
AL11
AC4
AE63
AV2
HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_RST/I2S_MCLK
AUDIO
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_SDO/I2S0_TXD
HDA_DOCK_EN/I2S1_TXD
HDA_DOCK_RST/I2S1_SFRM
I2S1_SCLK
SATA
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
PCH_TRST
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
RSVD
RSVD
JTAGX
RSVD
JTAG
SATA_IREF
RSVD
RSVD
SATA_RCOMP
SATALED
J5
H5
B15
A15
SATA_PRX_DKTX_N0_C
SATA_PRX_DKTX_P0_C
SATA_PTX_DKRX_N0_C
SATA_PTX_DKRX_P0_C
J8
H8
A17
B17
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
J6
H6
B14
C15
<20>
<20>
<20>
<20>
PCIE_PRX_SATATX_N6_L1
PCIE_PRX_SATATX_P6_L1
PCIE_PTX_SATARX_N6_L1
PCIE_PTX_SATARX_P6_L1
F5
E5
C17
D17
PCIE_PRX_WIGIGTX_N6_L0
PCIE_PRX_WIGIGTX_P6_L0
PCIE_PTX_WIGIGRX_N6_L0
PCIE_PTX_WIGIGRX_P6_L0
V1
U1
HDD_DET#
V6
SATA2_PCIE6_L1
AC1mCARD_PCIE#_SATA
A12
L11
K10
C12
U3
<34>
<34>
<34>
<34>
for DOCK
SATA HDD
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
for SATA‐CACHE (WWAN)
for WIGIG (WLAN)
MPCIE_RST#
<7>
HDD_DET#
<20,7>
SATA2_PCIE6_L1
<12,35>
mCARD_PCIE#_SATA
<36,7>
B
+PCH_ASATA3PLL
SATA_COMP
SATA_ACT#
SATA_ACT#
<29,7>
<30,7>
<10>
+3.3V_RUN
<39>
RPC18
5
6
7
8
MMICLK_REQ#
WIGIGCLK_REQ#
PCH_GPIO52
4
3
2
1
10K_8P4R_5%
BDW-ULT-DDR3L_BGA1168
5 OF 19
PCH_JTAG_TCK
51_0402_5%
SATA Impedance Compensation
+PCH_ASATA3PLL
1
SATA_COMP
3.01K_0402_1%
HDA for Codec
<21>
<21>
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
2
PCH_AZ_SDOUT
33_0402_5%
1
2
PCH_AZ_SYNC
RC20
33_0402_5%
1
2
PCH_AZ_RST#
RC22
33_0402_5%
1 EMC@ 2
PCH_AZ_BITCLK
RC23
33_0402_5%
RC19
PCH_AZ_CODEC_SYNC
PCH_AZ_CODEC_RST#
PCH_AZ_CODEC_BITCLK
A
CC5
@EMC@
27P_0402_50V8J
1
<21>
A
1
PCH_AZ_CODEC_SDOUT
2
<21>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Reserve for EMI
5
2
RC17
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
6
of
56
5
4
3
2
1
+3.3V_RUN
+3.3V_ALW_PCH
BDW_ULT_DDR3L
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
<27>
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_CS2#
PCH_SPI_DO
PCH_SPI_DIN
PCH_SPI_DO2
PCH_SPI_DO3
PCH_SPI_CLK
D
<27>
<27>
<27>
AU14
AW12
AY12
AW11
AV12
PCH_SPI_CS2#
PCH_SPI_DO
PCH_SPI_DIN
AA3
Y7
Y4
AC2
AA2
AA4
Y6
AF1
LAD0
LAD1
LAD2
LAD3
LFRAME
LPC
SMBUS
SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
SPI
SMBALERT/GPIO11
SMBCLK
SMBDATA
SML0ALERT/GPIO60
SML0CLK
SML0DATA
SML1ALERT/PCHHOT/GPIO73
SML1CLK/GPIO75
SML1DATA/GPIO74
CL_CLK
CL_DATA
CL_RST
C-LINK
AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3
AF2
AD2
AF4
MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#
<12>
2
<35,36>
<35,36>
<35,36>
<35,36>
<35,36>
6
MEM_SMBCLK
SML0_SMBCLK
SML0_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SML0_SMBCLK
<28>
SML0_SMBDATA
<28>
PCH_GPIO73
<11>
SML1_SMBCLK
<36>
SML1_SMBDATA
<36>
PCH_CL_CLK1
PCH_CL_DATA1
PCH_CL_RST1#
5
UC1G
RPC14
1
DDR_XDP_WAN_SMBCLK
1
2
3
4
SML1_SMBCLK
MEM_SMBCLK
MEM_SMBDATA
SML1_SMBDATA
<18,19,20,9>
QC1A
DMN66D0LDW-7_SOT363-6
8
7
6
5
2.2K_0804_8P4R_5%
MEM_SMBDATA 3
4
DDR_XDP_WAN_SMBDAT
<18,19,20,9>
SML0_SMBCLK
1K_0402_5%
SML0_SMBDATA
1K_0402_5%
QC1B
DMN66D0LDW-7_SOT363-6
PCH_CL_CLK1
<30>
PCH_CL_DATA1
<30>
PCH_CL_RST1#
<30>
2
1
2
1
RC33
D
RC34
+3.3V_SPI
BDW-ULT-DDR3L_BGA1168
7 OF 19
1
64Mb Flash ROM
SOFTWARE TAA
SPI_CLK32
UC2
SPI_PCH_CS0#
RC35 1
2 0_0402_5%
SPI_PCH_DO2
RC38 1
2 33_0402_5%
1
2
3
4
SPI_PCH_CS0#_R
SPI_DIN64
SPI_PCH_DO2_64
2
1
2
1
2
1
2
1
@EMC@
@EMC@
CC10
RC62
33P_0402_50V8J
33_0402_5%
@EMC@
@EMC@
CC9
RC61
33P_0402_50V8J
33_0402_5%
SPI_PCH_DIN
SPI_PCH_DO
SPI_PCH_CLK
SPI_PCH_DO3
1
1
2
3
4
2 SPI_PCH_DO2
1K_0402_5%
2 SPI_PCH_DO3
1K_0402_5%
RC29
1
RC31
8
7
6
5
VCC
/HOLD(IO3)
CLK
DI(IO0)
SPI_PCH_DO3_64
SPI_CLK64
SPI_DO64
W25Q64FVSSIQ_SO8
RPC11
C
/CS
DO(IO1)
/WP(IO2)
GND
SPI_CLK64
+3.3V_SPI
CC6
2
0.1U_0402_25V6
8
7
6
5
SPI_DIN64
SPI_DO64
SPI_CLK64
SPI_PCH_DO3_64
+3.3V_SPI
1
32Mb Flash ROM
33_0804_8P4R_5%
CC7
2
0.1U_0402_25V6
UC3
RPC12
SPI_PCH_DO3
SPI_PCH_CLK
SPI_PCH_DO
SPI_PCH_DIN
1
2
3
4
8
7
6
5
SPI_PCH_CS1#
RC50 1
2 0_0402_5%
SPI_PCH_DO2
RC55 1
2 33_0402_5%
1
2
3
4
SPI_PCH_CS1#_R
SPI_DIN32
SPI_PCH_DO2_32
SPI_PCH_DO3_32
SPI_CLK32
SPI_DO32
SPI_DIN32
/CS
DO/IO1
/WP/IO2
GND
VCC
/HOLD/IO3
CLK
DI/IO0
8
7
6
5
SPI_PCH_DO3_32
SPI_CLK32
SPI_DO32
W25Q32FVSSIQ_SO8
C
33_0804_8P4R_5%
1
@EMC@
CC13
<29>
<29>
<29,6>
MMI ‐‐‐>
Reserve for EMI
CLK_PCIE_MMI#
CLK_PCIE_MMI
MMICLK_REQ#
+3.3V_RUN
+3.3V_RUN
<28>
<28>
<28>
10/100/1G LAN ‐‐‐>
WLAN (NGFF1)‐‐‐>
RPC6
4
3
2
1
5
6
7
8
LANCLK_REQ#
mCARD_PCIE#_SATA
MPCIE_RST#
<6>
HDD_DET#
<20,6>
<36,6>
GPU‐‐‐>
WGIG‐‐‐>
B
PCIE1
H12 UMA SD card
PCIE2 PCIE3 PCIE4
PCIE5
WLAN
WIGIG
NA
LOM
RC66 1
MMICLK_REQ#
2 10K_0402_5%
CLK_PCIE_LAN#
CLK_PCIE_LAN
LANCLK_REQ#
<30>
CLK_PCIE_WLAN#
<30>
CLK_PCIE_WLAN
<12,30>
WLANCLK_REQ#
10K_8P4R_5%
PCB
BDW_ULT_DDR3L
UC1F
<40>
<40>
<40>
CLK_PCIE_GFX#
CLK_PCIE_GFX
GFXCLK_REQ#
+3.3V_RUN
<30>
CLK_PCIE_WIGIG#
<30>
CLK_PCIE_WIGIG
<30,6>
WIGIGCLK_REQ#
PCIE6
M2 3042
(HCA & SATA-Cache)
H12 Entry SD card
NA
LOM
WLAN
WIGIG
NA
H14 DSC SD card
NA
LOM
WLAN
GPU
WIGIG
H14 UMA SD card
NA
LOM
WLAN
WIGIG
M2 3042
(HCA & SATA-Cache)
PCH_GPIO19
C43
C42
U2
B41
A41
Y5
LANCLK_REQ#
C41
B42
AD1
WLANCLK_REQ#
B38
C37
N1
A39
B39
U5
RC68
1
2 10K_0402_5%
WIGIGCLK_REQ#
B37
A37
T2
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18
XTAL24_IN
XTAL24_OUT
RSVD
RSVD
DIFFCLK_BIASREF
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLOCK
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20
SIGNALS
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
WLAN
GPU
WIGIG
H14U_En SD card
NA
LOM
WLAN
WIGIG
NA
H15 DSC SD card
NA
LOM
WLAN
GPU
WIGIG
H15 UMA SD card
NA
LOM
WLAN
WIGIG
M2 3042
(HCA & SATA-Cache)
K21
M21
C26
CLK_BIASREF
C35
C34
AK8
AL8
MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4
AN15
AP15
PCI_CLK_LPC_0
PCI_CLK_LPC_1
RC72 1
2 22_0402_5%
H15U_En SD card
5
NA
NA
LOM
LOM
WLAN
WLAN
GPU
WIGIG
EMC@
RC74 1
2 22_0402_5%
PCI_CLK_LPC_1 EMC@
RC67 1
2 22_0402_5%
EMC@
RC70 1
2 22_0402_5%
CLK_PCI_SIO
CLK_PCI_MEC
<35>
<36>
CLK_PCI_LPDEBUG
CLK_PCI_DOCK
<36>
<34>
4
1
1
1
1
2
2
2
2
RC240
RC241
RC242
RC243
RC69
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
LPC_0
LPC_1
SIO
DOCK
MEC
DEBUG
JSPI1
RC224
2
RC225
RC226
2
RC227
RC228
2
RC229
RC230
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SPI_PCH_CS1#
PCH_SPI_CS1#
SPI_PCH_DO
PCH_SPI_DO
SPI_PCH_DIN
PCH_SPI_DIN
SPI_PCH_CLK
PCH_SPI_CLK
SPI_PCH_CS0#
PCH_SPI_CS0#
SPI_PCH_DO2
PCH_SPI_DO2
SPI_PCH_DO3
PCH_SPI_DO3
+3.3V_SPI
2
RC231
1
0_0402_5%
21
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND1
GND2
TYCO_2-2041070-0
CONN@
WIGIG
Express card
2
MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4
B35
A35
+3.3V_M
H15D_En SD card
+PCH_VCCACLKPLL
1
CLK_BIASREF
3.01K_0402_1%
support SPI TPM
2
A
CC11
2
1
2 XTAL24_OUT_R
0_0402_5%
18P_0402_50V8J
BDW-ULT-DDR3L_BGA1168
6 OF 19
PCI_CLK_LPC_0 EMC@
2
LOM
1
@ RC65
B
2
NA
XTAL24_IN
XTAL24_OUT
YC2
24MHZ_12PF_X3G024000DC1H
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
2
H14D_En SD card
A25
B25
3
4
2
PCI_CLK_LPC_1
12P_0402_50V8J
PCIECLK for DSC
1
1
2
1
@EMC@
CC12
1
2
PCI_CLK_LPC_0
12P_0402_50V8J
RC63
1M_0402_5%
2
CC8
2
18P_0402_50V8J
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
7
of
56
5
4
D
UC1C
<18>
DDR_A_D[0..63]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
C
B
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
3
BDW_ULT_DDR3L
<19>
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
DDR CHANNEL A
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
AU37
AV37
AW36
AY36
M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#1
M_CLK_DDR1
AU43
AW43
AY42
AY43
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
AP33
AR32
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#1
M_CLK_DDR1
2
<18>
<18>
<18>
<18>
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
<18>
<18>
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
<18>
<18>
AP32
AY34
AW34
AU34
DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#
AU35
AV35
AY41
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
AP49
AR51
AP51
DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#
<18>
<18>
<18>
DDR_A_BS0
<18>
DDR_A_BS1
<18>
DDR_A_BS2
<18>
DDR_A_MA[0..15]
<18>
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
<18>
<18>
+SM_VREF_CA
+SM_VREF_DQ0
+SM_VREF_DQ1
BDW-ULT-DDR3L_BGA1168
3 OF 19
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
D
BDW_ULT_DDR3L
UC1D
DDR_B_D[0..63]
1
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
DDR CHANNEL B
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM38
AN38
AK38
AL38
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3
AY49
AU50
AW49
AV50
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
AM32
AK32
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3
<19>
<19>
<19>
<19>
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
<19>
<19>
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
<19>
<19>
AL32
AM35
AK35
AM33
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
AL35
AM36
AU49
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
<19>
<19>
<19>
DDR_B_BS0
<19>
DDR_B_BS1
<19>
DDR_B_BS2
<19>
DDR_B_MA[0..15]
<19>
C
DDR_B_DQS#[0..7]
<19>
DDR_B_DQS[0..7]
<19>
B
BDW-ULT-DDR3L_BGA1168
4 OF 19
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
8
of
56
5
4
3
1
@ RC77
2
1
2 0_0402_5%
+3.3V_RUN
5
B
2
A
UC5
TC7SH08FU_SSOP5~D
O
4PCH_PLTRST#_EC
PCH_PLTRST#_EC
<27,30,35,36>
<36>
PM_APWROK
SIO_SLP_A#
1
PM_APWROK
2
B
+RTC_CELL
O
A
4
PM_APWROK_R
1
1
SYS_RESET#
@ UC4
74AHC1G09GW_TSSOP5
P
PCH_PLTRST#
4
O
A
P
B
G
2
UC6
TC7SH08FU_SSOP5~D
2
3
1
1 ME_RESET#
8.2K_0402_5%
3
RC81
@ RC82
2
@ RC80
+PCH_VCCDSW3_3
D
DSWODVREN
RC78
330K_0402_5%
ME_SUS_PWR_ACK
10K_0402_5%
SUSACK#
10K_0402_5%
2 SUS_STAT#/LPCPD#
10K_0402_5%
G
2
3
2
1
G
1
XDP_DBRESET#
1
RC79
P
+3.3V_ALW_PCH
5
+3.3V_ALW2
5
+3.3V_RUN
D
RPC1
4
3
2
1
5
6
7
8
PCH_BATLOW#
AC_PRESENT
PCH_PCIE_WAKE#
PM_LANPHY_ENABLE
<12,28>
1
2
RC91
@ RC2191
@ RC87 1
@ RC88 1
@ RC89 1
@ RC2201
<22>
PLTRST_VMM2320#
<27>
PLTRST_USH#
<29>
PLTRST_MMI#
<28>
PLTRST_LAN#
<40>
PLTRST_GPU#
10K_8P4R_5%
2
2
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
DSWODVREN ‐ ON DIE DSW VR ENABLE
PCH_PLTRST#
HIGH = ENABLED (DEFAULT)
LOW = DISABLED
PCH_RSMRST#_Q
10K_0402_5%
BDW_ULT_DDR3L
UC1H
SYSTEM POWER MANAGEMENT
<36>
+3.3V_RUN
<36>
<15,36>
PM_APWROK_R
PCH_PLTRST#
ME_RESET#
8.2K_0402_5%
<37>
PCH_RSMRST#_Q
<36>
ME_SUS_PWR_ACK
<36>
SIO_PWRBTN#
<36>
AC_PRESENT
<35>
SIO_SLP_WLAN#
PCH_RSMRST#_Q
ME_SUS_PWR_ACK
SIO_PWRBTN#
AC_PRESENT
PCH_BATLOW#
SIO_SLP_S0#
SIO_SLP_WLAN#
+3.3V_RUN
C
2
AW6
AV4
AL7
AJ8
AN4
AF3
AM5
DSWVRMEN
DPWROK
WAKE
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
RSMRST
SUSWARN/SUSPWRDNACK/GPIO30
PWRBTN
ACPRESENT/GPIO31
BATLOW/GPIO72
SLP_S0
SLP_WLAN/GPIO29
UC7 XDP@
14
2 TDO_XDP
0_0402_5%
1
2 TDI_XDP_R
0_0402_5%
5
4
RUNPWROK
<6>
PCH_JTAG_TMS
PCH_JTAG_TMS
12
TRST#_XDP
13
RUNPWROK
RUNPWROK
9
10
RUNPWROK
<35,36>
AJ6
AT4
AL5
AP4
AJ7
3
1B
CPU_XDP_TDO
1OE
2A
6
2B
CPU_XDP_TDI
3A
8
3B
Place near JXDP1
<13>
<13>
CFG0
CFG1
<13>
<13>
CFG2
CFG3
11
4B
4OE
CPU_XDP_TRST#
RC5 need to close to JCPU1
7
GND
<15>
15
H_VCCST_PWRGD
CFG2
CFG3
XDP_OBS0_R
XDP_OBS1_R
3OE
4A
CFG0
CFG1
<13>
<13>
CFG4
CFG5
CFG4
CFG5
CFG6
<13>
CFG6
2 1K_0402_5%
CFG7
RC102 1
<13>
CFG7
XDP@
2 1K_0402_5%
H_CPUPWRGD @ RC103 1
H_VCCST_PWRGD_XDP
SIO_PWRBTN#
74CBTLV3126BQ_DHVQFN14_2P5X3
<15>
PCH_JTAG_TRST#
2
0_0402_5%
1
CPU_XDP_TRST#
RC109 XDP@
<6>
PCH_JTAG_JTAGX
2
0_0402_5%
1
CPU_XDP_TCLK
RC112 XDP@
<18,19,20,7>
<18,19,20,7>
CPU_PWR_DEBUG#
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
<6>
PCH_JTAG_TCK
SYS_PWROK
CPU_XDP_TCLK
1
TDI_XDP_R
RC118 @
1
1
2
RC123
10K_0402_5%
@EMC@
CC83
100P_0402_50V8J
H_PROCHOT#
PECI_EC
1
RC121
2
<18,19>
DDR3_DRAMRST#
<18>
DDR_PG_CTRL
A
D61
K61
N62
H_PROCHOT#_R
56_0402_5%
K63
H_CPUPWRGD
C61
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC123
CFG17
CFG16
CFG8
CFG9
CFG8
CFG9
CFG10
CFG11
CFG10
CFG11
<13>
<13>
CFG19
CFG18
CFG19
CFG18
<13>
<13>
CFG12
CFG13
CFG12
CFG13
<13>
<13>
CFG14
CFG15
CFG14
CFG15
<13>
<13>
XDP_RST#_R
XDP_DBRESET#
TDO_XDP
TRST#_XDP
PCH_JTAG_TDI
PCH_JTAG_TMS
1
CFG3_R
RC113
XDP@
<13>
<13>
<13>
<13>
2
RC106
XDP@
1
PCH_PLTRST#_EC
1K_0402_5%
2
CFG3
1K_0402_5%
+1.05V_RUN
AU60
AV60
AU61
AV15
AV61
PROC_DETECT
CATERR
PECI
PROCPWRGD
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1
@
RC117
XDP_DBRESET#
2
1
2
MISC
PRDY
PREQ
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO
JTAG
PROCHOT
B
1
CC21 XDP@
0.1U_0402_25V6
<36>
H_CATERR#
PECI_EC
@ CC22
0.1U_0402_25V6
BDW_ULT_DDR3L
UC1B
EMI request add
<36,52,54>
C
Place near JXDP1.48
SYS_PWROK
H_CPUPWRGD
CFG17
CFG16
2
TDO_XDP
51_0402_5%
XDP@
RC120
1K_0402_5%
1
CPU_XDP_TCLK
RC119 @
H_PROCHOT#
2
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
+3.3V_ALW_PCH
@EMC@
CC20
22P_0402_50V8J
1
SIO_SLP_S0#
1
TDO_XDP
RC115 @
PCH_JTAG_TCK 2
0_0402_5%
2
SYS_RESET#
SAMTE_BSH-030-01-L-D-A CONN@
2
0_0402_5%
2
PCH_JTAG_TDO
0_0402_5%
1
GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
2
2
B
<6>
H_CATERR#
49.9_0402_1%
2
H_PROCHOT#
62_0402_5%
PCH_RTCRST#
PCH_RTCRST#
POWER_SW#_MB
+1.05V_RUN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
CPU_XDP_PREQ#
CPU_XDP_PRDY#
CPU_XDP_TMS
reference Shark Bay ULT Validation Customer Debug Port
Implementation Requirement Rev 1.0
1
@ RC114
1
RC116
<6>
<36,39>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND
GND
JXDP1
2OE
GND PAD
+1.05V_VCCST
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
+PCH_VCCDSW3_3
<30>
+1.05V_RUN
1A
2
PCH_JTAG_TDI 1
RC99
XDP@
PCH_JTAG_TDI
CLKRUN#
CLKRUN#
<12,35,36>
SUS_STAT#/LPCPD#
1
2
SUSCLK_R
SUSCLK
SIO_SLP_S5# @
@RC136
RC136
0_0402_5%
SIO_SLP_S5#
<36>
T8
PAD~D@
T9
PAD~D @
SIO_SLP_S4#
SIO_SLP_S4#
<36,49>
SIO_SLP_S3#
SIO_SLP_S3#
<36,49>
SIO_SLP_A#
SIO_SLP_A#
<36,50>
SIO_SLP_SUS#
SIO_SLP_SUS#
<36>
SIO_SLP_LAN#
SIO_SLP_LAN#
<28,36>
VCC
1
2
RUNPWROK
<6>
V5
AG4
AE6
AP5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SIO_SLP_S3#
+PCH_VCCDSW3_3
CONN@
ACES_50506-01841-P01
@ CC19
0.1U_0402_25V6
1
RC98
XDP@
JAPS1
+3.3V_ALW_PCH
PCH_DPWROK
<36>
PCH_PCIE_WAKE#
<35,36>
+1.05V_RUN
@ CC18
0.1U_0402_25V6
PCH_JTAG_TDO
DSWODVREN
PCH_DPWROK
PCH_PCIE_WAKE#
BDW-ULT-DDR3L_BGA1168
8 OF 19
CC17 XDP@
1
0.1U_0402_25V6
<6>
SLP_S4
SLP_S3
SLP_A
SLP_SUS
SLP_LAN
AW7
AV5
AJ5
1
@ RC95
SUSACK
SYS_RESET
SYS_PWROK
PCH_PWROK
APWROK
PLTRST
1
2
SYS_PWROK
RESET_OUT#
AK2
AC3
AG2
AY7
AB5
AG7
2
1
SUSACK#
SYS_RESET#
SYS_PWROK
SUSACK#
THERMAL
J62
K62
E60
E61
E59
F63
F62
CPU_XDP_PRDY#
CPU_XDP_PREQ#
CPU_XDP_TCLK
CPU_XDP_TMS
CPU_XDP_TRST#
CPU_XDP_TDI
CPU_XDP_TDO
J60
H60
H61
H62
K59
H63
K60
J61
XDP_OBS0_R
XDP_OBS1_R
XDP_OBS2_R
XDP_OBS3_R
XDP_OBS4_R
XDP_OBS5_R
XDP_OBS6_R
XDP_OBS7_R
Place near JXDP1.47
+3.3V_RUN
2
XDP_DBRESET#
1K_0402_5%
+1.05V_RUN
DDR3L
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
T10
T11
T12
T13
T14
T15
1
@
RC124
2
1
@
RC125
2
1
@
RC126
2
1
CPU_XDP_TCLK 2
51_0402_5%
CPU_XDP_TRST# 2
51_0402_5%
1
CPU_XDP_TMS
51_0402_5%
CPU_XDP_TDI
51_0402_5%
CPU_XDP_PREQ#
51_0402_5%
CPU_XDP_TDO
51_0402_5%
PWR
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
1 RC122
@
@
@
@
@
@
BDW-ULT-DDR3L_BGA1168
2 OF 19
2
1
RC127
RC128
@
RC129
A
DDR3 COMPENSATION SIGNALS
200_0402_1%
121_0402_1%
100_0402_1%
2
1 RC130
SM_RCOMP0
2
1 RC131
SM_RCOMP1
2
1 RC132
SM_RCOMP2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
1
Sheet
9
of
56
5
4
3
2
1
D
D
BDW_ULT_DDR3L
UC1A
<24>
<24>
<24>
<24>
<24>
<24>
<24>
<24>
DDI1_LANE_N0
DDI1_LANE_P0
DDI1_LANE_N1
DDI1_LANE_P1
DDI1_LANE_N2
DDI1_LANE_P2
DDI1_LANE_N3
DDI1_LANE_P3
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
DDI2_LANE_N0
DDI2_LANE_P0
DDI2_LANE_N1
DDI2_LANE_P1
DDI2_LANE_N2
DDI2_LANE_P2
DDI2_LANE_N3
DDI2_LANE_P3
C54
C55
B58
C58
B55
A55
A57
B57
C51
C50
C53
B54
C49
B50
A53
B53
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
DDI
EDP
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
EDP_RCOMP
EDP_DISP_UTIL
C45
B46
A47
B47
EDP_CPU_LANE_N0
EDP_CPU_LANE_P0
EDP_CPU_LANE_N1
EDP_CPU_LANE_P1
EDP_CPU_LANE_N0
EDP_CPU_LANE_P0
EDP_CPU_LANE_N1
EDP_CPU_LANE_P1
COMPENSATION PU FOR eDP
<23>
<23>
<23>
<23>
+VCCIOA_OUT
C47
C46
A49
B49
2
EDP_COMP
24.9_0402_1%
A45
B45
EDP_CPU_AUX#
EDP_CPU_AUX
D20
A43
EDP_COMP
EDP_CPU_AUX#
EDP_CPU_AUX
1
RC133
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
<23>
<23>
C
C
BDW-ULT-DDR3L_BGA1168
1 OF 19
+3.3V_RUN
RPC15
5
6
7
8
+3.3V_RUN
4
3
2
1
3.3V_TP_EN
<12>
CAM_MIC_CBL_DET#
USH_DET#
<12,27>
PCH_GPIO69
<12>
BDW_ULT_DDR3L
UC1I
<12,23>
RPC2
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
10K_8P4R_5%
1
2
RC134
DGPU_PWR_EN
10K_0402_5%
1
2
2
1
@ RC139
@ RC140
ENVDD_PCH
100K_0402_5%
PCH_GPIO53
1K_0402_5%
<23>
<23>
<23,36>
EDP_BIA_PWM
PANEL_BKLEN
ENVDD_PCH
<12,27>
CONTACTLESS_DET#
<12,35,44,53>
DGPU_PWROK
<12,20>
HDD_FALL_INT
<12>
PCH_GPIO80
@ T16
PAD~D
<12>
TOUCHPAD_INTR#
<6>
PCH_GPIO52
<40,44>
DGPU_PWR_EN
EDP_BIA_PWM
PANEL_BKLEN
ENVDD_PCH
DGPU_PWROK
HDD_FALL_INT
DGPU_PWR_EN
PCH_GPIO53
B
B8
A9
C6
U6
P4
N4
N2
AD4
U7
L1
L3
R5
L4
EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
eDP SIDEBAND
PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME
DISPLAY
PCIE
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
DDPB_HPD
DDPC_HPD
EDP_HPD
B9
C9
D9
D11
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
C5
B6
B5
A6
CPU_DPB_AUX#
CPU_DPC_AUX#
CPU_DPB_AUX
CPU_DPC_AUX
CPU_DPC_AUX#
C8
A8
D6
DPB_HPD
DPC_HPD
EDP_CPU_HPD
CPU_DPC_AUX
<24>
<24>
1
2
3
4
8
7
6
5
2.2K_0804_8P4R_5%
<25>
<25>
DPB_HPD
<24>
DPC_HPD
<25>
EDP_CPU_HPD
<23>
RPC20
1
2
3
4
CPU_DPB_AUX#
CPU_DPB_AUX
CPU_DPC_AUX
CPU_DPC_AUX#
8
7
6
5
B
100K_0804_8P4R_5%
BDW-ULT-DDR3L_BGA1168
9 OF 19
2
EDP_CPU_HPD
100K_0402_5%
2
DPC_HPD
100K_0402_5%
1
RC141
1
RC142
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
10
of
56
5
4
<40>
PEG_CRX_GTX_P[0..3]
<40>
PEG_CRX_GTX_N[0..3]
<40>
PEG_CTX_GRX_P[0..3]
<40>
D
PEG_CTX_GRX_N[0..3]
3
PCIE for DSC
PEG_CRX_GTX_N[0..3]
PEG_CTX_GRX_P[0..3]
PEG_CTX_GRX_N[0..3]
CC86
CC87
PEG_CTX_GRX_N1
PEG_CTX_GRX_P1
CC88
CC89
2
2
1 0.22U_0402_16V7K
1 0.22U_0402_16V7K
1 0.22U_0402_16V7K
1 0.22U_0402_16V7K
PEG_CRX_GTX_N0
PEG_CRX_GTX_P0
F10
E10
PEG_CTX_GRX_C_N0
PEG_CTX_GRX_C_P0
C23
C22
PEG_CRX_GTX_N1
PEG_CRX_GTX_P1
GPU ‐‐>
2
2
CC90
CC91
1 0.22U_0402_16V7K
1 0.22U_0402_16V7K
B23
A23
PEG_CRX_GTX_N2
PEG_CRX_GTX_P2
H10
G10
PEG_CTX_GRX_C_N2
PEG_CTX_GRX_C_P2
B21
C21
PEG_CRX_GTX_N3
PEG_CRX_GTX_P3
2
2
CC92
CC93
10/100/1G LAN ‐‐‐>
C
WLAN (Mini Card 2)‐‐‐>
MMI ‐‐>
1 0.22U_0402_16V7K
1 0.22U_0402_16V7K
<28>
<28>
PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
<28>
<28>
PCIE_PTX_GLANRX_N3
PCIE_PTX_GLANRX_P3
<30>
<30>
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
<30>
<30>
PCIE_PTX_WLANRX_N4
PCIE_PTX_WLANRX_P4
<29>
<29>
PCIE_PRX_MMITX_N1
PCIE_PRX_MMITX_P1
<29>
<29>
PCIE_PTX_MMIRX_N1
PCIE_PTX_MMIRX_P1
<31>
<31>
<31>
<31>
+PCH_AUSB3PLL
PEG_CTX_GRX_C_N3
PEG_CTX_GRX_C_P3
B22
A21
G11
F11
PCIE_PTX_GLANRX_N3
PCIE_PTX_GLANRX_P3
C29
B30
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
F13
G13
PCIE_PTX_WLANRX_N4
PCIE_PTX_WLANRX_P4
B29
A29
PCIE_PRX_MMITX_N1
PCIE_PRX_MMITX_P1
G17
F17
PCIE_PTX_MMIRX_N1
PCIE_PTX_MMIRX_P1
C30
C31
F15
G15
B31
A31
USB3TN4
USB3TP4
1
E6
F6
PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
USB3RN4
USB3RP4
RC149
F8
E8
PEG_CTX_GRX_C_N1
PEG_CTX_GRX_C_P1
2 3.01K_0402_1% PCH_PCIE_RCOMP
E15
E13
A27
B27
D
BDW_ULT_DDR3L
UC1K
PEG_CTX_GRX_N0
PEG_CTX_GRX_P0
PEG_CTX_GRX_N3
PEG_CTX_GRX_P3
1
PEG_CRX_GTX_P[0..3]
2
2
PEG_CTX_GRX_N2
PEG_CTX_GRX_P2
2
PERN5_L0
PERP5_L0
USB2N0
USB2P0
PETN5_L0
PETP5_L0
USB2N1
USB2P1
PERN5_L1
PERP5_L1
USB2N2
USB2P2
PETN5_L1
PETP5_L1
USB2N3
USB2P3
PERN5_L2
PERP5_L2
USB2N4
USB2P4
PETN5_L2
PETP5_L2
USB2N5
USB2P5
PERN5_L3
PERP5_L3
USB2N6
USB2P6
PETN5_L3
PETP5_L3
USB2N7
USB2P7
PERN3
PERP3
PETN3
PETP3
USB3RN1
USB3RP1
PCIE
USB
PERN4
PERP4
USB3TN1
USB3TP1
USB3RN2
USB3RP2
PETN4
PETP4
USB3TN2
USB3TP2
AN8
AM8
USBP0USBP0+
AR7
AT7
USBP1USBP1+
AR8
AP8
USBP2USBP2+
AR10
AT10
USBP3USBP3+
AM15
AL15
USBP4USBP4+
AM13
AN13
USBP5USBP5+
AP11
AN11
USBP6USBP6+
AR13
AP13
USBP7USBP7+
G20
H20
C33
B34
E18
F18
B33
A33
USBP0USBP0+
<31>
<31>
‐‐‐‐‐> Ext Port 1
USBP1USBP1+
<32>
<32>
‐‐‐‐‐> Ext Port 2 charge
USBP2USBP2+
<30>
<30>
‐‐‐‐‐> WLAN/BT
H12 Entry
USBP3USBP3+
<31>
<31>
‐‐‐‐‐> Ext Port 3
H14 DSC WWAN
USBP4USBP4+
<23>
<23>
‐‐‐‐‐> Touch
USBP5USBP5+
<23>
<23>
‐‐‐‐‐> Camera
USBP6USBP6+
<27>
<27>
‐‐‐‐‐> USH
H14D_En
NA
USBP7USBP7+
<30>
<30>
‐‐‐‐‐> WWAN
H14U_En
NA
USB3RN1
USB3RP1
<31>
<31>
USB3TN1
USB3TP1
<31>
<31>
USB3RN2
USB3RP2
<32>
<32>
USB3TN2
USB3TP2
<32>
<32>
H12 UMA WWAN
USBRBIAS
USBRBIAS
RSVD
RSVD
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
RSVD
RSVD
PCIE_RCOMP
PCIE_IREF
AJ10
AJ11
AN10
AM10
AL3
AT1
AH2
AV3
H15 DSC WWAN
‐‐‐‐‐> Ext USB3 Port 1
C
H15 UMA WWAN
‐‐‐‐‐> Ext USB3 Port 2 charge
H15D_En
NA
H15U_En Express
USBRBIAS
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
NA
H14 UMA WWAN
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
USB2 7
PCB
USB_OC0#
USB_OC1#
USB_OC2#
‐‐‐‐‐>
<12,31>
<32> ‐‐‐‐‐>
‐‐‐‐‐>
<12,31>
USB Port0(JUSB1)
USB Port1(JUSB3)
USB Port3(JUSB2)
+3.3V_ALW_PCH
BDW-ULT-DDR3L_BGA1168
11 OF 19
RPC19
B
4
3
2
1
USB_OC3#
PCB
PCIE1
PCIE2 PCIE3 PCIE4
PCIE5
<7>
<12,37>
PCIE6
PCH_GPIO73
KB_DET#
USB_OC1#
B
5
6
7
8
10K_8P4R_5%
LOM
WLAN
WIGIG
H12 Entry SD card
NA
LOM
WLAN
WIGIG
NA
H14 DSC SD card
NA
LOM
WLAN
GPU
WIGIG
H14 UMA SD card
NA
LOM
WLAN
WIGIG
M2 3042
(HCA & SATA-Cache)
H14D_En SD card
NA
LOM
WLAN
GPU
WIGIG
H14U_En SD card
NA
LOM
WLAN
WIGIG
NA
H15 DSC SD card
NA
LOM
WLAN
GPU
WIGIG
USBRBIAS
2
1
NA
A
H15 UMA SD card
NA
LOM
WLAN
WIGIG
M2 3042
(HCA & SATA-Cache)
H15D_En SD card
NA
LOM
WLAN
GPU
WIGIG
H15U_En SD card
5
NA
LOM
WLAN
Express card
WIGIG
4
RC152
22.6_0402_1%
H12 UMA SD card
M2 3042
(HCA & SATA-Cache)
CAD NOTE:
Route single‐end 50‐ohms and max 500‐mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15
mils.
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
11
of
56
5
4
3
2
1
+PCH_VCCDSW3_3
change to LAN_WAKE#
2
+1.05V_VCCST
1 LAN_WAKE#
10K_0402_5%
RC153
2
H_THERMTRIP#
1K_0402_5%
1
RC25
+3.3V_RUN
D
D
+3.3V_RUN
2
1
2
1
MPHYP_PWR_EN
100K_0402_5%
SIO_EXT_SCI#
100K_0402_5%
RC155
RC156
RPC17
5
6
7
8
PCH_GPIO85
3.3V_TS_EN
<10,20>
HDD_FALL_INT
BDW_ULT_DDR3L
UC1J
4
3
2
1
10K_8P4R_5%
<28,9>
<36>
SIO_EXT_WAKE#
PM_LANPHY_ENABLE
@T21
<28,36>
PAD~D
PCH_GPIO76
SIO_EXT_WAKE#
HOST_ALERT1_R_N
PCH_GPIO16
PCH_GPIO17
LAN_WAKE#
LAN_WAKE#
NFC_IRQ
AG6
AP1
AL4
AT5
AK4
AB6
U4
PCH_GPIO48
Y3
DGPU_HOLD_RST#
TOUCH_PANEL_INTR# P3
Y2
MPHYP_PWR_EN
AT3
KB_DET#
AH4
TPM_PIRQ#
AM4
3.3V_CAM_EN#
AG5
SIO_EXT_SMI#
AG3
PCH_GPIO46
MEDIACARD_RST#
PCH_GPIO57
SLATE_MODE
PCH_GPIO59
PCH_GPIO44
+3.3V_ALW_PCH
<29>
RPC10
C
P1
AU2
AM7
AD6
Y1
T3
AD5
AN5
AD7
AN3
4
3
2
1
5
6
7
8
PCH_GPIO44
USB_OC0#
<11,31>
USB_OC2#
<11,31>
MEDIACARD_IRQ#
@ T24 PAD~D
<40>
DGPU_HOLD_RST#
<23>
TOUCH_PANEL_INTR#
<38>
MPHYP_PWR_EN
<11,37>
KB_DET#
<27>
TPM_PIRQ#
<23>
3.3V_CAM_EN#
<36>
SIO_EXT_SMI#
10K_8P4R_5%
RPC5
4
3
2
1
5
6
7
8
PCH_GPIO46
SIO_EXT_SMI#
MEDIACARD_RST#
MEDIACARD_IRQ#
10K_8P4R_5%
<20>
<36>
RPC7
4
3
2
1
@ T27 PAD~D
mSATA_DEVSLP
<30>
5
6
7
8
SLATE_MODE
SIO_EXT_WAKE#
PCH_GPIO9
PCH_SMB_ALERT#
HDD_DEVSLP
SIO_EXT_SCI#
<21>
SPKR
PCH_GPIO9
PCH_GPIO10
SIO_EXT_SCI#
SPKR
AM3
AM2
P2
C4
L2
N5
V2
BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46
CPU/
MISC
THRMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD
D60
V4
T4
AW15
AF20
AB21
H_THERMTRIP#_R
SIO_RCIN#
IRQ_SERIRQ
PCH_OPI_COMP
@ 0_0402_5%2
1 RC161
H_THERMTRIP#
<36>
SIO_RCIN#
<12,36>
IRQ_SERIRQ
<35,36>
CPPE#
100K_0402_5%
FFS_INT2
100K_0402_5%
PCH_GPIO67
10K_0402_5%
PCH_GPIO68
10K_0402_5%
2
1
2
1
2
1
2
1
RC160
RC158
RC163
RC164
RPC16
GPIO
SERIAL IO
GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81
<7>
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2
PCH_GPIO85
BBS_BIT
PCH_GPIO87
3.3V_TS_EN
3.3V_HDD_EN
CPPE#
CPUSB#
GC6_EVENT#
<40>
GPU_GC6_FB_EN
<40,44>
<35,6>
<10>
<12,36>
SATA2_PCIE6_L1
TOUCHPAD_INTR#
SIO_RCIN#
5
6
7
8
PCH_GPIO16
10K_8P4R_5%
PAD~D
@ T109
3.3V_TP_EN
3.3V_TS_EN
<10>
<23>
RPC3
<10,35,44,53>
DGPU_PWROK
<30,7>
<10>
WLANCLK_REQ#
PCH_GPIO80
5
TOUCH_PANEL_INTR#6
7
8
PCH_GPIO57
10K_0402_5%
2
1
2
1
PCH_GPIO59
100K_0402_5%
TPM_PIRQ#
10K_0402_5%
RC244
RC245
RC247
C
FFS_INT2
LCD_CBL_DET#
I2C0_SDA
I2C0_SCL
I2C1_SDA_VMM
I2C1_SCL_VMM
USH_DET#
CAM_MIC_CBL_DET#
PCH_GPIO66
PCH_GPIO67
PCH_GPIO68
RPC4
FFS_INT2
<20>
LCD_CBL_DET#
<23>
<10,27>
CONTACTLESS_DET#
I2C1_SDA_VMM
<22>
I2C1_SCL_VMM
<22>
USH_DET#
<10,27>
CAM_MIC_CBL_DET#
<10,23>
PCH_GPIO69
5
6
7
8
LCD_CBL_DET#
CPUSB#
PCH_GPIO76
4
3
2
1
10K_8P4R_5%
RPC8
1
2
3
4
I2C1_SDA_VMM
I2C1_SCL_VMM
I2C0_SDA
I2C0_SCL
<10>
8
7
6
5
2.2K_0804_8P4R_5%
10K_8P4R_5%
1
4
3
2
1
10K_8P4R_5%
BDW-ULT-DDR3L_BGA1168
10 OF 19
2
4
3
2
1
RPC9
5
6
7
8
IRQ_SERIRQ
3.3V_HDD_EN
PCH_GPIO87
<35,36,9>
CLKRUN#
4
3
2
1
10K_8P4R_5%
+3.3V_RUN
B
+3.3V_ALW_PCH
HOST_ALERT1_R_N
TOP‐BLOCK SWAP OVERRIDE
BOOT BIOS STRAP BIT BBS
TLS CONFIDENTIALITY
HIGH depop RC288
HIGH
LOW(DEFAULT)
HIGH
LOW(DEFAULT)
LOW pop RC288 (DEFAULT)
LPC
SPI
ENABLE
DISABLE
1
PCH_OPI_COMP
49.9_0402_1%
@ RC180
1K_0402_5%
2
+3.3V_RUN
RC179
1K_0402_5%
PCH_GPIO66
1
1
RC175
@ RC171
2
1
2
RC174
1
2
3.3V_CAM_EN#
100K_0402_5%
NFC_IRQ
100K_0402_5%
MPHYP_PWR_EN
10K_0402_5%
2
1
@ RC176
1K_0402_5%
2
1
B
2
RC178
SPKR
NO REBOOT STRAP
HIGH
LOW(DEFAULT)
ENABLE
DISABLE
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
12
of
56
5
4
3
2
1
D
D
CFG STRAPS for CPU
BDW_ULT_DDR3L
CFG0
CFG8
CFG9
CFG10
AA62
U63
AA61
U62
V63
CFG_RCOMP
A5
E1
D1
J20
H18
B12
TDI_IREF
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RESERVED
RSVD
RSVD
RSVD
PROC_OPI_RCOMP
CFG16
CFG18
CFG17
CFG19
RSVD
RSVD
CFG_RCOMP
VSS
VSS
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
TD_IREF
AV63
AU63
PAD~D T28@
PAD~D T29@
C63
C62
B43
PAD~D T30@
PAD~D T31@
A51
B51
PAD~D T33@
PAD~D T34@
L60
PAD~D T35@
2
CFG16
CFG18
CFG17
CFG19
CFG4
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
EAR‐STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE
CFG0
N60
C
W23
Y22
AY15 PROC_OPI_RCOMP
CFG1
AV62
D58
P22
N21
P20
R20
PCH/PCH LESS MODE SELECTION
BDW-ULT-DDR3L_BGA1168
19 OF 19
CFG1
2
1
1
2
RC185
RC186
1:(Default) Normal Operation; No stall
0:Lane Reversed
1
<9>
<9>
<9>
<9>
AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
CFG0
CFG1
@ RC184
1K_0402_1%
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
2
C
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
@ RC183
1K_0402_1%
1
UC1S
CFG_RCOMP
49.9_0402_1%
TDI_IREF
8.2K_0402_1%
PROC_OPI_RCOMP
49.9_0402_1%
1
1:(Default) Normal Operation
0:Lane Reversed
2
RC187
B
B
CFG9
CFG8
CFG4
1
2
2
1
2
2
RC191
1K_0402_5%
NO SVID PROTOCOL CAPABLE VR CONNECTED
1: VRS support SVID protocol are present
0:No VR support SVID is present
CFG9
The chip will not generate(OR Respond to)
SVID activity
@ RC190
1K_0402_1%
SAFE MODE BOOT
1: POWER FEATURES ACTIVATED DURING
RESET
CFG10
0: POWER FEATURES (ESPECIALLY CLOCK
GATINE ARE NOT ACTIVATED
@ RC189
1K_0402_1%
@ RC188
1K_0402_1%
1
1
CFG10
Display Port Presence Strap
ALLOW THE USE OF NOA ON LOCKED UNITS
1: Enable(Default): Noa will be disable in
locked units and enable in un‐locked
CFG8
units
0:
Enable Noa will be available pegardless of
the locking of the unit
CFG4
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
13
of
56
5
4
3
2
1
D
D
2
1
1
@ RC192
0_0402_5%
BDW_ULT_DDR3L
UC1Q
AY2
DC_TEST_AY2_AW2
AY3
DC_TEST_AY3_AW3
AY60
DC_TEST_AY60
AY61
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62 AY62
B2
TP_DC_TEST_B2
B3
DC_TEST_A3_B3
B61
DC_TEST_A61_B61
B62
B63
DC_TEST_B62_B63
C1
C2
DC_TEST_C1_C2
C
DAISY_CHAIN_NCTF_AY2
DAISY_CHAIN_NCTF_AY3
DAISY_CHAIN_NCTF_AY60
DAISY_CHAIN_NCTF_AY61
DAISY_CHAIN_NCTF_AY62
DAISY_CHAIN_NCTF_B2
DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_B61
DAISY_CHAIN_NCTF_B62
DAISY_CHAIN_NCTF_B63
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
DC_TEST_A3_B3
DC_TEST_A4
DC_TEST_A60
DC_TEST_A61_B61
DC_TEST_A62
DC_TEST_AV1
DC_TEST_AW1
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
DC_TEST_AW63
2
2
0_0402_5%
2
0_0402_5%
1
@ RC193
1
@ RC194
4
C
BDW-ULT-DDR3L_BGA1168
17 OF 19
3
2
0_0402_5%
A3
A4
A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63
1
@ RC195
Package Daisy Chain:
1.B2‐PKG‐C1‐PCB‐C2‐PKG‐B3‐PCB‐A3‐PKG‐A4
2.A62‐PKG‐A61‐PCB‐B61‐PKG‐B62‐PCB‐B63‐PKG‐A60
3.AY60‐PKG‐AW61‐PCB‐AY61‐PKG‐AW62‐PCB‐AY62‐PKG‐AW63
4.AW1‐PKG‐AW3‐PCB‐AY3‐PKG‐AW2‐PCB‐AY2‐PKG‐AV1
UC1R
AT2
AU44
AV44
D15
B
F22
H22
J21
BDW_ULT_DDR3L
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
N23
R23
T23
U10
B
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
AL1
AM11
AP7
AU10
AU15
AW14
AY14
BDW-ULT-DDR3L_BGA1168
18 OF 19
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
14
of
56
5
4
3
2
1
ESD Request
+VCCIO_OUT
+VCC_CORE
+1.35V_MEM
1
@ RC198
10K_0402_5%
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
CC34
10U_0603_6.3V6M
@ CC33
10U_0603_6.3V6M
CC32
10U_0603_6.3V6M
CC31
10U_0603_6.3V6M
@ CC30
10U_0603_6.3V6M
+3.3V_RUN
1
@EMC@ CC85
CC29
10U_0603_6.3V6M
2
22U_0603_6.3V6M
CC28
2.2U_0402_6.3V6M
2
22U_0603_6.3V6M
1
@EMC@ CC84
CC27
2.2U_0402_6.3V6M
1
@EMC@ CC79
+1.05V_RUN
CPU_PWR_DEBUG#
VDDQ DECOUPLING
+VCC_CORE
2
+1.05V_RUN
@ CC26
2.2U_0402_6.3V6M
2
0_0603_5%
2
22U_0603_6.3V6M
@ CC25
2.2U_0402_6.3V6M
D
+1.35V_MEM
1
@EMC@ CC23
RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES
RC197
150_0402_1%
1
+1.05V_RUN
1
1
2
@ RC196
2
+1.05V_RUN
D
2
22U_0603_6.3V6M
H_VCCST_PWRGD
+1.05V_VCCST
2
2
H_VR_EN
1.5K_0402_5%
1
@ RC199
10K_0402_5%
1
1
@EMC@
2
+VCC_CORE
CC24
100P_0402_50V8J
UC1L
L59
J58
+1.35V_MEM
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
H_VR_READY
RC201
+3.3V_ALW
C
<36,9>
2
RESET_OUT#
3
NC
5
VCC
A
4
Y
1
@ CC35
2
0.1U_0402_25V6
1
UC8
1
RC202
1K_0402_5%
2
+1.05V_VCCST
+VCC_CORE
H_VCCST_PWRGD
GND
VCCSENSE
74AUP1G07GW_TSSOP5
+VCCIO_OUT
+VCCIOA_OUT
+1.05V_VCCST
<52>
2
VIDALERT_N
CPU_PWR_DEBUG#
H_CPU_SVIDALRT#
RC207
@ T74
@ T75
@ T76
@ T77
VIDSOUT
PAD~D
PAD~D
PAD~D
PAD~D
L62
N63
L63
B59
F60
C59
D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59
+1.05V_VCCST
AC22
AE22
AE23
+VCC_CORE
AB57
AD57
AG57
C24
C28
C32
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
HSW ULT POWER
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC
C
B
BDW-ULT-DDR3L_BGA1168
12 OF 19
+1.05V_RUN
+1.05V_VCCST
@PJP23
@
PJP23
2
1
2
CAD Note: RC209 SHOULD BE PLACED CLOSE TO CPU
A
CC37
1U_0402_6.3V6K
PAD-OPEN1x1m
1
1
VCCSENSE
CC36
22U_0603_6.3V6M
VCCSENSE
E63
AB23
A59
E20
AD23
AA23
AE59
RSVD
RSVD
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
@
2
1
+VCC_CORE
RC209
100_0402_1%
<52>
<9>
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
H_VCCST_PWRGD
H_VR_EN
H_VR_READY
CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 ‐ 1500mils
VIDSOUT
VCC_SENSE
H_VCCST_PWRGD
H_VR_EN
H_VR_READY
2
2
<52>
1
<9>
<52>
<52>
VIDSCLK
+1.05V_VCCST
RC208
110_0402_1%
SVID DATA
B
CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 ‐
1500mils
2
43_0402_5%
1
<52>
RC204
75_0402_1%
1
SVID ALERT
F59
N58
AC58
BDW_ULT_DDR3L
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
15
of
56
5
4
3
+1.05V_M
+1.05V_RUN
+
2
1
1
2
1
2
1
1
2
1
+
@EMC@ CC42
330U_D3_2.5VY_R6M
+
@EMC@ CC41
330U_2.5V_M
CC40
1U_0402_6.3V6K
CC44
1U_0402_6.3V6K
@ CC43
1U_0402_6.3V6K
CC40 place near K9;
CC44 place near L10
CC43 place near M9
VCCHSIO
S0 Iccmax = 1.838A
@ CC39
330U_D3_2.5VY_R6M
2
0_0805_5%
2
1
@ RC210
D
1
+1.05V_MODPHY_PCH
2
+1.05V_MODPHY
2
D
+RTC_CELL
DCPSUS4
AC20
AG16
AG17
CC72 place near AG16
+1.05V_RUN
2
2
2
+3.3V_ALW_PCH
2
1
RC212 @
2
1
RC213 @
0_0402_5%
+3.3V_ALW
CC73
1U_0402_6.3V6K
BDW-ULT-DDR3L_BGA1168
13 OF 19
+PCH_RTC_VCCSUS3_3
CC72
1U_0402_6.3V6K
RSVD
VCC1_05
VCC1_05
1
1
AB8
+1.05V_RUN
USB2
1
1
2
CC69 place near U8
LPT LP POWER
SUS OSCILLATOR
2
1
2
1
2013/06/10 refer 6L_WP chnage to float,6/14 change back
U8
T9
C
+PCH_VCC1P05
0_0402_5%
1
VCCSDIO
VCCSDIO
2
2
@
1
2
SERIAL IO
1
+3.3V_ALW_PCH
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3
1
CC70 close to Pin J17
CC71 close to Pin R21
J18
K19
A20
J17
R21
T21
K18
M20
V21
AE20
AE21
2
1
2
1
1
1
2
1
2
2
1
2
1
2
1
2
1
+3.3V_RUN
+1.5V_RUN
CC69
1U_0402_6.3V6K
+PCH_VCCACLKPLL
CC71
1U_0402_6.3V6K
2
+PCH_VCC1P05
CC65 place near AG19
CC65
1U_0402_6.3V6K
J15
K14
K16
1
5.11_0402_1%
CC66
0.1U_0402_10V7K
THERMAL SENSOR
VCCTS1_5
VCC3_3
VCC3_3
CC61 CC62 place near AE9
2
+PCH_VCCDSW
RC211
+PCH_VCCDSW_R
GPIO/LPC
+PCH_VCCDSW
CC59
1U_0402_6.3V6K
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3
+1.05V_M
CC58
1U_0402_6.3V6K
CORE
+1.05V_RUN
CC59 and CC60 place near
J11; CC58 place near AE8
+3.3V_RUN
+1.05V_RUN
CC70
1U_0402_6.3V6K
CC68
1U_0402_6.3V6K
CC67
100U_1206_6.3V6M
CC68 place near AA21
VCCAPLL
S0 Iccmax = 57mA
VRM
DCPSUS2
J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
@ CC62
22U_0603_6.3V6M
1
2
2.2UH_LQM2MPN2R2NG0L_30%
+PCH_VCCDSW3_3
CC64 place near V8
2013/06/10 refer 6L_WP chnage to +3.3V_M, 6/14 change back
CC64
22U_0603_6.3V6M
+V1.05S_APLLOPI
LC3
+3.3V_RUN
AC9
AA9
AH10
V8
W9
HDA
VCCHDA
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
CC61
1U_0402_6.3V6K
CC63 place near AC9
C
+1.05V_RUN
AH13
+3.3V_ALW_PCH
CC63
22U_0603_6.3V6M
CC57
0.1U_0402_10V7K
CC56
22U_0603_6.3V6M
CC55
22U_0603_6.3V6M
CC56 place near B11
VCCSATA3PLL
S0 Iccmax = 42mA
AH14
CC57 place near AH14
+1.05V_M
CC60
10U_0603_6.3V6M
LC2
1
2
2.2UH_LQM2MPN2R2NG0L_30%
AG14
AG13
USB3
DCPSUS3
1
J13
2
+3.3V_ALW_PCH
2
+PCH_ASATA3PLL
CC54 place near Y8
2
VCCASW
VCCASW
+1.05V_MODPHY
+3.3V_M
Y8
1
VCCSPI
OPI
2
SPI
RSVD
VCCAPLL
VCCAPLL
AH11
+PCH_RTC_VCCSUS3_3
AG10
AE7 +DCPRRTC 1
2
CC52
0.1U_0402_10V7K
1
VCCSUS3_3
VCCRTC
DCPRTC
2
1
2
1
2
1
2
RTC
HSIO
@ CC54
0.1U_0402_10V7K
+V1.05S_APLLOPI
Y20
AA21
W21
VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL
CC50
1U_0402_6.3V6K
@ CC53
1U_0402_6.3V6K
CC47
22U_0603_6.3V6M
CC51
22U_0603_6.3V6M
+PCH_AUSB3PLL
+PCH_ASATA3PLL
K9
L10
M9
N8
P9
B18
B11
+1.05V_MODPHY_PCH
+1.05V_RUN
CC49
0.1U_0402_10V7K
LC1
1
2
2.2UH_LQM2MPN2R2NG0L_30%
CC47 place near B18
VCCUSB3PLL
S0 Iccmax = 41mA
BDW_ULT_DDR3L
UC1M
CC48
0.1U_0402_10V7K
+PCH_AUSB3PLL
1
CC48,CC49, CC50 place near AG10
+1.05V_MODPHY
CC73 place near AH11
VCCSUS3_3
S0 Iccmax = 63mA
LC4
1
2
2.2UH_LQM2MPN2R2NG0L_30%
1
2
1
2
Reminder below power rail need isolation for layout refer
attach file for more detail that from Intel review feedback.
+PCH_VCCACLKPLL
0_0402_5%
+1.05V_RUN
+3.3V_ALW
1
1
CC82
1U_0402_6.3V6K
CC82 place near A20
VCCACLKPLL
S0 Iccmax = 31mA
CC81
100U_1206_6.3V6M
@ CC80
1U_0402_6.3V6K
CC80 place near AH10
VCCDSW3_3
S0 Iccmax = 114mA
1
LC5
1
2
2.2UH_LQM2MPN2R2NG0L_30%
2 0_0402_5%
2
@ RC2171
B
+PCH_VCCDSW3_3
2
2
1
@ RC216
2
+3.3V_ALW_PCH
CC78
1U_0402_6.3V6K
B
CC77
100U_1206_6.3V6M
CC78 place near J18
VCCCLK
S0 Iccmax = 200mA
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
1
Sheet
16
of
56
5
4
3
2
1
D
D
UC1N
A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
C
B
BDW_ULT_DDR3L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
UC1O
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
BDW_ULT_DDR3L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
BDW_ULT_DDR3L
UC1P
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
VSS
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
C
V58
AH46
V23
E62
AH16
VSSSENSE
<52>
BDW-ULT-DDR3L_BGA1168
16 OF 19
B
VSSSENSE
RC218
BDW-ULT-DDR3L_BGA1168
15 OF 19
1
2
100_0402_1%
CAD Note: RC218 SHOULD BE PLACED CLOSE TO CPU
BDW-ULT-DDR3L_BGA1168
14 OF 19
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
17
of
56
5
3
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D6
+0.675V_DDR_VTT
1
2
1
2
1
2
1
2
1
2
2
DDR_A_D17
DDR_A_D16
DDR_A_D36
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D62
DDR_A_D58
DDR_A_D60
DDR_A_D61
1
2
@ RD15
0_0402_5% +3.3V_RUN
0_0402_5%
+0.675V_DDR_VTT
2
205
207
GND1
BOSS1
GND2
BOSS2
1
2
1
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1
M_CLK_DDR#1
<8>
<8>
DDR_A_BS1
DDR_A_RAS#
<8>
<8>
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_CS0_DIMMA#
M_ODT1
DDR_A_D3
DDR_A_D7
2
1
<8>
+SM_VREF_CA_DIMM
DDR_A_D18
DDR_A_D19
+5V_ALW
DDR3L SODIMM ODT GENERATION
+1.35V_MEM
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D22
DDR_A_D23
DDR_A_D37
DDR_A_D32
1
3
1
RD10
1
RD11
1
RD12
1
RD13
0.675V_DDR_VTT_ON
DDR_A_D35
DDR_A_D39
DDR_A_D63
DDR_A_D59
DDR_A_DQS#7
DDR_A_DQS7
B
QD1
FDV301N_NL_SOT23-3~D
2
M_ODT0
66.5_0402_1%
2
M_ODT1
66.5_0402_1%
2
66.5_0402_1%
2
66.5_0402_1%
M_ODT2
<19>
M_ODT3
<19>
need change to SB503010080
+1.35V_MEM
DDR_A_D56
DDR_A_D57
UD1
1
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
<19,20,7,9>
<19,20,7,9>
<9>
DDR_PG_CTRL
+0.675V_DDR_VTT
2
3
206
208
NC
VCC
A
Y
5
4
1
@ CD30
2
0.1U_0402_25V6
0.675V_DDR_VTT_ON
0.675V_DDR_VTT_ON
<49>
GND
74AUP1G07GW_TSSOP5
A
E
N
O
D
K
N
I
L
BELLW_80001-1021
CONN@
0
0
7
P
0
0
0
7
0
P
S
CD32
0.1U_0402_25V6
A
@ CD31
2.2U_0402_6.3V6M
1
@ RD16
1
2
2
1
DDR_A_MA2
DDR_A_MA0
DDR_A_D5
DDR_A_D4
2
2_0402_1%
RD5
DDR_A_MA6
DDR_A_MA4
C
+SM_VREF_DQ0
1
DDR_A_MA11
DDR_A_MA7
@ RD14
2M_0402_5%
DDR_A_D34
DDR_A_D38
+DIMM1_VREF_DQ
RD9
220K_0402_5%
CD29
10U_0603_6.3V6M
CD28
10U_0603_6.3V6M
CD27
0.1U_0402_25V6
CD26
0.1U_0402_25V6
CD25
0.1U_0402_25V6
CD24
0.1U_0402_25V6
1
DDR_A_D21
DDR_A_D20
<8>
CD23
2.2U_0402_6.3V6M
DDR_A_D0
DDR_A_D1
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
RD7
24.9_0402_1%
<8>
<8>
<8>
<8>
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE1_DIMMA
CD22
0.1U_0402_25V6
Layout Note:
Place near
JDIMM1.203,204
M_CLK_DDR0
M_CLK_DDR#0
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
2
DDR_A_MA3
DDR_A_MA1
<8>
<8>
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
1
DDR_A_MA8
DDR_A_MA5
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
DDR_A_MA12
DDR_A_MA9
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
CD21
0.022U_0402_16V7K
2
DDR_A_BS2
+1.35V_MEM
DDR_A_D54
DDR_A_D55
1
DDR_CKE0_DIMMA
CAD NOTE
PLACE THE CAP NEAR TO DIMM RESET PIN
DDR_A_DQS#6
DDR_A_DQS6
RD6
1.8K_0402_1%
CD20
330U_D3_2.5VY_R6M
CD19
10U_0603_6.3V6M
CD18
10U_0603_6.3V6M
CD17
10U_0603_6.3V6M
@ CD16
10U_0603_6.3V6M
CD15
10U_0603_6.3V6M
CD14
10U_0603_6.3V6M
@ CD13
10U_0603_6.3V6M
CD12
10U_0603_6.3V6M
+
DDR_A_BS2
DDR_A_D52
DDR_A_D53
2
DDR_CKE0_DIMMA
<8>
<19,9>
DDR_A_D42
DDR_A_D46
S
<8>
DDR3_DRAMRST#
RD4
1.8K_0402_1%
+1.35V_MEM
C
DDR3_DRAMRST#
D
DDR_A_D49
DDR_A_D48
DDR_A_D45
DDR_A_D40
2
G
DDR_A_D51
DDR_A_D50
DDR_A_D27
DDR_A_D26
1
DDR_A_D43
DDR_A_D47
DDR3_DRAMRST#
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
CD11
1U_0402_6.3V6K
CD10
1U_0402_6.3V6K
CD4
1U_0402_6.3V6K
CD9
1U_0402_6.3V6K
CD8
1U_0402_6.3V6K
CD3
1U_0402_6.3V6K
CD2
1U_0402_6.3V6K
CD7
1U_0402_6.3V6K
1
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D25
DDR_A_D24
2
+1.35V_MEM
+1.35V_MEM
1
DDR_A_D44
DDR_A_D41
D
DDR_A_D15
DDR_A_D11
@ CD6
0.1U_0402_25V6
DDR_A_D30
DDR_A_D31
DDR_A_DQS#1
DDR_A_DQS1
470_0402_5%
RD2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D9
DDR_A_D12
1
DDR_A_D14
DDR_A_D10
DDR_A_D29
DDR_A_D28
Layout Note:
Place near JDIMM1
B
+1.35V_MEM
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
2
2
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
1
D
DDR_A_D13
DDR_A_D8
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
2
1
DDR_A_MA[0..15]
CD1
0.1U_0402_25V6
CD5
2.2U_0402_6.3V6M
<8>
1
JDIMM1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
1
DDR_A_DQS[0..7]
+1.35V_MEM
2
<8>
+DIMM1_VREF_DQ
1
DDR_A_D[0..63]
2
H=4mm
Reverse Type
DDR_A_DQS#[0..7]
<8>
2
<8>
4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Rev
A
4019RA
Date:
Thursday, November 14, 2013
1
Sheet
18
of
56
5
+1.35V_MEM
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
<8>
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_CS3_DIMMB#
DDR_B_D3
DDR_B_D7
DDR_B_D21
DDR_B_D20
+0.675V_DDR_VTT
1
2
1
2
1
2
1
2
1
2
2
DDR_B_D36
DDR_B_D33
CD62
10U_0603_6.3V6M
CD61
10U_0603_6.3V6M
CD60
0.1U_0402_25V6
CD59
0.1U_0402_25V6
CD58
0.1U_0402_25V6
CD57
0.1U_0402_25V6
1
DDR_B_D22
DDR_B_D23
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D35
DDR_B_D39
DDR_B_D52
DDR_B_D49
DDR_B_D48
DDR_B_D53
+3.3V_RUN
+3.3V_RUN
GND1
BOSS1
GND2
BOSS2
1
2
1
2
1
1
2
1
2
<8>
C
+1.35V_MEM
1
+DIMM2_VREF_DQ
DDR_B_MA6
DDR_B_MA4
2
DDR_B_MA11
DDR_B_MA7
+SM_VREF_DQ1
1
DDR_B_MA2
DDR_B_MA0
RD23
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
<8>
<8>
<8>
<8>
DDR_CS2_DIMMB#
M_ODT2
<18>
M_ODT3
1
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
2_0402_1%
2
M_CLK_DDR3
M_CLK_DDR#3
<8>
<18> +SM_VREF_CA_DIMM
DDR_B_D5
DDR_B_D0
DDR_B_D2
DDR_B_D6
2
B
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D19
DDR_B_D18
DDR_B_D37
DDR_B_D32
DDR_B_D34
DDR_B_D38
DDR_B_D51
DDR_B_D55
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D50
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
<18,20,7,9>
<18,20,7,9>
+0.675V_DDR_VTT
206
208
A
BELLW_80001-1021
CONN@
E
N
O
D
K
N
I
L
2
2
205
207
0
0
7
P
0
0
0
7
0
P
S
CD64
0.1U_0402_25V6
@ CD63
2.2U_0402_6.3V6M
@ RD28
0_0402_5%
A
1
+0.675V_DDR_VTT
2
0_0402_5%
1
1
1
2
@ RD27
DDR_CKE3_DIMMB
DDR_B_MA15
DDR_B_MA14
CD56
2.2U_0402_6.3V6M
DDR_B_DQS#0
DDR_B_DQS0
DDR_CKE3_DIMMB
CD55
0.1U_0402_25V6
DDR_B_D4
DDR_B_D1
Layout Note:
Place near
JDIMM2.203,204
DDR_B_D63
DDR_B_D62
RD25
24.9_0402_1%
<8>
<8>
<8>
DDR_B_MA10
DDR_B_BS0
DDR_B_DQS#7
DDR_B_DQS7
1
M_CLK_DDR2
M_CLK_DDR#2
2_0402_1%
2
<8>
<8>
M_CLK_DDR2
M_CLK_DDR#2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
CAD NOTE
PLACE THE CAP NEAR TO DIMM RESET PIN
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
DDR_B_MA3
DDR_B_MA1
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
2
RD24
1.8K_0402_1%
2
DDR_B_MA8
DDR_B_MA5
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
1
RD19
DDR_B_D47
DDR_B_D43
DDR_B_D61
DDR_B_D60
+SM_VREF_CA
CD54
0.022U_0402_16V7K
+
CD53
330U_D3_2.5VY_R6M
CD52
10U_0603_6.3V6M
CD51
10U_0603_6.3V6M
CD50
10U_0603_6.3V6M
CD49
10U_0603_6.3V6M
CD48
10U_0603_6.3V6M
@ CD47
10U_0603_6.3V6M
@ CD46
10U_0603_6.3V6M
CD45
10U_0603_6.3V6M
1
DDR_B_MA12
DDR_B_MA9
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
+SM_VREF_CA_DIMM
2
DDR_B_BS2
DDR_B_BS2
DDR_B_D45
DDR_B_D44
<18,9>
RD22
1.8K_0402_1%
+1.35V_MEM
DDR_CKE2_DIMMB
DDR_CKE2_DIMMB
<8>
DDR3_DRAMRST#
DDR_B_D30
DDR_B_D31
1
<8>
C
DDR3_DRAMRST#
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
DDR_B_D59
DDR_B_D58
DDR_B_D25
DDR_B_D24
RD21
24.9_0402_1%
DDR_B_D56
DDR_B_D57
CD44
1U_0402_6.3V6K
CD43
1U_0402_6.3V6K
CD42
1U_0402_6.3V6K
CD41
1U_0402_6.3V6K
CD40
1U_0402_6.3V6K
CD39
1U_0402_6.3V6K
CD38
1U_0402_6.3V6K
CD37
1U_0402_6.3V6K
2
DDR_B_D46
DDR_B_D42
D
+1.35V_MEM
DDR_B_D13
DDR_B_D15
CD36
0.022U_0402_16V7K
DDR_B_DQS#5
DDR_B_DQS5
+1.35V_MEM
DDR_B_DQS#1
DDR_B_DQS1
RD20
1.8K_0402_1%
DDR_B_D40
DDR_B_D41
DDR_B_D12
DDR_B_D9
@ CD35
0.1U_0402_25V6
DDR_B_D26
DDR_B_D27
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
RD18
1.8K_0402_1%
DDR_B_DQS#3
DDR_B_DQS3
Layout Note:
Place near JDIMM2
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
2
DDR_B_D10
DDR_B_D11
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
1
DDR_B_D8
DDR_B_D14
DDR_B_D28
DDR_B_D29
B
+1.35V_MEM
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
2
1
2
1
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
CD34
0.1U_0402_25V6
DDR_B_MA[0..15]
CD33
2.2U_0402_6.3V6M
DDR_B_DQS[0..7]
<8>
1
JDIMM2
DDR_B_D[0..63]
<8>
2
H=4mm
Reverse Type
+DIMM2_VREF_DQ
DDR_B_DQS#[0..7]
<8>
D
3
2
<8>
4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Rev
A
4019RA
Date:
Thursday, November 14, 2013
Sheet
1
19
of
56
4
3
2
1
SATA Repeater
@ RN1
100K_0402_5%
<6>
<6>
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
<6>
<6>
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
CN23 1
CN30 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_PTX_DRX_P1_C 1
SATA_PTX_DRX_N1_C 2
CN25 1
CN26 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_PRX_DTX_N1_C 4
SATA_PRX_DTX_P1_C 5
21
TDet_B# TDet_A#
A_EQ
B_EQ
A_EM
B_EM
EN
TDeT_EN
AI+
AI-
AO+
AO-
BOBO+
BIBI+
3
2
13
19 HDD_B_EQ
8 HDD_B_PRE
18
<12>
FFS_INT2
FFS_INT2
2
15 SATA_PTX_DRX_P1_RP
14 SATA_PTX_DRX_N1_RP
12 SATA_PRX_DTX_N1_RP
11 SATA_PRX_DTX_P1_RP
4
6
10
20
1
VDD
VDD
QN1B
DMN66D0LDW-7_SOT363-6
HDD_A_EQ
HDD_A_PRE
3
17
9
7
FFS_INT2_Q
5
QN1A
DMN66D0LDW-7_SOT363-6
DEW2
DEW1
2
RN2
100K_0402_5%
2
UN2
6
16 NC
NC
1
CN24
0.1U_0402_25V6
D
CN29
0.01U_0402_16V7K
1
1
+3.3V_RUN
1
+5V_HDD
+3.3V_HDD
2
5
D
GND
+3.3V_RUN
PI3EQX6741STZDEX_TQFN20_4X4
2nd: SA00003ZX00 S IC SN75LVCP601RTJR QFN20 SATA REDRIVER
+3.3V_RUN
2
RN4
TI SN75LVCP601RTJR
Pin6/16, de-emphasis width setup
Pin8/9, de-emphasis
C
1
DDR_XDP_WAN_SMBDAT
2.2K_0402_5%
DDR_XDP_WAN_SMBCLK
2.2K_0402_5%
2
2
1
1
CN2
0.1U_0402_25V6
2
RN3
CN1
10U_0603_6.3V6M
1
PERICOM PI3EQX6741ST:
Pin6/16, NC
Pin8/9, Pre-emphasis
Free Fall Sensor
UN1
<10,12>
HDD_FALL_INT
11
9
FFS_INT2
7
6
4
+3.3V_HDD
<18,19,7,9>
<18,19,7,9>
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
2
1
10
13
15
16
RES
RES
RES
RES
VDD_IO
VDD
INT 1
INT 2
5
12
GND
GND
SDO/SA0
SDA / SDI / SDO
SCL/SPC
NC
CS
NC
2
3
LNG3DMTR_LGA16_3X3
2
1
1
2
2
1
2
1
2
@RN20
@
RN20
200K_0402_5%
@ RN18
200K_0402_5%
@RN14
@
RN14
100K_0402_5%
@RN12
@
RN12
100K_0402_5%
@RN10
@
RN10
200K_0402_5%
@RN8
@
RN8
200K_0402_5%
1
8
HDD_A_PRE
C
LNG3DM
1
14
HDD_B_PRE
+3.3V_HDD
HDD_A_EQ
1
HDD_B_EQ
2
@ RN5
HDD_DEVSLP
10K_0402_5%
DEW2
B
B
JSATA1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
SATA_PTX_DRX_P1_RP CN19 2
SATA_PTX_DRX_N1_RP CN20 2
1 0.01U_0402_16V7K SATA_PTX_DRX_P1_RP_C
1 0.01U_0402_16V7K SATA_PTX_DRX_N1_RP_C
SATA_PRX_DTX_N1_RP CN18 2
SATA_PRX_DTX_P1_RP CN17 2
1 0.01U_0402_16V7K SATA_PRX_DTX_N1_RP_C
1 0.01U_0402_16V7K SATA_PRX_DTX_P1_RP_C
@ PJP4
1
2
+3.3V_HDD
+3.3V_RUN
1
2
1
2
1
2
1
2
1
1
@RN21
@
RN21
0_0402_5%
@RN19
@
RN19
0_0402_5%
@RN16
@
RN16
100K_0402_5%
@RN13
@
RN13
100K_0402_5%
@RN11
@
RN11
0_0402_5%
@RN9
@
RN9
0_0402_5%
2
DEW1
PAD-OPEN1x1m
<12>
HDD_DEVSLP
<6,7>
HDD_DET#
@ PJP5
+5V_HDD
+3.3V_HDD
+5V_RUN
1
2
+5V_HDD
PAD-OPEN1x1m
1
2
1
2
1
2
2
CN16
0.1U_0402_25V6
@ CN15
0.1U_0402_25V6
CN14
0.1U_0402_25V6
E
N
O
D
K
N
I
L
0
0
L
6
1
0
0
1
0
P
S
CN13
1000P_0402_50V7K
1
FFS_INT2_Q
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
G1
G2
G3
G4
ACES_50406-02071-001
CONN@
A
A
Place near HDD CONN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
20
of
56
2
1
E
N
O
D
K
N
I
L
0
0
I
W
0
0
0
2
0
P
S
I2S_DOUT
PCBEEP
I2S_LRCK
GPIO0/DMIC-CLK
GPIO1/DMIC-DATA12
SPDIF-OUT/DMIC-DATA34/GPIO2
1
1
EAPD+PD
CBP
CPVEE
VREF
LDO1-CAP
LDO2-CAP
LDO3-CAP
MIC1-VREFO
AVSS1
AVSS2
GND
35
2
0_0402_5%
30
26
37
2
2
1
2
1
2
1
2
<36>
<23>
<23>
1U_0603_10V6K
2
1
1 1U_0603_10V6K
CA49 2
CA35
2.2U_0402_6.3V6M
+MIC1_VREF_OUT
DMIC_CLK1
place close to pin2
place close to RA14 pin2
ALC3235-CG_MQFN48_6X6
@ PJP9
1
+5V_RUN
MIC1_L
CA43
1
MIC1_R
CA44
1
2 1
1
1
2
3
BEEP
CA29
34
25
1
1
RA36
EMC@
DMIC_CLK0
2
+5V_RUN_AUDIO
@ PJP10
1
+3.3V_RUN
2
+3.3V_RUN_AUDIO
PAD-OPEN1x1m
HP‐Out‐Right
AUD_HP_OUT_L
Nokia‐MIC
HP‐Out‐Left
2
4.7U_0603_6.3V6K
2
2
PAD-OPEN1X2m
DA5
RB751S40T1G_SOD523-2
0_0402_5%
<12>
1
place at AGND and DGND plane
1
RA35
EMC@
SPKR
Place CA29 close to Codec
36
<35>
Add for solve
pop noise and
detect issue
2
1K_0402_5%
2
1K_0402_5%
DMIC_CLK0
MIC1-R(PORT-B-R)
RA25
4.7K_0402_5%
DA4
RB751S40T1G_SOD523-2
S
AUD_HP_NB_SENSE
1
1
DMIC0
RA24
4.7K_0402_5%
2
G
1
1
0.1U_0402_25V6
RA12
1
1
0.1U_0402_25V6
RA13
2
DMIC_CLK0
2 33_0402_5% DMIC_CLK1
33_0402_5%
MIC1-L(PORT-B-L)
2
2
2
49
DMIC_CLK_L
DMIC1
D
@
CA41
0.1U_0402_25V6
QA1
L2N7002WT1G_SC-70-3
CA53
4.7U_0603_6.3V6K
AUD_SENSE_A
CA52
4.7U_0603_6.3V6K
CA51
4.7U_0603_6.3V6K
Verb table configures as 1 JD mode with
internal 47K pull high to save external rBOM.
21
39
7
2
2
2
10K_0402_5%
1
1
RA18
1
2
AUD_NB_MUTE#
AUD_NB_MUTE#
AUD_PC_BEEP
+VREFOUT
2
CA27
2
CA28
EMC@ RA14 1
EMC@ RA40 1
CA30
22P_0402_50V8J
<35>
+3.3V_RUN_AUDIO
48
12
2
4
47
RA6
1
I2S_DIN
INT_SPK_R+
INT_SPK_R-
2
1
SPK-OUT-R+
SPK-OUT-R-
I2S_SCLK
42
43
45
44
B
RA5
@
SPK-OUT-L+
SPK-OUT-LI2S_MCLK
AUD_HP_OUT_L
AUD_HP_OUT_R
AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
2
2
RESET#
31
33
32
1
RING2
2.2K_0402_5%
1
SLEEVE
2.2K_0402_5%
+VREFOUT
@EMC@
MIC-CAP
HPOUT-L(PORT-A-L)
HPOUT-R(PORT-A-R)
+VREFOUT
SLEEVE/RING2 please keep 40 mils trace width
2
10U_0603_6.3V6M
1
2
1
2 16_0402_1%
16_0402_1%
2
20
SDATA-IN
1
CA25
AUD_OUT_L
AUD_OUT_R RA7
RA8
INT_SPK_L+
INT_SPK_L-
1
MIC1_R
2
@EMC@
19
RING2
SLEEVE
1
CA54
22P_0402_50V8J
1
MIC1_L
LINE1-L(PORT-C-L)/RING2
LINE1-R(PORT-C-R)/SLEEVE
LINE1-VREFO
SYNC
CBN
CA31
1U_0603_10V6K
@EMC@ CA33
10P_0402_50V8J
BCLK: Audio serial data bus bit clock input/output
LRCK: Audio serial data bus word clock input/output
2
2
24
DAI_DI
SDATA-OUT
2
<34>
2
1
DAI_LRCK#
28
29
23
2
place close to pin45
BCLK
2
DAI_DO#
<34>
AUD_SENSE_A
AUD_SENSE_B
2 1
@EMC@ RA17
33_0402_5%
<34>
2
+5V_RUN_PVDD
13
14
22
1
CA26
1U_0603_10V4Z
PCH_AZ_CODEC_BITCLK
15
I2S_MCLK
22_0402_5%
16
2 I2S_BCLK
22_0402_5%
2 I2S_DO
Place RA32 close to codec 17
33_0402_5%
18
1
EMC@ RA30
1
EMC@ RA31
1
RA32
DAI_BCLK#
11
2
1
1
2
1
PCH_AZ_CODEC_RST#
DAI_12MHZ#
<34>
1
2
1
2
3
3
2
1
1
1
1
2
2
2
2
1
2
1
<34>
8
PCH_AZ_SDIN0_R
PCH_AZ_CODEC_RST#
Close to U17 pin6
2
2
33_0402_5%
HP/MIC1 JD(JD1)
I2S_IN/I2S_OUT JD(JD2)
TV Mode/LINE1-JD (JD3)
+VDDA_PVDD
place close to pin39
CA48
10U_0603_6.3V6M
1
RA9
DVDD
38
41
46
@ RA39
0_0805_5%
Place R136 close to codec
PCH_AZ_CODEC_SDIN0
<6>
5
10
PCH_AZ_CODEC_SYNC
CPVDD
PVDD1
PVDD2
1
CA47
0.1U_0402_25V6
<6>
PCH_AZ_CODEC_SDOUT
6
DVDD_IO
27
40
CA46
10U_0603_6.3V6M
PCH_AZ_CODEC_SDOUT
<6>
PCH_AZ_CODEC_BITCLK
AVDD1
AVDD2
CA45
0.1U_0402_25V6
<6>
2
I2S I/F Float
+1.5V_RUN_AUDIO
place close to pin38
CA18
4.7U_0603_6.3V6K
Close to U17
B
Place closely to Pin 13.
1
EN_I2S_NB_CODEC#
9
PCH_AZ_CODEC_BITCLK
1
UA1
<35>
3
<6>
place close to pin38
CA17
0.1U_0402_25V6
GND
GND
ACES_50279-0040N-001
2
BLM15PX600SN1D_2P
CA16
4.7U_0603_6.3V6K
@EMC@ DA7
L30ESDL5V0C3-2_SOT23-3
@EMC@ CA24
1000P_0402_50V7K
@EMC@ CA19
1000P_0402_50V7K
@EMC@ CA23
1000P_0402_50V7K
@EMC@ CA22
1000P_0402_50V7K
@EMC@ DA6
L30ESDL5V0C3-2_SOT23-3
5
6
CA9
10U_0603_6.3V6M
1
2
3
4
CA8
0.1U_0402_25V6
1
2
3
4
CA50
0.1U_0402_25V6
INT_SPKR_L+
INT_SPKR_LINT_SPKR_R+
INT_SPKR_R-
BLM18PG330SN1_2P
BLM18PG330SN1_2P
BLM18PG330SN1_2P
BLM18PG330SN1_2P
CA11
0.1U_0402_25V6
2
2
2
2
+3.3V_RUN_AUDIO
CA11 close to pin9
CA10 close to pin3
CA10
4.7U_0603_6.3V6K
EMC@ LA6 1
EMC@ LA7 1
EMC@ LA8 1
EMC@ LA9 1
INT_SPK_L+
INT_SPK_LINT_SPK_R+
INT_SPK_R-
LA5
1
+VDDA_AVDD1
CONN@
JSPK1
40 mils trace keep 20 mil spacing
+5V_RUN_AUDIO
@ RA4
0_0603_5%
Internal Speakers Header
+3.3V_RUN_AUDIO
1
+1.5V_RUN
@ RA3
0_0603_5%
place close to pin27
1
+5V_RUN_AUDIO
1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.)
iPhone‐MIC
AUD_HP_OUT_R
@ PJP6
2
4.7U_0603_6.3V6K
+3.3V_RUN_AUDIO
Global Headset
1
0_0402_5%
Combo Jack
RA1
10K_0402_5%
RING2
AUD_HP_OUT_L
<35>
LA2
1
2
14
13
AUD_HP_OUT_L1
BLM15BD601SN1D_2P
SLEEVE
+3.3V_RUN_AUDIO_R
RING2
2
EMC@
DA3
SLEEVE
1
2
3
2
3
EMI De-pop
EMC@
DA2
RA2
100K_0402_5%
GND
GND
A
12
11
10
9
8
7
6
5
4
3
2
1
E-T_6705K-Y12N-40L
2
2
Realtek feedback
Prevent the Noise from Combo Jack
while system entry into S3 / S4 /S5
2
EMC@
DA1
1
AUD_NB_MUTE#
2
1
1
2
2
1
12
11
10
9
8
7
6
5
4
3
2
1
E
N
O
D
K
N
I
L
L
0
4
N
2
1
Y
K
5
0
7
6
QA2A
DMN66D0LDW-7_SOT363-6
1
6
2
1
L03ESDL5V0CC3-2_SOT23-3
QA2B
DMN66D0LDW-7_SOT363-6
4
3
AUD_HP_OUT_R1
1
L03ESDL5V0CC3-2_SOT23-3
DMIC1
DMIC_CLK1
AUD_HP_NB_SENSE
+3.3V_RUN_AUDIO_R
AUD_HP_OUT_L1
AUD_HP_OUT_R1
BLM15BD601SN1D_2P
L03ESDL5V0CC3-2_SOT23-3
6
5
4
2
@EMC@ CA4
220P_0402_50V7K
GND
VCC
LEFT/RIGHT DATA
GND
CLOCK
SPM1437HM4H-6_6P
1
@EMC@ CA3
220P_0402_50V7K
MIC1
1
2
3
LA3
@EMC@ CA2
220P_0402_50V7K
+3.3V_RUN
5
EMC@
@EMC@ CA1
220P_0402_50V7K
Digital Mic
AUD_HP_NB_SENSE
AUD_HP_OUT_R
SLEEVE
RA21
100K_0402_5%
1
+RTC_CELL
2
5
DOCK_MIC_DET
QA3B
DMN66D0LDW-7_SOT363-6
CONN@
JAUD1
EMC@
3
2
2
2
1
1
2
4
1
DOCK_HP_DET
1
RA37
EMC@
+3.3V_RUN_AUDIO
3
1
2
6
1
2
1
RA26
100K_0402_5%
2
QA3A
DMN66D0LDW-7_SOT363-6
RA27
200K_0402_5%
<35>
RA29
100K_0402_5%
A
2
PAD-OPEN1x2m
RA28
100K_0402_5%
+3.3V_RUN_AUDIO
2
+3.3V_RUN_AUDIO
100K_0402_5%
1
1
RA38
AUD_SENSE_B
Place closely to Pin 14 for DOCK only
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
21
of
56
2
1
J2
C3
C4
C11
C12
K3
K4
K11
K12
J4
+3.3V_RUN_VDDA
VDDRXA0
VDDRXA1
VDDRXA2
VDDTX0A0
VDDTX0A1
VDDTX0A2
VDDTX1A0
VDDTX1A1
VDDTX1A2
VGA_AVDD
VGA_AVDD
VGA_AVDD
VGA_AVDD
VDDSA
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDXT3V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
1
2
1
2
1
1
2
C5
D5
D6
D7
D8
D9
D10
D11
E4
E11
F4
F5
F6
F7
+3.3V_RUN_VMM
LV25
1
2
BLM15AX102SN1D_2P
UV8A
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
VMM2320_P0
VMM2320_N0
VMM2320_P1
VMM2320_N1
VMM2320_P2
VMM2320_N2
VMM2320_P3
VMM2320_N3
VMM2320_AUX
VMM2320_AUX#
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
<25>
<9>
F8
F9
F10
F11
G4
G5
2
1
2
1
2
1
2
1
2
1
1M_0402_5%
1M_0402_5%
G6
G7
G8
G9
G10
G11
H4
D4
1M_0402_5%
150_0402_1%
150_0402_1%
2
150_0402_1%
2
100K_0402_5%
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
CV102
CV103
CV104
CV105
CV106
CV107
CV108
CV109
CV110
CV111
A13
PLTRST_VMM2320#
VMM_GPIO9
RV73
SW_DPC_AUX
RV74
SW_DPB_AUX
RV75
RED_2320
RV76
GREEN_2320
RV77
BLUE_2320
RV78
LP_CTL
RV79@
J5
J11
J12
K5
H10
J6
J7
J8
J9
VMM_MESCL
VMM_MESDA
VMM_SPI_WP#
B5
B6
B1
VMM_SPI_CS#
VMM_SPI_CLK
VMM_SPI_DIN
VMM_SPI_DO
A4
B3
B4
A3
D14
D13
C14
C13
B14
B13
C1
M12
M13
L3
B2
A5
VMM_GPIO6
VMM_GPIO7
VMM_GPIO8
VMM_GPIO9
LP_CTL
1
2
1
2
2
0_0402_5%
CV113
22P_0402_50V8J
CV115
22P_0402_50V8J
YV2
27MHZ_12PF_X1E000021042600
1
1
3
CLK_27M_OUT_R
IN
OUT
@ RV81
2
4
GND GND
K2
L2
M1
M2
RV80
1M_0402_5%
IDTVMM2320BKG8_BGA168
G1
G2
F1
F2
E1
E2
D1
D2
H1
H2
C2
J1
VMM2320_P0_C
VMM2320_N0_C
VMM2320_P1_C
VMM2320_N1_C
VMM2320_P2_C
VMM2320_N2_C
VMM2320_P3_C
VMM2320_N3_C
VMM2320_AUX_C
VMM2320_AUX#_C
SRCDET
VMM2320_HPD
1
1
1
2
2
1
2
2
CV97
0.01U_0402_16V7K
CV96
0.01U_0402_16V7K
CV95
0.1U_0402_25V6
CV94
1U_0603_10V6K
1
+3.3V_RUN_VDDIO
VDDLP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H5
C10
H12
K6
K7
2
J10
K8
K9
K10
VDDXT1V
1 V Analog
1
1
2
2
1
2
H11
E12
D12
VDDTX0
VDDTX0
VDDTX1
VDDTX1
3.3V IO
1
2
1
1
2
2
1
1
2
2
1
2
1
2
1
2
1
2
CV93
0.01U_0402_16V7K
CV92
0.01U_0402_16V7K
E10
C7
C6
VDDRX
VDDRX
VDDRX_33
VDDTX0_33
VDDTX1_33
VGA_AVDD33
VGA_AVDD33
CV101
1U_0603_10V6K
E5
H3
F3
D3
+3.3V_RUN_VDDA
3.3V Analog
CV100
0.1U_0402_25V6
CV89
0.01U_0402_16V7K
CV88
0.1U_0402_25V6
J3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CV99
0.01U_0402_16V7K
CV86
0.01U_0402_16V7K
CV85
0.01U_0402_16V7K
CV84
0.1U_0402_25V6
CV91
0.1U_0402_25V6
+3.3V_RUN_VMM
LV24
1
2
BLM15AX102SN1D_2P
E3
G3
C8
C9
F12
G12
+1.05V_VMM_VDDTX
CV90
1U_0603_10V6K
B
CV87
1U_0603_10V6K
LV23
1
2
BLM15AX102SN1D_2P
CV83
0.1U_0402_25V6
CV82
1U_0603_10V6K
+1.05V_RUN_VMM
E6
E7
E8
E9
H6
H7
H8
H9
2
UV8B
+1.05V_VMM_VDD
CV98
0.01U_0402_16V7K
LV22
1
2
BLM15AX102SN1D_2P
1V Digital
+1.05V_RUN_VMM
CLK_27M_IN
K1
CLK_27M_OUT
L1
RxP0
RxN0
RxP1
RxN1
RxP2
RxN2
RxP3
RxN3
RxAUXP
RXAUXN
RxSRCDET
RxHPD
Tx0P0
Tx0N0
Tx0P1
Tx0N1
Tx0P2
Tx0N2
Tx0P3
Tx0N3
CAD0
Tx0AUXP
Tx0AUXN
Tx0DDCSCL
Tx0DDCSDA
Tx0HPD
RSTN_IN
Tx1P0
Tx1N0
Tx1P1
Tx1N1
Tx1P2
Tx1N2
Tx1P3
Tx1N3
CAD1
Tx1AUXP
Tx1AUXN
Tx1DDCSCL
Tx1DDCSDA
Tx1HPD
MESCL
MESDA
ROMWP
SPICS
SPICLK
SPIDI
SPIDO
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6/INT
GPIO7/MSCL
GPIO8/MSDA
GPIO9
LP_CTL
LP_EN
VGA_VSYNC
VGA_HSYNC
VGA_RP
VGA_RN
VGA_GP
VGA_GN
VGA_BP
VGA_BN
VGA_SCL
VGA_SDA
VGA_DET
VGA_IREF
VGA_NC
RX_STS
TX0_STS
TX1_STS
TX2_STS
SSDA
SSCL
TRSTN
TCK
TMS
TMS2
TDI
TDO
XIN
XOUT
B7
A7
B8
A8
B9
A9
B10
A10
A14
B11
A11
B12
A12
A6
E13
E14
F13
F14
G13
G14
H13
H14
M14
J13
J14
K13
L14
K14
SW_DPC_AUX
SW_DPC_AUX#
VMM_DPC_CTRLCLK
VMM_DPC_CTRLDAT
DPB_LANE_P0
<34>
DPB_LANE_N0
<34>
DPB_LANE_P1
<34>
DPB_LANE_N1
<34>
DPB_LANE_P2
<34>
DPB_LANE_N2
<34>
DPB_LANE_P3
<34>
DPB_LANE_N3
<34>
DPB_CA_DET
<25,34>
SW_DPB_AUX
<25>
SW_DPB_AUX#
<25>
VMM_DPB_CTRLCLK
<25>
VMM_DPB_CTRLDAT
<25>
DPB_DOCK_HPD
<34>
SW_DPB_AUX
SW_DPB_AUX#
VMM_DPB_CTRLCLK
VMM_DPB_CTRLDAT
L9
M9
M6
L6
M7
L7
M8
L8
L4
M4
M3
M5
L5
DPC_LANE_P0
<34>
DPC_LANE_N0
<34>
DPC_LANE_P1
<34>
DPC_LANE_N1
<34>
DPC_LANE_P2
<34>
DPC_LANE_N2
<34>
DPC_LANE_P3
<34>
DPC_LANE_N3
<34>
DPC_CA_DET
<25,34>
SW_DPC_AUX
<25>
SW_DPC_AUX#
<25>
VMM_DPC_CTRLCLK
<25>
VMM_DPC_CTRLDAT
<25>
DPC_DOCK_HPD
<34>
B
VSYNC_2320
<26>
HSYNC_2320
<26>
RED_2320
<26>
GREEN_2320
<26>
BLUE_2320
<26>
CLK_DDC2_2320
DAT_DDC2_2320
VMM2320_VGA_DET
VMM2320_VGA_IREF
VMM2320_VGA_NC
<26>
<26>
@ T108PAD~D
A1
A2
I2C1_SDA_VMM
I2C1_SCL_VMM
<12>
<12>
M11
M10
L12
L13
L11
L10
IDTVMM2320BKG8_BGA168
+3.3V_RUN_VMM
1
SW_DPB_AUX#
1M_0402_5%
1
VMM_GPIO6
2.2K_0402_5%
1
SRCDET
1M_0402_5%
2
RV82
2
RV83
2
RV84
RPV1
EEPROM
+3.3V_RUN_VMM
CV114
1
UV9
VMM_SPI_CS#
VMM_SPI_DIN
VMM_SPI_WP#
VMM_DPB_CTRLCLK
VMM_DPB_CTRLDAT
VMM_GPIO7
VMM_GPIO8
1
2
3
4
CS#
VCC
DO(IO1) HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)
2
2.2K_0804_8P4R_5%
RPV2
1
8
2
7
3
6
4
5
VMM_SPI_HOLD
VMM_SPI_CLK
VMM_SPI_DO
2.2K_0804_8P4R_5%
1
2
SW_DPC_AUX#
1M_0402_5%
RV85
2
1
VMM_SPI_CS#
10K_0402_5%
RV86
2
1
VMM_SPI_HOLD
2.2K_0402_5%
RV87
1
VMM2320_VGA_DET 2
10K_0402_5%
RV88
2
VMM2320_VGA_IREF 1
3.74K_0402_1%
RV89
W25X10CVSNIG_SO8
A
+1.05V_RUN
8
7
6
5
VMM_MESCL
VMM_MESDA
VMM_DPC_CTRLCLK
VMM_DPC_CTRLDAT
0.1U_0402_25V6
8
7
6
5
1
2
3
4
A
+1.05V_RUN_VMM
@ PJP24
1
2
PAD-OPEN1x1m
+3.3V_RUN
+3.3V_RUN_VMM
@ PJP25
1
2
PAD-OPEN1x1m
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
22
of
56
5
4
3
2
1
+5V_TSP
JEDP1
LV27
<12>
+BL_PWR_SRC
LCD_TST
3
1
3
<10>
+LCDVDD
CV1 2
CV2 2
CV3 2
CV4 2
CV5 2
CV6 2
EDP_CPU_AUX#_C
EDP_CPU_AUX_C
EDP_CPU_LANE_P0_C
EDP_CPU_LANE_N0_C
EDP_CPU_LANE_P1_C
EDP_CPU_LANE_N1_C
LCD_CBL_DET#
1
1
1
1
1
1
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
EDP_CPU_AUX#
<10>
EDP_CPU_AUX
<10>
EDP_CPU_LANE_P0
<10>
EDP_CPU_LANE_N0
<10>
EDP_CPU_LANE_P1
<10>
EDP_CPU_LANE_N1
<10>
<12>
For Touchscreen
S
D
2
1
1
2
2
G
1
2
@
2
1
<36>
2
BAT54CW_SOT323-3
PANEL_BKEN_EC
1
D
3
1
2
@
1
2
@
1
2
1
@
PANEL_BKLEN
S
2
G
3.3V_TS_EN
<10>
1
DISP_ON
BIA_PWM_EC
RV2
4.7K_0402_5%
1
BIA_PWM_EC
<12>
3
<10>
1
RV1
4.7K_0402_5%
2
2
EDP_BIA_PWM
3
<35>
QV7
L2N7002WT1G_SC-70-3
EDP_BIA_PWM
1
Close to JEDP1.1
DV2
3
+5V_RUN
QV8
LP2301ALT1G_SOT23-3
CV81
0.1U_0402_25V6
Close to JEDP1.40
+5V_TSP
RV6
47K_0402_5%
CA7
0.1U_0402_25V6
Close to JEDP1.33
C
+5V_RUN
+3.3V_RUN
CZ2
0.1U_0402_16V4Z
Close to JEDP1.11,12
+5V_TSP
CZ1
0.1U_0402_25V6
@
+3.3V_CAM
CV8
0.1U_0402_25V6
CV7
0.1U_0603_50V7K
2
+LCDVDD
DV1
BIA_PWM
<11>
<35>
C
Close to JEDP1.24~27
<11>
USBP4+
D
ACES_50398-04041-001
CONN@
+BL_PWR_SRC
USBP4-
LOOP_BACK
2
EDP_CPU_HPD
3
ESD depop location
2
BIA_PWM
BLM15BB221SN1D_2P~D
1
EMC@ LV1 1
DISP_ON
<21>
1
2
<10,12>
2
1
CAM_MIC_CBL_DET#
2
<21>
DMIC_CLK0
+3.3V_RUN
+3.3V_CAM
LOOP_BACK
4
2
DLW21HN900HQ2L_4P
DMIC0
USBP5_DUSBP5_D+
2
RZ1
1K_0402_5%
G1
G2
G3
G4
G5
TOUCH_PANEL_INTR#
EMC@
1
@EMC@ DV4
L30ESDL5V0C3-2_SOT23-3
E
N
O
D
K
N
I
L
0
0
I
3
1
0
0
1
0
P
S
41
42
43
44
45
4
@EMC@ CA6
100P_0402_50V8J
confirm 15" panel spec
1
USBP4_DUSBP4_D+
@EMC@ CA5
100P_0402_50V8J
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
BAT54CW_SOT323-3
B
B
Backlight POWER
WebCAM
+BL_PWR_SRC
+LCDVDD
+EDP_VDD
2
1
2
3
<10,36>
3
ENVDD_PCH
EN_LCDPWR
BAT54CW_SOT323-3
1
3
5
4
EN
AP2821KTR-G1_SOT23-5
3
S
2
1
47K_0402_5%
D
1
GND
VIN
1
QV2
L2N7002WT1G_SC-70-3
RV5
2
2
LCD_VCC_TEST_EN
PWR_SRC_ON
change back to CCD_OFF at Goliad project
VOUT
@
1
2
1
2
2
G
<35>
PAD-OPEN1x1m
RV3
100K_0402_5%
1
S
D
AO6405_TSOP6
CV12
0.1U_0603_50V7K
G
RV4
270K_0402_5%
CV11
1000P_0402_50V7K
3.3V_CAM_EN#
CZ3
0.1U_0402_25V6
3
1
VIN
10U_0603_6.3V6M
DV3
2
S
4
QZ1
LP2301ALT1G_SOT23-3
1
UV24
2
CV10
0.01U_0402_16V7K
6
5
2
1
@ PJP29
1
1
+3.3V_RUN
@ CV9
2
1
2
QV1
D
+3.3V_CAM
<12>
LCDVDD POWER
+3.3V_ALW
+PWR_SRC
A
<11>
USBP5+
<11>
USBP5-
4
1
2
4
3
2
USBP5_D+
3
USBP5_D-
2
G
LZ1EMC@
1
<36>
A
EN_INVPWR
DLW21HN900SQ2L_4P
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
23
of
56
5
4
3
2
1
+1.5V_RUN
LV3 EMC@
TMDSE_RP_CLK
1
TMDSE_RP_CLK#
4
1
2
4
3
2
TMDS_CON_CLK
3
TMDS_CON_CLK#
DLW21HN900HQ2L_4P
+3.3V_RUN
LV6
1
12
40
20
31
19
11
37
TMDSE_RP_N1
LV12
TMDSE_RP_P2
4
TMDSE_RP_N2
1
PD#
I2C_CTL_EN
DCIN_EN/SCL_CTL
DDCBUF/SDA_CTL
25
24
27
26
30
29
22
21
DPB_HPD
ISET
SCL_SRC
SDA_SRC
SCL_SNK
SDA_SNK
CFG
32
33
HDMI_SCL_SINK
HDMI_SDA_SINK
28
HDMI_HPD_SINK
RV7 1
RV9 1
2
2
2.2K_0402_5%
2.2K_0402_5%
HPD_SRC
1
2
HDMI_CEC
10K_0402_5%
1
@ RV8
HDMI_CEC
TMDS_CON_CLK#
TMDS_CON_CLK
TMDS_CON_N0
TMDS_CON_P0
TMDS_CON_N1
2
1
2
15
35
41
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HDMI_SDA_SINK
HDMI_SCL_SINK
+3.3V_RUN
HDMI_EQ
TMDS_CON_P1
TMDS_CON_N2
1
TMDS_CON_P2
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
B
LCN_AUF05-1922S10-0019
2
E
N
O
D
K
N
I
L
9
1
0
0
0
1
S
2
2
9
1
5
0
F
U
A
@ RV204
4.7K_0402_5%
@ RV203
4.7K_0402_5%
1
C
JHDMI1 CONN@
@ RV202
4.7K_0402_5%
@ RV201
4.7K_0402_5%
2
TMDS_CON_N2
HDMI_HPD_SINK
HDMI_BUF
Enable active DDC buffer; Internal pull up at ~150KΩ, 3.3V I/O
L: default, passive DDC pass‐through
H: active DDC buffer with default threshold
M: passive DDC pass‐through with internal ~10KΩ pull up
2
PS8401ATQFN40GTR-A3_TQFN40_5X5
+3.3V_RUN
B
TMDS_CON_P2
+VHDMI_VCC
GND
EQ//I2C_ADDR0
PRE/I2C_ADDR1
REXT
3
+5V_RUN
+VHDMI_VCC
PS8401ATQFN40GTR2-A4
2
RV200
4.32K_0402_1%
+3.3V_RUN
1
18
2
2
3
1
TMDSE_RP_P0
TMDSE_RP_N0
TMDSE_RP_P1
TMDSE_RP_N1
TMDSE_RP_P2
TMDSE_RP_N2
TMDSE_RP_CLK
TMDSE_RP_CLK#
GND
GND
GND PAD
<10>
17
16
3
DLW21HN900HQ2L_4P
OUT_D0p
OUT_D0n
OUT_D1p
OUT_D1n
OUT_D2p
OUT_D2n
OUT_CKp
OUT_CKn
HPD_SNK
HDMI_EQ
HDMI_PRE
EMC@
4
1
23
TMDS_CON_N1
2
2 4.7K_0402_5%
2
TMDS_CON_P1
2
CV27
10U_0603_6.3V6M
RV198 1
1
3
@ CV26
0.1U_0402_10V7K
+3.3V_RUN
38
39
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
3
1
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
EMC@
4
UV2
AP2330W-7_SC59-3
C
<10>
<10>
D
DLW21HN900HQ2L_4P
@
34
4
CV23
0.1U_0402_16V4Z
HDMI_ISET
13
14
LV9
TMDSE_RP_P1
2
2 4.7K_0402_5%
HDMI_BUF
TMDS_CON_N0
1
@RV197
@
RV197 1
2
TMDS_CON_P0
2
IN
+3.3V_RUN
1
3
OUT
8
3
3
36
IN_D0p
IN_D0n
IN_D1p
IN_D1n
IN_D2p
IN_D2n
IN_CKp
IN_CKn
1
1
6
TMDS_P0_C
7
TMDS_N0_C
4
TMDS_P1_C
5
TMDS_N1_C
1
TMDS_P2_C
2
TMDS_N2_C
9
TMDS_CLK_C
TMDS_CLK#_C 10
TMDSE_RP_N0
EMC@
4
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
2
4
DLW21HN900HQ2L_4P
VDDRX
VDDRX
VDDTX
VDDTX
VDDTA
1
1
1
1
1
1
1
1
VDD33
VDD33
2
2
2
2
2
2
2
2
CV28
CV29
CV21
CV22
CV17
CV18
CV13
CV14
DDI1_LANE_P2
DDI1_LANE_N2
DDI1_LANE_P1
DDI1_LANE_N1
DDI1_LANE_P0
DDI1_LANE_N0
DDI1_LANE_P3
DDI1_LANE_N3
2
1
CV373
0.1U_0402_25V6
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
2
1
CV372
0.1U_0402_25V6
UV21
2
1
CV371
0.1U_0402_25V6
2
1
CV370
0.1U_0402_25V6
2
1
CV369
0.01U_0402_16V7K
2
1
CV368
0.1U_0402_25V6
1
CV367
0.01U_0402_16V7K
D
TMDSE_RP_P0
Receiver equalization setting; Internal pull down at ~150kΩ, 3.3V I/O.
L: programmable EQ for channel loss up to 5.3dB
H: programmable EQ for channel loss up to 10dB
M: programmable EQ for channel loss up to 14dB
+3.3V_RUN
2
1
2
@RV205
@
RV205
4.7K_0402_5%
@ RV206
4.7K_0402_5%
1
+3.3V_RUN
HDMI_PRE
2
MDS output swing adjustment; Internal pull down at ~150kΩ, 3.3V I/O.
default
: increase +13%
: reduce ‐13%
1
A
2
@ RV175
4.7K_0402_5%
@RV207
@
RV207
4.7K_0402_5%
A
1
HDMI_ISET
DELL CONFIDENTIAL/PROPRIETARY
Output pre‐emphasis setting; Internal pull down at ~150kΩ, 3.3V I/O.
L: no pre‐emphasis
H: 1.6dB pre‐emphasis
M: 3.0dB pre‐emphasis
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
24
of
56
RV53
1
RV69
1
D
RV71
H12 UMA PS8339+DP12412
1
RV67
H12 Entry
1
PS8339
RV68
1
RV70
H14 DSC
1
PS8338
H14 UMA
RV72
PS8338
DDI2_LANE_P0
DDI2_LANE_N0
<10>
<10>
DDI2_LANE_P1
DDI2_LANE_N1
<10>
<10>
DDI2_LANE_P2
DDI2_LANE_N2
<10>
<10>
DDI2_LANE_P3
DDI2_LANE_N3
1
CV71 1
CV72
1
CV73 1
CV74
1
CV75 1
CV76
1
CV77 1
CV78
1
2
1
2
1
2
1
2
1
2
2 OUT1_CA_DET
1M_0402_5%
2 OUT2_CA_DET
1M_0402_5%
2 VMM2320_AUX
100K_0402_5%
2 WIGIG_AUX
100K_0402_5%
<10>
<10>
2
DDI2_LANE_P0_C
2 0.1U_0402_25V6DDI2_LANE_N0_C
0.1U_0402_25V6
2
DDI2_LANE_P1_C
2 0.1U_0402_25V6DDI2_LANE_N1_C
0.1U_0402_25V6
2
DDI2_LANE_P2_C
2 0.1U_0402_25V6DDI2_LANE_N2_C
0.1U_0402_25V6
2
DDI2_LANE_P3_C
2 0.1U_0402_25V6DDI2_LANE_N3_C
0.1U_0402_25V6
+3.3V_RUN
H15 UMA
PS8338B_P0
PS8338
H15D_En
1
CV79 1
CV80
CPU_DPC_AUX
CPU_DPC_AUX#
PS8338B_PC11
PS8338B_PC20
DP12412
@ RV66
4.7K_0402_5%
2
1
@ RV65
4.7K_0402_5%
2
1
@ RV63
4.7K_0402_5%
2
1
@ RV64
4.7K_0402_5%
2
1
@ RV62
4.7K_0402_5%
2
1
12
13
15
16
4
3
2
1
60
11
19
52
61
PS8338B_PEQ
50
49
OUT1_D0p
OUT1_D0n
47
46
OUT1_D1p
OUT1_D1n
IN_D0p
IN_D0n
OUT1_D2p
OUT1_D2n
IN_D1p
IN_D1n
OUT1_D3p
OUT1_D3n
IN_D2p
IN_D2n
45
44
42
41
40
39
OUT2_D0p
OUT2_D0n
IN_D3p
IN_D3n
37
36
OUT2_D1p
OUT2_D1n
35
34
OUT2_D2p
OUT2_D2n
IN_CA_DET
IN_HPD
I2C_CTL_EN
Pl1/SCL_CTL
Pl0/SDA_CTL
32
31
OUT2_D3p
OUT2_D3n
OUT1_AUXp_SCL
OUT1_AUXn_SDA
IN_DDC_SCL
IN_DDC_SDA
IN_AUXp
IN_AUXn
OUT2_AUXp_SCL
OUT2_AUXn_SDA
CFG0
CFG1
PC10
PC11
PC20
PC21
OUT1_CA_DET
OUT1_HPD
OUT2_CA_DET
OUT2_HPD
SW
PEQ
PD
CEXT
REXT
GND
GND
GND
PAD(GND)
26
27
VMM2320_AUX
VMM2320_AUX#
28
29
WIGIG_AUX
WIGIG_AUX#
43
48
OUT1_CA_DET
33
38
OUT2_CA_DET
18
8
14
17
20
PS8338_SW
PS8338B_PEQ
1
<22>
<22>
VMM2320_P1
VMM2320_N1
<22>
<22>
VMM2320_P2
VMM2320_N2
<22>
<22>
VMM2320_P3
VMM2320_N3
<22>
<22>
WIGIG_LANE_P0
WIGIG_LANE_N0
<30>
<30>
WIGIG_LANE_P1
WIGIG_LANE_N1
<30>
<30>
WIGIG_LANE_P2
WIGIG_LANE_N2
<30>
<30>
WIGIG_LANE_P3
WIGIG_LANE_N3
<30>
<30>
VMM2320_AUX
VMM2320_AUX#
WIGIG_HPD
<34>
DPB_DOCK_AUX
1
2
2
1 SW_DPB_AUX_C
CV119
0.1U_0402_10V7K
DPB_DOCK_AUX
3
B
<22>
<34>
SW_DPB_AUX#
DPB_DOCK_AUX#
4
5
2
1 SW_DPB_AUX#_C
CV120
0.1U_0402_10V7K
DPB_DOCK_AUX#
6
7
VCC
BE3
B0
A3
BE1
A1
B3
BE2
B1
A2
GND
B2
14
13
12
<22>
VMM_DPB_CTRLCLK
<22>
<34>
11
10
9
<22>
VMM_DPB_CTRLDAT
<22>
<34>
SW_DPC_AUX
2
CV122
DPC_DOCK_AUX
SW_DPC_AUX#
DPC_DOCK_AUX#
2
CV123
1
2
1
SW_DPC_AUX_C
0.1U_0402_10V7K
DPC_DOCK_AUX
3
4
5
1
SW_DPC_AUX#_C
0.1U_0402_10V7K
DPC_DOCK_AUX#
6
8
7
PI3C3125LEX_TSSOP14~D
1
CV121
2
BE0
A0
VCC
BE3
B0
A3
BE1
A1
B3
BE2
B1
A2
GND
B2
14
13
12
VMM_DPC_CTRLCLK
<22>
B
11
10
9
VMM_DPC_CTRLDAT
<22>
8
PI3C3125LEX_TSSOP14~D
D
S
1
2
RV91
100K_0402_5%
RV90
100K_0402_5%
1
+3.3V_RUN_VMM
3
+3.3V_RUN_VMM
1
C
UV12
BE0
A0
2
<22>
<30>
0.1U_0402_25V6
UV11
SW_DPB_AUX
<30>
<30>
+3.3V_RUN_VMM
0.1U_0402_25V6
<22>
D
<22>
<22>
WIGIG_AUX
WIGIG_AUX#
AUX/DDC SW for DPC to E‐DOCK
VC118
2
VMM2320_P0
VMM2320_N0
VMM2320_HPD
PS8338BQFN60GTR-A0_QFN60_5X9
+3.3V_RUN_VMM
AUX/DDC SW for DPB to E‐DOCK
9
10
22
23
2
CPU_DPC_AUX_C 24
2 0.1U_0402_25V6 CPU_DPC_AUX#_C 25
0.1U_0402_25V6
59
PS8338_CFG0
58
56
PS8338B_PC10
55
PS8338B_PC11
54
PS8338B_PC20
53
PS8338B_PC21
PS8338B_PC21
DP12412
6
7
VDD33
VDD33
VDD33
VDD33
VDD33
CV60
2.2U_0402_6.3V6M
H15U_En
UV7
5
21
30
51
57
for support TMDS signal need contact SCL/SDA to P22,23
<10>
<10>
PS8338B_PC10
@ RV61
4.7K_0402_5%
2
1
C
@ RV60
4.7K_0402_5%
2
1
PS8338
@ RV58
4.7K_0402_5%
2
1
H15 DSC
@ RV57
4.7K_0402_5%
2
1
DP12412
DPC_HPD
PS8338B_P1
PS8338B_P0
@ RV56
4.7K_0402_5%
2
1
H14U_En
<10>
@ RV55
4.7K_0402_5%
2
1
DP12412
@ RV54
4.7K_0402_5%
2
1
H14D_En
Dock has high priority when both ports plugged
1
@
DP SWITCH
PCB
CV70
0.1U_0402_25V6
1
CV69
0.1U_0402_25V6
1
RV52
CV66
0.1U_0402_25V6
2 PS8338_CFG0
4.7K_0402_5%
2 PS8338_SW
4.7K_0402_5%
2 PS8338B_P1
4.7K_0402_5%
2 VMM2320_AUX#
100K_0402_5%
2 WIGIG_AUX#
100K_0402_5%
CV61
0.01U_0402_16V7K
1
RV51
1
+3.3V_RUN
CV62 CV90 close to pin30 &57
CV66,CV69,CV70 close to pin5,21,51
+3.3V_RUN
@
2
CV62
0.01U_0402_16V7K
12" use 8339
14"/15" use 8338 at DOCK config
14"/15" use 12412 at Entry config
3
2
4
RV50
4.99K_0402_1%
2
1
5
DPB_CA_DET#
DPB_CA_DET
DPB_CA_DET
1
<22,34>
3
DPC_CA_DET#
D
S
2
G
QV9
FDV301N_NL_SOT23-3~D
<22,34>
DPC_CA_DET
2
G
DPC_CA_DET
QV10
FDV301N_NL_SOT23-3~D
need change to SB503010080
need change to SB503010080
A
A
5
1
RV508
2
DPB_CA_DET
1M_0402_5%
1
RV509
2
DPC_CA_DET
1M_0402_5%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Rev
A
4019RA
Date:
Thursday, November 14, 2013
Sheet
1
25
of
56
5
4
+3.3V_RUN
3
2 DAT_DDC2_2320
2.2K_0402_5%
2 CLK_DDC2_2320
2.2K_0402_5%
VGA SW
D
source from VMM2320
VGA SWITCH
H12 UMA
NA
H12 Entry
NA
H15 DSC
PI3V713
H15 UMA
PI3V713
H15D_En
NA
H15U_En
NA
RV121
1
2 4.7K_0402_5%
TEST
8
Reserved
3
11
28
31
33
VDD
VDD
VDD
R1
G1
B1
H1_OUT
V1_OUT
SDA1
SCL1
R2
G2
B2
H2_OUT
V2_OUT
SDA2
SCL2
GND
GND
GND
GND
GPAD
D
4
23
32
27
25
22
20
18
12
14
RED_CRT
GREEN_CRT
BLUE_CRT
HSYNC_CRT
VSYNC_CRT
DAT_DDC2_CRT
CLK_DDC2_CRT
26
24
21
19
17
13
15
RED_DOCK
<34>
GREEN_DOCK
<34>
BLUE_DOCK
<34>
HSYNC_DOCK
<34>
VSYNC_DOCK
<34>
DAT_DDC2_DOCK
<34>
CLK_DDC2_DOCK
<34>
PI3V713-AZLEX_TQFN32_6X3~D
+3.3V_RUN
SEL1/SEL2
Chanel
Source
0
A=B1
MB
1
A=B2
APR/SPR
1
2
@
1
2
@
1
2
1
2
1
2
+5V_RUN
1
2
CV144
0.1U_0402_16V4Z
H14U_En
+3.3V_RUN
SEL
29
+3.3V_RUN
5V VDD
CV124
0.1U_0402_16V4Z
NA
30
DOCKED
DOCKED
R
G
B
H_SOURCE
V_HOURCE
SDA_SOURCE
SCL_SOURCE
CV125
0.1U_0402_16V4Z
H14D_En
<22>
RED_2320
<22>
GREEN_2320
<22>
BLUE_2320
<22>
HSYNC_2320
<22>
VSYNC_2320
<22>
DAT_DDC2_2320
<22>
CLK_DDC2_2320
CV126
0.1U_0402_16V4Z
PI3V713
+3.3V_RUN
16
CV127
0.01U_0402_16V7K
H14 UMA
1
2
5
6
7
9
10
CV128
0.01U_0402_16V7K
C
PI3V713
+5V_RUN
UV16
<28,31,35>
NA
H14 DSC
1
VGA SW for MB/DOCK
1
RV250
1
RV251
PCB
2
C
2
1
IN
3
2
2
2
@
2
40mils
@
1
3.3P_0402_50V8C
CV56
2
1
3.3P_0402_50V8C
CV55
1
3.3P_0402_50V8C
CV54
2
BLM15BB470SN1D_2P
12P_0402_50V8J
12P_0402_50V8J
2
1
CV53
12P_0402_50V8J
2
CV52
CV51
RV34
150_0402_1%
2
1
RV33
150_0402_1%
2
1
RV32
150_0402_1%
2
1
EMC@LV18
EMC@
LV18
1
@
1
2
@
RV38
1K_0402_5%
1
2
RV37
1K_0402_5%
1
2
VSYNC_CONN
M_ID2#
2
1
2
@
2
CV59
22P_0402_50V8J
1
@
CV58
22P_0402_50V8J
BLM15AG121SN1D_L0402_2P
4
3
16
17
G
G
C-H_13-122015XXCP-B
A
1
DELL CONFIDENTIAL/PROPRIETARY
2
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
2
BLM15AG121SN1D_L0402_2P
EMC@ LV20
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
.
0
9
2
7
0
3
1
6
0
C
D
o
t
e
g
n
a
h
C
1
1
CV57
0.1U_0402_16V4Z
RV36
2.2K_0402_5%
2
1
@
@
RV35
2.2K_0402_5%
2
1
GREEN
EMC@ LV19
VSYNC_CRT
A
JCRT1 CONN@
JCRT-11
RED
HSYNC_CONN
BLUE
CLK_DDC2_CRT
HSYNC_CRT
CV50
1U_0402_6.3V6K
T87 PAD~D
+CRT_VCC
DAT_DDC2_CRT
B
+CRT_VCC
BLM15BB470SN1D_2P
BLUE_CRT
1
OUT
1
BLM15BB470SN1D_2P
3
2
EMC@LV17
EMC@
LV17
UV4
AP2330W-7_SC59-3
GND
2
1
1
3
1
1
EMC@LV16
EMC@
LV16
GREEN_CRT
DV6 @EMC@
L30ESDL5V0C3-2_SOT23-3
RED_CRT
B
DV5 @EMC@
L30ESDL5V0C3-2_SOT23-3
2
+5V_RUN
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
26
of
56
5
4
3
2
1
D
D
+3.3V_ALW_PCH
@ PJP40
1
2
PAD-OPEN1x1m
+3.3V_M
+3.3V_M_TPM
@ PJP11
1
2
PAD-OPEN1x1m
RZ10
9
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
USBP6USBP6+
USH_SMBCLK
USH_SMBDAT
BCM5882_ALERT#
+3.3V_SUS
POA_WAKE#
POA_ON/OFF#
+3.3V_RUN
+3.3V_ALW2
<9>
PLTRST_USH#
<35>
USH_PWR_STATE#
<10,12>
CONTACTLESS_DET#
<36>
<36>
5
13
14
15
27
28
1
+3.3V_SUS
+5V_RUN
<10,12>
@
+3.3V_RUN
2
1
2
+5V_RUN
@
+3.3V_ALW2
AT97SC3205_TSSOP28~D
@
NBO_1
NBO_2
NBO_3
NBO_4
NBO_5
NBO_6
GND
GND
GND
GND
<11>
<11>
<36>
<36>
<35>
1
TESTBI
TESTI
2
USH_PWR_STATE#
1M_0402_5%
2
MISO
MOSI
SPI_CLK
SPI_CS#
SPI_RST#
PIRQ#
JUSH1
CZ12
0.1U_0402_25V6
1
25
18
11
4
1
2
17
6
7
1
GPIO_1
GPIO_2
GPIO_3
GPIO-Express-00
PP/GPIO
CZ11
0.1U_0402_25V6
1
26
23
21
22
16
20
V_BAT
RZ9
CZ10
0.1U_0402_25V6
2
SPI_DINTPM
SPI_DOTPM
SPI_CLKTPM
PCH_SPI_CS2#_R
VCC
VCC
VCC
VCC
12
CZ61
0.1U_0402_25V6
B
@EMC@
@EMC@
CZ9
0.1U_0402_25V6
RZ35
33_0402_5%
2
SPI_CLKTPM
1
3
10
19
24
USH CONN
2
USH_SMBCLK
2.2K_0402_5%
2
USH_SMBDAT
2.2K_0402_5%
RZ8
1
<30,35,36,9>
PCH_PLTRST#_EC
<12>
TPM_PIRQ#
1
UZ1
2
1
1
2
1
2
2
2
33_0402_5%
33_0402_5%
33_0402_5%
0_0402_5%
+3.3V_SUS
@
2
2
2
2
CZ7
2200P_0402_50V7K
1
1
1
1
CZ6
2200P_0402_50V7K
RZ30
RZ29
RZ26
RZ17
<7>
PCH_SPI_DIN
<7>
PCH_SPI_DO
<7>
PCH_SPI_CLK
<7>
PCH_SPI_CS2#
CZ5
4700P_0402_25V7K
C
@ CZ4
0.1U_0402_25V6
1
+3.3V_M_TPM
USH_DET#
27
28
C
CONN@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
B
GND1
GND2
HB_A532615-SCHR21
E
N
O
D
K
N
I
L
0
0
F
S
1
0
0
1
0
P
S
Close to JUSH1
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
27
of
56
LAN_DISABLE#_R
26
27
25
TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
32
34
33
35
VDD3P3_IN
1
2
1
1
1
2
2
2
25MHZ_18PF_7V25000034
12
RES_BIAS
LED0
LED1
LED2
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TCK
VDD3P3_15
VDD3P3_19
VDD3P3_29
VDD0P9_47
VDD0P9_46
VDD0P9_37
XTAL_OUT
XTAL_IN
VDD0P9_43
VDD0P9_11
VDD0P9_40
VDD0P9_22
VDD0P9_16
VDD0P9_8
CTRL0P9
VSS_EPAD
DOCKED
VDD
VDD
VDD
VDD
VDD
VDD
VDD
UL4
2
LAN_TX0+L
1
+RSVD_VCC3P3_1 RL6
2
1 4.7K_0402_5%
+3.3V_LAN
LAN_TX0-L
3
LAN_TX1+L
6
LAN_TX1-L
7
LAN_TX2+L
9
LAN_TX2-L
10
LAN_TX3+L
11
LAN_TX3-L
12
5
4
+3.3V_LAN
15
19
29
+0.9V_LAN
47
46
37
43
11
40
22
16
8
<26,31,35>
7
+0.9V_LAN
REGCTL_PNP10 1
4.7UH_FLF3215T-4R7M_20%
13
DOCKED
15
16
42
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
2
5
LL1
49
WGI218LM-QQ89-B0_QFN48_6X6~D
Place CL3, CL4 and LL1 close to UL1
43
1: TO DOCK
0: TO RJ45
6
TEST_EN
RBIAS
1
LAN_TX3+L
LAN_TX3-L
2
2 0_0603_5%
2 0_0603_5%
1
LAN_TX3+ EMC@ RL27 1
LAN_TX3- EMC@ RL28 1
1
23
24
CL4
10U_0603_6.3V6M
1
1
30
LAN_TEST_EN
RL13
3.01K_0402_1%
GND
9
10
XTALO
XTALI
2
2
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
RL12
1K_0402_5%
2
1
2
1
2
1
2
1
2
PAD~D
PAD~D
CL14
33P_0402_50V8J
CL13
33P_0402_50V8J
IN
GND
RSVD_VCC3P3_1
LAN_TX2+L
LAN_TX2-L
CL3
0.1U_0402_10V7K
CL8
0.1U_0402_10V7K
CL11
0.1U_0402_10V7K
CL10
0.1U_0402_10V7K
2
0_0402_5%
OUT
LANWAKE_N
LAN_DISABLE_N
SVR_EN_N
LAN_DISABLE#_R
YL1
4
SMB_CLK
SMB_DATA
VDD3P3_4
RL11
1M_0402_5%
3
MDI_PLUS3
MDI_MINUS3
LAN_TX1+L
LAN_TX1-L
2 0_0603_5%
2 0_0603_5%
CL7
1U_0603_10V6K
@ RL9
10K_0402_5%
<35>
1
XTALO_R
@ RL10
Note:
+1.0V_LAN will work at 0.95V to 1.15V
2
3
MDI_PLUS2
MDI_MINUS2
2 0_0603_5%
2 0_0603_5%
LAN_TX2+ EMC@ RL25 1
LAN_TX2- EMC@ RL26 1
1
LAN_WAKE#
SMBus Device Address 0xC8
PERp
PERn
LAN_TX1+ EMC@ RL23 1
LAN_TX1- EMC@ RL24 1
20
21
1
<12,36>
PETp
PETn
17
18
2
28
31
@ T88
@ T89
CL9
0.1U_0402_10V7K
CL12
22U_0603_6.3V6M
1
1
CL6
<7>
SML0_SMBCLK
<7>
SML0_SMBDATA
+0.9V_LAN
2
CL5
PCIE_PTX_GLANRX_N3
41
42
MDI_PLUS1
MDI_MINUS1
LAN_TX0+L
LAN_TX0-L
2
2
0_0402_5%
1
PE_CLKP
PE_CLKN
LED
1
2
1
@ RL7
1
PM_LANPHY_ENABLE
<11>
@ RL5
10K_0402_5%
D
2
CL2
PCIE_PTX_GLANRX_P3
38
39
LAN ANALOG SWITCH
+3.3V_LAN
2 0_0603_5%
2 0_0603_5%
1
PCIE_PRX_GLANTX_N3
<11>
1 PCIE_PRX_GLANTX_P3_C
0.1U_0402_10V7K
1 PCIE_PRX_GLANTX_N3_C
0.1U_0402_10V7K
2 PCIE_PTX_GLANRX_P3_C
0.1U_0402_10V7K
2 PCIE_PTX_GLANRX_N3_C
0.1U_0402_10V7K
MDI
<11>
+3.3V_LAN
44
45
2
CL1
PCIE
<7>
CLK_PCIE_LAN
<7>
CLK_PCIE_LAN#
PCIE_PRX_GLANTX_P3
MDI_PLUS0
MDI_MINUS0
SMBUS
<11>
CLK_REQ_N
PE_RST_N
LAN_TX0+ EMC@ RL21 1
LAN_TX0- EMC@ RL22 1
CL27
0.1U_0402_25V6
2
@ RL4
LANCLK_REQ#
PLTRST_LAN#
13
14
CL26
0.1U_0402_25V6
1
@ RL2
<7>
<9>
48
36
CL25
0.1U_0402_25V6
TP_LAN_JTAG_TMS
10K_0402_5%
2
TP_LAN_JTAG_TCK
10K_0402_5%
1
LANCLK_REQ#
4.7K_0402_5%
JTAG
2
@ RL1
<12,9>
Layout Notice : Place bead as
close UL4 as possible
UL1
1
1
2
+3.3V_LAN
2
39
30
21
14
8
4
1
3
2
4
2
5
B0+
B0-
A0+
A0-
B1+
B1-
A1+
B2+
B2-
A1-
B3+
B3-
A2+
A2-
LEDB0
LEDB1
LEDB2
A3+
C0+
C0-
A3-
C1+
C1-
SEL
C2+
C2-
LEDA0
LEDA1
LEDA2
C3+
C3LEDC0
LEDC1
LEDC2
PD
38
37
SW_LAN_TX0+
SW_LAN_TX0-
34
33
SW_LAN_TX1+
SW_LAN_TX1-
29
28
SW_LAN_TX2+
SW_LAN_TX2-
25
24
D
SW_LAN_TX3+
SW_LAN_TX3-
17
18
41
SW_ACTLED_YEL#
SW_100_ORG#
SW_10_GRN#
36
35
32
31
27
26
23
22
19
20
40
DOCK_LOM_TRD0+
DOCK_LOM_TRD0-
<34>
<34>
DOCK_LOM_TRD1+
DOCK_LOM_TRD1-
<34>
<34>
DOCK_LOM_TRD2+
DOCK_LOM_TRD2-
<34>
<34>
DOCK_LOM_TRD3+
DOCK_LOM_TRD3-
<34>
<34>
DOCK_LOM_ACTLED_YEL#
<34>
DOCK_LOM_SPD100LED_ORG#
<34>
DOCK_LOM_SPD10LED_GRN#
<34>
PAD_GND
PI3L720ZHEX_TQFN42_9X3P5~D
C
C
USE SA000066W3L(S IC WGI218LM SLJK3A B1 QFN 48P PHY)
+3.3V_WWAN
3.3V_WWAN_EN
100K_0402_5%
PJP32
PAD-OPEN1x1m
@
UZ2
6
7
CT1
VBIAS
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
GPAD
1
@ CZ24
2
0.1U_0402_10V7K
1
CZ49
2
470P_0402_50V7K
1
CZ23
2
470P_0402_50V7K
+3.3V_LAN
11
10
9
8
PJP13
+3.3V_LAN_UZ2
2
1
15
+3.3V_LAN
2
TPS22966DPUR_SON14_2X3
PAD-OPEN1x1m
@
TL1
CZ50
0.1U_0402_10V7K
@
SW_LAN_TX1- 1
SW_LAN_TX1+ 2
1:1
TD1+
TX1+
TX13
WLAN_LAN_DISBL#
UL2
NL17SZ08DFT2G_SSOP5~D
<35>
TDCT2
TD2+
TXCT1
TXCT2
TX2+
1:1
SW_LAN_TX0+ 6
SW_LAN_TX3- 7
QL1A
DMN66D0LDW-7_SOT363-6
1
6
SW_ACTLED_YEL#
LAN_ACTLED_YEL#
SW_LAN_TX3+ 8
TD2-
TX2-
1:1
TD3+
TX3+
2
LAN_ACTLED_YEL_R#
150_0402_5%
10
23 NB_LAN_TX1+
22
9
NB_LAN_TX3-
8
NB_LAN_TX3+
7
NB_LAN_TX1-
6
NB_LAN_TX2-
5
NB_LAN_TX2+
4
NB_LAN_TX1+
3
NB_LAN_TX0-
2
NB_LAN_TX0+
1
Z2805
21
Z2807
20 NB_LAN_TX0-
1
1
4
SW_LAN_TX0- 5
2
4
2
P
0.1U_0402_10V7K
O
A
G
2
B
3
LOM_SPD10LED_GRN#
1
CL17
0.47U_0603_10V7K
LOM_SPD100LED_ORG#
CL16
0.47U_0603_10V7K
5
@ CL15
1
2
TDCT1
+3.3V_LAN:20mils
JLOM1
+3.3V_LAN
B
RJ45 LOM circuit
24 NB_LAN_TX1LAN_ACTLED_YEL# 1
RL14
TD1-
CL19
0.1U_0402_10V7K
SIO_SLP_LAN#
ON1
+3.3V_WWAN_UZ2
12
CL18
470P_0402_50V7K
<36,9>
5
14
13
1
4
+5V_ALW
VOUT1
VOUT1
2
3.3V_WWAN_EN
VIN1
VIN1
2
<35>
3
1
1
2
2
+3.3V_ALW
1
2
1
1
RZ40
19 NB_LAN_TX0+
18 NB_LAN_TX3-
1
LED_10_GRN#
RL19
LED_100_ORG# 1
RL20
2
LED_10_GRN_R#
150_0402_5%
2
LED_100_ORG_R#
150_0402_5%
11
13
12
TD3-
17 NB_LAN_TX3+
2
TX3-
Yellow LED+
PR4-
B
PR4+
PR2PR3PR3+
GND
PR2+
GND
PR1GND
PR1+
GND
17
16
15
14
Green LEDOrange LEDGreen-Orange LED+
SANTA_130456-511
15
Z2808
14 NB_LAN_TX2-
SW_LAN_TX2+12
TD4-
TX4-
13 NB_LAN_TX2+
1 75_0402_1%
TXCT4
TX4+
1 75_0402_1%
TXCT3
1:1
1 75_0402_1%
TDCT4
TD4+
Z2806
1 75_0402_1%
TDCT3
16
1
10
SW_LAN_TX2-11
2
1
2
5
CL21
0.47U_0603_10V7K
MASK_BASE_LEDS#
CL20
0.47U_0603_10V7K
QL1B
DMN66D0LDW-7_SOT363-6
4
3
LED_100_ORG#
9
<39>
E
N
O
D
K
N
I
L
MASK_BASE_LEDS#
1
1
5
6
5
4
0
3
1
MASK_BASE_LEDS#
SW_100_ORG#
CONN@
Yellow LED-
350uH_IH-115-F
QL2A
DMN66D0LDW-7_SOT363-6
1
6
LED_10_GRN#
1
CL22
2
EMC@
150P_1808_2.5KV8J
RL18 2
RL17 2
+GND_CHASSIS
use 40mil trace if necessary
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
QL2B
DMN66D0LDW-7_SOT363-6
4
3
5
RL16 2
GND
CHASSIS
MASK_BASE_LEDS#
RL15 2
A
2
SW_10_GRN#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
A
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Rev
A
4019RA
Date:
Thursday, November 14, 2013
1
Sheet
28
of
56
A
B
+3.3V_MMI
C
D
E
CR3 close to U27.9
CR1 CR2 close to U27.35
1
2
1
2
1
2
2
1
2
CR3
0.1U_0402_25V6
CR2
0.1U_0402_25V6
CR6
0.1U_0402_25V6
CR4
0.1U_0402_25V6
1
CR1
4.7U_0603_6.3V6K
CR4 close to U27.42
CR6 close to U27.23
1
+3.3V_MMI
1
+3.3V_MMI
1
<11>
<11>
PCIE_PRX_MMITX_P1
PCIE_PRX_MMITX_N1
2
PCIE_PRX_MMITX_P1_C
PCIE_PRX_MMITX_N1_C
1
RR15
2
MAIN_LDO_EN
10K_0402_5%
<6,7>
6
5
7
8
2
3
MAIN_LDO_EN
<12>
4
15
PLTRST_MMI#
14
16
MEDIACARD_IRQ#
17
MMICLK_REQ#
IO_LDOSEL
@ RR8
100K_0402_5%
1
2
PE_REXT
191_0402_1%
PCIE_PTX_MMIRX_P1_C
PCIE_PTX_MMIRX_N1_C
CLK_PCIE_MMI#
CLK_PCIE_MMI
<9>
+3.3V_MMI
IO_LDOSEL
2
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
<7>
<7>
RR6
100K_0402_5%
1
+3.3V_MMI
RR2
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
CR26 1
CR27 1
18
SD_SKT_33VOUT
MAIN_LDO_VIN
SD_SKT_18VOUT
22
+3.3V_RUN_CARD
24
+1.8V_RUN_CARD
1
+1.8V_RUN_CARD
1
1
2
AUX _33VIN
2
SD_SKT_33VIN
1
2
SD_33VCCD
2
+3.3V_RUN_CARD
2
MAIN_LDO_12VOUT
CR31 near UR1.22
CORE_12VCCD
SD_WPI
SD_CD#
UHSII_12VCCAIN/NC
UHSII_12VCCAIN/NC
UHSII_12VCCAIN/NC
SD_CLK
SD_CMD
PE_12VCCAIN
MMC_D7
MMC_D6
MMC_D5
MMC_D4
SD_D3
SD_D2
SD_D1
SD_D0
PE_REXT
PE_RXP
PE_RXM
PE_TXP
PE_TXM
SD_RCLK_M/NC
SD_RCLK_P/NC
SD_D1P/NC
SD_D1M/NC
SD_D0M/NC
SD_D0P/NC
PE_REFCLKM
PE_REFCLKP
PE_RST#_GATE#
MAIN_LDO_EN
SD_REXT/NC
20
21
SDWP
SD/MMCCD#
43
45
SD/MMCCLK_R
SD/MMCCMD
RR1
1 EMC@ 2 10_0402_5%
39
40
44
46
47
48
37
38
SD/MMCDAT3@EMC@ RR31
SD/MMCDAT2@EMC@ RR41
SD/MMCDAT1
SD/MMCDAT0
29
30
32
33
34
35
SD_UHS2_D1P
SD_UHS2_D1N
SD_UHS2_D0N
SD_UHS2_D0P
26
1
SD_REXT
RR5
2 0_0402_5%
2 0_0402_5%
CR34 near UR1.24
SD/MMCCLK
1
2
1
2
1
2
1
1
+SD_IO_LDO
1
1
1
2
2
1
2
1
1
36
31
28
+AUX_LDO
25
SD/MMCDAT3_R
SD/MMCDAT2_R
EMI solution for SD card
@EMC@ CR23
5P_0402_50V8C
CR22
0.1U_0402_25V6
CR21
0.1U_0402_25V6
CR19
0.1U_0402_25V6
CR18
4.7U_0603_6.3V6K
2
41
12
2
11
10
CR24 1
CR25 1
AUX_LDO_CAP
CR34
4.7U_0603_6.3V6K
13
PCIE_PTX_MMIRX_P1
PCIE_PTX_MMIRX_N1
OZ777FJ2LN
CR31
1U_0402_6.3V6K
23
If support RTD3 cold the AUX and MAIN power rail should be
use different power rail; for RTD3 hot please keep this circuit
<11>
<11>
UHSII_33VCCAIN/NC
SD_IO_LDO_CAP
42
+1.2V_LDO
2
PE_33VCCAIN
CR17
1U_0402_6.3V6K
2
27
CR15
0.1U_0402_25V6
1
9
CR14
4.7U_0603_6.3V6K
CR10
0.1U_0402_25V6
CR13
0.1U_0402_25V6
CR9
4.7U_0603_6.3V6K
CR8
0.1U_0402_25V6
CR7
4.7U_0603_6.3V6K
2
UR1
+1.2V_LDO
2
EMI depop location
2
4.7K_0402_1%
DEV_WAKE#
CLKREQ#
LED#
IO0_LDOSEL
GND
19
49
OZ777FJ2LN_QFN48_6X6
please routing daisy chain
1. from UR1.38 (SD_D0) ‐> UR1.30 (SD_RCLK_P) ‐> LR3.4
2. From UR1.37 (SD_D1) ‐> UR1.29 (SD_RCLK_N) ‐> LR3.1
R231,R297,R306,R315,R333,R337 for EMI solution
3
3
+3.3V_RUN
@
1
+3.3V_MMI
PJP26
2
PAD-OPEN1x2m
JSD1
2
1
2
CR35
0.1U_0402_25V6
RR11
1M_0402_5%
1
+3.3V_RUN_CARD
+1.8V_RUN_CARD
SD/MMCCMD
SD/MMCCLK
4
14
2
5
SD/MMCCD#
SDWP
18
19
SD/MMCDAT0
SD/MMCDAT1
SD/MMCDAT2_R
SD/MMCDAT3_R
SD_UHS2_D0P
SD_UHS2_D0N
SD_UHS2_D1P
SD_UHS2_D1N
7
8
9
1
11
12
16
15
3
6
10
13
17
CONN@
VDD/VDD1
VDD2
CMD
CLK
CARD DETECT
WRITE PROTEC
DAT0/RCLK+
DAT1/RCLKDAT2
CD/DAT3
D0+
DOD1+
D1VSS1
VSS2
VSS3
VSS4
VSS5
20
21
22
23
24
25
26
GND1
GND2
GND3
GND4
GND5
GND6
GND7
ALPS_SCDADA0101_NR
E
N
O
D
K
N
I
L
0
0
L
1
1
0
0
7
0
P
S
4
4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
E
29
of
56
5
4
3
NGFF slot B Key B
2
1
NGFF slot A Key A
NGFF for DSC
+3.3V_WLAN
+3.3V_WWAN
JNGFF2
<35>
1
3
5
7
9
11
NGFF_CONFIG_3
<11>
<11>
USBP7+
USBP7-
+3.3V_WWAN
1
@ RZ39
D
2
mSATA_DEVSLP
10K_0402_5%
<35>
<35>
NGFF_CONFIG_0
WWAN_WAKE#
<6>
<6>
<6>
<6>
PCIE_PTX_SATARX_N6_L1
PCIE_PTX_SATARX_P6_L1
PCIE_PRX_SATATX_P6_L1
PCIE_PRX_SATATX_N6_L1
CZ32 1
CZ33 1
20.1U_0402_10V7K PCIE_PTX_SATARX_N6_L1_C
20.1U_0402_10V7K PCIE_PTX_SATARX_P6_L1_C
<35>
NGFF_CONFIG_1
<35>
NGFF_CONFIG_2
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
JNGFF1
1
3
5
7
CONN@
1
3
5
7
9
11
2
4
6
8
10
2
4
6
8
10
USBP2+
USBP2-
WWAN_RADIO_DIS#_R
WWAN_LED#
<25>
<25>
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
<11>
<11>
HW_GPS_DISABLE2#_R
UIM_RESET
UIM_CLK
UIM_DATA
1
CV145 1
CV146
1
CV148 1
CV147
WIGIG_LANE_N3
WIGIG_LANE_P3
<25>
<25>
WIGIG_LANE_N2
WIGIG_LANE_P2
<11>
<11>
PCIE_PTX_WLANRX_P4
PCIE_PTX_WLANRX_N4
<25>
+SIM_PWR
mSATA_DEVSLP
WIGIG_HPD
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
<12>
<11>
<11>
PCIE_PRX_WLANTX_P4
PCIE_PRX_WLANTX_N4
<7>
<7>
PCH_PLTRST#_EC
<12,7>
<35>
<6>
<6>
PCIE_PTX_WIGIGRX_P6_L0
PCIE_PTX_WIGIGRX_N6_L0
SUSCLK
CLK_PCIE_WLAN
CLK_PCIE_WLAN#
WLANCLK_REQ#
PCIE_WAKE#
CZ21 1
CZ22 1
<6>
<6>
UIM_DET
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PCIE_PRX_WIGIGTX_P6_L0
PCIE_PRX_WIGIGTX_N6_L0
<30,9>
<7>
<7>
9
11
13
15
17
19
21
23
25
27
PCIE_PTX_WLANRX_P4_C
29
PCIE_PTX_WLANRX_N4_C
31
33
35
37
39
41
43
45
47
PCIE_WAKE#
49
PCIE_PTX_WIGIGRX_P6_L0_C 51
PCIE_PTX_WIGIGRX_N6_L0_C 53
55
57
59
61
63
65
67
CLK_PCIE_WIGIG
CLK_PCIE_WIGIG#
69
69
GND
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
GND
68
GND
2
4
6
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
2
WIGIG_LANE_N3_C
2 0.1U_0402_25V6 WIGIG_LANE_P3_C
0.1U_0402_25V6
2
WIGIG_LANE_N2_C
2 0.1U_0402_25V6 WIGIG_LANE_P2_C
0.1U_0402_25V6
CZ13 1
CZ14 1
CONN@
1
3
5
7
GND
2
4
6
WLAN_LED#
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
BT_LED#
WIGIG_AUX#_C
WIGIG_AUX_C 0.1U_0402_25V6
0.1U_0402_25V6
WIGIG_LANE_N1_C
WIGIG_LANE_P1_C
0.1U_0402_25V6
0.1U_0402_25V6
WIGIG_LANE_N0_C
WIGIG_LANE_P0_C
0.1U_0402_25V6
0.1U_0402_25V6
2
2
1
1CV150
CV149
1
1CV152
CV153
1
1CV156
CV157
2
2
2
2
WIGIG_AUX#
WIGIG_AUX
<25>
<25>
D
WIGIG_LANE_N1
WIGIG_LANE_P1
<25>
<25>
WIGIG_LANE_N0
WIGIG_LANE_P0
<25>
<25>
PCH_CL_RST1#
<7>
PCH_CL_DATA1
<7>
PCH_CL_CLK1
<7>
SUSCLK
<30,9>
PCH_PLTRST#_EC
PCH_PLTRST#_EC
BT_RADIO_DIS#_R
WLAN_WIGIG60GHZ_DIS#_R
<27,35,36,9>
PCH_PLTRST#_EC
WIGIGCLK_REQ#
PCIE_WAKE#
<6,7>
68
BELLW_80148-3221
E
N
O
D
K
N
I
L
1
2
2
3
8
4
1
0
8
E
N
O
D
K
N
I
L
1
2
2
4
9
4
1
0
8
BELLW_80149-4221
+3.3V_WWAN
<35>
<35>
1
BT_RADIO_DIS#
2
1
2
2
2
1
1
HW_GPS_DISABLE2#_R
1
2
DZ6
RB751S40T1G_SOD523-2
1
1
HW_GPS_DISABLE2#
2
WLAN_WIGIG60GHZ_DIS#_R
1
2
DZ1
RB751S40T1G_SOD523-2
2
1
WLAN_WIGIG60GHZ_DIS#
CZ19
4.7U_0603_6.3V6K
<35>
CZ18
0.1U_0402_25V6
DZ5
RB751S40T1G_SOD523-2
2
1
1
WWAN_RADIO_DIS#_R
CZ17
0.1U_0402_25V6
2
WWAN_RADIO_DIS#
2
CZ16
0.047U_0402_16V4Z
2
1
<35>
1
CZ20
0.047U_0402_16V4Z
2
+
2
@
@CZ15
0.1U_0402_25V6
2
+
2
1
CZ57
150U_B2_6.3VM_R35M
2
+3.3V_WLAN
1
@ CZ56
150U_6.3V_M
CZ55
33P_0402_50V8J
CZ54
22U_0603_6.3V6M
CZ53
33P_0402_50V8J
CZ52
0.047U_0402_16V4Z
CZ51
0.047U_0402_16V4Z
1
C
1
C
BT_RADIO_DIS#_R
DZ2
RB751S40T1G_SOD523-2
Power Rating TBD
STATE # CONFIG_0
0
CONFIG_1
GND
GND
CONFIG_2
GND
CONFIG_3
GND
Module Type
PWR
Rail
Primary Power
Voltage
Tolerance
Peak
Aux Power
Normal
Normal
SSD-SATA
+3.3V
GND
HIGH
GND
GND
SSD-PCIE
8
HIGH
GND
GND
GND
WWAN
14
HIGH
GND
HIGH
HIGH
HCA-PCIE
15
HIGH
HIGH
HIGH
HIGH
NA
LED control circuit
5
4
BT_LED#
WLAN_LED#
UZ3
+5V_ALW
<36,49>
SUS_ON
4
5
6
7
A
ON1
VBIAS
CT1
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
GPAD
14
13
+3.3V_WLAN_UZ3
1
@CZ36
@
CZ36
2
0.1U_0402_10V7K
1
2
470P_0402_50V7K
12
CZ37
11
1
2
CZ62
470P_0402_50V7K
@ PJP17
2
+3.3V_SUS
10
9
8
1
+3.3V_SUS_UZ3
15
2
TPS22966DPUR_SON14_2X3
WIRELESS_LED#
<35,39>
1
6
QZ2A
DMN66D0LDW-7_SOT363-6
+3.3V_WWAN
2
3
AUX_EN_WOWL
VOUT1
VOUT1
WWAN_LED#
RZ37
100K_0402_5%
E
N
O
D
K
N
I
L
0
0
M
1
1
0
0
7
0
P
S
<35>
VIN1
VIN1
1
1
2
T-SOL_159-1000302602
3
QZ2B
DMN66D0LDW-7_SOT363-6
5
+3.3V_ALW
2
PJP12
PAD-OPEN1x1m
@
2
AUX_EN_WOWL
100K_0402_5%
2
2
2
1
1
RZ38
1
11
12
13
14
15
16
17
18
2
UIM_DET
+3.3V_WLAN
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
1
1
2
C263
1U_0402_6.3V6K
UIM_DATA
VCC
RST
CLK
D+
GND_1
VPP
I/O
DDET
COM
RZ15
100K_0402_5%
JSIM1 CONN@
1
2
3
4
5
6
7
8
9
10
RZ14
100K_0402_5%
+SIM_PWR
UIM_RESET
UIM_CLK
B
+3.3V_WLAN
SIM Card Push-Push
1
B
1
1
A
6
4
PAD-OPEN1x1m
QZ11A
DMN66D0LDW-7_SOT363-6
@CZ63
0.1U_0402_10V7K
3
QZ11B
DMN66D0LDW-7_SOT363-6
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
30
of
56
5
4
3
2
+USB_LEFT_PWR
DI1 EMC@
1
2
3
USB3RN1_D-
USB3RP1_D+
2
8
USB3RP1_D+
USB3TN1_D-
4
7
USB3TN1_D-
USB3TP1_D+
5
6
USB3TP1_D+
JUSB1
2
USB3RP1_D+
3
TVWDF1004AD0_DFN9
D
1
USB3TN1_C
0.1U_0402_10V7K
4
2
1
USB3TP1_C
0.1U_0402_10V7K
1
CI4
SW_USB3TP1
CI5
4
3
1
2
3
USB3TN1_D-
2
USB3TP1_D+
LI3
DLW21HN900HQ2L_4P
SW_USBP0+
1
SW_USBP0-
4
EMC@
1
2
4
3
2
USBP0_D+
3
USBP0_D-
1
2
EMC@
USB3TN1_DUSB3TP1_D+
GND
GND
GND
GND
10
11
12
13
SINGA_2UB4037-100201F
D
+USB_LEFT_PWR
+5V_ALW
DLW21HN900HQ2L_4P
CONN@
VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+
E
N
O
D
K
N
I
L
F
1
0
2
0
0
1
7
3
0
4
B
U
2
LI2
USB3RN1_DUSB3RP1_D+
DI2 EMC@
L30ESDL5V0C3-2_SOT23-3
2
DLW21HN900HQ2L_4P
SW_USB3TN1
1
2
3
4
5
6
7
8
9
USBP0_DUSBP0_D+
CI3
0.1U_0402_25V6
3
CI1
100U_1206_6.3V6M
4
2
1
USB3RN1_D-
3
SW_USB3RP1
9
1
4
1
2
SW_USB3RN1
USB3RN1_DEMC@
1
LI1
1
1
2
4
5
6
7
8
USB3TP1
USB3TN1
USB3RP1
USB3RN1
USBP0+
USBP0-
TX+A
TX-A
RX+A
RX-A
D+A
D-A
USB_IDA
TX+B
TX-B
RX+B
RX-B
D+B
D-B
USB_IDB
TX+
TXRX+
RXD+
DUSB_ID
OE#
<26,28,35>
10
32
DOCKED
SS_SEL
HS_SEL
GND
GND
HGND
31
30
27
26
19
18
17
SW_USB3TP1
SW_USB3TN1
SW_USB3RP1
SW_USB3RN1
SW_USBP0+
SW_USBP0-
25
24
23
22
15
14
13
2
USB2 3
<35>
USB_PWR_EN1#
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
USB_OC0#
H12 Entry
DOCK_USB3TP1
DOCK_USB3TN1
DOCK_USB3RP1
DOCK_USB3RN1
DOCK_USBP0+
DOCK_USBP0-
11
21
28
33
<34>
<34>
<34>
<34>
<34>
<34>
NA
NA
H14 DSC USB3102 NX3DV221
C
H14 UMA USB3102 NX3DV221
H14D_En
NA
NA
H14U_En
NA
NA
H15 DSC USB3102 NX3DV221
check port mapping
H15 UMA USB3102 NX3DV221
function
1
Dock
0
M/B
H15D_En
NA
NA
H15U_En
NA
NA
+USB_RIGHT_PWR
LI9
B
<11>
1
USB3RN4
JUSB2
1
2
3
4
5
6
7
8
9
EMC@
1
2
2
USB3RN4_D-
USBP3_DUSBP3_D+
USB3TP4
2
1
USB3TN4_C
0.1U_0402_10V7K
1
2
1
USB3TP4_C
0.1U_0402_10V7K
4
CI28
USB3TN4_D-
4
7
USB3TN4_D-
USB3TP4_D+
5
6
USB3TP4_D+
USB3RN4_DUSB3RP4_D+
USB3TN4_DUSB3TP4_D+
3
USB3RP4_D+
2
USB3RN4_D-
8
EMC@
1
2
2
USB3TN4_D-
3
USB3TP4_D+
3
4
3
1
TVWDF1004AD0_DFN9
CI27
DLW21HN900HQ2L_4P
+5V_ALW
CONN@
VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+
B
GND
GND
GND
GND
10
11
12
13
SINGA_2UB4037-100201F
E
N
O
D
K
N
I
L
F
1
0
2
0
0
1
7
3
0
4
B
U
2
USB3TN4
<11>
9
2
DI3 EMC@
L30ESDL5V0C3-2_SOT23-3
<11>
1
USB3RP4_D+
CI10
0.1U_0402_25V6
LI8
USB3RN4_D-
2
USB3RP4_D+
1
3
3
CI8
100U_1206_6.3V6M
4
DLW21HN900HQ2L_4P
2
4
USB3RP4
1
DI6 EMC@
<11>
<11,12>
G547I2P81U_MSOP8
H12 UMA USB3102 NX3DV221
PI3USB3102ZLEX_TQFN32_6X3
DOCKED
USB2 0
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
VDD
VDD
VDD
VDD
VDD
VDD
CI7
0.1U_0402_25V6
C416
0.1U_0402_25V6
C414
0.1U_0402_25V6
@ C417
0.1U_0402_25V6
<11>
<11>
<11>
<11>
<11>
<11>
C415
0.1U_0402_25V6
@ C418
0.1U_0402_25V6
@ C419
0.1U_0402_25V6
C420
4.7U_0603_6.3V6K
C
PCB
UI4
3
9
12
16
20
29
@ CI6
10U_0603_6.3V6M
+3.3V_SUS
1
UI1
1
2
3
4
+USB_RIGHT_PWR
UI2
4
1
2
C322
0.1U_0402_25V6
A
10
9
8
7
6
VCC
S
D+
DOE#
1D+
1D2D+
2DGND
1
2
3
4
5
3
USBP3_D+
3
USBP3_D-
SW_USBP3+
SW_USBP3DOCK_USBP3+
DOCK_USBP3-
1
2
DLW21HN900HQ2L_4P
UI5
<35>
DOCKED_LIO_EN
<11>
USBP3+
<11>
USBP3-
2
2
1
1
4
CI12
0.1U_0402_25V6
support APR/SPR/LIO Dock
1
SW_USBP3-
@ CI11
10U_0603_6.3V6M
+3.3V_SUS
SW_USBP3+
<35>
USB_PWR_EN2#
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
USB_OC2#
<11,12>
G547I2P81U_MSOP8
<34>
<34>
A
NX3DV221GM_XQFN10U10_2X1P55
DELL CONFIDENTIAL/PROPRIETARY
check port mapping
DOCKED_LIO_EN
5
1
2
3
4
EMC@
2
LI4
Compal Electronics, Inc.
function
1
Dock
0
M/B
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Rev
A
4019RA
Date:
Thursday, November 14, 2013
Sheet
1
31
of
56
5
4
3
2
1
+5V_USB_CHG_PWR
JUSB3
2
2
4
3
3
USB3RN2_D-
USB3T_N2
4
USB3RN2_D-
8
USB3RP2_D+
USB3TN2_D-
4
7
USB3TN2_D-
USB3TP2_D+
5
6
USB3TP2_D+
1
2
1
2
EMC@
1
2
4
3
2
USB3TP2_D+
3
USB3TN2_D-
3
TVWDF1004AD0_DFN9
DLW21HN900HQ2L_4P
+5V_ALW
EMC@
DI5
USB3RN2_DUSB3RP2_D+
USB3TN2_DUSB3TP2_D+
CONN@
VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+
GND
GND
GND
GND
D
10
11
12
13
SANTA_373025-1
E
N
O
D
K
N
I
L
1
5
2
0
3
7
3
1
9
2
L30ESDL5V0C3-2_SOT23-3
USB3T_P2
1
USB3RP2_D+
USBP1_R_DUSBP1_R_D+
CI17
LI5
USB3RN2_D-
CI14
DLW21HN900HQ2L_4P
EMC@
0.1U_0402_25V6
4
USB3RN2_RP
100U_1206_6.3V6M
DI4
D
1
2
3
4
5
6
7
8
9
USB3RP2_D+
2
1
3
1
USB3RP2_RP
EMC@
1
LI6
+5V_USB_CHG_PWR
UI3
1
+5V_ALW
2
CI19
0.1U_0402_25V6
1
<11>
<11>
<11>
<35>
FAULT#
4
EN
ILIM_LO
ILIM_HI
CI19 near UI3.1
<35,36>
6
7
8
USB_PWR_SHR_EN#
DP_IN
DM_IN
12
10
11
PS_USBP1_D+
PS_USBP1_D-
LI7
PS_USBP1_D-
4
PS_USBP1_D+
1
EMC@
4
3
3
USBP1_R_D-
2
USBP1_R_D+
ILIM_SEL
5
USB_PWR_SHR_VBUS_EN
OUT
DM_OUT
DP_OUT
13
USB_OC1#
ILIM_SEL
C
IN
2
3
USBP1USBP1+
CTL1
CTL2
CTL3
NC
GND
GNDP
+5V_ALW
15
16
RI14 2
1
22.1K_0402_1%
1
2
C
DLW21HN900HQ2L_4P
9
14
17
TPS2544RTER_WQFN16_3X3
RI13 2
1
ILIM_SEL
10K_0402_5%
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
1
1
1
2
2
2
2
1
2
2
2
@
1
2
1
1
1
2
2
B
UI6
1
13
A_EQ_1B
A_DE_0B
A_EQ_0B
A_DE_1B
0_0402_5%
2
1
1
1
1
2
2
2
2
2
1
1
2
RI36
2
1
1
1
1
1
1
2
1
@
0_0402_5%
2
@
0_0402_5%
0_0402_5%
0_0402_5%
4.99K_0402_1%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
2
2
@
CI37
0.1U_0402_16V4Z
2
1
CI36
0.01U_0402_16V7K
1
CI35
0.1U_0402_16V4Z
2
@
CI34
0.1U_0402_16V4Z
1
CI33
10U_0805_10V6K
4.7K_0402_5%
1
USB3 Repeater
RI27
RI26
RI25
RI24
RI23
RI22
2
@
RI32
@
RI35
@
4.7K_0402_5%
@
RI31
@
@
RI34
@
@
A_EQ_0B
A_EQ_1B
A_DE_0B
A_DE_1B
RI33
@
4.7K_0402_5%
B_EQ_0B
B_EQ_1B
B_DE_0B
B_DE_1B
REXTB
TESTB
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
B
@
RI30
@
RI29
@
RI21
@
RI20
@
RI19
@
RI18
@
RI17
RI16
@
<11>
<11>
USB3TP2
USB3TN2
CI13
CI16
2
2
1
1 0.1U_0402_10V7K
0.1U_0402_10V7K
USB3TP2_C
USB3TN2_C
19
20
9
8
USB3RP2_RP
USB3RN2_RP
PD#B
15
16
17
18
@ RI28
+3.3V_RUN
@ RI15 1
PD#B
REXTB
TESTB
2 4.7K_0402_5%
5
7
14
24
VDD
VDD
A_EQ1/SDA_CTL
A_DE0/SCL_CTL
A_EQ0/NC
A_DE1/NC
B_EQ1/I2C_ADDR1
B_DE0/I2C_ADDR0
B_EQ0/NC
B_DE1/NC
A_INp
A_INn
A_OUTp
A_OUTn
B_INp
B_INn
B_OUTp
B_OUTn
PD#
REXT
TEST
I2C_EN
GND
GND
GPAD
4
3
2
6
B_EQ_1B
B_DE_0B
B_EQ_0B
B_DE_1B
12
11
USB3TP2_RP
USB3TN2_RP
22
23
USB3RP2_C
USB3RN2_C
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
2
1
1 CI42
CI43
2
2
1
1 CI41
CI40
USB3T_P2
USB3T_N2
USB3RP2
USB3RN2
<11>
<11>
10
21
25
1
PS8713BTQFN24GTR2_TQFN24_4X4
use SA00005OR20
A
2K_0402_5%
2
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
32
of
56
5
4
3
2
1
D
D
C
C
Doesn't support.
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Rev
A
4019RA
Date:
Thursday, November 14, 2013
Sheet
1
33
of
56
4
3
EMC@ R257 1
EMC@ R263 1
2 33_0402_5%
2 33_0402_5%
DPC_DOCK_LANE_P2
DPC_DOCK_LANE_N2
C300 2
C301 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
DPC_LANE_P3_C
DPC_LANE_N3_C
EMC@ R265 1
EMC@ R266 1
2 33_0402_5%
2 33_0402_5%
DPC_DOCK_LANE_P3
DPC_DOCK_LANE_N3
<25>
<25>
DPC_DOCK_HPD
2
Close to DOCK
Its for Enhance ESD on
dock issue.
+NBDOCK_DC_IN_SS
C310 @EMC@
0.033U_0402_16V7K
1
DPC_DOCK_HPD
2
C
BLUE_DOCK
<26>
RED_DOCK
<26>
GREEN_DOCK
<26>
<26>
HSYNC_DOCK
VSYNC_DOCK
<36>
<36>
CLK_MSE
DAT_MSE
R268
100K_0402_5%
1
DPC_DOCK_HPD
<26>
<21>
<21>
DAI_BCLK#
DAI_LRCK#
<21>
<21>
DAI_DI
DAI_DO#
<21>
DAI_12MHZ#
D_LAD0
D_LAD1
<35>
<35>
D_LAD2
D_LAD3
<35>
<35>
CLK_PCI_DOCK
<36>
DOCK_SMB_CLK
DOCK_SMB_DAT
<35,47,55>
<36>
<35,47,55>
D_SERIRQ
D_DLDRQ1#
DOCK_SMB_ALERT#
<47>
DOCK_PSID
DOCK_PWR_BTN#
SLICE_BAT_PRES#
SLICE_BAT_PRES#
2
3
1
1
2
2
153
154
155
156
157
158
GND1
PWR1
PWR1
PWR1
PWR2
PWR2
PWR2
GND2
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
DPB_LANE_P2_C
DPB_LANE_N2_C
C305 2
C307 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
DPB_DOCK_LANE_P3 EMC@ R258 1
DPB_DOCK_LANE_N3 EMC@ R267 1
2 33_0402_5%
2 33_0402_5%
DPB_LANE_P3_C
DPB_LANE_N3_C
C308 2
C309 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
DPB_DOCK_AUX
DPB_DOCK_AUX#
SATA_PRX_DKTX_P0
SATA_PRX_DKTX_N0
ACAV_DOCK_SRC#
<55>
SATA_PTX_DKRX_P0
SATA_PTX_DKRX_N0
2
C312 2
C313
1
C314 1
C315
<26>
<26>
1
1 0.01U_0402_16V7K
0.01U_0402_16V7K
2
2 0.01U_0402_16V7K
0.01U_0402_16V7K
SATA_PRX_DKTX_P0_C
SATA_PRX_DKTX_N0_C
SATA_PTX_DKRX_P0_C
SATA_PTX_DKRX_N0_C
<22>
<22>
DPB_LANE_P1
DPB_LANE_N1
<22>
<22>
DPB_LANE_P2
DPB_LANE_N2
<22>
<22>
DPB_LANE_P3
DPB_LANE_N3
<22>
<22>
DPB_DOCK_HPD
<6>
<6>
DOCK_USBP3+
DOCK_USBP3-
DOCK_USBP0+
DOCK_USBP0CLK_KBD
DAT_KBD
D
<22>
Close to DOCK
Its for Enhance ESD on dock
issue.
<6>
<6>
DOCK_USBP3_D+
DOCK_USBP3_D-
<31>
<31>
<31>
<31>
<36>
<36>
C
DOCK_USB3RN1
DOCK_USB3RP1
<31>
<31>
DOCK_USB3TN1
DOCK_USB3TP1
<31>
<31>
EMI solution for E-Docking USB
DPB_DOCK_HPD
BREATH_LED#
<36,39>
DOCK_LOM_ACTLED_YEL#
<28>
DOCK_LOM_TRD0+
DOCK_LOM_TRD0-
<28>
<28>
DOCK_LOM_TRD1+
DOCK_LOM_TRD1-
<28>
<28>
+3.3V_ALW
+LOM_VCT
+LOM_VCT
DOCK_LOM_TRD2+
DOCK_LOM_TRD2-
<28>
<28>
DOCK_LOM_TRD3+
DOCK_LOM_TRD3-
<28>
<28>
DOCK_DCIN_IS+
DOCK_DCIN_ISDOCK_POR_RST#
DOCK_DET_R#
DOCK_DET#
10K_0402_5%
1
2
R272
<54>
<54>
<36>
D19
1
2
DOCK_DET#
<35,55>
B
RB751S40T1G_SOD523-2
+DOCK_PWR_BAR
DAI_12MHZ#
1
CLK_PCI_DOCK
@ CE319
@ RE273 12P_0402_50V8J
33_0402_5%
2
DAI_BCLK#
@ CE42
@ RE6
4.7P_0402_50V8C
10_0402_5%
E
N
O
D
K
N
I
L
0
A
3
1
0
0
0
3
0
P
S
@ CE43
@ RE41
4.7P_0402_50V8C
10_0402_5%
JAE_WD2F144WB5R400
<25>
<25>
DAT_DDC2_DOCK
CLK_DDC2_DOCK
149
150
151
152
159
160
161
162
163
164
DPB_DOCK_AUX
DPB_DOCK_AUX#
DPB_DOCK_HPD
C318
0.1U_0603_50V7K
D20 @EMC@
PESD24VS2UT_SOT23-3~D
C317
0.1U_0603_50V7K
@ CE33
4.7U_0805_25V6-K
1
+DOCK_PWR_BAR
145
146
147
148
2 33_0402_5%
2 33_0402_5%
@ C316
1U_0402_6.3V6K
<7>
B
GREEN_DOCK
D_LFRAME#
D_CLKRUN#
<35>
<35>
<36>
RED_DOCK
DPB_DOCK_LANE_P2 EMC@ R262 1
DPB_DOCK_LANE_N2 EMC@ R264 1
DPB_LANE_P0
DPB_LANE_N0
R271
100K_0402_5%
<35>
<35>
BLUE_DOCK
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
C311
0.033U_0402_16V7K
<22>
DPC_DOCK_AUX
DPC_DOCK_AUX#
DPC_DOCK_AUX
DPC_DOCK_AUX#
C298 2
C303 2
1
DPC_LANE_P2_C
DPC_LANE_N2_C
DPB_LANE_P1_C
DPB_LANE_N1_C
2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
2 33_0402_5%
2 33_0402_5%
1
C304 2
C306 2
DPB_DOCK_LANE_P1 EMC@ R254 1
DPB_DOCK_LANE_N1 EMC@ R256 1
2
DPC_DOCK_LANE_P1
DPC_DOCK_LANE_N1
@EMC@
2 33_0402_5%
2 33_0402_5%
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
1
EMC@ R253 1
EMC@ R255 1
C294 2
C296 2
2
DPC_LANE_P1_C
DPC_LANE_N1_C
DPB_LANE_P0_C
DPB_LANE_N0_C
1
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
2 33_0402_5%
2 33_0402_5%
2
C297 2
C299 2
<28>
DPB_DOCK_LANE_P0 EMC@ R260 1
DPB_DOCK_LANE_N0 EMC@ R261 1
1
DPC_DOCK_LANE_P0
DPC_DOCK_LANE_N0
2
DPC_LANE_P3
DPC_LANE_N3
2 33_0402_5%
2 33_0402_5%
1
DPC_LANE_P2
DPC_LANE_N2
<22>
<22>
EMC@ R259 1
EMC@ R252 1
DOCK_AC_OFF
<55>
DOCK_LOM_SPD100LED_ORG#
DPB_CA_DET
<22,25>
DPB_CA_DET
2
<22>
<22>
DPC_LANE_P0_C
DPC_LANE_N0_C
DOCK_AC_OFF
1
DPC_LANE_P1
DPC_LANE_N1
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
2
<22>
<22>
C302 2
C295 2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
1
DPC_LANE_P0
DPC_LANE_N0
DPC_CA_DET
2
D
<22>
<22>
DOCK_LOM_SPD10LED_GRN#
<22,25>
DPC_CA_DET
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
1
<28>
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
1
CONN@
JDOCK1
DOCK_DET_1
2
2
5
EMI depop location
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
34
of
56
5
4
3
2
1
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW_UE1
PJP14
1
+3.3V_ALW
2
1
2
BT_RADIO_DIS#
100K_0402_5%
2
HW_GPS_DISABLE2#
100K_0402_5%
2
PROCHOT_GATE
100K_0402_5%
RE11
1
RE12
1
@ RE83
LAN_DISABLE#_R
<34,47,55>
DOCK_SMB_ALERT#
@ T96 PAD~D
GPU_PWR_LEVEL
<40>
<31>
USB_PWR_EN2#
<21>
EN_I2S_NB_CODEC#
<27>
USH_PWR_STATE#
<55>
EN_DOCK_PWR_BAR
<30>
HW_GPS_DISABLE2#
<23>
PANEL_BKEN_EC
<23>
LCD_TST
<47>
PSID_DISABLE#
<26,28,31>
DOCKED
<34,55>
DOCK_DET#
<21>
AUD_NB_MUTE#
<28>
3.3V_WWAN_EN
<23>
LCD_VCC_TEST_EN
<30>
WWAN_WAKE#
<21>
AUD_HP_NB_SENSE
<31>
USB_PWR_EN1#
C
<55>
<34,47,55>
1
2 SYS_LED_MASK#
10K_0402_5%
RE21
1
2
RE20
<30>
LCD_TST
100K_0402_5%
SLICE_BAT_ON
SLICE_BAT_PRES#
@ T97 PAD~D
@ T99 PAD~D
WLAN_WIGIG60GHZ_DIS#
<36>
EC5048_TX
@ T98 PAD~D
<27>
<10,12,44,53>
USB_PWR_EN2#
HW_GPS_DISABLE2#
LCD_TST
WWAN_WAKE#
USB_PWR_EN1#
SLICE_BAT_ON
SLICE_BAT_PRES#
EXPRESS_DET#
SMART_DET#
WLAN_WIGIG60GHZ_DIS#
USB_DB_DET#
BCM5882_ALERT#
DGPU_PWROK
VGA_ID
+3.3V_ALW
1
VGA_ID
100K_0402_5%
1
VGA_ID
100K_0402_5%
2
RE84
2
RE85
@
B
<39>
<32>
SYS_LED_MASK#
<30,39>
WIRELESS_LED#
USB_PWR_SHR_VBUS_EN
SYS_LED_MASK#
USB_PWR_SHR_VBUS_EN
VGA_ID0
Discrete
0
UMA
1
<30>
<30>
BT_RADIO_DIS#
WWAN_RADIO_DIS#
SIO_SLP_WLAN#
B32
A31
B33
B15
A15
B16
A16
A1
B2
A2
B3
A3
B45
A42
B4
A59
B62
A58
B61
A56
B59
A55
B58
B47
A45
B48
A46
B49
A47
B50
A48
B13
A13
A53
B57
B14
A14
B17
B18
1
2
1
2
1
2
1
2
1
GPIOJ0
GPIOJ1/TACH1
GPIOJ2/TACH2
GPIOJ3
GPIOJ4
GPIOJ5
GPIOJ6
GPIOJ7
GPIOB0
GPIOB1
GPOC2
GPOC3
GPOC4
GPOC5
GPOC6/TACH4
GPIOC7
GPIOD0
GPIOC1
GPIOC0
GPIOB7
GPIOB6
GPIOB5
GPIOB4
GPIOB3
GPIOB2
GPIOK0
GPIOK1/TACH3
GPIOK2
GPIOK3
GPIOK4
GPIOK5
GPIOK6
GPIOK7
GPIOL0/PWM7
GPIOL1/PWM8
GPIOL2/PWM0
GPIOL3/PWM1
GPIOL4/PWM3
GPIOL5/PWM2
GPIOL6
GPIOL7/PWM5
GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
GPIOD6
GPIOD7
GPIOM1
GPIOM3/PWM4
GPIOM4/PWM6
GPIOE0/RXD
GPIOE1/TXD
GPIOE2/RTS#
GPIOE3/DSR#
GPIOE4/CTS#
GPIOE5/DTR#
GPIOE6/RI#
GPIOE7/DCD#
GPIOF0
GPIOF1
GPIOF2
GPIOF3/TACH8
GPIOF4/TACH7
GPIOF5
GPIOF6
GPIOF7
RE35
1
RE276
D
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ1#
SER_IRQ
14.318MHZ/GPIOM0
CLK32/GPIOM2
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLKRUN#
DLDRQ1#
DSER_IRQ
GPIOG0/TACH5
GPIOG1
GPIOG2
GPIOG3
GPIOG4
GPIOG5
GPIOG6
GPIOG7/TACH6
BC_INT#
BC_DAT
BC_CLK
GPIOH0
GPIOH1
SYSOPT1/GPIOH2
SYSOPT0/GPIOH3
GPIOH4
GPIOH5
GPIOH6
GPIOH7
A23
B63
A60
A61
B65
A62
B66
A63
RPE8
SATA2_PCIE6_L1
A8
B9
B10
A10
B11
A11
B12
A12
B60
A57
B64
B68
A9
B1
A18
A44
B34
B39
B51
A27
A26
B26
B25
A21
B22
A28
B20
A22
B21
A32
B35
B29
B28
A25
A24
B23
A19
B24
A20
<12,6>
DOCK_AC_OFF_EC
B67
A64
A5
B6
A6
B7
A7
B8
1
2
3
4
LPC_LDRQ1#
D_DLDRQ1#
D_SERIRQ
D_CLKRUN#
100K_0804_8P4R_5%
<55>
AUX_EN_WOWL
8
7
6
5
<30>
PCIE_WAKE#
GPIO_PSID_SELECT
DOCK_HP_DET
DOCK_MIC_DET
PCIE_WAKE#_R
MASK_SATA_LED#
PCIE_WAKE#_R 2
RE275
1
0_0402_5%
1
0_0402_5%
NGFF_CONFIG_0
<39>
<36,9>
Stuff RE275 and no stuff RE274 keep E5 design
Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
SLICE_BAT_ON 2
RE17
NGFF_CONFIG_3
PCH_PCIE_WAKE#
<30>
WLAN_LAN_DISBL#
NGFF_CONFIG_1
NGFF_CONFIG_2
2
@ RE274
<39>
LED_SATA_DIAG_OUT#
NGFF_CONFIG_0
<30>
<47>
<21>
<21>
1
100K_0402_5%
C
<28>
NGFF_CONFIG_1
NGFF_CONFIG_2
<30>
<30>
NGFF_CONFIG_3
<30>
DIS_BAT_PROCHOT#
<55>
LPC_LAD0
<36,7>
LPC_LAD1
<36,7>
LPC_LAD2
<36,7>
LPC_LAD3
<36,7>
LPC_LFRAME#
<36,7>
PCH_PLTRST#_EC
<27,30,36,9>
CLK_PCI_SIO
<7>
CLKRUN#
<12,36,9>
CLK_PCI_SIO
CLKRUN#
LPC_LDRQ1#
IRQ_SERIRQ
<12,36>
EC_32KHZ_ECE5048
<36>
D_LAD0
<34>
D_LAD1
<34>
D_LAD2
<34>
D_LAD3
<34>
D_LFRAME#
<34>
D_CLKRUN#
<34>
D_DLDRQ1#
<34>
D_SERIRQ
<34>
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ
A29
B31
A30
BC_INT#_ECE5048
BC_DAT_ECE5048
BC_CLK_ECE5048
B
<36>
<36>
<36>
+3.3V_ALW
PWRGD
OUT65
TEST_PIN
VSS
EP
RUNPWROK
<36,9>
B19
B46
2
10K_0402_5%
+CAP_LDO trace width 20 mils
1
10_0402_5%
LID_CL#
<39>
1
2
CE8
0.047U_0402_16V4Z
n
o
i
t
a
c
o
l
p
o
p
e
d
I
M
E
A
2
RE26
LID_CL_SIO#
CLK_PCI_SIO
2
B27
C1
1
RE24
+CAP_LDO
@EMC@ CE9
@EMC@ RE27
33P_0402_50V8J
33_0402_5%
DB Version 0.4
ECE5048-LZY_DQFN132_11X11~D
RUNPWROK
CE7
4.7U_0603_6.3V6K
CAP_LDO
A4
B56
RE25
100K_0402_5%
<9>
BT_RADIO_DIS#
WWAN_RADIO_DIS#
A33
B36
A34
B37
A35
B38
A36
A37
B40
A38
B41
A39
B42
A40
B43
A41
B44
2
2
PROCHOT_GATE
LID_CL_SIO#
DOCK_SMB_ALERT#
TOUCH_SCREEN_PD#
1
+3.3V_RUN
GPIOI0
GPIOI1
GPIOI2/TACH0
GPIOI3
GPIOI4
GPIOI5
GPIOI6
GPIOI7
1
100K_0804_8P4R_5%
<28>
GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
GPIOA6
GPIOA7
2
NGFF_CONFIG_0
NGFF_CONFIG_1
NGFF_CONFIG_2
NGFF_CONFIG_3
B52
A49
B53
A50
B54
A51
B55
A52
1
1
2
3
4
DOCKED_LIO_EN
2
RPE4
8
7
6
5
<31>
2
WWAN_WAKE# 2
10K_0402_5%
1
1
RE9
1
1
RE8
UE1
2
RE10
PCIE_WAKE#_R
10K_0402_5%
B5
A17
B30
A43
A54
SLICE_BAT_PRES#
100K_0402_5%
WWAN_RADIO_DIS#
100K_0402_5%
2 WLAN_WIGIG60GHZ_DIS#
100K_0402_5%
2
DOCK_SMB_ALERT#
100K_0402_5%
VCC1
VCC1
VCC1
VCC1
VCC1
2
CE6
0.1U_0402_25V6
2
1
CE5
0.1U_0402_25V6
1
RE5
CE4
0.1U_0402_10V7K
D
PAD-OPEN1x1m
CE3
0.1U_0402_25V6
<32,36>
CE2
0.1U_0402_25V6
USB_PWR_SHR_EN#
100K_0804_8P4R_5%
CE1
10U_0603_6.3V6M
1 USB_PWR_SHR_VBUS_EN
2
USB_PWR_EN1#
3
USB_PWR_EN2#
4
1
RPE9
8
7
6
5
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
35
of
56
5
4
3
2
1
+RTC_CELL
2
1
1
RE60
CE24 1
2
43_0402_5%
2 2200P_0402_50V7K
CE26 1
2 2200P_0402_50V7K
CE27 1
10K_8P4R_5%
THERMATRIP3#
H_PROCHOT#
V_SYS
<54>
I_SYS
<54>
<40>
<52,54,9>
JFAN1
GND1
GND2
WIGIG
DP4/DN4
V.R
+5V_RUN
ACES_50271-0040N-001
DIMM
DN2a/DP2a
FAN1_PWM
FAN1_TACH
+3.3V_ALW
+3.3V_ALW
1
1
2
REM_DIODE1_P
E
2
2
B
QE3
MMBT3904WT1G_SC70-3~D
REM_DIODE1_N
THERMATRIP2#
+1.05V_RUN
1
3
1
C
DP2/DN2 for SODIMM on QE5, place QE5 close
to SODIMM and CE37 close to QE5
1
RE70
2
2
2.2K_0402_5% B
3
E
DN2a/DP2a for WiGig on QE7, place QE7 close
to WiGig and CE46 close to QE7
2
1
2
1
1
3
2
3
1
1
2
E
2
B
QE5
MMBT3904WT1G_SC70-3~D
REM_DIODE2_N
THSEL_STRAP 1
RE78
2
1K_0402_5%
VSET_5085
E
2
2
B
QE6
MMBT3904WT1G_SC70-3~D
1
2
1
1
2
1
C
3
1
2
1
2
FWP#
1
BOARD_ID
C
RE77
1.58K_0402_1%
X00
X01
X02
A00
2
QE7
H_THERMTRIP#
C
REM_DIODE4_P
@ RE82
10K_0402_5%
4700p
4700p
4700p
4700p
CE40
4700P_0402_25V7K
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_PLTRST#_EC
240K
130K
33K
1K
REV
MMBT3904WT1G_SC70-3~D
<12>
DP4/DN4 for Skin on QE6, place QE6 close to Vcore VR choke.
@CE39
100P_0402_50V8J
*
+3.3V_RUN
CE40
B
reserve for DC fan
CE38
0.1U_0402_25V6
RE79
RE81
10K_0402_5%
<35>
RE79
240K_0402_5%
EC5048_TX
1
CPU
1
2
3
4
5
6
2
1
2
3
4
1
1
2
3
5
4
1
2
6
1
1
1
1
1
2
2
2
2
<54>
Place QE3 under CPU
Place CE35 close to the QE3 as possible
@ CE46
100P_0402_50V8J
+3.3V_ALW
HOST_DEBUG_TX
Pin8 5075_TXD for EC Debug
pin9 5048_TXD for SBIOS
debug
8
7
6
5
CE36
0.1U_0402_25V6
8
7
6
5
+3.3V_ALW
RPE6
1
2
3
4
THERMATRIP3#
CHARGER_SMBDAT
CHARGER_SMBCLK
PCH_RSMRST#
QE4
MMST3904-7-F_SOT323-3
1
<9>
2 2200P_0402_50V7K
VCP
@ CE37
100P_0402_50V8J
1
2
3
4
+1.05V_RUN
PECI_EC
C283, C285, C286, C287 Place near U38
THERMATRIP2#
THERMATRIP3#
THSEL_STRAP
H_PROCHOT#
1
2
RE64
4.7K_0402_5%
@ CE35
100P_0402_50V8J
RE74
10K_0402_5%
2
100K_0804_8P4R_5%
VSET_5085
RUNPWROK
QE2B
DMN66D0LDW-7_SOT363-6
RUN_ON
QE2A
DMN66D0LDW-7_SOT363-6
2
+RTC_CELL
2
1
2
REM_DIODE4_N
REM_DIODE4_P
8
7
6
5
<27>
1
B66
PECI_EC_R
REM_DIODE1_N
REM_DIODE1_P
REM_DIODE2_N
REM_DIODE2_P
POA_WAKE#
VCI_IN2#
1
1
2
1
2
1
2
2
1
2
1
1
B13
A13
B14
A14
A15
B16
A16
B17
B15
A17
A12
B34
A2
B29
A46
B61
A57
POA_WAKE#
1
2
3
4
BC_DAT_ECE1117
REM_DIODE2_P
MSCLK
MSDATA
CLK_PCI_LPDEBUG
C
RPE5
+3.3V_ALW2
RE69
8.2K_0402_5%
2
2
2
B51
A48
POA_ON/OFF#
<27>
ACAV_IN
<54,55>
ALWON
<48>
ACAV_IN
ALWON
POWER_SW_IN#
DOCK_PWR_SW#
VCI_IN2#
POA_WAKE#
2
1K_0402_5%
@ DE1
RB751S40T1G_SOD523-2
1
B62
A64
A60
B67
A63
B63
B68
1
RE57
5085 Channel Location
+3.3V_ALW
EMI depop location
@ RE75
100K_0402_5%
RE73
10K_0402_5%
RE72
10K_0402_5%
RPE7
10K_8P4R_5%
RE71
49.9_0402_1%
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
+3.3V_ALW
A59
RE67
10K_0402_5%
2
USH_SMBDAT
USH_SMBCLK
8
7
6
5
2.2K_0804_8P4R_5%
CE32
10U_0603_6.3V6M
1
GPU_SMBDAT
GPU_SMBCLK
CHARGER_SMBDAT
CHARGER_SMBCLK
DP2/DN2
+3.3V_ALW
+3.3V_ALW_DEG
+3.3V_RUN
RPE3
1
2
3
4
DOCK_SMB_DAT
DOCK_SMB_CLK
GPU_SMBDAT
GPU_SMBCLK
CONN@
RE68
100K_0402_5%
CE29
22P_0402_50V8J
YE1
32.768KHZ_12.5PF_Q13FC135000040
<9>
<9>
DOCK_SMB_DAT
<34>
DOCK_SMB_CLK
<34>
A_ON
<38,50>
SIO_EXT_WAKE#
<12>
SYS_PWROK
<9>
ENVDD_PCH
<10,23>
GPU_SMBDAT
<40>
GPU_SMBCLK
<40>
CHARGER_SMBDAT
<54>
CHARGER_SMBCLK
<54>
SIO_SLP_SUS#
<9>
PBAT_PRES#
<47,54,55>
USH_SMBDAT
<27>
USH_SMBCLK
<27>
+3.3V_RUN
<36,38>
HB_A531015-SCHR21
11
12
AC_PRESENT
SIO_PWRBTN#
E
N
O
D
K
N
I
L
0
0
S
T
0
0
0
2
0
P
S
MEC_XTAL2
@EMC@ CE34
4.7P_0402_50V8C
@EMC@ RE66
10_0402_5%
2
CE28
22P_0402_50V8J
@ RE65
100_0402_1%
CE30
1U_0402_6.3V6K
JTAG1 CONN@
@SHORT PADS~D
CONN@
JDEG1
1
2
3
4
5
G1 6
G2 7
8
9
10
DOCK_SMB_DAT
DOCK_SMB_CLK
A_ON
n
g
i
s
e
D
l
a
m
r
e
h
T
r
o
f
g
n
i
t
t
e
S
RE63
100K_0402_5%
1
+3.3V_ALW
1
2
3
4
5
6
7
8
9
10
AC_PRESENT
SIO_PWRBTN#
A3
B4
A4
B5
B7
A7
B48
B49
A47
B50
B52
A49
B53
A50
+3.3V_ALW
Thermal diode mapping
RUN_ON#
CONN@
JLPDE1
PM_APWROK
RESET_OUT#
PCH_PCIE_WAKE#
A54
B58
<37>
BREATH_LED#
<34,39>
BAT1_LED#
<39>
BAT2_LED#
<39>
ALW_PWRGD_3V_5V
<48>
SIO_SLP_A#
<50,9>
for no‐dock : B2 use Free
EC_32KHZ_ECE5048
<35>
ME_SUS_PWR_ACK
<9>
RUN_ON
<36,38>
PM_APWROK
<9>
RESET_OUT#
<15,9>
PCH_PCIE_WAKE#
<35,9>
DP1/DN1
Place close pin A29
A
PCH_RSMRST#
B57
B1
A55
A1
B28
B2
A8
B9
A9
B39
A44
CLK_PCI_MEC
32 KHz Clock
MEC_XTAL1
11
12
PCH_ALW_ON
SIO_SLP_S3#
PCH_DPWROK
MSDATA
MSCLK
PCH_RSMRST#
FWP#
ESR <2ohms
JTAG_RST#
1
2
3
4
5
6
7
8
9
10
ME_FWP_EC
<6>
RUNPWROK
<35,9>
EN_INVPWR
<23>
SIO_SLP_S4#
<49,9>
SIO_SLP_LAN#
<28,9>
USB_PWR_SHR_EN#
<32,35>
PCH_ALW_ON
<38>
SIO_SLP_S3#
<49,9>
PCH_DPWROK
<9>
RUNPWROK
EN_INVPWR
MEC5085-LZY_DQFN132_11X11
CE31
4.7U_0603_6.3V6K
+3.3V_ALW
1
2
3
4
5
G1 6
G2 7
8
9
10
1
XTAL1
XTAL2
15mil
B
2
VREF_PECI
PECI_DAT
DN1_DP1A/THERM
DP1_DN1A/VREF_T
DN2_DP2A
DP2_DN2A
DN3_DP3A
DP3_DN3A
DN4_DP4A
DP4_DN4A
VIN
VSET
VCP
THERMTRIP2#
GPIO002/THERMTRIP3#
GPIO024/THSEL_STRAP
PROCHOT_IN#/PROCHOT_IO#
V_ISYS0
V_ISYS1
mCARD_PCIE#_SATA
<6,7>
LAN_WAKE#
<12,28>
LAN_WAKE#
HOST_DEBUG_TX
2
A61
A62
GPIO011/nSMI
GPIO061/LPCPD#
SER_IRQ
LRESET#
PCI_CLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
CLKRUN#
GPIO100/NEC_SCI
AGND
MEC_XTAL1
MEC_XTAL2_R
0_0402_5%
BGP0
VCI_OVRD_IN
VCI_OUT
VCI_IN0#
VCI_IN1#
VCI_IN2#
VCI_IN3#
<47,55>
1
A6
A27
A28
B30
A29
B31
A30
B32
A31
B33
A32
A33
SYSPWR_PRES
H_VSS
SIO_EXT_SMI#
SIO_RCIN#
IRQ_SERIRQ
PCH_PLTRST#_EC
CLK_PCI_MEC
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#
GPIO123/BCM_A_CLK
GPIO122/BCM_A_DAT
GPIO121/BCM_A_INT#
GPIO032/BCM_E_CLK
GPIO031/GPTP-OUT2/BCM_E_DAT
GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7
GPIO047/LSBCM_D_CLK
GPIO046/LSBCM_D_DAT/GANG_STROBE
GPIO045/LSBCM_D_INT#
VSS_RO
A43
B45
A42
B20
A18
B19
A20
B21
A19
AC_DIS
BOARD_ID
CE25
0.1U_0402_25V6
1
<34>
RE58
100K_0402_5%
<12>
SIO_EXT_SMI#
<12>
SIO_RCIN#
<12,35>
IRQ_SERIRQ
<27,30,35,9>
PCH_PLTRST#_EC
<7>
CLK_PCI_MEC
<35,7>
LPC_LFRAME#
<35,7>
LPC_LAD0
<35,7>
LPC_LAD1
<35,7>
LPC_LAD2
<35,7>
LPC_LAD3
<12,35,9>
CLKRUN#
<12>
SIO_EXT_SCI#
MEC_XTAL2 2
@ RE61
SIO_SLP_S5#
BEEP
BC_CLK_ECE1117
BC_DAT_ECE1117
BC_INT#_ECE1117
BC_CLK_ECE5048
BC_DAT_ECE5048
BC_INT#_ECE5048
<35>
BC_CLK_ECE5048
<35>
BC_DAT_ECE5048
<35>
BC_INT#_ECE5048
<54,55>
ACAV_IN_NB
<9>
SIO_SLP_S5#
<21>
BEEP
<37>
BC_CLK_ECE1117
<37>
BC_DAT_ECE1117
<37>
BC_INT#_ECE1117
GPIO003/I2C1A_DATA
GPIO004/I2C1A_CLK
GPIO005/I2C1B_DATA/BCM_B_DAT
GPIO006/I2C1B_CLK/BCM_B_CLK
GPIO012/I2C1H_DATA/I2C2D_DATA
GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA3
GPIO130/I2C2A_DATA/BCM_C_DAT
GPIO131/I2C2A_CLK/BCM_C_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO141/I2C1F_DATA/I2C2B_DATA
GPIO142/I2C1F_CLK/I2C2B_CLK
GPIO143/I2C1E_DATA
GPIO144/I2C1E_CLK
B18
for no‐dock : A43 use BC_CLK_ECE1099
for no‐dock : B45 use BC_DAT_ECE1099
for no‐dock : A42 use BC_INT#_ECE1099
GPIO050/FAN_TACH1/GTACH0/GANG_START
GPIO051/FAN_TACH2/GANG _MODE
GPIO052/FAN_TACH3/GTACH1/GANG_ERROR
GPIO053/PWM0
GPIO054/PWM1/GPWM1
GPIO055/PWM2
GPIO056/PWM3/GPWM0
VR_CAP
BIA_PWM_EC
FAN1_PWM
GPIO151/GPTP-IN4/GANG_DATA2
GPIO152/GPTP-OUT4
B54
B22
A21
B23
B24
A23
B25
A24
SUS_ON
GPIO156/LED1/GANG_DATA1
GPIO157/LED0
GPIO153/LED2/GANG_DATA4
GPIO027/GPTP-OUT1
GPIO026/GPTP-IN1
GPIO001/ECSPI_CS1/32KHZ_OUT
GPIO015/GPTP-OUT7
GPIO016/GPTP-IN8
GPIO017/GPTP-OUT8
GPIO107/NRESET_OUT
GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY
GPIO145/I2C1K_DATA/JTAG_TDI
GPIO146/I2C1K_CLK/JTAG_TDO
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
JTAG_RST#
VSS_ADC
FAN1_TACH
GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0
GPIO110/PS2_CLK2/GPTP-IN6
GPIO111/PS2_DAT2/GPTP-OUT6
GPIO112/PS2_CLK1A
GPIO113/PS2_DAT1A
GPIO114/PS2_CLK0A
GPIO115/PS2_DAT0A
GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5
GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6
+VR_CAP B12
<34>
VTR
VTR
VTR
VTR
VTR
VTR
VSS
A51
B55
B56
A53
B47
VTR_ADC
B60
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
100K_0804_8P4R_5%
C
DOCK_PWR_BTN#
10K_0402_5%
2
H_VTR
A10
B10
B8
B27
B44
B46
B26
A25
B36
B37
B38
A34
A35
A36
A40
B43
A45
B65
1
GPIO021/RC_ID1
GPIO020/RC_ID2
GPIO014/GPTP-IN7/RC_ID3
GPIO025/UART_CLK
GPIO120/UART_TX/V2P_COUT_HI1
GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1
VCC_PWRGD
GPIO060/KBRST/BCM_B_INT#
GPIO101/ECGP_SCLK
GPIO103/ECGP_MISO
GPIO105/ECGP_MOSI
GPIO102/BCM_C_INT#
GPIO104/SLP_S0#
GPIO106
GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP
GPIO117/MSCLK/V2P_COUT_HI
GPIO127/A20M
nFWP
B11
DOCK_POR_RST#
<30,49>
SUS_ON
trace width 20 mils
<47>
PS_ID
trace width 20 mils
<9>
SUSACK#
<23>
BIA_PWM_EC
RUN_ON
SUS_ON
A_ON
PCH_ALW_ON
2
2
1
2
VBAT
C1
1
1
2
2
1
1
1
1
2
1
1
1
for no‐dock : A21 use LID_CL_SIO#
1
2
3
4
2
2
2
1
RPE10
PBAT_SMBDAT
PBAT_SMBCLK
A5
B6
A37
B40
A38
B41
A39
B42
B59
A56
SML1_SMBDATA
SML1_SMBCLK
CLK_TP_SIO
DAT_TP_SIO
DOCK_POR_RST#
100K_0402_5%
RE277
8
7
6
5
2
2
2
2
2
2
MSDATA
10K_0402_5%
1
CE19
0.1U_0402_25V6
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
4.7K_8P4R_5%
1
RE86
B3
A11
A26
B35
A41
A52
<7>
SML1_SMBDATA
<7>
SML1_SMBCLK
<37>
CLK_TP_SIO
<37>
DAT_TP_SIO
for no‐dock : A38 use LCD_TST
<34>
CLK_KBD
for no‐dock : B41 use Free
<34>
DAT_KBD
for no‐dock : A39 use SLP_ME_CSW_DEV#
<34>
CLK_MSE
for no‐dock :B42 use Free
<34>
DAT_MSE
<47>
PBAT_SMBDAT
<47>
PBAT_SMBCLK
RPE2
8
7
6
5
CE23
0.1U_0402_25V6
PAD-OPEN1x1m
CE18
0.1U_0402_25V6
1
A58
+5V_RUN
1
2
3
4
A22
CE22
0.1U_0402_25V6
2
RE55
@ RE56
+3.3V_ALW_UE2
CE17
0.1U_0402_25V6
1
EN_INVPWR
100K_0402_5%
RESET_OUT#
8.2K_0402_5%
2
D
2
@CE16
0.1U_0402_25V6
2
1
RE42
DOCK_PWR_SW#
<39,9>
UE2
B64
PJP15
1
CE21
10U_0603_6.3V6M
1
+3.3V_ALW
FAN1_PWM
10K_0402_5%
FAN1_TACH
10K_0402_5%
2
2
POWER_SW#_MB
C
2
1
RE51
10K_0402_5%
@ CE44
1
2
1U_0402_6.3V6K
CE45
1U_0402_6.3V6K
1
RE48
2
CE12
1U_0402_6.3V6K
+3.3V_RUN
1
RE33
POWER_SW_IN#
CE15
1U_0402_6.3V6K
CE20
0.1U_0402_25V6
D
CE14
1U_0402_6.3V6K
CE13
0.1U_0402_25V6
+3.3V_ALW_UE2
1U_0402_6.3V6K
2
1
2
+3.3V_ALW_UE2
+RTC_CELL
@ CE10
1
2
E
RE43
+RTC_CELL
B
2
RE37
+RTC_CELL_VBAT
0_0402_5%
RE62
100K_0402_5%
1
BC_DAT_ECE5048
100K_0402_5%
PBAT_SMBDAT
2.2K_0402_5%
PBAT_SMBCLK
2.2K_0402_5%
RE31
100K_0402_5%
2
CE11
0.1U_0402_25V6
2
1
1
1
@ RE32
1
RE36
EP
+3.3V_ALW
REM_DIODE4_N
A
Channel 1
Thermal Monitoring Interface Strap Option
HIGH
Thermistor Readings
LOW
Diode Readings
Rest=1.58K , Tp=96 degree
BOARD_ID rise time is measured from 5%~68%.
<7>
HB_A531015-SCHR21
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
1
Sheet
36
of
56
5
4
3
2
1
D
D
Touch Pad
Keyboard
1
2
1
2
@EMC@ CZ31
10P_0402_50V8J
@EMC@ CZ30
10P_0402_50V8J
C
+3.3V_TP
DAT_TP_SIO
CLK_TP_SIO
17
18
1
BC_CLK_ECE1117
2
<36>
CLK_TP_SIO
1
1
2
1
2
<36>
<36>
+3.3V_TP +3.3V_ALW +5V_RUN
@ CZ29
0.1U_0402_25V6
DAT_TP_SIO
+5V_RUN
+3.3V_ALW
BC_INT#_ECE1117
BC_DAT_ECE1117
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
@ CZ28
0.1U_0402_25V6
CLK_TP_SIO
JKBTP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
KB_DET#
@ CZ27
0.1U_0402_25V6
<36>
RZ19
4.7K_0402_5%
DAT_TP_SIO
RZ18
4.7K_0402_5%
PAD-OPEN1x1m
<36>
CONN@
<11,12>
2
2
+3.3V_TP
1
1
+3.3V_TP
PJP16
2
+3.3V_RUN
Place close to JKBTP1
GND1
GND2
ACES_50506-01641-P01
C
E
N
O
D
K
N
I
L
0
0
4
L
1
0
0
1
0
P
S
EMI depop location
@eDP Cable
@KBTP FFC
Part Number
RSMRST circuit
DC02C007A00
Description
H-CONN SET 13M MB-EDP
@eDP Cable w camera
Part Number
+5V_ALW_UZ5
1
2
CZ35
0.01U_0402_16V7K
2
RESET#
3
DC02C007B00
5
PCH_RSMRST#
1
2
RSMRST#
B
O
A
H-CONN SET 13M MB-EDP-CAMERA
Part Number
Description
FFC 16P G P0.5 PAD=0.3 66.5MM MB-TP 13M
@Audio Board FFC
Description
@eDP TS Cable w camera
0.1U_0402_25V6
NBX0001JH00
Part Number
NBX0001JP00
Description
FFC 12P F P.5 PAD=.35 26.85MM MB-AUDIO/B
@USH Board FFC
Description
H-CONN SET 13M MB-EDP-CAMERA-TS
Part Number
NBX0001JF00
Description
FFC 26P G P0.5 PAD=0.3 58MM MB-USH/B 13M
P
<36>
VCC
@ CZ34
1
2
GND
3
1
B
DC02C007900
+3.3V_ALW
4
PCH_RSMRST#_Q
G
1
2
UZ5
RZ22
10K_0402_5%
2
+3.3V_ALW
RZ21
33_0402_5%
1
+5V_ALW
Part Number
<9>
@SATA Cable-Spindle HDD
UZ6
TC7SH08FU_SSOP5~D
@LED Board FFC
B
Part Number
DC02C007800
Description
H-CONN SET 13M MB-SPINDLE HDD
Part Number
NBX0001JM00
Description
FFC 10P G P.5 PAD.3 192.5MM MB-LED/B 13M
RT9818A-44GU3_SC70-3
@SATA Cable-mSATA
Part Number
DC02C007700
@PWR Board FFC
Description
H-CONN SET 13M MB-MSATA HDD
@DC-IN Cable
Part Number
@RTC BATT
Description
FFC 6P G P0.5 PAD=0.3 31MM MB-PWR/B 13M
Part Number
NBX0001JN00
Description
FFC 8P F P0.5 PAD=0.3 170MM USH/B-FP VALIDITY
@FP FFC-TCS
Description
DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F
@ FAN
Part Number
NBX0001JL00
@FP FFC-Validity
Description
DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F
Part Number
Part Number
Part Number
NBX0001JO00
Description
FFC 8P F P0.5 PAD=0.3 164.8MM USH/B-FP_TCS
@ Speak
Description
Part Number
DC28A000800 FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
Description
PK230003Q0L SPK PACK ZJX 2.0W 4 OHM FG
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
37
of
56
4
2
1
2
1
2
ON
4
+5V_ALW
6
1
2
D
@ PJP18
VIN
VOUT
VIN
VOUT
7
1
+1.05V_RUN_UZ7
2
+1.05V_RUN
8
PAD-OPEN1x3m
2
1
G
3
1
2
3
4
1
2
6
3
RUN_ON
+1.05V_M
@
VBIAS
GND
GND
CT
5
9
TPS22965DSGR_SON8_2X2~D
+3.3V_ALW_PCH/+3.3V_M source
+3.3V_M
1
if support MODPHY off keep DSC solution
MODPHY timing spec 0.7V/us and <65us
C
RUN_ON
CZ64
470P_0402_50V7K
1
UZ7
<36>
CZ39
0.1U_0402_10V7K
CZ25
220P_0402_50V7K
2
QZ10B
DMN66D0LDW-7_SOT363-6
MPHYP_PWR_EN
QZ10A
DMN66D0LDW-7_SOT363-6
<12>
+1.05V_RUN source
4
1.05V_MODPHY_EN
5
+1.05V_MODPHY
CZ38
10U_0603_6.3V6M
RZ16
100K_0402_5%
MPHYP_PWR_EN#
6
5
2
1
RZ5
100K_0402_5%
+3.3V_ALW2
D
QZ6
SI3456DDV-T1-GE3_TSOP6
1
1
+1.05V_M
+5V_ALW
2
S
+1.05V_MODPHY
3
D
5
PJP19
PAD-OPEN1x2m
@
+3.3V_ALW
3
A_ON
4
+5V_ALW
<36>
5
PCH_ALW_ON
6
7
VIN1
VIN1
ON1
VBIAS
VOUT1
VOUT1
CT1
CT2
VIN2
VIN2
VOUT2
VOUT2
14
13
1
+3.3V_M_UZ8
@CZ40
@
CZ40
1
CZ41
2
470P_0402_50V7K
1
CZ42
2
470P_0402_50V7K
@ PJP20
1
2
2
0.1U_0402_10V7K
11
GND
ON2
C
12
10
9
8
+3.3V_ALW_PCH_UZ8
+3.3V_ALW_PCH
15
TPS22966DPUR_SON14_2X3
CZ43
0.1U_0402_10V7K
GPAD
1
1
2
<36,50>
2
UZ8
PAD-OPEN1x1m
2
@
+5V_RUN
+3.3V_RUN/+5V_RUN source
B
1
B
PJP21
PAD-OPEN1x3m
@
UZ9
3
4
5
RUN_ON
+3.3V_ALW
6
7
VIN1
VIN1
ON1
VBIAS
VOUT1
VOUT1
CT1
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
1
+5V_RUN_UZ9
@CZ44
@
CZ44
1
CZ45
2
470P_0402_50V7K
1
CZ46
2
1000P_0402_50V7K
@ PJP22
1
2
+3.3V_RUN
2
0.1U_0402_10V7K
11
10
9
8
+3.3V_RUN_UZ9
15
TPS22966DPUR_SON14_2X3
CZ47
0.1U_0402_10V7K
GPAD
14
13
12
1
1
2
2
+5V_ALW
PAD-OPEN1x3m
2
@
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
38
of
56
5
4
3
2
HDD LED solution for White LED
1
Battery LED
<6>
2
QZ3B
DMN66D0LDW-7_SOT363-6
4
3
SATA_ACT#
SATA_LED
3
RZ24
10K_0402_5%
1
+3.3V_ALW
QZ3A
DMN66D0LDW-7_SOT363-6
1
6
DZ3
1
2
QZ4
DDTA114EUA-7-F_SOT323-3
SATA_LED#
<36>
2
QZ5B
DMN66D0LDW-7_SOT363-6
4
3
BAT2_LED#
DZ4
<35>
BAT2_LED#_Q
1
RZ25
2
390_0402_5%
BATT_WHITE#
BATT_YELLOW#
D
MASK_BASE_LEDS#
MASK_SATA_LED#
1
<35>
2
5
5
RB751S40T1G_SOD523-2
D
1
LED_SATA_DIAG_OUT#
QZ5A
DMN66D0LDW-7_SOT363-6
1
6
2
1
RZ27
MASK_BASE_LEDS#
2
220_0402_5%
<36>
BAT1_LED#
1
BAT1_LED#_Q
RZ28
2
330_0402_5%
2
RB751S40T1G_SOD523-2
MASK_BASE_LEDS#
WLAN LED solution for White LED
Breath LED
WIRELESS_LED#
C
3
QZ7B
DMN66D0LDW-7_SOT363-6
4
3 BREATH_LED#_Q
QZ7A
DMN66D0LDW-7_SOT363-6
1
6
<34,36>
QZ9
DDTA114EUA-7-F_SOT323-3
BREATH_LED#
2
WLAN_LED_Q#
2
<30,35>
WLAN_LED
1
RZ32
2
BREATH_WHITE_LED_SNIFF#
150_0402_5%
5
2
C
RZ31
100K_0402_5%
1
+3.3V_ALW
1
MASK_BASE_LEDS#
MASK_BASE_LEDS#
1
RZ34
1
RZ33
2
BREATH_WHITE_LED#
220_0402_5%
2
390_0402_5%
+3.3V_ALW
1
SYS_LED_MASK#
2
LID_CL#
O
A
3
<35,39>
B
G
<35>
LED board CONN
POWER board CONN
P
5
@ CZ48
1
2
0.1U_0402_25V6
4
MASK_BASE_LEDS#
+5V_ALW
UZ10
TC7SH08FU_SSOP5~D
+5V_ALW
B
<36,9>
POWER_SW#_MB
BREATH_WHITE_LED#
SATA_LED
BATT_YELLOW#
BATT_WHITE#
WLAN_LED
CONN@
JPWR1
1
2
3
4
5
6
1
2
3
4
5 GND
6 GND
<35,39>
LID_CL#
+3.3V_ALW
7
8
1
2
3
4
5
6
7
8
9
10
11
12
ACES_50506-00641-P01
1
2
3
4
5
6
7
8
9
10
E
N
O
D
K
N
I
L
0
0
R
F
1
0
0
1
0
P
S
BREATH_WHITE_LED_SNIFF#
CONN@
JLED1
<28>
B
E
N
O
D
K
N
I
L
0
0
Y
O
1
0
0
1
0
P
S
GND1
GND2
ACES_50506-01041-P01
LED Circuit Control Table
SYS_LED_MASK#
Fiducial Mark
@ FD1
1
FIDUCIAL MARK~D
@ FD2
1
LID_CL#
0
1
1
Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened)
X
0
1
@ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H11 @ H12 @ H13 @ H14
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8
A
A
FIDUCIAL MARK~D
@ H7 @ H8 @ H9 @ H10
H_4P0 H_4P0 H_4P0 H_4P0
1
1
1
1
1
1
1
1
@ FD3
1
1
1
FIDUCIAL MARK~D
@ H18 @ H19 @ H21 @ H22
H_3P3 H_3P3 H_3P3 H_3P3
@ H20
H_2P2
@ H23
H_2P2X2P6
@ ST1
CLIP_C5P5
@ FD4
1
1
1
1
1
1
1
1
1
1
1
1
DELL CONFIDENTIAL/PROPRIETARY
FIDUCIAL MARK~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
STANDOFF
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
1
Sheet
39
of
56
5
4
3
2
1
UV1A
Part 1 of 6
PEG_CRX_GTX_C_P0
PEG_CRX_GTX_C_N0
PEG_CRX_GTX_P1
PEG_CRX_GTX_N1
CV190
CV191
1 0.22U_0402_16V7K
1 0.22U_0402_16V7K
PEG_CRX_GTX_C_P1
PEG_CRX_GTX_C_N1
PEG_CRX_GTX_P2
PEG_CRX_GTX_N2
CV192
CV193
2
2
1 0.22U_0402_16V7K
1 0.22U_0402_16V7K
PEG_CRX_GTX_C_P2
PEG_CRX_GTX_C_N2
2
2
CV194
CV195
1 0.22U_0402_16V7K
1 0.22U_0402_16V7K
PEG_CRX_GTX_C_P3
PEG_CRX_GTX_C_N3
2
G
DGPU_PWR_ON
QV88
D
3
C
GFXCLK_REQ_Q#
S
1
GFXCLK_REQ#
PEG_CRX_GTX_C_P0
PEG_CRX_GTX_C_N0
PEG_CRX_GTX_C_P1
PEG_CRX_GTX_C_N1
PEG_CRX_GTX_C_P2
PEG_CRX_GTX_C_N2
PEG_CRX_GTX_C_P3
PEG_CRX_GTX_C_N3
RV195
10K_0402_5%
2
1
+3.3V_GFX_AON
L2N7002WT1G_SC-70-3
2
1
0_0402_5%
RV196 @
2
CV129
0.1U_0402_10V7K
1
@
1
UV14
TC7SH08FU_SSOP5~D
SYS_PEX_RST_MON#
RV187
10K_0402_5%
CLK_PCIE_GFX
CLK_PCIE_GFX#
2
1
2
3
1
DGPU_PEX_RST#
RV40 2
RV25
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
AF22
AE22
2 DGPU_PEX_RST_R#
1 0_0402_5%
2.49K_0402_1%
AC7
AF25
2
0_0402_5%
3
THERMATRIP_GPU#
1
GPU_PEX_RST_HOLD#
AB6
NC
NC
NC
THERMATRIP3#
QV78
L2N7002WT1G_SC-70-3
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AG3
AF4
AF3
+3.3V_GFX_AON
AE3
AE4
1
GPU_SMBCLK_R
2
1.8K_0402_5%
2
1.8K_0402_5%
2
10K_0402_5%
2
100K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
RV191
1
GPU_SMBDAT_R
RV192
1
NVVDD_PSI
NC
TSEN_VREF
NC
W5
AE2
AF2
RV125
1
GPU_HOT#
RV104
2
THERMATRIP_GPU#
RV103
2
RV188
2
GPU_PEX_RST_HOLD#
RV189
2
GC6_EVENT#
RV190
3V3_MAIN_EN
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA
PLLVDD
SP_PLLVDD
B7
A7
C9
C8
A9
B9
D9
D8
RV510
RV511
RV512
RV513
1
1
1
1
1
RV514 1
RV515
GPU_SMBCLK_R
GPU_SMBDAT_R
L6
M6
2
2 1.8K_0402_5%
1.8K_0402_5%
2
2 1.8K_0402_5%
1.8K_0402_5%
2
2 1.8K_0402_5%
1.8K_0402_5%
RV109
1
N6
XTAL_IN
XTAL_OUT
PEX_RST_N
PEX_TERMP
XTAL_SSIN
XTAL_OUTBUFF
C11
B10
2
1
GPU_CLK_27M_IN
GPU_CLK_27M_OUT
1
A10
XTALSSIN
C10 XTALOUTBUFF
RV23 1
RV39
1
Place close to ball
1
2
LV10
2
1
BLM18PG300SN1D_2P
+PLLVDD
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
C
2
100K_0402_5%
2
10K_0402_5%
RV92
GPU_GC6_FB_EN
+CORE_PLLVDD
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N
1
FBVREF_ALTV
2
2
2 10K_0402_5%
10K_0402_5%
1
2
1
2
CV33
22U_0603_6.3V6M
GPU_PEX_RST_HOLD#
@
1
2
RV24 200_0402_1%
1
@ RV140
CV112
4.7U_0603_6.3V6K
2
@
@
GFXCLK_REQ_Q#
D
NVVDD_PSI
CV49
0.1U_0402_10V7K
DV8
SYS_PEX_RST_MON#
RV29
10K_0402_5%
B
RV208
0_0402_5%
1
+3.3V_GFX_AON
AE8
AD8
AC6
GPU_PWM_VID
DGPU_PEX_RST#
NC
2
3
A
SYS_PEX_RST_MON#
1
2
PLTRST_GPU#
4
G
O
FBVREF_ALTV
GPU_PWM_VID
GPU_HOT#
CV46
22U_0603_6.3V6M
B
3V3_MAIN_EN
GC6_EVENT#
THERMATRIP_GPU#
CV134
0.1U_0402_10V7K
DGPU_HOLD_RST#
P
5
2
+3.3V_ALW
RV45
10K_0402_5%
1
+3.3V_RUN
AC9
AB9
AB10
AC10
AD11
AC11
AC12
AB12
AB13
AC13
AD14
AC14
AC15
AB15
AB16
AC16
AD17
AC17
AC18
AB18
AB19
AC19
AD20
AC20
AC21
AB21
AD23
AE23
AF24
AE24
AG24
AG25
PEX_WAKE_NC
GC6_EVENT#
G
PEG_CRX_GTX_P3
PEG_CRX_GTX_N3
GPU_GC6_FB_EN
2
1 0.22U_0402_16V7K
1 0.22U_0402_16V7K
2
2
GPU_GC6_FB_EN
D
2
2
C6
B2
D6
C7
F9
A3
A4
B6
A6
F8
C5
E7
D7
B4
B3
C3
D5
D4
C2
F7
E6
C4
S
CV188
CV189
PEG_CRX_GTX_P0
PEG_CRX_GTX_N0
CLK
PEG_CRX_GTX_N[0..3]
D
GPIO
PEG_CRX_GTX_N[0..3]
DACs
PEG_CRX_GTX_P[0..3]
PEG_CRX_GTX_P[0..3]
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
OVERT
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
I2C
PEG_CTX_GRX_N[0..3]
PEG_CTX_GRX_N[0..3]
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PCI EXPRESS
PEG_CTX_GRX_P[0..3]
AG6
AG7
AF7
AE7
AE9
AF9
AG9
AG10
AF10
AE10
AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22
PEG_CTX_GRX_P0
PEG_CTX_GRX_N0
PEG_CTX_GRX_P1
PEG_CTX_GRX_N1
PEG_CTX_GRX_P2
PEG_CTX_GRX_N2
PEG_CTX_GRX_P3
PEG_CTX_GRX_N3
PEG_CTX_GRX_P[0..3]
+1.05V_PEX_VDD
LV8
2
1
BLM18PG181SN1D_2P
+1.05V_PEX_VDD
B
GM108-ES-S-A1_FCBGA595
1
ES sample : Depop DV8,RV29 , Pop RV208
QS sample : pop DV8,RV29 , depop RV208
2
GND
1
GPU_SMBCLK_R
4
GPU_HOT#
2
2
0_0402_5%
5
1
RV133
4
GND
2
1
@ RV30
GPU_PWR_LEVEL
GPU_CLK_27M_OUT
CV35
10P_0402_50V8J
BAT54A-7-F_SOT23-3
YV1
27MHZ_12PF_X1E000021042600
3
GPU_CLK_27M_IN 1
IN
OUT
2
0_0402_5%
QV14B
3
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p
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m
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20
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0
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0
0
0
.
F
o
3
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t
F
F
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5
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8
D
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.
p
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0
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la
0
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6
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i
C
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r
CV34
10P_0402_50V8J
DGPU_PEX_RST#
1
2
GPU_SMBCLK
DMN66D0LDW-7_SOT363-6
DGPU_PWR_EN
GPU_SMBCLK
DGPU_PWR_EN
DMN66D0LDW-7_SOT363-6
A
A
GPU_SMBDAT_R
1
1
@ RV26
6
GPU_SMBDAT
GPU_SMBDAT
QV14A
2
0_0402_5%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
GPU_PWR_LEVEL
LOW
Low Performace
HIGH
High Performace
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
40
of
56
4
3
2
1
UV1E
UV1C
Part 3 of 6
s
s
e
r
d
d
A
e
v
a
l
S
S
C
2
I
AB5
AB4
AB3
AB2
AD3
AD2
AE1
AD1
AD4
AD5
n
o
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D
R
D
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A
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9
x
0
)
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9
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T2
T3
T1
R1
R2
R3
N2
N3
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P
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a
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s
i
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R
N1
M1
M2
M3
K2
K3
K1
J1
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
0
0
1
1
0
0
1
0
K
K
K
K
K
9
9
0
5
0
9
.
1
1
2
.
4
4
2
M4
M5
L3
L4
K4
K5
J4
NC
NC
NC
NC
FBA_CMD32
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BUFRST_N
NC
NC
NC
NC
NC
NC
NC
NC
NC
GPIO8
)
h
2
0
3
e
d
o
C
s
s
a
l
C
(
e
c
i
v
e
D
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t
a
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e
c
c
A
D
3
y
r
a
m
i
r
P
n
o
N
0 1
C
V3
V4
U3
U4
T4
T5
R4
R5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GENERAL
D
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
LVDS/TMDS
AC3
AC4
Y4
Y3
AA3
AA2
AB1
AA1
AA4
AA5
NC
NC
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
NC
MULTI_STRAP_REF0_GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
THERMDP
THERMDN
NC
NC
NC
NC
NC
VDD_SENSE
F11
AD10
AD7
B19
V5
V6
G1
G2
G3
G4
G5
G6
G7
V1
V2
W1
W2
W3
W4
A2
A26
AB11
AB14
AB17
AB20
AB24
AC2
AC22
AC26
AC5
AC8
AD12
AD13
AD15
AD16
AD18
AD19
AD21
AD22
AE11
AE14
AE17
AE20
AF1
AF11
AF14
AF17
AF20
AF23
AF5
AF8
AG2
AG26
B1
B11
B14
B17
B20
B23
B27
B5
B8
E11
E14
E17
E2
E20
E22
E25
E5
E8
H2
H23
H25
H5
D11
D10
E9
1
2
RV31
10K_0402_5%
SYS_PEX_RST_MON#
SYS_PEX_RST_MON#
E10
F10
D1
D2
E4
E3
D3
C1
F6
F4
F5
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
MULTI_STRAP_REF0_GND
MULTI_STRAP_REF1_GND
MULTI_STRAP_REF2_GND
1
RV93 1
@ RV95 1
@RV95
@RV96
@
RV96
2
2 40.2K_0402_1%
2 40.2K_0402_1%
40.2K_0402_1%
F12
E12
F2
GPU_VDD_SENSE
Part 5 of 6
GND_001
GND_002
GND_003
GND_004
GND_005
GND_006
GND_007
GND_008
GND_009
GND_010
GND_011
GND_012
GND_013
GND_014
GND_015
GND_016
GND_017
GND_018
GND_019
GND_020
GND_021
GND_022
GND_023
GND_024
GND_025
GND_026
GND_027
GND_028
GND_029
GND_030
GND_031
GND_032
GND_033
GND_034
GND_035
GND_036
GND_037
GND_038
GND_039
GND_040
GND_041
GND_042
GND_043
GND_044
GND_045
GND_046
GND_047
GND_048
GND_049
GND_050
GND_051
GND_052
GND_053
GND_054
GND_055
GND_056
GND_057
GND_058
GND_059
GND_060
GND_061
GND_062
GND_063
GND_064
GND_065
GND_066
GND_067
GND_068
GND_069
GND_070
GND_071
GND_072
GND_073
GND_074
GND_075
GND_076
GND_077
GND_078
GND_079
GND_080
GND_081
GND_082
GND_083
GND_084
GND_085
GND_086
GND_087
GND_088
GND_089
GND_090
GND_091
GND_092
GND_093
GND_094
GND_095
GND_096
GND_097
GND_098
GND_099
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND
5
Use 16mils trace for sense pin
1
0
1
0
1
0
1
1
K
1
.
0
3
NC
NC
GND_SENSE
GND
GND
F1
K11
K13
K15
K17
L10
L12
L14
L16
L18
L2
L23
L25
L5
M11
M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14
U16
U18
U2
U23
U26
U5
V11
V13
V15
V17
Y2
Y23
Y26
Y5
D
C
AA7
AB7
GPU_VSS_SENSE
GM108-ES-S-A1_FCBGA595
K
8
.
4
3
0
1
1
1
0
1
1
0
K
3
.
5
4
1
1
1
1
1
1
1
0
J5
N4
N5
P3
P4
J2
J3
B
H3
H4
NC
NC
NC
TEST
NC
NC
TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
NC
NC
NC
NC
AD9
AE5
AE6
AF6
AD6
AG4
GPU_TESTMODE
GPU_JTAG_TCK
GPU_JTAG_TDI
GPU_JTAG_TDO
GPU_JTAG_TMS
GPU_JTAG_TRST#
RV107 1
2 10K_0402_5%
RV108 1
2 10K_0402_5%
+3.3V_GFX_AON
B
RPV3
SERIAL
ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK
Decive ID change to 0x1056
5
6
7
8
GPU_JTAG_TCK
GPU_JTAG_TDI
GPU_JTAG_TDO
GPU_JTAG_TMS
D12
B12
A12
C12
ROM_SI_GPU
ROM_SO_GPU
ROM_SCLK_GPU
4
3
2
1
10K_8P4R_5%
GM108-ES-S-A1_FCBGA595
@
@ RV124
8.45K_0402_1%
1
2
RV123
8.45K_0402_1%
1
2
@
@ RV122
8.45K_0402_1%
1
2
@
RV98
8.45K_0402_1%
1
2
@
RV97
8.45K_0402_1%
1
2
+3.3V_RUN_GFX
RV94
8.45K_0402_1%
1
2
@ RV47
8.45K_0402_1%
1
2
RV49
49.9K_0402_1%
1
2
+3.3V_GFX_AON
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
ROM_SCLK_GPU
ROM_SI_GPU
ROM_SO_GPU
RV129
4.99K_0402_1%
1
2
RV59
20K_0402_1%
1
2
RV128
4.99K_0402_1%
1
2
RV99
2K_0402_1%
2
1
RV41
2K_0402_1%
2
@
@
1
RV127
2K_0402_1%
2
@
1
RV126
2K_0402_1%
2
@
1
@
1
RV157
2K_0402_1%
2
A
Strap Pin Name
Logical Strapping Bit 3
Logical Strapping Bit 2
Logical Strapping Bit 1
Logical Strapping Bit 0
VENDER
STRAP
ROM_SCLK
SOR3_EXPOSED->0
SOR2_EXPOSED->0
SOR1_EXPOSED->0
SOR0_EXPOSED->0
ROM_SCLK pull-down 4.99k to GND
Hynix
0x3
H5TC4G63AFR-11C
20k PD
ROM_SI
RAM_CFG[3]
RAM_CFG[2]
RAM_CFG[1]
RAM_CFG[0]
ROM_SI pull-down 20k to GND
Micron
0x4
MT41J256M16HA-093G:E
24.9k PD
need change to MT41K256M16HA-107G:E
ROM_SO
DEVID_SEL->0(default)
PCIE_CFG->0(defual)
VGA_DEVICE->0
ROM_SO pull-down 4.99k to GND
Samsung
0x5
K4W4G1646D-HC1A
30.1k PD
STRAP0
Keep pull up to 3V3_AON and pull-down to GND footprint and stuff 50k ohm pull up
SMB_ALT_ADDR->0(default)
Note
Note(ROM_SI)
STRAP0 pull up 50k to +3.3V_GFX_AON
A
STRAP1
STRAP2
STRAP3
STRAP4
Reserve
DELL CONFIDENTIAL/PROPRIETARY
DEVID_SEL/PCIE_CFG defaul set 0, need refer Platform Update Notification for the latest configuration
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
Part Number
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
41
of
56
5
4
3
2
1
UV1D
PLACE NEAR BALLS PLACE NEAR GPU
Part 4 of 6
n
o
i
t
a
l
1111
u
p
o
P
e
p
y
T
5
350
r2008
0
8
6
o
0
4
0
0
t
0
i
F
F
F
c
u
F
u
u
a
2
u
0
7
p
2
1
1
.
a
4
C
1
2
FB_CAL_PD_VDDQ
2
40.2_0402_1%
C24
1
RV44
2
42.2_0402_1%
B25
1
RV43
2
51.1_0402_1%
+1.35V_MEM_GFX
1
2
+3.3V_RUN_GFX
1
2
1
2
1
2
1
2
CV130
4.7U_0603_6.3V6K
1
RV42
2
CV198
1U_0402_6.3V6K
FB_CAL_TERM_GND
D22
1
o
t
t
c
e
n
n
o
c
n
i
p
2
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G
/A
O
0
1
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G
X
F
0_
G
.
2
V
3
63
.
C
G
+
G10
G12
G8
G9
PLACE NEAR GPU
CV164
4.7U_0603_6.3V6K
3V3_AON
3V3_AON
VDD33_3
VDD33_4
C
+3.3V_GFX_AON
1
AB8
2
PEX_PLLVDD_1
PEX_PLLVDD_2
2
1
2
AA14
AA15
2
6
0
.
0
2
6
0
.
0
5
0
.
1
D
D
V
A
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L
L
P
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B
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2
3
0
.
0
2
3
0
.
0
5
0
.
1
D
D
V
A
_
L
L
D
_
A
B
F
2
1
2
1
2
CV135
4.7U_0603_6.3V6K
1
CV205
1U_0402_6.3V6K
5
0
.
1
PLACE UNDER GPU PLACE NEAR GPU
GM108-ES-S-A1_FCBGA595
CV63
0.1U_0402_10V7K
5
0
.
1
D
D
V
L
L
P
_
X
E
P
NC
NC
NC
NC
NC
1
CV159
4.7U_0603_6.3V6K
AA8
AA9
CV160
4.7U_0603_6.3V6K
Q
/
D
D
V
O
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P
5 3
0
)
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A 3
1 B
7 .
1
(
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F
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D 6
A
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1
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0 0
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r
o
C
_
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P
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5
3
.
)
1
V
/
(
5
.
1
PEX_PLL_HVDD_1
PEX_PLL_HVDD_2
PEX_SVDD_3V3
J7
K7
K6
H6
J6
D
+3.3V_GFX_AON
CV64
0.1U_0402_10V7K
T
G
S
5
1
N
M
G
S
5
1
N
l
i
a
R
y
l
p
p
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w
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P
+1.05V_PEX_VDD
7
6
1
.
0
2
2
0
.
0
2
2
0
.
0
5
2
2
.
0
5
2
0
.
0
3
.
3
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0
3
.
3
D
D
V
H
_
L
L
P
_
X
E
P
B
g
n
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p
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D
D
D
V
L
L
P
_
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E
P
8
5
0
.
0
3
.
3
3
V
3
_
D
D
V
S
_
X
E
P
D
D
V
L
L
P
_
P
S
5 5 5 3
0
0
0
.
.
.
.
1
1
1
3
N
O
A
3
V
3
+
3
3
D
D
V
D
D
V
_
L
L
P
B
IFPD_PLLVDD_2
NC
IFPD_RSET
NC
2
AA22
AB23
AC24
AD25
AE26
AE27
PLACE NEAR BGA
T7
R7
U6
R6
1
+1.05V_PEX_VDD
CV199
1U_0402_6.3V6K
NC
NC
NC
NC
2
CV30
0.1U_0402_10V7K
M7
N7
T6
P6
2
1
PLACE UNDER GPU
FB_CAL_PU_GND
C
2
1
CV40
0.1U_0402_10V7K
NC
NC
NC
NC
NC
1
CV68
0.1U_0402_10V7K
Q
D
n
D
o
V
i
B
t
F
a
/
l
D
g
22211
u
D
n
p
V
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B
l
P
F
p
u
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p
d
c
y
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T
5
5
3
s
D
2
3
0
r00008
8
6
Ud o
4
6
0
0
0
P
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t
0
0
C
n
i
F
F
F
i
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F
F
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3b
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2
0
7
R
m
p
1
0
2
1
.
D
o
a
.
.
4
D
C
C
0
1
V7
W7
AA6
W6
Y6
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6
AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27
CV36
22U_0603_6.3V6M
2
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
CV16
10U_0603_6.3V6M
2
1
CV161
0.1U_0402_10V7K
2
1
CV163
0.1U_0402_10V7K
2
1
CV168
1U_0402_6.3V6K
2
1
CV165
1U_0402_6.3V6K
2
1
CV24
4.7U_0603_6.3V6K
2
1
CV47
4.7U_0603_6.3V6K
1
CV39
10U_0603_6.3V6M
2
D
CV43
22U_0603_6.3V6M
1
PLACE UNDER GPU
FBVDDQ_01
FBVDDQ_02
FBVDDQ_03
FBVDDQ_04
FBVDDQ_05
FBVDDQ_06
FBVDDQ_07
FBVDDQ_08
FBVDDQ_09
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_AON
FBVDDQ_AON
FBVDDQ_AON
FBVDDQ_AON
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
CV65
4.7U_0603_6.3V6K
PLACE NEAR GPU
B26
C25
E23
E26
F14
F21
G13
G14
G15
G16
G18
G19
G20
G21
H24
H26
J21
K21
L22
L24
L26
M21
N21
R21
T21
V21
W21
CV211
1U_0402_6.3V6K
I=2000mA
POWER
+1.35V_MEM_GFX
d
e
n
i
b
m
o
C
l
i
a
R
r
e
w
o
P
Q
/
D
D
V
O
I
_
X
E
P
PLACE BETWEEN GPU
AND POWER SUPPLY
g
n
i
l
p
u
o
c
e
D
N
O
A
_
3
V
3
n
o
i
t
a
l
111
u
p
o
P
e
p
y
2
3
T
30
0
6
r400
6
0
o
0
t
F
F
i
F
u
u
c
u
1
7
a
1
.
.
p
0
4
a
C
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
42
of
56
A
5
4
3
2
1
Caps on Power Side
1UX4 4.7UX10 under GPU
4.7UX5 22UX1 47UX2 330UX2 near GPU
D
D
UV1F
+GPU_CORE
VDD_001
VDD_002
VDD_003
VDD_004
VDD_005
VDD_006
VDD_007
VDD_008
VDD_009
VDD_010
VDD_011
VDD_012
VDD_013
VDD_014
VDD_015
VDD_016
VDD_017
VDD_018
VDD_019
VDD_020
POWER
Part 6 of 6
K10
K12
K14
K16
K18
L11
L13
L15
L17
M10
M12
M14
M16
M18
N11
N13
N15
N17
P10
P12
+GPU_CORE
VDD_041
VDD_040
VDD_039
VDD_038
VDD_037
VDD_036
VDD_035
VDD_034
VDD_033
VDD_032
VDD_031
VDD_030
VDD_029
VDD_028
VDD_027
VDD_026
VDD_025
VDD_024
VDD_023
VDD_022
VDD_021
V18
V16
V14
V12
V10
U17
U15
U13
U11
T18
T16
T14
T12
T10
R17
R15
R13
R11
P18
P16
P14
C
C
GM108-ES-S-A1_FCBGA595
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
43
of
56
3
2
FBA_D[0..63]
1
1
RV193
2
0_0402_5%
3
+5V_ALW
4
2
0_0402_5%
5
6
7
CT1
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
GPAD
2
12
1
CV139
2
0.1U_0402_10V7K
1
CV140
2
470P_0402_50V7K
11
1
CV141
10
9
8
+3.3V_RUN_GFX_UV15
2
470P_0402_50V7K
@ PJP30
1
2
+3.3V_RUN_GFX
15
TPS22966DPUR_SON14_2X3
CLKA0
CLKA0#
CLKA1
CLKA1#
PAD-OPEN1x1m
B
+1.35V_MEM_GFX
+1.35V_MEM
+5V_ALW
2
6
1
1
2
@ RV177
20K_0402_5%
A
RV209
10K_0402_5%
BAT54CW_SOT323-3
@ CV366
100P_0402_50V8J
2
2
QV83
SI4164DY-T1-GE3_SO8~D
1
2
3
DGPU_PWR_ON
RV179
2.2M_0402_5%
1
GPU_GC6_FB_EN
QV84A
DMN66D0LDW-7_SOT363-6
1
)
mh
m
h
o
o
01
3
0
.0
3
d=
0
a
6
e
R0
BE
S
(
3
5
QV84B
DMN66D0LDW-7_SOT363-6
5
0
8
0
F
u
2
2
2 1
2
0
4
0
F
u
1
.
0
DGPU_PWR_ON#
DV7
8
7
6
5
CV365
10U_0603_6.3V6M
+3.3V_ALW2
GM108-ES-S-A1_FCBGA595
DGPU_PWROK
+1.35V_MEM_GFX
1
D18
C18
D17
D16
T24
U24
V24
V25
2
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
VBIAS
+1.05V_PEX_VDD_UV15
1
FBA_CLK1
FBA_CLK1_N
N22
M22
ON1
14
13
2
3V3_MAIN_EN
1
RV185
VOUT1
VOUT1
1
FBA_CLK0
FBA_CLK0_N
1
2
1
2
1
3
1
3V3_MAIN_EN
VIN1
VIN1
RV176
470K_0402_5%
FBA_CMD34
FBA_CMD35
1
2
2
FB_CLAMP
UV15
+3.3V_RUN
D24
D25
PJP31
PAD-OPEN1x1m
@
+1.05V_M
4
F3
F22
J22
C
+1.05V_PEX_VDD
RV178
100K_0402_5%
D
D
V
A
n
_ o
L
i
L
t
D a
_
l
B
u
F
p
o
d P
n
a
e
p
D T
y
D
V r
A
_
d
o
Le i
t
L
n
P
i
c
_
b
a
xo
ma
p
B
F
CC
1
1 60.4_0402_1%
60.4_0402_1%
FB_DLLAVDD
S
DGPU_PWR_EN#
1
1 FB_CLAMP_GPU
10K_0402_5%
H22
FB_VREF_PROBE
FBA_WP0
FBA_WP1
FBA_WP2
FBA_WP3
FBA_WP4
FBA_WP5
FBA_WP6
FBA_WP7
D
2
G
DGPU_PWR_EN
1
2
I=35mA
D23
E19
C15
B16
B22
R25
W23
AB26
T26
D
3
1
+1.35V_MEM_GFX
2
@ RV46 2
@ RV130
PAD~D
FBA_RN0
FBA_RN1
FBA_RN2
FBA_RN3
FBA_RN4
FBA_RN5
FBA_RN6
FBA_RN7
+3.3V_GFX_AON
QV86
LP2301ALT1G_SOT23-3
1
2
RV48
@T95
FB_PLLAVDD_1
FB_PLLAVDD_2
F19
C14
A16
A22
P25
W22
AB27
T27
+5V_RUN
FBA_RST
2
@
2
B
F16
P22
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
+3.3V_RUN
FBA_CMD5
RV119 1
FBA_WP[0..7]
CV142
0.1U_0402_10V7K
1
CV48
0.1U_0402_10V7K
PLACE CLOSE to GPU
2
FBA_CMD31
D19
D14
C17
C22
P24
W24
AA25
U25
FBA_WP[0..7]
RV118 1
FBA_CMD19
3
2
1
CV45
0.1U_0402_10V7K
1
CV133
0.1U_0402_10V7K
2
CV32
22U_0603_6.3V6M
1
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD0
T110 PAD~D@
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
T111 PAD~D@
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
T112 PAD~D@
1
+FB_PLLAVDD
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD3
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
CV363
0.1U_0402_25V6
PLACE UNDER GPU
LV26
1
2
BLM18PG300SN1D_2P
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22
J23
J25
J24
K27
K25
J27
J26
RV117 1
G
+1.05V_PEX_VDD
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
RV132 1
FBA_CMD18
D
C
FBA_D00
FBA_D01
FBA_D02
FBA_D03
FBA_D04
FBA_D05
FBA_D06
FBA_D07
FBA_D08
FBA_D09
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
S
ODT
CKE
A13
A8
A6
A11
A5
A3
BA2
BA1
A12
A10
RAS#
E18
F18
E16
F17
D20
D21
F20
E21
E15
D15
F15
F13
C13
B13
E13
D13
B15
C16
A13
A15
B18
A18
A19
C19
B24
C23
A25
A24
A21
B21
C20
C21
R22
R24
T22
R23
N25
N26
N23
N24
V23
V22
T23
U22
Y24
AA24
Y22
AA23
AD27
AB25
AD26
AC25
AA27
AA26
W26
Y25
R26
T25
N27
R27
V26
V27
W27
W25
FBA_CMD2
QV87
L2N7002WT1G_SC-70-3
A13
A8
A6
A11
A5
A3
BA2
BA1
A12
A10
RAS#
CAS#
CS0#
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FBA_CKE_H
RV181
100K_0402_5%
CAS#
A14
RST
A9
A7
A2
A0
A4
A1
BA0
WE#
FBA_CKE_L
FBA_DQM[0..7]
RV114
10K_0402_5%
ODT
CKE
A14
RST
A9
A7
A2
A0
A4
A1
BA0
WE#
FBA_RN[0..7]
FBA_DQM[0..7]
Part 2 of 6
CMD32
CMD33
CMD34
CMD35
CMD36
CMD37
CMD38
CMD39
CMD40
CMD41
CMD42
CMD43
CMD44
CMD45
CMD46
CMD47
CMD48
CMD49
CMD50
CMD51
CMD52
CMD53
CMD54
CMD55
CMD56
CMD57
CMD58
CMD59
CMD60
CMD61
CMD62
CMD63
2
CS0#
FBA_ODT_H
FBA_RN[0..7]
MEMORY
INTERFACE A
D
CMD0
CMD1
CMD2
CMD3
CMD4
CMD5
CMD6
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD15
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
CMD30
CMD31
FBA_ODT_L
FBA_D[0..63]
UV1B
4
GDDR3L CMD Mapping Table
1
2
4
2
5
DGPU_PWR_ON
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
44
of
56
5
4
3
Memory Partition A - Upper 16 bits
FBA_D[0..31]
2
1
256x16 DDR3L
FBA_D[0..31]
FBA_WP[0..3]
FBA_WP[0..3]
FBA_DQM[0..3]
FBA_DQM[0..3]
FBA_RN[0..3]
FBA_RN[0..3]
D
D
FBA_CMD3
J7
K7
K9
FBA_CMD2
FBA_CMD0
FBA_CMD30
FBA_CMD15
FBA_CMD13
K1
L2
J3
K3
L3
CLKA0
CLKA0#
FBA_CMD3
RV145
1
2
162_0402_1%
1
2
1
2
1
2
1
2
1
2
PLACE UNDER DRAM
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
1
2
1
2
PLACE CLOSE DRAM
GND
1
2
FBA_CMD2
FBA_CMD0
FBA_CMD30
FBA_CMD15
FBA_CMD13
K1
L2
J3
K3
L3
FBA_WP0
FBA_WP3
F3
C7
FBA_DQM0
FBA_DQM3
E7
D3
FBA_RN0
FBA_RN3
G3
B7
FBA_CMD5
T2
FBA_ZQ1
L8
ADDRESS
DATA
J7
K7
K9
CK
CK
CKE
B1
B9
D1
D8
E2
E8
F9
G1
G9
96-BALL
SDRAM DDR3
H5TC4G63AFR-11C_FBGA96
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RESET
ZQ
D7
C3
C8
C2
A7
A2
B8
A3
FBA_D25
FBA_D29
FBA_D26
FBA_D28
FBA_D27
FBA_D30
FBA_D24
FBA_D31
C
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.35V_MEM_GFX
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
FBA_D1
FBA_D4
FBA_D3
FBA_D6
FBA_D0
FBA_D7
FBA_D2
FBA_D5
A1
A8
C1
C9
D2
E9
F1
H2
H9
1
2
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
1
2
1
2
1
2
1
2
PLACE UNDER DRAM
1
2
1
2
@ CV136
10U_0603_6.3V6M
CLKA0
CLKA0#
FBA_CMD3
BA0
BA1
BA2
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
CV187
1U_0402_6.3V6K
M2
N8
M3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
NC
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
CV186
1U_0402_6.3V6K
NC
NC
NC
NCZQ1
FBA_CMD12
FBA_CMD27
FBA_CMD26
VREFCA
VREFDQ
CV179
1U_0402_6.3V6K
ZQ
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
1
243_0402_1%
RV152
J1
L1
J9
L9
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
CV132
1U_0402_6.3V6K
L8
RESET
FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14
CV172
0.1U_0402_10V6K
FBA_ZQ0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
M8
H1
CV174
0.1U_0402_10V6K
T2
2
@ CV42
10U_0603_6.3V6M
FBA_CMD5
243_0402_1%
RV148
B
G3
B7
1
CV184
1U_0402_6.3V6K
FBA_CMD5
FBA_RN1
FBA_RN2
DML
DMU
20130610
10U reserve
CV183
1U_0402_6.3V6K
2
FBA_DQM1
FBA_DQM2
A1
A8
C1
C9
D2
E9
F1
H2
H9
CV178
1U_0402_6.3V6K
CV335
0.01U_0402_25V7K
@
1
E7
D3
DQSL
DQSU
+FBA_VREF_CA0
+FBA_VREF_DQ0
+1.35V_MEM_GFX
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CV131
1U_0402_6.3V6K
F3
C7
FBA_WP1
FBA_WP2
CLKA0_C
ODT
CS
RAS
CAS
WE
B2
D9
G7
K2
K8
N1
N9
R1
R9
CV151
0.1U_0402_10V6K
2
@
FBA_D17
FBA_D21
FBA_D18
FBA_D20
FBA_D19
FBA_D22
FBA_D16
FBA_D23
CV143
0.1U_0402_10V6K
FBA_CMD2
FBA_CMD0
FBA_CMD30
FBA_CMD15
FBA_CMD13
80.6_0402_1%
RV147
80.6_0402_1%
RV146
@
CK
CK
CKE
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
D7
C3
C8
C2
A7
A2
B8
A3
1
CLKA0
CLKA0#
BA0
BA1
BA2
FBA_D11
FBA_D13
FBA_D10
FBA_D15
FBA_D9
FBA_D14
FBA_D8
FBA_D12
Control & DQM
M2
N8
M3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
20130610
10U reserve
PLACE CLOSE DRAM
GND
FBA_CMD12
FBA_CMD27
FBA_CMD26
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
NC
ADDRESS
DATA
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
2
FBA_CMD12
FBA_CMD27
FBA_CMD26
FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14
UV18
VREFCA
VREFDQ
POWER
C
M8
H1
Control & DQM
FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14
+FBA_VREF_CA0
+FBA_VREF_DQ0
POWER
UV17
+FBA_VREF_CA0
+FBA_VREF_DQ0
J1
L1
J9
L9
NC
NC
NC
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
B
96-BALL
SDRAM DDR3
H5TC4G63AFR-11C_FBGA96
SA00006E800 Link done
SA00006E800 Link done
1
2
1
1.33K_0402_1%
RV144
2
+1.35V_MEM_GFX
1.33K_0402_1%
RV139
1
2
1
2
CV334
0.01U_0402_25V7K
2
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+FBA_VREF_DQ0
1.33K_0402_1%
RV112
1
CV326
0.01U_0402_25V7K
1.33K_0402_1%
RV110
1
+FBA_VREF_CA0
2
A
g
n
i
l
p
u
o
n
c
o
e
i
D
t
a
Q
l
/
u240
D
p
D
o
V
P
B
F
d
ye
r
n
e
ob
iy
p
m
eo
mT235
M
0
rCr
o0
40
68
eQt000
pD
/c
iFFF
u
3D
au
u0
RB
Va
p.
1.
01
D
DFC01
+1.35V_MEM_GFX
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
5
4
3
2
Sheet
1
45
of
56
A
5
4
3
Memory Partition A - Lower 16 bits
FBA_D[32..63]
2
1
256x16 DDR3L
FBA_D[32..63]
FBA_WP[4..7]
FBA_WP[4..7]
FBA_DQM[4..7]
FBA_DQM[4..7]
FBA_RN[4..7]
FBA_RN[4..7]
D
D
FBA_CMD18
FBA_CMD16
FBA_CMD30
FBA_CMD15
FBA_CMD13
K1
L2
J3
K3
L3
1
2
J1
L1
J9
L9
NC
NC
NC
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
1
2
1
2
PLACE UNDER DRAM
K1
L2
J3
K3
L3
FBA_WP4
FBA_WP7
F3
C7
FBA_DQM4
FBA_DQM7
E7
D3
FBA_RN4
FBA_RN7
G3
B7
FBA_CMD5
T2
FBA_ZQ3
L8
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
B1
B9
D1
D8
E2
E8
F9
G1
G9
96-BALL
SDRAM DDR3
H5TC4G63AFR-11C_FBGA96
RESET
ZQ
FBA_D56
FBA_D60
FBA_D58
FBA_D61
FBA_D57
FBA_D63
FBA_D59
FBA_D62
C
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.35V_MEM_GFX
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
PLACE CLOSE DRAM
GND
1
1
243_0402_1%
RV156
2
2
FBA_CMD18
FBA_CMD16
FBA_CMD30
FBA_CMD15
FBA_CMD13
CK
CK
CKE
D7
C3
C8
C2
A7
A2
B8
A3
A1
A8
C1
C9
D2
E9
F1
H2
H9
1
2
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
1
2
1
2
1
2
1
2
PLACE UNDER DRAM
1
2
1
2
@ CV158
10U_0603_6.3V6M
1
J7
K7
K9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
FBA_D35
FBA_D37
FBA_D34
FBA_D39
FBA_D33
FBA_D38
FBA_D32
FBA_D36
CV215
1U_0402_6.3V6K
ZQ
2
CLKA1
CLKA1#
FBA_CMD19
BA0
BA1
BA2
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
CV197
1U_0402_6.3V6K
L8
RESET
1
M2
N8
M3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
NC
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
CV209
1U_0402_6.3V6K
FBA_ZQ2
243_0402_1%
RV155
B
T2
2
FBA_CMD12
FBA_CMD27
FBA_CMD26
VREFCA
VREFDQ
CV173
1U_0402_6.3V6K
FBA_CMD5
FBA_CMD5
DQSL
DQSU
1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
CV204
0.1U_0402_10V6K
G3
B7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14
CV203
0.1U_0402_10V6K
2
DML
DMU
1
@ CV15
10U_0603_6.3V6M
CV218
0.01U_0402_25V7K
@
1
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
20130610
10U reserve
CV196
1U_0402_6.3V6K
FBA_RN6
FBA_RN5
DQSL
DQSU
+1.35V_MEM_GFX
CV210
1U_0402_6.3V6K
FBA_DQM6
FBA_DQM5
E7
D3
A1
A8
C1
C9
D2
E9
F1
H2
H9
CV208
1U_0402_6.3V6K
F3
C7
CLKA1_C
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CV170
1U_0402_6.3V6K
FBA_WP6
FBA_WP5
ODT
CS
RAS
CAS
WE
CV181
0.1U_0402_10V6K
2
1
@
B2
D9
G7
K2
K8
N1
N9
R1
R9
CV180
0.1U_0402_10V6K
2
FBA_CMD18
FBA_CMD16
FBA_CMD30
FBA_CMD15
FBA_CMD13
80.6_0402_1%
RV154
80.6_0402_1%
RV153
@
CK
CK
CKE
FBA_D44
FBA_D40
FBA_D46
FBA_D41
FBA_D45
FBA_D43
FBA_D47
FBA_D42
M8
H1
ADDRESS
DATA
J7
K7
K9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
D7
C3
C8
C2
A7
A2
B8
A3
+FBA_VREF_CA1
+FBA_VREF_DQ1
POWER
FBA_CMD19
FBA_CMD19
BA0
BA1
BA2
FBA_D52
FBA_D49
FBA_D53
FBA_D50
FBA_D54
FBA_D48
FBA_D55
FBA_D51
20130610
10U reserve
PLACE CLOSE DRAM
GND
CLKA1
CLKA1#
RV151
1
2
162_0402_1%
ADDRESS
DATA
M2
N8
M3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
1
CLKA1
CLKA1#
FBA_CMD12
FBA_CMD27
FBA_CMD26
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
NC
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
2
FBA_CMD12
FBA_CMD27
FBA_CMD26
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
POWER
C
FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14
UV20
VREFCA
VREFDQ
Control & DQM
FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14
M8
H1
Control & DQM
UV19
+FBA_VREF_CA1
+FBA_VREF_DQ1
J1
L1
J9
L9
NC
NC
NC
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
B
96-BALL
SDRAM DDR3
H5TC4G63AFR-11C_FBGA96
SA00006E800 Link done
SA00006E800 Link done
2
1
+1.35V_MEM_GFX
1.33K_0402_1%
RV150
2
20130606
reduce 1 ???
1.33K_0402_1%
RV149
1
+1.35V_MEM_GFX
1
2
2
1
2
CV217
0.01U_0402_25V7K
2
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+FBA_VREF_DQ1
1.33K_0402_1%
RV143
1
CV216
0.01U_0402_25V7K
1.33K_0402_1%
RV142
1
+FBA_VREF_CA1
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
5
4
3
2
Sheet
1
46
of
56
A
5
4
3
2
1
+COINCELL
1
COIN RTC Battery
PR1
1K_0402_5%
Z4012
2
+3.3V_RTC_LDO
@ JRTC1
1
2 1 G
2 G
+COINCELL
EMC@ PL1
FBMJ4516HS720NT_2P
1
Primary Battery Connector
PD3
+3.3V_ALW
2
D
PC1
1U_0603_10V4Z
2
+PBATT
2
PR2
1
2
3
4
5
6
7
8
9
10
PRP2
8
7
6
5
PBAT_SMBCLK_C
PBAT_SMBDAT_C
PBAT_PRES#_C
1
2
3
4
PBAT_SMBDAT
PBAT_SMBCLK
100K_0402_5%
<36>
<36>
PBAT_PRES#
<36,54,55>
PQ1
ME2301D-G 1P SOT-23-3
100_0804_8P4R_5%
PD4
1
2
1
3
3
11
12
1
PC3
2200P_0402_50V7K
2
1
1
1
EMC@PL2
EMC@
PL2
FBMJ4516HS720NT_2P
1
2
PBATT+_C
BAS40CW SOT-323
2
@PBATT1
11
12
+RTC_CELL
1
EMC@ PD2
TVNST52302AB0_SOT523-3
3
2
3
2
EMC@ PD1
TVNST52302AB0_SOT523-3
1
2
3
4
5
6
7
8
9
10
3
4
TYCO_2-1775293-2~D
1
1
3
D
DOCK_SMB_ALERT#
<34,35,55>
SDMK0340L-7-F_SOD323-2~D
2
2
TYU_TU1513WNV-100201J16
GND
<34,35,55>
1
SLICE_BAT_PRES#
2
1
PR6
0_0402_5%
PC4
2
C
C
1500P_0402_50V7K
+3.3V_ALW
EMC@ PL3
BLM15AG102SN1D_2P
2
1
<34>
1
DOCK_PSID
NO
IN
6
GPIO_PSID_SELECT
<35>
PR8
2
2.2K_0402_5%
PR9
33_0402_5%
1
2
S
2
G
PR10
2
3
D
1
2
NB_PSID
PU1
2
PR7
1
0_0402_5%
GND
V+
5
+5V_ALW
1
@
3
NB_PSID_TS5A63157
PQ2
FDV301N-G_SOT23-3
NC
COM
4
PS_ID
<36>
TS5A63157DCKR_SC70-6~D
+5V_ALW
2
B
1
1
1
100K_0402_1%
B
C
PQ3
MMST3904-7-F_SOT323~D
B
PR11
10K_0402_1%
2
2
3
E
PR12
15K_0402_1%
1
1
@ PR13
2
PSID_DISABLE#
<35>
10K_0402_5%
DC_IN+ Source
PJP1
1
DCX124EK-7-F PNP/NPN_SC74-6~D
1
2
PC10
10U_0805_25V6K
<55>
2
SOFT_START_GC
PR15
1
<36,55>
2
10K_0402_5%
100K_0402_5%
4
1
PR14
2
1
AC_DIS
PR18
2
1
1
5
5
PR17
1
PQ6A
6
ACES_50299-0050N-001
PR16
+DCIN_JACK
2
-DCIN_JACK
4.7K_0805_5%
7
6
5
4
3
2
1
@
A
5
4
3
2
1
@EMC@ PC11
0.1U_0603_25V7K
2
1
EMC@ PC9
1000P_0603_50V7K
2
1
GND
GND
1M_0402_5%
PQ6B
2
@ PJPDC1
+DC_IN_SS
PQ4
FDMC6679AZ_MLP8-5
1
2
3
PC5
0.022U_0805_50V7K
1
2
EMC@ PL4
FBMJ4516HS720NT_2P
1
2
4
3
DCX124EK-7-F PNP/NPN_SC74-6~D
+DC_IN
A
1M_0402_5%
2
DELL CONFIDENTIAL/PROPRIETARY
PAD-OPEN 1x3m
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
1
Sheet
47
of
56
A
B
C
1
D
E
1
+3.3V_ALW2 +3.3V_RTC_LDO
PR100
130K_0402_1%
1
2
PR101
150K_0402_1%
1
2
3VALWP
TDC 6.0 A
Peak Current 8.6 A
OCP Current 10.32 A
TYP
MAX
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 13.5mohm , 16.5mohm
Choke DCR 15.5mohm
CAP ESR 18mohm
1
FB_5V
2
PC102
10U_0805_25V6K
UG_5V
17
BST_5V
18
SW1
DRVL1
EN1
3
2
1
PC110
0.1U_0603_25V7K
2
BST_5V_C 1
SW1
EN
5
15
20
VIN
13
12
11
VREG5
SW2
DRVL2
8
4
PR109
2.2_0603_5%
1
2
LG_3V
LG_5V
4
4
3
2
1
+5V_ALW2
2
+3V5V_PWR_SRC
PL102
3.3UH_6.3A_20%
1
2
+5V_ALWP
PC115
220U_6.3V_M
16
VBST2
VBST1
SW2
2
TPS51285BRUKR_QFN20_3X3
DRVH2
DRVH1
1
9
2
10
@EMC@ PR112
4.7_1206_5%
UG_3V
PR110
2.2_0603_5%
1
2
BST_3V
1
PC109
0.1U_0603_25V7K
1
2 BST_3V_C
2
1
+
2
@EMC@ PC114
680P_0603_50V7K
PR114
200_0402_1%
1
2
VCLK
4
14
19
PGOOD
SIS412DN-T1-GE3_POWERPAK8-5
PQ101
7
PGOOD_3V_5V
21
SI7716ADN-T1-GE3_POWERPAK8-5
PQ103
VO1
5
CS1
VFB1
1
2
1
3
VREG3
VFB2
CS2
PAD
2
PQ100
SIS412DN-T1-GE3_POWERPAK8-5
1
2
3
5
EN2
SNUB_5V
3
PR106
PC118
4.7U_0603_10V6K
2
1
2
6
EN
PC117
0.1U_0603_25V7K
2
1
+
100K_0402_1%
PR107
PR108
0_0402_5%
1
2
3
EN
<36>
ALWON
1
PR113
0_0402_5%
2
+5V_ALWP
PJP101
1
2
+5V_ALW
5VALWP
TDC 3.5 A
Peak Current 5.0 A
OCP Current 6.0 A
TYP
MAX
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 13.5mohm , 16.5mohm
Choke DCR 25mohm
CAP ESR 18mohm
PAD-OPEN 1x3m
PJP102
+3.3V_ALWP
1
2
+3.3V_ALW
PAD-OPEN 1x3m
PC119
1U_0603_10V6K
2
1
PC113
220U_6.3V_M
1
@EMC@ PC111
@EMC@ PR111
680P_0603_50V7K
4.7_1206_5%
2
1 SNUB_3V 2
1
PL101
2.2UH_7.8A_20%
1
2
+3.3V_ALWP
PQ102
SI7716ADN-T1-GE3_POWERPAK8-5
1
2
3
5
1
2
PC101
10U_0805_25V6K
+PWR_SRC
@EMC@ PC105
2200P_0402_50V7K
2
1
2
PU100
1
2
PAD-OPEN 1x3m
+3V5V_PWR_SRC
16.9K_0402_1%
FB_3V
4
+3.3V_ALW
5
+3V5V_PWR_SRC
PR104
100K_0402_1%
1
2
PC100
4.7U_0603_10V6K
2
1
2
ALW_PWRGD_3V_5V
PJP100
1
PR103
0_0402_5%
PR105
30K_0402_1%
2
1
<36>
@EMC@ PL100
1UH_PCMB053T-1R0MS_7A_20%
1
2
1
PR102
200K_0402_1%
1
2
@
4
4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A
B
C
D
SCHEMATICS,MB AA913
Document Number
Rev
A
4019RA
Thursday, November 14, 2013
Sheet
E
48
of
56
5
4
3
2
1
0.675Volt +/‐ 5%
TDC 0.7 A
Peak Current 1.0 A
OCP Current 1.2 A
PJP200
1.35V_B+
BOOT_1.35V
0.22U_0603_16V7K
S1/D2
1
PAD
VTTGND
PGND
VTTSNS
2
20
VTT
19
VLDOIN
18
BOOT
UGATE
LGATE
PU200
21
1
2
+V_DDR_REF
CS_1.35V
13
PC209
1U_0603_10V6K
G2
12
CS
GND
RT8207MZQW_WQFN20_3X3
VDDP
VTTREF
3
4
+V_DDR_REF
PR202
+5V_ALW
+1.35V_MEN_P
5
C
PC212
0.033U_0402_16V7K
FB sense trace
when FB pull down to GND
FB
PC211
1U_0603_10V6K
VDDQ
6
+5V_ALW
VDD
S3
11
S5
VDD_1.35V
7
2
8
1
5.1_0603_5%
TON
6
S2
14
9
1
7
2
S2
S2
D1
G1
5
4
3
1
2
PR201
6.04K_0402_1%
1
2
17
16
DL_1.35V
PHASE
1
PC204
SW_1.35V
15
PQ201
AON6932A_DFN5X6-8-7
@EMC@ PR203
4.7_1206_5%
SNUB_1.35V
1
2
+0.675V_P
@EMC@ PC208
680P_0603_50V7K
2
PC207
220U_D2_2VY_R17M
+
C
+1.35V_MEN_P
2
DH_1.35V
Footprint use AON6932A
PL200
1.0UH_PCMB104T-1R0MH_18A_20%
1
2
1
+VLDOIN_1.35V
PAD-OPEN1x1m
2
1
2
@EMC@ PC203
2200P_0402_50V7K
1
PC201
10U_0805_25V6K
2
1
PC200
10U_0805_25V6K
2
@
+1.35V_MEN_P
1
D
PJP201
PR200
1
2
2.2_0603_5%
PC205
22U_0805_6.3V6M
2
PAD-OPEN 1x2m~D
PGOOD
1
10
+PWR_SRC
D
PR205
8.06K_0402_1%
1
2
1.35V_FB
PC213
100P_0402_50V8J
1
2
PR206
1
<18>
0.675V_DDR_VTT_ON
@ PC215
.1U_0402_16V7K
<9,36>
Mode
S5
S3
S0
S3
L
L
H
2
1
PR208
0_0402_5%
1
2
SIO_SLP_S3#
10K_0402_1%
PR209
PR210
0_0402_5%
1
2
@ PC214
.1U_0402_16V7K
2
SUS_ON
1
1M_0402_1%
1
<30,36>
2
B
+1.35V_MEM
TDC 9.45 A
Peak Current 13.5 A
OCP Current 16.2 A
TYP
MAX
H/S Rds(on) 6.7mohm , 8.5mohm
L/S Rds(on) 2.4mohm , 3.2mohm
Choke DCR 3.0mohm , 3.5mohm
CAP ESR 17mohm
SIO_SLP_S4#
1.35V_B+
S5_1.35V
2
<9,36>
@ PR207
0_0402_5%
1
2
B
@ PR211
0_0402_5%
1
2
+1.35V_MEN_P
S5 +1.35V_MEN +V_DDR_REF +0.675V_P
L
off
off
off
H
on
on
off
H
on
on
on
FB sense trace
PJP203
1
1
2
2
JUMP_1x3m
+1.35V_MEN_P
A
PJP202
PJP204
1
1
2
2
+0.675V_P
+1.35V_MEM
1
+0.675V_DDR_VTT
2
A
JUMP_1x3m
PAD-OPEN1x1m
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
49
of
56
5
4
3
2
1
D
D
PR301
0_0402_5%
1
2
A_ON
PR302 @
0_0402_5%
1
2
SIO_SLP_A#
<9,36>
1
EN_+V1.05SP
<36,38>
1M_0402_1%
PR303
PJP300
2
+1.05V_MP
1
1
2
+1.05V_M
2
JUMP_43X118
@EMC@ PR305
@EMC@ PC301
4.7_1206_5%
680P_0603_50V7K
1
2 SNB_1.05V 1
2
PJP302
PU300
2
1
SY8208DQNC_QFN10_3X3
2
@ PR306
0_0402_5%
1
2
B
1
2
@ PC308
22U_0805_6.3VAM
1
2
PR310
133K_0402_1%
2
@ PR308
0_0402_5%
C
1
ILMT_1.05V
+3.3V_ALW
PC307
22U_0805_6.3VAM
5
1
LDO
2
PG
FB_+V1.05SP
7
1
2
4
1
BYP
+1.05V_MP
2
PC306
47U_0805_6.3V6M
+3.3V_ALW
3
PL301
0.68UH +-20% 7.9A
1
2
ILMT
FB
ILMT_1.05V
SW_+V1.05SP
PC305
47U_0805_6.3V6M
LX
10
1
GND
PC302
PR312
0.1U_0603_25V7K
0_0603_5%
2BST_+V1.05SP_C
1
2
BST_+V1.05SP 1
2
9
1
6
PC304
330P_0402_50V7K
BS
PR309
1K_0402_5%
2
1
EN
PR307
100K_0402_1%
2
1
IN
PC310
4.7U_0603_6.3V6K
2
C
8
+V1.05SP_B+
10U_0805_25V6K
PC303
2
1
PAD-OPEN 1x2m~D
1
2
@EMC@ PC300
2200P_0402_50V7K
1
PC309
4.7U_0603_6.3V6K
2
1
+PWR_SRC
+1.05V_MEM
TDC 6.5 A
Peak Current 9.1 A
OCP Current 11.0 A
TYP
MAX
Choke DCR 13.0mohm , 14.0mohm
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
2
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
50
of
56
5
4
3
2
1
+3.3V_RUN
D
D
1
+5V_ALW
PJP400
2
PC400
1U_0402_6.3V6K
9
PU400
1
2
PR402
1.54K_0402_1%
+1.5V_RUN
PAD-OPEN1x1m
PC403
0.01U_0402_25V7K
1
VIN
2
PJP401
1
1.5VSP
1
FB
PC401
4.7U_0805_6.3V6K
3
2
GND
PC404
22U_0805_6.3V6M
2
APL5930KAI-TRG_SO8
1
1
EN
+1.5V_VIN
PR403
1.74K_0402_1%
C
2
C
2
@ PR401
47K_0402_5%
2
1
100K_0402_5%
@EMC@ PC402
.1U_0402_16V7K
8
1
2
5
4
1
VOUT
PR400
1
VIN
VOUT
2
POK
2
7
+3.3V_RUN
VCNTL
6
2
1
PAD-OPEN1x1m
+1.5V_RUN
TDC 0.47 A
Peak Current 0.67 A
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
51
of
56
5
4
3
2
1
VREF
2
PR504
1
+PWR_SRC
PJP500
VBAT
SLEWA
THERM
IMON
OCP-I
B-RAMP
F-IMAX
O-USR
SKIP#
PWM1
@ PR516
2
1.91K_0402_1%
2
PR519
1
1_0603_5%
<15>
+3.3V_RUN
+3.3V_RUN
PWM1
2
TPS51622RSM_QFN32_4X4
H_VR_READY
2
VIDALERT_N
1
PC509
1U_0603_10V7K
+5V_RUN
PR512
2.15K_0402_1%
2
1
CSP1
<15>
<15>
PC511
0.1U_0402_25V6
VIDSCLK
<15>
VIDALERT_N
VCCSENSE
from processor
VIDSOUT
<17>
VSSSENSE
PR531
0_0402_5%
1
PR515
3.01K_0402_1%
2
1
2
PR514
20K_0402_1%
2
1
1
2
PR529
110_0402_1%
1
2
PR528
75_0402_1%
1
2
1
2
<15>
PR527
54.9_0402_1%
B
@
2
2
VFB
2
+1.05V_VCCST
PR520
0_0402_5%
3
1
H_PROCHOT#
TI recommend 1nF
2SKIP#
1
PC514
<9,36,54,55>
VIDSCLK
1
1
1
PR526
10_0603_1%
2
+5V_ALW
PC510
1U_0603_10V7K
1
2
2
PR534
0_0402_5%
PC507
1
2
0.33U_0603_10V7K
PC512
1500P_0402_50V7K
2
1
1
PR535
4.75K_0402_1%
2
2
VREF
1
CSD97374CQ4M_SON8_3P5X4P5
PL500
0.15UH_PCME064T-R15MS0R667_36A_20%
4
1
CORE_SW
47P_0402_50V8J
1 PR523 2
10K_0402_5%
VR_HOT#
4.87K_0402_1%
100P_0402_50V8J
PC503
1000P_0402_50V7K
1
2
C
+VCC_CORE
4
3
2
1SKIP#1
1
2
PC502
0.068U_0402_16V7K
PR521
1
1
PC505
1U_0603_10V6K
@ PC506
1
2
PU501
9
PC504
8 PGND2
1
2 CORE_BOOT
7 PWM
BOOT VSW
0.1U_0402_25V6
PGND1
2
1 CORE_BOOT_R
6
5 BOOT_R VDD
PR517
VIN
SKIP#
0_0603_5%
PC513
0.068U_0402_16V7K
1
2
PH501
10K_0402_1%_TSM0A103F34D1RZ
DROP
COMP
VREF
V5A
GND
VR_HOT#
VCLK
ALERT#
GND
25
26
27
28
29
30
31
32
33
C
PR539
0_0402_5%
1
@ PR513
1
2
75_0402_1%
@EMC@ PC508
680P_0603_50V7K
CORE_SW_CSP
8
7
6
5
4
3
2
1
@EMC@ PR522
4.7_1206_5%
1CORE_SNUB2
1
VR_ON
SKIP#
PWM1
PWM2
N/C
PGOOD
VDD
VDIO
VIDSOUT
CSP1
CSN1
CSN2
CSP2
PU3
N/C
GFB
VFB
VFB
<15>
2
CSN1
17
18
19
20
21
22
23
24
H_VR_EN
+
2
2
PU500
+3.3V_RUN
+3.3V_RUN
1
0_0402_5%
16
15
14
13
12
11
10
9
CSP1
PR536
1
@EMC@ PC520
2200P_0402_50V7K
2
1
2
PC519
100U_D_20VM_R55M
10K_0402_5%
GFB
@EMC@ PL501
@EMC@PL501
1
2
FBMA-L11-453215-121LMA90T_2
2
PC518
10U_0805_25V6K
2
1
PR511
PC517
10U_0805_25V6K
2
1
1
+VCC_PWR_SRC
CORE_BOOT_C
+VCC_PWR_SRC
2
PAD-OPEN 4x4m
PC516
10U_0805_25V6K
2
1
1
PC515
10U_0805_25V6K
2
1
PR509
2
D
1
1
PR508
2
O-USR
100K_0402_1%
2
PR507
1
150K_0402_1%
36.5K_0402_1%
2
PR503
1
681K_0402_1%
2
PR502
1
75_0402_1%
2
PR501
1
365K_0402_1%
PC500
1
2
2
F-IMAX
1
1
PR510
39K_0402_5%~N
B-RAMP
PR506
2
SLEWA
@
OCP-I
39K_0402_1%
D
PC501
.1U_0402_16V7K
2
1
PR505
10K_0402_5%
1
2
1
2
@ PR500
75_0402_1%
4700P_0603_50V7K
2
PH500
IMON
20K_0402_1%
1
100K_0402_1%_NCP15WF104F03RC
B
CSN1
PR532
0_0402_5%
1
2
GFB
CPU 15W
TDC 10 A
Peak Current 32 A
OCP Current 38.4 A
DC Load line ‐2.0 mV/A
Icc_Dyn_VID1 27 A
Choke DCR: 0.66m +‐7% ohm
PH500 B Value : 4250k 1%
PH501 B Value : 3370k 1%
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
52
of
56
B
I_ripple=(19-0.9)*0.9/
(304.89Khz*0.36u*19)=7.811A
Vmin= Vvref*[Rref2/(Rref2+Rboot)]*[Rt/(Rref1+Rt)]
Vmax=Vvref*Rref2/[(Rref1//Rrefadj)+Rboot+Rref2]
Vout=Vmin+N*Vstep
OCP=54A/2=27A per phase
Ivalley=27A-7.811A/2=23.1A
Vstep=(Vmax-Vmin)/Nmax
PWM-VID Spec and component Values
1
Config A
Config B
Config C
Vmin
0.6V
0.6V
0.65V
Vmax
1.2V
1.2V
1.15V
Vboot
0.875V
0.9V
0.9V
6.25mV
6.25mV
25mV
Voltage step
Module model information:
RT8813A_V1A for IC module
RT8813A_V1B for SW module
N of Voltage level
96
96
20
Rrefadj
PR9
39K
20K
39K
Rref1
PR5
39K
20K
30K
Rboot
PR8
1.5K
2K
3K
PR10
30K
18K
24K
PR12
1.5K
0
3K
PC8
1.5nf
2.7nf
Rref2=PR10+PR12
C
L-side MOS:TPCA8057
Rds(on):
2.0mohm@Vgs=10V
2.6~3.2mohm@Vgs=4.5V
Id :42A@Ta=25 degC
H-side MOS:TPCA8065
Rds(on):
11.7mohm@Vgs=10V
9.4mohm@Vgs=4.5V
Id :16A@Ta=25 degC
Choke: 0.36uH (Size:10*10*4)
Rdc=1.1mohm +-5%
Heat Rating Current=30A
Saturation Current=50A
C=3*330uF (9mohm)=990uF
Vripple=Iripple*ESR(min)=7.811A*3mohm=23.4mV
1.8nf
@ PR601
1K_0402_5%
1
2
PWM VID and Output voltage control
1.Boot mode
2.Standby mode (don't support)
3.Normal mode
1
D
Different VGA Chip (different EDP-Peak Current) need select different solution
VGA Chip
N14P-GV
N14M-GS
N14M-LP
N14P-LP
OpenVReg Configurations
Config B
Config B
Config B
Config B
Config B
Rated TDP Power at Tj=102C
18W
25W
18W
13W
18.9W
25W
25.6W
35.5W
Boosted GPU Total at Tj=102C
25W
32W
25W
20W
23W
N/A
30W
40W
EDP-Continuous at Tj=102C
24A
32A
26A
22A
25A
27A
38A
45A
EDP-Peak at Tj=102C
35A
55A
45A
35A
35A
40A
60A
75A
Istep max (Evaluation)
15A
27A
25A
20A
14A
12A
31.5A
35A
OCP Setting Current
42A
66A
54A
42A
42A
48A
72A
90A
Rocset
8.96K
12.45K
10.7K
8.96K
8.96K
9.83K
8.3K
N14P-GV2
N14P-GE
Config B
2
GPU_PWM_VID
<40>
1
2phase 1H1L
2phase 1H1L
2phase 1H1L
2phase 1H1L
2phase 1H1L
2phase 1H1L
2phase 1H2L
2phase 1H2L
Polymer Cap (330uF)
6mohm * 2
9mohm * 3
9mohm * 3
6mohm * 2
6mohm * 2
6mohm * 2
6mohm * 3
(L=0.22uH)
4.5mohm * 3
(L=0.15uH)
Or OSCON (390uF)
10mohm * 3
10mohm * 3
10mohm * 3
10mohm * 3
10mohm * 3
10mohm * 3
Operation phase Number
PSI Voltage setting
1 phase with DEM
0V to 0.8V
1 phase with CCM
1.2V to 1.8V
Active phase with CCM
2.4V to 5.5V
EMC@ PL600
HCB2012KF-121T50_0805
110C
113.4C
2
2
U2_PHASE2
2
U2_LGATE2
19
1
U2_PWM3 U2_PWM3
21
20
@
2
1
PC604
10U_0805_25V6K
2
1
PC603
10U_0805_25V6K
@EMC@ PR613
4.7_1206_5%
8
U2_LGATE1
22
1
23
1
+
1
+
2@
2
@EMC@ PC614
680P_0603_50V7K
BOOT2
18
U2_BOOT2
RT8813AGQW_WQFN24_4X4
3
PC617
0.22U_0603_25V7K
PQ601
CSD87351Q5D_SON8-7
PR620
18.7K_0402_1%
2
1
1
PC621
10U_0805_25V6K
2
1
2
2
1
1
+GPU_PWR_SRC
PR618
4.7_0603_5%
2
U2_BOOT21
PC620
10U_0805_25V6K
PGOOD
UGATE2
17
16
VCC/ISNE1
U2_LGATE1
PR615
8.87K_0402_1%
BOOT1
EN
UGATE1
PSI
1
1
2
3
@EMC@ PC602
2200P_0402_50V7K
2
1
1
U2_BOOT1
U2_UGATE1
GPU_EN
GPU_VID
GPU_PSI
4
6
5
VID
REFADJ
U2_PHASE1
2
PL602
0.22UH_PCME064T-R22MS0R985_28A_20%
2
U2_PHASE2_C 1
7
6
5
3
U2_PHASE2
1
4
8
+5V_RUN
DGPU_PWROK
<10,12,35,44>
2
106.38C
LAGTE2
PHASE2
24
+GPU_CORE
U2_LGATE2
@
PR623
10K_0603_5%
1
2
2
2
PC626
1U_0402_6.3V6K
+GPU_CORE
@EMC@ PR622
4.7_1206_5%
PR620=13K
PL601
0.22UH_PCME064T-R22MS0R985_28A_20%
2
U2_PHASE1_C 1
7
6
5
3
1
103.1C
2
4
@EMC@ PC625
680P_0603_50V7K
T_max
100C
+VGA_CORE
EDP-Continuous 32 A
EDP-Peak 60 A
OCP 72 A
CSD87351Q5D_SON8-7
Reserve Location
1
T_typical
96.73C
SS
PC622
1U_0402_6.3V6K
2
1
T_min
PR620=18.7K
PQ600
U2_UGATE1
GPU_SNUB2
4
PC605
0.22U_0603_25V7K
U2_UGATE2
PH600
470K_0402_5%_TSM0B474J4702RE
2
1
3. Thermal monitoring:
(VGPU_VREF-VTSNS)/PR620=VTSNS/Rth
VSNS
PVCC
U2_UGATE2
GPU_VREF
PR617
100_0402_1%
1. VSNS Soft-Start time (Internal) is 0.7ms (PC616 un-pop)
Tss=(Css*Vrefin)/Iss+2.3ms
=0.01U*0.9V/5uA+2.3ms=4.1ms (PC616 pop)
RGND
25
@ PC616
0.01U_0402_25V7K
1
2
2
12
LGATE1
GND/PWM3
15
GPU_FB
2. Switching frequency setting:
Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p)=304.89Khz
1
4
PHASE1
TON
GPU_DSBL/ISEN1
GPU_COMP
0_0402_5%
1
+GPU_CORE
10
11
@ PC615
47P_0402_50V8J
2
<36,38>
2
VREF
GND
1
9
TALERT/ISEN2
2
PR616
8
TSNS/ISEN3
GPU_FBRTN
PR614
100_0402_1%
GPU_VDD_SENSE
GPU_TON
2
3
<41>
GPU_VREF
@PC613
@PC613
0.01UF_0402_25V7K
14
1
2
REFIN
13
0_0402_5%
1
2
7
GPU_TSNS/ISEN3
1
1
GPU_VSS_SENSE
3V3_MAIN_EN
GPU_SNUB1
<41>
GPU_REFIN
+PWR_SRC
2
2
PR606
4.7_0603_5%
1
2
U2_BOOT1
U2_PHASE1
PU600
PR611
1
Pull high on HW side
PR612
499K_0402_1%
1
2
+GPU_PWR_SRC
NULL
<40>
PR625
1K_0402_5%
1
2
GPU_REFADJ
2
1
PR604
20K_0402_1%
1
2
PC607
2700P_0402_50V7K
1
2
PR610
0_0402_5%
2
@ PC606
0.01U_0402_25V7K
1
PR607
18K_0402_1%
2
1
NVVDD_PSI
0_0402_5%
PR603
2K_0402_5%
1
2
NULL
+GPU_PWR_SRC
@EMC@ PC601
0.1U_0402_25V6
2
1
2
2
1
9.39K
Recommendation
PSI Pull high on HW side
PR605
@ PC608
0.1U_0402_25V6
2
1
2
2
Config B
1
1
0_0402_5%
PR600
20K_0402_1%
N14P-GT
Config B
+3.3V_RUN
PR602
PC600
1U_0402_6.3V6K
N14P-GS
PC611
330U_X_2VM_R6M
Rt=Rrefadj // (Rboot+Rref2)
PWM-VID Spec
C
Current Limit threshold setting
Rocset= (Ivalley * Rds(on) + 40 mV) / 10uA
Vboot=Vvref*Rref2/(Rref1+Rref2+Rboot)
PC609
330U_X_2VM_R6M
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
D
Sheet
53
of
56
A
B
C
D
EMC@ PL700
1UH_PCMB053T-1R0MS_7A_20%
2
1
PR701
0.01_1206_1%
+SDC_IN
PC700
0.1U_0603_25V7K
2
PAD-OPEN 4x4m
D
2
G
PQ701
NTR4502PT1G_SOT23-3
3
D
2
G
1
PQ703A
NTGD4161PT1G_TSOP6~D
S
S
5
6
D
GNDA_CHG
<9,36,52,54,55>
ACP
13
CMPOUT 14
16
@ PR728
0_0402_5%
1
2
/PROCHOT
GND
CMPIN
NC
+PWR_SRC
PC708
22U_0805_25V6M
2
1
PC707
22U_0805_25V6M
2
1
PC705
10U_0805_25V6K
2
1
PC704
10U_0805_25V6K
2
1
3
PR707
100K_0402_1%
2
1
23
2
CHG_LGATE
22
+PWR_SRC
/BATPRES
CELL
SRN
/BATDRV
PWPD
BAT
BQ24715URUYR_WQFN28_4x4
21
7
6
5
20
PJP701
4
19
PR722
4.02K_0402_1%
1
2
18
17
1
PQ704
2
CSD87351Q5D_SON8-7
PR723
10_0603_1%+BATT_SUM
2
PC729
1U_0603_25V6K GNDA_CHG
1
2
CHG_SW1
PAD-OPEN1x1m
2
+VCHGR
PR721
0.01_1206_1%
2.2UH_12A_20%
1
1
PL701
3
CMPOUT
GNDA_CHG
PR729
121K_0402_1%
@
ISYS
SRP
15
/BATPRES
<55>
PC706
22U_0805_25V6M
2
1
1
PR706
100K_0402_1%
1
2
2
CSSN_1
1
ACN
LODRV
CHG_UGATE
CHG_SW
2
CMPIN
29
PBAT_PRES#
PHASE
26
27
IADP
2
<36,47,55>
HIDRV
ACOK
2
H_PROCHOT#
PR725
100K_0402_1%
SDA
1
4
1
3
2
@EMC@ PR726
4.7_1206_5%
1 BQ24770_REGN
GNDA_CHG
10
PR712
2.2_0603_5%
1
2
25
1 CHG_SNUB 1
I_SYS
0_0402_5%
2
BTST
PC726
0.1U_0402_25V6
1
2
PC727
0.1U_0402_25V6
1
2
@
PC728
0.1U_0402_25V6
1
2
GNDA_CHG
2
<36>
PR717
1
@
24
@EMC@ PC721
1000P_0603_50V7K
V_SYS
9
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
REGN
ACDET
IDCHG
@
1U_0603_10V6K
CMSRC
SCL
<55>
8
<36>
PR716
1
PR718
1
PR720
1
PC720
100P_0402_50V8J
1
2
2
VCP
8
PC719
100P_0402_50V8J
1
2
<36>
PR715
121K_0402_1%
PC718
100P_0402_50V8J
1
2
2
ACAV_IN
1
<36,54,55>
DK_CSS_GC
PC710
1
2
PC725
10U_0805_25V6K
2
1
7
2
GNDA_CHG
BQ24770_REGN
Near PL701
PC724
10U_0805_25V6K
2
1
CHARGER_SMBCLK
PR709
0_0402_5%
2
1
PC723
10U_0805_25V6K
2
1
CHARGER_SMBDAT
<36>
5
<34>
@EMC@ PC722
0.1U_0603_25V7K
2
1
12
2
0_0402_5%
VCC
DOCK_DCIN_IS-
@EMC@ PC713
2200P_0402_50V7K
2
1
1
0.1U_0402_25V4Z~D
<36>
2
4
1
6
1
PR714
1
PC712
0.047U_0603_25V7K~D
2
1
3
ACDRV
28
+DCIN
4
PC709
10U_0805_25V6K
2
1
2
2
PR710
294K_0402_1%
2
GNDA_CHG
PU700
1
BQ24770_REGN
2
PC711
GNDA_CHG
PR713
100K_0402_1%
PC702
0.1U_0402_25V6
1
2
2
PC703
0.1U_0402_25V6
11
1
CHARGER_SMBCLK
CHARGER_SMBDAT
pull up 10K in HW side (R827 R828)
PR711
49.9K_0402_1%
2
1
PC701
1U_0603_25V6K
1
2
1
PR708
10_1206_5%
<34>
G
SDMK0340L-7-F_SOD323-2~D
+SDC_IN
0_0402_5%
1
D
2
+BATT_SUM
PR703
10K_0402_5%
2
1
DOCK_DCIN_IS+
PQ703B
NTGD4161PT1G_TSOP6~D
S
PD702
PR705
1
BAT54CW_SOT323-3
2
+DC_IN_SS
G
PR704
0_0402_5%
1
CSSP_1
1
3
PC717
22U_0805_25V6M
2
1
PQ702
NTR4502PT1G_SOT23-3
3
PD701
2
S
PC716
22U_0805_25V6M
2
1
2
0_0402_5%
+DOCK_PWR_BAR
3
1
1
CSS_GC
2
PC715
22U_0805_25V6M
2
1
PR702
<55>
<55>
1
1
1
DC_BLOCK_GC
2
2
PJP700
1
@
4
PR700
1
TYP
MAX
H/S Rds(on) 7.4mohm , 8.8mohm
L/S Rds(on) 2.6mohm , 3.1mohm
Choke DCR 5.8mohm , 7.0mohm
CHAGER_SRC
@
0_0402_5%
1
+PWR_SRC_AC
4
PC714
22U_0805_25V6M
2
1
PQ700
SI4835DDY-T1-GE3_SO8
8
1
7
2
6
3
5
+DC_IN_SS
GNDA_CHG
2
GNDA_CHG
GNDA_CHG
BATDRV#
3
<55>
3
1
+DC_IN
2
PR737
649K_0402_1%
CMPOUT
PC737
100P_0402_50V8J
2
PR738
3M_0402_5%
1
CMPIN
1
PR745
100K_0402_1%
2
1
1
2
2
1
ACAV_IN_NB
<36,47>
2
PR743
0_0402_5%
PC741
100P_0402_50V8J
2
1
PR740
10K_0402_1%
+3.3V_ALW
4
4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
D
Sheet
54
of
56
3
1
DMN66D0LDW-7 2N_SOT363-6~D
PQ807A
8
7
6
5
3301_DSCHRG_FET_GC
3
<35,55>
PU804
TC7SH08FU_SSOP5~D
DMN66D0LDW-7 2N_SOT363-6~D
1
4
O
A
PR812
0_0402_5%
1
2
DIS_BAT_PROCHOT#
6
PQ806A
2
5
B
2
D
PR814
330K_0402_5%
2
1
+DOCK_PWR_BAR
5
2
PC811
0.01U_0603_25V7K
<35>
PBAT_PRES# 1
P
STSTART_DCBLOCK_GC
1
2
3
1
4
PQ810
FDS6679AZ-G_SO8
1
SLICE_BAT_ON
PR821
820_0603_5%~D
1
2
2
5
5
SLICE_BAT_ON
G
0.47U_0805_25V6K
FDS6679AZ-G_SO8
+3.3V_ALW
PC805
0.1U_0402_10V7K
1
2
3
PR811
0_0402_5%
1
2
PC807
1
2
<34,35,47,55>
4
SLICE_BAT_PRES#
4
2
5
3
2 DMN66D0LDW-7 2N_SOT363-6~D
PQ807B
4
4
PR817
1
330K_0402_5%
PQ806B
8
7
6
5
1
1
2
3
PD808
PDS5100H-13_POWERDI5-3
PQ812B
DMN66D0LDW-7 2N_SOT363-6~D
4
3
PBAT_PRES#
5
3
PQ811
+PBATT
PR816
100K_0402_5%
PR810
100K_0402_5%
DMN66D0LDW-7 2N_SOT363-6~D
2
1
2
2
+3.3V_ALW2
+3.3V_ALW
/BATPRES <34,35,47>
3
1
6 2
+3.3V_ALW
PR808
PQ833B
6
1
+PWR_SRC_AC
TC7SH08FU_SSOP5~D
+3.3V_ALW
PR803
100K_0402_5%
2
1
DMN66D0LDW-7 2N_SOT363-6~D
2
PQ833A
O
A
2
4
DMN66D0LDW-7 2N_SOT363-6~D
B
2
SLICE_BAT_ON
1
4
PR804
100K_0402_5%
2
1
<36,47,54>
1
SLICE_BAT_PRES#
PU801
+3.3V_ALW2
PQ812A
DMN66D0LDW-7 2N_SOT363-6~D
PR801
100K_0402_5%
2
1
5
2
1
PR802
100K_0402_5%
PC801
0.1U_0402_10V7K
1
2
100K_0402_5%
PR815
10K_0402_5%
2 2
+NBDOCK_DC_IN_SS
1
6
BATDRV#
1
PR813
100K_0402_5%
1
2
PD811
4
<54>
3
1
PQ800
SI4835DDY-T1-GE3_SO8
1
8
2
7
3
6
5
SDMK0340L-7-F_SOD323-2~D
+VCHGR
1
PQ809
SI4835DDY-T1-GE3_SO8
1
8
2
7
3
6
5
1
+3.3V_ALW
Purpose: Trigger PROCHOT# when
active battery is removed from
system.
Allows EC to re-establish
system performance for battery
next in line.
2
D
PD800
PDS5100H-13_POWERDI5-3
3
1
2
2
1
+BATT_SUM
+PBATT_IN_SS
2
PQ801
NTR4502PT1G_SOT23-3
3
+BATT_SUM
3
PD807
SDMK0340L-7-F_SOD323-2~D
P
4
PD806
PDS5100H-13_POWERDI5-3
3
1
2
G
5
PQ826
FDMC6679AZ_MLP8-5
+3.3V_ALW2
4
5
P
1
SLICE_BAT_PRES#
1
2
1
C
<34,35,47,55>
+3.3V_ALW2
1
1
2
PR819 2
100K_0402_5%
3
5
A
D
2
DOCK_DET#
G
PQ817
DMN65D8LW-7_SOT323-3
2 ACAV_IN#
S
PR820
0_0402_5%
3
PR822
<34,35,55>
1
2
PR829
1
A
PR825
0_0402_5%
PR851
<36,54,55>
ACAV_IN
1
2
0_0402_5%
37
+3.3V_ALW2
1
2
TP
0_0402_5%
ERC3
ERC2
<54> CSS_GC
<54> DK_CSS_GC
2
1
ACAV_IN_NB
<36,54>
DOCK_AC_OFF_EC
1
2
1
1
PR837
100K_0402_5%
3
PC814
0.1U_0402_10V7K
2
1
PR850
0_0402_5%
PR836
100K_0402_5%
<35>
PR854
0_0402_5%
1
2
+DC_IN_SS
4
+PBATT
O
A
1
2
SLICE_BAT_PRES# <34,35,47,55>
DOCK_DET# <34,35,55>
PR864
100K_0402_5%
PU808
TC7SH08FU_SSOP5~D
ACAV_IN#
PR872
0_0402_5%
1M_0402_5%
<34,35,47,55>
<36,54,55>
1
ACAV_IN
+NBDOCK_DC_IN_SS
1
+3.3V_ALW
DOCK_DET#
B
2
SLICE_BAT_PRES#
@ PR863
0_0402_5%
1
2
CD3301BRHHR_QFN36_6X6~D
PR859
0_0402_5%
2
P33ALW 1
<34,35,55>
PR858
1
+3.3V_ALW2
1
1
2
+3.3V_ALW2
3
S
2
D
1
2
2
2
G
3
3
1 PR840 2
100K_0402_5%
PQ831
DMN65D8LW-7_SOT323-3
1
3
1
2
PR852
0_0402_5%
2
PQ822
NTR4502PT1G_SOT23-3
2
1
DK_AC_OFF_EN
SL_BAT_PRES#
+3.3V_ALW2
1
2
2
NTR4502PT1G_SOT23-3
PQ830
3
1
2
1
100K_0402_5%
0_0402_5%
PR848
0_0402_5%
2
3301_ACAV_IN_NB 1
DK_AC_OFF
1
5
27
26
25
24
23
22
21
20
19
PR857
2
<34,35,47,55>
EN_DOCK_PWR_BAR
2
D
S
2
G
PQ825
DMN65D8LW-7_SOT323-3
<35>
0_0402_5%
A
EN_DK_PWRBAR
PC817
0.1U_0402_25V4Z~D
2
1
A
PC816
0.047U_0603_25V7M
2
1
PC815
0.1U_0603_25V7K
2
1
10
11
12
13
14
15
16
17
18
PR855
P50ALW
PBATT_OFF
DK_AC_OFF_EN
ACAV_IN_NB
GND
DK_AC_OFF_EN
SL_BAT_PRES#
BLKNG_MOSFET_GC
NBDK_DCINSS
SLICE_BAT_PRES#
1
DC_BLOCK_GC
DC_IN
SS_GC
ERC1
ACAVDK_SRC
GND
SDC_IN
DC_BLK_GC
ACAV_IN
P33ALW2
<35,55>
2
0_0402_5%
3
CD3301_SDC_IN
<54>
1
2
3
4
5
6
7
ACAVIN 8
P33ALW2 9
SLICE_BAT_ON
PR849
P
ERC1
2
G
PR847
0_0402_5%
1
2
2
PR845
1
PD821
SDMK0340L-7-F_SOD323-2~D
3
+SDC_IN
PR844
<34>
PQ821B
DMN66D0LDW-7 2N_SOT363-6~D
4
3
1
100K_0402_5%
10K_0402_5%
1
CD_PBATT_OFF
PD816
SDMK0340L-7-F_SOD323-2~D
DMN65D8LW-7_SOT323-3
2
ACAV_DOCK_SRC#
+5V_ALW
BAT54CW_SOT323-3
PR834
2
G
S
B
PQ828
1
PR842
0_0402_5%
1
2ACAVDK_SRC
100K_0402_5%
<34>
PU800
2
DOCK_DET#
DOCK_AC_OFF
3
PR843
0_0402_5%
1
2
<34,35,47>
D
+NBDOCK_DC_IN_SS
SLICE_BAT_PRES#
2
1
PR861
0_0402_5%
PQ821A
DMN66D0LDW-7 2N_SOT363-6~D
PR839
1
6 2
1
+PBATT
P50ALW
NC
CHARGERVR_DCIN
DC_IN_SS
DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
PBatt+
PR846
<47>
SOFT_START_GC
1
2
<34,35,55>
PD815
CSS_GC
DK_CSS_GC
ERC3
ERC2
GND
PWR_SRC
SS_DCBLK_GC
EN_DK_PWRBAR
P33ALW
+3.3V_ALW2
PR853
0_0402_5%
<34,35,47,55>
2
PR838
0_0402_5%
1
2
36
35
34
33
32
31
30
29
28
2
PC813
0.1U_0603_50V4Z
3
PD819
SDMK0340L-7-F_SOD323-2~D
1
2
DOCK_SMB_ALERT#
5
1
47_0805_5%~D
+DOCK_PWR_BAR
PR841
0_0402_5%
1
2 3301_DSCHRG_FET_GC
1
CD3301_DCIN
1
2
2
2
1 PR827 2
100K_0402_5%
2
2
DSCHRG_MOSFET_GC
PR835
1
DC_IN_SS
DK_PWRBAR
+DC_IN_SS
+DC_IN
PR832
0_0402_5%
1
2
PR831
0_0402_5%
1
2
B
+3.3V_ALW2
5
100K_0402_5%
1
PQ813B
DMN66D0LDW-7 2N_SOT363-6~D
4
3
3
100K_0402_5%
2
S
2
G
1
PQ814
NTR4502PT1G_SOT23-3
2
1
1
2
10K_0402_5%
3
AC_DIS
D PQ832
DMN65D8LW-7_SOT323-3
PR826
G
<36,47>
PR828
6 2
D
SLICE_BAT_PRES#
2
1
1
2
<35,55>
1
G
O
SLICE_BAT_ON
S
<34,35,47,55>
PQ813A
DMN66D0LDW-7 2N_SOT363-6~D
1
PR823
100K_0402_5%
1
B
3
PR830
100K_0402_5%
PD820
SDMK0340L-7-F_SOD323-2~D
1
2
Purpose: Turn on the PQ817
for Slice battery discharge
without AC exist
3
2
2
2
4
PQ818
PU807
TC7SH08FU_SSOP5~D
PD814
SDMK0340L-7-F_SOD323-2~D
1
2
SDMK0340L-7-F_SOD323-2~D
1
PC812
0.1U_0402_10V7K
2
1
DMN65D8LW-7_SOT323-3
PD813
1
0_0402_5%
+3.3V_ALW2
+3.3V_ALW2
Vth=0.5‐1.5V
5
3
2
G
S
P
2
1
PR895
3
1
+3.3V_ALW
1
PQ829
DMG2301U-7 1P SOT23-3
D
3
8
7
6
5
PQ816
AO3418_SOT23-3
2
FDS6679AZ-G_SO8
B
O
A
3
1
10K_0402_5%
2
PD810
SDMK0340L-7-F_SOD323-2~D
B
O
0.1U_0402_10V7K
P
1
2
3
4
4
PU806
TC7SH08FU_SSOP5~D
1
PQ815
PU805
TC7SH08FU_SSOP5~D
PC810
2
1
1
2
1500P_0402_50V7K
+3.3V_ALW2
G
2
PR818
1
@
PC809
100K_0402_5%
C
Purpose: Turn on the PQ817
for primary or module bay
battery to provide power to
dock side without AC exist.
PC808
0.1U_0402_10V7K
2
1
G
1
2
3
4
@
STSTART_DCBLOCK_GC
PR860
0_0402_5%
1
2
3301_PWRSRC
PR874
1
2
1M_0402_5%
+PWR_SRC_AC
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
1
Sheet
55
of
56
5
4
3
2
1
+VCC_CORE
D
D
2
2
2
1
2
1
PC922
22U_0805_6.3V6M
2
1
PC923
22U_0805_6.3V6M
2
1
PC924
22U_0805_6.3V6M
2
PC953
4.7U_0603_6.3V6K
PC952
4.7U_0603_6.3V6K
2
1
PC912
4.7U_0603_6.3V6K
2
1
PC911
4.7U_0603_6.3V6K
2
1
PC910
4.7U_0603_6.3V6K
2
1
PC917
22U_0805_6.3V6M
PC909
4.7U_0603_6.3V6K
2
1
1
PC916
22U_0805_6.3V6M
PC908
4.7U_0603_6.3V6K
2
1
2
1
PC915
22U_0805_6.3V6M
PC921
1U_0402_6.3V
2
1
PC914
22U_0805_6.3V6M
1
2
1
PC913
22U_0805_6.3V6M
PC907
4.7U_0603_6.3V6K
2
1
2
1
PC920
1U_0402_6.3V
2
1
2
+GPU_CORE
PC904
22U_0805_6.3V6M
PC906
4.7U_0603_6.3V6K
2
1
2
1
PC903
22U_0805_6.3V6M
PC919
1U_0402_6.3V
2
1
2
1
PC902
22U_0805_6.3V6M
1
2
1
PC901
22U_0805_6.3V6M
PC905
4.7U_0603_6.3V6K
2
1
2
1
PC900
22U_0805_6.3V6M
PC918
1U_0402_6.3V
2
1
1
nVidia GB4-64 package
Under GPU
4.7uF 0603 * 10
1uF 0402 * 4
1
PC925
22U_0805_6.3V6M
2
PC926
22U_0805_6.3V6M
C
C
1
2
1
PC927
22U_0805_6.3V6M
2
1
PC928
22U_0805_6.3V6M
2
1
PC929
22U_0805_6.3V6M
1
@
2
PC930
22U_0805_6.3V6M
2
@ PC931
22U_0805_6.3V6M
nVidia GB4-64 package
Near GPU
47uF 0805 *1
22uF 0805 *1
4.7uF 0805 *5
1
@
2
PC946
22U_0805_6.3V6M
2
PC942
4.7U_0805_6.3V6K
PC937
4.7U_0805_6.3V6K
2
1
PC936
4.7U_0805_6.3V6K
2
1
PC935
4.7U_0805_6.3V6K
2
1
1
@
PC947
22U_0805_6.3V6M
2
@ PC948
22U_0805_6.3V6M
1
1
PC934
4.7U_0805_6.3V6K
2
1
@ PC943
22U_0805_6.3V6M
@ PC951
4.7U_0805_6.3V6K
2
PC933
22U_0805_6.3V6M
2
1
2
PC941
22U_0805_6.3V6M
@ PC950
4.7U_0805_6.3V6K
2
1
1
@
2
2
PC940
22U_0805_6.3V6M
1
1
@
PC932
47U_0805_6.3V6M
2
1
1
@ PC949
4.7U_0805_6.3V6K
2
1
+GPU_CORE
2
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
SCHEMATICS,MB AA913
Size
Document Number
Date:
Thursday, November 14, 2013
Rev
A
4019RA
Sheet
1
56
of
56
www.s-manuals.com
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Create Date : 2014:05:19 20:26:34+02:00 Creator Tool : PDFsharp 1.2.1269-g (www.pdfsharp.com) Modify Date : 2015:04:13 00:55:09+03:00 Metadata Date : 2015:04:13 00:55:09+03:00 Producer : PDFsharp 1.2.1269-g (www.pdfsharp.com) Format : application/pdf Title : Compal LA-A913P - Schematics. www.s-manuals.com. Creator : Subject : Compal LA-A913P - Schematics. www.s-manuals.com. Document ID : uuid:faf8291d-f49f-4c5c-8703-732ff8e744d6 Instance ID : uuid:6dda424b-a513-4b09-9aa1-539ab0014774 Has XFA : No Page Count : 57 Keywords : Compal, LA-A913P, -, Schematics., www.s-manuals.com. Warning : [Minor] Ignored duplicate Info dictionaryEXIF Metadata provided by EXIF.tools