Compal LA B091P Schematics. Www.s Manuals.com. R1.0 Schematics
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A B C D E 1 1 Compal Confidential 2 2 ZIWB2/ZIWB3/ZIWE1 DIS M/B Schematics Document Intel Boardwell U Processor with DDR3L AMD Topaz XT / Jet LE 2014-02-10 3 3 LA-B091P REV： ：1.0 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: A B C D Cover Page Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 E Sheet 1 of 55 A B C D E For DIS 1 1 Jet LE(15W) Topaz XT(25W) PCIe X4 (Gen2) Memory Bus A-ch DDR3L-SO-DIMM X1 VRAM(DDR3L) 1GB/2GB/4GB DDR3L 1600MHz (1.35V) Memory Bus eDP X1 (2 Lanes) eDP Panel CRT Translator CRT Conn. DDI X1 (2 Lanes) ITE IT6513 2 DDI X1 (4 Lanes) HDMI Conn. Intel Broadwell U 15W Left USB3.0 x2 USB3.0 x2 USB30 Port 0,1 USB2.0 x7 Touch Screen PCIe Port 0 3 Finger Printer 2 USB20 Port 4 SATA Port 1 Realtek RTS5229-GR Audio Codec Realtek ALC233 AZALIA NGFF Conn. WLAN / BT Right USB2.0 x1 USB20 Port 1 ODD Conn. SATA X1 PCIe X1 (1 Lanes) Card Reader USB20 Port 3 SATA Port 0 Realtek RTL8106E/RTL8111G 10/100/GIGA PCIe Port 2 Int. Camera HDD Conn. SATA X1 RJ45 Conn. Right USB2.0 x1 USB20 Port 0 For E14 USB20 Port 2 1168pin BGA PCIe X1 (1 Lanes) LAN B-ch DDR3L-SO-DIMM X1 DDR3L 1600MHz (1.35V) PCIe X1 (1 Lanes) USB2.0 X1 (1 Lanes) Int. MIC Conn. Int. Speaker Conn. 3 Audio Combo Jacks HP & MIC PCIe Port 1 LPC BUS Sub-borad 15" 14" DC-in/B SPI ROM 8MB Docking/B For B15 Power/B Battery/B IO/B ODD/B For E14 4 EC Nuvoton NPCE288N Thermal Sensor Touch Pad Int. KBD APS For E14 LIS34ALTR 4 USB Charge Compal Secret Data Security Classification Issued Date 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title MB Block Diagram Size C Date: A B C D Compal Electronics, Inc. Document Number Rev 1.0 Wednesday, February 12, 2014 E Sheet 2 of 55 1 2 3 Voltage Rails 4 USB Port Table USB 2.0 Port +5VS +3VS power plane A +1.5VS +V1.05S_VCCP +1.5V +5VALW +VCC_CORE +B UHCI1 EHCI1 UHCI2 +VGA_CORE +VCC_GFXCORE_AXG +3VALW UHCI3 +1.8VS +0.75VS State 0 1 2 3 4 5 6 7 8 9 10 11 12 13 UHCI0 UHCI4 +1.05VS EHCI2 UHCI5 UHCI6 S0 O O O O S3 O O O X S5 S4/AC O O X X S5 S4/ Battery only O X X X S5 S4/AC & Battery don't exist X X X X BOM Structure Table 3 External USB Port USB Port (Left Side) USB3.0 USB Port (Left Side) USB3.0 Touch Screen Camera USB Port (Right Side USB-BD) Mini Card(WLAN) Card Reader B EC SM Bus1 address EC SM Bus2 address Device Address Device Address Smart Battery 0001 011x Thermal Sensor 0100 1100 PCH SM Bus address C Device Address DDR_JDIMM1 1010 000x A0h Device DDR_JDIMM2 1010 010x A4h SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 PCH_SMBCLK KB9012 +3VALW KB9012 +3VS PCH PCH_SMBDATA +3VALW PCH_SML0CLK VGA X SIGNAL STATE BATT KB9012 SODIMM WLAN V X X X V X X X X X X X +3VGS 41h +3VALW V +3VS Thermal Sensor X V X V +3VS +3VALW V X X +3VS X X X X X X X X V +3VS X X V +3VS X SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Full ON DR@ JET@ TOPAZ@ PX@ UMA@ COMS@ Issued Date Compal Secret Data 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 2 B Only in DIS Schematic C No USE D Security Classification 1 A Only in DIS Schematic APS (G-sensor) GS@ Touch Screen TS@ HDMI HDMI@ USB 2.0 USB2@ USB 3.0 USB3@ Full HD Panel (2 Lane) FHD@ ENE EC 9012 9012@ HDMI Royalty 45@ Connector ME@ VRAM indentify X76@ Un-pop component for EMI @EMI@ Un-pop component for ESD @ESD@ DA600140000 PCB_14_DIS@ DA600141000 PCB_14_UMA@ DA600140100 PCB_15_DIS@ DA600141100 PCB_15_UMA@ PCH V PCH PCH_SML0DATA +3VALW SML1CLK PCH SML1DATA +3VALW +3VGS D Address SMBUS Control Table SOURCE Item BOM Structure ZIWB2 (14") B14@ B15@ ZIWB3 (15") ZIWE1 (14") E14@ CPU_SA00006SM20 i5_4200U@ QFSY@ CPU_SA00007AM00 CPU_SA00006SU30 i3_4100U@ CPU_SA000072Q10 i3_4005U@ CPU_SA00006SX20 i3_4010U@ LAN 10/100 Transformer 100@ GIGA@ LAN GIGA Transformer LAN Switch mode SWITCH@ LAN RTL8106E-CG 8106ELDO@ LAN RTL8111GS-CG 8111GLDO@ 8106ESW@ LAN RTL8106EUS-CG LAN RTL8111GUS-CG 8111GSW@ Audio_233 233@ 233VB@ Audio_233VB For B15 Docking@ For B14, E14 NoDocking@ For Deep Sleep DS3@ For No Deep Sleep NoDS3@ WLAN Support ISCT ISCT@ WLAN No Support ISCT NoISCT@ For Intel ZERO ODD ZODD@ For No Intel ZERO ODD NoZODD@ For Green CLK GCLK@ For No Green CLK NoGCLK@ For No Green CLK NoGCLKDIS@ Green CLK IC For DIS GCLKDIS@ Green CLK IC For UMA GCLKUMA@ GPU support Dual Rank GPU Jet LE GPU Topaz XT For DIS For UMA Camera AMD-GPU SM Bus address Internal thermal sensor 0100 0001 5 3 4 Compal Electronics, Inc. Notes List Document Number LA-B091P Sheet Wednesday, February 12, 2014 3 55 of 5 Rev 1.0 5 4 3 2 1 Power-Up/Down Sequence "Mars" has the following requirements with regards to power-supply sequencing to avoid damaging the ASIC: ‧ All the ASIC supplies must reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. The maximum slew rate on all rails is 50 mV/µs. ‧ The external pull ups on the DDC/AUX signals (if applicable) should ramp up before or after both VDDC and VDD_CT have ramped up. ‧ VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC should reach 90% before VDD_CT starts to ramp up (or vice versa). ‧ For power down, reversing the ramp-up sequence is recommended. Topaz XT_VRAM_STRAP X76@ X76@ Vendor UV5, UV6, UV7, UV8 D C ID PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1 ] R_pu R_pd RV21 RV24 ZZZ01 2GBytes TH2G@ Hynix 4096Mbits SA00006E800 256Mx16 H5TC4G63AFR-11C 0 0 0 0 NC ZZZ02 1GBytes TS1G@ Samsung 2048Mbits SA000068U40 128Mx16 K4W2G1646Q-BC1A 1 0 0 1 8.45K 2K ZZZ03 1GBytes TM1G@ Micron 2048Mbits SA000067500 128Mx16 MT41J128M16JT-093G:K 2 0 1 0 4.53K 2K PCIE_VDDC(0.95VGSV) ZZZ04 1GBytes TH1G@ Hynix 2048Mbits SA00006H400 128Mx16 H5TC2G63FFR-11C 3 0 1 1 6.98K 4.99K VDDR1(1.5VGS) ZZZ05 2GBytes TM2G@ Micron 4096Mbits SA000077K00 256Mx16 MT41J256M16HA-093G:E 4 1 0 0 4.53K 4.99K VDDC/VDDCI(1.12V) ZZZ06 2GBytes TS2G@ Samsung 4096Mbits SA000076P00 256Mx16 K4W4G1646D-BC1A 5 1 0 1 3.24K 5.62K VDD_CT(1.8V) ZZZ07 1GBytes TM1G2@ Micron 2048Mbits SA00005XB00 128Mx16 MT41K128M16JT-107G:K 6 1 1 0 3.4K 10K PERSTb ZZZ08 2GBytes TM2G2@ Micron 4096Mbits SA000065D00 256Mx16 MT41K256M16HA-107G:E 7 1 1 1 4.75K NC REFCLK ZZZ01 ZZZ02 4.75K D VDDR3(3.3VGS) C ZZZ03 ZZZ04 Straps Reset TH2G@ TS1G@ TM1G@ TH1G@ 2G HYNIX 1G SAMSUNG 1G MICRON 1G HYNIX X7653638L01 X7653938L03 X7653938L02 Straps Valid X7653938L01 Global ASIC Reset T4+16clock Jet LE_VRAM_STRAP X76@ X76@ Vendor UV5, UV6, UV7, UV8 B ID PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1 ] R_pu R_pd RV21 RV24 ZZZ09 1GBytes JH1G@ Hynix 2048Mbits SA00006H400 128Mx16 H5TC2G63FFR-11C 0 0 0 0 NC ZZZ10 1GBytes JM1G@ Micron 2048Mbits SA000067500 128Mx16 MT41J128M16JT-093G:K 1 0 0 1 8.45K 2K ZZZ11 1GBytes JS1G@ Samsung 2048Mbits SA000068U40 128Mx16 K4W2G1646Q-BC1A 2 0 1 0 4.53K 2K ZZZ12 2GBytes JH2G@ Hynix 4096Mbits SA00006E800 256Mx16 H5TC4G63AFR-11C 3 0 1 1 6.98K 4.99K ZZZ13 2GBytes JS2G@ Samsung 4096Mbits SA000076P00 256Mx16 K4W4G1646D-BC1A 4 1 0 0 4.53K 4.99K ZZZ14 2GBytes JM2G@ Micron 4096Mbits SA000077K00 256Mx16 MT41J256M16HA-093G:E 5 1 0 1 3.24K 5.62K ZZZ08 2GBytes JM2G2@ Micron 4096Mbits SA000065D00 256Mx16 MT41K256M16HA-107G:E 6 1 1 0 3.4K 10K ZZZ16 1GBytes JM1G2@ Micron 2048Mbits SA00005XB00 128Mx16 MT41K128M16JT-107G:K 7 1 1 1 4.75K 4.75K B NC A A ZZZ09 ZZZ10 ZZZ11 ZZZ12 JH1G@ JM1G@ JS1G@ JH2G@ 1G HYNIX 1G MICRON 1G SAMSUNG 2G HYNIX X7653638L07 X7653638L08 X7653638L09 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification X7653638L04 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title VGA Notes List Size C Date: 5 4 3 2 Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 1 Sheet 4 of 55 5 4 3 2 1 DAZ DA600140000 PCB 14I LA-B091P REV0 M/B DIS 3 PCB_14_DIS@ DAZ DA600140100 PCB 14K LA-B091P REV0 M/B DIS 6 PCB_15_DIS@ DAZ DA600141000 PCB 14I LA-B092P REV0 M/B UMA 3 PCB_14_UMA@ D DAZ DA600141100 PCB 14K LA-B092P REV0 M/B UMA 6 PCB_15_UMA@ D BDW_ULT_DDR3L(Interleaved) UC1A <29> <29> <29> <29> CRT <37> <37> <37> <37> <37> <37> <37> <37> HDMI C54 C55 B58 C58 B55 A55 A57 B57 CPU_DP1_N0 CPU_DP1_P0 CPU_DP1_N1 CPU_DP1_P1 CPU_DP2_N0 CPU_DP2_P0 CPU_DP2_N1 CPU_DP2_P1 CPU_DP2_N2 CPU_DP2_P2 CPU_DP2_N3 CPU_DP2_P3 CPU_DP2_N0 CPU_DP2_P0 CPU_DP2_N1 CPU_DP2_P1 CPU_DP2_N2 CPU_DP2_P2 CPU_DP2_N3 CPU_DP2_P3 C51 C50 C53 B54 C49 B50 A53 B53 DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3 C45 B46 A47 B47 EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 DDI DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3 <27> <27> <27> <27> C47 C46 A49 B49 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 EDP EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 eDP A45 B45 EDP_AUXN EDP_AUXP D20 A43 EDP_RCOMP EDP_DISP_UTIL EDP_AUXN <27> EDP_AUXP <27> EDP_COMP R1 1 CPU_INV_PWM 2 24.9_0402_1% +VCCIOA_OUT T1 EDP_COMP (R1): Trace width=20 mils,Spacing=25mil,Max length=100mils 1 OF 19 BDW-ULT-DDR3L-IL_BGA1168 @ C C BDW_ULT_DDR3L(Interleaved) UC1B T2 T3 +1.05VS R2 <35> H_PECI 1 D61 K61 N62 PROC_DETECT CATERR PECI MISC 2 62_0402_5% R3 <35> H_PROCHOT# R4 1 2 56_0402_5% 1 2 10K_0402_5% H_PROCHOT#_R H_CPUPWRGD K63 C61 PROCHOT PROCPWRGD JTAG THERMAL R6 1 2 470_0402_5% R5 R7 R8 1 1 1 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 DIMM_DRAMRST# DDR_PG_CTRL AU60 AV60 AU61 AV15 AV61 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1 XDP_PRDY# XDP_PREQ# XDP_TCK XDP_TMS XDP_TRST# XDP_TDI XDP_TDO T31 T32 T4 T5 T6 T7 T8 BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7 DDR3L J60 H60 H61 H62 K59 H63 K60 J61 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7 C238 100P_0402_50V8J B 2 1 <16> DDR_PG_CTRL 2 200_0402_1% 2 120_0402_1% 2 100_0402_1% J62 K62 E60 E61 E59 F63 F62 PWR +1.35V <16,17> DIMM_DRAMRST# PRDY PREQ PROC_TCK PROC_TMS PROC_TRST PROC_TDI PROC_TDO DDR3 Compensation Signals (R9, R10, R11): 20 mils to comp signals 25 mils to non-comp signals 500 mil for Max trace length 2 OF 19 BDW-ULT-DDR3L-IL_BGA1168 ESD ESD B 2 1 H_CPUPWRGD UC1 SA00007G020 Intel 2957U 1.4G 2M D0 2cBGA CPU 2957U@ C237 100P_0402_50V8J UC1 SA00007G220 S IC CL8064701569500 QFAN D0 1.7G BGA 3558U@ UC1 SA00006SL70 S IC CL8064701477202 QEVD C0 1.8G BGA i7_4500U@ UC1 SA00006SM80 S IC CL8064701477702 SR170 C0 1.6G C38! i5_4200U@ UC1 SA00007AM00 S IC CL8064701614813 QFSY C0 1.6G BGA QFSY@ UC1 SA00006SU50 S IC CL8064701476302 SR16P C0 1.8G C38! i3_4100U@ UC1 SA000072Q70 S IC CL8064701478404 QEAR D0 1.7G C38 i3_4005U@ A A UC1 SA00006SX80 S IC CL8064701478202 SR16Q C0 1.7G C38! i3_4010U@ Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 5 4 3 2 HSW MCP(1/11) DDI,MSIC,XDP Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 1 Sheet 5 of 55 5 4 3 2 1 Interleaved Memory D D UC1C <16> DDR_A_D[0..15] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 <16> DDR_A_D[16..31] C <16> DDR_A_D[32..47] <16> DDR_A_D[48..63] B AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AY31 AW31 AY29 AW29 AV31 AU31 AV29 AU29 AY27 AW27 AY25 AW25 AV27 AU27 AV25 AU25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21 AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 BDW_ULT_DDR3L(Interleaved) BDW_ULT_DDR3L(Interleaved) UC1D SA_CLK#0 SA_CLK0 SA_CLK#1 SA_CLK1 SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3 SA_CS#0 SA_CS#1 SA_ODT0 SA_RAS SA_WE SA_CAS SA_BA0 SA_BA1 SA_BA2 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15 DDR CHANNEL A SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7 SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7 SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1 AU37 AV37 AW36 AY36 M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1 AU43 AW43 AY42 AY43 DDR_CKE0_DIMMA DDR_CKE1_DIMMA AP33 AR32 DDR_CS0_DIMMA# DDR_CS1_DIMMA# M_CLK_DDR#0 <16> M_CLK_DDR0 <16> M_CLK_DDR#1 <16> M_CLK_DDR1 <16> DDR_CKE0_DIMMA DDR_CKE1_DIMMA <17> DDR_B_D[0..15] <16> <16> T13 T9 AP32 DDR_CS0_DIMMA# DDR_CS1_DIMMA# <16> <16> T12 AY34 AW34 AU34 DDR_A_RAS# DDR_A_WE# DDR_A_CAS# DDR_A_RAS# <16> DDR_A_WE# <16> DDR_A_CAS# <16> AU35 AV35 AY41 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_BS0 <16> DDR_A_BS1 <16> DDR_A_BS2 <16> DDR_A_MA[0..15] AJ61 AN62 AV57 AV53 AW30 AV26 AW22 AV18 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 AJ62 AN61 AW57 AW53 AV30 AW26 AV22 AW18 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AP49 AR51 AP51 +SM_VREF_CA +SM_VREF_DQ0 +SM_VREF_DQ1 <17> DDR_B_D[16..31] <16> <17> DDR_B_D[32..47] DDR_A_DQS#[0..1] <16> DDR_A_DQS#[2..3] <16> DDR_A_DQS#[4..5] <16> DDR_A_DQS#[6..7] <16> DDR_A_DQS[0..1] <16> DDR_A_DQS[2..3] <16> DDR_A_DQS[4..5] <16> DDR_A_DQS[6..7] <16> <17> DDR_B_D[48..63] +SM_VREF_CA <16> +SM_VREF_DQ0 <16> +SM_VREF_DQ1 <17> Trace width >= 10mils DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51 AM29 AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25 AL25 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18 SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 SB_CK#0 SB_CK0 SB_CK#1 SB_CK1 SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3 SB_CS#0 SB_CS#1 SB_ODT0 SB_RAS SB_WE SB_CAS SB_BA0 SB_BA1 SB_BA2 DDR CHANNEL B SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7 SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7 3 OF 19 AM38 AN38 AK38 AL38 M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3 AY49 AU50 AW49 AV50 DDR_CKE2_DIMMB DDR_CKE3_DIMMB AM32 AK32 DDR_CS2_DIMMB# DDR_CS3_DIMMB# M_CLK_DDR#2 <17> M_CLK_DDR2 <17> M_CLK_DDR#3 <17> M_CLK_DDR3 <17> DDR_CKE2_DIMMB DDR_CKE3_DIMMB <17> <17> DDR_CS2_DIMMB# DDR_CS3_DIMMB# <17> <17> T10 T11 AL32 T14 AM35 AK35 AM33 DDR_B_RAS# DDR_B_WE# DDR_B_CAS# DDR_B_RAS# <17> DDR_B_WE# <17> DDR_B_CAS# <17> AL35 AM36 AU49 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_BS0 <17> DDR_B_BS1 <17> DDR_B_BS2 <17> DDR_B_MA[0..15] AM58 AM55 AL43 AL48 AN28 AN25 AN21 AN18 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 AN58 AN55 AL42 AL49 AM28 AM25 AM21 AM18 <17> DDR_B_DQS#[0..1] <17> DDR_B_DQS#[2..3] <17> DDR_B_DQS#[4..5] <17> DDR_B_DQS#[6..7] DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 C <17> DDR_B_DQS[0..1] <17> DDR_B_DQS[2..3] <17> DDR_B_DQS[4..5] <17> DDR_B_DQS[6..7] <17> B 4 OF 19 BDW-ULT-DDR3L-IL_BGA1168 BDW-ULT-DDR3L-IL_BGA1168 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 5 4 3 2 HSW MCP(2/11) DDRIII Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 1 Sheet 6 of 55 5 4 3 2 1 D D GCLK RG3 <41> CPU_RTCX1_GCLK 1 GCLK@ 2 0_0402_5% PCH_RTCX1 PCH_RTCX1 1NOGCLK@ 2 10M_0402_5% PCH_RTCX2 2 R9 BDW_ULT_DDR3L(Interleaved) UC1E R10 0_0402_5% 1 Y1 1 2 32.768KHZ 12.5PF 9H03200031 NOGCLK@ SJ10000HW00 1 1 C1 12P_0402_50V_NPO NOGCLK@ PCH_RTCX1 PCH_RTCX2 SM_INTRUDER# PCH_INTVRMEN PCH_SRTCRST# PCH_RTCRST# 2 2 AW5 AY5 AU6 AV7 AV6 AU7 C2 12P_0402_50V_NPO NOGCLK@ RTCX1 RTCX2 INTRUDER INTVRMEN SRTCRST RTCRST SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3 RTC SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2 HDA for AUDIO RP1 @EMI@ C227 22P_0402_50V8J R12 1 1 C3 2 1 CLRP1 R14 2 20K_0402_5% PCH_SRTCRST# 2 1 <35> ME_EN <39> HDA_SDIN0 1U_0402_6.3V6K SHORT PADS 2 20K_0402_5% C4 1 2 1U_0402_6.3V6K CLRP2 1 2 SHORT PADS Clear ME Clear CMOS 1 2 1M_0402_5% SM_INTRUDER# R16 1 2 330K_0402_5% PCH_INTVRMEN R17 1 HDA_SDOUT 1 AW8 AV11 AU8 AY10 AU12 AU11 AW10 AV10 AY8 HDA_BCLK/I2S0_SCLK HDA_SYNC/I2S0_SFRM HDA_RST/I2S_MCLK AUDIO HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_SDO/I2S0_TXD HDA_DOCK_EN/I2S1_TXD HDA_DOCK_RST/I2S1_SFRM I2S1_SCLK SATA AU62 AE62 AD61 AE61 AD62 AL11 AC4 AE63 AV2 SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1 SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0 SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37 2 0_0402_5% HDA_SDIN0 PCH_JTAG_TRST# PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_RTCRST# R15 HDA_BIT_CLK HDA_SYNC HDA_RST# HDA_SDIN0 EMI +RTCVCC R11 8 7 6 5HDA_SDOUT 33_0804_8P4R_5% 1 C 1 2 3 4 HDA_BITCLK_AUDIO HDA_SYNC_AUDIO HDA_RST_AUDIO# HDA_SDOUT_AUDIO 2 <39> <39> <39> <39> PCH_TRST PCH_TCK PCH_TDI PCH_TDO PCH_TMS RSVD RSVD JTAGX RSVD SATA_IREF RSVD RSVD SATA_RCOMP SATALED JTAG J5 H5 B15 A15 SATA_PRX_DTX_N0 <30> SATA_PRX_DTX_P0 <30> SATA_PTX_DRX_N0 <30> SATA_PTX_DRX_P0 <30> HDD J8 H8 A17 B17 SATA_PRX_DTX_N1 <30> SATA_PRX_DTX_P1 <30> SATA_PTX_DRX_N1 <30> SATA_PTX_DRX_P1 <30> ODD J6 H6 B14 C15 C F5 E5 C17 D17 V1 U1 V6 AC1 PCH_GPIO34 SATA_ODD_PRSNT PCH_GPIO36 PCH_GPIO37 A12 L11 K10 C12 U3 SATA_RCOMP PCH_SATALED# PCH_GPIO34 <10> SATA_ODD_PRSNT <30,9> PCH_GPIO36 <9> PCH_GPIO37 <10> +1.05VS_ASATA3PLL within 500 mils R13 1 2 3.01K_0402_1% PCH_SATALED# <33> 5 OF 19 BDW-ULT-DDR3L-IL_BGA1168 +3VS 2 330K_0402_5% @ PCH_SATALED# INTVRMEN: (*) H： ： Integrated VRM enable ( ) L： ： Integrated VRM disable B R18 1 2 10K_0402_5% B RTC Battery +RTCVCC +RTCBATT W=20mils R19 1 1 2 0_0402_5% C5 1U_0402_6.3V6K 2 Safty suggestion remove EE side ,Keep PWR side A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 5 4 3 2 HSW MCP(3/11) RTC,SATA,XDP Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 1 Sheet 7 of 55 5 4 3 2 1 GCLK 1 GCLK@ 2 0_0402_5% RG9 <41> CPU_XTAL24_IN_GCLK XTAL24_IN BDW_ULT_DDR3L(Interleaved) UC1F XTAL24_IN C43 C42 U2 PCH_GPIO18 <10> PCH_GPIO18 D Card Reader LAN WLAN dGPU B41 A41 Y5 <40> CLK_PCIE_CR# <40> CLK_PCIE_CR <40> CRCLK_REQ# C41 B42 AD1 <38> CLK_PCIE_LAN# <38> CLK_PCIE_LAN <38> LANCLK_REQ# B38 C37 N1 <31> CLK_PCIE_WLAN# <31> CLK_PCIE_WLAN <31> WLANCLK_REQ# <18> CLK_PCIE_GPU# <18> CLK_PCIE_GPU <19> GPUCLK_REQ# 1 R25 2 0_0402_5% <10> PCH_GPIO23 GPUCLK_REQ#_R A39 B39 U5 PCH_GPIO23 B37 A37 T2 CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 PCIECLKRQ0/GPIO18 XTAL24_IN XTAL24_OUT RSVD RSVD DIFFCLK_BIASREF CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 PCIECLKRQ1/GPIO19 TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8 CLOCK CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCIECLKRQ2/GPIO20 SIGNALS CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 PCIECLKRQ3/GPIO21 CLKOUT_LPC_0 CLKOUT_LPC_1 CLKOUT_ITPXDP CLKOUT_ITPXDP_P CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 PCIECLKRQ4/GPIO22 A25 B25 K21 M21 C26 C35 C34 AK8 AL8 AN15 AP15 XTAL24_IN XTAL24_OUT R21 2NOGCLK@ 1 1M_0402_5% XCLK_BIASREF RP3 4 3 2 1 1 2 3.01K_0402_1% R23 2 1 +1.05VS_AXCK_LCPLL 5 10K_8P4R_5% 6 7 8 CLKOUT_LPC0 B35 A35 R22 CK_LPC_KBC SJ10000DI00 1 C6 15P_0402_50V8J NOGCLK@ 1 22_0402_5% 1 XTAL24_OUT NOGCLK@ 24MHZ_12PF_7V24000020 Y2 3 GND GND 2 4 D 3 1 2 2 C7 15P_0402_50V8J NOGCLK@ <35> EMI CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 PCIECLKRQ5/GPIO23 +3VS 6 OF 19 PCH_GPIO32 <9> UC1G 2 GPUCLK_REQ#_R 1 AU14 AW12 AY12 AW11 AV12 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# <35> LPC_AD0 <35> LPC_AD1 <35> LPC_AD2 <35> LPC_AD3 <35> LPC_FRAME# LAD0 LAD1 LAD2 LAD3 LFRAME +3VS BDW_ULT_DDR3L(Interleaved) LPC SMBUS @EMI@ C225 22P_0402_50V8J R34 R35 1 1 2 1K_0402_1% 2 1K_0402_1% R36 1 2 33_0402_5% 2 EMI 1 C +3V_PCH PCH_SPI_CLK PCH_SPI_CS0# PCH_SPI_SI PCH_SPI_SO PCH_SPI_WP# PCH_SPI_HOLD# AA3 Y7 Y4 AC2 AA2 AA4 Y6 AF1 SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 SPI_MOSI SPI_MISO SPI_IO2 SPI_IO3 @ Q1A SPI SMBALERT/GPIO11 SMBCLK SMBDATA SML0ALERT/GPIO60 SML0CLK SML0DATA SML1ALERT/PCHHOT/GPIO73 SML1CLK/GPIO75 SML1DATA/GPIO74 CL_CLK CL_DATA CL_RST C-LINK AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3 PCH_GPIO11 SMBCLK SMBDATA PCH_GPIO60 SML0CLK SML0DATA PCH_GPIO73 SML1CLK SML1DATA PCH_GPIO11 <10> PCH_GPIO60 <10> PCH_GPIO73 <10> R27 1 2 PCH_GPIO32 6 SMBDATA 2.2K_0402_5% 2 +3VS 1 PCH_SMB_DATA <16,17> PCH_SMB_CLK <16,17> DMN65D8LDW-7 2N SOT363-6 @ Q1B 3 SMBCLK R29 1 5 8 7 6 5 10K_8P4R_5% PX@ R28 10K_0402_5% SMB： ：DIMM1, DIMM2 BDW-ULT-DDR3L-IL_BGA1168 RP4 1 2 3 4 2 1 +3VS UMA@ R26 10K_0402_5% 2.2K_0402_5% 2 +3VS C 4 DMN65D8LDW-7 2N SOT363-6 AF2 AD2 AF4 SMBDATA R31 1 2 0_0402_5% PCH_SMB_DATA SMBCLK R33 1 2 0_0402_5% PCH_SMB_CLK SML1： ：Thermal IC, EC, dGPU 7 OF 19 To SPI 8MByte ROM 8 7 6 5 EMI PCH_SPI_HOLD# PCH_SPI_CLK PCH_SPI_SI PCH_SPI_SO +3VS @ Q2A From PCH R38 1 6 SML1DATA 33_0804_8P4R_5% PCH_SPI_CS0#_R R37 1 2 RP5 1 2 3 4 PCH_SPI_HOLD#_R PCH_SPI_CLK_R PCH_SPI_SI_R PCH_SPI_SO_R BDW-ULT-DDR3L-IL_BGA1168 PCH_SPI_WP# 2.2K_0402_5% 2 +3VS 1 EC_SMB_DA2 <19,32,35> EC_SMB_CK2 <19,32,35> DMN65D8LDW-7 2N SOT363-6 2 0_0402_5% PCH_SPI_CS0# @ Q2B 3 SML1CLK R39 1 5 PCH_SPI_WP#_R 2.2K_0402_5% 2 +3VS 4 DMN65D8LDW-7 2N SOT363-6 SML1DATA R41 1 2 0_0402_5% EC_SMB_DA2 SML1CLK R42 1 2 0_0402_5% EC_SMB_CK2 B B +3V_PCH @ RP7 RP8 1 2 3 4 EC_SPI_CS0# EC_SPI_CLK EC_SPI_MOSI EC_SPI_MISO EMI 1 <35> <35> <35> <35> @EMI@ C226 22P_0402_50V8J 8 7 6 5 PCH_SPI_CS0#_R PCH_SPI_CLK_R PCH_SPI_SI_R PCH_SPI_SO_R 8 7 6 5 2.2K_0804_8P4R_5% To SPI 8MByte ROM SML0CLK SML0DATA 33_0804_8P4R_5% R46 R47 1 1 2 499_0402_1% 2 499_0402_1% 2 From EC (For share ROM) 1 2 3 4 SMBCLK SMBDATA SML1DATA SML1CLK EMI +3V_PCH SPI ROM ( 8MByte ) U1 PCH_SPI_CS0#_R PCH_SPI_SO_R PCH_SPI_WP#_R 1 2 3 4 /CS DO(IO1) /WP(IO2) GND @ VCC /HOLD(IO3) CLK DI(IO0) 8 7 6 5 +3V_ROM PCH_SPI_HOLD#_R PCH_SPI_CLK_R PCH_SPI_SI_R C8 1 2 .1U_0402_16V7K W25Q64FVSSIQ_SO8 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 5 4 3 2 HSW MCP(4/11) CLK,SPI,SMBUS Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 1 Sheet 8 of 55 5 ESD 4 1 1 EC_RSMRST# 1 C239 100P_0402_50V8J @ESD@ C240 100P_0402_50V8J 2 2 2 ESD SYS_PWROK D 3 D Note: SUSACK# and SUSWARN# can be tied together if EC does not want to involve in the handshake mechanism for the Deep Sleep state entry and exit DSWODVREN - On Die DSW VR Enable (*) H： ： Enable(DEFAULT) ( ) L： ： Disable +RTCVCC CAN be NC ,if not support Deep Sx SUSWARN#_R 1 R48 2 0_0402_5% @ 1 2 R54 10K_0402_5% <33,35> AC_PRESENT 1 DS3@ R51 <35,46> SUSACK# <10> SYS_RESET# <35> SYS_PWROK <35> PCH_PWROK R55 1 2 0_0402_5% 2 0_0402_5% SUSACK#_R SYS_RESET# SYS_PWROK PCH_PWROK APWROK_R CPU_PLT_RST# AK2 AC3 AG2 AY7 AB5 AG7 EC_RSMRST# SUSWARN#_R PBTN_OUT# AC_PRESENT PCH_GPIO72 AW6 AV4 AL7 AJ8 AN4 AF3 AM5 SUSACK SYS_RESET SYS_PWROK PCH_PWROK APWROK PLTRST DSWVRMEN DPWROK WAKE CLKRUN/GPIO32 SUS_STAT/GPIO61 SUSCLK/GPIO62 SLP_S5/GPIO63 AC_PRESENT <35> EC_RSMRST# <35> SUSWARN# <35> PBTN_OUT# 1 DS3@ R58 DS3 1 1 2 330K_0402_5% 2 330K_0402_5% @ SYSTEM POWER MANAGEMENT DS3 +3VALW R49 R50 BDW_ULT_DDR3L(Interleaved) UC1H 2 0_0402_5% T15 @ PCH_GPIO29 RSMRST SUSWARN/SUSPWRDNACK/GPIO30 PWRBTN ACPRESENT/GPIO31 BATLOW/GPIO72 SLP_S0 SLP_WLAN/GPIO29 SLP_S4 SLP_S3 SLP_A SLP_SUS SLP_LAN AW7 AV5 AJ5 DSWODVREN PCH_DPWROK R52 R53 R57 DS3 1 DS3@ 1NODS3@ 2 2 0_0402_5% 2 0_0402_5% EC_RSMRST# 1 10K_0402_5% PCH_PCIE_WAKE# V5 AG4 AE6 AP5 PCH_GPIO32 AJ6 AT4 AL5 AP4 AJ7 PM_SLP_S4# PM_SLP_S3# PCH_GPIO32 SUSCLK PM_SLP_S5# DPWROK_EC <35> <31> <8> SUSCLK <31> PM_SLP_S5# <35> PM_SLP_S4# <35> PM_SLP_S3# <35> SLP_SUS# SLP_SUS# <35> DS3 +3VS RP10 SERIRQ PCH_GPIO36 TPMPD# SATA_ODD_PRSNT SERIRQ <10,35> PCH_GPIO36 <7> TPMPD# <10> SATA_ODD_PRSNT 8 OF 19 BDW-ULT-DDR3L-IL_BGA1168 10K_8P4R_5% R59 2 RP11 PCH_GPIO38 <10> @ U3 2 CPU_PLT_RST# 10K_8P4R_5% 1 RP12 PCH_GPIO68 DGPU_PWROK PCH_GPIO55 PCH_GPIO68 B Y A <10,37> 4 PLT_RST# <18,31,35,38,40> R60 100K_0402_5% U74AHC1G08G-AL5-R_SOT353-5 2 8 7 6 5 3 1 2 3 4 1 0_0402_5% +3VS PCH_GPIO38 PCH_GPIO52 1 8 7 6 5 5 1 2 3 4 C <30,7> P 8 7 6 5 G 1 2 3 4 C 10K_8P4R_5% R61 R62 1 1 2 2.2K_0402_5% 2 2.2K_0402_5% DDI1_CTRL_CK DDI1_CTRL_DATA BDW_ULT_DDR3L(Interleaved) UC1I +3V_PCH R64 R65 1 1 2 10K_0402_5% 2 10K_0402_5% SUSWARN#_R PCH_GPIO72 <27> INVPWM <27,35> ENBKL <27> PCH_ENVDD R63 0_0402_5% 1 2 EDP_BKCTL <51> DGPU_PWROK <20,35,48,51> DGPU_PWR_EN <18> DGPU_HOLD_RST# <10,31> WLBT_OFF# B T16 +3VALW R66 R67 +3VGS +3VGS 1 1 @ 2 10K_0402_5% 2 1K_0402_5% PCH_GPIO29 PCH_PCIE_WAKE# <10> PCH_GPIO54 <10> PCH_GPIO51 <10> PCH_GPIO53 PCH_GPIO55 PCH_GPIO52 PCH_GPIO54 PCH_GPIO51 PCH_GPIO53 @ B8 A9 C6 U6 P4 N4 N2 AD4 U7 L1 L3 R5 L4 EDP_BKLCTL EDP_BKLEN EDP_VDDEN DDPB_CTRLCLK DDPB_CTRLDATA DDPC_CTRLCLK DDPC_CTRLDATA eDP SIDEBAND PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME DISPLAY PCIE GPIO55 GPIO52 GPIO54 GPIO51 GPIO53 DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP DDPB_HPD DDPC_HPD EDP_HPD B9 C9 D9 D11 DDI1_CTRL_CK DDI1_CTRL_DATA C5 B6 B5 A6 DDI1_AUX_DN DDI2_AUX_DN DDI1_AUX_DP DDI2_AUX_DP C8 A8 D6 DDPC_HPD HDMICLK_NB HDMIDAT_NB <28,37> <28,37> DDI1_AUX_DN DDI2_AUX_DN DDI1_AUX_DP DDI2_AUX_DP R148 1 2 0_0402_5% HDMI DDC (Port C) <29> <37> <29> <37> DP Aux (Port B for VGA) DP Aux (Port C for Docking) DP Aux (Port B for VGA) DP Aux (Port C for Docking) DDI1_HPD <29> TMDS_B_HPD <28,37> EDP_HPD <27> B From VGA Trans. From HDMI From eDP 9 OF 19 +3VS BDW-ULT-DDR3L-IL_BGA1168 R223 1 R224 1 2 10K_0402_5% 2 10K_0402_5% DGPU_PWR_EN @ R225 1 R226 1 2 10K_0402_5% 2 10K_0402_5% DGPU_HOLD_RST# @ +3VS A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 5 4 3 2 HSW MCP(5/11) PM,GPIO,DDI Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 1 Sheet 9 of 55 5 4 3 2 1 D D ESD +3V_PCH RP13 8 7 6 5 Docking_PRSNT# PCH_GPIO47 PCH_GPIO24 PCH_GPIO28 H_THERMTRIP# 1 1 2 3 4 +1.05VS PCH_GPIO11 PCH_GPIO60 PCH_GPIO26 PCH_GPIO58 PCH_GPIO11 PCH_GPIO60 <8> <8> R288 1 2 10K_0402_5% @ RP16 1 2 3 4 C 8 7 6 5 USB_OC1# PCH_GPIO59 PCH_GPIO8 PCH_GPIO43 PCH_GPIO57 PCH_GPIO43 <11,34> 1 2 3 4 2 <11> PCH_GPIO12 PCH_GPIO15 <30> ODD_EN <30> ODD_DA# <11> <9> TPMPD# <27> TS_INT# PCH_GPIO56 PCH_GPIO14 PCH_GPIO46 <27> TS_Detect <36,37> Docking_PRSNT# 10K_8P4R_5% +3VALW <11> PCH_GPIO10 R292 1 2 10K_0402_5% P1 AU2 AM7 AD6 Y1 T3 AD5 AN5 AD7 AN3 PCH_GPIO76 PCH_GPIO8 R69 1 @ 1K_0402_1% 10K_8P4R_5% @ RP9 8 7 6 5 R68 1K_0402_1% +3V_PCH 10K_8P4R_5% BDW_ULT_DDR3L(Interleaved) UC1J C241 100P_0402_50V8J 1 GPIO15 : TLS Confidentiality for iAMT ( ) H： ： Intel ME TLS with confidenAality (*) L： ： Intel ME TLS with no confidenAality (Have internal PD) PCH_GPIO24 PCH_GPIO27 PCH_GPIO28 PCH_GPIO26 AG6 AP1 AL4 AT5 AK4 AB6 U4 Y3 P3 Y2 AT3 AH4 AM4 AG5 AG3 PCH_GPIO56 PCH_GPIO57 PCH_GPIO58 PCH_GPIO59 PCH_GPIO44 PCH_GPIO47 TPMPD# DGPU_PRSNT# TS_INT# PCH_GPIO71 PCH_GPIO13 PCH_GPIO14 TS_Detect Docking_PRSNT# PCH_GPIO46 AM3 AM2 P2 C4 L2 N5 V2 PCH_GPIO33 PCH_GPIO27 <9> PCH_GPIO38 <35> EC_SCI# <39> HDA_SPKR PCH_GPIO38 BMBUSY/GPIO76 GPIO8 LAN_PHY_PWR_CTRL/GPIO12 GPIO15 GPIO16 GPIO17 GPIO24 GPIO27 GPIO28 GPIO26 GPIO56 GPIO57 GPIO58 GPIO59 GPIO44 GPIO47 GPIO48 GPIO49 GPIO50 HSIOPC/GPIO71 GPIO13 GPIO14 GPIO25 GPIO45 GPIO46 CPU/ MISC GPIO SERIAL IO GPIO9 GPIO10 DEVSLP0/GPIO33 SDIO_POWER_EN/GPIO70 DEVSLP1/GPIO38 DEVSLP2/GPIO39 SPKR/GPIO81 THRMTRIP RCIN/GPIO82 SERIRQ PCH_OPI_RCOMP RSVD RSVD GSPI0_CS/GPIO83 GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86 GSPI1_CS/GPIO87 GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89 GSPI_MOSI/GPIO90 UART0_RXD/GPIO91 UART0_TXD/GPIO92 UART0_RTS/GPIO93 UART0_CTS/GPIO94 UART1_RXD/GPIO0 UART1_TXD/GPIO1 UART1_RST/GPIO2 UART1_CTS/GPIO3 I2C0_SDA/GPIO4 I2C0_SCL/GPIO5 I2C1_SDA/GPIO6 I2C1_SCL/GPIO7 SDIO_CLK/GPIO64 SDIO_CMD/GPIO65 SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69 D60 V4 T4 AW15 AF20 AB21 R6 L6 N6 L8 R7 L5 N7 K2 J1 K3 J2 G1 K4 G2 J3 J4 F2 F3 G4 F1 E3 F4 D3 E4 C3 E2 H_THERMTRIP# 2 8 7 6 5 2 10K_8P4R_5% @ RP14 1 2 3 4 SERIRQ PCH_OPIRCOMP R70 1 KB_RST# <35> SERIRQ <35,9> 2 49.9_0402_1% PCH_GPIO86： ： Boot BIOS LocaAon ( ) H： ： LPC BUS (*) L： ： SPI BUS PCH_GPIO83 PCH_GPIO84 PCH_GPIO85 PCH_GPIO86 PCH_GPIO87 PCH_GPIO88 PCH_GPIO89 PCH_GPIO90 PCH_GPIO91 PCH_GPIO92 PCH_GPIO93 PCH_GPIO94 PCH_GPIO0 PCH_GPIO1 PCH_GPIO2 PCH_GPIO3 PCH_GPIO4 PCH_GPIO5 PCH_GPIO6 PCH_GPIO7 PCH_GPIO64 PCH_GPIO65 PCH_GPIO66 PCH_GPIO67 PCH_GPIO68 PCH_GPIO69 +3VS R71 R72 1 1 @ 2 1K_0402_1% 2 1K_0402_1% SDIO_D0 / GPIO66 : Top-Block Swap Override (*) H： ： DISABLED ( ) L： ： ENABLED(Have internal PD) R75 PCH_GPIO68 C +3VS 2 150K_0402_1% 1 <37,9> 10 OF 19 BDW-ULT-DDR3L-IL_BGA1168 +3VS BIOS Strap Pin +3VS RP17 1 2 3 4 B RP18 8 7 6 5 ODD_DA# PCH_GPIO23 KB_RST# SYS_RESET# PCH_GPIO23 <8> SYS_RESET# <9> 1 2 3 4 10K_8P4R_5% @ RP19 1 2 3 4 WLBT_OFF# WLBT_OFF# <31,9> Function PCH_GPIO33 PCH_GPIO76 10K_8P4R_5% RP20 8 7 6 5 1 2 3 4 PCH_GPIO65 PCH_GPIO5 PCH_GPIO67 10K_8P4R_5% @ RP21 1 2 3 4 8 7 6 5 8 7 6 5 PCH_GPIO34 ODD_EN PCH_GPIO37 PCH_GPIO71 PCH_GPIO34 <7> PCH_GPIO37 <7> PCH_GPIO18 <8> Reserved 0 Function GPIO54 NoDocking SKU 1 Docking SKU 0 Function +3VS R300 1 R301 1 @ @ 2 10K_0402_5% 2 10K_0402_5% 8 7 6 5 PCH_GPIO93 PCH_GPIO91 PCH_GPIO92 PCH_GPIO90 R304 1 R305 1 PCH_GPIO88 PCH_GPIO53 PCH_GPIO84 PCH_GPIO3 8 7 6 5 @ @ 2 10K_0402_5% 2 10K_0402_5% PCH_GPIO2 PCH_GPIO18 1 2 3 4 PCH_GPIO87 PCH_GPIO83 RP2 8 7 6 5 PCH_GPIO54 PCH_GPIO54 8 7 6 5 EC_SCI# PCH_GPIO85 PCH_GPIO0 PCH_GPIO89 10K_8P4R_5% PCH_GPIO53 <9> Function GPIO94 Reserved 1 Reserved 0 Function +3VS PCH_GPIO51 PCH_GPIO51 <9> GPIO44 Zero ODD 1 No Zero ODD 0 R302 1 R303 1 @ @ 2 10K_0402_5% 2 10K_0402_5% R284 1 ZODD@ 2 10K_0402_5% R285 1NOZODD@ 2 10K_0402_5% PCH_GPIO94 @ RP25 1 2 3 4 8 7 6 5 B PCH_GPIO64 PCH_GPIO44 DGPU_PRSNT# (GPIO49) 0 0 Reserved 0 1 DIS Only 1 0 UMA Only 1 1 +3VS PCH_GPIO69 PCH_GPIO4 PCH_GPIO7 PCH_GPIO6 R276 1 R277 1 2 0_0402_5% 2 0_0402_5% Function I2C_1_SCL <27> I2C_1_SDA <27> 2.2K_0804_8P4R_5% 2 1K_0402_5% GPIO13 SG R282 1 UMA@ R283 1 PX@ 2 10K_0402_5% 2 10K_0402_5% PCH_GPIO13 1 UMA@ 1 PX@ 2 10K_0402_5% 2 10K_0402_5% DGPU_PRSNT# GPIO73 Single Rank 1 Dual Rank 0 +3VS R73 R74 +3VS @ 1 Function +3VS A 1 TOPAZ XT R245 1 TOPAZ@ 2 10K_0402_5% 2 10K_0402_5% R246 1 JET@ <9> 10K_8P4R_5% RP26 R76 0 +3VS NoDocking@ 2 10K_0402_5% R248 1 2 10K_0402_5% R247 1 Docking@ PCH_GPIO1 GPIO64 JET LE 10K_8P4R_5% 10K_8P4R_5% 1 2 3 4 1 +3VS 10K_8P4R_5% @ RP24 1 2 3 4 GPIO1 Reserved A HDA_SPKR R286 1 R287 1 PCH_GPIO73 PCH_GPIO73 <8> Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date SR@ 2 10K_0402_5% DR@ 2 10K_0402_5% 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 5 4 3 2 HSW MCP(6/11) GPIO,LPIO Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 1 Sheet 10 of 55 5 4 3 2 1 D D BDW_ULT_DDR3L(Interleaved) UC1K F10 E10 <18> PCIE_CRX_GTX_N0 <18> PCIE_CRX_GTX_P0 1 PX@ 2 .1U_0402_16V7K 1 PX@ 2 .1U_0402_16V7K C10 C11 <18> PCIE_CTX_GRX_N0 <18> PCIE_CTX_GRX_P0 PCIE_PTX_DRX_N5_L0 PCIE_PTX_DRX_P5_L0 F8 E8 <18> PCIE_CRX_GTX_N1 <18> PCIE_CRX_GTX_P1 dGPU <18> PCIE_CTX_GRX_N1 <18> PCIE_CTX_GRX_P1 C12 C13 1 PX@ 2 .1U_0402_16V7K 1 PX@ 2 .1U_0402_16V7K PCIE_PTX_DRX_N5_L1 PCIE_PTX_DRX_P5_L1 C14 C15 1 PX@ 2 .1U_0402_16V7K 1 PX@ 2 .1U_0402_16V7K PCIE_PTX_DRX_N5_L2 PCIE_PTX_DRX_P5_L2 C16 C17 <18> PCIE_CTX_GRX_N3 <18> PCIE_CTX_GRX_P3 Card Reader (For B14/E14/B15) PCIE_PTX_DRX_N5_L3 PCIE_PTX_DRX_P5_L3 B22 A21 G11 F11 C22 C23 1 1 2 .1U_0402_16V7K 2 .1U_0402_16V7K PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3 C29 B30 F13 G13 <31> PCIE_PRX_DTX_N4 <31> PCIE_PRX_DTX_P4 C18 C19 <31> PCIE_PTX_C_DRX_N4 <31> PCIE_PTX_C_DRX_P4 USB2/3 Docking (For B15) 1 PX@ 2 .1U_0402_16V7K 1 PX@ 2 .1U_0402_16V7K <38> PCIE_PRX_DTX_N3 <38> PCIE_PRX_DTX_P3 <38> PCIE_PTX_C_DRX_N3 <38> PCIE_PTX_C_DRX_P3 WLAN B21 C21 E6 F6 <18> PCIE_CRX_GTX_N3 <18> PCIE_CRX_GTX_P3 LAN B23 A23 H10 G10 <18> PCIE_CRX_GTX_N2 <18> PCIE_CRX_GTX_P2 <18> PCIE_CTX_GRX_N2 <18> PCIE_CTX_GRX_P2 C C23 C22 1 1 2 .1U_0402_16V7K 2 .1U_0402_16V7K PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4 B29 A29 G17 F17 <36> USB3_RX3_N <36> USB3_RX3_P C30 C31 <36> USB3_TX3_N <36> USB3_TX3_P F15 G15 <40> PCIE_PRX_DTX_N2 <40> PCIE_PRX_DTX_P2 C20 C21 <40> PCIE_PTX_C_DRX_N2 <40> PCIE_PTX_C_DRX_P2 1 1 2 .1U_0402_16V7K 2 .1U_0402_16V7K PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2 B31 A31 PERN5_L0 PERP5_L0 USB2N0 USB2P0 PETN5_L0 PETP5_L0 USB2N1 USB2P1 PERN5_L1 PERP5_L1 USB2N2 USB2P2 PETN5_L1 PETP5_L1 USB2N3 USB2P3 PERN5_L2 PERP5_L2 USB2N4 USB2P4 PETN5_L2 PETP5_L2 USB2N5 USB2P5 PERN5_L3 PERP5_L3 USB2N6 USB2P6 PETN5_L3 PETP5_L3 USB2N7 USB2P7 PERN3 PERP3 PETN3 PETP3 USB3RN1 USB3RP1 PCIE USB USB3RN2 USB3RP2 PETN4 PETP4 USB3TN2 USB3TP2 R78 1 2 3.01K_0402_1% PCIE_RCOMP AR7 AT7 AR8 AP8 AR10 AT10 USB20_N0 <34> USB20_P0 <34> Left USB2/3__I/O Port (Near End User) USB20_N1 <34> USB20_P1 <34> Left USB2/3__I/O Port (Near HDMI CONN)(Debug Port) USB20_N2 <34> USB20_P2 <34> Right USB2__I/O Port (Sub Board) PETN1/USB3TN3 PETP1/USB3TP3 USBRBIAS USBRBIAS RSVD RSVD AM15 AL15 AM13 AN13 AP11 AN11 AR13 AP13 G20 H20 C33 B34 PERN2/USB3RN4 PERP2/USB3RP4 PETN2/USB3TN4 PETP2/USB3TP4 OC0/GPIO40 OC1/GPIO41 OC2/GPIO42 OC3/GPIO43 RSVD RSVD PCIE_RCOMP PCIE_IREF Docking@1 1 E14@ 1 E14@ Docking@1 Touch Screen USB20_N5 <27> USB20_P5 <27> Camera USB20_N6 <31> USB20_P6 <31> Bluetooth (NGFF) USB20_N7 <34> USB20_P7 <34> Finger Print (For B14/E14/B15) 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% USB20_N3_D USB20_N3_U USB20_P3_U USB20_P3_D <36> <34> <34> <36> Card Reader (For G14/15) Right USB Port (For E14) Docking (For B15) C Left USB2/3__I/O Port USB3_TX1_N <34> USB3_TX1_P <34> USB3_RX2_N <34> USB3_RX2_P <34> B33 A33 AL3 AT1 AH2 AV3 2 2 2 2 USB20_N4 <27> USB20_P4 <27> USB3_RX1_N <34> USB3_RX1_P <34> E18 F18 AJ10 AJ11 AN10 AM10 R241 R243 R244 R242 USB20_N3 USB20_P3 Left USB2/3__I/O Port USB3_TX2_N <34> USB3_TX2_P <34> PERN1/USB3RN3 PERP1/USB3RP3 +1.05VS_AUSB3PLL E15 E13 A27 B27 USB3TN1 USB3TP1 PERN4 PERP4 AN8 AM8 USBRBIAS USB_OC0# USB_OC1# PCH_GPIO42 PCH_GPIO43 R77 1 2 22.6_0402_1% CAD note: Route single-end 50-ohms and max 450-mils length. Avoid routing next to clock pins or under stitching capacitors. Recommended minimum spacing to other signal traces is 15 mils USB_OC0# <34> USB_OC1# <10,34> PCH_GPIO43 <10> B B 11 OF 19 BDW-ULT-DDR3L-IL_BGA1168 +3V_PCH RP27 USB_OC0# <10> PCH_GPIO10 PCH_GPIO42 <10> PCH_GPIO12 1 2 3 4 8 7 6 5 10K_8P4R_5% A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 5 4 3 2 HSW MCP(7/11) PCIE,USB Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 1 Sheet 11 of 55 5 4 3 2 L59 J58 +1.35V AH26 AJ31 AJ33 AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50 1 +1.05VS +CPU_CORE 2 R79 10K_0402_5% F59 N58 AC58 VCCST_PWRGD <35> VCCST_PWRGD E63 AB23 A59 E20 AD23 AA23 AE59 VCCSENSE T17 +VCCIOA_OUT L62 N63 L63 B59 F60 C59 H_CPU_SVIDALRT# <52> VR_SVID_CLK <52> VR_ON R80 1 H_CPU_SVIDDATA VCCST_PWRGD 2 10K_0402_5% <52> VGATE D63 H59 P62 P60 P61 N59 N61 T59 AD60 AD59 AA59 AE60 AC59 AG58 U59 V59 CPU_PWR_DEBUG C +1.05VS Place the PU resistors close to CPU 1 SVID ALERT 2 R81 75_0402_5% <52> VR_SVID_ALRT# +1.05VS R82 43_0402_1% 2 1 AC22 AE22 AE23 +CPU_CORE H_CPU_SVIDALRT# AB57 AD57 AG57 C24 C28 C32 +1.05VS D RSVD RSVD VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VCC RSVD RSVD VCC_SENSE RSVD VCCIO_OUT VCCIOA_OUT RSVD RSVD RSVD VIDALERT VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY HSW ULT POWER VSS PWR_DEBUG VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VCCST VCCST VCCST VCC VCC VCC VCC VCC VCC C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57 C 12 OF 19 Place the PU resistors close to CPU 2 SVID DATA +CPU_CORE BDW_ULT_DDR3L(Interleaved) UC1L D 1 BDW-ULT-DDR3L-IL_BGA1168 R83 1 130_0402_1% R84 <52> VR_SVID_DAT 1 2 H_CPU_SVIDDATA 0_0402_5% B +1.35V B VDDQ DECOUPLING 2 1 1 2 2 2 1 2 1 2 C33 10U_0603_6.3V6M 2 1 C32 10U_0603_6.3V6M 2 1 C31 10U_0603_6.3V6M <52> VCCSENSE 2 1 C30 10U_0603_6.3V6M CPU_PWR_DEBUG VCCSENSE 2 1 C29 10U_0603_6.3V6M @ 2 1 C28 10U_0603_6.3V6M PU resistor should be close to CPU 2 1 C27 2.2U_0402_6.3V6M R85 100_0402_1% R253: CPU_PWR_DEBUG CRB mount Check list ,XDP use only @ 1 C26 2.2U_0402_6.3V6M 2 R86 150_0402_1% C25 2.2U_0402_6.3V6M +CPU_CORE C24 2.2U_0402_6.3V6M 1 +1.05VS @ CRB: +1.35V : 470UF/2V/7343 *2 (Un-mount) 10UF/6.3V/0603 * 6 2.2UF/6.3V/0402 * 4 R87 @ 10K_0402_5% 1 1 <14,52> VSSSENSE PD resistor should be close to CPU 2 R88 100_0402_1% A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 5 4 3 2 HSW MCP(8/11) Power Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 1 Sheet 12 of 55 5 4 3 2 1 +RTCVCC +1.05VS_AUSB3PLL @ L1 2.2UH_LQM2MPN2R2NG0L_30% 1 2 2 +1.05VS_ASATA3PLL 42mA +1.05VS 1 2 R89 0_0603_5% 1 @ 2 Close to M9 C41 1U_0402_6.3V6K 2 L3 2.2UH_LQM2MPN2R2NG0L_30% 1 2 @ 1 2 C48 22U_0603_6.3V6M 2 C47 47U_0805_6.3V6M 1 @ C 1 1 @ 200mA 2 2 2 2 Y20 AA21 W21 +3VALW Close to AH10 C53 1U_0402_6.3V6K RTC HSIO VCCSUS3_3 VCCRTC DCPRTC 1 31mA C55 1U_0402_6.3V6K @ SPI RSVD VCCAPLL VCCAPLL VCCSPI OPI VCCASW VCCASW @ T18 J13 C54 1U_0402_6.3V6K AH14 1 @ T19 AH13 C62 1U_0402_6.3V6K Close to V8 1 41mA C63 22U_0603_6.3V6M DCPSUS3 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 DCPSUSBYP DCPSUSBYP VCCASW VCCASW VCCASW DCPSUS1 DCPSUS1 HDA VCCHDA VRM DCPSUS2 CORE VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3 GPIO/LPC 2 +1.05VS_AXCK_DCB +1.05VS Close to J17 SERIAL IO VCCSDIO VCCSDIO SUS OSCILLATOR DCPSUS4 +PCH_VCCDSW C59 RSVD VCC1_05 VCC1_05 @ @ U8 T9 AC20 AG16 AG17 +1.5VS Close to AC9,AA9, AE20,AE21 1 C58 10U_0603_6.3V6M 2 2 1U_0402_6.3V6K 3mA +3VS @ T22 1 C71 2 13 OF 19 BDW-ULT-DDR3L-IL_BGA1168 C57 1U_0402_6.3V6K 2 +1.05VS T20 T21 17mA 1 C64 1 C65 2 2 @ +3VS 1 C68 1 C69 2 2 +1.05VS USB2 1 J15 K14 K16 AB8 1 C56 1U_0402_6.3V6K 2 LPT LP POWER C70 22U_0603_6.3V6M 2 1 J11 H11 H15 AE8 AF22 AG19 AG20 AE9 AF9 AG8 AD10 AD8 1U_0402_6.3V6K Close to R21 1 +1.05VS .1U_0402_16V7K 2 +3V_PCH C67 1U_0402_6.3V6K 2 1U_0402_6.3V6K B 1 C66 VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD VCCSUS3_3 VCCSUS3_3 1741/1632mA AG14 AG13 1U_0402_6.3V6K 1 J18 K19 A20 J17 R21 T21 K18 M20 V21 AE20 AE21 VCCTS1_5 VCC3_3 VCC3_3 C +1.05VS C50 .1U_0402_16V7K 2@ Y8 USB3 THERMAL SENSOR +1.05VS_AXCK_LCPLL 658mA 22U_0603_6.3V6M 2 18mA +VCCRTCEXT 1U_0402_6.3V6K C61 47U_0805_6.3V6M C60 22U_0603_6.3V6M @ 2 AC9 AA9 AH10 V8 W9 +3VS C49 .1U_0402_16V7K 2 AH11 AG10 AE7 1 Close to AH14 2 2 2 1 +3V_PCH 1 +RTCVCC VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL +3VALW 1 C45 1U_0402_6.3V6K BDW_ULT_DDR3L(Interleaved) UC1M K9 L10 M9 N8 P9 B18 B11 +1.05VS_AUSB3PLL +3V_PCH 1 @ +1.05VS_AXCK_LCPLL 2 1 +1.05VS_APLLOPI L5 2.2UH_LQM2MPN2R2NG0L_30% 1 2 1 1 C44 2 2 2 +1.05VS_ASATA3PLL 1 C43 VCCHDA=11mA VCCDSW3_3= 114mA C52 47U_0805_6.3V6M C51 22U_0603_6.3V6M R272 0_0402_5% C46 1U_0402_6.3V6K +1.05VS_AXCK_DCB @ L4 2.2UH_LQM2MPN2R2NG0L_30% 1 2 1 1 @ 1U_0402_6.3V6K 57mA Close to K9, L10 1U_0402_6.3V6K 1 C42 +1.05VS_APLLOPI 1U_0402_6.3V6K C40 47U_0805_6.3V6M 2 C39 22U_0603_6.3V6M 1 2 63/62mA +3V_PCH 1838mA L2 2.2UH_LQM2MPN2R2NG0L_30% 1 2 C37 1 2 2 C36 1U_0402_6.3V6K 2 2 1 @ 1@ C38 .1U_0402_16V7K 1 @ 1 1U_0402_6.3V6K 1 D C35 22U_0603_6.3V6M R271 0_0402_5% C34 47U_0805_6.3V6M 1 <1mA 41mA 2 +1.05VS D B A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 5 4 3 2 HSW MCP(9/11) Power Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 1 Sheet 13 of 55 5 4 3 2 1 D D UC1N A11 A14 A18 A24 A28 A32 A36 A40 A44 A48 A52 A56 AA1 AA58 AB10 AB20 AB22 AB7 AC61 AD21 AD3 AD63 AE10 AE5 AE58 AF11 AF12 AF14 AF15 AF17 AF18 AG1 AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57 AJ13 AJ14 AJ23 AJ25 AJ27 AJ29 C B BDW_ULT_DDR3L(Interleaved) VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS UC1O AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20 AP22 AP23 AP26 AP29 AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49 AR5 AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63 AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS BDW_ULT_DDR3L(Interleaved) VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 15 OF 19 UC1P AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31 D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49 D5 D50 D51 D53 D54 D55 D57 D59 D62 D8 E11 E17 F20 F26 F30 F34 F38 F42 F46 F50 F54 F58 F61 G18 G22 G3 G5 G6 G8 H13 BDW_ULT_DDR3L(Interleaved) VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 16 OF 19 VSS VSS VSS VSS_SENSE VSS H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63 V58 AH46 V23 E62 AH16 C VSSSENSE VSSSENSE <12,52> BDW-ULT-DDR3L-IL_BGA1168 B BDW-ULT-DDR3L-IL_BGA1168 14 OF 19 BDW-ULT-DDR3L-IL_BGA1168 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 5 4 3 2 HSW MCP(10/11) GND Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 1 Sheet 14 of 55 1 BDW_ULT_DDR3L(Interleaved) UC1R UC1Q T23 T26 AY2 DC_TEST_AY2_AW2 AY3 DC_TEST_AY3_AW3 AY60 @ DC_TEST_AY61_AW61 AY61 DC_TEST_AY62_AW62 AY62 B2 @ B3 DC_TEST_A3_B3 B61 DC_TEST_A61_B61 B62 DC_TEST_B62_B63 B63 C1 DC_TEST_C1_C2 C2 RSVD RSVD RSVD RSVD BDW_ULT_DDR3L(Interleaved) DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_AY60 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4 17 OF 19 DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62 DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3 DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63 A3 A4 A60 A61 A62 AV1 AW1 AW2 AW3 AW61 AW62 AW63 DC_TEST_A3_B3 @ @ DC_TEST_A61_B61 @ @ @ DC_TEST_AY2_AW2 DC_TEST_AY3_AW3 DC_TEST_AY61_AW61 DC_TEST_AY62_AW62 @ AT2 AU44 AV44 D15 T24 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD T25 F22 H22 J21 T27 T28 T29 RSVD RSVD RSVD N23 R23 T23 U10 AL1 AM11 AP7 AU10 AU15 AW14 AY14 18 OF 19 BDW-ULT-DDR3L-IL_BGA1168 T30 BDW-ULT-DDR3L-IL_BGA1168 A AA62 U63 AA61 U62 CFG_RCOMP V63 A5 TD_IREF E1 D1 J20 H18 B12 RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD_TP RSVD_TP RSVD_TP RESERVED RSVD RSVD RSVD PROC_OPI_RCOMP CFG16 CFG18 CFG17 CFG19 RSVD RSVD CFG_RCOMP VSS VSS RSVD RSVD RSVD RSVD RSVD RSVD RSVD TD_IREF AV63 AU63 CFG Straps for Processor C63 C62 B43 CFG3 A51 B51 1 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 R92 1K_0402_1% @ L60 N60 W23 Y22 AY15 2 AC60 AC62 AC63 AA63 AA60 Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61 T60 CFG3 CFG4 BDW_ULT_DDR3L(Interleaved) A OPI_COMP AV62 D58 Physical Debug Enable (DFX Privacy) P22 N21 CFG3 P20 R20 1: DISABLED 0: ENABLED; SET DFX ENABLED BIT IN DEBUG INTERFACE MSR CFG4 1 UC1S 19 OF 19 BDW-ULT-DDR3L-IL_BGA1168 2 R93 1K_0402_1% 2 R94 2 R95 2 R96 1 CFG_RCOMP 49.9_0402_1% 1 OPI_COMP 49.9_0402_1% 1 TD_IREF 8.2K_0402_5% Display Port Presence Strap CFG4 1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: HSW MCP(11/11) RSVD Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 Sheet 15 of 55 A B C +SM_VREF_DQ0 <6> DDR_A_D[0..63] D E DIMM1 Reverse Type Near CPU <6> +1.35V D/DQ Signals link to CPU 1 <6> DDR_A_DQS#[0..7] <6> DDR_A_DQS[0..7] DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 Layout Note: Place near JDIMM1 DDR_A_D26 DDR_A_D27 +1.35V +1.35V 2 1 2 @ 1 2 DDR_A_BS2 C79 1U_0402_6.3V6K @ C78 1U_0402_6.3V6K 2 1 C77 1U_0402_6.3V6K 1 C76 1U_0402_6.3V6K 2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 M_CLK_DDR0 M_CLK_DDR#0 +1.35V 2 1 2 @ 1 + DDR_A_MA13 DDR_CS1_DIMMA# C250 330U_D3_2.5VY_R6M 2 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 Layout Note: Place near JDIMM1.203,204 Layout Note: Place near JDIMM1.199 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 3 +3VS +0.675VS DDR_A_D48 DDR_A_D49 1 2 1 2 DDR_A_DQS#6 DDR_A_DQS6 C99 0.1U_0402_25V6K 2 @ C98 2.2U_0402_6.3V6M 2 1 C97 1U_0402_6.3V6K 2 1 C96 1U_0402_6.3V6K @ 1 C95 0.1U_0402_25V6K 2 C94 0.1U_0402_25V6K @ 1 Address : 00 R105 1 2 0_0402_5% DDR_A_SA0 R106 1 2 0_0402_5% DDR_A_SA1 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 +0.675VS +3VS DDR_A_D58 DDR_A_D59 DDR_A_SA0 DDR_A_SA1 205 DDR3L SODIMM ODT GENERATION 4 R107 66.5_0402_1% 1 2 1 +5VALW R109 66.5_0402_1% 1 2 1 2 3 NC VCC A Y 4 GND 74AUP1G07GW TSSOP 5P BUFFER For ODT & VTT power control 1 From CPU 2 <5> DDR_PG_CTRL R108 220K_0402_5% 5 D 3 U4 1 S Q3 LBSS138LT1G_SOT-23-3 2 G M_A_B_DIMM_ODT ESD DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 +1.35V DDR_CKE1_DIMMA DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 2 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR1 M_CLK_DDR#1 +1.35V DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# SA_ODT0 R101 1.8K_0402_1% +VREF_CA SA_ODT1 10mils DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 1 2 1 2 R102 0_0402_5% 1 2 +SM_VREF_CA @ R103 1.8K_0402_1% DDR_A_D44 DDR_A_D45 @ R104 24.9_0402_1% DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 3 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 +0.675VS PCH_SMB_DATA PCH_SMB_CLK 206 4 SA_ODT0 R111 66.5_0402_1% 1 2 SA_ODT1 Interleaved Memory Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 Title <47> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size C Date: A <6> @ C93 0.022U_0402_16V7K SB_ODT1 <17> R110 66.5_0402_1% 1 2 Issued Date DDR_VTT_PG_CTRL DDR_A_D22 DDR_A_D23 <17,5> SB_ODT0 <17> +1.35V 2 GND2 DDR_A_D20 DDR_A_D21 C75 100P_0402_50V8J 2 @ESD@ ARGOS_DS2RK-20401-TP4B ME@ SP070014D00 +1.35V C100 .1U_0402_16V7K GND1 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 1 C91 DDR_A_D32 DDR_A_D33 CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT DIMM_DRAMRST# DDR_A_D14 DDR_A_D15 C92 0.1U_0402_25V6K 2 1 DDR_A_WE# DDR_A_CAS# C89 2 1 10U_0603_6.3V6M C88 2 @ 1 10U_0603_6.3V6M C87 2 1 10U_0603_6.3V6M C86 2 1 10U_0603_6.3V6M C85 @ 1 10U_0603_6.3V6M C84 10U_0603_6.3V6M C83 2 10U_0603_6.3V6M C82 10U_0603_6.3V6M 1 DDR_A_MA10 DDR_A_BS0 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT DDR3_DRAMRST# 2.2U_0402_6.3V6M 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDR_CKE0_DIMMA DDR_A_D12 DDR_A_D13 1 DDR_A_DQS#2 DDR_A_DQS2 1 DDR_A_D6 DDR_A_D7 1 2 DDR_A_D16 DDR_A_D17 SMBUS Signals link to CPU DDR_A_DQS#0 DDR_A_DQS0 2 DDR_A_D10 DDR_A_D11 CTL Signals from CPU DDR_A_D4 DDR_A_D5 1 DDR_A_D8 DDR_A_D9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 2 DDR_A_D2 DDR_A_D3 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS 1 2 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS 2 1 2 @2 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 DDR_A_D0 DDR_A_D1 DDR_A_DQS#1 DDR_A_DQS1 PCH_SMB_DATA PCH_SMB_CLK <17,8> PCH_SMB_DATA <17,8> PCH_SMB_CLK 1 2 Clock Signals from CPU JDIMM1 10mils R99 1.8K_0402_1% R100 24.9_0402_1% @ DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CS0_DIMMA# DDR_CS1_DIMMA# <6> DDR_CKE0_DIMMA <6> DDR_CKE1_DIMMA <6> DDR_CS0_DIMMA# <6> DDR_CS1_DIMMA# 1 1 2 M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1 <6> M_CLK_DDR#0 <6> M_CLK_DDR0 <6> M_CLK_DDR#1 <6> M_CLK_DDR1 @ C72 0.022U_0402_16V7K C74 0.1U_0402_25V6K 1 CMD Signals from CPU C73 2.2U_0402_6.3V6M DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_RAS# DDR_A_WE# DDR_A_CAS# <6> DDR_A_BS0 <6> DDR_A_BS1 <6> DDR_A_BS2 <6> DDR_A_RAS# <6> DDR_A_WE# <6> DDR_A_CAS# R97 1.8K_0402_1% +SM_VREF_DQ0_DIMM1 2 R98 0_0402_5% 1 2 <6> DDR_A_MA[0..15] B C D Compal Electronics, Inc. DDR3L_DIMMA Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 E Sheet 16 of 55 A B +SM_VREF_DQ1 <6> DDR_B_D[0..63] C D E DIMM2 Standard Type Near User <6> +1.35V D/DQ Signals link to CPU 1 <6> DDR_B_DQS#[0..7] <6> DDR_B_DQS[0..7] 2 2 @2 1 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 DDR_B_D23 DDR_B_D17 DDR_B_D21 DDR_B_D18 DDR_B_D3 DDR_B_D2 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D0 DDR_B_D1 CTL Signals from CPU DDR_B_D12 DDR_B_D8 PCH_SMB_DATA PCH_SMB_CLK <16,8> PCH_SMB_DATA <16,8> PCH_SMB_CLK 1 2 Clock Signals from CPU JDIMM2 10mils R114 1.8K_0402_1% R115 24.9_0402_1% @ DDR_CKE2_DIMMB DDR_CKE3_DIMMB DDR_CS2_DIMMB# DDR_CS3_DIMMB# <6> DDR_CKE2_DIMMB <6> DDR_CKE3_DIMMB <6> DDR_CS2_DIMMB# <6> DDR_CS3_DIMMB# 1 1 2 M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3 <6> M_CLK_DDR#2 <6> M_CLK_DDR2 <6> M_CLK_DDR#3 <6> M_CLK_DDR3 @ C101 0.022U_0402_16V7K C103 0.1U_0402_25V6K 1 CMD Signals from CPU C102 2.2U_0402_6.3V6M DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_RAS# DDR_B_WE# DDR_B_CAS# <6> DDR_B_BS0 <6> DDR_B_BS1 <6> DDR_B_BS2 <6> DDR_B_RAS# <6> DDR_B_WE# <6> DDR_B_CAS# R112 1.8K_0402_1% +SM_VREF_DQ1_DIMM2 1 R113 0_0402_5% 1 2 <6> DDR_B_MA[0..15] SMBUS Signals link to CPU DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D14 DDR_B_D15 DDR_B_D31 DDR_B_D25 Layout Note: Place near JDIMM2 DDR_B_D27 DDR_B_D24 +1.35V 2 @ 1 2 DDR_B_BS2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 +1.35V 2 1 2 C118 10U_0603_6.3V6M 2 1 C117 10U_0603_6.3V6M 2 @ 1 C116 10U_0603_6.3V6M 2 1 C115 10U_0603_6.3V6M 2 1 C114 10U_0603_6.3V6M 2 @ 1 C113 10U_0603_6.3V6M 1 C112 10U_0603_6.3V6M 2 C111 10U_0603_6.3V6M 1 M_CLK_DDR2 M_CLK_DDR#2 DDR_B_MA10 DDR_B_BS0 DDR_B_WE# DDR_B_CAS# DDR_B_MA13 DDR_CS3_DIMMB# DDR_B_DQS#4 DDR_B_DQS4 Layout Note: Place near JDIMM2.203,204 DDR_B_D36 DDR_B_D38 Layout Note: Place near JDIMM2.199 DDR_B_D40 DDR_B_D45 3 +3VS +0.675VS 1 2 1 2 @ 1 2 C127 2.2U_0402_6.3V6M 2 C126 0.1U_0402_25V6K 1 C125 1U_0402_6.3V6K 2 C124 1U_0402_6.3V6K @ 1 C123 0.1U_0402_25V6K 2 C122 0.1U_0402_25V6K @ 1 DDR_B_D43 DDR_B_D42 DDR_B_D52 DDR_B_D49 Address : 01 DDR_B_DQS#6 DDR_B_DQS6 +3VS R116 1 2 0_0402_5% DDR_B_SA1 R117 1 2 0_0402_5% DDR_B_SA0 DDR_B_D50 DDR_B_D53 DDR_B_D63 DDR_B_D62 +0.675VS +3VS DDR_B_D58 DDR_B_D59 DDR_B_SA0 DDR_B_SA1 205 207 GND1 BOSS1 CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT GND2 BOSS2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_B_D22 DDR_B_D16 DDR_B_DQS#2 DDR_B_DQS2 1 DDR_B_D19 DDR_B_D20 DDR_B_D4 DDR_B_D5 DDR3_DRAMRST# DIMM_DRAMRST# DDR_B_D6 DDR_B_D7 1 DDR_B_D13 DDR_B_D9 C104 100P_0402_50V8J 2 @ESD@ DDR_B_D11 DDR_B_D10 <16,5> ESD DDR_B_D30 DDR_B_D26 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D29 DDR_B_D28 +1.35V DDR_CKE3_DIMMB DDR_B_MA15 DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 2 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB# SB_ODT0 SB_ODT1 SB_ODT0 <16> SB_ODT1 <16> +VREF_CA 10mils DDR_B_D33 DDR_B_D34 1 DDR_B_D39 DDR_B_D37 @2 1 2 C121 0.1U_0402_25V6K DDR_B_D32 DDR_B_D35 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS C120 2.2U_0402_6.3V6M 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDR_CKE2_DIMMB C108 1U_0402_6.3V6K 2 1 C107 1U_0402_6.3V6K 2 @ 1 C106 1U_0402_6.3V6K 2 C105 1U_0402_6.3V6K 1 +1.35V VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS DDR_B_D44 DDR_B_D41 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D47 DDR_B_D46 3 DDR_B_D51 DDR_B_D55 DDR_B_D48 DDR_B_D54 DDR_B_D56 DDR_B_D57 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D60 DDR_B_D61 +0.675VS PCH_SMB_DATA PCH_SMB_CLK 206 208 ARGOS_DS2SK-20401-TP4B ME@ SP070014E00 4 4 Interleaved Memory Compal Secret Data Security Classification Issued Date 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: A B C D Compal Electronics, Inc. DDR3L_DIMMB Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 E Sheet 17 of 55 1 2 3 UV1A AF30 AE31 AE29 AD28 <11> PCIE_CTX_GRX_P1 <11> PCIE_CTX_GRX_N1 AD30 AC31 <11> PCIE_CTX_GRX_P2 <11> PCIE_CTX_GRX_N2 AC29 AB28 <11> PCIE_CTX_GRX_P3 <11> PCIE_CTX_GRX_N3 AB30 AA31 AA29 Y28 Y30 W31 W29 V28 B V30 U31 U29 T28 R29 P28 P30 N31 N29 M28 M30 L31 L29 K30 PCIE_RX0P PCIE_RX0N PCIE_TX0P PCIE_TX0N PCIE_RX1P PCIE_RX1N PCIE_TX1P PCIE_TX1N PCIE_RX2P PCIE_RX2N PCIE_TX2P PCIE_TX2N PCIE_RX3P PCIE_RX3N PCIE_TX3P PCIE_TX3N PCIE_RX4P PCIE_RX4N PCIE_TX4P PCIE_TX4N PCIE_RX5P PCIE_RX5N PCIE_TX5P PCIE_TX5N PCIE_RX6P PCIE_RX6N PCIE_TX6P PCIE_TX6N PCIE_RX7P PCIE_RX7N PCIE_TX7P PCIE_TX7N NC#V30 NC#U31 NC#W24 NC#W23 NC#U29 NC#T28 NC#V27 NC#U26 NC#T30 NC#R31 NC#R29 NC#P28 PCI EXPRESS INTERFACE T30 R31 5 AC Coupling Capacitor PCIe Gen3: Recommended value is 220 nF PCIe Gen1 and Gen2 only: Recommended value is 100 nF A <11> PCIE_CTX_GRX_P0 <11> PCIE_CTX_GRX_N0 4 NC#U24 NC#U23 NC#T26 NC#T27 NC#P30 NC#N31 NC#T24 NC#T23 NC#N29 NC#M28 NC#P27 NC#P26 NC#M30 NC#L31 NC#P24 NC#P23 NC#L29 NC#K30 NC#M27 NC#N26 AH30 AG31 PCIE_CRX_GTX_P0_C PCIE_CRX_GTX_N0_C .1U_0402_16V7K .1U_0402_16V7K 2 2 1 PX@ 1 PX@ CV1 CV2 AG29 AF28 PCIE_CRX_GTX_P1_C PCIE_CRX_GTX_N1_C .1U_0402_16V7K .1U_0402_16V7K 2 2 1 PX@ 1 PX@ CV3 CV4 AF27 AF26 PCIE_CRX_GTX_P2_C PCIE_CRX_GTX_N2_C .1U_0402_16V7K .1U_0402_16V7K 2 2 1 PX@ 1 PX@ CV5 CV6 AD27 AD26 PCIE_CRX_GTX_P3_C PCIE_CRX_GTX_N3_C .1U_0402_16V7K .1U_0402_16V7K 2 2 1 PX@ 1 PX@ CV7 CV8 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 <11> <11> PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 <11> <11> PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 <11> <11> PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 <11> <11> AC25 AB25 Y23 Y24 AB27 AB26 Y27 Y26 B W24 W23 V27 U26 U24 U23 No Use GPU Display Port outpud T26 T27 UV1F +VGA_CORE T24 T23 VARY_BL DIGON P27 P26 P24 P23 TXCAP_DPA3P TXCAM_DPA3N TX0P_DPA2P TX0M_DPA2N M27 N26 TX1P_DPA1P TX1M_DPA1N C CLK_PCIE_GPU CLK_PCIE_GPU# <8> CLK_PCIE_GPU <8> CLK_PCIE_GPU# AK30 AK32 CLOCK TX2P_DPA0P TX2M_DPA0N PCIE_REFCLKP PCIE_REFCLKN +0.95VGS NC_TXOUT_L3P NC_TXOUT_L3N +3VGS CALIBRATION PLT_RST# PLT_RST# 2 DGPU_HOLD_RST# 1 B Y A 4 AL27 GPU_RST# 3 1 <9> DGPU_HOLD_RST# N10 2 1K_0402_5% PCIE_CALR_RX AA22 RV1 2 1.69K_0402_1% RV3 1 PX@ 2 1K_0402_1% AB11 AB12 0_0402_5% 0_0402_5% 2 TOPAZ@ TOPAZ@1 RV255 2 TOPAZ@1 TOPAZ@ RV254 FOR TOPAS CORE POWER USE AL15 AK14 AH16 AJ15 AL17 AK16 C AH18 AJ17 AL19 AK18 TMDP TXCBP_DPB3P TXCBM_DPB3N PERSTB TX3P_DPB2P TX3M_DPB2N 216-0856050 A0 JET LE S3 JET@ PX@ RV4 100K_0402_5% TX4P_DPB1P TX4M_DPB1N UV1 SA000079N00 S IC 216-0858020 A0 TOPAZ XT S3 BGA C38 TOPAZ@ 2 MC74VHC1G08DFT2G_SC70-5 TEST_PG 1 PX@ G 35,38,40,9> 1 PX@ Y22 P 5 PCIE_CALR_TX RV2 UV2 PX@ A TX5P_DPB0P TX5M_DPB0N NC_TXOUT_U3P NC_TXOUT_U3N AH20 AJ19 AL21 AK20 AH22 AJ21 AL23 AK22 AK24 AJ23 216-0856050 A0 JET LE S3 JET@ D D Compal Secret Data Security Classification Issued Date 2013/01/11 Deciphered Date 2013/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Compal Electronics, Inc. SUN_PCIE/DP Size Document Number Custom LA-B091P Date: Sheet of Wednesday, February 12, 2014 18 55 Title 5 Rev 1.0 1 2 3 4 5 1 AC6 AC5 33_0402_5%JET@ RV16 4.7K_0402_5% TOPAZ@ 2 0_0402_5% GPU_SVD 2 0_0402_5% GPU_SVC JET@ CV210 10U_0603_6.3V6M 2 1 3.3V TO 1.8V LEVEL SHIF For JET/SUN to support SVI2 reaulator DNI for TOPAZ FB_VDDCI 1 PLL_ANALOG_IN 2 +VGA_CORE NC#J8 1 2 1 RV22 10K_0402_5% +3VGS C 1 4.7K_0402_5% THM_ALERT# RV257 1 TOPAZ@2 0_0402_5% RV258 1 TOPAZ@2 0_0402_5% RV237 1 TOPAZ@2 0_0402_5% RV238 1 TOPAZ@2 0_0402_5% FOR TOPAS CORE POWER USE +3VGS TV22 2 2 1 5.62k 101 3.4k 10k 110 4.75k NC 111 PS_1 @ Capacitor Divider Lookup Lable Y4 W5 Cap (nF) AA3 PLL_ANALOG_OUT Y2 1 PX@ 2 RV17 16.2K_0402_1% 1 1 RV261 1 TOPAZ@2 0_0402_5% 1 PX_EN TV25 GPU_GPIO5 AB13 W8 W9 W7 AD10 AJ9 AL9 AC14 AB16 R AVSSN#AK26 GENERAL PURPOSE I/O GPIO_0 GPIO_1 GPIO_2 SMBDATA SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16 GPIO_17_THERMAL_INT GPIO_18 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21 GPIO_22_ROMCSB GPIO_29 GPIO_30 CLKREQB G AVSSN#AJ25 B AVSSN#AG25 DAC1 HSYNC VSYNC +3VGS AL25 AJ25 @ AH24 AG25 RV371 4.7K_0402_5% @ AH26 AJ27 RSET AVDD AVSSQ VDD1DI VSS1DI AD22 01 PS_2[3:1]=000 10nF 10 PS_2[5:4]=00 NC 11 PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING 2 PS_1[5] STRAP_TX_DEEMPH_EN +1.8VGS Strap Name : PS_2[1] N/A @ RV57 8.45K_0402_1% PS_2[2] N/A PS_2[3] STRAP_BIOS_ROM_EN 2 PX@ CV32 RV373 4.7K_0402_5% 3 1 1 FutureASIC/SEYMOUR/PARK CEC_1 RSVD#AK12 RSVD#AL11 RSVD#AJ11 +1.8VGS PS_3[3:1]=000 PS_3[5:4]=11 PS_2[5] N/A AE23 AD23 Strap Name : X76@ RV21 8.45K_0402_1% OBFF OPTION: reserve by AMD request Pull down for none OBFF design PS_3 AM12 AK12 AL11 AJ11 B PS_2[4] STRAP_BIF_VGA_DIS PX@ RV19 4.75K_0402_1% 2 GPU_WAKEB @ 2N7002K_SOT23-3 QV20 RV372 4.7K_0402_5% PX@ AG24 AE22 PS_1[3] N/A 00 82nF +3VGS AM26 AK26 PS_1[2] TRAP_BIF_CLK_PM_EN PX@ RV14 4.75K_0402_1% PS_2 SCL SDA PS_1[1] STRAP_BIF_GEN3_EN_A Bitd [5:4] 680nF J8 Strap Name : @ RV9 8.45K_0402_1% CV31 W3 V2 2 PS_1[5:4]=11 0402 1% resistors are equired V4 U5 +1.8VGS PS_1[3:1]=000 1 100 3.24k 2 4.99k D GPIO19_CTF 011 4.53k S +1.8VGS RV58 1 @ NC#AA3 NC#Y2 010 4.99k G GPU_PROCHOT# CV17 .1U_0402_16V7K 2 TOPAZ@ RV18 2 PX@ U6 U10 T10 U8 VGA_SMB_DA3 U7 @ VGA_SMB_CK3 2 T9 GPU_GPIO5 DV1 1 <33,35,45> VCIN1_AC_IN T8 GPU_GPIO6 T7 DB2J31400L SOD323-2 GPU_PROCHOT# <51> P10 P4 P2 +VGA_CORE N6 N5 N3 Y9 RV236 1 TOPAZ@2 0_0402_5% N1 GPU_VID3 M4 FOR TOPAS CORE POWER USE 2 0_0402_5% THM_ALERT# RV251 1 PX@ THM_ALERT#_R R6 <32> THM_ALERT# W10 RV252 1 TOPAZ@2 0_0402_5% M2 GPIO19_CTF P8 GPU_VID1 P7 N8 AK10 AM10 1 2 N7 GPUCLK_REQ#_GPU @ <8> GPUCLK_REQ# RV25 0_0402_5% L6 JTAG_TRSTB L5 JTAG_TDI L3 JTAG_TCK 1 2 L1 JTAG_TMS @ +3VGS K4 1 RV26 5.11K_0402_5% JTAG_TDO TV24 K7 1 PX@ 2 TESTEN AF24 RV27 1K_0402_5% +VGA_CORE FOR TOPAS CORE POWER USE RV10 10K_0402_5% TOPAZ@ RV15 1K_0402_5% 1 2 TOPAZ@ RV13 2 10K_0402_5% @ NC#U1 NC#W1 NC#U3 NC#Y6 NC#AA1 +3VGS REAK CURRENT CONTROL ( Topaz only ) 1 DPC 001 2k 6.98k I2C R1 R3 1 NC#W3 NC#V2 NC#Y4 NC#W5 U1 W1 U3 Y6 AA1 B GPU_GPIO6 NC#AA5 NC#AA6 2k 4.53k 1 1 .1U_0402_16V7K JET@ TV18 1 NC#AC5 NC#AC6 8.45k A 2 2 TV23 NC#V4 NC#U5 000 PS_0[5] AUD_PORT_CONN_PINSTRAP[0] 1 CV211 1 RV245 1 @ RV246 1 @ AA5 AA6 RV11 4.7K_0402_5% TOPAZ@ NC#W6 NC#V6 4.75k 2 SVI2_SVD RV242 1 TOPAZ@2 0_0402_5% GPU_SVD SVI2_SVT RV243 1 TOPAZ@2 0_0402_5% GPU_SVT SVI2_SVC RV244 1 TOPAZ@2 0_0402_5% GPU_SVC GPU_SVD <51> GPU_SVT <51> GPU_SVC <51> 1 2 PS_3[2] BOARD_CONFIG[1] (Memory ID) PS_3[4] AUD_PORT_CONN_PINSTRAP[1] X76@ RV24 2K_0402_1% @ PS_3[1] BOARD_CONFIG[0] (Memory ID) PS_3[3] BOARD_CONFIG[2] (Memory ID) 1 JET@ W6 V6 PS_0[4] N/A PX@ RV7 2K_0402_1% 1 +1.8VGS AK8 AL7 2 10K_0402_5% 1 DIR NC#AK8 NC#AL7 AJ7 AH6 PS_0[3] ROM_CONFIG[2] 2 JET@ 33_0402_5% 1 2 GPU_SVD 1 2 GPU_SVC RV134 10K_0402_5% @ 1 1 RV250 2 NC#AJ7 NC#AH6 AK6 AM5 NC 1 2 8 7 RV131 6 RV130 4 GPU_VID3 GPU_VID1 +3VGS DPB @ AK5 AM3 PS_0[2] ROM_CONFIG[1] PS_3[5] AUD_PORT_CONN_PINSTRAP[2] 2 VCCB B1 B2 GND SN74LVC2T45DCTR_SM8 RV135 10K_0402_5% JET@ NC#AK6 NC#AM5 AK3 AK1 CV30 Bitd [3:1] R_pd (ohm) 0.68U_0402_10V VCCA A1 A2 DIR NC#AK5 NC#AM3 FOR TOPAZ,JET/SUN DOESN'T HAVE JET@ 2 2 GPU_VID3 GPU_VID1 1 2 3 5 JET@ 33_0402_5% 2GPU_VID3_GPIO_15 RV247 1 1 2GPU_VID1_GPIO_20 RV92 JET@ 33_0402_5%DIR CV208 .1U_0402_16V7K DVO R_pu (ohm) CV33 0.68U_0402_10V 2 1 UV13 JET@ 2 1 RV256 10K_0402_5% JET@ 1 .1U_0402_16V7K JET@ RV91 10K_0402_5% @ 1 CV209 2 2 2 +1.8VGS NC#AK3 NC#AK1 Resistor Divider Lookup Lable AH3 AH1 2 +3VGS +3VGS 2 +3VGS 1 A NC#AH3 NC#AH1 PS_0 1 VGA_SMB_CK3 QV9B DMN65D8LDW-7 2N SOT363-6 @ DPA AG3 AG5 2 1 <32,35,8> EC_SMB_CK2 4 NC#AG3 NC#AG5 2 3 DBG_DATA16 DBG_DATA15 DBG_DATA14 DBG_DATA13 DBG_DATA12 DBG_DATA11 DBG_DATA10 DBG_DATA9 DBG_DATA8 DBG_DATA7 DBG_DATA6 DBG_DATA5 DBG_DATA4 DBG_DATA3 DBG_DATA2 DBG_DATA1 DBG_DATA0 0.68U_0402_10V N9 L9 AE9 Y11 AE8 AD9 AC10 AD7 AC8 AC7 AB9 AB8 AB7 AB4 AB2 Y8 Y7 PS_0[1] ROM_CONFIG[0] PX@ RV12 8.45K_0402_1% AF2 AF4 0.68U_0402_10V NC#AF2 NC#AF4 VGA_SMB_DA3 1 PS_0[5:4]=11 5 QV9A DMN65D8LDW-7 2N SOT363-6 @ Strap Name : U? 1 1 2 2 2 6 <32,35,8> EC_SMB_DA2 +1.8VGS PS_0[3:1]=001 UV1B RV202 RV203 45.3K_0402_5% 45.3K_0402_5% @ @ 1 1 +3VGS FOR TOPAZ JET/SUN DOESN'T HAVE NATIVE SVI2 JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO TESTEN NC#AF24 GENLK_CLK GENLK_VSYNC AL13 AJ13 C SWAPLOCKA SWAPLOCKB GENERICA GENERICB GENERICC GENERICD GENERICE NC#AJ9 NC#AL9 PS_0 PS_1 PS_2 HPD1 PX_EN PS_3 AG13 AH12 AC19 PS_0 AD19 PS_1 AE17 PS_2 AE20 PS_3 10K_0402_5% JTAG_TDO TS_A DBG_VREFG JTAG_TRSTB JTAG_TDI JTAG_TMS JTAG_TCK DDC2CLK DDC2DATA XTALIN XTALOUT 10K_8P4R_5% RV28 1M_0402_5% NOGCLKDIS@ XTALIN D 4 1 XTALOUT OSC NC 2 10K_0402_5% 2 10K_0402_5% AM28 AK28 AC22 AB22 XTALIN XTALOUT AUX2P AUX2N XO_IN XO_IN2 NC#AD20 NC#AC20 NC#AE16 NC#AD16 YV1 NOGCLKDIS@ 3 NC OSC SEYMOUR/FutureASIC 2 1 RV248 1 RV249 1 <32> REMOTE1+ TO EXTERNAL THERMAL SENSOR <32> REMOTE1+1.8VGS 2 27MHZ 10PF 5YEA27000102IF50Q3 2 CV19 SJ10000GI00 8.2P_0402_50V_NPO NOGCLKDIS@ 1 <41> GPU_XTALIN_GCLK RV29 1 PX@ RV31 1 PX@ CV20 8.2P_0402_50V_NPO NOGCLKDIS@ GPU_XTALIN_GCLK RV253 1GCLKDIS@2 0_0402_5% LV4 1 THERM_D+ T4 THERM_D- T2 Enable MLPS RV33 1 JET@ 13mA 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 1 CV21 1U_0402_6.3V6K PX@ 2 2 10K_0402_5% GPIO28 +TSVDD R5 AD17 AC17 DPLUS DMINUS DDCVGACLK DDCVGADATA THERMAL AE6 AE5 OPTIAN FOR 3.3V tolerance VR, Check with VR vendor AD2 AD4 AC11 AC13 +VGA_CORE RV259 1 TOPAZ@2 0_0402_5% RV260 1 TOPAZ@2 0_0402_5% +1.8VGS FOR TOPAZ CORE POWER USE AD13 AD11 AD20 AC20 RV206 1 TOPAZ@2 0_0402_5% RV209 10K_0402_5% TOPAZ@ FB_GND RV37 1 TOPAZ@2 0_0402_5% FB_VDDC RV51 1 TOPAZ@2 0_0402_5% ONLY AVAILABLE ON TOPAZ, NC BALLS ON JET/SUN GPU_VDD_RUN_FB_L GPU_VDD_SEN <51> <51> AE16 AD16 SVI2_SVD SVI2_SVC +3VGS RV207 1 @ 2 0_0402_5% 2 AUX1P AUX1N 2 1 2 3 4 RPV1 @ 8 7 6 5 RV208 10K_0402_5% @ 1 DDC1CLK DDC1DATA PLL/CLOCK 1 DDC/AUX +3VGS 2 AC16 10K_0402_5% VGA_AC_BATT pull up AE19 2 2 D AC1 AC3 @ RV204 10K_0402_5% GPU_VDD_RUN_FB_L GPU_VDD_SEN RV30 1 RV32 1 2 10_0402_5% 2 10_0402_5% 1 @ 1 RV20 1 TOPAZ@ RV205 10K_0402_5% +VGA_CORE GPIO28_FDO TSVDD TSVSS Compal Secret Data Security Classification 216-0856050 A0 JET LE S3 JET@ Issued Date XTALIN 2013/01/11 Deciphered Date 2013/12/31 Title Date: 1 Compal Electronics, Inc. SUN_MSIC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 3 4 LA-B091P Sheet Wednesday, February 12, 2014 5 Rev 1.0 19 of 55 1 2 3 4 5 +1.35VS to +1.35VGS (6.234A) UV1E +1.35V 2 CV24 CV23 1U_0402_6.3V6K PX@ CV27 0.022U_0402_16V7K PX@ AG15 AG16 AF16 AG17 AG18 AG19 AF14 2 AG20 AG21 AF22 AG22 AD14 +0.95VGS 1 1U_0402_6.3V6K PX@ CV28 QV10A DMN65D8LDW-7 2N SOT363-6 PX@ CV29 4 4 QV10B DMN65D8LDW-7 2N SOT363-6 PX@ 2 1 AG14 AH14 AM14 AM16 AM18 AF23 AG23 AM20 AM22 AM24 AF19 AF20 AE14 2 +1.05VS to +0.95VGS B +1.05VS AF17 +0.95VGS UV15 @ AO4354_SO8 6 @ QV19 2N7002H_SOT23-3 2 2 1 S DP_VDDC#AG20 DP_VDDC#AG21 DP_VDDC#AF22 DP_VDDC#AG22 DP_VDDC#AD14 NC#AF6 NC#AF7 NC#AF8 NC#AF9 DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR NC#AE1 NC#AE3 NC#AG1 NC#AG6 NC#AH5 NC#AF10 NC#AG9 NC#AH8 NC#AM6 NC#AM8 NC#AG7 NC#AG11 DPAB_CALR NC#AE10 AE11 AF11 AE13 AF13 AG8 AG10 AF6 AF7 AF8 AF9 AE1 AE3 AG1 AG6 AH5 AF10 AG9 AH8 AM6 AM8 AG7 AG11 M6 N13 N16 N18 N21 P6 P9 R12 R15 R17 R20 T13 T16 T18 T21 T6 U15 U17 U20 U9 V13 V16 V18 Y10 Y15 Y17 Y20 R11 T11 AA11 M12 N11 V11 AE10 216-0856050 A0 JET LE S3? RV239 10_0603_5% @ 5 DGPU_PWR_EN_1.05VS 1 1 3 @ 1 RV263 2 0_0402_5% <35,48> GPU_1.8VGS_PWR_EN D DGPU_PWR_EN_MOS 2 G NC#AE11 NC#AF11 NC#AE13 NC#AF13 NC#AG8 NC#AG10 DGPU_PWR_EN#_GATE 4 RV61 @ 10K_0402_5% 1 DGPU_PWR_EN_1.05VS @ 1 RV262 2 0_0402_5% 2@ 3 1 4 2@ 1 NC/DP POWER DP_VDDR#AG15 DP_VDDR#AG16 DP_VDDR#AF16 DP_VDDR#AG17 DP_VDDR#AG18 DP_VDDR#AG19 DP_VDDR#AF14 2 2 DGPU_PWR_EN#_GATE_R @ RV241 100K_0402_5% DGPU_PWR_EN 2 1 2 3 CV34 1 8 7 6 5 1U_0402_6.3V6K RV59 200K_0402_5% @ +5VALW 1 CV44 .1U_0402_16V7K B+ U? DP POWER 1 10U_0603_6.3V6M PX@ 3 1 2 1.35VSG_GATE 2 1 .1U_0402_16V7K PX@ 6 RV34 10_0603_5% @ 5 GPU_PWR_EN# RV60 PX@ 2 1 2 PX@ JET@ UV1G CV22 2 PX@ 1 220K_0402_5% 1 GPU_PWR_EN# 1 1U_0402_6.3V6K 1.35VSG_GATE_R 2 PX@ AA27 AB24 AB32 AC24 AC26 AC27 AD25 AD32 AE27 AF32 AG27 AH32 K28 K32 L27 M32 N25 N27 P25 P32 R27 T25 T32 U25 U27 V32 W25 W26 W27 Y25 Y32 No Use GPU Display Port outpud +1.8VGS CV26 1 2 RV35 1M_0402_5% PX@ UV14 PX@ DMN3030LSS-13_SOP8L-8 1 2 3 10U_0603_6.3V6M B+ 8 7 6 5 CV25 .1U_0402_16V7K A 1 JET@ U? +1.35VGS QV22B DMN65D8LDW-7 2N SOT363-6 @ CV35 0.01U_0402_25V7K @ QV22A DMN65D8LDW-7 2N SOT363-6 @ GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VSS_MECH VSS_MECH VSS_MECH A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6 A B A32 AM1 AM32 216-0856050 A0 JET LE? S3 Reserve for GPU Sequence C C +3VS to +3VS_VGA (25mA) +5VALW 2 GPU_PWR_EN# 3 D RV43 PX@ <35,48,51,9> DGPU_PWR_EN <35> GPU_3VGS_PWR_EN PX@ 1 RV264 2 0_0402_5% @ 1 RV265 2 0_0402_5% DGPU_PWR_EN_3V3_MOS 1 D 10K_0402_5% D 3 20K_0402_5% S S 2 G 1 PX@ QV18 2N7002H_SOT23-3 PX@ CV38 .1U_0402_16V7K 2 G @ QV17 2N7002H_SOT23-3 <35,51> GPU_PWR_EN @ 1 RV267 2 0_0402_5% 5 RV41 100K_0402_5% @ 2 DGPU_PWR_EN# 3 RV42 PX@ 1 1 +5VALW DGPU_PWR_EN# QV11B PX@ RV39 470_0603_5% @ 2 DGPU_PWR_EN# QV11A PX@ RV53 470_0603_5% @ 2 RV56 470_0603_5% @ DGPU_PWR_EN# QV21A @ 5 DGPU_PWR_EN# QV21B @ D 2 DGPU_PWR_EN PX@ 1 RV266 2 0_0402_5% Reserve for GPU Sequence Compal Secret Data Security Classification Issued Date 2013/01/11 Deciphered Date 2013/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 2 2 2 @ RV40 470_0603_5% CV37 DMN65D8LDW-7 2N SOT363-6 4 3 1 1 DMN65D8LDW-7 2N SOT363-6 1 6 1 @ 2 2 CV36 4 1 PX@ PX@ RV38 100K_0402_5% 1 1 1U_0402_6.3V6K +0.95VGS +1.8VGS +VGA_CORE 4.7U_0603_6.3V6K 2 QV16 LP2301ALT1G_SOT23-3 PX@ 1 DMN65D8LDW-7 2N SOT363-6 1 6 1 +3VGS 3 DMN65D8LDW-7 2N SOT363-6 +3VS 2 3 4 Compal Electronics, Inc. SUN_Power/GND Size Document Number Custom LA-B091P Date: Sheet of Wednesday, February 12, 2014 20 55 Title 5 Rev 1.0 2 2 2 2 13mA +1.8VGS B 1.5A 5(3@) 5 5 1 0 +3VGS 1U_0402_6.3V6K PX@ VDDR1 25mA 0.1uF 100mA 1 1 0 MPLL_PVDD 130mA 2 1 0 SPLL_PVDD 75mA 0 1 0 (300mA) 0 0 0 1 0 VDDR4 V12 Y12 U12 2 +1.8VGS 1 0 C +DP_VDDC 0 +3VGS VDDR3 10uF 25mA 0 1 1 1uF 1 0 1 2 1 2 1 0.1uF VDDR3 VDDR3 VDDR3 VDDR3 VDDR4 VDDR4 VDDR4 VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC BIF_VDDC BIF_VDDC L8 75mA 2 LV2 1 2 0_0402_5% 1 2 H7 LV3 VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI SPLL_PVDD 100mA 1 2 0_0402_5% +SPLL_VDDC H8 J7 0 1 2 1 2 AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 AA12 M11 N12 U11 1 2 1 2 1 2 1 2 B +VGA_CORE VGA_CORE Cap in power side sheet 21A (VDDC + VDDCI (Merged) - PRO S3 (DDR3)) R21 U21 0.8A +VGA_CORE ISOLATED CORE I/O 1 2 +0.95VGS +PCIE_VDDC: 1A MPLL_PVDD +SPLL_PVDD +0.95VGS 2 +0.95VGS 1 +1.8VGS L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22 1 PLL +MPLL_PVDD 1U_0402_6.3V6K PX@ CV46 1 2 0_0603_5% 10U_0603_6.3V6M PX@ CV42 +DP_VDDR 90mA 1 1U_0402_6.3V6K PX@ CV43 0 LV1 10U_0603_6.3V6M PX@ CV41 13mA 0 1U_0402_6.3V6K PX@ CV40 +TSVDD 13mA 10U_0603_6.3V6M PX@ CV39 VDD_CT CORE POWER PCIE_PVDD 1 1U_0402_6.3V6K PX@ 1uF VDD_CT VDD_CT VDD_CT VDD_CT I/O AA17 AA18 AB17 AB18 .1U_0402_16V7K PX@ CV90 10uF CV56 2 +1.8VGS LEVEL TRANSLATION AA20 AA21 AB20 AB21 0.01uF CV55 +1.35VGS PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC 2 SPLL_VDDC M13 M15 M16 M17 M18 M20 M21 N20 +VDDCI RV234 1 2 0_0402_5% RV235 1 2 0_0402_5% CV62 0.1uF 2 1 C 1 1U_0402_6.3V6K @ 1uF 2 AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26 CV54 10uF 2 AM30 CV52 1 2 1 NC#AB23 NC#AC23 NC#AD24 NC#AE24 NC#AE25 NC#AE26 NC#AF25 NC#AG26 1U_0402_6.3V6K PX@ 1 2 1 PCIE_PVDD VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 CV51 0 2 1 H13 H16 H19 J10 J23 J24 J9 K10 K23 K24 K9 L11 L12 L13 L20 L21 L22 +1.35VGS +PCIE_PVDD: 50mA (PCIE2.0) +1.8VGS 100mA (PCIE3.0) 1U_0402_6.3V6K PX@ 100mA 2 1 .1U_0402_16V7K PX@ CV84 0 2 1 .1U_0402_16V7K PX@ CV86 1(1@) 2 1 .1U_0402_16V7K PX@ CV89 0 2 1 .1U_0402_16V7K PX@ CV82 0.8A 2 1 1U_0402_6.3V6K PX@ CV81 BIF_VDDC 2 1 1U_0402_6.3V6K PX@ CV79 0 1 1U_0402_6.3V6K PX@ CV78 5(1@) 1 1U_0402_6.3V6K PX@ CV77 1 1U_0402_6.3V6K PX@ CV76 1A 1 10U_0603_6.3V6M @ CV87 PCIE_VDDC + @ 1 10U_0603_6.3V6M PX@ CV83 0.1uF 1 10U_0603_6.3V6M @ CV80 1uF 10U_0603_6.3V6M @ CV74 10uF 1 U? MEM I/O 1A 1 JET@ 1U_0402_6.3V6K PX@ 3.5A +0.95VGS SPLL_VDDC UV1D CV48 +1.35VGS 1U_0402_6.3V6K PX@ 3 CV50 4 1U_0402_6.3V6K PX@ 16 TBD CV47 7 A 10U_0603_6.3V6M PX@ 0.1uF CV49 1uF 5 PCIE VDDCI 2.2uF 10U_0603_6.3V6M PX@ CV88 VDDC 10uF 4 .1U_0402_16V7K PX@ CV85 +VGA_CORE 3 220U_B2_2.5VM_R35 CV75 A 2 10U_0603_6.3V6M PX@ 1 2 SPLL_PVSS 1 2 216-0856050 A0 JET LE S3 ? VGA_CORE Cap in power side sheet D D Compal Secret Data Security Classification Issued Date 2013/01/11 Deciphered Date 2013/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Compal Electronics, Inc. SUN_Power Size Document Number Custom LA-B091P Date: Sheet of Wednesday, February 12, 2014 21 55 Title 5 Rev 1.0 1 2 3 4 JET@ UV1C <23,24> M_DA[63..0] <23,24> M_MA[15..0] <23,24> M_DQM[7..0] <23,24> M_DQS[7..0] <23,24> M_DQS#[7..0] GDDR5/DDR3 M_MA[15..0] M_DQM[7..0] M_DQS[7..0] M_DQS#[7..0] 1 +1.35VGS 2 PX@ RV44 40.2_0402_1% 1 B 1 2 PX@ CV65 1U_0402_6.3V6K 2 PX@ RV46 100_0402_1% 1 +1.35VGS 1 2 PX@ RV45 40.2_0402_1% 1 PX@ CV66 1U_0402_6.3V6K 2 2 PX@ RV47 100_0402_1% C RV52 PX@ RV48 49.9_0402_1% 1 2 1 2 M_DA0 M_DA1 M_DA2 M_DA3 M_DA4 M_DA5 M_DA6 M_DA7 M_DA8 M_DA9 M_DA10 M_DA11 M_DA12 M_DA13 M_DA14 M_DA15 M_DA16 M_DA17 M_DA18 M_DA19 M_DA20 M_DA21 M_DA22 M_DA23 M_DA24 M_DA25 M_DA26 M_DA27 M_DA28 M_DA29 M_DA30 M_DA31 M_DA32 M_DA33 M_DA34 M_DA35 M_DA36 M_DA37 M_DA38 M_DA39 M_DA40 M_DA41 M_DA42 M_DA43 M_DA44 M_DA45 M_DA46 M_DA47 M_DA48 M_DA49 M_DA50 M_DA51 M_DA52 M_DA53 M_DA54 M_DA55 M_DA56 M_DA57 M_DA58 M_DA59 M_DA60 M_DA61 M_DA62 M_DA63 K27 J29 H30 H32 G29 F28 F32 F30 C30 F27 A28 C28 E27 G26 D26 F25 A25 C25 E25 D24 E23 F23 D22 F21 E21 D20 F19 A19 D18 F17 A17 C17 E17 D16 F15 A15 D14 F13 A13 C13 E11 A11 C11 F11 A9 C9 F9 D8 E7 A7 C7 F7 A5 E5 C3 E1 G7 G6 G1 G3 J6 J1 J3 J5 +MVREFDA +MVREFSA K26 J26 2 120_0402_1% J25 K25 DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31 DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31 GDDR5/DDR3 MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA0_8/MAA_13 MAA0_9/MAA_15 MAA1_0/MAA_8 MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12 MAA1_5/MAA_BA2 MAA1_6/MAA_BA0 MAA1_7/MAA_BA1 MAA1_8/MAA_14 MAA1_9/RSVD WCKA0_0/DQMA0_0 WCKA0B_0/DQMA0_1 WCKA0_1/DQMA0_2 WCKA0B_1/DQMA0_3 WCKA1_0/DQMA1_0 WCKA1B_0/DQMA1_1 WCKA1_1/DQMA1_2 WCKA1B_1/DQMA1_3 EDCA0_0/QSA0_0 EDCA0_1/QSA0_1 EDCA0_2/QSA0_2 EDCA0_3/QSA0_3 EDCA1_0/QSA1_0 EDCA1_1/QSA1_1 EDCA1_2/QSA1_2 EDCA1_3/QSA1_3 DDBIA0_0/QSA0_0B DDBIA0_1/QSA0_1B DDBIA0_2/QSA0_2B DDBIA0_3/QSA0_3B DDBIA1_0/QSA1_0B DDBIA1_1/QSA1_1B DDBIA1_2/QSA1_2B DDBIA1_3/QSA1_3B MVREFDA MVREFSA NC#J25 MEM_CALRP0 ADBIA0/ODTA0 ADBIA1/ODTA1 CLKA0 CLKA0B CLKA1 CLKA1B RASA0B RASA1B CASA0B CASA1B CSA0B_0 CSA0B_1 CSA1B_0 CSA1B_1 CKEA0 CKEA1 DRST PX@ RV50 5.1K_0402_1% @ CV67 68P_0402_50V8J RV54 RV55 1 @ @ 1 1 2 51.1_0402_1% 2 51.1_0402_1% CV69 @1 @ CV70 @1 @ 2 .1U_0402_16V7K 2 .1U_0402_16V7K L10 K8 L7 Route 50ohms single-ended/100ohm diff and keep short debug only, for clock observation,if not need, DNI. 2 2 PX@ CV68 120P_0402_50V8J 1 PX@ PX@ RV49 10_0402_1% 2 1 1 <23,24> DRAM_RST A U? M_DA[63..0] MEMORY INTERFACE A 5 DRAM_RST WEA0B WEA1B K17 J20 H23 G23 G24 H24 J19 K19 G20 L17 M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA13 M_MA15 J14 K14 J11 J13 H11 G11 J16 L15 G14 L16 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_BA2 M_BA0 M_BA1 M_MA14 E32 E30 A21 C21 E13 D12 E3 F4 M_DQM0 M_DQM1 M_DQM2 M_DQM3 M_DQM4 M_DQM5 M_DQM6 M_DQM7 H28 C27 A23 E19 E15 D10 D6 G5 M_DQS0 M_DQS1 M_DQS2 M_DQS3 M_DQS4 M_DQS5 M_DQS6 M_DQS7 H27 A27 C23 C19 C15 E9 C5 H4 M_DQS#0 M_DQS#1 M_DQS#2 M_DQS#3 M_DQS#4 M_DQS#5 M_DQS#6 M_DQS#7 L18 K16 VRAM_ODT0 VRAM_ODT1 H26 H25 M_CLK0 M_CLK#0 G9 H9 M_CLK1 M_CLK#1 G22 G17 M_RAS#0 M_RAS#1 G19 G16 M_CAS#0 M_CAS#1 H22 J22 M_CS0B#0 M_CS0B#1 G13 K13 M_CS1B#0 M_CS1B#1 K20 J17 M_CKE0 M_CKE1 G25 H10 M_WE#0 M_WE#1 M_BA2 <23,24> M_BA0 <23,24> M_BA1 <23,24> +1.35VGS VRAM_ODT0 <23,24> VRAM_ODT1 <23,24> M_CLK0 <23,24> M_CLK#0 <23,24> M_CLK1 <23,24> M_CLK#1 <23,24> M_RAS#0 <23,24> M_RAS#1 <23,24> M_CAS#0 <23,24> M_CAS#1 <23,24> M_CS0B#0 <23> M_CS0B#1 <24> M_CS1B#0 <23> M_CS1B#1 <24> RV136 RV138 RV140 RV142 RV144 RV146 RV148 RV150 RV152 RV154 RV156 RV158 RV160 RV162 RV164 RV166 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ RV168 RV170 RV172 1 1 1 RV174 RV176 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ 2 100_0402_1% PX@ 2 100_0402_1% PX@ 2 100_0402_1% M_BA0 M_BA1 M_BA2 100_0402_1% 100_0402_1% 100_0402_1% 1 1 1 PX@ 2 RV169 PX@ 2 RV171 PX@ 2 RV173 1 1 PX@ 2 100_0201_1% PX@ 2 100_0201_1% VRAM_ODT0100_0201_1% VRAM_ODT1100_0201_1% 1 1 PX@ 2 RV175 PX@ 2 RV177 RV178 RV180 1 1 PX@ 2 100_0201_1% PX@ 2 100_0201_1% M_RAS#0 M_RAS#1 100_0201_1% 100_0201_1% 1 1 PX@ 2 RV179 PX@ 2 RV181 RV182 RV184 1 1 PX@ 2 100_0201_1% PX@ 2 100_0201_1% M_CAS#0 M_CAS#1 100_0201_1% 100_0201_1% 1 1 PX@ 2 RV183 PX@ 2 RV185 RV186 RV190 1 PX@ 1 PX@ 2 100_0201_1% 2 100_0201_1% M_CS0B#0 100_0201_1% M_CS1B#0 100_0201_1% 1 PX@ 1 PX@ 2 RV187 2 RV191 RV188 RV192 1 PX@ 1 PX@ 2 100_0201_1% 2 100_0201_1% M_CS0B#1 100_0201_1% M_CS1B#1 100_0201_1% 1 PX@ 1 PX@ 2 RV189 2 RV193 RV194 RV196 1 1 PX@ 2 100_0201_1% PX@ 2 100_0201_1% M_CKE0 M_CKE1 100_0201_1% 100_0201_1% 1 1 PX@ 2 RV195 PX@ 2 RV197 RV198 RV200 1 1 PX@ 2 100_0201_1% PX@ 2 100_0201_1% M_WE#0 M_WE#1 100_0201_1% 100_0201_1% 1 1 PX@ 2 RV199 PX@ 2 RV201 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 100_0402_1% 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RV137 RV139 RV141 RV143 RV145 RV147 RV149 RV151 RV153 RV155 RV157 RV159 RV161 RV163 RV165 RV167 B C M_CKE0 <23,24> M_CKE1 <23,24> M_WE#0 <23,24> M_WE#1 <23,24> CLKTESTA CLKTESTB 216-0856050 A0 JET LE S3 ? Place close to GPU (within 25mm) and place componment close to each other D D Compal Secret Data Security Classification Issued Date 2013/01/11 Deciphered Date 2013/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Compal Electronics, Inc. SUN_MEM Size Document Number Custom LA-B091P Date: Sheet of Wednesday, February 12, 2014 22 55 Title 5 Rev 1.0 VREFCA VREFDQ M_DQS[7..0] M_DQS#[7..0] A <22,24> M_BA0 <22,24> M_BA1 <22,24> M_BA2 <22,24> M_CLK0 <22,24> M_CLK#0 <22,24> M_CKE0 <22,24> <22> <22,24> <22,24> <22,24> M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 M_BA0 M_BA1 M_BA2 M2 N8 M3 M_CLK0 M_CLK#0 M_CKE0 J7 K7 K9 B BA0 BA1 BA2 CK CK CKE/CKE0 K1 L2 J3 K3 L3 VRAM_ODT0 M_CS0B#0 M_RAS#0 M_CAS#0 M_WE#0 VRAM_ODT0 M_CS0B#0 M_RAS#0 M_CAS#0 M_WE#0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 M_DQS2 M_DQS0 F3 C7 M_DQM2 M_DQM0 E7 D3 M_DQS#2 M_DQS#0 G3 B7 ODT/ODT0 CS/CS0 RAS CAS WE DQSL DQSU DML DMU DQSL DQSU T2 <22,24> DRAM_RST RESET 1 L8 ZQ/ZQ0 J1 L1 J9 L9 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 2 PX@ RV67 243_0402_1% M_CLK0 RV71 1 2 PX@ 80.6_0402_1% M_CLK#0RV72 1 2 PX@ 80.6_0402_1% UV4 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 M_DA19 M_DA21 M_DA18 M_DA22 M_DA17 M_DA23 M_DA16 M_DA20 D7 C3 C8 C2 A7 A2 B8 A3 M_DA4 M_DA2 M_DA7 M_DA0 M_DA5 M_DA1 M_DA6 M_DA3 VREFCA_UV4 VREFDQ_UV4 2 M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 M_BA0 M_BA1 M_BA2 M2 N8 M3 M_CLK0 M_CLK#0 M_CKE0 J7 K7 K9 +1.35VGS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.35VGS A1 A8 C1 C9 D2 E9 F1 H2 H9 VRAM_ODT0 M_CS0B#0 M_RAS#0 M_CAS#0 M_WE#0 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 K1 L2 J3 K3 L3 M_DQS1 M_DQS3 F3 C7 M_DQM1 M_DQM3 E7 D3 M_DQS#1 M_DQS#3 G3 B7 DRAM_RST T2 L8 B1 B9 D1 D8 E2 E8 F9 G1 G9 PX@ RV68 243_0402_1% 96-BALL SDRAM DDR3 H5TC2G63FFR-11C_FBGA96 X76@ 1 M8 H1 J1 L1 J9 L9 5 UV5 VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 M_DA14 M_DA9 M_DA15 M_DA10 M_DA12 M_DA11 M_DA13 M_DA8 D7 C3 C8 C2 A7 A2 B8 A3 M_DA26 M_DA28 M_DA27 M_DA31 M_DA25 M_DA29 M_DA24 M_DA30 M8 H1 VREFCA_UV5 VREFDQ_UV5 M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 M_BA0 M_BA1 M_BA2 M2 N8 M3 M_CLK1 M_CLK#1 M_CKE1 J7 K7 K9 +1.35VGS BA0 BA1 BA2 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 D9 G7 K2 K8 N1 N9 R1 R9 <22,24> M_CLK1 <22,24> M_CLK#1 <22,24> M_CKE1 +1.35VGS A1 A8 C1 C9 D2 E9 F1 H2 H9 <22,24> <22> <22,24> <22,24> <22,24> VRAM_ODT1 M_CS1B#0 M_RAS#1 M_CAS#1 M_WE#1 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 K1 L2 J3 K3 L3 M_DQS5 M_DQS4 F3 C7 M_DQM5 M_DQM4 E7 D3 M_DQS#5 M_DQS#4 G3 B7 DRAM_RST T2 L8 B1 B9 D1 D8 E2 E8 F9 G1 G9 96-BALL SDRAM DDR3 H5TC2G63FFR-11C_FBGA96 X76@ VRAM_ODT1 M_CS1B#0 M_RAS#1 M_CAS#1 M_WE#1 PX@ RV69 243_0402_1% J1 L1 J9 L9 UV6 VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 M_CLK1 RV75 1 2 PX@ 80.6_0402_1% M_CLK#1RV76 1 2 PX@ 80.6_0402_1% CV143 .01U_0402_16V7-K PX@ E3 F7 F2 F8 H3 H8 G2 H7 M_DA41 M_DA46 M_DA43 M_DA44 M_DA40 M_DA45 M_DA42 M_DA47 D7 C3 C8 C2 A7 A2 B8 A3 M_DA39 M_DA35 M_DA38 M_DA32 M_DA37 M_DA33 M_DA36 M_DA34 M8 H1 VREFCA_UV6 VREFDQ_UV6 M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 M_BA0 M_BA1 M_BA2 M2 N8 M3 M_CLK1 M_CLK#1 M_CKE1 J7 K7 K9 A1 A8 C1 C9 D2 E9 F1 H2 H9 VRAM_ODT1 M_CS1B#0 M_RAS#1 M_CAS#1 M_WE#1 K1 L2 J3 K3 L3 M_DQS7 M_DQS6 F3 C7 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 M_DQM7 M_DQM6 E7 D3 M_DQS#7 M_DQS#6 G3 B7 DRAM_RST T2 +1.35VGS BA0 BA1 BA2 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.35VGS L8 1 M8 H1 1 <22,24> M_DQS#[7..0] VREFCA_UV3 VREFDQ_UV3 M_DQM[7..0] 4 2 <22,24> M_DQS[7..0] UV3 M_MA[15..0] 1 <22,24> M_DQM[7..0] M_DA[63..0] 3 2 <22,24> M_DA[63..0] <22,24> M_MA[15..0] 2 B1 B9 D1 D8 E2 E8 F9 G1 G9 J1 L1 J9 L9 PX@ RV70 243_0402_1% 96-BALL SDRAM DDR3 H5TC2G63FFR-11C_FBGA96 X76@ 1 2 VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 M_DA58 M_DA63 M_DA59 M_DA61 M_DA57 M_DA62 M_DA56 M_DA60 D7 C3 C8 C2 A7 A2 B8 A3 M_DA55 M_DA52 M_DA51 M_DA50 M_DA53 M_DA49 M_DA54 M_DA48 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.35VGS A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 B B1 B9 D1 D8 E2 E8 F9 G1 G9 96-BALL SDRAM DDR3 H5TC2G63FFR-11C_FBGA96 X76@ CV166 .01U_0402_16V7-K PX@ C C 1 1 2 2 2 1 2 1 2 1 2 1 2 1 2 2 2 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 D 2 1 2 1 2 1 CV165 PX@ 1U_0402_6.3V6K 2 1 1 VREFDQ_UV6 1 RV218 4.99K_0402_1% PX@ 2 2 CV228 .1U_0402_16V7K PX@ RV220 4.99K_0402_1% PX@ 2 1 VREFDQ_UV5 1 2 CV229 .1U_0402_16V7K PX@ Compal Secret Data Security Classification Issued Date 2013/01/11 Deciphered Date 2013/12/31 Compal Electronics, Inc. SUN_VRAM A Lower Rev 1.0 LA-B091P of Date: Sheet Wednesday, February 12, 2014 23 55 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D Document Number Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 1 CV164 PX@ 1U_0402_6.3V6K 2 1 CV163 PX@ 1U_0402_6.3V6K 2 1 CV162 PX@ 1U_0402_6.3V6K 2 1 CV161 PX@ 1U_0402_6.3V6K 2 1 CV160 PX@ 1U_0402_6.3V6K 2 2 CV159 PX@ 1U_0402_6.3V6K 1 1 CV158 PX@ 1U_0402_6.3V6K 2 2 1 1 1 2 2 2 1 2 1 CV157 PX@ 1U_0402_6.3V6K 2 2 CV156 PX@ 10U_0603_6.3V6M 1 1 CV155 PX@ 1U_0402_6.3V6K 2 1 CV154 PX@ 1U_0402_6.3V6K 2 1 CV153 PX@ 1U_0402_6.3V6K 2 2 CV142 PX@ 10U_0603_6.3V6M 1 CV141 PX@ 10U_0603_6.3V6M 2 CV140 PX@ 10U_0603_6.3V6M 1 CV139 PX@ 10U_0603_6.3V6M 2 CV152 PX@ 1U_0402_6.3V6K CV227 .1U_0402_16V7K PX@ 2 1 CV151 PX@ 1U_0402_6.3V6K 2 1 CV150 PX@ 1U_0402_6.3V6K 1 1 +1.35VGS CV149 PX@ 1U_0402_6.3V6K RV216 4.99K_0402_1% PX@ CV225 .1U_0402_16V7K PX@ +1.35VGS VREFDQ_UV4 CV226 .1U_0402_16V7K PX@ 2 CV148 PX@ 1U_0402_6.3V6K +1.35VGS RV221 4.99K_0402_1% PX@ 2 2 CV138 @ .1U_0402_16V7K RV213 4.99K_0402_1% PX@ RV219 4.99K_0402_1% PX@ 1 1 CV137 @ .1U_0402_16V7K CV224 .1U_0402_16V7K PX@ RV217 4.99K_0402_1% PX@ RV215 4.99K_0402_1% PX@ 2 CV136 @ .1U_0402_16V7K 2 RV214 4.99K_0402_1% PX@ VREFDQ_UV3 1 CV135 @ .1U_0402_16V7K RV211 4.99K_0402_1% PX@ 1 CV147 PX@ 1U_0402_6.3V6K +1.35VGS 2 CV134 @ .1U_0402_16V7K CV145 .1U_0402_16V7K PX@ 1 CV146 PX@ 1U_0402_6.3V6K +1.35VGS 2 1 CV133 @ .1U_0402_16V7K RV78 4.99K_0402_1% PX@ 2 CV132 @ .1U_0402_16V7K CV144 .1U_0402_16V7K PX@ VREFCA_UV6 1 CV131 @ .1U_0402_16V7K 2 VREFCA_UV5 2 CV130 @ .1U_0402_16V7K VREFCA_UV4 1 1 CV129 @ .1U_0402_16V7K 1 RV212 4.99K_0402_1% PX@ CV128 @ .1U_0402_16V7K VREFCA_UV3 RV210 4.99K_0402_1% PX@ +1.35VGS CV127 @ .1U_0402_16V7K RV74 4.99K_0402_1% PX@ +1.35VGS +1.35VGS CV126 @ .1U_0402_16V7K RV73 4.99K_0402_1% PX@ RV77 4.99K_0402_1% PX@ +1.35VGS 1 +1.35VGS 1 +1.35VGS D A +1.35VGS BA0 BA1 BA2 2 1 2 3 4 5 1 2 3 4 5 M_DA[63..0] <22,23> M_DA[63..0] M_MA[15..0] M_DQS#[7..0] <22,23> M_DQS#[7..0] A <22,23> M_BA0 <22,23> M_BA1 <22,23> M_BA2 <22,23> M_CLK0 <22,23> M_CLK#0 <22,23> M_CKE0 <22,23> <22> <22,23> <22,23> <22,23> VRAM_ODT0 M_CS0B#1 M_RAS#0 M_CAS#0 M_WE#0 B M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 M_BA0 M_BA1 M_BA2 M2 N8 M3 M_CLK0 M_CLK#0 M_CKE0 J7 K7 K9 VRAM_ODT0 M_CS0B#1 M_RAS#0 M_CAS#0 M_WE#0 K1 L2 J3 K3 L3 M_DQS2 M_DQS0 F3 C7 M_DQM2 M_DQM0 E7 D3 M_DQS#2 M_DQS#0 G3 B7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 BA0 BA1 BA2 CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE DQSL DQSU DML DMU DQSL DQSU T2 <22,23> DRAM_RST RESET 1 L8 ZQ/ZQ0 J1 L1 J9 L9 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 2 DR@ RV79 243_0402_1% M_CLK0 RV83 1 2 PX@ 80.6_0402_1% M_CLK#0RV84 1 2 PX@ 80.6_0402_1% 1 2 UV8 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 M_DA21 M_DA19 M_DA22 M_DA18 M_DA20 M_DA16 M_DA23 M_DA17 D7 C3 C8 C2 A7 A2 B8 A3 M_DA2 M_DA4 M_DA0 M_DA7 M_DA3 M_DA6 M_DA1 M_DA5 VREFCA_UV8 VREFDQ_UV8 M8 H1 M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 M_BA0 M_BA1 M_BA2 M2 N8 M3 M_CLK0 M_CLK#0 M_CKE0 J7 K7 K9 +1.35VGS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.35VGS A1 A8 C1 C9 D2 E9 F1 H2 H9 VRAM_ODT0 M_CS0B#1 M_RAS#0 M_CAS#0 M_WE#0 K1 L2 J3 K3 L3 M_DQS1 M_DQS3 F3 C7 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 M_DQM1 M_DQM3 E7 D3 M_DQS#1 M_DQS#3 G3 B7 DRAM_RST T2 L8 B1 B9 D1 D8 E2 E8 F9 G1 G9 J1 L1 J9 L9 DR@ RV80 243_0402_1% 96-BALL SDRAM DDR3 H5TC2G63FFR-11C_FBGA96 @ CV183 .01U_0402_16V7-K PX@ UV9 VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 BA0 BA1 BA2 CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE DQSL DQSU DML DMU DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 M_DA9 M_DA14 M_DA10 M_DA15 M_DA11 M_DA12 M_DA8 M_DA13 D7 C3 C8 C2 A7 A2 B8 A3 M_DA28 M_DA26 M_DA31 M_DA27 M_DA30 M_DA24 M_DA29 M_DA25 VREFCA_UV9 VREFDQ_UV9 M8 H1 M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 M_BA0 M_BA1 M_BA2 M2 N8 M3 M_CLK1 M_CLK#1 M_CKE1 J7 K7 K9 +1.35VGS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 D9 G7 K2 K8 N1 N9 R1 R9 <22,23> M_CLK1 <22,23> M_CLK#1 <22,23> M_CKE1 +1.35VGS A1 A8 C1 C9 D2 E9 F1 H2 H9 <22,23> <22> <22,23> <22,23> <22,23> VRAM_ODT1 M_CS1B#1 M_RAS#1 M_CAS#1 M_WE#1 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 B1 B9 D1 D8 E2 E8 F9 G1 G9 96-BALL SDRAM DDR3 H5TC2G63FFR-11C_FBGA96 @ VRAM_ODT1 M_CS1B#1 M_RAS#1 M_CAS#1 M_WE#1 K1 L2 J3 K3 L3 M_DQS5 M_DQS4 F3 C7 M_DQM5 M_DQM4 E7 D3 M_DQS#5 M_DQS#4 G3 B7 DRAM_RST T2 L8 DR@ RV81 243_0402_1% J1 L1 J9 L9 UV10 VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 DQSL DQSU M_CLK1 RV87 1 2 PX@ 80.6_0402_1% M_CLK#1RV90 1 2 PX@ 80.6_0402_1% 1 2 CV187 .01U_0402_16V7-K PX@ M_DA44 M_DA41 M_DA45 M_DA43 M_DA47 M_DA42 M_DA46 M_DA40 D7 C3 C8 C2 A7 A2 B8 A3 M_DA35 M_DA37 M_DA32 M_DA39 M_DA34 M_DA38 M_DA33 M_DA36 M8 H1 VREFCA_UV10 VREFDQ_UV10 M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 M_BA0 M_BA1 M_BA2 M2 N8 M3 M_CLK1 M_CLK#1 M_CKE1 J7 K7 K9 A1 A8 C1 C9 D2 E9 F1 H2 H9 VRAM_ODT1 M_CS1B#1 M_RAS#1 M_CAS#1 M_WE#1 K1 L2 J3 K3 L3 M_DQS7 M_DQS6 F3 C7 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 M_DQM7 M_DQM6 E7 D3 M_DQS#7 M_DQS#6 G3 B7 DRAM_RST T2 +1.35VGS BA0 BA1 BA2 ODT/ODT0 CS/CS0 RAS CAS WE E3 F7 F2 F8 H3 H8 G2 H7 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.35VGS L8 1 VREFCA VREFDQ B1 B9 D1 D8 E2 E8 F9 G1 G9 J1 L1 J9 L9 DR@ RV82 243_0402_1% VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 96-BALL SDRAM DDR3 H5TC2G63FFR-11C_FBGA96 @ E3 F7 F2 F8 H3 H8 G2 H7 M_DA63 M_DA58 M_DA61 M_DA59 M_DA60 M_DA56 M_DA62 M_DA57 D7 C3 C8 C2 A7 A2 B8 A3 M_DA52 M_DA55 M_DA50 M_DA51 M_DA48 M_DA54 M_DA49 M_DA53 A DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 +1.35VGS BA0 BA1 BA2 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE +1.35VGS A1 A8 C1 C9 D2 E9 F1 H2 H9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 B A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 2 M8 H1 1 VREFCA_UV7 VREFDQ_UV7 1 UV7 M_DQS[7..0] <22,23> M_DQS[7..0] 2 M_DQM[7..0] <22,23> M_DQM[7..0] 2 <22,23> M_MA[15..0] 96-BALL SDRAM DDR3 H5TC2G63FFR-11C_FBGA96 @ C C 1 2 1 2 2 1 1 1 2 2 1 1 2 2 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 VREFDQ_UV10 2 CV233 .1U_0402_16V7K DR@ RV230 4.99K_0402_1% DR@ 2 1 1 2 CV234 .1U_0402_16V7K DR@ Compal Secret Data Security Classification Issued Date 2013/01/11 Deciphered Date 2013/12/31 Compal Electronics, Inc. SUN_VRAM A Upper Rev 1.0 LA-B091P of Date: Sheet Wednesday, February 12, 2014 24 55 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D Document Number Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 1 CV207 DR@ 1U_0402_6.3V6K 1 2 CV206 DR@ 1U_0402_6.3V6K 2 1 CV205 DR@ 1U_0402_6.3V6K 1 2 CV204 DR@ 1U_0402_6.3V6K 2 1 CV203 DR@ 1U_0402_6.3V6K 1 2 CV202 DR@ 1U_0402_6.3V6K 2 1 CV201 DR@ 1U_0402_6.3V6K 1 2 CV200 DR@ 1U_0402_6.3V6K 2 1 CV199 DR@ 1U_0402_6.3V6K 1 2 CV198 DR@ 10U_0603_6.3V6M 2 1 CV184 DR@ 10U_0603_6.3V6M 2 CV182 DR@ 10U_0603_6.3V6M 1 CV181 DR@ 10U_0603_6.3V6M 2 CV180 DR@ 10U_0603_6.3V6M 1 CV179 @ .1U_0402_16V7K 2 CV197 DR@ 1U_0402_6.3V6K RV228 4.99K_0402_1% DR@ 1 CV196 DR@ 1U_0402_6.3V6K CV232 .1U_0402_16V7K DR@ 2 CV195 DR@ 1U_0402_6.3V6K 2 1 CV194 DR@ 1U_0402_6.3V6K RV226 4.99K_0402_1% DR@ 2 CV193 DR@ 1U_0402_6.3V6K CV235 .1U_0402_16V7K DR@ VREFDQ_UV9 1 CV192 DR@ 1U_0402_6.3V6K 2 1 2 CV191 DR@ 1U_0402_6.3V6K RV232 4.99K_0402_1% DR@ VREFDQ_UV8 1 CV190 DR@ 1U_0402_6.3V6K RV231 4.99K_0402_1% DR@ 2 CV189 DR@ 1U_0402_6.3V6K RV229 4.99K_0402_1% DR@ 1 +1.35VGS CV188 DR@ 1U_0402_6.3V6K RV227 4.99K_0402_1% DR@ 1 CV231 .1U_0402_16V7K DR@ +1.35VGS RV233 4.99K_0402_1% DR@ VREFDQ_UV7 2 CV178 @ .1U_0402_16V7K +1.35VGS 1 CV177 @ .1U_0402_16V7K RV224 4.99K_0402_1% DR@ CV176 @ .1U_0402_16V7K 2 CV230 .1U_0402_16V7K DR@ CV175 @ .1U_0402_16V7K +1.35VGS 1 CV174 @ .1U_0402_16V7K RV222 4.99K_0402_1% DR@ CV173 @ .1U_0402_16V7K 2 CV186 .1U_0402_16V7K DR@ +1.35VGS CV172 @ .1U_0402_16V7K 1 +1.35VGS VREFCA_UV10 CV171 @ .1U_0402_16V7K RV89 4.99K_0402_1% DR@ VREFCA_UV9 CV170 @ .1U_0402_16V7K +1.35VGS D VREFCA_UV8 CV169 @ .1U_0402_16V7K 2 CV185 .1U_0402_16V7K DR@ RV225 4.99K_0402_1% DR@ CV168 @ .1U_0402_16V7K 1 RV223 4.99K_0402_1% DR@ CV167 @ .1U_0402_16V7K 1 VREFCA_UV7 +1.35VGS 2 2 RV86 4.99K_0402_1% DR@ 2 RV85 4.99K_0402_1% DR@ RV88 4.99K_0402_1% DR@ +1.35VGS 1 +1.35VGS 1 +1.35VGS 2 3 4 5 D 1 2 3 4 5 A A B B C C D D Compal Secret Data Security Classification Issued Date 2013/01/11 Deciphered Date 2013/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Compal Electronics, Inc. SUN_VRAM A Lower Size Document Number Custom LA-B091P Date: Sheet of Wednesday, February 12, 2014 25 55 Title 5 Rev 1.0 1 2 3 4 5 A A B B C C D D Compal Secret Data Security Classification Issued Date 2013/01/11 Deciphered Date 2013/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Compal Electronics, Inc. SUN_VRAM A Upper Size Document Number Custom LA-B091P Date: Sheet of Wednesday, February 12, 2014 26 55 Title 5 Rev 1.0 5 4 W=60mils LCD Power Circuit +3VS 3 2 Camera +3VS CMOS@ OC 3 Q4 LP2301ALT1G_SOT23-3 W=20mils 3 W=20mils 1 1 G 2 SY6288C20AAC_SOT23-5 D 1 D EN +LCDVDD_CONN S 4 1 2 2 OUT GND C128 IN 4.7U_0603_6.3V6K 5 +3VS_CMOS +LCDVDD_CONN U5 W=60mils 1 2 R119CMOS@ 150K_0402_5% <9> PCH_ENVDD 1 CMOS@ C129 .1U_0402_16V7K 2 C130 @ 10U_0603_6.3V6M D 4.7V 1 <35> CMOS_ON# 1 R120 100K_0402_5% 2 2 C132 CMOS@ .1U_0402_16V7K +3VS 2 B Y 1 A 4 DISPOFF# 2 3 2 <35> BKOFF# P <35,9> ENBKL From EC G From PCH 5 @ U15 R211 100K_0402_5% U74AHC1G08G-AL5-R_SOT353-5 eDP CONN. R124 100K_0402_5% 1 C 1 +LEDVDD R123 1 C B+ R121 0_0805_5% 1 2 2 0_0402_5% 1 2 @ C133 4.7U_0805_25V6-K JLVDS1 R126 1 EDP_HPD_R 1 <9> EDP_HPD 2 0_0402_5% <9> INVPWM DISPOFF# EDP_HPD_R R128 100K_0402_5% W=60mils 2 +LCDVDD_CONN eDP <5> EDP_AUXN <5> EDP_AUXP <5> EDP_TXP0 <5> EDP_TXN0 EMI B <5> EDP_TXP1 <5> EDP_TXN1 R125 2 1 0_0402_5% Reserve T33 for Presence Detect <11> USB20_N5 Camera <11> USB20_P5 4 4 1 @ L6 1 3 2 3 USB20_N5_R 2 USB20_P5_R <11> USB20_N4 Touch Screen <11> USB20_P4 4 4 1 1 2 R270 2 2 0_0402_5% TS_RST# R122 1 1 0_0603_5% +3VS_TS USB20_N5_R USB20_P5_R <39> DMIC_CLK <39> DMIC_DAT +3VS 3 USB20_N4_R 2 USB20_P4_R TS@ C242 .1U_0402_16V7K WCM-2012HS-900T R130 2 EDP_TXP1_C EDP_TXN1_C 2 0_0402_5% USB20_P4_R USB20_N4_R 1 0_0402_5% 3 EDP_TXP0_C EDP_TXN0_C C138 1FHD@ 2 .1U_0402_16V7K C139 1FHD@ 2 .1U_0402_16V7K R293 1 +3VS +3VS_CMOS Camera DMIC @ L7 EDP_AUXN_C EDP_AUXP_C 2 .1U_0402_16V7K 2 .1U_0402_16V7K <10> TS_Detect <10> TS_INT# <10> I2C_1_SDA <10> I2C_1_SCL <35> TS_DISABLE# 1 0_0402_5% R129 2 2 .1U_0402_16V7K 2 .1U_0402_16V7K C136 1 C137 1 Touch Screen WCM-2012HS-900T R127 2 C134 1 C135 1 2 1 1 2 TS@ C243 10U_0603_6.3V6M 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 G1 G2 G3 G4 G5 G6 41 42 43 44 45 46 B E-T_0871K-F40N-00L ME@ SP010011Z00 Close JLVDS1 1 0_0402_5% +3VS_TS R4452 1 2 100K_0402_5% TS_INT# A A Compal Secret Data Security Classification Issued Date 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title LVDS/CAMERA Size C Date: 5 4 3 2 Compal Electronics, Inc. Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 1 Sheet 27 of 55 5 4 3 For NoDocking Near JHDMI1 Near JHDMI1 2 1 EMI L8 C229 0_0402_5% Docking@ C230 0_0402_5% Docking@ <37> HDMI_CLK+_CK C229 1 2 .1U_0402_16V7K HDMI_CLK+_CK_C 1 <37> HDMI_CLK-_CK NoDocking@ 2 .1U_0402_16V7K C230 1 HDMI_CLK-_CK_C 4 C231 0_0402_5% Docking@ C232 0_0402_5% Docking@ <37> HDMI_TX0+_CK C231 1 <37> HDMI_TX0-_CK NoDocking@ 2 .1U_0402_16V7K C232 1 C233 0_0402_5% Docking@ C234 0_0402_5% Docking@ <37> HDMI_TX1+_CK C233 1 2 .1U_0402_16V7K HDMI_TX1+_CK_C 1 <37> HDMI_TX1-_CK NoDocking@ 2 .1U_0402_16V7K C234 1 HDMI_TX1-_CK_C 4 C235 0_0402_5% Docking@ C236 0_0402_5% Docking@ <37> HDMI_TX2+_CK C235 1 2 .1U_0402_16V7K HDMI_TX2+_CK_C 1 <37> HDMI_TX2-_CK NoDocking@ 2 .1U_0402_16V7K C236 1 HDMI_TX2-_CK_C 4 D HDMI@ 1 2 4 3 2 HDMI_CLK+_CONN 3 HDMI_CLK-_CONN +5V_Display U6 For NoDocking +5VS MURATA DLW21HN900HQ2L NoDocking@ L9 2 .1U_0402_16V7K 1 4 HDMI_TX0-_CK_C 1 2 2 HDMI_TX0+_CONN 1 4 3 3 HDMI_TX0-_CONN G L10 HDMI@ HDMI_TX1+_CONN 3 HDMI_TX1-_CONN <37,9> TMDS_B_HPD 3 1 .1U_0402_16V7K 4 3 L11 HDMI@ 1 2 4 3 2 HDMI_TX2+_CONN 3 HDMI_TX2-_CONN JHDMI1 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HDMI_DET <37> HDMI_DET MURATA DLW21HN900HQ2L +5V_Display For Docking HDMIDAT_R HDMICLK_R HDMI_CLK-_CONN HDMI_CLK+_CONN HDMI_TX0-_CONN HDMI_TX0+_CONN HDMI_TX1-_CONN HDMI_TX1+_CONN HDMI_TX2-_CONN HDMI_TX2+_CONN For NoDocking HDMICLK_NB 2 +3VS HDMIDAT_NB Q6A NoDocking@ DMN65D8LDW-7 2N SOT363-6 1 <37,9> HDMICLK_NB 6 R143 10K_0402_5% Docking@ R144 10K_0402_5% Docking@ 4 <37,9> HDMIDAT_NB 45@ HDMI Logo 20 21 22 23 RO0000003HM C For NoDocking HDMICLK_R RP29 5 For Docking ZZZ HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKG1 CK_shield G2 CK+ G3 D0G4 D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ CONCR_099ATAC19NBLCNF ME@ DC232001K00 +3VS R144 1NoDocking@2 2.2K_0402_5% AP2330W-7_SC59-3 For CRT and HDMI C R143 1NoDocking@2 2.2K_0402_5% 2 .1U_0402_16V7K R137 20K_0402_5% NoDocking@ MURATA DLW21HN900HQ2L NoDocking@ 1 2 1 NoDocking@ For NoDocking 2 W=40mils C140 GND 2 2 D 2 S 1 Q5 NoDocking@ 2N7002H_SOT23-3 3 IN C141 R133 1M_0402_5% NoDocking@ MURATA DLW21HN900HQ2L NoDocking@ OUT +3VS HDMI@ 1 2 HDMI_TX0+_CK_C 2 For Docking 1 D 3 5 6 7 8 HDMI_TX1+_CK_C HDMI_TX1-_CK_C HDMI_CLK+_CK_C HDMI_CLK-_CK_C HDMIDAT_R Q6B NoDocking@ DMN65D8LDW-7 2N SOT363-6 4 3 2 1 470 +-5% 8P4R NoDocking@ RP30 B R145 1 HDMI@ 2 2.2K_0402_5% HDMIDAT_R R146 1 HDMI@ 2 2.2K_0402_5% HDMICLK_R 5 6 7 8 HDMI_TX0+_CK_C HDMI_TX0-_CK_C HDMI_TX2+_CK_C HDMI_TX2-_CK_C For Docking +5V_Display <37> HDMICLK_R <37> HDMIDAT_R 4 3 2 1 B 470 +-5% 8P4R NoDocking@ 1 +3VS D ESD 3 S HDMIDAT_R E14@ 9 10 HDMICLK_R 8 HDMI_DET 7 6 D1 HDMIDAT_R HDMI_CLK-_CONN E14@ 9 10 2 HDMICLK_R HDMI_CLK+_CONN 8 4 HDMI_DET HDMI_TX1-_CONN 7 HDMI_TX1+_CONN 6 1 1 9 2 7 4 6 5 5 3 3 8 D2 1 1 HDMI_CLK-_CONN HDMI_TX0+_CONN E14@ 9 10 9 2 2 HDMI_CLK+_CONN HDMI_TX0-_CONN 8 7 4 4 HDMI_TX1-_CONN HDMI_TX2+_CONN 7 6 5 5 HDMI_TX1+_CONN HDMI_TX2-_CONN 6 3 3 1 1 HDMI_TX0+_CONN 9 2 2 HDMI_TX0-_CONN 7 4 4 HDMI_TX2+_CONN 6 5 5 HDMI_TX2-_CONN 3 3 8 L05ESDL5V0NA-4 SLP2510P8 ESD D3 2 G Q7 NoDocking@ 2N7002H_SOT23-3 8 L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title HDMI CONN Size C Document Number 5 4 3 2 Rev 1.0 LA-B091P Date: Wednesday, February 12, 2014 Sheet 1 28 of 55 5 4 +5VS 3 2 1 +5VS_CRT JP1 1 1 2 2 JUMP_43X39 @ +3VS Input Output +1.8VS_CRT +1.8VS_RXVCC JP2 1 RT1 2 @ 1 2 1 CT4 1U_0402_6.3V6K 1 CT3 10U_0603_6.3V6M 2 +1.8VS_CRT CT2 .1U_0402_16V7K 1 CT1 10U_0603_6.3V6M @ 2 +3VS_CRT Output Input +1.8VS_CRT +1.8VS_RXVDD 1 .1U_0402_16V7K 1 .1U_0402_16V7K CPU_DP1_C_P0 CPU_DP1_C_N0 26 27 CT15 CT18 2 2 1 .1U_0402_16V7K 1 .1U_0402_16V7K CPU_DP1_C_P1 CPU_DP1_C_N1 29 30 RT12 2 RT13 2 +3VS_CRT CT16 .1U_0402_16V7K 1 DDI1_AUX_C_DP 1 DDI1_AUX_C_DN 2 2 CT17 .1U_0402_16V7K DDI1_AUX_DP DDI1_AUX_DN 1 100K_0402_5% 1 1M_0402_5% @ @ 1 1 2 Pin.44 2 0_0402_5% Rated current 500mA, DC 0.1ohm Note: Depend on Project, if Vp-p small the 50mV change to 0 ohm Pin.46 IVDD IVDD IVDD IVDD 38 39 12 14 44 46 Pin.14 @ CT11 .1U_0402_16V7K 2 CT10 .1U_0402_16V7K CT9 .1U_0402_16V7K CT8 .1U_0402_16V7K @ CT7 4.7U_0603_6.3V6K 1 45 CT12 2 .1U_0402_16V7K 1 RX0P RX0N +5VS RX1P RX1N MCURSTN ISPSCL ISPSDA 20 19 RXAUXP RXAUXN 18 17 D +5VS_CRT MCUVDDH URDBG 1 1M_0402_5% 1 100K_0402_5% @ @ 2 @ VGADDCCLK VGADDCSDA DCAUXP DCAUXN VSYNC HSYNC 47 RT8 1 Note: ISPSCL/ISPSDA for F/W update 28 15 16 4 3 2 1 ISPSCL_R ISPSDA_R 23 21 3 4 @ CT19 .1U_0402_16V7K 22_0804_8P4R_5% TT1 5 6 7 8 CRT_CLK 1 2 CRT_DATA 2 VSYNC RPT1 VSYNC HSYNC C 2 0_0402_5% 5 2 2 <9> DDI1_AUX_DP <9> DDI1_AUX_DN 2 1 @ A G RT9 2 RT10 2 +3VS_CRT CT13 CT14 IVDDO IVDDO 1 HPD IVDD33 IVDD33 1 2 DDCSCL DDCSDA 40 <5> CPU_DP1_P1 <5> CPU_DP1_N1 1 Pin.12 VGA_HPD <5> CPU_DP1_P0 <5> CPU_DP1_N0 CT6 .1U_0402_16V7K 0_0402_5% 0_0402_5% UT1 2 0_0402_5% 2 2 0_0402_5% Note: Depend on Project, if Vp-p small the 50mV change to 0 ohm +1.8VS_DAC Y 4 CRT_VSYNC_1 RT18 1 2 33_0402_5% CRT_VSYNC_2 UT2 SN74AHCT1G125DCKR_SC70-5 3 2 2 35 36 1 1 1 2 OVDD OVDD RT4 RT5 2 13 48 ISPSDA_R ISPSCL_R 1 CT5 10U_0603_6.3V6M 1 2 C 1 +1.8VS_RXVDD RT3 @ RT7 4.7K_0402_5% RT2 Rated current 500mA, DC 0.1ohm Note: Depend on Project, if Vp-p small the 50mV change to 0 ohm Output +3VS_CRT 1 2 0_0402_5% Rated current 500mA, DC 0.1ohm 1 D RT6 Input +1.8VS_DAC 2 2 P 1 JUMP_43X39 @ OE# 1 <9> DDI1_HPD Output +1.8VS_CRT +3VS_CRT 1 2 IT6513FN +1.8VS_RXVCC 22 PVCC @ CRT_R CRT_G NC/VGADETECT RSET RPT3 VDDA PCSDA PCSCL PWDNB 37 +5VS_CRT RT15 1 XTALIN XTALOUT 41 1 5 2 100_0402_1% RT16 7 6 34 33 6 CRT JCRT1 2 1 1 2 CRT_CLK 1 2 1 2 CRT_HSYNC_2 CRT_B_2 1 2 1 2 1 2 CRT_VSYNC_2 CRT_CLK 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 DT2 CRT_R_2 6 I/O2 VDD GND I/O3 I/O1 16 17 A DC060006H00 E14@ I/O4 G G C-K_80443-5K1-152 ME@ AZC099-04S.R7G_SOT23-6 +5VS_CRT 3 CRT_B_2 1 1 @ CT35 2 18P_0402_50V8J 18P_0402_50V8J I/O1 CRT_B CRT_DATA CRT_G_2 CT33 10P_0402_50V8J I/O3 CRT_DATA CRT_R_2 CT32 10P_0402_50V8J 2 GND @ CT26 10P_0402_50V8J B CT31 10P_0402_50V8J 1 @ CT34 4 VDD 3 CRT_HSYNC_2 1 2 LT1 FCM1608CF-470T07 0603 1 2 LT2 FCM1608CF-470T07 0603 1 2 LT3 FCM1608CF-470T07 0603 1 2 CT30 10P_0402_50V8J CRT_VSYNC_2 I/O2 2 33_0402_5% +5V_Display E14@ I/O4 RT19 1 IT6513FN_QFN48_6X6 CT29 10P_0402_50V8J 5 IN CRT_HSYNC_1 XTALIN_6511 XTALOUT_6511 CT28 10P_0402_50V8J Reserve GND 4 UT3 SN74AHCT1G125DCKR_SC70-5 2 CT27 .1U_0402_16V7K CRT_G DT1 2 Y RPT2 75_0804_8P4R_1% +1.8VS_DAC 1 CRT_R CRT_HSYNC_2 @ YT1 27MHZ 10PF 5YEA27000102IF50Q3 Crystal 3 4 OUT GND A EMI +5VS_CRT XTALIN_6511 P CRT_B 2 10K_0402_5% ESD A 2 PAD PCSDA PCSCL COMP 43 42 49 CRT_DATA CRT_CLK PCSCL PCSDA 8 2 0_0402_5% 2 HSYNC ASPVCC 2.2K_0804_8P4R_5% @ RT17 1M_0402_5% XTALOUT_6511 RT14 1 @ CT23 .1U_0402_16V7K G DVDD18 32 8 7 6 5 11 9 +5VS 1 3 24 +1.8VS_RXVCC 1 2 3 4 2 8 7 6 5 IOGP IOBP +5VS_CRT 1 5 IORP +1.8VS_RXVDD Pin.25 B 10 1 VDDC OE# AVCC AVCC @ CT20 10P_0402_50V8J 1 2 3 4 2 CT25 .1U_0402_16V7K @ CT24 4.7U_0603_6.3V6K 2 1 CT22 .1U_0402_16V7K 1 25 31 1 CT21 1U_0402_6.3V6K 2 +1.8VS_RXVCC 5 CRT_G_2 4 2 Compal Secret Data Security Classification Issued Date 1 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. AZC099-04S.R7G_SOT23-6 Title Size C Date: 5 4 3 2 Compal Electronics, Inc. CRT Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 1 Sheet 29 of 55 A B C D E F G H HDD SATA HDD Conn. Near Connector JHDD1 2 2 0.01U_0402_16V7K 0.01U_0402_16V7K <7> SATA_PTX_DRX_P0 <7> SATA_PTX_DRX_N0 C144 1 C145 1 <7> SATA_PRX_DTX_N0 <7> SATA_PRX_DTX_P0 1 C142 1 C143 SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 SATA_PRX_C_DTX_P0 1 2 3 4 5 6 7 1 +3VS <35> HDD_DETECT# +5VS R141 1 2 0_0805_5% +3V_HDD R280 1 2 0_0402_5% R142 1 2 0_0805_5% +5V_HDD Near HDD 1 C199 .1U_0402_16V7K 1 2 @ C146 1000P_0402_50V7K 1 2 1 C147 .1U_0402_16V7K 2 3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND Reserved GND 12V 12V 12V GND1 GND2 23 24 ALLTO_C166KH-122H9-L ME@ SP011310171 2 ESD C148 10U_0603_6.3V6M 1 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 HDD_DETECT#_R +5V_HDD GND RX+ RXGND TXTX+ GND ODD 2 2 FOR 15" SATA ODD FFC Conn. JODD1 1 2 3 4 5 6 7 8 9 10 <7> SATA_PTX_DRX_P1 <7> SATA_PTX_DRX_N1 <7> SATA_PRX_DTX_N1 <7> SATA_PRX_DTX_P1 SATA_ODD_PRSNT_R +5V_ODD ODD_DA#_R 1 2 3 4 5 6 7 8 9 10 GND GND +5VALW +5VS +5V_ODD NOZODD@ 1 2 0_0805_5% 1 R147 11 12 ACES_88058-100N ME@ SP010016C00 OUT GND IN 3 <10> ODD_EN 1 Q8 LP2301ALT1G_SOT23-3 ZODD@ 2 1 1 2 3 ZODD@ R150 100K_0402_5% 1 2 G 2 D S ZODD@ R149 10K_0402_5% 3 2 C151 E14@ 0.01U_0402_16V7K C152 E14@ 0.01U_0402_16V7K 1 C149 0.01U_0402_16V7K ZODD@ 2 C150 10U_0603_6.3V6M Q9 DRC2124E0L NPN MINI3-G3-B ZODD@ 3 C153 E14@ 0.01U_0402_16V7K C154 E14@ 0.01U_0402_16V7K FOR 14" SATA ODD Conn. Near Connector JODD2 SATA_PTX_DRX_P1 B14@ C151 1 SATA_PTX_DRX_N1 B14@ C152 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P1_14 SATA_PTX_C_DRX_N1_14 SATA_PRX_DTX_N1 B14@ C153 1 SATA_PRX_DTX_P1 B14@ C154 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N1_14 SATA_PRX_C_DTX_P1_14 <7,9> SATA_ODD_PRSNT <10> ODD_DA# R151 1 2 0_0402_5% SATA_ODD_PRSNT_R +5V_ODD R152 1 2 0_0402_5% ODD_DA#_R 1 2 3 4 5 6 7 8 9 10 11 12 13 GND A+ AGND BB+ GND DP +5V +5V MD GND GND GND GND 15 14 ALLTO_C185S1-113H9-L ME@ SP011312061 4 4 Compal Secret Data Security Classification 2011/06/24 Issued Date Deciphered Date 2012/07/12 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HDD/ODD/BT Connector Size C Date: A B C D E F G Compal Electronics, Inc. Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 Sheet 30 H of 55 A B C D E 1 1 NGFF for WLAN / BT(Key E) +3VS Support ISCT(Intel Smart Connect Technology) +3VS_WLAN NOISCT@ 2 0_0805_5% R153 1 ISCT@ Q10 AO3413_SOT23-3 +3VALW +3VS_WLAN <11> PCIE_PTX_C_DRX_P4 <11> PCIE_PTX_C_DRX_N4 WLAN <11> PCIE_PRX_DTX_P4 <11> PCIE_PRX_DTX_N4 <8> CLK_PCIE_WLAN <8> CLK_PCIE_WLAN# For ISCT <8> WLANCLK_REQ# <9> PCH_PCIE_WAKE# <35,38> PCIE_LAN_WAKE# R158 1 R160 1 R162 1 @ 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% WLANCLK_REQ#_R WAKE#_R 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 GND PETP0 PETN0 GND PERP0 PERN0 GND REFCLKP0 REFCLKN0 GND CLKEQ0# PEWAKE0# GND RSRVD/PETP1 RSRVD/PETN1 GND RSRVD/PERP1 RSRVD/PERN1 GND RESERVED RESERVED GND UART_TX UART_CTS UART_RTS RESERVED RESERVED RESERVED COEX3 COEX2 COEX1 SUSCLK PERST0# W_DISABLE2# W_DISABLE1# I2C_DATA I2C_CLK ALERT RESERVED RESERVED RESERVED RESERVED 3.3VAUX 3.3VAUX 2 4 6 8 10 12 14 16 18 20 22 1 1 2 3.3VAUX 3.3VAUX LED1# PCM_CLK PCM_SYNC PCM_IN PCM_OUT LED2# GND UART_WAKE# UART_RX 1 C155 C156 G 2 GND USB_D+ USB_DGND SIDO_CLK SDIO_CMD SDO_DAT0 SDO_DAT1 SDO_DAT2 SDO_DAT3 SDIO_WAKE# SDIO_RESET# D S 3 JWLAN1 1 3 5 7 9 11 13 15 17 19 21 23 <11> USB20_P6 <11> USB20_N6 BT <35> WLAN_PWR_ON# 1 ISCT@ R154 150K_0402_5% 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 SUSCLK_R WL_RST# BT_DISABLE_R R155 1 R156 1 2 0_0402_5% 2 0_0402_5% R157 1 2 0_0402_5% R159 1 R161 1 2 0_0402_5% 2 0_0402_5% 2 2 4.7U_0603_6.3V6K @ 2 .1U_0402_16V7K ISCT@ C157 .1U_0402_16V7K 2 EC_TX <33,35> EC_RX <33,35> SUSCLK <9> WLBT_OFF# <10,9> EC_WL_OFF# <35> Note: The real behavior of BT_DISABLE are BT_DISABLE=LOW, BT=OFF BT_DISABLE=HIGH, BT=ON +3VS_WLAN 68 G 2 3 D 2 2 ISCT@ Q11 2N7002K_SOT23-3 1 WL_RST# 1 1 R507 100K_0402_5% @ R508 100K_0402_5% +3VS ISCT@ R163 100K_0402_5% LCN_DAN05-67306-0102 ME@ SP070013F00 3 2 MTG76 3 PLT_RST# PLT_RST# <18,35,38,40,9> S MTG77 1 69 R164 1NOISCT@ 2 0_0402_5% 4 4 Compal Secret Data Security Classification Issued Date 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size B C D Document Number Rev 1.0 LA-B091P Date: A Compal Electronics, Inc. Mini-Card/NEW Card/SIM Wednesday, February 12, 2014 E Sheet 31 of 55 5 4 3 2 1 3 Channel +3VGS 2 2 +3VS @ R165 0_0402_5% 2 <19> REMOTE1+ C159 2200P_0402_50V7K GPU Near DDR REMOTE2+ REMOTE2- 2 2 B <19> REMOTE1- 2 1 C Q12 MMST3904-7-F_SOT323-3 C161 2200P_0402_50V7K E 3 C160 100P_0402_50V8J 1 1 1 R167 10K_0402_5% @ +3V_Thermal 1 REMOTE1+ 2 REMOTE1- 3 REMOTE2+ 4 REMOTE2- 5 2 2 U7 1 D 1 SMSC thermal sensor placed near JWLAN1 1 1 @ C158 .1U_0402_16V7K +3V_Thermal R166 0_0402_5% VDD SMCLK DP1 SMDATA DN1 ALERT# DP2 THERM# DN2 10 EC_SMB_CK2 9 EC_SMB_DA2 D EC_SMB_CK2 <19,35,8> EC_SMB_DA2 <19,35,8> 8 THM_ALERT# <19> 7 THERM# 6 GND EMC1403-2-AIZL-TR_MSOP10 Address 1001_101xb Placed near U27 REMOTE1,2+/-: Trace width/space:10/10 mil Trace length:<8" 2 Channel +3V_Thermal @ C329 .1U_0402_16V7K C SMSC thermal sensor placed near JWLAN1 2 1 1 @ C251 2200P_0402_50V7K 1 2 C @ U17 REMOTE1+ 2 REMOTE1- 3 THERM# 4 VDD SCLK D+ SDATA D- ALERT# THERM# 8 EC_SMB_CK2 7 EC_SMB_DA2 6 THM_ALERT# 5 GND EMC1402-2-ACZL-TR MSOP 8P Address is 1001100xb H_3P3 H_3P3 H_3P2 FD1 FD2 FD3 FD4 H_3P3 H_3P3 B H_2P0N H19 HOLEA 1 H16 HOLEA 1 H21 HOLEA 1 H11 HOLEA 1 H_2P8X4P8 H20 HOLEA 1 H_2P8X5P1 H7 HOLEA 1 LANGAN H_2P8X4P6 1 ACES_85205-04001 ME@ SP020008X00 H18 HOLEA 1 H6 HOLEA 1 H10 HOLEA 1 2 3 4 G5 G6 1 C162 10U_0603_6.3V6M 1 2 3 4 5 6 1 +FAN 1 2 1 H9 HOLEA JFAN1 1 <35> FAN_SPEED1 0_0603_5% <35> EC_FAN_PWM 1 R168 2 H_2P6X4P0N H_2P6X4P0N H8 HOLEA 1 H_4P0 H24 HOLEA 1 H_4P0 H23 HOLEA 1 H_4P0 H22 HOLEA 1 H_4P0 H13 HOLEA H_2P6N FAN Conn +5VS Battery BD 1 1 H5 HOLEA 1 H15 HOLEA 1 H14 HOLEA 1 H17 HOLEA 1 H3 HOLEA 1 H2 HOLEA NGFF NPTH 1 H1 HOLEA B VGA 1 CPU H_2P5 H_2P5 H_2P8 H_2P8 H_3P3 H_6P0 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Fintek-Thermal IC/FAN/screw Size C Document Number 5 4 3 2 Rev 1.0 LA-B091P Date: Wednesday, February 12, 2014 Sheet 1 32 of 55 KB For B15 KB For B14/E14 JKB2 KSI[0..7] +3VLP 1 2 3 4 @ R274 100K_0402_5% 1 ACES_85205-0400 ME@ PWR_LED# ON/OFF# <35,36> ON/OFF# LID_SW# <35> LID_SW# 7 8 2 D24 D26 MESC5V02BD03 3P C/A SOT23 ESD MESC5V02BD03 3P C/A SOT23 ESD 1 ON/OFF# <33,35> KSO16 <33,35> KSO17 SHORT PADS <35> CAPS_LED# ESD R264 2 B15@ <35> NUM_LED# @ C200 1 R258 1 R259 1 +5VS @ 2 0_0402_5% 2 Power (Green) (E14) For B15/E14 2 0_0402_5% 1 @ C201 @ C202 1 2 @ C203 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 JKB1 KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15 CAPS_LED#_R CAPS_LED# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 E14@ LED1 1 LED2 @ C165 100P_0402_50V8J 8 7 6 5 B15_VCC_B14_R B15_CLK_B14_L B15_DATA_B14_GND 0_0804_8P4R_5% B15@ 1 2 3 4 ESD @ 1 2 .1U_0402_16V7K C167 .1U_0402_16V7K C166 1 TP_L TP_R @ 1 2 3 4 5 6 7 8 RP34 @ESD@ D5 PSOT24C_SOT23-3 Battery (Amber) (B14/B15/E14) JTP1 1 2 3 4 2 2 3 1 2 +3VALW RP34 0_0804_8P4R_5% TP_VCC TP_CLK TP_DATA 1 E14@ R171 1 2 200_0402_5% E14@ RP33 @ C164 100P_0402_50V8J 2 LTST-C190KGKT 0603 GRN SC590KGK020 E14@ <35> TP_CLK <35> TP_DATA 27 28 ACES_88514-02601-071 ME@ SP01000R500 RP33 0_0804_8P4R_5% @ C163 .1U_0402_16V7K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 GND2 GND1 31 32 GND GND PWR_LED# <35> PWR_LED# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ACES_88514-3001 ME@ SP010011A00 1 .1U_0402_16V7K ESD 2 +3VS 1 470_0402_5% NUM_LED#_R .1U_0402_16V7K 2 GND GND ACES_88058-060N ME@ SP010010T00 1 J2 1 2 3 4 5 6 .1U_0402_16V7K SHORT PADS 1 3 2 2 3 J1 1 JPWRB1 1 2 3 4 5 6 .1U_0402_16V7K J11: TOP J12: BOT R170 100K_0402_5% 1 1 2 3 4 +3VALW <31,35> EC_TX <31,35> EC_RX +3VALW 2 +3VALW JP3 2 For Debug KSI1 KSI[0..7] <35> KSI7 KSO[0..17] KSI6 KSO[0..17] <35> KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 +3VS KSO14 R263 KSO11 KSO10 470_0402_5% KSO15 B14@ KSO16 KSO17 1 470_0402_5% CAPS_LED#_R R263 2 B15@ 8 7 6 5 B15_GND_B14_DATA B15_L_B14_CLK B15_R_B14_VCC 1 2 3 4 5 6 1 BATT_LOW_LED# <35> BATT_LOW_LED# 2 R172 1 2 620_0402_5% +3VLP 19-217/S2C-FM2P1VY/3T 0603 ORANGE R173 SC500005T00 200_0402_5% R294 1 @ 2 0_0402_5% E14@ R173 330_0402_5% GND GND B14@ R173 LED3 ACES_88058-060N ME@ SP010010T00 Battery (Green) (B14/B15/E14) BATT_CHG_LED# <35> BATT_CHG_LED# R295 1 2 0_0402_5% 1 2 B15@ 1 2 330_0402_5% +3VLP LTST-C190KGKT 0603 GRN SC590KGK020 0_0804_8P4R_5% B15@ 1 R174 200_0402_5% E14@ R174 330_0402_5% For B14 2 HDD (Green) (B14/B15/E14) RP35 1 2 3 4 TP_VCC TP_CLK TP_DATA B14@ R174 LED4 8 7 6 5 B15_R_B14_VCC B15_L_B14_CLK B15_GND_B14_DATA 1 PCH_SATALED# <7> PCH_SATALED# 2 B15@ 1 2 330_0402_5% +3VS LTST-C190KGKT 0603 GRN SC590KGK020 0_0804_8P4R_5% B14@ DC-In LED (Green) For B14 / E14 RP36 1 2 2 3 3 VCC 1 CLK 2 DAT 3 6 VCC 1 5 CLK 2 4 DAT 3 VCC CLK DAT 1 2 3 1 2 3 4 TP_L TP_R VCC 8 7 6 5 B15_DATA_B14_GND B15_CLK_B14_L B15_VCC_B14_R CLK +3VLP <45> ACPRN# 0_0804_8P4R_5% B14@ R289 1 @ 2 0_0402_5% DC_LED DAT <19,35,45> VCIN1_AC_IN <35,9> AC_PRESENT 4 4 GND 4 L 3 4 GND 4 L 5 5 L 5 R 2 5 L 5 R 6 6 R 6 GND 1 6 R 6 GND R20 1 2 0_0402_5% DC_LED_Power JLED1 1 1 For B14 TP module(84*42) R298 1 R299 1 2 0_0402_5% @ 2 0_0402_5% 1 2 3 4 D 2 G <36> DC_LED Q20 2N7002K_SOT23-3 3 For B15/E14 TP module(100*50) 1 2 3 G1 4 G2 5 6 ACES_51512-0040N-P01 ME@ SP01001J100 S R278 1 +3VALW B15@ 1 R279 2 100K_0402_5% 2 0_0402_5% +VCC_LID L R 1 2 VDD B15@ C248 .1U_0402_16V7K OUTPUT R 4 2 3 1 4 2 3 1 TP_L SW3 SMT1-05_4P B14@ B15@ SW2 SMT1-05_4P 4 2 3 1 TP_L SW2 SMT1-05_4P B14@ 5 6 E14@ SW3 SMT1-05_4P 5 6 B15@ SW1 SMT1-05_4P 5 6 5 6 1 L 2 3 LID_SW# GND ESD 2 1 C198 .1U_0402_16V7K E14@ SW4 SMT1-05_4P 2 B15@ U16 1 B15@ C249 10P_0402_50V8J TCS20DLR SOT-23F 3P 4 2 3 1 TP_R TP_R Compal Secret Data Security Classification Issued Date 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: Compal Electronics, Inc. ROM/KBD/PWR/CR/LED/TP Conn. Document Number Rev 1.0 LA-B091P Friday, February 14, 2014 Sheet 33 of 55 5 4 3 2 1 ESD Finger Print +3VS E14@ U3RXDN1 9 10 D6 1 1 U3RXDN1 E14@ U3RXDN2 9 10 D7 1 1U3RXDN2 U3RXDP1 8 2 2 U3RXDP1 U3RXDP2 8 2 2U3RXDP2 4 4 U3TXDN1 U3TXDN2 7 7 4 4U3TXDN2 5 5 U3TXDP1 U3TXDP2 6 6 5 5U3TXDP2 3 3 3 3 9 U3TXDN1 7 7 U3TXDP1 6 6 9 E14@ U2DP1 3 2 1 JFP1 R291 1 1 2 3 4 5 6 2 0_0402_5% +3VS_FP 3 2 <11> USB20_P7 <11> USB20_N7 Finger Print (For B14/E14/B15) D 7 8 1 1 2 ESD C247 .1U_0402_16V7K D25 MESC5V02BD03 3P C/A SOT23 ESD 8 1 2 3 4 5 6 8 L05ESDL5V0NA-4 SLP2510P8 ESD GND GND I/O4 GND VDD I/O1 I/O3 E14@ 6 U2DP2 5 2 +USB3_VCCA 4 1 U2DN1 AZC099-04S.R7G_SOT23-6 4 1 2 4 USB2@ 3 1 4 <11> USB3_RX2_P 2 4 L13 2 U2DN2 3 U2DP2 2 U3RXDN2 USB20_N2_R 2 2 WCM-2012HS-900T USB20_P2_R 3 2 1 3 L14 4 R169 3 U3RXDP2 1 <11> USB20_P2 1 R178 2 +USB_VCCB <39> HPOUT_R <39> PLUG_IN USB20_N2_R USB20_P2_R Right USB2__I/O Port +5VALW 2A/Active Low 5 4 <35> USB_EN# OUT IN GND EN 1 OCB <35> NOVO# W=80mils 1 2 R179 2 USB_OC1#_U8 1 0_0402_5% 3 1 <11> USB3_TX2_P 14 12 G2 13 11 G1 10 9 8 7 6 5 4 3 2 1 ACES_88058-120N ME@ SP010015H00 C168USB3@ .1U_0402_16V7K 2 U3TXDN2_L 2 WCM-2012HS-900T 1 1 4 U3TXDP2_L 2 4 L15 C169 USB3@ .1U_0402_16V7K USB3@ 3 U3RXDN2 2 U3TXDN2 3 U3TXDP2 WCM-2012HS-900T 1 <11> USB20_N0 4 <11> USB20_P0 1 2 4 3 L16 USB_OC1# + 2 1 2 @ C171 470P_0402_50V7K USB2@ 2 U2DN1 3 U2DP1 2 U3RXDN1 3 U3RXDP1 Left USB CONN Intel_PCH_USB3.0 WCM-2012HS-900T 1 <11> USB3_RX1_N 1 4 <11> USB3_RX1_P 4 2 3 USB3@ +USB3_VCCA W=80mils JUSB2 9 1 8 3 7 2 6 4 5 U3TXDP1 L17 U3TXDN1 U2DP1 +5V_CHGUSB U2DN1 U3RXDP1 2 USB Charger OUT DP_IN DM_IN DM_OUT DP_OUT ILIM_LO ILIM_HI GND T-PAD TPS2544RTER WQFN 16P E14@ 12 10 11 2 3 15 16 14 17 <11> USB3_TX1_P 80mil +USB_VCCB R182 1 @ R184 1 E14@ 2 20K_0402_1% 2 16.5K_0402_1% USB20_N3_U <11> USB20_P3_U <11> Right USB2__I/O Port (For E14) @ 1 1 E14@ + C175 220U_6.3V_M 2 SF000006900 2 @ C176 470P_0402_50V7K E14@ L19 4 1 0_0402_5% 3 Right USB2__I/O Port 3 USB20_P3_R 2 USB20_N3_R NOVO# ESD 1 1 2 @ 1 0_0402_5% W=100mils +5VALW 20 18 G2 19 17 G1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ACES_50505-0184N-001 ME@ SP010010X00 4 1 2 U3TXDN1 3 U3TXDP1 4 3 USB3@ 4 Near End User L18 U10 5 USB_EN# 4 OUT IN GND EN OCB C196 .1U_0402_16V7K 2 3 USB_OC0#_R R185 1 2 0_0402_5% 1 + 2 1 2 @ C177 470P_0402_50V7K A Compal Electronics, Inc. Compal Secret Data 2011/06/24 Deciphered Date 2012/07/12 Title USB3.0/Left USB Ports THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 USB_OC0# <11> SY6288D20AAC_SOT23-5 C178 220U_6.3V_M Issued Date W=80mils 1 Date: 5 U3RXDN1 2 2A/Active Low+USB3_VCCA W=80mils Security Classification @ESD@ D27 MESC5V02BD03 3P C/A SOT23 ESD WCM-2012HS-900T R187 2 1 USB20_N3_C USB20_N2_R USB20_P2_R 2 4 @ 3 USB20_P3_C USB20_N3_R USB20_P3_R Right USB2__I/O Port (For E14) EMI R186 2 WCM-2012HS-900T 1 B Place TX AC coupling Cap (C843~C850). Close to connector JIO2 HPOUT_R PLUG_IN U3TXDP1_L SSTX+ VBUS SSTXD+ GND 10 DGND 11 SSRX+ GND 12 GND GND 13 SSRXGND J-L_TNBNRAC70010009 ME@ DC23300ET10 For E14 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HGNDB HGNDA HPOUT_L 2 C173USB3@ .1U_0402_16V7K USB20_P3_C USB20_N3_C 1 2 E14@ C174 .1U_0402_16V7K 1 <35> USB_CHG_EN# <35> USB_CHG_CTL1 <35> USB_CHG_CTL2 <35> USB_CHG_CTL3 IN STATUS# FAULT# ILIM_SEL EN CTL1 CTL2 CTL3 1 2 U9 1 9 13 4 5 6 7 8 USB_OC1#_U9 2 R131 1 0_0805_5% 2 0_0402_5% C172USB3@ .1U_0402_16V7K 2 U3TXDN1_L +5V_CHGUSB 1 R181 1 1 <11> USB3_TX1_N E14@ R297 10K_0402_5% <35> USB_CHG_STATUS# <10,11> USB_OC1# C Intel_PCH_USB2.0 B +5VALW SSTX+ VBUS SSTXD+ GND 10 DGND 11 SSRX+ GND 12 GND GND 13 SSRXGND J-L_TNBNRAC70010009 ME@ DC23300ET10 Near HDMI CONN. (Debug Port) 1 C170 220U_6.3V_M A JUSB1 9 1 8 3 7 2 6 4 5 SY6288D20AAC_SOT23-5 2 C195 .1U_0402_16V7K +USB_VCCB U8 W=80mils 12 11 10 9 8 7 6 5 4 3 2 1 1 <11> USB3_TX2_N W=80mils <39> HGNDB <39> HGNDA <39> HPOUT_L 1 0_0402_5% @ +USB3_VCCA U2DN2 W=80mils U3TXDP2 U3TXDN2 U2DP2 JIO1 Right USB2__I/O Port USB3@ 3 U2DN2 U3RXDP2 100K_0402_5% @ R275 1 4 <11> USB20_N2 4 +USB3_VCCA For B14 / B15 +3VLP 100K_0402_5% 2 +3VALW 1 0_0402_5% I/O3 Left USB CONN 1 <11> USB3_RX2_N @ VDD I/O1 WCM-2012HS-900T 1 <11> USB20_N1 WCM-2012HS-900T R177 2 GND 6 5 AZC099-04S.R7G_SOT23-6 Intel_PCH_USB3.0 USB2.0_Port I/O4 EMI Intel_PCH_USB2.0 L12 C D9 I/O2 D <11> USB20_P1 EMI 3 L05ESDL5V0NA-4 SLP2510P8 ESD USB3.0_Port ACES_88058-060N ME@ SP010010T00 D8 I/O2 Rev 1.0 Wednesday, February 12, 2014 1 Sheet 34 of 55 +3VLP +3VALW +3VLP R188 1 2 0_0603_5% @ R189 1 2 +3VALW_EC 2 KSI[0..7] <33> KSI[0..7] ESD +3VALW_EC R201 1 2 EC_SMB_CK1 2.2K_0402_5% R202 1 2 EC_SMB_DA1 2.2K_0402_5% <33> KSO16 <33> KSO17 <44,45> <44,45> <19,32,8> <19,32,8> DS3 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 77 78 79 80 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 <9> SUSWARN# <9> SLP_SUS# <9> PCH_PWROK 1 R207 2 10K_0402_5% Share ROM <34> NOVO# <33> NUM_LED# EC_TX EC_RX PCH_PWROK NOVO# PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 GPIO0A GPIO0B GPIO0C GPIO0D EC_INVT_PWM/GPIO11 FAN_SPEED1/GPIO14 EC_PME#/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PCH_PWROK/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A 122 123 <9> PBTN_OUT# <31,38> PCIE_LAN_WAKE# XCLKI/GPIO5D XCLKO/GPIO5E SA000079Y00 S IC NPCE288NA0DX LQFP 128P KBC NPCE288NA0DX LQFP 128P KBC_14X14 1 2 R212 1 2 R281 ADP_ID 68 70 71 72 PS2 Interface CPU1.5V_S3_GATE/GPXIOA00 WOL_EN/GPXIOA01 HDA_SDO/GPXIOA02 VCIN0_PH/GPXIOD00 83 84 85 86 87 88 GPIO Bus GPIO SPIDI/GPIO5B SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A ENBKL/GPIO40 PECI_KB930/GPIO41 FSTCHG/GPIO50 BATT_CHG_LED#/GPIO52 CAPS_LED#/GPIO53 PWR_LED#/GPIO54 BATT_LOW_LED#/GPIO55 SYSON/GPIO56 VR_ON/GPIO57 PM_SLP_S4#/GPIO59 EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04 PROCHOT_IN/GPXIOA05 H_PROCHOT#_EC/GPXIOA06 VCOUT0_PH/GPXIOA07 GPO BKOFF#/GPXIOA08 PBTN_OUT#/GPXIOA09 PCH_APWROK/GPXIOA10 SA_PGOOD/GPXIOA11 R198 1 GPI AC_IN/GPXIOD01 EC_ON/GPXIOD02 ON/OFF/GPXIOD03 LID_SW#/GPXIOD04 SUSP#/GPXIOD05 GPXIOD06 PECI_KB9012/GPXIOD07 V18R 110 112 114 115 116 117 118 124 For GPU <34> +3VS +5VALW @ TP_CLK TP_DATA 2 10K_0402_5% 2 10K_0402_5% +5VS R199 1 TP_CLK TP_DATA R215 1 2 0_0402_5% @ 1.05V_VS_PG_PWR LID_SW# SUSP# NUVOTON_VTT PECI +V18R 1 1 R216 1 2 0_0402_5% @ R209 1 @ 2 4.7K_0402_5% 2 100P_0402_50V8J 2 100P_0402_50V8J 2 @ 4.7K_0402_5% Reserve for +3VGS <20> GPU_1.8VGS_PWR_EN Reserve for +1.8VGS & +0.95VGS <20,48> DS3 PCH_PWR_EN <50> 2 R208 43_0402_1% 2 0_0402_5% +3VALW_EC 2 4.7K_0402_5% R261 1 <9> <42> VCIN1_AC_IN <19,33,45> EC_ON <46> ON/OFF# <33,36> LID_SW# <33> SUSP# <42,47,49,50> EC_ON +3VS DS3 DPWROK_EC EC_RSMRST# <9> GS_SELFTEST <36> VCIN1_ADP_PROCHOT <44> VCOUT1_PROCHOT# <44> VCOUT0_MAIN_PWR_ON <46> BKOFF# <27> BATT_LEN# <44> GPU_3VGS_PWR_EN +5VS 2 4.7K_0402_5% @ VCIN1_BATT_TEMP 1 C189 1 VCIN1_AC_IN C190 1 R203 GS_VOUTX <36> SYS_PWROK <9> WLAN_PWR_ON# <31> BATT_CHG_LED# <33> CAPS_LED# <33> PWR_LED# <33> BATT_LOW_LED# <33> SYSON <42,47> +3VS 2 4.7K_0402_5% @ R260 1 R200 1 EC_SPI_MISO <8> EC_SPI_MOSI <8> EC_SPI_CLK <8> EC_SPI_CS0# <8> BKOFF# 2 10K_0402_5% R194 USB_EN# 1 +3VALW TS_DISABLE# <27> HDD_DETECT# <30> ME_EN <7> VCIN0_PH1 <44> SYSON PM_SLP_S4#_R R310 1 @ GPU_PWR_EN EC_MUTE# <39> USB_EN# <34> PTC_PROTECT <44> CMOS_ON# <27> TP_CLK <33> TP_DATA <33> 119 120 126 128 100 101 102 103 104 105 106 107 108 USB_CHG_STATUS# IMON_CPU <52> SUSACK# <46,9> 97 98 99 109 73 74 89 90 91 92 93 95 121 127 2 0_0402_5% 2 0_0402_5% DS3 Reserve for +5VALW EN GPU_PWR_EN <20,51> DGPU_PWR_EN <20,48,51,9> EC_WL_OFF# <31> SPI Device Interface SPI Flash ROM R309 1 E14@ R308 1 @ <44> ADP_I <44,45> GS_VOUTY <36> ADP_ID <43> ENBKL <27,9> EC_MUTE# EC_MUTE#/GPIO4A USB_EN#/GPIO4B CAP_INT#/GPIO4C EAPD/GPIO4D TP_CLK/GPIO4E TP_DATA/GPIO4F ECAGND +3VALW ESD EC_SMB_CK1/GPIO44 EC_SMB_DA1/GPIO45 SM EC_SMB_CK2/GPIO46 EC_SMB_DA2/GPIO47 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 <9> PM_SLP_S3# <34> USB_CHG_CTL1 <46> 3V/5VALW_PG <34> USB_CHG_EN# <33,9> AC_PRESENT <34> USB_CHG_CTL2 <32> FAN_SPEED1 <44> ADP_65 <31,33> EC_TX <31,33> EC_RX KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 VCIN1_BATT_TEMP IMON_CPU_R VCOUT1_PROCHOT# <52> VR_HOT# R204 1 2 0_0402_5% R205 1 2 0_0402_5% H_PROCHOT# <5> H_PECI <5> VCOUT1_PROCHOT# ESD D S 2 G Q13 2N7002H_SOT23-3 9012@ 2 1 C188 22P_0402_50V8J 63 64 65 66 75 76 VCCST_PWRGD <12> BEEP# <39> EC_FAN_PWM <32> AC_OFF <45> BEEP# EC_FAN_PWM AC_OFF 3 KSO[0..15] DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D IREF/GPIO3E CHGVADJ/GPIO3F DA Output 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 <33> KSO[0..15] CLK_PCI_EC PCIRST#/GPIO05 EC_RST# EC_SCII#/GPIO0E GPIO1D BATT_TEMP/GPIO38 GPIO39 ADP_I/GPIO3A GPIO3B GPIO42 IMON/GPIO43 21 23 26 27 1 2 @ C191 47P_0402_50V8J +3VALW SYSON PCIE_LAN_WAKE# 10K_0402_5% @ESD@ HDD_DETECT# 100K_0402_5% .1U_0402_16V7K C193 1 <10> EC_SCI# <43> ADP_ID_CLOSE EC_RST# EC_SCI# AD Input AGND/AGND C187 .1U_0402_16V7K <8> CK_LPC_KBC PLT_RST# 1 <18,31,38,40,9> 2 47K_0402_5% 2 1 R192 2 +3VALW_EC 12 13 37 20 38 GPIO0F BEEP#/GPIO10 GPIO12 ACOFF/GPIO13 PWM Output 69 @EMI@ @EMI@ 2 1 1 10_0402_1% R190 2 C186 22P_0402_50V8J LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0LPC & MISC GND/GND GND/GND GND/GND GND/GND GND0 EMI 1 2 3 4 5 7 8 10 11 24 35 94 113 <34> USB_CHG_CTL3 <10> KB_RST# <10,9> SERIRQ <8> LPC_FRAME# <8> LPC_AD3 <8> LPC_AD2 <8> LPC_AD1 <8> LPC_AD0 C192 ECAGND U11 4.7U_0603_6.3V6K @ 67 2 EC_VDD/AVCC @ +EC_VCCA 9 22 33 96 111 125 2 1 EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD0 EC_VDD/VCC 2 1 C183 1000P_0402_50V7K @ 1000P_0402_50V7K 1 C182 1000P_0402_50V7K 2 +EC_VCCA C185 1 C181 .1U_0402_16V7K 1 C184 .1U_0402_16V7K 2 ECAGND 1 2 L21 FBM-11-160808-601-T_0603 C180 .1U_0402_16V7K L20 FBM-11-160808-601-T_0603 1 2 1 +3VALW_EC 1@ C179 100P_0402_50V8J 2 0_0603_5% LID_SW# 1 R206 2 100K_0402_5% 1 2 +1.05VS 1 C197 .1U_0402_16V7K R269 2 1 0_0402_5% NUVOTON_VTT 2 R210 1 2 0_0402_5% +3VS 1 P B Y A 4 PM_SLP_S4#_R G 2 3 <9> PM_SLP_S5# 5 @ U14 <9> PM_SLP_S4# +3VS U74AHC1G08G-AL5-R_SOT353-5 1 2 R214 FAN_SPEED1 10K_0402_5% Compal Secret Data Security Classification Issued Date 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Compal Electronics, Inc. BIOS & EC I/O Port Size C Date: Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 Sheet 35 of 55 1 2 3 4 5 To Docking BD +USB_VCCB +3VS A A +3VLP JDOCK1 31 32 33 34 35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 G1 G2 G3 G4 G5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 D1-_Docking D1+_Docking D1-_Docking <37> D1+_Docking <37> D0-_Docking D0+_Docking D0-_Docking <37> D0+_Docking <37> USB3_TX3_N <11> USB3_TX3_P <11> USB3_RX3_N <11> USB3_RX3_P <11> Docking_DP_HPD Docking_DP_HPD <37> DC_LED <33> AUXp_Docking <37> AUXn_Docking <37> Docking_Consumption ON/OFF# <33,35> Docking_PRSNT#_R USB20_P3_D USB20_N3_D <45> Docking@ 2 R227 1 1_0402_5% Docking_PRSNT# <10,37> <11> <11> ACES_50406-03071-001 ME@ SP010015L00 B B APS (G-Sensor) C 1 C RS1 100K_0402_5% GS@ 2 US1 2 <35> GS_SELFTEST +3VS GS@ ST 1 2 GS@ GS@ 1 2 1 2 .1U_0402_16V7K 2 1 CS6 1 GS_VOUTX <35> GS_VOUTY <35> .1U_0402_16V7K COM COM COM COM GS@ 2 56K_0402_5% 2 56K_0402_5% CS5 1 4 9 11 13 16 NC NC NC NC NC NC .1U_0402_16V7K 3 5 6 7 CS4 2 Vs Vs GS@ 1 GS@ 1 GS@ RS2 RS3 .1U_0402_16V7K 1 .1U_0402_16V7K 2 CS2 1 10U_0603_6.3V6M GS@ CS1 0_0603_5% GS@ VOUTX VOUTY CS3 14 15 2 12 10 8 Xout Yout Zout +3VS_GS RS4 GS@ APS_GND LIS34ALTR_LGA16_4X4 APS_GND @ J3 1 2 2MM APS_GND D D Compal Secret Data Security Classification Issued Date 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 1 2 3 4 Compal Electronics, Inc. Docking Document Number LA-B091P Sheet Wednesday, February 12, 2014 36 55 of 5 Rev 1.0 5 4 3 2 +3VS +3VS_DP 1 +3VS_DP JP4 1 2 2 1 CD3 1 CD4 2 2 2 Pin14 DP_Switching +3VS_DP RD3 1 RD21 1 @ @ 2 0_0402_5% 2 0_0402_5% 1 DP_CFG0 DP_Switching I2C_CTL_EN DDC pass through 2 L Docking@ RD1 4.7K_0402_5% Docking@ RD4 4.7K_0402_5% 1 DDC pass through with 40 kohm pull up resistor 2 DDC active buffer M From CPU +3VS_DP CD6 CD7 1 1 2 2 .1U_0402_16V7K .1U_0402_16V7K Docking@ Docking@ CPU_DP2_P0_C CPU_DP2_N0_C 3 4 <5> CPU_DP2_P1 <5> CPU_DP2_N1 CD5 CD8 1 1 2 2 .1U_0402_16V7K .1U_0402_16V7K Docking@ Docking@ CPU_DP2_P1_C CPU_DP2_N1_C 6 7 <5> CPU_DP2_P2 <5> CPU_DP2_N2 CD9 1 CD10 1 2 2 .1U_0402_16V7K .1U_0402_16V7K Docking@ Docking@ CPU_DP2_P2_C CPU_DP2_N2_C 9 10 <5> CPU_DP2_P3 <5> CPU_DP2_N3 CD11 1 CD12 1 2 2 .1U_0402_16V7K .1U_0402_16V7K Docking@ Docking@ CPU_DP2_P3_C CPU_DP2_N3_C 12 13 CD13 1 CD14 1 2 2 .1U_0402_16V7K .1U_0402_16V7K Docking@ Docking@ DDI2_AUX_DP_C DDI2_AUX_DN_C 52 51 TMDS_RT Function H Open drain driver with termination resistors L Standard open drain driver 1 2 1 2 2 no pre-emphasis DP_AUXp_SCL DP_AUXn_SDA DP_HPD DP_CFG1 IN_AUXp IN_AUXn TMDS_CH0p TMDS_CH0n IN_DDC_SCL IN_DDC_SDA TMDS_CH1p TMDS_CH1n IN_CA_DET TMDS_CH2p TMDS_CH2n PEQ 1 DP_MODE 4.7K_0402_5% Docking@ 1 DP_MODE H TMDS_RT TMDS_PRE REXT PD RD6 2 TMDS_SCL TMDS_SDA TMDS_HPD 46 1 1 2 L IN_D1p IN_D1n TMDS_DDCBUF 27 Docking@ RD7 4.7K_0402_5% 3.0dB pre-emphasis DP_D3p DP_D3n CEXT 2 8 DPSW_PEQ Docking@ RD5 4.42K_0402_1% @ RD19 4.7K_0402_5% 1.5dB pre-emphasis M TMDS_DDCBUF +3VS_DP Function H IN_D0p IN_D0n TMDS_CLKp TMDS_CLKn +3VS_DP TMDS_PRE DP_D2p DP_D2n IN_HPD 1 TMDS_PRE DP_CFG0/SCL_CTL SW/SDA_CTL I2C_CTL_EN DP_CA_DET 5 1 Docking@ RD16 4.7K_0402_5% DP_D1p DP_D1n IN_D3p IN_D3n 11 <28,9> TMDS_B_HPD Docking@ CD15 2.2U_0402_6.3V6M @ RD18 4.7K_0402_5% 2 TMDS_RT DP_D0p DP_D0n IN_D2p IN_D2n 50 49 <28,9> HDMICLK_NB <28,9> HDMIDAT_NB 2 1 @ RD15 4.7K_0402_5% VDD33 VDD33 VDD33 VDD33 44 45 38 <5> CPU_DP2_P0 <5> CPU_DP2_N0 <9> DDI2_AUX_DP <9> DDI2_AUX_DN 2 C UD1 14 28 41 56 DP output has higher priority Function H Pin56 +3VS_DP TMDS output has higher priority 1 Docking@ RD17 4.7K_0402_5% TMDS_PRE 1 TMDS_DDCBUF 2 1 @ RD14 4.7K_0402_5% H ＊ L Pin41 Function (For Automatic Switching) @ RD2 4.7K_0402_5% 2 <10,36> Docking_PRSNT# <10,9> PCH_GPIO68 2 +3VS_DP Pin28 D Docking@ 0.01U_0402_16V7K 1 CD2 2 Docking@ .1U_0402_16V7K 1 CD1 Docking@ 0.01U_0402_16V7K JUMP_43X39 @ Docking@ .1U_0402_16V7K D 1 53 GND GND GND Thermal/GND MODE 40 39 D0+_Docking <36> D0-_Docking <36> 37 36 D1+_Docking <36> D1-_Docking <36> 34 33 To DP For Docking 31 30 55 54 32 AUXp_Docking <36> AUXn_Docking <36> Docking_DP_HPD <36> 42 RD20 1Docking@ 2 1M_0402_5% 29 DP_CFG1 19 18 HDMI_TX0+_CK <28> HDMI_TX0-_CK <28> 22 21 HDMI_TX1+_CK <28> HDMI_TX1-_CK <28> 25 24 HDMI_TX2+_CK <28> HDMI_TX2-_CK <28> 16 15 C To HDMI HDMI_CLK+_CK <28> HDMI_CLK-_CK <28> 48 47 HDMICLK_R HDMIDAT_R 17 <28> <28> HDMI_DET <28> 23 20 TMDS_RT TMDS_PRE 26 35 43 57 PS8339BQFN56GTR2-A0_QFN56_7X7 Docking@ Function Automatic Switching Mode, HDMI ID disable ＊M (VDD33/2) Automatic Switching Mode, HDMI ID enable +3VS_DP L Control Switching Mode, HDMI ID disable B 2 B 1 @ RD10 4.7K_0402_5% 2 DPSW_PEQ Function H HEQ, compensate channel loss up to 15dB @ HBR2 M LLEQ, compensate channel loss up to 5dB @ HBR2 L default, LEQ, compensate channel loss up to 12dB @ HBR2 For NoDocking Near UD1.3, 4, 6, 7, 9, 10, 12, 13 For NoDocking Near UD1.15, 16, 18, 19, 21, 22, 24, 25 RP31 CPU_DP2_N1 CPU_DP2_P1 CPU_DP2_N0 CPU_DP2_P0 1 @ RD13 4.7K_0402_5% DPSW_PEQ 1 2 3 4 CPU_DP2_N1_R CPU_DP2_P1_R CPU_DP2_N0_R CPU_DP2_P0_R 1 2 3 4 0_0804_8P4R_5% NoDocking@ From CPU +3VS_DP RP37 8 7 6 5 2 CPU_DP2_N3 CPU_DP2_P3 CPU_DP2_N2 CPU_DP2_P2 1 2 DP_CFG0 RP38 8 7 6 5 CPU_DP2_N3_R CPU_DP2_P3_R CPU_DP2_N2_R CPU_DP2_P2_R 0_0804_8P4R_5% NoDocking@ H automatic EQ disable & AUX interception enable M automatic EQ disable & AUX interception disable, no pre-emphasis, 800mVpp swing L default, automatic EQ enable & AUX interception enable 1 2 3 4 8 7 6 5 HDMI_CLK-_CK HDMI_CLK+_CK HDMI_TX0-_CK HDMI_TX0+_CK 0_0804_8P4R_5% NoDocking@ 1 @ RD11 4.7K_0402_5% Function DP_CFG0 1 2 3 4 HDMI_TX1-_CK HDMI_TX1+_CK HDMI_TX2-_CK HDMI_TX2+_CK 0_0804_8P4R_5% NoDocking@ RP32 @ RD8 4.7K_0402_5% 8 7 6 5 +3VS_DP A 2 A DP_CFG1 2 1 @ RD9 4.7K_0402_5% H auto test enable & input offset cancellation enable M auto test disable & input offset cancellation disable L default, auto test disable & input offset cancellation enable Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 Title HDMI CONN 1 @ RD12 4.7K_0402_5% Function DP_CFG1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size C Document Number 5 4 3 2 Rev 1.0 LA-B091P Date: Wednesday, February 12, 2014 Sheet 1 37 of 55 5 4 +3V_LAN 1 W=60mil 2 0_0603_5% 8111GLDO@ +LAN_VDD LL1 1 2 2.2UH +-5% NLC252018T-2R2J-N SWITCH@ +LAN_SROUT1.05 2 CL1 1U_0402_6.3V6K 1 RL11 2 0_0603_5% 60mil 2 1 1 CL15 .1U_0402_16V7K 8111GLDO@ D W=60mils 1 CL16 2 SWITCH@ 2 1 .1U_0402_16V7K RL18 1 4.7U_0603_6.3V6K +3VALW 3 CL17 SWITCH@ 2 D LL1, CL16, and CL17 close to Pin24 ( Should be place within 200 mils ) RJ-45 CONN. +3V_LAN JLAN1 +LAN_VDD 2 2 2 @ CL21 2 2 CL10 1 2 CL4 2 Pin3 Close to Pin23 C CL5 2 Pin8 1 CL6 2 Pin22 1 CL7 2 Pin30 2 510_0402_5% 12 11 1 CL8 1 1 1 RL15 2 1U_0402_6.3V6K @ CL20 1 SWITCH@ CL3 1 4.7U_0603_6.3V6K CL2 CL9 4.7U_0603_6.3V6K 1 .1U_0402_16V7K 1 .1U_0402_16V7K 0_0603_5% 1 .1U_0402_16V7K 2+LAN_VDDREG .1U_0402_16V7K W=60mils .1U_0402_16V7K 1 +3V_LAN .1U_0402_16V7K RL1 .1U_0402_16V7K +3V_LAN LED0 W=40mils 4.7U_0603_6.3V6K Rising Ame (10%~90%)要 要>1mS and <100mS Pin22 +3V_LAN 1 LED2 RL16 CL2 close to Pin 11, only 8106E LDO mode unpop CL3 close to Pin 32 RJ45_TX3- 8 RJ45_TX3+ 7 RJ45_RX1- 6 RJ45_TX2- 5 RJ45_TX2+ 4 RJ45_RX1+ 3 RJ45_TX0- 2 RJ45_TX0+ 1 10 2 510_0402_5% 9 Yellow LEDYellow LED+ PR4PR4+ PR2PR3PR3+ PR2+ C PR1SHLD2 SHLD1 PR1+ 13 14 Green LEDGreen LED+ SANTA_130452-0P ME@ DC234007O00 LANGAN1 +LAN_VDD LANGAN +LAN_VDD +3VS LAN_MDIP1 LAN_MDIN1 LAN_MDIP2 LAN_MDIN2 EMI RL4 1 2 0.1U_0402_25V6K RL5 1 2 0.1U_0402_25V6K LAN_MDIP3 LAN_MDIN3 +3V_LAN <8> LANCLK_REQ# <11> PCIE_PTX_C_DRX_P3 <11> PCIE_PTX_C_DRX_N3 <8> CLK_PCIE_LAN <8> CLK_PCIE_LAN# LANGAN B @EMI@ RL6 1 2 0.1U_0402_25V6K @EMI@ RL7 1 2 0.1U_0402_25V6K MDIP0 MDIN0 AVDD10 MDIP1 MDIN1 MDIP2 MDIN2 AVDD10 MDIP3 MDIN3 AVDD33 CLKREQB HSIP HSIN REFCLK_P REFCLK_N HSOP HSON PERSTB ISOLATEB LANWAKEB DVDD10 VDDREG REGOUT LED2 LED1/GPIO LED0 CKXTAL1 CKXTAL2 AVDD10 RSET AVDD33 GND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 PCIE_PRX_DTX_P3_C PCIE_PRX_DTX_N3_C PLT_RST_BUF# ISOLATE# PCIE_LAN_WAKE# 1 CL11 1 CL12 PLT_RST# <18,31,35,40,9> PCIE_LAN_WAKE# .1U_0402_16V7K 2 PCIE_PRX_DTX_P3 <11> .1U_0402_16V7K PCIE_PRX_DTX_N3 <11> +3V_LAN 1 RL17 LED1_GPIO @ 2 10K_0402_5% RL10 15K_0402_5% TPL2 reserved GPIO pin 2.49K_0402_1% 2 1 RL9 +3V_LAN UL2 SA00006N910 S IC RTL8106EUL-CG QFN 32P E-LAN CTRL 8106ESW@ B UL2 RTL8111GS-CG_QFN32_4X4 SA00005O700 S IC RTL8111GS-CG QFN 32P E-LAN CTRL 8111GLDO@ EMI TL1 UL2 SA00006ML10 S IC RTL8111GUL-CG QFN 32P E-LAN CTRL 8111GSW@ CL13 2 CL18 1 2 EMI 0.01U_0402_16V7K NC 4 OSC OSC 2 NC 1 XTLO EMI YL1 25MHZ_10PF_7V25000014 NOGCLK@ SJ10000E800 @ DL1 LAN_MDIN3 1 I/O1 2 I/O3 GND VDD I/O2 I/O4 4 2 XTLI LAN_MDIP3 10P_0402_50V8J NOGCLK@ 3 DL1 Only For GIGA 1 LAN_MDIP3 2 LAN_MDIN3 3 +V_DAC 4 LAN_MDIP2 5 LAN_MDIN2 6 +V_DAC 7 LAN_MDIP1 8 5 LAN_MDIN1 CL14 1 +V_DAC LAN_MDIP2 3 1 6 AZC099-04S.R7G_SOT23-6 SC300001G00 RG6 1 GCLK@ 2 0_0402_5% @ DL2 XTLI LAN_MDIN1 1 A I/O1 I/O3 GND VDD I/O2 I/O4 4 9 +V_DAC 10 LAN_MDIP0 11 LAN_MDIN0 12 LAN_MDIN2 GCLK <41> LAN_XTLI_GCLK ISOLATE# UL2 SA000065Y00 S IC RTL8106E-CG QFN 32P E-LAN CTRL 8106ELDO@ LANGAN1 10P_0402_50V8J NOGCLK@ RL8 1K_0402_5% <31,35> +LAN_VDDREG +LAN_SROUT1.05 LED2 TPL1 LED0 XTLO XTLI 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 LAN_MDIP0 LAN_MDIN0 TL1 S0 X'FORM_ HH-065 10/100 100@ LAN_MDIP0 TCT1 TD1+ MCT1 MX1+ TD1- MX1- TCT2 MCT2 TD2 MX2+ TD2- MX2- TCT3 MCT3 TD3+ MX3+ TD3- MX3- TCT4 MCT4 TD4+ MX4+ TD4- MX4- 24 MCT RL19 23 RJ45_TX3+ 1 22 RJ45_TX3- 75_0805_5% CL19 1 2 2 10P_0603_50V 21 LANGAN 20 RJ45_TX2+ 19 RJ45_TX2- 18 2 17 RJ45_RX1+ 16 RJ45_RX1- 15 14 RJ45_TX0+ 13 RJ45_TX0- 1 DL3 BS4200N-C-LV_SMB-F2 EMI NS892407 GIGA@ A FOR 10/100 data transferring 2013/08/27 2 LAN_MDIP1 3 5 6 LAN_MDIN0 AZC099-04S.R7G_SOT23-6 SC300001G00 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title LAN RTL8411-CG Size C Date: 5 4 3 2 Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 1 Sheet 38 of 55 B C D E +3VS +3VDD_CODEC +IOVDD_CODEC +3V_PCH RA2 RA3 2 +5VS_PVDD 1 +3VDD_CODEC RA7 External DMIC EMI <27> DMIC_DAT <27> DMIC_CLK LA1 RA8 1 1 2 BLM15BB221SN1D_2P 2 10K_0402_5% @ DMIC_CLK_R RA11 1 <35> EC_MUTE# <7> HDA_RST_AUDIO# 31 30 +LINE1-VREFO-R 2 0_0402_5% PC_BEEP 2 PLUG_IN_R CA15 2 1 1U_0402_6.3V6K CA17 +3VLP 2 12 13 14 37 35 1 4.7U_0603_6.3V6K 233VB@ RA161 2 100K_0402_5% CA19 2 RA18 1 47 11 36 @ +3VDD_CODEC 2 3 1 2.2U_0402_6.3V6M @ 2 0_0402_5% RA18 pop on ALC283, NC on ALC233 20 19 4 49 SPK-OUT-LSPK-OUT-L+ SPK-OUT-R+ SPK-OUT-R- GPIO0/DMIC-DATA GPIO1/DMIC-CLK PDB RESETB ALC233-CG HPOUT-L(PORT-I-L) HPOUT-R(PORT-I-R) SYNC BCLK SPK_L1SPK_L2+ SPK_R2+ SPK_R1- 32 33 HP_OUTL HP_OUTR PCBEEP MONO-OUT SENSE A SENSE B MIC2-VREFO LDO3-CAP LDO2-CAP LDO1-CAP 5 8 VREF CPVREF JDREF CPVEE HDA_RST_AUDIO# Headphone 10 6 HDA_SYNC_AUDIO <7> HDA_BITCLK_AUDIO <7> HDA_SDIN0_AUDIO RA12 1 @EMI@ CA12 EMI HDA_SDOUT_AUDIO HDA_SDIN0 <7> AVSS1 AVSS2 <7> 3 2 0_0402_5% RA24 1 2 0_0402_5% RA25 1 2 0_0402_5% CA6 CA5 1 2 233@ QA1A DMN65D8LDW-7 2N SOT363-6 +3VS 16 29 7 39 27 LDO3 LDO2 LDO1 28 15 34 CA13 2 1 2.2U_0402_6.3V6M 2 CA14 2 1 2.2U_0402_6.3V6M CA16 2 1 2.2U_0402_6.3V6M 2 RA15 CA18 1 JDREF CPVEE RA17 1 233VB@ RA38 100K_0402_5% 25 38 1 1 RA39 1 100K_0402_5% 233@ 2 20K_0402_1% W=40mils W=40mils CA20 1U_0402_6.3V6K 2 0_0402_5% RA13 1 233@ RA13 200K_0402_5% 233VB@ RA19 2 RA20 2 RA22 1 RA23 1 PLUG_IN_R 2 1U_0402_6.3V6K EXT_MIC_SLEEVE EXT_MIC_RING2 HP_OUTL HP_OUTR Combo Jack (Normal Open) 2 39.2K_0402_1% PLUG_IN PLUG_IN EMI 1 1 2 2 HGNDB HGNDA HPOUT_L HPOUT_R FCM1608CF-121T03 0603 FCM1608CF-121T03 0603 47_0402_5% 47_0402_5% <34> HGNDB <34> HGNDA <34> HPOUT_L <34> HPOUT_R <34> For Universal Audio Jack UA1 ALC233-VB2-CG MQFN 48P 233VB@ RA21 1 2 For ALC233VB only ALC233-CG_MQFN48_6X6 233@ EMI 233@ QA1B DMN65D8LDW-7 2N SOT363-6 +MIC2-VREFO 2 DVSS Thermal PAD 233@ RA14 1 10K_0402_5% KABINI need to use this part Due to RST is 1.5V power rail Intel project can use dual 2N7002 22P_0402_50V8J 2 33_0402_5% 48 CPVDD MIC-CAP 5 RA101 @EMI@ 2 33_0402_5% SDATA-OUT SDATA-IN SPDIF-OUT/GPIO2 CBP CBN 43 42 45 44 EXT_MIC_SLEEVE 2 26 46 40 AVDD2 AVDD1 PVDD2 1 41 PVDD1 233@ RA9 100K_0402_5% MIC2-L(PORT-F-L) /RING2 MIC2-R(PORT-F-R) /SLEEVE LINE1-VREFO-L LINE1-VREFO-R +3VLP Place near Pin26 4 17 18 2 LINE1-L CA21 2 1 1U_0402_6.3V6K LINE1-R CA22 2 1 1U_0402_6.3V6K RA29 1 2 4.7K_0402_5% RA32 1 2 4.7K_0402_5% 2 EXT_MIC_RING2 EXT_MIC_SLEEVE 2 Place near Pin40 2 2 2.2K_0402_5% 2 2.2K_0402_5% LINE2-L(PORT-E-L) LINE2-R(PORT-E-R) 2 1U_0402_6.3V6K 0_0603_5% Place RA41 on AGND/DGND moat 1 1 RA6 1 1 +MIC2-VREFO LINE1-L(PORT-C-L) LINE1-R(PORT-C-R) 1 1 6 24 23 DVDD-IO DVDD wide 40MIL 22 21 9 CA8 2 0_0402_5% RA27 220P_0402_50V7K 1 RA5 2 3 +1.5VS LINE1-L LINE1-R 1 RA4 +IOVDD_CODEC UA1 Place near Pin9 +5VS 1 2 +5VDDA_CODEC 1 2 2 Place near Pin1 CA11 1U_0402_6.3V6K 1 1 CA7 .1U_0402_16V7K 1 1 .1U_0402_16V7K CA1 2 2 0_0603_5% RA26 220P_0402_50V7K 1 2 2 0_0805_5% .1U_0402_16V7K CA3 1 4.7U_0603_6.3V6K CA2 RA1 2 CA4 +5VS 1 .1U_0402_16V7K 1 1 1U_0402_6.3V6K 2 0_0603_5% .1U_0402_16V7K 1 1 A +LINE1-VREFO-R 3 RA28 1 @EMI@ 2 0_0402_5% GND GNDA 11/20 Change symbol of JSPK1 to SP02000H700 EMI wide 40MIL JSPK1 <10> HDA_SPKR 2 .1U_0402_16V7K 1 RA34 CA24 1 2 CA25 1 2 1K_0402_5% LA6 0_0603_5% PC_BEEP 2 .1U_0402_16V7K LA7 0_0603_5% .1U_0402_16V7K 1 2 3 4 5 6 SPK_R1-_CONN SPK_R2+_CONN SPK_L1-_CONN SPK_L2+_CONN 1 2 LA8 0_0603_5% 1 2 1 2 1 2 ESD ACES_85205-04001 ME@ SP020008X00 +5VS @ESD@ SPK_R1-_CONN 1 2 3 4 G5 G6 6 DA3 I/O4 I/O2 VDD GND 3 SPK_L2+_CONN 1 EC Beep PCH Beep CA23 1 FCM1608CF-121T03 0603 FCM1608CF-121T03 0603 FCM1608CF-121T03 0603 FCM1608CF-121T03 0603 CA28 LA5 0_0603_5% <35> BEEP# 2 2 2 2 1000P_0402_50V7K 1 1 1 1 1000P_0402_50V7K CA31 LA5 LA6 LA7 LA8 1000P_0402_50V7K CA30 @EMI@ @EMI@ @EMI@ @EMI@ 1000P_0402_50V7K CA29 SPK_R1SPK_R2+ SPK_L1SPK_L2+ PC Beep @ RA36 10K_0402_5% 5 2 4 2 4 SPK_R2+_CONN 4 I/O3 I/O1 1 SPK_L1-_CONN AZC099-04S.R7G_SOT23-6 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title HD Audio Codec_ALC3225 Size C Date: A B C D Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 E Sheet 39 of 55 5 4 3 2 1 D D +AV12 2 +DV12S CC2 1 CC3 2 +3VS 1 2 CC4 .1U_0402_16V7K 2 1 4.7U_0603_6.3V6K 1 .1U_0402_16V7K 4.7U_0603_6.3V6K CC1 CC5 1 2 4.7U_0603_6.3V6K CC6 1 2 .1U_0402_16V7K UCR1 +Card_3V3 LC1 1 +Card_3V3 2 0_0603_5% +DV33_18 +AV12 +DV12S 9 15 7 11 +Card_3V3_R 10 1 RC1 2 6.2K_0402_1% 8 3V3_IN DV33_18 AV12 DV12_S Card_3V3 GND 25 Close to UCR1 RREF RC2 <11> <11> <11> <11> C PCIE_PTX_C_DRX_P2 PCIE_PTX_C_DRX_N2 PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N2 CC7 CC8 1 1U_0402_6.3V6K <18,31,35,38,9> 2 2 .1U_0402_16V7K 2 .1U_0402_16V7K PCIE_PRX_DTX_P2_C PCIE_PRX_DTX_N2_C 3 4 <8> CLK_PCIE_CR <8> CLK_PCIE_CR# +DV33_18 CC10 1 1 1 2 5 6 23 PLT_RST# 24 <8> CRCLK_REQ# +3VS 2 RC8 1 19 SD_GPIO1 10K_0402_5% HSIP HSIN HSOP HSON SP1 SP2 SP3 SP4 SP5 SP6 12 13 14 16 17 18 1 RC3 1 SD_CLK_R RC5 1 RC6 1 RC7 1 2 0_0402_5% 2 0_0402_5% EMI SD_D1 SD_D0 RC9 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 1 SD_CMD SD_D3 SD_D2 2 33_0402_5% REFCLKP REFCLKN PERST# SD_WP CLK_REQ# SD_CD# GPIO MS_INS# 20 SD_WP 21 SD_CD# SD_CLK C 1 2 @EMI@ CC13 5.6P 50V D NPO 0402 EMI 22 RTS5229-GR_QFN24_4X4 +Card_3V3 JSD1 7 SD_D1 8 SD_D2 9 SD_D3 1 SD_CLK 5 SD_CMD 2 D0 VDD 4 B D1 D2 D3 CLK CMD WP CD VSS1 VSS2 Shading Shading 10 SD_WP 11 SD_CD# 3 6 12 13 CC11 1 2 CC12 1 2 .1U_0402_16V7K SD_D0 4.7U_0603_6.3V6K B TAITW_PSDBTC-09GLBS1N14H0 ME@ SP07000LN00 A A Compal Secret Data Security Classification Issued Date 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title P24-CardRead/RTS5229 Size C Date: 5 4 3 2 Compal Electronics, Inc. Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 1 Sheet 40 of 55 5 4 3 2 1 D D 1 +CHGRTC_R UG1 2 RG1 330_0402_5% GCLK@ SLG3NB3375VTR TQFN 16P C CG5 22U_0603_6.3V6M GCLK@ 1 2 GCLK_VRTC 15 +3VLP VOUT VDD 1 11 2 CG1 .1U_0402_16V7K GCLKDIS@ 1 2 8 +3V_LAN CG3 .1U_0402_16V7K GCLK@ 1 3 +1.05VS CG2 .1U_0402_16V7K GCLK@ 2 1 CLK_X2 CLK_X1 16 1 14 RTC_VOUT 9 CPU_RTCX1_GCLK_R RG4 1 GCLK@ 2 0_0402_5% 12 GPU_XTALIN_GCLK_R RG5 1GCLKDIS@ 2 22_0402_5% 6 LAN_XTLI_GCLK_R RG7 1 GCLK@ 2 33_0402_5% 5 CPU_XTAL24_IN_GCLK_R RG8 1 GCLK@ 2 0_0402_5% EMI V3.3A 32.768kHz +1.8VGS C CG11 2.2U_0402_6.3V6M GCLK@ VIOE_27M 27M VIO_25M 25M VIOE_24M 24M 1 X2 X1 2 SLG3NB3374VTR_TQFN16_2X3 GCLKDIS@ SA00006RD00 GND4 CG10 .1U_0402_16V7K GCLK@ VRTC GND1 GND2 GND3 2 +3VALW UG1 2 2 17 1 2 1 4 7 13 CG4 .1U_0402_16V7K GCLK@ 10 GCLKUMA@ SA00006RE00 1 CG8 5P_0402_50V8C GCLK@ <7> CPU_32.768KHz GPU_XTALIN_GCLK <19> GPU_27MHz only for DIS LAN_XTLI_GCLK LAN_25MHz <38> CPU_XTAL24_IN_GCLK <8> CPU_24MHz CG9 no stuff any of component CG8 just can use 4.7pF~33pF 1 2 CG9 5P_0402_50V8C @ CPU_RTCX1_GCLK CLK_X1 1 B CL28 12P_0402_50V_NPO GCLK@ OSC OSC NC 3 2 NC RG10 510_0402_5% @ CLK_X2 YG1 4 1 2 CG7 5P_0402_50V8C @ CG7 no stuff any of component 2 B 1 25MHZ_10PF_7V25000014 1 GCLK@ SJ10000E800 2 2 CL29 15P_0402_50V8J GCLK@ A A Compal Secret Data Security Classification Issued Date 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size 4 3 2 Document Number Rev 1.0 LA-B091P Date: 5 Compal Electronics, Inc. GCLK Wednesday, February 12, 2014 1 Sheet 41 of 55 A B 2 GND ON2 CT2 VIN2 VIN2 VOUT2 VOUT2 GPAD 1 1 JUMP_43X79 2 C207 470P_0402_50V7K 11 10 9 8 1 2 C213 220P_0402_50V7K +5VALW_5VS R235 1 1 @ 2 @ 2 470_0603_5% 3 D 1 C208 4.7U_0603_6.3V6K 2 SUSP G Q14 @ 2N7002H_SOT23-3 S 2 1 1 DS3@ Q15 LP2301ALT1G_SOT23-3 DS3@ 2 1 2 2 +5VALW DS3@ 15 1 R221 2 1 2 DS3@ 1 PCH_PWR_EN# +5VS APE8990GN3B DFN 14P 47K_0402_5% J5 2 1 1 @ 2 1 D S 2 G <35> PCH_PWR_EN C218 C217 1 .1U_0402_16V7K JUMP_43X79 10U_0603_6.3V6M +5VALW to +5VS 2 1 @ VBIAS 12 2 C209 4.7U_0603_6.3V6K 6 7 1 C215 C214 2 10U_0603_6.3V6M .1U_0402_16V7K 1 5 CT1 +3VALW_3VS C212 +5VALW ON1 14 13 .1U_0402_16V7K 4 VOUT1 VOUT1 C211 SUSP# J4 VIN1 VIN1 10U_0603_6.3V6M <35,47,49,50> +3V_PCH +3VS U13 1 2 +3VALW NODS3@ 2 R219 1 0_0603_5% +3VALW to +3VS 3 1 +3VALW to +3VALW_PCH DS3 3 @ 2 E 1 1 C206 2 10U_0603_6.3V6M C205 .1U_0402_16V7K 1 D +5VALW 3 +3VALW C DS3@ Q17 2N7002K_SOT23-3 1 DS3@ C216 .1U_0402_16V7K 2 2 2 2 R230 1 +1.05VS 1 +0.675VS 1 +5VALW R228 R229 @ @ @ 3 Q21 2 G S 2N7002H_SOT23-3 2 D SUSP @ Q22 2 G S 2N7002H_SOT23-3 1 SUSP @ D 3 2 D 1 Q23 SUSP# 2 G 470_0402_5% 3 SUSP 2 470_0402_5% 1 100K_0402_5% S @ 2N7002H_SOT23-3 3 3 +1.35V 1 1 S 1 2 D 3 1 IN 3 2 OUT @ Q24 DRC2124E0L NPN MINI3-G3-B GND SYSON# <35,47> SYSON @ R233 220K_0402_5% 1 2 +5VALW R234 470_0603_5% @ 2 SYSON# G Q25 2N7002H_SOT23-3 @ 2 R239 100K_0402_5% 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title DC Interface Size C Date: A B C D Document Number Rev 1.0 LA-B091P Wednesday, February 12, 2014 E Sheet 42 of 55 4 EMI@ PL101 HCB2012KF-121T50_0805 1 2 D 1 2 1 1 EMI@ PL102 HCB2012KF-121T50_0805 1 2 2 2 1 ACES_88299-0510 CONN@ VIN EMI@ PC103 100P_0402_50V8J PF101 7A_32VDC_0437007.WRML 1 2 APDIN1 2 APDIN EMI@ PC102 100P_0402_50V8J 1 2 3 4 5 1 2 3 4 5 EMI@ PC101 1000P_0402_50V7K JDCIN1 3 2 1 ADP_ID AC Adapter 90W 65W R(K ohm) open 10 ADP_ID(V) 3.3 1.65 Detection voltage >2.64 1.32~1.98 EMI@ PC104 1000P_0402_50V7K 5 D 1 PR102 750_0402_1% PR104 2 100K_0402_5% +CHGRTC PR105 1K_0603_5% 1 2 C PD101 S SCH DIO BAS40CW SOT-323 2 1 +RTCBATT 3 2 PQ101B 2N7002KDW-2N_SOT363-6 4 3 PR103 100K_0402_5% 1 2 1 VIN 1 PQ101A 2N7002KDW-2N_SOT363-6 6 1 2 2 PC105 0.1U_0402_16V7K 1 2 +3VALW PC106 680P_0603_50V7K @PR101 @ PR101 0_0402_5% 1 2 5 ADP_ID <35> A/D ADP_ID_CLOSE <35> +3VLP +CHGRTC_R JBATT1 PR106 1K_0603_5% 1 2 1 + C - 2 LOTES_AAA-BAT-019-K01 CONN@ RTC Battery B B A A Compal Secret Data Security Classification Issued Date 2011/06/24 2012/07/12 Deciphered Date Title Compal Electronics, Inc. PWR DCIN / RTC Battery THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 BE_BDW Date: 5 4 3 2 Wednesday, February 12, 2014 Sheet 1 43 of 55 3 2 1 Posestor 1 PTC@ PR234 1 PR210 PTC@ 0_0402_5% PTC@ PR225 1 2 PTC@ PR230 1 1K_0402_50% PTC@ PR229 2 1 OT1 <35> PTC_PROTECT 3 4 GND RHYST1 OT1 TMSNS2 OT2 RHYST2 7 6 TMSNS2 A/D MOS_OTP: Default:High Active :Low PTC_PROTECT: Default:Low Active :High 20120314 Change to +EC_VCCA from +3VLP 1 +EC_VCCA 2 1 PR215 16.5K_0402_1% 2 1 2 PH201 100K +-1% 0402 B25/50 4250K 2 PR223 75K_0402_1% 1 1 2 3 PR221 100K_0402_1% 1 6 1 1 PQ201A 2N7002KDW-2N_SOT363-6 1 4 ECAGND D 3 1 BATT_OUT <45> S 2 G PQ203 2N7002KW_SOT323-3 +3VLP 2 B 1.5M_0402_5% 2 PC206 100P_0402_50V8J <35> VCIN1_ADP_PROCHOT PQ201B 2N7002KDW-2N_SOT363-6 5 1N4148WS-7-F_SOD323-2 2 2 PD201 1 1 PR226 1 2 1 C <35> VCIN0_PH1 100K_0402_1% 2 2 8 P G 4 O @ 1 1 2 2 2 1 1 2 PR227 100K_0402_1% 1 PR218 PR217 30K_0402_1% <35,45> ADP_I 100K_0402_1% PU202A AS393MTR-E1 SO 8P OP 2 5 PH201 under CPU botten side : CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C VCIN1_BATT_TEMP <35,44> PC205 0.068U_0402_16V7K - 1 PTC@ PQ202 2N7002KW_SOT323-3 D PTC_PROTECT2 G S TMSNS1 <35> VCOUT1_PROCHOT# 2 2 1 2 MOS_OTP <46> +3VALW PR220 47K_0402_1% + 2 PR209 PTC@ 100K_0402_1% 1 VCC TMSNS1 8 PR231 0_0402_5% @ 0.01U_0402_25V7K 3 PTC@ PR233 2 1 G718TM1U_SOT23-8 PR219 <35,44> VCIN1_BATT_TEMP VL +3VLP VL PR222 75K_0402_1% 2 316K_0402_1% 1K_0402_50% 1K_0402_50% 1K_0402_50% +3VALW PC204 2 1K_0402_50% 1K_0402_50% 1K_0402_50% PR216 10K_0402_1% @ C 1K_0402_50% 3 0.1U_0603_25V7K 1 2 1 32 PTC@ PR207 TMSNS21 +5VALW 0_0402_5% GND VL PR224 GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 2 31 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 PTC@ PR206 2 1 D PC203 PTC@ EC_SMB_DA1 <35,45> 1 2 PR212 16.49K_0402_1% 2 PR213 @ 6.49K_0402_1% 1 2 PR214 10K_0402_5% 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 2 +3VLP PTC@ PR205 2 1 PU201 PTC@ EC_SMB_CK1 <35,45> CONN@ JBAT3 2 1K_0402_50% 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 PTC@ PR204 1 2 PC202 EMI@ 0.01U_0402_25V7K 2 2 PC201 EMI@ 1000P_0402_50V7K 2 1K_0402_50% 1 1 2 1 PR211 100_0402_1% ALLTO_C144PF-K07H9-L PTC@ PR203 1 VL BATT+ EMI@ PL202 HCB2012KF-121T50_0805 1 2 EC_SMCA EC_SMDA 2 1 PR201 100_0402_1% D PTC@ PR202 1 2 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 GND GND EMI@ PL201 HCB2012KF-121T50_0805 1 2 2 VMB PF201 F1206HB12V024TM 12A 24V UL FAST 1 2 1 VMB2 CONN@ JBAT1 1 4 PTC@ PR208 100K_0402_1% 5 B PR228 <35> ADP_65 ECAGND 1 <35> BATT_LEN# D 3 1 100K_0402_1% S 2 G PQ205 2N7002KW_SOT323-3 A A 135W: 150W(Turbo_V=1.2) 90W : 100W(Turbo_V=1.2) 65W : 70W(Turbo_V=1.2) 45W : 65W(Turbo_V=1.2) 5 active 135W(Turbo_V=1.072) recovery active 90W(Turbo_V=0.903) recovery active 65W(Turbo_V=0.918) recovery active 45W(Turbo_V=0.829) recovery 4 Compal Secret Data Security Classification Issued Date 2011/06/24 2012/07/12 Deciphered Date Title Compal Electronics, Inc. PWR-BATTERY CONN/OTP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 BE_BDW Date: 3 2 Wednesday, February 12, 2014 Sheet 1 44 of 55 4 2 1 EMI@ PC307 2200P_0402_50V7K PQ306 DTC115EUA_SC70-3 16 PC315 1 2 4 0.047U_0603_16V7K 2 1 3 2 1 15 2 1 PC319 1U_0603_16V7 BQ24737VDD 1 3 4 2 3 SRP BATT+ SRN PC318 10U_0805_25V6K 2 1 PD301 REGN 1 5 PR318 2.2_0603_5% 1 2 BST_CHG 0.01_1206_1% 2CHG 1 PC317 10U_0805_25V6K 2 1 4.7UH +-20% 5.5A 7X7X3 MOLDING 16251_SN 2 17 DH_CHG DL_CHG PC321 1 4.7uH DCR = 35+/- 15% mohm Power Rating = 1W Idc~Isat = 5.5~6 A VACP~VACN spec < 81.28mV PL302 PR314 1 RB751V-40_SOD323-2 @ PR323 10K_0402_5% PC311 0.1U_0603_25V7K 2 1 3 4 2 @EMI@ PR319 4.7_1206_5% ACN LODRV BTST GND ILIM 2PACIN_2 G S @EMI@ PC320 680P_0603_50V7K 1 1U_0603_25V6K 18 PQ309 2N7002KW _SOT323-3 D 5 PR310 10_1206_5% 2 1 1 2 3 CMPOUT CMPIN ACP HIDRV 1 PD303 1SS355_UMD2-2 1 2 B 2 0.1U_0402_25V6 A 5 4 1 @ PC322 0.1U_0402_25V6 Module model information VCIN1_AC_IN PR325 10K_0402_1% PR324 47K_0402_1% <19,33,35> PACIN 1 D S 2 G ACPRN# PR327 PQ314 2N7002KW _SOT323-3 12K_0402_1% 2 <33> ACPRN# 3 1 2 BQ24737_V1.mdd for dual layer PR326 10K_0402_1% 1 2 1 1 BQ24737VDD 2 **Design Notes** Maximum Charging current 2.0A Battery discharge power 55W. #Register Setting 1. 0X12 bit8 set 0 (default 1) to disable IFAULT HI if add ISN choke 2. 0X12 bit3 set 1 (default 0) to enable turbo boost function 3. 0X12 bit[12:11] set 00 (default 11) to set BAT Depletion Comparator Threshold Falling Threshold = 59.19% of voltage regulation limit (~2.486V/cell) 4. Disable turbo when AC only #Circuit Design 1. Make sure there is pull high for SMB on HW side 2. Use 10X10 choke and 3X3 H/L side MOSFET Charge current 2.0A Power loss : 1.82W Power density : 0.81 (15X15) 3. If use 4S per cell 4.35V battery, need change PR313 to 59K for ACDET setting) 4. For hybrid design, need double check PQ301,PQ302,PQ303,PQ309 component rating #Protect function 1. ACOVP : ACDET voltage > 3.15V 2. Charger timeout : No communication within 175s(default) 3. ACOC : 3.33 X Input current DAC setting(default) 4. CHGOCP : 3/4.5/6A based on current current setting 5. BATOVP : 104% 6. BATLOWV : 2.5V 7. TSHUT : 155C 8. IFAULT HI : 750mV (default) 9. IFAULT LOW : 135mV (default) PC323 0.1U_0402_25V6 2 +3VALW 2 1 Battery out function just for C38/A39 only, other customers please remove PQ313,PQ314,PR310,PR326 BQ24737VCC 19 2 VILIM = 20 X (VSRP - VSRN) = 20 X ICHG X RSR 20 LX_CHG SA00004RZ00 SCL 14 Make sure this pull high Voltage is same with EC VCC PHASE PU301 BQ24737RGRR_VQFN20_3P5X3P5 SRP +3VLP 10 SDA 2 13 1 PR321 10_0603_5% PR317 316K_0402_1% 1 2 PR320 100K_0402_1% EC_SMB_CK1 1 9 PR313 0_0402_5% 1 2 PC314 VCC SRN 100P_0603_50V8 8 EC_SMB_DA1 21 PR306 200K_0402_1% C IOUT BM 7 6.8_0603_5% 1 12 PR322 PC312 2 2200P_0402_25V7K TP 2 PC313 1 2 ACDET 11 6 2 1 ACOK <35,44> ADP_I PR312 59K_0402_1% 1 2 4 5 PR309 2 1 392K_0402_1% 0.1U_0402_25V6 1 3 B S Rds(on) = 30mohm max Vgs = 20V Vds = 30V ID = 7A (Ta=70C) PC310 1 2 VIN PQ310 AON7408L 1N DFN G S VIN 2ACOFF-1 1 PR305 47K_0402_1% PQ312 AON7408L 1N DFN BATT_OUT <44,45> 2 D 2 G 2N7002KW_SOT323-3 1 PQ313 ,45> BATT_OUT ACPRN# 3 2 1 2 2 PR316 @ 0_0402_5% PC309 SE00000G880 S CER CAP 0.1U 25V K X5R 0402 NoDock@ P2 PQ308 PC316 0.01U_0402_25V7K 2 1 10K_0402_1% 1 2 ACOFF-1 2 3 2 D <35,44> Make sure there is pull high for SMB<35,44> on HW side! 1 1 PR315 No support docking vaule PR328 0_0402_5% PR329 0_0402_5% PR330 @ PC309 0.1U_0402_25V PC309 0.1U_0402_25V6 1 2 D PR304 200K_0402_1% 1 2 2 3 1 2 4 5 1 PQ311 DTC115EUA_SC70-3 2N7002KW_SOT323-3 P2-2 3 PQ307B PR311 47K_0402_1% 1 2 PACIN 2N7002KDW-2N_SOT363-6 PR308 150K_0402_1% 6 1 PACIN_2 C <35> AC_OFF ACP PC308 0.1U_0402_25V6 1 2 <36> Dock@ PQ307A 2N7002KDW -2N_SOT363-6 2 DOCKING_CONSUMPTION DISCHG_G 2 PR307 20K_0402_1% 3 DTC115EUA_SC70-3 Dock@ PR330 1 2 10_0402_1% ACN 4 CELL: PR312 = 59.0k Typ Worst L => H 18.346V 18.529V H => L 17.925V 17.589V 1 PQ305 @EMI@ PC303 10U_0805_25V6K 8 7 6 5 1SS355_UMD2-2 P2-1 2 PQ303 AO4407AL_SO8 1 2 3 1DISCHG_G-1 2 3 CELL: PR312 = 64.9k Typ Worst L => H 16.896V 17.065V H => L 16.509V 16.199V 1 V1 3 2 1 @EMI@ PC306 0.1U_0402_25V6 ACDET 1 2 2 PC302 5600P_0402_25V7K 4 2 2 1 PC305 10U_0805_25V6K 1 2 2 3 DRA5144E0L PNP SOT323-3 PC301 0.1U_0603_25V7K 2 1 PR303 200K_0402_1% 1 1 PR301 47K_0402_5% D 1 1 PQ304 PR328 SD028000080 S RES 1/16W 0 +-5% 0402 NoDock@ PR329 SD028000080 S RES 1/16W 0 +-5% 0402 NoDock@ AO4407AL Vds=-30V Rds_on=12.7~17mohm@Vgs=-6V ID = 10A (Ta=70C) CHG_B+ EMI@ PL301 1UH +-30% 2.8A 4X4X2 FERRITE 1 2 PD302 PR302 0.01_1206_1% 2 1 PC304 10U_0805_25V6K 8 7 6 5 1 Need EC write ChargeOption() bit[8]=0 to disable iFault_Hi function. Isat: 4A DCR: 27mohm 2 1 2 3 4 1 2 3 4 8 7 6 5 VIN 2 Power Rating = 1W VACP~VACN spec < 80.64mV PQ302 AO4455_SO8 2 1 Dock@ PR329 10_0402_1% PQ301 AO4407AL_SO8 Dock@ PR328 10_0402_1% 2 1 P2 3 B+ 1 4 AO4423L Vds=-30V Rds_on=9.4~12mohm@Vgs=-6V P3 ID = 12.1A (Ta=70C) 2 1 @RF@ PC324 0.022U_0402_25V7K 5 AO4407AL Vds=-30V Rds_on=12.7~17mohm@Vgs=-6V ID = 10A (Ta=70C) A For disable pre-charge circuit 2011/06/24 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/07/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 3 2 Charger_BQ24737 Document Number Rev 1.0 BE_BDW W ednesday, February 12, 2014 Sheet 1 45 of 55 A B C D E Module model information SY8208B_V2.mdd 1 1 EN1 and EN2 dont't floating Change 3V5V_EN to 3VALW_EN PC407 C407 10U_0805_25V6K 2 1 IN EN1 IN EN2 3 6 BS PC403 PR403 0.01U_0402_25V7K 1K_0402_5% 1 2 1 2 3V5V_EN 1 BST_3V 3V_FB PR405 2 2.2_0603_5% 1 PC404 2 PL402 3.3V LDO 150mA~300mA 2 PR407 2.2K_0402_5% 1 2 1 <35> VCOUT0_MAIN_PWR_ON @ PR408 2 0_0402_5% 1 2 0_0402_5% @PR409 @ PR409 EMI@ PL403 HCB2012KF-121T50_0805 1 2 @EMI@ PC420 0.1U_0402_25V6 2 1 PC411 22U_0603_6.3V6M 1 2 2 +3VALW 1 2 EN1 and EN2 dont't floating PR415 1 PR416 1 2 0_0402_5% 3V5V_EN Reserve for USB Charger 2 2.2K_0402_5% @ @ 1 PC429 2 SUSACK# <35,9> 4.7U_0402_6.3V6M PR419 1 @ 2 1M_0402_1% PR417 1 @ 2 0_0402_5% VCOUT0_MAIN_PWR_ON PR418 1 @ 2 0_0402_5% MOS_OTP PU402 8 EN1 EN2 BS PC415 PR412 6800P_0402_25V7K 1K_0402_5% 1 2 1 2 1 5V_EN 3 5V_FB 6 BST_5V 1 PR413 2.2_0603_5% 2 PC417 0.1U_0603_25V7K 1 2 Vout is 4.998V~5.202V 3 TDC=6A PL404 PC428 22U_0603_6.3V6M PC425 22U_0603_6.3V6M 2 1 VL PC424 22U_0603_6.3V6M 2 1 7 PC423 22U_0603_6.3V6M 2 1 LDO +5VALWP 1 PG SY8208CQNC_QFN10_3X3 2 1.5UH_PCMB053T-1R5MS_6A_20% 2 OUT 1 LX_5V 4 PC422 22U_0603_6.3V6M 2 1 VCC 10 680P_0603_50V7K 4.7_1206_5% LX @EMI@ PC427 @EMI@ PR414 2 1 5V_SN 2 1 GND 1 1 2 PC421 4.7U_0603_6.3V6M 2 5 2 9 5V_VCC Module model information IN PC426 4.7U_0603_6.3V6M @ @P EMI@ PC419 2200P_0402_50V7K 2 1 PC418 C418 10U_0805_25V6K 2 1 3 @ PJ401 1 +3VALWP 5V_VIN PC416 10U_0805_25V6K 2 1 B+ TDC=6A JUMP_43X118 3V5V_EN 2 1 PR410 1M_0402_1% <44> MOS_OTP 2 Vout is 3.234V~3.366V EC VDD0 is +3VL, PC13 UNPOP EC VDD0 is +3VALW, PC13 POP PC414 4.7U_0402_6.3V6M <35> EC_ON PC410 22U_0603_6.3V6M 2 1 2 +3VLP Check pull up resistor of SPOK at HW side +3VLP PC412 4.7U_0603_6.3V6M 1 5 +3VALWP 2 LDO @EMI@ PR406 1 3V_SN 2 1 PG SY8208BQNC_QFN10_3X3 2 1.5UH_PCMB053T-1R5MS_6A_20% 680P_0603_50V7K 4.7_1206_5% OUT @EMI@ PC413 2 PR402 100K_0402_1% 1 2 GND 1 LX_3V 4 1 9 PC409 22U_0603_6.3V6M 2 1 10 LX 2 <35> 3V/5VALW_PG B+ 0.1U_0603_25V7K @ @P PC408 22U_0603_6.3V6M 2 1 PC406 10U_0805_25V6K 2 1 EMI@ PC405 2200P_0402_50V7K 2 1 8 3V_VIN 1 PR404 150K_0402_1% 2 1 PU401 7 EMI@ PL401 HCB2012KF-121T50_0805 1 2 @EMI@ PC401 0.1U_0402_25V6 2 1 B+ PR401 499K_0402_1% 1 2 ENLDO_3V5V @ PJ402 +5VALWP 1 1 2 2 +5VALW JUMP_43X118 5V LDO 150mA~300mA SY8208C_V2.mdd 4 4 Compal Secret Data Security Classification 2011/06/24 Issued Date 2012/07/12 Deciphered Date Title Compal Electronics, Inc. +3VALW/+5VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D Rev 1.0 BE_BDW Wednesday, February 12, 2014 Sheet E 46 of 55 5 4 3 2 1 Module model information RT8207M_V1.mdd RT8207M_V2.mdd For Single layer For Dual layer D D PR501 2.2_0603_5% 1 2 BOOT_1.35V +0.675VSP PAD VTTGND Change CS R to your estimation value CS 12 VDDP VTTREF VTTREF_1.5V off on on 1 2 2 +VTTREFP 5 +1.35VP FB PC509 0.033U_0402_16V7K FB_1.35V 6 S3 PR506 8.2K_0402_1% 1 2 +1.35VP B Change FB Rtop to 8.2K for 1.35V 1 7 EN_0.675VSP TON 3 4 1 <35,42> SYSON L/S Rds(on): 9.9mohm(Typ), 13mohm(Max) Idsm: 13.5A@Ta=25C, 11A@Ta=70C PR508 10K_0402_1% @ PR509 2 2 +0.75VSP off off on 2 0_0402_5% @ PC514 0.1U_0402_10V7K Choke: 7x7x3 Rdc=8.3mohm(Typ), 10mohm(Max) Note: S3 - sleep ; S5 - power off Switching Frequency: 285kHz Ipeak=10A Iocp~13A OVP: 110%~120% MOSFET footprint: SIS412DN <35,42,49,50> SUSP# @ PR510 1 2 0_0402_5% @ PJ501 1 +1.35VP PR505 1 2 0_0402_5% 2 <16> DDR_VTT_PG_CTRL 1 2 2 +1.35V JUMP_43X118 @ PJ502 1 2 1 2 1 Level L L H 1 1 Mode S5 S3 S0 C 2 Co-Lay MOSFET: 3x3 DFN H/S Rds(on): 27mohm(Typ), 34mohm(Max) Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C 8 B 9 PR507 887K_0402_1% 1 2 1.35V_B+ EN_1.35V +5VALW 10 PC512 1U_0603_10V6K VDDQ S5 VDD TON_1.35V 11 GND RT8207MZQW _W QFN20_3X3 1 VDD_1.35V 13 VTTSNS PGOOD +5VALW 4 2 @EMI@ PC513 680P_0402_50V7K PQ502 MDV1524URH 1N PDFN33-8 PR504 5.1_0603_5% 1 2 PGND 1 2 3 2 1 2 + @EMI@ PR503 4.7_1206_5% 2 1 ESR=9m ohm ESR=15m ohm PC510 330U_6.3V_ESR17M_6.3X6 5 1 1 2 3 PR502 18K_0402_1% 1 2 CS_1.35V PC508 1U_0603_10V6K 1 2 21 2 14 +1.35VP PC506 10U_0805_10V6K 20 VTT PU501 1 LGATE 19 17 1 15 VLDOIN DL_1.35V BOOT 4 PHASE PQ501 AON7408L_DFN8-5 18 16 2 5 1 SW _1.35V PC505 0.1U_0603_25V7K PC507 10U_0805_10V6K DH_1.35V C PL502 1UH +-20% 11A 7X7X3 MOLDING 1 2 0.75Volt +/- 5% TDC 0.7A Peak Current 1A +1.35VP UGATE 1 2 BST_1.35V PC504 10U_0805_25V6K 1 2 PC503 10U_0805_25V6K 1 2 EMI@ PC502 2200P_0402_50V7K 2 1 1.35V_B+ @EMI@ PC501 0.1U_0402_25V6 B+ Pin19 need pull separate from +1.5VP. If you have +1.5V and +0.75V sequence question, you can change from +1.5VP to +1.5VS. EMI@ PL501 HCB2012KF-121T50_0805 1 2 @ PC515 0.1U_0402_10V7K JUMP_43X118 PJ503 @ 1 +0.675VSP 1 2 2 +0.675VS JUMP_43X39 A Compal Secret Data Security Classification Issued Date 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title A Compal Electronics, Inc. RT8207M Size Document Number Custom Date: Rev 1.0 BE_BDW Wednesday, February 12, 2014 Sheet 1 47 of 55 A B C D Module model information APL5930_V1.mdd 1 1 +3VALW +5VALW 2 2 PJ602 1 2 2 +1.8VGS JUMP_43X79 PC603 0.01U_0402_25V7K 2 1 Rup @ 1 +1.8VGSP 1 2 +1.8VGSP PC604 22U_0603_6.3V6M 1 2 2 @ PR602 100K_0402_5% FB PR603 24K_0402_1% 2 EN POK 2 8 7 GND 2 2 2 PR604 47K_0402_5% +3VS 1 1 PU601 APL5930KAI-TRG_SO8 6 5 VCNTL 3 VOUT 4 9 VIN VIN VOUT 1 2 1 PR601 60.4K_0402_1% 1 2 1 <20,35,48,51,9> DGPU_PWR_EN PC605 0.1U_0402_16V7K <20,35,48> GPU_1.8VGS_PWR_EN @ PR607 100K_0402_5% PC602 1 2 4.7U_0805_6.3V6K 2 1 1 1 Ultra Low Dropout 0.23V(typical) at 3A Output Current PC601 1U_0402_6.3V6K 1 JUMP_43X79 @ PJ601 PR605 19.1K_0402_1% 2 Rdown Vout=0.8V* (1+Rup/Rdown) @ PR612 60.4K_0402_1% 1 2 Module model information GPU_1.8VGS_PWR_EN <20,35,48> SY8003_V1.mdd PR606 10K_0402_1% 1 2 PU602 SY8003DFC_DFN8_2X2 PR610 11.8K_0402_1% Rup 2 @ PJ604 PR611 20K_0402_1% Rdown 1 +0.95VGSP 2 1 FB=0.6V Note:Iload(max)=3A @EMI@ PC611 680P_0402_50V7K 1 FB_0.95V +0.95VGSP 1 5 PL601 S COIL 1UH +-30% 2.8A 4X4X2 FERRITE 1 2 2 NC LX_0.95V PC610 22U_0603_6.3V6M PGND 6 1 LX 2 4 EN IN 2 2 JUMP_43X79 PC607 22U_0603_6.3V6M PG PC609 22U_0603_6.3V6M 3 PC608 68P_0402_50V8J 2 1 2 1 @ 2 3 Note:Iload(max)=2.5A 2 1 1 1 9 8 7 1 PJ603 +3VALW PGND SGND FB 2 @EMI@ PR609 4.7_0603_5% 1 PR608 1M_0402_5% 2 3 DGPU_PWR_EN <20,35,48,51,9> 1 0.1U_0402_16V7K PC606 2 1 +0.95VSP_ON 1 2 2 +0.95VGS JUMP_43X79 Note: When design Vin=5V, please stuff snubber to prevent Vin damage 4 4 Vout=0.6V* (1+Rup/Rdown) Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 Title +1.8VGS-+0.95VVGS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C Rev 1.0 BE_BDW W ednesday, February 12, 2014 D Sheet 48 of 55 A B C D 1 1 Module model information SY8003_V1.mdd PR702 0_0402_5% 1 2 PR703 1M_0402_5% @ 5 PL701 1UH +-30% 2.8A 4X4X2 FERRITE 1 2 PR705 15K_0402_1% Rup FB_1.5V 2 PR706 10K_0402_1% Rdown PJ702 2 1 FB=0.6V Note:Iload(max)=3A @EMI@ PC706 680P_0402_50V7K 1 2 SY8003DFC_DFN8_2X2 2 +1.5VSP 1 NC LX_1.5V 6 2 PGND 7 PC705 22U_0603_6.3V6M LX 1 4 2 JUMP_43X79 PC701 22U_0603_6.3V6M EN IN 2 3 PC704 22U_0603_6.3V6M 2 PC703 68P_0402_50V8J 2 1 2 1 1 1 1 PGND SGND PG Note:Iload(max)=2.5A 2 +3VALW 2 FB 1 2 @EMI@ PR704 4.7_0603_5% 1 PJ701 @ 9 8 2 PU701 SUSP# <35,42,47,50> 1 0.1U_0402_16V7K PC702 2 1 +1.5VSP_ON +1.5VSP 1 1 @ 2 2 +1.5VS JUMP_43X79 Note: When design Vin=5V, please stuff snubber to prevent Vin damage Vout=0.6V* (1+Rup/Rdown) 3 3 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 Title +1.5VS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C Rev 1.0 BE_BDW W ednesday, February 12, 2014 D Sheet 49 of 55 5 4 3 2 1 D D Module model information SY8208D_V1.mdd EN pin don't floating If have pull down resistor at HW side, pls delete PR2 PR802 0_0402_5% 1 2 SUSP# <35,42,47,49> C 1 1 C @ PC802 0.22U_0402_10V6K 2 2 1M_0402_1% PR803 1 +1.05VSP 1 PJ801 2 2 JUMP_43X118 PL802 1UH +-20% 11A 7X7X3 MOLDING 1 2 SY8208DQNC_QFN10_3X3 2 2 <35> 1.05V_VS_PG_PWR The current limit is set to 8A, 12A or 16A when this pin is pull low, floating or pull high Pin 7 BYP is for CS. Common NB can delete FB = 0.6V 1 2 PC812 22U_0603_6.3V6M 1 2 1 2 +3VALW PC811 22U_0603_6.3V6M 3VLDO_1.05 2 5 PC810 47U_0805_6.3V6M Rup 7 1 LDO PR809 Rdown 20K_0402_1% 2 PG 1 BYP 2 PR801 10K_0402_5% ILMT PC814 4.7U_0603_6.3V6K FB ILMT_1.05V3 21.05V_VS_PG_PWR 2 1 1 +1.05VSP 4 2 LX_1.05V PC809 47U_0805_6.3V6M 10 TDC 8A PR805 PC804 2.2_0603_5% 0.1U_0603_25V7K 2 1 2 1 LX 1 BST_1.05V 1 GND 6 2 9 1 PC808 330P_0402_50V7K BS PR808 @ 0_0402_5% B EN PR807 15K_0402_1% 10U_0805_25V6K PC807 2 1 10U_0805_25V6K PC806 2 1 IN 1 +3VS 8 PC813 4.7U_0603_6.3V6K ILMT_1.05V 1 2 PR806 0_0402_5% @ PU801 B+_1.05V @EMI@ PC805 0.1U_0402_25V6 2 1 1 3VLDO_1.05 EMI@ PL801 HCB2012KF-121T50_0805 1 2 EMI@ PC801 2200P_0402_50V7K 2 1 B+ +1.05VS @ @EMI@ PR804 @EMI@ PC803 4.7_1206_5% 680P_0603_50V7K 1 2SNB_1.05V 1 2 +3VALW and PC15 B VFB=0.6V Vout=0.6V* (1+Rup/Rdown) Vout=1.05V A A Compal Secret Data Security Classification Issued Date 2011/06/24 Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 5 4 3 2 Compal Electronics, Inc. Document Number +1.05VS Rev 1.0 BE_BDW Wednesday, February 12, 2014 1 Sheet 50 of 55 5 4 3 2 1 +VGA_CORE GPU_B+ AMD TOPAZ TDC 31A, EDC 46.5A OCP min 58.1A Module model information EMI@ PL901 HCB2012KF-121T50_0805 ISL62771_V1A.mdd for IC portion 1 B+ 2 PQ901 UGATE1 7 PR904 0_0402_5% 1 2 1 2 G2 S1/D2 S2 G1 S2 D1 S2 6 5 1 2 PC906 0.22U_0603_25V7K 1 2 PC905 10U_0805_25V6K 2 1 PR905 2.2_0603_1% 2 BOOT11 PC904 10U_0805_25V6K PHASE1 D EMI@ PC903 2200P_0402_50V7K 2 1 LGATE1 @EMI@ PC902 0.1U_0402_25V6 2 1 ISL62771_V1B.mdd for SW portion AMD JET LE TDC 20A, EDC 30A OCP min 37.5A D 4 3 PR902 LGATE_NB1 PR945 41.2K_0402_1% SH00000NX00 (DCR:1.4± 5%) 10K_0402_1% 1 2 PHASE_NB1 +VGA_CORE LGATE2 PR908 3.65K_0603_1% 1 2 VSUM- PR910 1_0402_1% 1 2 +5VALW PHASE2 25W@ PR928 25W@PC922 25W@PC922 2.2_0603_1% 0.22U_0603_25V7K 2 1 2 BOOT21 PQ902 1 +3VS 7 25W@ 0_0402_5% PR921 2 UGATE2 1 @ PR917 100K_0402_1% 1 2 25W@ G2 S1/D2 S2 G1 S2 D1 S2 6 5 4 1 BOOT1 2 21 C PC908 330U_D2_2V_Y 3 AON6932A_DFN5X6-8-7 1 2 25W@ PL903 1 @ PR923 32.4K_0402_1% 1 2 2 PR925 PC923 137K_0402_1% 390P_0402_50V7K 1 2 1 2 PC926 330P_0402_50V7K 1 2 2 PR930 2K_0402_1% 1 2 PR929 @25WEMI@ 4.7_1206_5% ISEN2 25W@PR940 25W@ PR940 10K_0402_1% 1 2 25W@PR941 25W@PR941 1_0402_1% 1 2 PC944 2.2U_0402_6.3V6M 2 1 PC945 2.2U_0402_6.3V6M 2 1 PC959 0.1U_0402_10V7K 2 1 PC960 0.1U_0402_10V7K 2 1 PC946 2.2U_0402_6.3V6M PC943 2.2U_0402_6.3V6M 2 1 PC958 0.1U_0402_10V7K 2 1 PC942 2.2U_0402_6.3V6M 2 1 PC957 1U_0402_6.3V6K 2 1 PC937 2.2U_0402_6.3V6M 2 1 PC953 10U_0603_6.3V6M PC941 2.2U_0402_6.3V6M 2 1 PC936 2.2U_0402_6.3V6M 2 1 PC952 10U_0603_6.3V6M 2 1 PC940 2.2U_0402_6.3V6M 2 1 PC935 2.2U_0402_6.3V6M 2 1 PC951 10U_0603_6.3V6M 2 1 PC939 2.2U_0402_6.3V6M 2 1 PC934 2.2U_0402_6.3V6M 2 1 PC950 10U_0603_6.3V6M 2 1 PC938 2.2U_0402_6.3V6M 2 1 PC933 2.2U_0402_6.3V6M 2 1 PC954 1U_0402_6.3V6K 2 1 PC932 2.2U_0402_6.3V6M 2 1 2 1 PR931=536 ohm, PR924=1K ohm, PC925=0.1uF, PR944 =0 ohm, PR920=10K ohm, PC924=0.022U PC961 @, PC962 @, PR938 @ and PR939 @ while PR931=536 ohm to set OCP for GPU 15W application. PC949 10U_0603_6.3V6M 2 1 1 <19> 2 GPU_VDD_RUN_FB_L PC948 10U_0603_6.3V6M 2 1 GPU 15W setting B <19> PC931 2.2U_0402_6.3V6M 2 1 2 1 PC930 0.01U_0402_50V7K PR1046 set 536 ohm to OCP 26.32A ISEN1 +VGA_CORE GPU_VDD_SEN @ PR935 0_0402_5% 1 2 PC947 10U_0603_6.3V6M 2 1 @ PR933 0_0402_5% 2 1 25W@PR943 25W@ PR943 10K_0402_1% 1 2 PC927 @25WEMI@ 680P_0603_50V7K VSUM- @ PC929 @ PR934 820P_0402_50V7K 100_0402_1% 1 2 1 2 +VGA_CORE 4 0.22UH_PCME064T-R22MS_28A_20% 3 25W@PR942 25W@ PR942 3.65K_0603_1% 1 2 VSUM+ PC956 1U_0402_6.3V6K 2 1 25W@ PR924 866_0402_1% 1 2 PC920 25W@ 270P_0402_50V7 1 330P_0402_50V7K 1 2 @ PC921 PC919 PR922 1000P_0402_50V7K 301_0402_1% 1 2 1 2 1 2 1 25W@ 25W@ PC925 0.15U_0603_16V7K 1 2 1 PR927 11K_0402_1% 1 2 PC920 SE071181J80 S CER CAP 180P 50V J NPO 0402 15W@ + 2 GPU_B+ LGATE2 25W@ PR931 422_0402_1% 1 2 PC928 0.1U_0603_50V7K 2 1 PC918 25W@ 10U_0805_25V6K 2 1 UGATE1 1 PHASE1 22 2 23 PGOOD LGATE1 PC917 25W@ 10U_0805_25V6K PR913 1 2 1_0603_5% 25 24 2 VSUMPC924 SE075223K80 S CER CAP 0.022U 25V K X7R 0402 15W@ 2 PC925 SE042104K80 S CER CAP .1U 25V K X7R 0603 15W@ 25W@ PC924 0.047U_0402_25V7K 2 1 B PH902 10K +-5% 0402 B25/50 4250K 2 1 2 1 PR926 2.61K_0402_1% PR924 SD034100180 S RES 1/16W 1K +-1% 0402 15W@ + 2 VSUM+ 2 1 26 ISEN1 ISEN2 25W@ VSUM- VSUM+ 2 + PC909 330U_B2_2.5VM_R9M PHASE2 PC911 @EMI@ 680P_0603_50V7K DGPU_PWROK <51,9> PC962 0.22U_0402_10V6K 15W PR931 SD00000AN80 S RES 1/16W 536 +-1% 0402 15W@ ISEN2 1 25W 2 15W@ 10K_0402_1% 15W@ +5VS PC961 0.22U_0402_10V6K 2 1 2 ENABLE PR944 1 2 0_0402_5% Reserve for GPU Sequence 1 <20,35,48,9> DGPU_PWR_EN 0_0402_5% PR920 1 2 PR932 1 2 PH901 470K +-5% 0402 B25/50 4700K + 25W@PR939 25W@ PR939 10K_0402_1% 1 2 PC907 390U_2.5V_M 1 28 27 1 UGATE2 20 RTN COMP 19 18 17 12 FB BOOT1 PR918 20K_0402_1% 1 2 25W@PR938 25W@ PR938 10K_0402_1% 1 2 ISEN1 2 UGATE1 BOOT2 29 PC913 1U_0603_10V6K PHASE1 30 1 ENABLE IMON 1 PR907 @EMI@ 4.7_1206_5% 2 LGATE1 PWROK +5VALW PC912 1U_0603_10V6K 33 31 BOOT_NB UGATE_NB 32 35 34 LGATE_NB PHASE_NB COMP_NB PGOOD_NB 38 36 37 FB_NB VSEN_NB 40 39 VDD SVT 2 PC914 1000P_0402_50V7K PR919 27.4K_0402_1% 1 2 VDDP ISL62771HRTZ-T_TQFN40_5X5 VDDIO 11 1 SVD NTC PR916 133K_0402_1% LGATE2 VSEN 2 7 @ PR915 1 2 ENABLE 8 0_0402_5% 1 PR937 2 @ 9 0_0402_5% 10 IMON PHASE2 VR_HOT_L ISUMN <51,9> DGPU_PWROK 1 6 VDDIO 0_0402_5% <19> GPU_SVT 2 PC901 <20,35> GPU_PWR_EN 0.1U_0402_25V6K SVC 16 2 0_0402_5% @ @PR914 1 2 +1.5VS PR912 1 1 +1.8VGS C 5 <19> GPU_SVD BOOT2 UGATE2 ISUMP 4 100K_0402_1% 2 4 PL902 0.22UH_PCME064T-R22MS_28A_20% 3 2 1_0402_5% IMON_NB ISEN1 3 <19> GPU_SVC <19> GPU_PROCHOT# @ PR911 1 +3VS NTC_NB 15 2 14 1 100K_0402_1% 1 2 IMON_NB 13 100K_0402_1% 1 2 PR909 ISEN2 PR901 ISUMN_NB 41 TP ISUMP_NB PU901 1 PC910 390U_2.5V_M 1 PR906 BOOT_NB12 25WEMI@ PC916 2200P_0402_50V7K 2 1 2 PR903 10K_0402_1% 2 UGATE_NB1 1 @25WEMI@ PC915 0.1U_0402_25V6 2 1 Fsw=400K Hz @ PR947 1 2 0_0402_5% PC955 1U_0402_6.3V6K 2 1 @ PR946 1 2 0_0402_5% 1 AON6932A_DFN5X6-8-7 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Deciphered Date 2012/07/12 Title PWR-+VGA_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Rev 1.0 BE_BDW Wednesday, February 12, 2014 1 Sheet 51 of 55 5 4 3 2 1 Base on BDW PDDG Rev_0_73 Module model information: ISL95813 (for 15W & 28W CPU) 15W H-side MOS: MDV1525URH Rds(on): <10.1mohm@Vgs=10V <14.0mohm@Vgs=4.5V Id :24A@Vgs=10V TDC 14A Location D MAX 32A Note D OCP 39A L-side MOS: MDU1511RH Rds(on): <2.4mohm@Vgs=10V <3.3mohm@Vgs=4.5V Id :100A@Vgs=10V Loadline=-2.0mv/A Follow intel guideline +1.05VS 1 PC1102 1U_0402_6.3V6K 1 2 1 PR1102130_0402_1% 2 PR110354.9_0402_1% 2 <12> VR_SVID_DAT Note: VR_SVID_ALRT# Pull high on HW side PR1120 499 Ohm OCP PR537 1.27kOhm Droop PC528 0.022uF PR507 90.9kOhm PROG1 PR703 93.1kOhm IMON PC518 0.1uF ( 0402 ) RC Filter RC Match Choke: 0.12UH (Size:7*7*3) Rdc=0.62mohm +-5% Heat Rating Current=41.5A Saturation Current=41A <12> VR_SVID_ALRT# 2 NTC 5 COMP 6 NTC 2 PC1122 68U_25V_M 33U_25V_M PC1123 @RF@ PC1107 0.022U_0402_25V7K 2 1 EMI@PC1106 2200P_0402_50V7K 2 1 EMI@PC1105 0.01U_0402_50V7K 2 1 PC1103 10U_0805_25V6K 2 1 4 +CPU_CORE 3 1 1 2 PR1109 3.65K_0603_1% B 1 Note: PR1112=124K =>Slew rate=53mV/us Vboot = 1.7V PR1118 4.42K_0402_1% 1 PC1117 0.1U_0402_16V4Z 2 PC1116 0.033U_0402_25V7K 2 2 1 2 RC Match 1 1 PC1111 0.1U_0402_25V6 + 2 @ PR1117 4.99M_0402_1% 2 Droop 3 2 1 1 PRGM2 PR1112 124K_0402_1% 2 1 ISUMP 10 ISUMN RTN 8 7 1 2 PR1116 1.27K_0402_1% 1 @PR1115 10_0402_1% PR1114 2K_0402_1% @ @PC1115 390P_0402_50V7K 2 1 2 PC1114 330P_0402_50V7K 1 1 2 1 PR1113 909_0402_1% 2 1 2 @ 11 PRGM2 ISUMP FB 33P_0402_50V8J @ PC1112 9 COMP ISUMN Over temperature protection: OTP Setting: 100C active Pin5 (NTC) voltage <0.88V, Protect Pin5 (NTC) voltage >0.92v, recovery 4 +5VS 3.83K_0402_1% PR1111 27.4K_0402_1% 1 2 PC1113 6800P_0402_25V7K 2 1 2 B 12 VCC 2 BOOT 1 C @EMI@ PL1104 HCB2012KF-121T50_0805 1 2 2 1 @EMI@PR1107 4.7_1206_5% VR_HOT# PR1110 FB PC1109 47P_0402_50V8J 2 1 PH1101 470K +-5% 0402 B25/50 4700K 1 2 1 ISL95813HRZ-T_QFN20_3X4 VR_HOT_1# 4 <35> VR_HOT# 2 13 PR1108 PC1108 2.2_0603_5% 0.22U_0603_16V7K 2 1 2 BOOT 1 + 2 @EMI@PC1110 680P_0603_50V7K UAGTE 3 2 1 14 1 B+ PL1102 .15UH 20% PCME064T-R15MS0R667 36A 1 4 PQ1102 MDU1511RH_POWERDFN56-8-5 UGATE PQ1101 MDV1525URH_PDFN33-8-5 5 PRGM1 VR_SVID_DAT 17 VR_SVID_ALRT# 19 18 20 21 IMON PHASE 5 3 LAGTE 15 3 2 1 IMON_CPU PHASE EMI@ PL1103 HCB2012KF-121T50_0805 1 2 PR1119 11K_0402_1% 1 Note: VR_HOT# Pull high on HW side PGOOD 16 PQ1103 MDU1511RH_POWERDFN56-8-5 PR1106 97.6K_0402_1% 1 2 LGATE 4 5 2 VR_ON CPU_B+ PR1105 0_0603_5% 1 2 PRGM1 1 VR_ON SDA VR_SVID_CLK PC1101 1000P_0402_50V7K 1 2 ALERT# 2 PU1101 SCLK <12> VGATE <35> IMON_CPU PAD 1 @ PR1101 1.91K_0402_1% 1 2 +1.05VS PR1122 1.5K_0402_1% <12> VR_ON CPU_B+ Note: PR1104=169K =>Icc(max)=33A fsw=700KHz PC1104 10U_0805_25V6K 2 1 PR1104 169K_0402_1% 1 2 <12> VR_SVID_CLK C <12> VCCSENSE A PC1120 1 2 @PC1119 2 1 2 @ PC1118 1 2 330P_0402_50V7K 0.082U_0402_16V7K PH1102 10K +-5% 0402 B25/50 4250K OCP Setting PR1120 1 2 A 287_0402_1% 0.01U_0402_50V7K <12,14> VSSSENSE @ PC1121 @ PR1121 1 1 2 4700P_0402_25V7K 2 Compal Electronics, Inc. Title 1.5K_0402_1% ISL95813 for BDW-Y&U(15W/28W) CPU Local sense put on HW site Size Document Number Date: Wednesday, February 12, 2014 Rev 1.0 BE_BDW 5 4 3 2 Sheet 1 52 of 55 5 4 3 2 1 +CPU_CORE 24 X 22u/0603 2 2 1 2 2 @ 1 2 1 2 PC1210 22U_0603_6.3V6M PC1209 22U_0603_6.3V6M PC1208 22U_0603_6.3V6M PC1207 22U_0603_6.3V6M PC1205 22U_0603_6.3V6M PC1204 22U_0603_6.3V6M PC1203 22U_0603_6.3V6M PC1206 22U_0603_6.3V6M 1 2 1 PC1220 22U_0603_6.3V6M 2 1 2 @ 1 PC1219 22U_0603_6.3V6M 2 1 2 1 PC1218 22U_0603_6.3V6M 2 1 2 @ 1 PC1217 22U_0603_6.3V6M 1 2 @ 1 PC1216 22U_0603_6.3V6M 2 @ 2 @ 1 PC1215 22U_0603_6.3V6M 1 2 1 PC1214 22U_0603_6.3V6M 2 PC1211 22U_0603_6.3V6M 1 1 PC1213 22U_0603_6.3V6M 2 @ PC1212 22U_0603_6.3V6M 1 2 1 PC1202 22U_0603_6.3V6M D PC1201 22U_0603_6.3V6M D 2 1 2 1 2 PC1224 22U_0603_6.3V6M 2 1 PC1223 22U_0603_6.3V6M 1 PC1222 22U_0603_6.3V6M C PC1221 22U_0603_6.3V6M C 1 + @ PC1234 2 330U_D2_2VM_R9M B B A A Compal Electronics, Inc. Compal Secret Data Security Classification 2011/06/24 Issued Date Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PWR-PROCESSOR_DECOUPLING Size Document Number Custom Date: Rev 1.0 BE_BDW W ednesday, February 12, 2014 Sheet 1 53 of 55 5 4 3 2 Version change list (P.I.R. List) Item 1 Page 1 of 1 for PWR Reason for change PG# Modify List Date Phase 1 D D 2 3 4 6 7 8 C C 9 10 11 12 13 14 B B 15 16 17 A A 2011/06/24 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2012/07/12 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 PIR (PWR) Rev 1.0 BE_BDW W ednesday, February 12, 2014 Sheet 1 54 of 55 5 4 3 2 1 ZIWB2/ZIWB3/ZIWE1 HW PIR List D Item Page MODIFICATION LIST PURPOSE 1 P.36 Modify DP_SEL schematic Because the first design is wrong. EVT TO DVT 2 P.34 Delete D28 It already reserve in sub BD 3 P.36 Modify HPD schematic Because the first design is wrong. 4 P.36 Modify DP AUX schematic Cap already reserve in sub BD 5 P.20 Reserve +1.05VS to +0.95VGS AMD's suggestion 6 P.33 Add D26 for ESD 7 P.42 Add RV198, RV199 AMD's suggestion 8 P.22~24 Add GPU Termination Resistance AMD's suggestion 1 P.35 change U11.111 power rail to +3VLP It only use +3VLP 2 P.33 un-pop R294, pop R295. B series's LED need to follow E series D DVT TO PVT 3 P.10 Add R247, R248 For BIOS Stap Pin 4 P.20 Add RV60, delete RV36 for GPU Sequence 5 P.20 Add RV61, delete RV240 for GPU Sequence For HDMI audio issue C C 6 P.37 Change DP Switch IC solution 7 P.35 Add C197 for ESD 8 P.33 Add C198 for ESD 9 P.30 Add C199 for ESD 1 2 P.33 P.38 Reserve R298, R299 for DC-in LED control Change DL1 and DL2 footprint for ESD PVT TO PRE-MP To avoid LED shimmer B B A A Compal Secret Data Security Classification Issued Date 2011/06/15 2012/07/11 Deciphered Date Title Compal Electronics, Inc. HW-PIR1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Rev 1.0 LA-B091P Wednesday, February 12, 2014 Sheet 1 55 of 55 www.s-manuals.com
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.4 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Producer : PlotSoft PDFill 9.0 Modify Date : 2016:03:02 19:29:48+02:00 Create Date : 2014:02:17 05:28:27Z Creator Tool : PScript5.dll Version 5.2.2 Metadata Date : 2016:03:02 19:29:48+02:00 Document ID : d3cae905-99ef-11e3-0000-f8b3ebab048b Instance ID : uuid:14c6ed5b-4a50-4df6-919f-b48d0a01d065 Format : application/pdf Title : Compal LA-B091P - Schematics. www.s-manuals.com. Creator : Subject : Compal LA-B091P - Schematics. www.s-manuals.com. Page Count : 56 Keywords : Compal, LA-B091P, -, Schematics., www.s-manuals.com. Warning : [Minor] Ignored duplicate Info dictionaryEXIF Metadata provided by EXIF.tools