Compal LA B231P Schematics. Www.s Manuals.com. R1.0 Schematics

User Manual: Motherboard Compal LA-B231P Z5WAE - Schematics. Free.

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B

C

D

E

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1

Compal Confidential
2

2

Z5WAE Schematics Document
AMD "Beema" Platform
AMD 25W APU With Puma+ Core and 25W DGPU with Jet

LA-B231P REV: 1.0
2014-03-27

3

3

4

4

2014/03/27

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2016/03/27

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

COVER PAGE
Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
E

1

of

45

A

B

C

D

E

Compal Confidential
Model Name : Z5WAE
1

1

GFX*4

DGPU
JET With DDR3*4
Reserve OPAL With DDR3*8

Port 1

HDMI Conn.

204pin DDRIII-SO-DIMM X2

AMD
Beema

Display Port

Port 0

eDP Conn.

Memory BUS(DDR3) Single Channel

USB2.0

Port 0,1
VGA DAC

AMD FT3b APU

PCIE

MINI Card
(WLAN/BT)

WLAN
BT Combo

Port 5

USB
Camera

Touch
Screen

2

Port 0
Port 8

MB
3.0 Conn.

BGA 769-balls

GPP1
HD Audio(AZ)

LAN+Card Reader
RTL8411B

SATA III

Port 0

3

SPI

Transformer
RJ45

Port 3

USB3.0

Puma+ Core

GPP2

Port 2

Sub/B
2.0 Conn.

2

CRT Conn.

BANK 0, 1, 2

1.5V DDRIII 1600MHz

Card Reader
Conn.

Port 1

3

Audio
ALC283-CG

LPC

HDD/ Colay HDD Cable
Conn.

ODD
Conn.

BIOS (8M)
Share ROM

ENE
KBC9022

Discrete TPM

Sub-borad

Digital MIC

Power/B
Int.KBD

Int. MIC

Int. Speaker
Conn.

Touch Pad

Combo Jacks
4

4

USB/B

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

BLOCK DIAGRAMS
Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
E

2

of

45

5

4

3

2

1

RAM DDRIII SODIMMX2
+1.5V

VDD_MEM 8A

+0.75VS

VTT_MEM 2A

AMD APU FT3 Kabini (25W)

D

D

AC ADAPTOR
19V 65W

B+

VIN

PU201
CHARGER
BQ24725ARGRR

+APU_CORE
PU901
ISL6277HRTZ-T

+0.5~+1.4V

VDDCR_CPU @ 21A(EDC)

+0.7~1.325V

VDDCR_NB @ 17A(EDC)

+1.5V

VDDIO_MEM_S @ 3A

+1.5VS

VDDIO_AZ_ALW @ 0.1A

+APU_CORE_NB

BATT+
+1.5V
BATTERY

PU501
RT8207MZQW

+0.75VS

Q20
LP2301ALT1G

+1.5VS

CRT / HDMI
C

+5VS_DISP

+0.95VALW

+5VS
PU1
SY8208DQNC

HDD x1
ODD x1
+5VS_HDD @ 1.1A
+5VS_ODD @ 2A

Audio
ALC259-VC2-CG
+5VDDA_CODEC
+5VS_PVDD
+3VDD_CODEC
+IOVDD_CODEC

+1.8VS
PU601
SY8033BDBC

+5VS
+3VS
+1.5VS

+3VS

+5VS

USB2.0 x2
USB3.0 x1

U2
TPS22966DPUR

+EC_VCC

+5VALW

+INVPWR_B+
+LCDVDD @ 1.4A

B+
+3VS

+0.95VSDGPU

Mini Card (WLAN)

Issued Date

+5VS_TS

+1.8VALW

VDD_18_ALW @ 0.5A

+3VALW

VDD_33_ALW @ 0.2A

+3VS

VDD_33 @ 0.2A
B

U74
AP2821

+1.8VSDGPU

+RTCBATT
RTC
Bettary

PU101
NCP698SQ15T1G

+3VSDGPU

+VGA_CORE
A

+5VS

Compal Electronics, Inc.

Compal Secret Data
2014/03/27

Deciphered Date

2016/03/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

VDDBT_RTC_G @ 4.5uA

+1.5VSDGPU

Security Classification

Touch Screen

+3VS
+1.5VS

VDD_18 @ 1.5A

VGA JET
PU1201
ISL6288

+3VS

A

+3VS_WLAN @ 2A
+1.5VS

U1895
TPS22966DPUR

HD Camera
+3VS_CMOS

VDD_095_GFX @ 0.6A

+RTC_APU

PU101
TPS51212

+3VALW

VDD_095 @ 5A

+1.8VS

+1.5V_RTC
PU402
SY8208BQNC

C

+5VS

+3VLP
+3VALW

LCD panel
14"

LAN/CR Combo
RTL8411-CG
+3V_LAN @ 1A

+3VALW

PU401
SY8208BQNC

+0.95VS

VDD_095_ALW @ 0.5A

+1.8VALW

EC

FAN

+USB3_VCCA

+0.95VS
U3
TPS22966DPUR

+5VS

B

+VCC_FAN

+0.95VALW

VDD_095_USB3_Dual @ 1A

4

3

2

POWER MAP
Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
1

3

of

45

A

B

C

Power Plane

2

S0

S3

S5

VIN

Adapter power supply (19V)

Description

ON

ON

ON

B+

AC or battery power rail for power circuit.

ON

ON

ON

+APU_CORE

Core voltage for APU

ON

OFF

OFF

+APU_CORE_NB

Voltage for On-die VGA of APU

ON

OFF

OFF

+0.95VALW

0.95V always on power rail

ON

ON

ON

+0.95VS

0.95V switched power rail

ON

OFF

OFF

+1.8VALW

1.8V always on power rail

ON

ON

ON

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+1.5V

1.5V power rail for APU and DDR

ON

ON

OFF

+1.5VS

1.5V switched power rail

ON

OFF

OFF

+0.75VS

0.75V switched power rail for DDR terminator

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON

+5VS

5V switched power rail

ON

OFF

OFF

+RTC_APU

RTC power

ON

OFF

OFF

+3VSDGPU

VGA power

ON

OFF

OFF

+1.8VSDGPU

VGA power

ON

OFF

OFF

+1.5VSDGPU

VGA power

ON

OFF

OFF

+0.95VSDGPU

VGA power

ON

OFF

OFF

+VGA_CORE

VGA power

ON

OFF

OFF

SMBus List
EC SMBus Port1 (+3VALW) EC SMBus Port2 (+3VS)

3

4

E

Board ID / SKU ID Table for AD channel

Voltage Rails

1

D

BOARD ID Table
Board ID
0
1
2
3
4
5
6
7

PCB Revision
EVT
DVT
PVT
1

2

BOM Structure Table

BOM Structure
@
CONN@
Device
Address
HEX
Device
Address
HEX
EMI@
Smart Battery
0001 011X b
SB-TSI (APU)
1001 100X b
16H
98H
@EMI@
ESD@
VGA Temp.
41H
@ESD@
AL@
RS@
JP@
TP@
APU SMBus Port0 (+3VS) APU SMBus Port1(+3VALW)
SP@
Device
Address
HEX
Device
Address
HEX
1DMIC@
2DMIC@
DDR DIMM1
1010 000Xb
A0H
45@
DDR DIMM2
1010 001Xb
A2H
9012@
9022@
Mini Card (DNI)
A6@
E1@
BL@
ZZZ
UAPU1 A6@
ZZZ
UAPU1 E1@
TPM@
X7681@
TPUSB@
TPSM@
APU
PCB
APU
X76550BOL81
Part Number = DA60014I000
Part Number = SA00007RC00
HYN 128M16*4 Part Number = SA00007R900
VGA@
S IC A6-6310 AM6310ITJ44JB 1.8G BGA 769P
PCB 157 LA-B231P REV0 M/B 2
S IC E1-6010 EM6010IUJ23JB 1.35G BGA769P
ZZZ
MARS@
ZZZ
UAPU1 E2@
UAPU1 A4@
JET@
X7682@
128@
X76550BOL82
X76@
HDMI_ROYALTY
APU
MIC 128M16*4
APU
ROYALTY HDMI W/LOGO+HDCP
Part Number = SA00007RB00
Part Number = SA00007RA00
X76XX@
S IC E2-6110 EM6110ITJ44JB 1.5G BGA 769P
ZZZ
S IC A4-6210 AM6210ITJ44JB 1.8G BGA 769P
RO0000003HM

SIGNAL

STATE

BTO Item
Unpop

+VALW

+V

+VS

Clock

HIGH

HIGH

ON

ON

ON

ON

S1(Power On Suspend)

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

ON

OFF

OFF

OFF

Full ON

Connector part control by ME
EMI pop component
EMI unpop component
ESD pop component
ESD unpop component
Auto Load EC ROM
R-short
Jump

SLP_S3# SLP_S5#

APU POWER SEQUENCE

Test point

3

Short pad for clear CMOS
Use 1 DMIC

+RTC

G-A

Use 2 DMIC

EC_ON

HDMI royalty

+3VALW/+5VALW

G-B

Use KBC9012
Use KBC9022

+1.8VALW

Use A6 APU

+0.95VALW

Use E1 APU

SYSON

Keyboard backlight

+1.5V

G-C

Use discrete TPM module

SUSP#

Use USB to I2C IC for T/P

+3VS

G-D

Use APU SMBus for T/P

+1.8VS

Have discrete graphic

+1.5VS

Use Opal

+0.95VS

Use Jet

VR_ON

Dual channel VRAM,pop with MARS@
VRAM type select,control by X76XX@

4

+APU_CORE

G-E

+APU_CORE_NB

VRAM type select, control level X76

45@

X7683@

X76550BOL83
SAM 128M16*4

U44

9022@

U75

re check

JET@

2014/03/27

Issued Date
EC

VGA

Part Number = SA000075S20
Part Number = SA000079010
S IC KB9022QC LQFP 128P EC CONTROLLER, A.3 S IC 216-0856000 A0 JET XT M2 FCBGA ABO!,

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2016/03/27

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

NOTES LIST
Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
E

4

of

45

5

4

3

@
UAPU1A

<10,11> DDRAB_SMA[15..0]

2

1

DDRAB_SDQ[63..0] <10,11>
MEMORY

DDRAB_SMA0 AG38
DDRAB_SMA1 W35
DDRAB_SMA2 W38
DDRAB_SMA3 W34
U38
DDRAB_SMA4
U37
DDRAB_SMA5
U34
DDRAB_SMA6
R35
DDRAB_SMA7
R38
DDRAB_SMA8
N38
DDRAB_SMA9
DDRAB_SMA10 AG34
DDRAB_SMA11 R34
DDRAB_SMA12 N37
DDRAB_SMA13 AN34
DDRAB_SMA14 L38
DDRAB_SMA15 L35

D

AJ38
AG35
N34

<10,11> DDRAB_SBS0#
<10,11> DDRAB_SBS1#
<10,11> DDRAB_SBS2#
<10,11> DDRAB_SDM[7..0]

DDRAB_SDM0
DDRAB_SDM1
DDRAB_SDM2
DDRAB_SDM3
DDRAB_SDM4
DDRAB_SDM5
DDRAB_SDM6
DDRAB_SDM7

C

B33
A33
B40
A40
H41
H40
P41
P40
AH41
AH40
AP41
AP40
BA40
AY41
AY33
BA34
AA40
Y41

<10,11> DDRAB_SDQS0
<10,11> DDRAB_SDQS0#
<10,11> DDRAB_SDQS1
<10,11> DDRAB_SDQS1#
<10,11> DDRAB_SDQS2
<10,11> DDRAB_SDQS2#
<10,11> DDRAB_SDQS3
<10,11> DDRAB_SDQS3#
<10,11> DDRAB_SDQS4
<10,11> DDRAB_SDQS4#
<10,11> DDRAB_SDQS5
<10,11> DDRAB_SDQS5#
<10,11> DDRAB_SDQS6
<10,11> DDRAB_SDQS6#
<10,11> DDRAB_SDQS7
<10,11> DDRAB_SDQS7#

B

<10> DDRA_CLK0
<10> DDRA_CLK0#
<10> DDRA_CLK1
<10> DDRA_CLK1#
<11> DDRB_CLK0
<11> DDRB_CLK0#
<11> DDRB_CLK1
<11> DDRB_CLK1#
<10,11> MEM_MAB_RST#
<10,11> MEM_MAB_EVENT#

<10> DDRA_CKE0
<10> DDRA_CKE1
<11> DDRB_CKE0
<11> DDRB_CKE1
<10> DDRA_ODT0
<10> DDRA_ODT1
<11> DDRB_ODT0
<11> DDRB_ODT1
<10> DDRA_SCS0#
<10> DDRA_SCS1#
<11> DDRB_SCS0#
<11> DDRB_SCS1#
A

B32
B38
G40
N41
AG40
AN41
AY40
AY34
Y40

<10,11> DDRAB_SRAS#
<10,11> DDRAB_SCAS#
<10,11> DDRAB_SWE#
+MEM_VREF
T33

M_ADD0
M_ADD1
M_ADD2
M_ADD3
M_ADD4
M_ADD5
M_ADD6
M_ADD7
M_ADD8
M_ADD9
M_ADD10
M_ADD11
M_ADD12
M_ADD13
M_ADD14
M_ADD15

M_BANK0
M_BANK1
M_BANK2

M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7
M_DM8

M_DQS_H0
M_DQS_L0
M_DQS_H1
M_DQS_L1
M_DQS_H2
M_DQS_L2
M_DQS_H3
M_DQS_L3
M_DQS_H4
M_DQS_L4
M_DQS_H5
M_DQS_L5
M_DQS_H6
M_DQS_L6
M_DQS_H7
M_DQS_L7
M_DQS_H8
M_DQS_L8

AC35
AC34
AA34
AA32
AE38
AE37
AA37
AA38

M_CLK_H0
M_CLK_L0
M_CLK_H1
M_CLK_L1
M_CLK_H2
M_CLK_L2
M_CLK_H3
M_CLK_L3

G38
AE34

M_RESET_L
M_EVENT_L

L34
J38
J37
J34

M0_CKE0
M0_CKE1
M1_CKE0
M1_CKE1

AN38
AU38
AN37
AR37

M0_ODT0
M0_ODT1
M1_ODT0
M1_ODT1

AJ34
AR38
AL38
AN35

M0_CS_L0
M0_CS_L1
M1_CS_L0
M1_CS_L1

AJ37
AL34
AL35

M_RAS_L
M_CAS_L
M_WE_L

AD40
APU_VREFDQ AC38

M_VREF
M_VREFDQ

M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7

M_DATA8
M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15

M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23

M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31

M_DATA32
M_DATA33
M_DATA34
M_DATA35
M_DATA36
M_DATA37
M_DATA38
M_DATA39

B30
A32
B35
A36
B29
A30
A34
B34

DDRAB_SDQ0
DDRAB_SDQ1
DDRAB_SDQ2
DDRAB_SDQ3
DDRAB_SDQ4
DDRAB_SDQ5
DDRAB_SDQ6
DDRAB_SDQ7

B37
A38
D40
D41
B36
A37
B41
C40

DDRAB_SDQ8
DDRAB_SDQ9
DDRAB_SDQ10
DDRAB_SDQ11
DDRAB_SDQ12
DDRAB_SDQ13
DDRAB_SDQ14
DDRAB_SDQ15

F40
F41
K40
K41
E40
E41
J40
J41

DDRAB_SDQ16
DDRAB_SDQ17
DDRAB_SDQ18
DDRAB_SDQ19
DDRAB_SDQ20
DDRAB_SDQ21
DDRAB_SDQ22
DDRAB_SDQ23

M41
N40
T41
U40
L40
M40
R40
T40

DDRAB_SDQ24
DDRAB_SDQ25
DDRAB_SDQ26
DDRAB_SDQ27
DDRAB_SDQ28
DDRAB_SDQ29
DDRAB_SDQ30
DDRAB_SDQ31

AF40
AF41
AK40
AK41
AE40
AE41
AJ40
AJ41

DDRAB_SDQ32
DDRAB_SDQ33
DDRAB_SDQ34
DDRAB_SDQ35
DDRAB_SDQ36
DDRAB_SDQ37
DDRAB_SDQ38
DDRAB_SDQ39

M_DATA40
M_DATA41
M_DATA42
M_DATA43
M_DATA44
M_DATA45
M_DATA46
M_DATA47

AM41 DDRAB_SDQ40
AN40 DDRAB_SDQ41
AT41 DDRAB_SDQ42
AU40 DDRAB_SDQ43
AL40 DDRAB_SDQ44
AM40 DDRAB_SDQ45
AR40 DDRAB_SDQ46
AT40 DDRAB_SDQ47

M_DATA48
M_DATA49
M_DATA50
M_DATA51
M_DATA52
M_DATA53
M_DATA54
M_DATA55

AV41 DDRAB_SDQ48
AW40 DDRAB_SDQ49
BA38 DDRAB_SDQ50
AY37 DDRAB_SDQ51
AU41 DDRAB_SDQ52
AV40 DDRAB_SDQ53
AY39 DDRAB_SDQ54
AY38 DDRAB_SDQ55

M_DATA56
M_DATA57
M_DATA58
M_DATA59
M_DATA60
M_DATA61
M_DATA62
M_DATA63

BA36
AY35
BA32
AY31
BA37
AY36
BA33
AY32

M_CHECK0
M_CHECK1
M_CHECK2
M_CHECK3
M_CHECK4
M_CHECK5
M_CHECK6
M_CHECK7

V41
W40
AB40
AC40
U41
V40
AA41
AB41

M_ZVDDIO_MEM_S

AD41

@
UAPU1B
PCIE

D

R10
R8

<23> PCIE_ARX_DTX_P1
<23> PCIE_ARX_DTX_N1
<26> PCIE_ARX_DTX_P2
<26> PCIE_ARX_DTX_N2
+0.95VS_APU_GFX
2

P_TX_ZVDD_095 W8

1

R404
1.69K_0402_1%

P_GPP_RXP1
P_GPP_RXN1

P_GPP_RXP2
P_GPP_RXN2

LAN

K2
P_GPP_TXP1
P_GPP_TXN1 K1

PCIE_ATX_DRX_P1 C19 1
PCIE_ATX_DRX_N1 C20 1

2
2

.1U_0402_16V7K
.1U_0402_16V7K

WLAN

J2
P_GPP_TXP2
J1
P_GPP_TXN2

PCIE_ATX_DRX_P2 C17 1
PCIE_ATX_DRX_N2 C18 1

2
2

.1U_0402_16V7K
.1U_0402_16V7K

P_GPP_TXP3 H2
H1
P_GPP_TXN3

P_GPP_RXP3
P_GPP_RXN3

P_TX_ZVDD_095

P_RX_ZVDD_095

PEG_ATX_GRX_P0
PEG_ATX_GRX_N0

J5
J4

P_GFX_RXP1
P_GFX_RXN1

P_GFX_TXP1 F2
F1
P_GFX_TXN1

PEG_ATX_GRX_P1
PEG_ATX_GRX_N1

PEG_GTX_C_ARX_P2
PEG_GTX_C_ARX_N2

G5
G4

P_GFX_RXP2
P_GFX_RXN2

P_GFX_TXP2 E2
E1
P_GFX_TXN2

PEG_ATX_GRX_P2
PEG_ATX_GRX_N2

PEG_GTX_C_ARX_P3
PEG_GTX_C_ARX_N3

D7
E7

P_GFX_RXP3
P_GFX_RXN3

D2
P_GFX_TXP3
D1
P_GFX_TXN3

PEG_ATX_GRX_P3
PEG_ATX_GRX_N3

PEG_GTX_C_ARX_P1
PEG_GTX_C_ARX_N1

1
R73
1K_0402_1%

C

B

MEMORY VREF
+MEM_VREF

+1.5V
RP2
8
7
6
5

1
2
3
4

MEM_MAB_EVENT#

2

1

2

1

1K_0804_8P4R_1%

C337
1U_0402_6.3V6K

1

C163
.1U_0402_16V7K

2
+1.5V
R74
39.2_0402_1%

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

PCIE_ATX_C_DRX_P2 <26>
PCIE_ATX_C_DRX_N2 <26>

PEG_ATX_GRX_P[0..3] <12>
PEG_ATX_GRX_N[0..3] <12>

FT3_BGA_769P-T_A39
Part Number =

Date:

5

2

P_RX_ZVDD_095

G2
P_GFX_TXP0
P_GFX_TXN0 G1

L5
L4

PCIE_ATX_C_DRX_P1 <23>
PCIE_ATX_C_DRX_N1 <23>

+0.95VS_APU_GFX

W7

P_GFX_RXP0
P_GFX_RXN0

PEG_GTX_C_ARX_P0
PEG_GTX_C_ARX_N0

<12> PEG_GTX_C_ARX_P[0..3]
<12> PEG_GTX_C_ARX_N[0..3]

Issued Date
FT3_BGA_769P-T_A39
Part Number =

N5
N4

N10
N8

DDRAB_SDQ56
DDRAB_SDQ57
DDRAB_SDQ58
DDRAB_SDQ59
DDRAB_SDQ60
DDRAB_SDQ61
DDRAB_SDQ62
DDRAB_SDQ63

M_ZVDDIO

R5
R4

L2
P_GPP_TXP0
L1
P_GPP_TXN0

P_GPP_RXP0
P_GPP_RXN0

3

2

P05-FT3 MEMORY INTERFACE/PCIE
Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
1

5

of

45

A

B

C

D

E

@
UAPU1C
DISPLAY/SVI2/JTAG/TEST

A9 TDP1_TXP0
B9 TDP1_TXN0

<21> APU_DP1_P0
<21> APU_DP1_N0

A10 TDP1_TXP1
B10 TDP1_TXN1

<21> APU_DP1_P1
<21> APU_DP1_N1

HDMI

A11 TDP1_TXP2
B11 TDP1_TXN2

<21> APU_DP1_P2
<21> APU_DP1_N2

1

DP_150_ZVSS
DP_2K_ZVSS
DP_BLON
DP_DIGON
DP_VARY_BL

TDP1_AUXP
TDP1_AUXN

A12 TDP1_TXP3
B12 TDP1_TXN3

<21> APU_DP1_P3
<21> APU_DP1_N3
<19> EDP_TXP0
<19> EDP_TXN0

<19> EDP_TXP1
<19> EDP_TXN1

TDP1_HPD

A5 LTDP0_TXP1
B5 LTDP0_TXN1

LTDP0_HPD

H17

DAC_RED

B14

R674 1
R669 1
R670 1

2 33_0402_5% APU_SVT_R
2 33_0402_5% APU_SVC_R
2 33_0402_5% APU_SVD_R

2

<39> APU_PWRGD
<22,39,7> PROCHOT#

R117 1 RS@

2 0_0402_5%

APU_RST#
LDT_RST#

B20 APU_RST_L
A20 LDT_RST_L

R118 1 RS@

2 0_0402_5%

APU_PWRGD
LDT_PWRGD

B19 APU_PWROK
A19 LDT_PWROK

R120 1 RS@

2 0_0402_5%

D29
D31
D35
D33
G27
B25
A25

D23
G23
E25
E23

<39> APU_VDDNB_SEN
<39> APU_VDD_SEN

<39> APU_VDD_RUN_FB_L

TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L

A14

DAC_BLUE

B15

DAC_HSYNC
DAC_VSYNC

G19
E19

DAC_SCL
DAC_SDA

D19
D21

DAC_ZVSS

A16

1

HDMI_HPD <21>

EDP_AUXP <19>
EDP_AUXN <19>

RP23

DAC_RED <20>

150_0804_8P4R_1%

DAC_GRN <20>

CRT

DAC_BLU <20>

DAC_HSYNC <20>
DAC_VSYNC <20>

DAC_ZVSS

FREE_2
GIO_TSTDTM0_SERIALCLK
GIO_TSTDTM0_CLKINIT

A29 APU_TEST34_L
H21 APU_TEST36
H25 APU_TEST37

USB_ATEST0
USB_ATEST1
M_ANALOGIN
M_ANALOGOUT
TMON_CAL

HDMI_EN/DP_STEREOSYNC

DAC_HSYNC

AJ10
AJ8
R32
N32
AP29

APU_TEST42
APU_TEST43
APU_TEST39
APU_TEST40
APU_TEST41

E21

APU_TEST35

2 499_0402_1%

R416 1

T13
T14

1K_0804_8P4R_5%

1
1

2 511_0402_1%
2 511_0402_1%

8
7
6
5

1
2
3
4

APU_ALERT#
EC_SMB_DA2
APU_PROCHOT#
EC_SMB_CK2

Close To APU's Pin

1K_0804_8P4R_5%

4

PU +1.8VS

T4
T5
T6
T7

APU_RST#
APU_PWRGD

R80
R82

1
1

1
APU_PWRGD
C1270
1
APU_RST#
C1273
APU_PROCHOT# 1
C1276
1
APU_ALERT#
C1277

2
ESD@
10P_0402_50V8J
2
ESD@
10P_0402_50V8J
2
@ESD@
100P_0402_50V8J
2
@ESD@
100P_0402_50V8J

1K_0804_8P4R_5%
T10
T8
T9
T11
T12

APU_TEST35 R114 1

@

2 1K_0402_5%

HDT+

+1.8VS

3

JHDT1 @

7

APU_TRST# 1 @ESD@ 2
APU_TRST#_R
R666
0_0402_5%
HDT_P11
RP11
8
1
7
2
HDT_P13
6
3
5
4
HDT_P15
10K_0804_8P4R_5%

9
11
13
15
17
19

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

2

18

1 @ESD@ 2
APU_TCK
R664
0_0402_5%
1 @ESD@ 2
APU_TMS
R663
0_0402_5%
1 @ESD@ 2
APU_TDI
APU_TDI_R
R662
0_0402_5%
1 @ESD@ 2
APU_TDO
APU_TDO_R
R671
0_0402_5%
APU_PWRGD
APU_PWRGD_R 1 @ESD@ 2
R667
0_0402_5%
1 @ESD@ 2
APU_RST#
APU_RST#_R
R672
0_0402_5%
APU_DBRDY
APU_DBRDY_R 1 @ESD@ 2
R673
0_0402_5%
APU_DBREQ#
APU_DBREQ#_R 1 @ESD@ 2
R665
0_0402_5%
APU_TEST19

20

APU_TEST18

4
6
8
10
12
14
16

APU_TCK_R

+1.8VS

APU_TMS_R

RP6

APU_TDI
APU_TMS
APU_TCK
APU_DBREQ#

8
7
6
5

1
2
3
4

1K_0804_8P4R_5%

+1.8VS

RP8

APU_TRST#
APU_TEST19
APU_TEST18

8
7
6
5

1
2
3
4

1K_0804_8P4R_5%
4

SAMTE_ASP-136446-07-B

8
7
6
5

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

1K_0804_8P4R_5%
2 300_0402_5%
2 300_0402_5%

2014/03/27

Deciphered Date

2016/03/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

8
7
6
5

1
2
3
4

APU_TEST36
APU_TEST37
APU_TEST36
APU_TEST37

+1.8VS

@
RP5

1
2
3
4

APU_SVT_R
APU_SVC_R
APU_SVD_R

2
@ESD@
100P_0402_50V8J

+1.8VS

@
RP3

1

1
APU_PWRGD
C1272

8
7
6
5

1
2
3
4

APU_TEST16
APU_TEST17
APU_TEST14
APU_TEST15

+1.8VS
R19
R18

FT3_BGA_769P-T_A39
Part Number =

Close To PU801

2

@
RP7

5

+3VS

2 1K_0402_5%
2 1K_0402_5%

R115 1
R113 1

@
NOTE:
DAC_HSYNC
PU FOR HDMI ENABLE
PD FOR CUSTOMER (DNI)

DAC_DDC_CLK <20>
DAC_DDC_DATA <20>

3

RP4

8
7
6
5

1
2
3
4

DAC_RED
DAC_GRN
DAC_BLU

EDP_HPD <19>

H27 APU_TEST4
H29 APU_TEST5
D25
A27 APU_TEST14
B27 APU_TEST15
A26 APU_TEST16
B26 APU_TEST17
B28 APU_TEST18
A28 APU_TEST19
B24 APU_TEST25_H
A24 APU_TEST25_L
AV35 APU_TEST28_H
AU35 APU_TEST28_L
E33 APU_TEST31

VDDCR_NB_SENSE
VDDCR_CPU_SENSE
VDDIO_MEM_S_SENSE
VSS_SENSE

AV33 VDD_095_FB_H
AU33 VDD_095_FB_L

HDMI_CLK <21>
HDMI_DATA <21>

THERMDA
THERMDC
DIECRACKMON
BP0
BP1
BP2
BP3
PLLTEST1
PLLTEST0
BYPASSCLK_H
BYPASSCLK_L
PLLCHRZ_H
PLLCHRZ_L
M_TEST

APU_PROCHOT# A22 PROCHOT_L
B18 ALERT_L
APU_ALERT#

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

3

G31 SVT
D27 SVC
E29 SVD

B22 SIC
B21 SID

<13,22> EC_SMB_CK2
<13,22> EC_SMB_DA2

ENBKL <22>
ENVDD <19>
INVTPWM <19>

+3VS

K15 DISP_CLKIN_H
H15 DISP_CLKIN_L

<39> APU_SVT
<39> APU_SVC
<39> APU_SVD

DAC_GREEN

2 150_0402_1%
2 2K_0402_1%

R401 1
R400 1

H19

LTDP0_AUXP D15
LTDP0_AUXN E15

A7 LTDP0_TXP3
B7 LTDP0_TXN3

DP_150_ZVSS
DP_2K_ZVSS

D17
E17

A4 LTDP0_TXP0
B4 LTDP0_TXN0

A6 LTDP0_TXP2
B6 LTDP0_TXN2

eDP

B16
A21
B17
A17
A18

B

C

D

FT3 DISP/MISC/HDT
Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
E

6

of

45

A

B

2
150P_0402_50V8J

1
C615

C

D

E

@
UAPU1D
ACPI/SD/AZ/GPIO/RTC/MISC

AY5 RSMRST_L

BA8
AM19
AY7
APU_PCIE_W AKE# AW11

AY3 SLP_S3_L
BA5 SLP_S5_L

<22> SLP_S3#
<22> SLP_S5#

2 15K_0402_5% APU_TEST0
2 15K_0402_5% APU_TEST1
2 15K_0402_5% APU_TEST2

1
1
1

R40
R41
R42

<22> KBRST#
<22> GATEA20
<22> EC_SCI#
<22> EC_SMI#

LAN_CLKREQ#
W LAN_CLKREQ#

<23> LAN_CLKREQ#
<26> W LAN_CLKREQ#

T21

USB_OC0#
USB_OC1#

<28> USB_OC0#

T19
T20
2

HDA_BITCLK
HDA_SDOUT
HDA_SDIN0

<25> HDA_SDIN0

HDA_SYNC
HDA_RST#

AU13 TEST0
AY10 TEST1/TMS
AY6 TEST2

AR23
AR31
AN5
AL7

KBRST_L
GA20IN/GEVENT0_L
LPC_PME_L/GEVENT3_L
LPC_SMI_L/GEVENT23_L

AP15
AV13
BA9
BA10
AV15

AC_PRES/IR_RX0/GEVENT16_L
IR_TX0/GEVENT21_L
IR_TX1/GEVENT6_L
IR_RX1/GEVENT20_L
IR_LED_L/LLB_L/GPIO184

AU29
AW29
AR27
AV27
AY29

AY8
AW1
AV1
AY1

USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L
USB_OC1_L/TDI/GEVENT13_L
USB_OC2_L/TCK/GEVENT14_L
USB_OC3_L/TDO/GEVENT15_L

AN2
AN1
AK2
AK1
AM1
AL2
AM2
AL1

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST_L

AJ2 X32K_X1

32K_X2

AJ1 X32K_X2

SD_CMD/GPIO74
SD_CD/GPIO75
SD_W P/GPIO76

AY23
AY20
BA20

SD_DATA0/GPIO77
SD_DATA1/GPIO78
SD_DATA2/GPIO79
SD_DATA3/GPIO80

BA22
AY21
AY24
BA24

SD_LED/GPIO45

AY25

AU25 APU_SCLK0
AV25 APU_SDATA0

SCL1/GPIO227
SDA1/GPIO228

AY11 APU_SCLK1
BA11 APU_SDATA1

AV17 GEVENT2#
BA4 GEVENT4#
AR15
AP17
AP11
AN8
AU17
BA6

GENINT1_L/GPIO32
GENINT2_L/GPIO33

BA29
AP23

FANOUT0/GPIO52
FANIN0/GPIO56

AV31
AU31

AV11

RTCCLK

8
7
6
5

APU_SCLK0 <10,11,26>
APU_SDATA0 <10,11,26>
APU_SCLK1 <29>
APU_SDATA1 <29>

AP27
R691 1
AY28
BA28 APU_GPIO51
AV23
AP21
BA26
AV19
AY27
PE_GPIO0
BA27
AU21
PE_GPIO1
AY26
AV21
AM21 APU_GPIO71 R661 1
BA3 APU_GPIO174 R686 1

GEVENT2_L
GEVENT4_L
GEVENT7_L
GEVENT10_L
GEVENT11_L
GEVENT17_L
BLINK/GEVENT18_L
GEVENT22_L

+3VS

PU at T/P side

R693
10K_0402_5%

2 10K_0402_5%

DEVSLP0 <27>

APU_GPIO51
R692 @
10K_0402_5%

PE_GPIO0 <12>
APU_SPKR <25>
PE_GPIO1 <16>
@

2 0_0402_5%
2 10K_0402_5%

PROCHOT# <22,39,6>

2 10K_0402_5%
2 10K_0402_5%

R687 1
R689 1

1

GEVENT4#

2
@
R668
0_0402_5%

2

VGA_PW RGD <16,41,42>

RTC_CLK

LPC_FRAME#

HDA_RST#
HDA_SYNC
HDA_SDOUT
HDA_BITCLK

LPC_CLK0_EC

LPC_CLK1

GEVENT2_L

H

SPI ROM
(DEFAULT)

BOOT FAIL TIMER
ENABLED

CLKGEN
ENABLE
(DEFAULT)

1.8V SPI ROM

NORMAL POWR
UP/RESET TIMING
(DEFAULT)

RTC_CLK

L

LPC ROM

BOOT FAIL TIMER
DISABLED
(DEFAULT)

CLKGEN
DISABLED

3.3V SPI ROM
(DEFAULT)

FAST POWER
UP/RESET TIMING
FOR SIMULATION

+3VALW
+1.8VALW

R345
47K_0402_5%

C212
1U_0402_6.3V6K

1

C948
.1U_0402_16V7K
@ESD@

1

1

32K_X1

@
R903
2K_0402_5%

1

2

2

SJ100001K00 Y3
32.768KHZ_12.5PF_CM31532768DZFT

2

1
2

2

1

GEVENT2#
RTC_CLK

32K_X2

@
R927
2K_0402_5%

R926
2K_0402_5%

1

2

@
R950
2.2K_0402_5%

R929
2K_0402_5%

4

2

2

R949
10K_0402_5%

<22,27,8> LPC_FRAME#
<22,8> LPC_CLK0_EC
<27,8> LPC_CLK1

2

1

1

@
R928
10K_0402_5%

R925
10K_0402_5%

2

C209
1U_0402_6.3V6K

1

1

1

SYS_PW RGD_EC

32.768KMHz CRYSTAL

@
R904
10K_0402_5%

R902
10K_0402_5%

RB751 Max Vf=0.37V

2

HDA_BITCLK
HDA_SDIN0

EC_RSMRST#_R

1

2 10K_0402_5%
2 10K_0402_5%

2
1
D3
RB751V-40 SOD-323

<22> EC_RSMRST#

1

@
@

APU_SCLK0
APU_SDATA0

2

R684 1
R688 1

2 2.2K_0402_5%
2 2.2K_0402_5%

R914
20M_0402_5%

1

2

1
C686
18P_0402_50V8J

2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

C682
18P_0402_50V8J

2014/03/27

Deciphered Date

2016/03/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

3

+3VALW

2

R676 1
R677 1

1

+3VS

R685
10K_0402_5%

1

APU_PCIE_W AKE#
USB_OC0#
USB_OC1#
EC_LID_OUT#

2

100K_0402_5%
100K_0402_5%
100K_0402_5%
1K_0402_5%

1

@
@

2
2
2
2

2

@

2

1
1
1
1

2

R901
R905
R906
R675

4

TP_I2C_INT#_APU <29>

T17
EC_LID_OUT# <22>

33_0804_8P4R_5%
3

UMA: LOW
DIS: HIGH

STRAPS OF APU

FT3_BGA_769P-T_A39
Part Number =

1
2
3
4

1

SCL0/GPIO43
SDA0/GPIO47

GPIO49
GPIO50
GPIO51
GPIO55
GPIO57
GPIO58
GPIO59
GPIO64
SPKR/GPIO66
GPIO68
GPIO69
GPIO70
GPIO71
GPIO174

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60
CLK_REQ1_L/GPIO61
CLK_REQ2_L/GPIO62
CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63
CLK_REQG_L/GPIO65/OSCIN

32K_X1

EMI@
RP13

<25> HDA_RST#_AUDIO
<25> HDA_SYNC_AUDIO
<25> HDA_SDOUT_AUDIO
<25> HDA_BITCLK_AUDIO

PW R_BTN_L
PW R_GOOD
SYS_RESET_L/GEVENT19_L
W AKE_L/GEVENT8_L

BA23
AY22

2

1

EC_RSMRST#_R

SD_PW R_CTRL
SD_CLK/GPIO73

1

T16

<23> APU_PCIE_W AKE#

AY4 LPC_RST_L
AY9 PCIE_RST_L

2

2
150P_0402_50V8J

1
C912

<22> PBTN_OUT#
<22> SYS_PW RGD_EC

LPC_RST_A#
APU_PCIE_RST#_R

1

2 33_0402_5%
2 33_0402_5%

R602 1
R907 1

<22,27> LPC_RST#
<12,23,26> APU_PCIE_RST#

C

D

Title

FT3 GPIO/AZ/MISC/STRAPS
Size
Document Number
Custom

Rev
1.0

Z5WAE LA-B231P

Date:

Thursday, March 27, 2014

Sheet
E

7

of

45

A

B

C

D

E

@
UAPU1E
CLK/SATA/USB/SPI/LPC

BA14
AY14

<27> SATA_FTX_DRX_P0
<27> SATA_FTX_DRX_N0

HDD

1

<27> SATA_FRX_DTX_N0
<27> SATA_FRX_DTX_P0
<27> SATA_FTX_DRX_P1
<27> SATA_FTX_DRX_N1

ODD

2
2

R90
R96

+0.95VS

2

+3VS

BA16
AY16

SATA_RX0N
SATA_RX0P

AY19
BA19

SATA_TX1P
SATA_TX1N

AY17
BA17

<27> SATA_FRX_DTX_N1
<27> SATA_FRX_DTX_P1
1 1K_0402_1% SATA_ZVSS
1 1K_0402_1% SATA_ZVDD

1
@
R633
10K_0402_5%

SATA_ACT#

SATA_TX0P
SATA_TX0N

USBCLK/14M_25M_48M_OSC

USB_ZVSS AG4

SATA_ZVSS
SATA_ZVDD_095

BA30

SATA_ACT_L/GPIO67

AY12

SATA_X1

USB_HSD1P
USB_HSD1N

AJ4
AJ5

USB_HSD2P
USB_HSD2N

AG7
AG8

USB_HSD3P
USB_HSD3N

AG1
AG2

USB_HSD4P
USB_HSD4N

AF1
AF2

USB_HSD5P
USB_HSD5N

USB_HSD6P
USB_HSD6N

AD1
AD2

GFX_CLKP
GFX_CLKN

USB_HSD7P
USB_HSD7N

AC1
AC2

AC8
AC10

GPP_CLK0P
GPP_CLK0N

USB_HSD8P
USB_HSD8N

AB1
AB2

VGA

2

AE4
AE5

GPP_CLK1P
GPP_CLK1N

USB_HSD9P
USB_HSD9N

AA1
AA2

U4
U5

<12> CLK_PEG_VGA
<12> CLK_PEG_VGA#

LAN

<23> CLK_PCIE_LAN
<23> CLK_PCIE_LAN#

WLAN

<26> CLK_PCIE_WLAN
<26> CLK_PCIE_WLAN#

AC4
AC5

AA5
AA4

AP13

48M_X1

R103 1 RS@
R104 1 RS@

<22,27> LPC_AD0
<22,27> LPC_AD1
<22,27> LPC_AD2
<22,27> LPC_AD3
<22,27,7> LPC_FRAME#

3

<22,27> SERIRQ
<27> CLKRUN#
<27> LPCPD#

48MHz CRYSTAL

USB_SS_ZVSS AE10
AE8
USB_SS_ZVDD_095_USB3_DUAL

2

2

USB/B port 0

USB20_P1 <28>
USB20_N1 <28>

USB/B port 1

USB20_P2 <26>
USB20_N2 <26>

WLAN/BT combo

USB20_P3 <19>
USB20_N3 <19>

CAMERA

USB20_P5 <19>
USB20_N5 <19>

Touch Screen

USB20_P6 <29>
USB20_N6 <29>

USB to I2C bridge

USB20_P8 <28>
USB20_N8 <28>

MB USB3.0 port0 (2.0)

2 1K_0402_1%
2 1K_0402_1%

USBSS_ZVSS R644 1
USBSS_ZVDD R645 1

X14M_25M_48M_OSC

V2
USB_SS_0RXP
USB_SS_0RXN V1

USB3_FRX_DTX_P0 <28>
USB3_FRX_DTX_N0 <28>

X48M_X1

2 0_0402_5% AY2
2 0_0402_5% AW2

LPCCLK0
LPCCLK1

Port 4-7 USB OHCI2 ( Dev 13 Func 0 )
EHCI2 ( Dev 13 Func 2 )

2

USB2.0 Only
Port 8-9 USB OHCI2 ( Dev 16 Func 0 )
EHCI2 ( Dev 16 Func 2 )
USB3.0
Port 0-1 USB XHCI

( Dev 10 Func 0 )

USB_SS_1TXP R1
R2
USB_SS_1TXN

USB_SS_1RXP W1
W2
USB_SS_1RXN

SPI_CLK/GPIO162
SPI_CS1_L/GPIO165
SPI_CS2_L/GPIO166
SPI_DO/GPIO163
SPI_DI/GPIO164
SPI_HOLD_L/GEVENT9_L
SPI_WP_L/GPIO161

LAD0
LAD1
LAD2
LAD3
LFRAME_L
LDRQ0_L
SERIRQ/GPIO48
LPC_CLKRUN_L
LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L

AU7
AW9
AR4
AR11
AR7
AU11
AU9

APU_SPI_CLK_R R105 1 RS@
APU_SPI_CS1#
T37
APU_SPI_MOSI
APU_SPI_MISO
APU_SPI_HOLD#
APU_SPI_WP#

2 0_0402_5% APU_SPI_CLK R1676 1 RS@
R1677 1 RS@

2 0_0402_5%
2 0_0402_5%

R1678 1 RS@
R1679 1 RS@

2 0_0402_5%
2 0_0402_5%

EC_SPI_CLK <22>
EC_SPI_CS1# <22>

EC_SPI_MOSI <22>
EC_SPI_MISO <22>

3

8MB SPI ROM

FT3_BGA_769P-T_A39
Part Number =

+3VALW

+3VALW

48M_X1

2
1
C635 @
.1U_0402_16V7K

RP12
8
7
6
5

1
2
3
4
1

1

Port 0-3 USB OHCI1 ( Dev 12 Func 0 )
EHCI1 ( Dev 12 Func 2 )

+0.95VALW

USB3_FTX_DRX_P0 <28>
USB3_FTX_DRX_N0 <28>

48M_X2
2
1 R938
1M_0402_5%

USB20_P0 <28>
USB20_N0 <28>

T2
USB_SS_0TXP
USB_SS_0TXN T1

X48M_X2

AT2
AT1
AR2
AR1
AP2
AP1
AV29
AP25
AV2

2 11.8K_0402_1%

GPP_CLK3P
GPP_CLK3N

N1

48M_X2

<22,7> LPC_CLK0_EC
<27,7> LPC_CLK1

N2

GPP_CLK2P
GPP_CLK2N

R641 1

AE1
AE2

SATA_X2

BA12

USB_ZVSS

AL4
USB_HSD0P
AL5
USB_HSD0N

SATA_RX1N
SATA_RX1P

AR19
AP19

W4

APU_SPI_CS1#
APU_SPI_WP#
APU_SPI_HOLD#

U56

APU_SPI_CS1#
APU_SPI_MISO
APU_SPI_WP#

1

10K_0804_8P4R_5%

1
2
3
4

VCC
CS#
DO(IO1) HOLD#(IO3)
CLK
WP#(IO2)
DI(IO0)
GND

8
7
6
5

APU_SPI_HOLD#
APU_SPI_CLK
APU_SPI_MOSI

EN25QH64-104HIP_SO8
2
2
1
APU_SPI_CLK1
R617 @EMI@ C636
@EMI@
10_0402_5%
10P_0402_50V8J

Y1
48MHZ_8PF_X3S048000D81H-W
Part Number = SJ10000AF00

4

3

Issued Date

C794
6P_0402_50V8D

C795
6P_0402_50V8D

Compal Electronics, Inc.

Compal Secret Data

Security Classification

4

2

1
2

4

1

3

2014/03/27

Deciphered Date

2016/03/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

4

D

FT3 SATA/CLK/USB/SPI
Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
E

8

of

45

A

B

C

D

E

CORE POWER OF APU
VDDCR_CPU

+APU_CORE

1

1

180P_0402_50V8J

1U_0402_6.3V6K

2

C190

C189

2

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C188

1

C187

2

1U_0402_6.3V6K

2

1

C186

1

1U_0402_6.3V6K

2

C184

2

1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C183

1

C182

C181

1U_0402_6.3V6K

1U_0402_6.3V6K

2

C180

C179

1

1

2

1

2

1

@

INTEGRATED GPU POWER OF APU

+3VALW/+3VS OF APU

VDD_33

1

180P_0402_50V8J

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

180P_0402_50V8J

180P_0402_50V8J

2

C256

1

2

C255

1

2

C254

C232

C161

C258

1

2

1

2

1

1

1

180P_0402_50V8J

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

180P_0402_50V8J

2

C233

1

2

C240

1

2

C239

1

2

C237

1

2

C238

1

2

C236

1

2

VDD_18

+1.8VS

C933

L22
2
1
FBMA-L11-201209-121LMA50T_0805

C203

1

2

+0.95VS_APU_GFX

C950

C213

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

@

1

2

C260

1

2

1

2

+1.8VALW/+1.8VS OF APU

VDD_095_GFX
C206

C204

1

2

C205

1

2

C199

1

2

C198

C934

C935

3

1

2

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

.1U_0402_16V7K

1U_0402_6.3V6K

VDD_095

1

2

2

1

2

2

1

2

C946
.1U_0402_16V7K
@ESD@

1

C947
.1U_0402_16V7K
@ESD@

1

2

180P_0402_50V8J

1U_0402_6.3V6K

2

1

C245

1U_0402_6.3V6K

2

1U_0402_6.3V6K

2

1

C248

1

C246

2

1U_0402_6.3V6K

4.7U_0603_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

@

VDD_095_ALW

1

C250

1

2

C244

1

2

C160

1

2

C217

1U_0402_6.3V6K

1U_0402_6.3V6K

@

1

2

C222

1

2

C220

1U_0402_6.3V6K

180P_0402_50V8J

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

@

VDD_095_USB3_DUAL

1

2

C219

1

2

C221

1

2

C218

C216

1

2

C214

C937

C938

1

2

1

L13
L17
N11
N13
N17
R11
R13
R17
U13
U17
W13
W17
AA13
AA17
AC13
AC17
AE15
AE17
AE19
AG17
AG21

2

VDDCR_NB_1
VDDCR_NB_2
VDDCR_NB_3
VDDCR_NB_4
VDDCR_NB_5
VDDCR_NB_6
VDDCR_NB_7
VDDCR_NB_8
VDDCR_NB_9
VDDCR_NB_10
VDDCR_NB_11
VDDCR_NB_12
VDDCR_NB_13
VDDCR_NB_14
VDDCR_NB_15
VDDCR_NB_16
VDDCR_NB_17
VDDCR_NB_18
VDDCR_NB_19
VDDCR_NB_20
VDDCR_NB_21

+APU_CORE

R119
0_0402_5%
RS@

+APU_CORE_NB

AL10
AL11

B1
B2

VDD_18_ALW_1
VDD_18_ALW_2

VDD_18_1
VDD_18_2
VDD_18_3
VDD_18_4

A2
A3
B3
C3

+3VALW

AL13
AM13

VDD_33_ALW_1
VDD_33_ALW_2

VDD_33_1
VDD_33_2

AM15
AM17

+3VS

+0.95VALW

AR5
AU4
AV7
AW5

VDD_095_USB3_DUAL_1
VDD_095_USB3_DUAL_2
VDD_095_USB3_DUAL_3
VDD_095_USB3_DUAL_4

AE11
AE13
AJ11
AJ13

VDD_095_ALW_1
VDD_095_ALW_2
VDD_095_ALW_3
VDD_095_ALW_4

AG23
AG27
AJ21
AJ27
AL21
AL23
AL27
AM23
AM25

+0.95VS

+0.95VALW

VDD_095_1
VDD_095_2
VDD_095_3
VDD_095_4
VDD_095_5
VDD_095_6
VDD_095_7
VDD_095_8
VDD_095_9

VDD_095_GFX_1
VDD_095_GFX_2
VDD_095_GFX_3

U10
W10
AA10

+0.95VALW
+1.8VALW

L21
L23
L25
L27
L29
N21
N23
N27
R21
R23
R27
U21
U23
U27
W21
W23
W27
AA21
AA23
AA27
AC21
AC23
AC27
AE21
AE23
AE27

+1.5VS

@

+0.95VALW

VDDCR_CPU_1
VDDCR_CPU_2
VDDCR_CPU_3
VDDCR_CPU_4
VDDCR_CPU_5
VDDCR_CPU_6
VDDCR_CPU_7
VDDCR_CPU_8
VDDCR_CPU_9
VDDCR_CPU_10
VDDCR_CPU_11
VDDCR_CPU_12
VDDCR_CPU_13
VDDCR_CPU_14
VDDCR_CPU_15
VDDCR_CPU_16
VDDCR_CPU_17
VDDCR_CPU_18
VDDCR_CPU_19
VDDCR_CPU_20
VDDCR_CPU_21
VDDCR_CPU_22
VDDCR_CPU_23
VDDCR_CPU_24
VDDCR_CPU_25
VDDCR_CPU_26

+1.8VALW

2

+RTC_APU_R

+RTC_APU_R

AN4

VDDIO_AZ_ALW_1
VDDIO_AZ_ALW_2

VDDBT_RTC_G

@
UAPU1H
GND

POWER

VDDIO_MEM_S_1
VDDIO_MEM_S_2
VDDIO_MEM_S_3
VDDIO_MEM_S_4
VDDIO_MEM_S_5
VDDIO_MEM_S_6
VDDIO_MEM_S_7
VDDIO_MEM_S_8
VDDIO_MEM_S_9
VDDIO_MEM_S_10
VDDIO_MEM_S_11
VDDIO_MEM_S_12
VDDIO_MEM_S_13
VDDIO_MEM_S_14
VDDIO_MEM_S_15
VDDIO_MEM_S_16
VDDIO_MEM_S_17
VDDIO_MEM_S_18
VDDIO_MEM_S_19
VDDIO_MEM_S_20
VDDIO_MEM_S_21
VDDIO_MEM_S_22
VDDIO_MEM_S_23

@

+0.95VALW/+0.95VS OF APU
+0.95VS

1

2

C259

1

2

@

@

@

1

2

C231

1

2

C230

1

2

C207

1

2

C208

1

2

C211

1

2

C210

1

2

C932

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

@

1

2

C930

1

2

C931

1

2

C929

1

2

C928

1

2

C926

1

2

C927

1

2

C923

C925

C949

C924

1

@
UAPU1G

@
UAPU1F
J35
L32
L37
N35
R31
R37
U32
U35
W31
W32
W37
AA31
AA35
AC32
AC37
AE31
AE35
AG32
AG37
AJ35
AL32
AL37
AR35

+1.5VS

VDDIO_MEM_S

2

3A
2

VDD_33_ALW

PLANE SPLIT

+1.5V

+1.5V

1

VDDIO_AZ_ALW
(Could be S0 or S5 power rail)

+1.5V/+1.5VS OF APU
2

2

1U_0402_6.3V6K

2

1

C253

1

1U_0402_6.3V6K

2

C252

1

180P_0402_50V8J

2

+3VALW

C257

1

1U_0402_6.3V6K

2

C249

1

180P_0402_50V8J

1U_0402_6.3V6K

2

C197

1

1U_0402_6.3V6K

2

C194

1

C195

2

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C193

1

1U_0402_6.3V6K

2

C192

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C191

C201

1U_0402_6.3V6K

2

1

C202

C200

1

+3VS

1

VDDCR_NB

+APU_CORE_NB

+1.8VS

A8
A13
A23
A31
A35
A39
B8
B13
B23
B31
B39
C1
C2
C5
C7
C9
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C33
C35
C37
C39
C41
D9
D11
D13
E3
E4
E9
E11
E13
E27
E31
E35
E38
E39
G3
G7
G11
G13
G15
G17
G21
G25
G29
G35
G37
G39
G41
H11
H13
H23
H31

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62

GND

VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124

J3
J7
J8
J39
K11
K13
K17
K19
K21
K23
K25
K27
K29
K31
L3
L7
L8
L10
L11
L15
L19
L31
L39
L41
M1
M2
N3
N7
N15
N19
N25
N29
N31
N39
P1
P2
R3
R7
R15
R19
R25
R29
R39
R41
U1
U2
U3
U7
U8
U11
U15
U19
U25
U29
U31
U39
W3
W5
W11
W15
W19
W25

FT3_BGA_769P-T_A39
Part Number =

W29
W39
W41
Y1
Y2
AA3
AA7
AA8
AA11
AA15
AA19
AA25
AA29
AA39
AC3
AC7
AC11
AC15
AC19
AC25
AC29
AC31
AC39
AC41
AE3
AE7
AE25
AE29
AE32
AE39
AG3
AG5
AG10
AG11
AG13
AG15
AG19
AG25
AG29
AG31
AG39
AG41
AH1
AH2
AJ3
AJ7
AJ15
AJ17
AJ19
AJ23
AJ25
AJ29
AJ31
AJ32
AJ39
AL3
AL8
AL15
AL17
AL19
AL25
AL29

VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186

VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSSBG_DAC
VBURN
PSEN

AL39
AL41
AM11
AM27
AM31
AN3
AN7
AN39
AP31
AR3
AR13
AR17
AR21
AR25
AR29
AR39
AR41
AU1
AU2
AU3
AU15
AU19
AU23
AU27
AU39
AV9
AW3
AW7
AW13
AW15
AW17
AW19
AW21
AW23
AW25
AW27
AW31
AW33
AW35
AW37
AW39
AW41
AY13
AY15
AY18
AY30
BA2
BA7
BA13
BA15
BA18
BA21
BA25
BA31
BA35
BA39
A15
AL31
AM29

2

3

FT3_BGA_769P-T_A39
Part Number =

+0.95VS_APU_GFX

FT3_BGA_769P-T_A39
Part Number =

VDD_18_ALW
VDDBT_RTC_G
+RTC_APU

W=20mils

R93

1

2 10K_0402_5%

2

1

4

1

C166
0.22U_0402_10V6K

2

RTC OF APU

4

+RTC_APU_R

CLRP1 SP@
SHORT PADS

Need OPEN
for Clear CMOS

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

FT3 PWR/GND
Size
C
Date:

A

B

C

D

Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
E

9

of

45

A

B

+1.5V

+1.5V

DDRAB_SDQ2
DDRAB_SDQ3
DDRAB_SDQ8
DDRAB_SDQ9

1

DDRAB_SDQS1#
DDRAB_SDQS1

<11,5> DDRAB_SDQS1#
<11,5> DDRAB_SDQS1

DDRAB_SDQ10
DDRAB_SDQ11



2

2

2

1

C136
.1U_0402_16V7K

1

C944 @ESD@
.1U_0402_16V7K

1

C945 @ESD@
.1U_0402_16V7K

205

G1

G2

.1U_0402_16V7K

+3VS

1

2

4.7U_0603_6.3V6K

DDRAB_SDQ58
DDRAB_SDQ59

2

C127

DDRAB_SDM7

1

@ESD@

DDRAB_SDQ56
DDRAB_SDQ57

1

2

C126

DDRAB_SDQ50
DDRAB_SDQ51

.1U_0402_16V7K

DDRAB_SDQS6#
DDRAB_SDQS6

@

1

2

C128
.1U_0402_16V7K
@ESD@

DDRAB_SDQ48
DDRAB_SDQ49
<11,5> DDRAB_SDQS6#
<11,5> DDRAB_SDQS6

3

1

2

C129

DDRAB_SDQ42
DDRAB_SDQ43

1

2

.1U_0402_16V7K

DDRAB_SDM5

@

@

1

2

.1U_0402_16V7K

DDRAB_SDQ40
DDRAB_SDQ41

1

2

C123

DDRAB_SDQ34
DDRAB_SDQ35

1

2

.1U_0402_16V7K

DDRAB_SDQS4#
DDRAB_SDQS4

<11,5> DDRAB_SDQS4#
<11,5> DDRAB_SDQS4

@

1

2

C122

DDRAB_SDQ32
DDRAB_SDQ33

@

1

2

C121

DDRAB_SMA13
DDRA_SCS1#

<5> DDRA_SCS1#

DDRAB_SDQS3# <11,5>
DDRAB_SDQS3 <11,5>

1

2

.1U_0402_16V7K

DDRAB_SWE#
DDRAB_SCAS#

<11,5> DDRAB_SWE#
<11,5> DDRAB_SCAS#

DDRAB_SDQ28
DDRAB_SDQ29
DDRAB_SDQS3#
DDRAB_SDQS3

1

2

.1U_0402_16V7K

DDRAB_SMA10
DDRAB_SBS0#

<11,5> DDRAB_SBS0#

DDRAB_SDQ22
DDRAB_SDQ23

C120

DDRA_CLK0
DDRA_CLK0#

<5> DDRA_CLK0
<5> DDRA_CLK0#

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDRAB_SDM2

.1U_0402_16V7K

DDRAB_SMA3
DDRAB_SMA1

2

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

DDRAB_SDQ20
DDRAB_SDQ21

C119

DDRAB_SMA8
DDRAB_SMA5

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDRAB_SDQ14
DDRAB_SDQ15
C118

DDRAB_SMA12
DDRAB_SMA9

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

1

+0.75VS

+1.5V

.1U_0402_16V7K

DDRAB_SBS2#

<11,5>

+1.5V/+0.75VS OF DIMM1
MEM_MAB_RST# <11,5>

.1U_0402_16V7K

DDRA_CKE0

<5> DDRA_CKE0
<11,5> DDRAB_SBS2#

DDRAB_SDM1
MEM_MAB_RST#

C116

DDRAB_SDQ26
DDRAB_SDQ27

DDRAB_SDQ12
DDRAB_SDQ13

C117

DDRAB_SDM3

<11,5>
<11,5>

DDRAB_SDQS0# <11,5>
DDRAB_SDQS0 <11,5>

.1U_0402_16V7K

DDRAB_SDQ24
DDRAB_SDQ25

DDRAB_SMA[0..15]

E

DDRAB_SDQ6
DDRAB_SDQ7

.1U_0402_16V7K

DDRAB_SDQ18
DDRAB_SDQ19

DDRAB_SDQS0#
DDRAB_SDQS0

C114

DDRAB_SDQS2#
DDRAB_SDQS2

<11,5> DDRAB_SDQS2#
<11,5> DDRAB_SDQS2

DDRAB_SDQ[0..63]
DDRAB_SDM[0..7]

DDRAB_SMA[0..15]

DDRAB_SDQ4
DDRAB_SDQ5

C115

DDRAB_SDQ16
DDRAB_SDQ17

DDRAB_SDQ[0..63]

1

2

@

DDRAB_SDQ30
DDRAB_SDQ31

DDRA_CKE1

DDRA_CKE1 <5>

DDRAB_SMA15
DDRAB_SMA14
DDRAB_SMA11
DDRAB_SMA7

DDRAB_SMA6
DDRAB_SMA4
DDRAB_SMA2
DDRAB_SMA0

DDRA_CLK1
DDRA_CLK1#

DDRAB_SBS1#
DDRAB_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1

15mil

VREF for DIMM1,2

2

DDRA_CLK1 <5>
DDRA_CLK1# <5>

DDRAB_SBS1# <11,5>
DDRAB_SRAS# <11,5>

+1.5V

+VREF_DQ
RP9

DDRA_SCS0# <5>
DDRA_ODT0 <5>

1
2
3
4

+VREF_CA

DDRA_ODT1 <5>

8
7
6
5

1K_0804_8P4R_1%

+VREF_CA

DDRAB_SDQ36
DDRAB_SDQ37
DDRAB_SDM4
DDRAB_SDQ38
DDRAB_SDQ39

DDRAB_SDQ44
DDRAB_SDQ45

DDRAB_SDQS5#
DDRAB_SDQS5

1

2

2

C167

DDRAB_SDM0

2

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

C134

DDRAB_SDQ0
DDRAB_SDQ1

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

D

DDRAB_SDM[0..7]

JDIMM1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

.1U_0402_16V7K

1

1

C142

C176

2

1000P_0402_50V7K

.1U_0402_16V7K

15mil

1000P_0402_50V7K

+VREF_DQ

C

2
1
MEM_MAB_RST#
C1274
@ESD@
100P_0402_50V8J

1

DDRAB_SDQS5# <11,5>
DDRAB_SDQS5 <11,5>

DDRAB_SDQ46
DDRAB_SDQ47
DDRAB_SDQ52
DDRAB_SDQ53

DDRAB_SDM6

3

DDRAB_SDQ54
DDRAB_SDQ55
DDRAB_SDQ60
DDRAB_SDQ61

DDRAB_SDQS7#
DDRAB_SDQS7

DDRAB_SDQS7# <11,5>
DDRAB_SDQS7 <11,5>

DDRAB_SDQ62
DDRAB_SDQ63
MEM_MAB_EVENT#

MEM_MAB_EVENT# <11,5>
APU_SDATA0 <11,26,7>
APU_SCLK0 <11,26,7>

+0.75VS

206

FOX_AS0A621-U4R6-7H
CONN@

SP07000J510

DIMM_A H:4mm RVS

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

DDR3 SODIMM-I Socket
Size
C
Date:

A

B

C

D

Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
E

10

of

45

A

B

+VREF_DQ

+1.5V

DDRAB_SDQ16
DDRAB_SDQ17

DDRAB_SDQ56
DDRAB_SDQ57

DDRAB_SDM7

DDRAB_SDQ58
DDRAB_SDQ59
1
R690

+3VS

2 DDRB_SA0
10K_0402_5%

1

C140
.1U_0402_16V7K


2

205

G1

G2

.1U_0402_16V7K

DDRAB_SDQ50
DDRAB_SDQ51

1

2

4.7U_0603_6.3V6K

DDRAB_SDQS6#
DDRAB_SDQS6

<10,5> DDRAB_SDQS6#
<10,5> DDRAB_SDQS6

2

C175

DDRAB_SDQ48
DDRAB_SDQ49
3

@

1

C158

DDRAB_SDQ42
DDRAB_SDQ43

2

.1U_0402_16V7K

DDRAB_SDM5

2

1

C172

DDRAB_SDQ40
DDRAB_SDQ41

2

.1U_0402_16V7K

DDRAB_SDQ34
DDRAB_SDQ35

@

2

1

.1U_0402_16V7K

DDRAB_SDQS4#
DDRAB_SDQS4

<10,5> DDRAB_SDQS4#
<10,5> DDRAB_SDQS4

2

1

C170

DDRAB_SDQ32
DDRAB_SDQ33

DDRB_CKE1 <5>

2

1

C171

<5> DDRB_SCS1#

DDRB_CKE1

2

1

.1U_0402_16V7K

DDRAB_SMA13
DDRB_SCS1#

@

2

1

.1U_0402_16V7K

DDRAB_SWE#
DDRAB_SCAS#

<10,5> DDRAB_SWE#
<10,5> DDRAB_SCAS#

DDRAB_SDQ30
DDRAB_SDQ31

2

1

C169

DDRAB_SMA10
DDRAB_SBS0#

<10,5> DDRAB_SBS0#

DDRAB_SDQS3# <10,5>
DDRAB_SDQS3 <10,5>

1

.1U_0402_16V7K

DDRB_CLK0
DDRB_CLK0#

<5> DDRB_CLK0
<5> DDRB_CLK0#

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDRAB_SDQ28
DDRAB_SDQ29

1

C168

DDRAB_SMA3
DDRAB_SMA1

2

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

DDRAB_SDQ22
DDRAB_SDQ23

.1U_0402_16V7K

DDRAB_SMA8
DDRAB_SMA5

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDRAB_SDM2

DDRAB_SDQS3#
DDRAB_SDQS3

+0.75VS

+1.5V

C165

DDRAB_SMA12
DDRAB_SMA9

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDRAB_SDQ20
DDRAB_SDQ21

C162

DDRAB_SBS2#

+1.5V/+0.75VS OF DIMM2

DDRAB_SDQ14
DDRAB_SDQ15

.1U_0402_16V7K

DDRB_CKE0

<5> DDRB_CKE0
<10,5> DDRAB_SBS2#

<10,5>

1

MEM_MAB_RST# <10,5>

.1U_0402_16V7K

DDRAB_SDQ26
DDRAB_SDQ27

DDRAB_SDM1
MEM_MAB_RST#

C132

DDRAB_SDM3

<10,5>

DDRAB_SDQ12
DDRAB_SDQ13

.1U_0402_16V7K

DDRAB_SDQ24
DDRAB_SDQ25

<10,5>

DDRAB_SDM[0..7]
DDRAB_SMA[0..15]

DDRAB_SDQ6
DDRAB_SDQ7

C155

DDRAB_SDQ18
DDRAB_SDQ19

DDRAB_SMA[0..15]

C133

DDRAB_SDQS2#
DDRAB_SDQS2

<10,5> DDRAB_SDQS2#
<10,5> DDRAB_SDQS2

DDRAB_SDQS0# <10,5>
DDRAB_SDQS0 <10,5>

+1.5V

1

1

C644

DDRAB_SDQ10
DDRAB_SDQ11

DDRAB_SDQ[0..63]

DDRAB_SDM[0..7]

DDRAB_SDQS0#
DDRAB_SDQS0

+
2

220U_6.3V_M

DDRAB_SDQS1#
DDRAB_SDQS1

<10,5> DDRAB_SDQS1#
<10,5> DDRAB_SDQS1

DDRAB_SDQ[0..63]

DDRAB_SDQ4
DDRAB_SDQ5

2

@

2
1
MEM_MAB_RST#
C1275
@ESD@
100P_0402_50V8J

DDRAB_SMA15
DDRAB_SMA14
DDRAB_SMA11
DDRAB_SMA7

DDRAB_SMA6
DDRAB_SMA4
DDRAB_SMA2
DDRAB_SMA0

DDRB_CLK1
DDRB_CLK1#

DDRAB_SBS1#
DDRAB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1

15mil

2

DDRB_CLK1 <5>
DDRB_CLK1# <5>

DDRAB_SBS1# <10,5>
DDRAB_SRAS# <10,5>

DDRB_SCS0# <5>
DDRB_ODT0 <5>
DDRB_ODT1 <5>
+VREF_CA

DDRAB_SDQ36
DDRAB_SDQ37
DDRAB_SDM4
DDRAB_SDQ38
DDRAB_SDQ39

1

2

2

C174

1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

C139

DDRAB_SDQ2
DDRAB_SDQ3
DDRAB_SDQ8
DDRAB_SDQ9

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

.1U_0402_16V7K

DDRAB_SDM0

2

E

+1.5V

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

1000P_0402_50V7K

DDRAB_SDQ0
DDRAB_SDQ1
C143

C177

1000P_0402_50V7K

.1U_0402_16V7K

1

1

D

JDIMM2

15mil
2

C

1

DDRAB_SDQ44
DDRAB_SDQ45

DDRAB_SDQS5#
DDRAB_SDQS5

DDRAB_SDQS5# <10,5>
DDRAB_SDQS5 <10,5>

DDRAB_SDQ46
DDRAB_SDQ47
DDRAB_SDQ52
DDRAB_SDQ53

DDRAB_SDM6

3

DDRAB_SDQ54
DDRAB_SDQ55
DDRAB_SDQ60
DDRAB_SDQ61

DDRAB_SDQS7#
DDRAB_SDQS7

DDRAB_SDQS7# <10,5>
DDRAB_SDQS7 <10,5>

DDRAB_SDQ62
DDRAB_SDQ63
MEM_MAB_EVENT#

MEM_MAB_EVENT# <10,5>
APU_SDATA0 <10,26,7>
APU_SCLK0 <10,26,7>

+0.75VS

206

LCN_DAN06-K4406-0100
CONN@

DIMM_B H:4mm STD

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

DDR3 SODIMM-II Socket
Size
C
Date:

A

B

C

D

Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
E

11

of

45

A

B

C

D

E

GFX PCIE LANE REVERSAL
U75G

U75A

<5> PEG_ATX_GRX_P[0..3]
<5> PEG_ATX_GRX_N[0..3]

PEG_GTX_C_ARX_P[0..3]

PEG_ATX_GRX_N[0..3]

PART 7 0F 9

PEG_GTX_C_ARX_P[0..3] <5>

PART 1 0F 9

PEG_GTX_C_ARX_N[0..3]

RSVD/VARY_BL
RSVD/DIGON

PEG_GTX_C_ARX_N[0..3] <5>

AK27
AJ27

LVDS CONTROL

PEG_ATX_C_GRX_P1
PEG_ATX_C_GRX_N1

Y35
W36

PEG_ATX_GRX_P2
PEG_ATX_GRX_N2

VGA@ C60 1
VGA@ C61 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

PEG_ATX_C_GRX_P2
PEG_ATX_C_GRX_N2

W38
V37

PEG_ATX_GRX_P3
PEG_ATX_GRX_N3

VGA@ C64 1
VGA@ C63 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

PEG_ATX_C_GRX_P3
PEG_ATX_C_GRX_N3

V35
U36
U38
T37
T35
R36
R38
P37
P35
N36

2

N38
M37

PCIE_TX1P
PCIE_TX1N

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N
NC#N33
NC#N32

NC#N38
NC#M37
NC#M35
NC#L36

L38
K37

NC#L38
NC#K37

K35
J36
J38
H37
H35
G36
G38
F37

NC#N30
NC#N29

NC#L33
NC#L32

NC#K35
NC#J36

NC#L30
NC#L29

NC#J38
NC#H37

NC#K33
NC#K32

NC#H35
NC#G36

NC#J33
NC#J32

NC#G38
NC#F37

NC#K30
NC#K29

NC#F35
NC#E37

NC#H33
NC#H32

VGA@ C65 1
VGA@ C66 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

1

PEG_GTX_C_ARX_P0
PEG_GTX_C_ARX_N0

W33
W32

PEG_GTX_ARX_P1
PEG_GTX_ARX_N1

VGA@ C67 1
VGA@ C68 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

PEG_GTX_C_ARX_P1
PEG_GTX_C_ARX_N1

U33
U32

PEG_GTX_ARX_P2
PEG_GTX_ARX_N2

VGA@ C70 1
VGA@ C69 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

PEG_GTX_C_ARX_P2
PEG_GTX_C_ARX_N2

U30
U29

PEG_GTX_ARX_P3
PEG_GTX_ARX_N3

VGA@ C71 1
VGA@ C72 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

PEG_GTX_C_ARX_P3
PEG_GTX_C_ARX_N3

TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N
TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N

T33
T32

NC#AF35
NC#AG36

T30
T29

TXCAP_DPA3P
TXCAM_DPA3N
TX0P_DPA2P
TX0M_DPA2N

P33
P32

TX1P_DPA1P
TX1M_DPA1N

P30
P29

TX2P_DPA0P
TX2M_DPA0N

N33
N32

NC#AN36
NC#AP37

AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37
AF35
AG36

AP34
AR34
AW37
AU35
AR37
AU39
2

AP35
AR35
AN36
AP37

N30
N29
2160842006A0MARSXT_FCBGA962
@

L33
L32
L30
L29

R405
0_0402_5%
2
1
@

K33
K32

+3VS

J33
J32
<23,26,7> APU_PCIE_RST#

K30
K29

<7> PE_GPIO0

APU_PCIE_RST#

1

PE_GPIO0

2

IN1
IN2

OUT

4

GPU_RST#

H33
H32

R1578
2.2K_0402_5%
VGA@

3

U37
MC74VHC1G08DFT2G_SC70-5
VGA@

R391
100K_0402_5%
VGA@

1

F35
E37

PCI EXPRESS INTERFACE

M35
L36

3

PCIE_RX1P
PCIE_RX1N

PEG_GTX_ARX_P0
PEG_GTX_ARX_N0

1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

Y33
Y32

2

VGA@ C49 1
VGA@ C50 1

PCIE_TX0P
PCIE_TX0N

5

PEG_ATX_GRX_P1
PEG_ATX_GRX_N1

PCIE_RX0P
PCIE_RX0N

VCC

AA38
Y37

GND

PEG_ATX_C_GRX_P0
PEG_ATX_C_GRX_N0

3

2 .1U_0402_16V7K
2 .1U_0402_16V7K

LVTMDP

VGA@ C47 1
VGA@ C48 1

PEG_ATX_GRX_P0
PEG_ATX_GRX_N0

2

1

PEG_ATX_GRX_P[0..3]

CLOCK

AB35
AA36

<8> CLK_PEG_VGA
<8> CLK_PEG_VGA#

PCIE_REFCLKP
PCIE_REFCLKN
CALIBRATION

PCIE_CALR_TX
2 VGA@ 1
AH16
R795
1K_0402_5%
GPU_RST#

TEST_PG

AA30

PCIE_CALR_RX

2 1.69K_0402_1%

Y30

VGA_PCIE_CALRP

R797 1 VGA@

Y29

VGA_PCIE_CALRN

R796 1 VGA@ 2 1K_0402_1%

+0.95VSDGPU
+0.95VSDGPU

PERSTB

3.3-V tolerant
2160842006A0MARSXT_FCBGA962
@

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Issued Date

Deciphered Date

2016/03/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

MARS-Pro_PCIE

Size
Document Number
Custom

Rev
1.0

Z5WAE LA-B231P

Date:

Thursday, March 27, 2014

Sheet
E

12

of

45

A

B

C

D

External VGA Thermal Sensor

10K_0402_5% 1

2

@

<42> GPU_VID2

GPIO_19_CTF
GPU_VID2

T140

(GPIO1, 2, 7, 11, 12, 13, 18, 21

R
AVSSN

GPIO_0
GPIO_1
GPIO_2
GPIO_5_AC_BATT
GPIO_6_TACH
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21
GPIO_22_ROMCSB
CLKREQB

G
AVSSN

B
AVSSN
DAC1

HSYNC
VSYNC
RSET

AVDD
AVSSQ
VDD1DI
VSS1DI

is NC at SUN)

AG32
AG33

VREFG:Use a voltage divider to set
VREFG = 1.80 V / 3 (or 0.60-V nominal).

GPIO_29
GPIO_30

NC_SVI2#AC31
NC_SVI2#AD30
NC_SVI2#AD32

GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

PS_0

AC30
+1.8VSDGPU

R810 1 MARS@ 2 499_0402_1%

AK24

20mil

R811 1 MARS@ 2 249_0402_1%

1
C841
MARS@

2 0.1U_0402_16V4Z

AH13
(SUN NC)

+VGA_VREF

2

Pull high @ VGA side

HPD1

MLPS

XTALOUT

3

27MHZ_10PF_X3G027000BA1H-U

1

PS_3

DDC/AUX

DDC1CLK
DDC1DATA
TESTEN

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO

1

DDC2CLK
DDC2DATA

AUX2P
AUX2N
NC#AL30
NC#AM30

1
2

THERMAL

+3VSDGPU

C849 VGA@
10P_0402_50V8J

2
1
@
R819
10K_0402_5%
1 VGA@ 2
R820
10K_0402_5%
+1.8VSDGPU
L69
1

Crystals must have a max ESR of 80 ohm

GPU_THERM_D+
GPU_THERM_DMLPS_EN#

AF29
AG29
AK32
AL31

RS@ 2

13mA
0_0603_5%

10U_0603_6.3V6M 2
1U_0402_6.3V6K 2
0.1U_0402_16V4Z 2

10mil

1 @
1 @
1 VGA@

C844
C845
C846

+TSVDD

AJ32
AJ33

NC_XTAL_PVDD
NC_XTAL_PVSS

AK10
AL10

T137
T138

AU20
AT19

@

2160842006A0MARSXT_FCBGA962
@

AU22
AV21

@

AT23
AR22

AD39
AD37

T154

AE36
AD35

T156

AF37
AE38

AC36
AC38

T155

+VDD1DI

@

1

2

10mil

@

@

1

2

AM34

PS_0

AD31

PS_1

AG31

PS_2

AD33

PS_3

L67

1

PS0_[1]=1
PS0_[2]=0
PS0_[3]=0
PS0_[4]=1
PS0_[5]=1

2

L68
0_0603_5%
1
MARS@

2

100
101
101
101
101
100
101

+1.8VSDGPU

1@

2

DPLUS
DMINUS

NC#AL29
NC#AM29
NC#AN21
NC#AM21

GPIO_28_FDO
TS_A

TSVDD
TSVSS

NC#AK30
NC#AK29
DDCVGACLK
DDCVGADATA

Bits[5:1] PU(1%)

-

:
:
:
:
:

B

NC

4.75k

xx001

8.45k

2.00k

xx010

4.53k

2.00k

xx011

6.98k

4.99k

xx100

4.53k

4.99k

xx101

3.24k

5.62k

xx110

3.40k

10.0k

xx111

4.75k

NC

2

00xxx

680nF

01xxx

82nF

10xxx

10nF

11xxx

NC

same as GPIO_11
Since the frame buffer size is 512 MB
same as GPIO_12
the aperture size is set to 256 MB.
same as GPIO_13
Reserved for internal use only. Must be 1
AUD_PORT_CONN_PINSTRAP[0]

512Kbit
1Mbit
2Mbit
4Mbit
8Mbit
512Kbit
1Mbit

M25P05A
M25P10A
M25P20
M25P40
M25P80
Pm25LV512
Pm25LV010

(ST)
(ST)
(ST)
(ST)
(ST)
(Chingis)
(Chingis)

AL29
AM29

2

AN21
AM21

@

@

@

1

1

2

1

2

2

0
0
0
1
1

:
:
:
:
:

PCIeR GEN3 is not supported.
Reserved for internal use only
Reserved for internal use only
TX_PWRS_ENB: Full Tx output swing.
TX_DEEMPH_EN: Tx deemphasis enabled.

PS_2[1]
PS_2[2]
PS_2[3]
PS_2[4]
PS_2[5]

=
=
=
=
=

0
0
0
0
1

:
:
:
:
:

Reserved.
Reserved.
BIOS_ROM_EN :Disable the external BIOS ROM device.
VGA_DIS : 0=VGA controller capacity enabled.
Reserved.

+VDDC_CT

+VDDC_CT

@
R816
10K_0402_5%

@

1

=
=
=
=
=

X76@
@
R812
R822
10K_0402_5% 10K_0402_5%

PS_0
PS_1
PS_2
PS_3

AL30
AM30

PS_1[1]
PS_1[2]
PS_1[3]
PS_1[4]
PS_1[5]

+VDDC_CT

VGA@
R808
8.45K_0402_1%

X76@
R823
R821
R809
R815
10K_0402_5% 4.75K_0402_1% 4.75K_0402_1% 2K_0402_1%
VGA@
VGA@
VGA@

PS_3[1]
PS_3[2]
PS_3[3]
PS_3[4]
PS_3[5]
=======
000
001
010
011
100
101

=
=
=
=
=

x
x
x
1
1

:
:
VRAM ID
:
: AUD_PORT_CONN_PINSTRAP[1]
: AUD_PORT_CONN_PINSTRAP[2]

VRAM ID for Jet

=======

Hynix S IC D3 128M16 H5TC2G63FFR-11C*4(SA00006H430)
Micron S IC D3 128M16 MT41J128M16JT-093G:K*4(SA000067550)
Samsung S IC D3 128M16 K4W2G1646Q-BC1A*4(SA000068U90)
Hynix S IC D3 256M16 H5TC4G63AFR-11C*4(SA00006E840)
Micron S IC D3 256M16 MT41J256M16HA-093G:E*4(SA000077K20) 4
Samsung S IC D3 256M16 K4W4G1646D-BC1A*4(SA000076P20)

AK30
AK29
AJ30
AJ31

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

Title

MARS-Pro_STRAP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2160842006A0MARSXT_FCBGA962
@

Rev
1.0

Z5WAE LA-B231P

Date:

A

PD(1%) Cap

xx000

3

AM27
AL27

AN20
AM20

Mars MLPS configuration

+1.8VSDGPU

AM26
AN26

AM19
AL19

@

2

+0.95VSDGPU

70mA

MARS@
0_0603_5%

1

117mA

AC31
AD30
AD32

2

10mil

RSET
R805 1 MARS@ 2 499_0402_1%
(SUN NC)
2
AD34
+AVDD
(SUN NC)
AE34

V13
U13
AF33
AF32
AA29
AG21
AC32

1

2 10K_0402_5%
2 10K_0402_5%

R803 1 @
R804 1
@

AUD_1
AUD_0

@

AUD[1:0]:
00 - No audio function

AB34

AC33
AC34

1

2

AT21
AR20

+VDDC_CT
DEBUG

1

10K_0804_8P4R_5%
@

CLKTESTA
CLKTESTB

C840
.1U_0402_16V7K

IN

4

AM23
AN23
AK23
AL24
AM24

2

AF30
AF31

AT17
AR16

C843
.1U_0402_16V7K

VGA@ C848
10P_0402_50V8J

GND

PX_EN

AUX1P
AUX1N

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
T18
@

SPLL_PVSS

C847
0.01U_0402_16V7K

2

GND

8
7
6
5

1
2
3
4

XTALIN

AN10

C842
.1U_0402_16V7K

4

OUT

BACO

RP21

X2
VGA@
Crystal

2

AD28

2 VGA@ 1
TESTEN
R817
1K_0402_5%

+3VSDGPU

VGA@
R824
1M_0402_5%
2
1

PS_1

PS_2

DBG_VREFG

R813
0_0402_5%
@

R814
+3VSDGPU 5.11K_0402_1%
2 @
1

XO_IN2

CEC_1

Place VREFG divider and cap close to ASIC
AL21

SPLL_VDDC

C838
1U_0402_6.3V6K

3

AT15
AR14

C837
0.1U_0402_16V4Z

AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

+SPLL_VDDC

AU16
AV15

(SUN NC)

NC#V13
NC#U13
NC#AF33
NC#AF32
NC#AA29
NC#AG21
NC#AC32

L66
MBK1608121YZF_0603
2
1
VGA@

100mA

I2C

GENERAL PURPOSE I/O

2

AW35 XO_IN2 2
1
@
0_0402_5% R802

1

R806

SPLL_PVDD

2
XO_IN 1
@
0_0402_5% R799

VGA@ 1 VGA@ 1

C835
0.1U_0402_16V4Z

GPU_VID1
GPU_VID3
THM_ALERT#

<42> GPU_VID1
<42> GPU_VID3

SCL
SDA

+SPLL_VDDC AN9

AW34

2

GPU_VID5

<42> GPU_VID5

NC#AT23
NC#AR22

AT33
AU32
AU14
AV13

C834
1U_0402_6.3V6K

AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13

GPU_ACIN_D
GPU_VID4

NC#AU22
NC#AV21

XO_IN
+SPLL_PVDD AM10

1

5
2
G

2

1

AH20
AH18
AN16

DPD

SMBCLK SMBus
SMBDATA

2

AR32
AT31

1

2

AK26
AJ26

GPU_ACIN_D

<42> GPU_VID4

NC#AT17
NC#AR16
NC#AU20
NC#AT19

MPLL_PVDD
MPLL_PVDD

1

AJ23
AH23

GPU_DPRSLPVR

<42> GPU_DPRSLPVR

VGA@

2
1
D7
RB751V-40 SOD-323

NC#AU16
NC#AV15

H7
H8

+MPLL_PVDD

2

0_0402_5%
RS@ 2VGA_SMB_CK2_R
RS@ 2VGA_SMB_DA2_R
0_0402_5%

2

<22> GPU_ACIN

NC#AT15
NC#AR14
DPC

NC#AT21
NC#AR20

Slave ID: 0x41

R409
100K_0402_5%
VGA@

NC#AU14
NC#AV13

VGA@ 1 VGA@ 1

AV31
AU30

C891
R841
0.1U_0402_16V4Z 51.1_0402_1%

+3VSDGPU

NC#AT33
NC#AU32

XTALOUT

AR30
AT29

C892
R910
0.1U_0402_16V4Z 51.1_0402_1%

R908
1
VGA_SMB_CK2
1
VGA_SMB_DA2
R909

NC#AR32
NC#AT31

L65
MBK1608121YZF_0603
2
1
+1.8VSDGPU
VGA@

+SPLL_PVDD

C833
10U_0603_6.3V6M

EC_SMB_DA2 <22,6>

DPB

75mA

2

C832
1U_0402_6.3V6K

S

Q54B VGA@
DMN66D0LDW-7_SOT363-6
6
EC_SMB_DA2

D

1

VGA_SMB_DA2

EC_SMB_CK2 <22,6>

D

4
S

1

1

G

Q54A VGA@
DMN66D0LDW-7_SOT363-6
3
EC_SMB_CK2

NC#AV31
NC#AU30

XTALOUT

AT27
AR26

1

2

2
R801
4.7K_0402_5%
VGA@

NC#AR30
NC#AT29

AU34

2

+1.8VSDGPU

SM010030010 200ma
120ohm@100mhz DCR 0.2

C830
10U_0603_6.3V6M

VGA_SMB_CK2

T112
T113
T114
T115
T118
T117
T119
T121
T120
T122
T124
T123
T125
T127
T126
T128
T130
T129
T131
T133
T132
T134
T136
T135

XTALIN

C829
1U_0402_6.3V6K

+3VSDGPU

NC#AT27
NC#AR26

AV33

2

T111

+3VSDGPU
1

NC#AR8
NC#AU8
DBG_CNTL0
NC#AW8
NC#AR3
NC#AR1
DBG_DATA0
DBG_DATA1
DBG_DATA2
DBG_DATA3
DBG_DATA4
DBG_DATA5
DBG_DATA6
DBG_DATA7
DBG_DATA8
DBG_DATA9
DBG_DATA10
DBG_DATA11
DBG_DATA12
DBG_DATA13
DBG_DATA14
DBG_DATA15
DBG_DATA16
DBG_DATA17
DBG_DATA18
DBG_DATA19
DBG_DATA20
DBG_DATA21
DBG_DATA22
DBG_DATA23

XTALIN

PLLS/XTAL

AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

AT25
AR24
AU26
AV25

1

NC#AU26
NC#AV25

ADM1032ARMZ-2REEL_MSOP8

R800
4.7K_0402_5%
VGA@

NC#AT25
NC#AR24

DPA

2

+3VSDGPU

SWAPLOCKA
SWAPLOCKB

1

AJ21
AK21

2
4.7K_0402_5%

@

2

1
R798

1

THM_ALERT#

VGA@ 1 VGA@ 1

2

GND

THERM#

6
5

AU24
AV23

1

SDATA

ALERT#

NC#AU24
NC#AV23

2

D+
D-

VGA_SMB_DA2

+MPLL_PVDD
PART 9 0F 9

MUTI GFX

GENLK_CLK
GENLK_VSYNC

1

4

7

AD29
AC29

T109
T110

2

3

VGA_SMB_CK2

C826
10U_0603_6.3V6M

2

2

GPU_THERM_D+
2200P_0402_50V7K
2
C827 1
@
GPU_THERM_D-

8

C825
1U_0402_6.3V6K

1

C824
0.1U_0402_16V4Z

@

SCLK

VDD

1

U52 @

1

L64
MBK1608121YZF_0603
2
1
VGA@

130mA

PART 2 0F 9

2

+3VSDGPU

E

U75I

U75B

C

D

Thursday, March 27, 2014
E

Sheet

13

of

45

B

C

D

E

MAA[0..15]

U75D

MAA[0..15] <17>

U75C
PART 4 0F 9

1

2

R911
0_0402_5%
@

2

+1.5VSDGPU

R829

1

2

40.2_0402_1%
MARS@

2

1 MARS@

2

C852
1U_0402_6.3V6K

R830
100_0402_1%
MARS@

15mil
MVREFSA

3

L18
L20
L27
N12
AG12

R835 1 VGA@
120_0402_1%

2

MEM_CALRP0 M27

CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B

CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1

MVREFDA
MVREFSA

CKEA0
CKEA1

NC#L27
NC#N12
NC#AG12

W EA0B
W EA1B

MEM_CALRP0

NC#M12
NC#AH12

MAA0_8/MAA_13
MAA1_8/MAA_14
MAA0_9/MAA_15
MAA1_9/RSVD

J21
G19

ODTA0
ODTA1

H27
G27

CLKA0
CLKA0#

J14
H14

CLKA1
CLKA1#

K23
K19

RASA0#
RASA1#

K20
K17

CASA0#
CASA1#

K24
K27

CSA0#

M13
K16

CSA1#

K21
J20

CKEA0
CKEA1

K26
L15

WEA0#
WEA1#

H23
J19
M21
M20

MAA13
MAA14
MAA15

ODTA0 <17>
ODTA1 <17>
CLKA0 <17>
CLKA0# <17>

CLKA1 <17>
CLKA1# <17>
RASA0# <17>
RASA1# <17>

CASA0# <17>
CASA1# <17>
CSA0# <17>

CSA1# <17>

MVREFDB Y12
MVREFSB AA12

CKEA0 <17>
CKEA1 <17>

DDBIB0_0/QSB_0B
DDBIB0_1/QSB_1B
DDBIB0_2/QSB_2B
DDBIB0_3/QSB_3B
DDBIB1_0/QSB_4B
DDBIB1_1/QSB_5B
DDBIB1_2/QSB_6B
DDBIB1_3/QSB_7B

ADBIB0/ODTB0
ADBIB1/ODTB1

CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B

CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1

CKEB0
CKEB1

MVREFDB
MVREFSB

W EB0B
W EB1B

WEA0# <17>
WEA1# <17>

MAB0_8/MAB_13
MAB1_8/MAB_14
MAB0_9/MAB_15
MAB1_9/RSVD

DRAM_RST

H3
H1
T3
T5
AE4
AF5
AK6
AK5

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

T7
W7

ODTB0
ODTB1
CLKB0
CLKB0#

CLKB1
CLKB1#

T10
Y10

RASB0#
RASB1#

W 10
AA10

CASB0#
CASB1#

P10
L10

CSB0#

AD10
AC10

CSB1#

U10
AA11

CKEB0
CKEB1

N10
AB11

WEB0#
WEB1#

T8
W8
U12
V12

MAB13
MAB14
MAB15

1

QSA#[0..7] <17>

MAB[0..15]

MAB[0..15] <18>
1

DQMB#[0..7]

DQMB#[0..7] <18>

QSB[0..7]
B_BA2 <18>
B_BA0 <18>
B_BA1 <18>

QSB[0..7] <18>

QSB#[0..7]

QSB#[0..7] <18>

+1.5VSDGPU

VGA@

L9
L8

2160842006A0MARSXT_FCBGA962
@

2160842006A0MARSXT_FCBGA962
@

QSA[0..7] <17>

QSA#[0..7]

R825

AD8
AD7

AH11

QSA[0..7]

1

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

EDCB0_0/QSB_0
EDCB0_1/QSB_1
EDCB0_2/QSB_2
EDCB0_3/QSB_3
EDCB1_0/QSB_4
EDCB1_1/QSB_5
EDCB1_2/QSB_6
EDCB1_3/QSB_7

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

40.2_0402_1%

15mil

2

A34
E30
E26
C20
C16
C12
J11
F8

W CKB0_0/DQMB_0
W CKB0B_0/DQMB_1
W CKB0_1/DQMB_2
W CKB0B_1/DQMB_3
W CKB1_0/DQMB_4
W CKB1B_0/DQMB_5
W CKB1_1/DQMB_6
W CKB1B_1/DQMB_7

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

MVREFDB

1

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

2

M12
AH12

ADBIA0/ODTA0
ADBIA1/ODTA1

C34
D29
D25
E20
E16
E12
J10
D7

GDDR5/DDR3

DQB0_0
DQB0_1
DQB0_2
DQB0_3
DQB0_4
DQB0_5
DQB0_6
DQB0_7
DQB0_8
DQB0_9
DQB0_10
DQB0_11
DQB0_12
DQB0_13
DQB0_14
DQB0_15
DQB0_16
DQB0_17
DQB0_18
DQB0_19
DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31
DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8
DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31

1 VGA@

R827 VGA@
100_0402_1%

ODTB0 <18>
ODTB1 <18>

2

+1.5VSDGPU

2

R912
0_0402_5%
@

CLKB0 <18>
CLKB0# <18>

CLKB1 <18>
CLKB1# <18>
RASB0# <18>
RASB1# <18>

R832
VGA@
40.2_0402_1%

CASB0# <18>
CASB1# <18>

CSB0# <18>

15mil
MVREFSB

1 VGA@

R831
VGA@
100_0402_1%

2

CSB1# <18>

C853
1U_0402_6.3V6K

MVREFDA
MVREFSA

DDBIA0_0/QSA_0B
DDBIA0_1/QSA_1B
DDBIA0_2/QSA_2B
DDBIA0_3/QSA_3B
DDBIA1_0/QSA_4B
DDBIA1_1/QSA_5B
DDBIA1_2/QSA_6B
DDBIA1_3/QSA_7B

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

A_BA2 <17>
A_BA0 <17>
A_BA1 <17>

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

2

1

2

EDCA0_0/QSA_0
EDCA0_1/QSA_1
EDCA0_2/QSA_2
EDCA0_3/QSA_3
EDCA1_0/QSA_4
EDCA1_1/QSA_5
EDCA1_2/QSA_6
EDCA1_3/QSA_7

A32
C32
D23
E22
C14
A14
E10
D9

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

2

2

1
2

100_0402_1%
MARS@

1 MARS@
C850
1U_0402_6.3V6K

R828

15mil
MVREFDA

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1

1

R826
40.2_0402_1%
MARS@

W CKA0_0/DQMA_0
W CKA0B_0/DQMA_1
W CKA0_1/DQMA_2
W CKA0B_1/DQMA_3
W CKA1_0/DQMA_4
W CKA1B_0/DQMA_5
W CKA1_1/DQMA_6
W CKA1B_1/DQMA_7

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

2

1

+1.5VSDGPU

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_BA2
MAA1_6/MAA_BA0
MAA1_7/MAA_BA1

1

1

GDDR5/DDR3

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

MEMORY INTERFACE A

(SUN 64 bin on at Channel B)

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

DQMA#[0..7] <17>

C851
1U_0402_6.3V6K

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

DQMA#[0..7]

MDB[0..63]

2

MDA[0..63]

<17> MDA[0..63]

<18> MDB[0..63]

MEMORY INTERFACE B

PART 3 0F 9

1

A

CKEB0 <18>
CKEB1 <18>
3

WEB0# <18>
WEB1# <18>

2
1
2
1
VGA@
VGA@
R838
R839
10_0402_5% 1 VGA@ 51.1_0402_1%
VGA@
C854
R840
120P_0402_50V8
4.99K_0402_1%
2

VRAM_RST# <17,18>

Place all these components very close
to GPU (Within 25mm) and
keep all component close to
each Other (within5mm) except Rser2
The suggested components are tested on the AMD
reference board only. Customers must measure the slew
on each memory part to ensure that the slew rate meets
the DRAM specification.

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Issued Date

Deciphered Date

4

2016/03/27

Title

MARS-Pro_MEMORY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

Z5WAE LA-B231P

Date:

A

B

C

D

Thursday, March 27, 2014

Sheet
E

14

of

45

A

B

C

D

E

U75E
PART 5 0F 9

+1.5VSDGPU

VGA@

VGA@
1

2

300mA

20mil
+1.8VSDGPU

+VDDR4

2

1
@
2

C899
0.1U_0402_16V4Z

2

C908
1U_0402_6.3V6K

MARS@ MARS@
1
1
C907
10U_0603_6.3V6M

2
1
L73
MBK1608121YZF_0603
MARS@

25mA

+VDDR3

AF23
AF24
AG23
AG24
AD12
AF11
AF12
AF13

AF15
AG11
AG13
AG15

I/O

VDDR3
VDDR3
VDDR3
VDDR3
DVP

VDDR4
VDDR4
VDDR4
VDDR4

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

VDDR4
VDDR4
VDDR4
VDDR4

(SUN NC)

FB_VDDCI
FB_GND

1

<42> VSS_GPU_SENSE

AG28

2

@
R842
0_0402_5%
4

VGA@
1

VGA@
1

VGA@
1

VGA@
1

2

2

2

2

2

2

1.4A 60mil
VGA@
1

VGA@
1

VGA@
1

2

2

2

+VGA_CORE

30A (TBD)

+0.95VSDGPU

Must always be connected to PCIE_VDDC.
0.95 V for "Mars" and
"Heathrow"/"Chelsea" on both BACO and
non-BACO designs.

2

AH22
AH27
AH28
M26
N24
R18
R21
R23
R26
T17
T20
T22
T24
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

3

360mil
+VGA_CORE
VGA@

3.5A (DDR3)
1

2

VGA@

VGA@
1

2

1

2

2160842006A0MARSXT_FCBGA962
@

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

+0.95VSDGPU

C919
0.1U_0402_16V4Z

T139

VSS_GPU_SENSE AH29

FB_VDDC

VGA@
1

C918
0.1U_0402_16V4Z

VCC_GPU_SENSE AF28

VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI

VGA@
1

C917
0.1U_0402_16V4Z

VOLTAGE
SENESE

10mil
<42> VCC_GPU_SENSE

ISOLATED
CORE I/O

3

1

C876
10U_0603_6.3V6M

2

10mil

C898
0.1U_0402_16V4Z

2

VGA@
1

C897
1U_0402_6.3V6K

@
1

2

VDD_CT
VDD_CT
VDD_CT
VDD_CT

100mil

2

+1.8VSDGPU

C875
1U_0402_6.3V6K

2

LEVEL
TRANSLATION

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18

2

@
1

C888
10U_0603_6.3V6M

2

1
@

13mA

+VDDC_CT AF26
AF27
AG26
AG27

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

N27
T27

2.5A

C889
1U_0402_6.3V6K

VGA@
1

C896
1U_0402_6.3V6K

2
1
L74
MBK1608121YZF_0603
VGA@

VGA@
1

C887
0.1U_0402_16V4Z

L72
MBK1608121YZF_0603
VGA@

C886
1U_0402_6.3V6K

+3VSDGPU

20mil

1

C885
10U_0603_6.3V6M

2

2

CORE

BIF_VDDC
BIF_VDDC

2

100mA

C890
1U_0402_6.3V6K

+VDDC_CT

+1.8VSDGPU

BACO

@
1

C874
1U_0402_6.3V6K

2

VGA@
1

C866
10U_0603_6.3V6M

2

NC For Mars

C873
1U_0402_6.3V6K

2

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

20mil
C862
1U_0402_6.3V6K

2

VGA@
1

C884
2.2U_0402_6.3V6M

2

VGA@
1

C883
2.2U_0402_6.3V6M

2

VGA@
1

C882
2.2U_0402_6.3V6M

2

@
1

C881
2.2U_0402_6.3V6M

2

C880
2.2U_0402_6.3V6M

@
1

C879
10U_0603_6.3V6M

VGA@
1

C878
10U_0603_6.3V6M

VGA@
1

C877
10U_0603_6.3V6M

VGA@
1

2

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

AA31
AA32
AA33
AA34
W30
Y31
V28
W29
AB37

C872
1U_0402_6.3V6K

2

NC#AA31
NC#AA32
NC#AA33
NC#AA34
NC#W30
NC#Y31
NC_BIF_VDDC
NC_BIF_VDDC
PCIE_PVDD

C869
1U_0402_6.3V6K

2

VGA@
1

C870
0.1U_0402_16V4Z

@
1

C867
0.1U_0402_16V4Z

VGA@
1

2

MEM I/O

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

C871
1U_0402_6.3V6K

2

VGA@
1

C863
0.01U_0402_16V7K

1

C861
0.01U_0402_16V7K

2

2

C868
0.1U_0402_16V4Z

2

C865
0.1U_0402_16V4Z

@
1

C864
0.1U_0402_16V4Z

VGA@
1

1

C860
0.01U_0402_16V7K

2

@

VGA@

@
1

C857
0.01U_0402_16V7K

2
1

C856
0.01U_0402_16V7K

1

AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

PCIE

1.5A

C

D

Title

MARS-Pro_PWR/GND

Size Document Number
Custom

Rev
1.0

Z5WAE LA-B231P

Date:

Thursday, March 27, 2014

Sheet
E

15

of

45

A

B

C

D

E

U75F
PART 6 0F 9

U75H

AW28

AW18

NC#AW18

DP_CALR

R406
0_0402_5%
2
1
@

5

+3VALW

R807
10K_0402_5%
1 VGA@ 2

<7> PE_GPIO1

1

@ R913
100K_0402_5%

2
1

VGA@ C178
0.22U_0402_10V6K

IN1
IN2

2

OUT

4

VGA_ON

U38
MC74VHC1G08DFT2G_SC70-5
VGA@

2

Delay 2ms
+3VALW

1

VGA_ON

2

+1.8VALW TO +1.8VSDGPU
+0.95VALW TO +0.95VSDGPU
Load switch

OUT

4

VGA_ON_B

VGA_ON_B <42>

3

VGA@ C185
0.22U_0402_10V6K

IN1
IN2

VCC

R833
33K_0402_5%
1 VGA@ 2

+3VSDGPU

1

U39
MC74VHC1G08DFT2G_SC70-5
VGA@

2

3

+3VS TO +3VSDGPU

VIN 1.8V and 0.95V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
+1.8VSDGPU

+1.8VALW
U1895
1
2

<41,42,7> VGA_PWRGD

R127 1 RS@

3

2 0_0402_5%

+5VALW

+0.95VALW

ON1

CT1

VBIAS

GND

ON2

CT2

VIN2
VIN2

VOUT2
VOUT2
GPAD

14
13

+1.8VSDGPU_LS

U74 VGA@

VGA@ 1
2200P_0402_50V7K

2
C35

11
10

4

VGA@ 1
2200P_0402_50V7K

9
8

2
C28

15

JUMP_43X118

TPS22966DPUR_SON14_2X3
VGA@

Issued Date

C620
4.7U_0603_6.3V6K
VGA@

+0.95VSDGPU
JP12JP@

+0.95VSDGPU_LS
2 C31
@

1

2

VOUT

2014/03/27

100mil(1.5A)

VIN
GND

EN
1

1

2

2

C621
VGA@
1 4.7U_0603_6.3V6K

SS
3

AP2821KTR-G1_SOT23-5

2 C32
@

1

VGA_ON

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2160842006A0MARSXT_FCBGA962
@

5

JUMP_43X118
12

+3VSDGPU

+3VS

JP11JP@
VOUT1
VOUT1

0.1U_0402_16V4Z

2

6
7

VIN1
VIN1

0.1U_0402_16V4Z

2

1U_0402_6.3V6K

2

1 C29 1 C30
@
@

1U_0402_6.3V6K

1U_0402_6.3V6K

1 C39 1 C40
VGA@
@

T116
T141
T142

4
5

VGA_ON 1 VGA@ 2
R128
47K_0402_5%

AG22

A39
AW1
AW39

NC#AW28

AN27
AP27
AP28
AW24
AW26
AN29
AP29
AP30
AW30
AW32
AN17
AP16
AP17
AW14
AW16
AN19
AP18
AP19
AW20
AW22
AN34
AP39
AR39
AU37
AF39
AH39
AK39
AL34
AV27
AR28
AV17
AR18
AN38
AM35
AN32

2160842006A0MARSXT_FCBGA962
@

2

VSS_MECH
VSS_MECH
VSS_MECH

DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR

GND

AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

Delay 4ms
NC#AG22

1

5

R845
150_0402_1%
2 MARS@ 1 AM39

2

DP GND

DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR

CALIBRATION

AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20

AP13
AT13
AP14
AP15

2

VCC

2

2

GND

2

1 VGA@ 1 VGA@ 1 VGA@

3

VGA@
1

NC#AP13
NC#AT13
NC#AP14
NC#AP15

+0.95VSDGPU

280mA

2

2

VGA@
1

NC#AP20
NC#AP21
NC#AP22
NC#AP23
NC#AU18
NC#AV19

20mil

1

@
1

AH34
AJ34
AF34
AG34
AM37
AL38
AM32

NC#AN24
NC#AP24
NC#AP25
NC#AP26
NC#AU28
NC#AV29

AP31
AP32
AN33
AP33
AL33
AM33
AK33
AK34
AN31

C953
10U_0603_6.3V6M

237mA
+1.8VSDGPU

0.22U_0402_10V6K

4

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

AP20
AP21
AP22
AP23
AU18
AV19

DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC

C952
1U_0402_6.3V6K

3

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

AN24
AP24
AP25
AP26
AU28
AV29

DP_VDDC

C954
0.1U_0402_16V4Z

2

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

PART 8 0F 9

DP_VDDR

C951
1U_0402_6.3V6K

GND

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20

C956
10U_0603_6.3V6M

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

C955
0.1U_0402_16V4Z

1

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

2016/03/27

Deciphered Date

Title

MARS-Pro_PWR/GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

Z5WAE LA-B231P

Date:

A

B

C

D

Thursday, March 27, 2014

Sheet
E

16

of

45

B

C

F3
C7

DQMA#2
DQMA#0

E7
D3

QSA#2
QSA#0

G3
B7

2

VRAM_RST#

<14,18> VRAM_RST#

T2

1

L8

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET

ZQ/ZQ0

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

R846
243_0402_1%
128@

J1
L1
J9
L9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CLKA0
CLKA0#
CKEA0

J7
K7
K9

+1.5VSDGPU
A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTA0
CSA0#
RASA0#
CASA0#
WEA0#

K1
L2
J3
K3
L3

QSA3
QSA1

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#3
DQMA#1

E7
D3

QSA#3
QSA#1

G3
B7

VRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

R847
243_0402_1%
128@

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
128X76@
+1.5VSDGPU

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

DML
DMU
DQSL
DQSU

RESET

ZQ/ZQ0

G3
B7

VRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R848
243_0402_1%
128@

J1
L1
J9
L9

DQSL
DQSU

RESET

ZQ/ZQ0

ODTA1
CSA1#
RASA1#
CASA1#
WEA1#

K1
L2
J3
K3
L3

QSA6
QSA7

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#6
DQMA#7

E7
D3

QSA#6
QSA#7

G3
B7

VRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

R849
243_0402_1%
128@

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
128X76@
+1.5VSDGPU

2

2

15mil

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA48
MDA51
MDA55
MDA54
MDA50
MDA52
MDA49
MDA53

D7
C3
C8
C2
A7
A2
B8
A3

MDA63
MDA58
MDA60
MDA59
MDA61
MDA56
MDA62
MDA57

1

+1.5VSDGPU
B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

+1.5VSDGPU
A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET

ZQ/ZQ0

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
128X76@

3

15mil

1

C962

VREFDA_Q3

128@

2

R863
4.99K_0402_1%
128@

C977

1

128@

2

+1.5VSDGPU

+1.5VSDGPU

2

2

2

2

2

2

2

2

2

2

+1.5VSDGPU

128@
1

2

2

2

2

2

C988
1U_0402_6.3V6K

2

128@
1

C982
1U_0402_6.3V6K

2

128@
1

C964
1U_0402_6.3V6K

2

128@
1

C963
1U_0402_6.3V6K

2

128@
1

C965
1U_0402_6.3V6K

2

C980
1U_0402_6.3V6K

128@
1

C966
1U_0402_6.3V6K

128@
1

C981
1U_0402_6.3V6K

128@
1

C986
1U_0402_6.3V6K

128@
1

C979
1U_0402_6.3V6K

128@
1

C959
1U_0402_6.3V6K

128@
1

C961
1U_0402_6.3V6K

128@
1

C983
1U_0402_6.3V6K

128@
1

C972
1U_0402_6.3V6K

128@
1

C976
1U_0402_6.3V6K

128@
1

+1.5VSDGPU

+1.5VSDGPU

+1.5VSDGPU

128@
1

2

2

2

2

2

2

2

2

Issued Date

2014/03/27

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification

C1030
10U_0603_6.3V6M

128@
1

C1027
10U_0603_6.3V6M

128@
1

C1028
10U_0603_6.3V6M

2

128@
1

C1029
10U_0603_6.3V6M

2

128@
1

C978
10U_0603_6.3V6M

2

128@
1

128@
1

C974
10U_0603_6.3V6M

C406
0.01U_0402_16V7K
2
128@

2

128@
1

C1025
10U_0603_6.3V6M

2

128@
1

C1023
10U_0603_6.3V6M

2

128@
1

128@
1

C1026
10U_0603_6.3V6M

2

128@
1

128@
1

C973
10U_0603_6.3V6M

128@
1

128@
1

C975
10U_0603_6.3V6M

128@
1

VREFCA
VREFDQ

R855
4.99K_0402_1%
128@

1

2

C984
128@

J1
L1
J9
L9

+1.5VSDGPU

VREFCA_A3

1

1
2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

R862
4.99K_0402_1%
128@

C1024
10U_0603_6.3V6M

1

QSA#4
QSA#5

DML
DMU

A1
A8
C1
C9
D2
E9
F1
H2
H9

0.1U_0402_16V4Z

1

C967
1U_0402_6.3V6K

2
40.2_0402_1%

E7
D3

J7
K7
K9

128@
1

2

128@

DQMA#4
DQMA#5

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

CLKA1
CLKA1#
CKEA1
+1.5VSDGPU

128@
1

C971
10U_0603_6.3V6M

1
R869

F3
C7

ODT/ODT0
CS/CS0
RAS
CAS
WE

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M2
N8
M3

128@
1

C970
10U_0603_6.3V6M

<14> CLKA1#

2
40.2_0402_1%

QSA4
QSA5

+1.5VSDGPU

C985
10U_0603_6.3V6M

1
R868

K1
L2
J3
K3
L3

CK
CK
CKE/CKE0

M8
H1

A_BA0
A_BA1
A_BA2

128@
1

C969
10U_0603_6.3V6M

128@

<14> CLKA1

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

ODTA1

MDA43
MDA44
MDA40
MDA45
MDA42
MDA46
MDA41
MDA47

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

+1.5VSDGPU

VREFDA_Q1

C958
1U_0402_6.3V6K

4

<14> ODTA1
<14> CSA1#
<14> RASA1#
<14> CASA1#
<14> WEA1#

D7
C3
C8
C2
A7
A2
B8
A3

VREFDA_Q3
VREFCA_A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

15mil

R859
4.99K_0402_1%
128@

C987
1U_0402_6.3V6K

C395
0.01U_0402_16V7K
2
128@

J7
K7
K9

MDA35
MDA32
MDA38
MDA34
MDA37
MDA36
MDA39
MDA33

128@
1

2
40.2_0402_1%
1

CLKA1
CLKA1#

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

0.1U_0402_16V4Z

2

C960
1U_0402_6.3V6K

<14> CLKA0#

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

M2
N8
M3

<14> CKEA1

+1.5VSDGPU
A1
A8
C1
C9
D2
E9
F1
H2
H9

A_BA0
A_BA1
A_BA2

0.1U_0402_16V4Z

128@

0.1U_0402_16V4Z

1

C957

128@
1
R867

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B2
D9
G7
K2
K8
N1
N9
R1
R9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

1

1
2

15mil

C968
1U_0402_6.3V6K

2
40.2_0402_1%

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

+1.5VSDGPU

128@

+1.5VSDGPU
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

VREFCA
VREFDQ

R854
4.99K_0402_1%
128@

VREFCA_A1

1
R866

MDA14
MDA11
MDA12
MDA10
MDA13
MDA9
MDA15
MDA8

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

R851
4.99K_0402_1%
128@

R858
4.99K_0402_1%
128@

<14> CLKA0

D7
C3
C8
C2
A7
A2
B8
A3

M8
H1

VREFCA_A3
VREFDA_Q3

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
128X76@

+1.5VSDGPU

R850
4.99K_0402_1%
128@

3

M2
N8
M3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDA25
MDA30
MDA24
MDA29
MDA26
MDA31
MDA27
MDA28

1

QSA2
QSA0

ODT/ODT0
CS/CS0
RAS
CAS
WE

A_BA0
A_BA1
A_BA2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

2

K1
L2
J3
K3
L3

CK
CK
CKE/CKE0

B2
D9
G7
K2
K8
N1
N9
R1
R9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

1

ODTA0

+1.5VSDGPU
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

VREFCA
VREFDQ

2

<14> ODTA0
<14> CSA0#
<14> RASA0#
<14> CASA0#
<14> WEA0#

J7
K7
K9

MDA0
MDA5
MDA1
MDA7
MDA3
MDA4
MDA2
MDA6

M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

1

CLKA0
CLKA0#
<14> CKEA0

D7
C3
C8
C2
A7
A2
B8
A3

VREFDA_Q1
VREFCA_A1

1

M2
N8
M3

<14> A_BA0
<14> A_BA1
<14> A_BA2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDA23
MDA19
MDA22
MDA18
MDA21
MDA16
MDA20
MDA17

2

QSA#[0..7]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

2

QSA[0..7]

<14> QSA[0..7]
<14> QSA#[0..7]

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

1

DQMA#[0..7]

<14> DQMA#[0..7]

VREFCA
VREFDQ

2

MDA[0..63]

<14> MDA[0..63]

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

1

MAA[0..15]

<14> MAA[0..15]
1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15

E

U57

U58

2

VREFCA_A1 M8
VREFDA_Q1 H1

D

U55

U54

2

A

2016/03/27

Deciphered Date

Title

VRAM_DDR3 / Channel A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

Z5WAE LA-B231P

Date:

A

B

C

D

Thursday, March 27, 2014

Sheet
E

17

of

45

B

C

<14> QSB#[0..7]

QSB[0..7]

QSB#[0..7]

M2
N8
M3

<14> B_BA0
<14> B_BA1
<14> B_BA2

CLKB0
CLKB0#
<14> CKEB0
<14> ODTB0
<14> CSB0#
<14> RASB0#
<14> CASB0#
<14> WEB0#

2

ODTB0

K1
L2
J3
K3
L3

QSB3
QSB1

F3
C7

DQMB#3
DQMB#1

E7
D3

QSB#3
QSB#1

G3
B7

VRAM_RST#

<14,17> VRAM_RST#

J7
K7
K9

T2

1

L8

R870
243_0402_1%

D7
C3
C8
C2
A7
A2
B8
A3

MDB12
MDB11
MDB15
MDB9
MDB13
MDB8
MDB14
MDB10

N3
MAB0
P7
MAB1
P3
MAB2
N2
MAB3
P8
MAB4
P2
MAB5
R8
MAB6
R2
MAB7
T8
MAB8
R3
MAB9
MAB10 L7
MAB11 R7
MAB12 N7
MAB13 T3
MAB14 T7
MAB15 M7

+1.5VSDGPU
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET

ZQ/ZQ0

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

VGA@

J1
L1
J9
L9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VREFDB_Q1 M8
VREFCB_A1 H1

B2
D9
G7
K2
K8
N1
N9
R1
R9

B_BA0
B_BA1
B_BA2

M2
N8
M3

CLKB0
CLKB0#
CKEB0

J7
K7
K9

+1.5VSDGPU
A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTB0
CSB0#
RASB0#
CASB0#
WEB0#

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

K1
L2
J3
K3
L3

QSB2
QSB0

F3
C7

DQMB#2
DQMB#0

E7
D3

QSB#2
QSB#0

G3
B7

VRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R871
243_0402_1%

J1
L1
J9
L9

VGA@

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@
+1.5VSDGPU

E3
F7
F2
F8
H3
H8
G2
H7

MDB23
MDB16
MDB22
MDB18
MDB21
MDB19
MDB20
MDB17

D7
C3
C8
C2
A7
A2
B8
A3

MDB2
MDB4
MDB0
MDB6
MDB3
MDB7
MDB1
MDB5

VREFCB_A3 M8
VREFDB_Q3 H1
N3
MAB0
P7
MAB1
P3
MAB2
N2
MAB3
P8
MAB4
P2
MAB5
R8
MAB6
R2
MAB7
T8
MAB8
R3
MAB9
MAB10 L7
MAB11 R7
MAB12 N7
MAB13 T3
MAB14 T7
MAB15 M7

+1.5VSDGPU
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET

ZQ/ZQ0

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

B2
D9
G7
K2
K8
N1
N9
R1
R9

B_BA0
B_BA1
B_BA2

M2
N8
M3

CLKB1
CLKB1#

J7
K7
K9

<14> CKEB1

+1.5VSDGPU
A1
A8
C1
C9
D2
E9
F1
H2
H9

<14> ODTB1
<14> CSB1#
<14> RASB1#
<14> CASB1#
<14> WEB1#

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

ODTB1

K1
L2
J3
K3
L3

QSB4
QSB5

F3
C7

DQMB#4
DQMB#5

E7
D3

QSB#4
QSB#5

G3
B7

VRAM_RST#

T2

L8

1

<14> QSB[0..7]

MDB31
MDB26
MDB25
MDB29
MDB28
MDB30
MDB24
MDB27

B1
B9
D1
D8
E2
E8
F9
G1
G9

R872
243_0402_1%

VGA@

J1
L1
J9
L9

U61

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDB35
MDB37
MDB34
MDB39
MDB33
MDB38
MDB32
MDB36

D7
C3
C8
C2
A7
A2
B8
A3

MDB46
MDB43
MDB47
MDB41
MDB44
MDB42
MDB45
MDB40

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET

ZQ/ZQ0

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

A1
A8
C1
C9
D2
E9
F1
H2
H9

K1
L2
J3
K3
L3

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

QSB6
QSB7

F3
C7

DQMB#6
DQMB#7

E7
D3

QSB#6
QSB#7

G3
B7

VRAM_RST#

L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R873
243_0402_1%

J1
L1
J9
L9

VGA@

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET

ZQ/ZQ0

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU
A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

2

B1
B9
D1
D8
E2
E8
F9
G1
G9

1

1

2

2

2

+1.5VSDGPU

1

1

1

VGA@

1

2

VGA@
1

VGA@
1

VGA@
1

VGA@
1

VGA@
1

2

2

2

2

2

2

2

2

VGA@
1

VGA@
1

VGA@
1

2

2

2

2

2

C1022
1U_0402_6.3V6K

2

VGA@
1

+1.5VSDGPU

+1.5VSDGPU

1 VGA@

1

2

1

1
VGA@ VGA@
2

2

VGA@
C1037
10U_0603_6.3V6M

2014/03/27

2

VGA@

C1035
10U_0603_6.3V6M

2

VGA@

C1036
10U_0603_6.3V6M

1

C1045
10U_0603_6.3V6M

2

C1012
10U_0603_6.3V6M

2

1
VGA@ VGA@

2016/03/27

Deciphered Date

Title

VRAM_DDR3 / Channel B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

Z5WAE LA-B231P

Date:

A

B

C

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

1

C1014
10U_0603_6.3V6M

2

VGA@

C1038
10U_0603_6.3V6M

1

C1044
10U_0603_6.3V6M

2

1

C1046
10U_0603_6.3V6M

2

C1032
10U_0603_6.3V6M

2

2

C1021
10U_0603_6.3V6M

1 VGA@

C1049
10U_0603_6.3V6M

2

C1050
10U_0603_6.3V6M

2

C1048
10U_0603_6.3V6M

2

C1047
10U_0603_6.3V6M

1 VGA@ 1 VGA@ 1 VGA@

C1013
10U_0603_6.3V6M

2

2

VGA@
1

C1017
1U_0402_6.3V6K

+1.5VSDGPU

VGA@
1

C998
1U_0402_6.3V6K

2

VGA@
1

C1033
1U_0402_6.3V6K

2

2

1

VREFDB_Q3
C992

R887
4.99K_0402_1%
VGA@

C1018
1U_0402_6.3V6K

2

1

C997
1U_0402_6.3V6K

2

+1.5VSDGPU

C410
0.01U_0402_16V7K
VGA@

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

C1020
1U_0402_6.3V6K

VGA@

C996
1U_0402_6.3V6K

2

VGA@
1

C995
1U_0402_6.3V6K

2

VGA@
1

C994
1U_0402_6.3V6K

2

VGA@
1

C1042
1U_0402_6.3V6K

VGA@
1

C993
1U_0402_6.3V6K

VGA@
1

C991
1U_0402_6.3V6K

VGA@
1

C1031
1U_0402_6.3V6K

VGA@
1

1

2

1

+1.5VSDGPU

BA0
BA1
BA2

C1019
1U_0402_6.3V6K

2

C1039

C1041
1U_0402_6.3V6K

2

2

R886
4.99K_0402_1%
VGA@

1 VGA@ 1 VGA@ 1 VGA@

R893
40.2_0402_1%
1 VGA@ 2

MDB59
MDB62
MDB58
MDB63
MDB56
MDB61
MDB57
MDB60

3

0.1U_0402_16V4Z

VGA@

VGA@
1

C1040
1U_0402_6.3V6K

R892
40.2_0402_1%
1 VGA@ 2

C409
0.01U_0402_16V7K
VGA@

D7
C3
C8
C2
A7
A2
B8
A3

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@

VREFCB_A3
1

+1.5VSDGPU

C990
1U_0402_6.3V6K

R891
40.2_0402_1%
1 VGA@ 2

T2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDB55
MDB49
MDB52
MDB50
MDB53
MDB48
MDB54
MDB51

R879
4.99K_0402_1%
VGA@

0.1U_0402_16V4Z

2

C1051
1U_0402_6.3V6K

<14> CLKB1#

ODTB1
CSB1#
RASB1#
CASB1#
WEB1#

+1.5VSDGPU

2

4

J7
K7
K9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

1

1
2

VREFDB_Q1
C989

R883
4.99K_0402_1%
VGA@

+1.5VSDGPU

1

<14> CLKB1

CLKB1
CLKB1#
CKEB1
+1.5VSDGPU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

+1.5VSDGPU

R878
4.99K_0402_1%
VGA@

0.1U_0402_16V4Z

VGA@

1

0.1U_0402_16V4Z

C1034

C1043
1U_0402_6.3V6K

<14> CLKB0#

M2
N8
M3

VREFCA
VREFDQ

+1.5VSDGPU

VREFCB_A1

R890 40.2_0402_1%
1 VGA@ 2

B_BA0
B_BA1
B_BA2

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@

96-BALL
SDRAM DDR3
MT41K256M16HA-107G_FBGA96
X76@

R875
4.99K_0402_1%
VGA@

R882
4.99K_0402_1%
VGA@

<14> CLKB0

N3
MAB0
P7
MAB1
P3
MAB2
N2
MAB3
P8
MAB4
P2
MAB5
R8
MAB6
R2
MAB7
T8
MAB8
R3
MAB9
MAB10 L7
MAB11 R7
MAB12 N7
MAB13 T3
MAB14 T7
MAB15 M7

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU
R874
4.99K_0402_1%
VGA@

3

VREFDB_Q3 M8
VREFCB_A3 H1

+1.5VSDGPU

2

1

MDB[0..63]
DQMB#[0..7]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

1

<14> MDB[0..63]
<14> DQMB#[0..7]

MAB[0..15]

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2

<14> MAB[0..15]

N3
MAB0
P7
MAB1
P3
MAB2
N2
MAB3
P8
MAB4
P2
MAB5
R8
MAB6
R2
MAB7
T8
MAB8
R3
MAB9
MAB10 L7
MAB11 R7
MAB12 N7
MAB13 T3
MAB14 T7
MAB15 M7

U60

U62

VREFCA
VREFDQ

E

1

U59

VREFCB_A1 M8
VREFDB_Q1 H1

D

2

A

D

Thursday, March 27, 2014

Sheet
E

18

of

45

5

4

3

2

1

LCD POWER CIRCUIT
INVTPWM
BKOFF#

+LCDVDD

D

VOUT

5

GND

2

SS

1

2
EN

1

@
R653
100K_0402_5%

C522
4.7U_0603_6.3V6K

R899
10K_0402_5%

eDP PANEL Conn.

D

3

AP2821KTR-G1_SOT23-5

ENVDD <6>
1

C1278
1U_0402_6.3V6K

1

VIN

4

2

1

1

W=60mils

W=60mils

2

U72

2

+3VS

JLVDS1

100K_0402_5%
R652

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

2

+INVPWR_B+

+INVPWR_B+

W=40mils
C

@EMI@ 1
C364
1000P_0402_50V7K
2

B+
L11 EMI@
HCB2012KF-221T30_0805
2
1
W=40mils

1 @EMI@
C365
68P_0402_50V8J
2

SM010014520 3000ma
220ohm@100mhz
DCR 0.04

<6> EDP_TXP0
<6> EDP_TXN0
<6> EDP_TXP1
<6> EDP_TXN1

EDP_TXP0
EDP_TXN0

C27 1
C33 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

EDP_TXP0_C
EDP_TXN0_C

EDP_TXP1
EDP_TXN1

C34 1
C36 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

EDP_TXP1_C
EDP_TXN1_C

C44 1
C45 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

EDP_AUXN_C
EDP_AUXP_C

<6> EDP_AUXN
<6> EDP_AUXP

INVTPWM
BKOFF#
EDP_HPD

<6> INVTPWM
<22> BKOFF#
<6> EDP_HPD

+LCDVDD

TS_EN

<22> TS_EN
+3VS

2
1
@
R1540
4.7K_0402_5%

TS_EN

2 100K_0402_5% EDP_HPD

R9001

EDP_AUXN_C
EDP_AUXP_C
EDP_TXP0_C
EDP_TXN0_C
R696 1 @EMI@ 2 0_0402_5%

<8> USB20_P3

EDP_TXP1_C
EDP_TXN1_C

USB20_P3_R

L58 EMI@
1
4

1

2

4

3

2

Touch Screen

<8> USB20_N3

2 0_0603_5%
2 0_0603_5%

+3VS

3

R1663 1 RS@

For Camera

DLW21HN900HQ2L_4P
R695 1 @EMI@ 2 0_0402_5%

B

+3VS
+5VS
<8> USB20_P5
<8> USB20_N5

R1666 1
@
R1664 1
USB20_P5
USB20_N5

+5VS_TS
2 0_0603_5% +3VS_CMOS
USB20_P3_R
USB20_N3_R

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

USB20_N3_R

41
42
43
44
45
46

G1
G2
G3
G4
G5
G6

C

B

E-T_0871K-F40N-00L
CONN@

USB20_N3

R697 1 @EMI@ 2 0_0402_5%

USB20_N3_RR

L59 @EMI@
1

1

2

4

3

2

JCAM1
4

USB20_P3

3

+3VS

DLW21HN900HQ2L_4P
R702 1 @EMI@ 2 0_0402_5%

For Camera

USB20_P3_RR
USB20_N3_RR

USB20_P3_RR

1
2
3
4

1
2
3
4

G1
G2

5
6

ACES_88266-04001
CONN@

SP02000K200

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

eDP/Camera/TS
Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
1

19

of

45

A

B

C

D

E

3

2
1

2

3

1

JCRT1

1
L36 EMI@
2
BLM15BB470SN1D_2P
L37 EMI@
2
1
BLM15BB470SN1D_2P
L38 EMI@
2
1
BLM15BB470SN1D_2P

1

1
2

1
2

1
2

1
2

1
2

6P_0402_50V8D
C1107

6P_0402_50V8D
C1106

8
7
6
5

CRT_HSYNC_CONN
CRT_BLUE
6P_0402_50V8D
C1105

6P_0402_50V8D
C1104

6P_0402_50V8D
C1103

RP22
150_0804_8P4R_1%

6P_0402_50V8D
C1094

1
2
3
4

<6> DAC_BLU

CRT_DDC_DAT_CONN
CRT_GREEN

1

<6> DAC_GRN

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

T25

CRT_RED

2

<6> DAC_RED
1

2

C936 ESD@
.1U_0402_16V7K

D21 @ESD@
AZC199-02SPR7G_SOT23-3

1

1

@ESD@ D20
AZC199-02SPR7G_SOT23-3

2

3

2

3

+5VS_DISP

CRT_VSYNC_CONN
T27

CRT_DDC_CLK_CONN

1

G
G

16
17

CCM_070546HR015M25FZR
CONN@

EMI@ EMI@ EMI@

EMI@ EMI@ EMI@

+5VS_DISP

2
1
C537
.1U_0402_16V7K

7

@

10

<6> DAC_DDC_DATA

11

<6> DAC_DDC_CLK

13

<6> DAC_VSYNC

15

<6> DAC_HSYNC

DDC_IN1

VIDEO3

DDC_IN2

DDC_OUT1

SYNC_IN1

DDC_OUT2

SYNC_IN2

SYNC_OUT1

GND

SYNC_OUT2

4

CRT_GREEN

5

CRT_BLUE

9

CRT_DDC_DAT

12

CRT_DDC_CLK

14

CRT_VSYNC

16

CRT_HSYNC

1
2
3
4

RP10 EMI@
22_0804_8P4R_5%
8
7
6
5

TPD7S019-15DBQR_SSOP16
3

+3VS

+5VS_DISP
U23
Vcc

1

5

2 C1182 @
0.1U_0402_16V4Z

2

1

2

1

2

3

2

OE

2

1

G

1

1

CRT_DDC_DAT_CONN
CRT_DDC_CLK_CONN
CRT_VSYNC_CONN
CRT_HSYNC_CONN
C414 @
18P_0402_50V8J

VIDEO2

C413 @
18P_0402_50V8J

VCC_DDC

3

C412 @
18P_0402_50V8J

VIDEO1

2

C411 @
18P_0402_50V8J

6

VCC_VIDEO

2
1
C23
0.22U_0402_10V6K
CRT_RED

8

BYP

VCC_SYNC

@

@

2

+3VS

@

U10
1

2
1
C529
.1U_0402_16V7K

2

DAC_DDC_CLK

1

4
DAC_DDC_DATA

Q2506B
DMN66D0LDW-7_SOT363-6
Q2506A
DMN66D0LDW-7_SOT363-6
3
CRT_DDC_DAT_CONN

GND OUT Y

4

CRT_HSYNC

+5VS_DISP

CRT_DDC_CLK_CONN

D

6

D

M74VHC1GT125DF2G_SC70-5

S

G

3

IN A

S

2

5

DAC_HSYNC

U24
1

OE

Vcc

5

+3VS
RP18

DAC_VSYNC

2
3

IN A
GND OUT Y

4

CRT_VSYNC

1
DAC_DDC_CLK
2
DAC_DDC_DATA
CRT_DDC_CLK_CONN3
CRT_DDC_DAT_CONN4

8
7
6
5

+5VS_DISP

4.7K_0804_8P4R_5%

4

4

M74VHC1GT125DF2G_SC70-5

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

CRT CONN
Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
E

20

of

45

5

4

3

2

1

RP15

.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K

HDMI_TX0HDMI_TX0+
HDMI_TX2HDMI_TX2+

8
7
6
5

1
2
3
4

HDMI_GND

+5VS_DISP
U73
6

2
2
2
2

499_0804_8P4R_1%

+3VS

2

+5VS

G

1
1
1
1

D

D

C56
C55
C52
C51

<6> APU_DP1_N2
<6> APU_DP1_P2
<6> APU_DP1_N0
<6> APU_DP1_P0

S

1
1
1
1

2
2
2
2

.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K

HDMI_CLKHDMI_CLK+
HDMI_TX1HDMI_TX1+

1
2
3
4

3

OUT
1

8
7
6
5

W=40mils

D

1

IN

1

RP16

C58
C57
C54
C53

<6> APU_DP1_N3
<6> APU_DP1_P3
<6> APU_DP1_N1
<6> APU_DP1_P1

Q86B
DMN66D0LDW-7_SOT363-6

2

GND

2

@
C543
.1U_0402_16V7K

AP2330W-7_SC59-3

+3VS

1

499_0804_8P4R_1%

Q86A
DMN66D0LDW-7_SOT363-6
1

4

3

2

1

2

EMI@
C59
220P_0402_50V7K

JHDMI1 CONN@

+5VS_DISP

HDMIDAT_R
HDMICLK_R
3

+3VS

L39 @EMI@
1

1

2

2

HDMI_R_CLK-

HDMI_R_CLK@ESD@
D42
YSLC05CH_SOT23-3
SCA00000U10

1

HDMI_CLK-

C

HDMI_R_CLK+

DLW21HN900HQ2L_4P

HDMI_HPD

1

R765 1 @EMI@ 2 0_0402_5%

R915
100K_0402_5%

L40 @EMI@

3

HDMI_R_TX0+

+3VS
RP1

1
HDMI_R_CLK@EMI@ C2562
1
HDMI_R_CLK+
@EMI@ C2563
1
HDMI_R_TX0@EMI@ C2564
1
HDMI_R_TX0+
@EMI@ C2565
1
HDMI_R_TX1@EMI@ C2568
1
HDMI_R_TX1+
@EMI@ C2569
1
HDMI_R_TX2@EMI@ C2570
1
HDMI_R_TX2+
@EMI@ C2571

L41 @EMI@

HDMI_TX1+

4

1
4

2

3

2

HDMI_R_TX1-

3

HDMI_R_TX1+

DLW21HN900HQ2L_4P

R782 1 @EMI@ 2 0_0402_5%

R783 1 @EMI@ 2 0_0402_5%
L42 @EMI@

A

HDMI_TX2-

1

HDMI_TX2+

4

1

2

4

3

2

HDMI_R_TX2-

3

HDMI_R_TX2+

2
10P_0402_50V8J
2
10P_0402_50V8J
2
10P_0402_50V8J
2
10P_0402_50V8J
2
10P_0402_50V8J
2
10P_0402_50V8J
2
10P_0402_50V8J
2
10P_0402_50V8J

B

+5VS_DISP

8
7
6
5

1
2
3
4

4.7K_0804_8P4R_5%

+3VS

2

R779 1 @EMI@ 2 0_0402_5%
R781 1 @EMI@ 2 0_0402_5%

1

SUYIN_100042GR019M23MZR

HDMI_CLK
HDMI_DATA
HDMICLK_R
HDMIDAT_R

DLW21HN900HQ2L_4P

HDMI_TX1-

20
21
22
23

G

3

HDMI_R_TX0-

C

1

<6> HDMI_CLK

<6> HDMI_DATA

6

Q75A Q75B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
3

4

HDMICLK_R

D

4

2

S

2

5

1

G

4

HDMI_R_TX1+
HDMI_R_TX2-

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKCK_shield
CK+
D0D0_shield
D0+
D1D1_shield
GND
D1+
GND
D2D2_shield GND
GND
D2+

HDMIDAT_R

D

HDMI_TX0+

HDMI_R_TX0+
HDMI_R_TX1-

HDMI_R_TX2+

S

B

1

HDMI_R_CLK+
HDMI_R_TX0-

2

R769 1 @EMI@ 2 0_0402_5%

HDMI_TX0-

E

2HDMI_HPD_CONN
1
2
B
R281
150K_0402_5%
Q18
MMBT3904_NL_SOT23-3
R283
@
365K_0402_1%

1

3

1

3

2

4

3

4

HDMI_CLK+

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HDMI_HPD_CONN

2

R756 1 @EMI@ 2 0_0402_5%

C942 ESD@
.1U_0402_16V7K

1

@
R898
100K_0402_5%

C

2

HDMI_HPD_CONN

D

2
@
R153
0_0402_5%

S

1

<6> HDMI_HPD

2

G

5

@
R618
1M_0402_5%

EMI request 1pF.

A

DLW21HN900HQ2L_4P

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

R794 1 @EMI@ 2 0_0402_5%

2014/03/27

Deciphered Date

2016/03/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

HDMI CONN
Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
1

21

of

45

5

4

3

2

1

+EC_VCCA
L44
FBM-11-160808-601-T_0603
2
1

2

2
1
2
1
C1263
@EMI@ R1560 @EMI@
10_0402_5%
22P_0402_50V8J

LPC_CLK0_EC

<7,8> LPC_CLK0_EC
<27,7> LPC_RST#

1 9012@ 2
EC_RST#
R818
47K_0402_5%
2
1
C819
1000P_0402_50V7K
ESD@

+EC_VCC

1

@

R207
1

C1279

<7> EC_SCI#
<26> WLAN_ON

<29> KSI[0..7]

2
LPC_RST#
100K_0402_5%
2
@ESD@
100P_0402_50V8J

<29> KSO[0..17]

C

<33,34>
<33,34>
<13,6>
<13,6>

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

LPC_CLK0_EC
LPC_RST#
EC_RST#
EC_SCI#

12
13
37
20
38

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

SLP_S3#
EC_I2C_ALERT#
EC_SMI#

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0LPC & MISC

EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47

2

1

GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13

DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F

PS2 Interface

CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00

21
23
26
27

SPI Flash ROM

Bus

LAN_PWR_EN
EC_BEEP#

LAN_PWR_EN <23>
EC_BEEP# <25>

63
64
65
66
75
76

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

ENBKL/AD6/GPIO40
PECI_KB930/AD7/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

S

BATT_TEMP

BATT_TEMP <33>
VCIN1_BATT_DROP <33>
ADP_I <33,34>

ADP_I
AD_BID

+3VS

68
70
71
72

EN_DFAN

83
84
85
86
87
88

EC_MUTE#
USB_EN#
EC_I2C_TPCLK
EC_I2C_TPDAT
TP_CLK
TP_DATA

97
98
99
109

ENBKL
GPU_ACIN
0.95VS_PWR_EN#
9012_PH1

KBL_EN# <29>
EN_DFAN <27>
TP_SENOFF# <29>

EC_MUTE#

R1565 1

@

2 10K_0402_5%

EC_I2C_ALERT#

R116 1

@

2 1K_0402_5%

EC_SMB_DA1

R1577 1

2 2.2K_0402_5%

EC_SMB_CK1

R1574 1

2 2.2K_0402_5%

LID_SW#

R344 1

2 47K_0402_5%

+EC_VCC

EC_MUTE# <25>
USB_EN# <28>

R124 1
R125 1

@
@

2 0_0402_5%
2 0_0402_5%

TP_I2C_CLK <29>
TP_I2C_DAT <29>

TP_CLK <29>
TP_DATA <29>
ENBKL <6>
GPU_ACIN <13>
0.95VS_PWR_EN#
9012_PH1 <33>

119
120
126
128

<30>

C

EC_SPI_MISO <8>
EC_SPI_MOSI <8>
EC_SPI_CLK <8>
EC_SPI_CS1# <8>

73
74
89
90
91
92
93
95
121
127

VGATE

For share ROM reserved

VGATE <39>

BATT_BLUE_LED#
TP_3V_EN
PWR_LED
BATT_AMB_LED#
SYSON
VR_ON
0.95_1.8VALW_PWREN

BATT_BLUE_LED# <29>
TP_3V_EN <29>
BATT_AMB_LED# <29>
SYSON <36>
VR_ON <39>
0.95_1.8VALW_PWREN

1
0.95_1.8VALW_PWREN
R1575

@

2
4.7K_0402_5%

1

@

2
4.7K_0402_5%

EC_RSMRST#
R1576

<7> PBTN_OUT#
<7> SLP_S5#

B

EC_SPOK
FAN_SPEED
LAN_WAKE#
EC_TX
EC_RX
SYS_PWRGD_EC
PWR_SUSP_LED#

PBTN_OUT#
SLP_S5#

122
123

XCLKI/GPIO5D
XCLKO/GPIO5E

KB9012QF-A4_LQFP128_14X14
Part Number = SA00004OB30

GPIO

GPI

AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07

110
112
114
115
116
117
118

ACIN
EC_ON
ON/OFFBTN#
LID_SW#
SUSP#

124

C1265
1

C1266

EC_RSMRST# <7>
EC_LID_OUT# <7>
9012_VCIN <33>

R1675
1

ENBKL
R206

1

3V_EN
R940

ACIN <34>
EC_ON <35>
ON/OFFBTN# <29>
LID_SW# <29>
SUSP# <30,36>

R16 1 9022@

2
100K_0402_5%
2
100K_0402_5%
2
1M_0402_5%

1

SYSON

MAINPWON <33,35>
BKOFF# <19>
LAN_GPO <23>
3V_EN <35>

1

2
R1690 9022@
0_0402_5%

PROCHOT# <39,6,7>

+EC_VCC

V18R

2
100P_0402_50V8J
2
100P_0402_50V8J

1

BATT_TEMP

<37,38>

D

2 0_0603_5%

Q89 9012@
2N7002K_SOT23-3

2

EC_THERM

B

G

1

S

2

C823 9012@
4.7U_0603_6.3V6K

L43
FBM-11-160808-601-T_0603
2
1

20mil
PWR_LED# <29>
1

ECAGND

V18R

EC_RSMRST#
EC_LID_OUT#
9012_VCIN
EC_THERM
MAINPWON
BKOFF#
LAN_GPO
3V_EN

1

SYS_PWRGD_EC@1.8VALW
EC can be OD pin
for reduce Level shifter

<27> FAN_SPEED
<23> LAN_WAKE#
<26> EC_TX
<26> EC_RX
<7> SYS_PWRGD_EC
<29> PWR_SUSP_LED#

100
101
102
103
104
105
106
107
108

3

2
R1682
0_0402_5%

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11

AGND/AGND

<26> WL_OFF#
<26> WLAN_WAKE#
<19> TS_EN

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

69

1

<35> SPOK

<7> EC_SMI#

GND/GND
GND/GND
GND/GND
GND/GND
GND0

<7> SLP_S3#

2

R1683
0_0402_5%

11
24
35
94
113

1 RS@

Q91
2N7002K_SOT23-3

G
R1563
100K_0402_5%

ACIN
<29> TP_I2C_INT#

D

2

EC_RTCRST

SPI Device Interface

GPIO

+RTC_APU_R

D

BATT_TEMP/AD0/GPIO38
AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
IMON/AD5/GPIO43

AD

C1269 @
.1U_0402_16V7K

EC_RTCRST

PWM Output

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

1

2

1

1
2
3
4
5
7
8
10

Rb

ECAGND

2

GATEA20
KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

AD_BID
R1564
15K_0402_5%
2

U44
D

<7> GATEA20
<7> KBRST#
<27,8> SERIRQ
<27,7,8> LPC_FRAME#
<27,8> LPC_AD3
<27,8> LPC_AD2
<27,8> LPC_AD1
<27,8> LPC_AD0

C1262
.1U_0402_16V7K

1

2

2

67

2

R1562
100K_0402_5%

Ra

1

1

EC_VDD/AVCC

@

1

9
22
33
96
111
125

2

1

C1261
1000P_0402_50V7K

@

1

C1259
1000P_0402_50V7K

2

C1257
.1U_0402_16V7K

2

1

C1258
.1U_0402_16V7K

C1255
.1U_0402_16V7K

1

C1256
.1U_0402_16V7K

R1665
0_0603_5%

2

3

+EC_VCC
1 RS@

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

+3VLP

1

+EC_VCC

D
2

1

PWR_LED

Q88
2N7002K_SOT23-3

G
S

2

3

R208
100K_0402_5%

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

EC ENE-KB9012
Size
C
Date:

5

4

3

2

Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
1

22

of

45

5

4

+3VALW

3

2

1

+3V_LAN
JP@
JP14

W=60mil

JUMP_43X79

60mil
5

Place near Pin 3,8,33,46

2

1

2

Place near Pin 20

1

2

1

2

1

2

1

2

C2550
.1U_0402_16V7K

2

1

C2549
.1U_0402_16V7K

2

1

C2548
.1U_0402_16V7K

High active.
EN threshold voltage min:1.2V typ:1.6V max:2.0V
Current limit threshold 1.5~2.8A

2

1

C2547
4.7U_0603_6.3V6K

Using for Switch mode
The trace length from Lx to
PIN48 (REGOUT) and from C to Lx
must < 200mils.

From EC

2

1

C2546
.1U_0402_16V7K

2

1

C2545
1U_0402_6.3V6K

AP2821KTR-G1_SOT23-5

1

2

1

C2544
.1U_0402_16V7K

LAN_PWR_EN <22>

1

C2543
.1U_0402_16V7K

EN

C2551
1U_0402_6.3V6K

LAN_PWR_EN

C2542
.1U_0402_16V7K

3

C2541
.1U_0402_16V7K

2

C2540
.1U_0402_16V7K

2

GND

SS

C2539
.1U_0402_16V7K

VIN

4

W=60mil
1.4A

2
1
2.2UH_NLC252018T-2R2J-N_5%

+REGOUT

C2538
4.7U_0603_6.3V6K

D

+3V_LAN

+LAN_VDD

300mA

L2506

1

VOUT

W=60mil

IDC=1200mA

60mil

U76

1

D

2

Place near Pin 11,32,48

Using for Switch mode
Place near Pin 35

+3V_LAN Rising time must >0.5ms and <100ms

EC_PME# pull high 10K to +3VALW on EC side
1

R2532

<7> APU_PCIE_WAKE#

+3V_LAN

R121 1 RS@

U2505
Power Manahement/Isolation

2 0_0402_5%
ISOLATEB
LAN_PME#

2 0_0402_5%

31
39

ISOLATEBPIN
LANWAKEB

2

<22> LAN_WAKE#

@

PCI-Express

1

R1566
10K_0402_5%

<8> CLK_PCIE_LAN
<8> CLK_PCIE_LAN#

LAN_WAKE#

C

<12,26,7> APU_PCIE_RST#
<7> LAN_CLKREQ#

C788,C791
Place near Pin 25,26

<5> PCIE_ARX_DTX_P1
<5> PCIE_ARX_DTX_N1
<5> PCIE_ATX_C_DRX_P1
<5> PCIE_ATX_C_DRX_N1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

1

+3VS

C2552 1
C2553 1

<24> LAN_MIDI0+
<24> LAN_MIDI0<24> LAN_MIDI1+
<24> LAN_MIDI1<24> LAN_MIDI2+
<24> LAN_MIDI2<24> LAN_MIDI3+
<24> LAN_MIDI3-

2

R2540
10K_0402_5%
@

LAN_CLKREQ#

1

+3V_LAN

2

R2541
10K_0402_5%
@

XTLO

2 0_0402_5%

23
24

APU_PCIE_RST#
LAN_CLKREQ#

30
29

PCIE_ARX_C_DTX_P1
PCIE_ARX_C_DTX_N1

25
26
21
22

LAN_MIDI0+
LAN_MIDI0LAN_MIDI1+
LAN_MIDI1LAN_MIDI2+
LAN_MIDI2LAN_MIDI3+
LAN_MIDI3-

1
2
4
5
6
7
9
10

XTLI
XTLO_R

44
45

2
@
R620
0_0402_5%

+REGOUT

LAN_GPO <22>
+3V_LAN

SWR mode

1

+LAN_VDD

R2533 1
R2534 1
R2538 1
R2535 1
R2536 1
R2537 1

RS@
RS@
EMI@
RS@
RS@
RS@

2
2
2
2
2
2

0_0402_5%
0_0402_5%
10_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

SD_D0_R
SD_D1_R
SD_CLK_R
SD_CMD_R
SD_D3_R
SD_D2_R

SD_D0_R <24>
SD_D1_R <24>
SD_CLK_R <24>
SD_CMD_R <24>
SD_D3_R <24>
SD_D2_R <24>

2

SD_WP <24>

1
HSOP
HSON
HSIP
HSIN
Transceiver Interface
MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3
CKXTAL1
CKXTAL2

SD_CD#
MS_CD#

HV_GIGA
HV_GIGA
VDD33
VDD33

Clock

VDD10
AVDD10
AVDD10

42
43

SD_CD#

C2554Reserve
5P_0402_50V8C
@EMI@

3

2
C99
10P_0402_50V8J

GND

3

47

LAN_RST

T22

2
XTLO

36
35
34
46

VDDTX

REG_OUT
VDDREG
ENSWREG
LV_GEN

Card_3V3

RSET

T23
T15

GPO

41
38
37
40

LED0
LED1/GPO
LED2
LED_CR

1400mA

33
3
8

Protect cotact

+LAN_VDD

20

800mA

13

1

49

C100
10P_0402_50V8J

Card Uninsert
Card insert

+CARD_3V3

Write protect Write Enable
(Lock)
(Unlock)
Open
Open
Open
Close

Open
Close

+VDD33_18

2

4

Card contact

300mA

LEDs

E_Pad

C

+3V_LAN

48
11
12
32

27

for EMI please close to IC

SD_CD# <24>

1

2

@

1

2

C2557
.1U_0402_16V7K

1

1

GND

2

SD_D0
SD_D1
SD_CLK
SD_CMD
SD_D3
SD_D2
SD_WP

C2556
4.7U_0603_6.3V6K

1

15
14
16
17
18
19
28

C2555
.1U_0402_16V7K

XTLI

PERSTBPIN
CLKREQBPIN

SD_D0/MS_D1
SD_D1
SD_CLK/MS_D0
SD_CMD/MS_D2
SD_D3/MS_D3
SD_D2/MS_CLK
MS_BS/SD_WP#

DV33/18

R2542
2.49K_0402_1%

Y2500
25MHZ_10PF_7V25000014

B

REFCLK_P
REFCLK_N

Card Reader

Regulator and Reference

1

GPO

R619 1

CLK_PCIE_LAN
CLK_PCIE_LAN#

1

B

2

Place near Pin 27
RTL8411B-CGT_QFN48_6X6

1

+3VS

ISOLATEB

2

2

R2543
1K_0402_5%

1

R2544
15K_0402_5%

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

2016/03/27

Deciphered Date

Title

LAN RTL8411-CG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

Z5WAE LA-B231P

Date:

5

4

3

2

Thursday, March 27, 2014

Sheet
1

23

of

45

5

4

3

2

1

D

D

LAN Connector
JRJ1

CONN@

T2500

<23> LAN_MIDI1<23> LAN_MIDI1+

LAN_MIDI1LAN_MIDI1+

7
8
9

<23> LAN_MIDI0<23> LAN_MIDI0+

LAN_MIDI0LAN_MIDI0+

10
11
12

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

RJ45_MIDI0+

1

RJ45_MIDI3RJ45_MIDI3+

RJ45_MIDI0-

2

21
20
19

RJ45_MIDI1+

3

RJ45_MIDI2RJ45_MIDI2+

RJ45_MIDI2+

4

18
17
16

RJ45_MIDI1RJ45_MIDI1+

15
14
13

RJ45_MIDI0RJ45_MIDI0+

6

RJ45_MIDI3+

7

RJ45_MIDI3-

8

1
R2545
75_0402_1%
1
R2546
75_0402_1%
2
1
R2547
75_0402_1%
2
1
R2548
75_0402_1%

GST5009-E
SP050006B10

1

2

RJ45_MIDI1-

2

C2561
.1U_0402_16V7K

SHLD1
SHLD2

9
10

PR1-

PR2+

L2501 @EMI@
B88069X9231T203_4P5X3P2-2
2
1

PR3+

40mil

PR3-

2
1
C2560
10P_0402_50V8J

RJ45_GND

PR2-

40mil

PR4+

PR4-

JP@
JUMP_43X118
JP2502

D8 ESD@
L30ESDL5V0C3-2_SOT23-3

C

RJ45_MIDI2-

5

PR1+

LANGND

SANTA_130452-0B

Place close to TCT pin

1

4
5
6

24
23
22

LANGND
C

L2500
@EMI@
B88069X9231T203_4P5X3P2-2

2

LAN_MIDI2LAN_MIDI2+

MCT1
MX1+
MX1-

3

<23> LAN_MIDI2<23> LAN_MIDI2+

TCT1
TD1+
TD1-

2

LAN_TERMAL1
2
3

1

LAN_MIDI3LAN_MIDI3+

2

<23> LAN_MIDI3<23> LAN_MIDI3+

RJ45_GND

Card Reader Connector
B

B

JREAD1

+CARD_3V3

<23> SD_D3_R

SD_D3_R

<23> SD_CMD_R

SD_CMD_R

1
2
3
4

Close to Card Reader CONN

2

C2566
.1U_0402_16V7K

C2567
4.7U_0603_6.3V6K

1

<23> SD_CLK_R

5

SD_CLK_R

1

2

6
<23> SD_D0_R

SD_D0_R

7

<23> SD_D1_R

SD_D1_R

8

<23> SD_D2_R

SD_D2_R

9

<23> SD_CD#

<23> SD_WP

SD_CD#

10

SD_WP

11

CD/DAT3
CMD
VSS1
VDD
CLK
VSS2
DAT0
DAT1

G1

DAT2

G2

CD

G3

WP

G4

12
13
14
15

TAITW_PSDAT4-11GLBS1NN4H2
CONN@

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

2016/03/27

Deciphered Date

Title

LAN RJ45/CR SD Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

Z5WAE LA-B231P

Date:

5

4

3

2

Thursday, March 27, 2014

Sheet
1

24

of

45

A

B

C

D

E

HD Audio Codec
+VDDA

+5VS

40mil

Reserved for ESD

CBP
CBN

LDO3-CAP
LDO2-CAP
LDO1-CAP

2
36

+3VS_DVDD

MIC-CAP

1 C583

GND

10U_0603_6.3V6M 2

1 C574

GNDA

7
39
27

10U_0603_6.3V6M 2

1 C584

GNDA

28

R526 2
100K_0402_5%

15
34

CODEC_VREF
20K_0402_1%

AVSS1
AVSS2

GNDA

CPVEE

Close codec
25
38

2

C575
2.2U_0402_6.3V6M

@

2

MONO_IN

+3VS

+3VALW

GND

JP51
JUMP_43X39
2
1
2
JP@ 1

JP53
JUMP_43X39
2
1
2
JP@ 1

GNDA

GND

GND

2

3

3

3

ENHANCE GND

2

2

3

2

2

2

2

DMIC_CLK

1

@

2

D2009
MESC5V02BD03_SOT23-3
@ESD@

1

3

2

1

L76
L77

RING2_L
SLEEVE_L

GND

C2142
ESD@
680P_0402_50V7K

R539
2.2K_0402_5%

2 ESD@
2 ESD@

1
1

RING2
SLEEVE

2

1

2

1

3

C2140
ESD@
680P_0402_50V7K

+MIC2_VREFO

1

GND GND

C607 @ESD@
0.1U_0402_16V4Z

2

2

HP_RIGHT

R237
0_0603_5%
2
1

1

JHP1

HPOUT_L_1

R9

60.4_0603_1%
2
1

R13

60.4_0603_1%
2
1

RING2_L
HPOUT_L_2

3
1

HP_PLUG#

5

HPOUT_R_2

2

SLEEVE_L

4
7

D

3

S

Q9
MESS138W-G_SOT323-3

1
C557
1
C560

LINE1-L

GNDA

LINE1-R

+MICBIAS

6
HPOUT_R_1

2
4.7U_0603_6.3V6K
2
4.7U_0603_6.3V6K

C444
@EMI@
330P_0402_50V7K

D6

GND

2

2 R533
1
4.7K_0402_5%

3

2 R535
1
4.7K_0402_5%

2

1

2

C445
@EMI@
330P_0402_50V7K
1

SINGA_2SJ3080-001111F
CONN@

GNDA

4

1

GND

GNDA

HP_LEFT

R238
0_0603_5%
2
1

100K_0402_5%

1
1

S

2
G

Headphone Out

R550

To solve the background noise while combo jack
connecting to an active
speaker and system entry into S3/S4/S5 without analog
power

BAT54A-7-F_SOT23-3

Issued Date

GNDA

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

2016/03/27

Deciphered Date

Title

HD Audio Codec ALC283

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GNDA

Rev
1.0

Z5WAE LA-B231P

Date:

A

DMIC_DATA

4

R540
2.2K_0402_5%

GNDA

2

4

D

3

@
2 R553
1
10K_0402_5%
1
HDA_RST#_AUDIO 2 R554
10K_0402_5%

EC_MUTE#

1

JP54
JUMP_43X39
2
1
2
JP@ 1

5

S MIC ST MP45DT02TR

RING2

2
G
Q90
2N7002K_SOT23-3

@ C563
1U_0402_6.3V6K

JP52
JUMP_43X39
2
1
2
JP@ 1

2

@
R551
100K_0402_5%

1

<22> EC_MUTE#

JP50
JUMP_43X39
2
1
2
JP@ 1

2

1

+3VLP

1

@
R552
100K_0402_5%

GND

<7> HDA_RST#_AUDIO

1

CLK

GND
2

2
2

GNDA

R531
4.7K_0402_5%

<7> APU_SPKR

2

1

C555
1U_0402_6.3V6K

1

@EMI@
C556
100P_0402_50V8J

R530
47K_0402_5%
2
1

1

<22> EC_BEEP#

1

BEEP#_R

1

MESC5V02BD03_SOT23-3
D10 ESD@

R529
47K_0402_5%
2
1
@

DATA

CS

HPOUT_L_2
HPOUT_R_2

Place next pin27

GND

GND

2
2 2DMIC@ 1
R130
0_0402_5%

@

VDD

+MIC2_VREFO

ALC283-CG_MQFN48_6X6

3

DMIC_CLK

R526 Realtek add request

10mil

2 R546

1

1

1
2

10U_0603_6.3V6M 2

1
DVSS
Thermal PAD

4

3
ENHANCE GND
S MIC ST MP45DT02TR

29

C578
10U_0603_6.3V6M

4
49

JDREF
CPVEE

CLK

DMIC_DATA_S

16

1
VREF

CS

5

+MIC2_VREFO

CPVDD
CPVREF

HDA_SDOUT_AUDIO <7>
HDA_SDIN0 <7>

2
1 R547
33_0402_5%

48

2
1

GND

@

19

1 C585

2 C573 @EMI@
22P_0402_50V8J

1

C577
2.2U_0402_6.3V6M

10U_0603_6.3V6M 2

1 @EMI@ 2
R548 0_0402_5%
HDA_SDOUT_AUDIO
HDA_SDIN0_AUDIO

HDA_SYNC_AUDIO <7>
HDA_BITCLK_AUDIO <7>

C576
0.1U_0402_16V4Z

GNDA

5
8

HDA_SYNC_AUDIO
HDA_BITCLK_AUDIO

DATA

VDD

MESC5V02BD03_SOT23-3
D9 @ESD@

20

10
6

MIC2

6

1

MIC2-VREFO

6

+3VS

@

1

MONO-OUT
SENSE A
SENSE B

MIC1

1

40
AVDD2

46

26

PVDD2

SPDIF-OUT/GPIO2
PCBEEP

Digital MIC
+3VS

GND

2

C570
2.2U_0402_6.3V6M

SDATA-OUT
SDATA-IN

HP_LEFT
HP_RIGHT

GND

2

37
35

ALC283-CG

32
33

1

13
14

GPIO0/DMIC-DATA
GPIO1/DMIC-CLK

SPKR+
SPKR-

1

SENSE_A

SYNC
BCLK

45
44

3

39.2K_0402_1%

HPOUT-L(PORT-I-L)
HPOUT-R(PORT-I-R)

SPKLSPKL+

GND

SP02000K200

R131 1DMIC@
0_0402_5%

1

1

SPK-OUT-R+
SPK-OUT-R-

MIC2-L(PORT-F-L) /RING2
MIC2-R(PORT-F-R) /SLEEVE

43
42

C606
0.1U_0402_16V4Z

2

10mil

12

2

R129 1DMIC@
0_0402_5%

Close codec

R545

HP_PLUG#

MONO_IN

SPK-OUT-LSPK-OUT-L+

LINE2-L(PORT-E-L)
LINE2-R(PORT-E-R)

PDB
RESETB

2

MESC5V02BD03_SOT23-3
D5 @ESD@

47
11

EC_MUTE#
HDA_RST#_AUDIO

1

1
2
5
3 G1 6
4 G2
ACES_88266-04001
CONN@

2

2
3

DMIC_DATA
DMIC_CLK

2

1

GND

LINE1-L(PORT-C-L)
LINE1-R(PORT-C-R)

LINE1-VREFO-L
LINE1-VREFO-R

2

1

1

31
30

+MICBIAS

1

1
2
3
4

SPK_R+
SPK_RSPK_L+
SPK_L-

2

24
23
17
18

AVDD1

DVDD

22
21

GNDA

Place near Pin40

+1.5VS

0_0603_5%

JSPK1

40mil

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

D4 @ESD@
MESC5V02BD03_SOT23-3

U36

2

2
2
2
2

R15 1
R10 1
R12 1
R14 1

D2 @ESD@
MESC5V02BD03_SOT23-3

GND

RING2
SLEEVE

+MICBIAS

R7
1 RS@

10U_0603_6.3V6M
C605

2

LINE1-L
LINE1-R

40mil

0.1U_0402_16V4Z
1
C604

0.1U_0402_16V4Z
2

Place near Pin1

2

SPKR+
SPKRSPKL+
SPKL-

Place near Pin26

+1.5VS_VDDA

1
C582 @

1

41

C637

10U_0603_6.3V6M
2
2
0.1U_0402_16V4Z

Combo MIC

1

Int. Speaker Conn.

+3VS_DVDD

1

PVDD1

C564

GND

EMI@ C366
1000P_0402_50V7K

20mil

2

0_0603_5%

4.75V

(output = 300 mA)

EMI@ C369
1000P_0402_50V7K

GNDA

2

+3VS_DVDD

GND

JUMP_43X118
JP@

40mil

+VDDA

EMI@ C368
1000P_0402_50V7K

1

1

+3VS

2
0.1U_0402_16V4Z

2

0_0603_5%

3

C638

C561

EMI@ C367
1000P_0402_50V7K

Place near Pin46

10U_0603_6.3V6M
2
2
0.1U_0402_16V4Z
R8
1 RS@

C562
@

R11
1 RS@

20mil

1

1

+1.5VS_DVDDIO

9

1

C565

0_0603_5%

0.1U_0402_16V4Z
1

1

GND

GND

Place near Pin41

2

2

1

@

2

C554

0.1U_0402_16V4Z
@ESD@ 2

+AVDD1_HDA

DVDD-IO

+1.5VS

0.1U_0402_16V4Z
1
C559

10U_0603_6.3V6M
C567

R17
1 RS@

C608
10U_0603_6.3V6M

1

+PVDD_HDA

40mil
0.1U_0402_16V4Z
1
C558

2

1
L33 2
HCB2012KF-221T30_0805

+VDDA

2

2

SM01000EJ00 3000ma 220ohm@100mhz DCR 0.04

JP56

1

1

B

C

D

Thursday, March 27, 2014

Sheet
E

25

of

45

A

B

U77 @
5
4
1

1

2

C

VOUT

1

D

E

Mini-Express Card(WLAN/WiMAX) H=4mm

+3VS_WLAN

+3VALW

W=60mils

VIN
GND

+3VS_WLAN

2

3

EN
@
C173
AP2821KTR-G1_SOT23-5
1U_0402_6.3V6K

WLAN_ON <22>

<22> WLAN_WAKE#

1
R1681
R1680 1

@
@

2
10K_0402_5%
2 0_0402_5%

<7> WLAN_CLKREQ#

<8> CLK_PCIE_WLAN#
<8> CLK_PCIE_WLAN
+3VS
R622 1

2 8.2K_0402_5%

@

WLAN_CLKREQ#

<5> PCIE_ARX_DTX_N2
<5> PCIE_ARX_DTX_P2

<5> PCIE_ATX_C_DRX_N2
<5> PCIE_ATX_C_DRX_P2
+3VS_WLAN

2

<22> EC_TX
<22> EC_RX

1 RS@
1 RS@

2 0_0402_5%
2 0_0402_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53

1

Use RX for BT off function

R1498
R1499

JP@
JP5

JMINI1

WLAN_WAKE#_R

3.3V
WAKE#
GND
NC
1.5V
NC
NC
CLKREQ#
NC
GND
NC
REFCLKNC
REFCLK+
NC
GND
GND
NC
NC
NC
PERST#
GND
+3.3Vaux
PERn0
GND
PERp0
+1.5V
GND
SMB_CLK
GND
SMB_DATA
PETn0
GND
PETp0
USB_DGND
USB_D+
NC
GND
NC
LED_WWAN#
NC
LED_WLAN#
NC
LED_WPAN#
NC
+1.5V
NC
GND
NC
+3.3V
NC

GND

+3VS

+3VS_WLAN

+1.5VS

SS

GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

1

JUMP_43X79
2
1
C164 4.7U_0603_6.3V6K
2
1
C941 .1U_0402_16V7K

WL_OFF# <22>
APU_PCIE_RST# <12,23,7>
0_0402_5%
APU_SCLK0_R
R1496 1
@
APU_SDATA0_R R1497 1
@
0_0402_5%

2
2

APU_SCLK0 <10,11,7>
APU_SDATA0 <10,11,7>
USB20_N2 <8>
USB20_P2 <8>

2

54

ACES_50709-0524W-P01

R1501
100K_0402_5%

2

CONN@

For EC to detect
debug card insert.

H3
H10 H11
H6
H9
H5
H4
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

H17 H21
H_6P5 H_3P0
3

1

1

1

1

1

1

1

1

1

3

@

@

@

@

@

@

@

@

@

1

1

@

@

@

FD2

FD1
@

@

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FD3

FD4

1

1

H27
H_3P7

1

1

@

@

@

1

1

@

1

1

H13 H14 H15 H16 H20
H_4P0 H_4P0 H_4P0 H_4P0 H_4P0

4

4

FIDUCIAL_C40M80

@

@

Issued Date

2014/03/27

Deciphered Date

2016/03/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

1

@

H25
H_3P0N

Compal Electronics, Inc.

Compal Secret Data

Security Classification
H23
H_3P5X3P0N

Date:

A

B

C

FIDUCIAL_C40M80

D

MINI CARD (WLAN)/Screw
Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
E

26

of

45

A

B

C

D

E

F

SATA HDD Conn.

G

SATA ODD Conn.

JHDD1

<8> SATA_FTX_DRX_P0
<8> SATA_FTX_DRX_N0

1

<8> SATA_FRX_DTX_N0
<8> SATA_FRX_DTX_P0

SATA_FTX_DRX_P0 C137 1
SATA_FTX_DRX_N0 C138 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_FTX_C_DRX_P0
SATA_FTX_C_DRX_N0

SATA_FRX_DTX_N0 C596 1
SATA_FRX_DTX_P0 C597 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_FRX_C_DTX_N0
SATA_FRX_C_DTX_P0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

<7> DEVSLP0

2

1 RS@

+5VS

+5VS_HDD

R555
0_0805_5%

1

C602
10U_0603_6.3V6M

2

1
@
C598
1000P_0402_50V7K
2
2

1

C599
.1U_0402_16V7K

H

JODD1

GND
A+
AGND
BB+
GND

<8> SATA_FTX_DRX_P1
<8> SATA_FTX_DRX_N1
<8> SATA_FRX_DTX_N1
<8> SATA_FRX_DTX_P1

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

C619 1
C616 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_FTX_C_DRX_P1
SATA_FTX_C_DRX_N1

C614 1
C613 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_FRX_C_DTX_N1
SATA_FRX_C_DTX_P1

1 RS@

+5VS

2

+5VS_ODD

R556
0_0805_5%

T24
1

1

C641
10U_0603_6.3V6M

GND
GND
GND
GND

2

C642
.1U_0402_16V7K

1
2
3
4
5
6
7
8
9
10
11
12
13

GND
A+
AGND
BB+
GND

1

DP
+5V
+5V
MD
GND
GND

GND
GND

14
15

SANTA_201902-1
CONN@

2

23
24
25
26

CCM_C127043HR022M27FZR
CONN@

TPM

FAN Conn

near pin5

2

1

2

LPC_AD3_R
LPC_AD2_R
LPC_FRAME#_R
LPC_AD1_R
LPC_AD0_R
SERIRQ_R

R1684
R1685
R1686
R1687
R1688
R1689

1
1
1
1
1
1

TPM@
TPM@
TPM@
TPM@
TPM@
TPM@

2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

LPC_AD3
LPC_AD2
LPC_FRAME#
LPC_AD1
LPC_AD0
SERIRQ

LPC_AD3 <22,8>
LPC_AD2 <22,8>
LPC_FRAME# <22,7,8>
LPC_AD1 <22,8>
LPC_AD0 <22,8>
SERIRQ <22,8>

2
1
C632
4.7U_0603_6.3V6K
U31
1
2 EN
3 VIN
4 VOUT
VSET

+VCC_FAN

<22> EN_DFAN

near pin10, 19, 24

1

SELECTION

0

2

EEh - EFh

* 1

8
7
6
5

GND
GND
GND
GND

NCT3942S_SO8
@
C626
.1U_0402_16V7K

U2600 TPM@

7Eh - 7Fh

1
2
6
9
15

GPIO3/BADD with Internal PH (default)

3

2 R2602 TPM_BADD
CLKRUN#
<8> CLKRUN#

0_0402_5%

1

@

AMD CLKRUN# no need PH (DG1.1)

LPCPD# had internal PH

R447 1

<8> LPCPD#

@

<7,8> LPC_CLK1

SERIRQ no need PH

<22,7> LPC_RST#

2 0_0402_5%
LPC_CLK1
LPC_FRAME#_R
LPC_RST#
SERIRQ_R

28
21
22
16
27
7

LAD0/MISO
LAD1/MOSI
LAD2/SPI_IRQ#
LAD3
LPCPD#
LCLK/SCLK
LRFAME#/SCS#
LRSET#/SPI_RST#
SERIRQ
PP

VSB
VDD
VDD
VDD
TEST

+3VALW_TPM
+3VS_TPM
3

+VCC_FAN

8

+3VS
NC
NC
NC
NC

3
12
13
14

2
1
C627
4.7U_0603_6.3V6K
2
1
C631
@
1000P_0402_50V7K

R516
10K_0402_5%

40mil
GND
GND
GND
GND

4
11
18
25

<22> FAN_SPEED
C630
1000P_0402_50V7K
@EMI@

1

2

NPCT650AA0WX_TSSOP28

+3VS_TPM
2
1
@
10K_0402_5%
R2604

4

26
23
20
17

LPC_AD0_R
LPC_AD1_R
LPC_AD2_R
LPC_AD3_R

GPIO0/XOR_OUT
GPIO1
GPIO2/GPX
GPIO3/BADD
GPIO4/CLKRUN#

5
10
19
24

1

BADD

2

1

C2605 TPM@
0.1U_0402_16V4Z

2

1

C2604 TPM@
0.1U_0402_16V4Z

1

C2603 TPM@
0.1U_0402_16V4Z

2

+5VS

close to EC
C2602 TPM@
10U_0603_6.3V6M

2

1

R2601
2
1
0_0603_5%
TPM@

C2601 TPM@
0.1U_0402_16V4Z

1

C2600 TPM@
10U_0603_6.3V6M

R2600
2
1
0_0603_5%
TPM@

2

+3VS_TPM

+3VS

+3VALW_TPM

+3VALW

2

2

1
2 GND
3 GND

0118 modify
4
5

ACES_88231-03041
CONN@

SP020020710

SA00007IO00

CLKRUN#

JFAN1
1
2
3

4

CLKRUN# PH request by TPM chip DG 1/22

2 33_0402_5% C2606 1

LPC_CLK1 R2603 1

Deciphered Date

2016/03/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@EMI@

@EMI@

2014/03/27

Issued Date

2 22P_0402_50V8J

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Date:

A

B

C

D

E

F

HDD/ODD/FAN/TPM
Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014
G

Sheet

27

of
H

45

5

4

3

2

1

+USB3_VCCA
+5VALW
1 @EMI@ 2
R566
0_0402_5%

U35

@
C704
.1U_0402_16V7K

L51 EMI@
1

<8> USB20_N8

1

2

4

3

2

USB20_N8_R

D

4

<8> USB20_P8

+USB3_VCCA

3

1

2
3
USB_EN# 4
1

2

IN
IN
EN/ENB
GND

OUT
OUT
OUT
OCB

W=80mils

6
7
8
5

1

C736

USB_OC0# <7>

SY6288D10CAC_MSOP8

USB20_P8_R

+

150U_6.3V_M_D2
2

1

2

EMI@
C735
470P_0402_50V7K

D

2A/Active Low

DLW21HN900HQ2L_4P
2
@EMI@ 0_0402_5%

1

R562

W=80mils
+USB3_VCCA
1

1 @EMI@ 2
R567
0_0402_5%

USB3.0 Port0

2

C943 ESD@
.1U_0402_16V7K

1

<8> USB3_FRX_DTX_P0

4

<8> USB3_FRX_DTX_N0

1

2

4

3

2

USB3_FRX_L_DTX_P0

3

USB3_FRX_L_DTX_N0

USB20_N8_R
USB20_P8_R

2
@EMI@ 0_0402_5%

1

R563

C

1 @EMI@ 2
R568
0_0402_5%

USB3_FRX_L_DTX_N0
USB3_FRX_L_DTX_P0

USB3_FRX_L_DTX_N0

D27
@ESD@
9 10

1

1

USB3_FRX_L_DTX_N0

USB3_FRX_L_DTX_P0

8

9

2

2

USB3_FRX_L_DTX_P0

USB3_FTX_L_DRX_N0

7

7

4

4

USB3_FTX_L_DRX_N0

USB3_FTX_L_DRX_P0

6

6

5

5

USB3_FTX_L_DRX_P0

3

3

DLW21HN900HQ2L_4P

JUSB1
1
2
3
4
5
6
7
8
9

L50 EMI@

USB3_FTX_L_DRX_N0
USB3_FTX_L_DRX_P0

VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+

GND
GND
GND
GND

10
11
12
13
C

ACON_TARAC-9V1391
CONN@

L49 EMI@

<8> USB3_FTX_DRX_P0

1
C859

2 USB3_FTX_C_DRX_P0
.1U_0402_16V7K

1

1

2

2

USB3_FTX_L_DRX_P0

8
YSCLAMP0524P_SLP2510P8-10-9

<8> USB3_FTX_DRX_N0

1
C858

2 USB3_FTX_C_DRX_N0
.1U_0402_16V7K

4

4

3

3

USB3_FTX_L_DRX_N0

DLW21HN900HQ2L_4P

1

R564

2
@EMI@ 0_0402_5%

USB/B(USB Port 0, Port1)

1 @EMI@ 2
R569
0_0402_5%

B

<8> USB20_N0

USB20_N0_R

2

USB20_P0_R

1

<8> USB20_P0

+5VALW

DLW21HN900HQ2L_4P
3
4
3
4
1
L52 EMI@

1

R565

2

JUSB2

<22> USB_EN#

USB20_N0_R
USB20_P0_R

2
@EMI@ 0_0402_5%

USB20_N1_R
USB20_P1_R

1 @EMI@ 2
R570
0_0402_5%

<8> USB20_N1

DLW21HN900HQ2L_4P
3
4
3
4

USB20_N1_R

2

USB20_P1_R

1

<8> USB20_P1

1
L53 EMI@

1

R571

2

1
2
3
4
5
6
7
8
9
10
11
12
13
14

B

1
2
3
4
5
6
7
8
9
10
11
12
13
14

ACES_88514-01201-071
CONN@

SP01001BF00

2
@EMI@ 0_0402_5%
A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

USB2.0 / USB3.0
Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
1

28

of

45

C663 @
0.1U_0402_16V4Z
2
1

1
R132
1
R133

E-T_6916K-Q08N-00L
CONN@

+3VALW

2

1

2

@EMI@ C551
100P_0402_50V8J

TP_I2C_INT# <22>
TP_SENOFF# <22>

1

TP_I2C_INT#_D

1

2

U78
5

GND

C523 @
4.7U_0603_6.3V6K

2
+VDDD_M 1
@
R139
0_0402_5%
2
1
@
+TPUSB_VCC
R147
0_0402_5%
+3VS

2

SS

1

EN

3

TP_3V_EN <22>

SCB_0/GPIO_6
SCB_5/GPIO_7
VSSD
GPIO_8
GPIO_9
GPIO_10
GPIO_11
SUSPEND
WAKEUP
USBDP
USBDM
VCCD

CY7C65211-24LTXI_QFN24_4X4

KB BackLight Conn. Reserve
+5VS

@

3

2

5
G

S

3

I2C_DAT

2 0_0402_5%
2 0_0402_5%

1

2
1

APU_SCLK1
APU_SDATA1

R135 1 TPSM@ 2 0_0402_5%
R136 1 TPSM@ 2 0_0402_5%

I2C_CLK
I2C_DAT

R140 1
R141 1

@
@

2 0_0402_5% USB20_P6_R
2 0_0402_5% USB20_N6_R

USB20_P6_R R143 1
USB20_N6_R R142 1

@
@

2 0_0402_5%
2 0_0402_5%

I2C_DAT_R
I2C_CLK_R

R144 1 TPUSB@2 0_0402_5%
R145 1 TPUSB@2 0_0402_5%

I2C_DAT_R
I2C_CLK_R

I2C_DAT
I2C_CLK

3

C524
0.1U_0603_25V7K
@

12MHZ_18PF_7V12000001
Part Number = SJ10000C210
PCB Footprint = Y_CRG3201212_4P

@

2

1

1

C73
33P_0402_50V8J

2

S

TPUSB_X2

@

@

2.2K_0804_8P4R_5%

C62
33P_0402_50V8J

D
G

@

4

USB20_P6
USB20_N6

@
2
1 R939
1M_0402_5%

+3VALW

1

2

Q85 @
2N7002K_SOT23-3

8
7
6
5

R452
10K_0402_5%

SP01000Z300

<7> APU_SCLK1
<7> APU_SDATA1

+3VS
RP24
1
TP_I2C_CLK
2
TP_I2C_DAT
TP_I2C_INT#_D 3
TP_I2C_INT#_APU4

@
@

TP SMBus to CPU

2

2

G

ACES_50504-0040N-001
CONN@

R122 1
R123 1

TPUSB_X1

1

D

S

1
RS@ 2
R592
0_0402_5%

6
5

I2C_CLK

2N7002K_SOT23-3
2 0_0402_5%

2.2K_0804_8P4R_5%
G2
G1

TP_I2C_DAT

TP_I2C_INT#

Y9
JBL1

<22> KBL_EN#

8
7
6
5

1
2
3
4

1
6
Q2505B TPUSB@
DMN66D0LDW-7_SOT363-6
Q2505A TPUSB@
DMN66D0LDW-7_SOT363-6
4

S

D
@ Q92
R150 1

RP20

I2C_DAT
I2C_CLK
TP_I2C_INT#

TP_I2C_CLK

<22> TP_I2C_CLK

<22> TP_I2C_DAT
3

1

<7> TP_I2C_INT#_APU

2

TP I2C to bridge & EC

2N7002K_SOT23-3
2 0_0402_5%

+TP_VCC

+TP_VCC

4
3
2
1

+TPUSB_VCC

D

+3VALW

@

4.7K_0804_8P4R_5%

4
3
2
1

1

G

TPUSB@ Q87
R126 1

2

8
7
6
5

1
2
3
4

TP_I2C_INT#

G

KSO[0..17] <22>

+5VS_BL

1

2

C43 TPUSB@
1U_0402_6.3V6K

D

TP_CLK
TP_DATA
APU_SCLK1
APU_SDATA1

KSI[0..7] <22>

1

1

2

+3VS
1

S

+TP_VCC

3

1

2

1

2

3

TP_I2C_INT#_D
RP19

BL@
Q44
R451
100K_0402_5% DMG2301U-7_SOT23-3
1
BL@ 2 KBL_EN_R

2

AP2821KTR-G1_SOT23-5

SP01000IJ00

+5VALW

VDDD
SCB_4/GPIO_5
SCB_3/GPIO_4
SCB_2/GPIO_3
SCB_1/GPIO_2
GPIO_1
GPIO_0
VSSA
VSSD
VBUS
nXRES
VSSD
thermal pad

D

@ C1280
1U_0402_6.3V6K

2

<8> USB20_P6
<8> USB20_N6

2

27
28

1

VIN

4
G1
G2

1

2 .1U_0402_16V7K
1
+VDDD_M_M
4.7U_0603_6.3V6K

@ C668 1
2
@ C836

+TP_VCC
VOUT

+VDDD_M

C831 TPUSB@
4.7U_0603_6.3V6K

I2C_DAT_R
I2C_CLK_R
TP_I2C_INT#
TP_SENOFF#

+VDDD_M_M

TP_CLK
TP_DATA

TP_CLK <22>
TP_DATA <22>

+VDDD 2
RS@ 1
R137
0_0402_5%
TP_I2C_DAT
TP_I2C_CLK
TPUSB_X2
TPUSB_X1
2
1
@
+5VS
R148
0_0402_5%
1
+VBUS 2
R138 @
0_0603_5%
1
T26 2
R149 TPUSB@
0_0603_5%

24
23
22
21
20
19
18
17
16
15
14
13
25

C666 TPUSB@
0.1U_0402_16V4Z

8
7
6
5
4
3
2
1

G2
G1

+TPUSB_VCC

U69 TPUSB@
1
2
3
4
5
6
7
8
9
10
11
12

+VBUS

+VDDD

C828 TPUSB@
4.7U_0603_6.3V6K

R146
0_0402_5%
2
1
@

+TP_VCC

+3VALW
+3VS

C665 TPUSB@
0.1U_0402_16V4Z

10
9

8
7
6
5
4
3
2
1

E-T_6905-E26N-01R
CONN@

KSO[0..17]

2
1
+TPUSB_VCC
@
R151
0_0603_5%
2 TPUSB@1
R152
0_0603_5%

+3VS
+3VALW

JTP1

2

KSI[0..7]

2
0_0402_5%
2
0_0402_5%

@
@

G

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

+TP_VCC

To TP/B Conn.

S

JKB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

C667 @
0.1U_0402_16V4Z

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

@EMI@ C553
100P_0402_50V8J

KB Conn.

PWR/B

+3VALW

LED6

JPWR1

7
8

1
2
3
4
G1 5
G2 6

1
2
3
4
5
6

+3VALW
+3VLP
LID_SW# <22>

PWR_LED#
ON/OFFBTN#

<22> BATT_BLUE_LED#

<22> BATT_AMB_LED#

BATT_BLUE_LED# 1

BATT_AMB_LED#

3

<22> PWR_LED#

+3VLP
2

R534
100K_0402_5%

SW3
TJE-532QR5_6P
1
2
6
5

4

2
200_0402_5%

4

1
R698

2
390_0402_5%

<22> PWR_SUSP_LED#

PWR_LED#

1

PWR_SUSP_LED# 3

B
A

2

1
R700

2
200_0402_5%

4

1
R701

2
390_0402_5%

LTST-C295TBKF-CA_AMBER-BLUE

ON/OFFBTN#

1

3

A

1
R699

LTST-C295TBKF-CA_AMBER-BLUE
LED7

ACES_51524-0060N-001
CONN@

ON/OFF BTN

B

2

ON/OFFBTN# <22>

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

P21-PBTN/LIDSW/LED/KB/TP
Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet

29

of

45

A

B

C

D

VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
U2

+3VALW

1

+5VALW TO +5VS
+3VALW TO +3VS
Load switch

<22,36> SUSP#

1 RS@

2

3VS_ON

R1667
0_0402_5%
2
1 RS@

R1668
0_0402_5% 1
@
C37
.1U_0402_16V7K
2

1
2

2
1
C12
@
1U_0402_6.3V6K 3

4

+5VALW

5

5VS_ON
+5VALW
1

2

@
C38
.1U_0402_16V7K

6
7
2
1
C11
@
1U_0402_6.3V6K

E

+3VS
JP7 JP@

VIN1
VIN1

VOUT1
VOUT1

ON1

CT1

VBIAS

14
13

CT2

VIN2
VIN2

VOUT2
VOUT2

2

JUMP_43X118
2
1
C10
560P_0402_50V7K

12

11

GND

ON2

+3VS_LS

10

1

2
1
C9
330P_0402_50V7K JP8 JP@
+5VS_LS

9
8
15

GPAD

1

@
C13
.1U_0402_16V7K

+5VS

2

JUMP_43X118

TPS22966DPUR_SON14_2X3

1

@
C14
.1U_0402_16V7K

VIN 1.8V and 1.5V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
+1.8VS
U3

+1.8VALW
2

1.8VS_ON

R1669
0_0402_5%
2
1 RS@

R1670
0_0402_5% 1
@
C42
.1U_0402_16V7K
2

2
1
C24
@
1U_0402_6.3V6K 3

4

+5VALW

5

1.5VS_ON

1

2

+1.5V
@
C41
.1U_0402_16V7K

2
1
C22
@
1U_0402_6.3V6K

6
7

VIN1
VIN1

VOUT1
VOUT1

ON1

CT1

VBIAS

2
1
C21
330P_0402_50V7K

11
10

CT2

2
1
C15
330P_0402_50V7K
+1.5VS_LS

9
8

VOUT2
VOUT2

VIN2
VIN2

12

2

JUMP_43X118

GND

ON2

+1.8VS_LS

15

GPAD

1

+1.5VS

2

JUMP_43X79

4

2

3

1
D

3

R1671 @
470_0603_5%

C16
.1U_0402_16V7K

D

0.95VS_PWR_EN# 2

Q83 @
2N7002K_SOT23-3

G

2

2

S

G
3

<22> 0.95VS_PWR_EN#

@2

0.95VS_GATE
1

2
1
R1674
4.7K_0402_5%

+0.95VALW to +0.95VS

2

+0.95VS

1

1 2

+5VALW

1

C46
1U_0402_6.3V6K

1

@
C25
.1U_0402_16V7K

+0.95VS
1
2
3

C939
4.7U_0603_6.3V6K

C940
4.7U_0603_6.3V6K

1

U4
AO4304L_SO8
8
7
6
5

2

JP10JP@

TPS22966DPUR_SON14_2X3

+0.95VALW

@
C26
.1U_0402_16V7K

1

+1.8VALW TO +1.8VS
+1.5V TO +1.5VS
Load switch

SUSP# 1 RS@

JP9 JP@
14
13

3

2

1
2

S Q84
2N7002K_SOT23-3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

P22-DC INTERFACE
Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
E

30

of

45

5

4

3

2

1

0.2

D

1. Add R693 for UMA/DIS select
2. Change R756,R765,R769,R779,R781,R782,R783 and R794 to Rshort for EMI request
3. Change BID to 1 for DVT
4. Change LAN_WAKE# PU to +3V_LAN
5. Add L76,L77,C2142 and C2140 for ESD request
6. Change R238 and R237 to 59ohm
7. Add L52,L53,R565,R569,R570 and R571 for EMI request.
8. Add R140,R141,R142,R143,R144 and R145 for reserve USB TP
9. Pop Q89, unpop R1690
10. Change D10 to SCA00001B00
11. Change L11 to SM01000EJ00
12. Add U39,R833,C185,R1578 for VGA power sequence issue
13. Remove APU_ALERT#_R
14. Add C668 and C836 for vendor request

D

0.3

C

1. Change JTP1
2. Add U78 for TP +3V power plane
3. Change C849, C849 to 10p
4. Change C736 to 150u D2 type.
5. Change R699, R700 to 330ohm; R698, R701 to 560ohm
6. Change U69 +3VALW to +3VS
7. Add C366, C367, C368, C369 for EMI request
8. Add on board TPM
9. Add R619

C

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

HW-PIR
Size
C
Date:

5

4

3

2

Document Number

Rev
1.0

Z5WAE LA-B231P
Thursday, March 27, 2014

Sheet
1

31

of

45

A

B

C

D

VIN

1

@
PJP101
ACES_50305-00441-001_4P

DC_IN_S1

1
EMI@ PC102
100P_0603_50V8

2

2

1

1
2
3
4
GND
GND

1

EMI@ PL101
HCB2012KF-121T50_0805
2
1

EMI@ PC103
1000P_0603_50V7K

2

2

+RTC_APU

3
2
1

2

+RTCVCC

Vo=1.5V

PC111
0.1U_0603_25V7K

PD101
BAS40-04_SOT23-3

Vout

Vin

3

1

GND

1

1

PU101
AP2138N-1.5TRG1_SOT23-3

2

PC110
680P_0603_50V8J

+RTCBATT

2

+CHGRTC

3

3

@ PR111
0_0402_5%
2
1

+3VLP

-

PBJ101 @
2

+
1

PR112
560_0603_5%
2
1

+CHGRTC

PR113
560_0603_5%
2
1

+RTCBATT

ML1220T13RE

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

Title

DCIN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

Rev
1.0

Thursday, March 27, 2014
D

Sheet

32

of

45

A

B

C

D

+3VLP

PR201
6.49K_0402_1%
2
1
PR210
1K_0402_1%

TH

1

2

@ PU201

1

@ PR206
100K_0402_1%

+3VLP

VCC TMSNS1

2
MAINPWON

<22,35> MAINPWON

BATT_TEMP<22>

GND RHYST1

3

OT1 TMSNS2

4

OT2 RHYST2

8
2

7

6

1

@ PR207
47K_0402_1%

@ PH201
100K_0402_1%_B25/50 4250K

5

G718TM1U_SOT23-8

PR211

BI

1
2

EC_SMB_CK1 <22,34>

1

1

1

@ PR205
10K_0402_1%

@ PR204
10K_0402_1%

EC_SMB_DA1 <22,34>

2

2

1

1
EC_SMCK

100_0402_1% PR208
2
1

@ PC202
0.1U_0603_25V7K

2

100_0402_1% PR209
2
1

1

EC_SMDA

2

1

@ PJP201
SUYIN_200275GR008G13GZR
10
GND 9
GND 8
8 7
7 6
6 5
5 4
4 3
3 2
2 1
1

2

0_0402_5%
EMI@ PL201
HCB2012KF-121T50_0805
2
1

BATT_S1

1
2

BATT+ <45,47>

EMI@ PL202
HCB2012KF-121T50_0805
2
1
EMI@ PC201
1000P_0402_50V7K

2014/01/02 update
For KB9012
OTP

2

---Battery_pin define--PIN1 GND
PIN2 GND
PIN3 SMD
PIN4 SMC
PIN5 TS
PIN6 B/I
PIN7 Batt+
PIN8 Batt+

℃
56℃

---Battery Con_pin define--PIN8 GND
PIN7 GND
PIN6 SMD
PIN5 SMC
PIN4 TS
PIN3 B/I
PIN2 Batt+
PIN1 Batt+

For KB9022
OTP

92

For KB9022
sense 20mΩ

Active

Recovery

70W,0.73V

55.9W,0.59V

2

1.0V
2.0V

PR216

65W

16.9K ohm
2013/10/22 Modify
PH201,PH202 change to common part.

PH201 under CPU botten side :
CPU thermal protection at 92 degree C ( shutdown )
Recovery at 56 degree C
+EC_VCCA

2013/10/02
Add for ENE9022 Battery Voltage drop detection.
Connect to ENE9022 pin64 AD1.

2013/12/16 Modify
Delete PR223.(remove HW hysteresis)

ADP_I <22,34>
1

Battery is 3-cell design.
B+=9V

PR216
16.9K_0402_1%

2

1

2013/10/25 Modify
PR227(9012@) change to 26.1K ohm.
2014/02/07 Modify
Delete @PR227.(remove HW hysteresis)

2

@

@

PR203
10K_0402_1%

2

2
4

PR226
1_0402_1%

1

2

For 65W adapter==>action 70W , Recovery 55.9W

1

9022@ PR228
10K_0402_1%

PH202
100K_0402_1%_B25/50 4250K

B value:4250K±1%

2

VCIN1_BATT_DROP<22>

1

2

9012_VCIN <22>

<22> 9012_PH1

PR225
0_0402_5%

@ PR229
0_0402_5%
2
1

1

@9022@ PC203
0.1U_0402_25V6

PR202
10K_0402_1%

2
9022@
PR230
80.6K_0402_1%

1

2

1

B+

3

1

3

4

ECAGND

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

Title

BATTERY CONN / OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

Rev
1.0

Thursday, March 27, 2014
D

Sheet

33

of

45

A

B

C

D

Rds(on) = 15.8mohm max
Vgs = 20V
Vds = 30V
ID = 10.5A (Ta=70C)

VIN

CMSRC

SRP

ACDRV

SRN

4

PC318
0.1U_0603_16V7K

ILIM

1
2

1

PR317
100K_0402_1%

1

2

PR316
316K_0402_1%

1

ADP_I <22,33>

2

1
2

3

PC315
10U_0805_25V6K

2

1

CSOP1
1
2

PR311
0.01_1206_1%
4

PC316
0.1U_0402_25V6

1
2

1

2

BATT+

**Design Notes**
#For 65 /90W system, 3S1P/3S2P battery
Maximum Charging current 3.5A
Maximum Battery discharge power 55W.
#Register Setting
1. 0X12 bit8 set 0 (default 1) to disable IFAULT HI if add ISN choke
#Circuit Design
1. ACOK,ILIM pull high voltage need base on 3/5V enable control
2. Use 10X10 choke and 3X3 H/L Side MOSFET
Charge current 3.5A
Power loss : 1.82W
Power density : 0.81 (15X15)
3. If use 4S per cell 4.35V battery, need additional circuit
for ACDET(PR218/PR220/PR222 change to 0.1%, parallel resistors
with PR222 for ACDET setting)
4. PC223 0.22U can't be changed. (Wrong adapter concern)
5. For the design, need double confirm PQ202,PQ203,PQ204 rating
#Protect function
1. ACOVP : ACDET voltage > 3.14V
2. Charger timeout : No communication within 175s(default)
3. ACOC : 3.33 X Input current DAC setting(default)
4. CHGOCP : 3/4.5/6A based on current current setting
5. BATOVP : 103-106%
6. BATLOWV : 2.5V
7. TSHUT : 155C
8. IFAULT HI : 750mV (default)
9. IFAULT LOW : 150mV (default)

EC_SMB_DA1 <22,33>

2014/01/24 update

CHG

PC314
10U_0805_25V6K

PQ305
AON7408L_DFN8-5

1

BQ24725A_BATDRV

10

SCL
9

SDA

3
2
1

11

+3VALW

@ PR320
0_0402_5%
2
1

2

1

5

12

PR313
10_0603_1%
2 CSOP1
SRP1
PR314
6.8_0603_1%
2 CSON1
SRN1

13

BQ24725A_ILIM

2

BQ24725A_ACDET

2

2

1

@EMI@ PC306
0.1U_0402_25V6

1
2

4

14

EC_SMB_CK1 <22,33>

PC322
100P_0402_50V8J
2
1

PC321
0.22U_0402_16V7K
2
1

PR319
66.5K_0402_1%
2
1

PR318
422K_0402_1%
2
1

VIN

8

6

<22> ACIN
3

BATDRV

IOUT

ACOK

DL_CHG

2

GND

7

PR315

PL302
10UH_3.5A_20%_7X7X3_M

@EMI@ PC319 @EMI@ PR312
680P_0402_50V7K 4.7_1206_5%

ACP

15

PQ306
AON7408L_DFN8-5

LODRV

BQ24725A_IOUT

+3VLP

5

5

1
2
BQ24725A_REGN

16

PR307
2.2_0603_5%
1
BQ24725A_BST2

17
BTST

DH_CHG
18

2

Power loss: 0.32W for 3.5A
CSR rating: 1W
VSRP-VSRN spec < 81.28mV

7X7X3
Isat: 3.5A

BQ24725A_LX

ACN

ACDET

BQ24725A_ACDRV 4
2
100K_0402_1%

1

4

PC313
1U_0603_25V6K

BQ24725ARGRR_QFN20_3P5X3P5

BQ24725A_CMSRC 3

PR308
0_0402_5%
2
1

DH_CHG

3
2
1

PR306
10_1206_1%

BQ24725A_LX
19

PD302
RB751V-40_SOD323-2

1

2BQ24725A_BATDRV_1

1

PR305
4.12K_0603_1%

1

2

PAD

VF = 0.37V

REGN

1

HIDRV

21

PHASE

1 1

PU301

20

1U_0603_25V6K

BQ24725A_BATDRV

2

2

3
2

PC312
2
1

BQ24725A_VCC2

1

1
2

PC309
0.1U_0402_25V6

PQ304
AON7506_DFN33-8-5

Rds(on) = 30mohm max
Vgs = 20V
Vds = 30V
ID = 7A (Ta=70C)

PC311
0.047U_0402_25V7K
2
1

1
2
3

5

PD301
BAS40CW _SOT323-3

VCC

1
2

PR310
4.12K_0603_1%

1

2

BQ24725A_ACN

2

1

BQ24725A_ACP

2

PR309
4.12K_0603_1%

PC308
0.1U_0402_25V6

BQ24725A_ACDRV_1

VF = 0.5V

EMI@ PC305
2200P_0402_25V7K

VIN

1

1

PQ303
AON7506_DFN33-8-5

2

3

PC304
10U_0805_25V6K

2

1

CHG_B+

EMI@ PL301
1UH_2.8A_30%_4X4X2_F
2
1

PC320
0.01U_0402_25V7K

PR303
0.02_1206_1%
4

PC303
10U_0805_25V6K

1

2

4

5

PC310
0.1U_0402_25V6

1
2

PC302
0.1U_0402_25V6

1

@ PR304
0_0402_5%

4

PQ302
AON6414AL_DFN8-5

2

1

PC301
2200P_0402_50V7K

5

2

P2
1
2
3

2

P1
1
2
3

1

3M_0402_5%

PC307
0.01U_0402_50V7K

1M_0402_5%

Need check the SOA for inrush

CSON1

1

Rds(on) = 15.8mohm max
Vgs = 20V
Vds = 30V
ID = 10.5A (Ta=70C)

2

1

PC317
0.1U_0402_25V6

2

B+

S 2N7002KW _SOT323-3

PR302

PR301
1

2013/10/14
PR303 10m ohm chang -->20m ohm
SD00000S120

Vgs = 20V
Vds = 60V
Id = 250mA

1

3

2
G

D

2013/10/16 Modify
PQ305,PQ306 change to AON7408L.
2013/10/22 Modify
PL302 change to common part.
2013/11/29 Modify
PL301 change to common part.

2

PQ201

1

Protection for reverse input

@ PC323
100P_0402_50V8J

3

Close EC chip
4

4

Vin Dectector
L-->H
H-->L

Min.
17.16V
16.76V

Typ
17.63V
17.22V

Max.
18.12V
17.70V
Compal Secret Data

Security Classification

VILIM = 20*ILIM*Rsr
ILIM = 3.3*100/(100+316)/20/0.01
= 3.966 A

Issued Date

2014/03/27

Deciphered Date

2016/03/27

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

Compal Electronics, Inc.
CHARGER
Document Number

Rev
1.0

Thursday, March 27, 2014
D

Sheet

34

of

45

A

B

C

D

E

Module model information
SY8208B_V2.mdd
SY8208C_V2.mdd

1

1

EN1 and EN2 dont't floating
PR402
499K_0402_1%
2
1

PC402
PR403
0.01U_0402_25V7K 1K_0402_5%
2
1
2
1

PU401
7
8

PC406
10U_0805_25V6K
2
1

3V_VIN

EN2
IN

EN1
FB

BS

1
3

6

3V_EN <22>

3V_FB
PR401
2
1
BST_3V
2.2_0603_5%

PC403
2
PL402

PR412
100K_0402_5%
2

3.3V LDO 150mA~300mA

<22> SPOK

PC410
22U_0603_6.3V6M

PC409
22U_0603_6.3V6M
2
1

1
2

PC408
22U_0603_6.3V6M
2
1

1

2

PC411
4.7U_0603_6.3V6M

+3VALWP
PC407
22U_0603_6.3V6M
2
1

+3VLP

PR405
1

5

2
1 3V_SN

LDO

2

1.5UH_PCMB053T-1R5MS_6A_20%

680P_0603_50V7K 4.7_1206_5%

PG

@EMI@

OUT

PC412
2

2

GND

1

LX_3V

4

@EMI@

9

10

SY8208BQNC_QFN10_3X3

2

B+

0.1U_0603_25V7K
LX

@

+3VALWP

Check pull up resistor of SPOK at HW side

1

1

PC405
10U_0805_25V6K
2
1

EMI@ PC404
2200P_0402_50V7K
2
1

EMI@ PL401
HCB2012KF-121T50_0805
2
1
@EMI@ PC401
0.1U_0402_25V6
2
1

B+

PR404
150K_0402_1%
2
1

ENLDO_3V5V

22u Capacitor change to 0603 size.
2013/10/16 modify.

2

Vout is 3.234V~3.366V
TDC=6A
@ PJ401
1

+3VALWP

1

2

2

+3VALW

JUMP_43X118

B+

EN1 and EN2 dont't floating

EMI@ PL403
HCB2012KF-121T50_0805
2
1

5V_VIN
@ PJ402

@EMI@ PC418
0.1U_0402_25V6
2
1

8

FB

1

PR407
2.2_0603_5%
2

1

2

2

+5VALW

JUMP_43X118

TDC=6A

PC416
0.1U_0603_25V7K
2
1

@ PR410
2

Add non-pop PR413 for Test.
2013/11/04 modify.

0_0402_5%

@ PC428
22U_0603_6.3V6M

@ PC427
22U_0603_6.3V6M
2
1

PC423
22U_0603_6.3V6M
2
1

PC422
22U_0603_6.3V6M
2
1

1

PC424
4.7U_0603_6.3V6M

5V LDO 150mA~300mA

PC421
22U_0603_6.3V6M
2
1

VL

PC420
22U_0603_6.3V6M
2
1

7

1

LDO

+5VALWP

2

PG

SY8208CQNC_QFN10_3X3

2

1.5UH_PCMB053T-1R5MS_6A_20%
680P_0603_50V7K 4.7_1206_5%

OUT

1

LX_5V
PR408
1

VCC

10
4

PC425
2
2
1 5V_SN

LX

@EMI@

2

GND

2

SPOK_5V
1
2

1

<22,33> MAINPWON

5V_FB

BST_5V

@EMI@

5

SPOK

PR409
2.2K_0402_5%
2
1

3
6

3V5V_EN

1

+5VALWP

PL404

9

PC419
4.7U_0603_6.3V6M

1
2

<22> EC_ON

EN

BS

VCC_3V
3

IN

1

@ PR413
0_0402_5%

@

EMI@ PC417
2200P_0402_50V7K
2
1

PC415
10U_0805_25V6K
2
1

PC414
10U_0805_25V6K
2
1

Vout is 4.998V~5.202V
PR406
PC413
6800P_0402_25V7K 1K_0402_5%
2
1
2
1

PU402

3

22u Capacitor change to 0603 size.
2013/10/16 modify.
reserve PC427,PC428 for IC Application.
2013/11/29 modify.

1
2

PC426
4.7U_0402_6.3V6M

2

1
PR411
1M_0402_1%

3V5V_EN

EC VDD0 is +3VL, PC13 UNPOP
EC VDD0 is +3VALW, PC13 POP

4

4

Compal Secret Data

Security Classification
2014/03/27

Issued Date

2016/03/27

Deciphered Date

Title

Compal Electronics, Inc.
+3VALW/+5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
1.0

Thursday, March 27, 2014

Sheet
E

35

of

45

5

4

3

2

1

Module model information
RT8207M_V1.mdd
RT8207M_V2.mdd

For Single layer
For Dual layer
D

D

VTTREF_1.5V
off
on
on

Note: S3 - sleep ; S5 - power off

@ PC514
0.1U_0402_10V7K

L/S Rds(on): 13mohm(Typ), 15.8mohm(Max)
Idsm: 12A@Ta=25C, 10.5A@Ta=70C

1
1

+1.5VP

2

PC510
0.033U_0402_16V7K

6

PR506
10K_0402_1%
2
1

+1.5VP
B

PR508
10K_0402_1%

@ PR510
0_0402_5%
2
1

@ PJ501

1

+1.5VP
1

<22,30> SUSP#

2

1

2

2

+1.5V

JUMP_43X118
@ PJ502
2
1
2
1

@ PC515
0.1U_0402_10V7K

JUMP_43X118

PJ503
@

1

+0.75VSP

1

2

2

+0.75VS

JUMP_43X39

Compal Secret Data

Security Classification
Issued Date

2014/03/27

Deciphered Date

2016/03/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

PC507
10U_0805_6.3V6K

VTTREF_1.5V

5

@ PR509
0_0402_5%
2
1

<22> SYSON

for this project
Switching Frequency: 285kHz
Ipeak=11A
OCP:15.939A~13.371A
OVP: 110%~120%
VFB=0.75V, Vout=1.515V

5

2

1

VTT

2

4

FB

S3

S5

3

1

MOSFET: 3x3 DFN
H/S Rds(on): 27mohm(Typ), 34mohm(Max)
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C

Choke: 7x7x3
Rdc=8.3mohm(Typ), 10mohm(Max)

A

PC506
10U_0805_6.3V6K

20

19
VLDOIN

BOOT

18

17
UGATE

TON

2

FB_1.5V

PR507
887K_0402_1%
2
1

7

1.5V_B+

VDDQ

EN_0.75VSP

VDD

1

2

+0.75VSP
off
off
on

VTTREF

VDDP

10

+5VALW

2

PC513
1U_0603_10V6K

GND

RT8207MZQW _W QFN20_3X3

C

1

Level
L
L
H

CS

21

2

Mode
S5
S3
S0

11

PAD

VTTSNS

1

VDD_1.5V

12

PU501

VTTGND

PGND

9

5

+5VALW

1
2
3

PQ502
AON7506_DFN33-8-5

4

PR504
5.1_0603_5%
2
1

13

LGATE

8

14
PR502
22.6K_0402_1%
2 CS_1.5V
1
PC508
1U_0603_10V6K
2
1

2013/10/14 update
PQ502__AON7702A EOL chang
-->AON7506_SB000010A00

B

15

EN_1.5V

DL_1.5V

TON_1.5V

4

1
1 2
@EMI@ PC512
680P_0402_50V7K

2

2

ESR=17m ohm

PC509
330U_2.5V_ESR17M_6.3X4.5

+

@EMI@ PR503
4.7_1206_5%

+0.75VSP

PHASE

16

PC501
0.1U_0603_25V7K

1
2
3

PL502
1UH_11A_20%_7X7X3_M
2
1

+1.5VP

SW _1.5V

1
2

5

2013/10/22 Modify
PL502,PC509 change to common part.

1

BOOT_1.5V

0.75Volt +/- 5%
TDC 1.4A
Peak Current 2A

DH_1.5V

PQ501
AON7408L_DFN8-5

C

+1.5VP

PR501
2.2_0603_5%
2
1

PGOOD

1
2

BST_1.5V

PC505
10U_0805_25V6K

1
2

PC504
10U_0805_25V6K

1
2

EMI@ PC503
2200P_0402_50V7K

2

1

1.5V_B+
@EMI@ PC502
0.1U_0402_25V6

B+

Pin19 need pull separate from +1.5VP.
If you have +1.5V and +0.75V sequence question,
you can change from +1.5VP to +1.5VS.

EMI@ PL501
HCB2012KF-121T50_0805
2
1

3

2

Title

A

Compal Electronics, Inc.
+1.5VP/+0.75VSP

Size
Document Number
Custom
Date:

Thursday, March 27, 2014

Rev
1.0
Sheet
1

36

of

45

5

4

3

2

1

Module model information
SY8033_V1.mdd
D

D

22u Capacitor change to 0603 size.
2013/10/16 modify.
FB=0.6V
Note:Iload(max)=3.5A

2013/10/22 Modify
PL601 change to common part.

1
2

1
2

PC604
22U_0603_6.3V6M

1

Rdown

PC603
22U_0603_6.3V6M

FB_1.8V

PC602
68P_0402_50V8J
2
1

PR604
20K_0402_1%

Rup

22u Capacitor change to 0603 size.
2013/10/16 modify.

PR606
10K_0402_1%
2

1
2

@EMI@ PC606
680P_0402_50V7K

SY8033BDBC_DFN10_3X3

Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage

B

1

1

6

+1.8VALWP

2

4
PG

FB

EN

11
1
2

PC605
0.1U_0402_16V7K

<22,38> 0.95_1.8VALW_PWREN

3

SVIN

TP

@ PR601
0_0402_1%
2 +1.8VSP_ON
1

LX

2

5

LX

C

PL601
1UH_2.8A_30%_4X4X2_F
2
1

@EMI@ PR603
4.7_0603_5%

8

PVIN
PVIN

LX_1.8V

2

NC

9

NC

2

JUMP_43X79

10
PC601
2
1

1

PU601
2
22U_0603_6.3V6M

1

1

@ PJ601

+3VALW

7

C

Vout=0.6V* (1+Rup/Rdown)
B

@ PJ602

Delete PR605,because same net name have two PD resister in circuit.
2013/11/29 modify.

+1.8VALWP

1

1

2

2

+1.8VALW

JUMP_43X79

A

A

2014/03/27

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2016/03/27

Title

+1.8VALWP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
1.0

Thursday, March 27, 2014

Sheet
1

37

of

45

5

4

3

2

1

D

D

Module model information
SY8208D_V1.mdd

EN pin don't floating
If have pull down resistor at HW side, pls delete PR2

1

@ PR702
0_0402_5%
2

for this project
Ipeak=8A
Add 22u*2 capacitor,
Chock change to 0.68u.
meet DC-DC design check form.
2013/10/02 Modify.

0.95_1.8VALW_PWREN <22,37>

1

1

C

@ PC702
0.22U_0402_10V6K

2

2

1M_0402_1%
PR703

SY8208DQNC_QFN10_3X3

FB = 0.6V

1
2

PC715
22U_0603_6.3V6M

1
2

PC716
22U_0603_6.3V6M

1
2

PC712
22U_0603_6.3V6M

1
2

1

PC711
22U_0603_6.3V6M

22u Capacitor change to 0603 size.
2013/10/16 modify.

PR709

Rdown

20K_0402_1%
2

2

2

@ PR708
0_0402_5%

+3VALW

2

LDO_3V

2

Rup

7
5

+0.95VALWP

1

LDO

1

PG

2

BYP

PC714
4.7U_0603_6.3V6K

ILMT

1

2

4

PC713
4.7U_0603_6.3V6K

FB

ILMT_0.95V3

ILMT_0.95V

TDC 8A

PL702
0.68UH_PCMC063T-R68MN_15.5A_20%
2
1

LX_0.95V

PC710
47U_0805_6.3V6M

10

PC706
0.1U_0603_25V7K
2
1

1

LX

PR705
0_0603_5%
2

2

GND

1
BST_0.95V

1

9

1
6

PC709
47U_0805_6.3V6M

BS

1

EN

2

IN

PC708
330P_0402_50V7K

8

PR707
11.8K_0402_1%

10U_0805_25V6K
PC705
2
1

10U_0805_25V6K
PC707
2
1

B+_0.95V

1

2

@ PR706
0_0402_5%

PU701

@EMI@ PC704
0.1U_0402_25V6
2
1

1

LDO_3V

@EMI@ PR704
@EMI@ PC703
4.7_1206_5%
680P_0603_50V7K
2SNB_0.95V 1
1
2

EMI@ PL701
HCB2012KF-121T50_0805
2
1
EMI@ PC701
2200P_0402_50V7K
2
1

B+

C

B

Pin 7 BYP is for CS.
Common NB can delete

The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high

@ PJ701
1

+0.95VALWP

+3VALW and PC714

1

2

2

+0.95VALW

B

JUMP_43X118

VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=0.954V

A

A

Compal Secret Data

Security Classification
Issued Date

2014/03/27

Deciphered Date

2016/03/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

+0.95VALWP
Size
C
Date:

5

4

3

2

Compal Electronics, Inc.
Document Number

Rev
1.0

Thursday, March 27, 2014

Sheet
1

38

of

45

5

4

CPU_B+

RT8880A_V1A.mdd for IC portion

EMI@ PL801
HCB2012KF-121T50_0805
2
1

2

+APU_CORE

110K_0402_1%
4

LGATE_NB1

45

LGATE_NB1

44

PHASE_NB1

43

UGATE_NB1

42

BOOT_NB1

PC801
10U_0805_25V6K
2
1

PHASE1
PR823
2.2_0603_1%
2
BOOT11
VGATE <22>

PR826
100K_0402_5%

PC820
0.22U_0603_25V7K

+3VS
4

LGATE1

VR_ON <22>

1
2

PC826
2
1

4

PC831
0.1U_0402_25V4K

560P_0402_50V7K
PR832

330P_0402_50V7K

2

1
2

SET1

2

10_0402_5%

APU_core
TDC 20A
Peak Current 25A
OCP current > 35A
Load line -4mV/A
FSW=450kHz
DCR 1.4mohm +/-5%
TYP
H/S Rds(on) :6.7mohm ,
L/S Rds(on) :3mohm ,

0.1U_0402_25V6

ISEN1N

B

@ PR831
4.12K_0402_1%
2
1

1

PR838
910_0402_1%
2

MAX
8.5mohm
3.8mohm

+5VS

SET2

PR848
124K_0402_1%
2
1

PC830
0.01U_0402_50V7K

<6>

PR847
1K_0402_1%
2
1

1

+APU_CORE_NB

APU_VDD_RUN_FB_L

@ PC829
680P_0402_50V7K

APU_VDDNB_SEN

PR846
470_0402_1%
2
1

2

1

0.1U_0402_25V6

2

1

2

@ PR837
2K_0402_1%

PC827

+APU_CORE

PC821
.1U_0402_16V7K

SNB_APU

@ PC828
2
1

@

10K_0402_1%

PR842

PR845
124K_0402_1%
2
1

3

ISEN1P

1

PR844
1K_0402_1%
2
1

2
PR829
2.61K_0402_1%
2
1

2

1

97.6K_0402_1%

PR843
20.5K_0402_1%
2
1

PL803
0.36UH_PDME064T-R36MS_24A_20%
4
1

PR833
2

1

1

+
2

ISEN1N-1

68P_0402_50V8J
2

2

3
2
1

2

1

1
BOOT1-1

4

EMI@ PC819
2200P_0402_50V7K
2
1

PR820 0_0603_5%
2
1

UGATE1

1

@EMI@ PC818
0.1U_0402_25V6
2
1

PGOOD

CPU_B+

PC815

2

110K_0402_1%

+5VS

PC811
2
1

PR819
1

68U_25V_M

+5VS

PC816
10U_0805_25V6K
2
1

41
40

MAX
8.5mohm
3.8mohm

CPU_B+

@EMI@ PR828
4.7_1206_5%

BOOT1

2

PR814
10_0603_5%

PQ803
AON6552_DFN5X6-8-5

UGATE1

46

1

PQ805
AON6554_DFN5X6-8-5
1 2
1

47

VCC

PC814

PHASE1

39

38

37

EN

ISENA1P
36

35

ISENA1N

100K_0402_1%
PR827
2

TONSETA

ISENA1P

ISENA2N
34

ISENA2P
33

28

27

VCC

VSENA

VCC

OCP_L

SET2

LGATE1

48

C

5

PWMA2

PGOODA

BOOTA1

ISENA1N

OFSA
SET1

PVCC

49

@

APU_CORE_NB
TDC 13A
Peak Current 17 A
OCP current > 33A
Load line -4mV/A
FSW=450kHz
DCR 1.4mohm +/-5%
TYP
H/S Rds(on) :6.7mohm ,
L/S Rds(on) :3mohm ,

3
2
1

UGATEA1

50

PVCC

5

OFS

PR812
910_0402_1%
2

3
2
1

PHASEA1

51

PQ804
AON6554_DFN5X6-8-5

LGATEA1

SVT

1

5

SVD

PC825
1

@ PR811
0_0402_5%
2

1

+5VS
@ PR813
0_0402_1%
2
1

PC813
2.2U_0603_10V7K
2
1

BOOT1

Pull high at HW side

SNB_APU_NB

53

2.2U_0603_10V7K
2
1

1

2
BOOT2

UGATE2

3
PWM3

5

4

ISEN2P

TONSET

UGATE1

<22,6,7> PROCHOT#

2

1

PC808
.1U_0402_16V7K

ISENA1N

52

+APU_CORE_NB

3

PC817
10U_0805_25V6K
2
1

TONSET

ISEN1N
6
ISEN2N

ISEN1P

7
ISEN1N

9

8

ISEN3P

ISEN1P

ISEN3N

10

11
VSEN

PWROK
SVC

FBA

25
26

PHASE1

COMPA

SET1
SET2

VDDIO

32

23
24

LGATE1

IMONA

31

OFS
OFSA
1

0_0402_5%

@ PR818
2

1

@ PR817
2
1
2

PC823
0.1U_0402_25V6

PH802
100K_0402_1%_B25/50 4250K

1
2

1
2

PC822
0.1U_0402_25V6

19.6K_0402_1%

PR825
16.9K_0402_1%

0_0402_5%

16K_0402_1%
PR816
1
2

24.9K_0402_1%
PR815
2
1

2

1

2

PR824

1

1
2

22

<6> APU_SVT

PVCC

V064

FBA

21

<6> APU_SVD

LGATE2

IBIAS

20

<6> APU_SVC

PH801
100K_0402_1%_B25/50 4250K

17

19

<6> APU_PWRGD

VREF

16

18

GND

IMON

30

VREF
IMONA
PC812
1U_0402_6.3V6K +1.5VS
2
1
VDDIO

15

2

PR810
2.61K_0402_1%
2
1

ISENA1P
PU801
RT8880BGQW_WQFN52_6X6

PHASE2

29

IMON

+5VS

RGND

1 IBIAS
COMPA

14

C

PR822
7.68K_0402_1%
2
1

FB

COMP

2013/10/22 Modify
PH801,PH802 change to common part.

12

13

FB

COMP

3
2
1

+5VS

PR821
4.99K_0402_1%
2
1

D

ISENA1N-1

PC807
68P_0402_50V8J
2
1

PC804
10U_0805_25V6K
2
1

PQ801
AON6552_DFN5X6-8-5

PHASE_NB1

4.7_1206_5%

0.22U_0603_25V7K

CPU_B+

2

PL802
0.36UH_PDME064T-R36MS_24A_20%
4
1

680P_0603_50V7K

PR808
1

PC806
2
1
BOOT_NB1-1

@EMI@ PC810 @EMI@ PR809
2
1
2
1

PR807
64.9K_0402_1%
2
1

PC809
560P_0402_50V7K
2
1

B+

5

PR801 0_0603_5%
4
2
1

PR805
2.2_0603_1%
2
1
BOOT_NB1

PQ802
AON6554_DFN5X6-8-5

PR806
10K_0402_1%
2
1

UGATE_NB1

3
2
1

2

5

1

2K_0402_1%
@ PR804
2
1

2

1

@ PC803
680P_0402_50V7K

PR803

PR802

RT8880A_V1B.mdd for SW portion

@EMI@ PC824
680P_0603_50V7K

1

Module model information
PC802
0.01U_0402_50V7K

10_0402_5%
2
1

@ PC805
330P_0402_50V7K

B

1

2013/10/16 Modify
PQ801,PQ803 change to AON6552.
PQ802,PQ804,PQ805 change to AON6554.

APU_VDD_SEN <6>

10_0402_5%
2
1
D

2

2

<6> APU_VDD_RUN_FB_L

3

A

A

Delete PR834.PR835.PR836.PR839.PR840.PR841,
follow vender FAE suggest.
2013/11/29 modify.

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

APU_CORE/APU_CORE_NB
Size
Document Number
Custom
Date:

5

4

3

2

Rev
1.0

Thursday, March 27, 2014

Sheet
1

39

of

45

5

4

3

2

+APU_CORE (36.4)

1

+APU_CORE_NB (36.5)

+APU_CORE

PC907
10U_0805_6.3V6M
2
1

1U_0402_6.3V6K
PC915
2
1

1U_0402_6.3V6K
PC917

PC904
10U_0805_6.3V6M
2
1
1U_0402_6.3V6K
PC914
2
1

1U_0402_6.3V6K
PC916
2
1

PC903
10U_0805_6.3V6M
2
1

PC902
10U_0805_6.3V6M
2
1

2

1U_0402_6.3V6K
@ PC928

1U_0402_6.3V6K
PC927
2
1

1U_0402_6.3V6K
PC926
2
1

1U_0402_6.3V6K
PC925
2
1

1U_0402_6.3V6K
PC924
2
1

2

1

1U_0402_6.3V6K
PC923

1U_0402_6.3V6K
PC922
2
1

1

1U_0402_6.3V6K
PC912

1U_0402_6.3V6K
PC911
2
1
1U_0402_6.3V6K
PC921
2
1

PC906

10U_0805_6.3V6M
2
1
1U_0402_6.3V6K
PC910
2
1

1U_0402_6.3V6K
PC920
2
1

PC905
10U_0805_6.3V6M
2
1

1U_0402_6.3V6K
PC909
2
1

1U_0402_6.3V6K
PC919
2
1

1U_0402_6.3V6K
PC908
2
1
1U_0402_6.3V6K
PC918
2
1

+

2

2

1
+

2

PC935
560U_D2_2VM_R4.5M

1

+

@ PC934
330U_D2_2V_Y

1

PC933
330U_D2_2V_Y

PC932
560U_D2_2VM_R4.5M

B

+APU_CORE_NB

+APU_CORE

1

1

+

+

2

2

@ PC936
330U_D2_2V_Y

B

PC931
180P_0402_50V8J
2
1

@

D

C

PC930
180P_0402_50V8J
2
1

PC901
10U_0805_6.3V6M
2
1

1
2
PC929
0.22U_0402_16V7K
2
1

2

1

C

1U_0402_6.3V6K
PC913
2
1

+APU_CORE_NB

D

A

A

2014/03/27

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2016/03/27

Title

APU_CORE/APU_CORE capacitor

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
1.0

Thursday, March 27, 2014

Sheet
1

40

of

45

5

4

3

2

1

Module model information
TPS51212_V1.mdd for Single layer
TPS51212_V2.mdd for Dual layer
D

9

UG_+1.5VSDGPUP

8

SW _+1.5VSDGPUP

VGA@
PR1006
470K_0402_1%

6

LG_+1.5VSDGPUP

11

TPS51212DSCR_SON10_3X3

VGA@
PC1007
1U_0603_6.3V6M

4

3
2
1

2

@

TP

+5VALW

VGA@ PC1004
10U_0805_25V6K
2
1

VGA_EMI@ PC1003
2200P_0402_50V7K
2
1

PC1005
10U_0805_25V6K
2
1

+1.5VSDGPUP

@EMI@
PR1005
4.7_1206_5%

C

VGA@ PC1009
330U_2.5V_ESR17M_6.3X4.5

DRVL

7

1

TST

VRAM

2

SW

V5IN

1

EN
VFB

2013/10/22 Modify
PL1002,PC1009 change to common part.

VGA@ PL1002
2.2UH_7.8A_20%_7X7X3_M
2
1

1

DRVH

@

PC1010 @EMI@
680P_0402_50V7K

2

PC1006
0.1U_0402_16V7K
2
1

RF_+1.5VSDGPUP 5

VBST

TRIP

VGA@ PQ1002
AON7506_DFN33-8-5

3

PGOOD

5

EN_+1.5VSDGPUP

FB_+1.5VSDGPUP 4
C

VGA@ PR1001 VGA@ PC1001
2.2_0603_5%
0.1U_0603_25V7K
2
1
2
1
BST_+1.5VSDGPUP

2

@ PR1004
0_0402_5%
2
1

<16,42,7> VGA_PW RGD

10

VGA@
PU1001

1
VGA@ PR1003
66.5K_0402_1%
2TRIP_+1.5VSDGPUP2
1

1

2013/10/18 Modify
PR1004 change to 0 ohm.

B+

3
2
1

4

@EMI@ PC1002
0.1U_0402_25V6
2
1

VGA@ PQ1001
AON7408L_DFN8-5

5

2013/10/16 Modify
PQ1001 change to AON7408L.
PQ1002 change to AON7506.

D

VGA_EMI@ PL1001
HCB2012KF-121T50_0805
2
1

+1.5VSDGPUP_B+

1
+

ESR=17m ohm
2

1

VGA@ PR1007
11.5K_0402_1%
2
1

2

VGA@
PR1008
10K_0402_1%

B

MOSFET: 3x3 DFN
H/S Rds(on): 27mohm(Typ), 34mohm(Max)
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C

B

@ PJ1001

1

+1.5VSDGPUP

1

2

2

+1.5VSDGPU

JUMP_43X118
@ PJ1002
2
1
2
1

L/S Rds(on): 13mohm(Typ), 15.8mohm(Max)
Idsm: 12A@Ta=25C, 10.5A@Ta=70C

JUMP_43X118

Choke: 7x7x3
Rdc=15.5mohm +/-15%

Vout

PR1007 PR1008 PR1003

+1.2V

7.15K

10k

105K

+1.05V

4.99k

10k

93.1k

+1.5V

11.5K

10k

105K

A

+1.5V(for this project)
Switching Frequency: 290kHz
Ipeak=4.7A
OCP:6.884A~5.751A
OVP: 120%~130%
VFB=0.704V, Vout=1.514V
PR1003=66.5K Ohm

A

Compal Secret Data

Security Classification
2014/03/27

Issued Date

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Compal Electronics, Inc.
1.5VSDGPUP

Size
Date:

Document Number
Thursday, March 27, 2014

Rev
1.0
Sheet
1

41

of

45

B

0

0

0

1.100V

0

0

0

1

1.075V

1

0

0

1

0

1.050V

1

0

0

1

1

1.025V

0

1.000V

0

1

0.975V

1

0

1

1

0

0.950V

1

0

1

1

1

1

0

0

0

1

1

0

0

1

0.875V

1

1

0

1

0

0.850V

1

1

0

1

1

0.825V

1

1

1

0

0

0.800V

1

1

1

0

1

0.775V

25A (TDC)

21A (TDC)

EDC

48A

37.5A

31.5A

26A

OCP

57.6A

45A

37.8A

Vboot

0.85V

0.85V

Load line

1mohm

19A (TDC)

25A (TDC)

NA

24A

28.5A

37.5A

NA

31.2A

28.8A

34.2A

45A

NA

0.85V

0.85V

0.9V

0.9V

0.9V

NA

1mohm

1mohm

---------

---------

---------

1mohm

NA

750 Ohm

---------

---------

---------

887 Ohm

Rdroop
PR1229

1.43K Ohm

1.13K Ohm

953 Ohm

---------

---------

---------

1.13K Ohm

for LoadLine
Setting

PR1233

187K Ohm

147K Ohm

124K Ohm

---------

---------

---------

147K Ohm

for Compensation

PR1236

51.1K Ohm

51.1K Ohm

51.1K Ohm

---------

---------

---------

51.1K Ohm

for Positive offset

2

3

ISEN1_VGA

VSUM+_VGA ISEN2_VGA

+VGA_B+

1
2

VGA@ PL1203
0.22UH_PCME064T-R22MS_28A_20%

2

Transient response :
Rntcnet=(Rntcs+Rntc)*Rp/(Rntcs+Rntc+Rp)
Cn=L*(Rntcnet+Rsum/N)/[Rntcnet*DCR*(Rsum/N)]
N is the number of phases

Rntc

Rdroop=Io*LL/Idroop

VSUM+_VGA

3

+VGA_CORE

2 PR1242 1
1_0402_1%

4

VGA@

1
2

VGA@ PR1239
3.65K_0402_1%
2
1

@EMI@
PR1238
4.7_1206_5%
2
1
SNUB1_VGA

3
2
1

@EMI@
PC1229
680P_0603_50V7K
2
1

2

VGA@ PR1244
2.61K_0402_1%

Rntcs

1NTC_VGA

2
1
VGA@ PR1245
11K_0402_1%

Rp

4

LGATE1_VGA

1
2

VGA@ PR1241
10K_0402_1%
2
1

4

2
1
2 BOOT1_1_VGA
PR1235
2.2_0603_5%
VGA@ PC1220
0.22U_0603_25V7K

1
VGA@

VGA@ PC1218
10U_0805_25V6K
2
1

5
VGA@ PR1232
0_0603_5%
2
1

TDC 28A
Peak Current = 42A
OCP Current = 48.6A
Load line=mohm

PHASE1_VGA

VGA@ PR1248
976_0402_1%
2
1

ISEN2_VGA

ISEN1_VGA

VSUM-_VGA
4

2013/10/22 Modify
PH1201,PH1202 change to common part.

VSUM-_VGA

2

1

Ri
VGA@ PC1234
.1U_0402_16V7K

Layout Note:
PH1202 should place near
Phase1 Choke

Compal Secret Data

Security Classification

Issued Date

2014/03/27

Deciphered Date

2016/03/27

Title

Date:

B

VSUM-_VGA

2013/11/29 Modify
PL1202.PL1203 change to common part.

+5VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

+VGA_CORE

Ro

VGA@ PR1240
10K_0402_1%

+5VS

VGA@ PC1232
0.033U_0402_16V7K
2
1

VGA@ PC1231
0.15U_0603_16V7K
2
1

2

4

VGA@

UGATE1_VGA

VGA@ PH1202
10K_0402_1%_B25/50 3370K

VGA@ PR1247
10_0402_1%

1
2

2

Rsum

VGA@ PC1217
10U_0805_25V6K

+5VS

PR1230 Pop:
for Loadline disable
PR1230 @:
for Loadline enable
and LL=1mohm

2

1
1

2013/10/25 Modify
PR1229 change to 1.24K ohm.
PR1248 change to 976 ohm.

@EMI@ PC1210
@EMI@ PR1219
680P_0603_50V7K
4.7_1206_5%
2
1
2
1
SNUB2_VGA

5
3
2
1
1
2

1
2
+VGA_B+

1

0_0402_5%

VGA@ PL1202
0.22UH_PCME064T-R22MS_28A_20%

PHASE2_VGA

4

B+

Module model information:
ISL62883C_V1A for IC
ISL62883C_V1B for SW Choke/MOS on BTN
ISL62883C_V2B for SW Choke on BTN, MOS on TOP

5

VGA@ PC1223
1U_0603_10V6K
2
1

1
2

2
@ PR1230
10K_0402_1%

@ PR12310_0402_5%
2
1

2

<15> VSS_GPU_SENSE

VGA@ PC1233
1000P_0402_50V7K

1

4

2

3

Cn
VGA@ PC1228
1000P_0402_50V7K

@ PR1246
2
1

@EMI@ PC1202
0.1U_0402_25V6
2
1

5

VGA@ PR1213
GPU_VID0 2

<13>

4

VGA@ PC1206
0.22U_0603_25V7K
2
1

GPU_VID0

GPU_VID1
<13>

GPU_VID2
<13>

GPU_VID3
<13>

VGA@ PR1217
2.2_0603_5%
2
1
BOOT2_2_VGA
BOOT2_VGA

VGA@ PQ1201
AON6552_DFN5X6-8-5

10K_0402_1%
1

10K_0402_1%
1

VGA@ PR1212
GPU_VID1 2

VGA@
PR1216
0_0603_5%
2
UGATE2_VGA 1

VSUM+_VGA

@ PR1243
2

0_0402_5%

PL1201

FBMA-L11-453215800LMA90T_2P

ISL62883CHRTZ-T_TQFN40_5X5
VGA@

1

@ PC1230
330P_0402_50V7K
2
1

1

VGA_EMI@

3
2
1

10K_0402_1%
1
VGA@ PR1211
GPU_VID2 2

@

VGA@ PR1237
10_0402_1%

<15> VCC_GPU_SENSE

Choke: 0.22uH (Size:7*7*4)
Rdc=0.98mohm +-5%
Heat Rating Current=28A
Saturation Current=28A

1

2

1

for OCP and
LoadLine Setting

+VGA_B+

VSUM-_VGA

+VGA_CORE

TYP
MAX
H/S Rds(on) :6.7mohm , 8.5mohm
L/S Rds(on) :3mohm , 3.8mohm

887 Ohm

10K_0402_1%
1

@

MOS

1.13K Ohm

VGA@ PQ1203
AON6552_DFN5X6-8-5

11
12
13
14
15
16
17
18
19
20
1
2

1

16A (TDC)

VGA@

VGA@ PR1234
1_0402_5%

2

NA

17A (TDC)

Ri
PR1248

10K_0402_1%
1

10K_0402_1%
1
PR1208
GPU_VID5 2

10K_0402_1%
1

10K_0402_1%
1
PR1207
GPU_VID0 2

10K_0402_1%
1

32A (TDC)

Remark: MARS LP/ SUN UL/ SUN PRO
don't use this 2-phase solution

1
VIN_VGA

VGA@ PC1221
0.22U_0402_16V7K

1
2

0.800~1.150V

BOOT1_VGA

VSEN_VGA

ISEN2_VGA

VGA@ PR1236
51.1K_0402_1%

0.800~1.075V

3
2
1

AGND

Rdroop
ISEN1_VGA

0.775~1.125V

VGA@ PQ1204
AON6554_DFN5X6-8-5

41

VGA@ PR1229
1.24K_0402_1%
2
1

for positive offset

TDC

30
29
28
27
26
25
24
23
22
21

BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1

PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2

VGA@
VGA@ PC1215
PR1228
390P_0402_50V7K
499_0402_1%
2
1
2FB1_VGA
1

VGA@ PC1219
VGA@ PR1233
150P_0402_50V8J
147K_0402_1%
2FB2_VGA1
1
2

NA

0.775~1.000V

PC1213
1U_0603_10V6K

VGA@ PC1214
1000P_0402_50V7K
2
1

VGA@ PR1227
5.9K_0402_1%
2
1

VGA@ PC1211
22P_0402_50V8J

VGA@ PC1216
33P_0402_50V8J
2
1

0.775~1.050V

PC1212
1U_0603_10V6K

COMP_VGA
FB_VGA
2ISEN3_VGA

1

Rfset

3

VW_VGA

1
2
3
4
5
6
7
8
9
10

VGA@ PC1224
0.22U_0603_25V7K

VGA@ PH1201

@

VDD_VGA

470K_0402_5%_B25/50 4700K
2
1

SUN XT

PU1201

Rth

VGA@ PR1226

SUN PRO

40
39
38
37
36
35
34
33
32
31

VGA@ PR1225
100K_0402_5%
2
1

6.98K_0402_1%
2
1

0.775~1.125V

Description

SUN UL

LGATE2_VGA

RTN_VGA
ISUM-_VGA

+3VSDGPU

VGA@ PR1220
147K_0402_1%
2
1

CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0

Layout Note:
PH1201 should place near
phase1 H-side MOS

@

VRON_VGA
GPU_VID6

2
1
VGA@ PR1218
100K_0402_5%

+3VSDGPU

Rbias

0.775~1.175V

AMD SUN series

Vboot regulation

GPU_VID4
<13>

GPU_VID5

<16,41,7> VGA_PWRGD

5. Switching frequency set :
Rfset(kohm)=[period(us)-0.29]*2.65
=5.9Kohm
fsw=1/period(us)=400KHZ

VDDC

ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1

Recovery T
96C +-3

1.91K_0402_1%

PSI#_VGA

Recovery T
105C +-3

@

MARS LP

VGA@ PR1215
2
1

+3VSDGPU

VGA@ PC1222
0.22U_0402_16V7K

protect T
100C +-3

RBIAS_VGA

protect T
110C +-3

10K_0402_1%
1

PR1226=1.5K

10K_0402_1%
1

DPRSLPVR_VGA-1

10K_0402_1%

PR1226=6.98K

VGA@ PR1202
GPU_VID5 2

VGA@ PR1214
2
1

VGA@ PR1203
GPU_VID4 2

@ PR1249
0_0402_5%
2
1

VGA@ PC1201
33P_0402_50V8J
2
1

4. Thermal throttling:
Protect: (6.98K+Rth)*60uA=1.2V
=> Rth=13.02K
=>Tp=110C (+-3C) <13> GPU_DPRSLPVR
Recovery:(6.98K+Rth)*56uA=1.24V
=> Rth=15.16K
=> Tr=105C (+-3C)

+3VSDGPU

@ PR1250
1M_0402_1%
2
1

<16> VGA_ON_B

2

2013/11/29 Modify
Delay Time follow HW request.
Add PD Resister(PR1250)
2013/12/16 Modify
Delay Time follow HW request.

@ PR1201
0_0402_5%
2
1

3. Rbias=147K =>overshoot reduction function disable
Rbias=47k =>overshoot reduction function enable

MARS PRO

VGA@ PQ1202
AON6554_DFN5X6-8-5

2013/10/18 Modify
EN Signal change to VGA_ON.
Delay Time follow HW request.

Vboot(merge)

0.900V

1

MARS XT

1

0.925V

PR1206
GPU_VID1 2

2. When 2 Phase GPU config
a. DPSLPVR (Pin39)=0 PSI# (Pin2)=0
=>1 phase CCM operation mode
b. DPSLPVR (Pin39)=0 PSI# (Pin2)=1
=>2 phase CCM operation mode
c. DPSLPVR (Pin39)=1 PSI# (Pin2)=0 or 1
=>1 phase DE operation mode

0

1

10K_0402_1%
1

1. PWM3 (Pin24) tie to 5V & CLK# (Pin40) external pull high
=> 2 phase CPU VR config
PWM3 (Pin24) tie to 5V & CLK# (Pin40) tie to GND or floating
=> 2 phase GPU VR config

1

0

@ PR1205
GPU_VID2 2

"Jet Type"

0

1

PR1204
GPU_VID3 2

1

1

MARS XTX

2
1
VGA@ PR1224
1_0402_1%

0

1

GPU

2
1
VGA@ PR1223
10K_0402_1%

1

AMD MARS series
VDDC
1.125V

VGA@ PR1222
10K_0402_1%

1

1

VID1

1

2

VID2

1

PC1205
VGA@ 10U_0805_25V6K
2
1

VID3

1

1

VID4

0

E

UL: DDR3
Pro/XT/XTX: GDDR5

2

VID5

D

LP: DDR3
Pro/XT/XTX: GDDR5

PC1204
VGA@ 10U_0805_25V6K

GPIO15

VGA@ PR1221
3.65K_0402_1%
2
1

GPIO20

VGA_EMI@ PC1203
2200P_0402_50V7K
2
1

GPIO30

2013/10/16 Modify
PQ1201,PQ1203 change to AON6552.
PQ1202,PQ1204 change to AON6554.

Remark:

C

GPIO29

VGA@ PR1210
GPU_VID3 2

GPIO21

PR1209
GPU_VID4 2

A

C

D

Compal Electronics, Inc.
ISL62883C
Document Number

Rev
1.0
Sheet

Thursday, March 27, 2014
E

42

of

45

5

VGA@ PC1331
2.2U_0402_6.3V6M
2
1
VGA@ PC1332
10U_0402_6.3V6M
2
1

VGA@ PC1342
22U_0603_6.3V6M
2
1

VGA@ PC1343
22U_0603_6.3V6M

4

VGA@ PC1314
10U_0402_6.3V6M
2
1

VGA@ PC1324
2.2U_0402_6.3V6M
VGA@ PC1325
560U_2.5V_M

2

VGA@ PC1326
560U_2.5V_M

+

Issued Date

+

2@

PC1327
330U_D2_2.5VY_R9M

1

VGA@ PC1338
10U_0402_6.3V6M

VGA@ PC1306
2.2U_0402_6.3V6M
2
1

VGA@ PC1313
2.2U_0402_6.3V6M
2
1

VGA@ PC1323
10U_0402_6.3V6M
2
1

VGA@ PC1318
10U_0402_6.3V6M

VGA@ PC1317
2.2U_0402_6.3V6M
2
1

VGA@ PC1316
2.2U_0402_6.3V6M
2
1

VGA@ PC1315
2.2U_0402_6.3V6M
2
1

VGA@ PC1305
10U_0402_6.3V6M
2
1

VGA@ PC1312
10U_0402_6.3V6M
2
1

VGA@ PC1322
10U_0402_6.3V6M
2
1

VGA@ PC1308
2.2U_0402_6.3V6M

VGA@ PC1307
10U_0402_6.3V6M
2
1

VGA@ PC1304
2.2U_0402_6.3V6M
2
1

VGA@ PC1303
10U_0402_6.3V6M
2
1

VGA@ PC1311
10U_0402_6.3V6M
2
1

VGA@ PC1321
2.2U_0402_6.3V6M
2
1

2

1

VGA@ PC1337
10U_0402_6.3V6M
2
1

1

VGA@ PC1302
10U_0402_6.3V6M
2
1

+

VGA@ PC1336
10U_0402_6.3V6M
2
1

2

VGA@ PC1301
2.2U_0402_6.3V6M
2
1

VGA@ PC1310
2.2U_0402_6.3V6M
2
1

1

VGA@ PC1320
2.2U_0402_6.3V6M
2
1

2
VGA@ PC1309
10U_0402_6.3V6M
2
1

1

VGA@ PC1319
2.2U_0402_6.3V6M
2
1

1

VGA@ PC1335
2.2U_0402_6.3V6M
2
1

VGA@ PC1334
10U_0402_6.3V6M
2
1

C

2

D

VGA@ PC1333
10U_0402_6.3V6M
2
1

VGA@ PC1330
2.2U_0402_6.3V6M
2
1

VGA@ PC1341
22U_0603_6.3V6M
2
1

1

VGA@ PC1329
10U_0402_6.3V6M
2
1

2

VGA@ PC1340
22U_0603_6.3V6M
2
1

1
VGA@ PC1328
10U_0402_6.3V6M
2
1

2

B

VGA@ PC1339
22U_0603_6.3V6M
2
1

5
4
3

+VGA_CORE

+VGA_CORE

Security Classification

2014/03/27

3

2

Deciphered Date
2016/03/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

1

AMD MARS
GPU_CORE
560uF*2+330uF*1
10uF*8+2.2uF*16
D

C

AMD MARS
meet ripple
22uF*5+10uF*11

B

A
A

Compal Secret Data

Title

Compal Electronics, Inc.

Size Document Number
Custom

VGA_CORE CAP

Date:
Thursday, March 27, 2014

Rev
1.0

Sheet
1

43

of
45

5

4

3

2

Version change list (P.I.R. List)
Item
D

C

Fixed Issue

1

Page 1of 2
for PWR
Reason for change

Design Change of Diode Application.

Rev.

PG#

0.2

32

Modify List

Date

Change PD101 to SCSS4004010(S SCH DIO BAS40-04 SOT23).

Phase

1

Design Change.

2013/11/29

DVT

2

Design Change.

Design Change of IC Application.

0.2

35

Add non-pop component PC427,PC428.

2013/11/29

DVT

3

Design Change.

reduce part count.

0.2

37

Delete PR605 PD resister.

2013/11/29

DVT

4

Design Change.

reduce part count.

0.2

39

Delete @PR834.@PR835.@PR836.@PR839.@PR840.@PR841.

2013/11/29

DVT

5

Design Change.

Design Change of VGA Type Application.

0.2

42

PR1205 change to non-pop.
PR1211 change to pop.

2013/11/29

DVT

6

Design Change.

Design Change of common part.

0.2

34

Change PL301 to SH00000YG00
(S COIL 1UH +-30% 2.8A 4X4X2 FERRITE).

2013/11/29

DVT

7

Design Change.

Design Change of common part.

0.2

42

Change PL1202.PL1203 to SH000011H00
(S COIL .22UH +-20% 24A 7X7X4 MOLDING).

2013/11/29

DVT

8

Design Change.

Design Change of Delay Time.

0.2

42

Change PR1201 to SD028000080(S RES 1/16W 0 +-5% 0402).
Change PC1201 to non-pop.

2013/11/29

DVT

9

Design Change.

Design Change of EC Type Application.

0.2

35

Add PD401 SCS00000Z00(S SCH DIO RB751V-40 SOD-323).

2013/11/29

DVT

10

Design Change.

Design Change of Circuit Application.

0.2

42

Add PR1250 SD034100480(S RES 1/16W 1M +-1% 0402).

2013/11/29

DVT

11

Design Change.

Design Change of Delay Time.

0.2

42

Change PR1201 to SD028000080(S RES 1/16W 0 +-5% 0402).
Change PC1201 to SE071330J80(S CER CAP 33P 50V J NPO 0402)

2013/12/16

DVT

12

Design Change.

Design Change of Circuit Application.

0.2

33

Delete PR223.(remove HW hysteresis)

2013/12/16

DVT

13

Design Change.

Design Change of Circuit Application.

0.2

42

Change PR1250 to non-pop.

2013/12/16

DVT

14

Design Change.

Design Change of Circuit Application.

0.2

34

Change PQ303,PQ304 to SB000010A00(S TR AON7506 1N DFN).

2013/12/19

DVT

15

Design Change.

Design Change of Circuit Application.

0.2

33

Add PL202 SM01000C000
(S SUPPRE_ TAI-TECH HCB2012KF-121T50 0805)

2013/12/19

DVT

D

C

B

B

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

A

2016/03/27

Title

PWR_PIR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Thursday, March 27, 2014

Rev
1.0
Sheet
1

44

of

45

5

4

3

2

1

Version change list (P.I.R. List)
Item

Fixed Issue

Page 2 of 2 for PWR
Reason for change

Rev.

PG#

Modify List

Date

Phase

16

Design Change.

Design Change of Circuit Application.

0.2

33

Change PR211 to SD028000080(S RES 1/16W 0 +-5% 0402).

2013/12/25

DVT

17

Design Change.

Design Change of Circuit Application.

0.2

35

Change PC426 to pop.

2013/12/25

DVT

18

Design Change.

Design Change of Circuit Application.

0.2

33

Change PR216 to SD034162280(S RES 1/16W 16.2K +1% 0402).

2013/12/25

DVT

19

Design Change.

Design Change of Circuit Application.

0.2

33

Change PR216 to SD034169280(S RES 1/16W 16.9K +-1% 0402).

2014/01/02

DVT

20

Design Change.

Design Change of Circuit Application.

0.2

33

Change PR202 to SD034100280(S RES 1/16W 10K +-1% 0402).

2014/01/02

DVT

21

Design Change.

Design Change of Circuit Application.

0.3

Change PR813,PR601,PR706,PR702,PR1004
to SD028000080(S RES 1/16W 0 +-5% 0402).

2014/02/07

PVT

22

Design Change.

Design Change of Circuit Application.

0.3

Remove PD401.
Add @PR410 SD028000080(S RES 1/16W 0 +-5% 0402).

2014/02/07

PVT

D

D

C

37.38.
39.41.

C

35

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/27

Deciphered Date

2016/03/27

Title

PWR_PIR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Thursday, March 27, 2014

Rev
1.0
Sheet
1

45

of

45

www.s-manuals.com



---

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Creator                         : 
Title                           : Compal LA-B231P - Schematics. www.s-manuals.com.
Subject                         : Compal LA-B231P - Schematics. www.s-manuals.com.
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