Cortex M4 Technical Reference Manual
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- Cortex-M4 Technical Reference Manual
- Contents
- List of Tables
- List of Figures
- Preface
- Introduction
- Functional Description
- Programmers Model
- System Control
- Memory Protection Unit
- Nested Vectored Interrupt Controller
- Floating Point Unit
- 7.1 About the FPU
- 7.2 FPU Functional Description
- 7.3 FPU Programmers Model
- Debug
- Data Watchpoint and Trace Unit
- Instrumentation Trace Macrocell Unit
- Trace Port Interface Unit
- 11.1 About the Cortex-M4 TPIU
- 11.2 TPIU functional description
- 11.3 TPIU programmers model
- 11.3.1 Asynchronous Clock Prescaler Register, TPIU_ACPR
- 11.3.2 Formatter and Flush Status Register, TPIU_FFSR
- 11.3.3 Formatter and Flush Control Register, TPIU_FFCR
- 11.3.4 TRIGGER
- 11.3.5 Integration ETM Data
- 11.3.6 ITATBCTR2
- 11.3.7 Integration ITM Data
- 11.3.8 ITATBCTR0
- 11.3.9 Integration Mode Control, TPIU_ITCTRL
- 11.3.10 TPIU_DEVID
- Revisions
- Glossary