Embedded Peripherals IP User Guide Users
User Manual:
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- Embedded Peripherals IP User Guide
- Contents
- 1. Embedded Peripherals IP User Guide Introduction
- 2. SDRAM Controller Core
- 3. Tri-State SDRAM Core
- 4. Compact Flash Core
- 5. EPCS Serial Flash Controller Core
- 6. JTAG UART Core
- 7. UART Core
- 8. 16550 UART Core
- Core Overview
- Feature Description
- Software Programming Model
- Address Map and Register Descriptions
- Document Revision History
- 9. SPI Core
- 10. Optrex 16207 LCD Controller Core
- 11. PIO Core
- 12. Avalon-ST Serial Peripheral Interface Core
- 13. Avalon-ST Single-Clock and Dual-Clock FIFO Cores
- 14. MDIO Core
- 15. On-Chip FIFO Memory Core
- Core Overview
- Functional Description
- Configuration
- Software Programming Model
- Programming with the On-Chip FIFO Memory
- On-Chip FIFO Memory API
- altera_avalon_fifo_init()
- altera_avalon_fifo_read_status()
- altera_avalon_fifo_read_ienable()
- altera_avalon_fifo_read_almostfull()
- altera_avalon_fifo_read_almostempty()
- altera_avalon_fifo_read_event()
- altera_avalon_fifo_read_level()
- altera_avalon_fifo_clear_event()
- altera_avalon_fifo_write_ienable()
- altera_avalon_fifo_write_almostfull()
- altera_avalon_fifo_write_almostempty()
- altera_avalon_write_fifo()
- altera_avalon_write_other_info()
- altera_avalon_fifo_read_fifo()
- Document Revision History
- 16. Avalon-ST Multi-Channel Shared Memory FIFO Core
- 17. SPI Slave/JTAG to Avalon Master Bridge Cores
- 18. Avalon Streaming Channel Multiplexer and Demultiplexer Cores
- 19. Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores
- 20. Avalon Packets to Transactions Converter Core
- 21. Avalon-ST Round Robin Scheduler Core
- 22. Avalon-ST Delay Core
- 23. Avalon-ST Splitter Core
- 24. Scatter-Gather DMA Controller Core
- Core Overview
- Resource Usage and Performance
- Functional Description
- Parameters
- Simulation Considerations
- Software Programming Model
- Programming with SG-DMA Controller
- Data Structure
- SG-DMA API
- alt_avalon_sgdma_do_async_transfer()
- alt_avalon_sgdma_do_sync_transfer()
- alt_avalon_sgdma_construct_mem_to_mem_desc()
- alt_avalon_sgdma_construct_stream_to_mem_desc()
- alt_avalon_sgdma_construct_mem_to_stream_desc()
- alt_avalon_sgdma_enable_desc_poll()
- alt_avalon_sgdma_disable_desc_poll()
- alt_avalon_sgdma_check_descriptor_status()
- alt_avalon_sgdma_register_callback()
- alt_avalon_sgdma_start()
- alt_avalon_sgdma_stop()
- alt_avalon_sgdma_open()
- Document Revision History
- 25. Modular Scatter-Gather DMA Core
- Core Overview
- Feature Description
- mSGDMA Interfaces and Parameters
- mSGDMA Descriptors
- Programming Model
- Register Map of mSGDMA
- Modular Scatter-Gather DMA Prefetcher Core
- Driver Implementation
- alt_msgdma_standard_descriptor_async_transfer
- alt_msgdma_extended_descriptor_async_transfer
- alt_msgdma_descriptor_async_transfer
- alt_msgdma_standard_descriptor_sync_transfer
- alt_msgdma_extended_descriptor_sync_transfer
- alt_msgdma_descriptor_sync_transfer
- alt_msgdma_construct_standard_st_to_mm_descriptor
- alt_msgdma_construct_standard_mm_to_st_descriptor
- alt_msgdma_construct_standard_mm_to_mm_descriptor
- alt_msgdma_construct_standard_descriptor
- alt_msgdma_construct_extended_st_to_mm_descriptor
- alt_msgdma_construct_extended_mm_to_st_descriptor
- alt_msgdma_construct_extended_mm_to_mm_descriptor
- alt_msgdma_construct_extended_descriptor
- alt_msgdma_register_callback
- alt_msgdma_open
- alt_msgdma_write_standard_descriptor
- alt_msgdma_write_extended_descriptor
- alt_avalon_msgdma_init
- alt_msgdma_irq
- Document Revision History
- 26. DMA Controller Core
- 27. Video Sync Generator and Pixel Converter Cores
- 28. Interval Timer Core
- 29. Mutex Core
- 30. Vectored Interrupt Controller Core
- Core Overview
- Functional Description
- Register Maps
- Parameters
- Altera HAL Software Programming Model
- Software Files
- Macros
- Data Structure
- VIC API
- Run-time Initialization
- Board Support Package
- altera_vic_driver.enable_preemption
- altera_vic_driver.enable_preemption_into_new_register_set
- altera_vic_driver.enable_preemption_rs_<n>
- altera_vic_driver.linker_section
- altera_vic_driver.<name>.vec_size
- altera_vic_driver.<name>.irq<n>_rrs
- altera_vic_driver.<name>.irq<n>_ril
- altera_vic_driver.<name>.irq<n>_rnmi
- Default Settings for RRS and RIL
- VIC BSP Design Rules for Altera Hal Implementation
- RTOS Considerations
- Implementing the VIC in Qsys
- Example Designs
- Advanced Topics
- Document Revision History
- 31. System ID Core
- 32. Performance Counter Core
- 33. Avalon Streaming Test Pattern Generator and Checker Cores
- Core Overview
- Resource Utilization and Performance
- Test Pattern Generator
- Test Pattern Checker
- Hardware Simulation Considerations
- Software Programming Model
- Test Pattern Generator API
- data_source_reset()
- data_source_init()
- data_source_get_id()
- data_source_get_supports_packets()
- data_source_get_num_channels()
- data_source_get_symbols_per_cycle()
- data_source_set_enable()
- data_source_get_enable()
- data_source_set_throttle()
- data_source_get_throttle()
- data_source_is_busy()
- data_source_fill_level()
- data_source_send_data()
- Test Pattern Checker API
- data_sink_reset()
- data_sink_init()
- data_sink_get_id()
- data_sink_get_supports_packets()
- data_sink_get_num_channels()
- data_sink_get_symbols_per_cycle()
- data_sink_set enable()
- data_sink_get_enable()
- data_sink_set_throttle()
- data_sink_get_throttle()
- data_sink_get_packet_count()
- data_sink_get_symbol_count()
- data_sink_get_error_count()
- data_sink_get_exception()
- data_sink_exception_is_exception()
- data_sink_exception_has_data_error()
- data_sink_exception_has_missing_sop()
- data_sink_exception_has_missing_eop()
- data_sink_exception_signalled_error()
- data_sink_exception_channel()
- Document Revision History
- 34. Avalon Streaming Data Pattern Generator and Checker Cores
- 35. PLL Cores
- 36. Altera MSI to GIC Generator Core
- 37. Altera Interrupt Latency Counter Core
- 38. Altera GMII to RGMII Converter Core
- 39. Altera Generic Quad SPI Controller Core
- 40. Altera Serial Flash Controller Core
- 41. Altera Avalon Mailbox (simple) Core
- 42. Altera I2C Slave to Avalon-MM Master Bridge Core
- 43. Avalon-MM DDR Memory Half Rate Bridge Core
- 44. Altera Avalon I2C (Master) Core
- Core Overview
- Feature Description
- Configuration Parameters
- Interface
- Registers
- Register Memory Map
- Register Descriptions
- Transfer Command FIFO (TFR_CMD)
- Receive Data FIFO (RX_DATA)
- Control Register (CTRL)
- Interrupt Status Enable Register (ISER)
- Interrupt Status Register (ISR)
- Status Register (STATUS)
- TFR CMD FIFO Level (TFR CMD FIFO LVL)
- RX Data FIFO Level (RX Data FIFO LVL)
- SCL Low Count (SCL LOW)
- SCL High Count (SCL HIGH)
- SDA Hold Count (SDA HOLD)
- Reset and Clock Requirements
- Functional Description
- Document Revision History
- A. Document Revision History