ESD7M5.0DT5G Datasheet. Www.s Manuals.com. On

User Manual: Marking of electronic components, SMD Codes L7, L7*, L7***, L7-, L7-***, L77. Datasheets 2SC1623, 2SC1623W, BZX384-B10, ESD7M5.0DT5G, FMMTL717, RT9166A-28PXL, RT9818E-12PV, SST507, Si2307BDS.

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ESD7M5.0DT5G
Transient Voltage
Suppressors
ESD Protection Diodes with Ultra−Low
Capacitance
The ESD7M5.0DT5G is designed to protect voltage sensitive
components from damage due to ESD in applications that require ultra
low capacitance to preserve signal integrity. Excellent clamping
capability, low leakage and fast response time are combined with an
ultra low diode capacitance of 2.5 pF to provide best in class
protection from IC damage due to ESD. The ultra small SOT−723
package is ideal for designs where board space is at a premium. The
ESD7M5.0DT5G can be used to protect two uni−directional lines or
one bi−directional line. When used to protect one bi−directional line,
the effective capacitance is 1.25 pF. Because of its low capacitance, it
is well suited for protecting high frequency signal lines such as
USB2.0 high speed and antenna line applications.

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PIN 1. CATHODE
2. CATHODE
3. ANODE

Specification Features:

0.047” x 0.047” (1.20 mm x 1.20 mm)
Low Body Height: 0.020″ (0.5 mm)
Stand−off Voltage: 5 V
Low Leakage
Response Time is Typically < 1.0 ns
IEC61000−4−2 Level 4 ESD Protection
This is a Pb−Free Device

MARKING DIAGRAM
XX M
1
XX = Specific Device Code
M = Date Code

Mechanical Characteristics:
CASE: Void-free, transfer-molded, thermosetting plastic

Epoxy Meets UL 94 V−0
LEAD FINISH: 100% Matte Sn (Tin)
MOUNTING POSITION: Any

ORDERING INFORMATION
Device

Package

Shipping†

ESD7M5.0DT5G

SOT−723
(Pb−Free)

8000/Tape & Reel

QUALIFIED MAX REFLOW TEMPERATURE: 260°C

Device Meets MSL 1 Requirements
MAXIMUM RATINGS
Rating
IEC 61000−4−2 (ESD)

SOT−723
CASE 631AA

• Low Capacitance 2.5 pF Max
• Low Clamping Voltage
• Small Body Outline Dimensions:
•
•
•
•
•
•

Symbol
Contact

Value

Unit

†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

±10

Total Power Dissipation on FR−5 Board
(Note 1) @ TA = 25°C

°PD°

150

Storage Temperature Range

Tstg

−55 to +150

°C

DEVICE MARKING INFORMATION

Junction Temperature Range

−55 to +125

°C

Lead Solder Temperature − Maximum
(10 Second Duration)

260

°C

See specific marking information in the device marking
column of the Electrical Characteristics tables starting on
page 2 of this data sheet.

Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−5 = 1.0 x 0.75 x 0.62 in.

See Application Note AND8308/D for further description of survivability specs.

December, 2008 − Rev. 3

Publication Order Number:
ESD7M5.0D/D

ESD7M5.0DT5G
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol

Parameter

IPP

Maximum Reverse Peak Pulse Current

Clamping Voltage @ IPP

VRWM
IR

Working Peak Reverse Voltage

VBR

Test Current

Forward Current

Forward Voltage @ IF

Ppk

Peak Power Dissipation

IR VF
IT

Breakdown Voltage @ IT

VC VBR VRWM

Maximum Reverse Leakage Current @ VRWM

IPP

Uni−Directional TVS

Capacitance @ VR = 0 and f = 1.0 MHz

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted, VF = 1.1 V Max. @ IF = 10 mA for all types)
VRWM
(V)

IR (mA)
@ VRWM

VBR (V)
@ IT
(Note 2)

C (pF),
uni−directional
(Note 3)

C (pF),
bi−directional
(Note 4)

VC (V)
@ IPP = 1 A
(Note 5)

VC
Per
IEC61000−
4−2
(Note 6)

Device

Device
Marking

Max

Min

Max

ESD7M5.0DT5G

5.0

1.0

5.4

1.0

2.5

1.25

10.4

2.
3.
4.
5.
6.

Figures 1
and 2

VBR is measured with a pulse test current IT at an ambient temperature of 25°C.
Uni−directional capacitance at f = 1 MHz, VR = 0 V, TA = 25°C (pin1 to pin 3; pin 2 to pin 3).
Bi−directional capacitance at f = 1 MHz, VR = 0 V, TA = 25°C (pin1 to pin 2).
Surge current waveform per Figure 5.
For test procedure see Figures 3 and 4 and Application Note AND8307/D.

Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV contact per IEC 61000−4−2

Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV contact per IEC 61000−4−2

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2

ESD7M5.0DT5G
IEC61000−4−2 Waveform

IEC 61000−4−2 Spec.

Ipeak

Level

Test
Voltage
(kV)

First Peak
Current
(A)

Current at
30 ns (A)

Current at
60 ns (A)

7.5

22.5

100%
90%

I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns

Figure 3. IEC61000−4−2 Spec

ESD Gun

Oscilloscope

TVS

50 W
Cable

50 W

Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.

systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger

% OF PEAK PULSE CURRENT

100

PEAK VALUE IRSM @ 8 ms

PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms

80
70
60

HALF VALUE IRSM/2 @ 20 ms

50
40
30

20
10
0

40
t, TIME (ms)

Figure 5. 8 X 20 ms Pulse Waveform

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3

ESD7M5.0DT5G
PACKAGE DIMENSIONS
SOT−723
CASE 631AA−01
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.

−X−
D

A
−Y−

3
1

b 2X
0.08 (0.0032) X Y

DIM
A
b
b1
C
D
E
e
HE
L

MILLIMETERS
MIN
NOM
MAX
0.45
0.50
0.55
0.15
0.21
0.27
0.25
0.31
0.37
0.07
0.12
0.17
1.15
1.20
1.25
0.75
0.80
0.85
0.40 BSC
1.15
1.20
1.25
0.15
0.20
0.25

INCHES
MIN
NOM
MAX
0.018 0.020 0.022
0.0059 0.0083 0.0106
0.010 0.012 0.015
0.0028 0.0047 0.0067
0.045 0.047 0.049
0.03 0.032 0.034
0.016 BSC
0.045 0.047 0.049
0.0059 0.0079 0.0098

SOLDERING FOOTPRINT*
0.40
0.0157
0.40
0.0157
1.0
0.039
0.40
0.0157

0.40
0.0157

0.40
0.0157
SCALE 20:1

mm Ǔ
ǒinches

*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com

N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850

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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative

ESD7M5.0D/D

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