TMS320x2806x Piccolo Technical Reference Guide (Rev. G) F28069 Manual Uj
f28069_manual_uj
User Manual:
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- Table of Contents
- Preface
- 1 System Control and Interrupts
- 1.2 Flash and OTP Memory Blocks
- 1.3 Code Security Module (CSM)
- 1.4 Clocking
- 1.4.1 Clocking and System Control
- 1.4.2 OSC and PLL Block
- 1.4.2.1 Input Clock Options
- 1.4.2.2 Configuring XCLKIN Source and XCLKOUT Options
- 1.4.2.3 Configuring Device Clock Domains
- 1.4.2.4 PLL-based Clock Module
- 1.4.2.5 PLL Control (PLLCR) Register
- 1.4.2.6 PLL Control, Status and XCLKOUT Register Descriptions
- 1.4.2.7 PLL2 Registers
- 1.4.2.8 Input Clock Fail Detection
- 1.4.2.9 Missing Clock Reset and Missing Clock Status
- 1.4.2.10 NMI Interrupt and Watchdog
- 1.4.2.11 XCLKOUT Generation
- 1.4.2.12 External Reference Oscillator Clock Option
- 1.4.3 Low-Power Modes Block
- 1.4.4 CPU Watchdog Block
- 1.4.5 32-Bit CPU Timers 0/1/2
- 1.5 General-Purpose Input/Output (GPIO)
- 1.6 Peripheral Frames
- 1.7 Peripheral Interrupt Expansion (PIE)
- 1.8 VREG/BOR/POR
- 2 Boot ROM
- 2.1 Boot ROM Memory Map
- 2.2 Bootloader Features
- 2.2.1 Bootloader Functional Operation
- 2.2.2 Bootloader Device Configuration
- 2.2.3 PLL Multiplier and DIVSEL Selection
- 2.2.4 Watchdog Module
- 2.2.5 Taking an ITRAP Interrupt
- 2.2.6 Internal Pullup Resisters
- 2.2.7 PIE Configuration
- 2.2.8 Reserved Memory
- 2.2.9 Bootloader Modes
- 2.2.10 Device_Cal
- 2.2.11 Bootloader Data Stream Structure
- 2.2.12 Basic Transfer Procedure
- 2.2.13 InitBoot Assembly Routine
- 2.2.14 SelectBootMode Function
- 2.2.15 CopyData Function
- 2.2.16 SCI_Boot Function
- 2.2.17 Parallel_Boot Function (GPIO)
- 2.2.18 SPI_Boot Function
- 2.2.19 I2C Boot Function
- 2.2.20 eCAN Boot Function
- 2.2.21 ExitBoot Assembly Routine
- 2.3 Building the Boot Table
- 2.4 Bootloader Code Overview
- 3 Enhanced Pulse Width Modulator (ePWM) Module
- 3.1 Introduction
- 3.2 ePWM Submodules
- 3.2.1 Overview
- 3.2.2 Time-Base (TB) Submodule
- 3.2.3 Counter-Compare (CC) Submodule
- 3.2.4 Action-Qualifier (AQ) Submodule
- 3.2.5 Dead-Band Generator (DB) Submodule
- 3.2.6 PWM-Chopper (PC) Submodule
- 3.2.7 Trip-Zone (TZ) Submodule
- 3.2.8 Event-Trigger (ET) Submodule
- 3.2.9 Digital Compare (DC) Submodule
- 3.3 Applications to Power Topologies
- 3.3.1 Overview of Multiple Modules
- 3.3.2 Key Configuration Capabilities
- 3.3.3 Controlling Multiple Buck Converters With Independent Frequencies
- 3.3.4 Controlling Multiple Buck Converters With Same Frequencies
- 3.3.5 Controlling Multiple Half H-Bridge (HHB) Converters
- 3.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
- 3.3.7 Practical Applications Using Phase Control Between PWM Modules
- 3.3.8 Controlling a 3-Phase Interleaved DC/DC Converter
- 3.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
- 3.3.10 Controlling a Peak Current Mode Controlled Buck Module
- 3.3.11 Controlling H-Bridge LLC Resonant Converter
- 3.4 Registers
- 3.4.1 Time-Base Submodule Registers
- 3.4.2 Counter-Compare Submodule Registers
- 3.4.3 Action-Qualifier Submodule Registers
- 3.4.4 Dead-Band Submodule Registers
- 3.4.5 PWM-Chopper Submodule Control Register
- 3.4.6 Trip-Zone Submodule Control and Status Registers
- 3.4.7 Digital Compare Submodule Registers
- 3.4.8 Event-Trigger Submodule Registers
- 3.4.9 Proper Interrupt Initialization Procedure
- 4 High-Resolution Pulse Width Modulator (HRPWM)
- 4.1 Introduction
- 4.2 Operational Description of HRPWM
- 4.3 HRPWM Register Descriptions
- 4.4 Appendix A: SFO Library Software - SFO_TI_Build_V6.lib
- 4.5 Scale Factor Optimizer Function - int SFO()
- 4.6 Software Usage
- 4.7 SFO Library Version Software Differences
- 5 High Resolution Capture (HRCAP)
- 5.1 Introduction
- 5.2 Description
- 5.3 Operational Details
- 5.4 Register Descriptions
- 5.4.1 HRCAP Control Register (HCCTL) – EALLOW protected
- 5.4.2 HRCAP Interrupt Flag Register (HCIFR)
- 5.4.3 HRCAP Interrupt Clear Register (HCICLR)
- 5.4.4 HRCAP Interrupt Force Register (HCIFRC)
- 5.4.5 HRCAP Counter Register (HCCOUNTER)
- 5.4.6 HRCAP Capture Counter On Rising Edge 0 Register (HCCAPCNTRISE0)
- 5.4.7 HRCAP Capture Counter On Rising Edge 1 Register (HCCAPCNTRISE1)
- 5.4.8 HRCAP Capture Counter On Falling Edge 0 Register (HCCAPCNTFALL0)
- 5.4.9 HRCAP Capture Counter On Falling Edge 1 Register (HCCAPCNTFALL1)
- 5.5 HRCAP Calibration Library
- 6 Enhanced Capture (eCAP) Module
- 6.1 Introduction
- 6.2 Description
- 6.3 Capture and APWM Operating Mode
- 6.4 Capture Mode Description
- 6.5 Capture Module - Control and Status Registers
- 6.6 Register Mapping
- 6.7 Application of the ECAP Module
- 6.7.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger
- 6.7.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger
- 6.7.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger
- 6.7.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger
- 6.8 Application of the APWM Mode
- 7 Enhanced QEP (eQEP) Module
- 7.1 Introduction
- 7.2 Description
- 7.3 Quadrature Decoder Unit (QDU)
- 7.4 Position Counter and Control Unit (PCCU)
- 7.5 eQEP Edge Capture Unit
- 7.6 eQEP Watchdog
- 7.7 Unit Timer Base
- 7.8 eQEP Interrupt Structure
- 7.9 eQEP Registers
- 8 Analog-to-Digital Converter and Comparator
- 8.1 Analog-to-Digital Converter (ADC)
- 8.1.1 Features
- 8.1.2 Block Diagram
- 8.1.3 SOC Principle of Operation
- 8.1.4 ONESHOT Single Conversion Support
- 8.1.5 ADC Conversion Priority
- 8.1.6 Simultaneous Sampling Mode
- 8.1.7 EOC and Interrupt Operation
- 8.1.8 Power-Up Sequence
- 8.1.9 ADC Calibration
- 8.1.10 Internal/External Reference Voltage Selection
- 8.1.11 ADC Registers
- 8.1.11.1 ADC Control Register 1 (ADCCTL1)
- 8.1.11.2 ADC Control Register 2 (ADCCTL2)
- 8.1.11.3 ADC Interrupt Registers
- 8.1.11.4 ADC Priority Register
- 8.1.11.5 ADC SOC Registers
- 8.1.11.6 ADC Calibration Registers
- 8.1.11.7 Comparator Hysteresis Control Register
- 8.1.11.8 ADC Revision Register
- 8.1.11.9 ADC Result Registers
- 8.1.12 ADC Timings
- 8.1.13 Internal Temperature Sensor
- 8.2 Comparator Block
- 8.2.1 Features
- 8.2.2 Block Diagram
- 8.2.3 Comparator Function
- 8.2.4 DAC Reference
- 8.2.5 Ramp Generator Input
- 8.2.6 Initialization
- 8.2.7 Digital Domain Manipulation
- 8.2.8 Comparator Registers
- 8.2.8.1 Comparator Control (COMPCTL) Register
- 8.2.8.2 Compare Output Status (COMPSTS) Register
- 8.2.8.3 DAC Control (DACCTL) Register
- 8.2.8.4 DAC Value (DACVAL) Register
- 8.2.8.5 Ramp Generator Maximum Reference Active (RAMPMAXREF_ACTIVE) Register
- 8.2.8.6 Ramp Generator Maximum Reference Shadow (RAMPMAXREF_SHDW) Register
- 8.2.8.7 Ramp Generator Decrement Value Active (RAMPDECVAL_ACTIVE) Register
- 8.2.8.8 Ramp Generator Decrement Value Shadow (RAMPDECVAL_SHDW) Register
- 8.2.8.9 Ramp Generator Status (RAMPSTS) Register
- 8.1 Analog-to-Digital Converter (ADC)
- 9 Control Law Accelerator (CLA)
- 9.1 Control Law Accelerator (CLA) Overview
- 9.2 CLA Interface
- 9.3 CLA Configuration and Debug
- 9.4 Register Set
- 9.4.1 Register Memory Mapping
- 9.4.2 Task Interrupt Vector Registers
- 9.4.3 Configuration Registers
- 9.4.3.1 Control Register (MCTL)
- 9.4.3.2 Memory Configuration Register (MMEMCFG)
- 9.4.3.3 CLA Peripheral Interrupt Source Select 1 Register (MPISRCSEL1)
- 9.4.3.4 Interrupt Enable Register (MIER)
- 9.4.3.5 Interrupt Flag Register (MIFR)
- 9.4.3.6 Interrupt Overflow Flag Register (MIOVF)
- 9.4.3.7 Interrupt Run Status Register (MIRUN)
- 9.4.3.8 Interrupt Force Register (MIFRC)
- 9.4.3.9 Interrupt Flag Clear Register (MICLR)
- 9.4.3.10 Interrupt Overflow Flag Clear Register (MICLROVF)
- 9.4.4 Execution Registers
- 9.5 Pipeline
- 9.6 Instruction Set
- 9.7 Appendix A: CLA and CPU Arbitration
- 10 Viterbi, Complex Math and CRC Unit (VCU)
- 11 Direct Memory Access (DMA) Module
- 11.1 Introduction
- 11.2 DMA Overview
- 11.3 Architecture
- 11.4 Pipeline Timing and Throughput
- 11.5 CPU Arbitration
- 11.6 Channel Priority
- 11.7 Address Pointer and Transfer Control
- 11.8 Overrun Detection Feature
- 11.9 Register Descriptions
- 11.9.1 DMA Control Register (DMACTRL) — EALLOW Protected
- 11.9.2 Debug Control Register (DEBUGCTRL) — EALLOW Protected
- 11.9.3 Revision Register (REVISION)
- 11.9.4 Priority Control Register 1 (PRIORITYCTRL1) — EALLOW Protected
- 11.9.5 Priority Status Register (PRIORITYSTAT)
- 11.9.6 Mode Register (MODE) — EALLOW Protected
- 11.9.7 Control Register (CONTROL) — EALLOW Protected
- 11.9.8 Burst Size Register (BURST_SIZE) — EALLOW Protected
- 11.9.9 BURST_COUNT Register
- 11.9.10 Source Burst Step Register Size (SRC_BURST_STEP) — EALLOW Protected
- 11.9.11 Destination Burst Step Register Size (DST_BURST_STEP) — EALLOW Protected
- 11.9.12 Transfer Size Register (TRANSFER_SIZE) — EALLOW Protected
- 11.9.13 Transfer Count Register (TRANSFER_COUNT)
- 11.9.14 Source Transfer Step Size Register (SRC_TRANSFER_STEP) — EALLOW Protected
- 11.9.15 Destination Transfer Step Size Register (DST_TRANSFER_STEP) — EALLOW Protected
- 11.9.16 Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) — EALLOW protected)
- 11.9.17 Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT)
- 11.9.18 Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) — EALLOW Protected
- 11.9.19 Shadow Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) — All EALLOW Protected
- 11.9.20 Active Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR/DST_BEG_ADDR)
- 11.9.21 Shadow Destination Begin and Current Address Pointer Registers (SRC_ADDR_SHADOW/DST_ADDR_SHADOW) — All EALLOW Protected
- 11.9.22 Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR)
- 12 Serial Peripheral Interface (SPI)
- 12.1 Enhanced SPI Module Overview
- 12.1.1 SPI Block Diagram
- 12.1.2 SPI Module Signal Summary
- 12.1.3 Overview of SPI Module Registers
- 12.1.4 SPI Operation
- 12.1.5 SPI Interrupts
- 12.1.6 SPI FIFO Description
- 12.1.7 SPI 3-Wire Mode Description
- 12.1.8 SPI STEINV Bit in Digital Audio Transfers
- 12.2 SPI Registers and Waveforms
- 12.2.1 SPI Example Waveforms
- 12.2.2 SPI Control Registers
- 12.2.2.1 SPI Configuration Control Register (SPICCR)
- 12.2.2.2 SPI Operation Control Register (SPICTL)
- 12.2.2.3 SPI Status Register (SPIST)
- 12.2.2.4 SPI Baud Rate Register (SPIBRR)
- 12.2.2.5 SPI Emulation Buffer Register (SPIRXEMU)
- 12.2.2.6 SPI Serial Receive Buffer Register (SPIRXBUF)
- 12.2.2.7 SPI Serial Transmit Buffer Register (SPITXBUF)
- 12.2.2.8 SPI Serial Data Register (SPIDAT)
- 12.2.2.9 SPI FIFO Transmit, Receive, and Control Registers
- 12.2.2.10 SPI Priority Control Register (SPIPRI)
- 12.1 Enhanced SPI Module Overview
- 13 Serial Communications Interface (SCI)
- 13.1 Enhanced SCI Module Overview
- 13.1.1 Architecture
- 13.1.1.1 SCI Module Signal Summary
- 13.1.1.2 Multiprocessor and Asynchronous Communication Modes
- 13.1.1.3 SCI Programmable Data Format
- 13.1.1.4 SCI Multiprocessor Communication
- 13.1.1.5 Idle-Line Multiprocessor Mode
- 13.1.1.6 Address-Bit Multiprocessor Mode
- 13.1.1.7 SCI Communication Format
- 13.1.1.8 SCI Port Interrupts
- 13.1.1.9 SCI Baud Rate Calculations
- 13.1.1.10 SCI Enhanced Features
- 13.1.1 Architecture
- 13.2 SCI Registers
- 13.2.1 SCI Module Register Summary
- 13.2.2 SCI Communication Control Register (SCICCR)
- 13.2.3 SCI Control Register 1 (SCICTL1)
- 13.2.4 SCI Baud-Select Registers (SCIHBAUD, SCILBAUD)
- 13.2.5 SCI Control Register 2 (SCICTL2)
- 13.2.6 SCI Receiver Status Register (SCIRXST)
- 13.2.7 Receiver Data Buffer Registers (SCIRXEMU, SCIRXBUF)
- 13.2.8 SCI Transmit Data Buffer Register (SCITXBUF)
- 13.2.9 SCI FIFO Registers (SCIFFTX, SCIFFRX, SCIFFCT)
- 13.2.10 Priority Control Register (SCIPRI)
- 13.1 Enhanced SCI Module Overview
- 14 Inter-Integrated Circuit Module (I2C)
- 14.1 Introduction to the I2C Module
- 14.2 I2C Module Operational Details
- 14.3 Interrupt Requests Generated by the I2C Module
- 14.4 Resetting/Disabling the I2C Module
- 14.5 I2C Module Registers
- 14.5.1 I2C Mode Register (I2CMDR)
- 14.5.2 I2C Extended Mode Register (I2CEMDR)
- 14.5.3 I2C Interrupt Enable Register (I2CIER)
- 14.5.4 I2C Status Register (I2CSTR)
- 14.5.5 I2C Interrupt Source Register (I2CISRC)
- 14.5.6 I2C Prescaler Register (I2CPSC)
- 14.5.7 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
- 14.5.8 I2C Slave Address Register (I2CSAR)
- 14.5.9 I2C Own Address Register (I2COAR)
- 14.5.10 I2C Data Count Register (I2CCNT)
- 14.5.11 I2C Data Receive Register (I2CDRR)
- 14.5.12 I2C Data Transmit Register (I2CDXR)
- 14.5.13 I2C Transmit FIFO Register (I2CFFTX)
- 14.5.14 I2C Receive FIFO Register (I2CFFRX)
- 15 Multichannel Buffered Serial Port (McBSP)
- 15.1 Overview
- 15.2 Clocking and Framing Data
- 15.3 Frame Phases
- 15.4 McBSP Sample Rate Generator
- 15.5 McBSP Exception/Error Conditions
- 15.6 Multichannel Selection Modes
- 15.7 SPI Operation Using the Clock Stop Mode
- 15.8 Receiver Configuration
- 15.8.1 Programming the McBSP Registers for the Desired Receiver Operation
- 15.8.2 Resetting and Enabling the Receiver
- 15.8.3 Set the Receiver Pins to Operate as McBSP Pins
- 15.8.4 Enable/Disable the Digital Loopback Mode
- 15.8.5 Enable/Disable the Clock Stop Mode
- 15.8.6 Enable/Disable the Receive Multichannel Selection Mode
- 15.8.7 Choose One or Two Phases for the Receive Frame
- 15.8.8 Set the Receive Word Length(s)
- 15.8.9 Set the Receive Frame Length
- 15.8.10 Enable/Disable the Receive Frame-Synchronization Ignore Function
- 15.8.11 Set the Receive Companding Mode
- 15.8.12 Set the Receive Data Delay
- 15.8.13 Set the Receive Sign-Extension and Justification Mode
- 15.8.14 Set the Receive Interrupt Mode
- 15.8.15 Set the Receive Frame-Synchronization Mode
- 15.8.16 Set the Receive Frame-Synchronization Polarity
- 15.8.17 Set the Receive Clock Mode
- 15.8.18 Set the Receive Clock Polarity
- 15.8.19 Set the SRG Clock Divide-Down Value
- 15.8.20 Set the SRG Clock Synchronization Mode
- 15.8.21 Set the SRG Clock Mode (Choose an Input Clock)
- 15.8.22 Set the SRG Input Clock Polarity
- 15.9 Transmitter Configuration
- 15.9.1 Programming the McBSP Registers for the Desired Transmitter Operation
- 15.9.2 Resetting and Enabling the Transmitter
- 15.9.3 Set the Transmitter Pins to Operate as McBSP Pins
- 15.9.4 Enable/Disable the Digital Loopback Mode
- 15.9.5 Enable/Disable the Clock Stop Mode
- 15.9.6 Enable/Disable Transmit Multichannel Selection
- 15.9.7 Choose One or Two Phases for the Transmit Frame
- 15.9.8 Set the Transmit Word Length(s)
- 15.9.9 Set the Transmit Frame Length
- 15.9.10 Enable/Disable the Transmit Frame-Synchronization Ignore Function
- 15.9.11 Set the Transmit Companding Mode
- 15.9.12 Set the Transmit Data Delay
- 15.9.13 Set the Transmit DXENA Mode
- 15.9.14 Set the Transmit Interrupt Mode
- 15.9.15 Set the Transmit Frame-Synchronization Mode
- 15.9.16 Set the Transmit Frame-Synchronization Polarity
- 15.9.17 Set the SRG Frame-Synchronization Period and Pulse Width
- 15.9.18 Set the Transmit Clock Mode
- 15.9.19 Set the Transmit Clock Polarity
- 15.10 Emulation and Reset Considerations
- 15.11 Data Packing Examples
- 15.12 McBSP Registers
- 15.12.1 Register Summary
- 15.12.2 Data Receive Registers (DRR[1,2])
- 15.12.3 Data Transmit Registers (DXR[1,2])
- 15.12.4 Serial Port Control Registers (SPCR[1,2])
- 15.12.5 Receive Control Registers (RCR[1, 2])
- 15.12.6 Transmit Control Registers (XCR1 and XCR2)
- 15.12.7 Sample Rate Generator Registers (SRGR1 and SRGR2)
- 15.12.8 Multichannel Control Registers (MCR[1,2])
- 15.12.9 Pin Control Register (PCR)
- 15.12.10 Receive Channel Enable Registers (RCERA, RCERB, RCERC, RCERD, RCERE, RCERF, RCERG, RCERH)
- 15.12.11 Transmit Channel Enable Registers (XCERA, XCERB, XCERC, XCERD, XCERE, XCERF, XCERG, XCERH)
- 15.12.12 Interrupt Generation
- 16 Enhanced Controller Area Network (eCAN)
- 16.1 CAN Overview
- 16.2 The CAN Network and Module
- 16.3 eCAN Controller Overview
- 16.4 Message Objects
- 16.5 Message Mailbox
- 16.6 eCAN Registers
- 16.6.1 Mailbox Enable Register (CANME)
- 16.6.2 Mailbox-Direction Register (CANMD)
- 16.6.3 Transmission-Request Set Register (CANTRS)
- 16.6.4 Transmission-Request-Reset Register (CANTRR)
- 16.6.5 Transmission-Acknowledge Register (CANTA)
- 16.6.6 Abort-Acknowledge Register (CANAA)
- 16.6.7 Received-Message-Pending Register (CANRMP)
- 16.6.8 Received-Message-Lost Register (CANRML)
- 16.6.9 Remote-Frame-Pending Register (CANRFP)
- 16.6.10 Global Acceptance Mask Register (CANGAM)
- 16.6.11 Master Control Register (CANMC)
- 16.6.12 Bit-Timing Configuration Register (CANBTC)
- 16.6.13 Error and Status Register (CANES)
- 16.6.14 CAN Error Counter Registers (CANTEC/CANREC)
- 16.6.15 Interrupt Registers
- 16.6.16 Overwrite Protection Control Register (CANOPC)
- 16.6.17 eCAN I/O Control Registers (CANTIOC, CANRIOC)
- 16.7 Timer Management Unit
- 16.8 Mailbox Layout
- 16.9 Acceptance Filter
- 16.10 CAN Module Initialization
- 16.11 Steps to Configure eCAN
- 16.12 Handling of Remote Frame Mailboxes
- 16.13 Interrupts
- 16.14 CAN Power-Down Mode
- 17 Universal Serial Bus (USB) Controller
- 17.1 Introduction
- 17.2 Features
- 17.3 Functional Description
- 17.4 Initialization and Configuration
- 17.5 Register Map
- 17.6 Register Descriptions
- 17.6.1 USB Device Functional Address Register (USBFADDR), offset 0x000
- 17.6.2 USB Power Management Register (USBPOWER), offset 0x001
- 17.6.3 USB Transmit Interrupt Status Register (USBTXIS), offset 0x002
- 17.6.4 USB Receive Interrupt Status Register (USBRXIS), offset 0x004
- 17.6.5 USB Transmit Interrupt Enable Register (USBTXIE), offset 0x006
- 17.6.6 USB Receive Interrupt Enable Register (USBRXIE), offset 0x008
- 17.6.7 USB General Interrupt Status Register (USBIS), offset 0x00A
- 17.6.8 USB Interrupt Enable Register (USBIE), offset 0x00B
- 17.6.9 USB Frame Value Register (USBFRAME), offset 0x00C
- 17.6.10 USB Endpoint Index Register (USBEPIDX), offset 0x00E
- 17.6.11 USB Test Mode Register (USBTEST), offset 0x00F
- 17.6.12 USB FIFO Endpoint n Register (USBFIFO[0]-USBFIFO[3])
- 17.6.13 USB Device Control Register (USBDEVCTL), offset 0x060
- 17.6.14 USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ), offset 0x062
- 17.6.15 USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ), offset 0x063
- 17.6.16 USB Transmit FIFO Start Address Register (USBTXFIFOADD), offset 0x064
- 17.6.17 USB Receive FIFO Start Address Register (USBRXFIFOADD), offset 0x066
- 17.6.18 USB Connect Timing Register (USBCONTIM), offset 0x07A
- 17.6.19 USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF), offset 0x07D
- 17.6.20 USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF), offset 0x07E
- 17.6.21 USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[0]-USBTXFUNCADDR[3])
- 17.6.22 USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[0]-USBTXHUBADDR[3])
- 17.6.23 USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[0]-USBTXHUBPORT[3])
- 17.6.24 USB Receive Functional Address Endpoint n Registers (USBRXFUNCADDR[1]-USBRXFUNCADDR[3)
- 17.6.25 USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[1]-USBRXHUBADDR[3)
- 17.6.26 USB Receive Hub Port Endpoint n Registers (USBRXHUBPORT[1]-USBRXHUBPORT[3])
- 17.6.27 USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[1]-USBTXMAXP[3])
- 17.6.28 USB Control and Status Endpoint 0 Low Register (USBCSRL0), offset 0x102
- 17.6.29 USB Control and Status Endpoint 0 High Register (USBCSRH0), offset 0x103
- 17.6.30 USB Receive Byte Count Endpoint 0 Register (USBCOUNT0), offset 0x108
- 17.6.31 USB Type Endpoint 0 Register (USBTYPE0), offset 0x10A
- 17.6.32 USB NAK Limit Register (USBNAKLMT), offset 0x10B
- 17.6.33 USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[1]-USBTXCSRL[3)
- 17.6.34 USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[1]-USBTXCSRH[3])
- 17.6.35 USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[1]-USBRXMAXP[3])
- 17.6.36 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]-USBRXCSRL[3)
- 17.6.37 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]-USBRXCSRH[3])
- 17.6.38 USB Receive Byte Count Endpoint n Registers (USBRXCOUNT[1]-USBRXCOUNT[3)
- 17.6.39 USB Host Transmit Configure Type Endpoint n Register (USBTXTYPE[1]-USBTXTYPE[3])
- 17.6.40 USB Host Transmit Interval Endpoint n Register (USBTXINTERVAL[1]USBTXINTERVAL[3])
- 17.6.41 USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[1]-USBRXTYPE[3])
- 17.6.42 USB Host Receive Polling Interval Endpoint n Register (USBRXINTERVAL[1]-USBRXINTERVAL[3])
- 17.6.43 USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[1]-USBRQPKTCOUNT[3)
- 17.6.44 USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS), offset 0x340
- 17.6.45 USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS), offset 0x342
- 17.6.46 USB External Power Control Register (USBEPC), offset 0x400
- 17.6.47 USB External Power Control Raw Interrupt Status Register (USBEPCRIS), offset 0x404
- 17.6.48 USB External Power Control Interrupt Mask Register (USBEPCIM), offset 0x408
- 17.6.49 USB External Power Control Interrupt Status and Clear Register (USBEPCISC), offset 0x40C
- 17.6.50 USB Device RESUME Raw Interrupt Status Register (USBDRRIS), offset 0x410
- 17.6.51 USB Device RESUME Raw Interrupt Mask Register (USBDRIM), offset 0x414
- 17.6.52 USB Device RESUME Interrupt Status and Clear Register (USBDRISC), offset 0x418
- 17.6.53 USB General-Purpose Control and Status Register (USBGPCS), offset 0x41C
- 17.6.54 USB DMA Select Register (USBDMASEL), offset 0x450
- Revision History
- Important Notice