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Getting Started
With the Raisonance 8051, XA
and ST6 Development Kits

Revision 1.00

Getting Started with the Raisonance Development Kits
Information in this document is subject to change without notice and does not
represent a commitment on the part of the manufacturer. The software described in this
document is furnished under license agreement or nondisclosure agreement and may
be used or copied in accordance with the terms of the agreement. It is against the law
to copy the software on any medium except as specifically allowed in the license or
nondisclosure agreement. No part of this manual may be reproduced or transmitted in
any form or by any means, electronic or mechanical, including photocopying,
recording, or information storage and retrieval systems, for any purpose other than the
purchaser’s personal use, without prior written permission.
Every effort was made to ensure the accuracy in this manual and to give appropriate
credit to persons, companies and trademarks referenced herein.

Local Distributor

Microsoft® and Windows™ are trademarks or registered trademarks of Microsoft
Corporation.
PC® is a registered trademark of International Business Machines Corporation.
Written by Andrew Ayre
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Getting Started with the Raisonance Development Kits

Contents
Chapter 1. Introduction....................................................... 7
Development Tools ..................................................................................................... 8
Development Tool Names........................................................................................... 9
Conventions Used in this Manual ............................................................................. 10
Additional Help or Information ................................................................................ 11

Chapter 2. Development Steps ........................................ 13
The Relationship Between the Tools ........................................................................ 13
Listing Files............................................................................................................... 15
Summary of File Extensions ..................................................................................... 16

Chapter 3. Installing the Software ................................... 17
Minimum System Requirements............................................................................... 17
Installing the Software .............................................................................................. 17
Directory Structure.................................................................................................... 18

Chapter 4. Getting Started with RIDE ............................. 21
Overview of RIDE .................................................................................................... 21
Starting RIDE............................................................................................................ 23
Creating a Project...................................................................................................... 24
Creating and Adding a Source File ........................................................................... 26
Building the Project................................................................................................... 27
Adding More Code.................................................................................................... 28
Starting the RIDE Debugger ..................................................................................... 32
Breakpoints and Measuring Execution Time............................................................ 38
Setting Watchpoints .................................................................................................. 40
Simulation Animation ............................................................................................... 41
Stepping Through Code ............................................................................................ 42
Final Code Additions ................................................................................................ 45
Tracing and Displaying Waveforms ......................................................................... 46
Generating Waveforms on Pins ................................................................................ 50

Chapter 5. Compiler Listing and Linker Map Files ........ 55
Understanding the Compiler Listing File.................................................................. 55
Understanding the Linker Map File .......................................................................... 57

Chapter 6. Header Files .................................................... 61
Chapter 7. Compiler .......................................................... 63
Changing the Compiler Settings in RIDE................................................................. 63
8051 Compiler Options Overview ............................................................................ 64
XA Compiler Options Overview .............................................................................. 73
ST6 Compiler Options Overview.............................................................................. 81
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Getting Started with the Raisonance Development Kits
Compiler Command Line Syntax..............................................................................86

Chapter 8. Assembler ....................................................... 87
Changing the Assembler Settings in RIDE...............................................................87
8051 Assembler Options Overview ..........................................................................88
XA Assembler Options Overview ............................................................................91
ST6 Assembler Options Overview............................................................................94
Assembler Command Line Syntax............................................................................97

Chapter 9. Linker ............................................................... 99
Changing the Linker Settings in RIDE .....................................................................99
8051 Linker Options Overview...............................................................................100
XA Linker Options Overview .................................................................................106
ST6 Linker Options Overview ................................................................................110
Linker Command Line Syntax ................................................................................112

Glossary ........................................................................... 113
Index ................................................................................. 117

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Getting Started with the Raisonance Development Kits

Tables
Table 1.1 Tools Overview............................................................................................... 8
Table 1.2 Tool Names ..................................................................................................... 9
Table 2.1 Summary of File Extensions ......................................................................... 16
Table 6.1 SFR Bit Addresses ........................................................................................ 62
Table 7.1 8051 Compiler Source Settings .................................................................... 64
Table 7.2 8051 Compiler Floating Point Settings......................................................... 65
Table 7.3 8051 Compiler Code Generation Settings .................................................... 66
Table 7.4 8051 Compiler Listing Settings .................................................................... 67
Table 7.5 8051 Compiler Object Settings ..................................................................... 68
Table 7.6 8051 Compiler Memory Model Settings ...................................................... 70
Table 7.7 8051 Compiler Memory Models................................................................... 70
Table 7.8 8051 Compiler Register Settings .................................................................. 71
Table 7.9 8051 Compiler Optimizer Settings ............................................................... 71
Table 7.10 8051 Compiler Messages Settings .............................................................. 72
Table 7.11 XA Compiler Source Settings..................................................................... 73
Table 7.12 XA Compiler Floating Point Settings ......................................................... 73
Table 7.13 XA Compiler Code Generation Settings..................................................... 74
Table 7.14 XA Compiler Listing Settings .................................................................... 76
Table 7.15 XA Compiler Object Settings ..................................................................... 77
Table 7.16 XA Compiler Memory Model Settings....................................................... 78
Table 7.17 XA Compiler Memory Models ................................................................... 79
Table 7.18 XA Compiler Optimizer Settings................................................................ 79
Table 7.19 XA Compiler Messages Settings ................................................................ 80
Table 7.20 ST6 Compiler Source Settings.................................................................... 81
Table 7.21 ST6 Compiler Code Generation Settings.................................................... 81
Table 7.22 ST6 Compiler Listing Settings.................................................................... 83
Table 7.23 ST6 Compiler Object Settings .................................................................... 84
Table 7.24 ST6 Compiler Memory Model Settings...................................................... 84
Table 7.25 ST6 Compiler Memory Models .................................................................. 84
Table 7.26 ST6 Compiler Optimizer Settings............................................................... 85
Table 7.27 ST6 Compiler Messages Settings ............................................................... 85
Table 8.1 8051 Assembler Source Settings .................................................................. 88
Table 8.2 8051 Assembler Listing Settings .................................................................. 89
Table 8.3 8051 Assembler Object Settings ................................................................... 90
Table 8.4 XA Assembler Source Settings..................................................................... 91
Table 8.5 XA Assembler Listing Settings .................................................................... 92
Table 8.6 XA Assembler Object Settings ..................................................................... 93
Table 8.7 ST6 Assembler Source Settings.................................................................... 94
Table 8.8 ST6 Assembler Listing Settings.................................................................... 95
Table 8.9 ST6 Assembler Object Settings .................................................................... 96
Table 9.1 8051 Linker Settings ................................................................................... 101
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Getting Started with the Raisonance Development Kits
Table 9.2 8051 Linker Listing Settings.......................................................................101
Table 9.3 8051 Linker Bank Switching Settings ........................................................102
Table 9.4 8051 Linker Flash Settings .........................................................................103
Table 9.5 8051 Linker Kernel Settings .......................................................................104
Table 9.6 8051 Linker ROM-Monitor Settings...........................................................105
Table 9.7 XA Linker Settings ..................................................................................... 107
Table 9.8 XA Linker Relocation Settings ...................................................................107
Table 9.9 XA Linker Kernel Settings .........................................................................108
Table 9.10 XA Linker ROM-Monitor Settings...........................................................108
Table 9.11 ST6 Linker Settings ..................................................................................110
Table 9.12 ST6 Linker Listing Settings ......................................................................111

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Getting Started with the Raisonance Development Kits

Chapter 1. Introduction
The Raisonance 8051, XA and ST6 Development Kits are a complete solution to
creating software for the 8051 family, XA family and ST6 family of microcontrollers.
The Development Kits comprise many different tools that allow projects ranging from
simple to highly complex to be developed with relative ease.
Raisonance has been developing embedded tools since 1988 and has built up many
years of experience. You will find that with the Raisonance Development Kits you can
rely on tools that have been tested by real users over a long period of time.
This manual has been written to introduce the first time user to the Raisonance
Development Kits and guide them through many of the features available. With the aid
of this manual users should be able to quickly understand the tools, how they interact
with each other and how to start developing their own projects. This manual does not
cover the features in great detail or cover advanced features, but provides a familiarity
to the tools that will provided a basis for using more complex features.
It is assumed that the user is familiar with Windows and has at least some familiarity
with the 8051, XA or ST6 microcontroller family and the C programming language.
This manual is organized into two main parts. The first part takes on a tutorial form,
guiding the user through installation and the Windows front-end, demonstrating the
main features and ideas. The second part takes on a reference form and provides
information about each of the tools in turn.
In some places there are differences between the 8051, XA and ST6 tools and they will
be pointed out. To demonstrate the RIDE simulator an 8051 will be simulated,
however the simulator is identical in all the Development Kits apart from the aspects
specific to the 8051.

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Chapter 1 Introduction

Development Tools
The following is a list of the tools included in the Development Kit with a short
overview of each one:
Tool
ANSI C
Compiler

Assembler

Linker/Locator

Object-to-HEX
Converter
RIDE

Library
Manager
Monitor

Page 8

Overview
The C Compiler is an ANSI compliant compiler that takes source
files and generates object files. Extensions to the C language are
used to enable features of the microcontroller to be used or
controlled.
The Assembler takes source files written in assembler and
generates object files. Controls are included to enable features of
the microcontroller to be used or controlled.
The Linker combines the object files generated by the Compiler
and Linker and produces a different kind of object file. The
Linker also decides where certain types of Data and Code are
located in memory.
The converter converts an object file generated by the linker and
generates an Intel Hex file, compatible with most device
programmers.
The Raisonance Integrated Development Environment. RIDE is a
Windows program that allows the user to create projects, easily
call the Compiler, Assembler and Linker to build the project and
either simulate or debug the project.
The Library Manager can take object files generated by the
Compiler or Assembler and create a library that is included in
other projects.
The Monitor is a program that runs on hardware and transmits
debugging information back to RIDE as the program executes. It
also provides a means of controlling the execution of the program
and debugging the program while it is executing on hardware
Table 1.1 Tools Overview

Getting Started with the Raisonance Development Kits

Development Tool Names
Some of the tools have names by which they are often referred to. The table below lists
the names for each of the three toolsets.
Tool
ANSI C Compiler
Assembler
Linker/Locator
Object-HEX
Converter
Library Manager

8051 Tool Name
RC-51
MA-51
LX-51
OH51XA

XA Tool Name
RC-XA
MA-XA
RL-XA
OH51XA

LIB-51

LIB-XA

ST6 Tool Name
RC-ST6
MA-ST6
RL-ST6
OHST6
LIB-ST6
Table 1.2 Tool Names

RIDE (Raisonance Integrated Development Environment) is common to all three tool
chains. Only the installation specifies which Microcontroller family is available.

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Chapter 1 Introduction

Conventions Used in this Manual
File | New

Refers to the menu item “New” on the File menu

while(1);

(bold, monospaced type) User input

filename

Replace the italicized text with the item it represents.

[ ]

Items inside [ and ] are optional.

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Getting Started with the Raisonance Development Kits

Additional Help or Information
You may find additional documentation in the DOCS folder inside the RIDE
installation. In addition help is available via the Help menu in RIDE.
Also you can visit the following web sites:
http://www.raisonance.com
http://www.amrai.com
North and South America:
Address:

American Raisonance Inc.,
PO Box 1784,
Addison, TX 75001-1784
USA

Telephone:
Fax:

1-877-315-0792
1-972-818-0996

Email:

info@amrai.com (General information)
sales@amrai.com (Sales)
support@amrai.com (Customer Support)

Rest of the World:
Address:

Raisonance S.A.
755, Avenue Ambroise Croizat,
38920 Crolles, France

Telephone:
Fax:

+33 4 76 08 18 16
+33 4 76 08 09 97

Email:

info@raisonance.com

If you find any errors in this manual or omissions from it, or if you have suggestions
for improving this manual, please let us know by Emailing:
support@amrai.com

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Chapter 1 Introduction

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Getting Started with the Raisonance Development Kits

Chapter 2. Development Steps
The Relationship Between the Tools

The following diagram shows the relationship between the tools.
RIDE Editor
.a51/.st6/
.axa file

.c file

Compiler

Assembler

.obj file

.lib file

Linker/Locator

Library Manager
.lib file

.aof file
Object-HEX Converter
.hex file

RIDE Simulator/Debugger
1. RIDE provides an editor which allows the user to generate C source files (.c
extension) and Assembler source files (.a51 extension for 8051, .axa extension for XA
and .st6 extension for ST6).
2. Each source file is translated using the appropriate tool. The Compiler translates C
source files. The Assembler translates assembler source files. Each tool generates a
relocatable object file (.obj extension). If a project has more than one C source file or
more than one Assembler source file, then the Compiler and Assembler are executed
as many times as required.
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Chapter 2 Development Steps

3. If a library file is being generated then the Library Manager takes all the relocatable
object files and combines them into a library file (.lib extension). The library file may
then be linked in with other projects.
4. The Linker/Locator takes relocatable object files and library files and links them
together resolving external references. The Linker/Locator then locates variables and
code to specific addresses in the memory map. The Linker/Locator generates a single
Absolute Object File (.aof extension). It also generates the same file with no extension.
5. The Absolute Object File may then be used by the simulator or debugger in RIDE,
as the file can contain debugging information. Alternatively the Absolute Object File
may be used with In-Circuit Emulators.
6. The Object-HEX Converter tool converts an Absolute Object File into an Intel HEX
file (.hex extension) which is a representation of the pure binary code generated,
without debugging information. The Intel HEX File is accepted by virtually all device
programmers.
In addition to being an editor, simulator and debugger, RIDE also controls and
automates the entire build process. By selecting a single menu item, RIDE will execute
the correct tools to generate either a library file or an Absolute Object File and Intel
HEX File.

NOTE
Each relocatable object file is referred to as a module. Each module must have a
unique name. For example the source file foo.c generates the relocatable object file
foo.obj. The module name is therefore “foo”. However the source file foo.a51 also
generates the relocatable object file foo.obj.
The result is two modules with the same name. Therefore each source file must have a
unique name, regardless of whether it is a C source file or an Assembler source file.

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Getting Started with the Raisonance Development Kits

Listing Files
Some of the tools generate text files, collectively referred to as Listing Files, in
addition to the files shown in the diagram. These listing files aid the user in
understanding how the tools processed the input files and in tracking down problems.
The Compiler and Assembler generate a listing file (.lst extension) for each source file
they translate. The listing file contains such information as the assembly code
generated, a symbol table, the memory requirements of the module and how the tool
was invoked.
The Linker generates a listing file commonly referred to as the Map File (.m51
extension for 8051, .mxa extension for XA and .mst extension for ST6). This file will
be referred to as the Map File in the rest of this manual. The Map File contains a list of
input modules and libraries, a memory map of the project, a summary of the memory
requirements, a call tree and a symbol table. Only one Map File is generated as the
Linker is only executed once.

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Chapter 2 Development Steps

Summary of File Extensions

The following table provides a summary of the file extensions used.
File
Project
Compiler Source File
Assembler Source File
Compiler and Assembler Object Files
Compiler and Assembler Listing Files
Linker Object File
Linker Map File
Intel Hex File
Library File

8051 File
XA File
ST6 File
Extension
Extension
Extension
.prj
.prj
.prj
.c
.c
.c
.a51
.axa
.ast
.obj
.obj
.obj
.lst
.lst
.lst
.aof
.aof
.aof
.m51
.mxa
.mst
.hex
.hex
.hex
.lib
.lib
.lib
Table 2.1 Summary of File Extensions

Note
The file extensions used may be modified or additional file extensions supplied. In
RIDE choose Options | Tools then select the relevant tool and click on Edit.
Fields are provided to enter the input and output file extensions.

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Getting Started with the Raisonance Development Kits

Chapter 3. Installing the Software
Minimum System Requirements
•
•
•
•

Windows 95/98/NT/2000/Me
Pentium Processor
20Mb Hard Drive Space
32Mb RAM

Installing the Software
If the software is being installed from CD then the installation program should
automatically run when the CD is inserted.
If the CD autorun feature is turned off or you have downloaded the software from a
web site then the software may be installed simply by running INSTALL.EXE.

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Chapter 3 Installing the Software

Directory Structure
The following is the directory structure placed into the installation folder
BIN folder

This folder contains the executable files for the tools and associated library files
that are required by the tools.
DOC folder
Contains manuals for each of the tools as well as manuals for various evaluation
boards
EXAMPLES folder
Contains example projects for use with RIDE, including Monitor example
projects. The examples are subdivided into categories.
HELP folder
Contains the on-line help files used by RIDE.
INC folder (INCST6 for the ST6)
Contains include files that may be used by users in projects. Some of the include
files define Special Function Registers for various derivatives. Include files for
the Standard C Libraries may also be found in this folder.
In addition source code for the Monitor (8051 and XA), some of the Standard C
Library functions, such as memory allocation (8051 and XA) and low-level I/O
and the startup code may be found in the Sources sub-folder.
LIB folder
Contains libraries that the Compiler and Linker/Locator may use in the compiling
of a source file or linking of a project. The libraries include such things as
routines to perform mathematical operations on floating point numbers, the
Standard C Library functions and the Monitor (8051 and XA).

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Getting Started with the Raisonance Development Kits

NOTE
The Compiler will look in the INC folder for header files (INCST6 for ST6). If the
Special Function Register Header File for the particular device you are using is not
present in the INC folder then you can easily create your own and place it in the INC
folder.
1. Find the header file of the device that is closest to the device you are using
2. Copy it and rename the copy to the name of the device
3. Using the device datasheet, add in the missing Special Function Register
declarations using the same format as shown in the file.
4. Include the header file in your C source files inside “<” and “>”, for example
#include

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Chapter 3 Installing the Software

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Getting Started with the Raisonance Development Kits

Chapter 4. Getting Started with RIDE
Overview of RIDE
It is possible to create the source files in a text editor such as Notepad, run the
Compiler on each C source file, specifying a list of controls, run the Assembler on
each Assembler source file, specifying another list of controls, run either the Library
Manager or Linker (again specifying a list of controls) and finally running the ObjectHEX Converter to convert the Linker output file to an Intel Hex File. Once that has
been completed the Hex File can be downloaded to the target hardware and debugged.
Alternatively RIDE can be used to create source files, automatically compile, link and
convert using options set with an easy to use user interface and finally simulate or
perform debugging on the hardware with access to C variables and memory.
Unless you have to use the tools on the command line, the choice is clear. RIDE
greatly simplifies the process of creating and testing an embedded application.
Projects
The use of RIDE centers on “projects”. What is a project? A project is a list of all the
source files required to build a single application, all the tool options which specify
exactly how to build the application, and – if required – how the application should be
simulated.
A project contains enough information to take a set of source files and generate exactly
the binary code required for the application.
Because of the high degree of flexibility required from the tools, there are many
options that can be set to configure the tools to operate in a specific manner. It would
be tedious to have to set these options up every time the application is being built,
therefore they are stored in a project file. Loading the project file into RIDE informs
RIDE which source files are required, where they are, and how to configure the tools
in the correct way. RIDE can then execute each tool with the correct options.
It is also possible to create new projects in RIDE. Source files are added to the project
and the tool options are set as required. The project can then be saved to preserve the
settings. The project also stores such things as which windows were left open in the
simulator/debugger, so when a project is reloaded and the simulator or debugger
started, all the desired windows are opened.
RIDE project files have the extension .prj.

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Chapter 4 Getting Started with RIDE
Simulator/Debugger
The simulator/debugger in RIDE can perform a very detailed simulation of a
microcontroller along with external signals. It is possible to view the precise execution
time of a single assembly instruction, or a single line of C code, all the way up to the
entire application, simply by entering the crystal frequency.
A window can be opened for each peripheral on the device, showing the state of the
peripheral. This enables quick troubleshooting of mis-configured peripherals.

Breakpoints may be set on either assembly instructions or lines of C code, and
execution may be stepped through one instruction or C line at a time.
The contents of all the memory areas may be viewed along with the ability to find
specific variables. In addition the registers may be viewed allowing a detailed view of
what the microcontroller is doing at any point in time.
This chapter will highlight the main features of RIDE and demonstrate how they are
used.

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Getting Started with the Raisonance Development Kits

Starting RIDE
Starting RIDE is very easy. Select “Ride IDE” from the Start | Programs | Raisonance
Kit menu.
You will be presented with the following splash screen:

After a few moments the main window will open. The main window is described in
the next section.

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Chapter 4 Getting Started with RIDE

Creating a Project
The first thing we will do is create a new project. We will then take a look at the main
RIDE window and become familiar with it.
Choose Project | New and you will be presented with a window which looks like the
following:

The Name field shows the path to the project file that will be created. The Type field
shows the microcontroller family type the project will use. Depending on which
development kit you are using the Type field will show either: 80C51, XA or ST6. If
you are running the combined 51+XA development kit then you are able to choose
between the 80C51 and XA at this point. Remember whether you choose 80C51 or XA
as you will need that information later on.
Click on the Browse button and browse to the folder where the project is to be created.
This manual will use the location:
C:\work
In the Filename field the name of the project is entered. Enter test.prj and click on
the Open button then click on the OK button to create the project.

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Getting Started with the Raisonance Development Kits
The main RIDE window should now look like the following:

Project
and
Debugger
windows

Toolbar

Make,
Debug,
Grep and
Script
windows

The Project window acts like a project manager, showing which source files are in the
project and giving instant access to each one in both the editor and debugger.
If you look at the Project window you will see one entry with the following pathname:
C:\WORK\TEST.AOF
This entry represents the project as a whole and the .aof file will be the result of
building the project.

Note
The .aof file (Absolute Object File) always takes its name from the name of the
project. In this case the project is called “Test” so the .aof file will be called “test.aof”.
Likewise the generated Intel Hex File will also be named after the project (“test.hex”).

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Chapter 4 Getting Started with RIDE

Creating and Adding a Source File
The next step we will take is to create a new, basic source file and add it to the project.
The following section will show how to build the project. We will then know that all
the tools are working and you will then have a starting point for all future projects.
To create a new source file choose File | New followed by “C Files” from the pop-up
menu that appears. A blank window will open.

Enter the following into the new window:
void main(void)
{
while(1);
}
To save the source file:
•
•
•

Choose File | Save. A standard Save As window will open.
Enter main.c into the Filename field.
Click on Save.

To add the file to the project:
•
•
•
•

Select “C:\WORK\TEST.AOF” in the project window and press the right
mouse button (right-click). A menu will pop up.
Select Add Node/Source Application from the menu.
Select main.c in the File Open window.
Click on Open.

A small “+” sign should appear next to the .aof file in the Project window. Click on the
“+” to expand the project tree. The source file should now appear in the Project
window under the .aof file:

Page 26

Getting Started with the Raisonance Development Kits

Building the Project
To build the project simply click on the Make All button on the toolbar
Make All button

Or choose Project | Make All
Once the project has been built, the Make window will show the result of the build
process in tree form:

Note
If the Compiler or Linker generated any warnings or errors then it would be possible to
view them in the Make window. In the case of Compiler warnings or errors, double
clicking on them in the Make window will take you to the relevant point in the source
code.

XA Development Kit Users:
Enter the following line at the top of the main.c source file before the main function:
#include
ST6 Development Kit Users:
Enter the following line at the top of the main.c source file before the main function:
#include
All Users:
•

Using the mouse select just the filename of the header file (for example
“reg51.h”):

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Getting Started with the Raisonance Development Kits
•
•

Press the right mouse button and a menu will pop-up.
Choose Open Document filename.

RIDE will find and open the header file you are including in main.c. You can now
examine the contents of the header file to see how SFRs are declared using the
language extensions.

Note
For more information on header files please refer to the Header Files chapter.

Below the #include add the following line:
unsigned char counter = 0;
We are going to add two functions. The first, called init, initializes a timer and the
timer interrupt. The second function, called timerisr, is the Interrupt Service Routine
for the timer. The code for both these functions is different for all three microcontroller
families, so please refer to the correct section below for the tools you are using.
8051 Development Kit Users
Add the following code before the main function, but after the line you just added
declaring the counter variable:
void timerisr(void) interrupt 1
{
TF0 = 0;
// clear overflow flag
counter++;
}
void init(void)
{
TMOD = 0x02; //
ET0 = 1;
//
EA = 1;
//
TR0 = 1;
//
}

8-bit auto-reload timer
enable timer interrupt
global interrupt enable
run timer

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Chapter 4 Getting Started with RIDE
XA Development Kit Users
Add the following code before the main function, but after the line you just added
declaring the counter variable:

void timerisr(void) interrupt 1 priority 15
{
TF0 = 0;
// clear overflow flag
counter++;
}
void init(void)
{
TMOD = 0x02; //
IPA0 = 0x70; //
ET0 = 1;
//
EA = 1;
//
TR0 = 1;
//
}

8-bit auto-reload timer
priority 15
enable timer interrupt
global interrupt enable
run timer

ST6 Development Kit Users
Add the following code before the main function, but after the line you just added
declaring the counter variable:
void timerisr(void) interrupt 3
{
TSCR &= 0x7f; // clear underflow flag
counter++;
}
void init(void)
{
TSCR = 0x48;
IOR = 0x10;

// timer interrupt enable, prescaler
// enable, divide by 1
// global interrupt enable

}
All Users:
Add the following line inside the main function, just before the while(1);
init();

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Getting Started with the Raisonance Development Kits
Save the source file by choosing File | Save or clicking on the Save button:
File Save button

Build the project by choosing Project | Make All or clicking on the Make All button:
Make All button

4
If “+” signs appear next to the Compiler or Linker items in the Make window, click on
the “+” sign to expand the tree and view the warnings. Double-click on the Compiler
warnings to jump to the relevant point in the source code and fix the problem.

Once you have the project successfully built we are ready to start the debugger.

Page 31

Chapter 4 Getting Started with RIDE

Starting the RIDE Debugger
The debugger is integrated into RIDE and is one mouse-click or menu item away.
To start the debugger either choose Debug | Start test.aof or click on the Debug button:
Debug button

4
You will be presented with the following debug options window:

Click on the OK button and the advanced options window will open:

Click on OK to accept the advanced options then click on OK in the debug options
window to accept those options.
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Note
Next time the debugger is started the debug options window will not open as you have
already confirmed that the options are correct. If you wish to change the debug options
either before starting the debugger or while debugging then choose Options | Debug.
The RIDE window should now look something like this:
Debug
Toolbar

Debugger
Window

4
Debug
Window

If you are currently not using the largest screen mode available to you then now might
be a good time to switch to it. The debugger features many windows that may be
opened.
There is a possible point of confusion over the window names in the debugger so both
windows will be described.

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Chapter 4 Getting Started with RIDE
The Debugger window shows a tree view of select debugger windows that may be
opened by double-clicking on the time in the tree. The windows listed are memory
viewing windows and peripheral windows.

4
Double-click on the “Data View” item. A window will open showing the contents of
memory (in this case Data memory)

The memory is shown in rows of eight bytes, first in hexadecimal and then in ASCII.
If the ASCII equivalent is a character that cannot be displayed then a period is
displayed instead.
Static variables may be searched for simply by entering the variable name in the search
field. Try entering
counter
and pressing return. A memory location will be highlighted indicating where the
variable is stored.

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Getting Started with the Raisonance Development Kits
Other features of the Data view are the ability to set write and read access breakpoints
(execution will stop when the memory location is written to or read from) by clicking
on the “W” and “R” buttons.

Pressing the right mouse button over the Data view window opens a pop-up menu that
provides the following functions:
•
•
•
•
•
•

Associate a memory location with a symbol
Associate a memory location with a function generator
Change the number of bytes shown per line
Go to a specific address or symbol
Fill memory with a value
Toggle write and read breakpoints

Double-clicking on a memory location in the window allows the value at that location
to be modified.

Close the Data View window, but make sure that no write or read breakpoints have
been set and that any memory locations that you modified are set back to their original
values.
The Debug window shows messages that relate to the debug session. For example if
you stop and start the simulation a message will appear for each, complete with a time
stamp.

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Chapter 4 Getting Started with RIDE
The blue bar in the source code window indicates the current execution point. It
highlights the next piece of code to be executed. The Compiler automatically includes
some startup code (written in assembler) that is executed before the main function is
reached. When you start the debugger it automatically executes the startup code and
stops at the first line in the main function. If you look at the status bar at the bottom of
the RIDE window you will see a time displayed:

4
This is the current execution time so far. As the only code that has been executed is the
startup code, this time shows how long the startup code took to execute.

Note
During a simulation the debugger will bring the source code window to the front. If the
source code window is maximized or covering other windows then it will not be
possible to view those other windows. We recommend that you do not maximize the
source code window and that you drag it out of the way when you want to view other
windows.
Enough of the window descriptions, lets watch the code be simulated!
You may have noticed the large GO button on the toolbar. It will come as no surprise
to learn that clicking on the GO button will start the simulation. Do that now.
GO button

Two things indicate that the simulation is taking place: periodically the execution time
at the bottom of the RIDE window will update and the GO button has changed into a
STOP button:
STOP button

Click on the STOP button to stop the simulation.

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Getting Started with the Raisonance Development Kits
Using the pointer, highlight “counter” in the source code window then hover the
pointer over the highlighted “counter” text for a moment. A tooltip will appear
showing the current value of the variable counter in hexadecimal:

This may be used for any identifier in the source code window. Try it for the SFR TFO
and a function name.

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Chapter 4 Getting Started with RIDE

Breakpoints and Measuring Execution Time
To the left of each C source line that generated code (and therefore was not optimized
out) a green dot appears.
Set a breakpoint on the first line of the timer Interrupt Service Routine by clicking on
the green dot. The dot will turn red with an “S” inside it and a red bar will highlight
the source line.

Click on the GO button. The simulation will stop almost immediately. If you look at
the debug window a message will indicate that the breakpoint was reached:

We are going to measure the time between interrupts. Choose Debug | Reset Time and
note that the current execution time shown at the bottom of the RIDE window has been
reset to zero:

Now click on the GO button to execute up to the start of the next interrupt. The
execution time between interrupts will now be shown at the bottom of the RIDE
window.

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Getting Started with the Raisonance Development Kits

Note
Using breakpoints and resetting the execution time makes it possible to measure the
time to execute any piece of code, including parts of functions or the whole
application, as well as verifying if you have correctly configured a timer to generate
interrupts at a specific rate.

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Chapter 4 Getting Started with RIDE

Setting Watchpoints
Don’t remove the breakpoint just yet.
Rather than highlighting the counter variable to see its value it would be useful if the
value was always shown on the screen. To do that we need to add the counter variable
to the Watch window.

•
•
•
•

Open the Watch window by choosing View | Watch.
With the pointer over the Watch window press the right mouse button.
Choose Add from the menu that pops up.
Enter counter into the expression field.

•

Click on OK

The Watch window will now show the current value of the counter variable in
decimal, with the hexadecimal equivalent in parentheses.

Click on the GO button to run to the next breakpoint. The value of counter will
increment and turn red. The value turns red to indicate that it has changed, and
therefore draws attention to itself.

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Getting Started with the Raisonance Development Kits

Simulation Animation
It’s as fun to see the simulation animate as it is to say the title of this section.
First remove the breakpoint by clicking on the red dot with an “S” inside it. The red
bar will also disappear.
Choose Debug | Animated Mode or click on the Animate button.
Animate button

Finally click on the GO button.
Every once in a while the blue bar will move to the Interrupt Service Routine, visit
each source line inside the ISR in turn then return to the while(1). At the same time
the value of counter will increment in the Watch window.
In the Debugger window, scroll down to the list of peripherals and double click on
“timer” or “timer0”, The timer peripheral window will open with the value of the timer
count register constantly changing as the execution progresses. The screen shot below
is for the 8051 timer so the one you see may look different.

Stop the simulation by clicking on the STOP button and either choose Debug |
Animated Mode or click on the Animate button to turn the animate mode off.
You can also close the timer peripheral window.

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Chapter 4 Getting Started with RIDE

Stepping Through Code
The RIDE debugger makes it possible to step through the simulation, one source line
at a time or one instruction at a time.
Set a breakpoint on the first line of the Interrupt Service Routine by clicking on the
green dot.
Green Dots

Click on the GO button to simulate up to that line.
To step through the source lines one at a time choose Debug | Step Into or click on the
Step Into button:
Step Into button

The blue bar will move onto the next source line on each press of the button or
selection of the menu entry. At the same time the current execution time shown at the
bottom of the RIDE window will increase.
Click on GO to execute up to the ISR again.
To view the assembly code equivalent of the C source code open the Disassembly
window by choosing View | Code or clicking on the Disassembly button:
Disassembly button

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Getting Started with the Raisonance Development Kits
The disassembly window will look something like:

Source code lines are shown in purple, with the assembler equivalent immediately
below.
When the Disassembly window has the focus (the title bar is not gray), performing a
Step Into will step through assembly code.
When the source code window has the focus, performing a Step Into will step through
C source code.
Open the Register window by choosing View | Main Registers, then repeatedly press
the Step Into button and watch the bar move and the registers change accordingly.
Even if the Disassembly window has the focus you can click on the GO button to
execute up to the next breakpoint.
When you are finished close the Disassembly window and remove the breakpoint.
Also close the Register window as well.
Either choose Debug | Terminate test.aof or click on the debug button to end the debug
session.
Debug button

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Chapter 4 Getting Started with RIDE

Note
When simulating more complex applications sometimes clicking on the STOP button
appears to have no effect. However if you wait for a short while the disassembly
window will open and a Break button will appear on the toolbar. If you wait some
more then eventually the simulation will stop.

This appears to be a bug but it is not. You tried to stop the simulation while the
debugger was in the middle of a large block of assembly code that corresponded to the
current C source line. Typically the assembly code will be library routines such as
printf. The debugger recognized that it would take some time to simulate all the
assembly code and reach the next C source line so it opened the disassembly window
for you at the current execution point in the assembly code. The Break button is
provided to allow you to stop the simulation immediately in the assembly code, rather
than wait for the next C source line to be reached.
If you do not like this behavior of the simulator then identify the C source lines that
take some time to execute and set a breakpoint on the following lines.

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Getting Started with the Raisonance Development Kits

Final Code Additions
In order to show a couple of useful features of the debugger we need to make some
additions to our code.
Change the line:
unsigned char counter = 0;

To:
unsigned char counter = 0, toggler = 0;
Just below counter++; inside the timerisr function, add the following line:
toggler = 0xFF – toggler;
Save the file by clicking on the Save button and rebuild the project by clicking on the
Make All button
Save button

Make All button

If there are any errors or warnings go back to your source code and fix them.

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Chapter 4 Getting Started with RIDE

Tracing and Displaying Waveforms
The RIDE debugger has the ability to graphically display waveforms relating to a
microcontroller pin or a variable. This allows the relationship between variables,
inputs and outputs to be clearly shown.
Start the debugger by choosing Debug | Start test.aof or by clicking on the Debug
button.

Open the Watch window by choosing View | Watch.
With the pointer over the Watch window press the right mouse button and choose Add
from the menu that pops up.
In the expression field enter
toggler
And click on OK. Toggler should appear in the Watch window.
Select toggler in the Watch window so it is highlighted in blue and press the right
mouse button again. This time select Add/Delete from Trace List from the menu that
pops up. A small “T” in a circle will appear next to toggler in the Watch window.

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Getting Started with the Raisonance Development Kits
Choose View | Trace | Options. The Trace Options window will open and look like:

Select “On Changes” and in the Maximum Number of records field enter
50
Click on OK.
To open the Trace window choose View | Trace | View.

Click on the GO button to start the simulation and allow it to run for a few moments
before stopping it by clicking on the STOP button.
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Chapter 4 Getting Started with RIDE
The top part of the Trace window will now show the trace records for the last 50
changes of toggler:

4
You can scroll through the trace records. The columns are:
t
dt
PC
Source
toggler

The simulation time
The change in simulation time between the records
The Program Counter at that point
The source code to be executed at that point
The value of toggler at that point

Because we selected the “On Changes” option, records are only generated when the
variables being traced (in our case toggler) change.
To view a waveform of toggler click on the title button of the toggler column

The lower part of the trace window will show a square wave as toggler changed
between 0xFF and 0x00.

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Getting Started with the Raisonance Development Kits
It is possible to zoom in on the waveform by dragging a box around the area of
interest. Timing information is shown along the bottom of the window.

4
Pressing the right mouse button while the point is over the waveform will zoom out to
the original view.
The trace records may be saved as a text file. Press the right mouse button over the
trace records and choose Save As from the pop-up menu.
Browse to the desired folder and enter the filename. Click on Open to save.

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Chapter 4 Getting Started with RIDE

Generating Waveforms on Pins
The RIDE debugger makes it easy to generate waveforms on a specific pin of the
microcontroller being simulated. Using function generators the program may be tested
with external input stimuli.
Choose View | Function Generators followed by Options from the pop-up menu. The
function generator main window will open.

Click on New to create a new function generator. The Function Generator Options
window will open.

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Getting Started with the Raisonance Development Kits
In the Name field enter
square wave
Select the Wave Form option.
In the Expression to Evaluate field enter
(L100U,H200U)
and click on OK. This will create a function generator that generates a square wave,
low for 100us and high for 200us.
Click on Close in the function generator main window.
The function generator needs to be attached to a microcontroller pin, and that is
achieved using a netlist. A netlist is a form of representing electrical circuits by giving
each connection (called a node) a unique name, then specifying what is connected to
the node.
Choose View | Nets. You will be presented with the Nets window.

Click on New to create a new node. Net0 will appear in the Net List area.

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Chapter 4 Getting Started with RIDE
8051 and XA Users
Find test.P0.0 in the Available list, select it and click on the “>” button. Test.P0.0 will
appear on the right side in the Connected list to show it is connected to the node.
ST6 Users
Find test.PB0 in the Available list, select it and click on the “>” button. Test.PB0 will
appear on the right side in the Connected list to show it is connected to the node.

All Users
Find square wave in the Available list, select it and click on the “>” button. Square
wave will appear on the right side in the Connected list to show it is connected to the
node.

Click on the Close button to close the Nets window.
Having a waveform on a pin is no good unless we can view it. We therefore need to
add the pin to the watch window.
With the pointer over the Watch window press the right mouse button and choose Add
from the pop-up menu.
8051 and XA Users
In the expression field enter:
P0.0
ST6 Users
In the expression field enter:
PB.0

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Getting Started with the Raisonance Development Kits
All Users
Click on OK.
Select the pin in the watch window so it is highlighted with a blue bar and press the
right mouse button. Choose Add/Delete from Trace List. A small blue “T” in a circle
will appear next to the pin name.

Start the simulation by pressing the GO button and allow it to run for a short while,
then stop the simulation by pressing the STOP button.
The trace records in the Trace window will now have a column for the port pin, with
entries either “TRUE” or “FALSE”.

Press the toggler column title button followed by the title button of the port pin column
to display the waveforms of both.

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Chapter 4 Getting Started with RIDE
You can zoom in to obtain a closer view of the waveforms.
Additional Things to Try
Add another variable to the code which is 0xFF only when toggler is 0xFF, and the
port pin is high, otherwise it is 0x00.
Add the variable to the watch window and trace it to see its waveform.

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Getting Started with the Raisonance Development Kits

Chapter 5. Compiler Listing and Linker Map
Files
This section is intended as a brief introduction to the Compiler listing file and the
Linker map file. For a more detailed examination of the file contents please refer to the
Compiler and Linker manuals.

Understanding the Compiler Listing File
Choose View | Listing from Compiler. A window will open showing the listing file
(.lst) generated by the Compiler when it processed main.c.
The Compiler listing file is very useful in understanding what the Compiler did. The
listing file contains six consecutive pieces of information.
Command Line Invocation
This information shows exactly how the Compiler would be called from the command
line to obtain the exact same result. This information is very useful if you want to
relate the Compiler options in RIDE with the command line options, or for better
understanding how the command line version of the Compiler is used.
Source Code
A listing of the input source code is included in the listing file. Each line is numbered
and source lines that actually generated code have a second number which relates to
the nesting level of the code.
It is possible to change how this section looks and include the source code from header
files by changing the compiler options.
Generated Assembler Equivalent
The assembly code generated by the compiler is listed to indicate exactly what the
compiler did when it processed the source code. This section is useful for tracking
down bugs in source code and understanding better how the compiler works.
Throughout the assembly code there are comments like:
; SOURCE LINE # 8
The assembly code immediately following the comment relates to that source code
line, which may be found by looking for the line number in the Source Code section of
the listing file.
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Chapter 5 Compiler Listing and Linker Map Files
The assembly code is divided up into functions.
Symbol Table
The symbol table lists all the static variables and functions that were found in the
source file. For each one various information is listed.
Module Information
The module information table gives a summary of the memory requirements of the
module. Some memory may be overlaid.

Errors and Warnings
The final piece of information given in the listing file is a summary of the number of
warnings and errors that were generated by the compiler. Note however that it does not
list the actual warnings and errors.

Note
You may have noticed at the start of the listing file a line that looks like:
QCW(0x00002D32)
The hexadecimal value is the internal compiler representation of most of the compiler
options. This value is for internal use only and aids Raisonance in supporting
customers, so you can safely ignore it.

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Getting Started with the Raisonance Development Kits

Understanding the Linker Map File
Choose View | Map Report from Linker. A window will open showing the Map File
(.m51 for 8051, .mxa for XA and .mst for ST6) generated by the Linker when it
processed all the object files in the project.
The Linker Map File is invaluable in understanding what the Linker did. It is probably
the most useful piece of information generated by the tools and understanding the
contents will vastly improve the chances of a project’s success. Indeed, without
understanding it many projects will never work. The listing file contains eight
consecutive pieces of information (nine for the ST6).

Command Line
This information shows exactly how the linker would be called from the command line
to obtain the exact same result. This information is very useful if you want to relate the
linker options in RIDE with the command line options, or for better understanding
how the command line version of the linker is used.
Memory Model
This section shows the memory model that was used for the project. This is useful for
double-checking that the intended memory model was used.
Input Modules
A list of all the input modules is given. The input modules include the modules
generated by the source files, plus any library modules if required.
After the path to each module, the module name is given in parentheses.
Link Map
The Link Map is the memory map of the project and shows exactly where every piece
of code and data was located.
The memory map is given as a table, divided into the various memory areas supported
by the microcontroller.
Each source file is divided up into segments. All the code in a function will be placed
in a single segment. All the static DATA variables will be placed in another segment.
All the static IDATA variables will be placed in yet another segment.
Each line in the link map is one segment, showing where it was located and how big
the segment is.
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Chapter 5 Compiler Listing and Linker Map Files
Function segment names are given the following format:
memorytype?functionname?modulename
Data segment names are given the following format:
memorytype?modulename
Some special segments do not follow the above formats.
More information on segment names may be found in the Compiler and Linker
manuals.

Using the Link Map you can quickly and easily see which regions of memory your
project uses and how much memory your project uses. Also you can see if you
configured the Linker correctly to use only specific regions of memory.
Executable Summary
The executable summary gives the total memory usage for each of the various memory
areas, excluding dynamic memory requirements such as the stack.
Reference Map
The reference map shows which executable segments call other segments. This is
useful in determining if the linker correctly figured out such things as indirect function
calls.
Symbol Table
Every variable, function and code line are listed in the symbol table along with the
address they were located at and their type. This is very useful when using the
debugger as you can look up the location a variable is stored at then watch that
location during the simulation.
Project Call Tree (ST6 only)
The Project Call Tree is an analysis of the stack usage by the project. The ST6
supports only six stack levels and the linker makes an attempt to determine if the
project will go over the six level limit. This section indicates what the linker did to
work out the stack usage of the project.

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Getting Started with the Raisonance Development Kits
Errors and Warnings
The final piece of information given in the map file is a summary of the number of
warnings and errors that were generated by the linker. Note however that it does not
list the actual warnings and errors.

Note
Sometimes it will appear that a variable has been omitted from the symbol table. This
isn’t a bug, but an indication that the variable was optimized out and therefore is not
present in the .aof file. You cannot therefore watch that variable in the debugger.
If you need to see the variable then try declaring the variable as “volatile”. The volatile
keyword will instruct the Compiler to avoid performing optimizations on the variable.
volatile unsigned char foo;
Note however that using the volatile keyword will change the code generated and
therefore may not behave in quite the same way as the final version without the
volatile keyword.

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Chapter 5 Compiler Listing and Linker Map Files

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Getting Started with the Raisonance Development Kits

Chapter 6. Header Files
Each tools installation contains a set of pre-written header files that declare Special
Function Registers for many derivatives of the microcontroller family you are using.
Each header file is specific to a particular derivative, however it is easy to generate
your own header files if you find that one for the derivative you are using is not
included.
Follow the steps below to generate your own header file.
1. Find the header file of the device most similar to the one you are using.
Alternatively find the header file of the most basic derivative. For example for the
8051 it would be reg51.h.
Header files are stored in the INC folder in 8051 and XA installations and the INCST6
folder in ST6 installations.
2. Make a copy of it in the same folder and rename the new file to the name of the
derivative you are using, following the same naming format at the other header files.
3. Open the header file in RIDE or a text editor such as Notepad.
4. Using the table of SFRs from the datasheet of the device you are using, simply enter
the missing SFRs following the same declaration format:
at address sfr name;
for example on 8051s the SFR P0 is located at 0x80, so it is declared as:
at 0x80 sfr P0;
The 8051 and XA also allow declarations of individual bits in the bit-addressable
SFRs. They are declared using the following format:
at address sbit name;
where the address is the address of the SFR which contains the bit plus the bit position.

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Chapter 6 Header Files
For example:
Address
0x80
0x81
0x83

Corresponds to
Bit 0 in the SFR at 0x80
Bit 1 in the SFR at 0x80
Bit 3 in the SFR at 0x80
Table 6.1 SFR Bit Addresses

So bit 1 in the SFR at 0x80 would be declared as:
at 0x81 sbit FOO;
As you can see, it is quick and easy to generate your own header files.

Once generated you may include them in the C source code in the usual manner. For
example:
#include

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Getting Started with the Raisonance Development Kits

Chapter 7. Compiler
Changing the Compiler Settings in RIDE
With a project loaded into RIDE the Compiler options for the project as a whole may
be accessed by choosing Options | Project then expanding the tree for the Compiler
and clicking on the various sections. The following screenshot is for the 8051:

Once all the options have been set up accordingly click on OK to confirm them.
The Compiler options may also be set individually for each source file in the project:
•
•
•

In the Project window select the source file whose options you wish to change
Press the right mouse button.
From the pop-up menu choose Options | Local Options. A window will open
allowing you to change the Compiler options for that source file.

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Chapter 7 Compiler

8051 Compiler Options Overview
The following Compiler options are grouped by section, as listed in the Options
window.
Where there are two directives for an option, the first directive is the one used with the
option selected. The second directive is the one used when the option is not selected.
In some cases the lack of a directive selects the default setting, which is indicated by
(none).
Source
Option
ANSI C

80C51 Specific
Language
Extensions
‘struct/union/enum’
optional

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Description
Strictly ANSI C only allowed. No language extensions.
Directive: NOEXTEND
ANSI C plus language extensions allowed.
Directive: EXTEND
Allows the struct, union and enum keywords to be omitted
when declaring structures, unions and enumerators in certain
situations.
Directive: SUE_OPT
Table 7.1 8051 Compiler Source Settings

Getting Started with the Raisonance Development Kits
Floating Point
Option
No floating point

Description
No floating point variables are allowed in the
project.
Directive: FP(NOFLOAT)
IEEE: Standard
Allows single-precision floating point numbers
(IEEE-754) – little endian
Directive: FP(IEEE,STANDARD)
IEEE: Reversed (251 compatible) Allows single-precision floating point numbers
(IEEE-754) – big endian
Directive: FP(IEEE,FP251)
BCD: All types
Allows 32-bit, 48-bit and 56-bit floating point
numbers in BCD format.
Directive: FP(BCD,ALL)
BCD: “float” only
Allows 32-bit floating point numbers in BCD
format.
Directive: FP(BCD.FLOAT)
BCD: “double” only
Allows 48-bit floating-point numbers in BCD
format.
Directive: FP(BCD,DOUBLE)
BCD: “long double” only
Allows 56-bit floating-point numbers in BCD
format.
Directive: FP(BCD,LONG)
Table 7.2 8051 Compiler Floating Point Settings

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Chapter 7 Compiler
Code Generation
Option
Enable ANSI Integer
Promotion Rules

Stack Automatic
Variables

Initialize static
variables to zero

Generic

7
Unsigned characters

Description
If selected chars will be promoted to ints before
comparison. This does not generate optimal code on 8-bit
microcontrollers such as the 8051, but is included for ANSI
compliance.
Directive: IP/NOIP
With this option on all automatic variables will be located
on the stack rather than in fixed memory locations. The
result is reentrant but larger code.
Directive: AUTO/NOAUTO
Includes startup code to initialize non-initialized static
variables to zero. This is a safeguard that can be used
against uninitialized variables.
Directive: IS/NOIS
When selected all non-memory specific pointers are
generic pointers. When not selected, non-memory specific
pointers point to the default memory space for the current
memory model.
Directive: GENERIC/NOGENERIC
When selected chars are converted to unsigned chars.
Directive: UNSIGNEDCHAR/SIGNEDCHAR
Table 7.3 8051 Compiler Code Generation Settings

Note
With the generic option turned on the following pointer declaration results in a pointer
that can point to any memory space, however the code to manipulate the pointer is
large and involves library calls:
unsigned char *foo;
With the generic option turned off the same pointer declaration results in a pointer that
points to the default memory space for the current memory model (such as DATA in
the Small memory model), however generic pointers can still be declared using the
generic keyword, for example
unsigned char generic *foo;
This makes turning the generic option off the best setting to use, however be aware of
the effects.
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Getting Started with the Raisonance Development Kits
Defines
This section allows you to enter identifiers that are defined for such things as
conditional compilation.
Directive: DEFINE(text)
Listing
Option
Generate listing
Show lines omitted
from compilation
Display the contents
of the include files
Generate
Preprocessor listing
file
Append assembly
mnemonics list
Generate a list of
symbols
Insert form feeds at
the end of pages
Number of lines
printed per page
Number of characters
printed per line

Description
If selected a .lst listing file will be generated
Directive: PR(filename)/NOPR
If selected then the source code listing in the listing file will
include files that were not involved in the compilation
Directive: CO/NOCO
If selected then the contents of the include files are inserted
into the source code listing in the listing file
Directive: LC/(none)
If selected then a separate file will be generated showing
macro expansions
Directive: PP(filename)/(none)
If selected then the compiler generated assembly code will
be included in the listing file
Directive: CD/NOCD
If selected then a symbol table will be included in the
listing file
Directive: SB/NOSB
If selected then form feed control characters will be
inserted into the listing file
Directive: PL(lines)/(none)
Specifies how long a page is
Directive: PL(lines)
Specifies how wide a line is
Directive: PW(characters)
Table 7.4 8051 Compiler Listing Settings

Page 67

Chapter 7 Compiler
Object
Option
Generate an assembler
source file

Generate an object file

Debugging information –
no information
Debugging information –
Standard

Debugging information –
Extended
Debugging information –
Extended 1997 version

Generate interrupt vectors

Interval for interrupt
vectors
Offset for interrupt
vectors

Page 68

Description
The compiler will generate a .src file which is the
complete assembler equivalent of the C source code.
The .src file may be assembled by the assembler.
Directive: SRC
The compiler will generate a relocatable object file that
make be linked with other object files
Directive: OBJECT(filename)
No debugging information will be included in the
object file.
Directive: NODB
Includes basic debugging information in the object file,
compatible with the original Intel OMF-51
specification.
Directive: DB
Includes extended debugging information in the object
file, including type information.
Directive: OE(1)
Includes yet more debugging information in the object
file, including the temporary locations of automatic
variables when located in registers.
Directive: OE(2)
The compiler will generate interrupt vectors
automatically for interrupt functions
Directive: INTVECTOR(offset)/NOINTVECTOR
The number of bytes between interrupt vectors
Directive: INTERVAL(bytes)
The vector for interrupt zero will be located at this
code address + 3
Directive: INTVECTOR(offset)
Table 7.5 8051 Compiler Object Settings

Getting Started with the Raisonance Development Kits
Memory Model
Option
Tiny
Small
Compact
Large
Huge
Use external stack

Component with
XRAM
Advanced features –
none
Advanced features –
Philips component
with dual DPTR
Advanced features –
Dual DPTR
Dallas/AMD
Advanced features –
Dual DPTR Atmel
80C517

Use additional data
pointers

Description
Selects the Tiny memory model
Directive: TINY
Selects the Small memory model
Directive: SMALL
Selects the Compact memory model
Directive: COMPACT
Selects the Large memory model
Directive: LARGE
Selects the Huge memory model
Directive: HUGE
Uses a simulated external stack, rather than the system
stack for a reentrant stack
Directive: EXTSTK/(none)
Ensures the correct startup code is used for devices with onchip XRAM.
Directive: INTXD/(none)
The compiler will use library that use a single DPTR and
no arithmetic units
Directive: (none)
For certain library functions the compiler will use the
Philips dual DPTR scheme
Directive: PHILIPSDDPTR
For certain library functions the compiler will use the
Dallas/AMD dual DPTR scheme
Directive: MODAMD(DP2)
For certain library functions the compiler will use the
Atmel dual DPTR scheme
Directive: MODATM
Allows the compiler to use the additional data pointers
and/or arithmetic processor of the 80C517 for certain
library function, depending on which 517 options are
selected.
For certain library functions the compiler will use the
80C517 multiple DPTR scheme
Directive:
MOD517(DP8,otherparam)/MOD517(NODP8,otherparam
)
Page 69

Chapter 7 Compiler
Use the arithmetic
processor

For certain library functions the compiler will use the
80C517 arithmetic processor
Directive:
MOD517(otherparam,AU)/MOD517(otherparam,NOAU)
Table 7.6 8051 Compiler Memory Model Settings

Note
The memory models affect the compiler in several ways. The following table is a
summary of the memory models
Small and Large are the preferred memory models to use. The 8051 supports up to 256
bytes of internal RAM so using the Small memory model is not always possible. In
those situations the Large memory model should be used.

Memory Model
Tiny

Default Data Space
DATA

Small

DATA

Compact

PDATA

Large

XDATA

Huge

PDATA

Page 70

Description
Suitable for small applications.
Maximum program size is 2k.
Best memory model for most
applications.
Retained for backwards compatibility
with preexisting applications.
Retained for backwards compatibility
with preexisting applications.
A simulated external stack is used for
every stack operation giving a larger
stack size however execution is slow.
Table 7.7 8051 Compiler Memory Models

Getting Started with the Raisonance Development Kits
Registers
Option
Use absolute register
address for R0-R7

Pass function arguments
in registers
Registerbank

Description
Allows the compiler to use absolute register addressing
for the register, generating more efficient but
registerbank dependant code
Directive: AREGS/NOAREGS
Allows function arguments to be passed in registers
therefore reducing memory requirements
Directive: REGPARMS/NOREGPARMS
Selects which registerbank to use for the functions
Directive: RB(banknumber)
Table 7.8 8051 Compiler Register Settings

Optimizer
Option
Optimize for tight code

Optimize for fast code

Optimizer level

Generate post-optimizing
information

Description
The optimizer will favor generating smaller code over
faster code
Directive: OT(otherparam, SIZE)
The optimizer will favor generating faster code over
smaller code
Directive: OT(otherparam, SPEED)
The level at which the optimizer will operate. The
higher the level the more optimizations are performed
Directive: OT(level, otherparam)
This option generates information for the global
optimizer.
Directive: POSTOPT/(none)
Table 7.9 8051 Compiler Optimizer Settings

Page 71

Chapter 7 Compiler
Messages
Option
Warning level

Stop after n errors

Stop after n
warnings

Page 72

Description
The compiler warnings are grouped into levels, with the higher
levels containing all the warnings in the lower levels. This
option indicates which levels of warnings you want the
compiler to generate
Directive: WL(level)
The number of errors after which the compiler should abandon
compilation
Directive: MAXERR(errornum)
The number of warnings after which the compiler should
abandon compilation
Directive: MAXWAR(warningnum)
Table 7.10 8051 Compiler Messages Settings

Getting Started with the Raisonance Development Kits

XA Compiler Options Overview
The following Compiler options are grouped by section, as listed in the Options
window.
Where there are two directives for an option, the first directive is the one used with the
option selected. The second directive is the one used when the option is not selected.
In some cases the lack of a directive selects the default setting, which is indicated by
(none).
Source
Option
ANSI C
XA Specific Language
Extensions
‘struct/union/enum’
optional

Description
Strictly ANSI C only allowed. No language extensions.
Directive: NOEXTEND
ANSI C plus language extensions allowed.
Directive: EXTEND
Allows the struct, union and enum keywords to be omitted
when declaring structures, unions and enumerators in
certain situations.
Directive: SUE_OPT
Table 7.11 XA Compiler Source Settings

Floating Point
Option
No floating point
IEEE: Standard

Description
No floating point variables are allowed in the project.
Directive: FP(NOFLOAT)
Allows single-precision floating point numbers (IEEE-754) –
little endian
Directive: FP(IEEE,STANDARD)
Table 7.12 XA Compiler Floating Point Settings

Page 73

Chapter 7 Compiler
Code Generation
Option
Enable ANSI Integer
Promotion Rules
Initialize static
variables to zero

Generic

Unsigned characters

Far access allowed

Load ES on far data
access

Load CS on far code
access

Save segment
registers in interrupt
handlers

Page 74

Description
If selected chars will be promoted to ints before
comparison.
Directive: IP/NOIP
Includes startup code to initialize non-initialized static
variables to zero. This is a safeguard that can be used
against uninitialized variables.
Directive: IS/NOIS
When selected all non-memory specific pointers are
generic pointers. When not selected, non-memory specific
pointers point to the default memory space for the current
memory model.
Directive: GENERIC/NOGENERIC
When selected chars are converted to unsigned chars.
Directive: UNSIGNEDCHAR/SIGNEDCHAR
Allows access to far data in page zero mode when using the
SmartXA.
Directive:
FARDATAALLOWED/FARDATANOTALLOWED
When selected the ES register is reloaded before every
access to far data. Turn this option off if you wish to set up
and maintain the ES register manually.
Directive: LOADES/NOLOADES
When selected the CS register is reloaded before every
access to far code. Turn this option off if you wish to set up
and maintain the CS register manually.
Directive: LOADCS/NOLOADCS
When selected the CS and ES registers are saved and
restored on the entry and exit of interrupt service routines
Directive: SAVESEG/NOSAVESEG
Table 7.13 XA Compiler Code Generation Settings

Getting Started with the Raisonance Development Kits

Note
If the LOADCS and LOADES directives are being used the Compiler will
automatically set up the CS and ES registers before every far access. In addition the
relevant bit in the SSEL register will be set and cleared before and after every far
access. This results in inefficient code.
There are two steps that can be taken to remove both inefficiencies:
1. Use NOLOADES and NOLOADCS and set up the ES and CS registers
manually. This is most suitable when only one far segment is being used.
2. Use SSELINIT to initialize the SSEL register manually. The Compiler will
then use only the registers whose corresponding bits in the SSEL register are set for far
accesses. The other registers will be used for near accesses. For example:
SSELINIT(0x04)
Results in R2 being used for far accesses, and the other registers being used for near
accesses.
Defines
This section allows you to enter identifiers that are defined for such things as
conditional compilation.
Directive: DEFINE(text)
Page 75

Chapter 7 Compiler
Listing
Option
Generate listing
Show lines omitted
from compilation
Display the contents
of the include files
Generate
Preprocessor listing
file
Append assembly
mnemonics list

Generate a list of
symbols
Insert form feeds at
the end of pages
Number of lines
printed per page
Number of characters
printed per line

Page 76

Getting Started with the Raisonance Development Kits
Object
Option
Generate an assembler
source file

Generate an object file

Include debugging
information
Include variable type and
definition information

Page 77

Chapter 7 Compiler
Memory Model
Option
Tiny
Small
Compact
Medium
Large
Huge
Functions in system mode

7
Functions in user mode

Functions in generic mode

Use extended register set

Page 78

Description
Selects the Tiny memory model
Directive: TINY
Selects the Small memory model
Directive: SMALL
Selects the Compact memory model
Directive: COMPACT
Selects the Medium memory model
Directive: MEDIUM
Selects the Large memory model
Directive: LARGE
Selects the Huge memory model
Directive: HUGE
Indicates that the functions will execute in system
mode – only of use to SmartXA users when using an
RTOS
Directive: SYSTEMFCT
Indicates that the functions will execute in user mode
– only of use to SmartXA users when using an RTOS
Directive: USERFCT
Indicates that the functions will execute in a
combination of user and system modes – only of use
to SmartXA users when using an RTOS
Directive: GENERICFCT
Enables the compiler to generate code using registers
R8 to R15.
Directive: EXTREGS/NOEXTREGS
Table 7.16 XA Compiler Memory Model Settings

Getting Started with the Raisonance Development Kits

Note
The memory models affect the compiler is several ways. The following table is a
summary of the memory models
Memory Model
Tiny (page 0)

Default Data
Space
DATA

Small (page 0)

DATA

Compact (non page 0)
Medium (non page 0)
Large (non page 0)

DATA
IDATA
IDATA

Huge (non page 0)

Description
24-bit addressing is not supported.
Maximum 32k of Code space and 32k of
Data space
24-bit addressing is not supported.
Maximum of 64k of Code space and 64k
of Data space
All addressing modes are supported.
All addressing modes are supported.
All addressing modes are supported.
Pointers default to 24-bit addressing.
The Huge memory model is currently not
implemented.
Table 7.17 XA Compiler Memory Models

Optimizer
Option
Optimize for tight code

Optimize for fast code

Optimizer level

Page 79

Chapter 7 Compiler
Messages
Option
Warning level

Stop after n errors

Stop after n
warnings

Page 80

Getting Started with the Raisonance Development Kits

ST6 Compiler Options Overview
The following Compiler options are grouped by section, as listed in the Options
window.
Where there are two directives for an option, the first directive is the one used with the
option selected. The second directive is the one used when the option is not selected.
In some cases the lack of a directive selects the default setting, which is indicated by
(none).
Source
Option
‘struct/union/enum’
optional

Description
Allows the struct, union and enum keywords to be omitted
when declaring structures, unions and enumerators in certain
situations.
Directive: SUE_OPT
Table 7.20 ST6 Compiler Source Settings

Code Generation
Option
Enable ANSI
Integer
Promotion Rules
Initialize static
variables to zero

Generic

Unsigned
characters
Use DRWR
copy

Description
If selected chars will be promoted to ints before comparison.
This does not generate optimal code on 8-bit microcontrollers
such as the ST6, but is included for ANSI compliance.
Directive: IP/NOIP
Includes startup code to initialize non-initialized static variables
to zero. This is a safeguard that can be used against uninitialized
variables.
Directive: IS/NOIS
When selected all non-memory specific pointers are generic
pointers. When not selected, non-memory specific pointers
point to the default memory space for the current memory
model.
Directive: GENERIC/NOGENERIC
When selected chars are converted to unsigned chars.
Directive: UNSIGNEDCHAR/SIGNEDCHAR
Instructs the compiler to make a copy of the DRWR register in
DRWRCOPY just before the register contents are changed.
Directive: DRWRCOPY/(none)
Table 7.21 ST6 Compiler Code Generation Settings
Page 81

Chapter 7 Compiler

Note
With the generic option turned on the following pointer declaration results in a pointer
that can point to any memory space, however the code to manipulate the pointer is
large and involves library calls:
unsigned char *foo;
With the generic option turned off the same pointer declaration results in a pointer that
points to the default memory space for the current memory model, however generic
pointers can still be declared using the generic keyword, for example
unsigned char generic *foo;
This makes turning the generic option off the best setting to use, however be aware of
the effects.
Defines

This section allows you to enter identifiers that are defined for such things as
conditional compilation.
Directive: DEFINE(text)

Page 82

Getting Started with the Raisonance Development Kits
Listing
Option
Generate listing
Show lines omitted
from compilation
Display the contents
of the include files
Generate
Preprocessor listing
file
Append assembly
mnemonics list
Generate a list of
symbols
Insert form feeds at
the end of pages
Number of lines
printed per page
Number of characters
printed per line

Page 83

Chapter 7 Compiler
Object
Option
Generate an assembler
source file

Generate an object file

Include debugging
information

Memory Model

Option
Small
Large

Description
Selects the Small memory model
Directive: SMALL
Selects the Large memory model
Directive: LARGE
Table 7.24 ST6 Compiler Memory Model Settings

Note
The memory models affect the compiler is several ways. The following table is a
summary of the memory models
Memory Model
Small
Large

Page 84

Description
No bank switching. Maximum program size of 4k. Maximum
128 bytes of DATA.
Bank switching supported. Maximum program size of 8k.
Maximum 512 bytes of RAM + EEPROM.
Table 7.25 ST6 Compiler Memory Models

Getting Started with the Raisonance Development Kits
Optimizer
Option
Optimize for tight code

Optimize for fast code

Optimizer level

Messages
Option
Warning level

Stop after n errors

Stop after n
warnings

Page 85

Chapter 7 Compiler

Compiler Command Line Syntax
All three compilers have the same command line syntax:
toolexename sourcefile [directiveslist]
toolexename:
one of: RC51, RCXA, RCST6
sourcefile:
an absolute or relative path to a C source file
directiveslist:
a space separated list of directives. The directives may be listed in any order.

If each directive is not explicitly listed then defaults will be used for the missing
directives.
Command line examples:
RC51 test.c PR(test.lst) OBJECT(test.obj) CD SB
RCXA C:\work\xa.c USERFCT EXTSTK SAVESEG
RCST6 ..\foo.c DRWRCOPY
RC51 bar.c

Page 86

Getting Started with the Raisonance Development Kits

Chapter 8. Assembler
Changing the Assembler Settings in RIDE
With a project loaded into RIDE the Assembler options for the project as a whole may
accessed by choosing Options | Project then expanding the tree for the Assembler and
clicking on the various sections. The following screenshot is for the 8051:

8
Once all the options have been set up accordingly click on OK to confirm them.
The Assembler options may also be set individually for each source file in the project:
•
•
•

Page 87

Chapter 8 Assembler

8051 Assembler Options Overview
The following Assembler options are grouped by section, as listed in the Options
window.
Where there are two directives for an option, the first directive is the one used with the
option selected. The second directive is the one used when the option is not selected.
In some cases the lack of a directive selects the default setting, which is indicated by
(none).
Source
Option
Define symbols for the
8051 function registers

Accept Intel MPL

ASM-51 Syntax

Raisonance Syntax

Description
When selected a standard 8051 set of Special Function
Registers will be defined, thus avoiding having to define
them in the assembler file
Directive: MOD51/NOMOD51
When selected the assembler will accept the Intel Macro
programming language.
Directive: MACRO(MPL)/(none)
When selected the assembler will accept the Intel ASM51 assembler syntax.
Directive: SYNTAX(ASM51)
When selected the assembler will accept the syntax of
older Raisonance assemblers, such as EMA-51.
Directive: SYNTAX(EMA)
Table 8.1 8051 Assembler Source Settings

Set
By entering text with the format:
symbol [ = value] [, symbol [ = value]]
values can be assigned to symbols. If no value is specified then the symbol is assigned
the value 0xFFFF.
Directive: SET(text)

Page 88

Getting Started with the Raisonance Development Kits
Listing
Option
Generate Listing
Include the program
source text
Display the contents
of the include files
Show unassembled
lines of conditional
constructs
Expand assembly
instructions of macros
Generate a table of the
symbols
Insert form feeds at
the end of pages
Generate a cross
reference table of the
symbols
Number of characters
printed per line
Number of lines
printed per page

Description
When selected the assembler will generate a .lst listing file
Directive: PRINT(filename)/NOPRINT
When selected the assembler source code will be included
in the listing file
Directive: LIST/NOLIST
When selected the contents of include files will be
inserted into the source code listing in the listing file
Directive: LC/(none)
Lines that were not assembled will be included in the
source code listing when this option is selected
Directive: COND/NOCOND
When selected assembly code inside macro definitions
will appear in the listing file
Directive: GEN/NOGEN
When selected a symbol table will be included in the
listing file
Directive: SB/NOSB
When selected form feed control characters will be
inserted into the listing file at the end of every page
Directive: EJECT/(none)
Includes a cross reference table of all the symbols in the
listing file
Directive: XR/NOXR
Specifies the page width of the listing file in characters
Directive: PW(characters)
Specifies the page length used in the listing file in lines
Directive: PL(lines)
Table 8.2 8051 Assembler Listing Settings

Page 89

Chapter 8 Assembler
Object
Option
Generate an
object file
Generate post
optimizing
information
Debugging
information –
no information
Debugging
information –
standard
Debugging
information –
extended
Register banks
used

Page 90

Description
When selected the assembler will generate a relocatable object file
Directive: OBJECT(filename)/NOOBJECT
When selected the assembler will generate information used in
global optimization
Directive: POSTOPT/(none)
Selection of this option will omit debugging information from the
object file
Directive: (none)
This option includes basic debugging information in the object file
Directive: DB
This option includes additional debugging information in the
object file
Directive: OE
This section of the options allow you to select which register
banks are to be reserved by the assembler.
Directive: RB(registerbank[,registerbank])
Table 8.3 8051 Assembler Object Settings

Getting Started with the Raisonance Development Kits

XA Assembler Options Overview
The following Assembler options are grouped by section, as listed in the Options
window.
Where there are two directives for an option, the first directive is the one used with the
option selected. The second directive is the one used when the option is not selected.
In some cases the lack of a directive selects the default setting, which is indicated by
(none).
Source
Option
Define symbols for the
XA function registers

Accept Intel MPL

Always set code labels
on even addresses
Use extended register
set R8 – R15

Description
When selected a standard XA set of Special Function
Registers will be defined, thus avoiding having to define
them in the assembler file
Directive: MODXA/NOMO
When selected the assembler will accept the Intel Macro
programming language.
Directive: MACRO(MPL)/(none)
When selected the assembler will ensure that code labels
are word-aligned.
Directive: ECL/NOECL
Allows the use of registers R8 – R15 when selected.
Directive: EXTREGS/NOEXTREGS
Table 8.4 XA Assembler Source Settings

Page 91

Chapter 8 Assembler
Listing
Option
Generate Listing
Include the program
source text
Display the contents
of the include files
Show unassembled
lines of conditional
constructs
Expand assembly
instructions of macros
Generate a table of the
symbols

Insert form feeds at
the end of pages
Generate a cross
reference table of the
symbols
Number of characters
printed per line
Number of lines
printed per page

Page 92

Getting Started with the Raisonance Development Kits
Object
Option
Generate an
object file
Include
Debugging
information
Register banks
used

Description
When selected the assembler will generate a relocatable object
file
Directive: OBJECT(filename)/NOOBJECT
This option includes debugging information in the object file
Directive: DB/NODB
This option is not used by the assembler and is only included for
compatibility with the 8051 toolset.
Table 8.6 XA Assembler Object Settings

Page 93

Chapter 8 Assembler

ST6 Assembler Options Overview
The following Assembler options are grouped by section, as listed in the Options
window.
Where there are two directives for an option, the first directive is the one used with the
option selected. The second directive is the one used when the option is not selected.
In some cases the lack of a directive selects the default setting, which is indicated by
(none).
Source
Option
Define symbols for the
ST6 function registers

Use AST6 syntax

Description
When selected a standard ST6 set of Special Function
Registers will be defined, thus avoiding having to define
them in the assembler file
Directive: MODST6/NOMO
When selected the assembler will accept files written for
the ST Microelectronics AST6 assembler.
Directive: PREPROST/(none)
Table 8.7 ST6 Assembler Source Settings

Page 94

Getting Started with the Raisonance Development Kits
Listing
Option
Generate Listing
Include the program
source text
Display the contents
of the include files
Show unassembled
lines of conditional
constructs
Expand assembly
instructions of
macros
Generate a table of
the symbols
Insert form feeds at
the end of pages
Generate a cross
reference table of the
symbols
Number of characters
printed per line
Number of lines
printed per page

Description
When selected the assembler will generate a .lst listing file
Directive: PRINT(filename)/NOPRINT
When selected the assembler source code will be included
in the listing file
Directive: LIST/NOLIST
When selected the contents of include files will be inserted
into the source code listing in the listing file
Directive: LC/(none)
Lines that were not assembled will be included in the
source code listing when this option is selected
Directive: COND/NOCOND
When selected assembly code inside macro definitions will
appear in the listing file
Directive: GEN/NOGEN
When selected a symbol table will be included in the listing
file
Directive: SB/NOSB
When selected form feed control characters will be inserted
into the listing file at the end of every page
Directive: EJECT/(none)
Includes a cross reference table of all the symbols in the
listing file
Directive: XR/NOXR
Specifies the page width of the listing file in characters
Directive: PW(characters)
Specifies the page length used in the listing file in lines
Directive: PL(lines)
Table 8.8 ST6 Assembler Listing Settings

Page 95

Chapter 8 Assembler
Object
Option
Generate an
object file
Include
Debug
information
ROM fill
value

Page 96

Description
When selected the assembler will generate a relocatable object file
Directive: OBJECT(filename)/NOOBJECT
This option includes basic debugging information in the object file
Directive: DB/NODB
The ROM area not used by code or constants is filled with the ROM
fill value. This is useful in ensuring the ROM area has a particular
checksum.
Directive: ROMFILL(value)
Table 8.9 ST6 Assembler Object Settings

Getting Started with the Raisonance Development Kits

Assembler Command Line Syntax
All three assemblers have the same command line syntax:
toolexename sourcefile [directiveslist]
toolexename:
one of: MA51, MAXA, MAST6
sourcefile:
an absolute or relative path to an assembler source file
directiveslist:
a space separated list of directives. The directives may be listed in any order.
If each directive is not explicitly listed then defaults will be used for the missing
directives.

Command line examples:
MA51 test.a51 PR(test.lst) OBJECT(test.obj) SB
MAXA C:\work\xa.axa NOMO XR
RCST6 ..\foo.st6 ROMFILL(0xFF)
MA51 bar.a51

Page 97

Chapter 8 Assembler

Page 98

Getting Started with the Raisonance Development Kits

Chapter 9. Linker
Changing the Linker Settings in RIDE
With a project loaded into RIDE the Linker options for the project as a whole may be
accessed by choosing Options | Project then expanding the tree for the Linker and
clicking on the various sections. The following screenshot is for the 8051:

9
Once all the options have been set up accordingly click on OK to confirm them.

Page 99

Chapter 9 Linker

8051 Linker Options Overview
The following Linker options are grouped by section, as listed in the Options window.
Where there are two directives for an option, the first directive is the one used with the
option selected. The second directive is the one used when the option is not selected.
In some cases the lack of a directive selects the default setting, which is indicated by
(none).
Linker
Option
Libraries – RC51x.LIB

Ram size
Initialized Ram size
(s)printf buffer size
External stack size

Initial value of timer 1

Generate an Intel Hex file
Generate a binary file
Include debug info.

Starting addresses – Code

Starting addresses - Xdata

Starting addresses - Idata
Page 100

Description
When selected the libraries supplied with the toolset
will be used.
Directive: (none)/NLIB
Specifies the amount of internal RAM on the device
Directive: RS(size)
Specifies the amount of internal RAM to initialize to 0
Directive: RSI(size)
Specifies the buffer size used to construct strings in
printf and sprintf
When using an external reentrant stack this options
specifies the size of the stack.
In the startup code timer 1 is initialized to be used as a
baud rate generator. This option allows the initial value
to be changed therefore changing the baud rate.
When selected an Intel Hex file will be generated.
When selected a raw binary file will be generated.
Debugging information will be included in the absolute
object file when this option is selected.
Directive: DL + DP + DS/NODL + NODP + NODS
Specifies the starting address for Code segments. Note
that it does not specify a starting address for the reset
vector or interrupt vectors.
Directive: CODE(address)
Specifies the starting address for the external RAM
(Xdata) segments.
Directive: XDATA(address)
Specifies the starting address of the indirect internal
RAM (Idata) segments.

Getting Started with the Raisonance Development Kits

Starting addresses - Data

Starting addresses - Bit

Absolute segments offset
- code

Directive: IDATA(address)
Specifies the starting address of the direct internal
RAM (Data) segments. Note that it does not affect the
location of the registerbanks.
Directive: DATA(address)
Specifies the starting address of the internal bitaddressable area (Bdata).
Directive: BDATA(address)
Specifies an offset to apply to absolute code segments
Directive: ABSCODEOFFS(offset)
Table 9.1 8051 Linker Settings

Note
Sometimes it is undesirable to have the project code starting at 0x0000 and another
address is required. For example if two separate projects must be loaded into the same
ROM at the same time.
To relocate all code to a specific address two steps must be performed:
1. Specify the address in the Starting addresses – Code box
2. Specify the address in the Absolute segments offset – code box
Always remember to check the link map of module table in the map file to verify that
the memory map of your project is correct.
Listing
Option
Include the cross
references table XREF
Insert form feeds at the
end of pages
Number of lines printed
per page
Number of characters
printed per line

Description
When selected a cross reference table will be included in
the listing file.
Directive: IX/NOIX
When selected form feed control characters will be
inserted into the listing file.
Directive: EJECT/(none)
Specifies the page length in lines.
Directive: PL(lines)
Specifies the page width in characters.
Directive: PW(lines)
Table 9.2 8051 Linker Listing Settings

Page 101

Chapter 9 Linker
Bank Switching
Option
Use bank switching
mode
Maximum number of
banks
Starting address of the
code banking
Ending address of the
code banking
Use external stack
Use the macro
definition
Evaluate the expression
for the currently
selected bank
Modules Tab

Description
When selected the linker will use bank switching to
provide more than 64k of code space
Directive: BANKAREA(start, end)
The maximum number of code banks used in the project
(must be a power of 2)
The base address of the code banks
Directive: BANKAREA(address, otherparam)
The top address of the code banks
Directive: BANKAREA(otherparam, address)
When selected allows functions to be reentrant.
Directive: BM(SMA)/BM(PLM)
The macro in the box is used to switch code banks. A
custom macro may be entered into the box.
The symbol that represents the currently selected code
bank, and is used in the macro definition.
The section under the Modules tab may be used to select
which code banks to place various object files and
libraries into, by double-clicking on each one. Note that
object files are only listed if the project has previously
been built.
Directive: BANKbanknumber{objectfile}
Table 9.3 8051 Linker Bank Switching Settings

Note
Code Banking is an involved and complex area of the linker. Please refer to the Linker
manual for full and detailed information on Code Banking.

Page 102

Getting Started with the Raisonance Development Kits
Flash
Option
Use Flash mode/Start
Address

FLS file – locked mode

Reserved data space
Reserved bit space
Reserved Bdata space

Object files to be in
Flash

Description
Activate the Flash mode. Specify the border address
between the ROM part (lowest bound) and the Flash part
(highest bound)
Directive: FLASH(address)
Relocate/Link modules of the Flash Part, and keep intact
the ROM part.
Directive: REFLASH
Reserve a gap of n bytes for future DATA storage needs.
Directive: RESERVE(DATA, n)
Reserve a gap of n bytes for future BIT storage needs.
Directive: RESERVE(BIT, n)
Reserve a gap of n bytes for future BDATA storage
needs.
Directive: RESERVE(BDATA, n)
Select the modules to be located in the Flash.
Directive: FLASH(otherparam, objectfilelist)
Table 9.4 8051 Linker Flash Settings

Page 103

Chapter 9 Linker
Kernel
Option
Use KR-51 Kernel
Kernel Model – KRTiny
Kernel Model - KRStandard
Kernel Model - KRHuge
Debug
Semaphores
Time – use the
automatic definitions
CPU cycles/tick
Dividers – Group 1
Dividers – Group 2
Dividers – Group 3

Page 104

Description
When selected the KR-51 RTOS will be used
Selects the Tiny model – up to 8 tasks
Selects the Standard model – up to 32 tasks with Xdata
required.
Selects the Huge model – up to 256 tasks with Xdata
required.
When selected the extended debug libraries will be used.
Select this option if semaphores are used.
When selected the clock and dividers settings in the
window are used, otherwise the same settings must be
provided in an assembly file.
Specifies the relationship between the CPU clock cycles
and the RTOS tick rate.
The number of ticks in a single group 1 tick.
The number of group 1 ticks in a single group 2 tick
The numberof group 2 ticks in a single group 3 tick
Table 9.5 8051 Linker Kernel Settings

Getting Started with the Raisonance Development Kits
ROM-Monitor
Option
Use the ROM-Monitor
Communications - Standard
UART
Communications - External
UART
Communications - ROMMonitor
Communications –
Communication baud rate
Dynamically modifiable code

XEVA board
Von Neuman board

Description
When selected the ROM Monitor will be used to
provide in-system debugging.
Select to use the first internal UART of the
microcontroller for the monitor to communicate
with RIDE
Select to use an external UART for the monitor to
communicate with RIDE
Select to use a customized method for the monitor
to communicate with RIDE
Specify the baud rate of the communications
between RIDE and the monitor
Select if the code is located in RAM where it may
be modified. This is required if the use of
breakpoints is desired.
Select if the board is a Raisonance XEVA board
Select if the board is a Von Neuman board (code
space is mapped to external RAM).
Table 9.6 8051 Linker ROM-Monitor Settings

More
Linker directives may be entered into the More box in the form of a space separated
list.
Note however that you should not specify a directive that will already be specified by
selection or non-selection of a linker option in one of the sections previously
described.

Page 105

Chapter 9 Linker

XA Linker Options Overview
The following Linker options are grouped by section, as listed in the Options window.
Where there are two directives for an option, the first directive is the one used with the
option selected. The second directive is the one used when the option is not selected.
In some cases the lack of a directive selects the default setting, which is indicated by
(none).
Linker
Option
Libraries –
RCXAx.LIB
BTR initialization
needed
BTR init value
Ram size
Initialized Ram size

User stack size
System stack size
Buffer size for printf
Initial value of timer 1

Generate an Intel Hex
file
Generate a binary file
Include debug info.

Generate crossref table
file
Page 106

Description
When selected the libraries supplied with the toolset will
be used.
Directive: (none)/NLIB
This option should be selected if the Bus Timing Register
needs to be initialized before execution.
The value to initialize the Bus Timing Register to.
Directive: BTRINIT(value)
Specifies the amount of internal RAM on the device
Directive: RS(size)
Specifies the amount of internal RAM to initialize to 0
Directive: RSI(size)
Specifies the size of the user stack
Directive: USS(size)/NOUSS
Specifies the size of the system stack
Directive: SSS(size)/NOSSS
Specifies the buffer size used to construct strings by printf
and sprintf
In the startup code timer 1 is initialized to be used as a
baud rate generated. This option allows the initial value to
be changed therefore changing the baud rate.
When selected an Intel Hex file will be generated.
When selected a raw binary file will be generated.
Debugging information will be included in the absolute
object file when this option is selected.
Directive: DL + DP + DS/NODL + NODP + NODS
When selected a cross-reference table is included in the
map file.

Getting Started with the Raisonance Development Kits
file
Generate an ABS file
Manage stacks
System overflow

User overflow

System location
Listing – lines/page
Listing –
characters/line

map file.
Directive: IX/NOIX
When selected an ABS format file compatible with some
emulators will be generated.
Enables the stack overflows and the system stack location
to be controlled.
Specifies the number of bytes to reserve below the system
stack overflow point.
Directive: SSTKOV(bytes)
Specifies the number of bytes to reserve below the user
stack overflow point.
Directive: USTKOV(bytes)
Specifies the location of the system stack.
Directive: SSTACK(address)
Specifies the page length of the map file in lines
Directive: PL(lines)
Specifies the page width of the map file in characters
Directive: PW(characters)
Table 9.7 XA Linker Settings

Relocation
Option
Near code relocation –
base address
Far code relocation –
base address
Near data relocation –
Near data/idata segment
Near data relocation Idata base address
Near data relocation –
data base address
Far data relocation –
Idata base address
Far data relocation –
Data base address

Description
Specifies the starting address for near code segments
Directive: CO(address)
Specifies the starting address for far code segments
Directive: FARCODE(address)
Specifies the segment to located the near data and idata
into.
Directive: NDTSEG(segment)
Specifies the starting address for near idata segments
Directive: NID(address)
Specifies the starting address for near data segments
Directive: NDT(address)
Specifies the starting address for far idata segments
Directive: FID(address)
Specifies the starting address for far data segments
Directive: FDT(address)
Table 9.8 XA Linker Relocation Settings
Page 107

Chapter 9 Linker
Kernel
Option
Use KRXA Kernel
Debug
Semaphores
Use the automatic
definitions
CPU cycles/tick
Dividers – group 1
Dividers – group 2
Dividers – group 3

Description
When selected the KR-XA RTOS will be used
When selected the extended debug libraries will be used.
Select this option if semaphores are used.
When selected the clock and dividers settings in the window
are used, otherwise the same settings must be provided in an
assembly file.
Specifies the relationship between the CPU clock cycles and
the RTOS tick rate.
The number of ticks in a single group 1 tick.
The number of group 1 ticks in a single group 2 tick
The numberof group 2 ticks in a single group 3 tick
Table 9.9 XA Linker Kernel Settings

ROM-Monitor

Option
Use the ROMMonitor
Communications Standard UART 0
Communications –
Standard UART 1
Communications –
External UART
Communications –
Communication
baud rate
Dynamically
modifiable code
XEVA board
Von Neuman
board

Page 108

Description
When selected the ROM Monitor will be used to provide insystem debugging.
Select to use the first internal UART of the microcontroller
for the monitor to communicate with RIDE
Select to use the second internal UART of the microcontroller
for the monitor to communicate with RIDE
Select to use an external UART for the monitor to
communicate with RIDE
Specify the baud rate of the communications between RIDE
and the monitor
Select if the code is located in RAM where it may be
modified. This is required if the use of breakpoints is desired.
Select if the board is a Raisonance XEVA board
Select if the board is a Von Neuman board (code space is
mapped to external RAM).
Table 9.10 XA Linker ROM-Monitor Settings

Page 109

Chapter 9 Linker

ST6 Linker Options Overview
The following Linker options are grouped by section, as listed in the Options window.
Where there are two directives for an option, the first directive is the one used with the
option selected. The second directive is the one used when the option is not selected.
In some cases the lack of a directive selects the default setting, which is indicated by
(none).
Linker
Option
Generate a Hex file
Generate a binary file
Include debug
information
ROM – Fill unused areas

ROM – Fill reserved
areas

Use RCST6x.LIB library
files
Initialized static RAM
size
Printf argument max size

Description
When selected an Intel Hex file will be generated
When selected a raw binary file will be generated
Select to include debugging information in the absolute
object file
Directive: DL + DP + DS/NODL + NODP + NODS
When selected enter a value to fill the unused areas of
ROM with.
Directive: ROMFILLUNUSEDVALUE(value)
When selected enter a value to fill the reserved areas of
ROM with.
Directive: ROMFILLRESERVEDVALUE(value)
Select to use the libraries that are supplied with the
toolset.
Directive: (none)/NLIB
Number of bytes to initialize in the static RAM
Directive: RAMSIZEINIT(bytes)
Maximum printf argument size in bytes
Directive: PRSTATICSIZE(bytes)
Table 9.11 ST6 Linker Settings

Bank Switching
This section allows the code bank for specific object and library files to be selected.
Double-click on a file to select the code bank.

Page 110

Getting Started with the Raisonance Development Kits
More
Linker directives may be entered into the More box in the form of a space separated
list.
Note however that you should not specify a directive that will already be specified by
selection or non-selection of a linker option in one of the sections previously
described.
Listing
Option
Include the cross
reference table XREF
Insert form feeds at the
end of pages
Number of lines printed
per page
Number of characters
printed per line
Print call tree
Print module mapping

Description
When selected a cross reference table will be included in
the map file.
Directive: IX/NOIX
When selected form feed control characters will be
inserted into the map file.
Directive: EJECT/(none)
Specifies the page length of the map file in lines
Directive: PL(lines)
Specifies the page width of the map file in characters.
Directive: PW(characters)
When selected includes the call tree in the map file.
Directive: CALLTREE/NOCALLTREE
When selected includes the module mapping information
in the map file
Directive: MODULEMAP/NOMODULEMAP
Table 9.12 ST6 Linker Listing Settings

Page 111

Chapter 9 Linker

Linker Command Line Syntax
All three linkers have the same command line syntax:
toolexename objectfilelist [directiveslist]
toolexename:
one of: LX51, RLXA, RLST6
objectfilelist:
a comma separated list of object files and library files to be linked together
directiveslist:
a space separated list of directives. The directives may be listed in any order.
If each directive is not explicitly listed then defaults will be used for the missing
directives.
Command line examples:
LX51 test.obj, foo.lib TO(test.aof) RS(128) IX

RLXA c:\work\bar.obj SSS(256) TO(bar.aof)
RLST6 ..\baz.obj, test.obj CODESTART(80) TO(baz.aof)

Page 112

Getting Started with the Raisonance Development Kits

Glossary
8051 – an 8-bit microcontroller family which is the world’s most popular and features
the most derivatives. Many different silicon vendors make 8051s.
Absolute Object File – an object file generated by the linker containing data to be
stored in a target’s ROM and RAM. Addresses are specified for all the target’s data in
the file. The file may also contain debugging information.
Assembler – a program which takes a source file containing a textual representation of
assembly code and converts it into a binary form stored in a relocatable object file. The
assembler processes symbols converting them to addresses to be fixed and performs
macro processing.
Breakpoint – a code address at which execution must stop once the microcontroller
reaches it.
Build process – the process involving the compilation and/or assembly of source files,
followed by the linking of generated object files, and optionally followed by the
processing of the linker generated absolute object file to convert it into other file
formats.
Compiler – a program which takes a source file containing a C program and converts
it into a binary form stored in a relocatable object file.
Debugger – software which enables high-level as well as low-level debugging to be
performed, including debugging of software running on target hardware.
Execution point – the address at which the next instruction will be executed, i.e. the
location where the Program Counter points to.
Intel Hex File – an ASCII file format that represents binary data stored at specific
addresses.
Interrupt Service Routine – the function which is executed when a particular
interrupt is generated, providing the interrupt has been correctly enabled.
I/O – input/output – for example pins on a microcontroller which allow signals to be
generated or read.
Language extension – an extension to the ANSI C programming language which
allows features specific to a microcontroller to be used. Language extensions take the
form of new keywords and new operator syntax.
Page 113

Glossary
Library – a set of relocatable object files combined into a single file called a library.
The library may then be linked with other relocatable object files producing the same
result as if each relocatable object file in the library had been linked individually.
Library Manager – a program that allows the creation of library and the addition and
removal of relocatable object files from the library.
Linker – a program that takes a set of relocatable object files and combines them into
a single absolute object file. All relocatable code and data is located at specific
addresses. All symbols are resolved to specific addresses.
Listing file – the text files generated by the assembler and compiler which detail what
the assembler and compiler did when they processed a source file and the result of the
processing.
Map file – the text file generated by the linker which details what the linker did when
it processed the input files and the result of the processing.
Memory model – the memory model configures the Compiler to operate in a certain
way by selecting the default memory space and the addressing modes allowed.
Microcontroller – a single-chip computer. Integrated onto one chip is a
microprocessor, RAM, peripherals, such as UART, I/O ports, timers, CAN controllers,
etc, usually ROM/EPROM/Flash/OTP ROM, sometimes EEPROM.
Microcontroller family – a collection of microcontrollers that feature the same
instruction set, memory areas, and other core features.
Module – the code and data generated by the assembling or compiling of a single
source file.
Monitor – a program that runs on the target system along with a user program and
reports back debugging information.
Peripheral – a unit integrated onto a microcontroller chip with a specific function, not
considered part of the core functions. For example UART, timer, CAN controller, I/O
port, PCA, watchdog, I2C
Program Counter – a register which contains the address of the next instruction to be
executed.
Project – a description of all the information necessary to create an absolute object file
and possibly an Intel Hex File. This includes the source files required, any libraries
required, a list of tools required in the build process, how to execute the tools.
Page 114

Getting Started with the Raisonance Development Kits
Project File – a file containing all the project information.
Relocatable object file – a file containing code and data generated by the processing
of a source file. However some symbols may not be fixed to specific addresses.
RIDE – Raisonance Integrated Development Environment. RIDE functions as an
editor, project manager, make utility and simulator/debugger, featuring a menu driven
and toolbar driven user interface.
Segment – when a source file is processed it is broken up into segments. There is a
segment for each function and a segment for each of the memory areas that have static
relocatable variables in the source file.
Simulator – a program that takes code for a microcontroller and executes it in exactly
the same way the microcontroller would execute it – allowing detailed analysis of what
would happen if the code was executed in the microcontroller.
Source file – a text file that contains either a textual representation of assembly code
or a C program.
Special Function Register – a register in a microcontroller that allows control of
features of the microcontroller.
ST6 – an 8-bit microcontroller family manufactured by ST-Microelectronics.
Startup code – the section of assembler code that executes before the main function is
reached. Usually the startup code is automatically inserted by the linker, however it
can be modified.
Symbol table – a table listing each symbol and the address it is stored at.
Timer – a peripheral that can count either up or down or count pulses on a pin.
XA – a 16-bit microcontroller family manufactured by Philips Semiconductors.

Page 115

Glossary

Page 116

Getting Started with the Raisonance Development Kits

Index
Assembler ... 8, 9, 13, 14, 15, 16, 21,
55, 87, 88, 89, 90, 91, 92, 93, 94,
95, 96, 97, 113
Assembler options...... 87, 88, 91, 94
assembly code15, 42, 43, 55, 56, 67,
76, 83, 89, 92, 95, 113, 115
assembly instruction... 22, 89, 92, 95
AST6 ............................................ 94
Atmel............................................ 69
AUTO .......................................... 66

2
251................................................65

5
51....................................... See 8051
517.................................See 80C517

8
8051...1, 7, 9, 13, 15, 16, 18, 28, 29,
41, 52, 57, 61, 63, 64, 65, 66, 67,
68, 70, 71, 72, 87, 88, 89, 90, 93,
99, 100, 101, 102, 103, 104, 105,
113
80C51 ................................ See 8051
80C517 ...................................69, 70

B
BANK ........................................ 102
bank switching ............. 84, 102, 110
BANKAREA ............................. 102
baud rate............. 100, 105, 106, 108
BCD ............................................. 65
BDATA.............................. 101, 103
big endian..................................... 65
BIN folder .................................... 18
binary file ................... 100, 106, 110
bit-addressable SFRs.................... 61
blue bar....................... 36, 41, 42, 53
BM ............................................. 102
break button ................................. 44
breakpoint 22, 35, 38, 39, 40, 41, 42,
43, 44, 105, 108, 113
BTR............................................ 106
BTRINIT.................................... 106
build process .......... 14, 27, 113, 114
Bus Timing Register ..........See BTR

A
.aof file .............................25, 26, 59
ABS File.....................................107
ABSCODEOFFS........................101
Absolute Object File ......14, 25, 113
absolute register addressing .........71
additional help.................... See help
address..........................................11
addressing modes .................79, 114
advanced options ..........................32
advanced options window ............32
AMD ............................................69
animate ...................... See animation
animation......................................41
ANSI .......................... See Compiler
ANSI C...................8, 9, 64, 73, 113
ANSI C Compiler....... See Compiler
ANSI Integer Promotion ..66, 74, 81
application ........................21, 22, 39
AREGS.........................................71
arithmetic processor ...............69, 70
ASCII ...................................34, 113
ASM-51........................................88

C
call tree........................... 15, 58, 111
CALLTREE ............................... 111
CD ........................ 17, 67, 76, 83, 86
CO ............................ 67, 76, 83, 107
CODE......................................... 100
code bank ........................... 102, 110
code labels.................................... 91
CODESTART ............................ 112
Page 117

Index
Command Line....21, 55, 57, 86, 97,
112
Command Line Invocation...........55
COMPACT.............................69, 78
Compiler 8, 9, 13, 15, 16, 18, 19, 21,
27, 28, 31, 36, 55, 58, 59, 63, 64,
65, 66, 67, 68, 70, 71, 72, 73, 74,
76, 77, 78, 79, 80, 81, 83, 84, 85,
86, 113, 114
Compiler options ..55, 63, 64, 73, 81
COND...............................89, 92, 95
conditional compilation....67, 75, 82
conventions...................................10
cross reference table 89, 92, 95, 101,
111
crystal frequency ..........................22
CS register ....................................74

DL ..............................100, 106, 110
DOC folder...................................18
DOCS .................See documentation
documentation..............................11
DP...............................100, 106, 110
DPTR ...........................................69
DRWRCOPY .........................81, 86
DS...............................100, 106, 110
dynamic memory requirements....58

E
ECL ..............................................91
editor ............13, 14, 21, 25, 61, 115
EJECT ..............89, 92, 95, 101, 111
EMA-51 .......................................88
Email ............................................11
enum.................................64, 73, 81
errors ..11, 27, 45, 56, 59, 72, 80, 85
ES register ....................................74
evaluation boards .........................18
example projects ..........................18
EXAMPLES folder ......................18
executable files.............................18
executable summary.....................58
execution point ...............36, 44, 113
execution time ......22, 36, 38, 39, 42
EXTEND................................64, 73
EXTREGS..............................78, 91
EXTSTK ................................69, 86

D
Dallas............................................69
DATA....57, 66, 70, 75, 79, 84, 101,
103
datasheet .................................19, 61
DB ..................68, 77, 84, 90, 93, 96
debug options .........................32, 33
debug options window ...........32, 33
debug session..........................35, 43
Debug window .............................35
Debugger .13, 14, 21, 22, 25, 31, 32,
33, 34, 36, 41, 42, 44, 45, 46, 50,
58, 59, 113, 115
Debugger window ..................34, 41
debugging information 8, 14, 68, 77,
84, 90, 93, 96, 100, 106, 110,
113, 114
DEFINE............................67, 75, 82
derivative................................28, 61
Development Kit ..................7, 8, 24
device programmers .................8, 14
directive ...64, 73, 81, 86, 88, 91, 94,
97, 100, 105, 106, 109, 110, 111,
112
directory structure ........................18
Disassembly window........42, 43, 44
Page 118

F
far code.................................74, 107
far data..................................74, 107
far idata ......................................107
FARCODE .................................107
FARDATAALLOWED ...............74
FARDATANOTALLOWED.......74
Fax................................................11
FDT ............................................107
FID .............................................107
file extensions ..............................16
filling memory..............................35
Flash ...................................103, 114
FLASH .......................................103

Getting Started with the Raisonance Development Kits
Flash mode .................................103
floating point ....................18, 65, 73
form feed .......67, 76, 83, 89, 92, 95,
101, 111
FP ...........................................65, 73
function generator ............35, 50, 51
Function Generator Options
window.....................................50

installation folder ......................... 18
installation program ..................... 17
Intel Hex File 8, 14, 16, 21, 25, 100,
106, 110, 113, 114
Intel MPL ............................... 88, 91
Intel OMF-51 ............................... 68
interrupt. 29, 30, 38, 39, 68, 74, 100,
113
Interrupt Service Routine 29, 38, 41,
42, 74, 113
interrupt vectors ........................... 68
INTERVAL.................................. 68
INTVECTOR............................... 68
INTXD ......................................... 69
IP 66, 74, 81
IS 66, 74, 81
ISR ....See Interrupt Service Routine
IX ....................... 101, 106, 111, 112

G
GEN..................................89, 92, 95
GENERIC ........................66, 74, 81
generic keyword ...............66, 75, 82
generic mode ................................78
generic option...................66, 75, 82
generic pointers ....66, 74, 75, 81, 82
GENERICFCT .............................78
green dot.................................38, 42

K
Header File .....19, 28, 29, 55, 61, 62
help ...............................................11
Help Files .....................................18
HELP folder .................................18
Help menu ....................................11
Hex File ............... See Intel Hex File
hexadecimal................34, 37, 40, 56
HUGE.....................................69, 78

I
I/O ......................................113, 114
IDATA ...........................57, 79, 100
identifier .......................................37
IEEE .......................................65, 73
IEEE-754......................................65
INC folder ........................18, 19, 61
In-Circuit Emulators.....................14
Include Files ..18, 67, 76, 83, 89, 92,
95
INCST6 Folder.................18, 19, 61
indirect function calls...................58
information ...................................11
Input Files.............................15, 114
input stimuli .................................50
installation ................................9, 17

Kernel........... See RTOS and KR-51
KR-51......................................... 104
KR-XA....................................... 108

L
language extension.... 28, 29, 64, 73,
113
LARGE ............................ 69, 78, 84
LC .................. 67, 76, 83, 89, 92, 95
LIB folder..................................... 18
LIB-51............................................ 9
library .... 8, 9, 14, 15, 16, 18, 21, 44,
57, 66, 69, 70, 75, 82, 100, 102,
104, 106, 108, 110, 112, 114
Library File .................................. 16
Library Manager ..... 8, 9, 13, 14, 21,
114
LIB-ST6 ......................................... 9
LIB-XA .......................................... 9
link map ......................... 57, 58, 101
Linker .... 8, 9, 13, 14, 15, 16, 18, 21,
27, 31, 55, 57, 58, 99, 100, 101,
102, 103, 104, 105, 106, 107,
108, 109, 110, 111, 112, 114
Page 119

Index
Linker options ......99, 100, 106, 110
Linker/Locator................ See Linker
LIST .................................89, 92, 95
Listing File ....15, 16, 55, 56, 57, 67,
76, 83, 89, 92, 95, 101, 114
little endian.............................65, 73
LOADCS................................74, 75
LOADES ................................74, 75
Locator ........................... See Linker
low-level I/O ................................18
LX-51 .....................................9, 112

Microcontroller family...........9, 114
minimum system requirements .. See
system requirements
MOD51 ........................................88
MOD517 ................................69, 70
MODAMD ...................................69
MODATM ...................................69
MODST6......................................94
module.......14, 15, 56, 57, 101, 102,
103, 111, 114
module information......................56
MODULEMAP..........................111
MODXA.......................................91
Monitor.............8, 18, 105, 108, 114
MPL ..........................See Intel MPL

M
MA-51 ......................................9, 97
macro .....67, 76, 83, 89, 92, 95, 102,
113
MACRO .................................88, 91
macro expansions .............67, 76, 83
Make All...........................27, 31, 45
Make window.........................27, 31
manuals.............................18, 55, 58
Map File ......15, 16, 55, 57, 59, 101,
106, 107, 111, 114
MA-ST6 ...................................9, 97
mathematical operations...............18
MA-XA ....................................9, 97
MAXERR.........................72, 80, 85
MAXWAR .......................72, 80, 85
MEDIUM .....................................78
memory8, 14, 15, 18, 21, 22, 34, 35,
56, 57, 58, 66, 69, 70, 71, 74, 75,
78, 79, 81, 82, 84, 101, 114, 115
memory allocation........................18
memory areas ...22, 57, 58, 114, 115
memory location...........................34
memory map.............14, 15, 57, 101
memory model.....57, 69, 70, 74, 78,
79, 84, 114
memory requirements.15, 56, 58, 71
memory specific pointers .66, 74, 81
memory viewing windows ...........34
Microcontroller..7, 8, 22, 24, 28, 29,
46, 50, 51, 57, 61, 66, 81, 105,
108, 113, 114, 115
Page 120

N
NDT ...........................................107
NDTSEG....................................107
near code ....................................107
near data .....................................107
near idata ....................................107
nesting level .................................55
netlist ............................................51
Nets window ..........................51, 52
NID.............................................107
NLIB ..........................100, 106, 110
NOAREGS...................................71
NOAUTO.....................................66
NOCALLTREE .........................111
NOCD ..............................67, 76, 83
NOCO ..............................67, 76, 83
NOCOND.........................89, 92, 95
NODB ..................68, 77, 84, 93, 96
node ........................................51, 52
NODL.........................100, 106, 110
NODP.........................100, 106, 110
NODS.........................100, 106, 110
NOECL ........................................91
NOEXTEND ..........................64, 73
NOEXTREGS........................78, 91
NOGEN............................89, 92, 95
NOGENERIC...................66, 74, 81
NOINTVECTOR .........................68

Getting Started with the Raisonance Development Kits
NOIP ................................66, 74, 81
NOIS ................................66, 74, 81
NOIX..........................101, 106, 111
NOLIST............................89, 92, 95
NOLOADCS ..........................74, 75
NOLOADES ..........................74, 75
NOMO..............................91, 94, 97
NOMOD51...................................88
NOMODULEMAP ....................111
non page 0 ....................................79
NOOBJECT .....................90, 93, 96
NOOE...........................................77
NOPR ...............................67, 76, 83
NOPRINT ........................89, 92, 95
NOREGPARMS ..........................71
NOSAVESEG ..............................74
NOSB .............67, 76, 83, 89, 92, 95
NOSSS .......................................106
NOUSS.......................................106
NOXR ..............................89, 92, 95

O
OBJECT ..68, 77, 84, 86, 90, 93, 96,
97
Object File .8, 13, 16, 57, 68, 77, 84,
102, 112, 113, 114
Object-Hex Converter ...8, 9, 13, 14,
21
OE ....................................68, 77, 90
OH51XA ........................................9
OHST6 ...........................................9
OMF-51...............See Intel OMF-51
optimizations ..............59, 71, 79, 85
optimizer ..........................71, 79, 85
OT ....................................71, 79, 85

P
page 0 .....................................74, 79
peripheral..........22, 34, 41, 114, 115
PHILIPSDDPTR ..........................69
PL ..67, 76, 83, 89, 92, 95, 101, 107,
111
pointer 37, 40, 46, 52, 66, 75, 79, 82
port pin ...................................53, 54

POSTOPT .............................. 71, 90
PP ..................................... 67, 76, 83
PR......................... 67, 76, 83, 86, 97
PREPROST.................................. 94
PRINT .............................. 89, 92, 95
printf..................... 44, 100, 106, 110
Program Counter.......... 48, 113, 114
project ... 7, 8, 13, 14, 15, 18, 21, 24,
25, 26, 27, 28, 31, 45, 57, 58, 63,
65, 73, 87, 99, 101, 102, 114, 115
Project File .... 16, 24, 26, 31, 58, 63,
87, 99, 114, 115. See Project
project manager............................ 25
project tree ................................... 26
Project window ...................... 25, 26
PRSTATICSIZE ........................ 110
PW. 67, 76, 83, 89, 92, 95, 101, 107,
111

R
Raisonance Integrated Development
Environment................. See RIDE
RAM 17, 70, 84, 100, 101, 105, 106,
108, 110, 113, 114
RAMSIZEINIT .......................... 110
RB .......................................... 71, 90
RC-51....................................... 9, 86
RC-ST6 .............................. 9, 86, 97
RC-XA ..................................... 9, 86
red bar .................................... 38, 41
red dot .......................................... 41
reentrant ................. 66, 69, 100, 102
reentrant stack .............................. 69
reference map............................... 58
REFLASH.................................. 103
Register window .......................... 43
registerbank............................ 71, 90
registers ... 22, 43, 68, 71, 74, 78, 88,
91, 94
REGPARMS ................................ 71
Relocatable Object File... 13, 14, 68,
77, 84, 90, 93, 96, 113, 114, 115
RESERVE.................................. 103
reset vector ................................. 100
Page 121

Index
RIDE..7, 8, 9, 11, 13, 14, 16, 18, 21,
22, 23, 24, 25, 29, 32, 33, 36, 38,
42, 46, 50, 55, 57, 61, 63, 87, 99,
105, 108, 115
RL-ST6...................................9, 112
RL-XA....................................9, 112
ROM....96, 101, 105, 108, 110, 113,
114
ROMFILL ..............................96, 97
ROMFILLRESERVEDVALUE 110
ROMFILLUNUSEDVALUE ....110
ROM-Monitor .............. See Monitor
RS ...............................100, 106, 112
RSI......................................100, 106
RTOS............................78, 104, 108

SSS .....................................106, 112
SSTACK ....................................107
SSTKOV ....................................107
ST6 ....1, 7, 9, 13, 15, 16, 18, 19, 24,
28, 30, 52, 57, 58, 61, 81, 83, 84,
85, 94, 95, 96, 110, 111, 115
stack ..58, 66, 69, 70, 100, 102, 106,
107
Standard C Libraries ....................18
Standard C Library functions.......18
startup code ...18, 36, 66, 69, 74, 81,
100, 106, 115
status bar ......................................36
Step Into .................................42, 43
struct.................................64, 73, 81
SUE_OPT.........................64, 73, 81
symbol table ..15, 56, 58, 59, 67, 76,
83, 89, 92, 95, 115
SYNTAX .....................................88
system mode.................................78
system requirements.....................17
system stack .............. 107. See stack
SYSTEMFCT...............................78

S
.src file ..............................68, 77, 84
SAVESEG..............................74, 86
SB .......67, 76, 83, 86, 89, 92, 95, 97
segment....57, 58, 74, 100, 101, 107,
115
semaphores .........................104, 108
SET...................................88, 91, 94
SIGNEDCHAR ................66, 74, 81
simulated external stack .........69, 70
simulation 22, 35, 36, 38, 41, 42, 44,
47, 48, 53, 58
Simulator ...7, 13, 14, 21, 22, 28, 44,
115
single-precision floating point......65
SMALL ............................69, 78, 84
Source Code window .......36, 37, 43
Source File.8, 13, 14, 15, 16, 18, 19,
21, 25, 26, 28, 31, 56, 57, 63, 68,
77, 84, 86, 87, 97, 113, 114, 115
Sources sub-folder........................18
Special Function Register18, 19, 28,
29, 37, 61, 62, 88, 91, 94, 115
sprintf .................................100, 106
square wave ......................48, 51, 52
SRC ..................................68, 77, 84
SSEL.............................................75
SSELINIT.....................................75
Page 122

T
tasks............................................104
Telephone.....................................11
tick rate...............................104, 108
timer ....29, 30, 38, 39, 41, 100, 106,
114, 115
TINY ......................................69, 78
TO ..............................................112
tool ....7, 8, 9, 13, 14, 15, 16, 18, 21,
26, 29, 57, 61, 114
toolbar ......................27, 36, 44, 115
trace list ..................................46, 53
Trace Options window .................47
trace records .....................48, 49, 53
Trace window...................47, 48, 53

U
UART.........................105, 108, 114
union.................................64, 73, 81
UNSIGNEDCHAR ..........66, 74, 81

Getting Started with the Raisonance Development Kits
user mode .....................................78
user stack ....................................106
USERFCT ..............................78, 86
USS ............................................106
USTKOV....................................107

watchpoints .................................. 40
waveform . 46, 48, 49, 50, 52, 53, 54
waveform expression ................... 51
web sites....................................... 11
WL ................................... 72, 80, 85

X
variable ....29, 30, 34, 37, 40, 46, 54,
58, 59, 77
volatile..........................................59
Von Neuman ......................105, 108

W
warnings ..27, 31, 45, 56, 59, 72, 80,
85
Watch window ...........40, 41, 46, 52

XA..... 1, 7, 9, 13, 15, 16, 18, 24, 28,
30, 52, 57, 61, 73, 74, 76, 77, 78,
79, 80, 91, 92, 93, 106, 107, 108,
115
XDATA........................ 70, 100, 104
XEVA ................................ 105, 108
XR .............................. 89, 92, 95, 97
XRAM.......................................... 69

Page 123

Getting Started with the Raisonance Development Kits
Notes

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Getting Started with the Raisonance Development Kits
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