OT2 SCHEMATIC 3.22 Hp Compaq 2510P Quanta

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5

4

3

2

1

Sapporo 1.0 BLOCK DIAGRAM
CPU Thermal
Sensor

P38

CPU CORE

Merom

D

+1.05V/+1.5V /+1.25V/+1.25VM

Clock Generator

P04

MAX6657

D

CK505

P17

P37

478Pins
(Micro-FCBGA)

P35

3VPCU/5VPCU

14.318MHz

P4,P5

Ambient Light Sensor

667/800 MHz FSB

1.8V/SMDDR_VTERM/SMDR_VREFP36
BATT CHARGER
MAX8724/1908

Cable Docking
LCD Panel P18

P34

DISCHARGE

CRT port P27

P33

LVDS
Singal Channel DDR2

Crestline

DDR2-SODIMM1

1 TO 4 USB HUB
LINE IN
LINE OUT
RJ45
CRT PORT
SVIDEO OUT
POWER JACK

P16

1299 uFCBGA

R.G,B

P7,P8,P9,P10,P11

+3VM_LAN_SW/3V_S5/+3V_CK505/3VSUS/+3V
P39
C

+5V/5VSUS

C

DMI
P35

PCI-E
SATA/PATA

WLAN MiniCard
P19

HDD (1.8 inch) P28

ICH8M

PATA
DVD-ROM

PCI-E

P28

USB PORT 0

USB 2.0

PCI BUS

P30

P12,P13,P14,P15

PCMCIA Controller
Ricoh 5C847

LAN
Intel Nineveh-MM

P20,P21

USB PORT 1(POWER
P30
USB)

SMBUS

PCMCIA /SMART CARD
P20

B

P24,P25

1394 P21

RJ45

B

P25

Bluetooth Module P30

Accelerometer

Azalia

LIS3LV02DL

FingerPrint(AES2501B)
P30

3.3V LPC, 33MHz

SPI

WWAN MiniCard
P19

SIM CARD

SYSTEM
BIOS

TPM (1.2)
SLB9635

P23

P23

P31

SMSC KBC1070

MODEM
MDC 1.5 P30

P26

FAN
P29

4

MIC
JACK

TLV2462CDGKR
P23

A

5

AUDIO
JACK

TPA6211A
P23

AMP

USB for Docking P32

P19

AMP

Audio
CODEC
AD1981 P22,P23

Track
PointP29
3

RJ11
JACK P30

A

PROJECT : OT2
Quanta Computer Inc.

Keyboard
P29

2

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

System Block Diagram
Sheet
1

1

of

42

5

4

INDEX
Description

NOTE

Label

System Information

3

System Power Block Diagram

4-5

Merom CPU/THERMAL SENSOR

16
17
18
19

C

LCD CONNECTOR / LCD PWR
WAN/WWAN /SIM CARD connector

AUDIO CODEC / AUDIO JACK

HDD / CD-ROM
FAN,KB,LEDs,TRACK POINT

CABLE DOCKING

CPU CORE POWER (1.25/1.15V)

VRON

FSB POWER (1.05V)

MAIND

M0.M1

IAMT_ON

S0

MAIND

3VSUS

S0, S3

SUSON

3V_S5

S0, S3, S4, S5
S0, S3, S4, S5.M0.M1.Moff

S5_ON
ALWAYS POWER (3V)

+5V

S0

MAIND

5VSUS

S0, S3

SUSON

S0, S3, S4, S5
S0, S3, S4, S5.M0.M1.Moff

DISCHARGE

34

-CHARGER(MAX1908/8724)

35

MAX1999(3VPCU/5VPCU)

36

MAX1992(1.8VSUS/DDR_VTERM)

37

MAX1540 (+1.05V/+1.5V)

38

--MAX8736

39

+3VM/+3V_S5/1.25V_M

S5_ON
ALWAYS POWER (5V)

S0

+1.5VM

USB,BLUE TOOTH,FINGER PRINT, MDC,TPM

32

D

RTC & KBC POWER (3_3V)

+3V

+1.5V

POWER SEQUENCE,BIOS

MAIND

M0.M1

IAMT_ON

1.8VSUS

S0, S3

+2.5V

S0

SMDDR_VTERM

S0

DDR COMMAND & CONTROL PULL UP POWER

SMDDR_VREF

S0, S3

DDR REF POWER

SUSON

VDDA

S0

AUDIO ANALOG POWER (5V)

MAINON

DDR CORE POWER

SUSON
MAINON
MAINON

B

+3V_CK505

M0.M1

IAMT_ON

+3V_LAN_SW

M0.M1

IAMT_ON

S0

MAIND

+1.25V
+1.25VM

M0.M1

IAMT_ON

POWER SEQUENCE

PCI DEVICES IRQ ROUTING
DEVICE

S0

5VPCU

31

40

S0

+1.05V

5V_S5

CRT PORT

AC ADAPTER (19V)
MAIN BATTERY + (10~17V)

C

KBC

28

33

CPU_CORE

3VPCU

LAN/TRANSFORMER

27

30

B

CLOCK GEN

Control
Signal

S0, S3, S4, S5.M0.M1.Moff +15V

+1.05VM

DDR II SO-DIMM

CARDBUS CONTROLLER

29

S0, S3, S4, S5.M0.M1.Moff

+15V

ICH8_M

22-23

26

S0, S3, S4, S5.M0.M1.Moff

VCCRTC

Crestline_

20-21

24-25

1

Description

S0, S3, S4, S5.M0.M1.Moff

MBAT

2

12-15

ACTIVE

VIN

Schematic Block Diagram

D

7-11

2

Power & Ground

Pg#
1

3

IDSEL #

A

5

REQ/GNT #

PCI_INT

PCB STACK UP
LAYER 1 : TOP
LAYER 2 : GND
LAYER 3 : IN1
LAYER 4 : IN2
LAYER 5 : VCC
LAYER 6 : IN3
LAYER 7 : GND
LAYER 8 : BOT
4

SM BUS
DEVICE

ADDRESS

BUS

CLOCK GENERATOR

A

DDR II
Accelemter sensor

PROJECT : OT2
Quanta Computer Inc.

CHARGER
CPU THERMAL SENSOR
3

2

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

System Information
Sheet
1

2

of

42

5

4

3

2

1

S5_ON

SYSTEM POWER BLOCK DIAGRAM

S.W
3V_S5

MOS-FET
IAMT_ON

S.W
+3V_CK505

D

S.W
Adaptor

MOS-FET

MOS-FET

D

IAMT_ON

S.W

3VPCU
ALWAYS

VIN

+3VM_LAN_SW

MOS-FET

MAX1999

IAMT_ON

SC4215

+1.25VM

VIN

MAIND

+3V

S.W
MOS-FET

C

CHARGER

C

3VSUS

SUSD

MAX8724/1908
MAIND

+15V

+5V

S.W
MOS-FET

5VSUS

SUSD

5VPCU
ALWAYS
BATTERY

SUSON

S.W
MOS-FET

MAINON

SMDDR_VTERM

B

MAX1992

1.8VSUS

TPS51100

B

SMDDR_VREF
MAINON
MAINON

SC4215

1.5V

VIN

+1.25V

MAIND

MAX1540
1.05V_M

S.W
+1.05V

MOS-FET
VIN

IAMAT_ON
MAINON

VRON
KBC_PW_ON
A

SLP_S5#
CPU_VID[0..5]

MAX1907

HWPG

SLP_S3#

CPU_CORE

TC7SH08FU
TC7SH08FU

S5_ON

DISCHARGE

S5_OND
A

SUSON

DISCHARGE
DISCHARGE

TC7SH08FU

SUSD
MAIND

DPRSLPVR

PROJECT : OT2
Quanta Computer Inc.

STP_CPU#

5

4

3

2

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

System pwr block diagram
Sheet
1

3

of

42

STPCLK#
LINT0
LINT1
SMI#

M4
N5
T2
V3
B2
C3
D2
D22
D3
F6

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]

H_STPCLK#
H_INTR
H_NMI
H_SMI#

H_LOCK# (6)

C1
F3
F4
G3
G2

H_RESET# (6)
H_RS#0 (6)
H_RS#1 (6)
H_RS#2 (6)
H_TRDY# (6)

HIT#
HITM#

G6
E4

H_HIT# (6)
H_HITM# (6)

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

D21
A24
B25

H_PROCHOT#
H_THERMDA
H_THERMDC

THERMTRIP#

+1.05V

75
1

C7

R62
1K/F

+1.05V
H_PROCHOT# (39)

PM_THRMTRIP# (7,12)

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

(6) H_DSTBN#1
(6) H_DSTBP#1
(6) H_DINV#1

V_CPU_GTLREF AD26
CPU_TEST1
C23
CPU_TEST2
D25
CPU_TEST3
C24
CPU_TEST4
AF26
CPU_TEST5
AF1
CPU_TEST6
A26

R54
2K/F

H CLK
BCLK[0]
BCLK[1]

A22
A21

CLK_CPU_BCLK (17)
CLK_CPU_BCLK# (17)

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

COMP[0]
COMP[1]
COMP[2]
COMP[3]

R26
U26
AA1
Y1

COMP0
COMP1
COMP2
COMP3

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#

E5
B5
D24
D6
D7
AE6

H_DSTBN#2 (6)
H_DSTBP#2 (6)
H_DINV#2 (6)
H_D#[0..63]

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

Layout Note:
Place voltage
divider within
0.5" of GTLREF
pin

XDP_DBRESET# (14,31)

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

(17) CPU_BSEL0
(17) CPU_BSEL1
(17) CPU_BSEL2

H_D#[0..63] (6)

A

H_D#[0..63]

(6) H_D#[0..63]

R105
2

PROCHOT#
THERMDA
THERMDC

(6) H_DSTBN#0
(6) H_DSTBP#0
(6) H_DINV#0

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

DATA GRP 2

H4

2

CONTROL

LOCK#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

B22
B23
C21

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

MISC

BSEL[0]
BSEL[1]
BSEL[2]

H_D#[0..63] (6)

B

H_DSTBN#3 (6)
H_DSTBP#3 (6)
H_DINV#3 (6)

H_DPRSTP# (7,12)
H_DPSLP# (12)
H_DPWR# (6)
H_PWRGOOD (12)
H_CPUSLP# (6)
PSI#
(39)

Merom Ball-out Rev 1a

DB1A:change for intel
schematic
R124
CPU_TEST1
1
2
*1K/F
R119
CPU_TEST2
1
2
C49
*1K/F
CPU_TEST4
2
1
R125 *0.1U/10V
CPU_TEST6
1
2
*0

Merom Ball-out Rev 1a
C

CPU_TEST3
CPU_TEST5

PAD T92
PAD T6

For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
C

Place C close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.

2

COMP0
COMP1
COMP2
COMP3

R78
54.9/F

R67
27.4/F

2

(12)
(12)
(12)
(12)

D5
C6
B4
A3

+1.05V
H_INIT# (12)

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#

2

A20M#
FERR#
IGNNE#

R112 56
1
2

H_IERR#

RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#

THERMAL

ICH

A6
A5
C4

H_DEFER# (6)
H_DRDY# (6)
H_DBSY# (6)
H_BR0# (6)

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

2

T11
(6) H_ADSTB#1
(12) H_A20M#
(12) H_FERR#
(12) H_IGNNE#

D20
B3

H_D#[0..63]

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

1

B

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

XDP/ITP SIGNALS

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

H_BNR# (6)
H_BPRI# (6)

F1

8

U21B
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

T25

RESERVED

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_A#[17..35]

(6) H_A#[17..35]

BR0#

PAD

H5
F21
E1

IERR#
INIT#

H_D#[0..63]

(6) H_D#[0..63]

H1
E2
G5

7

DATA GRP 1

K3
H2
K2
J3
L1

DEFER#
DRDY#
DBSY#

ADDR GROUP
1

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

6

DATA GRP 0

H_REQ#[0..4]

ADS#
BNR#
BPRI#

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

ADDR GROUP
0

(6) H_ADSTB#0
(6) H_REQ#[0..4]

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

5

H_ADS# (6)

U21A
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

A

4

1

H_A#[3..16]

(6) H_A#[3..16]

3

DATA GRP 3

2

2

1

R83
54.9/F

R87
27.4/F

XDP_BPM#2
+1.05V
XDP_BPM#1
XDP_BPM#0

R76
R69
R71
R63
R66
R56

0
*0
0
*56/F
0
0

XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3

D

H_PWRGOOD
+1.05V

R57
R42

1K/F
54.9/F

H_PWRGD_XDP

T5
T2
L_CLKCTLB
L_CLKCTLA

(7) L_CLKCTLB
(7) L_CLKCTLA
R38

27/F

XDP_TCK

DB1A stage:change for change list

*CONN60_ITP-XDP
1

2

Comp0,2 connect with Zo=27.4ohm,Comp1,3
connect with Zo=55ohm, make those traces
length shorter than 0.5".Trace should be
at least 25 mils away from any other
toggling signal.

+3V

R350
100R

H/W MONITOR
XDP_DBRESET# (14,31)

C420
0.1U

U28
6657VCC

SI stage:no install to avoid leakage current
+1.05V

H_THERMDA

CLK_CPU_XDP (17)
CLK_CPU_XDP# (17)
R47
XDP_DBRESET# R46

1K/F
*1K/F

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS

*54.9/F
680
150
39

R41
R40
R36
R39

C422
2200P
+3V

VCC

SMCLK

8

SMBCK

2

DXP

SMDATA

7

SMBDT

3

DXN

-ALT

6

THERM_ALERT#

-OVT

GND

5

H_THERMDC

H_RESET#

4
(35) SYS_SHDN#

SMBCK

1

(17,19,27)

SMBDT

MAX6657/GMT-781

PROJECT : OT2
Quanta Computer Inc.

+1.05V
C50
0.1U

C39
0.1U

4

5

6

D

(17,19,27)

THERM_ALERT# (14)

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

(HOST BUS)/THERMAL

DB1A stage:change for change list
3

1

layout note for H_THERMDA/H_THERMDC - Trace width/Spacing
should be 10/10 mils

1

GND0
GND1
OBSFN_A0
OBSFN_C0
OBSFN_A1
OBSFN_C1
GND2
GND3
OBSDATA_A0
OBSDATA_C0
OBSDATA_A1
OBSDATA_C1
GND4
GND5
OBSDATA_A2
OBSDATA_C2
OBSDATA_A3
OBSDATA_C3
GND6
GND7
OBSFN_B0
OBSFN_D0
OBSFN_B1
OBSFN_D1
GND8
GND9
OBSDATA_B0
OBSDATA_D0
OBSDATA_B1
OBSDATA_D1
GND10
GND11
OBSDATA_B2
OBSDATA_D2
OBSDATA_B3
OBSDATA_D3
GND12
GND13
PWRGD/HOOK0 ITPCLK/HOOK4
HOOK1
ITPCLK#/HOOK5
VCC_OBS_AB
VCC_OBS_CD
HOOK2
RESET#/HOOK6
HOOK3
DBR#/HOOK7
GND14
GND15
SDA
TDO
SCL
TRSTn
TCK1
TDI
TCK0
TMS
GND16
GND17

1

XDP_BPM#5
XDP_BPM#4
XDP_BPM#3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

1

JITP1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

7

Sheet

4

of
8

42

1

2

3

4

5

VCC_CORE

6

7

8

VCC_CORE
U21C

2

C82
22U/6.3V

C144
22U/6.3V
2

C145
22U/6.3V
2

2

C79
22U/6.3V

1

1

1

1
C142
22U/6.3V
2

2

C143
22U/6.3V

8 inside cavity, south side, secondary layer.

1

1
2

C140
22U/6.3V

C141
22U/6.3V
2

1
C139
22U/6.3V
2

C138
22U/6.3V
2

C170
22U/6.3V
2

2

C45
22U/6.3V

1

1

1

VCC_CORE

6 inside cavity, north side, primary layer.
VCC_CORE

VCCA[01]
VCCA[02]

B26
C26

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VCCSENSE

VSSSENSE

AE7

VSSSENSE

+1.05V

+ C106
330U/4V

DB1A stage:change
to 330u

+1.5V

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6

(39)
(39)
(39)
(39)
(39)
(39)
(39)

C156
0.01U/25V

VCCSENSE (39)

C163
10U/4V

Layout Note:
Place C156 near
PIN B26.

.

VSSSENSE (39)

C41
22U/6.3V

VCC_CORE
1

2

2

C42
22U/6.3V

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

Merom Ball-out Rev 1a

1

1

1
C43
22U/6.3V
2

C46
22U/6.3V
2

C47
22U/6.3V
2

2

C48
22U/6.3V

1

1

1

C

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

1

1

1
C83
22U/6.3V
2

C84
22U/6.3V
2

2

C80
22U/6.3V

VCC_CORE

1

B

1

1

1
2

C81
22U/6.3V

A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3

2

8 inside cavity, north side, secondary layer.
VCC_CORE

1

2

C174
22U/6.3V

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

2

1

1
C167
22U/6.3V
2

C168
22U/6.3V
2

C85
22U/6.3V
2

2

C86
22U/6.3V

1

1

1

VCC_CORE

U21D
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

1

2

C169
22U/6.3V

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

2

1

1
C171
22U/6.3V
2

C172
22U/6.3V
2

2

C173
22U/6.3V
2

C44
22U/6.3V

A

1

1

All use 22U 6.3V(+-20%,X5R,0805)Pb-Free.

1

VCC_CORE

A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

R45
100/F
2

6 inside cavity, south side, primary layer.

1

VCCSENSE
VSSSENSE

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]

D

B

C

Merom Ball-out Rev 1a
.

C123
0.1U/10V

Route VCCSENSE and VSSSENSE
traces at 27.4ohms and
length matched to within 25
mil. Place PU and PD within
2 inch of CPU.

2

2

C96
0.1U/10V

A

2

1

1

1
C117
0.1U/10V
2

C105
0.1U/10V
2

C87
0.1U/10V
2

2

C98
0.1U/10V

1

1

R44
100/F

1

+1.05V

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

Layout out:
Place these
inside
socket
cavity on
North side
secondary.

D

PROJECT : OT2
Quanta Computer Inc.

1

2

3

4

5

6

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

Merom(POWER/NC)
7

Sheet

5

of
8

42

1

2

3

4

5

6

U30A

1

+1.05V

R134
221/F

2

1

2

H_SWING

2

1

C189
0.1U/10V

B

1

1

+1.05V

R174
54.9/F
2

2

R175
54.9/F

H_SCOMP
H_SCOMP#

1

H_RCOMP

2

R142
24.9/F

C

Layout Note:
H_RCOMP trace should be
10-mil wide with 20-mil
spacing.

2

+1.05V

E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
M10
N12
N9
H5
P13
K9
M2
W10
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
Y3
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13

H_SWING
H_RCOMP

B3
C2

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

W1
W2

H_SCOMP
H_SCOMP#

B6
E5

H_CPURST#
H_CPUSLP#

(4) H_RESET#
(4) H_CPUSLP#

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

1

R132
1K/F

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

B9
A9

8

H_A#[3..35] (4)

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

H_ADS# (4)
H_ADSTB#0 (4)
H_ADSTB#1 (4)
H_BNR# (4)
H_BPRI# (4)
H_BR0# (4)
H_DEFER# (4)
H_DBSY# (4)
CLK_MCH_BCLK (17)
CLK_MCH_BCLK# (17)
H_DPWR# (4)
H_DRDY# (4)
H_HIT# (4)
H_HITM# (4)
H_LOCK# (4)
H_TRDY# (4)

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

K5
L2
AD13
AE13

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

M7
K3
AD2
AH11

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

(4)
(4)
(4)
(4)

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

L7
K2
AC2
AJ10

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

(4)
(4)
(4)
(4)

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

M14
E13
A11
H13
B12

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#_0
H_RS#_1
H_RS#_2

E12
D7
D8

H_RS#0 (4)
H_RS#1 (4)
H_RS#2 (4)

A

B

(4)
(4)
(4)
(4)

C

(4)
(4)
(4)
(4)
(4)

H_AVREF
H_DVREF
CRESTLINE_1p0

C186
0.1U/10V

2

2

R136
2K/F

1

1

H_REF

HOST

A

R141
100/F

H_A#[3..35]

H_D#[0..63]

(4) H_D#[0..63]

7

Layout Note:
Place the 0.1 uF
decoupling capacitor
within 100 mils from
GMCH pins.

D

D

PROJECT : OT2
Quanta Computer Inc.

1

2

3

4

5

6

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

Crestline_1(HOST)
7

Sheet

6

of
8

42

1

2

3

4

5

6

7

8

1

1.8VSUS
U30B

+VCC_PEG

U30C

R210

SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4

BE29
AY32
BD39
BG37

DDR_CKE0_DIMMA (16)
DDR_CKE1_DIMMA (16)

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

BG20
BK16
BG16
BE13

DDR_CS0_DIMMA# (16)
DDR_CS1_DIMMA# (16)

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

BH18
BJ15
BJ14
BE16

M_ODT0 (16)
M_ODT1 (16)

SM_RCOMP
SM_RCOMP#

BL15
BK14

SMRCOMPP
SMRCOMPN

SM_RCOMP_VOH
SM_RCOMP_VOL

BK31
BL31

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF_0
SM_VREF_1

AR49
AW4

2
R167
2.4K

L_IBG
L_VBG
L_VREFH
L_VREFL
TXLCLKOUTTXLCLKOUT+

1

PAD T32
(18) TXLCLKOUT(18) TXLCLKOUT+

UMA

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

TXLOUT0TXLOUT1TXLOUT2-

TXLOUT0TXLOUT1TXLOUT2-

G51
E51
F49

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2

(18) TXLOUT0+
(18) TXLOUT1+
(18) TXLOUT2+

TXLOUT0+
TXLOUT1+
TXLOUT2+

G50
E50
F48

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2

G44
B47
B45

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2

E44
A47
A45

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2

E27
G27
K27

TVA_DAC
TVB_DAC
TVC_DAC

F27
J27
L27

TVA_RTN
TVB_RTN
TVC_RTN

M35
P33

TV_DCONSEL_0
TV_DCONSEL_1

H32
G32
K29
J29
F29
E29

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

(18)
(18)
(18)

R198
20/F
2

SMRCOMPP
SMRCOMPN

LCD_BLON

R199
20/F

SMDDR_VREF_MCH

R160
100K

DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

B42
C42
H48
H47

PEG_CLK
PEG_CLK#

K44
K45

MCH_DREFCLK (17)
MCH_DREFCLK# (17)
DREF_SSCLK (17)
(32)
DREF_SSCLK# (17)
(32)
CLK_MCH_3GPLL (17)
CLK_MCH_3GPLL# (17)

R155
TV_Y/G
TV_C/R

TV_Y/G
TV_C/R
R166
R163

*150/F

150/F
150/F

+3V

(4,12) PM_THRMTRIP#
(14,39) PM_DPRSLPVR

PLTRST#_R
PM_THRMTRIP#
1
2
R154

D

0

TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8
TP_NC9
TP_NC10
TP_NC11
TP_NC12
TP_NC13
TP_NC14
TP_NC15
TP_NC16

BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16

NC

PAD T109
PAD T111
PAD T120
PAD T118
PAD T113
PAD T116
PAD T115
PAD T110
PAD T108
PAD T103
PAD T98
PAD T105
PAD T107
PAD T101
PAD T99
PAD T112

(13)
(13)
(13)
(13)

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

AJ46
AJ41
AM40
AM44

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

(13)
(13)
(13)
(13)

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

AJ47
AJ42
AM39
AM43

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

(13)
(13)
(13)
(13)

CRT_B

(27)

CRT_G

(27)

CRT_R

CRT_B
CRT_G
CRT_R

(27) DDCCLK
(27) DDCDATA
R150
(27) CRT_HSYNC
R139

DDCCLK
DDCDATA
39/F
1.3K/F

(27) CRT_VSYNC

CRTIREF
R145
39/F

K33
G35
F33
C32
VSYNC E33

CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

AM49
AK50
AT43
AN49
AM50

CL_CLK0 (14)
CL_DATA0 (14)
MPWROK (14,31)
ICH_CL_RST0# (14)

R179
1K/F

1

MCH_CLVREF

H35
K36
G39
G40

TEST_1
TEST_2

A37
R32

CLKREQ#_B (17)
MCH_ICH_SYNC#

DFGT_VR_EN (38)

DMI X2 Select

CFG9

PCI Express
Graphic Lane

CFG
[12:13] XOR/ALLZ/Clock
Un-gating
(14)

CFG19
R137
0

CFG20

3

C237
0.1U/10V

CFG5

CFG16

R172
20K

4

2

(38)
(38)
(38)
(38)

MCH_CLVREF

SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

+1.25VM

2

DFGT_VID_0
DFGT_VID_1
DFGT_VID_2
DFGT_VID_3
2 R144
1
0

PV stage:install for
HP request

R182 100
2
1 PLTRST#_R

2

75/F
75/F
75/F

R180
392/F

A

B

C

DB1A :install
CRESTLINE_1p0
+3V

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN

E35
A39
C38
B39
E36 GFX_VR_EN

1
1

(27)

R139

For Calero : 255
For Cresstline:1.3K/F
For external VGA:0
ohm

CRESTLINE_1p0

(13) PLT_RST-R#

R156
R162
R149

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

1

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

2.2K
2.2K

DB1A Stage: ADD

2

(14,31,39) DELAY_VR_PWRGOOD

PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

AM47
AJ39
AN41
AN45

R956
R957

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

R169 24.9/F
1
2

UMA
R151
R153

1
1

2 10K
2 10K

R143

1

2 *10K

+3V

L_CLKCTLA
L_CLKCTLB

R170 1
R164 1

DFGT_VR_EN

2 10K
2 10K

1.8VSUS

PM_EXTTS#0
PM_EXTTS#1

DB2 stage:R164 install

1

PM_EXTTS#0
PM_EXTTS#1

G41
L39
L36
J36
AW49
AV20
N20
G36

PM

(14) PM_BMBUSY#
(4,12) H_DPRSTP#
(16) PM_EXTTS#0

*4.02K/F
*4.02K/F

(13)
(13)
(13)
(13)

2

R171 2
R161 2

*4.02K/F

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

1

R168 2

AN47
AJ38
AN42
AN46

2

+3V

*4.02K/F
*4.02K/F

GRAPHICS VID

C

*4.02K/F

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

VGA

R165 2
R152 2

CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

*4.02K/F

CFG

R148 2

PAD T18
PAD T100
1
PAD T33
PAD T21
PAD T23
1
PAD T38
PAD T26
1
1
PAD T19
T27
PAD
1
PAD T34
PAD T30
1
1

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

ME

R159 2

P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35

MISC

(17) MCH_BSEL0
(17) MCH_BSEL1
(17) MCH_BSEL2

DMI

Layout Note:
Location of all MCH_CFG strap
resistors needs to be close to
minmize stub.

N43
M43

GRAPHICS

1

1.8VSUS

L41
L43
N41
N40
D46
C45
D44
E42

PEG_COMPI
PEG_COMPO

PCI-EXPRESS

M_CLK_DDR#0 (16)
M_CLK_DDR#1 (16)

FSB Dynamic
ODT
DMI Lane
Reversal
SDVO/PCIE
Concurrent
Operation
5

DB1A:change to
10k

Low=DMIx2
High=DMIx4(Default)
Low= Reveise Lane
High=Normal operation
00=Reserved.
01=XOR Mode Enabled.
10=ALL-Z Node Enabled.
11=Clock gating Enabled(default).
Low=Dynamic ODT Disable
High=Dynamic ODT Enable(default).
Low=Normal(default).
High=Lane Reversed
Low=Only SDVO or PCIEx1 is operational
(defaults)
High=SDVO and PCIEx1 are operating
simultaneously via PEG port
6

R192
*10K/F
0
SMDDR_VREF_MCH
2

AW30
BA23
AW25
AW23

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

C633
0.1U/10V

R187
SMDDR_VREF

SMDDR_VREF (16,37)

R191
*10K/F

1

SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4

L_IBG

1

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

M_CLK_DDR0 (16)
M_CLK_DDR1 (16)

2

BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34

MUXING

PAD T117
PAD T50
PAD T60
PAD T106
PAD T20
PAD T97
PAD T24
PAD T96
PAD T102
PAD T95
PAD T94
PAD T93

DDR

2

RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31

AV29
BB23
BA25
AV23

J40
H39
E39
E40
C37
D35
K40

TV

H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24

RSVD

B

PAD T22
PAD T104
PAD T58
PAD T114
PAD T55
PAD T59
PAD T119
PAD T56
PAD T54
PAD T57
PAD T52
PAD T53

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

DPST_PWM
LCD_BLON
L_CLKCTLA
L_CLKCTLB
EDIDCLK
EDIDDATA
DISP_ON

(18) DPST_PWM
(18) LCD_BLON
(4) L_CLKCTLA
(4) L_CLKCTLB
(18) EDIDCLK
(18) EDIDDATA
(18)
DISP_ON

LVDS

2

1

C283
2.2U/10V

2

2

C286
0.01U/25V

1

SM_RCOMP_VOL
1

A

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

CLK

1

C279
2.2U/10V

2

C280
0.01U/25V

2

1

SM_RCOMP_VOH

P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20

PAD T36
PAD T35
PAD T37
PAD T31
PAD T49
PAD T48
R209 PAD T46
3.01K/F PAD T45
PAD T29
PAD T43
PAD T44
PAD T42
PAD T47
PAD T17
R208
1K/F

12

1K/F

DB2 stage:add

D

PM_EXTTS#1

R158

*0

PM_DPRSLPVR (14,39)

PROJECT : OT2
Quanta Computer Inc.
Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

Crestline(VGA,DMI)
7

Sheet

7

of
8

42

2

3

4

5

6

7

8

C

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

SA_CAS#

BL17

DDR_A_CAS#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
BJ29

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

SA_RAS#
SA_RCVEN#
SA_WE#

BE18 DDR_A_RAS#
AY20
*PAD
T51
BA19 DDR_A_WE#

DDR_A_BS0 (16)
DDR_A_BS1 (16)
DDR_A_BS2 (16)
DDR_A_CAS# (16)
DDR_A_DM[0..7] (16)

DDR_A_DQS[0..7]

DDR_A_DQS#[0..7]

(16)

(16)

DDR_A_MA[0..14] (16)

BJ29 renamed to
SA_MA14 pin for intel
update 6/9

DDR_A_RAS# (16)
DDR_A_WE# (16)

AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

MEMORY

BB19
BK19
BF29

SYSTEM

A

SA_BS_0
SA_BS_1
SA_BS_2

MEMORY

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SYSTEM

B

AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11

DDR

U30D
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

B

U30E

(16) DDR_A_D[0..63]
A

DDR

1

SB_BS_0
SB_BS_1
SB_BS_2

AY17
BG18
BG36

SB_CAS#

BE17

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_RAS#
SB_RCVEN#

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
BE24
AV16
AY18

SB_WE#

A

B

BE24 renamed to
SB_MA14 pin for intel
update 6/9

BC17

C

CRESTLINE_1p0

CRESTLINE_1p0

D

D

PROJECT : OT2
Quanta Computer Inc.

1

2

3

4

5

6

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

Crestline(DDR2)
7

Sheet

8

of
8

42

5

4

3

2

+1.05V

1

+3V

JP2
C204
330U/6.3V

1

2

+1.05V

2

2

+

*SHORT PAD

(11)

BL1_DET

B2_DET
BL1_DET
BL51_DET

1
C228
22U/4V

A51 _DET

(11) A51 _DET

2

C210
10U/6.3V

1
C249
0.22U/10V
2

2

C442
22U/4V

C243
0.1U/10V

1

1

2

C234
0.1U/10V
2

1
1

2

C238
0.1U/10V

1

Layout Note:
Inside GMCH cavity.

+1.05VM

C253
0.22U/10V
2

2

C212
1U/10V
2

2

C227
0.47U/10V

1

1

(11) BL51_DET

C233
0.1U/10V
2

2

C216
0.1U/10V

B2_DET

+VCCGFX
1

1

1

Layout Note:
Inside GMCH
cavity for
VCC_AXG.

(11)

Layout Note:
Place close to GMCH edge.

AL24
AL26
AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33
AL29
AL31
AL32
AR31
AR32
AR33

VSS NCTF

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

D

POWER
VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

A3
B2 B2_DET
C1
BL1 BL1_DET
BL51 BL51_DET
A51 A51 _DET

C

+1.05VM

VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

B

CRESTLINE_1p0

C259
1U/10V

2

2

2
1
C267
1U/10V

Layout Note:
Place C2630 where
LVDS and DDR2 taps.

C288
22U/4V

C287
22U/4V

Layout Note:
Place on the edge.
A

2

C276
0.47U/10V
2

C270
0.22U/10V

1

1

1
C269
0.22U/10V

2

C258
0.1U/10V

2

C251
0.1U/10V

C313
330U/6.3V

1

+
C461
0.1U/10V

2

1

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

1

1

1.8VSUS

PROJECT : OT2
Quanta Computer Inc.

CRESTLINE_1p0

5

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS SCB

C429
330U/6.3V

+

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50

VCC AXM

1

1

+VCCGFX

AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36
AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36
Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37

VCC NCTF

1
C225
0.1U/10V
2

2

C214
0.22U/10V

2

C217
0.22U/10V

2

C223
22U/4V

1

1

1

1
2

C425
220U/2.5V

+VCCGFX

Layout Note:
370 mils
from edge.

1

AW45
BC39
BE39
BD17
BD4
AW8
AT6

2

Layout Note:
Inside GMCH cavity.

2

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

+

Layout Note:
370 mils from edge.

1

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

D10
1

+1.05V

2

A

R20
T14
W13
W14
Y12
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14

10
2 +VCC_GMCH_L

CH751H-40HPT

1

+VCCGFX
B

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

2

C

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC GFX NCTF

AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30

VCC SM

POWER

1.8VSUS

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC SM LF

VCC_13

VCC CORE

R30

U30F
R157
1

VCC GFX

D

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC AXM NCTF

U30G
AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32

4

3

2

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

Crestline_D(VCC,NCTF)
Sheet
1

9

of

42

5

4

3

2

1

+3V
U30H

VCCA_MPLL

+VCC_TX_LVDS

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

L28

+ C273
470U/4V

1

K49
C207
0.1U/10V

C202
0.1U/10V

+VCCA_PEG_PLL

VTT

PLL

2
1

C193
1U/10V

VCCD_QDAC
VCCD_HPLL

U48

VCCD_PEG_PLL
VCCD_LVDS_1
VCCD_LVDS_2

2

AXF

1.8VSUS

+VCC_TX_LVDS

2
1

A43
C40
B40

VCC_RXR_DMI_1
VCC_RXR_DMI_2

AH50
AH51

2
C199
0.1U/10V

C192
220U/4V

+VCC_PEG

VTTLF1
VTTLF2
VTTLF3

A7
F2
AH1

+1.05V

L38
2
1

+VCC_RXR_DMI

1
91nH/1.5A

1

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

AD51
W50
W51
V49
V50

+

C195
1000P/50V
2

VCC_HV_1
VCC_HV_2

1
1uH/300MA

1

+3V

91uH+-20%_1.5A

+
C282
220U/4V

C222
10U/6.3V
+1.05V

+VTTLF1
+VTTLF2
+VTTLF3

L34
2

C447
220U/4V

C229
10U/6.3V

2

2

CRESTLINE_1p0

C196
0.47U/10V

R130

C175

1

2

C177
+VCCQ_TVDAC_R
*22nF

A

100 R133
C658
1U

FB_180ohm+-25%_
100mHz_1500mA_
0.09ohm DC

C182
0.1U/10V

C659
.1U

PROJECT : OT2
Quanta Computer Inc.

C184
1

*22nF

2

1

C183

2

L18
1
2 +VCCQ_TVDAC
BLM18PG181SN1

2

C165
0.1U/10V

*CH751H-40HPT

TV DAC Voltage Follower Circuit -700 mV.

2

*10
2

C285
10U/6.3V
2

1

*22nF

+VCC_TVDACC_R

1

R128
1 +VCC_TVDAC_L 1

+VCC_SM_CK_L

+VCCD_TVDAC_R

R131

+VCC_TVDACC
1

+1.5V

0

R196
1/F/0603
C281
0.1U/10V

2

0

2

2

1

C456
22U/10V

+1.5V

1uH+-20%_300mA

12

+VCC_TVDACB_R

1

1

R129

C162
0.1U/10V

1.8VSUS

L39
1uH/300mA
2
1

+VCC_SM_CK
1

2

C200
0.47U/10V
2

C232
0.47U/10V

*22nF

1

1

1

+VTTLF1
+VTTLF2
+VTTLF3

A

+3V

B

1
91nH/1.5A

91uH+-20%_1.5A

+

C187
10U/6.3V

2
1
0

+VCC_TVDACB

1

*22nF

C

2

SM CK

1

Place caps close
to VCC_AXF

1uH+-20%_300mA

1

1
2

+1.25V
C224
0.1U/10V

+VCC_SM_CK

C194
10U/6.3V

2

N28
AN2

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

BK24
BK23
BJ24
BJ23

VCC_TX_LVDS

C164
0.1U/10V

22nF

SI stage:change R133 to 100ohm and
C658,C659,C184 install
5

Place caps close
to VCC_AXD.

2

VCCD_CRT
VCCD_TVDAC

C166

2

C160
0.1U/10V

C149
0.1U/10V

2

1

R118 0/F
2
1

1

2

+VCC_TVBG

C154

D9
2

+VCC_AXF

+VCC_AXF

1

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

+VCC_TVDACA_R

1

1
2

R121

+VCC_TVBG_R

0

C457
22U/10V

R123

2

0

M32
L29

J41
H42

C205
1U/10V
0

C181
10U/4V

C257
1U/10V

R140

Reserved L2612 pad
for inductor.

1

1.8VSUS

+VCC_TVDACA

22nF & 0.1uF for
VCC_TVDACA:C_R should
be placed with in 250
mils from Crestline.

2
0

L32

L25

VCCA_SM_CK_1
VCCA_SM_CK_2

2

2

C215
0.1U/10V

0

FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC
L16
1
2
BLM18PG181SN1

1

2

1

2

1

2

+VCCA_PEG_PLL
R138

C25
B25
C27
B27
B28
A28

AJ50

2

1

+VCCQ_TVDAC_R

C242
0.1U/10V

+3V

+VCC_AXD_L

1

1

+1.25VM
C220
0.1U/10V

C219
10U/6.3V

B

+1.25V

2

+VCC_TVDACC_R

+VCCD_TVDAC_R

12

FB_220ohm+-25%_100MHz
_2A_0.1ohm DC

+3V

+1.25VM

B23
B21
A21

VCC_DMI

VTTLF

+VCC_TVDACB_R

VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

HV

+VCC_TVDACA_R
C278
0.1U/10V

2

1

1

C272
1U/10V

2

1

C260
1U/10V

2

1

C271
22U/4V

L29
+VCCA_PEG_PLL
1
2
BLM21PG221SN1D
R177
1/F/0603

AR29

PEG

BC29
BB29

+VCCA_SM_CK

POWER

DMI

1

C240
1U/10V

2

C264
22U/4V

2

1

1
2

2
1

C261
22U/4V

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5

A SM

AT22
AT21
AT19
AT18
AT17
AR17
AR16

1
2

C241
4.7U/6.3V

0

2

+1.25V

VCC_AXD_NCTF

A CK

2

+ C454
100U/6.3V

R189

+ C198
220U/4V

2

1
2

+1.25VM

+1.25VM

VCCA_PEG_PLL

AT23
AU28
AU24
AT29
AT25
AT30

TV

2

2

AW18
AV19
AU19
AU18
AU17

C244
0.1U/10V

C255
22U/10V

U51

VSSA_PEG_BG

C231
4.7U/10V

2

0.1Caps should be
placed 200 mils
with in its pins.

1

+VCCA_MPLL

+VCCA_MPLL_L

C

1 +VCCA_DPLLB
10uH/100MA
1

2

1

L31
BLM11A121S
2
1
R186
0.5/F/0603
1
2

C226
0.47U/6.3V

Place on the edge.

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6

AXD

2

C245
0.1U/10V

+3V

2

2

C250
22U/10V

C197
0.1U/10V

2

1

+ C201
470U/4V

1

VCCA_HPLL

AM2

A PEG

+VCCA_HPLL

1
BLM11A121S
1

2

C191
1000P/50V
2
1

+VCCA_DPLLA

D TV/CRT

L30

1
10uH/100MA

1

VCCA_DPLLB

AL2

+VCCA_MPLL

LVDS

2

10uH+-20%_100mA

1

L26

1

FB_120ohm+-25%_100mHz
_200mA_0.2ohm DC

+1.25VM

2

H49

+VCCA_HPLL

1

+VCCA_DPLLB

A LVDS

40mA MAx.
+1.25V

2

1

2

45mA MAx.

D

R127
*10

Place on the edge.

1

VCCA_DPLLA

1

B49

+1.05V

2

+VCCA_DPLLA

D

+VCC_HV_L

2

VSSA_DAC_BG

1

VCCA_DAC_BG

B32

2

A30

D8
*CH751H-40HPT

C188
4.7U/10V

1

+VCC_TVBG_R

*22nF

C221
2.2U/6.3V

2

C190

1

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

2

C185
0.1U/10V

C176
0.1U/10V

2

A33
B33

1

+VCCA_CRTDAC_R
1

+VCCA_CRTDAC_R

+1.05V

VCC_HV

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

2

+VCCA_CRTDAC

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

1

VCCSYNC

2

J32
R135

1

+3V

0

2

L17
1
2
BLM18PG181SN1

CRT

FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC

4

3

2

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

Crestline_E(POWER)
Sheet
1

10

of

42

5

4

3

2

1

SI stage: add test pin
+3V

U30I

R202

U30J

B

A

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

100K
R203
100K

3

VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

D

(9)

BL1_DET 2

BL1_DET

2N7002E
R206
*0

T162

+3V

Q14
1

K12
K47
K8
L1
L17
L20
L24
L28
L3
L33
L49
M28
M42
M46
M49
M5
M50
M9
N11
N14
N17
N29
N32
N36
N39
N44
N49
N7
P19
P2
P23
P3
P50
R49
T39
T43
T47
U41
U45
U50
V2
V3

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

R204

100K
R207
100K

(9)

3

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

B2_DET

B2_DET

2
C

2N7002E
R205
*0

T163

Q13
1

C46
C50
C7
D13
D24
D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36
F4
F40
F50
G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48
G8
H24
H28
H4
H45
J11
J16
J2
J24
J28
J33
J35
J39

VSS
+3V

R200
BGA_MON_DET (14,26)
100K
R193
100K
3

VSS

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

(9)

A51 _DET

A51 _DET

2

2N7002E
R194
*0

T164

Q12
1

C

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

B

+3V
R201
100K

R216

3

D

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

100K
(9)

BL51_DET

BL51_DET

CRESTLINE_1p0

2

2N7002E
T165

R217
*0

Q15
1

A13
A15
A17
A24
AA21
AA24
AA29
AB20
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AL1
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16

A

CRESTLINE_1p0

PROJECT : OT2
Quanta Computer Inc.

5

4

3

2

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

Crestline(VSS)
Sheet
1

11

of

42

1

2

3

4

5

6

1
R407
332K/F

R421
332K/F
ICH_LAN100_SLP
2
1

2

ICH_INTVRMEN

1

VCCRTC

8

VCCRTC

1

VCCRTC

7

A

A

C335
18P

+1.05V

(24)
(24)
(24)
(24)
(24)
(24)
C521 C526 C341

C339

*10P

*22P

*10P

*10P

LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2

R401 24.9/F
1
2 GLAN_COMP

+1.5V_PCIE_ICH

R476

(22,23) ACZ_RST_ADI#

33
33

ACZ_BCLK
ACZ_SYNC

33

ACZ_RST#

(30) ACZ_BITCLK_MDC
(30) ACZ_SYNC_MDC
(30) ACZ_RST_MDC#
(30) ACZ_SDOUT_MDC

R471

33

R240
R243
R470
R464

33
33
33
33

ACZ_SDOUT
JP5
2

*10P

LAN_TXD0
LAN_TXD1
LAN_TXD2
GLAN_DOCK#/GPIO13

D25
C25

GLAN_COMPI
GLAN_COMPO

AJ16
AJ15

HDA_BIT_CLK
HDA_SYNC

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

AE13

HDA_SDOUT

T129

AE10
AG14

HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34

T132

AF10

SATALED#

T158
T159
T160
T161

AF6
AF5
AH5
AH6

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

T73
T75

AG3
AG4
AJ4
AJ3

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

T144
T78

AF2
AF1
AE4
AE3

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

T171
T172

AB7
AC6

SATA_CLKN
SATA_CLKP

R518 *24.9/F
2
1 SATABIAS

AG1
AG2

SATARBIAS#
SATARBIAS

1

*SHORT PAD

C514 C517 C340 C337
*10P

D21
E20
C20

HDA_RST#

(29) G_BATLED#

C

LAN_RXD0
LAN_RXD1
LAN_RXD2

AJ17
AH17
AH15
AD13

T68
T131
(22) ACZ_SDOUT_ADI

C21
B21
C22

AE14

ACZ_SDIN0
ACZ_SDIN1

(22) ACZ_SDIN0
(30) ACZ_SDIN1

LAN_RSTSYNC

AH21

(25) ENERGY_DET

R242
R244

(22) ACZ_BITCLK_ADI
(22) ACZ_SYNC_ADI

GLAN_CLK

*10P

G9
E6

PAD
PAD

A20GATE
A20M#

AF13
AG26

DPRSTP#
DPSLP#

AF26
AE26

FERR#

AD24

CPUPWRGD/GPIO49

AG29

IGNNE#

AF27

INIT#
INTR
RCIN#

AE24
AC20
AH14

NMI
SMI#

AD23
AG28

GATEA20

2

2

+3V

H_DPRSTP# (4,7)

B

H_DPSLP# (4)

H_FERR# (4)
0/F

R466
10K

H_PWRGOOD (4)

R468
10K

H_IGNNE# (4)
GATEA20
KBCCPURST#

H_INIT# (4)
H_INTR (4)

KBCCPURST#

KBCCPURST# (26)
H_NMI (4)
H_SMI# (4)

STPCLK#

AE27

THERMTRIP#_ICH

TP8

AA23

PAD

H_STPCLK# (4)

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15

V1
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

DA0
DA1
DA2

AA4
AA1
AB3

PDA0
PDA1
PDA2

DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ

0/F H_DPRSTP#
0/F
H_DPSLP#

H_FERR#
R126

R417
56

GATEA20 (26)
H_A20M# (4)

R393
R396

THRMTRIP#

Y6
Y5

H_DPRSTP#
H_DPSLP#
H_FERR#

T136
T141

AA24

DCS1#
DCS3#

LFRAME#/FWH4 (26,30)

R395
*56

1

LDRQ0#
LDRQ1#/GPIO23

R390
*56
1

C4

IDE

B

B24
D22

FWH4/LFRAME#

LFRAME#/FWH4

(26,30)
(26,30)
(26,30)
(26,30)

2

(24) GLAN_CLK
(24) LAN_RSTSYNC

INTVRMEN
LAN100_SLP

LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3

1

ICH_INTVRMEN AF25
ICH_LAN100_SLP AD21

INTRUDER#

LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3

2

AD22

E5
F5
G8
F6

1

RTCRST#

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

2

RTCX1
RTCX2

AF23

1

INTRUDER#

AG25
AF24

CPU

CLK_32KX2

LAN / GLAN

C336
18P

1
2

RTC
LPC

U17A

IHDA

CN32

BAT_CONN

R238
10M

SATA

Y5
32.768KHZ

2

G1
SHORT_ PAD1

2

C485
1U

R420
1M/F

1

CLK_32KX1

1

D18
CH500H-40

*10P

2

R414
20K

VCCRTC_2

R415
1K

R424
*0

2

D19
CH500H-40

R413
*0

C482 1U

VCCRTC

3VPCU

R384

24.9/F

PM_THRMTRIP# (4,7)
R383

T121

1

PDD[15:0] (28)

2
+1.05V
56

C

PDA[2:0] (28)

PDCS1#
PDCS3#

PDCS1# (28)
PDCS3# (28)

W4
W3
Y2
Y3
Y1
W5

PDIOR# (28)
PDIOW# (28)
PDDACK# (28)
IRQ14
(28)
PDIORDY (28)
PDDREQ (28)

+3V

ICH8M REV 1.0
R958
8.2K

R959
4.7K

2

+3V

R462
*1K
1

D

PDIORDY
IRQ14

D

ACZ_SDOUT
ICH_RSVD (14)

2

PROJECT : OT2
Quanta Computer Inc.

1

R239
*1K

1

2

3

4

5

6

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

ICH8(CPU,SATA,IDE)
7

Sheet

12

of
8

42

1

2

3

4

5

6

7

8

MINI CARD PCI-E
PCIE_RXN2
PCIE_RXP2
PCIE_TXN2_C
PCIE_TXP2_C

PERN3
PERP3
PETN3
PETP3

H27
H26
G29
G28

PERN4
PERP4
PETN4
PETP4

F27
F26
E29
E28

PERN5
PERP5
PETN5
PETP5

PCIE_RXN6
PCIE_RXP6
PCIE_TXN6_C
PCIE_TXP6_C

D27
D26
C29
C28

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

SPI_CS1_R#

C23
B23
E22

SPI_CLK
SPI_CS0#
SPI_CS1#

D23
F21

SPI_MOSI
SPI_MISO

Intel LAN
0.1U
0.1U

(31)
SPI_CLK
(31)
SPI_CS0#
(14,26) SPI_CS1#

PV stage:change R399 to 15 ohm for intel request
(31)

SPI_SI

(31)

SPI_SO

SI2 stage:Change power source to avoid leakage
current

(30)

0/F

R456

BT_OFF

USBOC#0
USBOC#1
USBOC#2
USBOC#3
USBOC#4
USBOC#5
USBOC#6
USBOC#7
USBOC#8
USBOC#9

0/F

R455

(19) WWAN_OFF#

3V_S5

B

R399 15
R409

0/F

RP31
6
7
8
9
10

5
4
3
2
1

USBOC#7
USBOC#2
USBOC#1
USBOC#8

USBOC#0

8.2KX8
SI stage:Change power source to avoid leakage current
3V_S5

R241
8.2K

C644 1

OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#

USBOC#2

C646 1

2 0.1U/10V

USBOC#4

C647 1

2 0.1U/10V

USBOC#6

C649 1

2 0.1U/10V

USBOC#7

C650 1

2 0.1U/10V

USBOC#8

C651 1

2 0.1U/10V

USBOC#9

C652 1

2 0.1U/10V

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB26
AB25
AA29
AA28

DMI_MTX_IRX_N2 (7)
DMI_MTX_IRX_P2 (7)
DMI_MRX_ITX_N2 (7)
DMI_MRX_ITX_P2 (7)

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

AD27
AD26
AC29
AC28

DMI_MTX_IRX_N3 (7)
DMI_MTX_IRX_P3 (7)
DMI_MRX_ITX_N3 (7)
DMI_MRX_ITX_P3 (7)

T26
T25

DMI_ZCOMP
DMI_IRCOMP

Y23
Y24

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

USBRBIAS#
USBRBIAS

F2
F3

DMI_COMP

D

INTC#
INTD#

INTA#
INTB#
INTC#
INTD#

F9
B5
C5
A10

PCI

A4
D7
E18
C18
B19
F18
A11
C10

C/BE0#
C/BE1#
C/BE2#
C/BE3#

C17
E15
F16
E17

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

C8
D9
G6
D16
A7
B7
F10
C16
C9
A17

IRDY#
PAR
PCI_RST#_G
DEVSEL#
PERR#
LOCK#
SERR_1#
STOP#
TRDY#
FRAME#

PLTRST#
PCICLK
PME#

PLT_RST-R#
AG24
B10 CLK_PCI_ICH
PCI_PME#
G7

PAD
PAD
PAD
PAD

T74
T140
T127
T123
REQ2#
GNT2#

PAD
PAD

SI stage:add to avoid leakage currurt

PAD
PAD
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+

PAD
PAD

USBP7USBP7+
USBP8USBP8+
T146
T79

Place within 500mils of ICH8

SYSTEM(RIGHT)

3V_S5

R448

+3V
B

RP30

USBRBIAS

6
7
8
9
10

STOP#
+3V

REQ2#
REQ1#
FRAME#
DEVSEL#

8.2KX8
+3V
RP32
INTF#
INTG#
REQ3#
INTD#

6
7
8
9
10

+3V

5
4
3
2
1

TRDY#
SERR_1#

8.2KX8

GNT0#

SPI_CS1#

LPC

11

No stuff

No stuff

PCI

10

No stuff

Stuff

SPI

01

Stuff

No stuff

2

5
4
3
2
1

R512
22.6/F

+3V
RP33
IRDY#
INTA#
INTE#
LOCK#

(20)
(20)

+3V

T70
T134

6
7
8
9
10

5
4
3
2
1

REQ0#
INTB#
INTC#
PERR#

C

8.2KX8
+3V
C/BE0#
C/BE1#
C/BE2#
C/BE3#

(20)
(20)
(20)
(20)

IRDY#
PAR

(20)
(20)

C539
1
2

PCI DEVICES IRQ ROUTING
DEVICE

IDSEL # REQ/GNT # PCI_INT

Add Buffers as needed for
Loading and fanout concerns.

0.047U/10V

U36

2
4
PCI_RST#_G

DEVSEL# (20)
PERR# (20)

CardBus

AD22

2

1

C,D,E

SERR_1# (20)
STOP# (20)
TRDY# (20)
FRAME# (20)

PCIRST# (20)

7SH32
R489
*0
+3V

R990
100K

C490
1
2
0.047U/10V
PLT_RST-R# (7)

DB1A stage:add
U32

2

CLK_PCI_ICH (17)
PCI_PME# (20)

4
PLT_RST-R#

PLTRST# (19,26,28,30)

1
7SH32

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

F8
G11
F12
B3

INTE#
INTF#
INTG#
SES_INT

INTE#

R991
100K

(20)

SES_INT (27)

PROJECT : OT2
Quanta Computer Inc.

C525
*8.2P/16V
1

3

D

R479
*10

Reserved for EMI.
Place resister and cap
close to ICH.
2

USBOC#5

(30) USBOC#5

USBP5- (30)
SYSTEM(LEFT)
USBP5+ (30)
USBP6- (30)
Bluetooth Module
USBP6+ (30)
(32)
(32) Docking
(19)
(19) WWAN

ICH8M REV 1.0

1

8.2K

SI stage:Change power source to avoid leakage current

FINGER PRINT
DB1A stage:change for HP
request

CLK_PCI_ICH

Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

(26)

A

2

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

R411
*1K

SERR#

21

C

D20
E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15
B6
C11
A9
D11
B12
C12
D10
C7
F13
E11
E13
E12
D8
A6
E8
D6
A3

R501
1K
1

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PAD
PAD
PAD
PAD
T155
T156

USBP1- (30)
USBP1+ (30)
T77
T76
T149
T145

Boot BIOS Strap

2

U17B

SERR#

1

CH751H-40HPT

+1.5V_PCIE_ICH
USBP0- (30)
USBP0+ (30)

USBP1+
USBP2USBP2+
USBP3USBP3+

SPI_CS1_R#
GNT0#

(20) AD[31..0]

24.9/F
1

USBP0USBP0+

Short F2 and F3 at the package
and keep length to less than
500mils. Trace Impedance
should be 60ohms +/- 15%.

SI stage:add to avoid WWAN Noise

D33
2

SERR_1#

CLK_PCIE_ICH# (17)
CLK_PCIE_ICH (17)
R412
2

ICH8M REV 1.0

USBOC#9

(20)
(20)

DMI_MTX_IRX_N1 (7)
DMI_MTX_IRX_P1 (7)
DMI_MRX_ITX_N1 (7)
DMI_MRX_ITX_P1 (7)

DMI_CLKN
DMI_CLKP

USB

2 0.1U/10V

Y27
Y26
W29
W28

1

3V_S5

USBOC#3
USBOC#4
USBOC#0
USBOC#6

AJ19
AG16
AG15
AE15
AF15
AG17
AD12
AJ18
AD14
AH18

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

5

C468
C467
R398 15
R403 15
R410 15

PERN2
PERP2
PETN2
PETP2

K27
K26
J29
J28

A

(24) PCIE_RXN6
(24) PCIE_RXP6
(24) PCIE_TXN6
(24) PCIE_TXP6

M27
M26
L29
L28

DMI_MTX_IRX_N0 (7)
DMI_MTX_IRX_P0 (7)
DMI_MRX_ITX_N0 (7)
DMI_MRX_ITX_P0 (7)

5

0.1U
0.1U

V27
V26
U29
U28

2

C466
C465

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

1

PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2

PERN1
PERP1
PETN1
PETP1

SPI

(19)
(19)
(19)
(19)

P27
P26
N29
N28

PCI-Express
Direct Media Interface

U17D

4

5

6

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

ICH8(USB,PCIE,DMI)
7

Sheet

13

of
8

42

1

2

3

3V_S5

R972 2

1 10K

R969

R1052

ICH_RI#

AF17

RI#

F4
AD15

SUS_STAT#/LPCPD#
SYS_RESET#

AG12

BMBUSY#/GPIO0

AG22

SMBALERT#/GPIO11

5

AH11

PCIE_WAKE#
SERIRQ

(19) PCIE_WAKE#
(20,26,30) SERIRQ

SI2 stage:add R1049 to modify CLK_PWRGD timing to avoid CPU frequency
R385
0
4 error
NL17SZ14DFT2G

R1049
100K_4

R941

T65

*0

AJ20

VRMPWRGD

AJ22

TP7

OCP#

OCP#

(26) RUNSCI_EC#

*0

PR_INSERT#

(7) MCH_ICH_SYNC#

R247 2

PCSPK

AD9
AJ13

MCH_SYNC#

AJ21

TP3

C

(12) ICH_RSVD

No Reboot strap.

PR_INSERT#

Low = Default.
High = No
Reboot.

PCSPK

SPKR

AG9
G5

CLK_ICH_14M
CLK_ICH_48M

SUSCLK

D3

ICH_SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

AG23
AF21
AD18

S4_STATE#/GPIO26

AH27

PWROK

AE23

DPRSLPVR/GPIO16

AJ14

BATLOW#

AE21

CLK14
CLK48

PAD

SLP_S3# (26,31)
SLP_S4# (37)
SLP_S5# (31)

ICH_PWROK (31)

C2
AH20

RSMRST#

AG27

PM_RSMRST#_R R400

CK_PWRGD

E1

R388

CLPWROK

E3

MPWROK

F23
AE18

CL_DATA0
CL_DATA1

F22
AF19

CL_VREF0
CL_VREF1

D24
AH23

CL_RST#

AJ23

MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14
WOL_EN/GPIO9

AJ27
AJ24
AF22
AG19

R245
DB1A stage:Add 100R
1

PM_DPRSLPVR_R

PWRBTN#

CL_CLK0
CL_CLK1

+3V

C536
*4.7P/50V

S4_STATE (40)

LAN_RST#

AJ25

R491
*10

T147

ICH_PWROK

0

ICH_PWROK

R418 2

1 *10K

LAN_WOL_EN

R437 1

2 *100K

PM_RSMRST#_R

R404 2

1 *10K

MPWROK

R507 2

1 *1M

PM_DPRSLPVR_R

R955 1

2 100K

RSMRST# (26)

CLK_PWRGD (17)
MPWROK (7,31)

CL_CLK0 (7)
ICH_CL_CLK1 (19)
CL_DATA0 (7)
ICH_CL_DATA1 (19)
CL_VREF0
CL_VREF1

DB1A :reserve 100k
ohm

ICH_CL_RST0# (7)
R408 2
1 0

CB_IN#
R231 2
LAN_WOL_EN

+3V

R517

DB1A :no install
R418,due to dual layout

NBSWON# (31)
LAN_RST# (25)
100/F RSMRST#

B

PM_DPRSLPVR (7,39)
BATLOW# (26)

SUSM_1#

1 0

DB1A stage:delete
R431

RF_OFF# (19)
DET_P
AMT ADP_PRES (26)

(25)
C

LAN_WOL_EN (40)
3V_S5
100K
2

PV stage:Add for intel suggestion
R511

+3VM
2

100K

R392
3.24K/F

A1_DET

AJ1_DET

2
1

(15) AJ1_DET

2N7002E
R516
*0

Q42

CL_VREF0
R252
*0

2N7002E

R419
453/F

2
BGA_MON_DET (11,26)

3

T166

C486
0.1U/10V

3

BGA_MON_DET (11,26)
100K

100K R253 AJ1_DET

D

R513

+3V

R402
453/F

2

1

1

R508

100K R515 A1_DET

MCH_ICH_SYNC#_R

C483
0.1U/10V

2

+3V
+3V

CL_VREF1

Q41
1

+3V

DB1A stage:add for
pr_insert_dock#

R416
3.24K/F

2

A1_DET

1

(15)

3V_S5

BGA_MON_DET (11,26)

1

+3V

12

CLK_ICH_14M (17)
CLK_ICH_48M (17)

D26
PM_BATLOW#_R
2
CH751H-40HPT
NBSWON#
2 R428 0 1
2 R397 *01

SLP_M#

CLK_ICH_14M

T137

2 R430 0 1
2 R440 0 1

100K

2

ACC_LED (29)
NPCI_RST# (26)
PAD

R1063
1

PR_INSERT# (22,27)

R961
10K

R246
*10K

8.2K

NPCI_RST#
SATA3GP

BGA_MON_DET (11,26)

2

C550
*4.7P/50V

3

1

R970

AJ12
AJ10
AF11
AG11

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37

ICH8M REV 1.0

D24
PDZ5.6B
(25,32) PR_INSERT_DOCK#

+3V

3

PCSPK

TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
GPIO8
GPIO12
TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48

1 0 MCH_ICH_SYNC#_R

1

(22)

CLKRUN#/GPIO32
WAKE#
SERIRQ
THRM#

2

R940

STP_PCI#/GPIO15
STP_CPU#/GPIO25

AE17
AF12
AC13

AJ8
AJ9
AH9
AE16
(7,31,39) DELAY_VR_PWRGOOD
(18) LID_SW#
LAN_PHYPC_R AC19
2 R1065 *01
(25) LAN_PHYPC
AG8
GPIO18AH12
T71
GPIO20AE11
2 R1066 0 1
T133
(13,26) SPI_CS1#
+3V
GPIO22AG10
T139
PV stage:add option (Add R1066)from LAN_PHYPC and
DB1A stage:delete
AH25
T63
reserve R1065
AD16
T157
Q32,R394,add U46,C628 to
(18)
ALS_EN#
AG13
T170
control VRMPWRGD
SI2 stage:delete R467 ,add T170 test
SLOAD
AF9
T138
R492
SDATAOUT0
point
AJ11
T72
*10K
SDATAOUT1 AD10
T135
(34)

CLK_PWRGD

(26,31)

1

R472
10K/F

1 0 AE20
1 0 AG18

CLKRUN#

(20,26,30) CLKRUN#

SUSM#

SI2 stage:delete Q61,add R1051

1

C628 .1U/16V/04

0

2

R457 2
R442 2

(17) H_STP_PCI#
(17) H_STP_CPU#

R1051

2

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

SMB

AJ26
AD19
AG21
AC17
AE19

PV stage:R442 install for intel suggestion

+3V

A

U17C

PCLK_SMB
PDAT_SMB
ICH_CL_RST1#
R1012
0
R1013
0

SMBALERT#

+3V

CLK_ICH_48M
R495
*10

SUSM_1#

PM_BMBUSY#

(7) PM_BMBUSY#

U46

GPIO29 (26)

DB1A stage:no
install R423,due to SI2 stage:delete D32,Add
R1052
dual pull up

(30) SUS_STAT#
(4,31) XDP_DBRESET#

DB1A stage:change R473 to 10k refer to
intel schematic

Place these close to ICH8.

PV stage:no install R441,R434
for intel request

SI stage: add to avoid leakage current

Clocks SATA
GPIO

DB2 stage:reserve 0
ohm

(4) THERM_ALERT#

H_STP_PCI#
H_STP_CPU#

0

1

10K CB_IN#
*10KICH_CL_RST1#
10K ME_EC_CLK
10K ME_EC_DATA
10K ICH_RI#
*10KOCP#
1K PCIE_WAKE#
10K XDP_DBRESET#

(16,17) PCLK_SMB
(16,17) PDAT_SMB
(19) ICH_CL_RST1#
(26) ME_EC_CLK
(26) ME_EC_DATA

1 10K
8.2K
1 10K
1 10K

1
2
3

8.2K NPCI_RST#

R434
*10K

2

1
1
1
1
1
1
1
1

SYS
GPIO
Power MGT

+3V

(39) VR_PWRGD_CLKEN#

R971

R441
*10K

SI stage: install to avoid leakage current
DB1A stage:Add,refer to
PM_BMBUSY#
Oak schematic

DB1A stage:add R962 refer to
Oak schematic

B

GPIO20

1 10K LAN_PHYPC_R

2
2
2
2
2
2
2
2

R960 *8.2K
DB1A stage:change R487 to 8.2K ,and pull
up to
DB2 stage:no install R960 to avoid leakage current

1 1K

8.2K

1

R405
R425
R453
R435
R451
R423
R454
R452

SI stage:add R1028 ,Q62,reserve R1029 for
auto power on issue

R480 2

GPIO22

R965
MPWROK

12

(24,25,32) LAN_LINKLED#

SLOAD

GPIO18

8.2K

2

2

1

2

*0

1 10K

8.2K

R964

1

R1029

A

RUNSCI_EC# R490 2

R963
RF_OFF#

1 10K

R962 2

2N7002E

1

100K

D

T167
100K R219 A29_DET

(15) A29_DET

T168

A29_DET

2

(15) AJ29_DET

AJ29_DET 2

100K R391 AJ29_DET
RP29

T169

DB1A stage:change to
3V_S5

2N7002E
R224
*0

2 PDAT_SMB
4 PCLK_SMB

1
3

Q18

2N7002E
R389
*0

1

3V_S5

PROJECT : OT2
Quanta Computer Inc.

SI stage: add test pin

4P2R-2.2K

1

Q31
1

1

31

Q62
2

R485 2
R487
R473 2
R483 2

8

SMBALERT#

R482
*10

SDATAOUT0
SATA3GP
SERIRQ
SDATAOUT1

7

DB1A stage:Add,refer to
Oak schematic

8.2K PM_BATLOW#_R

R966 2

(26,31) SLP_S3#

6

+3VM

10K

CLKRUN#

5

+3V

R1028

R481
8.2K

1

4

DB1A stage:Add,refer to
Oak schematic

3V_S5

MISC
GPIO
Controller Link

Option to " Disable "
clkrun. Pulling it down
will keep the clks
running.

2

2

+3V

2

3

4

5

6

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

ICH8(PM,GPIO,SMB)
7

Sheet

14

of
8

42

1

2

3

4

5

VCCRTC
2

U17F

1

12

+VCCSATPLL_L

C540
1U/10V
2

L49
10uH/100MA

+VCCSATPLL

VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

AC1
AC2
AC3
AC4
AC5

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

AC10
AC9

VCC1_5_A[11]
VCC1_5_A[12]

AA5
AA6

VCC1_5_A[13]
VCC1_5_A[14]

2

2

1

1

C464
22U/10V

2

2

1

C528
0.1U/10V

1
1

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

C480
0.1U/10V

C484
0.1U/10V

C495
4.7U/10V

2

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

+V_CPU_IO
1

AA3
U7
V7
W1
W6
W7
Y7

0/0805

+3V

1

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

R446

2

1

C471
0.1U/10V

2

1

2
+V_CPU_IO

1

C558
0.1U/10V

C470
0.1U/10V

C544
0.1U/10V

C580
0.1U/10V

C578
0.1U/10V

3V_S5

VCCHDA

AC12

VCCSUSHDA

AD11

VCCSUS1_05[1]
VCCSUS1_05[2]

J6
AF20

TP_VCCSUS1.05_1
TP_VCCSUS1.05_2

VCCSUS1_5[1]

AC16

TP_VCCSUS1.5_1

VCCSUS1_5[2]

J7

TP_VCCSUS1.5_2

VCCSUS3_3[01]

C3

VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
VCCSUS3_3[06]

AC18
AC21
AC22
AG20
AH28

VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

+3V

2

1

2

2

C481
4.7U/6.3V
+3V

A24

VCCGLANPLL

A26
A27
B26
B27
B28

VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

B25

2

2
1

1

1

C560
0.1U

2

1
2

1
C654

C655

C656

C577
4.7U/10V

SI stage:change size
to 0805
DB2 stage:change C561,C560,C577 for intel recommend

VCCCL1_05

G22

TP_VCCCL1.05

VCCCL1_5

A22

+VCCCL1_5

VCCCL3_3[1]
VCCCL3_3[2]

F20
G21

C487
*0.1U/10V

4

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

A

B

C

A1_DET (14)
A29_DET (14)
AJ1_DET (14)
AJ29_DET (14)

ICH8M REV 1.0

D

PROJECT : OT2
Quanta Computer Inc.

C488
*1U/10V

ICH8M REV 1.0
3

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

PAD T122

+3VM

VCCGLAN3_3

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]

2

0.1U/10V 0.1U/10V 0.1U/10V 0.1U/10V

1

1
+1.5V_PCIE_ICH
C319
10U/6.3V

VCCLAN3_3[1]
VCCLAN3_3[2]

C561
0.1U

A23
A5
AA2
AA7
A25
AB1
AB24
AC11
AC14
AC25
AC26
AC27
AD17
AD20
AD28
AD29
AD3
AD4
AD6
AE1
AE12
AE2
AE22
AD1
AE25
AE5
AE6
AE9
AF14
AF16
AF18
AF3
AF4
AG5
AG6
AH10
AH13
AH16
AH19
AH2
AF28
AH22
AH24
AH26
AH3
AH4
AH8
AJ5
B11
B14
B17
B2
B20
B22
B8
C24
C26
C27
C6
D12
D15
D18
D2
D4
E21
E24
E4
E9
F15
E23
F28
F29
F7
G1
E2
G10
G13
G19
G23
G25
G26
G27
H25
H28
H29
H3
H6
J1
J25
J26
J27
J4
J5
K23
K28
K29
K3
K6

2

+VCCGLANPLL

C493
0.1U/10V

VCCLAN1_05[1]
VCCLAN1_05[2]

F19
G20

C653

2

T128PAD
T124PAD

3V_S5

1

VCC1_5_A[25]

C538
0.1U/10V

SI stage:WWAN Noise -ICH improvements

1

W23

C545
0.1U/10V

PAD T142

1

VCC1_5_A[20]
VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

GLAN POWER

1

F1
L6
L7
M6
M7

TP_VCCSUSLAN1 F17
TP_VCCSUSLAN2 G18

2

1uH+-20%_800mA
+VCCGLANPLL

VCCUSBPLL

PAD T143
PAD T125
PAD T130

8

2

+3VM

L43
1uH_800MA

VCC1_5_A[18]
VCC1_5_A[19]

D1

1

C546
0.1U/10V

1

12

+VCCGLANPLL_L

2

C469
10U/6.3V

+1.05V

2

2

2
1

C548
0.1U/10V

R225
1

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

USB CORE

+1.5V

2

AC8
AD8
AE8
AF8

2

0/0805

+1.25V

1

+1.5V

1

C472
0.01U/25V

2

AC7
AD7

+1.5V

1

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

+1.5V

L42
R226
1uH_800MA
2
1+1.5V_DMIPLL_R 1

+1.5V_DMIPLL

1

SI stage:Change footprint to 0805

C321
2.2U/10V

VCC3_3[02]

AD2

2
*0/0805

1uH+-20%_800mA

2

G12
G17
H7

D

AF29

*CH751H-40HPT

2

VCCSATAPLL

VCCPSUS

C519
1U/10V
2

C542
10U/6.3V
2

2

C547
1U/10V

VCC3_3[01]

1

1

+1.5V

1

1

C

2

10uH+-20%_100mA

AJ6
AE7
AF7
AG7
AH7
AJ7

ATX

+1.5V

ARX

+VCCSATPLL
R493
0

AC23
AC24

+1.5V

R422
1

2

1

SI stage:Change footprint to 0805

V_CPU_IO[1]
V_CPU_IO[2]

D20
2

1

+1.5V

VCC_DMI[1]
VCC_DMI[2]

AE28
AE29

+1.05V

2

C489
2.2U/10V
1

C316
22U/10V
2

C320
22U/10V
2

2

C297
220U/4V

R29

.022U/04

1

+

VCCDMIPLL

C515

.047U/10V/04

2

2

1

1

1

B

2

+1.5V_PCIE_ICH

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

1

L46
BLM21PG331SN1D

FB_330ohm+-25%_100mHz_
1.5A_0.09 ohm DC

VCCA3GP

1

+1.5V

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

2

2
1

C531
0.1U/10V

CORE

+ICH_V5REF_SUS

1

CH751H-40HPT

VCCP_CORE

D21
2

3VPCU

VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCPUSB

5VPCU

10
2

AA25
AA26
AA27
AB27
AB28
AB29
D28
D29
E25
E26
E27
F24
F25
G24
H23
H24
J23
J24
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
U25
V23
V24
V25
W25
Y25

PCI

1

A

V5REF_SUS

IDE

G4
C543
0.1U/10V

R484
1

V5REF[1]
V5REF[2]

2

CH751H-40HPT

A16
T7

+ICH_V5REF_RUN

1

C518

VCCRTC

1

AD25

D22
2

+3V

DB1A stage:change for check list

1

1

C494
0.1U/10V

2

2

1
100
2

C491
0.1U/10V

2

R447
1

7

U17E

+1.05V
C499
1U/10V

+5V

6

5

6

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

ICH8(POWER,GND)
7

Sheet

15

of
8

42

DDR_A_DM7
DDR_A_D59
DDR_A_D63

D

DDRDAT_SMB
DDRCLK_SMB
+3VM

DDRDAT_SMB
DDRCLK_SMB

FOX_AS0A426-M2SN-7F

SMbus address A0

1

CLOCK 0,1
CKE 0,1
2

1

1

1

1

1

2

2

2

2
1

1
2

2

1

1

1

2

2

2

1
2

R211
*10K/F

1
3

DDR_A_D25
DDR_A_D24

0
SMDDR_VREF_1

DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D31
DDR_A_D27

C296
*0.1U

R212
SMDDR_VREF

2
4

Please these resistor
closely DIMMA,all
trace length<750 mil.

SMDDR_VREF (7,37)

DDR_A_MA8
DDR_A_MA9

2
4

DDR_A_MA3
DDR_A_MA5

2
4

DDR_A_BS0
DDR_A_MA10

2
4

1
3
B

1
3
4P2R-S-56
RP15

+3VM

(8) DDR_A_BS0

DDR_A_MA14

2
3

(14,17) PDAT_SMB

Q17

R227

R235

RHU002N06

10K

10K

DDR_A_WE#
DDR_A_CAS#

(8) DDR_A_WE#
(8) DDR_A_CAS#

DDR_A_BS1 (8)
DDR_A_RAS# (8)
DDR_CS0_DIMMA# (7)

2
4

DDRDAT_SMB

1

DDR_A_MA2
DDR_A_MA0

2
4

R223
DDR_A_MA1 R221
R232
R222
R220
R233

1
1
1
1
1
1

+3VM
(7)

Q16

M_ODT0 (7)

(7)
(7)
(7)
(7)

RHU002N06

3

(14,17) PCLK_SMB

DDRCLK_SMB

1

1
3
4P2R-S-56
RP19

DDR_A_BS1
DDR_A_RAS#

DDR_A_D36
DDR_A_D37

1
3
4P2R-S-56
RP16

Add for intel update

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

M_ODT0
DDR_A_MA13

1
3

4P2R-S-56
RP14

DDR_CKE1_DIMMA (7)

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

1
3

4P2R-S-56
RP13

R214
*10K/F

C289
*0.1U

2
4

DDR_A_BS2
DDR_A_MA12

(8) DDR_A_BS2

M_ODT1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA

1
3
4P2R-S-56
2
2
2
2
2
2

56
56
56
56
56
56

DDR_A_DM4

C

DDR_A_D34
DDR_A_D39

TOP
SMDDR_VTERM

1

C312
0.1U/10V

2
C305
*0.1U/10V

1

1

C304
0.1U/10V

2
C303
*0.1U/10V

1

1

C293
0.1U/10V

2
C290
*0.1U/10V

1

1

C333
*0.1U/10V

C324
0.1U/10V

2

C329
*0.1U/10V

C332
0.1U/10V

1

1

C330
*0.1U/10V

C323
0.1U/10V

2

C306
0.1U/10V

1

C326
0.1U/10V

1

C309
0.1U/10V

2

C307
0.1U/10V

1

C302
0.1U/10V

1

C310
0.1U/10V

1

C311
0.1U/10V

2

DDR_A_D46
DDR_A_D42

Layout note: Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM.

2

DDR_A_DQS#5
DDR_A_DQS5

1

DDR_A_D40
DDR_A_D44

DDR_A_D49
DDR_A_D53
M_CLK_DDR1 (7)
M_CLK_DDR#1 (7)

BOT

SMDDR_VTERM

DDR_A_DQS#7
DDR_A_DQS7

C300
2.2U/6.3V

C308
*0.1U/10V

C328
*0.1U/10V

C325
*0.1U/10V

C292
*0.1U/10V

C331
*0.1U/10V

2

C291
*0.1U/10V

2

C327
*0.1U/10V

2

DDR_A_D60
DDR_A_D56

+3VM

2

DDR_A_D54
DDR_A_D51

2

DDR_A_DM6

2

DDR_A_D61
DDR_A_D57

PM_EXTTS#0 (7)

DDR_A_D19
DDR_A_D23

1

DDR_A_D50
DDR_A_D55

2
4

1
3

4P2R-S-56
RP12

2

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_RAS#
DDR_A_BS1

DDR_A_MA13
M_ODT0

(7) M_ODT0

1

DDR_A_D48
DDR_A_D52

1.8VSUS

2

DDR_A_D47
DDR_A_D43

PM_EXTTS#0
DDR_A_DM2

2

DDR_A_DM5

DDR_A_D21
DDR_A_D20

1

DDR_A_D41
DDR_A_D45

2
4
4P2R-S-56
RP20

2

DDR_A_D35
DDR_A_D38

DDR_A_MA6
DDR_A_MA4

A

1
3

4P2R-S-56
RP21

1

DDR_A_DQS#4
DDR_A_DQS4

C

2

4P2R-S-56
RP18

(8) DDR_A_RAS#
(8) DDR_A_BS1

2

DDR_A_D32
DDR_A_D33

2
4

C460
0.1U/10V

1

M_ODT1

(7) M_ODT1

C476
0.1U/10V

2

DDR_A_CAS#

C477
0.1U/10V

2

(8) DDR_A_CAS#
(7) DDR_CS1_DIMMA#

C462
0.1U/10V

DDR_A_D14
DDR_A_D15

1

(8) DDR_A_BS0
(8) DDR_A_WE#

M_CLK_DDR0 (7)
M_CLK_DDR#0 (7)

2

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_MA11
DDR_A_MA7

Place these Caps near So-Dimm1.

1

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

1
RP17

DDR_A_DM1

2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

R234

1.8VSUS

1

DDR_A_BS2

(8) DDR_A_BS2

DDR_A_D12
DDR_A_D13

2

(7) DDR_CKE0_DIMMA

SMDDR_VTERM

C458
2.2U/6.3V

C322
2.2U/6.3V

1

DDR_A_D26
DDR_A_D30

C334
0.1U/10V

2

B

C473
2.2U/6.3V

56

1

DDR_A_DM3

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

C475
2.2U/6.3V

Add for intel update

2

DDR_A_D28
DDR_A_D29

VSS20
DQ20
DQ21
VSS6
NC3
DM2
VSS21
DQ22
DQ23
VSS24
DQ28
DQ29
VSS25
DQS#3
DQS3
VSS10
DQ30
DQ31
VSS8
CKE1
VDD8
A15
A14
VDD11
A11
A7
A6
VDD4
A4
A2
A0
VDD12
BA1
RAS#
S0#
VDD1
ODT0
A13
VDD6
NC2
VSS12
DQ36
DQ37
VSS28
DM4
VSS42
DQ38
DQ39
VSS55
DQ44
DQ45
VSS43
DQS#5
DQS5
VSS56
DQ46
DQ47
VSS44
DQ52
DQ53
VSS57
CK1
CK1#
VSS45
DM6
VSS32
DQ54
DQ55
VSS35
DQ60
DQ61
VSS7
DQS#7
DQS7
VSS36
DQ62
DQ63
VSS13
SA0
SA1

C459
2.2U/6.3V

8

DDR_A_MA14

DDR_A_D2
DDR_A_D3

1

DDR_A_D18
DDR_A_D22

VSS18
DQ16
DQ17
VSS1
DQS#2
DQS2
VSS19
DQ18
DQ19
VSS22
DQ24
DQ25
VSS23
DM3
NC4
VSS9
DQ26
DQ27
VSS4
CKE0
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)

C474
2.2U/6.3V

2

DDR_A_DQS#2
DDR_A_DQS2

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

Place these Caps near So-Dimm1.

DDR_A_DM0

1

DDR_A_D17
DDR_A_D16

7

(8) DDR_A_MA[0..14]

SMDDR_VREF_1

1

DDR_A_D10
DDR_A_D11

DDR_A_D5
DDR_A_D1

2

DDR_A_DQS#1
DDR_A_DQS1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

C301
0.1U/10V
D

DDR_A_D62
DDR_A_D58
2 R1004
2

DDR_A_D8
DDR_A_D9

VSS46
DQ4
DQ5
VSS15
DM0
VSS5
DQ6
DQ7
VSS16
DQ12
DQ13
VSS17
DM1
VSS53
CK0
CK0#
VSS41
DQ14
DQ15
VSS54

6

R236
10K

DB2 stage:on install for C327,C219---C331 for only one channel DIMM
1

+3VM

PROJECT : OT2
Quanta Computer Inc.

*10K
R237
10K

DB2 stage:reaerve

1

DDR_A_D6
DDR_A_D7

VREF
VSS47
DQ0
DQ1
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50

2

A

BOT
JDIM1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

5

1.8VSUS

DDR_A_DM[0..7] (8)
DDR_A_D[0..63] (8)
DDR_A_DQS[0..7] (8)
DDR_A_DQS#[0..7] (8)
DDR_A_MA[0..14] (8)

1

DDR_A_D0
DDR_A_D4
DDR_A_DQS#0
DDR_A_DQS0

4

SMDDR_VREF_1

PC4800 DDR2
SDRAM SO-DIMM
(200P)

A is required to route to Top
SoDIMM for AMT to
function.This will need to
change for M08

3

1.8VSUS

2

2

1.8VSUS

2

1

3

4

5

6

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

DDR2 SO-DIMM(200P)
7

Sheet

16

of
8

42

2

3

4

5

6

Y2

1.0
2

CLK_XTAL_IN 1

2

A

U5
L7

R77
1

16
9
2
61
39
55

1

1

BK2125HM601

L12

R99
1

C104
22U/10V
2

2

C64
3300P

12
20
26
45
36

VDDIO

1.0
2

49
48

(14) CLK_PWRGD
CLK_BSEL1

R59

56
57

0

SMBCK
SMBDT

2

3

(14,16) PDAT_SMB

R61
10K

R60
10K
SMBDT

1

SMBDT (4,19,27)

CPU_BCLK R1067
CPU_BCLK# R1068

CPUCLKT1
CPUCLKC1

51
50

MCH_BCLK 4
MCH_BCLK# 2

3 RP3
1 4P2R-S-0

CPUT2_ITP/SRCT8
CPUT2_ITP/SRCC8

47
46

CPU_XTP
CPU XTP#

4
2

3 RP4
1 4P2R-S-0

DOTT_96/SRCT0
DOTC_96/SRCC0

13
14

DOT96
DOT96#

2
4

1 RP7
3 4P2R-S-0

27MHz_Nonss/SRCCLK1/SE1
27Mhz_ss/SRCCLC1/SE2

17
18

3
1

4 RP8
2 4P2R-S-0

SRCCLKT2/SATACL
SRCCLKC2/SATACL

21
22

PCIE_SATA
PCIE_SATA#

SRCCLKT3/CR#_C
SRCCLKC3/CR#_D

24
25

PCIE_ICH
PCIE_ICH#

2
4

1 RP10
3 4P2R-S-0

CLK_PCIE_ICH (13)
CLK_PCIE_ICH# (13)

SRCCLKT4
SRCCLKC4

27
28

MCH_3GPLL 2
MCH_3GPLL#4

1 RP11
3 4P2R-S-0

CLK_MCH_3GPLL (7)
CLK_MCH_3GPLL# (7)

4
2

3 RP5
1 4P2R-S-0

VDD96I/O
VDDPLL3I/O
VDDSRCI/O
VDDSRCI/O
VDDSRCI/O
VDDCPU_IO
NC
X1
X2

PCI_STOP#
CPU_STOP#

38
37

SRCCLKT6
SRCCLKC6

41
40

SRCCLKT7/CR#_F
SRCCLKC7/CR#_E

44
43

SRCCLKT9
SRCCLKC9

30
31

SRCCLKT10
SRCCLKC10

34
35

SRCCLKT11/CR#_H
SRCCLKC11/CR#_G

33
32

CK_PWRGD/PD#
FSLB/TEST_MODE

3

(14,16) PCLK_SMB

SMBCK

1

15
19
11
52
8
58
23
29
42

GND
GND
GND48
GNDCPU
GNDPCI
GNDREF
GNDSRC
GNDSRC
GNDSRC

CLKREQ#_B 2

4.7K
1
*10K

CLK_CPU_XDP (4)
CLK_CPU_XDP# (4)
MCH_DREFCLK (7)
MCH_DREFCLK# (7)
DREF_SSCLK (7)
DREF_SSCLK# (7)

FSC

FSB

FSA

CPU

SRC

PCI

1

0

1

100

100

33

0

0

1

133

100

33

0

1

1

166

100

33

0

1

0

200

100

33

0

0

0

266

100

33

1

0

0

333

100

33

1

1

0

400

100

33

1

1

1

RSVD

100

33

H_STP_PCI# (14)
H_STP_CPU# (14)

B

EMI

1
3

CLK_ICH_48MC128 *10P

CLK_PCIE_MINI1 (19)
CLK_PCIE_MINI1# (19)

PCLK_KBC

4P2R-S-0

T9
MINI1CLK_REQ# R98

PCICLK0/CR#_A
PCICLK1/CR#_B
PCICLK2/TME
PCICLK3
PCICLK4/27_SELECT

1
3
4
5
6

PCI_F5/ITP_EN

7

USB_48MHZ/FSLA

10

FSLC/TST_SL/REF

62

C412 *10P

PCLK_R5C847C126 *10P
2

1

MINI1CLK_REQ#G

MINI1CLK_REQ#G (19)

475_1%
SATA_CLKREQ#
CLKREQ#
R106 2
R1031 2

1 475_1%
1 33

CLK_PCI_ICH C127 *10P
PCLK_TPM

CLKREQ#_B (7)

PCLK_DBP_1
(26)
SI2 stage:delete ,R82, R341 due
to
R347 2
no use
1 33
PCLK_TPM (30)
PCLKKBC
R337 2
1 33
PCLK_KBC (26)
R348 2
1 33
PCLK_R5C847 (20)
PV stage: change R347,R348 to 33 ohm for EA issue
CLK_PCI_ICH_1 R97 2
1 33
CLK_PCI_ICH (13)
R340 2
1 33
CLK_ICH_48M (14)

C125 *10P

CLK_ICH_14MC53

*10P

14M_KBC

*10P

C52

R1033
0 *BK1608LL680
CLK_BSEL0
R339 2.2K
L54
CLK_BSEL2
2
1
R52
10K
2 R51
1 33
14M_KBC (26)

R1034
0
L55
*BK1608LL680

2

R81

CLK_MCH_BCLK (6)
CLK_MCH_BCLK# (6)

C672 *10P

RP6

ICS9LPRS355AGLFT
SATA_CLKREQ# 2

CLK_CPU_BCLK (4)
CLK_CPU_BCLK# (4)

C670 3.3P
C671 *10P

SI stage:add R1031 for EA team test easy

R96

10K

A

T173
T174

PCIE_MINI1 2
PCIE_MINI1# 4

1

R104

4.7
4.7

DB2 Stage:no install RP9,R82 due to no
SATA HDD

PCLKKBC

Pull low for UMA
C

SCLK
SDATA

SMBCK (4,19,27)

+3V

MINI1CLK_REQ#G

64
63

2

+3VM_CK505
Q29
2N7002E

14.318MHz
PV stage:reserve for WWAN issue

54
53

+3VM_CK505

Q30
2N7002E

C72
27P/50V

CPUCLKT0
CPUCLKC0

CK505

2

2

C57
22U/10V

CLK_XTAL_IN 60
CLK_XTAL_OUT 59

DB1A:change R59 for
intel schematic

VDDPLL3
VDD48
VDDPCI
VDDREF
VDDSRC
VDDCPU

1

1

1
2

2

C66
C62
C113
0.1U/10V 0.1U/10V 0.1U/10V

2

2

2

1

1

1

1

BK2125HM601
C115
C107
C65
0.1U/10V 0.1U/10V 0.1U/10V

C55
27P/50V

C669 3.3P

VDDCPU

1.0
2

CLK_XTAL_OUT

2
14.318MHZ

2

1

internal have
already build-in
33ohm damping
resisteor
PV stage:delete RP2 ,add
R1067,R1068

C56
22U/10V

2

C112
0.1U/10V

2

2

2

2

C114
0.1U/10V

1

1

1

1

1

120 ohms@100Mhz
C409
C63
C67
0.1U/10V 0.1U/10V 0.1U/10V

8

2

R86
1
BK2125HM601

1

L11

B

7

VDD

1

1

+3VM_CK505

R346 1 10K

2 R53

1 33

C

CLK_ICH_14M (14)

DB1A:change R339,R52
for intel schematic
SI stage:reserve L53, L54,add
R1033,R1034 for WWAN noise
improvement

PV stage:change R51,R53 to 33ohm for EA issue
CLK_PCI_ICH_12

R338 1 10K

CPU Clock select
R952
(4) CPU_BSEL0
+1.05V

R1036

0/04

R1037

*56/04

R1038

*1K/04

R1039

0/04

CLK_BSEL0

2

1

MCH_BSEL0 (7)

R953
(4) CPU_BSEL1

+1.05V

R1040

*0/04

R1041

*1K/04

R1042

0/04

R1043

*0/04

R1044

*1K/04

FSB

BCLK

533

133

BSEL2
0

BSEL1
0

BSEL0
1

667

166

0

1

1

800

200

0

1

0

1K/F

CLK_BSEL1

2

1

MCH_BSEL1 (7)

1K/F
R954

(4) CPU_BSEL2

CLK_BSEL2

2

1

MCH_BSEL2 (7)

1K/F

D

D

+1.05V

PROJECT : OT2
Quanta Computer Inc.

SI stage: strapping options for
CPU_BSEL{0:2}

1

2

3

4

5

6

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

CLOCK(CK505)
7

Sheet

17

of
8

42

5

4

3

2

1

5

+3V

CN3

C

BK1608HS121-T

DPST_PWM (7)

4
1 FPBACK

1

+3V

U3
TC7SH08FU

LCDVCC
C18
1000P

EDIDDATA_1
EDIDCLK_1

C20
0.1U

C16
1000P

C15
*0.1U

C690

3

VIN

C29
10U/25V

C5
*0.1U/0402

0.1U

D3

+3V
ALS_EN
R17

R23
10K

+5V

0

D

+3V

2

1

2

FPBACK

2

1

3

R35
10K

SI2 stage:delete

LID_SW_EC# (26)

CH751H-40HPT
D34

D2
1

2

LID_SW# (14)

1SS355
CH751H-40HPT

+3V
TXLOUT0+
TXLOUT0-

2

TXLOUT1+ (7)
TXLOUT1- (7)

(7) LCD_BLON

R26

LCD_BLON

2

TXLOUT2+ (7)
TXLOUT2- (7)

TXLCLKOUT+
TXLCLKOUT-

C19
0.1U

Q7
DTC144EUA

330

TXLOUT2+
TXLOUT2-

R25
33K

1

TXLOUT1+
TXLOUT1-

Q6
DTC144EUA

3

TXLOUT0+ (7)
TXLOUT0- (7)

CN2
2
1

1

D

L2

2
PWM_INV_1

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

ALS_EN

TXLCLKOUT+ (7)
TXLCLKOUT- (7)

3V_S5

LID SW
3

32
31

Q2

C

2N7002E

LCD_CON30

2

ALS_EN# (14)

1

PV stage:reser for Lid s/w function to EC
R22
*10K

PANEL VCC CONTROL
3VPCU
R20

10K

+3V
Q3
FDC624P
R30

EDIDCLK_1

R32

R19
*10K

R28
(7) EDIDDATA

2.2K

+3V
(7)

2

2

2.2K

1
Q1

3

3

(7) EDIDCLK

2N7002E
3

82K
C32
0.1U

3

G

S

4

2
1

D
D

D
D

5
6

B

+3V

40mil

LCDVCC

L3
FBM2125HM330

2

DISP_ON

Q4
DTC144EUA

EDIDDATA_1
R27
100K

2N7002E

C17
0.1U

1

B

Q5
1

C34
10U/10V/0805

C14
1000P

C13
0.1U

C33
4.7U/10V

SI2 stage:add soft start for LCD panel rush current issue

A

A

PROJECT : OT2
Quanta Computer Inc.
5

4

3

2

Size
B

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

LCD CON
Sheet
1

18

of

42

A

B

C

Mini PCI-E Card1 LAN

(29)

D

D16
2

RF_LINK

RF_LINK

E

*SW1010C
BLUELED
1

+1.5V_WLAN

3V_S5
3VPCU

C348
1000P

DB2 stage:change
R270

ICH_CL_CLK1_1

*0

C351
0.01U

C354
10U/10V/0805

+3VM_WLAN
+3V

SI stage:change footprint to 1206
R258
R249

3V_S5

0

0

D

D

C353
1000P

R259

C352
0.1U/10V

C355
1U

RF_OFF#_1

CN33

51 Reserved
49 Reserved
47
ICH_CL_CLK1_145 Reserved
Reserved
43 Reserved
+3VM_WLAN
R268
41 Reserved
0 R271
39 Reserved
0
DB2 stage:change power source
37 Reserved
DB1A stage:change R268,R271 to footprint
35 GND
DB2 Stage:delete R274,R265 (13) PCIE_TXP2
1206
33 PETp0
31 PETn0
Add R1025
(13) PCIE_TXN2
29 GND
+3V
3V_S5
27 GND
R272
0
PCIE_RXP2_C
25 PERp0
(13) PCIE_RXP2
PCIE_RXN2_C
R273
0
23 PERn0
(13) PCIE_RXN2
21 GND
R1024 *0
R257
0
19 Reserved
17 Reserved
SI2 stage:delete R1025 due to no use
15 GND
13 REFCLK+
(17) CLK_PCIE_MINI1
11 REFCLK(17) CLK_PCIE_MINI1#
9 GND
MINI1CLK_REQ#G
7 CLKREQ#
DB2 stage:install
(17) MINI1CLK_REQ#G
R255
*0 CCI_CLK
5 Reserved
(30)
CH_CLK
R256
*0 CCI_DATA
3 Reserved
(30) CH_DATA
3
1
1 WAKE#
(14) PCIE_WAKE#
Q23
DTC144EUA
PCI-E Card
R262
R267
R269

0
0
0

2

(14) ICH_CL_RST1#
(14) ICH_CL_DATA1
(14) ICH_CL_CLK1

R248
*10K

+3VM

*0

DB2 stage:change

C

C345
0.1U/10V

3V_S5

+3.3V
GND
+1.5V
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
Reserved
GND

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

Reserved
Reserved
Reserved
Reserved
Reserved
+1.5V
GND
+3.3V

16
14
12
10
8
6
4
2

SI2 stage:no install
DB1A stage:change to footprint
1206
R250
R251

*0
0

+3VM_WLAN

BLUELED
RF_LINK

DB2 stage:change power source

T80
C347
1000P

C346
0.1U/10V

C350
10U/10V/0805

SMBDT (4,17,27)
SMBCK (4,17,27)
PLTRST# (13,26,28,30)
D15
RF_OFF#_1
2
CH751H-40HPT
+1.5V
DB2

1

RF_OFF# (14)

Stage:delete RP22,RP23,R254

R1026
0
SI2 stage:change to CH751H-40HPT for lower Vf
+1.5V_WLAN

C

+3VM_WLAN

DB2 stage:change

Mini PCI-E Card2 WWAN
3VSUS

R55

(13) WWAN_OFF#

+3V

0

WWLAN_OFF_SIM

+1.5V

C124
1000P

C74
0.01U

C61
0.1U/10V

C109
10U/10V/0805

C89
1000P

C75
0.1U/10V

C88
1U

C59
1000P

C58
0.1U/10V

C68
10U/10V/0805

3VSUS
+3V
R43
+1.5V

B

A

51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
Reserved
Reserved

15
13
11
9
7
5
3
1

GND
REFCLK+
REFCLKGND
CLKREQ#
Reserved
Reserved
WAKE#

B

R74

0

CN20
+3V

+3.3V
GND
+1.5V
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
Reserved
GND

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

Reserved
Reserved
Reserved
Reserved
Reserved
+1.5V
GND
+3.3V

16
14
12
10
8
6
4
2

+3V

*0

0
R73

R64
0

WWAN# (29)

U8

USBP8+ (13)
USBP8- (13)
SMBDT (4,17,27)
SMBCK (4,17,27)

1

CH1

2

VN

3

CH2

CH3

4

VP

5

CH4

6

+3V

2

UIM_CLK
3

*CM1213_04ST

1

PLTRST# (13,26,28,30)

WWLAN_OFF_SIM

EMI

D6

R92
*22R

BAV99W
CN4

UIM_VPP
UIM_RST
UIM_CLK_1 R85
UIM_DATA_1 R101
UIM_PWR

R102
0
0

UIM_CLK
UIM_DATA

GND

VCC

2

3

VPP

RST

4

UIM_RST

5

I_O

CLK

6

UIM_CLK

7

N/A

N/A

8

R111
C132
.1U

+3V

C120
4.7UA

C91
*.1U

C100
*.1U

*10K

UIM_PWR

1
0

9
13

PCI-E Card

CT
SHIELD

DET
SHIELD

C94
*22P

10
14

A

600-0000-0012
UIM_PWR

PROJECT : OT2
Quanta Computer Inc.

PV stage:Add shielding connect to
GND

Size
Document Number
Custom
WAN/WWAN
Date:
A

B

C

D

Thursday, March 22, 2007

Rev
1A

CARD
Sheet
E

19

of

42

5

4

3

2

1

+3V

1

+3V
C612
10U/6.3V

C605
0.01U

C604
0.01U

C606
0.01U

DB2 stage:change power source form 3VSUS to 3V due to not support wake up in S3

+3V

VCC_PCI1
VCC_PCI2
VCC_PCI3

R6
E13
L1
E14

VCC_RIN1
VCC_RIN2
VCC_ROUT1
VCC_ROUT2

VCC_3V1
VCC_3V2
VCC_3V3
VCC_3V4

F5
J19
K19
G5

1

2

U40A
W3
R11
R12

C602 C552 C593 C607 C613

1

D

C574

C597

C575

10U/6.3V 0.01U

0.01U

0.01U

C603 C572 C573

2

C611

2

0.01U 0.01U 0.01U 0.01U 10U/6.3V

D

C571
0.47U

0.01U 0.01U 0.47U
VCC_MD
(13) AD[31..0]

GRESET#

R545

*0

PCIRST#

R1027

(26,31) HWPG

(13)
(13)
(13)
(13)
(13)
(13)

*0

(13)
(13)
(13)
(13)
(13)
(13)
(13)
(13)
(13)

+3V

R551
10K

PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
AD22

PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
AD22

REQ2#
GNT2#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR_1#

REQ2#
GNT2#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR_1#
GRESET#

C615

PCIRST#
PCLK_R5C847

(13)
PCIRST#
(17) PCLK_R5C847

SHIELD GND

CLKRUN#
R5C847_PME#

(14,26,30) CLKRUN#

1U/25V

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
IDSEL

M4
M5
V3
V4
W4
T5
V5
W5
T6

REQ#
GNT#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#

G2
L4
K1

GBRST#
PCIRST#
PCICLK

L5
G4

CLKRUN#
PME#/RI_OUT#

TEST1
TEST2

A4
J1
J5
K5
E9
R10
T10
V10
W10
L15
M19
A9
B9
D9
D14
A15
B15

+3V
C1

R546
10K

E1

F4
R7

C2

HWSPND#

F2

SPKROUT#

F1

T153

R533
100K

D2
E2

UDIO5
UDIO4

R522
10K

SDA

H5
H4

UDIO2

H2

UDIO1

H1

VCC
WP
SCL
SDA

A0
A1
A2
GND

1
2
3
4

Serial EEPROM
SERIRQ (14,26,30)

INTA#

J2

INTC#

* NOT Use EEPROM :
R524,R522,R537 : installed
R533,U39,C585: NOT installed
* Use EEPROM :
R533: NOT installed

(13)

INTB#

K4

INTD#

(13)

INTC#

K2

INTE#

(13)

NC0

L2

R522,R524,U39,C585,R537 :
installed
E8
D8

MDID13
MDID12
MDID11
MDID10

B8
A8
E7
D7
B7
A7
E6
D6

MDID9

B6

MDID8

A6
D5

SDVCC_MSVCC
B5
A5
CN34

4

R5C847_PME#

47

MDID9_R

5

2

C596
6
3

1

C616
*22P

R531

3

22P

PCI_PME# (13)

MDID10

R529

47

MDID10_R

MDID11

R532

47

MDID11_R

7

Q47
2N7002E
8
C595

500mA

B3

DATA2
DATA3
CMD

A3
A2

VDD

MDID0

B1

CDATA15/CAD8
CDATA14
CDATA13/CAD6
CDATA12/CAD4
CDATA11/CAD2
CDATA10/CAD31
CDATA9/CAD30
CDATA8/CAD28
CDATA7/CAD7
CDATA6/CAD5
CDATA5/CAD3
CDATA4/CAD1
CDATA3/CAD0
CDATA2
CDATA1/CAD29
CDATA0/CAD27
OE#/CAD11
WE#/CGNT#
CE2#/CAD10
CE1#/CCBE0#
REG#/CCBE3#
RESET/CRST#
WAIT#/CSERR#
WP/CCLKRUN#
RDY/CINT#
BVD2/CAUDIO
BVD1/CSTSCHG
VS2#/CVS2
VS1#/CVS1
CD2#/CCD2#
CD1#/CCD1#
INPACK#/CREQ#

MDIO19
MDIO18
MDIO17
MDIO16
MDIO15
MDIO14
MDIO13
MDIO12
MDIO11
MDIO10
MDIO09

J18
J15
K16
L16
L18
M16
N19
N16
P16
L19
K15
N18
N15
K18
R18
U19
R19
P15
J16
H15
H18
G15
G18
F15
F18
E16

R509

CADR25
CADR24
CADR23
CADR22
CADR21
CADR20
CADR19
CADR18
CADR17
CADR16
CADR15
CADR14
CADR13
CADR12
CADR11
CADR10
CADR9
CADR8
CADR7
CADR6
CADR5
CADR4
CADR3
CADR2
CADR1
CADR0

0

T19
M15
T18
V19
F16
H19
G16
A18
M18
F19
E18
H16
R16
D15
T14
G19

DATA1

C

CDATA[15..0] (21)

OE#
(21)
WE#
(21)
CE2#
(21)
CE1#
(21)
REG#
(21)
RESET (21)
WAIT# (21)
WP
(21)
RDY
(21)
BVD2
(21)
BVD1
(21)
VS2#
(21)
VS1#
(21)
CD2#
(21)
CD1#
(21)
INPACK# (21)

B

DIFFERENTIAL IMPEDANCE : 90 ohms
IORD#/CAD13
IOWR#/CAD15

MDIO07

SHIELD GND

P18
P19

IORD#
IOWR#

(21)
(21)

MDIO06
MDIO05

USBDP
USBDM

V14
W14

T151
T152

MDIO04
MDIO03
MDIO02
VPPEN1
VPPEN0
VCC3EN#
VCC5EN#

MDIO01
MDIO00

W13
V13
T13
R13

VPPEN1 (21)
VPPEN0 (21)
VCC3EN# (21)
VCC5EN# (21)
R497 100K

VSS2
VSS1
DATA0

SHIELD GND
*CLOCK LINE FOR CARDBUS MODE

CDATA15
CDATA14
CDATA13
CDATA12
CDATA11
CDATA10
CDATA9
CDATA8
CDATA7
CDATA6
CDATA5
CDATA4
CDATA3
CDATA2
CDATA1
CDATA0

U18
W18
V17
V16
V15
B19
C18
D18
W17
W16
W15
T15
R14
C19
D19
E19

MDIO08

CLK

SD_SLOT

S

B4

MDID3

WP

SHIELD GND

MDID4

CADR25/CAD19
CADR24/CAD17
CADR23/CFRAME#
CADR22/CTRDY#
CADR21/CDEVSEL#
CADR20/CSTOP#
CADR19
CADR18
CADR17/CAD16
CADR16/CCLK
CADR15/CIRDY#
CADR14/CPERR#
CADR13/CPAR
CADR12/CCBE2#
CADR11/CAD12
CADR10/CAD9
CADR9/CAD14
CADR8/CCBE1#
CADR7/CAD18
CADR6/CAD20
CADR5/CAD21
CADR4/CAD22
CADR3/CAD23
CADR2/CAD24
CADR1/CAD25
CADR0/CAD26

CHECK FOOTPRINT
R5C847-V10_0

10

9
1
2

GND
GND
CD/WP
CD

MDID12_R
MDID13_R
MDID8_R

47
47
33

14
13
12
11

R528
R527
R530

NC7

U39

22P
C594

MDID9

NC6

*24C02

J4

22P

R548
10K

NC5

0.01U

8
7
6
5

SCL

+3V

R555
*22R

NC4

C585

R524
10K

G1

UDIO3

UDIO0/SRIRQ#

E4

C592

MDID12
MDID13
MDID8

NC3

+3V
R537
*100K

CoreLogic CLOCKRUN#

PCLK_R5C847

NC2

+3V

PCMSPK#

R5C847-V10_0

EMI

NC1

+3V

When CLKRUN# is controlled by
system, the pull-down
resistor(R1050) dose not need to
apply.

+3V

D1

PCMSPK# (22)

PowerOnReset for VccCore
When GRESET# is controlled by system,
the pull-up resistor(R551) and
capacitor(C615) do not need to apply.

CADR[25..0] (21)

R547
*100K

DB2 Stage:R551 from 100k chang to
10K to solve GBRST too slow for 1394/Firewire
B

U40B

When HWSPND# is controlled by
system, the pull-up
resistor(R1041) dose not need to
apply.

CARDBUS / MEDIA CARD

C

M2
M1
N5
N4
N2
N1
P5
P4
R4
R2
R1
T2
T1
U2
U1
V1
T7
V7
W7
R8
T8
V8
W8
R9
V9
W9
T11
V11
W11
T12
V12
W12
V6
P2
W2
W6
T9
P1

PCI / OTHER

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
AGND1
AGND2
AGND3
AGND4
AGND5
AGND6

22P
C598

D

DB2 stage:change to push-push type

SDVCC_MSVCC
22P

G

A

R981

220K

Q52
C609
AO3413
BAM341300010.1U
CC0402

C610
0.1U
CC0402

R542
C608
1U

A

*150KA

RC0402
1

33

MDID3

R534

33

MDID0_R
MDID3_R

reserve for MMC card detect properly
2

DTC144EU

5

R541

3

Q53

MDID4

MDID0

PROJECT : OT2
Quanta Computer Inc.

DB1A change :modify for
detect function

4

3

2

Size
C

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

RC5847(1394)
Sheet
1

20

of

42

4

3

D12

2

BLM21P300S

C553

C587

C567

10U/6.3V 0.1U/10V

C554
0.001U 0.1U/10V

C590

TPBIAS0
0.33U

GUARD GND
XI

A13

TPBP0

B13

TPB0N

IEEE1394

24.576MHz 50ppm 10pF
Y6
1394_XOUT B16

C584
10P

A14

XO

TPB0P

B14

REXT

VREF

D13

VREF

0

TPA0N

TPAP0

B12

TPA0P

EB3
R498

C

NC9

D10

NC10

A11

NC11

B11

0 *1632090
4
1

1
4

1
4

CN31
TPB0N_C 1

1

TPB0P_C 2

2

TPA0N_C 3

3

TPA0P_C 4

4

SHIELD GND

*1632090
0

R520 R523
56

C588

CHECK FOOTPRINT

270pF
R521

GUARD GND
E12

0

A12

10K 1%
C591
0.01U/25V

R499

TPAN0

FIL0

REXT

4
1

R496
2 2
3 3

56

R519

R500
EB4 3
3
2 2

1

TPBN0

1394_CONN

R525
56

5 6 7 8

56

5
6
7
8

R526
A16

(20) CDATA[15..0]

C568
0.001U

C589
0.01U/25V
1394_XIN

A_VPP

NC12

A10

NC13

B10

NC8

5.1K

R5C847-V10_0

CARDBUS POWER SWITCH
+3V

DB2 stage:change power source form 3VSUS to 3V due to not support wake up in S3

A_VCC
C505

1

U35
+5V
NC3
NC2

11

3VIN

13
15

5VIN1
5VIN2

1U
CC0402

(20)
(20)
(20)
(20)

VPPEN1
VPPEN0
VCC3EN#
VCC5EN#

SI stage:change to 5V due not
support wake on S3

VCCOUT1
VCCOUT2
VCCOUT3
VPPOUT

6

NC1

4
3
2
1

EN1
EN0
VCC3EN
VCC5EN

9
12
14

/FLAG
GND

(20)
OE#
(20)
WE#
(20)
CE2#
(20)
CE1#
(20)
REG#
(20)
RESET
(20)
WAIT#
(20)
WP
(20)
RDY
(20)
BVD2
(20)
BVD1
(20)
VS2#
(20)
VS1#
(20)
CD2#
(20)
CD1#
(20) INPACK#
(20)
(20)

8

IORD#
IOWR#

SHIELD GND
C357
C551
0.1U/10V

5

56
55
54
53
50
49
48
47
46
19
20
14
13
21
10
8
11
12
22
23
24
25
26
27
28
29
41
40
39
38
37
66
65
64
6
5
4
3
2
32
31
30

A25/CAD19
A24/CAD17
A23/CFRAME#
A22/CTRDY#
A21/CDEVSEL#
A20/CSTOP#
A19/CBLOCK#
A18/RSVA18
A17/CAD16
A16/CCLK
A15/CIRDY#
A14/CPERR#
A13/CPAR
A12/CCBE2#
A11/CAD12
A10/CAD9
A9/CAD14
A8/CCBE1#
A7/CAD18
A6/CAD20
A5/CAD21
A4/CAD22
A3/CAD23
A2/CAD24
A1/CAD25
A0/CAD26
D15/CAD8
D14/RSVD14
D13/CAD6
D12/CAD4
D11/CAD2
D10/CAD31
D9/CAD30
D8/CAD28
D7/CAD7
D6/CAD5
D5/CAD3
D4/CAD1
D3/CAD0
D2/RSVD2
D1/CAD29
D0/CAD27

9
15
42
7
61
58
59
33
16
62
63
57
43
67
36
60

OE#/CAD11
WE#/CGNT#
CE2#/CAD10
CE1#/CCBE0#
REG#/CCBE3#
RESET/CRST#
WAIT#/CSERR#
WP/CCLKRUN#
READY/CINT#
BVD2/CAUDIO
BVD1/CSTSCHG
VS2#/CVS2
VS1#/CVS1
CD2#/CCD2
GND1
CD1#/CCD1
GND2
INPACK#/CREQ# GND3
GND4

44
45

IORD#/CAD13
IOWR#/CAD15

C342

CARD_SLOT_0

DIFFERENTIAL IMPEDANCE : 90 ohms

A_VPP

1

C506

C504
0.1U/10V
2

10
7

CADR25
CADR24
CADR23
CADR22
CADR21
CADR20
CADR19
CADR18
CADR17
CADR16
CADR15
CADR14
CADR13
CADR12
CADR11
CADR10
CADR9
CADR8
CADR7
CADR6
CADR5
CADR4
CADR3
CADR2
CADR1
CADR0
CDATA15
CDATA14
CDATA13
CDATA12
CDATA11
CDATA10
CDATA9
CDATA8
CDATA7
CDATA6
CDATA5
CDATA4
CDATA3
CDATA2
CDATA1
CDATA0

270pF

VCC1
VCC2

17
51

VPP1
VPP2

18
52

D

C344

C349

C343
0.01uF
0.01uF

10U/6.3V

C

B

1
34
35
68

C338
270pF

*0.01uF

2

1U
CC0402

B

A_VCC

CN10

C586

10U/6.3V

D

C569
10P

1

AVCC_PHY
(20) CADR[25..0]

1

TPBIAS0

L48

2

CPS

E10
E11
A17
B17

2

D11

AVCC_PHY1
AVCC_PHY2
AVCC_PHY3
AVCC_PHY4

1

AVCC_PHY

+3V

1

U40C

2

5

16

DB1A stage:delete C342

R5531V-002

A

A

PROJECT : OT2
Quanta Computer Inc.
5

4

3

2

Size
B

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

RC5847(Cardbus)
Sheet
1

21

of

42

5

4

3

2

1

JP6 *SHORT PAD
1
2
JP7
1

3V_DVDD

2

AVDD

SI2 stage:change 22U for ESD issue

+3V
+5V
*SHORT PAD
JP8

0

C520
10U/10V

C524
0.1U

C508
10U/10V

AGND

C512
0.1U

3V_DVDD

(12) ACZ_SYNC_ADI
(12) ACZ_BITCLK_ADI
(12) ACZ_SDOUT_ADI
(12) ACZ_SDIN0
(12,23) ACZ_RST_ADI#

SENSE_A_A_R

R504
R503
R502
R477

*4.7K
*4.7K
*4.7K
*4.7K

10
6
5
8
11
43
44
2
3

4

BYP

BEEP2

C497 0.1U

R432
4.7K

C496
.01U

BEEP

C516
1U

AGND

C534
0.047U

NC
NC
NC
NC
NC

AGND

C527
1U

C583
0.1U

HP_OUT_R
HP_OUT_L

PORT-B_R
PORT-B_L

22
21

MIC2
MIC1

PORT-C_R
PORT-C_L

24
23

LINE_IN_R
LINE_IN_L

C507 1U
C502 1U

PORT-D_R
PORT-D_L

36
35

LINE_OUTR1
LINE_OUTL1

C541 0.33U LINE_OUTR
C535 0.33U LINE_OUTL

PORT-E_R
PORT-E_L

15
14

PORT-F_R
PORT-F_L

17
16

CD-R
CD-L
CD-GND

20
18
19

MIC_BIAS_B
MIC_BIAS_C
MIC_BIAS_D
MIC_BIAS_F
SENSE_B/SRC_A
SENSE_A/SRC_B

28
29
32
30
34
13

(20)

MIC2
MIC1

(23)
(23)
R461
R445

LINE_IN_R_1
LINE_IN_L_1

4.7K
4.7K

DOCK_LINE_IN_R (32)
DOCK_LINE_IN_L (32)
LINE_OUTR (23)
LINE_OUTL (23)

R494
R444
R460

SI stage:change for HP request
AVDD
AVDD

4.7K
4.7K

AGND

C446 .1U
C498
*0.1U

R475
2.67K

R438
2.67K/F

C298 .1U

AGND

C529 .1U
R478

0
C557 .1U

R486

SI stage:change for HP request
C492 .1U

*0

R433

0 SENSE_A_R

R439

39.2K/F

SENSE_A_A

R450

20K/F

SENSE_A_B

R459

10K/F

SENSE_A_C

C277 .1U

SENSE_A_A (23)
AVDD

SENSE_A_B (23)

R449
*10K

3

4
7

5

C236 .1U

2
1

Q38
2N7002

AGND
LINE_IN_SENSE

LINE_IN_SENSE (32)

C503
*1U

R458
100K

AGND

AGND

BEEP1

2

PCSPK

C

C562 .1U

SI stage:add for internal mic issue

B

AGND
U33
7SH86

3

(14)

0_1206

C582 .1U

AGND
AGND
4

PLACE TO
X
HP OUT, DOCK HP LO
M/B MIC
DOCK LI
M/B SPK
X
X

C643 1U INT_MIC

C500
0.1U

1

PCMSPK#

PORT
MONO_OUT
PORT A
PORT B
PORT C
PORT D
PORT E
PORT F

HP_OUT_R (23)
HP_OUT_L (23)

C501
1U

B

D

AD1981HDJSTZ

AVDD

NORMAL : LOW

C581
10U/10V

MAINON (25,31,34,36,37,38,39,40)

Vset=1.242V

41
39

EPAD
SPDIF_OUT
PCBEEP
VREF_FILT

PC BEEP CONTROL

AGND

PORT-A_R
PORT-A_L

GPIO0_JS1
GPIO1/JS0
GPIO2
GPIO3

DVSS1
DVSS2

AGND

31
33
40
45
46

C513
0.1U

BLM11A20
C530
0.1U

TPS793475

37

SYNC
BIT-CLK
SDATA-OUT
SDATA-IN
RESET#

2

MAINON

AVSS1
AVSS2

47K

47
48
12
27

EN

3

1

26
42

R436

EAPD

EAPD

GND

1

MONO-O

SI stage:R502 no install

BEEP1

2

25
38
AVDD1
AVDD2

DVDD1
DVDD2

ACZ_SYNC_ADI
10
ACZ_BITCLK_ADI R474
AC_BITCLK1
ACZ_SDOUT_ADI
R469
33
ACZ_SDIN0
AC_SDIN
ACZ_RST_ADI#
DB1A stage:change to 33 ohm for change list

(14,27) PR_INSERT#

C

C556
22U/25V

Vin

AGND

*4.7K ACZ_RST_ADI#

AGND

(23,26)

C555
0.1U

AGND

(23) SENSE_A_A_R

C509
10P

Vout

C549
1U

U34
R1054

R465
0

C510
0.1U

PLACED NEAR
PIN1&9

SI2 stage:reserve for
ADI suggest

AC_BITCLK1

C537
0.1U

L50

5

2
*SHORT PAD

D

1
9

1

U37
L47

AGND
AVDD

AGND

MIC_REF1
AVDD
INT_MIC1_CN

AVDD

C636

R1015

C635
.01U

100P
INT_MIC

R1016
C637

0.22U

L53

R1017

10K

0603CS-101EJTS
3K

C657
47P

C640
68P

PV stage:change due to BOM error

C641

220P

R1020

182K

PV stage:change due to BOM error

47K
MIC_REF1

1

1OUT

VDD+

8

2

1IN-

2OUT

7

AGND

3

1IN+

2IN-

6

2 R1019

4

GND

2IN+

5

3K
C639
4.7U

R1014

U47

R1018

100

1 0
C638
4.7U

TLV2462CDGKR

AGND

AGND
R1021

A

AGND

AGND

AGND

CN36
INT_MIC1_CN

INT MIC

2
1
C664 R1050
Mic
*1000P
*0
AGND

SI stage:change connect to pin1
for internal mic issue
PV stage:change C641 to 220P
for Mic gain issue

AGND
5

and

47K

A

C642
4.7U

R1020 to 182K

PROJECT : OT2
Quanta Computer Inc.
Size
Custom

Document Number

Date:

Thursday, March 22, 2007

AGND
4

3

2

Rev
1A

Audio codec(ADI1981)
Sheet
1

22

of

42

5

4

3

2

1

+5V
AVDD

1

SI2 stage:reserve for anti-pop circuit
R1055
HP_CONTROL

2

C576
10U

C566
.1U_10V
2

1

1

*330K/F
3
1

2

2

Q63

R1056

D

C665
*4.7U/10V

(22) LINE_OUTR
(22) LINE_OUTL
C564 0.1U

*2N7002E

2

R514
R510

34.8K/F
34.8K/F

R506

16.2K

U38
LINE_OUT

AGND

PV stage:reser for mute noise issue
AGND

4
3
2
1

1

3V_DVDD

+5V

C691
*.1U_10V

C565
10U

CN13
5
6
7
8

SPK+

L52

BK1608LL121

SPK-

L51

BK1608LL121

SPK_1+
SPK_1-

2
1

INT. SPEAKER

Speaker

TPA6211A1DRBR

C617
100P

D

C619
100P

2

*10K/F

AGND

INVO+
IN+
VDD
BYPASS
GND
SHUTDOWN VO-

1

(12,22) ACZ_RST_ADI#

AGND

1

R1057

R505
10K

2

AGND AGND

AGND
R229

C666
*0.047U

MUTE_AMP

EAPD

C478

R382

60.4 HP_L_1

100U/6.3V HP_R

R381

60.4 HP_R_1

3

R1058

R1059

AVDD
2
3

*22K/F_6

*22.K/F_6

(32) DOCK_HP_OUT_L
(32) DOCK_HP_OUT_R

HP_L_2

L41

BK1608LL121

HP_L_3

HP_R_2

L40

BK1608LL121

HP_R_3

1
2
6
3
4
5

4
1

IO1 Vin
IO2 Gnd

R215
1K

AGND AGND

R218
1K

C294
470P

C299
470P

0.1U/10V
1

C256
2

0 ohm

C284
2

HP_CONTROL
7

1
R230

0

Q22
8

0.1U/10V
1

Q20

HP_R_1

HP-JACK-GREEN

C463
2

C

*2N7002E

*2N7002E
3

1

1

HP_R_2

3

T-GND

SI2 stage:for
ESD issue

AGND

AVDD

(22) SENSE_A_A_R

SENSE_A_A_R

T-GND
AGND

AGND

SENSE_A_A

AGND

T-GND

AGND

LINE OUT

AVDD
R380
100K

3

(22) SENSE_A_A

HP_CONTROL
AVDD

R379
100K
R197
100K

3

2
1

Q34
2N7002

R195

2
Q35
2N7002k

R371
470

(32) DOCK_HP_SENSE

AGND

2

R373
470

100K

C274
2.2U

C248
4.7U

3

1

AGND

C455
2

R370 0_1206

3

1

Q33
2N7002

AGND

DOCK_HP_SENSE

0.1U/10V
1

AVDD
2

AGND

R372
3.9K

R374
3.9K

AGND

C262
4.7U

0.1U/10V
1

C318
2

0.1U/10V
1

C314
2

MIC

T-GND

AGND

CN29

SI2 stage:change to 2N7002K for ESD issue
Q36
2N7002

1

B

HP_L_2

3

2

DOCK_HP_OUT_R
MICSENSE

SR05

1

SI2 sage:change to 0 ohm for
EA audio issue

CN30

U31

1

AGND

SI2 stage:reserve for anti-pop circuit

C

HP_L_1

2

HP_OUT_R

AGND

100U/6.3V HP_L

Q39
2N7002

2

(22) HP_OUT_R

C479

+

(22) HP_OUT_L

HP_OUT_L

56.2 ohm

+

SI stage:change to

*2N7002E

*2N7002E

Q40
*2N7002

1

AGND

2

A_SD

Q19

Q21

3
(26)

2

(22,26)

2

1

PV stage:change for HP request

3

*1K/F

0

R427
100K

EXT_MIC1

L36

BK1608LL121

EXT_MIC1_4

EXT_MIC2

L35

BK1608LL121

EXT_MIC2_4

1
2
6
3
4
5

AVDD

AGND
R376
33K

AGND

C265
470P

C275
470P

B

7

8
MIC-JACK-PINK

DB2 stage:Close CN32

CLOSE TO #3 #5

AGND

AGND

T-GND

T-GND

AVDD
R377
33K

C451
.01U

C450
4.7U

AVDD
(22) SENSE_A_B

AGND

U15
3
5

CLOSE TO #5 #6
C445
33P
A

EXT_MIC1
EXT_MIC2

C268
C263

0.33U
0.33U

EXT_MIC1_1 L37
EXT_MIC2_1 L33

BK1608LL121
BK1608LL121

R190
R188

EXT_MIC1_2
EXT_MIC2_2

10K
10K

EXT_MIC1_3
EXT_MIC2_3

1IN+
2IN+

8
4

VDD+
GND

C453
33P

C444
.1U_16V

1IN2IN-

1
7

1OUT
2OUT

MIC1_1 C448 1U
MIC2_1 C449 1U

MIC1
MIC2

(22)
(22)

AGND

C254
68P

100K

C452

100P

R375

100K

C443

100P

C252
0.1U
AGND

A

SI2 stage:change to 2N7002K for ESD issue

PROJECT : OT2
Quanta Computer Inc.

AGND

SI stage: change to 10k for Mic gain

5

R378

Q11
2N7002K

AGND

TLV2462CDGKR
C266
68P

MICSENSE

2
AGND

2
6

R183
47K

3

AGND

1

AGND

CLOSE TO #2 #3

4

3

2

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

AUDIO AMP&JACK
Sheet
1

23

of

42

5

4

3

2

1

+3VM_LAN_SW

GLAN_TXP-NC
GLAN_TXN-NC

J4
H4

GLAN_RXP-NC
GLAN_RXN-NC

G7
H7

KBIAS_P-RBIAS100
KBIAS_N-RBIAS10

A4
B4
A5

LED0-LINK_UP_N
LED1-ACT_LED_N
LED2-SPEED_LED_N

TX0P_R
TX0N_R

B8
B9

MDI_PLUS[0]-TDP
MDI_MINUS[0]-TDN

TX1P_R
TX1N_R

D9
D8

MDI_PLUS[1]-RDP
MDI_MINUS[1]-RDN

R335 1

2 1.4K/F

LAN_KMRN_RCOMP_P

LAN_KMRN_RCOMP_N
Layout Note:
Place the resistors less than 1" from LAN controller.
(14,25,32) LAN_LINKLED#
(25,32) LOM_ACTLED#

(25)
(25)

TX1P_R
TX1N_R

(25)
(25)

TX2P_R
TX2N_R

(25)
(25)

TX3P_R
TX3N_R

Layout Note:
Keep this resistor on
top side.
Layout Note:
Connect the resistor
to GND near ball E6

TX2P_R
TX2N_R

F9
F8

MDI_PLUS[2]-NC
MDI_MINUS[2]-NC

TX3P_R
TX3N_R

H8
H9

MDI_PLUS[3]-NC
MDI_MINUS[3]-NC

A7
B7

IEEE_TEST_P-NC
IEEE_TEST_N-NC

J6
J7

RSVD_J6-NC
RSVD_J7-NC

E7
E6

RBIAS_P-NC
RBIAS_N-NC

R307
2

*0
1

R336
1

LAN_ATEST_P
LAN_ATEST_N

1.4K/F
LAN_RBIAS_P
2

PAD T85

R306 100/F
1
2

RSVD_B5-NC

A6
C5
B6

RSVD_A6-ADV10/LAN_DIS_N
RSVD_C5-NC
TEST_EN

NINEVEH-EKRON_N (REV 1p0)

R317
49.9/F

R321
49.9/F

R314
49.9/F

R311
49.9/F

2

1

1

2

1
2

E5

1

B
C

Q9
BCP69T1
4

C368
0.1U/10V

C54
4.7U/10V

+1.8V_LOM
C70
10U/6.3V

C

+1.0V_LOM

+3VM_LAN_SW

VCCFC1P0-VCC

H3

VCC3P3[02]-VCCP
VCC3P3[01]-VCC

F2
B3

VCC1P8[04]-NC
VCC1P8[03]-NC
VCC1P8[02]-NC
VCC1P8[01]-NC

G5
F5
D5
C2

+1.8V_LOM

VCC1P0-VCCA2

G4

+1.0V_LOM

VCC[02]
VCC[01]

E4
D4

V1P0_OUT-NC

B1

CTRL_10-NC
CTRL_18-NC

C3
B2

CTRL_10
CTRL_18

THERM_D_P-NC
THERM_D_N-NC

A2
A3

LAN_THERM_D_P
LAN_THERM_D_N

C396
0.1U/10V

C77
4.7U/10V

+1.8V_LOM

B

R982
1
R983
1

PAD T14
PAD T16
PAD T90
PAD T15

1

1

TX0N_R
TX0P_R

1

1

TX1N_R
TX1P_R

VCCF1P0-VCC

JTAG

B5

B

F7
E8
D7

MDI

(25)
(25)

TX0P_R
TX0N_R

VDD1P0[03]-VCCA
VDD1P0[02]-VCCT
VDD1P0[01]-VCCR

GLCI

(13) PCIE_TXP6
(13) PCIE_TXN6

CTRL_18

2

H2
J2

C376
0.01U/25V

1

PCIE_RXP6_R
PCIE_RXN6_R

1

JRXD0
JRXD1
JRXD2

2

D3
D2
C1

2 0.1U/10V
2 0.1U/10V

1

2

LAN_RXD0_R
LAN_RXD1_R
LAN_RXD2_R

3

1 0
1 0
1 0

E

R324 2
R315 2
R313 2

C

(12) LAN_RXD0
(12) LAN_RXD1
(12) LAN_RXD2

2

JTXD0
JTXD1
JTXD2

+3VM_LAN_SW

1

D1
F3
F1

1
1

D

+1.0V_LOM

2

LAN_TXD0_R
LAN_TXD1_R
LAN_TXD2_R

C400
C404

VSSA[17]-NC
VSSA[16]-NC
VSSA[15]-VSSA2
VSSA[14]-VSS
VSSA[13]-NC
VSSA[12]-VSS
VSSA[11]-VSS
VSSA[10]-VSS
VSSA[09]-VSS
VSSA[08]-VSS
VSSA[07]-VSS
VSSA[06]-VSS
VSSA[05]-VSS
VSSA[04]-VSS
VSSA[03]-VSSR
VSSA[02]-NC
VSSA[01]-VSS
VSS[04]-VSS
VSS[03]-VSSP
VSS[02]-VSS
VSS[01]-NC

2

1 0
1 0
1 0

C40
4.7U/10V

C78
10U/6.3V

1

R320 2
R334 2
R327 2

C367
0.1U/10V

1

JRSTSYNC

(12) LAN_TXD0
(12) LAN_TXD1
(12) LAN_TXD2

(13) PCIE_RXP6
(13) PCIE_RXN6

C

JKCLK-JCLK

E3

J9
J8
J5
J3
J1
G9
G8
G6
F6
E9
D6
C9
C8
C7
C6
A9
A8
F4
E1
C4
A1

1

GLCI
Runing
Idle
Idle
Idle
Power down

E2

LCI

LCI
Runing
Runing
Runing
Runing or power down
Power down

C

Q10
BCP69T1
4

2

U6

(12) LAN_RSTSYNC

Link Speed
1000Mbps
100Mbps
10Mbps
No Link
Power down

B

H5
H6

SI stage:change to 1%
33_F
2

XTAL2-X2
XTAL1-X1

(12) GLAN_CLK

1

DB2 stage:change to vender: KDS for
intel recommend

JTAG_TCK-ISOL_TCK
JTAG_TDI-ISOL_TI
JTAG_TDO-TOUT
JTAG_TMS-ISOL_EXEC

R84
1

CTRL_10

2

0MHz
5MHz
50MHz
62.5MHz

G1
H1
G3
G2

JKCLK Pin
Power down
10Mbps
100Mbps
1000Mbps

C689
*0.1U

D

C377
0.01U/25V

C

LOM_XTAL2
LOM_XTAL1

2

GLAN_CLK

Y4
25MHz
C411
27P/50V
1
2

3

1

PV stage:reserve for EMI

E

1 30

2

2

SI2 stage:add R1053 for LAN issue R1053

C410
27P/50V
1
2

+3VM_LAN_SW
*200
2
*200
2

R305
2

*0
1

Layout Note:
Keep this resistor on
top side.

DB1A stage:reserve

2

2
R328
49.9/F

1
C382
470P/50V
2

C375
0.1U/10V
2

C388
0.1U/10V
2

2

C395
0.1U/10V

1

1

1

1
C402
0.1U/10V
2

2

C406
0.1U/10V

1

1

1

1

R325
49.9/F

TX3N_R
TX3P_R

2

2

C71
22U/4V

TX2N_R
TX2P_R

A

1

C385
0.1U/10V

2

C391
0.1U/10V

1

1

2
1

2

+1.8V_LOM

R330
49.9/F

R332
49.9/F

A

2

2

5

4

PROJECT : OT2
Quanta Computer Inc.

1

1
2

C380
0.1U/10V

C392
470P/50V
2

1
C394
0.1U/10V
2

C405
0.1U/10V
2

C379
0.1U/10V
2

3

1

1

1
C387
0.1U/10V
2

C393
0.1U/10V
2

C401
0.1U/10V
2

C378
0.1U/10V

1

1

1
C69
22U/4V

2

Layout Note:
Place termination resistors close to
LAN controller(less than 0.25").

2

C407
0.1U/10V
2

2

C397
0.1U/10V

1

1

2
1

2

+1.0V_LOM

2

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

LAN(Nineveh)
Sheet
1

24

of

42

5

4

3

2

1

LAN
SI2 stage:EMI suggest

RJ45 Connector

LAN_LED_M#

DB2 stage:change to 330 ohm for intel recommend
+3VM

D

LAN_ACTLED_M#

C667
*.1U

C668
*.1U
D

CN14
R1

330

9
LAN_LED_M# 10
XTX0P

1

XTX0N

2

XTX1P

3

XTX2P

4

XTX2N

5

XTX1N

6

XTX3P

7

XTX3N

8

LAN_ACTLED_M#

11
12

+3VM_LAN_SW

DB2 stage:change to 330 ohm for intel recommend

TO SYSTEM
+3VM_LAN_SW

1

3

LAN_LINKLED#

XTX0P
XTX0N

LAN_LINKLED# (14,24,32)

XTX1P
XTX1N
XTX2P
XTX2N

2

Q54
2N7002E

LAN_ACTLED_M# 3

2

1 LOM_ACTLED#

XTX3P
XTX3N

LOM_ACTLED# (24,32)

XTX0P
XTX0N

(32)
(32)

XTX1P
XTX1N

(32)
(32)

XTX2P
XTX2N

(32)
(32)

XTX3P
XTX3N

(32)
(32)

+3VM

Q56
2N7002E

R5

330

1

Q55
DTC144EUA

2

(14,32) PR_INSERT_DOCK#

3

3

R986
10K

R985
10K

TO DOCK

2

LAN_LED_M#

Q57
DTC144EUA

DET_P

DET_P

TX+/0+
TX-/0RX+/1+
NC1/2+
NC2/2RX-/1NC/3+
NC4/3Y+
Y-

13
14

DET1
DET2

1

(14)

G+
G-

15
16

DET_P
R7

GND
GND
RJ45

*0

C

C

DB1A tage:Remove U1, RP24,
RP25, RP26, RP27, and
RP1,C24,C26,C28,R941-R951

LAN RESET

DB2 stage:change to +1.8V_LOM for intel
recommend

3VPCU

2

TX1P_R
TX1N_R

4
5
6

TX2P_R
TX2N_R

7
8
9

TX3P_R
TX3N_R

10
11
12

(24)
(24)
(24)
(24)

MCT1
MX1+
MX1-

24
23
22

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

21
20
19

TCT3
TD3+
TD3TCT4
TD4+
TD4-

3
1

XTX0P
XTX0N
C21
.1U

XTX1P
XTX1N

C22
.1U

SI2 stage:no install R973 ,install
Q48 for HP request

C23
.1U

C630
0.1U

C631
0.1U

MCT3
MX3+
MX3-

XTX2P
XTX2N

MCT4
MX4+
MX4-

15
14
13

XTX3P
XTX3N

+3VM_LAN_SW
R973
SI2301DBS

+3VM transfer to +3VM_LAN_SW

2

3

B

Q48

PVstage:delete C27
R6
75/F

C632
0.1U

+3VM

*0

18
17
16

DB1A
stage:add

NS892402P
C629
0.1U

LAN_RST# (14)

R4
75/F

R3
75/F

R2
75/F

R974
1M/F

C624

(24)
(24)

TCT1
TD1+
TD1-

4

C623
1000P

R975
3

C2
1500P/2KV

DB2 stage:add for intel
recommend,please make sure this
capacitor(C629-C632) is 16V,X7R

PV stage:change to +3VM for
ACBS issue

100K
Q49
2N7002E

2

(14) LAN_PHYPC

4.7U/10V/0805

1
2
3

C622
0.1U

1

TX0P_R
TX0N_R

U43
7SV17

2
100K

U42
7SV17

DB1A
stage:add

+3VM
U18
(24)
(24)

4
R968

LAN TRANSFORMER

C621
0.1U

2
CH751H-40HPT

120K

PV stage:add for EMI

5

BLM18AG601SN1D

1

R967

SI2 stage:change power
source for HP request

L56

C620
0.1U

5

+3VM

3
1

D25

+1.8V_LOM

B

3VPCU

10 ms time delay

1

+3VM

LAN Energy Detect circuit
3

R976
0

Q50

82556 Support Deep Smart Power Down Feature for power saving
R11
*200K

C25
.1U

R21
1.5K

(26,33) ACPRES

2

3

R9
100K

*2N7002E

Q51

1
.01U

TRD0+_EN

R8

10K

.01U

TRD1+_EN

R16

10K

ED_ACT

1
3

C3
10P

R18
1.87K

*2N7002E

2

ENERGY_DET (12)

SI2 stage:no install Q50,Q51
,install R976 for HP request

2

R10
100K

(22,31,34,36,37,38,39,40) MAINON

A

4

-

C4

+

TX1P_R

A

U2
G1331

1

C1

5

TX0P_R

DB2
stage:install

PROJECT : OT2
Quanta Computer Inc.

SI stage:change footprint

SI stage:change to 1.4K from Intel on LAN Energy Detect.

SI2 stage:change to 1.87K for
suggestion
5

4

Intel
3

2

Size
C

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

Transformer&RJ45
Sheet
1

25

of

42

5

4

R1032
0
LOOPBACK
LFRAME#/FWH4
R987
0
PLTRST#
R988
0
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3

(17) PCLK_DBP_1

VIN

3VPCU

SI stage: R1005 install,R297 no install
R1005

SPI_CLK_1 (31)
SPI_CS0#_1 (31)
SPI_SI_1 (31)
SPI_SO_1 (31)
SPI_HOLD#_R
SPI_CS1#_1
LOOPBACK

C362
10U/10V/0805

C371
0.1U

C363
0.1U

C384
0.1U

C369
0.1U

C389
0.1U

R297

C364
1U

SPI_CS1#_1 2

DB2 stage: change to +3V
power source

R365 1 0

DB1A
stage:add

C365
0.1U

R984
*0

C76
10U/10V/0805
ADP_PS0 R290 10K
ADP_PS1 R309 10K

R995

SPI_CS1# (13,14)

D

+3V
C374
0.1U

*0
SPI_HOLD# (31) PV stage:install

R1062

R1062 ,no install
R995

3VPCU
PV stage: reserve for lid S/W for EC side
R329
100K

14M_KBC
(18) LID_SW_EC#

T154
3VPCU
R296 2

1K

KSIN[0..7]

(29) KSIN[0..7]
+5V

+5V

R323
10K

+5V

R319
10K

+5V

R996
10K

R997
10K

DB1A stage:Add

KBCLK
KBDAT
TS_CLK
TS_DAT

B

IMCLK
IMDAT
KCLK
KDAT
EMCLK
EMDAT

(12,30) LAD0/FWH0
(12,30) LAD1/FWH1
(12,30) LAD2/FWH2
(12,30) LAD3/FWH3
(12,30) LFRAME#/FWH4

*0
SERIRQ

(14,20,30) SERIRQ

35
36
38
40
41
42

0

R943

(13,19,28,30) PLTRST#

SI stage:R1045-R1048
R1045
0
R1046
0
R1047
0
R1048
0
EMCLK
T88
EMDAT
T10

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

(17) PCLK_KBC
(14,20,30) CLKRUN#

LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LFRAME#/FWH4
PCLK_KBC
CLKRUN#
14M_KBC

(17) 14M_KBC

ADP_PS1

DB2 stage:install 0 ohm
R1011

C370 (14) RUNSCI_EC#
*10P

46
48
50
51
52
53
54
55
57
59

LAD0
LAD1
LAD2
LAD3
LFRAME~
LRESET~
PCI_CLK
CLKRUN~
SER_IRQ
CLOCKI

0

45
76

LPCPD~/GPIO23
EC_SCI~

KBC_XTAL1

70

XTAL1

KBC_XTAL2

71

XTAL2

Y1
32.768KHZ
1
2

TQFP128-16X16-4

68

GND
GND
GND
GND
GND
GND
GND

R300

29
28
27
26
25
24
23
22

*4.7K

3VPCU
3VPCU

SI2 stage:add for HP request
KBC_PW_ON (31)
3VPCU
OUT0
OUT1/IRQ8~
OUT7/SMI~
OUT8/KBRST
OUT9/PWM2
OUT10/PWM0
OUT11/PWM1

124
125
123
122
121
120
118

GPIO01
GPIO02
GPIO03
RESET_OUT~/GPIO06
GPIO07/PWM3
GPIO08/RXD
GPIO09/TXD

107
79
80
60
85
86
87

GPIO11/AB2A_DATA
GPIO12/AB2A_CLK
GPIO13/AB2B_DATA
GPIO14/AB2B_CLK
GPIO15/FAN_TACH1
GPIO16/FAN_TACH2
GPIO17/A20M
GPIO19/WINDMON/24MHZ_OUT
GPIO20/PS2CLK
GPIO21/PS2DAT
32KHZ_OUT/GPIO22
GPIO25/(PGM)
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32

88
89
90
91
92
101
102
61
103
105
75
73
74
93
98
99
100
126

AB1A_DATA
AB1A_CLK
AB1B_DATA
AB1B_CLK

111
112
109
110

KBC1070

11
37
47
56
82
104
117

(29)
(29)

KSIN0
KSIN1
KSIN2
KSIN3
KSIN4
KSIN5
KSIN6
KSIN7

AGND

FOR EMI

T86
T83

(34) CELL_DET

1

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12/GPIO00/KBRST
KSO13/GPIO18
GPIO04/KSO14
GPIO05/KSO15
GPIO24/KS016
GPIO26/KSO17/(EA~)

72

C366
*10P

VCC0

21
20
19
18
17
16
13
12
10
9
8
7
6
5
81
83
4
108

LPC Bus

R291
*33

KSOUT0
KSOUT1
KSOUT2
KSOUT3
KSOUT4
KSOUT5
KSOUT6
KSOUT7
KSOUT8
KSOUT9
KSOUT10
KSOUT11

Keyboard/Mouse Interface

C372
*10P

General Purpose I/O Interface

(29) KSOUT[0..11]

R322

A_SD

1
2
3
30
31
32
33
34
43
44
62
63
64
65
66
67
94
95
96
97
127
128

U4

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

R301
*33

TEST_PIN
PWRGD
VCC1_PWRGD
DMS_LED~/GPIO10
BAT_LED~
PWR_LED~/8051TX
FDD_LED~/8051RX

R1060 10K

KBC_PW_ON

R316
10K
D5
1

BAT_GRNLED# (29)

BATSELB

T89
A_SD

PWM_FAN#
CC-SET

(23)
PWM_FAN# (29)
CC-SET (33)

3VPCU

PWSWON# (31,32)
R294

BATLOW# (14)
PWROK (31,39)

0

RSMRST#_R

BGA_MON_DET (11,14)
CAP_RST (29)

R292
3VPCU

CA_DATA
CA_CLK

R298
100K
D4
1

RB751V-40
2

GATEA20 (12)
NUMLED#

SLP_S3#
ADP_EN
CA_AKZ
ACPRES

CA_AKZ

(14,31)
(34)
(29)
(25,33)

R1030
10K

3VPCU
SUSM#

GPIO29
2 R289 0 1

GPIO29 (14)
AMT ADP_PRES (14)

SERR#

(14,31)

SI stage: add to avoid leakage current
Q60
2N7002E

(13)
3

MBDATA
MBCLK

1

EAPD

(22,23)

MBDATA (33)
MBCLK (33)

ABDATA
ABCLK

69 TEST_PIN
78
77
116
113
115
114

C

*0 HWPG_1

3VPCU

CA_DATA (29)
CA_CLK (29)
ME_EC_DATA (14)
R295
ME_EC_CLK (14)
10K
AIR_NON_CHG# (33)
MBAT_ID (33)

MBAT_ID
GATEA20_R
ADP_PS0
NUMLED#
SLP_S3#

KBCCPURST# (12)

DB2 stage:change to 100K for
same as Chimay

R284
100K

T7

BATLOW#

RB751V-40
2

T8
T87

2

0

49

1 0

VCC2

SPI_HOLD#_R 2 R50

14
39
58
84
106
119

PCLK_KBC

(14) NPCI_RST#

HWPG_1

VCCRTC

87216-24

(30)
(30)

*0

3VPCU

For debug(BIOS)

C

0

C398
0.1U

CAP

500mA

1

+3V

POWER_LED#
CAPSLED#
NUMLED#
VCC1_PWRGD

13
14
15
16
17
18
19
20
21
22
23
24

1
2
3
4
5
6
7
8
9
10
11
12

B

+3V
SI stage: add to avoid leakage current
HWPG_1
R286

R285
1K

0

HWPG (20,31)
VCC1_PWRGD (31)

LED_BAT# (29)
POWER_LED# (29,32)
CAPSLED#
R310
10K

15

D

2

VCC1
VCC1
VCC1
VCC1
VCC1
VCC1

+3V

3

DB2 stage:change pin12 to VIN, pin16 to
VCC1_PWRGD,reserve R987,R988 for +3V

SI stage:add for EA team easy test
CN6

R308
10K

R304
100K

R31
3VPCU
R58
C35
22P

C31
22P

*4.7K

0

3VPCU

RSMRST#_R

1

*MMBT3906
3

RSMRST# (14)

3VPCU

R287
3VPCU

R283
MD2

MBDATA R299
MBCLK R302

4.7K
4.7K

R288

DB1A stage:no install R31,Q8,install
R58

A

3VPCU
TEST_PIN

*4.7K

10K

2

DB2 stage:move T/P connector to Finger
board

3VPCU

C101
4.7U/10V

Q8

1K

A

PROJECT : OT2
Quanta Computer Inc.

MD1
BAV99

BAV99
R29
2.2K

5

4

3

2

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

SMSC 1070
Sheet
1

26

of

42

5

4

MB_CRT_R1

L8

BK1608LL680

MB_CRT_R2

MB_CRT_G1

L10

BK1608LL680

MB_CRT_G2

MB_CRT_B1

L14

BK1608LL680

MB_CRT_B2

3

2

1

5V_CRT
F1
2

C661
*18P

C662
C663
*18P *18P

C146
*18P

C116
C133
*18P *18P

1

+5V
POLY SWITCH 1.1A
C415
0.1U

D

SI2 stage:reserve for EMI
suggestion
CRT_R

(7)

CRT_G

(7)

CRT_B

D

for EMI suggestion

CRT PORT

L22

39nH

L19

110nH

CRT_R_1

L24

39nH

L21

110nH

CRT_G_1

L23

39nH

L20

110nH

CRT_B_1

16

(7)

SI2 stage:change

6
1
7
2
8
3
9
4
10
5

MB_CRT_R2
C178
C180
18P
18P

C179
18P

MB_CRT_G2
MB_CRT_B2
T91

CN22
CRT_CONN

11
DDCDAT2

12
13

PR_CRT_HSYNC

14

PR_CRT_VSYNC
DDCCLK2

15

close to Northbridge
17

C

C161
*10P

C155
*10P

C159
*10P

C

C414
*10P

+5V

For EMI

1

S

VCC

16

2

1B1

OE#

15

MB_CRT_B1 3

1B2

4B1

14

4

1A

4B2

13

5

2B1

4A

12

MB_CRT_G1 6

(32) DOCK_CRT_B

CRT_B_1
(32) DOCK_CRT_G

CRT_G_1

2B2

3B1

11

7

2A

3B2

10

8

GND

3A

9

R114

0 C153
.1U
2

PR_INSERT#

(14,22) PR_INSERT#

1

U12

+3V

5V_CRT

ESD PROTECTION

DOCK_CRT_R (32)

C419
0.1U

MB_CRT_R1

C417
0.1U
U14

CRT_R_1

1
2
3
4
5
6
7
8

FSAV330QSCX_NL

B

VCC_SYNC
VCC_VIDEO
VIDEO_1
VIDEO_2
VIDEO_3
GND
VCC_DDC
BYP

SYNC_OUT2
SYNC_IN2
SYNC_OUT1
SYNC_IN1
DDC_OUT2
DDC_IN2
DDC_IN1
DDC_OUT1

16
15
14
13
12
11
10
9

R120
CRT_HSYNC
R117
CRT_VSYNC
DDCCLK1
DDCCLK
DDCDATA
DDCDAT1

39

PR_CRT_HSYNC (32)
CRT_HSYNC (7)

39

PR_CRT_VSYNC (32)
CRT_VSYNC (7)

R122

0 DDCCLK2

DDCCLK (7)
DDCDATA (7)

R349

0 DDCDAT2

B

CM2009

S

Accelerometer Sensor
SES_INT

OE#

C418
0.22U
+3V

DDCCLK2 (32)

Function

L

L

A=B1

H

L

A=B2

R354
2.2K

R351
2.2K

R352
2.2K

R353
2.2K

DDCDAT2 (32)

2 R228
1
8.2K
D17

+3V

DB1 stage:install R373

BAS316

+3V
U16

C315
10U

C317
0.1U

C295
0.1U

A

(13)

SES_INT

(4,17,19) SMBDT
(4,17,19) SMBCK
+3V

R213

10K

13
11
4

VDD
VDD
VDD_IO

10
15
12

Reserved
Reserved
Reserved

1
2
3
5
6
8

RDY/INT
SDO
SDA/SDI/SDO
SCL/SPC
CS
CK

NC

7
5V_CRT

A

GND
GND
GND

PROJECT : OT2
Quanta Computer Inc.

16
9
14

LIS3LV02DL
5

4

3

2

Size
B

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

CRT PORT
Sheet
1

27

of

42

1

2

3

4

5

6

7

8

1.8 inch HDD CONNECTOR

HDD, CD-ROM

CN19
45
41
+3V

42
1
2
(12) PDA[0..2]

PDA[0..2]

PLTRST_#

3

PDD[0..15]

PDD7

5

PDD6

7

(12) PDD[0..15]

PDIOW#
PDDREQ
PDIORDY
PDIOR#
IRQ14
PDDACK#
PDCS1#
PDCS3#

(12)
PDIOW#
(12)
PDDREQ
(12) PDIORDY
(12)
PDIOR#
(12)
IRQ14
(12) PDDACK#
(12)
PDCS1#
(12)
PDCS3#
(13,19,26,30) PLTRST#

PDD5

9

PDD4

11

PDD3

13

PDD2

15

PDD1
33

A

60MIL

6

PDD8

8

PDD9

10

PDD10

12

PDD11

14

PDD12

16

PDD13

18

PDD14

20

PDD15

22

PDDREQ

24

PDIOW#

C399
0.1U

C390
1000P

C403
0.1U

C383
10U/10V/0805

17

PDD0
R282

0_0805

4

A

PLTRST#

L44

HDD_VDD

19

PLTRST_#
21
23
PDIOR#

25
26

PDIORDY

27

PDDACK#

29

PDA1

31

PDA0

33

28

B

PDCS1#
(29)

IRQ14

32

PDIAG

34

PDA2

36

PDCS3#

35

HDDLED#

HDDLED#

B

30

37
38

HDD_VDD

39

HDD_VDD

40
43

44
46

DB2 Stage:delete CN9,R463,C533,C532,C522,C523,C511,R488
40-Pin

CD-ROM
C

PDIOW#
PDIORDY
IRQ14
PDA1
PDA0
PDCS1#
HDDLED#
CDVCC

D

CDVCC

R178

470R CDSEL
T39
CN26

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

51
52

PLTRST_#
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0

51
52

C

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDDREQ
PDIOR#

CDVCC

+5V

PDDACK#
IOCS16#
PDIAG
PDA2
PDCS3#

T28

C203
0.1U

C208
0.1U

2

3

4

C209
0.1U

C206
0.1U

C211
10U/10V/0805

CDVCC

T41

D

T40

PROJECT : OT2
Quanta Computer Inc.

CD-ROM

CDSEL
--> High, Slave device

1

60MIL

L27
PBY201209T-4A

5

6

Size
B

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

HDD,CD-ROM
7

Sheet

28

of
8

42

5

4

3

2

1

APPLICATION
BUTTON BOARD
3VPCU

TRACK POINT

(26)

KEYBOARD

CA_CLK
CA_DATA

R15
R13

4.7K
4.7K

R_BUTTOM

3VPCU

KSOUT11
KSOUT0
KSOUT2
KSOUT5
KB_KSIN14
KB_KSIN8
KB_KSIN12
KB_KSIN10
KB_KSIN0
KB_KSIN4
KB_KSIN2
KB_KSIN1
KB_KSIN3
KSOUT3
KSOUT8
KSOUT4
KSOUT7
KSOUT6
KSOUT10
KSOUT1
KB_KSIN5
KB_KSIN6
KSIN7
KB_KSIN13
KB_KSIN11
KB_KSIN9
KSOUT9

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

C

L_BUTTOM
R_BUTTOM

CN7

CP2
1
3
5
7

*220PX4
KB_KSIN12
2
4
KB_KSIN8
6
KB_KSIN14
8

CP3
1
3
5
7

*220PX4
2
4
6
8

KB_KSIN2
KB_KSIN4
KB_KSIN0
KB_KSIN10

CP4
1
3
5
7

*220PX4
2
4
6
8

KSOUT8
KSOUT3
KB_KSIN3
KB_KSIN1

KSOUT5
KSOUT2
KSOUT0
KSOUT11

KSIN2
KSIN3
KSIN6
KSIN7

10
9
8
7
6

KSIN1
KSIN0
KSIN5
KSIN4

1
2
3
4
5

(26)
(26)

L_BUTTOM
TS_CLK
TS_DAT

TS_CLK
TS_DAT

3VPCU
+5V

10KX8

3VPCU
CA_AKZ
R1022

KSOUT10
KSOUT6
KSOUT7
KSOUT4

CP6
1
3
5
7

*220PX4
2
4
6
8

KSIN7
KB_KSIN6
KB_KSIN5
KSOUT1

CP7
1
3
5
7

*220PX4
2
4
6
8

(26)

CA_DATA

R14
1

10
2

CA_CLK_1

R12 210
1
R1000
0/F

CA_DATA_1
POWER

+3V
C7
1000P

C8
1000P

C6
1000P

C9
1000P

3VPCU

*0/F

33P

FAN OUT PWM CONTROL

D1
R279

R1003

330

5VPCU

CN37

LED

CA_AKZ
CAP_RST_1

CN25
L45

5V_FAN

0-0805

1
2
3
4

(26) PWM_FAN#
5VPCU
C421
10U

R278
10K

R277
10K

C424
0.1U

1
2
3
4
5
6
7
8
9
10
11
12

CA_CLK_1

FAN
C416
1000P

CA_DATA_1
POWER
RF_LED_1#

C423
1000P

BAT_GRNLED#1
3VPCU

2

3

ACC_LED#
R1061

G_BATLED# (12)

2

LED BOARD

5VPCU

+5V 5VPCU

Accelerometer LED
2

(14) ACC_LED

Q26

Q45
DTC144EUA

Q64

U24

2N7002E

2

R544
10K

1

1

2N7002E

U23

1K

3

(26) BAT_GRNLED#

Q27

3

2N7002E
1

DB2 stage:change K/B footprint

B

KB_KSIN0

4

3

KSIN0

KB_KSIN4

4

ACC_LED#
KB_KSIN12

5

HDD LED

1

KB_KSIN8

5
5VSUS

2 KB_KSIN13

2 KB_KSIN9

(28) HDDLED#

POWER/SLEEP LED

5VPCU

1
2
3
4
5
6
7
8
9
10
CN12

HDDLED#
R543

330

R552

330

R554

330

R556

330

LED_BAT#

(26) LED_BAT#

BAT_GRNLED#1
KSIN1

1 KB_KSIN1

6

KSIN5

POWER_LED_1#

POWER LED

1 KB_KSIN5

6

RF_LED#
UMP11

R275
10K

3

KSIN2

KB_KSIN6

4

+3V
C614
0.1U

POWER_LED_1#

U27

4

W/L B/T ON/OFF LED

3

3

U26
KB_KSIN2

R276
10K

KSIN6

R535

+3V

10K
5

UMP11

Active : LOW
2

1 KB_KSIN3

6

6

1

Q25
(19)

2N7002E
Q24

BT_LED

Active : High

1
4

D23
1

3

10K

1
U41
TC7SH08FU

2

A

SW1010CPT
(30)

UMP11

5

WWAN#

Active : LOW

2

(26,32) POWER_LED#
UMP11

2N7002E
1

A

KSIN3

4
R536

+3V

3

2 KB_KSIN11

2

(19) RF_LINK

2

C601
0.1U

3

5

PROJECT : OT2
Quanta Computer Inc.

2
Q44
DTC144EUA
1

KB_KSIN14

5

3

KB_KSIN10

B

LED-BOARD

KSIN4

3

C

SW-BOARD

PV stage:dul-layout for second source
KSOUT9
KB_KSIN9
KB_KSIN11
KB_KSIN13

D

C11

33P

SI stage: change footprint for another vender

POWER_LED_1#

0/F RF_LED_1#

SW-BOARD

C10

KSIN[0..7]

R1002

CA_DATA_1
CA_CLK_1

KSOUT[0..11]

(26) KSIN[0..7]

1
2
3
4
5
6
7
8
9
10
11
12

+3V

TRACK POINT

+5V

*220PX4
2
4
6
8

CA_CLK

RF_LED#

C618
1000P
(26) KSOUT[0..11]

CP5
1
3
5
7

*10K

3VPCU

(26)

3

D

*220PX4
2
4
6
8

10k
CAP_RST_1

0/F

DB2 stage:install

8
7
6
5
4
3
2
1

RP28
CP1
1
3
5
7

CN5
R998

(26) CAP_RST

CN8

KEYBOARD

C12

CA_AKZ

2

Size
B

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

FAN ,KB,LED,TP
Sheet
1

29

of

42

5

4

3

2

1

SI stage:it make for a much smoother transition when modems transition to deriving the IO voltage from that pin

BLUE TOOTH

3VSUS

MDC

DB2 stage:move T/P connector to Finger board,so change connector type
3V_FP

(12) ACZ_SDOUT_MDC
CN11

R539
R540

USBP1USBP1+

0
0

8
7
6
5
4
3
2
1

USBP1-1
USBP1+1
(26)
(26)

3V_FP

KBCLK
KBDAT

C599 +5V
0.1U
C600
1000P

ACZ_SDOUT_MDC
ACZ_SYNC_MDC
R184
33 AC_SDIN1

(12) ACZ_SYNC_MDC
(12) ACZ_SDIN1

D

(13)
(13)

CN35

CN28
1
3
5
7
9
11

C246 *10P

GND
A_SDO
GND
A_SYNC
A_SDI
A_RST#

REV
REV
VCC
GND
GND
A_BCLK

C230
0.1U

2
4
6
8
10
12

C239
2.2U

(13)
(13)
(29)
(19)
(19)

ACZ_BITCLK_MDC

ACZ_BITCLK_MDC

R553
R550

USBP6+
USBP6-

BT_LED
CH_DATA
CH_CLK

SI stage:Change power source to avoid leakage currurt
R185
*33

R538
10K

(13)

BT_OFF

BT_OFF

1

CN17

Q46
IRLML5103

2

+3V_BT
3

3
4

TIP GND
GND
RING

24mil
1

2

2
220K

CN16
1

D

R549

RJ11 CONNECTOR
TIP
RING

10
9

3VSUS

C634 Finger Printer/Touch pad
0.1U

2
1

1
2
3
4
5
6 10
7 9
8

BLUE TOOTH

3V_S5

C247
*10P

MDC

0 USBP6+1
0 USBP6-1

(12)

MDC

(12) ACZ_RST_MDC#

1
2
3
4
5
6
7
8

+3V_BT

C235
1000P

1

FINGER PRINT

RJ11
C30
1000P

C356
100U/10V

C359
1000P

C358
0.1U

2

C37
1000P

SI2 stage:delete R280,R281for EMI suggestion
C

C

TPM (1.2)
+3V
5VSUS

U10

PCLK_TPM
U29
5
4
2

C440
1U

OUT

1

ON# SET

3

IN

USBPWR0_1 R369

+
C441
470P

R368
*6.8K

GND

(12,26)
(12,26)
(12,26)
(12,26)
(17)

0-0805
R107
*33

C439
220U/6.3V_ESR25

G5240

LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
PCLK_TPM

(12,26) LFRAME#/FWH4
(13,19,26,28) PLTRST#
(14) SUS_STAT#
(14,20,26) SERIRQ

C129
*10P

LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
PCLK_TPM

26
23
20
17
21

LAD0
LAD1
LAD2
LAD3
LCLK

LFRAME#/FWH4
PLTRST#
SUS_STAT#
SERIRQ

22
16
28
27

LFRAME#
LRESET#
LPCPD#
SERIRQ

CLKRUN#

15

PV stage:change to 220U for USB drop fail issue
R176

9
(14,20,26) CLKRUN#

FOR EMI

0

+3V

1
3
12

CN27
EB1
(13)
(13)

2
3

USBP0USBP0+

2
3

1
4

USBPWR0
USBP0-1
USBP0+1

1
4

1
2
3
4

B

*1632090
R173
0

Address

USB 1

HIGH
LOW

Suyin_020173

R116
4.7K

BADD
4EH/4F
2EH/2FH

C218
*Clamp-Diode

CLKRUN#
NC
NC
NC

10
19
24
5

GND
GND
GND
GND

4
11
18
25

GPIO
GPIO2
PP
TESTI

XTALI/32K IN
XTALO

+3V

C122
0.1U

C137
0.1U

C111
0.1U

C135
0.1U
R90
*4.7K

R100
*4.7K

R91
4.7K

R103
4.7K

6
2
R109
R110

7
8
13
14

*0
*0

+3V

TPM_XIN
TPM_XOUT
Y3
32.768KHZ
1
2

SLB9635

(default)

C148
22P

B

C147
22P

R115
*4.7K

2

2

1

ESD
1

8
7
6
5

GND
GND
GND
GND

TEST/BADD

VDD
VDD
VDD
VSB

C213
*Clamp-Diode

5VSUS
C97
1U

POWER USB (LEFT SIDE)
R93
10K

U7
12
9
3
5

R79

USBOC#5

0

4
6
13

A

C93

R88
*0

NC
OUT
OUT

SEL
FAULT
ISET

8

PV stage:change to 220U for USB drop fail issue
10
1
7

ON(ON)
GND
THREMAL-G
MAX1563

*1000P

NC
NC

11
2

R72
4.22K

4.7U/10V/0805/X5S

C90

+

C73

C102
0.1U

C108
1000P

220U/6.3V_ESR25
R326

0
CN21

EB2
(13)
(13)

3
2

USBP5USBP5+

3
2

4
1

USBPWR1
USBP5-1
USBP5+1

4
1

*1632090
R331
0

I
5

Limit:17120/R814
=17120/4220=4.05687A
4

3

1
2
3
4

GND
GND
GND
GND

8
7
6
5

A

USB 2

1

Suyin_020173

PROJECT : OT2
Quanta Computer Inc.

2

1

ESD

2

(13)

IN
IN

C92
*Clamp-Diode

C99
*Clamp-Diode

2

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

USB,BT,FP,TPM,MDC
Sheet
1

30

of

42

5

4

3

2

1

POWER SEQUENCE

1

(36) HWPG_1.25VM

HWPG_1.05VM
1

+3V

2

D30
D29 CH751H-40HPT
2

+3V
CH751H-40HPT
D28
0
1

+3V
R89
10K

D12

BAS316

D13

*BAS316

D14

(37) HWPG_1.8VSUS

HWPG

2

2

MPWROK (7,14)

R989

4

*180K

2

CH751H-40HPT

VRON

4

VRON

R993
10K

(38,39)

Q58

*BAS316

C627
*1U

U45
*7SV17

*2N7002E

2

SMDDR_VTERM
U44
*7SV17

D

3

5

C626
*0.1U

R994

3.3K

Q59

2

C95
*1U

MMBT3904
1

1

(36) HWPG_1.05VM

R992

3

(35) HWPG_3/5VPCU

BAS316

*1SS355
2

3
1

D11

(36) HWPG_1.25V

D27
1

C625
*0.1U

3
1

(38) INT_VGA_PWRGD

D

*BAS316
5

D7

HWPG_1.8VSUS
3V_S5

DB1A stage: no install
D7,D13,D14,C95

3VPCU

R980
HWPG

0

(20,26)

3VPCU
+3VM

DB1A stage: reserve for
power sequence modify

5

R303
100K

2

VCC1_PWRGD

4

+3VM

ICH_PWROK (14)

3V_S5

3
1

3V_S5

2
4

2

1

R333

4

0

3

1
U25
TC7SH08FU
3

R345
10K

3.3K

SPI_WP0#

U22
TC7SH08FU

(13)

SPI_CS0#

SPI_CS0#

(13)

SPI_CLK

SPI_CLK

(13)

SPI_SI

R357 2
2
R356
C431
*33P

R367
2
R361

(26) SPI_CLK_1
(26) SPI_CS0#_1

2

(26) SPI_SI_1

2

(26) SPI_SO_1

2

1 0
1 0

SPI_CLK

C433
*33P

1 0

SPI_CLK_R_0

6

1
0

SPI_SI_R_0

5

C432
*33P

VSS

4

W
C

HOLD

1

SPI_S0

R343
10K

(4,14) XDP_DBRESET#

VCC

3
7

5

0

0

R355

(26) SPI_HOLD#

C408
0.047U

5
R942
R344

CN23
8

3.3K

SI2 stage:delete R49

(26,39) PWROK

C426
0.1U

R362

C413
0.047U

C

(7,14,39) DELAY_VR_PWRGOOD

FLASH ROM(BIOS)

VCC1_PWRGD (26)

U19
7SV17
C373
0.1U

16Mbit (2M Byte), SPI
+3VM

S
C
Q

D

2

SPI_SO_R_0 R366 15

SPI_SO

G6179-1001

SPI_SO (13)

C430
33P

PV stage:change R357,R356 to 0 ohm,and C431,C432,C433 no install for intel request

SPI_CS0#

R147

POWER SWITCH

SPI_SO

B

2

R318
10K
2
4

3

R978

1
Q28
2N7002E

C386
0.1U
R979

0

0

NBSWON#

NBSWON# (14)

DB1A stage:add
PWSWON#

3VPCU
C118
0.1U

5

2
S5_ON

1

S5_ON (40)

(14)

SLP_S5#

1

C679
0.1U

3
*0

R312

*0

5VSUS

+3V

SUSON (37,40)

U20
TC7SH08FU

3
R113

SUSON

4

U13
TC7SH08FU

+1.05V

+5V

2
4

due to only one 4MB

3VPCU

DB1A
stage:add
C151
0.1U

5

SI stage:delete CN24
flash part

PWSWON# (26,32)

3VPCU
3VPCU

(26) KBC_PW_ON

SPI_SI

1 0

3V_S5

B

SW1
1
3
5

1 0
R146

3VPCU

C680
0.1U

C681
0.1U

C682
0.1U

C152
0.1U

C157
0.1U

C119
0.1U

C103
0.1U

C110
0.1U

C121
0.1U

C136
0.1U

C130
0.1U

C134
0.1U

3VPCU

3VPCU
3VPCU
A

5

C381
0.1U
4

1

EMI

2
(14,26) SUSM#

2
(14,26) SLP_S3#

A

C131
0.1U

5

3VPCU

MAINON

IAMT_ON

4
1

IAMT_ON (36,37,40)

U9
TC7SH08FU

MAINON (22,25,34,36,37,38,39,40)

PROJECT : OT2
Quanta Computer Inc.

3

3

U11
TC7SH08FU
R94
R108
5

*0

*0
4

3

2

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

POWER SEQUENCE,BIOS
Sheet
1

31

of

42

A

B

C

D

E

VA

DOCKING BOARD CONNECT

1

1

C678
.1U/50V_6

51

2

C677
.1U/50V_6

VA

PV stage:for EMI
request

C360
0.1U

(25)
(25)
(25)
(25)

LAN

C361
0.1U

5VSUS
+5V

(13)
(13)

3

R33
R37

USBP7+
USBP7-

(7)
TV_C/R
(7)
TV_Y/G
(26,29) POWER_LED#

TV

USBP7+1
USBP7-1

0
0

TV_C/R
TV_Y/G
POWER_LED#
DOCK_CRT_B_1
DOCK_CRT_G_1
DOCK_CRT_R_1

CRT
Line-out

(23) DOCK_HP_OUT_L
(23) DOCK_HP_OUT_R

AGND
DOCK_HP_OUT_L
DOCK_HP_OUT_R

R68
R65

0
0

47

48

24
25
26
27

1
2
3
4

28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

XTX2P
XTX2N
XTX3P
XTX3N

XTX2P
XTX2N
XTX3P
XTX3N

(25)
(25)
(25)
(25)

DOCK_CRT_G_1

L6

BK1608LL680

1

H3
H13
H-C313I160D110P2 h-c197d47p2

5VSUS

ADP_ID
PWSWON#
PR_INSERT_DOCK#
DDCDAT2
DDCCLK2
PR_CRT_HSYNC
PR_CRT_VSYNC
AGND
LINE_IN_SENSE
DOCK_HP_SENSE
0
DOCK_LINE_IN_L
0
DOCK_LINE_IN_R

R75
R70

ADP_ID (33,34)
PWSWON# (26,31)
PR_INSERT_DOCK# (14,25)
DDCDAT2 (27)
DDCCLK2 (27)
PR_CRT_HSYNC (27)
PR_CRT_VSYNC (27)
LINE_IN_SENSE (22)
DOCK_HP_SENSE (23)
DOCK_LINE_IN_L (22)
DOCK_LINE_IN_R (22)

SI2 stage:add for EMI suggestion
3V_S5

CRT

3

R34
10K

Line-in

PR_INSERT_DOCK#
C36
0.1U

DOCK

H15
H-C315I160D110P2

H2
H-OT1-2-2P

H1
H-OT1-1-2P

H16
h-c157d47p2

+1.05V
+1.05V
+1.05V
+1.05V
1.8VSUS

H20
h-c157d47p2

1

+1.5V
+1.5V

1

2

1

2

1

1

1

1
1

H12
H11
H-C313I160D110P2 H-C313D110P2

H9
h-r313x165d118p2L

H19
H-C313D110P2

H18
h-c313d118p2

EMI spring
PAD7

H17
h-c157d47p2

VA
H21
h-c157d47p2

VIN
VIN
VIN

EC4
EC11
EC12
EC2
EC8

470P
*0.1U
*0.1U
*0.1U
*0.1U

EC16
EC17

*0.1U
*0.1U

EC5
EC6

*0.1U
*0.1U

EC1

*0.1U

EC10
EC14
EC13

*0.1U
*0.1U
*0.1U

+3V
+3V
5VSUS
5VSUS
+1.5V

2

+3V
+3V
+3V
+3V
+3V
3VPCU
+3V
+3V

1

1

1

1

1

1

1

1

1

1

1
H23
h-O91x59d91x59n

4

LAN_LINKLED# (14,24,25)
LOM_ACTLED# (24,25)

H22
h-c59d59n

PAD1
EMIPAD-276X100

*5.6P

C660
1000P
LAN_LINKLED#
LOM_ACTLED#

1.8VSUS
+5V

H8
h-c313d118p2

C38

*5.6P

ADP_ID

2

PAD3
EMIPAD-276X100

DOCK_CRT_R_1
C51

LAN

Area of Hole
PAD2
EMIPAD-276X100

1

DOCK_CRT_B_1

BK1608LL680

C60

50

Pin43 for Dock detect

EMI spring
PAD8

BK1608LL680

L5

*5.6P

XTX0P
XTX0N
XTX1P
XTX1N

XTX0P
XTX0N
XTX1P
XTX1N

DB2 stage:modify due to no LAN S/W

USB

(27) DOCK_CRT_R

L4

CN15

49

52

4

(27) DOCK_CRT_G

2

1
C676
.1U/50V_6
2

C675
.1U/50V_6
2

C674
.1U/50V_6
2

2

C673
.1U/50V_6

1

1

1

(27) DOCK_CRT_B

H7
h-c313d118p2

H6
H-C313D110P2

H5
H-C313D110P2

H14
h-c313d118p2

H4
H-C313D110P2

FOR EMI

1

H10
h-c197d47p2

EMI spring
PAD6

EMI spring
PAD4

1

1

1

1

1

1
EMI spring
PAD5

1

1

1

1

PROJECT : OT2
Quanta Computer Inc.

1

SI stage:for modem cble

A

and mic cable

B

C

D

Size
B

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

DOCKING
Sheet
E

32

of

42

5

4

3

AC power from docking or system AC
jack.Will not present at the same
time.

E

Normal:19.5 Volts
Airline:15.0 Volts

PR13

ADP_ID (32,34)

(34)

2

2

2

4

0_4

-

3

PR120
10K_4

PR183

*0_4

2

REFIN

12
ACOK#

9
28

SHDN#

8

CCV

7

CCI

6

DLO

ICHG

PGND

IINP
SHDN

CSIP
CSIN

CCV

BATT

CCI

REF

2

PC149
.01U/50V_6

GND

CCS

PR172

PC120

*2.2_6

*1000P_4

2

4.7uH L-F

2P

16

MBAT+

4

8724_REF

3 CLS

3

4
S2

2

1

G2

CSIP

(34)

CSIN

(34)

D1

PC150
1U/10V_6
0_4

CLS connect to REF
For Full-scale 75mV

6

5

1P
PC6
.1U/50V_6

PC7
10U/25V/1206

PC8
10U/25V/1206

PL2
FBMJ3216HS800

7

4

MBAT
MB_DATA

2

PC106
.01U/50V_6

MB_CLK

3

EC: SI2

1

PR135
100_4

BAT_CONN

PR393
100K_6

PR134
100_4

EC: SI1
PR110
100K_4

B

(26)
(26)

EC: SI1
PR205
15K_6

MBDATA (26)

MBAT_ID
PD8
UDZS5.6B

PD19
2

SHDN#

1

3

1

CH501H-40
PR211
470K/F_4

PC184
.1U/16V_6

PD7
UDZS5.6B

2

PC363

Change PR110 from
10K to 100K
Remove
PR113,PR130,PC105,PC24,PR131,PR132,PQ25,PQ26

2

CC-SET

MBCLK
1

DEL PR211-0ohm

ACOK#

1

PD20
SW1010C

1P

MBAT+

1

CN18

ACOK#

(26)

2P

1

19
18

(25,26) ACPRES

8724_ACIN

2

15m/1W/3720 L-F

20

2

PR204
10K_4

C

PR22
2

3VPCU

Present AC:
When AC voltage level > 12.3 Volts.

4

1

2

MBAT+
PL4
1

PQ51
DTA124EUA

B

PC109
10U/25V/1206

PQ5
SI4814DY L-F

2

CLS

PC45
10U/25V/1206

5

CHG_DL

PC132
.1U/50V_6

6

21

G1

CHG_LX

S1D2

CHG_DH

23

PC43
.1U/50V_6

1

PR203
0_4

1

24 CHG_BST

25

PC42
2200P_4

2

1

2
1

8724_LDO

26

ACOK

GND

CCS 5
PC148
.01U/50V_6

2

8724_LDO

22 8724_DLOV

PR212

PC147
.1U/16V_6
1

DHI
REFIN

1

1

PC142
*1000P_4

1

PR213
1K_6

2

PR210
10K_4

3

11

PC141
*1000P_4
1

1

2

PC125
.1U/50V_6

2

PQ50
2N7002E-T1-E3 PR209
20K_6

1

EC:DB2

2
1

2

ICTL

29

3

ICHG

PD17
CH501H-40

MAX8765

LX

PR200
*40.2K/F_4

IINP

CH501H-40

BST

HI0805R800R_5A

2

VCTL

14

PC128
10U/10V_8

PD15
1

DLOV

17

PL3
VIN_CHG
PC152
1U/10V_6

7

13

LDO

VIN
33_6
PC145
1U/10V_6

8

ICTL

CELLS

ACIN

0_4

PR192
1M/F_4

1

REFIN

2

15

EC: SI1

PR191
470_4

PR127
*680K_6

2

VCTL

PR197
49.9K/F_4

When system with AC and DC can
support DC discharge for Battery
learning.

VIN_PRO

1

10
PR112

EC: SI1
PR196
16.5K/F_6

27

CELLS

PR199
10K/F_4

Change PR196 from
30.1K change to 16.5K

DCIN

CSSP

PU11
1

CSSN

3VPCU

8724_DCIN

8724_ACIN

PC49
2200P_4

3VPCU

PR128
*680K_6

D

PR214

(34,35) 8778REF

CC-SET

PC108
*.1U/50V_6

PD10
*UDZ2.7B

PQ24
*2N7002E
EC DB2

8778REF

PQ29
2N7002E-T1-E3

2

2

REFIN=4CELLS

PR47
15K/F_6

PR116
10K_6

PR141
*680K_6

1
PC101
*.1U/50V_6

Float= 3 CELLS
PR46
10.5K/F_6

(34)

3

4

1
PR123
*1M_6

*10K_4
DC/C-

VIN

2

1
PC146
1U/25V_8
2

1

2

PU2
LMV331

+

PR125
0_4
VA

PR124
*10K_4
PQ21
*2N7002E

VA

1

8724_SHDN1#

PR44
75K/F_6

PR115

2

PR40
(26) AIR_NON_CHG#

PR43
75K/F_6

5

AC_LATCH

1

.01U/16V_6
5

PR41
10K_4

2

6

2

IMD2

2

1

1

1

3

2

PC52

2

3AC_DIS

CSSP

1
5VPCU
D

If AC voltage lower then 16.3V will
disable charger/charge LED/OS
charge icon.

PC19

.1U/50V_6
PC23
.1U/50V_6

8724_DCIN

220K/F_6
AC_DIS_G (34)

PQ28

100/F_4

1

VA
3VPCU

4

PR12

AIR_DET

8
7
6
5

PR118

PR145
220K_6

2

2
PD16
CH501H-40

FBMJ3216HS800

(34)

PC107
.1U/50V_6

PR10
0_4

2

JP3-2

MBATR

1
2
3

2

PL6

2

PC4
.1U/50V_6

PC99
.1U/50V_6

8
7
6
5

1

1

1

1

1
PC100
.1U/50V_6

POWER JACK

1
2
3

VAD

3

1

JP3-1

PQ3
AO4407

3

PL7
FBMJ3216HS800

CSSN

1
2
3
4
5

7
6

PQ67
2N7002K

1

PQ31
AO4407

2

JP3

2

PD1
SBM1040 L-F

VIN

ADAPTER 90W 19.5 Volts 4.61A

PD9
SBM1040 L-F

VA

1000P_4

(26)

E

ADAPTER 65W 19.5 Volts 3.33A

10K/F_4

I_SET

3
PC362
1
2

C

1

1U/25V_X6S_8

2

1

PR387
1M_4

A

A

PROJECT : OT2
Quanta Computer Inc.

5

4

3

2

Size
C

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

CHARGE(MAX1908/8724)
Sheet
1

33

of

42

5

4

3

2

1

EC: SI1
PR19

*100K_4

GAIN 20

PR175
*0_4

PU8
(26) CELL_DET

1

SHDN

2

GND

OUT

6

CS-

5

D

+5V
+5V

+5V

+5V

2

D

PR185

(33)

PC118
*.1U/16V_6

PR184
*0_4

*SC310A
PC117
*.1U/16V_6

1

+

3

-

1

PR182
8778REF

PR177

2

+

2

-

PR28
*80.6K_6

4

*49.9K/F_4

3

PR17
*10K_4

1
PU6A
*LM393

*1K_4

*LMV321
PU9

PR18
*604K/F_6

2

4

1

CS+

VCC

2

3

PC110
*.1U/16V_6

PR27
*133K/F_6

1

CSIN

*0_4

8

(33)

4

CSIP

2

+5V

5

PR170
*100K_4

PR181
*182K/F_6
2

PC121

PC41
*0.027U/16V_6

+3V

+3V

1

PR29
10K_4

PD14
*CH501H-40

C

PR30
*10K_4

1

EC: SI1

PU6B
6

-

5

+

PQ40
IRLM5103
PR160

PR168
1

(32,33) ADP_ID

7

3

PR167
100K_4

I_SET (33)

*330K_4
EC: SI1

3

1

1

2

PQ4
*2N7002E

PR31
PC114
3900P_6

PR162
3.9K/F_4

2

*LM393

*39K/F_4

2

100_4

OCP# (14)
3

*.22U/10V_6

C

2
PQ44
IRLM5103

1

PQ42
SST3904
VA

3VPCU
(22,25,31,36,37,38,39,40) MAINON

5.63~5.76V
(33) AC_DIS_G

DC/C- (33)
B

PC111
.1U/50V_6

PR164

PR165
10K_4

1

150K_6

3

VA
2

B

1

VA

2

PR137

PR158
47K_6
5

2
PQ62
2N7002E-T1-E3

PR166
10K/F_4

2

2
PQ39
2N7002E-T1-E3

CH501H-40
PR143
220K_6
PR163

AIR_DET (33)
3

1M/F_4
1

PR241
220K_6

1

2

3

PR161
191K/F_6

ADP_EN (26)

PR144
220K_6

PD13

4

+

3

-

1
PR242
220K_6

PU5
TL331

3

22.6K/F_6

1

VA

2
PQ38
2N7002E-T1-E3

A

1

A

5

4

3

PROJECT : OT2
Quanta Computer Inc.
2

Size
B

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

CHARGER II
Sheet
1

34

of

42

5

4

3

2

1

5V_AL

PR57
100K_4
PR234
EN
PR194
390K_4

0_4
PR236

2

1

SYS_SHDN# (4)
*0_4

PR195
150K_4

D

D

VIN
PR33
5V_AL

PR202
47_6

PC131
.1U/50V_6

+5V_VCC1

1

1
0_8

1
+

+

2

PC46
10U/25V/1206

PC51
10U/25V/1206
2

2

PC135
1U/10V_6

3.3 Volt +/- 5%
Design Current:7.5A
Maximum current:11A
OCP minimum 12A

1
PC127
1U/10V_6
2

PC124
2
1

PC48
1000P_4

PC47
.1U/50V_6

2

0.1U/10V_4

2

8778REF
PC134
10U/25V/1206

5
6
7
8

+

PC144
.1U/50V_6

2

PC143
1000P_4

PR188
*0_4

PC183
2
1

1

1

Place these CAPs
close to FETs

1

VIN

5 Volt +/- 5%
Design Current: 4.9 A
Maximum current:7A
OCP minimum 8A

8
7
6
5

8
7
6
5
4
3
2
1
35
34
33

PC136
.1U/50V_6
PR49
0_4
1
2
3

PR208

3V_DL

2

PGOOD2
PC129
*1500P_4

PC138
4.7U/10V_8

PC130
.1U/50V_6

PR39
0_4

1

PC137
.1U/50V_6

1

PR37
*100K_4

0_6
.1U/50V_6
2

21

1

PR45
100K_4

PR198
*22_8

1

3

3VPCU

Close to Controller
PR186

PC133

1
PD2
BAT54S

3.4A
5VSUS

3
2
1

PC122
0.1U/10V_4

2

21

2
2
5
6
7
8

PQ9
SI4800BDY

PR32
*0_4

3VPCU

1

PD3
BAT54S
2

PC153
*1500P_4

3
2
1
5
6
7
8

PC123
.1U/50V_6

5V_AL

4

(40) S4_STATE_PWR

C

2

5VPCU

PR215
*22_8

PC188
220U_4V_ESR25

EC:DB2

1_6

PC140
.1U/10V_4

+
PC44
220U_4V_ESR25

PR229 EN
0_4

1_6

5V_DL

5VPCU

+

PR178
0_4

PR180
BST2 1

1

PC119
.1U/50V_6
PQ48
AO4422

4

2

4

PGOOD2

1

PQ53
AO4422

EC:DB2

32
31
30
29
28
27
26
25

2

PR48
*0_4

REFIN2
ILIM2
OUT2
SKIP
PGOOD2
PU10
ON2
ISL6236IRZA
DH2
LX2

PGOOD1

3

1

PC57
220U/6.3V_ESR25

PR206
0_4

PAD
PAD
PAD

PC53
.1U/50V_6

+

8
7
6
5

+
PC187
220U/6.3V_ESR25

EN

BYP
OUT1
FB1
ILIM1
PGOOD1
ON1
DH1
LX1
PAD
PAD

+3.3V_ALWP

3
2
1

PGOOD1

LDOREFIN
LDO
IN
RTC
ONLDO
VCC
TON
REF

9
10
11
12
13
14
15
16
37
36

5V_LX

C

3V_LX
PR179
402K/F_4

3VPCU

PL9
1.5UH/9A (DCR-14)
1
2

+5V_VCC1

17
18
19
20
21
22
23
24

1
2
3

PL10
2.2UH/8A (DCR-18)
1
2

PQ49
AO4422

BST1
DL1
VDD
SECFB
AGND
PGND
DL2
BST2

1

PC139
0.1U/10V_4
5VPCU
PR207
402K/F_4

Place these CAPs
close to FETs

4

400K/500KHz

2

4 5V_DH
PQ52
AO4422

5VPCU

3V_DH

0.1U/10V_4
PR187
0_4

HWPG_3/5VPCU (31)
3VPCU

2
12VAL

2

5

PC34
.1U/50V_6

PR190
39K/F_4

PC364
2

6

200K/F_4
PC126
.1U/50V_6

7

PC54
.1U/10V_4

2
8

1

12VAL

2

PC55
.1U/10V_4

B

(40)

1

1

PR193

B

1
*10P_4

PQ2
AO4812
3VPCU

PC25
.1U/50V_6

1
4

PC26
.1U/50V_6

4

3

2
1

5

6

7

+3VM_CK505

(40)

PC12
.1U/50V_6

S5_OND

2.55A

+5V

4

1

3

3
2
1

(40) IAMT_OND_WOL
+3V

SUSD (40)

PC58
.1U/10V_4
PC113
.1U/10V_4

2A
3VSUS

2

2

PC56
.1U/10V_4

1

1

PC2
.1U/50V_6

PQ41
SI4804BDY-T1-E3

3.8A

2

IAMT_OND (40)
PC29
.1U/10V_4

PC3
.1U/50V_6
3

PQ10
SI4800BDY

4

2

MAIND

6
5
2
1

8

PC151
.1U/10V_4

+3VM

1

5
6
7
8

2

PQ1
AO6402

1

3V_S5
3VPCU

2

5VPCU

1

3VSUS (19,30,38,40)
(36,40) MAIND

PC115
.1U/10V_4

A

2

A

PROJECT : OT2
Quanta Computer Inc.

5

4

3

2

Size
C

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

3v/5v/1.25v
Sheet
1

35

of

42

5

4

3

D

2

D

1

8717BST1
2

8717BST2
PD5
DAP202U

VIN

2

VIN

PR224
PC155
1000P_4

1

LX2

16

8717LX1

GND

29

CSL2

CSH1

24

PR220
0_4
PR79
10K/F_4
PD18

ON1

CSL1

ON2

FB1

1

2

( 6.28A/Peak )
EC: SI1
PL13
1.5UH/9A (DCR-14)
1
2

8717DL1

PC159
1U/10V_6

8717_ON1

6

8717_ON2

7

8717ILIM2

8

8717ILIM1

28

4

8717REF

CH501H-40

2
4

8717FB2

10

EC: SI1
PR228
487/F_6

C

*100P_6

PGOOD1
PGOOD2
FSEL

SKIP1

FB2

PC169

26

Rc

PR227
5.36K/F_6

PC171
*100P_4

.22U/10V_6

25
8717FB1

Vout=[1+(Rc/Rd)]*1

27 HWPG_1.5VM

PR381
0_4

9

PR226
10K/F_4

Rd

HWPG_1.05VM (31)

PC168
*100P_4

5 8717REF
8717REF

SKIP2

18

8717REF

PC179
330UF/2V_ESR9

3
2
1

MAX8717

ILIM1

+1.5VM
PC85
.1U/10V_4

PC89
*1500P_4

PC366

CSH2

ILIM2

+1.5VM

PR97
*22_8
1

11

Rb

+1.05VM

21

20

AGND

.22U/10V_6
(31,37,40) IAMT_ON

PR218
10K/F_4

LX1

PQ58
SI4392DY

PQ59
SI4856ADY

PGND

12

PC158
*100P_4

8717DH1

DL1

PC157

8717FB2

DH1

22

REF

3

FSET= GND=200KHz

PC162
.22U/10V_6 REF f = 300KHz

19

*100P_4

C

Vout=(1+Ra/Rb)*1

1

DL2

1
2
3

8717FB2

PR216
604/F_6

23

PC74
*1500P_4

PC365

Ra
PC156
*100P_4

BST1

2

8717DL2

1
PR221
487/F_6

PR225
0_6
2

17

1

1
2
3

DH2

8
7
6
5

2
PR80
*22_8

2

PC75
330UF/2V_ESR9

PQ57
SI4856ADY
4

PC165
.1U/50V_6
4

VDD

5
6
7
8

PC77
.1U/10V_4

14

8717LX2 15

1

(9,40) +1.05VM

8717DH2

BST2

PC82
10U/25V/1206

2

EC: SI1
PL12
1.5UH/9A (DCR-14)
1
2

+1.05VM

PC163
1U/10V_6

VCC

PU12
13

PC154
.01U/50V_6

5
6
7
8

10_6
PC164
1U/10V_6

PC160
.1U/50V_6

3
2
1

PQ56
SI4392DY
4

( 7.32A )

5VPCU

3

PR217
0_6

PC174
1000P_4

1

PC173
.01U/50V_6

8
7
6
5

PC86
10U/25V/1206

1

+1.5VM

PR95
120K/F_4

PQ13
IRF7821

PR82
120K/F_4

5
6
7
8

5
6
7
8

VCC f = 500KHz

PR83

PQ64
IRF7821

4

(35,40) MAIND

8717ILIM1

8717ILIM2

PR90
100K/F_4

0_6

4

(35,40) MAIND

PR81
100K/F_4

(6A)

3
2
1

3
2
1

+1.5V

( 7.32A )
+1.05V

B

B

PC185
.1U/10V_4

PC186
.1U/10V_4

Max Current ? A

PQ66
AO6402

+1.5VM
6
5
2
1
PC201
10U/10V_8

PC356
10U/10V_8

PC357
10U/10V_8

6
5
2
1

(10,15,40)

PC358
.1U/10V_4

PC199
10U/10V_8

Max Current ? A

PQ65
AO6402

+1.5VM
+1.25V

+1.25VM
4

PC198
10U/10V_8

+1.25VM (7,10,40)
PC359
10U/10V_8

PC360
10U/10V_8

PC361
.1U/10V_4

3

3

PC200
10U/10V_8

+1.25V
4

+3V

5VPCU

PU4
G938
1

PR379
100K_4

DRV
PC194
.1U/10V_4

PR223
0_4

(31) HWPG_1.25V

2
3
4

PC195
*.1U/10V_4

5VPCU

47_4

PU14
G938

PC355

6

GND

1

VCC

2

GND

PR380
100K_4

33N_6

PR366
DRV

PC192
.1U/10V_4

PC354

6
47_4

33N_6

PR240

PGD
ADJ

PR237
0_4

(22,25,31,34,37,38,39,40) MAINON
A

+3VM
PR369

VCC

5

(31) HWPG_1.25VM

PR222
0_4

3

ADJ

150/F_4

EN
PR368
100/F_4

(31,37,40) IAMT_ON

Vout1=(1+R1/R2)*0.5

PR189

PGD

PR201
0_4

4

5
150/F_4

EN
PR367
100/F_4

PC193
*.1U/10V_4

A

Vout1=(1+R1/R2)*0.5

PROJECT : OT2
Quanta Computer Inc.

5

4

3

2

Size
C

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

+-1.5V &VCCP+1.05V(MAX8743)
Sheet
1

36

of

42

5

4

3

2

1

D

D

5VPCU
PR100
2

1

51116_V5FILT
10_6

VIN

1

PC93
1U/10V_6
2

PC175
4.7U/10V_8
PL5
HI0805R800R-00/5A

PR231
6.98K/F_6

1

VBST 22

VBST

1.8VSUS

+
PC98
220U/2V_ESR15

PC182
.1U/50V_6

20

PR106
*2.2_6

VLDOIN
51116_DRVL

4

19
18
17

PR233
143K/F_4

PC97
*1000P_4

8
1
2
3

PC176
*100P_4

S3

LL

PQ63
SI4856ADY

Ra
51116_VDDQSET

TPS51116

51116_V5FILT

PR232

COMP

VTTGND
PGND
CS_GND
MODE
VDDQSET

6

COMP

0_4

5

*0_4

Rb
PR235
100K/F_4

Ra=Vout-0.75/0.75*Rb
Rb value from 100K to 300K ohm

13

PR238
0_4

VTT
VTTSNS
PAD
PAD

0_4

PR372
PR102

11 51116_S5

0_4
*0_4
PR375

10

HWPG_1.8VSUS (31)

51116_PGOOD

51116_S3

PR104

SLP_S4# (14)
SUSON (31,40)

*0_4

*0_4

23

1.8VSUS

PR385

12
7

PC190
1
2

PR386

1

*4.7U/10V_8

MAINON (22,25,31,34,36,38,39,40)
0_4

IAMT_ON (31,36,40)

*0_4

SLP_S4# (14)

C

S0-S3
SMDDR_VTERM

PC178
10U/10V_8

4

VDDQSNS

9

51116_V5FILT

NC
NC

DRVL

PR108

Fix 1.8V Output

PR101

16

DRVH
S5

2

PC96
220U/2V_ESR15

51116_LX

CS

PGOOD

VTTREF

1
+
C

21

PQ61
SI4392DY

2

8
7
6
5

1

1
2
3

PL14
1.0UH/11A (DCR-9)

1.8VSUS (7,9,10,16,32)

51116_DRVH

51116_CS

V5IN

2

PU13
PC177
.1U/50V_6

4

14

8
7
6
5

S0-S3

15

PR107
0_6

V5FILT

PC92
2200P_4

GND
PAD
PAD
PAD

PC94
.1U/50V_6

PC181
10U/10V_8

SMDDR_VTERM

24
2

0.9V/1.5A
SMDDR_VTERM (16,31,40)

51116_VTTSNS

PR239
0_4

25
26

3
28
27
29

PC95
10U/25V/1206
2

2

PC91
10U/25V/1206
2

PC71
10U/25V/1206

9A

VBST_1

1

1

1

51116_VIN

S0-S3
SMDDR_VREF
SMDDR_VREF (7,16)

SMDDR_VREF
0.9V/10mA

PC180
0.033U/25V_6

B

B

V_TRIP(mV)=R_TRIP(Kohm)*10(uA)
I_OCP=V_trip/Rds_on+I_Ripple/2
VDDQSET

VDDQ(V)

VTTREF and Vtt

Mode

Discharge Mode

Note

V5IN

No discharge

GND

2.5

V_ vddqsns/2

DDR

VDDQ

Tracking discharge

V5IN

1.8

V _vddqsns/2

DDR2

Gnd

Non-tracking discharge

FB

Adjustable

V_VDDQSNS/2

1.5V 3A

0

1

0

Active Mode

< 18A

0

1

1

Active Mode

> 15A

RILIMPK = Battery V x RTRC / (IPK x RSENSE) = 8V x 1.24K / ( Ioutput peak x 0.001) OCP=17.7A
fsw=300kHZ*143kohm/Rosc
1

1

dV_Target/dt=12.5mV/us*71.5kohm/R_TIME

8736VCC

5VPCU

VIN_8736_1

PL1

VIN

2.2_6
EC 0110

(5) H_VID2
(5) H_VID3
(5) H_VID4
(5) H_VID5
(5) H_VID6

35

PR4

0_4

36

PR3

0_4

37

PR2

0_4

38

PR1

0_4

39

PR7

0_4

40

(26,31) PWROK

PR146

*0_4 8736SHDN#

PR140

*0_4

PR374

0_4

4

DL1

8736DL1

1
2

2

2

PR129
1.21K/F_6
PR230

PR119

PGND

NTC 10K_6-B4.25K

31

EC DB2

D5
PC11

D6

6

8736CSP1
.22U/10V_6

SHDN

DRSKP

DPRSLPVR

CSP2
CSN2

2

5

8736CSN1

PR157
*10_4

Intel Recommendation Option 1 :
250KHZ<= Fs <= 300K HZ
0.351uH<= Lo <=0.500uH
+-20%
Low-Freq. Decoupling : ESR 1.5m Ohms ; ESL 1.8nH/6
SPCAP EEFSX0D331R * 6 or
POSCAP 2R5TPE330M9 * 6
Mid-Freq. Decoupling : 3m Ohms/32
MLCC 22uF_0805_X5R * 32 PCS.

8
7

PSI
EC:DB2
PWM3

PR152
1.91K/F_4
PR150

0_4

24

0_4

1

+3V

29
8736VCC

CSP3

10

IMVPOK

CSN3

9

CLKEN

GNDS

11

PR148
1.91K/F_4

EC:DB2
PR20

PR8

MAX8736AGTL
PR16
22

(4) H_PROCHOT#

GND
VR_HOT
VPS

0_4

2

*100P_4

8736GNDS
1

(14) VR_PWRGD_CLKEN#
PC27
1
2

20

100_6
PC31
4700P_4
EC:DB2

PR15
17.4K/F_4

13

EC:SI2

PR149
FBS

GND
GND
GND

GND
GND
GND

49
50
48

2

41
42
43

GND
GND
GND
GND

2

PC28
PR147
100P_4 *0_4

EC:DB2
PR21

12

PU1

1

13K/F_4

THRM

1

23

8736VCC

PR142
NTC 100K_6-B4.25K

PR154
*10_4

Vo
VID6 VID5 VID4 VID3 VID2 VID1 VID0
---------------------------------------------1.5000
0
0
0
0
0
0
0
---------------------------------------------1.4375
0
0
0
0
1
0
1
---------------------------------------------1.4000
0
0
0
1
0
0
0
---------------------------------------------1.3000
0
0
1
0
0
0
0
---------------------------------------------1.2875
0
0
1
0
0
0
1
---------------------------------------------1.2000
0
0
1
1
0
0
0
---------------------------------------------1.1500
0
0
1
1
1
0
0
---------------------------------------------1.1000
0
1
0
0
0
0
0
---------------------------------------------1.0000
0
1
0
1
0
0
0
---------------------------------------------0.9625
0
1
0
1
0
1
1
---------------------------------------------0.9000
0
1
1
0
0
0
0
---------------------------------------------0.8375
0
1
1
0
1
0
1
---------------------------------------------0.8000
0
1
1
1
0
0
0
---------------------------------------------0.7625
0
1
1
1
0
1
1
---------------------------------------------0.7500
0
1
1
1
1
0
0
---------------------------------------------0.7000
1
0
0
0
0
0
0
---------------------------------------------0.6000
1
0
0
1
0
0
0
---------------------------------------------0.5000
1
0
1
0
0
0
0
---------------------------------------------0.3000
1
1
0
0
0
0
0
----------------------------------------------

8736VCC

28

0_4

56_4

1

2

2.49K/F_6
EC 0110

D4

*100K_4

PSI#

PR151

PC16
330U/2V/ESR6

PC103
2200P_4
PQ36
SI7336

+3V

+1.05V

PC18
*30U/2V/ESR6

1
3

PR9

(7,14,31) DELAY_VR_PWRGOOD

PC14
330U/2V/ESR6

4

EC:DB2

3

PC15
330U/2V/ESR6

1

1
PC17
330U/2V/ESR6

2

PR126
2.2_6

2

PC112
.1U/50V_6

PC22
4700P_4

499/F_6

PR11
(4)

1

1

1
3
2
1

VCC_CORE (5)

D2

PWM2
PR136

32

D3

CSN1

33

(7,14) PM_DPRSLPVR

VCC_CORE

2

(31,38) VRON

PL8
0.36UH/25A

D0

CSP1

(22,25,31,34,36,37,38,40) MAINON

PC13
.22U/10V_6


8736LX1

TRC

D1

All phase active,forced-PWM mode(full powr)

PQ34
SI7392

5
34

0_4

1-phase forced-PWM mode(inteermediate power)

3
2
1

2

1.78K/F_6
0_4

PR5

0
1

2

18

26

0
0

4

1

PR24
8736TRC

PR6

REF
LX1

EC:SI2

(5) H_VID1

ILIM

825K/F_6
2

.22U/10V_6

(5) H_VID0

27

1

19

DH1

PC39
.1U/50V_6

1-phase pulse-skipping mode(low power)

2

8736REF

CCV

2200P_4

PC38
2200P_4

PSI#

X

1

16

8736DH1

2

17

8736ILIM

TIME

2

PC30
1

PR23

8736CCV

DPRSLPVR
1

1

EC:SI2

PC32
1
2

PC20
10U/25V/1206

8736BST

PR26
71.5K/F_4

PC36
10U/25V/1206

1

PR14
25

2

1

30
BST1

PC35
10U/25V/1206

HI0805R800R-00/5A L-F

2

15

OSC

PC37
*10U/25V_12

PD11
CH501H-40

5

8736TIME

PC5
10U/10V_8

8736BST1

14

VCC

8736OSC

VDD

21

PC33
1U/10V_6

PR25
143K/F_4

2

2

10_6

1

fsw=300KHZ*143Kohm/Rosc
fsw= 300KHz

2

PR138

100_6
PC40
4700P_4
EC:DB2



44
45
46
47

EC:DB2

VR_HOT#-Active Low when THRM Voltage
level below 1.5V

PR156

0_4
VSSSENSE_1

(5) VSSSENSE

VCCSENSE_1

(5) VCCSENSE
PR153

0_4

Parallel

3

4

4

PROJECT : OT2
Quanta Computer Inc.

A

B

C

D

E

F

G

Size
C

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

MAX8736
Sheet

39
H

of

42

5

4

3

2

1

12VAL

+3VM
12VAL
VIN

PR91
22_8

IAMT_OND_WOL (35)

PR155
1M/F_4

2
3

1

1

PQ37
DTC144EUA

3

1

1

2

PQ33
2N7002E-T1-E3

PR159
1M/F_4

2

(31,36,37) IAMT_ON
PQ19
2N7002E-T1-E3

1

D

PC104
*2200P_6

1

3

PC88
*2200P_6

2

1

PQ20
DTC144EUA

PQ18
2N7002E-T1-E3

2

2

2

3

3

3

PQ17
2N7002E-T1-E3

PR103
1M/F_4

2

PQ32
2N7002E-T1-E3

PR92
22_8
IAMT_OND (35)

(31,36,37) IAMT_ON

3

PR99
1M/F_4

PR122
1M/F_4

PR121
1M/F_4

PR96
1M/F_4

1

(35)

1

D

12VAL

+1.05VM

2

+1.25VM

3

VIN

PQ60
DTC144EUA

2

1

(14) LAN_WOL_EN

+3V

12VAL

+1.25V

+5V

12VAL
PR111
1M_6

C

PR133
1M_6

3

PQ30
2N7002E-T1-E3

2

PQ12
2N7002E-T1-E3

2

C

MAIND

PR388
1M_6

VIN

(35,36)

PC102
2200P_4

S4_STATE_PWR (35)
PR391
1M_4

2

3

2

PR76
22_8
3

PQ22
2N7002E-T1-E3

PQ11
2N7002E-T1-E3

2

PR117
22_8
3

PR114
22_8
3

PR77
22_8
3

VIN

3

SMDDR_VTERM

3

1

PR392
1M_4

2

S4_STATE

1

1

1

1

(14)

PQ71
DTC144EUA

1

MAINON_G

1

PQ27
DTC144EUA

PC367
2200P_4

2

PQ23
2N7002E-T1-E3

PR139
1M_6

2

1

(22,25,31,34,36,37,38,39) MAINON

PQ70
2N7002EPT

3VPCU

3

2

PV stager:add for HP request

1

PC368
.1U/10V_4

S4_STATE_PWR 2

500mA
PV stager:add for HP request

3V_FP

1

PQ72
AO3403

B

1

B

PC369
.1U/10V_4

12VAL

2

3V_S5

12VAL
3VSUS

2

2
PQ14
DTC144EUA

1

1

PQ43
2N7002E-T1-E3

S5_ON

PQ15
2N7002E-T1-E3

PQ16
2N7002E-T1-E3

S5_ON_G
1

3
PQ47
DTC144EUA

PR89
1M_6

2
(31)

PR171
1M_6

2

2

3

PC116
2200P_4

SUSON_G
1

(31,37) SUSON

PC78
2200P_4

1

PQ45
2N7002E-T1-E3

2

(35)

3

3

SUSD
PR173
1M_6

3

PR85
1M_6

1

PR176
22_8

3

S5_OND (35)

PR169
1M_6

VIN

PR86
1M_6

PR84
22_8

VIN

DEL PR174, PQ46
For S4-STATE

A

A

PROJECT : OT2
Quanta Computer Inc.

5

4

3

2

Size
C

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

DISCHARGE
Sheet
1

40

of

42

5

4

3

MODEL
Date
2006.11

1

CHANGE LIST

DB2 --->SI
OT2 MB
31OT2MBXXXX

2

Page

Reason for change

modify list

change from 5VSUS to +5v due to not support wake up from
suspend

change U35 pin13,15 to +5V

D

D

change footprint to 0805 to easy prepare material

change U2, C577 footprint
change power plan from 3VSUS to 3V_S5 at RP31 , R241 , R448 ,

avoild leakage cruuent

R538,change card bus switch poewr from 5VSUS to 5V
R452 Install, R46 on instal ;delete R496,Add D32
Add D33,D34 ;delete R293 ,and add Q60

EC VCC2 pin is used in a comparator to sample when Vcc2 is going up
or down. It will draw some current. Approx 300ua
For auto boot issue

R1005 install,R297 no install
reserve

R1029,add

R1028 ,Q62 for

remove Q37,R443,R426,CN1,R977

remove Kill switch function

add for EA team easy test

add R1031,R1032

C

add C643, and modify pin 1 for
and add C657

for internal mic issue
modify footprint firm right angle tyoe to straight type

C

U47 OP circuit

CN36

change footprint for another vender for easy insert

change footprint for track point connector CN8
D31 close to ICH8 and pull up 10k(R1035)
to +3V

move D31 close to ICH8 to solve battery LED issue ,else it will cause LED function abnormally
WWAN noise --- ICH improvement

reserve L53, L54,add R1033,R1034

due to use 4MB flash part
add strapping options for CPU_BSEL{0:2} so we can hardwire

auto power issue

delete CN24
the clock to the FSB frequency if needed

R1036-R1044

PU13.11, add IAMT_ON control signal option with 0-Ohm NO INSTALL to control power up of 0.9V
add PR385
This is to save system power in S3 when iAMT is disabled.
For ENERGY_DET, Change R18 to 1.4K, this is a change from Intel on LAN Energy Detect.
R18

DB2 --->SI2

RP31 pin10 from 3V_S5 to 3VSUS
schematic error and change to avoid leakage voltage

Date
change Lan crystal layout for intel suggestion

B

Lan crystal

layout

B

2007.1
to avoid the ripple for signal

CLK_PWRGD
add R1049 for intel suggestion

tune Adp_Id signal for layout. to avoid overlay

for EMI suggestion

for EMI suggestion

reseve C661,C662,C663

for EMI suggestion(CRT)

L8,L10,L14 change to BK1608LL680

for EMI suggestion(internal Mic)

reserve R664, R1050 for Mic

delete R280,R281 due to useless
for EMI suggestion(modem)
PWM signal(LCD)to avoid work abnormally

change to 1.87K for

C5 no install

Intel suggestion

change R18 to 1.87k

A

A

Q61,D32 is for leakage voltage issue ,but will influence LAN function ,change to 0 ohm

delete Q61,add R1051;deleteD32,Add R1052

PROJECT : OT2
Quanta Computer Inc.
5

4

3

2

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

change list-1
Sheet
1

41

of

42

5

4

3

MODEL
Date
2007.1

1

CHANGE LIST

DB2 --->SI2
OT2 MB
31OT2MBXXXX

2

Page

Reason for change
For LCD rush current issue

modify list
change R30 to 82K,C32 to 0.1u ,and change R20 power source to 3VPCU

D

D

due to no use

delete R341,R1025,L9,L13,L15,L8,L10,L14,R342,R95,R81

SI2--->PV
2007.1

C

C

B

B

A

A

PROJECT : OT2
Quanta Computer Inc.
5

4

3

2

Size
Custom

Document Number

Date:

Thursday, March 22, 2007

Rev
1A

change list-2
Sheet
1

42

of

42



---

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File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.2
Linearized                      : No
Title                           : OT2 SCHEMATIC 3.22
Author                          : 90072307
Creator                         : pdfFactory Pro http://www.fineprint.com
Producer                        : pdfFactory Pro v1.53 (Windows XP Chinese)
Create Date                     : 2007:03:22 19:18:08
Page Count                      : 42

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