Inventec Diamond Schematics. Www.s Manuals.com. Ra02 Schematics
User Manual: Motherboard Inventec Diamond 6050A0032501 - Schematics. Free.
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Page Count: 68
![](asset-1.png)
VER
2008/08/21
MV B
Time Changed
Drawn by
Date Changed QA CHK
Size
TITLE
Engineer
R&D CHK
MFG ENGR CHK
FINAL
Model Number Sheet
Changed by
DOC CTRL CHK
EE2 Thursday, August 21, 2003 11:19:38 am
David Du
David Du
A02 PC8803 167
DIAMOND
A3
DIAMOND npubished dataOND
- BUILD
of
INVENTEC
![](asset-2.png)
6- SELECT & BATTERY CONN
7- SYSTEM POWER(3V/5V/12V)
40- KBC
35- CRT& SVEDIO CONN
DOC CTRL CHK
37- ICH4-1
MFG ENGR CHK
51- CARDBUS CONTROLL
16- BANIAS-1
TITLE
36- LCD CONN
QA CHK
24- ODEM-4
15- CLOCK_GENEATOR
27- DDR-SDRAM-3
of
57- DOCKING CONN
26- DDR-SDRAM-2
43- SERIAL PORT
34- VIDEO RAM-2
30- ATI-M10-P-2
28- DDR-SDRAM-4
55- LAN INTERFACE-1
21- ODEM-1
25- DDR-SDRAM-1
44- PARALLER PORT
10- DAUGHTER SYSTEM POWER(2.5V/VGAVCC)
9- SYSTEM POWER(VCCP/1.2V)
38- ICH4-2 59- BOARD TO BOARD CONN & LID SWITCH
31- ATI-M10-P-3
5- DC& BATTERY CHANGER
INVENTEC
52- PC CARD SLOT
54- MINIPCI CONN
56- LAN INTERFACE-2
VERChanged by
PAGE
19- BANIAS-4
18- BANIAS-3
8- DAUGHTER SYSTEM POWER(1.5V/1.8V)
41- INT.KBC/POINT DEVICES
29- ATI-M10-P-1
Drawn by
49- MULTIBAY CONN
17- BANIAS-2
42- SUPER I/O
39- ICH4-3
R&D CHK
62- DAUGTHER TCPA CONN
63- DAUGTHER CONN & SWITCH LED
64- DAUGTHER LED & VOL BUTTON
11- CPU POWER(VCC_CORE)
Model Number
23- ODEM-3
47- AUDIO AMP&HP JACK
46- EQ&MIC JACK
58- BLUETOOTH
Sheet
45- AC97 CODEC
60- DAUGHTER FHW
12- DDR_TERMINATION
61- DAUGTHER MDC CONN
20- THERMAL&FAN CONTROLLER
PAGE
Size
13- POWER(SLEEP)
33- VIDEO RAM DEPEND
22- ODEM-2
David Du
David Du
10:53:56 amThursday, July 31, 2003EE2 672
PC8803A02
DIAMOND
A3
Date Changed Time Changed
TABLE OF CONTENTS
32- ATI-M10-P-4
50- USB&IR CONN
48- HDD CONN
Engineer
PAGE
53- SD CARD CONN
14- POWER(SEQUENCE)
![](asset-3.png)
421 BGA
Primary_IDE
ATA 66/100
CONN B
USB2
Dock
USB3
Bluetooth
BATTERY
System Charger & AC97 Codec
PORT REPLICATOR
QA CHK VER Model Number
INVENTEC
Giga-bit LAN
ITP
RJ11
System BIOS TCPA
47N250
3.3V, AC97 LINK 3.3MHz 3.3V, LPC_Interface,33MHz
PSB, VCCP,400MHz
BANIAS
(Micro-FCPGA)
3.3V, PCI_Interface,33MHz
BCM 5705
ICH4-M
CK 408
Clock generator
CRT
ATI_M9-X
VGA Chip
Multi-bay/ Battery
Mini_PCI
Wireless LAN
O2_711M3B
CARD BUS
Odem MCH-M
Date Changed
RJ45 ANT ANT SD Card
Changed by Time Changed
MFG ENGR CHK
SLOT Cardbus
SLOT A/B
Module
Module 56K
AD_1981
Engineer
Drawn by
Super I/O
47N227
Kahuna Lite
1.5V,AGP 4X/8X_BUS,66MHz
R&D CHK
DOC CTRL CHK
Sheet of
1.8V, Hub Link, 66MHz
HDD
FWH
32MB/64MB
Size
TITLE
DDR RAM
S-video
LCM
593 BGA
David Du
David Du
10:54:58 amThursday, July 31, 2003EE2
673
PC8803A02
DIAMOND
A3
DDR _SODIMM0
DDR _SODIMM1
2.5V,DDR SDRAM200/266 Interface
Secondary_IDE
USB0
CONN A
USB1
Dock
USB4
USB5
DC/DC System power
MDC/Modem
![](asset-4.png)
COMA
CHGA
+VGAVCC
+V2.5L
1.8V
ACOK
MFG ENGR CHK
ICTL
DOC CTRL CHK
+VBATB
+V5
+VBATA
+V5S
+V1.2L
+V3S
+V3
+V1.5A
PDS
BATSTAT
0.0295
Time Changed
ON1
DISB
ADPT
ON1
+VBATR
ACPRES#
+VCC_CORE
ON2
+V12
5V
+V3L NS_LM2621MMX
1.2V
1.5V
+V2.5
2.5V
SKIP#
ON2
+V3A
of
TITLE
+V1.2_MCH
INVENTEC
Engineer
R&D CHK Size
+V1.2L
THMB
Sheet
DISA
Model Number
+V5A
SKIP#
+V1.5S
Drawn by
ON1
+V5L
SKIP#
+V3L
3V
+V2.5S
+V5L
BATSELB_A#
BATSTAT#
BATSEL
+VCCP
SKIP#
Changed by
+V1.5A
Date Changed
+V1.8S
+VBDC
EE2 Thursday, July 31, 2003 10:56:04 am
David Du
David Du
A02 PC8803 467
DIAMOND
A3
ON2
VERQA CHK
1.05V
+V1.25
COMB
THMA
+VGAVCC
CHGB
![](asset-5.png)
$V
Engineer
Time Changed
CELLSEL=1,Vcharger=12.6V
5.4V_15mil
Icharger=2.5A
Date Changed
DC JACK
Size
2.5A_100mil
15mil
VER
15mil
15mil
R&D CHK
Model Number Sheet
10mil
Changed by
$V
$V
Drawn by
15mil
15mil
15mil
Note:
high power trace
CELLSEL=0,Vcharger=16.8V
15mil
WAIT TO CHANGE 38.3K
QA CHK
MFG ENGR CHK
INVENTEC
+
++
+
+
TITLE
4.096V_10mil
Iadp=3.3A
11:22:36 amThursday, August 21, 2003EE2
675
PC8803A02
DC &BATTERY CHANGER
DIAMOND
A3
of
3.3A_150mil 3.3A_150mil
10mil
3.3A_150mil
DOC CTRL CHK
R16
3.3A_150mil
10mil
10mil
R1016 CHANGE TO 133K_1%
15mil
10mil
10mil
C
E
2
1772REF
R1035
0.018_1%_1W
12
David Du
David Du
3
10K_5%
R1053
1
2
Q1003
MMBT3906
B
1
3
FDS6680S
U1007
8
D
7
6
5
4
G
S
12
R1051
1K_5%
12
C1038
10UF_25V
1
2
1UF_10V
C10491
2
R1061
37.4K_1%
1
2
+VBDC
R1067
40.2K_1%
12
1UF_25V
C10151
2
499_1%
R6036
12
C6038
1UF_6.3V
1
2
1
2
+VBATR
R265
0.05_1W_1%
12
5-
C301
10PF
1
2
VADP1
0.01UF_16V
C1042
0.1UF_25V
12
1772LDO
C288
10UF_25V
1
2
+V3A
40-
40-,6- R1055
10K_5%
12
VADP C1051
R1588
OPEN
12
R1068
10.2K_1%
12
+V5S
57-,55-
3
2
4
5
4.7
R1048
12
OUT 8
0.1UF_25V
C3001
2
SINGA_2DC_S028I200
JACK3
1
52.3K_1%
1
2
U1002 LM324A
10 +
-
9
11
4
1
2
5-
2
R1064
1
2
R1052
12
4.7
R1049
1
2
10UF_25V
C1037
R1050
1
2
1UF_10V
C10441
2
C1053 0.1UF_16V
C1043
1
2
R1046
2.2_5%
12
52.3K_1%
1
NC
NC 2
ANODE
5
CATHODE 3
REF
4
+VBATR
+VADP2
0.01UF_16V
R1036
0.015_1W_1%
12
5-
+V3A
NS_LMV431ACM5X_SOT23_5P
U1000
5+
6-
11
4
7
OUT
133K_1%
R1016
1
2
37-,16-
C1033
0.47UF_25V
1
2
LM324A
U1002
OPEN
C6023
1
2
0.1UF_16V
C1040
1
2
VADP
C1052
1
2
10K_5%
R1037
1
2
1
2
2N7002
Q1005 3
D
2
G
S
1
0.1UF_16V
1UF_25V
1
2
0.1UF_25V
C2991
2
VADP1
10K_0.5%
R1006
2200PFC1000
12 100K_5%
R1019
12
C1034
R1039
237K_1%
12
R1062
47K_5%
1
2
47K_5%
R1063
12
10PF
C302
1
2
R1592
OPEN
1
2
OPEN
R1590
12 +V3A
1
0.1UF_25V
C1039
12
R1038
47K_5%
1
2
6-
1N4148
D1004
2
1
1N4148
D1006
2
R1015
100K_5%
12
0_5%
R6029
12 37-
3
+
2
-
11
4
1OUT
0_5%
R1022
1
2
1772LDO
12
R1021
0_5%
1
2
LM324A
U1002
2
R1065
1
2
1772LDO
L27
PLFC1055P_220A_22UH
12
-
13
11
4
OUT 14
7-
1772REF
100K_0.5%
R1001
12
2
10K_5%
R1040
1
2
U1002
LM324A
+
+V3A
100K_5%
R1071
1
2
D1000 BAT54S
1
3
R1020
4.7K
1
2R1011
10
1
2
54 G
S
1
2
3
40-
R1000
10K_1%
1
2
R1017
1
2
IRF7807V
Q1007
8
D7
6
OPEN
12
MMBT3906
Q1002
1
B
C
3
2
E
80.6K_1%
3
0.1UF_25V
C1050
12
R1591
R6043
0
12
R6044
OPEN
12
BAT54C
D6009
1
2
1
2
10K_5%
R1047
1
2
2
22UF_23V_METAL
C297
1
VADP
0.47UF_25V
C1041
Q1008
SST3904
2
B
3
C
E
1
C1046
0.1UF_16V
1
21
22
DL0V
10 ICHG
14 ICTL
IINP 28
2LD0
23
LX
PGND 20
REF
4
13 REFIN 15
VCTL
CCI
CCS
5
CCV
7
16
CELLS
CLS
3
CSIN 18
CSIP 19
26
CSSN
CSSP 27
DCIN
1
DHI 24
DL0
S2
U1008
MAX_MAX1772EEI_QSOP_28P
GND
8
GND
9
AC0K
12 ACIN
11 17
BATT
25
BST
6
2
5-
Q1004
NDC7002N
D1 6
D2 4
1G1
G2
3
S1 5
2
12
1UF_6.3V
C1045
1
2
R1059
100K_1%
1
12
R1054
100K_5%
1
2
33
R1041
C10031
2
R1066
49.9K_1%
1
2
0_5%
R1060
1.37K_1%
R1070
1
2
C1016
6800PF_25V
1
2
1UF_16V
NFM60R30T222
12
3
4
0.1UF_25V
C312
1
2
STBY_SWIN#_3
L26
H_STPCLK#
1772GND
1772GND
AIRACIN#
AIRACIN
MAX_LX5
CELLSEL
+VADPTR
1772GND
CHGCTRL_3
1772GND
ICHG
ACIN#
![](asset-6.png)
3.3A_150mil
10mil
+
INVENTEC
10mil
MAIN BATT
5A_200mil
VER
2.5A_100mil
2.5A_100mil
Sheet
5A_200mil
Date ChangedChanged by QA CHK
DOC CTRL CHK
10mil
TITLE
10mil
5A_200mil 5A_200mil
2.5A_100mil
2.5A_100mil
15mil
15mil
10mil 3.3V_10mil
10mil
15mil
15mil
DIAMOND
SELECT & BATTERY CONN
A3
3.3A_150mil
10mil
10mil
R&D CHK
of
2nd BATT
Size
+
10mil
10mil
MFG ENGR CHK
Time Changed Model Number
Engineer
Drawn by
5A_200mil
5A_200mil
47PF_50V
1
2
+V3A
57-,40-
EE2 Thursday, July 31, 2003 10:58:32 am
David Du
David Du
A02 PC8803 667
100K_5%
R1218
1
2
6-
40-,6-
C1245
DISA 17
DISB
8EXTLD
6GND
7MINV
9PDS
14
TCOMP
THMA
2THMB 19
15
VDD
ACDET
10 12
ACPRES#
BATA
120
BATB
13
BATSEL
BATSTAT 11
CHGA
3CHGB 18
COMA
5COMB 16
4
12
+V3A
UDZS5.6B
D1015
2
1
MAX_MAX1773EUP_TSSOP_20P
U12
R1216
12
100K_5%
R1214
12
100_5%
R1217
+VBATB
6-
40-
R1219
0_5%
12
0_5%
1
2
+V3A
40-
+V3A
57-,40-
+VBATB
40-,6-
12
C1291
0.022UF
1
2
2.2UF_25V
C204
SFPB74
21
2.2UF_25V
C12881
2
R1234
100_5%
R1244
100K_5%
12
100K_1%
R203
12
D1002
R1581
3.3K_1%
1
2
R202
0_5%
12
34
4
55
66
0.022UF
C1287
1
2
6-
1.8K_5%
1
2
AMP_C1470694_1_6P
CN1003
1
12
23
R1232
12
C1282
47PF_50V
1
2
+V3A
R1231
UDZS5.6B2
1
1N4148
D1003
2
1
100_5%
1
22
33
4
45
56
6
+VBATA
D1016
65
G
41
S
23
CN14
AMP_1470444_1_6P
1
65
4
G
S
123
Q1025
FDS4435
D
87
100K_1%
12
VADP
+VBATA
FDS4435
Q1032
D
87
1
210K
R1245
1
2
40-,6-
R205
3.3K_5%
R1252
12
D1014
1N4148
2
1
R1246
10K
R1251
470K_5%
1
2
+VADP2
+VBDC
5
4
G
S
123
2.7K_1%
R1215
1
2
65
G
41
S
23
Q1028
FDS4435
8
D
76
5
G
41
S
23
Q1029
FDS4435
D
87
0.1UF_25V
1
2
Q1001
FDS6675
D
876
10K
R1026
12
100K_5%
R1247
12
C1289
R1250
1
2
+VADP2
+VBDC
0.1UF_25V
C2031
2
1
R283
13.0K_1%
1
2
40-,5-
+VBDC
47K_5%
100K_1%
R204
1
2
VADP1
SST3904
Q1062
2
B
3
C
E
10K_1%
R1249
12
R1248
100K_5%
12
1
2
40-
40-
+V3A
390K_5%
R1589
1
2
C1290
1
2
100_5%
R1229
12
R1233
100K_5%
6-
40-,6- MMBT3906
Q1030
1
B
C
3
2
E
0.33UF_10V
Q1031
D1 7
8
6
D2
5
G1
2
4G2
S1 1
S2 3
+V3A
5-
2
1
R1230
1.8K_5%
1
2
FDS4935
CELLSEL
BAT6CELL#
D1017
UDZS5.6B2
1
D1064
UDZS5.6B
BATSELB_A#
AIRACIN#
SDA_MAIN
BAT6CELL#
SDA_MBAY
SCL_MBAY
SCL_MAIN
1773VDD
THM_MBAY#
THM_MBAY#THM_MAIN#
BATSTAT#
1773VDD
THM_MAIN#
![](asset-7.png)
MFG ENGR CHK
For power test
Sheet
4A_160mil
6A_250mil
4A_160mil
6A_250mil
2A_80mil
4A_160mil
20mil
20mil
15mil15mil
15mil
15mil
15mil
of
QA CHK
Size
Drawn by
120mA_30mil
15mil
15mil
15mil
15mil
15mil
120mA_30mil
15mil
15mil
20mil
15mil
10mil
10mil
15mil
A02 PC8803 767
DIAMOND
SYSTEM POWER(3V/5V/12V)
A3
15mil
30mil
20mil
10mil
5A_200mil
DOC CTRL CHK
Changed by Date Changed Time Changed
R&D CHK
Model Number
5A_200mil
VER
TITLE
INVENTEC
Engineer
10mil
10mil
0
R1241
12
EE2 Thursday, July 31, 2003 10:59:19 am
David Du
David Du
2
C182
220UF_6.3V_OSCON
1
47UF_20V
C1032
1
12
+V3L
7-
+V12
+VBATP
R1195
0
1
12
0_5%
R213 1
222
R1194
21
+V5
R1211
0_5%
1
2
R231
4.7_1206_1/4W
SIL520_6.8UH
L1000
12
1632GND
1632GND
D1005
EC10QS03L
59-,47-,45-,40-,38-,13-,12-,9-
0.022UF
C1244
1
2
+VBATP
324K_1%
R1209
1
2
0.1UF_25V
C226
1
2
+V5L
NS_LM2621MMX_MSO8_8P
U1006
BOOT 7
2EN
4FB
FREQ
3
PGND
1
5
SGND
8
SW
6
VDD
OPEN
C201
1
2
POWERPAD_4A
PAD1
1
2
3
4
1
2
C202
330UF_4V_OSCON
1
1632GND
1632GND
2
5-
C1222
10UF_25V
1
2 1UF_25V
C1223
2
C1221
0.1UF_25V
12
1632GND
C1219
0.1UF_10V
1
12
0
R1207
12C1242 0.1UF_25V
1
3
4
R1210
80.6K_1%
1
2
R216
10.2K_1%
R1213
12
7-
PAD4
POWERPAD_4A
1N4148
D1012
21
10UF_K_6.3V
C1981
2
OPEN
2
1UF_6.3V
C199
12
R232
220K_5%
1
2
C1048
0.1UF_16V
12
7-
R1044
0
1
1
2
+V5A
+V3A
MAX3V
+V5
10UF_K_6.3V
C1851
2
3
2.2PF_50V
C1035
1
2
22UF_10V
C1047
2FDS6680S
Q1024
8
D
7
6
5
4
G
S
12
S2
3
4.7UF_K_6.3V
C2001
2
143K_1%
R1242
1
2
FDS6982S
Q1022
D1
7
8
6
D2
5
G1
2
4
G2
1
S1
C225
4.7UF_K_25V
1
2
R1042
16.9K_1%
1
10UF_K_16V
C10361
2
147K_1%
R1043
12
+V5L
G
S
123
7-
0.22UF_K_10V
C1243
1
2
MAX5V L21
12
FDS6612A
Q1021
8
D
765
4
100UF_25V
C197
1
R1212
10K_5%
1
2
PLFC1055P_6R8A_6.8UH
C1218
10UF_25V
1
2
R1243
274K_1%
1
2
+VBATR
PAD2
1
2
3
4
470PF_50V
C1286
1
2
R1208
1
2
16K_1%
R214
12
POWERPAD_4A
C12171
2
SIQ127A_10UH
L19
12
+V5L
47K_5%
21
2PGOOD
10 PRO#
REF
8
SHDN#
6
SKIP#
12
TON
13
V+ 20
17
VCC
+V5L
10UF_25V
5ILIM3
11 ILIM5
25
LDO3
LDO5 18
LX3 27
LX5 15
1NC
3ON3
4ON5
22
OUT3
OUT5
U1012
MAX_MAX1999EEI_QSOP28_28P
28
BST3
BST5
14
26
DH3
DH5 16
DL3 24
DL5 19
7FB3
FB5
9
23
GND
12
3
+VBATP
C1220
4.7UF_K_6.3V
1
2
2
150K_1%
R1045
12
BAT54C
D1018
MAX5V
0
R217 12 R218
OPEN
1
+V3A
BAT54A
D10113
12
MAX_LX5
SLP_S3#_3R
M1999FB5
M1999FB5
M1999FB3
M1999FB3
![](asset-8.png)
15mil 15mil
10mil
SYSTEM POWER (1.5&1.8) ON BUTTON DAUGHTER BOARD
12mil
12mil
12mil
Drawn by
12mil
3A_100mil
3A_100mil
15mil
15mil
10mil
15mil
TITLE
of
Time ChangedChanged by
40mil
40mil
Engineer
Date Changed VER
15mil
QA CHK
15mil
12mil
12mil
15mil
INVENTEC
12mil
10mil
2
EE2 Thursday, July 31, 2003 10:59:26 am
David Du
David Du
A02 PC8803 867
DIAMOND
SYSTEM POWER(1.5V/1.8V)
A3
Size
DOC CTRL CHK
MFG ENGR CHK
R&D CHK
Model Number Sheet
12
PLFC0735P_6R8A
L4001
12
L4000
PLFC0735P_6R8A
1
22
7
PGOOD
REF
9
SKIP#
6
5TON
V+ 4
VCC
21
20
VDD
10
R4025
12 ILIM2
27
LX1
16
LX2
23 NC0
NC1
28
15
NC2
10 ON1
11 ON2
OUT1 1
OUT2 14
PGND
AGND
8
25
BST1
18
BST2
DH1 26
DH2 17
DL1 24
19
DL2
FB1 2
FB2 13
ILIM1
3
2
+VBATP_BN
C4003
0.1UF_16V
1
2
63-,10-
+VBATP_BN
U4000
MAX_MAX1715_QSOP_28P
C4001
1
2
+V1.5A_BN
15A18SGND
15A18SGND
R4004
20K_1%
1
G2
4
S11
3
S2
R4006
23.7K_1%
1
2
15A18SGND
0.1UF_25V
+VBATP_BN
+V1.8S_BN
Q4004
FDS6984S
7
D1 8
D2 6
5
2G1
1
2
220UF_2.5V_S18_METAL
C4004
1
180PF_50V
1
2
R4003
0_5%
12
C4005
220P_25V
BAT54A
3
12
15A18SGND
+V5A_BN
C4008
10UF_25V
C40111
2
220UF_2.5V_S18_METAL
C4010
1
D4004
3
C4002
0.1UF_25V
1
2
0.1UF_25V
C40211
2
2
FDS6984S
Q4000
D1 7
8
6
D2
5
G1
2
4G2
1
S1
S2
1
2
1UF_10V
C40201
2
C4009
0.1UF_16V
1
1
2
R4002
20K_1%
1
2
C4006
1UF_10V
10
1
2
0
R4008
12
R4001
10K_1%
10UF_25V
C4000
1
2
22
R4005
1
2
R4022
C4007
1UF_6.3V
1
2
0.1UF_25V
C4012
1
2
R4000
274K_1%
12
274K_1%
R4007
1
2
SLP_S3#_3R_BN
![](asset-9.png)
of
VGAVCC NOTES :
Engineer
R1582_5.49K_1%
Sheet
TITLE
INVENTEC
15mil
5A_200mil
OPEN
10mil
10mil
10mil
15mil
10mil
Size
Drawn by
R&D CHK
DOC CTRL CHK
Date Changed
4A_160mil
15mil
12mil
12mil
15mil
10mil
OPEN
VER Model Number
15mil
15mil
MFG ENGR CHK
QA CHK
60mil
15mil
USED M10 (1.0V/ 1.2V) USED M9(1.25V/ 1.5V)
12mil
Time Changed
R219_ 1K_1%
R220_20K_1%
15mil
R219_ 10.2K_1%
R220_40.2K_1%
R1582_40.2K_1%
Changed by
15mil 15mil
15mil
12
David Du
David Du
11:26:35 amThursday, August 21, 2003EE2
679
PC8803A02
SYSTEM POWER (2.5V/1.25V)
DIAMOND
A3
15mil
4A_160mil
4A_160mil
40mil
4
1S
2
3
OPEN
C1469
1
2
300K_1%
R221
12
VGA25LGND
Q1020
NDS8425
D8
7
6
5
G
R207
0
12
R223
200K_5%
TI_SN74LVC1G17DBVR_SOT_5P
U4005
2
3
5
4
PAD5
POWERPAD_2_0610
2
SSM3K17FU
Q1058 D
D
G
G
S
S
OPEN
R6019
1
2
PAD3
POWERPAD_2_0610
R1583
OPEN
1
220UF_4V_METAL
1
+VBATR
VGA25LGND
1UF_6.3V
C208
1
2
C231
1UF_10V
1
2
+VGAVCC
+V5A
C213
9.76K_1%
R225
1
2
220K_5%
R238
1
2
2
G1
G2
4
S11
3
S2
Q1019
NDS7002A
D
3
G
2
1
S
VGA25LGND
C212
1
2
Q12
FDS6982S
7
D1 8
D2 6
5
OUT2
22 PGND
PGOOD 7
9REF
SKIP#
6
TON
5
4
V+
21 VCC
VDD 20
VGA25LGND
0.1UF_25V
FB2
3ILIM1
ILIM2
12
LX1 27
LX2 16
NC0
23
28 NC1
NC2 15
ON1
10
ON2
11
1
OUT1 14
MAX_MAX1715_QSOP_28P
U13
8AGND
BST1 25
18
BST2
26
DH1
17
DH2
24
DL1
DL2 19
2
FB1
13
1
2
+V1.2_MCH
22
R1175
1
2
+VBATR
+VBATR
D
D
G
G
S
S
SIL104R_5R2
L20
12
1UF_10V
C209
1
2
220P_25V
C207
1
2
Q1057
SSM3K17FU
2
C186
0.1UF_25V
1
2
29-
R220
20K_1%
1
2
1UF_10V
C189
1
2
15K_1%
R226
1
0.1UF_25V
1
2
0.1UF_16V
C242
1
2
59-,47-,45-,40-,38-,13-,12-,7-
OPEN
C210
R236
10
12
OPEN
R1582
1
2
C232
1
2
1K_1%
R219
1
2
2
10
R235 1
2
59-,55-
+V3A
0.012UF_16V
C6016
10UF_25V
1
2
14-
+V3A
BAT54AD4
3
1
1
2
14-
68UF_6.3V_METAL
C1189
1
C205
6
5
G
41
S
23
470_5%
R1166
0.1UF_25V
C2061
2Q15
FDS6680S
D
87
5
4
G
S
123
+V1.2L
+V2.5L
C230
220UF_2.5V
1
SIL104R_7R0
L22
12
FDS6612A
Q7
8
D
76
300K_1%
R224
1
2
C211
10UF_25V
1
2
LAN_ON_3
PWRPLAY
SLP_S3#_3R
PWR_GOOD#_5
PWR_GOOD_5
![](asset-a.png)
15mil
15mil
15mil
15mil
10mil
R&D CHK Size
TITLE
of
15mil
3A_100mil
Sheet
SYSTEM POWER (VCCP&1.2) ON BUTTON DAUGHTER BOARD
15mil
10mil
10mil
40mil
40mil
15mil
DOC CTRL CHK
15mil
15mil
Date Changed Time Changed
15mil
Engineer
Drawn by
10mil
10mil
INVENTEC
MFG ENGR CHK
Model Number
15mil
15mil
VER
3A_100mil
15mil
Changed by
1
David Du
David Du
6:06:02 pmThursday, July 31, 2003EE2
6710
PC8803A02
SYSTEM POWER(VCCP/1.2V)
DIAMOND
A3
15mil
12mil
QA CHK
1
3
S2
C4040
0.1UF_25V
1
2
+V5A_BN
C4044
220UF_2.5V_S18_METAL
Q4006
FDS6984S
7
D1
8
D2
6
5
2G1
G2
4
S1
1
2
0.1UF_25V
C40351
2
+V1.2L_BN
C4026
1
2
PLFC0735P_6R8A
L4004
12
C4041
10UF_25V
1UF_6.3V
C4025
1
2
1.1K_1%
R4032
1
2220P_25V
VCCP12LGND
VCCP12LGND
R4050
100K_5%
1263-,10-
63-
2
1UF_10V
C4027
1
2
C4032
0.1UF_25V
1
2
1
2
0.1UF_16V
C4038
1
2
20K_1%
R4034
1
+VBATP_BN
R4042
22
1
2
VCCP12LGND
0.1UF_16V
C4043
0.1UF_25V
1
2
R4040
10
12
+VBATP_BN
220UF_2.5V_S18_METAL
1
R4029 0_5%
12
63-,8-
C4037
10UF_25V
1
2
L4003
PLFC0735P_6R8A
12
VCCP12LGND
C4039
10
R4041
1
2
1UF_10V
C40331
2
C4036
Q4007
FDS6984S
D1 7
8
6
D2
5
G1
2
4G2
1
S1
S2 3
2
100PF_50V
C4024
1
2
+VCCP_BN
63-,10-
+VBATP_BN
PGOOD 7
9REF
6SKIP#
TON
5
4
V+
21 VCC
VDD 20
R4028
274K_1%
1
12
LX1 27
LX2 16
NC0
23
28 NC1
NC2 15
ON1
10
ON2
11
1
OUT1 14
OUT2
22 PGND
U4003
8AGND
BST1 25
BST2 18
26
DH1
17
DH2
24
DL1
DL2 19
2
FB1
13
FB2
3ILIM1
ILIM2
63-
BAT54AD4005
3
12
MAX_MAX1715_QSOP_28P
3.92K_1%
R4027 1
2
R4030
0
12
MCH_GOOD_BN
18.7K_1%
R4026
1
2
274K_1%
R4031
1
2
SLP_S3#_3R_BN
PWR_GOOD_3_BN
LAN_ON_3_BN
PWR_GOOD_3_BN
![](asset-b.png)
Size
MFG ENGR CHK
C1780 C532 C531 PIN2 CONNECT TO Q16 , Q20 GND
TITLE
10mil
10mil
x3
10mil
of
10mil
x3
DOC CTRL CHK
R&D CHK
Date Changed
KENVEN SENSE
Time Changed Sheet
5A_200mil
25A
Drawn by
LAYOUT NOTES: C1779 C502 C503 PIN2 CONNECT TO Q14 , Q18 GND
10mil
10mil
10mil
10mil
10mil
KENVEN SENSE
VER
20mil
15mil
QA CHK
20mil
6711
PC8803A02
CPU POWER(VCC_CORE)
DIAMOND
A3
20mil
15mil
20mil
25mil
25mil
25mil
25mil
15mil
Changed by
10mil
Model Number
10mil
10mil
20mil
15mil
25mil
25mil
25mil
Engineer
INVENTEC
KENVEN SENSE
2
MAX1987GND
R272
3K_5%
1
2
David Du
David Du
10:53:10 amThursday, July 31, 2003EE2
C54
0.1UF_16V
1
2
100PF_50V
C1059 1
FAIR_NC7WZ17_SC70_6P
U1035
3
2
5
4
D1009
SSM34_3A40V2
1
MAX1987GND
+V3S
FAIR_NC7WZ17_SC70_6P
U1035
1
2
5
6
6
5
G
4
1S
2
3
10UF_25V
C10681
2
R1085
1
2
MAX1987GND
59-
Q1016FDS6694
D8
7
2
VCC_IN
C1107
220UF_2.5V
1
+VCC_CORE
0_5%
17- R2740_5%
12
S0
0_5%
R1082
1
Q1013FDS7764A
D8
7
6
5
G
4
1S
2
3
11-
0.1UF_25V
12
R10760_5%
12
+V5S
6
5
G
4
1S
2
3
59-,40-,30-,14-
15-
C1070
470PF_50V
12
+VCCP
S1
Q1012 FDS7764A
D8
7
2
11-
0.1UF_16V
C1402
1
2
11-
B2
38-
C1056
L24
12
S2
R1078
100K_5%
1
D8
7
6
5
G
4
1S
2
3
11-
HMU1050_0.6UH_17A
Q1011 8
D7
6
54 G
S
1
2
3
Q1010
FDS6694
0_5% R268
12
C11621
2
FDS6694
C291
1UF_6.3V
1
2
0.1UF_25V
C1067
12
12
R1092
4.7_5%
12
11-
R1079
1.1K_1%
1
2
R1094
750_1%
1
2
0_5%
R264
C11601
2
B0
470PF_50V
C1055
1
2
MAX1987GND
11-
OPEN
R273
1
2
+V3S
18-
S1
R1103
0_5% 12
1M_5%
R10811
2
2
R267
10
1
2
270PF_50VC1057
12
B1
S2 0.0015_5%_1W
R250
12
1K_1%
R1098
1
54 G
S
1
2
3
0_5% R1104
12
18-
R1101
0_5% 12
FDS7764AQ1014
8
D7
6
2
VCC_IN
11-
REF
SSM34_3A40V
D1008
2
1
B1
B2
R257
0.0015_5%_1W
12
100K_5%
R270
1
R1097
1K_1%
1
2
750_1%
R1095
1
2
11-
1000PF_50V_X7R
1
2
C1066
10UF_25V
1
2
11-
11-
R1404
200K_5%
12
C11611
2
C1123
R1077
28K_5%
12
0_5%
R1084
1
2
1
2
C263
220UF_2.5V
1
38-
MAX1987GND
MAX1987GND
12
0_5% R1102
12
C1058
4700PF_50V
2
L23
HMU1050_0.6UH_17A
12
18-
18-
4.7_5%
R1073
REF
R271
1.1K_1%
1
2
2.2UF_K_10V
C10691
R269
0_5%
12
C1054
0.22UF_K_10V
1
2
C10651
2
18-
MAX1987GND
OPEN
R1083
1
2
3
1
2
S0
0_5% R1075
12 SUS
43
SYSPOK
22
TH 49
TIME
1
TON
2
42
V+
12 VCC VDD 36
BAT54A
D1007
NEG
20
OAIN+
OAIN- 19
PGND 37
POS 15
PSI#
21
REF
10
6S0
S1
7
8S2
9SHDN#
34
DHS 39
35
DLM
38
DLS
44 DPSLP#
FB 18
13
GND
11 ILIM
IMVPOK
23
33
LXM
LXS 40
16
CMP 45
47
CSN
CSP 48
D0
30
29 D1
28 D2
D3
27
D4
26
25 D5
31 DDO#
DHM
MAX_MAX1987ETM_QFN48_48P
U1009
3B0
B1
4
B2
5
BSTM 32
41
BSTS
17
CCI
14 CCV
24 CLKEN#
CMN 46
1
B0
18-
C303
1UF_6.3V
1
21000PF_50V_X7R
C1064
1
2
11-
D1025 1N4148
2
FDS7764AQ1015
8
D7
6
54 G
S
1
2
3
REF
OPEN
C292
1
2
0_5% R1100
12
+VBATR
R1117
20_5%
1
2
OPEN
R1087
1
2
R1080
30.1K_1%
1
2
220UF_2.5V
C281
1
FDS6694
Q1017
8
D7
6
54 G
S
1
2
3
220UF_2.5V
C262
1
20_5%
R1159
1
2
R1086
0_5%
1
2
R1099
0_5% 12
11-
12
R1096
4.7K_5%
1
2
MAX1987GND
MAX1987GND
38-,15-
R1074
OPEN
MAX1987GND
PM_VGATE
SB_VGATE
MCH_GOOD
POWER_GROUND
LXM
PM_DPRSLPVR
CPUSTOP#_3
PSI#
PWR_GOOD_3
VR_VID2
VR_VID3
VR_VID4
VR_VID5
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
DLM
VR_VID2
VR_VID3
VR_VID4
VR_VID5
H_VID0 VR_VID0
VR_VID1
DHM
UGATE2
VR_VID0
VR_VID1
![](asset-c.png)
INVENTEC
R&D CHK
40mil
40mil
10mil
10mil
10mil
Drawn by
Engineer
3A_120mil
Changed by Date Changed
MFG ENGR CHK
Model NumberVERQA CHKTime Changed
DOC CTRL CHK
Sheet
2
EE2 Thursday, July 31, 2003 10:53:16 am
David Du
David Du
A02 PC8803 12 67
DIAMOND
VGA POWER(VDD_CORE)
A3
TITLE
of
Size
1
C298
0.01UF_16V
1
2
R266
68K_5%
1
2
10UF_K_6.3V
C11001
2
C290
330UF_2.5V_METAL
+V3
R1144 10
1
2
C1121
1UF_10V
1
GND 9
EXTREF
6
8FB
1SHDN#
SS
5
7TOFF
R1138
1K_1%
12
VCC 12
13
PGND 14
LX
PGND 15
16
LX
IN
2
3LX
4IN
1
2
+V1.25S
U1010
MAX_MAX1809EEE_QSOP_16P
10
REF 11
GND
1
2
R263
100
12
0.1UF_10V
C261
VCC
VEE
2
+V5
BAT54D6 13
C1099
10UF_K_6.3V
C1122
1UF_6.3V
1
2
59-,47-,45-,40-,38-,13-,9-,7-
MAX_MAX4322EUK_SOT23_5P
U1011
IN+
34
IN-
1OUT 5
0_5%
R1146
12
1UH
L25
12
1
2
+V2.5
26-,25-,21-
C1119
0.01UF_16V
1
2
1
2
10K_1%
R256
1
20.1UF_10V
C280
SM_VREF
10K_1%
R255
1
2
C1120
0.1UF_10V
SLP_S3#_3R
MAX1809_LXA
MA1809_V3
MA1809LX_FB
![](asset-d.png)
MFG ENGR CHK
R&D CHK
DOC CTRL CHK
QA CHK VER Model Number of
Size
INVENTEC
Drawn by
Date Changed
6
14
David Du
David Du
11:28:38 amThursday, August 21, 2003EE2
6713
PC8803A02
POWER(SLEEP)
DIAMOND
A3
Changed by Sheet
TITLE
Time Changed
Engineer
5
R78
220K
1
2
74ACT14MTC
U1038
7
5
FDR840P
Q1046 1
D2
3
6
74 G
S
8
47UF_6.3V_METAL
C1350
1
100K
R206
1
2
+V2.5L
+V5A
59-,47-,45-,40-,38-,12-,9-,7-
Q11
1
D2
3
6
74 G
S
8
5
C274
10UF_K_6.3V
1
2
49-,32-
FDR840P
+V5A
+V5
470_5%
R1345
1
2
+V1.5S
7
G
4
8
S
5
Q1039
NDS7002A
D
3
G
2
1
S
R1407
470_5%
1
2
Q10
FDR840P
D
1
2
3
6
R1344
470_5%
1
2
C1368
47UF_6.3V_METAL
1
S
5
C1369
OPEN
1
2
+V5A
+V1.5A
+V5A
+V2.5L
Q1041
FDR840P
D
1
2
3
6
7
G
4
8
470_5%
R1359
1
2
0.039UF_10V
C187
1
2
Q1042
FDC638P
D1
2
5
6
G
3
4S
NDS7002A
Q1033 3
D
2
G
S
1
+V2.5S
2
57-
+V3A
+V5A
C175
68UF_4V_METAL
1
470_5%
R1371
1
2
+V5A
+V2.5
220K
R1372
1
1
NDS7002A
Q1023 3
D
2
G
S
1
14
74ACT14MTC
U1038
7
34
14
68UF_4V_METAL
C188
C53
1
2
+V5A
74ACT14MTC
U1038
7
98
U1038
74ACT14MTC
7
11 10
14
0.1UF_16V
Q1043
NDS7002A
D
3
G
2
1
S
47UF_6.3V_METAL
C1351
1
+V3
NDS7002A
D
3
G
2
1
S
R1383
220K
1
2
7
6
54
G
S1
2
3
Q1047
1000PF_0402
C6024
1
2
NDS8425
Q6
8D
63 G
S
4
NDS7002A
Q1054 3
D
2
G
S
1
38-
R1373
330K
1
2
FDC638P
Q1035 1
D2
5
R1236
470_5%
1
2
0.1UF_16V
C52
1
2
Q1034
NDS7002A
D
3
G
2
1
S
+V3A
470_5%
R1382
1
2
2
R1204
220K
1
2
+V3S +V5S
2
14
47UF_6.3V_METAL
C1377
1
220K
R1343
1
74ACT14MTC
U1038
7
1
SLP_S3_5R
SLP_S3#_3R SLP_S3#_5R
SLP_S5#_3R SLP_S5#_5R
![](asset-e.png)
Time Changed
Changed by
MFG ENGR CHK
QA CHK
INVENTEC
of
Engineer
DOC CTRL CHK
Model Number Sheet
Size
Date Changed
+V5S
David Du
David Du
10:53:25 amThursday, July 31, 2003EE2
6714
PC8803A02
POWER(SEQUENCE)
DIAMOND
A3
Drawn by
VER
TITLE
R&D CHK
10K_5%
R1425
1
2
1N4148
D1029
2
1
1
2
Q1052
NDS7002A
D
3
G
2
1
S
59-,40-,30-,11-1
2IN2
3IN3
IN4
4
9
OUT1
OUT2 8
OUT3 7
6
OUT4
VCC
10
C1408
1UF_10V
U1032
2
3
5
4
U1036
MAX_MAX6338KUB_UMAX_10P
5
GND
IN1
C306
0.1UF_16V
1
2
+V1.5S
+V5A
TI_SN74LVC1G17DBVR_SOT_5P
180_0.5%
R1424
1
2
100K_5%
R278
1
2
1
2
R277
511K_1%
1
2
40-,38-
9-
9-
R1412
4.7K_5%
1
2
+V3S
+V3A+V3A
0.1UF_16V
C307
+V2.5S
+V5A
U1038
74ACT14MTC
7
13 12
14
VCC1_POR#_3
PWR_GOOD_5
+V1.8S
+V3S
PWR_GOOD#_5
PWR_GOOD_3
![](asset-f.png)
(10/5)
INVENTEC
Sheet
mils of CLK_TITAN
(15/5)
of
Size
TITLE
Engineer
Place crystal within 500
Date Changed Time Changed Model Number
R&D CHK
Drawn by
(10/5)
DOC CTRL CHK
MFG ENGR CHK
QA CHK VER
(10/5)
R1333 33_5%
12
EE2 Thursday, July 31, 2003 10:53:30 am
David Du
David Du
A02 PC8803 15 67
DIAMOND
CLOCK_GENEATOR
A3
Changed by
2
+V3S
38-
38-
40-
33_5%
R1340
12
2
33_5%
R1368
12
0.01UF_16V
C118
1
2
R1316
33_5% 12
37-
R1367 33_5%
1
1
2
R1313
OPEN
1
2
R1315
33_5% 1
1
2
49.9_1%R150
12
1K_5%
R1312 10PF
12
10PFC1339
12
R1366
10K_5%
OPEN 12
1K_5%
R1327
12
C1340
R147 49.9_1%
12
54-
16-
R1361
1
19-
22-
42-
45-
0.1UF_16V
C134
1
2
R1342
33_5% 12
NDS7002A
Q1040 3
D
2
G
S
29-
R1331 33_5%
12
49.9_1%R148
12
12
BLM11A221S
L1019
12
42-
C133
1
2
OPEN
R1329
12
+V3S
R1369 33_5%
2
R1341
33_5% 12
51-
16-
0.1UF_16V
R1334
33_5% 12
0_5%R1324
1
49.9_1%
R1308
12
0.01UF_16V
C1366 1
2
+V3S
1
33_5% R1338
12
19-
37-
R131733_5% 12
C1363
22UF_6.3V
X1001
14.318MHZ
1
2
0.1UF_16V
C132
1
2
0.1UF_16V
C135
1
2
33_5%
R1584
12
1
2
R1310 33_5%
12
11-
+V3S
37-,26-,25-,20-
12
R1311
1K_5%
1
2
R1335
475_1%
12
21-
R1314
OPEN
1
2
R1370
33_5%
NFM40P12C223
L1018
12
34
33_5%
R1332
1
2
49.9_1%R149
12
40-
33_5%
12
38-
49.9_1%
R1325
12
C1365
10UF_K_6.3V
0_5%
12
R1328 10K_5%
12
R1330
R133933_5% 12
59-
37-,26-,25-,20-
R1309
12
C1367
22UF_6.3V
1
55-
+V3S
38-,11-
20
VSS
31
VSS
36
VSS
47
28 VTT_PWRGD#
XTAL_IN
2
3XTAL_OUT
33_5%
R1326
37 VDD
46 VDD
50 VDD
27
VSSA
41 VSSIREF
VSS
4
VSS
9
VSS
15
VSS
55 SEL1
40 SEL2
39
USB
26
VDDA
1VDD
8VDD
14 VDD
19 VDD
32 VDD
17
PCI5
PCI6 18
5
PCIF0
PCIF1 6
7
PCIF2
34 PCI_STOP#
PWRDWN#
25
REF 56
30 SCLOCK
29 SDATA
SEL0
54
DOT 38
DRCG0
33
35 DRCG1_VCH
42 IREF
MULT0
43
PCI0 10
11
PCI1
PCI2 12
PCI3 13
16
PCI4
66BUF0
22
66BUF1
66BUF2 23
24
66INPUT
CPU0 52
CPU0# 51
49
CPU1
48
CPU1#
45
CPU2
CPU2# 44
CPU_STOP#
53
33_5% 12
38-
22-
ICS_950810_TSSOP_56P
U1020
21
PM_VGATE
CPUSTOP#_3
CLK_SIO14_3
33_5% R1337
12
R1336
CLK_ITP
CLK_MINIPCI_3R
ICH_SMDAT_3
ICH_SMCLK_3
SLP_S1#_3R
PCISTOP#_3
CLK_KBC14_3R
CLK_NICPCI_3
ADI48M
CLK_NICPCI_3R
ADI48M_3
CLK_ITP#
CLK_MCH66
CLK_MCH66_3
CLK_KBCPCI_3R
CLK_KBCPCI_3
CLK_ITP#_3
CLK_AGPCONN_3
CLK_ICHHUB_3
CLK_ICHPCI_3
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_MCH_BCLK#_3
CLK_AGPCONN
CLK_ICHHUB
CLK_ICHPCI_3R
CLK_CPU_BCLK_3
CLK_CPU_BCLK#_3
CLK_ITP_3
CLK_FWHPCI_3
CLK_SIOPCI_3R
CLK_SIOPCI_3
CLK_ICH48_3R
CLK_ICH48_3
CLK_SIO14_3R
CLK_ICH14_3R
CLK_MCH_BCLK_3
CLK_CBPCI_3R
CLK_CBPCI_3
CLK_MINIPCI_3
CLK_FWHPCI_3R
![](asset-10.png)
ADDR GROUP 0
ADDR GROUP 1
CONTROL
THERMH_CLK ITP SIGNALS
GTL4/8
POWER15/5
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
AGP4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
POWER15/5
CLK4/4_25A
CLK4/4_25A
GTL4/8
GTLDQS5/15-4/12
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTLDQS5/15-4/12
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
THERM10/10
THERM10/10
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
Time Changed
Engineer
Drawn by
R&D CHK
H_TCK FORKS
AT CPU PIN
Changed by Model NumberDate Changed Sheet of
Size
TITLE
DOC CTRL CHK
VER
INVENTEC
MFG ENGR CHK
QA CHK
GTL4/8
David Du
David Du
10:53:36 amThursday, July 31, 2003EE2
6716
PC8803A02
BANIAS-1
DIAMOND
A3
LAYOUT NOTES
23-
22-,19-
23-
37-
37-,5-
20-
22-
22-
23-
23-
23-
2
+VCCP
38-,19-
20-
38-
15-
15-
23-
22-
1
2
+VCCP
TP1
19-
56_5%
R261
1
680_5%
1
2
19-
19-
19-
R1140
150_5%
TCK A13
C12
TDI
TDO A12
B18
THERMDA
THERMDC A18
C17
THERMTRIP#
C11
TMS
M3
TRDY#
TRST# B13
R1120
R2
REQ1#
P3
REQ2#
T2
P1 REQ3#
T1 REQ4#
B11
RESET# H1
RS0#
RS1# K1
RS2# L2
B4 SMI#
C6 STPCLK#
A4
IGNNE#
A3
B5
INIT#
A16
ITP_CLK0
ITP_CLK1 A15
LINT0
D1
D4 LINT1
J2
LOCK#
A10
PRDY#
PREQ# B10
PROCHOT# B17
REQ0#
C9
BPM#3
J3
BPRI#
N4
BR0#
DBR# A7
M2
DBSY#
L4
DEFER#
DRDY# H2
D3 FERR#
HIT# K3
K4
HITM#
IERR#
W1
A9#
T4
N2
ADS#
U3 ADSTB#0
AE5 ADSTB#1
BCLK0 B15
B14
BCLK1
BNR# L1
C8
BPM#0
BPM#1 B8
BPM#2 A9
A26#
A27#
AE2
AD6 A28#
A29#
AF3
A3#
P4
A30#
AE1
AF1 A31#
U4 A4#
V3 A5#
A6#
R3
V2 A7#
A8#
A17#
AF4
A18#
AC4
AC7 A19#
A20#
AC3
A20M#
C2
AD3 A21#
AE4 A22#
A23#
AD2
A24#
AB4
AC6 A25#
AD5
19-
CN19
AMP_MPGA479M_C_1376756_479P_BANIAS
W2 A10#
Y4 A11#
A12#
Y1
A13#
U1
AA3 A14#
A15#
Y3
AA2 A16#
37-
19-
19-
19-
19-
19-
19-
19-
23-
23-
23-
37-
37-
37-
37-
22-
22-
23-
23-
23-
59-,37-
H_A#(13)
H_A#(14)
H_A#(15)
H_A#(16)
H_A#(5)
H_A#(6)
H_A#(7)
H_A#(8)
H_A#(9)
H_A#(10)
H_A#(11)
H_A#(12)
H_REQ#(2)
H_REQ#(3)
H_REQ#(4)
H_RS#(0)
H_RS#(1)
H_RS#(2)
H_A#(3)
H_A#(4)
H_A#(28)
H_A#(29)
H_A#(30)
H_A#(31)
H_BR0#
ITP_DBRESET#
H_REQ#(0)
H_REQ#(1)
H_A#(20)
H_A#(21)
H_A#(22)
H_A#(23)
H_A#(24)
H_A#(25)
H_A#(26)
H_A#(27)
TDI_FLEX
H_TDO
PM_THRMTRIP#
H_THERMDA
H_THERMDC
H_TMS
H_TRST#
H_BPM1_ITP#
H_BPM0_ITP#
H_A#(17)
H_A#(18)
H_A#(19)
CLK_CPU_BCLK#
H_BPM2_ITP#
H_BPM3_ITP#
H_BPM4_PRDY#
H_BPM5_PREQ#
H_FERR_S#
H_IGNNE#
H_INTR
H_NMI
H_SMI#
H_STPCLK#
H_TCK
H_TCK
H_HITM#
H_A#(3:16)
H_ADSTB#0H_REQ#(4:0)
H_A#(17:31)
H_LOCK#
H_INIT#
H_RS#(0:2)
H_TRDY#
H_CPURST#
H_A20M#
CLK_CPU_BCLK
H_ADS#
H_ADSTB#1
H_BNR#
H_BPRI#
H_DBSY#
H_DEFER#
H_DRDY#
H_HIT#
![](asset-11.png)
MISC
DATA GRP 0
DATA GRP 1
DATA GRP 2DATA GRP 3
Changed by Date Changed Sheet
R&D CHK
DOC CTRL CHK
MFG ENGR CHK
QA CHK VER Model Number
TITLE Size
DIAMOND
BANIAS-2
A3
LAYOUT NOTES : PLACE R1275 , R1276 CLOSE TO CN1008
of
INVENTEC
Time Changed
Engineer
Drawn by
22-
22-
22-
22-
22-
EE2 Thursday, July 31, 2003 10:53:41 am
David Du
David Du
A02 PC8803 17 67
R1118 330_5%
12
22-
22-
1K_1%
R242
1
2
21-
37-
1
2
TP570
TP571 27.4_1%R244 12
R241
2K_1%
27.4_1%R109312
PSI#
E4
PWRGOOD
C14 RSVD1
RSVD2
C3
AF7 RSVD3
A6
SLP#
TEST1 C5
F23
TEST2
C16 TEST3
DSTBN3#
DSTBP0#
C22
DSTBP1#
L24
DSTBP2# W24
AE25
DSTBP3#
GTLREF0
AD26
E26 GTLREF1
GTLREF2
G1 GTLREF3
AC1
NC0
A1
B2 NC1
E1
B24 D9#
D25 DINV0#
J26 DINV1#
T24
DINV2#
DINV3# AD20
DPSLP# B7
C19
DPWR#
DSTBN0#
C23
DSTBN1#
K24
DSTBN2# W25
AE24
AF23
AD24
D57# AF20
D58#
D59# AE21
A21 D6#
AD21
D60#
D61# AF25
D62# AF22
AF26
D63#
D7#
B20
D8#
C20
D46#
D47# Y25
AB25
D48#
D49# AC23
B26 D5#
D50# AB24
AC20
D51#
D52# AC22
D53# AC25
AD23
D54#
D55# AE22
D56#
D37# R24
D38# R26
R23
D39#
D4#
A24
AA23
D40#
D41# U26
D42# V24
D43# U25
D44# V26
Y23
D45# AA26
D27#
D28#
M25
H26 D29#
B21 D3#
N25 D30#
D31#
K25
D32# Y26
AA24
D33# T25
D34#
D35# U23
V23
D36#
D17#
L23 D18#
D19#
M26
D2#
A22
H24 D20#
D21#
F25
D22#
G24
J23 D23#
D24#
M23
D25#
J25
D26#
L26
N24
COMP3 AB1
A19 D0#
D1#
A25
D24 D10#
D11#
E24
C26 D12#
D13#
B23
E23 D14#
C25 D15#
D16#
H23
G25
22-
+VCCP
AMP_MPGA479M_C_1376756_479P_BANIAS
CN19
COMP0 P25
P26
COMP1 AB2
COMP2
22-
22-
22-
TP572
+VCCP
22-
R1088
12
11-
22-
22-
1
2
OPEN
R1141
1
2
0_5%
12
37-
R260
OPEN
12
R243 54.9_1%
37-,21-
22-
22-
R1091 54.9_1%
PSI#
R1147
OPEN
1
2
H_D#(9)
H_PWRGD
H_DPWR#
H_CPUSLP#
H_DPSLP#
H_D#(60)
H_D#(61)
H_D#(62)
H_D#(63)
H_D#(7)
H_D#(8)
H_D#(55)
H_D#(56)
H_D#(57)
H_D#(58)
H_D#(59)
H_D#(6)
H_D#(49)
H_D#(5)
H_D#(50)
H_D#(51)
H_D#(52)
H_D#(53)
H_D#(54)
H_D#(43)
H_D#(44)
H_D#(45)
H_D#(46)
H_D#(47)
H_D#(48)
H_D#(37)
H_D#(38)
H_D#(39)
H_D#(4)
H_D#(40)
H_D#(41)
H_D#(42)
H_D#(31)
H_D#(32)
H_D#(33)
H_D#(34)
H_D#(35)
H_D#(36)
H_D#(26)
H_D#(27)
H_D#(28)
H_D#(29)
H_D#(3)
H_D#(30)
H_D#(2)
H_D#(20)
H_D#(21)
H_D#(22)
H_D#(23)
H_D#(24)
H_D#(25)
H_D#(14)
H_D#(15)
H_D#(16)
H_D#(17)
H_D#(18)
H_D#(19)
H_D#(0)
H_D#(1)
H_D#(10)
H_D#(11)
H_D#(12)
H_D#(13)
H_D#(32:47)
H_DINV#2
H_DSTBN#2
H_DSTBP#2
H_D#(48:63)
H_DINV#3
H_DSTBN#3
H_DSTBP#3
H_D#(0:15)
H_DINV#0
H_DSTBN#0
H_DSTBP#0
H_D#(16:31)
H_DSTBP#1
H_DSTBN#1
H_DINV#1
![](asset-12.png)
Drawn by
R&D CHK
Changed by
Engineer
MFG ENGR CHK
QA CHK VERTime Changed
INVENTEC
DOC CTRL CHK
NOTES : INSTALL 54.9_1% FOR TESTING
Model Number Sheet of
Date Changed
Size
TITLE
0.1UF_16V
C1136
1
2
EE2 Thursday, July 31, 2003 10:53:46 am
David Du
David Du
A02 PC8803 18 67
DIAMOND
BANIAS-3
A3
10UF_K_6.3V
C11091
2
C265
10UF_K_6.3V
1
2
10UF_K_6.3V
C11141
2
C272
10UF_K_6.3V
1
2
10UF_K_6.3V
C2671
2
C284
10UF_K_6.3V
1
2
2
0.01UF_16V
C1071
1
2
0.01UF_16V
C1072
1
2
OPEN
R258
1
2
11-
0.01UF_16V
C293
1
0.1UF_16V
C1088
1
2
C1085
0.1UF_16V
1
2
0.1UF_16V
C1133
1
2
C1090
0.1UF_16V
1
2
VSSSENSE
0.1UF_16V
C1089
1
2
C1087
0.1UF_16V
1
2
VCCP8
VCCP9 F14
P23
VCCQ0
VCCQ1 W4
VCCSENSE AE7
E2
VID0 F2
VID1 F3
VID2
VID3 G3
VID4 G4
H4
VID5
AF6
VCCP20 R21
R5
VCCP21
VCCP22 T22
T6
VCCP23 U21
VCCP24
D16
VCCP3 E11
VCCP4 E13
VCCP5
VCCP6 E15
VCCP7 F10
F12
VCCP10 K6
VCCP11
VCCP12 L21
L5
VCCP13
VCCP14 M22
VCCP15 M6
VCCP16 N21
VCCP17 N5
P22
VCCP18 P6
VCCP19
D14
VCCP2
AA7
Y22
VCC70 Y6
VCC71
AA9 VCC8
AB10 VCC9
F26
VCCA0 B1
VCCA1
VCCA2 N1
VCCA3 AC26
D10
VCCP0
VCCP1 D12
F16
H22
VCC60
VCC61 H6
J21
VCC62 J5
VCC63 K22
VCC64 U5
VCC65 V22
VCC66
VCC67 V6
W21
VCC68
VCC69 W5
VCC7
E5
E7 VCC51
VCC52
E9
F18 VCC53
VCC54
F20
F22 VCC55
F6 VCC56
F8 VCC57
VCC58
G21
VCC59 G5
AA5 VCC6
VCC40
VCC41
AF8
VCC42
D18
D20 VCC43
D22 VCC44
D6 VCC45
D8 VCC46
VCC47
E17
E19 VCC48
E21 VCC49
VCC5
AA21
VCC50
VCC31
AE13
AE15 VCC32
AE17 VCC33
VCC34
AE19
VCC35
AE9
VCC36
AF10
AF12 VCC37
AF14 VCC38
VCC39
AF16
VCC4
AA19
AF18
AC17
AC19 VCC22
VCC23
AC9
AD10 VCC24
AD12 VCC25
VCC26
AD14
VCC27
AD16
VCC28
AD18
VCC29
AD8
AA17 VCC3
AE11 VCC30
VCC11
VCC12
AB16
VCC13
AB18
AB20 VCC14
VCC15
AB22
VCC16
AB6
AB8 VCC17
VCC18
AC11
AC13 VCC19
VCC2
AA15
VCC20
AC15
VCC21
0.01UF_16V
C243
1
2
+VCC_CORE
CN19
AMP_MPGA479M_C_1376756_479P_BANIAS
AA11 VCC0
AA13 VCC1
VCC10
AB12
AB14
10UF_K_6.3V
C10731
2
10UF_K_6.3V
C2941
2
10UF_K_6.3V
C2821
2
10UF_K_6.3V
C2451
2
10UF_K_6.3V
C2661
2
C1137
10UF_K_6.3V
1
2
2
C283
10UF_K_6.3V
1
210UF_K_6.3V
C11051
2
1
2
C264
10UF_K_6.3V
1
210UF_K_6.3V
C10931
+VCCP
11-
10UF_K_6.3V
C11311
2
C271
10UF_K_6.3V
1
2
C1138
10UF_K_6.3V
1
2
+VCC_CORE
+VCCA
0.1UF_16V
C1135
1
2
C1134
0.1UF_16V
1
2
C1084
10UF_K_6.3V
10UF_K_6.3V
C2951
2
C1132
0.1UF_16V
1
2
10UF_K_6.3V
C10921
2
C269
10UF_K_6.3V
1
2
11-
10UF_K_6.3V
C2731
2
C1091
10UF_K_6.3V
1
2
10UF_K_6.3V
C11061
2
C268
10UF_K_6.3V
1
2
2
C1110
10UF_K_6.3V
1
2
10UF_K_6.3V
C10831
2
1
2
C1113
10UF_K_6.3V
1
210UF_K_6.3V
C11281
1
2
+V1.5S
+V1.8S
11-
11-
11-
10UF_K_6.3V
C1129
1
2
R246
OPEN
1
2
R247
0
C2701
2
C1082
10UF_K_6.3V
1
2
10UF_K_6.3V
C1139
10UF_K_6.3V
C11111
2
C1112
10UF_K_6.3V
1
210UF_K_6.3V
10UF_K_6.3V
C2521
2
C1130
10UF_K_6.3V
1
2
C1108
100UF_2.5V_METAL
1C1086
100UF_2.5V_METAL
1
OPEN
R259
1
2
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
![](asset-13.png)
of
Size
TITLE
INVENTEC
LAYOUT NOTES : H_CPURST# PIN OF MCH_M FORK OUT INTO TWO BRANCHES ON CPU AND ITP CONNECTOR
POWER15/5
CLK4/4_25A
CLK4/4_25A
GTL4/8
POWER15/5
POWER15/5
19 67
DIAMOND
BANIAS-4
A3
In-Target Probe
Changed by Date Changed Time Changed
Engineer
Drawn by
R&D CHK
DOC CTRL CHK
MFG ENGR CHK
QA CHK VER Model Number Sheet
240_5%
R1106
1
2
EE2 Thursday, July 31, 2003 10:53:51 am
David Du
David Du
A02 PC8803
16-
16-
16-
16-
16-
38-,16-
C1074
0.1UF_16V
1
2
D5
D7 VSS94
VSS95
D9
D11 VSS96
D13
VSS97
VSS98 D15
D17
VSS99
+V3A
16-
VSS84
C4
C7 VSS85
C10 VSS86
VSS87
C13
C15 VSS88
VSS89
C18
VSS9
AA1
VSS90
C21
VSS91
C24
D2 VSS92
VSS93
AF24
B3 VSS75
VSS76
B6
B9 VSS77
B12 VSS78
VSS79
B16
A26 VSS8
VSS80
B19
VSS81
B22
VSS82
B25
C1 VSS83
VSS64
VSS65
AF2
VSS66
AF5
AF9 VSS67
VSS68
AF11
AF13 VSS69
A23 VSS7
AF15 VSS70
VSS71
AF17
AF19 VSS72
VSS73
AF21
VSS74
VSS55
AE6
AE8 VSS56
VSS57
AE10
VSS58
AE12
AE14 VSS59
VSS6
A20
VSS60
AE16
VSS61
AE18
AE20 VSS62
VSS63
AE23
AE26
VSS45
AD9 VSS46
VSS47
AD11
AD13 VSS48
VSS49
AD15
VSS5
A17
VSS50
AD17
VSS51
AD19
VSS52
AD22
AD25 VSS53
AE3 VSS54
AC8
AC10 VSS36
VSS37
AC12
VSS38
AC14
AC16 VSS39
A14 VSS4
AC18 VSS40
VSS41
AC21
VSS42
AC24
AD1 VSS43
VSS44
AD4
AD7
VSS26
AB13
AB15 VSS27
VSS28
AB17
AB19 VSS29
VSS3
A11
AB21 VSS30
VSS31
AB23
AB26 VSS32
AC2 VSS33
AC5 VSS34
VSS35
Y5
VSS19
AA22
Y21
VSS190
VSS191 Y24
A8 VSS2
AA25 VSS20
VSS21
AB3
AB5 VSS22
AB7 VSS23
AB9 VSS24
VSS25
AB11
V4
AA20 VSS18
V5
VSS180 V21
VSS181
VSS182 V25
W3
VSS183
VSS184 W6
VSS185 W22
W23
VSS186
VSS187 W26
Y2
VSS188
VSS189
AA18 VSS17
T5
VSS170
VSS171 T21
T23
VSS172 T26
VSS173
VSS174 U2
U6
VSS175 U22
VSS176
VSS177 U24
V1
VSS178
VSS179
AA16
VSS160 P2
VSS161 P5
P21
VSS162
VSS163 P24
R1
VSS164 R4
VSS165 R6
VSS166 R22
VSS167
VSS168 R25
VSS169 T3
AA14
VSS150 M1
M4
VSS151
VSS152 M5
VSS153 M21
M24
VSS154
VSS155 N3
N6
VSS156 N22
VSS157
VSS158 N23
N26
VSS159
VSS16
VSS140 J24
K2
VSS141
VSS142 K5
K21
VSS143
VSS144 K23
VSS145 K26
L3
VSS146 L6
VSS147 L22
VSS148 L25
VSS149
VSS15
G23
G26
VSS131
VSS132 H3
VSS133 H5
H21
VSS134
VSS135 H25
J1
VSS136
VSS137 J4
VSS138 J6
J22
VSS139
AA12 VSS14
VSS120 F13
VSS121
VSS122 F15
F17
VSS123
VSS124 F19
VSS125 F21
F24
VSS126
VSS127 G2
G6
VSS128 G22
VSS129
AA10 VSS13
VSS130
VSS111 E18
E20
VSS112 E22
VSS113
VSS114 E25
F1
VSS115
VSS116 F4
VSS117 F5
VSS118 F7
VSS119 F9
VSS12
AA8
F11
D21
D23
VSS102
VSS103 D26
E3
VSS104 E6
VSS105
VSS106 E8
E10
VSS107 E12
VSS108
VSS109 E14
AA6 VSS11
E16
VSS110
R1123
1
2
CN19
AMP_MPGA479M_C_1376756_479P_BANIAS
VSS0
A2
A5 VSS1
VSS10
AA4
VSS100 D19
VSS101
R112512
R1122 22.6_1%
12
39.2_1%
1
2
54.9_1%
R1105
1
2
+VCCP
22.6_1%
16-
15-
15-
27.4_1%
R1121
1
2
R1124
54.9_1%
55
6
6
77
88
9
9
16-
16-
16-
22-,16-
23
23
24
24
25 25
26
26
27
27
28 28
3
3
44
16
17
17
18
18
19 19
22
20
20
21 21
22 22
CN1002
MLX_52435_2891
11
10
10
11 11
12
12
13 13
14
14 15
15
16 H_BPM5_PREQ#
H_BPM4_PRDY#
H_BPM3_ITP#
H_BPM2_ITP#
H_BPM1_ITP#
H_BPM0_ITP#
ITP_DBRESET#
+VCCP+VCCP
16-
16-
H_TMS
H_TCK
H_TRST#
H_TDO
TDI_FLEX
H_CPURST#
H_TCK
CLK_ITP#
CLK_ITP
![](asset-14.png)
VER
Size
TITLE
LAYOUT NOTES: PUT THE THERMAL SENSOR CLOSE TO CPU
INVENTEC
Date ChangedChanged by
EE2 Wednesday, August 13, 2003 10:20:09 pm
David Du
David Du
A02 PC8803 20 67
DIAMOND
THERMAL&FAN CONTROLLER
A3
Time Changed
DOC CTRL CHK
Drawn by
R&D CHK
Sheet
MFG ENGR CHK
QA CHK of
Model Number
Engineer
8
GND 5
INT#_NTO 14
PWM_OUT1 1
3
PWM_OUT2
16 SCL
15 SDA
2
TACH1_AIN1
TACH2_AIN2 4
THERM# 7
VCC
6
2
+V3S
U15
ANLG_ADM1031ARQ_QSOP_16P
13
ADD
10 D+
D1-_NT1
9
D2+
12 D2-
11 FAN_FAULT#
2
0.1UF_16V
C285
1
2
+V5
R1435
2.2K_5%
1
NC7SZ00M5
U17
3
1
24
5
C111
0.1UF_16V
1
38-,20-
30-
30-
MLX_53398_0390_3P
CN20
GND
2
REFENCE
3
VCC
1
12
1K_5%
R262
12
+V3S
38-,20-
2
+V3S
2200PF_50V
C287
13
Q13
FDV303N
D
3
G
1
2
S
C296
1UF_10V
1
37-,26-,25-,15-
37-,26-,25-,15-
0.01UF_16V
C1060
1
2
D5
BAT54
C286
OPEN 12
40-
37-
16-
16-
ICH_SMDAT_3
ICH_SMCLK_3
THERM_SCI#
H_THERMDA
H_THERMDC
TEMP_WARN#_3
DMINUS
DPLUS
FAN_PWM_3
TEMP_WARN#_3
![](asset-15.png)
MEMORY
HUB
MEMORY
AGP
Drawn by
R&D CHK
Changed by
HUB_VREF_MCH
INVENTEC
Engineer
SM_VREF
TITLE
100MILS(+-5MILS)
QA CHKTime Changed
MCH_TEST#
Date Changed of
Size
DOC CTRL CHK
MFG ENGR CHK
VER Model Number Sheet
28-,26-
EE2 Thursday, July 31, 2003 10:54:07 am
David Du
David Du
A02 PC8803 21 67
DIAMOND
ODEM-1
A3
TP544
28-,26-
29-
37-
28-,27-,26-
27-,28-,26-
TP540
AGPREF
+V1.8S
29-
28-,25-
29-
TP539
26-,25-,12-
0.1UF_16V
C1165
1
2
TP545
29- R253
0_5%
12
10_5%
12
37-
29-
29-
10_5%
12
55-,48-,37-,29-
R1143
ST2
SWE# G11
H26 TESTIN#
AE23 WBF#
+V1.25S
TP546
R1161
G18
SMA4
SMA5 E18
F19
SMA6 G20
SMA7
SMA8 G19
F21
SMA9
SMRCOMP
J28
SRAS# F11
AG25 ST0
ST1
AF24
AG26
E3
E15
SDQS8
SDREF0 J21
J9
SDREF1
E12
SMA0
SMA1 F17
SMA10 F13
SMA11 E20
SMA12 G21
SMA2 E16
G17
SMA3
C15
D14
SDQ71
E27
SDQ8
SDQ9 C27
F26
SDQS0 C26
SDQS1 C23
SDQS2
SDQS3 B19
D12
SDQS4
SDQS5 C8
C5
SDQS6
SDQS7
C2
SDQ61 E2
SDQ62
SDQ63 G4
SDQ64 C16
D16
SDQ65
SDQ66 B15
C14
SDQ67
SDQ68 B17
C17
SDQ69
SDQ7 B28
SDQ70
B3
E6
SDQ52
SDQ53 B5
C4
SDQ54 E4
SDQ55
SDQ56 C3
SDQ57 D3
SDQ58 F4
F3
SDQ59
SDQ6 F25
SDQ60 B2
SDQ41 D8
SDQ42
SDQ43 E8
SDQ44 E11
SDQ45 B9
B7
SDQ46 C7
SDQ47
SDQ48 C6
D6
SDQ49
SDQ5 G27
D4
SDQ50
SDQ51
E13
SDQ32
SDQ33 C12
SDQ34 B11
C10
SDQ35
SDQ36 B13
C13
SDQ37 C11
SDQ38
SDQ39 D10
H25
SDQ4
SDQ40 E10
C9
SDQ22
SDQ23 B21
SDQ24 C21
SDQ25 D20
C19
SDQ26 D18
SDQ27 C20
SDQ28
SDQ29 E19
SDQ3 E28
SDQ30 C18
E17
SDQ31
B27
D27
SDQ13 D26
SDQ14 E25
SDQ15 D24
SDQ16 E23
SDQ17
SDQ18 C22
E21
SDQ19
C28
SDQ2
SDQ20 C24
B23
SDQ21 D22
SCKE2
H23
SCKE3
F23
SCS#0
E9
SCS#1
F7
SCS#2
F9
E7 SCS#3
SDQ0 G28
F27
SDQ1
SDQ10 B25
C25
SDQ11
SDQ12
J24
SCK#4 G7
SCK#5 J23
J25
SCK0
SCK1 G5
SCK2 G24
G25
SCK3
G6
SCK4
K23
SCK5
SCKE0
G23
E22 SCKE1
AE25 SBA7
G12 SBS0
SBS1
G13
SB_STB
AF27
SB_STB#
AF26
G8
SCAS#
K25
SCK#0
F5
SCK#1
E24
SCK#2
SCK#3
RSVD1
RSVD2 G22
SBA0
AH28
AH27 SBA1
AG28 SBA2
SBA3
AG27
AE28 SBA4
SBA5
AE27
SBA6
AE24
HI_REF
HI_STB
N25
HI_STB#
N24
P27 HLRCOMP
AD26 NC0
AD27 NC1
AF22 PIPE#
RBF#
AE22
RCVENIN#
G15
RCVENOUT#
G14
RSTIN#
J27
H27
P24 HI_1
M24 HI_10
N27 HI_2
HI_3
P23
HI_4
M26
HI_5
M25
L28 HI_6
HI_7
L27
M27 HI_8
HI_9
N28
P26
AA23
GDEVSEL#
W28 GFRAME#
Y24
GGNT#
AH25
GIRDY#
W27
W25 GPAR
GRCOMP
AD25
AG24 GREQ#
GSTOP#
W23
W24 GTRDY#
HI_0
P25
T27
GAD6
U27
U28 GAD7
V26 GAD8
GAD9
V27
GCBE0#
V25
V23 GCBE1#
Y25 GCBE2#
GCBE3#
GAD26
GAD27
AB24
AC25 GAD28
GAD29
AC24
GAD3
R25
GAD30
AC22
AD24 GAD31
T26 GAD4
GAD5
GAD19
T25 GAD2
GAD20
AB27
AA27 GAD21
AB26 GAD22
GAD23
Y23
GAD24
AB23
AA24 GAD25
AA25
GAD11
GAD12
T24
U24 GAD13
U25 GAD14
GAD15
V24
Y27 GAD16
GAD17
Y26
GAD18
AA28
AB25
AD_STB0
R24
AD_STB1
AC27
AGPREF
AA21
DPSLP#
V8
Y8 DPWR#
GAD0
R27
R28 GAD1
GAD10
T23
U23
27-
17-
29-
U16
ITL_ODEM_BGA_593P
P22 66IN
AD_STB#0
R23
AC28 AD_STB#1
0_5%
R251
12
R254 0_5%
12
29-
29-
29-
25-
25-
TP547
28-,27-,26-
0.1UF_16V
C218
1
2
8.2K_1%
R237
1
2
0.01UF_16V
C1190 1
2
R1155 10_5%
12
R252
1
2
15-
28-,27-,26-
29-
29-
R1156 10_5%
12
26-
0_5%
29-
29-
+V1.5S
28-,27-,26-
R1169
150_1%
1
2
R1228
10_5%
12
29-
21-
29-
29-
29-
26-
28-,25-
29-
28-,25-
21-
25-
R1191 10_5%
12
29-
21-
C1191
0.1UF_16V
1
2
+V1.8S
29-
26-
R229
OPEN
12
21-
21-
28-,25-
R1205 10_5%
12
29-
26-
+V1.5S
37-,17-
28-,27-,26-
C1180
0.1UF_16V
1
2
37-
21-
1
2
28-,26-
40.2_1%R227
1
2
36.5_1%
1
2
21-
C1148
0.1UF_16V
28-,26-,25-
R1168
150_1%
1
2
R1167
12
28-,26-
30_1%
R228
12
M_CS1_R#
M_CS0_R#
M_CS3
M_CS2
M_CS1
M_CS0
21-
25-
10_5%R1170
H_DPWR#
SM_VREF
M_CS3_R#
M_CS2_R#
PCI_RESET1#_3
AGP_ADSTB1#
AGP_ADSTB0#
H_DPSLP#
M_CAS#
M_CAS#
AGP_SBSTB#
M_BS1#
M_BS1#
M_BS0#
M_BS0#
M_CLK_DDR2
M_CLK_DDR1
M_CLK_DDR5#
M_CLK_DDR4#
M_CLK_DDR2#
M_CLK_DDR1#
M_CS1
M_CS0
M_CKE3_R#
M_CKE2_R#
M_CKE1_R#
M_CKE0_R#
M_CLK_DDR5
M_CLK_DDR4
M_CS3
M_CS2
M_A(11)
M_A(9)
M_A(0)
M_DQS7
M_DQS6
M_DQS5
M_A(7)
M_A(6)
M_A(5)
M_A(4)
M_A(3)
M_A(2)
M_A(1)
M_A(12)
AGP_WBF#
M_WE#
M_WE#
M_RAS#
M_RAS#
M_RCOMP
M_A(8)
M_A(10)
M_DQS4
AGP_ST0
AGP_ST1
AGP_ST2
M_DATA(63:0)
M_DQS_R(7:0)
AGP_AD(31:0)
AGP_CBE#(3:0)
AGP_SBA(7:0)
HUB_PD(10:0)
M_A(12:0)
AGP_SBSTB
M_DQS0
M_DQS1
M_DQS2
M_DQS3
HUB_PSTRB
HUB_PSTRB#
AGP_RBF#
M_RCVIN
GRCOMP
AGP_FRAME#
AGP_GNT#
AGP_IRDY#
AGP_PAR
AGP_REQ#
AGP_STOP#
AGP_TRDY#
HUB_RCOMP
CLK_MCH66
AGP_DEVSEL#
AGP_ADSTB0
AGP_ADSTB1
![](asset-16.png)
HOST
H_CPURST# FORKS
Size
VER
HYSWING, HXSWING 12 mil trace, 10 mil space
Sheet of
CLOSE TO MCH
LAYOUT NOTES
QA CHKChanged by Time Changed
Engineer
TITLE
INVENTEC
Drawn by
MFG ENGR CHK
Model Number
R&D CHK
DOC CTRL CHK
Date Changed
AT ODEM PIN
1
2
EE2 Thursday, July 31, 2003 10:54:13 am
David Du
David Du
A02 PC8803 22 67
DIAMOND
ODEM-2
A3
17-
17-
19-,16-
0.1UF_16V
C1140
+VCCP
220P_25V
C310
1
2
R1160
27.4_1%
1
2
+VCCP
R1148
150_1%
1
2
HSWNG0
HSWNG1
AD13
HVREF0
M7
HVREF1
P8
AA9 HVREF2
AB12 HVREF3
HVREF4
AB16
17-
17-
HDSTBP0#
AG6 HDSTBP1#
AE11 HDSTBP2#
HDSTBP3#
AC16
AC2 HRCOMP0
AC13 HRCOMP1
U2 HREQ0#
HREQ1#
T7
R7 HREQ2#
U5 HREQ3#
HREQ4#
T4
AA7
AH17
HD61# AD17
HD62#
HD63# AE16
AA6
HD7# AE3
HD8#
HD9# AB7
AD4 HDSTBN0#
HDSTBN1#
AF6
HDSTBN2#
AD11
AC15 HDSTBN3#
AD3
AF14
AG14
HD52#
HD53# AE14
HD54# AG15
AG16
HD55# AG17
HD56#
HD57# AH15
HD58# AC17
AF16
HD59#
HD6# AA3
AE15
HD60#
AF10
AG11
HD42#
HD43# AG10
AH11
HD44#
HD45# AG12
HD46# AE13
AF12
HD47#
HD48# AG13
AH13
HD49#
HD5# AC5
AC14
HD50#
HD51#
AC11
HD32#
HD33# AC12
HD34# AE9
AC10
HD35#
HD36# AE10
AD9
HD37# AG9
HD38#
HD39# AC9
AB4
HD4#
HD40# AE12
HD41#
HD22#
HD23# AD7
HD24# AH7
AE6
HD25# AC8
HD26#
HD27# AG8
AG7
HD28#
HD29# AH3
HD3# AB3
HD30# AF8
HD31# AH5
HD12# AC3
HD13# AF4
HD14#
HD15# AE2
AG4
HD16#
HD17# AG2
HD18# AE7
AE8
HD19#
AA5
HD2#
HD20# AH2
AC7
HD21# AG3
HA6#
U3
R3 HA7#
HA8#
P7
HA9#
T3
HADSTB0#
R5
N7 HADSTB1#
HD0# AA2
AB5
HD1#
HD10# AE5
AF3
HD11# AC6
HA24#
HA25#
L6
L2 HA26#
HA27#
K5
HA28#
L3
L7 HA29#
HA3#
U6
K4 HA30#
HA31#
J5
T5 HA4#
HA5#
R2
HA13#
N2 HA14#
HA15#
N5
N3 HA16#
J3 HA17#
HA18#
M3
M4 HA19#
M5 HA20#
HA21#
L5
HA22#
K3
J2 HA23#
N6
BCLK
J8 BCLK#
K8
CPURST#
AE17
AD5 DBI0#
DBI1#
AG5
DBI2#
AH9
AD15 DBI3#
P4 HA10#
P3 HA11#
HA12#
P5
R6
2
15-
15-
U16
ITL_ODEM_BGA_593P
R1151
150_1%
1
2
R1149
301_1%
1
17-
0.1UF_16V
C1142
1
2
1UF_10V
C1144
1
2
17-
17-
19-,16-
17-
1
2
100_1%
R1153
1
2
220P_25V
C308
1
2
C309
220P_25V
1
2
+VCCP
220P_25V
C1166
1
2
17-
17-
27.4_1%
R1142
C1143
220P_25V
1
2
16-
16-
R1150
301_1%
1
2
17-
17-
R1152
49.9_1%
1
2
16-
17-
16-
HXSWING
HYRCOMP
HYSWING
H_A#(31:3)
H_REQ#(4:0)
H_D#(63:0)
H_DSTBP#3
MCH_GTLREF
HXRCOMP
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBN#0
H_ADSTB#0
H_ADSTB#1
CLK_MCH_BCLK#
CLK_MCH_BCLK
H_CPURST#
H_CPURST#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
![](asset-17.png)
HOST
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
POWER15/5
POWER15/5
POWER15/5
POWER15/5
POWER15/5
POWER15/5
GTL4/8
GTL4/8
INVENTEC
Sheet
ODEM-3
DIAMOND
A3
Changed by Date Changed Time Changed
Engineer
Drawn by
R&D CHK
DOC CTRL CHK
MFG ENGR CHK
QA CHK VER Model Number of
Size
TITLE
20.1UF_16V
C1150
1
2
David Du
David Du
10:54:19 amThursday, July 31, 2003EE2
6723
PC8803A02
1
2
C216
0.1UF_16V
1
2
C1149
0.1UF_16V
1
2
+V1.5S
0.1UF_16V
C235
1
2
+V1.8S
0.1UF_16V
C1193
20.1UF_16V
C1145
1
2
0.1UF_16V
C1147
1
1
2
0.1UF_16V
C248
1
20.1UF_16V
C249
1
0.1UF_16V
C236
1
2
0.1UF_16V
C1183
1
2
0.1UF_16V
C1177
C1184
0.1UF_16V
1
2
C1182
0.1UF_16V
1
2
2
16-
0.1UF_16V
C215
1
2
16-
+VCCP
+V2.5
+V1.2_MCH
16-
0.1UF_16V
C234
1
2
16-
0.1UF_16V
C1164
1
C11791
2
16-
16-
0.1UF_16V
C1141
1
2
1
2
10UF_K_6.3V
C275
1
2
10UF_K_6.3V
1
C1178
100UF_2.5V_METAL
1
0.22UF_K_10V
C1146
2
100UF_2.5V_METAL
C246
1
C278
150UF_4V_METAL
2
16-
16-
10UF_K_6.3V
C11681
2
C1211
10UF_K_6.3V
1
2
C1212
10UF_K_6.3V
1
2
C1169
0.015UF
1
2
100UF_2.5V_METAL
C1170
1
C1176
2.2UF_0805_16V
1
1
2
C1172
10UF_K_6.3V
1
2
C1213
0.01UF_16V
1
0.1UF_16V
C250
1
20.1UF_16V
C1115
1
2
C276
0.1UF_16V
1
2
16-
C1194
0.1UF_16V
1
2
16-
2
25-
16-
C253
0.1UF_16V
1
2
16-
0.1UF_16V
C1181
AE19
VTT9 AE21
0.047UF_10V
C1174
1
2
+V1.8S
0.1UF_16V
C1192
1
VTT16 AJ21
VTT17 AJ23
M8
VTT18
VTT19 T8
VTT2 AB18
AB20
VTT3
VTT4 AB8
VTT5 AC19
AD18
VTT6 AD20
VTT7
VTT8
VCCSM7 C29
VCCSM8 D11
D15
VCCSM9
AB10
VTT0 AB14
VTT1
AF18
VTT10
VTT11 AF20
AG19
VTT12 AG21
VTT13
VTT14 AG23
VTT15 AJ19
VCCSM30
VCCSM31 H8
J6
VCCSM32 K22
VCCSM33
VCCSM34 K24
K26
VCCSM35
VCCSM36 K7
VCCSM37 L23
VCCSM4 A5
A9
VCCSM5
VCCSM6 C1
G29
VCCSM21
VCCSM22 H10
H12
VCCSM23
VCCSM24 H14
VCCSM25 H16
H18
VCCSM26 H20
VCCSM27
VCCSM28 H22
VCCSM29 H24
A25
VCCSM3
H5
VCCSM11 D23
D25
VCCSM12
VCCSM13 D7
VCCSM14 E5
F10
VCCSM15
VCCSM16 F14
F16
VCCSM17 F18
VCCSM18
VCCSM19 F22
VCCSM2 A21
VCCSM20 G1
AC29
T17 VCCGA
VCCHA
T13
L25 VCCHL0
L29 VCCHL1
M22 VCCHL2
VCCHL3
N23
N26 VCCHL4
VCCSM0 A13
VCCSM1 A17
VCCSM10 D19
AF23 VCCAGP13
AG29 VCCAGP14
VCCAGP15
AJ25
R22 VCCAGP2
VCCAGP3
R29
U22 VCCAGP4
VCCAGP5
U26
VCCAGP6
W22
W29 VCCAGP7
AB21 VCCAGP8
VCCAGP9
VCC4
P17
R14 VCC5
R16 VCC6
VCC7
T15
VCC8
U14
U16 VCC9
VCCAGP0
AA22
AA26 VCCAGP1
VCCAGP10
AD21
AD23 VCCAGP11
AE26 VCCAGP12
RSVD3
RSVD4
G10
RSVD5
G9
H7 RSVD6
H3 RSVD7
G3 RSVD8
RSVD9
G2
N14 VCC0
VCC1
N16
VCC2
P13
VCC3
P15
DEFER# Y4
W2
DRDY#
ETS#
H4
HIT# Y5
Y3
HITM#
HLOCK# W3
V4
HTRDY#
RS0# W7
W5
RS1#
RS2# W6
G16
1
2
U16
ITL_ODEM_BGA_593P
ADS# U7
BNR# V3
Y7
BPRI#
V7
BR0
DBSY# V5
0.1UF_16V
C1210
1
2
C233
0.1UF_16V
1
2
C1171
0.1UF_16V0.1UF_16V
C214
1
2
C1163
0.1UF_16V
1
2
2
C277
10UF_K_6.3V
1
2
0.1UF_16V
C1214
1
2
1
2
150UF_4V_METAL
C1215
1
0.01UF_16V
C1175
1
C1167
1
2
100UF_2.5V_METAL
C247
1
0.022UF_16V
C1173
ETS#
0.1UF_16V
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_RS#(2:0)
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DBSY#
![](asset-18.png)
Model Number Sheet of
Size
TITLE
INVENTEC
POWER15/5
EE2 Thursday, July 31, 2003 10:54:24 am
David Du
David Du
A02 PC8803 24 67
DIAMOND
ODEM-4
A3
Changed by Date Changed Time Changed
Engineer
Drawn by
R&D CHK
DOC CTRL CHK
MFG ENGR CHK
QA CHK VER
J29
VSS92
VSS93 J4
VSS94 J7
K27
VSS95
VSS96 K6
L1
VSS97
VSS98 L22
VSS99 L24
H13
H15
VSS83 H17
VSS84
VSS85 H19
VSS86 H21
H6
VSS87
VSS88 H9
J1
VSS89
VSS9
AA4
J22
VSS90
VSS91 J26
VSS72 E29
VSS73
VSS74 F12
F15
VSS75
VSS76 F20
VSS77 F24
F6
VSS78
VSS79 F8AA29 VSS8 G26
VSS80 H11
VSS81
VSS82
VSS63
AJ7
AJ9 VSS64
VSS65
D13
VSS66
D17
D21 VSS67
D5 VSS68
VSS69
D9
AA1 VSS7
E1 VSS70
VSS71 E14
E26
AH19
VSS54
AH21
AH23 VSS55
AJ11 VSS56
VSS57
AJ13
VSS58
AJ15
AJ17 VSS59
VSS6
A7
VSS60
AJ27
AJ3 VSS61
AJ5 VSS62
AF19
AF21 VSS44
VSS45
AF25
VSS46
AF5
AF7 VSS47
VSS48
AF9
AG1 VSS49
VSS5
A3
AG18 VSS50
VSS51
AG20
AG22 VSS52
VSS53
VSS34
AE1
AE18 VSS35
VSS36
AE20
AE29 VSS37
AE4 VSS38
VSS39
AF11
A27 VSS4
VSS40
AF13
AF15 VSS41
AF17 VSS42
VSS43
AC26
AC4 VSS25
AD10 VSS26
VSS27
AD12
AD14 VSS28
VSS29
AD16
VSS3
A23
VSS30
AD19
AD22 VSS31
AD6 VSS32
VSS33
AD8
VSS141
VSS15
AB19
AB22 VSS16
VSS17
AB6
VSS18
AB9
AC1 VSS19
A19 VSS2
VSS20
AC18
AC20 VSS21
AC21 VSS22
VSS23
AC23
VSS24
VSS132 U4
U8
VSS133
VSS134 V22
V6
VSS135 W1
VSS136
VSS137 W26
W4
VSS138
VSS139 W8
AB17 VSS14
VSS140 Y22
Y6
VSS122
VSS123 T14
VSS124 T16
T22
VSS125
VSS126 T6
U1
VSS127 U13
VSS128
VSS129 U15
AB15 VSS13
U17
VSS130
VSS131 U29
VSS112
VSS113 P14
P16
VSS114
VSS115 P6
VSS116 R1
R13
VSS117
VSS118 R15
R17
VSS119
VSS12
AB13
R26
VSS120
VSS121 R4
R8
M23
VSS103
VSS104 M6
N1
VSS105
VSS106 N13
VSS107 N15
N17
VSS108
VSS109 N22
AB11 VSS11
VSS110 N29
N4
VSS111 N8
U16
ITL_ODEM_BGA_593P
VSS0
A11
A15 VSS1
VSS10
AA8
L26
VSS100
VSS101 L4
L8
VSS102
![](asset-19.png)
INVENTEC
Size
QA CHK
LAYOUT NOTES : LOCATION MUST BE CENTER OF BOTTON SODIMM 0
SCK/SCK#(3)=SCK/SCK#(4)=SCK/SCK#(5)
MFG ENGR CHK
TITLE
SCK(5:3) be longer than DQS 1"~2"
VER
SDQ(63:0) from MCH to DIMM0 2"~3.5"
Model Number
DQ=CB=DQS
Date ChangedChanged by
SCK 3"~6.5"
of
Time Changed
David Du
David Du
10:54:29 amThursday, July 31, 2003EE2
6725
PC8803A02
DDR-SDRAM-1
DIAMOND
A3
SCK/SCK#(0)=SCK/SCK#(1)=SCK/SCK#(2)
SMA(12:0),SBS(1:0),SRAS#,SCAS#,SWE# 2"~3.5"
Sheet
SCS#,SCKE from MCH to DIMM0 2"~4.5"
SO DIMM 0
SM_VREF
DOC CTRL CHK
Engineer
Drawn by
R&D CHK
SCK(2:0) be longer than DQS 1"~2"
0.1UF_16V
C1117
1
2
+V2.5
+V3
87
VSS9 103
28-,27-,26-
0.1UF_16V
C1197
1
2
+V2.5
VSS29 138
VSS3 27
150
VSS30 162
VSS31 174
VSS32 186
VSS33
39
VSS4
VSS5 51
63
VSS6 75
VSS7
VSS8
VSS19
VSS2 15
VSS20 38
40
VSS21
VSS22 52
VSS23 64
76
VSS24 88
VSS25
VSS26 90
VSS27 104
126
VSS28
VREF2
3
VSS1
125
VSS10 137
VSS11
VSS12 149
VSS13 159
VSS14 161
VSS15 173
185
VSS16
VSS17 4
16
VSS18 28
192 VDD33
45 VDD4
VDD5
57
69 VDD6
VDD7
81
VDD8
93
113 VDD9
199 VDDID
VDDSPD
197
VREF1
1
2
70
82 VDD24
92 VDD25
VDD26
94
VDD27
114
132 VDD28
144 VDD29
VDD3
33
VDD30
156
VDD31
168
180 VDD32
VDD13
VDD14
167
VDD15
179
191 VDD16
10 VDD17
22 VDD18
34 VDD19
VDD2
21
VDD20
36
VDD21
46
58 VDD22
VDD23
202
G
DU1 85
123
DU2 124
DU3
DU4 200
9VDD1
VDD10
131
VDD11
143
155 VDD12
157
1
2
37-,26-,20-,15-
27-
AMP_1473005_1_200P
CN15
G
201
C181
150UF_4V_METAL
1
C1198
0.1UF_16V
28-,21-
26-,21-,12-
+V2.5
C1185
0.1UF_16V
1
2
196 SA1
198 SA2
SCL
195
SDA
193
WE#
119
21-
DQS3
DQS4
133
147 DQS5
169 DQS6
DQS7
183
DQS8
77
RAS#
118
86 RESET_DU
121 S0#
122 S1#
SA0
194
14
DQ60 178
182
DQ61 188
DQ62
DQ63 190
18
DQ7 19
DQ8
DQ9 23
11 DQS0
DQS1
25
47 DQS2
61
171
DQ50
DQ51 175
164
DQ52
DQ53 166
DQ54 172
176
DQ55 177
DQ56
DQ57 181
DQ58 187
189
DQ59
DQ6
141
145
DQ41 151
DQ42
DQ43 153
142
DQ44
DQ45 146
DQ46 152
154
DQ47
DQ48 163
165
DQ49
8
DQ5
66
68
DQ31 127
DQ32
DQ33 129
DQ34 135
139
DQ35
DQ36 128
130
DQ37 136
DQ38
DQ39 140
6
DQ4
DQ40
44
DQ21 50
DQ22
DQ23 54
DQ24 55
59
DQ25 65
DQ26
DQ27 67
56
DQ28
DQ29 60
DQ3 17
DQ30
DQ11
DQ12 20
24
DQ13 30
DQ14
DQ15 32
41
DQ16
DQ17 43
DQ18 49
53
DQ19
13
DQ2
DQ20 42
DM1
DM2
48
DM3
62
134 DM4
DM5
148
DM6
170
184 DM7
78 DM8
DQ0 5
DQ1 7
DQ10 29
31
84 CB7
35 CK0
CK0#
37
160 CK1
CK1#
158
CK2
89
CK2#
91
96 CKE0
95 CKE1
DM0
12
26
117
BA1
116
98 BA2_DU
CAS#
120
71 CB0
CB1
73
79 CB2
83 CB3
CB4
72
CB5
74
80 CB6
100
A12
99
97 A13_DU
110 A2
A3
109
108 A4
A5
107
A6
106
105 A7
A8
102
101 A9
BA0
1
2
CN15
AMP_1473005_1_200P
A0
112
111 A1
115 A10_AP
A11
28-,26-,21-
C1186
0.1UF_16V
1
2
0.1UF_16V
C1116
28-,21-
150UF_4V_METAL
C311
1
27-
27-
21-
28-,21-
37-,26-,20-,15-
0.1UF_16V
C176
1
2
27-
150UF_4V_METAL
C1241
1
OPEN
R1172
1
2
C1151
0.1UF_16V
1
2
+V3S
1
2
27-
10K_5%
R1154
1
2
23-
C1187
0.1UF_16V
GND
2
4HYST
OUT# 3
1SET
VCC 5
R248
10K_5%
1
2
OPEN
R1171
1
2
MAX_MAX6509HAUK_T_SOT23_5P
U14
27-
21-
ETS#
SM_VREF
21-
28-,21-
M_CS1_R#
ICH_SMCLK_3
ICH_SMDAT_3
M_WE_FR#
M_A_FR_(12:0)
M_DQS_R(7:0)
M_DATA_R_(63:0)
M_RAS_FR#
M_CS0_R#
M_CLK_DDR2
M_CLK_DDR2#
M_CLK_DDR1
M_CLK_DDR1#
M_CKE0_R#
M_CKE1_R#
M_BS0_FR#
M_BS1_FR#
M_CAS_FR#
![](asset-1a.png)
Sheet
Size
INVENTEC
SO DIMM 1
Date Changed Time Changed
Drawn by
SMA(12:0),SBS(1:0)
RAS#,CAS#,WE#
SMA(12:0),SBS(1:0)
Changed by Model Number
TITLE
SCK(2:0) be longer than SCS(1:0),CKE(1:0) 1"~3"
RAS#,CAS#,WE#
QA CHK VER
SCK(5:3) be longer than SCS(3:2),CKE(3:2) 1"~3"
SM_VREF
of
MFG ENGR CHK
R&D CHK
Engineer
EE2 Thursday, July 31, 2003 10:54:35 am
David Du
David Du
A02 PC8803 26 67
DIAMOND
DDR-SDRAM-2
A3
DOC CTRL CHK
28-,27-,21-
21-
C1216
0.1UF_16V
1
2
162
174
VSS32
VSS33 186
VSS4 39
51
VSS5
VSS6 63
VSS7 75
87
VSS8 103
VSS9
52
VSS22 64
VSS23
VSS24 76
VSS25 88
90
VSS26 104
VSS27
VSS28 126
138
VSS29
27
VSS3
VSS30 150
VSS31
VSS12
VSS13 159
161
VSS14 173
VSS15
VSS16 185
4
VSS17
VSS18 16
VSS19 28
15
VSS2
38
VSS20
VSS21 40
69
VDD7
81
93 VDD8
VDD9
113
VDDID
199
197 VDDSPD
1VREF1
VREF2
2
VSS1 3
VSS10 125
VSS11 137
149
114 VDD27
VDD28
132
VDD29
144
33 VDD3
156 VDD30
168 VDD31
VDD32
180
VDD33
192
VDD4
45
57 VDD5
VDD6
10
22 VDD18
VDD19
34
21 VDD2
36 VDD20
46 VDD21
VDD22
58
70 VDD23
VDD24
82
VDD25
92
94 VDD26
123
124
DU3 200
DU4
VDD1
9
131 VDD10
143 VDD11
VDD12
155
VDD13
157
167 VDD14
179 VDD15
VDD16
191
VDD17
CN16
AMP_C_1279284_1_DDR_SODIMM_200P
201
GG
202
85
DU1
DU2
28-,21-
C1118
0.1UF_16V
1
2
27-,28-,21-
195
SDA
193
WE#
119
21-
OPEN
R239
1
2
25-,21-,12-
28-,27-,21-
169 DQS6
DQS7
183
DQS8
77
RAS#
118
86 RESET_DU
121 S0#
122 S1#
SA0
194
196 SA1
198 SA2
SCL
DQ62
DQ63 190
18
DQ7 19
DQ8
DQ9 23
11 DQS0
DQS1
25
47 DQS2
61 DQS3
DQS4
133
147 DQS5
DQ52
DQ53 166
DQ54 172
176
DQ55 177
DQ56
DQ57 181
DQ58 187
189
DQ59
DQ6 14
DQ60 178
182
DQ61 188
DQ43 153
142
DQ44
DQ45 146
DQ46 152
154
DQ47
DQ48 163
165
DQ49
8
DQ5
171
DQ50
DQ51 175
164
129
DQ34 135
139
DQ35
DQ36 128
130
DQ37 136
DQ38
DQ39 140
6
DQ4
DQ40 141
145
DQ41 151
DQ42
54
DQ24 55
59
DQ25 65
DQ26
DQ27 67
56
DQ28
DQ29 60
DQ3 17
DQ30 66
68
DQ31 127
DQ32
DQ33
30
DQ14
DQ15 32
41
DQ16
DQ17 43
DQ18 49
53
DQ19
13
DQ2
DQ20 42
44
DQ21 50
DQ22
DQ23
DM4
DM5
148
DM6
170
184 DM7
78 DM8
DQ0 5
DQ1 7
DQ10 29
31
DQ11
DQ12 20
24
DQ13
37
160 CK1
CK1#
158
CK2
89
CK2#
91
96 CKE0
95 CKE1
DM0
12
26 DM1
DM2
48
DM3
62
134
CAS#
120
71 CB0
CB1
73
79 CB2
83 CB3
CB4
72
CB5
74
80 CB6
84 CB7
35 CK0
CK0#
A2
A3
109
108 A4
A5
107
A6
106
105 A7
A8
102
101 A9
BA0
117
BA1
116
98 BA2_DU
CN16
AMP_C_1279284_1_DDR_SODIMM_200P
A0
112
111 A1
115 A10_AP
A11
100
A12
99
97 A13_DU
110
150UF_4V_METAL
C313
1
28-,21-
28-,25-,21-
28-,27-,21-
+V3S
OPEN
R240
1
2
1
2
28-,21-
21-
+V3S
1
2
0.1UF_16V
C217
+V2.5
+V2.5
28-,21-
0.1UF_16V
C1195
2
0.1UF_16V
C1196
1
2
28-,27-,21-
21-
37-,25-,20-,15-
C1152
0.1UF_16V
1
1
2
0.1UF_16V
C177
1
2
150UF_4V_METAL
C1312
1
37-,25-,20-,15-
C254
0.1UF_16V
0.1UF_16V
1
2
28-,27-,21-
28-,27-,25-
SM_VREF
C1153
M_RAS#
M_CS2_R#
M_CS3_R#
ICH_SMCLK_3
ICH_SMDAT_3
M_WE#
M_A(12:0)
M_DQS_R(7:0)
M_CAS#
M_CLK_DDR5
M_CLK_DDR5#
M_CLK_DDR4
M_CLK_DDR4#
M_CKE2_R#
M_CKE3_R#
M_BS0#
M_BS1#
M_DATA_R_(63:0)
![](asset-1b.png)
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
Drawn by
TITLE
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
DDR4/8
Sheet of
close to DIMM0<750 mil
close to DIMM1<750 mil
MFG ENGR CHK
QA CHKChanged by
DOC CTRL CHK
VERDate Changed
David Du
David Du
10:54:40 amThursday, July 31, 2003EE2
6727
PC8803A02
DDR-SDRAM-3
DIAMOND
A3
R&D CHK
INVENTEC
Model NumberTime Changed
Engineer
Size
3
1
4
27
5
8
6
10_5%
R1162
12
10
RS13
25-
25-,27-28-,26-,21-,27-
10
4
3
1
27
8
6
5
RS10
3
1
2
45
7
8
6
RS1011
4
2
1
36
8
7
5
10
1
2
3
45
6
7
8
RS101510
45
6
7
8
28-,26-,21-
RS1000
10_5%
45
6
7
8
10_5%
RS1001
1
2
3
5
6
7
8
10_5%
RS1003
1
2
3
6
7
8
RS1004
10_5%
1
2
3
4
7
8
10_5%
RS1009
1
2
3
45
8
RS1005
10_5%
1
2
3
45
6
10_5%
RS1008
1
2
3
45
6
7
10_5%
1
2
3
45
6
7
8
10_5%
RS1019
1
2
3
45
6
7
8
RS1010
1
2
3
45
6
7
8
1
2
3
45
6
7
8
RS1014
10_5%
2
3
45
6
7
8
RS1020
10_5%
3
45
6
7
8
10_5%
RS1021
1
45
6
7
8
RS1024
10_5%
1
2
5
6
7
8
10_5%
RS1025
1
2
3
6
7
8
RS1029
10_5%
1
2
3
4
12
10_5%
RS1030
1
2
3
45
25-
25-,27-
28-,26-,21-
28-,26-,21-
28-,26-,21-
28-,26-,21-
28-,26-,21-,27-
R1163
10_5%
21-
28-,26-,25-
25-
25-
25-
M_A_FR_(2)
M_BS0#
M_BS1#
M_CAS#
M_RAS#
M_A(2)
M_WE_FR#
M_WE#
M_A_FR_(4)
M_A_FR_(6)
M_A_FR_(7)
M_A_FR_(10)
M_A_FR_(3)
M_A_FR_(0)
M_A_FR_(1)
M_BS0_FR#
M_BS1_FR#
M_CAS_FR#
M_RAS_FR#
M_A(5)
M_A(9)
M_A(8)
M_A(4)
M_A(6)
M_A(7)
M_A(10)
M_A(3)
M_A(1)
M_A(0)
M_A_FR_(12:0)
M_A_FR_(12)
M_A_FR_(11)
M_A_FR_(5)
M_A_FR_(9)
M_A_FR_(8)
M_A(12:0) M_A(12)
M_A(11)
M_DATA(63:0)
M_DATA_R_(63:0)
![](asset-1c.png)
Close to DDR as passible
Changed by Date Changed Time Changed
Engineer
Drawn by
R&D CHK
DOC CTRL CHK
MFG ENGR CHK
QA CHK VER Model Number Sheet of
Size
TITLE
INVENTEC
28
PC8803A02
DDR-SDRAM-4
DIAMOND
A3
close to DIMM1< 800mil
78
C255
0.1UF_16V
1
2
David Du
David Du
10:54:46 amThursday, July 31, 2003EE2
67
RS1012
56
1234
56
R1164 56_5%
1
2
R1235 56_5%
1
2
5678
56_5%
R1145
1
2
RS1002
56
1234
C6036
100PF_50V
1
2
100PF_50V
C6037
1
2
25-,21-
2
C6034
100PF_50V
1
2100PF_50V
C6035
1
2
1
2
100PF_50V
C6032
1
2
100PF_50V
C6033
1
2
0.1UF_16V
C241
1
2
C6031
100PF_50V
1
8765
27-,26-,21-
0.1UF_16V
C1199
1
1
2
56
RS1031
432
2
0.1UF_16V
C179
1
2
27-,26-,25-,28-
C221
0.1UF_16V
0.1UF_16V
C195
1
2
27-,26-,21-
0.1UF_16V
C178
1
100PF_50V
C256
1
2
27-,26-,21-,28-
0.1UF_16V
C194
1
2
0.1UF_16V
C1157
1
2
56_5%
R1173
1
2
0.1UF_16V
C279
1
2
27-,26-,21-,28-
5
56_5%R1193
1
2
C257
0.1UF_16V
1
2
56
RS15
4321
87665
26-,21-
C223
0.1UF_16V
1
2
1
2
56
RS16
4321
87
2
27-,26-,25-,28-
56_5%
R249
1
2
C1188
0.1UF_16V
56_5%R1192
1
2
C239
0.1UF_16V
1
0.1UF_16V
C192
1
2
R1157 56_5%
1
2
RS12
56
1324
5768
1
2
C1158
0.1UF_16V
1
2
25-,21-
26-,21-
C1154
0.1UF_16V
1
2
C1155
0.1UF_16V
23
6758
C259
0.1UF_16V
1
2
C191
0.1UF_16V
1
2
RS11
56
14
RS1006
56
1234
5678
5
0.1UF_16V
C180
1
2
56
RS1027
4321
876
2
C238
0.1UF_16V
1
2
56_5%
R1158
1
2
23
6758
0.1UF_16V
C193
1
8765
56
RS14
14
1
2
56
RS1026
4321
RS18
4321
8765
C224
0.1UF_16V
2
27-,26-,21-
C219
0.1UF_16V
1
2
56
C1159
0.1UF_16V
1
2
56_5%R1206
1
RS1013
56
1243
6578
1234
5678
27-,26-,21-
RS1022
4321
8765
RS1007
56
2
26-,21-
C196
0.1UF_16V
1
2
56
5
25-,21-
0.1UF_16V
C258
1
2
0.1UF_16V
C240
1
56
RS17
4321
876
0.1UF_16V
C1200
1
2
0.1UF_16V
C222
1
2
1234
5678
0.1UF_16V
C1156
1
2
26-,21-
26-,25-,21-,28-
RS8
56
1
2
+V1.25S
+V1.25S
C220
0.1UF_16V
1
2
8
25-,21-
0.1UF_16V
C251
1
2
C237
0.1UF_16V
RS5
56
1234
567
8765
27-,26-,21-
0.1UF_16V
C260
1
2
78
56
RS1017
4321
78
RS7
56
1234
56
RS9
56
1234
56
56
RS1016
3421
8756
1
2
C1201
0.1UF_16V
M_A(12:0) M_DQS_R(7:0)
M_BS1#
M_CKE0_R#
M_CKE1_R#
M_CKE2_R#
M_CKE3_R#
M_WE#
M_RAS#
M_CAS#
M_DATA_R_(63:0)
M_DATA_R_(63:0)
M_BS0#
M_A(12:0)
M_DQS_R(7:0)
M_CS2_R#
M_CS3_R#
M_CS0_R#
M_CS1_R#
![](asset-1d.png)
8X 4X
AGP PCI / AGP
LVDS
AGP2X
DVO / EXT TMDS / GPIO
R&D CHK
QA CHK Model Number
LAYOUT NOTE : C1255 , C3 CLOSE TO M9+X
TITLE
Changed by Date Changed
Size
of
M10 R1277, R191 USED 3K OHM
Sheet
Time Changed
USED M10 R184 , R181, R177, R188 PULL UP 10K
USED M9+X R1198 49.9 OHM
USED M10 R1198 47 OHM
Engineer
USED M9+X R184 , R181 OPEN
DOC CTRL CHK
EE2 Thursday, July 31, 2003 10:54:52 am
David Du
David Du
A02 PC8803 29 67
DIAMOND
ATI-M10-P-1
A3
VER
Drawn by
M9+X R1277, R191OPEN
INVENTEC
MFG ENGR CHK
15-
R1274
OPEN
12
TP563
20K_5%R122212
R1273
OPEN
12
R1286 1K_1%
12
1K_5%R195 12
21-
2
21-
21-
21-
21-
36-
R183 1K_1%
12
29-
R190
OPEN
1
12
29-
1K_1%
R185 12
R1183 12
21-
21-
1K_1%
R1265
36-
21-
36-
36-
+V3S
10_5%
2
10K_1%
R188
12
10K_1%
R184
12
R1198 47_5%
12
R177
10K_1%
1
1K_5%
12
C1232
0.1UF_16V
1
2
36-
2
10UF_K_6.3V
C12081
2
21-
29-
36-
55-,48-,37-,21-
R196
2
R1181 10_5%
12
R1178 10_5%
1
12
TP14
10_5%
R1177 1
1K_1%
R194 12
TP559
21-
1K_1%
R1287
21-
36-
R1267
OPEN
1
2
AGPREF
+V3S
36-
R186 12
TP568
21-
10K_5%
R1269 12
36-
TP562
1K_1%
2
R1186 10_5%
12
R1271 1K_1%
12
3K_5%
R191
1
2
R1200 20K_5%
1
2
TP566
36-
21-
9-
36-
10_5%
R1185 12
29-
R189 1K_1%
1
1
2
OPEN
R1268
1
2
36-
21-
12
R1184 10_5%
12
10K_5%
R1275
12
R1187 10_5%
12
21-
10_5%
R1179
R1266 12
36-
10_5%
R1180
2
R1189 10_5%
12
36-
21-
1K_5%
10_5%
R1182 12
10_5%
R1188 1
12
36-
10K_5%
R1270 12
1K_1%
R1285 12
21-
21-
36-
36-
R181
10K_1%
1
2
36-
R1262 1K_1%
12
+V3S
21-
R1199 20K_5%
12
OPEN
R1272
R1277
3K_5%
1
2
+V1.5ATIAGP
36-
36-
36-
ZV_LCDDATA8
ZV_LCDDATA9 AJ9
36-
36-
37-
30-
ZV_LCDDATA19
ZV_LCDDATA2 AK6
ZV_LCDDATA20 AE9
AF9
ZV_LCDDATA21 AG10
ZV_LCDDATA22
ZV_LCDDATA23 AF10
AH7
ZV_LCDDATA3 AK7
ZV_LCDDATA4
ZV_LCDDATA5 AJ7
AH8
ZV_LCDDATA6
ZV_LCDDATA7 AJ8
AH9
AJ6
ZV_LCDDATA1
ZV_LCDDATA10 AK9
AH10
ZV_LCDDATA11 AE6
ZV_LCDDATA12
ZV_LCDDATA13 AG6
AF6
ZV_LCDDATA14
ZV_LCDDATA15 AE7
ZV_LCDDATA16 AF7
ZV_LCDDATA17 AE8
ZV_LCDDATA18 AG8
AF8
TXOUT_U2N
TXOUT_U2P AE18
TXOUT_U3N AH20
AG20
TXOUT_U3P
VREFG AG4
WBF#
AC26
AJ10
ZV_LCDCNTL0
ZV_LCDCNTL1 AK10
AJ11
ZV_LCDCNTL2 AH11
ZV_LCDCNTL3
ZV_LCDDATA0 AH6
TXOUT_L0P AH17
TXOUT_L1N
TXOUT_L1P AJ16
TXOUT_L2N AH18
AJ17
TXOUT_L2P AK19
TXOUT_L3N
TXOUT_L3P AH19
AG16
TXOUT_U0N
TXOUT_U0P AF16
TXOUT_U1N AG17
AF17
TXOUT_U1P AF18
ST0
AF29
ST1
AD27
AE28 ST2
STOP#
N26
TRDY#
V28
TXCLK_LN AK18
AJ18
TXCLK_LP
AF19
TXCLK_UN AG19
TXCLK_UP
TXOUT_L0N AK16
AH16
RST#
AD28 SBA0
SBA1
AD29
SBA2
AC28
AC29 SBA3
SBA4
AA28
AA29 SBA5
Y28 SBA6
Y29 SBA7
SB_STBF
AB29
AB28 SB_STBS
AF4
AJ3
GPIO6 AK3
GPIO7
GPIO8 AH3
GPIO9 AJ2
AE26 INTA#
W29 IRDY#
PAR
M25
PCICLK
AG30
AE29 RBF#
REQ#
AF28
AG28
AH2
GPIO10 AH1
GPIO11
GPIO12 AG3
AG1
GPIO13
GPIO14 AG2
GPIO15 AF3
AF2
GPIO16
GPIO2 AJ4
AK4
GPIO3 AH4
GPIO4
GPIO5
P26
U26 C_BE#3
AB25 DBI_HI
AB26 DBI_LO
V29 DEVSEL#
DIGON AE12
DVOMODE AE10
FRAME#
W28
GNT#
AD26
GPIO0 AJ5
AH5
GPIO1
AD9
ADSTBS_0
M29
V26 ADSTBS_1
M28 AD_STBF_0
V25 AD_STBF_1
AGP8X_DET#
AC25
M26 AGPREF
AGPTEST
M27
AG12
BLON
N29 C_BE#0
C_BE#1
U28
C_BE#2
AD28
Y25
AA26 AD29
J28 AD3
AA25 AD30
AD31
AA27
AD4
K29
K28 AD5
L29 AD6
L28 AD7
AD8
N28
P29
AD18
AD19
R27
AD2
J29
R25 AD20
AD21
T25
AD22
T26
U25 AD23
V27 AD24
W26 AD25
AD26
W25
Y26 AD27
H29 AD0
AD1
H28
P28 AD10
AD11
R29
R28 AD12
AD13
T29
AD14
T28
U29 AD15
AD16
N25
R26 AD17
P25
21-
21-
TP561
21-
+V3S
ATI_M9_M10_BGA_748P
U11
R1263 1K_1%
12
R193 1K_5%
12
1K_1%
R182 12
R187 1K_1%
12
AGP_WBF#
AGP_STOP#_R
AGP_DEVSEL#_R
AGP_TRDY#_R
AGP_ADSTB0_R
AGP_ADSTB1_R
AGP_SBSTB_R
AGP_WBF#_R
AGP_REF#_R
AGP_FRAME#_R
AGP_IRDY#_R
AGP_IRDY#
AGP_TRDY#
AGP_ADSTB0
AGP_ADSTB1
AGP_SBSTB
AGP_STOP#
AGP_DEVSEL#
AGP_FRAME#
AGP_ADSTB0#_R
AGP_SBSTB#_R
AGP_SBSTB#
AGP_ADSTB0#
AGP_ADSTB1#
AGP_ADSTB1#_R
PWRPLAY
GPIO16
VGA_GPIO(0)
VGA_GPIO(1)
VGA_GPIO(2)
VGA_GPIO(3)
LCM_ID0
LCM_ID1
LCM_ID2
LCDDATA20
LCM_ID3
LCM_ID4
AGP_AD(31:0)
AGP_CBE#(3:0)
AGP_SBA(7:0) TXOUTL2+
TXOUTU0-
TXOUTU0+
TXOUTU1-
TXOUTU1+
TXOUTU2-
TXOUTU2+
TXCLKOUTL+
TXCLKOUTU-
TXCLKOUTU+
TXOUTL0-
TXOUTL0+
TXOUTL1-
TXOUTL1+
TXOUTL2-
AGP_SBA(5)
AGP_SBA(6)
AGP_SBA(7)
AGP_ST0
AGP_ST1
AGP_ST2
TXCLKOUTL-
AGP_RBF#
AGP_REQ#
PCI_RESET1#_3
AGP_SBA(0)
AGP_SBA(1)
AGP_SBA(2)
AGP_SBA(3)
AGP_SBA(4)
DIGON
AGP_GNT#
VGA_GPIO(0)
VGA_GPIO(1)
VGA_GPIO(2)
VGA_GPIO(3)
PIRQA#_3
AGP_PAR
CLK_AGPCONN
BLON#
AGP_CBE#(0)
AGP_CBE#(1)
AGP_CBE#(2)
AGP_CBE#(3)
AGP_AD(4)
AGP_AD(5)
AGP_AD(6)
AGP_AD(7)
AGP_AD(8)
AGP_AD(9)
AGP_AD(26)
AGP_AD(27)
AGP_AD(28)
AGP_AD(29)
AGP_AD(3)
AGP_AD(30)
AGP_AD(31)
AGP_AD(2)
AGP_AD(20)
AGP_AD(21)
AGP_AD(22)
AGP_AD(23)
AGP_AD(24)
AGP_AD(25)
AGP_AD(14)
AGP_AD(15)
AGP_AD(16)
AGP_AD(17)
AGP_AD(18)
AGP_AD(19)
AGP_AD(0)
AGP_AD(1)
AGP_AD(10)
AGP_AD(11)
AGP_AD(12)
AGP_AD(13)
![](asset-1e.png)
DAC2
PWR
THERM
TMDS
DAC1
SS
CLK
MAN
(20/5)
Drawn by
R&D CHK
(20/5)
FOR EMI
Changed by
M9+X USED R1203 120 OHM , R1202 100 OHM
M10 USED R1203 200 OHM , R1202 120 OHM
MFG ENGR CHK
Engineer
TITLE
INVENTEC
OPEN
Sheet
Date Changed
LAYOUT NOTES : R1359, R1361, R1360, R1362 CLOSE TO M9+X
QA CHKTime Changed
DOC CTRL CHK
EE2 Thursday, August 21, 2003 11:32:01 am
David Du
David Du
A02 PC8803 30 67
DIAMOND
ATI-M10-P-2
A3
VER of
Size
Model Number
AJ14
AH15
TX1P
TX2M AJ15
AK15
TX2P AH13
TXCM
TXCP AK13AK24 V2SYNC
AH25
VSYNC
AH28 XTALIN
XTALOUT
AJ29
AJ22 Y_G
AG29 RSTB_MSK
SSIN
AK25
AJ25 SSOUT
STP_AGP#
AH30
AG26 SUS_STAT#
TESTEN
AH27
B6 TEST_MCLK
E8 TEST_YCLK
AJ13
TX0M
TX0P AH14
TX1M
AG24
DMINUS AE11
DPLUS AF11
AJ27
G
H2SYNC
AJ24
AF12
HPD1
HSYNC AG25
PLLTEST
AE25
RAK27
R2SET
AK21
RSET AH26
AH29 AGP_BUSY#
AF26
AUXWIN
BAJ26
COMP_B
AK22
AJ23 C_R
DDC1CLK AF24
AF25
DDC1DATA
AE13
DDC2CLK
DDC2DATA AE14
AG23 DDC3CLK
DDC3DATA
57-
33_5%
R1288
12
57-
U11
ATI_M9_M10_BGA_748P
R1226
330_5%
12
120_5%
R1202
1
2
10K_5%
R208
12
+V3S
+V3S
330_5%
R1227
12
BLM21A121S
L1015
12
330_5%
R1225
12
R1201
1K_5%
12
OPEN
R64
1
2
10UF_10V_METAL
C1325
1
10K_5% R161
12
TP20
TP19
C1239
15PF
1
2
12
R1203
200_5%
12
57-
57-
29-
10K_5%
R1319
12
57-
+V3S
1K_5%
R1190
12
715_1%
R192
12
20K_5%
R1436
1
2
12
75_1%
R6027
12
R1276
330_5%
+V3S
57-
R1630_5%
12
R6026 75_1%
499_1%
12
R1176
1K_1%
1
2
57-
57-
12
57-
C1240
0.1UF_16V
1
2R209
8
38-
20-
AGPREF
57-
+V1.5ATIAGP
59-,42-,40-,38-
+V3S
0.1UF_16VC1326
2
CYS_IMISM560BZT_SOIC_8P
U10
3
GND
7S0
6S1 SSCC 5
SSCLK 4
2VDD
1
XIN_CLK
XOVT
57-
35-
35-
R1290
10K_5%
1
12
20-
57-
35-
30-
+V3S
+V3S
36-
57-,35-
OPEN
R164
1
2
59-,40-,14-,11-
R6028 75_1%
GND 2
OE
1
3
OUTVDD
4
10K_5%
R1318
12
57-
57-,35-
2
R210 OPEN
12
57-
27MHZ
X1000
R1197
1K_1%
1
2
30-
0_5%
R211 1
1
2
+V3S
38-
57-
36-
35-
GPIO16
PWR_GOOD_3
R162
10K_5%
C3_STAT#
DMINUS
DPLUS
HSYNC
VSYNC
DDCDATA
DDCCLK
SUS_STAT#_3
TX2P
TXCM
TXCP
DVIDDCCLK
DVIDDCDATA
R
G
B
LUMA_Y
27MHZ
HPD
TX0M
TX0P
TX1M
TX1P
TX2M
AGPBUSY#_3
LCM_DDCCLK
LCM_DDCDATA
27MHZ
COMP_B
CHROMA_C
![](asset-1f.png)
MEMORY INTERFACE A
MEMORY INTERFACE B
Date Changed
near the ATI
CLOSE TO MEMORY
VER
Engineer
Time Changed
R&D CHK
LAYOUT NOTES : R176 R175 CLOSE TO ATI
LAYOUT NOTES : R171 R172 CLOSE TO ATI
Changed by
THEN R145 R1370 OPEN
INVENTEC
TITLE
of
place these componts
USED ELPIDA MEMORY R1253 & R1256 CHANGE TO 732 OHM
IF USED ELPIDA MEMORY R134 R135 ADD 4.7K
R237, R238 CLOSE TO U2163
LAYOUT NOTES:
CLOSE TO ATI
DOC CTRL CHK
Layout Note:
PLEASE OPEN ON M9+X
Layout note:
Size
Layout Note:
Drawn by
MFG ENGR CHK
C120 , C125 USED M9+X 0.01UF , M10 470PF
CLOSE TO MEMORY
Layout Note:
Model Number Sheet
ONLY ELPIDA MEMORY TO INSTALL
1
2
EE2 Thursday, July 31, 2003 10:55:09 am
David Du
David Du
A02 PC8803 31 67
DIAMOND
ATI-M10-P-3
A3
QA CHK
34-
34-
34-
34-
31-
+V1.8S
R1256
1K_1%
1
3
6
7
89
31-
31-
31-
4
10
11
14
16
15
12
13
5
2
12
TP71
31- 10
RS1033
R171 10_5%
1
2
+VRAM_VCC
31-
OPENR1261
47_5%
R1259
1
2
34-
34-
10_5%R172
12
470PF_50V
C125
1
2
34-
TP25
12
1K_1%
R1254
1
2
34-
TP69
34-
10_5%R173
1K_1%
R1253
1
2
0.1UF_16V
C1300
1
2
34-
10_5%
R1283 12
31-
34-
34-
31-
31-
31-
34-
OPEN
12
TP66
31-
31-
34-
31-
TP28
R1258
31-
R143
56_5%
12
34-
34-
34-
R1260
4.7K_5%
1
2
215
31-
+V1.8S
34-
34-
31-
31-
12
11
10
9
7
6
5
4
1
3
1
2
31-
RS3 10
8
14
16
13
R174 10_5%
12
31-
31-
34-
R1255
1K_1%
34-
2
31-
34-
31-
34-
34-
34-
34-
34-
31-
34-
4.7K_5%R1257 1
0_5%R1281 12
34-
34-
34-
12
R1284 0_5%
12
C120
470PF_50V
1
2
10_5%R175
31-
31-
31-
C1299
10UF_K_6.3V
1
2
34-
34-
31-
TP67
34-
QSA4 E16
B16
QSA5 B11
QSA6
QSA7 F10
A19
RASA#
E19
WEA#
31-
TP68
MAA5 F22
MAA6
MAA7 F21
MAA8 C21
A24
MAA9
B7
MVREFD
MVREFS B8
J27
QSA0
QSA1 F30
QSA2 F24
B27
QSA3
E11
E22
MAA0
MAA1 B22
C24
MAA10
MAA11 A25
E21
MAA12
MAA13 B20
MAA14 C19
MAA2 B23
B24
MAA3
MAA4 C23
C22
G26 DQA7
G30 DQA8
DQA9
D29
J25
DQMA#0
DQMA#1 F29
DQMA#2 E25
A27
DQMA#3
DQMA#4 F15
C15
DQMA#5 C11
DQMA#6
DQMA#7
B9
B10 DQA55
E13 DQA56
DQA57
E12
DQA58
E10
F12 DQA59
DQA6
H26
DQA60
F11
E9 DQA61
F9 DQA62
DQA63
F8
DQA44
DQA45
B14
DQA46
C14
C16 DQA47
DQA48
A13
A12 DQA49
DQA5
H25
C12 DQA50
DQA51
B12
C10 DQA52
DQA53
C9
DQA54
F16 DQA35
DQA36
E15
F14 DQA37
E14 DQA38
DQA39
F13
J26 DQA4
DQA40
C17
B18 DQA41
B17 DQA42
DQA43
B15
C13
DQA25
C25 DQA26
DQA27
C27
B28 DQA28
DQA29
B25
DQA3
K26
DQA30
C26
B26 DQA31
F17 DQA32
DQA33
E17
DQA34
D16
F28
G25 DQA16
DQA17
F26
DQA18
E26
F25 DQA19
K25 DQA2
DQA20
E24
F23 DQA21
E23 DQA22
DQA23
D22
DQA24
B29
C29
F20
CSA1#
D30
DIMA_0
DIMA_1 B13
DQA0
L25
L26 DQA1
DQA10
D28
E28 DQA11
DQA12
E29
G29 DQA13
G28 DQA14
DQA15
31-
ATI_M9_M10_BGA_748P
U11
CASA# E18
CKEA B19
B21
CLKA0
CLKA0# C20
CLKA1 C18
A18
CLKA1#
CSA0# E20
34-
34-
1
2
31-
31-
34-
33-
31-
C1298
0.1UF_16V
12
56_5%
R145
12
34-
34-
R144
56_5%
12
34-
R176 10_5%
TP70
R1585 10_5%
12
34-31-
31-
QSB5 W1
QSB6 AC5
AD1
QSB7
R2
RASB#
AF5
ROMCS#
WEB# T6
31-
MAB7 N3
MAB8
MAB9 K2
MEMTEST C8
MEMVMODE_0 C6
C7
MEMVMODE_1
QSB0 F6
B3
QSB1 K6
QSB2
QSB3 G1
V5
QSB4
MAB1
MAB10 K3
J2
MAB11
MAB12 P5
MAB13 P3
P2
MAB14
M3
MAB2
MAB3 L3
L2
MAB4
MAB5 M2
MAB6 M5
P6
C5 DQB9
DQMB#0 E6
B2
DQMB#1
DQMB#2 J5
DQMB#3 G3
W6
DQMB#4
DQMB#5 W2
DQMB#6 AC6
AD2
DQMB#7
MAB0 N5
M1
AB2
AB3 DQB57
AC2 DQB58
DQB59
AC3
E5 DQB6
AD3 DQB60
DQB61
AE1
DQB62
AE2
AE3 DQB63
DQB7
C4
DQB8
B5
DQB46
DQB47
AA2
AA6 DQB48
DQB49
AA5
DQB5
F5
DQB50
AB6
AB5 DQB51
DQB52
AD6
AD5 DQB53
AE5 DQB54
DQB55
AE4
DQB56
DQB37
W4
DQB38
Y6
Y5 DQB39
G5 DQB4
U2 DQB40
DQB41
V2
DQB42
V1
V3 DQB43
DQB44
W3
Y2 DQB45
Y3
DQB27
DQB28
F2
J3 DQB29
G6 DQB3
F1 DQB30
DQB31
H3
DQB32
U6
U5 DQB33
U3 DQB34
DQB35
V6
W5 DQB36
DQB17
H5 DQB18
DQB19
J6
DQB2
E7
DQB20
K5
DQB21
K4
DQB22
L6
L5 DQB23
G2 DQB24
DQB25
F3
DQB26
H2
E2
DIMB_1 AA3
D7 DQB0
DQB1
F7
DQB10
A4
DQB11
B4
C2 DQB12
DQB13
D3
DQB14
D1
D2 DQB15
DQB16
G4
H6
ATI_M9_M10_BGA_748P
U11
T5
CASB#
R3
CKEB
CLKB0 N1
N2
CLKB0#
T2
CLKB1
CLKB1# T3
R5
CSB0#
CSB1# R6
E3
DIMB_0
2
+VRAM_VCC
34-
10UF_K_6.3V
C13011
2
56_5%
R142
1
DIMB_1
DIMB_0
DDR_CSB1#
GMAB_R(6)
DDR_CSB1#
GMAB(8)
GMAB(13)
GMAB(12)
GMAB(6)
GMAB(7)
GMAB(0) GMAB_R(0)
GDQMB(2)
GDQMB(3)
GDQMB(4)
GDQMB(5)
GDQMB(6)
GDQMB(7)
GMAB(9)
GMAB(3)
GMAB(4)
GMAB(2)
GMAB(5)
GMAB(1)
GDQMB(0)
GDQMB(1)
GMAB_R(1)
GMAB_R(7)
DDR_CSB1#_R
GMAB_R(12)
GMAB_R(13)
GMAB_R(8)
DDR_CASB#
GMAB(10)
GMAB_R(5)
GMAB_R(2)
GMAB_R(4)
GMAB_R(3)
GMAB_R(9)
GMAB_R(10)
GMAB_R(11)
QSB0
QSB7
QSB6
QSB5
QSB4
GMAB(11)
QSB3
QSB2
QSB1
DDR_CLKB1_R
DDR_CLKB0#
DDR_CLKB0
DDR_CLKB0#_R
DDR_CLKB0_R
DDR_CKEB DDR_CKEB_R
DDR_CSB0#
DDR_RASB# DDR_CSB0#_R
DDR_RASB#_R
DDR_CLKB1#
DDR_CLKB1
DDR_CLKB1#_R
DDR_CLKB0#
DDR_CLKB1
DDR_CLKB1#
DDR_WEB#
DDR_CASB#_R
DDR_WEB#_R
GMAB(5)
GMAB(4)
GMAB(3)
GMAB(2)
GMAB(1)
GMAB(0)
DDR_CASB#
DDR_WEB#
DDR_CSB0#
DDR_CKEB
DDR_CLKB0
GMDB(1)
GMDB(0)
GMAB(13:0)
GMAB(12)
GMAB(11)
GMAB(10)
GMAB(9)
GMAB(8)
GMAB(7)
GMAB(6)
GMDB(9)
GMDB(8)
GMDB(7)
GMDB(6)
GMDB(5)
GMDB(4)
GMDB(3)
GMDB(2)
GMDB(17)
GMDB(16)
GMDB(15)
GMDB(14)
GMDB(13)
GMDB(12)
GMDB(11)
GMDB(10)
GMDB(25)
GMDB(24)
GMDB(23)
GMDB(22)
GMDB(21)
GMDB(20)
GMDB(19)
GMDB(18)
GMDB(33)
GMDB(32)
GMDB(31)
GMDB(30)
GMDB(29)
GMDB(28)
GMDB(27)
GMDB(26)
GMDB(41)
GMDB(40)
GMDB(39)
GMDB(38)
GMDB(37)
GMDB(36)
GMDB(35)
GMDB(34)
GMDB(49)
GMDB(48)
GMDB(47)
GMDB(46)
GMDB(45)
GMDB(44)
GMDB(43)
GMDB(42)
GMDB(57)
GMDB(56)
GMDB(55)
GMDB(54)
GMDB(53)
GMDB(52)
GMDB(51)
GMDB(50)
GMAB(13)
DDR_RASB#
GMDB(63:0)
GMDB(63)
GMDB(62)
GMDB(61)
GMDB(60)
GMDB(59)
GMDB(58)
![](asset-20.png)
I / O POWER
CORE GND
M9 INNER ROWS
M10 CENTER ARRAY
INVENTEC
DOC CTRL CHK
Sheet
INSTALL L1005 INSTALL L18
of
Size
QA CHK VER
TITLE
USED M9+X PLEASE OPEN THIS SYMBOL
USED M10 PLEASE OPEN THIS SYMBOL
R1282,R1221 USED M9+X IS OPEN , USED M10 CHANGE TO 0 OHM
USED M9+X OPEN L18 , USED M10 OPEN L1005
NOTES: USED+V1.5S FOR M10 INSTALL L1013 OPEN L1009
NOTES: USED+V1.8S FOR M9+X INSTALL L1009 OPEN L1013
Date Changed Time Changed
Engineer
Drawn by
Changed by
R&D CHK
Model Number
MFG ENGR CHK
USED M9+X OPEN L1011 , USED M10 OPEN D6008
INSTALL D6008 , INSTALL L1011
1
2
David Du
David Du
8:32:25 pmThursday, August 14, 2003EE2
6732
PC8803A02
ATI-M10-P-4
DIAMOND
A3
1
2
L17
BLM11A121S
12
1000PF_0402
C1254
1
2
C1258
10UF_K_6.3V
1
2
0.1UF_16V
C1278
2
VDD_MEM2.5
C1262
0.01UF_16V
1
2
10UF_K_6.3V
C1251
12
1000PF_0402
C1272
1
2
C1277
0.01UF_16V
1
68UF_4V_METAL
C1268
1
+V2.5S
BLM21A121S
L18
1
2
C1256
0.1UF_16V
1
2
NFM41P11C204
L11
12
3
4
1000PF_0402
C1267
C1234
0.01UF_16V
1
2
+VRAM_VCC
0.1UF_16V
C1273
1
2
C1324
22UF_6.3V
1
C1266
0.1UF_16V
1
2
OPEN
L1009
12
+V1.8S
0.01UF_16V
C1259
1
2
+V1.5ATIAGP
2
1000PF_0402
C1261
1
2
C1260
22UF_6.3V
1
+VRAM_VCC
C1269
0.01UF_16V
1
2
0.1UF_16V
C1307
1
Y8
VDD15
VDD_PNLPLL1.8+V1.8S
+VGAVCC
+V1.8S
VDD2DI
F18 VDDRH0
VDDRH1
N6
AE23
VSS1DI
VSS2DI AE21
F19
VSSRH0
VSSRH1 M6
W30
VDDP
Y23
VDD15
VDDP Y27
TPVDD
TPVSS AJ12
U27
VDDP
V23
VDDP
VDDP V24
VDDR1
V4
VDDR1
V7
V8 VDDR1
VDD1DI
AE24
AE22
VDDR1
R4 VDDR1
T23
VDDP T24
VDDP
VDDP T30
T4 VDDR1
VDDR1
T7
T8 VDDR1
AK12
N4 VDDR1
VDDR1
N7 VDDR1
N8
P23
VDDP
VDDP P27
VDD15 P8
PVDD
AK28 PVSS AJ28
R1
VDDR1
L8
LPVDD
AJ20
AJ19
LPVSS
M23
VDDP
VDDP M24
M4 VDDR1
A7 MPVDD A6
MPVSS
VDDP N30
J23 VDDR1
VDDR1
J24
VDDP J30
VDDR1
J4 VDDR1
J7
J8 VDDR1 VDD15 L23
L27 VDDR1
H11
VDD15
VDDR1
H13
VDDR1
H15
H17 VDDR1
VDDR1
H19
VDD15 H20
H22 VDDR1
J1 VDDR1
VDDR1
G10
G13 VDDR1
G15 VDDR1
VDDR1
G19
VDDR1
G22
G27 VDDR1
VDDR1
G7
H10 VDDR1
D19 VDDR1
VDDR1
D20
D23 VDDR1
D26 VDDR1
VDDR1
D5 VDDR1
D8
E27 VDDR1
F4 VDDR1
AVDD
AH23
AVSSN
AVSSQ AD24
VDDR1
B1
VDDR1
B30
D11 VDDR1
VDDR1
D13
D14 VDDR1
VDDR1
D17
AG13
AG14
TXVSSR
A2VDD
AG21
VDDR4 AG7
AH12
TXVSSR
AH21 A2VDD
A2VSSN AH22
AJ21
A2VSSN
AH24
LVDDR_25
AE30
VDDP
TXVDDR
AF13
AF14 TXVDDR
LVSSR AF15
LVSSR AF20
AF21 LVDDR_18
AF27
VDDP
TXVSSR
AD22
VDDR1
AD4
VDDR3 AD7
AD9
VDDR4
LVDDR_18
AE15
AE16
LVSSR
LVDDR_25
AE17
AE19
LVSSR
AE20
AC27
AC8
VDDR3
VDDR4 AC9
AD10
VDDR4
AD13
VDDC AD15
VDDC
AD19
VDDR3 AD21
VDDR3
VDDR3
AC13
VDDC AC15
AC17
VDDC
VDDR3 AC19
VDD15 AC20
VDDR3 AC21
AC22
VDDR3
AC23
VDDP
VDDP
VDDP
VDDP AA24
VDDR1
AA4
VDDR1
AA7
AA8 VDDR1
VDDP AB30
VDDR4 AC10
AC11
VDD15
VDDC
VDDR1
A15
A21 VDDR1
A28 VDDR1
A2VDDQ
AF22 A2VSSQ AF23
A3 VDDR1
VDDR1
A9
AA1 VDDR1
AA23 C1209
22UF_6.3V
1
+V1.5S
U11
ATI_M9_M10_BGA_748P
L1004
BLM11A121S
12
C1257
0.01UF_16V
1
2
BLM11A121S
L1008
12
0.01UF_16V
C1280
1
2
0.01UF_16V
C1253
1
2
C1263
1000PF_0402
1
2
VSS U8
VSS V30
W23
VSS
VSS W24
VSS W27
VSS W7
W8
VSS
Y4
VSS
VSS R24
R30
VSS
VSS R7
R8
VSS
T1
VSS
VSS T27
U23
VSS
U4
VSS
VSS M30
M7
VSS
M8
VSS
VSS N23
VSS N24
N27
VSS P4
VSS
VSS R23
VSS K1
VSS
K23 VSS
K24
K27 VSS
VSS
K30
VSS K7
K8
VSS
L4
VSS
VSS
H16
H18 VSS
VSS
H21
H23 VSS
H27 VSS
H4 VSS
H8 VSS
VSS
H9
VSS
G12
G16 VSS
G18 VSS
VSS
G21
VSS
G24
G9 VSS
H12 VSS
VSS
H14
VSS
D24
VSS D25
VSS
D27
VSS
D4
D6 VSS
VSS
D9
VSS
E4
VSS
F27
C28 VSS
VSS
C3
C30 VSS
D10
VSS
D12 VSS
D15 VSS
VSS
D18
D21 VSS
VSS
AG27
VSS
AG5
AG9 VSS
AJ1
VSS
VSS AJ30
AK2
VSS
VSS AK29
VSS
C1
VSS AD18
AD25
VSS
AD30
VSSVSS
AE27
VSS
AG11
AG15 VSS
AG18 VSS
AG22 VSS
AB8
VSS
VSS AC12
AC14
VSS
VSS AC16
VSS AC18
AC4
VSS
AD12 VSS
AD16
VSS
A29 VSS
VSS AA30
VSS AB1
VSS AB23
AB24
VSS
AB27
VSS
AB4 VSS
VSS AB7
2
U11
ATI_M9_M10_BGA_748P
A10 VSS
A16 VSS
VSS
A2
VSS
A22
3
4
0.01UF_16V
C1231
1
2
C1270
0.1UF_16V
1
2
C1228
1000PF_0402
1
2
L1010 NFM41P11C204
12
L16
BLM11A121S
12
L1013
BLM21A121S
1
22UF_6.3V
C168
1
BLM11A121S
L1012
12
VDD_PNLIO1.8
1
2
0.1UF_16V
C1230
1
2
2
C1276
0.01UF_16V
1
2
VDD_DAC1.8
0.1UF_16V
C1309
+V3S
+V1.5S
+V2.5S
0.01UF_16V
C1303
1
R1282
12
C174
10UF_K_6.3V
1
2
1000PF_0402
C1274
1
2
C1229
0.01UF_16V
1
2
0_5%
C1322
1
2
C1233
0.01UF_16V
1
2
W9
VDDC
Y22
Y9 VDDC
+V1.8S
1000PF_0402
C1302
1
2
0.01UF_16V
R9
T22 VDDC
VDDC
T9
U22 VDDC
VDDC
U9
VDDC
V22
V9 VDDC
W22
VSS
VSS
L9
M22 VDDC
VDDC
M9
VSS N22
N9
VSS
P22 VDDC
VDDC
P9
R22 VDDC
VDDC
VDDC
J20
VSS
VDDC
J21
VSS J22
VSS J9
VDDC
K22
K9 VDDC
L22
VSS
VSS
VSS
VDDC
J12
J13
VSS
J14 VDDC
VDDC
J15
J16 VDDC
VDDC
J17
VSS J18
J19
ATI_M9_M10_BGA_748P
U11
AA22
VSS
VSS AA9
VDDC
AB22
AB9 VDDC
J10 VDDC
J11
10UF_K_6.3V
C12551
2
0.01UF_16V
C1252
1
2
C1237
10UF_K_6.3V
1
2
C1275
0.01UF_16V
1
2
VDD_DAC2.5
+V1.8S
1
2
0.1UF_16V
C1308
1
2
VDD_PLL1.8
VDD_MEMPLL1.8
D6008
BAT54C_OPEN
12
3
0.01UF_16V
C1279
2
C1305
0.01UF_16V
1
2
BLM11A121S
L1007
12
1
C1321
0.01UF_16V
1
2
C1306
0.1UF_16V
1
4
0_5%
R1221
12
C167
22UF_6.3V
W19
L1005
OPEN
12
NFM41P11C204
L1003
12
3
VDDC
W12 VDDC
VDDC
W13
VDDC
W14
W15
VSS
W16
VDDC1
W17 VDDC
VDDC
W18
VDDC
U19
VDDC
V12 VDDC
V13
V14 VDDC
VSS V15
V16
VSS
VDDC
V17
V18 VDDC
V19
VSS
VSS T19
VDDC
U12
U13 VDDC
VDDC
U14
VSS U15
VDDC
U17
U18 VDDC
VDDC
VSS
VDDC1 R19
T12
VDDC1
T13
VSS
VSS T14
VSS T15
VSS T16
T17
VSS
T18
VDDC
P19 VDDC
VSS R12
R13
VSS
R14
VSS
VSS R15
VSS R16
R17
VSS
R18
VDDC
VDDC
N19
P12 VDDC
P13 VDDC
P14 VDDC
P15
VSS
VSS P16
VDDC
P17
P18
VDDC
M19 VDDC
N12 VDDC
N13 VDDC
N14 VDDC
VSS N15
VSS N16
VDDC
N17
N18
U11
U16
VSS
VDDC
M12
VDDC
M13
VDDC
M14
VDDC1 M15
M16
VSS
VDDC
M17
M18
1
2 0.01UF_16V
C1236
1
2
ATI_M9_M10_BGA_748P
0.01UF_16V
C1265
1
2
10UF_K_6.3V
C1238
22UF_6.3V
C1207
1
+V1.8S
+AGP_V3S
C1304
22UF_6.3V
1
0.01UF_16V
1
2
+V1.8S
C190
10UF_K_6.3V
1
2
12
C1281
10UF_K_6.3V
1
2
C1310
S
4
49-,13-
C1264
1000PF_0402
1
2
L1011 BLM11A121S
1
2
FDC638P
Q6006
1
D2
5
63 G
1
2
0.01UF_16V
C1271
1
2
0.01UF_16V
C1311
C1235
0.01UF_16V
1
2
VDD_PNLIO2.5 0.01UF_16V
C1323
SLP_S3_5R
![](asset-21.png)
INVENTEC
TITLE
QA CHK
Changed by
R&D CHK
INVENTEC
R&D CHK
Changed by
Size
MFG ENGR CHK
QA CHK
Time Changed Model Number
LAYOUT NOTES : THIS IS DEPEND RESISTOR NEED CLOSE TO VIDEO RAM
DOC CTRL CHK
Model NumberDate Changed
Drawn by
MFG ENGR CHK
Size
VER of
VER Sheet of
33 67
DIAMOND
A3
Drawn by
TITLE
Time Changed
Engineer
Engineer
DOC CTRL CHK
Sheet
Date Changed
34-
34-
David Du
David Du
10:55:23 amThursday, July 31, 2003EE2
67
33
A02
VGA DEPEND RESISTOR
DIAMOND
A3
EE2 Thursday, July 31, 2003 10:55:23 am
David Du
David Du
A02 PC8803
31-
31-
34-
34-
34-
34-
34-
34-
34-
34-
34-
34-
31-
31-
31-
31-
31-
31-
31-
31-
31- 31-
31-
34-
34-
34-
34-
34-
34-
34-
34-
34-
34-
34-
31-
31-
31-
34-
34-
34-
34-
34-
34-
31-
31-
31-
31-
31-
31-
31-
34-
34-
34-
34-
22
RS1038
3
1
4
27
5
8
6
1
3
2
45
7
6
8
31-
31-
1
2
3
45
6
7
8
22
RS1042
4
2
3
18
6
7
5
RS1043
22
1
2
45
7
8
6
RS1049
22
3
18
6
7
5
22
RS1046
3
31-
31-
31-
31-
31-
31-
RS1036
22
4
2
5
31-
31-
31-
31-
31-
31-
34-
34-
31-
31-
7
22
RS1035
4
3
2
18
7
6
22
RS1040
2
3
4
18
5
6
RS1041
22
1
4
3
27
6
5
8
22
RS1045
4
3
2
18
7
6
5
RS1044
22
4
2
3
18
6
7
5
22
RS1048
4
3
1
27
8
6
5
22
4
3
2
18
7
6
5
4
3
2
18
7
6
5
RS1039
RS1047
1
3
2
45
7
6
8
RS1034
22
2
4
3
18
6
5
7
22
31-
31-
34-
34-
34-
34-
34-
34-
RS1037
22
31-
31-
31-
31-
31-
34-
34-
31-
31-
31-
31-
34-
34-
34-
34-
34-
31-
31-
31-
31-
31-
31-
34-
34-
34-
34-
34-
34-
34-
34-
34-
34-
31-
31-
31-
31-
31-
34-
34-
34-
34-
34-
34-
GMDB_R(47)
GMDB_R(43)
GMDB_R(49)
GMDB_R(53)
31-
31-
31-
GMDB_R(1)
GMDB_R(3)
GMDB_R(28)
GMDB_R(30)
GMDB_R(24)
GMDB_R(26)
GMDB(62)
GMDB(57)
GMDB(59)
GMDB(63)
GMDB(56)
GMDB(58)
GMDB_R(6)
GMDB(55)
GMDB(52)
GMDB(54)
GMDB(53)
GMDB(60)
GMDB(61)
GMDB(28)
GMDB(48)
GMDB(50)
GMDB(51)
GMDB(49)
GMDB(27)
GMDB(26)
GMDB(25)
GMDB(24)
GMDB(31)
GMDB(30)
GMDB(29)
GMDB(40)
GMDB(41)
GMDB(45)
GMDB(46)
GMDB(42)
GMDB(47)
GMDB(44)
GMDB(35)
GMDB(34)
GMDB(33)
GMDB(32)
GMDB(39)
GMDB(43)
GMDB(18)
GMDB(23)
GMDB(20)
GMDB(21)
GMDB(17)
GMDB(16)
GMDB(22)
GMDB(10)
GMDB(15)
GMDB(14)
GMDB(13)
GMDB(12)
GMDB(19)
GMDB(6)
GMDB(4)
GMDB(7)
GMDB(5)
GMDB(9)
GMDB(11)
GMDB(8)
GMDB_R(59)
GMDB_R(57)
GMDB_R(58)
GMDB_R(56)
GMDB(3)
GMDB(2)
GMDB(0)
GMDB(1)
GMDB_R(54)
GMDB_R(52)
GMDB_R(55)
GMDB_R(63)
GMDB_R(62)
GMDB_R(61)
GMDB_R(60)
GMDB_R(40)
GMDB_R(46)
GMDB_R(45)
GMDB_R(44)
GMDB_R(51)
GMDB_R(50)
GMDB_R(48)
GMDB_R(35)
GMDB_R(39)
GMDB_R(33)
GMDB_R(38)
GMDB_R(32)
GMDB_R(34)
GMDB_R(42)
GMDB_R(41)
GMDB_R(23)
GMDB_R(22)
GMDB_R(27)
GMDB_R(25)
GMDB_R(31)
GMDB_R(29)
GMDB(37)
GMDB_R(36)
GMDB_R(37)
GMDB_R(15)
GMDB_R(16)
GMDB_R(17)
GMDB_R(18)
GMDB_R(19)
GMDB_R(21)
GMDB_R(20)
GMDB_R(4)
GMDB_R(10)
GMDB_R(8)
GMDB_R(11)
GMDB_R(9)
GMDB_R(12)
GMDB_R(13)
GMDB_R(14)
GMDB(36)
GMDB(38)
GMDB_R(7)
GMDB_R(0)
GMDB_R(2)
GMDB_R(5)
![](asset-22.png)
DDR4/8DDR4/8
TO THE MOMORY
of
INVENTEC
PLACE IN
DOC CTRL CHK
QA CHK
Engineer
Size
R&D CHK
Sheet
+V1.8S FOR ELPIDA MEMORY
TITLE
PLACE CLOSE
TO THE MOMORY
Thursday, July 31, 2003EE2
6734
PC8803A02
VIDEO RAM-2
DIAMOND
A3
PLACE CLOSE
Model Number
MOMORY SECTION
VER
MFG ENGR CHK
Time ChangedDate ChangedChanged by
MOMORY SECTION
PLACE IN
Drawn by
12
C130 0.1UF_16V
12
David Du
David Du
10:55:28 am
31-
31-
31-,34-
31-,34-
0.1UF_16VC126
C129 0.1UF_16V
12
C131 0.1UF_16V
12
31-
12
31-,34-
0.1UF_16VC149
12
12
31-
31-
C128 0.1UF_16V
31-
31-
31-,34-
0.1UF_16VC151
R1322
1K_1%
1
2
R1323
1K_1%
1
2
+VRAM_VCC
22UF_6.3V
C13451
2
34-
12
C144 0.1UF_16V
12
31-,34-
+V2.5S
22_5% 12
22_5%R1304 12
0.1UF_16VC142
R1303 22_5% 12
22_5%R1306 12
R1300
12
0.1UF_16VC143
12
22_5%
12
R1296 22_5%
12
22_5%R1293
22_5%R1298
12
R1294
31-,34-
31-
0.1UF_16VC140
12
31-
C1348
22UF_6.3V
1
2
22UF_6.3V
C1344
1
2
C146 0.1UF_16V
12
C127 0.1UF_16V
12
1K_1%
R1321
1
2
31-,34-
31-
22_5%R1305 12
R1301 22_5% 12
R1299 22_5%
12
22_5%R1295
12
0.1UF_16VC141
12
+VRAM_VCC
0.1UF_16V
C1342
1
2
1K_1%
R1320
1
2
31-
+VRAM_VCC
34-
47UF_6.3V_METAL
C1349
1
34-
31-
MCL
M13
N3 NC
RAS#
M2
N13 VREF
WE#
L3
31-,34-
31-,34-
34-
34-
34-
VDD L4
L5
VSS
L7
VDD L8
VDD
L9 RFU
RFU
M10
M3 NC
NC
M4
K6
VSS
VSS K7
VSS K8
K9
VSS
VSS L10
VDD L11
L12 NC
NC
L13
TH_GND
J6
J7 TH_GND
J8 TH_GND
TH_GND
J9
VSSQ K10
VDDQ K11
K4
VDDQ
K5
VSSQ
H6 TH_GND
TH_GND
H7
TH_GND
H8
H9 TH_GND
J10
VSSQ
J11
VDDQ
VDDQ J4
VSSQ J5
G6 TH_GND
TH_GND
G7
TH_GND
G8
G9 TH_GND VSSQ H10
NC
H11
H4 NC
H5
VSSQ
TH_GND
F6
F7 TH_GND
F8 TH_GND
TH_GND
F9
VSSQ G10
G11
VDDQ
VDDQ G4
G5
VSSQ
VSSQ E6
VSS E7
VSS E8
E9
VSSQ
F10
VSSQ
VDDQ F11
F4
VDDQ
VSSQ F5
H13
H2 DQS2
DQS3
B13
E10
VSS
E11
VDD
E12
VDDQ
VDDQ E3
VDD E4
E5
VSS
DQ29
B5
DQ3
C9
DQ30
DQ31 B8
DQ4 C2
D3
DQ5 D2
DQ6
DQ7 E2
DQ8 K13
K12
DQ9
B2 DQS0
DQS1
DQ2 B6
J3
DQ20
DQ21 J2
DQ22 K2
K3
DQ23 E13
DQ24
DQ25 D13
DQ26 D12
C13
DQ27
DQ28 B10
B9
C6
J13
DQ10
DQ11 J12
G13
DQ12
DQ13 G12
DQ14 F13
F12
DQ15
DQ16 F3
F2
DQ17 G3
DQ18
DQ19 G2
VSSQ D6
D7
VDD
VDD D8
D9
VSSQ
DM0
B3
H12 DM1
DM2
H3
B12 DM3
B7
DQ0
DQ1
L2 CAS#
CKE
N12
M11 CLK
CLK#
M12
N2 CS#
D10
VSSQ
VSSQ D11
VSSQ D4
D5
VSSQ
BA1
C10
VDDQ
NC
C11
VDDQ C12
VDDQ C3
C4 NC
C5
VDDQ C7
VDDQ
VDDQ C8
A3
A4
N8
M9 A5
N9 A6
A7
N10
N11 A8_AP
A9
M8
VSSQ B11
B4
VSSQ
BA0
N4
M5
N13 VREF
WE#
L3
U1019
SAM_K4D263238A_GC40_FBGA_144P
N5 A0
A1
N6
A10
L6
M7 A11
A2
M6
N7
L7
VDD L8
VDD
L9 RFU
RFU
M10
M3 NC
NC
M4
MCL
M13
N3 NC
RAS#
M2
K9
VSS
VSS L10
VDD L11
L12 NC
NC
L13
VDD L4
L5
VSS
J8 TH_GND
TH_GND
J9
VSSQ K10
VDDQ K11
K4
VDDQ
K5
VSSQ
K6
VSS
VSS K7
VSS K8
H9 TH_GND
J10
VSSQ
J11
VDDQ
VDDQ J4
VSSQ J5
TH_GND
J6
J7 TH_GND
G9 TH_GND VSSQ H10
NC
H11
H4 NC
H5
VSSQ
H6 TH_GND
TH_GND
H7
TH_GND
H8
F8 TH_GND
TH_GND
F9
VSSQ G10
G11
VDDQ
VDDQ G4
G5
VSSQ
G6 TH_GND
TH_GND
G7
TH_GND
G8
E9
VSSQ
F10
VSSQ
VDDQ F11
F4
VDDQ
VSSQ F5
TH_GND
F6
F7 TH_GND
E10
VSS
E11
VDD
E12
VDDQ
VDDQ E3
VDD E4
E5
VSS
VSSQ E6
VSS E7
VSS E8
DQ4 C2
D3
DQ5 D2
DQ6
DQ7 E2
DQ8 K13
K12
DQ9
B2 DQS0
DQS1
H13
H2 DQS2
DQS3
B13
K2
K3
DQ23 E13
DQ24
DQ25 D13
DQ26 D12
C13
DQ27
DQ28 B10
B9
DQ29
B5
DQ3
C9
DQ30
DQ31 B8
DQ12
DQ13 G12
DQ14 F13
F12
DQ15
DQ16 F3
F2
DQ17 G3
DQ18
DQ19 G2
DQ2 B6
J3
DQ20
DQ21 J2
DQ22
D9
VSSQ
DM0
B3
H12 DM1
DM2
H3
B12 DM3
B7
DQ0
DQ1 C6
J13
DQ10
DQ11 J12
G13
CLK#
M12
N2 CS#
D10
VSSQ
VSSQ D11
VSSQ D4
D5
VSSQ
VSSQ D6
D7
VDD
VDD D8
C12
VDDQ C3
C4 NC
C5
VDDQ C7
VDDQ
VDDQ C8
L2 CAS#
CKE
N12
M11 CLK
A7
N10
N11 A8_AP
A9
M8
VSSQ B11
B4
VSSQ
BA0
N4
M5 BA1
C10
VDDQ
NC
C11
VDDQ
U1018
SAM_K4D263238A_GC40_FBGA_144P
N5 A0
A1
N6
A10
L6
M7 A11
A2
M6
N7 A3
A4
N8
M9 A5
N9 A6
R1302 22_5% 12
34-
34-
34-
34-
0.1UF_16VC150
12
C1347
0.1UF_16V
1
2
34-
33-
31-
31-
C123 0.1UF_16V
12
31-
34-
POWERPAD_2
PAD1001
31-,34-
31-,34-
2
0.1UF_16VC124
12
31-
34-
34-
34-
12
31-
34-
34-
34-
C145 0.1UF_16V
1
+V1.8S
PAD1002
POWERPAD_2
0.1UF_16VC152
34-
34-
34-
34-
31-,34-
34-
+V2.5S
+V2.5S
+VRAM_VCC
12
31-
31-,34-
2
10UF_K_6.3V
C13431
2
0.1UF_16VC121
34-
34-
34-
34-
31-
C1346
10UF_K_6.3V
1
12
34-
34-
34-
34-
31-
33-
C147 0.1UF_16V
22_5%R1297
12
31-,34-
C139 0.1UF_16V
12
12
31-
22_5%R1307 12
12
34-
31-
R1292 22_5%
DDR_CSB1#_R
0.1UF_16VC148
12
C122 0.1UF_16V
GDQMB_R(2)
GDQMB_R(1)
GDQMB_R(0)
QSB0_R
QSB3_R
QSB1_R
QSB2_R
QSB0_R
QSB3_R
QSB1_R
QSB2_R
QSB5_R
QSB4_R
QSB6_R
QSB7_R
QSB5_R
QSB4_R
GDQMB_R(3)
GDQMB_R(0)
GDQMB_R(1)
GDQMB_R(2)
GDQMB_R(3)
GDQMB_R(5)
GDQMB_R(7)
GDQMB_R(7)
GDQMB(6)
GDQMB(5)
GDQMB(4)
GDQMB_R(6)
GDQMB_R(5)
GDQMB_R(4)
QSB6_R
QSB7_R
GMDB_R(11)
GMDB_R(12)
GMDB_R(7)
GMDB_R(2)
GMDB_R(3)
GMDB_R(4)
GMDB_R(5)
GMDB_R(6)
GDQMB_R(6)
GMDB_R(15)
GMDB_R(16)
GMDB_R(17)
GMDB_R(18)
GMDB_R(13)
GMDB_R(8)
GMDB_R(9)
GMDB_R(10)
GMDB_R(38)
GMDB_R(25)
GMDB_R(20)
GMDB_R(21)
GMDB_R(22)
GMDB_R(23)
GMDB_R(24)
GMDB_R(19)
GMDB_R(14)
GMDB_R(40)
GMDB_R(41)
GMDB_R(42)
GMDB_R(43)
GMDB_R(34)
GMDB_R(35)
GMDB_R(36)
GMDB_R(37)
GMDB_R(52)
GMDB_R(53)
GMDB_R(44)
GMDB_R(45)
GMDB_R(46)
GMDB_R(47)
GMDB_R(48)
GMDB_R(39)
GMDB_R(54)
GMDB_R(55)
GMDB_R(56)
GMDB_R(57)
GMDB_R(58)
GMDB_R(49)
GMDB_R(50)
GMDB_R(51)
QSB5
QSB0
QSB1
QSB2
DIMB_0 DIMB_1
GMDB_R(30)
GMDB_R(1)
GMDB_R(0)
GDQMB(7)
GDQMB_R(4)
QSB6
QSB7
GMDB_R(33)
GMDB_R(59)
GMDB_R(61)
GMDB_R(62)
GMDB_R(31)
GMDB_R(26)
GMDB_R(27)
GMDB_R(28)
GMDB_R(29)
DDR_CASB#_R
DDR_WEB#_R
DDR_CLKB1_R
DDR_CKEB_R
QSB4
GMDB_R(63:32)
GMDB_R(32)
GMDB_R(60)
GMDB_R(63)
GMAB_R(6)
GMAB_R(7)
GMAB_R(8)
GMAB_R(13)
GMAB_R(11)
GMAB_R(10)
GMAB_R(12)
GMAB_R(9)
DDR_CSB1#_R
DDR_CLKB1#_R
DDR_CSB0#_R
DDR_RASB#_R
GDQMB(1)
GDQMB(2)
DDR_CLKB0_R
DDR_CKEB_R
QSB3
GMDB_R(31:0)
GMAB_R(13:0)
GMAB_R(0)
GMAB_R(1)
GMAB_R(2)
GMAB_R(3)
GMAB_R(4)
GMAB_R(5)
GMAB_R(8)
GMAB_R(13)
GMAB_R(11)
GMAB_R(10)
GMAB_R(12)
GMAB_R(9)
DDR_CLKB0#_R
DDR_CSB0#_R
DDR_RASB#_R
DDR_CASB#_R
DDR_WEB#_R
GDQMB(3)
GDQMB(0)
GMAB_R(13:0)
GMAB_R(0)
GMAB_R(1)
GMAB_R(2)
GMAB_R(3)
GMAB_R(4)
GMAB_R(5)
GMAB_R(6)
GMAB_R(7)
![](asset-23.png)
Sheet
VER
Size
SVIDEO CN
(10/5)
QA CHK
INVENTEC
(10/5)
Changed by Time Changed of
(10/5)
TITLE
Date Changed
(10/5)
R&D CHK
Engineer
Drawn by
Model Number
DOC CTRL CHK
MFG ENGR CHK
2
3
1
EE2 Friday, August 1, 2003 1:31:54 pm
David Du
David Du
A02 PC8803 35 67
DIAMOND
CRT& SVEDIO CONN
A3
1GND
GND
25
G
G6
C
4
3Y
BAV99 D1023
30-
126_VCC
57-
R155
75_1%
1
2
SIN_2MJ_1572_005
CN6
1
2
+V3S
+V3
+V3
57-
30-
57-,30-
57-
30-
10K_5%
1
2
30-
2.2K_5%
R139
82PF
C157
1
2
USBVCC1
R151
C6021
OPEN
1
2
OPEN
C6022
1
2
21
OPEN
C6020
1
2
1
2
0R6039
12
D2 1N4148
2
57-
57-
57-
+V3
C153
82PF
L12
LS_1MH_1.8U
12
82PF
C156
1
1
2
57-,30- LS_1MH_1.8U
L10
12
1
2
126_VCC
0
R6037
12
75_1%
R167
4
5
5
6
6
77
88
9
9
2.2K_5%
R140
12
13
13 14
14
15 15
G16
G17
22
33
4
1
CN5
SYN_7519S_15G2
11
10
10 11
11
12
C154
82PF
1
2
D1022BAV99
2
3
R152
10K_5%
1
2
R6038 0
12
0.1UF_16V
1
2
0.1UF_16V
C114
1
2
57-
USBVCC1
0.1UF_16V
C119
1
2
C1341
0.1UF_16V
1
2
C113
14
VCC3
1
VCC4
VIDEO1
3
4VIDEO2
5VIDEO3
C115
10UF_10V
1
2
SD2 24
SYNC_IN1
19
21 SYNC_IN2
SYNC_OUT1 20
22
SYNC_OUT2
8TERM1
TERM2
9
TERM3
10
VBIAS 13
VCC1 2
12
VCC2
U1017
CMD_VGA200_QSOP_24P
7AGND
DDC_IN1
16
17 DDC_IN2
DDC_OUT1 15
18
DDC_OUT2
DGND
6
PWRUP 11
23
SD1
DDCDATA
DDCCLK
R_CRT
B_CRT
G_CRT
DOCK_DDCDATA
DOCK_HSYNC
VSYNC
DOCK_VSYNC
CHROMA_C
LUMA_Y
HSYNC
DOCK_DDCCLK
![](asset-24.png)
Sheet
TITLE
Changed by
(20/5)
Drawn by
R&D CHK
Engineer
QA CHK VER
(20/5)
(20/5)
DOC CTRL CHK
MFG ENGR CHK
Model NumberDate Changed Time Changed of
Size
EE2 Thursday, July 31, 2003 10:55:39 am
David Du
David Du
A02 PC8803 36 67
DIAMOND
LCD CONN
A3
INVENTEC
USED M9+X OPEN R1403 , USED M10 OPEN R1396 , Q1051
Place as passible as close to connector
1
2
3
45
6
7
8
29-
BLM41P800S
L1028
12
29-
RS1055
OPEN
1G1
G2
3
S15
2
S2
R1401
100_5%
12
0.1UF_16V
C1401
1
2
Q1049
NDC7002N
6
D1
D2 4
1
2
29-
29-
100_5%
R1402
1
2
29-
+V3S
29-
R1416
4.7K_5%
1
2
29-
C1397
0.1UF_16V
D
3
G
2
1
S
29-
30-
OPEN
R1396
1
2
+V3S
G
5
56
6
77
88
9
9
Q1051
2N7002_OPEN
35
36 36
37
37 38
38
39 39
44
40 40
41
G42
28
29
29
33
30
30 31
31
32 32
33
33 34
34
35
20
21 21
22 22
23 23
24 24
25
25 26
26
27 27
28
13 14
14
15 15
16 16
17
17 18
18
19 19
22
20
12
CN2
IPEX_20265_040E
11
10
10 11
11 12
12 13
29-
1000PF_0402
C1395
1
2
29-
R1403
0_5%
OPEN
R1417
12
C1416
10UF_K_6.3V
1
2
Q1050
FDR840P
D
1
2
3
6
7
G
4
8
S
5
29-
+V3S
29-
+V5
29-
29-
0_5%
R1414
1
2
29-
100_5%
R1395
12
29-
0.1UF_16VC1417
12
29-
29-
4.7K_5%
R1415
1
2
+V3S
0.1UF_16V
C1400
1
2
29-
100UF_10V
C1396
1
29-
30-
29-
47K_5%
R1400
1
2
0.01UF_16V
C1399
1
2
29-
29-
DIGON
BLON#
TXOUTU1-
LCM_DDCCLK
LCM_ID4
INV_PWM_3
TXOUTL2-
TXOUTL2+
TXCLKOUTL-
TXOUTL1-
LCM_DDCDATA
TXCLKOUTL+
TXOUTU2+
TXCLKOUTU+
TXCLKOUTU-
TXOUTL0+
TXOUTL0-
TXOUTL1+
LCM_ID3
LCM_ID0
LCM_ID1
LCM_ID2
TXOUTU0+
TXOUTU0-
TXOUTU1+
TXOUTU2-
![](asset-25.png)
PCI
I/F
CPU I/F
HUBLINK
I/F
Interrupt
I/F
EEPROM
I/F
LAN
I/F
System
Management
I/F
HUB4/8
HUB4/8
HUB4/8
HUBST5/10/15-4/8/12
HUBST5/10/15-4/8/12
HUB4/8
HUB4/8
POWER15/5
POWER15/5
POWER15/5
POWER15/5
POWER15/5
POWER15/5
GTL4/8
POWER15/5
POWER15/5
POWER15/5CLK4/16
CLK4/16
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
GTL4/8
HUB4/8
HUB4/8
HUB4/8
HUB4/8
HUB4/8
HUB4/8
MFG ENGR CHK
QA CHK Model Number Sheet
VER
C179 , C158 , R222
Drawn by
10:55:45 amThursday, July 31, 2003EE2
6737
PC8803A02
ICH4-1
DIAMOND
A3
R&D CHK
INVENTEC
LAYOUT NOTES :
CLOSE TO ICH4
Time Changed
DOC CTRL CHK
Engineer
of
Size
TITLE
HUB_VREF_ICH
Changed by Date Changed
R1749 ,
PCI_TRDY#
F2
SMB_CLK AC4
AB4
SMB_DATA
SMLINK0 AC3
SMLINK1 AB1
W6
SM_INTRUDER#
51-,37-
David Du
David Du
PCI_PAR
G1 PCI_PERR#
L4
PCI_PME#
W2
PCI_REQ#0
B1
A2 PCI_REQ#1
PCI_REQ#2
B3
C7 PCI_REQ#3
B6 PCI_REQ#4
PCI_RST#
U5
K5 PCI_SERR#
F3 PCI_STOP#
PCI_CLK
P5
M3 PCI_DEVSEL#
F1 PCI_FRAME#
C1 PCI_GNT#0
E6 PCI_GNT#1
PCI_GNT#2
A7
B7 PCI_GNT#3
PCI_GNT#4
D6
L5 PCI_IRDY#
M2 PCI_LOCK#
PCI_AD28
D3
R1 PCI_AD29
K1 PCI_AD3
D2 PCI_AD30
PCI_AD31
P4
PCI_AD4
G5
J4 PCI_AD5
H4 PCI_AD6
PCI_AD7
J5 PCI_AD8
K2
G2 PCI_AD9
E5 PCI_AD19
N2
PCI_AD2
H3
E3 PCI_AD20
PCI_AD21
N3 PCI_AD22
E4
M5 PCI_AD23
E2 PCI_AD24
PCI_AD25
P1 PCI_AD26
E1
P2 PCI_AD27
H5 PCI_AD0
PCI_AD1
J3
L1 PCI_AD10
PCI_AD11
G4
L2 PCI_AD12
PCI_AD13
H2
PCI_AD14
L3
F5 PCI_AD15
F4 PCI_AD16
N1 PCI_AD17
PCI_AD18
LAN_RST# Y5
B11
LAN_RSTSYNC
LAN_RXD0 A10
A9
LAN_RXD1 A11
LAN_RXD2
LAN_TXD0 B10
LAN_TXD1 C10
A12
LAN_TXD2
PCI_C/BE#2
M4 PCI_C/BE#3
N4
INT_IRQ14 AC13
AA19
INT_IRQ15
D5
INT_PIRQA#
INT_PIRQB# C2
INT_PIRQC# B4
INT_PIRQD# A3
INT_SERIRQ J22
PCI_C/BE#0
J2 PCI_C/BE#1
K4
C11
LAN_JCLK
HUB_PD7
HUB_PD8 P23
HUB_PD9 L22
HUB_PSTRB P21
N20
HUB_PSTRB#
R23
HUB_RCOMP
HUB_VREF M23
R22
HUB_VSWING
INT_APICCLK J19
INT_APICD0 H19
K20
INT_APICD1
T21
HUB_CLK
L19
HUB_PD0
HUB_PD1 L20
N22
HUB_PD10
HUB_PD11 K21
M19
HUB_PD2 M21
HUB_PD3
HUB_PD4 P19
HUB_PD5 R19
T20
HUB_PD6 R20
CPU_RCIN#
CPU_SLP# U21
W23
CPU_SMI#
CPU_STPCLK# V23
INT_PIRQF#/GPIO3 D7
PCI_GPIO16/GNTA#
E8 D10
EER_CS D11
EER_DIN
EER_DOUT A8
C12
EER_SHCLK
CPU_A20M# AB23
CPU_DPSLP# U23
AA21
CPU_FERR# W21
CPU_IGNNE# V22
CPU_INIT#
CPU_INTR AB22
V21
CPU_NMI Y23
CPU_PWRGOOD U22
A6
SMB_ALERT#/GPIO11 AA5
PCI_GPIO0/REQA#
B5
INT_PIRQG#/GPIO4 C3
INT_PIRQH#/GPIO5 C4
PCI_GPIO17/GNTB#/GNT5#
C5
INT_PIRQE#/GPIO2 C8
Y22
CPU_A20GATE
12+V3A
R113
8.2K_5%
12
ITL_ICH4_M_BGA_421P
U1037
PCI_GPIO1/REQB#/REQ5#
12
55-,54-,51-,37-
8.2K_5%
R81
12
R73
8.2K_5%
37-
+VCCP
54-,37-
55-,54-,51-,37-
55-,54-,51-,37-
R94
8.2K_5%
28.2K_5%
R70
12
40-,37-
+V3S
55-,54-,51-,37-
26-,25-,20-,15-
59-,51-,42-,40-,37-
48-,37-
54-,37-
51-,37-
37-
8.2K_5%
R76
1
R60
8.2K_5%
12
8.2K_5%
R1397
12
40-
21-,17-
37-
R1431
2.2K_1%
12
37-
12
37-
48-,37-
R40
1K_1%
1
2
+V3S
2N7002
Q1055
3
D
2
G
S
1
51-,37-
+V3S
R37
2.2K_1%
26-,25-,20-,15-,37-
8.2K_5%
R92
12
R1386
36.5_1%
1
2
55-,37-
17-
16-
51-,37-
+V5S
29-,37-
37-
8.2K_5%
R53
12
R1119
56_5%
1
2
2
R98 10K_5%
1
2
15-
55-,37-
5-,37-
55-,54-,51-,37-
55-,54-,51-,37-
51-,37-
5-,37-
55-,54-,51-
55-
+V1.8S
C1389
0.01UF_16V
1
54-,37-
37-
U1039
FAIR_NC7WZ17_SC70_6P
1
2
5
6
59-,51-,42-,40-,37-
37-
37-
0_5%
R83 1
2
16-
55-,54-,51-,37-
54-,37-
1
2
R71
10K_5%
12
26-,25-,20-,15-
16-
+VS_HUBREF
20-,37-
37-
37-
49-,37-
37-
+VS_HUBVSWING
29-,37-
C1387
0.01UF_16V
R56
12
8.2K_5%
R72
12
26-,25-,20-,15-,37-
55-,37-
2
Q1053
2N7002
D
3
G
2
1
S
+V3S
21-
8.2K_5%
8.2K_5%
R75
12
37-
R91
8.2K_5%
1
12
16-
55-,54-,51-,37-
37-
8.2K_5%
R77
12
54-,37-
16-
54-,37-
55-,37-
C1390
0.01UF_16V
1
2
R49
8.2K_5%
12
150_1%
R1387
1
2
+V3S
12
10K_5%
R1427
1
2
51-,37-
40-,37-
56_5%
R111
U1039
FAIR_NC7WZ17_SC70_6P
3
2
5
4
100K_5%
R41
R51
8.2K_5%
12
37-
+V3S
+V3S
51-,37-
55-,54-,51-,37-
R1390
1
2
37-
R68
8.2K_5%
12
55-,54-,51-,37-
+V3A
1
2
55-,54-,51-,37-
R93
8.2K_5%
12
150_1%
2.2K_1%
R63
12
+V_RTC
37-
37-
R86
10K_5%
55-,54-,51-,37-
16-
54-,51-,55-
8.2K_5%
R74
12
49-,37-
2
+V3S
55-,54-,51-,40-,37-
21-
R1388
150_1%
1
2
40-
37-
R54
8.2K_5%
12
37-
R59
8.2K_5%
1
2
R67
8.2K_5%
12
8.2K_5%
R90
12
2
10K_5%
R39
12
R69
8.2K_5%
1
12
51-,37-
37-
17-
R1356
10K_5%
1
12
R1418
10K_5%
1
2
37-
R1421
33_5%
55-,54-,51-,40-,37-
+V1.8S
16-,5-
+V3A
51-,37-
R85
8.2K_5%
20-,37-
59-,16-
37-
R1428
33_5%
12
51-,37-
2
55-,54-,51-,37-
55-,51-,54-
21-
150_1%
R1389
1
2
+V3S
10K_5%
R84 1
2
37-
55-,54-,51-,37-
C26
0.1UF_16V
1
R48
12
8.2K_5%
R50
12
8.2K_5%
12
8.2K_5%
R1439
12
8.2K_5%
2.2K_1%
R1429
12
8.2K_5%
R47
12
R52
GNT3#_3
DMA_GNTB#_3
DMA_GNTA#_3
THERM_SCI#
IRQ15_3
PIRQF#_3
PIRQG#_3SERIRQ_3
IRQ14_3
55-,48-,29-,21-
15-
59-,54-,51-,42-,40-
CBGNT2#_3
GNT4#_3
MPCIREQ0#_3
NICREQ1#_3
CBREQ2#_3
REQ4#_3
PIRQD#_3
PIRQC#_3
PIRQB#_3
PIRQA#_3
PIRQH#_3
REQ3#_3
ALERT_CLK_3
ALERT_DAT_3
ICH_SMDAT_3
ICH_SMCLK_3
RUNSCI0#_3
INTRUDER#_3
STBY_SWIN#_3
PCI_RESET1#_3
PCI_PME#_3
PIRQG#_3
PCI_FRAME#_3
PCI_IRDY#_3
PCI_TRDY#_3
PCI_STOP#_3 PCI_LOCK#_3
PCI_PERR#_3
PCI_DEVSEL#_3
PCI_SERR#_3
MPCIGNT0#_3
NICGNT1#_3
H_INIT#
NICGNT1#_3
NICREQ1#_3
STBY_SWIN#_3
REQ4#_3
GNT4#_3
PCI_RESET2#_3
PIRQB#_3
PIRQC#_3
PIRQD#_3
PIRQF#_3
PIRQH#_3
SERIRQ_3
IRQ14_3
IRQ15_3
PIRQE#_3
H_FERR_S#
H_PWRGD
H_CPUSLP#
H_SMI#
H_STPCLK#
HUB_PSTRB
HUB_PSTRB#
PIRQA#_3
DMA_GNTB#_3
A20GATE_3
KBCPURST#_3
ALERT_DAT_3
ICH_SMCLK_3
ICH_SMDAT_3
H_DPSLP#
H_IGNNE#
H_INTR
H_NMI
PCI_IRDY#_3
PCI_PAR_3
PCI_PERR#_3
PCI_LOCK#_3
PCI_PME#_3
PCI_SERR#_3
PCI_STOP#_3
PCI_TRDY#_3
DMA_GNTA#_3
ALERT_CLK_3
INTRUDER#_3
CBGNT2#_3
GNT3#_3
CBREQ2#_3
REQ3#_3
CLK_ICHPCI_3R
RUNSCI0#_3
THERM_SCI#
PCI_DEVSEL#_3
PCI_FRAME#_3
HUB_PD(0)
PCI_CBE#(3:0) PCI_CBE#(0)
PCI_CBE#(1)
PCI_CBE#(2)
PCI_CBE#(3)
H_A20M#
CLK_ICHHUB
MPCIGNT0#_3
MPCIREQ0#_3
PCI_AD(0)
HUB_PD(10:0)
HUB_PD(10)
HUB_PD(9)
HUB_PD(8)
HUB_PD(7)
HUB_PD(6)
HUB_PD(5)
HUB_PD(4)
HUB_PD(3)
HUB_PD(2)
HUB_PD(1)
PCI_AD(7)
PCI_AD(6)
PCI_AD(5)
PCI_AD(4)
PCI_AD(3)
PCI_AD(2)
PCI_AD(1)
PCI_AD(16)
PCI_AD(15)
PCI_AD(14)
PCI_AD(13)
PCI_AD(12)
PCI_AD(11)
PCI_AD(10)
PCI_AD(9)
PCI_AD(8)
PCI_AD(23)
PCI_AD(22)
PCI_AD(21)
PCI_AD(20)
PCI_AD(19)
PCI_AD(18)
PCI_AD(17)
PCI_AD(31:0)
PCI_AD(31)
PCI_AD(30)
PCI_AD(29)
PCI_AD(28)
PCI_AD(27)
PCI_AD(26)
PCI_AD(25)
PCI_AD(24)
![](asset-26.png)
LPC
I/F
IDE
I/F
AC’97
I/F
USB
I/F
Misc
Clocks
Unmuxed
GPIO
Power
Management
IST
GPIO
Engineer
TITLE
Date Changed
05h
Changed by
02h Hynix 64MB
01
TBD
Time Changed
$V
Drawn by
Infineon 64MB
15
Samsung 32MB
Hynix 32MB
RTC CIRCUITRY
05
Ch
Model Number
VMEM_CFG(3:0)-Memory type
DOC CTRL CHK
04
Eh
00
Infineon 128MB
Hynix 128MB
07h
03
06h
07
Ah02
TBD
GPIO[34:36,42]
Infineon 32MB
INVENTEC
08
TBD
10
12
09h
TBD
TBD
TBD
Samsung 64MB
06
04h
08h
of
QA CHK VER
14
TBD
Sheet
MFG ENGR CHK
EE2 Thursday, August 21, 2003 11:35:30 am
David Du
David Du
A02 PC8803 38 67
DIAMOND
ICH4-2
A3
VMEM_CFG(3:0)-Memory type
R&D CHK
Samsung 128MB
Size
03h
00h
01h
Fh
Bh
09
Dh
11
GPIO[34:36,42]
13
59-
59-,42-,40-,30-
0.1UF_16V
C6039
1
2
59-,45-
10K_5%
R89 12
45-
42-
45-
49-
OPEN
R82 12
8.2K_5%
R118
12
2
59-,57-,40-
16-
59-,42-,40-
+V5A
48-
57-
15-
57-
1
2
+V3L
R38
8.2K_5%
1
1
2
OPENR139112
R1434
10K_5%
15-,11-
180K_1%
R65
1
2
40-,14-
R112
56_5%
40-
48-
R1430
33_5%
12
RTCBAT
11-
48-
59-,55-,54-,51-,42-,40-
45-
+V3S
R1405
1K_5% 12
47-
OPENR1433 12
0.1UF_16V
C45
1
2
2
C1403
1UF_10V
1
2
59-,42-,40-
+VCCP
30-
19-,16-
59-,42-,40-
49-
58-
49-
R88
10K_5%
1
48-
48-
+V3S
49-
49-
48-
8.2K_5%
R115
12
10M_5%
R1406
12
+V_RTC
12
50-
15-
49-
48-
11-
15-
48-
59-,45-
48-
+V3A
+V5A
49-
15PF_50VC1419
12
0_5%
R1420
12
+V3S
+V5A
+V3S
OPEN R117
12
40-
10K_5%
R87
50-
OPEN R119
12
OPEN
R44
1
2
56_5%
R1139
1
2
22.6_1%
R1398 12
50-
59-,45-
48-
R116 8.2K_5%
12
59-,42-,40-
OPEN
R66
1
2
TP550
57-
57-
+V3S
59-,47-,45-,40-,13-,12-,9-,7-
0_5%
R1432
12
59-
30-
59-
49-
49-
13-
57-,56-,43-
49-
+V3S
48-
+V3A
59-
42-
59-,42-,40-
57-
50-
20-
40-
59-
15PF_50VC1418
12
42-
49-
58-
24
5
R46
100K_5%
1
2
49-
2
R1392 8.2K_5%
12 TC7S04F
U1031
3
W19 PM_STPCPU#/GPIO20
PM_CPUPERF#/GPIO22
Y20
PM_STPPCI#/GPIO18
Y21
+V3S
15-
10K_5%
R6020
1
USB_PP0
C20 USB_PP1
A21
C18 USB_PP2
A19 USB_PP3
USB_PP4
C16
A17 USB_PP5
USB_RBIAS
A23
B23 USB_RBIAS#
V19 PM_VGATE/VRMPWRGD
PM_SLP_S1#/GPIO19
W18
USB_OC1#
A15 USB_OC2#
USB_OC3#
B14
A14 USB_OC4#
D14 USB_OC5#
D20 USB_PN0#
USB_PN1#
B21 USB_PN2#
D18 USB_PN3#
B19
D16 USB_PN4#
USB_PN5#
B17
PM_SUS_CLK
PM_SUS_STAT#_LPCPD#
AB3
PM_SYSRST#
Y3
V1 PM_THRM#
R2 PM_AGPBUSY#/GPIO6
W7
RTCRST#
H23
SPKR
PM_C3_STAT#/GPIO21
T3
THRMTRIP# W20
USB_OC0#
B15
C14
U4
T5 LPC_FRAME#
PM_BATLOW#
AB2
V20 PM_DPRSLPVR
AA1 PM_PWRBTN#
PM_PWROK
AB6 PM_RI#
Y1 PM_RSMRST#
AA6
PM_SLP_S3#
Y4
Y2 PM_SLP_S4#
AA2 PM_SLP_S5#
AA4
IDE_SDIOR#
IDE_SDIOW# AA18
AC19
IDE_SIORDY
GPIO32
J20
J21 PM_GMUXSEL/GPIO23
T2 LPC_AD0
LPC_AD1
R4
T4 LPC_AD2
U2 LPC_AD3
U3 LPC_DRQ0#
LPC_DRQ1#
W16
IDE_SDD2
IDE_SDD3 AC16
IDE_SDD4 W15
IDE_SDD5 AB15
W14
IDE_SDD6
IDE_SDD7 AA14
IDE_SDD8 Y14
IDE_SDD9 AC15
AB19
IDE_SDDACK#
IDE_SDDREQ AB18
Y18
AC21
AB21
IDE_SDCS1#
IDE_SDCS3# AC22
IDE_SDD0 W17
AB17
IDE_SDD1
IDE_SDD10 AA15
IDE_SDD11 Y15
AB16
IDE_SDD12 Y16
IDE_SDD13
IDE_SDD14 AA17
Y17
IDE_SDD15
AA8
IDE_PDD7 AB9
IDE_PDD8
IDE_PDD9 Y9
Y12
IDE_PDDACK#
AA11
IDE_PDDREQ
AC12
IDE_PDIOR#
W12
IDE_PDIOW#
IDE_PIORDY AB12
AA20
IDE_SDA0
IDE_SDA1 AC20
IDE_SDA2
IDE_PDD10 AC9
W9
IDE_PDD11 AB10
IDE_PDD12 W10
IDE_PDD13 W11
IDE_PDD14
IDE_PDD15 Y11
IDE_PDD2 Y10
IDE_PDD3 AA10
AA7
IDE_PDD4
IDE_PDD5 AB8
IDE_PDD6 Y8
H20
GPIO41
H21
GPIO39
H22
IDE_PDA0 AA13
AB13
IDE_PDA1
IDE_PDA2 W13
IDE_PDCS1# Y13
AB14
IDE_PDCS3#
IDE_PDD0 AB11
AC11
IDE_PDD1
G20
GPIO33
G22
GPIO40
G23
GPIO_12 V5
GPIO_13 W3
V2
GPIO_25
GPIO_27 W1
W4
GPIO_28
R3
GPIO_7
GPIO_8 V4
GPIO37 AC7
CLK_RTCX1
CLK_RTCX2 AC6
CLK_VBIAS Y6
GPIO43
E23
GPIO34
F20
GPIO36
F21
GPIO42
F22
GPIO38
F23
GPIO35
AC2 PM_CLKRUN#/GPIO24
B8 AC_BITCLK
AC_RST#
C13 AC_SDATAIN0
D13 AC_SDATAIN1
A13 AC_SDATAIN2
B13 AC_SDATAOUT
D9 AC_SYNC
C9
CLK_14 J23
CLK_48 F19
10K_5%
1
2
10M_5%
R1422
1
2
ITL_ICH4_M_BGA_421P
U1037
12
34
R45
OPEN
1
2
R43
12
3
0.047UF_10V
C1405
1
2
X1004
32.768KHZ
13
R114
OPEN
12
BAT54C
D1026
R139312
C1404
0.1UF_16V
1
2
BAT54
D1
VMEM_CFG3
NPCI_RESET
OPEN
CPUSTOP#_3
PM_DPRSLPVR
SLP_S1#_3R
CLK_ICH14_3R
CLK_ICH48_3R
VCC1_POR#_3
SLP_S5#_3R
SB_VGATE
PDD(2)
PDD(1)
PDD(0)
AGPBUSY#_3
TEMP_WARN#_3
ITP_DBRESET#
PM_THRMTRIP#
PCISTOP#_3
PDD(10)
PDD(9)
PDD(8)
PDD(7)
PDD(6)
PDD(5)
PDD(4)
PDD(3)
SDD(2)
SDD(1)
SDD(0)
PDD(15)
PDD(14)
PDD(13)
PDD(12)
PDD(11)
SDD(10)
SDD(9)
SDD(8)
SDD(7)
SDD(6)
SDD(5)
SDD(4)
SDD(3)
SDATA_OUT_ICH
SDATA_IN1_ICH
CODEC_RST#_ICH
SDD(15)
SDD(14)
SDD(13)
SDD(12)
SDD(11)
SHUTDOWN
FWH_WP#_3
MBAY_DISABLE
LID_SW#_3
MBAY_ATTACHED#
SER_SHD#_3
FWH_TBL#_3
PP_FDD_SMI
FRAME_SYNC_ICH
SDA(2)
SDA(1)
SDA(0)
PDIORDY_35
PDIOR#_3
PDCS3#_3
PDA(2)
PDA(1)
PDA(0)
LPC_AD(1)
LPC_AD(0)
SDIORDY_35
SDIOW#_3
SDIOR#_3
SDDRQ_35
SDDACK#_35
SDCS3#_3
SDCS1#_3
USB_PN3
USB_PN2
USB_PN1
USB_PN0
USB_OC#1
USB_OC#0
PWR_SWIN#_3
LPC_AD(3)
LPC_AD(2)
CLKRUN#_3
PCSPKR_ICH_3
PREP
USB_PP4
USB_PP3
USB_PP2
USB_PP1
USB_PP0
USB_PN4
WAKEUP0#_3
C3_STAT#
LPC_DRQ1#
LPC_DRQ0#
PM_PWROK
PDDRQ_35
PDIOW#_3
LPC_FRAME#_3
LOW_BAT#_3
SLP_S3#_3R
SUS_STAT#_3
USB_PN5
USB_PP5
PDD(15:0)
SDD(15:0)
BITCLK_3_ICH
SDATA_IN0_ICH
VMEM_CFG0
VMEM_CFG2
VMEM_CFG1
PDCS1#_3
PDDACK#_35
![](asset-27.png)
VSS
POWER
Model Number Sheet
TITLE
INVENTEC
Changed by Date Changed Time Changed
Engineer
Drawn by
R&D CHK
DOC CTRL CHK
MFG ENGR CHK
EE2 Thursday, July 31, 2003 10:55:59 am
David Du
David Du
A02 PC8803 39 67
DIAMOND
ICH4-3
A3
of
Size
QA CHK VER
VSS94 V3
VSS95 V15
V17
VSS96
VSS97 W5
VSS98 W8
VSS99 W22
1K_1%
R1408
12
VSS84 P13
VSS85 P20
VSS86 P22
VSS87 R5
VSS88 R18
VSS89 R21
AA16 VSS9
VSS90 T1
VSS91 T19
VSS92 T23
U20
VSS93
N10
VSS74
VSS75 N11
N12
VSS76
VSS77 N13
VSS78 N14
VSS79 N19
AA12 VSS8
VSS80 N21
VSS81 N23
P3
VSS82 P11
VSS83
L14
VSS65 L21
VSS66
VSS67 M1
VSS68 M11
M12
VSS69
VSS7
AA9
VSS70 M13
M20
VSS71
VSS72 M22
VSS73 N5
J6
VSS55
VSS56 K3
VSS57 K11
VSS58 K13
VSS59 K19
VSS6
AA3
VSS60 K23
VSS61 L10
VSS62 L11
L12
VSS63
VSS64 L13
VSS45
VSS46
E19 VSS47
E21 VSS48
E22 VSS49
F8
VSS5
A22
G3 VSS50
VSS51
G6
VSS52 G19
VSS53 G21
VSS54 H1
VSS35
VSS36
D17 VSS37
D19 VSS38
D21
D22 VSS39
VSS4
A20
VSS40
D23
E10 VSS41
E14 VSS42
E16 VSS43
VSS44
E17
E18
C15 VSS26
C17 VSS27
VSS28
C19 VSS29
C21
VSS3
A18
VSS30
C23 VSS31
D1 VSS32
D4 VSS33
D8
D12 VSS34
D15
AC14 VSS17
AC18 VSS18
AC23 VSS19
B9
VSS2
A16
VSS20
B12 VSS21
B16 VSS22
B18 VSS23
B20 VSS24
B22 VSS25
C6
U1037
VSS0
A1 VSS1
A4
VSS10
AA22
Y7
VSS100
VSS101 Y19
VSS11
AB7 VSS12
AB20
AC1 VSS13
VSS14
AC5
AC10 VSS15
VSS16
D1027
13
C58
0.1UF_16V
1
2
ITL_ICH4_M_BGA_421P
1
2
0.1UF_16V
C51 1
2
BAT54
1
2
+V1.5S
1UF_16V
C1422 1
2
C1386
0.1UF_16V
2
0.1UF_16V
C63
1
2
C81
0.1UF_16V
1
2
0.01UF_16V
C77
1
2
C1391
10UF_K_6.3V
1
1
2
D1031
BAT54
1
3
C66
0.1UF_16V
10UF_K_6.3V
1
2
+V3A
+V1.5A +V1.5A_ICH
C60
0.1UF_16V
C62
0.1UF_16V
1
2
C68
0.1UF_16V
1
2
C1421
0.1UF_16V
1
2
10UF_K_6.3V
C1406
1
2
0.1UF_16V
1
2
+V_RTC
0.1UF_16V
C44
1
2
C67
1
2
+V1.5S
C76
0.1UF_16V
1
2
C65
12
+V3S
R1423
1K_1%
12
C78
0.1UF_16V
2
10UF_K_6.3V
C1439
1
2
L1031
BLM21A121S
1
2
C1388
10UF_K_6.3V
1
2
0.1UF_16V
C82
1
1
2
C95
0.1UF_16V
1
2
C1420
0.1UF_16V
1
2
0.1UF_16V
C48
1
2
C1407
1UF_16V
2
+V5L
0.1UF_16V
C57
1
2
C74
0.1UF_16V
2
+V5S_ICHREF
C59
0.1UF_16V
1
2
C50
0.1UF_16V
1
2C79
0.1UF_16V
1
2
0.1UF_16V
C94
1
2
0.1UF_16V
C56
1
2
+V5S
0.1UF_16V
C49
1
VCC_CPU_IO_2
+V3S
0.1UF_16V
C55
1
2
0.1UF_16V
C61
1
F10
F15
VCCSUS3.3_2 F16
VCCSUS3.3_3 F18
VCCSUS3.3_4 K14
VCCSUS3.3_5
VCCSUS3.3_6 V7
VCCSUS3.3_7 V8
V9
VCCSUS3.3_8 F17
VCCSUS3.3_9
P14 VCC_CPU_IO_0
VCC_CPU_IO_1
U18
AA23
VCCRTC AB5
E12 VCCSUS1.5_0
E13 VCCSUS1.5_1
VCCSUS1.5_2
E20 VCCSUS1.5_3
F14 VCCSUS1.5_4
G18 VCCSUS1.5_5
R6
T6 VCCSUS1.5_6
U6 VCCSUS1.5_7
VCCSUS3.3_0 E11
VCCSUS3.3_1
VCC5REF2
V6
VCC5REFSUS1
E15
VCCHI_0
L23 VCCHI_1
M14 VCCHI_2
P18
T22 VCCHI_3
F6 VCCLAN1.5_0
F7 VCCLAN1.5_1
VCCLAN3.3_0
E9 VCCLAN3.3_1
F9
VCCPLL
C22
AC17
VCC3.3_15
H6
VCC3.3_2 H18
VCC3.3_3 J1
VCC3.3_4 J18
VCC3.3_5
VCC3.3_6 K6
VCC3.3_7 M10
P6
VCC3.3_8 P12
VCC3.3_9
VCC5REF1
E7
VCC1.5_4 P10
VCC1.5_5 T18
U19
VCC1.5_6 V14
VCC1.5_7
VCC3.3_0 A5
VCC3.3_1 B2
VCC3.3_10 U1
VCC3.3_11 V10
VCC3.3_12 V16
VCC3.3_13 V18
AC8
VCC3.3_14
2
+V1.5S
+V3A
+V1.8S
U1037
ITL_ICH4_M_BGA_421P
K10
VCC1.5_0 K12
VCC1.5_1
VCC1.5_2 K18
VCC1.5_3 K22
R245
0_5%
12
+VCCP
C244
1UF_16V
1
L1025
12
BLM21A121S
L1027
12
+V3A_ICH
1
2
0.1UF_16V
C46
1
2
+V3S
BLM21B121SD
1
2
0.1UF_16V
C75
1
2
C47
0.1UF_16V
C80
0.1UF_16V
1
2C64
0.1UF_16V
![](asset-28.png)
RTC
General Purpose I/O InterfaceMiscellaneous
SIRQ
Access Bus Interface
Keyboard/Mouse Interface
Power Mgmt
LPC Bus
Model Number
Engineer
INVENTEC
Changed by VER of
Drawn by
R&D CHK Size
Time Changed
EE2 Thursday, July 31, 2003 10:56:09 am
David Du
David Du
A02 PC8803 40 67
DIAMOND
KBC
A3
QA CHK Sheet
DOC CTRL CHK
Date Changed
MFG ENGR CHK
TITLE
FOR FINE-TUNE SEQUENCE TIME
2
BLM21A121S
L1023
12
150K_1%
R279
12
55-,54-,51-,37-
C314 0.1UF_16V
1
2
59-,51-,42-,37-
10UF_K_6.3V
C1409
1
2
59-,41-
37-
300_5%
R1413
1
2
R106
10K_5%
1
2
+V3A
R1410 10K_5%
12
R104
20K_5%
1
2
59-,54-,51-,42-,37-
15-
58-,54-
C1413
0.1UF_16V
1
1
2
59-,40-
55-
59-
6-
59-,42-,38-
37-
+V3A_MSIO
59-,42-,38-,30-
1N4148D1065
21
C85
0.1UF_16V
PWR_LED#_8051TX
49
RESET_OUT#
SER_IRQ
46
TEST_PIN 1
51 VCC0
60
VCC1_PWRGD
52 XOSEL
XTAL1
53 XTAL2
54
40-
+V3A
OUT0 99
OUT10_PWM0 95
93
OUT11_PWM1
OUT1_IRQ8# 100
OUT7_SMI# 98
97
OUT8_KBRST 96
OUT9_PWM2
43 PCI_CLK
56
PGM
PWRGD 61
90
KSO7
KSO8
7KSO9
6
LAD0
35 LAD1
37 LAD2
39
40 LAD3
41 LFRAME#
34 LPCPD#
42 LRESET#
57
MODE
17 KSO1
16
5KSO10
4KSO11
KSO12_OUT8_KBRST
3KSO13_GPIO18
2
15 KSO2
KSO3
14
13 KSO4
KSO5
12
10 KSO6
9
29 KCLK
31 KDAT
25 KSI0
KSI1
24 KSI2
23
22 KSI3
21 KSI4
20 KSI5
KSI6
19 KSI7
18
KSO0
62
GPIO20_PS2CLK 78
80
GPIO21_PS2DAT
GPIO3 63
64
GPIO4_KSO14
GPIO5_KSO15 66
68
GPIO7_PWM3
GPIO8_RXD 69
70
GPIO9_TXD
IMCLK
26 IMDAT
27
EMCLK
EMDAT
33
FDD_LED#_8051RX 89
FWP# 82
GPIO11_AB2A_DATA 71
72
GPIO12_AB2A_CLK
GPIO13_AB2B_DATA 73
74
GPIO14_AB2B_CLK 75
GPIO15_FAN_TACH1
GPIO16_FAN_TACH2 76
GPIO17_A20M 77
GPIO2
87
AB1A_CLK 86
AB1A_DATA
85
AB1B_CLK
AB1B_DATA 84
88
BAT_LED#
CLKRUN#
44
48
CLOCK
91
DMS_LED#
EA# 83
59 EC_SCI#
32
AGND
55
65 GND
67
VCC1
79 GND
GND
8
VCC1 8192 GND VCC1 94
11
50
24MHZ_OUT
28 GND VCC2 30
58
32KHZ_OUT
GND
36 VCC2 38
45 GND
VCC2 47
12
40-
41-,59-
+V3S_MSIO
SMSC_LPC47N250_TQFP_100P
U1033
VCC1
D1030
BAT54
1
3
6-
59-,30-,14-,11-
59-,57-
59-,55-,54-,51-,42-,38-
R103 10K_5%
R101
OPEN
12
15PF
C1411
1
2
59-
57-
OPEN
R107 1 2
2
1K_1%
R139912
41-
+V3S
100K_1%
R1 12
37-
20K_5%
R102
1
1
2
52-,51-
41-
22PF_50V
C315 12
20-
TP574
59-
+V3S
C316
0.1UF_16V
+V3A
0.1UF_16V
C98
1
2
15-
38-,14-
57-,6- +V3A_MSIO
5-
R128
10K_5%
1
2
2
+V3S
+V3A
59-
C83
0.1UF_16V
1
2
C1412
15PF
1
12
C1410
0.1UF_16V
1
2
38-
TP576
TP129
59-,47-,45-,38-,13-,12-,9-,7-
59-,57-,38-
57-
57-
R127
OPEN
1
2
+V_RTC
1K_1%
R108 12
X1003
32.768KHZ
1
23
4
57-,6-
C84
0.1UF_16V
1K_5%
R62
12
5-
57-
OPEN
12
L1029
BLM21A121S
12
TP573
1
2
6-
59-,38-,42-
6-
38-
59-
R100
FAIR_NC7WZ17_SC70_6P
3
2
5
4
C97
0.1UF_16V
2
38-
U1045
FAIR_NC7WZ17_SC70_6P
1
2
5
6U1045
100K_5%
R99 12
6-
+V3A
OPEN
R105
1
R1411
10K_5%
12
6-,5-
6-
C1392
10UF_K_6.3V
1
5
66
G7
G8
36-
C99
0.1UF_16V
1
2
AIRACIN2
MLX_67451_0006
CN1006
1
1
2
2
3
3
44
5
XMIT_OFF#
SUS_STAT#_3
PWRGD
LOW_BAT#_3
PCI_SERR#_3
PWR_LED#_3
AIRACIN#
VOL_DN
VOL_UP
CHGCTRL_3
PM_PWROK
NUM_LED#_3
SLP_S3#_3R
PWR_SWIN#_3
SCL_MAIN
SDA_MAIN
SCL_MBAY
SDA_MBAY
BATSTAT#
SCROLL_LED#_3
THM_MBAY#
A20GATE_3
ACIN#
BATSELB_A#
THM_MAIN#
S_CLK
PWR_GOOD_3
BAT_LED#_3
PWRGD
CLK_KBCPCI_3R
VCC1_POR#_3
CLKRUN#_3
KB_CLK_5
KB_DAT_5
EM_CLK_5
EM_DAT_5
IM_CLK_5
IM_DAT_5
RUNSCI0#_3
FAN_PWM_3
INV_PWM_3
CAPS_LED#_3
NUM_LED#_3
PCI_RESET2#_3
LPC_FRAME#_3
WAKEUP0#_3
SERIRQ_3
CLK_KBC14_3R
SCAN_OUT(4)
SCAN_OUT(5)
SCAN_OUT(6)
SCAN_OUT(7)
SCAN_OUT(8)
SCAN_OUT(9)
SCAN_OUT(10)
SCAN_OUT(11)
LPC_AD(3:0)
LPC_AD(3)
LPC_AD(2)
LPC_AD(1)
LPC_AD(0)
KBCPURST#_3
SCAN_IN(7:0)
SCAN_IN(0)
SCAN_IN(1)
SCAN_IN(2)
SCAN_IN(3)
SCAN_IN(4)
SCAN_IN(5)
SCAN_IN(6)
SCAN_IN(7)
SCAN_OUT(11:0)
SCAN_OUT(0)
SCAN_OUT(1)
SCAN_OUT(2)
SCAN_OUT(3)
![](asset-29.png)
INVENTEC
Size
TITLE
TOUCH PAD
POINT STICK
$V
$V
DIAMOND
A3
(15/5)
Date Changed Time Changed
Engineer
Drawn by
Changed by
MFG ENGR CHK
QA CHK
R&D CHK
DOC CTRL CHK
Sheet of
VER Model Number
41-
41-
41-
40-,41-
David Du
David Du
10:56:18 amThursday, July 31, 2003EE2
6741
PC8803A02
INT.KBC/POINT DEVICES
41-
40-,41-
59-,41-
40-,41-
41-
40-,41-
59-,41-
40-,41-
41-
41-
40-,41-
41-
41-
41-
R230
OPEN
1
2
ROHM_UMP11_SSOP_6P
1
2
34
5
6
40-,41-
41-
40-,41-
4.7K_5%
1
2
4.7K_5%
R1279
1
2
U1029
59-,41-
41-
41-
C173
680PF
1
2
R1278
30
30
44
5
56
6
77
88
9
9
59-,40-,41-
23 23
24 24
25
25 26
26
27 27
28 28
29
29
33
16 16
17
17 18
18
19 19
22
20 20
21 21
22 22
11
10
10 11
11 12
12 13
13 14
14
15 15
4
3
1
27
8
6
5
CN13
MLX_52610_3094_30P
RS1056
4
3
2
18
7
6
5
OPEN
RS1057
34
5
6
41-
40-,41-
41-
40-,41-
41-
OPEN
2
34
5
6
U1027
ROHM_UMP11_SSOP_6P
1
2
1
2
34
5
6
59-,41-
ROHM_UMP11_SSOP_6P
U1028
1
9
41-
41-
+V5S
40-,41-
41-
ROHM_UMP11_SSOP_6P
U1030
G
2
2
3
3
4
4
55
66
7
7
8
8
9
1
1
10 10
11 11
12 12
G13
G14
15
G16
40-
BLM21A121S
L14
12
40-,41-
MLX_52559_1292_12P
CN10
41-
41-
41-
59-,41-
41-
59-,41-
40-,41-
40-
5
6789
41-
41-
+V3A
40-,41-
RS1
47K
4
10
321
59-,40-,41-
41-
OPEN
R212
12
59-,40-
4
4
55
66
7
78
8
9G
41-
41-
41-
+V3A
CN8
MLX_52559_0890_8P
1
1
10 G
2
23
3
KSCAN_IN(0)
KSCAN_IN(2)
SCAN_IN(3)
KSCAN_IN(4)
SCAN_IN(5)
KSCAN_IN(6)
KSCAN_IN(3)
SCAN_IN(2)
KSCAN_IN(1)
SCAN_IN(0)
SCAN_IN(6)
KSCAN_IN(5)
SCAN_IN(4)
KSCAN_IN(13)
SCAN_IN(7)
KSCAN_IN(6)
SCAN_IN(1)
KSCAN_IN(8)
KSCAN_IN(14)
KSCAN_IN(10)
KSCAN_IN(0)
KSCAN_IN(5)
KSCAN_IN(4)
KSCAN_IN(11)
KSCAN_IN(9)
SCAN_IN(5)
SCAN_IN(7)
SCAN_IN(6)
SCAN_IN(7:0)
SCAN_OUT(11:0)
SCAN_OUT(9)
SCAN_OUT(1)
SCAN_OUT(10)
SCAN_OUT(6)
SCAN_OUT(7)
SCAN_OUT(4)
SCAN_OUT(8)
SCAN_OUT(3)
SCAN_OUT(5)
SCAN_OUT(2)
SCAN_OUT(0)
SCAN_OUT(11)
KSCAN_IN(3)
KSCAN_IN(2)
KSCAN_IN(1)
KSCAN_IN(12)
KSCAN_IN(12)
SCAN_IN(5)
SCAN_IN(6)KSCAN_IN(6)
SCAN_IN(2)
KSCAN_IN(3)
KSCAN_IN(14)
IM_CLK_5
+5VS_IM
IM_DAT_5
SCAN_IN(0)
SCAN_IN(4)
SCAN_IN(1)
SCAN_IN(3)
SCAN_IN(2)
KSCAN_IN(9)
KSCAN_IN(1)
SCAN_IN(0)KSCAN_IN(0)
KSCAN_IN(8)
SCAN_IN(1)
KSCAN_IN(11)
KSCAN_IN(2)
KSCAN_IN(10)
SCAN_IN(3)
SCAN_IN(4)
KSCAN_IN(5)
KSCAN_IN(13)
KSCAN_IN(4)
![](asset-2a.png)
INVENTEC
Changed by Time ChangedDate Changed
Drawn by
Engineer
DOC CTRL CHK
R&D CHK
QA CHK
MFG ENGR CHK
Model NumberVER ofSheet
57-,44-
+V3S
49-
David Du
David Du
10:56:25 amThursday, July 31, 2003EE2
6742
PC8803A02
SUPER I/O
DIAMOND
A3
Size
TITLE
8
1
10K_5%R1362 1
2
42-
42-
15-
RS1052
10K
310
9
2
6
54
7
C112
0.1UF_16V
1
2
10K_5%R1364 12
42-
42-
57-,43-
OPEN
R125 12
49-
+V3S
48-
59-,54-,51-,40-,37-
42-
42-
38-
49-,48-,42-
R126
0_5%
1
2
49-
+V3S
42-
+V3S
+V3S
+V3S
10K_5%
1
2
42-
100K_1%
R135
1
2
R123
OPEN
1
2
42-
R1381
2
42-
0.1UF_16V
C1364
1
2
42-
TP537
2
10K_5%
R1394 12
R124
10K_5%
1
R1365 10K_5%
1
2
10K_5%
R122 1
44-,42-
38-
+V3S
59-
R121
47K_5%
12
42-
57-,44-
42-
42-
49-
59-,51-,40-,37-
57-,44-
57-,44-
57-,44-
49-
59-
R1363 10K_5%
1
2
15-
42-
+V3S
59-,55-,54-,51-,40-,38-
310
2
4
8
51
7
6
9
42-
RXD1 84
RXD2 95
SER_IRQ
30
77
SLCT
85
TXD1
96
TXD2
18 VTR
42-
RS1053
10K
15
PCI_CLK
29
68
PD0
PD1 69
PD2 70
71
PD3 72
PD4
PD5 73
PD6 74
75
PD7
PE 78
16
90
NRI1
92
NRI2
NRTS1 87
NRTS2 98
67
NSLCTIN
9NSTEP
83
NSTROBE
14 NTRK0
10 NWDATA
NWGATE
11
NWRTPRT
NERROR 81
12 NHDSEL
13 NINDEX
NINIT 66
17 NIO_PME
25 NLDRQ
NLFRAME
24
NLPCPD
27
NMTR0
3
NPCI_RESET
26
NRDATA
NCTS1
NCTS2 99
NDCD1 91
94
NDCD2
NDIR
8
5NDS0
4NDSKCHG
NDSR1 86
97
NDSR2
NDTR1 89
100
NDTR2
GP47
63
IRMODE_IRRX3
IRRX2 61
62
IRTX2
LAD0
20
21 LAD1
22 LAD2
LAD3
23
80
NACK
82
NALF
28 NCLKRUN
88
GP35
37 GP36
38 GP37
39
40 GP40
GP41
41
42 GP42
43 GP43
GP44
44 GP45
45
46 GP46
47
55
57
GP20
GP21 58
GP22 59
GP23_FDC_PP 64
GP24
6
32 GP30
33 GP31
GP32
34 GP33
35
36 GP34
79
CLOCKI
19
1DRVDEN0
2DRVDEN1
GP10
48 GP11_SYSOPT
49
50 GP12_NIO_SMI
GP13_IRQIN1 51
52
GP14_IRQIN2
54
GP15
GP16 56
GP17
U1026
31 VSS
53
VCC
VSS 60
65
VCC
VSS
7
76
VSS
93
VCC
BUSY
3
4
59
8
7
6
42-
SMSC_LPC47N227_STQFP_100P
C117
0.1UF_16V
1
2
42-
RS1054
10K
110
2
59-,38-,40-
44-,57-
+V3S
49-
49-
49-
49-
49-
43-
49-
42-
42-
42-
42-
+V5S
42-
42-
42-
57-,43-
0.1UF_16V
C96
1
2
57-,43-
42-
43-
42-
43-
42-
+V3S
FDG6301N_SC70_6
Q1045
D1
6
D2
3
2
G1
5
G2
1
S1
S2
4
59-,40-,38-,30-
57-,44-
42-42-
42-
42-
44-,42-
43-
42-
43-
42-
42-
42-
42-
+V3S
49-
49-,48-,42-
49-
+V3S
42-
42-
42-
+V3S
49-
47K_5%
R120
12
42-
42-
+V3S
42-
42-
38-
59-,40-,38-
59-
+V3S
42-
+V3S
57-,44-
57-,44-
+V3S
57-,44-
PP_FDD_SMI
CLK_SIO14_3R
CLK_SIOPCI_3R
SLCT_5
STXD_3
SRXD_3
IR_TX_3
IR_RX_3
GP22
GP22
CLKRUN#_3
LPC_AD(3)
LPC_AD(2)
LPC_AD(1)
LPC_AD(0)
FE_TRK0#_5
STEP#_3
DIR#_3
HDSEL#_3
WDATA#_3
FE_RDATA#_5
PINIT#_5
PE_5
SLCTIN#_5
DRVDEN0_3
FE_INDEX#_5
FE_DSKCHG#_5
FE_WPROT#_5
MTR0#_3
MTR0#_3
DS0#_3
PDATA(7)
PDATA(6)
PDATA(5)
PDATA(4)
PDATA(3)
PDATA(2)
PDATA(1)
PDATA(0)
GP17
GP16
GP16 GP20GP20 GP21
GP21
MB_FDD_IDE#
MB_RESET
PTF
PTF
IR_SD_3
HDD_RESET#
GP15
GP15
GP13_IRQIN1
GP13_IRQIN1
GP14_IRQIN2
GP14_IRQIN2
GP17
GP43
GP44
GP10
GP45
SYSOPT GP46GP47
PCI_RESET2#_3
NPCI_RESET
GP47
GP10
SYSOPT
GP30
GP31
GP32
GP33
GP34
GP35
GP36
GP37
GP31
GP32
GP33
GP34
GP35
GP36
GP37
GP43
GP44
GP45
GP46
BUSY_5
STRB#_5
ALF#_5
WGATE#_3
SUS_STAT#_3
GP30
LPC_AD(3:0)
PDATA(7:0)
LPC_DRQ0#
LPC_FRAME#_3
SCTS_3
SRTS_3
SDSR#_3
SDTR#_3
SDCD#_3
RI#_3
SERIRQ_3
ERROR#_5
ACK#_5
![](asset-2b.png)
Model Number Sheet
DOC CTRL CHK
Engineer
INVENTEC
Time Changed QA CHKChanged by VER
MFG ENGR CHK
TITLE
Date Changed of
Size
Drawn by
R&D CHK
C1127
330PF_50V
1
2
EE2 Thursday, July 31, 2003 10:56:30 am
David Du
David Du
A02 PC8803 43 67
DIAMOND
SERIAL PORT&IR
A3
43-
TP579
R1360
10K_5%
1
2
43-
43-
43-
43-
43-
43-
43-
43-
43-
43-
43-
43-
43-
43-
43-
43-
43-
43-
43-
43-
43-
43-
43-
43-
+V3S
43-
43-
43-
43-
43-
43-
42-,43-
42-,43-
57-57-
57- 57-
+V5S
+V3S
TP578
VCC U1015
FAIR_NC7SZ66P5X_SC70_5P
A
1
2B
GND
3OE 4
VCC 5
42-,43-
42-,43-
42-,43-
A3 14
B0
4
7B1 B2 10
13
B3
BE0
2
5BE1 12
BE2
BE3 15
GND
8
16
PER_PI5C3126Q_QSOP_16P
U1014
NC
1
NC 9
3A0
A1
6A2 11
RS1051
33
4
3
2
18
7
6
5
RS1050
33
4
3
2
18
7
6
5
R5OUT
15
T1IN
14 9
T1OUT
13 T2IN 10
T2OUT
T3IN
12 11
T3OUT
27
V+
3
V-
26
VCC
INVALID# 21
4
R1IN
R1OUT
19
5
R2IN
18 R2OUT
20 R2OUTB
R3IN 6
17 R3OUT
7
R4IN
16 R4OUT
8
R5IN
MAX_3243E_SSOP_28P
U1023
28 C1+
24 C1-
C2+
1
2C2-
FORCEOFF#
22
23 FORCEON
25
GND
G
2
3
4
5
6
7
8
9
NDS7002A
D
3
G
2
1
S
CN17
SYN_7517P_09G2T
1
G
R138
100K_5%
1
2
42-,43-
57-,56-,38-
Q1044
57-
43-
+V5
330PF_50V
C1126
1
2
57-,42-
42-,43-
42-,43-
57-,42-
57-,42-
42-,43-
+V3S
+V5
1
2
C1124
330PF_50V
1
2
+V5S
+V5S
42-,43-
C1103
330PF_50V
1
2
330PF_50V
C1104
1
2
330PF_50V
C1125
C1101
330PF_50V
1
2
330PF_50V
C1102
1
2
0.1UF_16VC116
12
C1361 0.1UF_16V
12
0.1UF_16V
C1362
1
2
0.1UF_16V
C1360
1
2
R4IN
R2IN
T1OUT
T3OUT
T2OUT
+V3S C1359
0.1UF_16V
1
2
T3OUT_R
R4IN_R
T2OUT_R
R2IN_R
R3IN
R1IN
T1OUT
T3OUT
R4IN
T2OUT
R2IN
R1IN_R
R2IN_R
R3IN_R
R4IN_R
R5IN
R3IN
R1IN
SDSR#_3R SDCD#_3R
RI#_3R
R5IN_R
R3IN_R
R1IN_R
T1OUT_R
SCTS_3
SDSR#_3
RI#_3
SDCD#_3
SRXD_3
SRXD_3R
SCTS_3R
R5IN
R5IN_R
T2OUT_R
T1OUT_R
T3OUT_R
STXD_3
SRXD_3
PREP
RI#_3
SDCD#_3
SCTS_3
SDTR#_3
SRTS_3
SDSR#_3
![](asset-2c.png)
(20?5)
Changed by Model Number of
Date Changed Time Changed
Engineer
Drawn by
DOC CTRL CHK
INVENTEC
44
PC8803A02
PARALLER PORT
DIAMOND
A3
TITLE
MFG ENGR CHK
QA CHK VER Sheet
Size
LAYOUT NOTES : PUT THESE CIRCUIT CLOSE TO PARALLER PORT
R&D CHK
(20/5)
57-,42-
100PF_50V C1248
1
2
David Du
David Du
10:56:35 amThursday, July 31, 2003EE2
67
2
57-,42-
57-,42-,44-
42-,44-
C1226
100PF_50V
1
2
57-,42-,44-
57-,42-,44-
EXTFDD_VCC
44-
57-,42-,44-
57-,42-,44-
57-,42-,44-
100PF_50V C1227
1
10_5%
R234
12
44-
100PF_50V C1206
1
2
1
2
44-
100PF_50V C1250
1
2
+V5
E
1
R1196
10K_5%
1
2
47K_5%
R1165
100PF_50V
1
2
44-
57-,42-,44-
44-
DTC124EK
Q9
2B
3
C
8
7
6
57-,42-,44-
100PF_50V C1246
1
2
C1205
RS4
4.7K
410
3
2
1
59
8
7
6
5
44-
C1249
100PF_50V
1
2
4
3
2
1
RS1032
10_5%
4
3
2
1
8
9
44-
10_5%
RS1023
8
7
6
5
RS6
4.7K
410
3
2
1
56
7
10_5%
RS1028
8
7
6
54
3
2
1
57-,42-,44-
1
+V5S
57-,42-,44-
R233
4.7K_5% 12
3
4S
C1296
100PF_50V
1
2
44-
47UF_6.3V_METAL
C229
0.1UF_25V
1
2
Q1018
FDC638P
D1
2
5
6
G
C1224
1
2
57-,42-,44-
57-,42-,44- 44-
+V5
42-,44-
C227
1
2
57-,42-
C1204
100PF_50V
1
2
100PF_50V
1
2
R1174
47K_5%
1
2
100PF_50V C1247
2
18
7
6
5 44-
57-,42-
4.7UF_10V
C1202
2
44-
57-,42-
44-
10_5%
RS1018
4
3
D1010 13
+V5S
57-,42-,44-
100PF_50V C1225
1
27
33
44
5
56
6
77
88
9
9
BAT54
2
20 20
21 21
22 22
23
23 24
24
25 25
G26
G
12 13
13 14
14
15 15
16 16
17
17 18
18
19 19
2
57-,42-,44-
44-
CN9
SYN_7518S_25G2
11
10
10 11
11 12
1
2
100PF_50V C1295
1
2
44- 57-,42-,44-
100PF_50V C1203
1
2
C1297
100PF_50V
100PF_50V
1
2
57-,42-,44-
44-
44-
44-
57-,42-
EXTFDD_VCC
44-
PDATA(7)_R
ACK#_5R
BUSY#_5R
PE_5R
57-,42-,44-
C228
PE_5R
BUSY#_5R
ACK#_5R
STRB#_5R
PTF
STRB#_5R
PDATA(0)_R
PDATA(1)_R
ALF#_5R
ERROR#_5R
PINIT#_5R
PDATA(2)_R
SLCTIN#_5R
SLCT_5R
PDATA(3)_R
PDATA(4)_R
PDATA(5)_R
PDATA(6)_R
PDATA(5)_R
PDATA(4)_R
PDATA(3)_R
PDATA(2)_R
PDATA(1)_R
PDATA(0)_R
SLCTIN#_5R
PINIT#_5R
ERROR#_5R
ALF#_5R
SLCT_5R
ERROR#_5
PINIT#_5
SLCTIN#_5
SLCT_5
PTF
PDATA(7)_R
PDATA(6)_R
PDATA(7:0)
PDATA(0)
PDATA(1)
PDATA(2)
PDATA(4)
PDATA(5)
PDATA(6)
PDATA(7)
PDATA(3)
STRB#_5
ACK#_5
BUSY_5
PE_5
ALF#_5
![](asset-2d.png)
Drawn by
INVENTEC
Changed by Date Changed QA CHKTime Changed
LAYOUT NOTES : R697 MUST BE PLACED ACROSS DIGITAL & ANALOG GROUND
VER
R&D CHK
DOC CTRL CHK
MFG ENGR CHK
TITLE
Engineer
Sheet of
Size
Model Number
47-
EE2 Thursday, July 31, 2003 10:56:41 am
David Du
David Du
A02 PC8803 45 67
DIAMOND
AC97 CODEC
A3
(20/5)
OPEN
R13
12
59-,47- 4.7K_5%
R1441
12
R280
10K_5%
1
2
+V3S
+V3S
1
2
C27
OPEN
1
2
47-
38-
1
2
C18
0.1UF_16V
1
2
R23
4.7K_5%
1
49-
57-
59-,38-
0.1UF_16V
C1459
0.1UF_16V
1
2
C1436 270PF
12
C1460
10UF_10V
1
2
54-
49.9K_1%
R1462
1
2C1462
C1431
12
R21 33_5%
12
54-
0.1UF_16V
C29
OPEN
R16
12
C1434
0.1UF_16V1
2
2.2UF_0805_16V
3
D
2
G
S
1
C10
OPEN
1
2
12
C28 0.1UF_16V
12
2N7002
Q1059
R1438
4.7K_5%
12
49-
59-,38-
15-
0.1UF_16VC16
0.01UF_16V
C1465
1
2
C1438 OPEN
12
143K_1%
R1464
1
2
49-
C1456 2.2UF_0805_16V
12
OPEN
C1435
1
2R1457
2.7K_5%
12
Q1060
2N7002
D
3
G
2
1
S
R281
10K_5%
1
2
270PFC1437 12
1K_1%
R1459
1
2
46-
11 RESET#
8SDATA_IN
5SDATA_OUT
48 SPDIF
SYNC
10
27
VREF
VREFOUT 28
XTL_IN
2
3XTL_OUT
45
46 ID1#
JS0 17
16
JS1
23
LINE_IN_L
24
LINE_IN_R
LINE_OUT_L 35
LINE_OUT_R 36
MIC1 21
37
MONO_OUT
13
PHONE_IN
6
19
CD_GND_REF
CD_L 18
CD_R 20
DVDD1 1
9
DVDD2
DVSS1
4
7DVSS2
EAPD
47
39
HP_OUT_L
41
HP_OUT_R
ID0#
AUX_L 14
AUX_R 15
AVDD1 25
38
AVDD2
AVDD3 43
34 AVDD4
AVSS1
26
40 AVSS2
AVSS3
44
AVSS4
33
BIT_CLK
AD_1981B_TQFP_48P
U1043
NC 12
22
MIC2
42 NC
AFILT1
29
30 AFILT2
AFILT3
31
32 AFILT4
1UF_10V
C1453 12
4.7K_5%
R1437
1
2
59-,38-
47-
46-,45-
46-
+V5
OPEN
R14
12
1K_1%
1
2
4.7K_5%
R1453
12
AUDIO_VCC
0.1UF_16V
C15 12
59-
BLM21A121S
L1036
12
R1460
1
2
0.1UF_16V
C1463
1
2
AUDIO_VCC
0.1UF_16V
C17
1
2
47-
59-,47-,40-,38-,13-,12-,9-,7-
OPEN
C12
51-
0.1UF_16V
C14
1
2
R1455
4.7K_5%
12
OPEN
12
4.7K_5%
R1456
12
38-
R1454
4.7K_5%
12
R17
1K_5%
1
2
R12
OPEN
C11
1
2
1UF_10V
C1433
1
2
1
2
AVDD
C1468
22UF_10V
1
46-,45-
2
57-
+V3S
C1457 OPEN
12
100PF_50V
C1466
1
2
10UF_10V
C1461
1C1458
0.1UF_16V
1
S
2.7K_5%
R1452
12
R1466
0_1206_1/4W
OPEN
R1458
1
2
+V3S
Q1061
2N7002_OPEN
D
3
G
2
1
2
R15
2.2K_5%
12
R11
OPEN
12
C1432 2.2UF_0805_16V
12
57-
38-
R18
4.7K_5%
1
C14671
2
270PF_50VC31 12
AVDD
12
R19 33_5%
12
1UF_10V
C30 270PF_50V
12
C32 0.1UF_16V
12
C1430 1UF_10V
33_5%R20 12
OPEN
R1586
1
2
12
MIC_MIC5205BM5_SOT23_5P
U1044
ADJ 4
3EN
GND
2
1IN 5
OUT
4.7K_5%
1
2
AUDIO_VREF
33_5%R22
2.2UF_0805_16VC1454
12
2.2UF_0805_16VC1455
12
R1440
OPEN
1
2
C1464
22UF_6.3V
1
47-
PHONE_AMP
A_MPCI_IN
PCSPKB_3
PCSPKR_ICH_3
MPCI_PWM
C13
MIC1
HPSENSE
LINEINL
LINEINRMIC2
EAPD
SLP_S3#_3R
PHONE_AMP
A_CD_GND
A_CD_L
A_CD_R
BITCLK_3_ICH
SDATA_IN0_ICH
FRAME_SYNC_ICH
A_LEFT
A_RIGHT
CODEC_RST#_ICH
SDATA_OUT_ICH
ADI48M
AC97_BIT_CLK
HPL
HPR
SPDIF
![](asset-2e.png)
VER Model Number
Size
of
QA CHKChanged by
MFG ENGR CHK
Sheet
R&D CHK
Engineer
Drawn by
Date Changed Time Changed
DOC CTRL CHK
46-
EE2 Friday, August 15, 2003 1:50:14 pm
David Du
David Du
A02 PC8803 46 67
DIAMOND
EQ&MIC JACK
A3
TITLE
INVENTEC
470_5%
1
2
4.7UF_K_6.3V
C14411
2
46-
AUDIO_VCC
46-
12
C1440
470PF_50V
1
2
R25
0.1UF_16V
C3
1
2
AUDIO_VCC
100K_5%
R1426
+
5
-
6
11
4
OUT 7
10K_5%
R28
12
U1
MAX4492AUD
+
12
-
13
11
4
OUT 14
U1
MAX4492AUD
10
-
9
11
4
OUT 8
46-
AUDIO_VCCAUDIO_VREF
MAX4492AUD
+
3
-
2
11
4
OUT 1
U1
MAX4492AUD
+
12 10K_5%
R30
12
46-
U1
0.01UF_16V
C5 1
2
0.22UF_K_10VC40
4700PF
C42
12
C1443
470PF_50V
1
2
C23
0.01UF_16V
1
2
470_5%
R24
1
2
46-
AUDIO_VCC
C6
0.01UF_16V
1
2
R35
100K_5%
12
1
2
R27
3K_5%
12
46-
46-
1
2
R29
100K_5%
12
C4
0.1UF_16V
12
45-
C25 100PF_50V
12
R1443
3.9K_1%
12
BLM21A121S
L1033
12
C21
0.22UF_16V
R34
0_5%
1
2
46-
AUDIO_VREF
AUDIO_VREF
R31
100K_5%
1
2
100K_5%
R32
12
2
45-
C7
OPEN
1
2
C19
1UF_10V
1
2
C6043
100PF_50V
1
2
C8
OPEN
1
3G
4G
C6041
OPEN
1
2
100PF_50V
C6042
OPEN
C24
12
JST_BM2B_SRSS
CN3
11
22
1
2
3
4
5
6
7
8
46-
C41 4700PF
12
JA9033L_1F0
JACK1
R33
10K_5%
1
2
45-
3K_5%
R26
12
100PF_50VC1423
12
C22 680PF_50V
12
C1442
4.7UF_K_6.3V
1
2
AUDIO_VCC
AUDIO_VCC
3.92K_1%
R1442
1
2
C43 0.22UF_K_10V
12
L1034
BLM21A121S
12
AUDIO_VREF
OPEN
R36
12
59-,54-
MIC1
MIC2
EXT_MIC2
INT_MIC
INT_MIC_CN
PHONE_AMP
PHONE
EXT_MIC1
INT_MIC_SW
INT_MIC
INT_MIC_CN
INT_MIC_SW
EXT_MIC1
JACKGND
EXT_MIC2
![](asset-2f.png)
LAYOUT NOTES : C1568 C1973 C1565 CLOSE TO PIN 6
QA CHK VER
LACATE IN AUDIO LACATE AT JACK
INTERNAL SPEAKER
Sheet
Model Number of
Date Changed
EARPHONE
(LEFT)
MFG ENGR CHK
Time Changed
R&D CHK
DOC CTRL CHK
(RIGHT)
Engineer
Changed by
LAYOUT NOTES : C1971 C1972 C1566 CLOSE T0 PIN 15
Size
Drawn by
12
EE2 Wednesday, August 13, 2003 10:34:34 pm
David Du
David Du
A02 PC8803 47 67
DIAMOND
AUDIO AMP & HP JACK
A3
TITLE
INVENTEC
NDC7002N
Q1056
D1 6
4
D2
G1
1
3G2
5
S1
S2 2
C1427
1UF_16V
OPEN
R1446
12
R1447 0_5%
12
59-,45-,40-,38-,13-,12-,9-,7-
1
2
L1035
BLM11A121S
12
57-
45-
12
C37
100PF_50V
1
2
1K_1%
R3
16
VDD
C1429
150UF_10V
1
R1461
100K_5%
3
LIN+
9LIN-
5
4
LOUT+
LOUT- 8
12 NC
RIN+
7RIN-
17
18
ROUT+
14
ROUT-
SHUTDOWN#
19
1
GND
GND 11
13
GND
15
PVDD
GND 20
PVDD 6
10 BYPASS
2GAIN0
GAIN1
12
C6019
1UF_10V
12
TI_TPA6017A2_PWP_20P
U1042
1
2
1UF_10VC6017
12
C6018 1UF_10V
1
2
45-
C2
470PF_50V
1
2
C1448
0.1UF_16V
10UF_K_6.3V
C142612
45-
+V5
470PF_50V
C1445
47-
1000PF_0402
C1449
1
2
24
5
57-
OPEN
R1451
12
0_5%
R1450
12
AUDIO_VCC
TC7S08F
U1040
3
1
100PF_50V
1
2
C1428
0.47UF_10V
1
2
45-
+V3A
100PF_50V
C36 1
2
0.01UF_16V
C6040
12
C34
59-,45-
57-
AUDIO_VCC
0.47UF_10V
C1425 1
2
1
2
100K_5%
R57
1
2
47-
AUDIO_VCC
+V3A
100K_5%
R58
12C33
OPEN
5
R10
OPEN
12
0_5%
R9
12
C1424
1
TC7S02F
U1041
3
1
2
4
R1445
33
12
33
R2
12
150UF_10V
2
100PF_50V
C35
1
2
47-
47-
12
150UF_10V
C1446
1
C1452
0.047UF_16V
1
12
+V5
0_5%
R1449
12
BLM11A121S
L1
2
47-
R1448
OPEN
12
OPEN
R1463
2
C1
150UF_10V
1
47-
C1451
4.7UF_K_6.3V
11
2
38-
+V5
47-
45-
0_5%
R1465
1
4
4
47-
C9 0.047UF_16V
12
4.7UF_K_6.3V
C1447
6
7
8
MLX_53398_0490
CN1005
1
12
23
3
2
JACK2
JA9033L_1F0
1
2
3
4
5
2
0.1UF_16V
C1450
1
2
R55
100K_5%
1
PR_HPSENSE#
R1444
1K_1%
1
HPSENSE
SPK_OUT_L-
SPK_OUT_R+
SPK_OUT_L-
SPK_OUT_R+
SPK_OUT_R-
SHUTDOWN
EAPD
SPK_OUT_R-
A_LEFT
A_RIGHT
SPK_OUT_L+
JACKGND
PR_AOUTR
PR_AOUTL
HPL
HPR
SPK_OUT_L+
SLP_S3#_3R
![](asset-30.png)
VER
R&D CHK
LAYOUT NOTES : THE WIDTH NEED 20 MILS
MFG ENGR CHK
QA CHK
TITLE
INVENTEC
Model NumberChanged by
Drawn by
DOC CTRL CHK
Date Changed Time Changed
Engineer
David Du
David Du
10:57:01 amThursday, July 31, 2003EE2
6748
PC8803A02
HDD CONN
DIAMOND
A3
of
Size
(20/5)
Sheet
180PF_50V
C6029
1
2
38-
47K_5%
1
2
C6028
180PF_50V
1
2
38-
38-
0.1UF_16V
C1327
1
2
R1587
C1333
0.1UF_16V
1
2
+V5S
33_5%
R146
1
2
R1291
47K_5%
1
2
59-
59-,48-
55-,37-,29-,21-
38-
38-
37-
+V5S
U1016
TC7S08F
3
1
24
5
49-
38-
42
43
43
44 44
5
56
6
77
88
9
9
35
36 36
37
37 38
38
39 39
44
40 40
41
41
42
28
29
29
33
30
30 31
31 32
32 33
33 34
34
35
20
21 21
22 22
23 23
24 24
25
25 26
26
27 27
28
13
13 14
14
15 15
16 16
17
17 18
18
19 19
22
20
38-
SYN_200227MB044S414ZA_44P
CN7
11
10
10 11
11 12
12
3
1
2
4
5
4.7K_5%
R165
12
1
2
59-,48-
+V5S
+V5S
38-
TC7S08F
U1025
+V3S
R166 470_5%
12
1000PF_0402
C1332
49-,42-
42-
+V3S
38-
PDD(10)
PDD(4)
HDDASP#_5
MTR0#_3
PDCS1#_3
PDCS3#_3
IRQ14_3
PDA(1)
PDA(0)
PDA(2)
HDDASP#_5
PDD(8)
PDD(6)
PDD(9)
PDD(5)
PDD(15)
PDDRQ_35
PDIOW#_3
PDIOR#_3
PDIORDY_35
PDDACK#_35
PDD(7)
PDD(11)
PDD(3)
PDD(12)
PDD(2)
PDD(13)
PDD(1)
PDD(14)
PDD(0)
PDD(15:0)
PCI_RESET1#_3
PDA(2:0)
MBDASP#_5 MBLED#_3
HDD_RESET#
![](asset-31.png)
Sheet
INVENTEC
Changed by Date Changed Time Changed QA CHK of
Model Number
Size
LAYOUT NOTES :
DOC CTRL CHK
(20/5)
MFG ENGR CHK
David Du
David Du
A02 PC8803 49 67
DIAMOND
MULTIBAY CONN
A3
(20/5)
R&D CHK
(20/5)
Drawn by
Engineer
(20/5)
TITLE
VER
2
38-
42-
45-
38-
EE2 Thursday, July 31, 2003 10:57:06 am
12
R215
470K_5%
1
1
2
36
7
8
5
R136
330_5%
2
48-
+V3S
42-,49-
42-,49-
1K
RS2
4
32-,13-
BAT54C
D1020
12
3
10K_5%
R1280
1
NDS7002A
Q1027
3
D
2
G
S
1
38-
C183
22UF_10V
1
+V5A
38-,49-
G69
SD5
7
70 G
SD10
8
SD4
9
45-
61 WGATE#
62 TRK0# GND 63
64 WRPRO#
GND 65
66 RDATA
67
GND
68 HDSEL#
54 MOTORON#
55 DEN0
56 DIR
57 STEP#
MPBID2
58
59 WDATA
SD9
6
GND 60
47
ROUT
48 INDEX#
VCC 49
SD6
5
50 DS0#
51 DCHANGE#
MPBID0 52
53 MID0
SD8
4
40
GND
VCC_LOGIC 41
VCC_MOTOR 42
43
GND
44
LOUT 45
LRTN 46
RRTN
NC
32
SA1
33
PDIAG# 34
SA0
35
SA2
36
CS0# 37
CS1# 38
DASP# 39
IOR# 25
GND 26
IORDY 27
CSEL 28
DMACK 29
SD7
3
30
GND
IRQ 31
SD15
18
GND 19
GND 2
MPBID1
20
DMARQ 21
GND 22
IOW# 23
GND 24
SD11
10
SD3
11
SD12
12
SD2
13
SD13
14
SD1
15
SD14
16
SD0
17
1
2
42-,49-
+V5S_MB
+V5A
CN11
MLX_SD_87537_6873_68P
RST# 1
100K_5%
R1240
1
2
C184
0.047UF_16V
1
+V5S
+V5S_MB
220K_5%
R199
12
R200
12
45-
NDS7002A
Q5 3
D
2
G
S
38-
R197
100_5%
1
2
42-
38-
42-
4.7K_5%
49-
0.1UF_16V
C1314
1
2
38-
1
2
5
6
G
3
4S
33_5%
R1238
12
G2
5
S1 1
4
S2
42-,49-
38-
42-
42-,49-
Q4
FDC638P
D
47K_5%
1
2
Q8
FDG6301N
6
D1
D2 3
2G1
12
NDS7002A
Q1026
3
D
2
G
S
1
42-
37-
R198
U1013
FAIR_NC7WZ17_SC70_6P
3
2
5
4
+V5S
R1237
1K_5%
10K_5%
R1239
1
2
49-
38-,49-
12
3
4
10UF_K_6.3V
C1313
1
2
0.1UF_16V
C1285
1
2
38-,49-
+V5S
+V3A
L1006
NFM41R11C223
48-,42-
42-,49-
42-,49-
6
10K_5%
R42
1
2
38-,49-
42-
42-
U1013
FAIR_NC7WZ17_SC70_6P
1
2
5
42-,49-
42-,49-
42-
0.1UF_16V
C1315
1
2
38-
470_5%
R20112
+V5S_MB
42-,49-
2
0.1UF_16V
C1283
1
2
C1284
0.1UF_16V
1
2
+V5S_MB
C1316
0.1UF_16V
1
MBAY_ATTACHED#
SLP_S3_5R
42- MB_RESET
IRQ15_3
A_CD_L
A_CD_R
A_CD_GND
FE_RDATA#_5
FE_DSKCHG#_5
FE_INDEX#_5
FE_TRK0#_5
FE_WPROT#_5
IRQ15_3R
DRVDEN0_3
DIR#_3
STEP#_3
MBAY_ATTACHED#
WDATA#_3
WGATE#_3
FE_TRK0#_5
FE_WPROT#_5
FE_RDATA#_5
HDSEL#_3
IRQ15_3R
SDIORDY_35
SDIOR#_3
SDIORDY_35
SDDACK#_35
SDCS1#_3
SDCS3#_3
MBDASP#_5
FE_INDEX#_5
DS0#_3
FE_DSKCHG#_5
MTR0#_3
SDD(4)
SDD(3)
SDD(2)
SDD(1)
SDD(0)
MB_FDD_IDE#
SDDRQ_35
SDIOW#_3
SDD(12)
SDD(11)
SDD(10)
SDD(9)
SDD(8)
SDD(7)
SDD(6)
SDD(5)
SDA(2:0) SDA(2)
SDA(1)
SDA(0)
SDD(15:0)
SDD(15)
SDD(14)
SDD(13)
![](asset-32.png)
Date Changed Time Changed
Engineer
of
DOC CTRL CHK
MFG ENGR CHK
QA CHK
(20/5)
Size
TITLE
INVENTEC
(20/5)
(20/5)
EE2 Thursday, July 31, 2003 10:57:19 am
David Du
David Du
A02 PC8803 50 67
DIAMOND
USB&IR CONN
A3
Changed by
Drawn by
(20/5)
R&D CHK
VER Model Number Sheet
C20
150UF_6.3V_S18_METAL
1
150UF_6.3V_S18_METAL
C69
1
GND
ILIM 42 OC#
0.01UF
C1415
1
2MIC_MIC2545A_1BM_SOP_8P
U2
VIN
5VOUT 6
VIN
7VOUT 8
EN
13
2
D+
3
4GND
VCC
5
6D-
7D+
GND
8
GND 9
C39
1
2
CN1
SYN_020122MR008SX20ZU_8P+2G
1VCC 10
GND
D-
1
2
1UF_10V
C38
1
2
0.1UF_16V
VOUT
7VIN 8
VOUT
1EN GND 3
4
ILIMOC#
2
+V5
0.1UF_16V
C1394
38-
C1414
0.01UF
1
2
U3
MIC_MIC2545A_1BM_SOP_8P
5VIN 6
2
3
1
4
38-
38-
38-
+V5
+V5A
DLW21SN900SQ2L
L1032 2
3
1
4
L1030
DLW21SN900SQ2L
R80
76.8_1%
12
1UF_10V
C1393
1
2
+V5A
USBVCC1
USBVCC0
115_1%
R79
12
USB_PN1_B
USB_PP1_B
USB_PN0_B
USB_PP0_B
USB_PN0
USB_PP0
USB_PP1
USB_PN1
![](asset-33.png)
Engineer
Changed by Date Changed Time Changed
R&D CHK
Sheet of
Size
DOC CTRL CHK
NOTS : U2054 WILL BE OZH31B IN THE FEATURE
Drawn by
QA CHK
David Du
David Du
10:57:24 amThursday, July 31, 2003EE2
6751
PC8803A02
CARDBUS CONTROLLER
DIAMOND
A3
MFG ENGR CHK
VER Model Number
TITLE
INVENTEC
12
53-
53-
59-,42-,40-,37-
59-,55-,54-,42-,40-,38-
1
2
R1031 100_5%
12
R1008
0_5%
1
2
10K_5%
R1009
12
10UF_K_6.3V
C1005
55-,54-,37-
0.1UF_16V
C1020
1
2
0.1UF_16V
C1011
52-
52-
10UF_10V
C1026
1
2
55-,54-,37-
52-
52-
52-
52-
52-
53-
C1007
0.1UF_16V
1
2
52-
55-,54-,37-
52-,40-
45-
59-,54-,42-,40-,37-
37-
52-
52-
37-
52-
55-,54-,37-
0.1UF_16V
1
2
52-
52-
52-
53-
52-
C1022
0.1UF_16V
1
2
0.1UF_16V
C1024
1
2
C1030
4
52-
52-
52-
52-
52-
U1003
TI_SN74LVC1G17DBVR_SOT_5P
2
3
5
0.01UF_16V
C1014 1
2
53-
52-
+V3S
37-
52-
52-
C1010
0.1UF_16V
1
2
52-
52-
52-
1
2
C1012
10UF_K_6.3V
1
2
55-,54-,37-
SLATCH_B_VCC_5# K17
SPKR_OUT#
K19
STOP#
L5
L2 TRDY#
GNDV15
W5 GND
ACARDVCC
BCARDVCC
C1031
0.1UF_16V
B4
SC_OC#_SD_DATA3
U16
D3 SC_RST#_SD_CMD
SC_RSVD4_SD_WP#
C4
C16 SC_RSVD8_SD_DATA1
SC_VCC3#_SD_VCC3#
T17
T18 SC_VCC5#
D17 SC_VCC_SD_VCC
K15
SDATA_B_VCC_3#
V16 SD_DATA2
SERR#
M1
E3
L6 PERR#
R10CORE_VCC
A_SKT_VCC R13
R7
A_SKT_VCC
REQ#
G6
RST#
D1
SCLK_A_VCC_5# K14
SC_CLK_SD_CLK
B16
D2 SC_DET#_SD_DET#
SC_IO_SD_DATA0
U4
T3 MS_CLK
MS_DET#
D18
T2 MS_SDIO
MS_VCC
B15 MS_VCC3#
V4
NC
E5
P2 GND
PCI_VCC P5
M2 PAR
PCI_CLK
C5
IRQ7_B_VPP_PGM_EXT_REQ#
E6
IRQ9_A_VPP_VCC_PGM P19
CORE_VCC J18
PCI_VCC J5
GNDK18
K5 GND
LEDO#_SKTA_ACTV
J19
M6PCI_VCC
MS_BS
INTA#
B5
F6 INTB#_IRQ4_A_VPP_PGM
INTC#_LOCK#
V5
IRDY#
L1
F19 IRQ10_B_VPP_VCC_PGM_EXT_GNT#
E8 IRQ11_SKTB_ACTV
B14 IRQ12_PME#
IRQ14_CLKRUN#
A4
V9 IRQ15_RI_OUT#
W12
IRQ3_A_VCC_3#
IRQ5_SERIRQ#
E7
B_SKT_VCC
B_SKT_VCC F13
F2PCI_VCC
FRAME#
K6
G19
B_SKT_VCC
F5 GNT#
N18 GRST#
GNDH3
H5 IDSEL
B_CVS1
B_CVS2 A10
C14
B_R2_A18
B_R2_D14 G17
B_R2_D2 F7
R1 C_BE0#
M3 C_BE1#
C_BE2#
K3
G1 C_BE3#
L3 DEVSEL#
E11 GND
F12
B_CINT#
C12
B_CIRDY#
B_CPAR C15
A15
B_CPERR#
B_CREQ# C9
C10
B_CRST#
A9
B_CSERR#
B_CSTOP# C13
F8
B_CSTSCHG
B_CTRDY# A13
E18
B_CCD1#
B_CCD2# C6
B_CCLK E12
A5
B_CCLKRUN#
G14
B_CC_BE0#
B_CC_BE1# A16
B_CC_BE2# A12
F9
B_CC_BE3#
B13
B_CDEVSEL#
B12
B_CFRAME#
B_CGNT# E13
H18
A6 B_CAD30
B6 B_CAD31
H17 B_CAD4
H14 B_CAD5
H15 B_CAD6
G18 B_CAD7
F17 B_CAD8
F18 B_CAD9
B_CAUDIO C8
B_CBLOCK# A14
J15
F11 B_CAD20
E10 B_CAD21
F10 B_CAD22
B9 B_CAD23
E9 B_CAD24
A8 B_CAD25
B8 B_CAD26
A7 B_CAD27
C7 B_CAD28
B7 B_CAD29
B_CAD3
E19 B_CAD10
G15 B_CAD11
F14 B_CAD12
E17 B_CAD13
F15 B_CAD14
D19 B_CAD15
E14 B_CAD16
A11 B_CAD17
B11 B_CAD18
C11 B_CAD19
H19 B_CAD2
N19
A_CSTSCHG
A_CTRDY# W14
W10
A_CVS1
A_CVS2 W16
P11
A_R2_A18
A_R2_D14 V8
A_R2_D2 L19
B10CORE_VCC
J17 B_CAD0
B_CAD1
J14
A_CDEVSEL#
U14
A_CFRAME#
A_CGNT# R12
P12
A_CINT#
P13
A_CIRDY#
A_CPAR R11
V12
A_CPERR#
A_CREQ# P17
P15
A_CRST#
R18
A_CSERR#
A_CSTOP# W13
A_CAD9
A_CAUDIO M14
A_CBLOCK# U12
V6
A_CCD1#
A_CCD2# L14
A_CCLK V13
L17
A_CCLKRUN#
W8
A_CC_BE0#
A_CC_BE1# V11
A_CC_BE2# V14
N15
A_CC_BE3#
U13
A_CAD28 M15
M18
A_CAD29
U7
A_CAD3
M19
A_CAD30
A_CAD31 L18
A_CAD4 V7
W7
A_CAD5 R8
A_CAD6
A_CAD7 U8
A_CAD8 W9
U9
A_CAD18
A_CAD19 U15
A_CAD2 W6
R14
A_CAD20
A_CAD21 T19
A_CAD22 R17
N14
A_CAD23 R19
A_CAD24
A_CAD25 P18
A_CAD26 N17
M17
A_CAD27
L15
U6
A_CAD0
A_CAD1 P8
R9
A_CAD10
A_CAD11 P9
V10
A_CAD12
A_CAD13 U10
A_CAD14 W11
P10
A_CAD15
A_CAD16 U11
W15
A_CAD17 P14
AD29
F3
W4 AD3
AD30
E2
E1 AD31
T1 AD4
AD5
R3
R2 AD6
AD7
P6
N5 AD8
AD9
P3
AUX_VCC
J3
AD2
R6
AD20
J2
J1 AD21
AD22
H1
H2 AD23
AD24
G2
G3 AD25
H6 AD26
AD27
G5
F1 AD28
P7
U5 AD1
P1 AD10
AD11
N6 AD12
N3
N1 AD13
AD14
N2
M5 AD15
K2 AD16
AD17
K1
J6 AD18
AD19
52-
52-
U2054
O2_OZH31B_MINI_BGA_224P
AD0
52-
52-
53-
10K_5%
R1010 1
2
Q6005
2N7002
D
3
G
2
1
S
+V5S
37-
15-
55-,54-,37-,51-
55-,54-,37-
R1003 20K_5%
12
+V3S
55-,54-,37-,51-
52-
55-,54-,40-,37-
55-,54-,37-
52-
52-
53-
52-
52-
52-
52-
37-
52-
55-,54-,37-
55-,54-,37-
55-,54-,37-
1
2
52-
VCC_SD
52-
52-
C1023
1
2
C1029
0.1UF_16V
1
2
0.1UF_16V
C1025
52-
52-
+V3
52-
0.1UF_16V
+V3
C1009
10UF_10V
1
2
55-,54-,37-
52-
20K_5%
R1004
12
52-
52-
52-
52-
52-
1
2
55-,54-,37-
52-
52-
52-
52-
53-
+V3S
52-
52-
52-
52-
10UF_10V
C1027
53-
52-
52-
52-
PCSPKB_3
S_LATCH
PCI_RESET2#_3
B_CSTSCHG
B_CCBE3#
B_CCBE2#
B_CCBE1#
B_CCBE0#
PCI_CBE#(2)
PCI_CBE#(1)
PCI_CBE#(0)
PCI_AD(22)
GRST# B_CPERR#
B_CSERR#
B_CGNT#
B_CINT#
B_CBLOCK#
B_CCLKRUN#
B_CREQ#
B_CRST#
B_D2
B_A18
B_CVS1
B_CVS2
B_CCD1#
B_D14
B_CCD2#
B_CAUDIO
A_CCD1#
A_D14
A_CCD2#
A_CAUDIO
S_CLK S_DATA
A_CSTSCHG
PCI_CBE#(3)
B_CCLK
B_CFRAME#
B_CTRDY#
B_CDEVSEL#
B_CSTOP#
B_CPAR
B_CIRDY#
A_CDEVSEL#
A_CSTOP#
A_CPAR
A_CIRDY#
A_CPERR#
A_CSERR#
A_CGNT#
A_CINT#
A_CBLOCK#
A_CCLKRUN#
A_CREQ#
A_CRST#
A_D2
A_A18
A_CVS1
A_CVS2
B_CAD(8)
B_CAD(7)
B_CAD(6)
B_CAD(5)
B_CAD(4)
B_CAD(3)
B_CAD(2)
B_CAD(1)
B_CAD(0)
A_CCBE3#
A_CCBE2#
A_CCBE1#
A_CCBE0#
A_CCLK
A_CFRAME#
A_CTRDY#
PCI_AD(3)
PCI_AD(2)
PCI_AD(1)
PCI_AD(0)
B_CAD(31:0)
B_CAD(13)
B_CAD(14)
B_CAD(15)
B_CAD(12)
B_CAD(11)
B_CAD(10)
B_CAD(9)
PCI_AD(11)
PCI_AD(10)
PCI_AD(9)
PCI_AD(8)
PCI_AD(7)
PCI_AD(6)
PCI_AD(5)
PCI_AD(4)
PCI_AD(19)
PCI_AD(18)
PCI_AD(17)
PCI_AD(16)
PCI_AD(15)
PCI_AD(14)
PCI_AD(13)
PCI_AD(12)
PCI_AD(27)
PCI_AD(26)
PCI_AD(25)
PCI_AD(24)
PCI_AD(23)
PCI_AD(22)
PCI_AD(21)
PCI_AD(20)
SD_PWREN#
SD_DAT2
PCI_SERR#_3
PCI_STOP#_3
PCI_TRDY#_3
A_CAD(31:0)
PCI_AD(31:0)
PCI_AD(31)
PCI_AD(30)
PCI_AD(29)
PCI_AD(28)
CLKRUN#_3
SERIRQ_3
PCI_PAR_3
CLK_CBPCI_3R
PCI_PERR#_3
CBREQ2#_3
SD_CLK
SD_CD#
SD_DAT0
SD_DAT3
SD_CMD
SD_WP
SD_DAT1
B_CAD(28)
B_CAD(29)
B_CAD(30)
B_CAD(31)
PCI_DEVSEL#_3
PCI_FRAME#_3
CBGNT2#_3
PIRQC#_3
PIRQD#_3
PIRQG#_3
PCI_IRDY#_3
PCI_PME#_3
A_CAD(8)
A_CAD(9)
B_CAD(16)
B_CAD(17)
B_CAD(18)
B_CAD(19)
B_CAD(20)
B_CAD(21)
B_CAD(22)
B_CAD(23)
B_CAD(24)
B_CAD(25)
B_CAD(26)
B_CAD(27)
A_CAD(21)
A_CAD(22)
A_CAD(23)
A_CAD(24)
A_CAD(25)
A_CAD(26)
A_CAD(27)
A_CAD(28)
A_CAD(29)
A_CAD(3)
A_CAD(30)
A_CAD(31)
A_CAD(4)
A_CAD(5)
A_CAD(6)
A_CAD(7)
A_CAD(0)
A_CAD(1)
A_CAD(10)
A_CAD(11)
A_CAD(12)
A_CAD(13)
A_CAD(14)
A_CAD(15)
A_CAD(16)
A_CAD(17)
A_CAD(18)
A_CAD(19)
A_CAD(2)
A_CAD(20)
![](asset-34.png)
Screw
Ground
Drawn by
TITLE
of
INVENTEC
VER
Engineer
NOTES: U2055 WILL BE OZ2216S IN THE FEATURE
MFG ENGR CHK
DOC CTRL CHK
52 67
DIAMOND
PC CARD SLOT
A3
Time ChangedChanged by
SizeR&D CHK
QA CHK Model Number Sheet
Date Changed
12
51-
51-
51-
51-
EE2 Thursday, July 31, 2003 10:57:30 am
David Du
David Du
A02 PC8803
C1094
0.1UF_16V
1
2
BCARDVPP
R1132
10_5%
R1135
22K_5%
12
51-
51-
51-
+V5
51-
51-
51-,40-
51-,52-
51-
51-,52-
51-
51-
OPEN
R1129
12
12
22K_5%
R1109
12
51-
51-
51-
+V3
C1008
4.7UF_K_25V
1
2
51-
51-
R1110
22K_5%
51-
51-
51-
0.1UF_16V
C289
1
2
51-
51-
51-
4.7UF_K_25V
1
2
51-
51-
51-
BCARDVCC
51-
51-
51-51-
51-
0.1UF_16V
C1098
1
2
C1004
GND8
75
GND9
51-
51-,52-
51-,52-
51-
R1107
22K_5%
12
ACARDVCC
76 GND26
GND27
153
GND28
154 GND29 155
142 GND3
GND30 156
134 GND4
126 GND5
118 GND6
84 GND7
77
GND14
33
GND15
25
GND16
17
GND17
9
GND18
1
GND19
149 GND2
92 GND21
2
GND22
100 GND23
108 GND24
G4
G5
G5
G6 G6
G7
G7
G8 G8
G9
G9
150 GND1 74
GND10
67
GND11
59
GND12
51
GND13
43
G24
G24 G25
G25
G26 G26
G27 G27
G28
G28
G29 G29
G3 G3
G30
G30 G31
G31
G32 G32
G4
G14
G15 G15
G16
G16
G17 G17
G18
G18 G19
G19
G2
G2
G20 G20
G21
G21
G22 G22
G23 G23
B_RFU
39
B_VCC
37
B_VPP1_VPP2
21
B_WAIT#
42
B_WE#
4
B_WP
G1 G1
G10 G10
G11
G11
G12 G12
G13 G13
G14
7
B_D9
19
B_INPACK#
55
B_IORD#
53
B_IOWR#
38
B_NONE
56
B_OE#
40
B_RDY_BSY#
16
B_REG#
23
B_RESET
57
B_RFSH
26
B_D12
66
B_D13
64
B_D14
62
B_D15
6
B_D2
72
B_D3
70
B_D4
68
B_D5
65
B_D6
63
B_D7
10
B_D8
B_A9
12
B_BVD1
14
B_BVD2
73
B_CD1#
3
B_CD2#
61
B_CE1# 60
B_CE2#
11
B_D0
8
B_D1
5
B_D10
71
B_D11
69
35
B_A22
32
B_A23
30
B_A24
28
B_A25
20
B_A3
22
B_A4
24
B_A5
27
B_A6
29
B_A7
49
B_A8
52
B_A12
47
B_A13
45
B_A14
34
B_A15
36
B_A16
50
B_A17
48
B_A18
46
B_A19
18
B_A2
44
B_A20
41
B_A21
A_RFSH
101 A_RFU
114 A_VCC
112 A_VPP1_VPP2
96 A_WAIT#
117 A_WE#
79 A_WP
13
B_A0
15
B_A1
58
B_A10
54
B_A11
31
85 A_D8
82 A_D9
94 A_INPACK#
130 A_IORD#
128 A_IOWR#
113 A_NONE
131 A_OE#
115 A_RDY_BSY#
91 A_REG#
98 A_RESET
132
146 A_D11
144 A_D12
141 A_D13
139 A_D14
137 A_D15
81 A_D2
147 A_D3
145 A_D4
143 A_D5
140 A_D6
138 A_D7
A_A8
127 A_A9
87 A_BVD1
89 A_BVD2
148 A_CD1#
78 A_CD2#
136 A_CE1#
135 A_CE2#
86 A_D0
83 A_D1
80 A_D10
116 A_A21
110 A_A22
107 A_A23
105 A_A24
103 A_A25
95 A_A3
97 A_A4
99 A_A5
102 A_A6
104 A_A7
124
129 A_A11
106 A_A12
122 A_A13
120 A_A14
109 A_A15
111 A_A16
125 A_A17
123 A_A18
121 A_A19
93 A_A2
119 A_A20
OC#
6RESET
14 RESET#
51-
CN18
AMP_C97_25852_EMI
88 A_A0
90 A_A1
133 A_A10
CLOCK
3DATA
12
GND
5LATCH
19 NC
NC_1
13
25
NC_2
NC_3 26
NC_4 27
28
NC_5
29
NC_6
18
25V_2
30 5V_3
9
AVCC_1 10
AVCC_2 11
AVCC_3
8
AVPP
20
BVCC_1 21
BVCC_2 22
BVCC_3 23
BVPP
4
51-
51-
O2_OZ2206_SSOP_30P
U1001
712V_1
24 12V_2
15 3.3V_1
16 3.3V_2
17 3.3V_3
15V_1
51-
+V3
51-
51-
51-
51-
51-,52-
51-
51-
51-
ACARDVPP
BCARDVCC
51-
51-
51-,52-
51-,52-
51-
51-
51-
51-
51-,52-
51-,52-
51-,52-
51-
51-,52-
51-
51-
51-,52-
51-,52-
51-
0.1UF_16V
C1002
1
2
51-
51-
51-
51-
12
51-
51-
51-,52-
51-
ACARDVCC
51-
51-
51-
51-
51-
22K_5%
R1136
12
R1137
22K_5%
12
51-
51-
51-
4.7UF_K_25V
C1001
1
2
0.1UF_16V
C1095
1
2
R1134
22K_5%
12
22K_5%
R1127
51-
51-
51-,52-
51-,52-
C1097
0.1UF_16V
1
2
ACARDVCC
51-
51-
51-,52-
51-,52-
51-,52-
51-,52-
51-
51-
51-,52-
51-,52-
1251-
51-
51-
51-
51-,52-
51-
51-
ACARDVPP
2
51-
51-
51-,52-
51-,52-
BCARDVPP
10_5%
R1133
51-
22K_5%
R1131
12
R1130
22K_5%
1
R1108
OPEN
12
22K_5%
R1113
12
51-
22K_5%
R1112
12
C1006
0.1UF_16V
1
251-
4.7UF_K_25V
C1013
1
2
22K_5%
R1115
12
51-,52-
51-
+V12
51-
C1096
0.1UF_16V
1
2
51-
51-,52-
BCARDVCC
51-
51-,52-
51-,52-
51-,52-
51-
51-
51-
51-
51-
51-
51-
51-
51-,52-
51-
51-
51-
51-
51-
OPEN
12
51-
51-
R1114
22K_5%
12
51-
B_CSERR#
B_CREQ#
B_CAUDIO
B_CDEVSEL#
B_CSTOP#
B_CPERR#
B_CINT#
B_CCLKRUN#
A_CCLKRUN#
51-
51-,52-
R1002
A_CPERR#
A_CSTOP#
A_CDEVSEL#
A_CINT#
A_CCLKRUN#
A_CSERR#
A_CREQ#
A_CAUDIO
A_CAD(15)
A_CAD(14)
A_CINT#
A_CAD(17)
A_CAD(18)
A_CAD(19)
A_CAD(20)
A_CVS2
A_CRST#
A_CAD(22)
A_CSERR#
B_CAD(27)
B_CCLKA_CCLK
B_CREQ#
B_CAD(13)
B_CAD(15)
B_CAD(11)
B_CINT#
B_CCBE3#
B_CRST#
B_CVS1
B_CVS2
B_CSERR#
B_CGNT#
B_CCLKRUN#
A_CAD(9)
A_CVS1
A_CAD(11)
A_CAD(13)
A_CAD(12)
B_CAD(10)
B_CAD(29)
B_CAD(31)
B_CAD(2)
B_CAD(4)
B_CAD(6)
B_D14
B_CAD(8)
B_D2
B_CAD(0)
B_CAD(1)
B_CAD(3)
B_CAD(5)
B_CAD(7)
B_CAD(28)
B_CAD(30)
B_CDEVSEL#
B_CTRDY#
B_CFRAME#
B_CAD(17)
B_CAD(19)
B_CAD(23)
B_CAD(22)
B_CAD(21)
B_CAD(20)
B_CAD(18)
B_CCBE1#
B_CAD(14)
B_CSTSCHG
B_CAUDIO
B_CCD1#
B_CCD2#
B_CCBE0#
A_CAD(30)
A_CREQ#
A_CCBE3#
A_CGNT#
B_CAD(26)
B_CAD(25)
B_CAD(9)
B_CAD(12)
B_CCBE2#
B_CPAR
B_CPERR#
B_CIRDY#
B_CAD(16)
B_A18
B_CBLOCK#
B_CAD(24)
B_CSTOP#
A_CAD(10)
A_CAD(27)
A_CAD(29)
A_CAD(31)
A_CAD(2)
A_CAD(4)
A_CAD(6)
A_D14
A_CAD(8)
A_D2
A_CAD(0)
A_CAD(1)
A_CAD(3)
A_CAD(5)
A_CAD(7)
A_CAD(28)
A_CPERR#
A_CIRDY#
A_CAD(16)
A_A18
A_CBLOCK#
A_CAD(24)
A_CSTOP#
A_CDEVSEL#
A_CTRDY#
A_CFRAME#
A_CAD(23)
A_CAD(21)
A_CCBE1#
A_CSTSCHG
A_CAUDIO
A_CCD1#
A_CCD2#
A_CCBE0#
S_CLK
S_DATA
S_LATCH
GRST#
A_CAD(26)
A_CAD(25)
A_CCBE2#
A_CPAR
![](asset-35.png)
R&D CHK
Changed by Date Changed
A02 PC8803 53 67
DIAMOND
SD CARD CONN
A3
VER Model Number Sheet
DOC CTRL CHK
MFG ENGR CHK
QA CHK
INVENTEC
Time Changed of
Size
TITLE
Engineer
Drawn by
1
6
5
+V3
+V3
EE2 Thursday, July 31, 2003 10:57:35 am
David Du
David Du
NC7WZ14
U1004
2
34
5
U1004
NC7WZ14
2
47K_5%
R1032
1
2
C1028
10PF
1
2
1
2
R1034
47K_5%
1
2
51-
51-
+V3
2
51-
51-
R1028
47K_5%
1
2
C1021
2.2UF_K_10V
C1017
10UF_K_6.3V
1
2
+V3
51-
51-
C1018
0.01UF_16V
1
U1005
NC7SZ08M5
3
1
24
5
VCC_SD
WP
51-
51-
47K_5%
R1029
1
2
CD
10
1CD_DAT3
5CLK
CMD
2
DAT0 7
8
DAT1
DAT2 9
VDD
4
3VSS1
6
VSS2
13
2
VCC_SD
51-
MLX_54786_0991_14P
CN1000
GND 11
GND 12
GND 14
12
47K_5%
R1033
1
2
0.01UF_16V
C1019
1
1
2
R1027
47K_5%
1
2
R1030
10_5%
FDC638P
Q1000 1
D2
5
63 G
S
4
47K_5%
R1007
47K_5%
R1025
1
2
+V3
SD_PWREN#
SD_CLK
SD_DAT3
SD_CMD
SD_CD#
SD_WP
SD_DAT0
SD_DAT1
SD_DAT2
![](asset-36.png)
Engineer
MFG ENGR CHK
QA CHK of
Size
INVENTEC
MINIPCI CONN
A3
TITLE
Date Changed VERChanged by Time Changed
R&D CHK
DOC CTRL CHK
LAYOUT NOTES : +V3 15~20 mil
Drawn by
Model Number Sheet
2
+V3
37-,54-
15-
EE2 Thursday, July 31, 2003 10:57:40 am
David Du
David Du
A02 PC8803 54 67
DIAMOND
L1002
BLM21B121SD
12
55-,51-,37-
+V5S
C1081
0.1UF_16V
1
47K_5%
R1069
1
2
+V3
+V3 +V5S
55-,51-,37-
55-,51-,37-
37-
C1080
0.1UF_16V
1
2
37-
55-,51-,37-
55-,51-,37-
R1116
10K_5%
12
55-,51-,37-
59-,55-,51-,42-,40-,38-
55-,51-,37-
55-,51-,37-
2
59-
58-,40-
37-,54-
R1072
OPEN
12
+V5S
100_5%
R1111
12
59-,51-,42-,40-,37-
+V3S
+V3
0.1UF_16V
C1077
1
55-,51-,37- 55-,51-,37-
55-,51-,37-,54-
1
2
Q1009
NDS7002A
D
3
G
2
1
S
58-
R1090
8.2K_5%
1
2
0.1UF_16V
C1062
0.1UF_16V
1
2
0.1UF_16V
C1079
1
2
0.1UF_16V
C1075
1
2
55-,51-,37-
58-
59-,46-
55-,51-,37-,54-
C1061
0.1UF_16V
C1076
1
2
0.1UF_16V
C1063
1
2
117
1
TIP
TRDY#
66
VCC5VA 123
45-
45-
+V3
55-,51-,40-,37-55-,51-,37-
121
RESERVED_7
RESERVED_WIP5_0
98
RESERVED_WIP5_1
100
RING
2
RST#
26
67
SERR#
68 STOP#
SYS_AUDIO_IN
116
SYS_AUDIO_IN_GND
118 115
SYS_AUDIO_OUT
SYS_AUDIO_OUT_GND
PAR
56
71
PERR#
PME#
34
29
REQ#
16 RESERVED_0
RESERVED_1
22 21
RESERVED_2
RESERVED_3
36
RESERVED_4 43
93
RESERVED_5
112 RESERVED_6
48
INTA#
20 INTB# 17
61
IRDY#
13
LED1_GRNN
11
LED1_GRNP
LED2_YELN
14 LED2_YELP
12
M66EN
104
MOD_AUDIO_MON 111
122 MPCIACT#
GROUND_13 GROUND_14 101
114 GROUND_15
GROUND_2
32
37
GROUND_3
GROUND_4
50 49
GROUND_5
55
GROUND_6
GROUND_7
62
69
GROUND_8
GROUND_9
74
IDSEL
145
G1
G2
146 147
G3
148 G4
GNT#
30
23
GROUND_0
27
GROUND_1
77
GROUND_10
GROUND_11
82 83
GROUND_12
102
AUDIO_GND_0 AUDIO_GND_1 119
15
CHSGND
25
CLK
65
CLKRUN#
C_BE0#
86
73
C_BE1#
59
C_BE2#
45
C_BE3#
DEVSEL#
72
FRAME#
64
52
47
AD23
AD24
46
41
AD25
AD26
44
39
AD27
AD28
42
35
AD29
AD30
38
33
AD31
113
AUDIO_GND
120
AD12 79
AD13
78 75
AD14AD15
76
AD16
60 57
AD17AD18
58
53
AD19AD20
54 51
AD21AD22
AD01
AD02
94 95
AD03
AD04
92 91
AD05
AD06
90 87
AD07
85
AD08
AD09
84 AD10 81
80 AD11
7
8PMJ-7 9
8PMJ-8
107
AC_BIT_CLK
108 AC_CODEC_ID0# AC_CODEC_ID1# 109
AC_RESET#
110
105
AC_SDATA_INAC_SDATA_OUT
106 AC_SYNC 103
AD00
96
99
3.3V_5
70
3.3V_6
88 89
3.3V_7
5V_0
18
5V_1 97
8PMJ-1
4
8PMJ-2
63
8PMJ-3
8PMJ-4
8
8PMJ-5
10
5
8PMJ-6
AMP_1318228_1_124P
CN1001
3.3VAUX_0
24
3.3VAUX_1
124
19
3.3V_0
3.3V_1
28
31
3.3V_2
3.3V_3
40
63
3.3V_4
PCI_CBE#(3)
CH_CLK
0.1UF_16V
C1078
1
2
CH_DATA
PCI_RESET2#_3
PCI_PME#_3
PHONE
PCI_AD(31:0)
PCI_AD(20)
LED_WLAN_LINK
XMIT_OFF#
PCI_AD(6)
PCI_AD(4) PCI_AD(5)
PCI_AD(2)
PCI_AD(0) PCI_AD(3)
PCI_AD(1)
MPCI_PWM
PCI_AD(13)
PCI_AD(11) PCI_AD(12)
PCI_AD(10)
PCI_AD(9)
PCI_CBE#(0)
PCI_AD(8)
PCI_AD(7)
PCI_TRDY#_3 CLKRUN#_3
PCI_STOP#_3 PCI_SERR#_3
PCI_DEVSEL#_3 PCI_PERR#_3
PCI_CBE#(1)
PCI_AD(15) PCI_AD(14)
PCI_PAR_3
PCI_AD(18) PCI_AD(17)
PCI_AD(16)
PCI_CBE#(2)
PCI_IRDY#_3
PCI_FRAME#_3
PCI_AD(28) PCI_AD(25)
PCI_AD(26)
PCI_AD(24)
PIRQF#_3
PCI_AD(23)
PCI_AD(22) PCI_AD(21)
PCI_AD(20) PCI_AD(19)
CLK_MINIPCI_3R
A_MPCI_IN
MPCIGNT0#_3 MPCIREQ0#_3
PCI_AD(31)
PIRQF#_3
PCI_AD(29)
PCI_AD(30)
PCI_AD(27)
![](asset-37.png)
Changed by Sheet
Date Changed
Size
DOC CTRL CHK
MFG ENGR CHK
QA CHK Model Number
R&D CHK
Drawn by
Engineer
TITLE
VER of
INVENTEC
Time Changed
1
TP554
EE2 Thursday, July 31, 2003 10:57:45 am
David Du
David Du
A02 PC8803 55 67
DIAMOND
LAN INTERFACE-1
A3
0.1UF_16V
C88
1
2
+V3A
1N4148D1024
2
C1398
0.1UF_16V
1
2
100_5%
R1357
12
3300PF_50V
C1356
1
2
C87
0.01UF_16V
1
2
1
2
59-,9-,55-
R97
1K_5%
12
54-,51-,37-
54-,51-,40-,37-
C1471
10UF_K_6.3V
1
2
C71
0.1UF_10V
0.1UF_16V
1
2
R132
OPEN
12
+V3S
54-,51-,37-
C93
1
2
+V2.5_LAN
R1355
OPEN
12
C103
C1358
0.1UF_16V
1
2
TP555
0.1UF_16V
C110
0.1UF_16V
1
2
0.01UF_16V
C100
1
2
51-,54-,37-,55-
54-,51-,37-
TP556
54-,51-,37-
54-,51-,37-
37-
12
40-
0.1UF_10V
C73
1
2
+V3_LAN
C14701
2
0_5%
R6033
12
R6034
OPEN 24
5
R1350
100_5%
1
2
10UF_K_6.3V
0.1UF_16V
C108
1
2
+V3A
NC7SZ00M5
U1022
3
1
12
4.7K_5%
R109
12
+V3_LAN
54-,51-,37-,55-
NDS7002A
Q1036 3
D
2
G
S
1
L1017
BLM21B121SD
12
48-,37-,29-,21-
Q1038
NDS7002A
D
3
G
2
1
S
54-,51-,37-
2
0.1UF_16V
C1357
1
2
15-
R133
4.7K_5%
100K_5%
R1354 12
R1358
1M_5%
1
VCC
8
7WP
TC7S32F
U1021
3
1
24
5
12
ATM_AT24C64A_SOIC_8P
U1034
A0 1
A1 2
A2 3
GND 4
SCL
6SDA
5
2
37-
54-,51-,37-
R96
4.7K_5%
2
C109
0.1UF_10V
1
2
L1020
BLM11A601S
1
54-,51-,37-
+V3
+V2.5L
0.1UF_10V
C72
1
57-,5-
FDC638P
Q1037
D1
2
5
6
G
3
4S
R95
4.7K_5%
12
+V3_LAN
+V3_LAN
VSS_22 G8
D9
VSS_23
VSS_24 E9
VSS_25 F9
54-,51-,37-
10UF_K_6.3V
C1355
1
2
VSS_11 F6
VSS_12
VSS_13 G6
VSS_14 L6
D7
VSS_15
VSS_16 E7
VSS_17 F7
VSS_18 G7
VSS_19 D8
E8
VSS_20
VSS_21 F8
VESD_3
VSS_01 N1
VSS_02 E2
K2
VSS_03
D4
VSS_04
G4
VSS_05
VSS_06 D5
VSS_07 E5
F5
VSS_08 G5
VSS_09 D6
VSS_10 E6
L4
VDDIO_PCI06
VDDIO_PCI07 C5
N6
VDDIO_PCI08
VDDIO_PCI09 E4
VDDIO_PCI10 A7
VDDP_01 P11
L13
VDDP_02 K14
VDDP_03
P1
VESD_1 G2
VESD_2 A1
D11
J12 VAUX_PRSNT
A11
VDDIO_01
VDDIO_02 F11
K12
VDDIO_03
VDDIO_04 L12
VDDIO_PCI01 E1
G1
VDDIO_PCI02
VDDIO_PCI03 P2
B3
VDDIO_PCI04 K3
VDDIO_PCI05
A2
E10
SI
SMB_CLK
A10
SMB_DATA
C9
SO G11
STOP#
H1
TCK C12
D12
TDI
B12
TDO A12
TMS
G3 TRDY#
TRST#
J2 PERR#
A6 PME#
B10
REGCTL12
REGCTL25 C11
REGSEN12 A9
REGSEN25 C10
B9
REGSUP12
B11
REGSUP25
C3 REQ#
E11
SCLK
SERR#
P7
MAC_PLL_VSS M6
L14
NC_01
NC_02 J11
L11
NC_03
NC_04
J4
K4 NC_06
L7 NC_07
J1 PAR
A3 PCI_CLK
C2 PCI_RST#
M10
P10
EEDATA
F2 FRAME#
GNT#
J3
GPIO0 H12
K13
GPIO1
GPIO2 J13
IDSEL
A4
INTA#
H2
F1 IRDY#
M66EN
F4
MAC_PLLVDD3
AD29
C7
A8 AD30
AD31
B8
CBE0#
M4
CBE1#
L3
F3 CBE2#
C4 CBE3#
CLK_RUN#
H4
CS# H11
H3 DEVSEL#
EECLK
D1
D2 AD19
AD20
D3
AD21
C1
B1 AD22
B2 AD23
B4 AD24
AD25
A5
B5 AD26
B6 AD27
AD28
C6
AD07
P3 AD08
AD09
N3
N2 AD10
M1 AD11
M2 AD12
AD13
M3
AD14
L1
L2 AD15
K1 AD16
AD17
E3
AD18
BCM_BCM5705M_BGA_196P
U1024
AD00
N7
M7 AD01
AD02
P6
AD03
P5
AD04
N5
M5 AD05
AD06
P4
N4
R1352
1
2
R1353 100K_5%
12
1
2
+V3S
59-,9-,55-
37-
220K_5%
1
2
0.1UF_16V
C319
1
2
0.1UF_16V
C104
59-,54-,51-,42-,40-,38-
C317
0.1UF_16V
1
20.1UF_16V
C318
PCI_AD(0)
PCI_AD(0:31)
LAN_ON_3
PCI_PME#_3
AIRACIN
AIRACIN2
PCI_AD(8)
PCI_AD(7)
PCI_AD(6)
PCI_AD(5)
PCI_AD(4)
PCI_AD(3)
PCI_AD(2)
PCI_AD(1)
PCI_AD(16)
PCI_AD(15)
PCI_AD(14)
PCI_AD(13)
PCI_AD(12)
PCI_AD(11)
PCI_AD(10)
PCI_AD(9)
PCI_AD(24)
PCI_AD(23)
PCI_AD(22)
PCI_AD(21)
PCI_AD(20)
PCI_AD(19)
PCI_AD(18)
PCI_AD(17)
PCI_CBE#(0:3)
PCI_AD(31)
PCI_AD(30)
PCI_AD(29)
PCI_AD(28)
PCI_AD(27)
PCI_AD(26)
PCI_AD(25)
PCI_DEVSEL#_3
CLK_NICPCI_3R
PCI_CBE#(3)
PCI_CBE#(2)
PCI_CBE#(1)
PCI_CBE#(0)
NICREQ1#_3
PCI_PERR#_3
PCI_PAR_3
PCI_RESET1#_3
PCI_IRDY#_3
PIRQE#_3
PCI_AD(30)
NICGNT1#_3
PCI_FRAME#_3
CLKRUN#_3
PCI_TRDY#_3
PCI_STOP#_3
PCI_SERR#_3 LAN_ON_3
![](asset-38.png)
GND
VCC
INVENTEC
Model Number
R&D CHK
Date Changed Time Changed
MFG ENGR CHK
QA CHK VER Sheet of
Changed by
EE2 Wednesday, August 13, 2003 10:36:22 pm
David Du
David Du
A02 PC8803 56 67
DIAMOND
LAN INTERFACE-2
A3
DOC CTRL CHK
Drawn by
Size
TITLE
Engineer
12
1.18K_1%
R134
12
+V_LAN
1
20.1UF_16V
C325
1
2
25MHZ
X1002
1
2
C323
0.1UF_16V
1
2
C324
0.1UF_16V
0.1UF_16V
1
20.1UF_16V
C321
1
2
0.1UF_16V
C322
R1378
470_5%
12
0.1UF_16V
C1354
1
2
C320
49.9_1%
1
2
56-
0.1UF_16V
C1383
1
2
1
2
L1024
BLM11A601S
12
56-
R1374
0.1UF_16V
1
2
L1016
BLM11A601S
12
0.1UF_16V
C107
2
0.1UF_16V
C91
1
2
+V1.2L
57-
57-
C102
2
C86
0.1UF_16V
1
2
0.1UF_16V
C92
1
12
BLM11A601S
L4008
12
0.1UF_16V
C1374
1
1
2
R1376
49.9_1%
1
2
R110
4.7K_5%
2
56-
0.1UF_16V
C1375
1
2
57-
C1380
2.2UF_0805_16V
57-
2200PF_2000V
C13701
2
C1373
0.1UF_16V
1
R130
75_1%
1
2
57-
75_1%
R131
1
2
TX+
2TX-
9Y1 10
Y2
57-
49.9_1%
R1377
1
2
11 G2 12
P4
4
5P5
P7
7P8
8
RX+
3
6RX-
1
0.1UF_16V
1
2
+V2.5_LAN
AMP_C_1470693_1_RJ45
CN4
G13
G14
G1
Q1048
NDC7002N
6
D1
D2 4
1G1
G2
3
S15
2
S2
C89
TCT4
2TD1+
3TD1-
TD2+
5
6TD2-
TD3+
8TD3-
9
11 TD4+
12 TD4-
57-
+V3S
23
MX1- 22
MX2+ 20
19
MX2-
MX3+ 17
16
MX3-
14
MX4+ 13
MX4-
TCT1
1
TCT2
4
7TCT3
10
49.9_1%
1
2
U9
LANK_LG_2402S_24P
24
MCT1
21
MCT2
18
MCT3
MCT4 15
MX1+
12
C1376
0.1UF_16V
1
2
57-
R1347
C106
0.1UF_16V
1
2
BLM11A601S
L1022
C1382
1
2
R1348
49.9_1%
1
2
56-
200_5%
R1385
12
R137
75_1%
1
2
0.1UF_16V
C1371
1
2
C101
0.1UF_16V
1
2
IXO
2IXO
3
IXO
4
IXO
5IXO
6
IXO
7
IXO
8
57-
57-57-
0.1UF_16V
57-
+V3S
470_5%
R1379
12
PER_PI5C3306_TSSOP_8P
U7
IXO
1
56-
C90
0.1UF_16V
1
2
C1352
0.1UF_16V
1
2
C1379
1
2
75_1%
R129
1
2
1
2
+V5S
56-
C105
0.1UF_16V
1
2
0.1UF_16V
1
2
57-
10K_5%
R1384
12
49.9_1%
R1349
0.1UF_16V
C1353
1
2
+V2.5_LAN
56-
+V3S
49.9_1%
R1346
2
BLM11A601S
L1021
12
57-
+V2.5_LAN
+V2.5_LAN
2
0.1UF_16V
C1372
1
2
+V_LAN
0.1UF_16V
C1381
1
2
0.1UF_16V
C70
1
2
C1384
27PF
1
N11 XTALI
XTALO
N10
XTALVDD
J14
N13 XTAL_VSS
57-
57-
57-,43-,38-
49.9_1%
R1375
1
M14
VDDC_24
N14
VDDC_25
P14
VSS_26
F10
G10 VSS_27
VSS_28
M12
N12 VSS_29
G9 VSS_30
VSS_31
H9
VSS_32
L9
B7 VSS_33
J8
VDDC_13
K8
P8 VDDC_14
J9 VDDC_15
VDDC_16
K9
VDDC_17
J10
K10 VDDC_18
L10 VDDC_19
VDDC_20
E12
VDDC_21
P12
VDDC_22
P13
VDDC_23
J5 VDDC_02
VDDC_03
K5
L5 VDDC_04
VDDC_05
H6
J6 VDDC_06
VDDC_07
K6
H7 VDDC_08
VDDC_09
J7
K7 VDDC_10
H8 VDDC_11
VDDC_12
H14
RDAC D10
TRD0M B14
B13
TRD0P
C14
TRD1M
TRD1P C13
TRD2M D14
D13
TRD2P
E14
TRD3M
TRD3P E13
H5 VDDC_01
G14
LED_LNK# G13
LOW_PWR M11
MC_09 N8
L8
MC_10
MC_11 M8
P9
MC_12
M9
MC_14
MC_15 N9
K11
MC_16
H10 NC_08
PLLVDD2
BCM_BCM5705M_BGA_196P
U1024
AVDDL_01 F12
F13
AVDDL_02
A13
AVDD_01
AVDD_02 F14
A14
BIASVDD
C8 DC_01
GPHY_PLL2_VSS M13
LED_100# H13
LED_1000# G12
LED_ACT#
1
2
10UF_K_6.3V
C1378
1
2
57-
+V_LAN
L1026
BLM41P800S
12
56-
C1385
27PF
D-
D+
LED_LINK#_R_DUCK
LED_ACT#_R_DUCK
LED_ACT#_R
C+
C-
57-
D+
D-
LED_ACT#
TD-
TD+
RD-
RD+
LED_LINK#
C-
TD+
TD-
LED_LINK#_R
PREP
LED_ACT#_R LED_ACT#
LED_LINK#_R LED_LINK#
TRD3P
RD+
RD-
C+
TRD0M
TRD0P
TRD1M
TRD1P
TRD2M
TRD2P
TRD3M
![](asset-39.png)
Engineer
QA CHK VER
Date Changed
TITLE
MFG ENGR CHK
Drawn by
Time ChangedChanged by
SizeR&D CHK
OPEN
DOC CTRL CHK
INVENTEC
ofSheet
LAYOUT NOTES : 40~60 MIL
Model Number
+V5S
38-
EE2 Thursday, August 21, 2003 11:41:59 am
David Du
David Du
A02 PC8803 57 67
DIAMOND
PORT PARALLER
A3
1
2
47-
+VADPTR
13-
R169 0_5%12
12
75_1%
R1223
1
2
44-,42-
33PF_50V
C162
C1338
100PF_50V
1
2
40-
BLM11B750S
L13
1K_5%
R6024
1
2
C6025
0.01UF_16V
1
2
1
2
56-
35-
R6023
1K_5%
1
2
1
2
35-,57-
BLM11B750S
L8
12
33PF_50V
C166
33PF_50V
C1328
1
2
30-
35-
40-
C1329
33PF_50V
R158
4.7K_5%
1
2
100PF_50VC1335
12
AK
R
1K_5%
R6022
1
2
56-
44-,42-
R285
100K_5%
1
2
D7
FAIR_LM431SACMF_3P
+V5S
C330
100PF_50V
1
2
38-
38-
1
2
45-
38-
C1330 100PF_50V
12
1
2
100PF_50V
C329
1
2
33PF_50V
C164
+V3S
30-
0_5%
R122412
C328
100PF_50V
43- 18PF
C165
1
2
30-
+V5
43-
1
2
C161
33PF_50V
1
2
56-
56-
30-
100PF_50V
C6027
1
2
56-
C171
0.1UF_16V
1
2
OPEN
R168 1
2
1
2
44-,42-
R154
1K_5%
12
56-
C1320
33PF_50V
2
35-
30-
+V3
30-
38-
0.01UF_16V
C6026
100PF_50V
C1336
1
2
56-
33PF_50V
C155
1
L9
BLM11B750S
12
C1337
OPEN
1
2
33PF_50V
C158
1
2
R157
2.2K_5%
1
2
R170 0_5%
12
43-,42-
43-,42-
C163
33PF_50V
1
233PF_50V
C169
1
2
VA
P2
A4 VA_ON#
47-
+V5
44-,42-
44-,42-
44-,42-
B76
SPDIF
A50
TV_CHROMA B13
B12
TV_COMP
B14
TV_LUMA
A43 USB3+
USB3-
A41
A39 USB4+
USB4-
A37
USBOC3#
A35 USBOC4#
A34
PR_RI
PR_RTS#
A8
PR_SIN
A12
A13 PR_SOUT
PWRLED B4
RJ45ACTLED
A69
A71 RJ45_GND RJ45_LILED B70
A75 RJ45_RX+
RJ45_RX-
A76 B75
RJ45_TX+
RJ45_TX-
PREP
A7 PR_CTS
A11 PR_DCD#
GND
PR_DRT#
A14
PR_DSR#
A9
A48 PR_HPSENSE#
PR_KB_CLK B6
B5
PR_KB_DATA
B8
PR_MS_CLK
PR_MS_DATA B7
A10
A31 PPT_PD2
A30
A29 PPT_PD3
PPT_PD4
A28
A27 PPT_PD5
A26 PPT_PD6
PPT_PD7
A25
PPT_PE
A21
A20 PPT_SLCT
A16 PPT_SLIN#
PPT_STB#
A24
A70
A55 LINEINR
LINEOUTL
A57
A58 LINEOUTR
B1
NBSWON#
A23 PPT_ACK#
PPT_AFD#
A19
A22 PPT_BUSY
PPT_ERR#
A18
A17 PPT_INIT#
A32 PPT_PD0
PPT_PD1
DVI_D5+ B52
DVI_D5- B50
DVI_DDC_CLK B26
B27
DVI_DDC_DATA
G1
GND
GND G2
HPD B20
B10
I2C_CLOCK
I2C_DATA B9
A54 LINEINL
DVI_CLK-
B47
DVI_D0+
B45
DVI_D0-
DVI_D1+ B37
DVI_D1- B35
B32
DVI_D2+
DVI_D2- B30
B62
DVI_D3+
B60
DVI_D3-
DVI_D4+ B57
DVI_D4- B55
CRTVS
CRT_B B22
B18
CRT_DDC_CLK B19
CRT_DDC_DATA
B23
CRT_G
CRT_R B24
D+
A72
A73 D-
DETECT1
A2
B69
DETECT2
B42
DVI_CLK+
B40
NC B67
NC B68
GND
B71
RJ45_GND
B74
RJ45_GND
B77
RJ45_GND
C+ B72
B73
C-
CRTHS B17
B16
GND
B56
NC
B58
GND B59
GND
B61
NC
B63
GND B64
GND B65
NC B66
NC
B43
GND B44
GND
B46
NC
B48
GND B49
GND
B51
NC
B53
GND B54
GND
B3
3V_03
B31
NC
B33
GND B34
GND
B36
NC
B38
GND B39
GND
B41
ACIN
A5
B11
GND
B15
GND
NC B2
B21
AGND
B25
AGND
B28
GND B29
GND
A6
GND
A60
NC
A62
GND
A64
NC
A66
GND
A68
RJ45_GND
A74
RJ45_GND
A77
NC
A46
NC
A47
NC
A49
AUDIO_GND
A51
NC
A52
AUDIO_GND
A53
AUDIO_GND
A56
AUDIO_GND
A59
P1 5V_03
A15
GND
A33
GND
A36
NC
A38
GND
A40
NC
A42
GND
A44
GND
A45
12V_03
A65 1394TPAN1
1394TPAP1
A67
A61 1394TPBN1
1394TPBP1
A63
2G
3
G
3V_03
A3
G4
+V3
45-
43-
56-
CN1004
JAE_WD_154S4VH_VF_154P
G
1
A1 1
2
R1220 1K_5%
12
35-,57-
1
2
C137
18PF
1
2
R6021
1K_5%
12
NDS7002A
Q1
3
D
2
G
S
1
4.7K_5%
R156
2
C1319
33PF_50V
1
2
+V5
35-,57-
R179
0_5%
44-,42-
30-
44-,42-
C1318
33PF_50V
1
+V5S
35-
+V12
30-
55-,5-
30-
35-,57-
12
35-,57-
0_5%R284
12
30-
56-,43-,38-
18PF
C138
1
2
43-
C6030 100PF_50V
45-
43-,42-
33PF_50V
C1317
1
2+V3S
56-
R6041
12
R6040
0
12
44-,42-
30-
59-,40-,38-
10K_5%
1
2
+V3
1K_5%R141 12
0
2
Q2
NDS7002A
D
3
G
2
1
S
R180
43-
R6042
0
12
C159
33PF_50V
1
1
2
R178
OPEN
1
2
2
47-
44-,42-
0.1UF_25V
C172
1
2
1UF_10V
C170
2
NDS7002A
Q3
D
32
G
S
1
2.2K_5%
R159
1
33PF_50V
C160
1
2
40-
C1331
33PF_50V
1
2
57-
30-
57-
C1334
OPEN
12
SCL_MBAY
30-
30-
35-,57-
56-
40-
FBM_11_321611_3A
L15
1
HPD
B
KB_DAT_5
KB_CLK_5
EM_DAT_5
EM_CLK_5 SDA_MBAY
SPDIF
LINEINR
TX1M
TX2P
TX2M
DVIDDCCLK_D
DVIDDCDATA_D
PWR_SWIN#_3
PWR_LED_3
LED_LINK#_R_DUCK
TD+
TD-
DOCK_DDCCLK
DOCK_DDCDATA
G_CRT
R_CRT
TXCP
TXCM
TX0P
TX0M
TX1P
R
DVIDDCCLK
DVIDDCDATA
C+
C-
DOCK_HSYNC
DOCK_VSYNC
B_CRT
PR_AOUTL
LINEINL
D-
D+
AIRACIN
MBAY_DISABLE
PDATA(3)
PDATA(2)
PDATA(1)
PDATA(0)
PINIT#_5
ERROR#_5
BUSY_5
ALF#_5
ACK#_5
PR_AOUTR
SDCD#_3R
SCTS_3R
PREP
STRB#_5
SLCTIN#_5
SLCT_5
PE_5
PDATA(7)
PDATA(6)
PDATA(5)
PDATA(4)
RD+
LED_ACT#_R_DUCK
STXD_3
SRXD_3R
SRTS_3
RI#_3R
PR_HPSENSE#
SDSR#_3R
SDTR#_3
USB_PN2
USB_PP2
USB_PN3
USB_PP3
RD-
B_CRT
G_CRT G
R_CRT
SLP_S3#_5R
PDATA(7:0)
PWR_LED#_3
PWR_LED_3
COMP_B
CHROMA_C
LUMA_Y
DVIDDCCLK_D
DVIDDCDATA_D
![](asset-3a.png)
ADD NOTES : 32 AWG MUST BE USED FOR THE CABLE
Engineer
DIAMOND
BLUETOOTH
A3
Drawn by
Time ChangedChanged by
DOC CTRL CHK
QA CHK of
Size
TITLE
Date Changed
R&D CHK
MFG ENGR CHK
VER Model Number Sheet
INVENTEC
100K_5%
R1056
1
2
+V3S
EE2 Thursday, July 31, 2003 10:58:02 am
David Du
David Du
A02 PC8803 58 67
12
R1058 100_5%
12
54-
54-
2
+V3
NDS7002A
Q1006 3
D
2
G
S
1
R1057 100_5%
59-
220K_5%
R276
12
R275
10K_5%
1
4
Q14
FDC638P
D1
2
5
6
G
3
4S
BLUETOOTH_VCC
C305
0.1UF_16V
1
2
DLW21SN900SQ2L
L1001 2
3
1
9
+V3
38-
10UF_K_6.3V
C3041
2
54-,40-
10
2
2
3
3
4
4
55
66
7
7
8
8
G
CH_DATA
CH_CLK
XMIT_OFF#
38-
JST_FM_SM8B_SRSS_TB_8P
CN21
1
1
G
USB_PP4
BLUETOOTH_LED
USB_PN4
![](asset-3b.png)
DOC CTRL CHK
Changed by
TITLE
3A_120mil
3A_120mil
VER
Drawn by
3A_120mil
4A_160mil
of
Model Number
R&D CHK
Date Changed
INVENTEC
Size
Time Changed
Engineer
Sheet
4A_160mil
47-,45-,40-,38-,13-,12-,9-,7-
57-,40-,38-
David Du
David Du
10:58:07 amThursday, July 31, 2003EE2
6759
PC8803A02
SWITCH BUTTON & LED
DIAMOND
A3
LID SWITCH
MFG ENGR CHK
QA CHK
S8
SCREW2.8_6_7_5P
40-
+V5A
1
2
41-,40-,59-
40-
42-
SCREW2.8_6.5_8_5P
S3
S7
40-
+V3S
C1294
0.1UF_16V
G4
G
0.1UF_16V
C136
1
2
SCREW2.8_6_7_5P
1
+V5S
48-
JST_BM2B_SRSS
CN6002
1
1
2
23
L7
BLM11B141S
12
48-
40-
38-
68UF_4V_METAL
C327
42-
SCREW2.8_6_7_5P
S5
38-
41-,40-
47-,45-
58-
68UF_4V_METAL
C326 1
42-,40-,38-
42-,40-,38-
+V3A
+VCCP
SCREW2.8_8_5P
S26
54-
SCREW2.8_6_7_5P
S12
PAD1004
SMDPAD3UM_5_1P
11
41-,40-
S2
SCREW2.8_6.5_8_5P
45-,38-
45-,38-
40-
+V1.8S
FIX_MASK
FIX4
66
7
78
8
99
RTCBAT
51-,42-,40-,37-
42-,40-,38-,30-
S20
SCREW2.8_6_5P
37
37 38
38
39 39
4
4
40 40
41
G42
G
55
3
3
30
30 31
31 32
32 33
33 34
34
35 35
36 36
22 22
23 23
24 24
25
25 26
26
27 27
28 28
29
29
15
15 16
16
17 17
18 18
19
19
2
2
20
20
21 21
MLX_53643_0404_40P
CN22
1
1
10 10
11 11
12 12
13 13
14 14
24
G
33
44
5
5
6
6
77
88
9
9
17 18
18
19 19
22
20 20
G21
G22
23
G
11
10
10 11
11 12
12 13
13 14
14
15 15
16 16
17
1
1
S19
SCREW2.8_6_5P
CN12
MLX_52559_2092_20P
54-,46-
45-
C1292
0.1UF_16V
1
2
SMDPAD3UM_5_1P
PAD1003
SCREW2.8_6_5P
S21 FIX_MASK
FIX3
FIX2
FIX_MASK
SCREW2.8_6_7_5P
S14
45-,38-
57-,40-,59-
42-,40-,38-
41-,40-,59-
41-,40-,59-
FIX1
FIX_MASK
2
3
1
15-
S15
SCREW2.8_6_7_5P
+V3A
S6
SCREW2.8_6_7_5P
42-,40-,38-
38-
D3 BAV99
S11
SCREW2.8_6_7_5P
38-
SCREW2.8_6_5P
S18
54-,51-,42-,40-,37-
S13
SCREW2.8_6_5P
42-
S17
SCREW2.8_8_5P
SCREW2.8_6.5_8_5P
S1
+V1.5A
+V3A
88
9
9
+V1.2L
FIX5
FIX_MASK
FIX6
FIX_MASK
39 39
44
40 40
41
G42
G
5
56
6
77
31
31 32
32 33
33 34
34
35 35
36 36
37
37 38
38
24 24
25
25 26
26
27 27
28 28
29
29
33
30
30
17
17 18
18
19 19
22
20 20
21 21
22 22
23 23
11
10
10 11
11 12
12 13
13 14
14
15 15
16 16
R153
100K_1%
12
55-,54-,51-,42-,40-,38-
41-,40-,59-
CN23
MLX_53643_0404_40P
1
2
34
+VBATR
57-,40-,59-
11-
40-,30-,14-,11-
41-
40-
+V3A
42-,40-,38-
SW_DT006_PT11ABH_E
SW1
55-,9-
37-,16-
41-
SCREW2.8_6_7_5P
S9
1
2
38-
+V3S
SCREW2.8_8_5P
S16
0.1UF_16V
C1293
MCH_GOOD
PWR_GOOD_3
LPC_AD(2)
LPC_AD(3)
SERIRQ_3
CLKRUN#_3
KSCAN_IN(1)
KSCAN_IN(5)
SCAN_OUT(3)
PWR_LED#_3
PHONE
LPC_FRAME#_3
CLK_FWHPCI_3R
LPC_AD(0)
LPC_AD(1)
SCAN_IN(7)
SCAN_IN(7)
SCAN_OUT(1)
SCAN_OUT(8)
LAN_ON_3
SLP_S3#_3R
AC97_BIT_CLK
FRAME_SYNC_ICH
SDATA_IN1_ICH
SCAN_OUT(1)
PWR_SWIN#_3
NUM_LED#_3
CAPS_LED#_3
SCROLL_LED#_3
FWH_WP#_3
FWH_TBL#_3
H_INIT#
SDATA_OUT_ICH
CODEC_RST#_ICH
PWR_LED#_3
BAT_LED#_3
HDDASP#_5
LED_WLAN_LINK
EAPD
PCI_RESET2#_3
SUS_STAT#_3
LPC_DRQ1#
LID_SW#_3
BLUETOOTH_LED
MBLED#_3
VOL_UP
VOL_DN
IR_TX_3
IR_RX_3
IR_SD_3
![](asset-3c.png)
CLK4/20
QA CHK VER Model Number
POWER15/5
Changed by Date Changed Time Changed
Engineer
Drawn by
R&D CHK
DOC CTRL CHK
FHW ON BUTTON DAUGHTER BOARD
(15/5)
of
Size
TITLE
INVENTEC
MFG ENGR CHK
Sheet
EE2 Thursday, July 31, 2003 10:58:37 am
David Du
David Du
A02 PC8803 60 67
DIAMOND
FHW
A3
2
R4044
OPEN
1
2
100_5%
R4023
12
2
R4024
0_5%
1
2
OPEN
R4039
1
1
2
OPEN
R4038
1
2
0_5%
R4020
1
1
2
FWH_VPP_BN
+V3S_BN
OPEN
R4021
63-,62-
63-,62-
63-,62-
63-
63-
63-,62-
63-,62-
C4018
0.01UF
INIT#
24
RFU
21
2RST#
8TBL#
VCC1
25
32 VCC2
VCCA
27
1VPP
WP#
7
63-,62-
63-,62-
FWH3
FWH4 23
22
FWH5
GND1
16 GND2
26 GND3
28
IC
29
12
ID0
ID1 11
10
ID2
ID3 9
20 DPPO
19 FDIS
6
FGPI0
FGPI1 5
4
FGPI2
FGPI3 3
30
FGPI4
FWH0 13
14
FWH1
FWH2 15
17
20.01UF
C4017
1
2
CN4002
AMP_C822273-1_SOKT_32P
31 CLK
CLKRUN#
18
1
2
C4028
4.7UF_K_6.3V
1
2
4.7UF_K_6.3V
C40191
1
2
0.1UF_16V
C4029
1
2
C4031
0.1UF_16V
1
2
R4035 100_5%
12
63-
C4030
0.1UF_16V
100_5%
1
2
100_5%
R4037
1
2
R4036
100_5%
PCI_RESET2#_3_BN
CLK_FWHPCI_3R_BN
FWH_INIT#_3_BN
+V3S_BN
R4043
LEGACY_FRE_EN#
PCBREV2
PCBREV1
PCBREV0
LPC_FRAME#_3_BN
LPC_AD_BN(3)
LPC_AD_BN(2)
LPC_AD_BN(1)
LPC_AD_BN(0)
FWH_WP#_3_BN
FWH_TBL#_3_BN
![](asset-3d.png)
AUDIO4/12
MDC CONN
Changed by Date Changed Time Changed
Engineer
Drawn by
R&D CHK
DOC CTRL CHK
POWER15/5
PC8803 61 67
DIAMOND
MDC CONN
A3
MFG ENGR CHK
QA CHK VER Model Number Sheet of
Size
TITLE
INVENTEC
MDC CONN ON BUTTON DAUGHTER BOARD
22
C4042
OPEN
1
2
EE2 Thursday, July 31, 2003 10:58:42 am
David Du
David Du
A02
9
CD_LEFT
13
11 CD_RIGHT
MONO_OUT_PC_BEEP
14
MONO_PHONE
MSTRCLK
29
PRIMARY_DN 16
RESET#
25 SDATA_INA 26
24
SDATA_INB
23 SDATA_OUT SYNC
G6 36
18
5VD
5VMAIN 10
6
RESERVED
GND 8
AUDIO_PWRDN 2
AUXA_LEFT
7
5AUXA_RIGHT
30
BITCLK
CD_GND
28
GND
3GND
3.3VAUX
17
21 3.3VMAIN
31 G1 G2 32
G3
33 34
G4
35 G5
CN4003
AMP_3_179397_5_30P+6G
RESERVED 12
14
RESERVED
15 GND
19 GND GND 20
GND
27 2
33_5%
R4049 12
R4009 33_5%
12
C4013
1
2
+V5S_BN
R4048 33_5%
1
C4023
10UF_6.3V
1
+V3S_BN
C4048
0.1UF_16V
1
2
0.1UF_16V
2
+V3S_BN
C4022
0.1UF_16V
1
2
63-
63-
63-
63-
63-
63-
BLM41P800S
L4002
1
AC97_BIT_CLK_BN
PHONE_BN
CODEC_RST#_ICH_BN SDATA_IN1_ICH_BN
SDATA_OUT_ICH_BN FRAME_SYNC_ICH_BN
![](asset-3e.png)
AMP 20PIN CONNECTOR
ACES_88028_2400
VERTime Changed
Drawn by
R&D CHK
MFG ENGR CHK
POWER15/5
Date Changed QA CHK
MOTHERBOARD SIDE
INVENTEC
Model Number
TCPA CONN ON BUTTON DAUGHTER BOARD
DOC CTRL CHK
TITLE
of
Size
Changed by Sheet
EE2 Thursday, July 31, 2003 10:58:47 am
David Du
David Du
A02 PC8803 62 67
DIAMOND
TCPA
A3
Engineer
12
C4034
4.7UF_K_6.3V
1
2
63-,60-
63-,60-
10K_5%
R4046
1
2
R4047 OPEN
63-,60-
63-,60-
63-,60-
+V3S_BN
OPEN
R4045
12
63-
63-
88
9
9
63-,60-
63-
+V3S_BN
63-
63-,60-
28
29 29
33
30
30
44
5
56
6
77
20 20
21
21 22
22
23 23
24 24
25 25
26 26
27
27 28
13 14
14
15 15
16 16
17
17 18
18
19 19
22
CN4000
ACES_88028_2400_24P
11
10
10 11
11 12
12 13
CLK_FWHPCI_3R_BN
SERIRQ_3_BN
LPC_DRQ1#_BN
LPC_AD_BN(0)
LPC_AD_BN(1)
LPC_AD_BN(2)
LPC_AD_BN(3)
SUS_STAT#_3_BN
CLKRUN#_3_BN
LPC_FRAME#_3_BN
PCI_RESET2#_3_BN
![](asset-3f.png)
Date Changed
TITLE
Changed by
SWITCH & CONN & LED ON BUTTON DAUGHTER BOARD
P1
P2
R&D CHK
INVENTEC
Time Changed
Engineer
Drawn by
P3
INTERNAL
E-MAIL
DOC CTRL CHK
10:58:55 am
David Du
David Du
A02 PC8803 63 67
DIAMOND
CONN & SWITCH & LED
A3
Sheet of
Size
Model Number
SERCH
MFG ENGR CHK
QA CHK VER
77
88
9
9
63-
+V3A_BN
63-
EE2 Thursday, July 31, 2003
38
39 39
44
40 40
41
G42
G
5
56
6
30 31
31 32
32 33
33 34
34
35 35
36 36
37
37 38
23 23
24 24
25
25 26
26
27 27
28 28
29
29
33
30
16 16
17
17 18
18
19 19
22
20 20
21 21
22 22
11
10
10 11
11 12
12 13
13 14
14
15 15
+V5S_BN
62-,60-
R4018
330_5%
1
2
63-
CN4005
MLX_52885_0404_40P
2
1000PF_J_50V
C4014
1
2
62-,60-
+V1.2L_BN
10-61-
+V3S_BN
1
D4001 DSLED_CL150YG
21
63-
SWTT_TC003_PS11AT_A
SW4003
1
C4046
0.1UF_16V
1
2
BAV99
D4000
2
3
C
E
1
SST3904
Q4002
B
2
C
3
1
E
63-
10-
10-,8-
63-
62-,60-
63-
SST3904
Q4001
2
B
3
63-
FIX_MASK
FIX9
62-
R4016
1.3K_1%
1
2
+V3A_BN
63-
+V5A_BN
FIX_MASK
FIX8
63-
S23
62-
63-
63-
S25
SCREW3.3_5_5P
62-,60-
62-,60-
FIX_MASK
FIX11
+V3A_BN
SCREW2.8_6_5P
55
6
67
78
8
99
S4
SCREW2.8_6_5P
36 36
37
37 38
38
39 39
4
4
40 40
41
G42
G
29
29
3
3
30
30 31
31 32
32 33
33 34
34 35
35
21 21
22 22
23 23
24 24
25
25 26
26
27 27
28
28
14 14
15
15 16
16
17 17
18 18
19
19
2
2
20 20
MLX_52885_0404_40P
CN4004
1
1
10 10
11 11
12 12
13
13
DSLED_CL150YG
D4002 21
270_5%
R4012
12
C4047
0.1UF_16V
1
2
R4013
270_5%
12
2
+VBATP_BN
+V1.5A_BN
+VCCP_BN
61-
62-
10-
+V3S_BN
SW4001
SWTT_TC003_PS11AT_A
1
2
0.1UF_16V
C4045
1
61-
63-
SCREW2_6_5P
S24
100K_5%R401112
S22
SCREW2_6_5P
63-
63-
60-
FIX_MASK
FIX10
+V1.8S_BN
63-
FIX_MASK
FIX7
330_5%
12
FIX_MASK
FIX12
62-,60-
62-,60-
60-
60-
2
61-
61-
62-
D4003 DSLED_CL150YG
21
R4015
+V3S_BN
SWTT_TC003_PS11AT_A
SW4000
1
2
270_5%
R4014
1
SWTT_TC003_PS11AT_A
SW4002 1
2
63-
63-
63-
63-
61-
SCAN_IN_BN(7)
SCAN_OUT_BN(8)
PWR_GOOD_3_BN
PWR_SWIN#_3_BN
63-
63-
LPC_FRAME#_3_BN
CLK_FWHPCI_3R_BN
LPC_AD_BN(0)
LPC_AD_BN(1)
LPC_AD_BN(2)
LPC_AD_BN(3)
SERIRQ_3_BN
CLKRUN#_3_BN
SCAN_OUT_BN(1)
PWR_LED#_3_BN
MCH_GOOD_BN
LAN_ON_3_BN
SLP_S3#_3R_BN
CODEC_RST#_ICH_BN
PHONE_BNFRAME_SYNC_ICH_BN
SDATA_IN1_ICH_BN
H_INIT#_BN
FWH_INIT#_3_BN
SCROLL_LED#_3_BN
FWH_WP#_3_BN
FWH_TBL#_3_BN
H_INIT#_BN
AC97_BIT_CLK_BN
KSCAN_IN_BN(5)
SCAN_OUT_BN(3)
KSCAN_IN_BN(1)
SDATA_OUT_ICH_BN
SCAN_OUT_BN(8)
SCAN_OUT_BN(1) KSCAN_IN_BN(5)
KSCAN_IN_BN(1)
SCAN_OUT_BN(3)
PCI_RESET2#_3_BN
SUS_STAT#_3_BN
LPC_DRQ1#_BN
PWR_SWIN#_3_BN
NUM_LED#_3_BN
CAPS_LED#_3_BN
NUM_LED#_3_BN
CAPS_LED#_3_BN
SCROLL_LED#_3_BN
SCAN_IN_BN(7)
![](asset-40.png)
VER Model Number Sheet of
LED & VOL BUTTON ON LED DAUGHTER BOARD
Size
TITLE
INVENTEC
EE2
6764
PC8803A02
LED & VOL BUTTON
DIAMOND
A3
(15/5)(15/5)
IR
Changed by Date Changed Time Changed
Engineer
Drawn by
R&D CHK
DOC CTRL CHK
MFG ENGR CHK
QA CHK
64-
LEDBOARD_GND
R6000
47_5%
12
David Du
David Du
10:59:01 amThursday, July 31, 2003
Q6002
BSS84
D
3
G
2
1
S
10UF_K_6.3V
C60021
2
64-
FIX_MASK
LEDBOARD_GND
64-
0.1UF_16V
C6008
1
2
64-
64-
TC010-PS11CET_B
SW6000
1
2
3
4
5
FIX13
3
D
2
G
S
1
R6008
270_5%
12 64-
64-
1
2
64-
D6006
DSLED_CL150YG
21
BSS84
Q6004
91
VCC
64-
64-
R6001
100K_1%
1
2
100K_1%
R6006
11
GND
7
GND
AGND 2
FIR_SEL
3
LEDA
10
MD0
4
5MD1
6
NC
8RXD
TXD
64-
64-
LEDBOARD_GND
LEDBOARD_GND
LEDBOARD_GND
LEDBOARD_GND
LEDBOARD_GND
64-
D6005
HSDL_3600_008
+V3S_LD
+V3A_LD
64-
R6003
270_5%
1
2
64-
64-
1
2
64-
Q6001
NDS7002A
D
3
G
2
1
S
64-
C60031
2
C6004
0.1UF_16V
1
2
4.7K_5%
R6009
12
SW6002
ALPS_SKQHFSE010_4P
12
34
64-
4.7UF_K_6.3V
+V3S_LD
+V3S_LD
R6004
270_5%
12
R6011
2.7_2010_1/2W
C6007
1
2
64-
LEDBOARD_GND
DSLED_CL150YG
D6003 21
LEDBOARD_GND
DSLED_CL150YG
21
C6006
0.1UF_16V
1
2
0.1UF_16V
LEDBOARD_GND
LEDBOARD_GND
FIX_MASK
FIX17
FIX15
FIX_MASK
LEDBOARD_GND
D6007
2
R6010
47K_5%
12
FIX16
FIX_MASK
FIX_MASK
FIX14
C6001
0.1UF_16V
1
2
LEDBOARD_GND
64-
270_5%
R6013
1
64-
64-
LEDBOARD_GND
D6004
CL_150TY_LED
21
64-
LEDBOARD_GND
+V3S_LD
2
47_5%
R6002
12
64-
+V3S_LD
LEDBOARD_GND
LEDBOARD_GND
LEDBOARD_GND
2
270_5%
R6007
12
0.1UF_16V
C6000
1
55
66
7
7
8
8
9
9
270_5%
R6012
1
2
2
20
20
21
G22
G
G23
G24
3
3
4
4
11
12
12
13 13
14 14
15
15 16
16
17 17
18 18
19
19
C6005
0.47UF_16V
1
2
MLX_52559_2092_20P
CN6000
1
1
10 10
11
G2
5
S1
S2 2
+V3A_LD
SML011BBT
D6001
21
64-
LEDBOARD_GND
LEDBOARD_GND
FIX18
FIX_MASK
NDC7002N
Q6000
D1 6
4
D2
G1
1
3
D6002
2
3
1
BAV99
D6000
2
3
1
2
SW6001 TC010-PS11CET_B
1
2
3
4
5
BAV99
64-
+V3S_LD
+V3A_LD
+V3A_LD
+V3A_LD
64-
100K_1%
R60051
SCAN_IN_LD(7)
SCAN_OUT_LD(1)
HDDASP#_3_LD
HDDASP#_3_LD
MBLED#_3_LD IR_SD_3_LD
IR_RX_3_LD
PWR_LED#_3_LD
BAT_LED#_3_LD
LED_WLAN_LINK_LD
EAPD_LD
BLUETOOTH_LED_LD
EAPD_LD
IR_TX_3_LD
BLUETOOTH_LED_LD
VOL_UP_LD
VOL_DN_LD
SCAN_IN_LD(7)
IR_TX_3_LD
IR_RX_3_LD
IR_SD_3_LD
SCAN_OUT_LD(1)
PWR_LED#_3_LD
BAT_LED#_3_LD
MBLED#_3_LD
VOL_UP_LD
VOL_DN_LD
LED_WLAN_LINK_LD
![](asset-41.png)
SHEET 20SHEET 22
1. ADD BYPASS CAPACITORS , C311, C313 (150UF)
SHEET 54
2. REMOVE C1671 C1673 C1674 C1675 THEN C1672 PIN2 CHAISY GND CHANGE TO DIGITAL GND
SHEET 20
7. Add 10K pull down RESISTOR to prevent leakage for ZV_LCDDATA(16:17)
Time Changed
INVENTEC
NOTE: Above items for ATI recommed
CHANGE LIST FEBRUARY 27
AFTER THE RC CIRCUIT TO PIN10 OF U2008
SHEET 29
1. MAKE A NOTE R1957 R1958 TO INSTALL M9+X OR M10 BE USED
2. Add SERIES RESISTORS DBI_LO(R198), DBI_HI(R197)
SHEET 31
1. CHANGE C1982 C1983 TO 10 PF THESE TWO CAPACITORS VALUSE CAN BE TUNED
2. ADD SERIES RESISTORS R237 R238 ON EACHOF THE TWO SIGNAL (DIMB_0 DIMB_1 )
SHEET 13
SHEET 32
1. ADD L21 TO POWER PIN( P8, Y8, AC11,AC20,Y23, L23,H20,H11)
TITLE
DOC CTRL CHK
1. ADD TWO SIGNAL AT CN1036 PIN6(CH_DATA) , PIN7(CH_CLK) THEN ADD TWO SERIES RESISTORS
9. Add SERIES RESISTORS STOP(R192) DEVSEL(R199) TRDY(R200) IRDY(R217) FRAME(R216)
Model Number
SHEET 10
MAKE A NOTES: THIS RAIL HAVE JUMPER TO SWITCH FOR +V1.5S FOR M10 , +V1.8S FOR M9+X
SHEET 33
1. CHANGE THE TITLE , THESE IS A TYPO" VEDIO". IT SHOULD BE " VIDEO"
2. MAKE A NOTE R1956 TO INSTALL M9+X OR M10 BE USED
1. Del PAD2 , PAD515 and to short power
1. Add SERIES RESISTORS on SB_STBS(R208), ADSTBS_0(R211), ADSTBS_1(R212)
SHEET 10
MAKE A NOTE TO ONLY INSTALL THESE RESISTORS FOR ELPIDA MEMORY
1. Add 0 OHM series resistor on the path of osc output to X’TAL and XTALOUT
CHANGE LIST FEBRUARY 15
SHEET 56
SHEET 58
1. ADD NOTE TO M9+X , M10 R153, R154 USED OR NOT
100 OHM TO THESE PIN
1. ADD U22 SCHMITT BUFFER FROM PIN2 R1096
2. Change CN7 (stick point) geoetric ( layout pattern)
1. Change CN2062 point name
SHEET 11
1.R1096 change from 10K to 200K and add CAP (0.01UF) to GND
SHEET 20
1. ADD BYPASS CAPACITORS C308, C309, C310 (220P)
SHEET 41
1.CHANGE USB POWER FROM +V5A TO +V5 TO MATCH RUBY SCH(REF.RUBY)
SHEET 25 26
SHEET 30
10. Add SERIES RESISTORS WBF(R205) RBF(R215) AD_STBF_0(R202) AD_STBF_1(R203) SB_STBF(R204)
11. R189 , R190 PIN2 TO GND
SHEET 36
1. Add R219 TO JUMP M10 OR M9+X
1. U509 -V19 (PM_VGATE/VRMPWRGD) change from PM_VGATE to SB_VGATE
Changed by Date Changed
1. Change for ATI M9+X , M10 dual footprint schematic
SHEET 38
2.ADD NOTE : R687&R1766 FOR M9+X OR M10 USED
CHANGE LIST FEBRUARY 21
1. ADD THE BLUETOOTH SIGNAL AT CN1020 PIN43(CH_DATA) , PIN36(CH_CLK)
SHEET 20
1. OPEN L12 AND L21 PUT BLM21A121S TO USED M9+X +V1.8S
SHEET 42
NOTE: For ATI power sequence
Drawn by
R&D CHK
2. Add CAP (OPEN) in Q25 pin3 to GND
MFG ENGR CHK
2. ADD THE CAP 10UF C91 PIN1 TO LINK Q26 (PIN1,2,5,6) C91 PIN2 TO GND
1. ADD RESISTOR 100K PULL UP TO +V3S ANOTHER PIN TO LINK Q53 PIN2(XMIT_OFF#)
Sheet
SHEET 49
1. Change R155 from 10K to 100K
SHEET 50
CHANGE LIST FEBRUARY 14
1. Rotate CN8 (the touch-pad conect):180 point of view and pin5,6 link to GND, pin7,8 link to CN7 pin3
Engineer
Size
2.CHANGE R1061 TO OPEN(REF.RUBY)
SHEET 13
1.CHANGE R1122 FROM 220K TO 100K (REF.RUBY)
SHEET 29
SHEET 11
2. Change AGPTEST DBI_LO & DBI_HI TO +V1.5ATIAGP RAIL TO MATCH RUBY
CHANGE LIST FEBRUARY 17
SHEET 32
SHEET 12
NOTE: Modify LAN signal to right
SHEET 29,30, 31, 32
3. Change R72 from 10K to 20K
SHEET 11
NOTE: For PCI_RESET, PCI_CLOCK , PM_VGATE TIMING
(ZV_LCDDATA(5:15), (18:19), ZV_LCDCNTL(0:3) )
4.Add TEST POINT in GPIO(4:7) GPIO(9:14)
SHEET 30
2. Add CAP (0.1UF) in R2024 pin1 to GND
1. R1122 change from 220K to 100K and add CAP(0.1UF) in R1122 pin1 to GND
CHANGE LIST FEBRUARY 12
QA CHK VER
SHEET 56
SHEET 63
SHEET 64
NOTE: For ATI power sequence
1. CHANGE DEPEND RESISTORS PACKAGE TO LAYOUT ROUTES
NOTE: Select frequency enter chalnnel
1.Change D21 for mechanical
1.Change SW4 for mechanical
SHEET 32
3.CHANGE L5/L4,&L12 TO MATCH RUBY SCH(REF.RUBY)
1.ADD L20 NFM41P11C204 TO MATCH RUBY SCH (REF.RUBY)
2.CHANGE L19,L1062, L1056, L1063, L1064, L1059,&L1060 TO MATCH RUBY SCH (REF.RUBY)
2. ADD INVERTER BETWEEN PIN H22 (GPIO39) AND U2038 (PIN26) TO MATCH RUBY SCH (REF.RUBY)
SHEET 50
1. CHANGE U2019 , U2329 FROM ADM1032 TO ADM1031 TWO PACKAGE THERMAL MONITOR
1. Change CN2068 for mechanical
SHEET 33
1. Add PM_VGATE DELAY CIRCUIT: U18, D23, R156, C90, C107
6. Add 1K pull down RESISTOR to prvent leakage for some ZV_LCDDATA, ZV_LCDCNTL pin
1. CHANGE GPIO42 TO VMEM_CFG3 AND PULL UP TO +V3S & 8.2K TO GROUNDTO MATCH RUBY SCH (REF.RUBY)
1. OPEN L12 AND L21 PUT BLM21A12. CHANGE SIGNAL NAME R252 PIN2 FROM PCI_RESET TO NPCI_RESET
CHANGE LIST FEBRUARY 20
1. U2010 PIN2(TON) TO ADD RESISTOR (OPEN) THEN PULL UP TO +VCCP
3. ADD 10K PULL-UP +V3S TO AUXWIN PIN AF26 (REF.RUBY) SHEET 13
1. CHANGE C66 VAULE FROM 22UF TO 68UF
David Du
David Du
10:59:06 amThursday, July 31, 2003EE2
6765
PC8803A02
CHANGE LIST
DIAMOND
A3
1.OPEN R2102 TO MATCH RUBY SCH (REF.RUBY)
of
SHEET 29
12. R72 PIN 1 TO LINK +V3S
8. R153,R154, change form 1K to 3K
NOTE: For +V3S power rail ( ATI- VREFG)
SHEET 30
2. Add U509 GPIO42 resistors R236 pull up +V3S and R237 pull down to GND
SHEET 38
NOTE: To chose memory type
CHANGE LIST FEBRUARY 23
1.Change C65 TO CONNECTED TO PIN2 OF R2024(REF.RUBY)
5. Add 1K pull down on GPIO8
![](asset-42.png)
2003/04/03 update
SHEET 45
1. ISOLATE PHONE USING A 2N7002 WITH DRAIN CONNECTED TO +V3S THROUGH A 10K PULL-UP ,
SHEET 52
1. CHANGE R1132 , R1133 FROM 47 OHM TO 22 OHM FOR A_CCLK & B_CCLK TIMING
SHEET 55
1.CHANGE R1460 FROM OPEN TO 1K FOR AC’97 CHOOSE FRQUENCE
SEE THE ATI REFERENCE DESIGN BOARD
2. ISOLATE PCSPKB_ICH_3 USING A 2N7002 WITH DRAIN CONNECTED TO +V3S THROUGH A 10K PULL-UP ,
SOURCE TO GROUND , & GATE TO PCSPKB_ICH_3 . PIN 2 OF C15 SHOULD BE CONNECTED TO DRAIN OF 2N7002 ,
WHICH FEEDS THE AUX INPUT OF CODEC
SHEET 46
1.CHANGE R126 VALUE TO 0 AND R125 VALUE CHANGE
SHEET44
1.CHANGE R1165_PIN-1 VOLTAGE FROM +5VA TO +V5
1. CAPS C120 AND C125 ON CLOCK LINES CHANGE TO 10NF
SHEET 31
SHEET36
Sheet of
TITLE
SHEET 50
2003/04/05 update
1. THE HPD CIRCUIT REQUIRES A 2.5V ZENER (IN PARALLEL WITH R1264) , AND ADDITIONAL 20K IN SERIES.
SHEET 57
2. KBC INITIAL NEED TO PULL DOWN 100K RESISTOR R1
1. R1049 FOR PCI_SERR#_3 PULL DOWN TO OPEN
4. REMOVE L3 AND TO SHORT
1. REMOVE L2 AND TO SHORT
SHEET 38
2003/03/26 update
SHEET13
2. ADD CAPACITORS C6015 , C6014 10UF FOR BCM MODIFY
AND HDD ACTIVITY LED TO JUST THE FIXED HDD
1. CHANGE P MOS , Q1050 HIGH CURRENT AND LOW RDS ON
SHEET 40
1. REMOVE R1409 , D1028 AND TO SHORT PCI_SERR#_3
2. U2 , U3 PIN_1(EN) CONNECT +5V
3. U2 , U3 PIN_5 CONNECT +V5A
1. ADD U4005 , R6016 , Q6005 , D6009 , C6015 , C6014 THIS CIRCUIT AND CN6001 TO SECOND FAN
SHEET 59
1. REMOVE CN22_PIN-5-RTCBAT
1. CHANGE P MOS Q1041 , Q1046 , Q10 , Q11 HIGH CURRENT AND LOW RDS ON
Size
Drawn by
R&D CHK
SHEET 40
SHEET 15
SHEET 34
1. CHANGE SW6001 AND SW6000 FOR MECHICNAL MODIFY
2. CHANGE D6005 I.R. SIZE FOR MECHICNAL MODIFY
SHEET 41
2. ADD CN6002 TO RCT CONNECTOR FOR MECHICNAL CHANGE
1. CHANGE VALUE C1358 , C1357 , C1398 FROM 0.01UF TO 0.1UF FOR BCM MODIFY
SHEET 55
1. ADD TWO 0.1uF DECAPS C6018 AND C6019 TO +V3S RAIL
SHEET 56
SOURCE TO GROUND , & GATE TO PHONE . PIN 1 OF C24 SHOULD BE CONNECTED TO DRAIN OF 2N7002 ,
WHICH FEEDS THE AUX INPUT OF CODEC
SHEET 47 , 64
3. ADD U4004 , D6008 , R6014 , C6011 , C6012 THIS CIRCUIT TO FINE_TUNE POWER ON SEQUENCE TIME
1. ISOLATE PCSPKB_3 USING A 2N7002 WITH DRAIN CONNECTED TO +V3S THROUGH A 10K PULL-UP ,
SOURCE TO GROUND , & GATE TO PCSPKB_3 . PIN 2 OF C28 SHOULD BE CONNECTED TO DRAIN OF 2N7002 ,
WHICH FEEDS THE AUX INPUT OF CODEC
1.CHANGE R1068 VALUE FROM 150K TO 10K AND R1070 VALUE
SHEET15
1.CHANGE R6015 VALUE FROM OPEN TO 33 AND R1361 VALUE
SHEET42
VER Model Number
FROM 20K TO 1.3K FOR AC DETECT LEVEL
SHEET45
1. ADD Q6004 TO PREVENT THE CURRENT FROM D6006 INTO HDDLED LOGIC OUTPUT
2003/03/24 update
SHEET 31 & 34
SHEET 50
2003/03/18 update
1. RNET FOR KAHUNA PROGRAMMING. NEED ONLY FOR FLASH RECOVERY SATURATION
Changed by Date Changed Time Changed
1. REMOVE R1126 , R1128 TO A_CCLKRUN# , B_CCLKRUN# SIGNAL PULL UP REPEAT
SHEET 5
1. ADD R6021 RESISTOR OPEN TO MODIFY OCP
SHEET 33
INVENTEC
1. REMOVE PWM_GOOD_3 SIGNAL DELETE R1419
1. CHANGING FDD ACTIVITY LED TO MULTI-BAY ACTIVITY LED
SHEET 17
1. REMOVE USB_OC#0 U2 , U3 PIN_2 TO OPEN
SHEET 52
1. CHANGE THE VALUE OF SERIAL TERMINATION RESISTOR OF QS LINE TO 22-HHMS
SHEET 40
1. R105 SHOULD BE OPEN TO FINE TUNE KBC POWER UP SEQUENTIAL
SHEET 63
1. ADD R6013 RESISTOR OPEN TO JUMP CLK_SIO14_3R & ADI48M
1. ADD C6013 18P CAPICATOR BYPASS TO LOW_BAT#_3 THIS SIGNAL
SHEET 64
DOC CTRL CHK
FOR SI SCHEMATIC CHANGE
QA CHK
1.REMOVE CN4001 RTC CONNECTOR , CN1010_PIN-5-RTCBAT FOR MECHICNAL CHANGE
SHEET 64
SHEET5
CHANGE TO OPEN FOR AC’97 FRQUENCE CHANGE 14.318MHZ
1. ADD SIX 0.1uF DECAPS C6021 , C6022 , C6023 , C6024 , C6025 , C6026 TO +V_LAN RAIL
2. ADD 0.1uF DECAPS C6019 TO +V3_LAN
MFG ENGR CHK
EE2 Thursday, July 31, 2003 10:59:10 am
David Du
David Du
A02 PC8803 66 67
DIAMOND
CHANGE LIST
A3
FROM 0 TO OPEN FOR SUPER I/O USED_NPCI_RESET
2003/03/30 update
1. FOR PSI# PULL HIGH +VCCP TO OPEN R1089
1. ADD DDR_CSB1# SIGNAL FOR 8M*32 VRAN USED
AND ADD R6016 RESISTOR DEPEND TO LINK U1018 & U1019 PIN M4
Engineer
2003/03/19 update
SHEET 20
1. CHANGE THE VALUE OF SERIAL TERMINATION RESISTORS ON THE DATA ,
DQM AND QS LINES TO 22-OHMS
SHEET 40
![](asset-43.png)
FOR MV B SCHEMATIC CHANGE 2003/08/21
1. CHANGE RESISTOR VALUE R1581 FROM 2.7K OHM TO 3.3K OHM FOR BATTERY SOLUTION
SHEET 6
1. CHANGE CAPACITOR VALUE C6016 FROM OPEN TO 12000PF FOR ATI RECOMMEND
SHEET 9
1. CHANGE CAPACITOR VALUE C187 FROM 0.1UF TO 39000PF FOR ATI RECOMMEND
SHEET 13
SHEET 5 57
FOR PVR SCHEMATIC CHANGE 2003/07/28
2.REMOVE L1014
SHEET 47
1. R1465 , R1449 CHANGE VALUE FROM OPEN TO 0 OHM
2. R1463 , R1448 CHANGE VALUE FROM 0 OHM TO OPEN
SHEET 57
1. change capacitor value C1268 from 22uF to 68uF
FOR MV B SCHEMATIC CHANGE 2003/08/13
1. CHANGE CAPACITOR VALUE C286 2200pF TO NON-INSTALL
SHEET 20
SHEET 32
1. ADD P-MOS Q6006 PIN4 LINK TO SLP_S3_5R , PIN5,8 LINK TO +AGP_V3S & PIN1, 2, 3, 6, 7, LINK TO +V3S
SHEET 38
1. ADD C6039 0.1UF BYPASS CAPACITOR .
SHEET 5 54
1. MOVE Q1009 , R1071 FOR LAYOUT PLACEMENT BECAUSE MECHANICAL COVER HAVE TO SHORT
SHEET 46
4. CHANGE C137 , C138 , C165 FROM OPEN TO 18PF CAPICATORS
1. ADD CAPACITORS C6031 , C6032 , C6033 , C6034 , C6035 , C6036 , C6037 100PF FOR EMI SOLUTION
2. CHANGE CAPACITOR VALUE C256 FRPM 0.1uF TO 100PF
SHEET 47
SHEET 56
1. CHANGE RESISTOR R6035 0 OHM TO C6040 0.01UF CAPACITOR .
1. CHANGE RESISTOR VALUE R134 FROM 1.21K TO 1.18K OHM.
2. CHANGE R1351 FROM 4.7OHM TO BLM11A601S FITTER BEAD (L4008) TO INCREASE THE SIGNAL VOLTAGE LEVEL TO MEETING THE IEEE SPEC.
SHEET 57
ADD R6021 , R6022 , R6023 , R6024 , RESISTORS TO PULL UP +V5S
2. CHANGE L4 , L5 , L6 FROM BEAD TO 0 OHM RESISTORS
SHEET 57
TO FIX INTEL WIRELESS CARD TO TOUCH CAPACITOR MECHANICAL ISSUE
FOR PVR SCHEMATIC CHANGE 2003/07/17
Engineer
2. ADD PAD1004 FOR THERMAL
SHEET 63
1. DELETE R4010 AND LED_POWER_SWITCH CIRCUIT CHANGE TO SWITCH CIRCUIT FOR MECHANICAL REQUIREMENT
2. SWAP MPCI_PWM THIS SIGNAL FROM C24 PIN1 TO Q1061 PIN 2 THAN Q1061 PIN 3 SWAP TO LINK R12 PIN 1
1. Change resistors value R6021,R6022 ,R6023 , R6024 from 4.7k ohm to 1k ohm for KBC PS2 microsoft keyboard to match .
SHEET 35
1. ADD C6020 , CC6021 , C6022 CAPACITORS PULL DOWN TO OPEN
SHEET 51
VER Model Number Sheet of
Size
TITLE
1. CHANGE C1435 FROM 4.7UF TO OPEN
2. CHANGE C5 , C6 , C23 FROM 0.1UF TO 0.01UF
1. ADD Q6005 NMOS TO CLEAR BACKWARD CURRENT
FOR PV SCHEMATIC CHANGE
FOR PVR SCHEMATIC CHANGE 2003/07/23
SHEET 9
1. R1582 , R1583 , R6019 , C1469 , Q1057 , Q1058 CHANGE TO OPEN FOR HP REQUIREMENT
SHEET 20
1. CN24 NOT TO USE
SHEET 59
1. CLEAR PAD1003 LINK TO GND FOR EMI SOLUTION
SHEET 64
1. IR_PIN11 LINK TO GND
1. ADD CAPACITOR C328 , C329 , C330 TO 150PF FOR EMI SOLUTION
SHEET 32
FOR PVR SCHEMATIC CHANGE 2003/07/31
Changed by Date Changed
1. CHANGE RESISTOR R134 VALUE FROM 1.24K TO 1.21K TO INCREASE THE SIGNAL VOLTAGE LEVEL TO MEETING THE IEEE SPEC.
1. CHANGE CAPACITOR VALUE C6027, C1335 FROM OPEN TO 100PF FOR EMI SOLUTION
2. ADD CAPACITOR C6030_100PF FOR EMI SOLUTION
SHEET 28
1. SWAP PHONE THIS SIGNAL FROM R12 PIN1 TO C24 PIN 2
FOR PVR SCHEMATIC CHANGE 2003/08/01
SHEET 35
1. change ferrite-bead from L4, L5 , L6 (BLM11B750S) to resistors R6037 , R6038 , R6039 0 ohm
SHEET 57
1. change ferrite-bead from L4007, L4006 , L4005 (111XJBC_110NH) to resistors R6040 , R6041 , R6042 0 ohm
2. change ferrite-bead from L8, L9 , L13 (111XJBC_39NH) to ferrite-bead L8 , L9 , L10 BLM11B750S
SHEET 9
add R6044(open) and D6009(BAT54C) between U1002-13 and U1002-5
1. CHANGE CAPACITOR C1075 , C1076 , C1077 , C1078 , C1079 , C1080 , SIZE FROM 0603 TO 0402
SHEET 56
R&D CHK
DOC CTRL CHK
MFG ENGR CHK
QA CHK
1. CHANGE CAPACITOR C230 IMPROVE VGA/VCC BYPASS CAPACITOR ESR
SHEET 54
INVENTEC
SHEET 45
LAYOUT NOTE:
1. CLK_CBIPCI_3R==>L5 CHANGE TO L3
2. CLK_MINIPCI_3R==>L5 CHANGE TO L3
FOR PV-R SCHEMATIC CHANGE 2003/07/15
Drawn by
SHEET 30
1. ADD R6026 , R6027 , R6028 75 OHM RESISTORS TO PULL DOWN TO CRT SIGNAL R G B
EE2 Thursday, August 21, 2003 11:48:22 am
David Du
David Du
A02 PC8803 67 67
DIAMOND
CHANGE LIST
A3
FOR MV B SCHEMATIC CHANGE 2003/08/15
FOR OCP circuit add R6043(0ohm) between U1002-8 and U1002-5
SHEET 5
SHEET 46
2. ADD CAPACITOR C6041 open between U1 pin 2 , pin 3 .
1. ADD CAPACITOR C6042_100PF between U1 pin 12 , pin 13 .
3. ADD CAPACITOR C6043_100PF between U1 pin 9 , pin 10 .
1. KB_DAT_5 , KB_CLK_5 , EM_DAT_5 , EM_CLK_5, THIS SIGNAL
2. CHANGE L8 , L9 , L13 FROM 110 OHM FITTER BEAD TO 39 NH FITTER BEAD
3. CHANGE L4007 , L4006 , L4005 FROM 75 OHM FITTER BEAD TO 110 NH FITTER BEAD
Time Changed
SHEET 58
1. MOVE R1057 , R1058 FOR LAYOUT PLACEMENT BECAUSE MECHANICAL COVER HAVE TO SHORT