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PD - 91257E

IRLML2402

HEXFET® Power MOSFET
l
l
l
l
l
l
l

Generation V Technology
Ultra Low On-Resistance
N-Channel MOSFET
SOT-23 Footprint
Low Profile (<1.1mm)
Available in Tape and Reel
Fast Switching

G 1

VDSS = 20V
3 D

S

RDS(on) = 0.25Ω

2

Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
and reliable device for use in a wide variety of applications.
A customized leadframe has been incorporated into the
standard SOT-23 package to produce a HEXFET Power
MOSFET with the industry's smallest footprint. This
package, dubbed the Micro3, is ideal for applications
where printed circuit board space is at a premium. The low
profile (<1.1mm) of the Micro3 allows it to fit easily into
extremely thin application environments such as portable
electronics and PCMCIA cards.

Micro3™

Absolute Maximum Ratings
Parameter
I D @ TA = 25°C
I D @ TA = 70°C
IDM
PD @TA = 25°C
VGS
dv/dt
TJ, TSTG

Max.

Continuous Drain Current, V GS @ 4.5V
Continuous Drain Current, V GS @ 4.5V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt ‚
Junction and Storage Temperature Range

Units

1.2
0.95
7.4
540
4.3
± 12
5.0
-55 to + 150

A
mW
mW/°C

V
V/ns
°C

Thermal Resistance
Parameter

RθJA

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Maximum Junction-to-Ambient „

Typ.
–––

Max.
230

Units
°C/W

1
12/14/11

IRLML2402
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
ΔV(BR)DSS/ΔTJ

Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient

RDS(on)

Static Drain-to-Source On-Resistance

VGS(th)
g fs

Gate Threshold Voltage
Forward Transconductance

IDSS

Drain-to-Source Leakage Current

V(BR)DSS

IGSS
Qg
Qgs
Qgd
t d(on)
tr
t d(off)
tf
Ciss
Coss
Crss

Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance

Min.
20
–––
–––
–––
0.70
1.3
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––

Typ.
–––
0.024
–––
–––
–––
–––
–––
–––
–––
–––
2.6
0.41
1.1
2.5
9.5
9.7
4.8
110
51
25

Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
0.25
VGS = 4.5V, ID = 0.93A ƒ
Ω
0.35
VGS = 2.7V, ID = 0.47A ƒ
–––
V
VDS = VGS, ID = 250µA
–––
S
VDS = 10V, ID = 0.47A
1.0
VDS = 16V, VGS = 0V
µA
25
VDS = 16V, VGS = 0V, TJ = 125°C
-100
VGS = -12V
nA
100
VGS = 12V
3.9
ID = 0.93A
0.62
nC VDS = 16V
1.7
VGS = 4.5V, See Fig. 6 and 9 ƒ
–––
VDD = 10V
–––
ID = 0.93A
ns
–––
RG = 6.2Ω
–––
RD = 11Ω, See Fig. 10 ƒ
–––
VGS = 0V
–––
pF
VDS = 15V
–––
ƒ = 1.0MHz, See Fig. 5

Source-Drain Ratings and Characteristics
IS
I SM

VSD
t rr
Q rr

Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge

Min. Typ. Max. Units
–––

–––

0.54

–––

–––

7.4

–––
–––
–––

–––
25
16

1.2
38
24

A
V
ns
nC

Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 0.93A, VGS = 0V ƒ
TJ = 25°C, IF = 0.93A
di/dt = 100A/µs ƒ

D

G
S

Notes:

 Repetitive rating; pulse width limited by

ƒ Pulse width ≤ 300µs; duty cycle ≤ 2%.

‚ ISD ≤ 0.93A, di/dt ≤ 90A/µs, VDD ≤ V(BR)DSS,

„ Surface mounted on FR-4 board, t ≤ 5sec.

max. junction temperature. ( See fig. 11 )

TJ ≤ 150°C

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2

IRLML2402
100

100

VGS
7.5V
5.0V
4.0V
3.5V
3.0V
2.5V
2.0V
BOTTOM 1.5V

10

1

0.1

1.5V
20μs PULSE WIDTH
TJ = 25°C
A

0.01
0.1

1

10

1

1.5V
0.1

R DS(on) , Drain-to-Source On Resistance
(Normalized)

2.0

I D , Drain-to-Source Current (A)

TJ = 25°C
TJ = 150°C
1

0.1

V DS = 10V
20μs PULSE WIDTH
2.5

3.0

3.5

VGS , Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics

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10

Fig 2. Typical Output Characteristics

10

2.0

1

VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

0.01

20μs PULSE WIDTH
TJ = 150°C
A

0.01
0.1

10

VDS , Drain-to-Source Voltage (V)

1.5

VGS
7.5V
5.0V
4.0V
3.5V
3.0V
2.5V
2.0V
BOTTOM 1.5V
TOP

I , Drain-to-Source Current (A)
D

I , Drain-to-Source Current (A)
D

TOP

A

4.0

I D = 0.93A

1.5

1.0

0.5

0.0
-60 -40 -20

VGS = 4.5V
0

20

40

60

A

80 100 120 140 160

TJ , Junction Temperature (°C)

Fig 4. Normalized On-Resistance
Vs. Temperature

3

IRLML2402
200

V GS, Gate-to-Source Voltage (V)

160

C, Capacitance (pF)

10

V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
C oss = C ds + C gd

Ciss
120

Coss

80

Crss
40

0
1

10

100

I D = 0.93A
VDS = 16V

8

6

4

2

0
0.0

A

1.0

2.0

3.0

A

4.0

Q G , Total Gate Charge (nC)

VDS , Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage

Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage

10

100

OPERATION IN THIS AREA LIMITED
BY R DS(on)
TJ = 150°C

I D , Drain Current (A)

ISD , Reverse Drain Current (A)

FOR TEST CIRCUIT
SEE FIGURE 9

1

TJ = 25°C

0.1

VGS = 0V

0.01
0.2

0.4

0.6

0.8

1.0

1.2

VSD , Source-to-Drain Voltage (V)

Fig 7. Typical Source-Drain Diode
Forward Voltage

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A

1.4

10

100μs
1

1ms

TA = 25°C
TJ = 150°C
Single Pulse

0.1
1

10ms

10

A

100

VDS , Drain-to-Source Voltage (V)

Fig 8. Maximum Safe Operating Area

4

IRLML2402
4.5V

QGS

RD

V DS

QG

VGS

QGD

D.U.T.

RG

VG

+

- VDD

4.5V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

Charge

Fig 9a. Basic Gate Charge Waveform

Fig 10a. Switching Time Test Circuit

Current Regulator
Same Type as D.U.T.

VDS
50KΩ

90%

.2μF

12V

.3μF

D.U.T.

+
V
- DS

10%
VGS

VGS
3mA

td(on)
IG

tr

t d(off)

tf

ID

Current Sampling Resistors

Fig 9b. Gate Charge Test Circuit

Fig 10b. Switching Time Waveforms

Thermal Response (Z thJA )

1000

100

D = 0.50
0.20
0.10
0.05

10

0.02
0.01

PDM
t1

SINGLE PULSE
(THERMAL RESPONSE)

1

0.1
0.00001

t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x Z thJA + TA

0.0001

0.001

0.01

0.1

1

10

100

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient

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5

IRLML2402
Peak Diode Recovery dv/dt Test Circuit
+

D.U.T

Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer

ƒ
+

‚
-

-

„

+


RG

•
•
•
•

Driver Gate Drive
P.W.

+

dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test

Period

D=

-

VDD

P.W.
Period
VGS=10V

*

D.U.T. ISD Waveform
Reverse
Recovery
Current

Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt

Re-Applied
Voltage

Body Diode

VDD

Forward Drop

Inductor Curent
Ripple ≤ 5%

ISD

* VGS = 5V for Logic Level Devices
Fig 12. For N-Channel HEXFETS

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6

IRLML2402
Micro3 (SOT-23) (Lead-Free) Package Outline
Dimensions are shown in millimeters (inches)
A

6

DIMENSIONS

5

D

SYMBOL

3
6

E

E1
1

B

5

A
A1
A2
b
c
D
E
E1
e
e1
L
L1
L2

0.15 [0.006] M C B A

2

e
e1

A
A2

H

C

4

L1

c
0.10 [0.004] C

A1

L2

3X b

3X L

0.20 [0.008] M C B A

7

Recommended Footprint

0.950

INCHES

MIN

MAX

MIN

MAX

0.89
0.01
0.88
0.30
0.08
2.80
2.10
1.20
0.95
1.90
0.40
0.54
0.25
0

1.12
0.10
1.02
0.50
0.20
3.04
2.64
1.40
BSC
BSC
0.60
REF
BSC
8











%6&
%6&


0.0004












0

REF
BSC
8

NOTES:
1. DIMENSIONING & TOLERANCING PER ANSI Y14.5M-1994
2. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
3. CONTROLLING DIMENSION: MILLIMETER.
4. DATUM PLANE H IS LOCATED AT THE MOLD PARTING LINE.
5. DATUM A AND B TO BE DETERMINED AT DATUM PLANE H.
6. DIMENSIONS D AND E1 ARE MEASURED AT DATUM PLANE H. DIMENSIONS DOES
NOT INCLUDE MOLD PROTRUSIONS OR INTERLEAD FLASH. MOLD PROTRUSIONS
OR INTERLEAD FLASH SHALL NOT EXCEED 0.25 MM [0.010 INCH] PER SIDE.
7. DIMENSION L IS THE LEAD LENGTH FOR SOLDERING TO A SUBSTRATE.
8. OUTLINE CONFORMS TO JEDEC OUTLINE TO-236 AB.

0.972

0.802

MILLIMETERS

2.742

1.900

Micro3 (SOT-23 / TO-236AB) Part Marking Information
Micro3 / SOT-23 Package Marking

W = (1-26) IF PRECEDED B Y LAS T DIGIT OF CALENDAR YEAR

Y = YEAR
W = WEEK
PART NUMBER

A YW LC
HALOGEN FREE
INDICATOR

LOT
CODE

PART NUMBER CODE REFERENCE:
A = IRLML2402
B =IRLML2803
C = IRLML2402
D = IRLML5103
E = IRLML6402
F = IRLML6401
G = IRLML2502
H = IRLML5203
Note: A line above the work week
(as shown here) indicates Lead-free

YEAR

Y

2001
2002
2003
2004
2005
2006
2007
2008
2009
2010

1
2
3
4
5
6
7
8
9
0

WORK
WEEK

W

01
02
03
04

A
B
C
D

24
25
26

X
Y
Z

W = (27-52) IF PRECEDED B Y A L ETT ER
YEAR

Y

2001
2002
2003
2004
2005
2006
2007
2008
2009
2010

A
B
C
D
E
F
G
H
J
K

WORK
WEEK

W

27
28
29
30

A
B
C
D

50
51
52

X
Y
Z

Note: For the most current drawing please refer to IR website at http://www.irf.com/package

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7

IRLML2402
Micro3™ Tape & Reel Information
Dimensions are shown in millimeters (inches)
2.05 ( .080 )
1.95 ( .077 )

1.6 ( .062 )
1.5 ( .060 )
4.1 ( .161 )
3.9 ( .154 )

TR

FEED DIRECTION

1.85 ( .072 )
1.65 ( .065 )

3.55 ( .139 )
3.45 ( .136 )

4.1 ( .161 )
3.9 ( .154 )

1.32 ( .051 )
1.12 ( .045 )

8.3 ( .326 )
7.9 ( .312 )

0.35 ( .013 )
0.25 ( .010 )

1.1 ( .043 )
0.9 ( .036 )

178.00
( 7.008 )
MAX.

9.90 ( .390 )
8.40 ( .331 )
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package

Data and specifications subject to change without notice.

IR WORLD HEADQUARTERS: 101N.Sepulveda Blvd, El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/2011

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