OEM MICRONOTES
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TABLE OF CONTENTS
uNOTE NO.
TITLE
DATE
PAGE NO.
001
MUL, DIV, & ASH Instruction for the
FALCON and the FALCON-PLUS
13-Apr-82
1
002
Block Mode DMA
01-Jun-83
5
003
Compatible Bootstrap for the LSI-11/73
28-Nov-83
25
004
LSI-11/73 Upgrade Paths
28-Nov-83
27
005
Q22 Compatible Options
23-Apr-84
33
006
Differences Between the LSI-ll/73
and LSI-11/23
23-Apr-84
39
007
User Defined Memory Maps for the FALCON
and the FALCON-PLUS
01-May-84
47
008
Memory Management and the LSI-l1/73
22-Jun-84
61
009
Cache Concepts and the LSI-l1/73
02-Jul-84
73
010
MicroVAX I/O Programming
27-Jul-84
79
011
LSI-11/73 Advanced Memory Management
04-0ct-84
85
012
OMA on the Q-bus
09-0ct-84
97
013
Run-time System Performance Evaluation
Using MicroPower/Pascal V 1.5
09-0ct-84
101
014
Using Fortran Routines In A
VAXELN/pascal Environment
16-0ct-84
107
015
Q-bus Hardware Bootstrap
16-0ct-84
111
016
KXTI1-CA Software Development Tools
16-0ct-84
115
017
LSI-11/23 ECO History
19-Nov-84
123
018
Programming the KXTII-CA
28-Dec-84
131
019
Disabling RAM on the MXV11-iBF
10-Jan-85
155
I
DM.~
Controller
uNOTE NO.
DATE
TITLE
PAGE NO.
020
Differences between the Mxv11-A
and MXV11-B
10-Jan-85
159
021
Floating Point Consideration
on MicroVAX I
10-Jan-85
161
022
Differences Between the MicroVAX I and
MicroVAX II CPUs
28-Apr-85
163
023
MicroVAX I to MicroVAX II Upgrade Issues
28-Apr-85
177
024
MicroVAX Instruction Set Differences
28-Apr-85
183
025
FPJ11-AA Compatibility with the
LSI-11/73 (KDJ11-A)
28-Jun-85
195
026
The MicroVAX Multicomputing Capability
28-Jun-85
197
027
Using Messages with VAXELN
28-Jun-85
211
028
MSV11-Q/M/J Memory Comparisons
28-Jun-85
217
029
Q-bus Expansion Concepts
28-Jun-85
221
030
The Private Memory Interconnect between
the KDJ11-B and the MSV11-J
28-Jun-85
227
031
MSV11-QA Revision Differences
28-Jun-85
237
032
KXT11-C Parallel I/O Programming
28-Jun-85
247
033
System Configuration of DL-type Devices
28-Jun-85
289
034
Programming the KXT11-C Multiprotocal SLU
19-Jul-85
303
035
Backplane Expansion/Termination
19-Jul-85
327
036
MicroVMS Revealed
19-Jul-85
335
037
In Search of NanoVMS
19-Jul-85
361
038
DECnet Downline Loading
26-Jul-85
369
039
Differences between KDJ11-A and KDJ11-B
08-Aug-85
379
040
FPJ11 Theory of Operation
17-Sep-85
385
041
Device Ordering Chart for Q-bus Systems
17-Sep-85
389
II
APPENDIX A
ORIGINAL MICRONOTES - TABLE OF CONTENTS
A1
APPENDIX B
SUBJECT INDEX
B1
III
·I
uNOTE # 001
Title: MUL,DIV and ASH Instruction for the FALCON
and the FALCON-PLUS
Date: 13-APR-82
Originator: Charlie Giorgetti
Page 1 of 4
There is no hardware support for the EIS, FIS, or FPP instruction sets.
For FALCON SBC-ll/21 applications that need the ability to perform the
EIS instructions MUL, DIV, and ASH, equivalent software routines can be
substituted. These callable routines do not do any form of error
checking.
A user should be aWarE! that extensive use of these software
routines for hardware instructi()ns will have
impact
on
system
performance. These routines can bE! incorporated into an application and
called as a subroutine. The calling sequence for the subroutines can be
set-up in a macro. The followin9 is a list of each of the subroutines
and the macros that are used to set-up and call the software MUL, DIV,
and ASH routines.
1
uNOTE # 001
Page 2 of 4
The following macro and subroutine can be
instruction in software:
• MACRO
SMUL
used
to
perform
the
MUL
A,B,HI,LO
MOV
MOV
JSR
MOV
A,-(SP)
B,-(SP)
PC,$MUL
(SP)+,HI
MOV
(SP)+,LO
Push a multiplier onto the stack
Push the other multiplier as well
Call the MUL subroutine
Get the most significant part of
the result
Get the least significant part of
the result
.ENDM
$MUL: : MOV
MOV
MOV
MOV
CLR
10$: ROR
ROR
BCC
ADD
CLC
20$: DEC
BNE
TST
MOV
MOV
MOV
MOV
RTS
RO,-(SP)
R1,-(SP)
10(SP),R1
#21,-(SP)
RO
RO
Rl
20$
10(SP),RO
Save some work registers
Obtain the value of A from the stack
Initialize the shift counter
; Initialize the high 16-bit accumulator
Perform multiplication
(SP)
10$
(SP)+
R1,10(SP)
RO,6(SP)
(SP)+,Rl
(SP)+,RO
PC
Bump the shift counter
Not done ?
Romove the counter from the stack
Save the low 16-bit value on the stack
Save the high 16-bit value on the stack
Restore the work registers
Return
2
uNOTE # 001
page 3 of 4
The following macro and subroutine can be
instruction in software:
used
to
perform
the
DIVSOR,DIVHI,DIVLO,REM,QUO
.MACRO
SDIV
MOV
MOV
MOV
JSR
MOV
MOV
DIVSOR,-(SP);
DIVHI ,-( SP) i
DIVLO ;-( SP) i
PC,$DIV
;
(SP)+,REM
(SP)+,QUO
Push the divisor onto the stack
Push the upper 16-bits of the dividend
Push the lower 16-bits of the dividend
Call the DIV subroutine
Get the remainder
Get the quotient
.ENDM
$DIV:: MOV
MOV
MOV
MOV
MOV
MOV
MOV
CLR
MOV
1$: ASL
ROL
ROL
CMP
BLO
SUB
I~C
2$: DEC
BNE
TST
MOV
MOV
MOV
MOV
MOV
MOV
MOV
RTS
DIV
.RS ,-(SP)
R4,-(SP)
R3,-(SP)
RO,-(SP)
14.(SP),R3
12.(SP),R4
10. (SP) , RS
RO
#32.,-(SP)
RS
R4
RO
RO,R3
2$
R3,RO
RS
(SP)
1$
(SP)+
RO,12.(SP)
RS,14.(SP)
(SP)+,RO
(SP)+,R3
(SP)+,R4
(SP)+,RS
(SP)+,(SP)
PC
; Get some work registers
Get the divisor from the stack
i Get the high 16-bits of the dividend
as well as low 16-bits
i Clear an accumulator
; Shi :Et counte r
Perform the division
Not done ?
; Remove the counter from the stack
Store the remainder on the stack
; store the quotient as well
Restore the work registers
Update the return PC
Return
3
uNOTE .# 001
Page 4 of 4
The following macro and subroutine can be
instruction in software:
used
to
perform
. MACRO
SASH
MOV
MOV
JSR
MOV
COUNT,-(SP) ; Push the shift count
Push what is to be shifted
VAL,-(SP)
Call the ASH subroutine
PC,$ASH
Get the results of the shift
(SP)+,VAL
the
COUNT,VAL
.ENDM
$SASH: : MOV
MOV
MOV
MOV
BIC
BEQ
CMP
BGT
5$: ASL
DEC
BNE
BR
10$: NEG
BIC
11$: ASR
DEC
BNE
20$: MOV
MOV
MOV
MOV
RTS
~
RO,-(SP)
R1,-(SP)
6(SP),RO
8.(SP),R1
#"C<77>,R1
20$
R1,#31.
10$
RO
R1
5$
20$
R1
#"C<77>,R1
RO
R1
11$
RO,8.(SP)
(SP)+,R1
(SP)+,RO
(SP)+,(SP)
PC
Get a couple of work registers
RO - value to be shifted
R1 - direction and shift count
Get out if no shifting
; What direction is the shift
go to the corection direction shift
Store the shifted result on the stack
Restore the work registers
update the return PC
Return
4
ASH
uNOTE # 002
Title: Block Mode DMA
Date: 01-JUN-83
Originator: Scott Tincher and Mike Collins
Page 1 of 20
What is Block Mode DMA?
Block Mode DMA is a method of data transfer which increases throughput
due to the reduced handshaking necessary over the Q-bus.
In order to
implement Block Mode DMA both the master and slave devices must
understand the block Mode protocol.
If either device does not have
Block Mode capability the transfers proceed via standard DATI or DATO
cycles.
Conventional Direct Memory Access on the Q-bus
Under conventional DMA operations, after a DMA device has become bus
master, it begins the data transfers. This is accomplished by gating an
address onto the bus followed by the data being transferred to or from
the memory device.
If more than one transfer is performed by the
temporary bus master, the address portiort of the cycle must be repeated
for each data transfer.
Block Mode Direct Memory Access on the Q-bus
Under block Mode DMA operations an address cycle is followed by multiple
word transfers to sequential addresses. Therefore data throughput is
increased due to the elimination of the address portion of each transfer
after the initial transfer.
5
uNOTE :1 002
Page 2 of 20
There are two types of block Mode transfer, DATBI
(input) and DATBO
(output).
An overview of what occurs during each type of block Mode
transfer is outlined in figures 1 (DATBI, Block Mode input.) and 2
(DATBO, block mode output).
indicates a
In the following discussion the signal prefix T(Transmit)
bus driver input and the signal prefix R(Receive) indicates a bus
receiver output.
DATBI Bus Cycle
Before a DATBI block mode transfer can occur the DMA bus master device
must request control of the bus. This occurs under conventional Q-bus
protocol ..
o REQUEST BUS
The bus master device requests control of the bus
TDMR ..
by
asserting
o GRANT BUS CONTROL
The bus arbitration logic in the CPU asserts the DMA grant
signal TDMGO 0 nsec minimum after TDMR is received and 0 nsec
minimum after RSACK negates (if a DMA device was previous bus
master) .
o ACKNOWLEDGE BUS MASTERSHIP
The DMA bus master device asserts TSACK 0 nsec minimum after
receivin~ ,RDMGI, 0 nsec minimum after the negation of RSYNC and
o nsec mlnlmum after the negation of RRPLY. The DMA bus master
device negates TDMR 0 nsec minimum after the assertion of TSACK.
o TERMINATE GRANT SEQUENCE
The bus arbitration logic in the CPU negates TDMGO 0 nsec
minimum after receiving RSACK. The bus arbitration logic will
also negate TDMGO if RDMR negates or if RSACK fails to assert
within 10 usec ('no SACK timeout').
6
uNOTE # 002
Page 3 of 20
o EXECUTE A BLOCK MODE DATBI
T~ANSFER
o ADDRESS DEVICE MEMORY
a) The address is asserted by the bus master on TADDR<21:00>
along with the negation of TWTBT.
b) The bus master asserts TSYNC
gating the address onto the bus.
150
nsec
minimum
after
o DECODE ADDRESS
The appropriate memory device recognizes
respond to the address on the bus.
that
it
must
o REQUEST DATA
a) The address is removed by the
bus
master
from
TADDR<21:00> 100 nsec minim,um after the assertion of TSYNC.
b) The bus master asserts the first TDIN
after asserting TSYNC.
100
nsec
minimum
c) The bus master asserts TBS7 50 nsec maximum after
asserting TDIN for the first time. TBS7 remains asserted
until 50 nsec maximum after the assertion of TDIN for the
last time.
In each case, TBS7 can be asserted or negated as
soon as the conditions for asserting TDIN are met.
The assertion of TBS7 indicates the bus master is requesting
another read cycle after the current read cycle.
o SEND DATA
a) The bus slave asserts TRPLY 0 nsec m~n~mum (8000
maximum to avoid a bus timeout) after receiving RDIN.
nsec
b) The bus slave asserts TREF concurrent with TRPLY if,
and
only if, it is a block mode device which can support another
RDIN after the current RDIN.
NOTE
Block mode
boundaries
transfers
7
must
not
cross
16
word
uNOTE # 002
Page 4 of 20
c) The bus slave gates TDATA<15:00> onto the bus 0 nsec
minimum after receiving RDIN and 125 nsec maximum after the
assertion of TRPLY.
o TERMINATE INPUT TRANSFER
a) The bus master receives stable RDATA<15:00> from 200 nsec
maximum after recelvlng RRPLY until 20 nsec minimum after
the negation of RDIN.
(The 20 nsec minimum represents total
minimum
receiver
delays
for RDIN at the slave and
RDATA<15:00> at the master.)
b) The bus master
receiving RRPLY.
negates
TDIN
200
nsec
minimum
after
0
nsec
minimum
after
o OPERATION COMPLETED
a)
The bus slave negates TRPLY
receiving the negation of RDIN.
b) If RBS7 and TREF are both asserted when TRPLY negates,
the bus slave prepares for another DIN cycle.
RBS7 is
stable from 125 nsec after RDIN is received until 150 nsec
after TRPLY negates.
c) If TBS7 and RREF were both asserted when TDIN neg~t~d,
the bus master asserts TDIN 150 nsec minimum after recelvlng
the negation of RRPLY and continues with timing relationship
'SEND DATA' above. RREF is stable from 75 nsec after RRPLY
asserts until 20 nsee minimum after TDIN negates.
(The 0
nsee mlnlmum represents total minimum receiver delays for
RDIN at the slave and RREF at the master.)
NOTE
The bus master must limit itself to not more than
eight transfers unless it monitors RDMR.
If it
monitors RDMR, it may perform up to 16 transfers as
long as RDMR is not asserted at the end of the
seventh transfer.
8
uNOTE # 002
Page 5 of 20
o TERMINATE BUS CYCLE
a) Ie RBS? and TREF were not both asserted when TRPLY
negated,
the bus slave removes TDATA<15:00> from the bus 0
nsec minimum and 100 nsec maximum after negating TRPLY.
b) If TBS? and RREF were not both asserted when TDIN negated
the
bus master negates TSYNC 250 nsec minimum after
receiving the last assertion of RRPLY and 0 nsec minimum
after the negation of that RRPLY.
o RELEASE THE BUS
a) The DMA bus master negates TSACK 0 nsec after negation of
the last RRPLY.
b) The DMA bus master negates TSYNC 300 nsec
it negates TSACK.
maximum
after
c) The DMA bus master must remove RDATA<15:00>,
TBS?, and
TWTBT from the bus 100 nsec maximum after clearing TSYNC.
o RESUME PROCESSOR OPERATION The bus arbitration logic in the CPU
enables processor-generated TSYNC or will issue another bus
grant (TDMGO) if RDMR is asserted.
9
uNOTE # 002
Page 6 of 20
Figure 1 - DATSI CYCLE
MEMORY
I/O DEVICE
PROCESSOR
Request Bus
5
Assert TDMR
Grant Bus Control <
. Near end of the current bus
cycle (RRPLY is negated) assert
TDMGO and inhibit new processor
generated TSYNC for the duration
ope~:
of the DMA
I
Acknowledge Bus Mastership
· Receive RDMGO
· Wait for negation of RSYNC and RRPLY
· Assert TSACK
Negate TDMR
V
Terminate Grant Sequence
DMA
(DATSI) Data Transfer
Address Device Memory
· Assert address on TADDR<21:00>
· Assert TSYNC
· Negate TWTBT ~
~>
Decode Address
. Store "Device
Selected" operation
10
uNOTE # 002
Page 7 of 20
Figure 1 - DATSI CYCLE (continued)
I/O DEVICE
PROCESSOR
r--->
MEMORY
Request Data
· Remove address from TADDR<21:00>
· Assert TDIN
· Assert TBS7 (request for an
additional DIN cycle after
the curre!nt one
L _____ >
Send Data
· Data on TDATA<15:00>
· Assert TRPLY
· Assert TREF (to
indicates block
mode capability)
Terminate' Input <--------'1
Transfer
· Accept data and respond
by nega,ting TDIN
L ______
> Operation Completed
. Negate TRPLY
1
yes
are
~----------------------~RBS7 & TREF
Asserted
?
,------'
I
V
11
no
uNOTE # 002
Page 8 of 20
Figure 1 - DATBl CYCLE (continued)
I/O DEVICE
PROCESSOR
Terminate Bus Cycle
and Release the Bus
I
· Negate TSACK
· Negate TSYNC
· Remove TDAL, TBS?, and,
TWTBT from the Bus
V
Resume Processor Operation
. Enable processor generated TSYNC or
issue another grant if RDMR is asserted
12
MEMORY
uNOTE #002
Page 9 of 20
T
R DMG
....._--,-""""
T SAO:
T/R D.AL
__________- J
R/T
100 ns
\
T O:N
:15
'
I
~ ~-.~\ \\\)\\~
~
RE:
"-----'r
--------------~------~~ ~
\
ns ::tax
,.,. 35_7_ _
10 \ \ \ \ " \ \ \ \ \ \ \ \\\\\S\\S\\\\\\
~iminq at slave device.
- • bus driver input
~ • Bus rece~ver ou:~~~
DA,7SI
13
uNOTE #002
Page 10 of 20
THIS PAGE INTENTIONALLY LEFT BLANK
14
uNOTE #002
page 11 of 20
'!' DATA
R ADDR
ns :nax ____ 1
~----~--~--~----------------------~--~
R SYNC
R
D!~
\
t
/
'L
!
\
/
R 857
\
slave dev~ce.
7 • bus driver in~ut
~ • Sus rece~ver OU~?~:
~~:n~ng
a~
D ATE
15
uNOTE #002
page 12 of 20
THIS PAGE INTENTIONALLY LEFT BLANK
16
uNOTE # 002
Page 13 of 20
DATBO Bus Cycle
DATBO Bus cycles Before a block mode transfer can occur the DMA bus
master device must request control of the bus. This occurs under
conventional Q-bus protocol.
o REQUEST BUS The bus master device requests control of the bus by
asserting TDMR.
o GRANT BUS CONTROL The bus arbItration logic in the CPU asserts
the DMA grant signal TDMGO 0 nsec minimum after RDMR is received
and 0 nsec minimum after TSACK negates (if a DMA device was
previous bus master).
o ACKNOWLEDGE BUS MASTERSHIP The DMA bus master device asserts
TSACK 0 nsec minimum after receiving RDMSI, 0 nsec minimum after
the negation of RSYNC and 0 nsec minimum after the negation of
RRPLY.,
The DMA bus master device negates TDMR 0 nsec minimum
after the assertion of TSACK.
o TERMINATE GRANT SEQUENCE The bus arbitration logic in the CPU
negates TDMGO 0 nsec minimum after receiving RSACK. The bus
arbitration logic will also ne9ate TDMGO if RDMR negates or if
RSACK fails to assert within 10 usec ('no SACK timeout').
o EXECUTE A BLOCK MODE DATBO TRANSFER
o ADDRESS DEVICE MEMORY
a) The address is asserted by the bus master on TADDR<21:00>
along wi th the assertion of T'WTBT.
b) The bus master asserts TSYNC
gating the address onto the bus.
150
nsec
minimum
after
o DECODE ADDRESS The appropriate memory device recognizes that
it must respond to the address on the bus.
o SEND DATA
a) The bus master gates TDATA<15:00> along with
nsee minimum after the assertion of TSYNC.
negated.
b) The bus master asserts the first TDOUT 100
after gating TDATA<15,: 00>.
NOTE
During DATBO cycles TBS7 is undefined
17
TWTBT 100
TWTBT is
nsec
minimum
uNOTE # 002
Page 14 of 20
o RECEIVE DATA
a) The bus slave receives stable data on RDATA<15:00> from
25 nsec minimum before receiving RDOUT until 25 nsec minimum
after receiving t~e negation of RDOUT.
b) The bus slave
receiving RDOUT.
asserts
TRPLY
0
nsec
minimum
after
c) The bus slave asserts TREF concurrent with TRPLY if,
and
only if, it is a block mode device which can support another
RDOUT after the current RDOUT.
NOTE
Blockmode transfers
boundaries
must
not
cross
16
o TERMINATE OUTPUT TRANSFER The bus master negates
nsec minimum after receiving RRPLY.
word
TDOUT
150
o OPERATION COMPLETED
a)
The bus slave negates TRPLY
receiving the negation of RDOUT.
0
nsec
minimum
after
b) If RREF was asserted when TDOUT negated and if the bus
master wants to transfer another word, the bus master gates
the new data on TDATA<15:00> 100 nsec minimum after negating
TDOUT.
RREF is stable from 75 nsec maximum afterRRPLY
asserts until 20 nsec minimum after RDOUT negates.
(The 20
nsee minimum represents minimum receiver delays for RDOUT at
the slave and RREF at the master).
c) The bus master asserts TDOUT 100 nsec minimum after
gating new data on TDATA<15:00> and 150 nsec minimum after
receiving the negation of RRPLY.
The cycle continues with
the timing relationship in 'RECEIVE DATA' above.
NOTE
The bus master must limit itself to not more than
eight transfers unless it monitors RDMR.
If it
monitors RDMR, it may perform up to 16 transfers, as
long as RDMR is not asserted at the end of the
seventh transfer.
o TERMINATE BUS CYCLE
a). If RREF was not asserted when RRPLY negated or if the bus
master has no additional data to transfer, the bus master
removes data on TDATA<15:00> from the bus 100 nsec minimum
after negating TDOUT.
18
uNOTE # 002
Page 15 of 20
b) If RREF was not asserted when TDOUT negated the bus
master negates TSYNC 275 nsec minimum after receiving the
last RRPLY and 0 nsec minimum after the the negation of the
last RRPLY.
o RELEASE THE BUS
a) The DMA bus master negates TSACK 0 nsec after negation of
the last RRPLY.
b) The DMA bus master negate!s TSYNC 300 nsec
it negates TSACK.
maximum
after
c) The DMA bus master must remove TDATA,
TBS7,
and
from the bus 100 nsec maximum after clearing TSYNC.
TWTBT
o RESUME PROCESSOR OPERATION The! bus arbitration logic in the CPU
enables processor-generated TSYNC or will issue another bus
grant (TDMGO) if RDMR is asserted.
19
uNOTE # 002
Page 16 of 20
Figure 2 - DATBO CYCLE
I/O DEVICE
PROCESSOR
MEMORY
Request Bus
. Assert TDMR
Grant Bus Control
. Near the end of the current bus
cycle (RRPLY is negated) assert
TDMGO and inhibit new processor
generated TSYNC for the duration
of the DMA operation.
~>
I
Acknowledge Bus Mastership
· Receive RDMG
· Wait for negation of RSYNC
and RRPLY
· Assert TSACK
Negate TDMR
V
Terminate Grant Sequence
. Negate TDMGO and wait for DMA
operation to be completed.
~I--------_>
Execute A Block Mode DMA
(DATBO) Data Transfer
Address Memory
· Assert Address on TADDR<21:00>
· Assert TWTBT
· Assert TSYNC ~
L->
Decode Address
. Address match
selects device
20
uNOTE i 002
Page 17 of 20
Figure 2 - DATBO CYCLE (continued)
PROCESSOR
I/O DEVICE
MEMORY
r----> Send Da ta
· Assert TDATA <15:00>
· Negate TWTBT
· Assert TDOUT ~
L>
Receive Data
· Accept data and
RWTBT
• Assert TRPLY
• Assert TREF
(Indicates block
mO
Operation Completed
. Negate TRPLY
I
yes
Does Master
Wish to Transfer
More Data ?
-
I
<
Terminate Bus Cycle and
yes
is RREF
Asserted ?
no
<------~
Release the Bus
,.
. Negate TSACK
. Negate TSYNC
Remove TDAL, TDAL,TBS7, and TWTBT
from the Bus
Resume Processor Operation
. Enable processor generated TSYNC
(processor is bus master) or issue
another grant if RDMR is asserted
21
uNOTE #002
Page 18 of 20
THIS PAGE INTENTIONALLY LEFT BLANK
22
uNOTE #002
Page 19 of 20
::::~~~-.r-'~-------------------------------------------rc~~~~~~~
~~~~~----------.---------------------------------\
TD~
~ :~3 ~~-~-~~~7~A---~X~__-_:_A_T_A_ _~(~~~_ _
R/T
T
_
__
T SACK
------------ ~5JnS~'1~J~O~ns~----·------------~--------------r_tt::J
SYNC \'..\...\.....____-+_m.:.__
"
",,-n ~OOns
H\(,:
--.J1oons)
~
-----~r__-~~
JOt~
\
)15~. ~~ I -,-----
R R?:'Y
-t---__-t___•
?-':":.? _ _ _ _ _ _
/
f
\
' -_ _ _-
!
\L-__________________-
_ _ _ _ _ _ _1
T fITET
'---~\\~._________
1
~------------_t----------~----.
~
\loon'l
/
~~~ng
at master =eVl:e.
T • Sus driver in;:u": .
R a Bus receiver out;:u~
23
CArBO
uNOTE i002
Page 20 of 20
R
~R
-
R SYNC
AJ:)OA
X
X
R DATA
R DATA
A
\
!
R DOur
-
T RPLY
.....I. REF
- L
R
-/
WTB~r
"
:""NDEFIm::J
R aS1
\
':'illlinq at slave devic:: ••
T n Bus driver input
R n Bus rec::eiver output
DATIO
24
uNOTE #003
Title: Compatible Bootstraps for the LSI-11/73
Date: 28-NOV-83
Originator: Mike Collins
Page 1 of 2
The LSI-l1/73 (KDJ11-AA) is a high performance CPU for the Q-Bus.
It is
a CPU only, which means that there is no boot capability on the module
itself. Therefore a boot module must be selected to work with the
LSI-11/73.
This uNOTE will discuss the bootstrap modules which can be used with the
11/73.
There are 4 possible modules which can be used for bootstrap.
They are : MXV11-BF w/MXV11-B2 boot ROMs
MRV11-D w/MXV11-B2 boot ROMs
MXV11-AA or -AC w/MXV11-A2 boot ROMs
BDV11
For an LSI-l1/73 based system to be Field Serviceable the bootstrap code
must execute a cache memory diagnostic on power-up.
The only boot code
which satisfies this requirement is found in the MXV11-B2 boot ROMs.
Therefore an LSI-11/73 based, Field Serviceable system must use either
the MXV11-BF w/MXVII-B2 ROMs or the MRVII-D w/MXVII-B2 ROMs.
NOTE
The MXVII-B2 ROMs will not work on the MXVII-A module.
MXVII-BF or MRVII-D w/MXVII-B2 ROft1:s
The Mxvl1-BF w/MXVI1-B2 ROMs is the preferred choice since this module
has 2 asynchronous serial lines as well as 128Kb of dynamic RAM in
addition to the boot capability. However, if your application does not
need the extra serial lines and RAM, an alternate choice would be the
MRV11-D w/MXV11-B2 ROMs.
The MXVI1-B2 ROMs will boot the following devices :
RL01 / RL02 (DL)
RX01 / RX02 (DX,DY)
TU58 (DD)
TSV05 (MS)
MSCP type Devices e.g. RD51, RXSO (DU)
DECnet via DPVll, DLV11-E, DLV11-F, DUVl1
25
uNOTE # 003
Page 2 of 2
NOTE
The MXV11-BF is not supported by RSTS due to its
non-parity memory.
An alternative configuration would
be to use the MRV11-D with the MXV11-B2 boot ROMs, and a
DLV11-J or other DLV11 serial line device.
The remaining 2 boot modules do NOT have the necessary cache
diagnostic code to make an 11/73 based system Field Serviceable.
memory
Below is a list of all of
remaining boot modules.
the
the
KNOWN
WORKING
bootstraps
for
MXV11-A w/MXV11-A2 ROMs
working bootstraps
RLOl
RX01
TUS8
TUS8
/ RL02
/ RX02
conventional boot
standalone boot
WARNING
If the MXV11-A is used in a 22 bit system the
RAM must be disabled. Refer to uNOTE #106.
on-board
BDV11
Working bootstraps
RL01 /
RX02
RKOS
RL02
WARNING
Disable the processor and memory tests since an odd
address trap does occur in each of them.
See NOTE
below.
To disable the CPU test,
set swit~h E1S-1 to
OFF.
To disable the memory test, set switch E1S-2 to
OFF.
(Refer to the Microcomputer
and
Interfaces
Handbook for complete configuration information.)
The 11/73 has an on-board Line Time Clock Register,
therefore the BDV11 BEVNT switch E21-S should be set to
the OPEN position. This disables software control of
the BEVNT signal via the BDV11 LTC register and allows
software control of this signal via the 11/73 LTC
register.
If the BDV11 is used in a 22 bit system, it must be CS
REV E or later or ECO M8012-MLOOOS must be installed.
NOTE
ODD ADDRESS TRAPS.
The 11/23 ignores an odd address
reference whereas the KDJ11-A will trap to address 4.
26
2
r=
uNOTE 1004
Title: LSI-11/73 upgrade Paths
Date: 28-NOV-83
Originator: Mike Collins
Page 1 of 6
With the announcement of the KDJ11-A cpu module, there will be numerous
questions regarding configuring the module into a current system. The
purpose of this MicroNote is to address all possible configuration
upgrade paths (within reason).
Generally a KDJ11-A will be installed as an upgrade to
from components or DEC packaged system.
a
system
built
In the case of a component upgrade it is assumed the processor is a
KDF11-A and the boot mechanism is an MXV11-A with the MXV11-A2 Boot
ROMs.
System upgrades fall into 2 categories:
1. KDF11-A based systems and
2. KDF11-B based systems (11/23+ and Micro/PDP-11)
There are 3 issues which must be addressed when
upgrade.
They are:
1. The Boot mechanism
2. 18 or 22 bit system
3. Single or multiple box system
considering
a
KDJ11-A
NOTE
1. In the following upgrade scenarios, the systems have
been labeled as being Field Serviceable or not. A
system which is Field Serviceable has a bootstrap which
meets Field Service requirements. The requirement is
that the bootstrap must execute an 11/73 cache memory
diagnostic on power-up. There is no guarantee that the
overall system will be Field Serviceable or that it will
be FCC compliant.
2. Systems using cpu's other
KDF11-B (i.e.
11/03 systems)
upgrade.
than the KDF11-A or
are not considered for
CAUTION:
It is recommended that the AC and DC loading for the final
configuration be checked for conformance with the Q-BuS loading rules.
27
uNOTE # 004
Page 2 of 6
It is also recommended to check for.overloading on the +5 Volt
volt Power Supplies.
and
+12.
For each system upgrade the following parameters are listed for both the
'Current' system and the 'Upgraded' system:
1.
2.
3.
4.
CPU
Boot Mechanism
System Size
Number of Boxes
5. Field Serviceable or not
6. Special Conditions
COMPONENT UPGRADE PATHS:
1. Current System
KDF11-A
MXV11-A
18 Bit System
1 Box
Upgrade 1
KDJ11-A
MXV11-B/MRV11-D with MXV11-B2 Boot ROMs
18 Bit System
1 Box
Field Serviceable
Upgrade 2
KDJ11-A
MXV11-A
18 Bit System
1 Box
NOT Field Serviceable
2. Current System
KDF11-A
MXV11-A
18 Bit System
More than 1 box
3. Current System
KDF11-A
MXV11-A (Memory Disabled)
22 Bit System
1 Box
Upgrade
See upgrades for category #1
upgrade
See upgrades for category #1
28
uNOTE # 004
Page 3 of 6
UP9 rade
4. Current System
Not currently configureable with
KDF11-A
DEC equipment.
MXV11-A (Memory Disabled)
22 Bit System
More than 1 box
This system is not currently configureable with DEC equipment.
PDP 11/23A SYSTEM UPGRADE PATHS:
5. Current System
UP9rade 1
KDF11-A
BDV11
18 Bit System
1 Box
KD~Jl1-A
MXV11-B/MRV11-D with MXV11-B2 Boot ROMs
18 Bit System
1 130x
Field Serviceable
Upc;rade 2
KD,J11-A
BDV11
18 Bit System
1 160x
NOT Field Serviceable
Disable the Processor and Memory tests
and also the BEVNT register on the
BDV11.
Uptgrade 3
KDIJ11-A
MXV11-A (with MXV11-A2 boot ROMs)
18 Bit System
1 :Box System
NOT Field Serviceable
Check AC loading since termination was
removed when the BDV11 was removed from
th!e system.
6. Current System
UP'9rade 1
KD,J11-A
MXV11-B/MRV11-D with MXV11-B2 Boot ROMs
18 Bit System
More than 1 box
Field Serviceable
Use Bcv1A and BCV1B expansion cables.
KDF11-A
BDV11
18 Bit System
More than 1 Box
29
uNOTE # 004
:I?age 4 of 6
upgrade 2
KDJ11-A
BDV11
18 Bit System
More than 1 Box
NOT Field Serviceable
Disable the Processor and Memory tests
and also the BEVNT register on the
BDV11.
Use BCV1B cable set between 1st and 2nd
box and the BCV1A cable set between the
2nd and 3rd box. Note: If in a 3 box
system the expansion cable set lengths
must differ by 4 ft.
Upgrade 3
KDJ11-A
MXV11-A (with MXV11-A2 boot ROMs)
18 Bit System
More than 1 Box
NOT Field Serviceable
Use BCV1A and BCV1B expansion cables.
7. Current System
KDF11-A
BDV11
22 Bit System
1 Box
Systems with this configuration were never shipped by DEC.
PDP 11/23 PLUS SYSTEM UPGRADE PATHS:
8. Current System
KDF11-B
Boot is on CPU
22 Bit System
1 Box System
upgrade 1
KDJ11-A
MXV11-B/MRV11-D with MXV11-B2 Boot ROMs
22 Bit System
1 Box
Field Serviceable
Upgrade 2
KDJ11-A
MXV11-A (with MXV11-A2 boot ROMs)
22 Bit System
1 Box
NOT Field Serviceable
Must disable RAM on MXV11-A.
30
uNOTE # 004
Page 5 of 6
Upgrade 3
KDJII-A
BDVl1
22 Bit System
1 Box System
NOT Field Serviceable
Must have BDV11 ECO M8012-MLOOS
installed. Disable the Processor and
Memory tests and also the BEVNT register
on the BDV11.
9. ·Current System
Upgrade 1
KDFI1-B
Boot is on CPU
22 Bit System
More than 1 Box
Not currently configureable with
DEC equipment.
Upgrade 2
Not currently configureable with
DEC equipment.
upgrade 3
Not currently configureable with
DEC equipment.
MICRO/PDP-11 SYSTEM UPGRADE PATHS:
10. Current System
upgrade
Micro/PDP-11
KDF11-BE
Boot is on CPU
22 Bit System
1 Box system
Same as 11/23+ rules, see category
#8, Upgrade 1. upgrades 2 and
3 are not recommended since the
MXV11-A and BDV11 cannot boot the
5 1/4" media in the Micro/PDP-II.
11. Current System
Upgrade
Same as 11/23+ rules, see upgrades
for category #9.
Micro/PDP-11
KDF11-BE
Boot is on CPU
22 Bit System
More than 1 box
31
uNOTE # 004
Page 6 of 6
NOTE
It is not currently possible to expand out
Micro/PDP-11 while maintaining FCC compliance.
of
the
11/23 PLUS and Micro/PDP-11 system upgrades will require
an EXTRA backplane slot to accomodate the additional
boot module (i.e. MXV11-A,-B or BDV11).
11/23-S SYSTEM UPGRADE SOLUTIONS:
12. Current System
KDF11-BA
Boot is on CPU
18 Bit System
1 Box system
13. Current System
KDF11-BA
Boot is on CPU
18 Bit system
More than 1 box
upgrade
See upgrades for category #5.
Upgrade
See upgrades for category #6.
NOTE
It is not currently possible to expand
11/23-8 while maintainin9 FCC compliance.
32
out
of
the
uNOTE # 005
Title: Q22 Compatible Options
Date: 23-Apr-84
Originator: Charlie Giorgetti
page 1 of 6
This is a list of Q22 compatible options. A Q22 compatible option is
defined as a Q-bus option that will work without restriction in an
extended Q-bus system, that is a 22-bit Q-bus system.
This list also
includes options that are not compatible in Q22 systems and the reason
for the restriction.
The requirements for a device to be Q22 compatible are the following:
1. Processors, memories, and OM. devices must all be capable of
addressing.
2. Devices must use backplane pins BC1, BD1, BEl,
DEl, DF1, for BDAL18-21 only.
BF1
and
DC1,
22-bi t
001,
Processors, memories, or DMA devices which are not capable of 22-bit
may generate or decode erroneous addresses if they are used
ln
systems
which
implement
22-bit
addressing.
Memory
and
memory-addressing devices which implement only 16 or 18-bit addressing
may be used in a 22-bit backplane, but the size of the system memory
must be restricted to the address range of those devices (64 KB for
systems with 16-bit devices and 256 KB for systems with an lS-bit
devices).
~ddressing
Any device which uses backplane pins BC1, BD1, BEl, BF1 or DC1, 001,
DEl, OF!, for purposes other than BDAL18-21 is electrically incompatible
with the 22-bit bus and may not be used without modification.
NOTE
Eighteen or sixteen bit DMA devices can potenitially work in
Q22 systems by buffering I/O in the 18- or 16-bit address
space.
I.
Fully Compatible Options
Options in this category meet both of the requirements
and may be used in any Q-bus configuration.
A. Processors
KD32-A
M7135/M7136
MicroVAX I CPU Module
33
mentioned
above
uNOTE # 005
Page 2 of 6
KDFll-A
M8186
LSI-ll/23 CPU
(Etch Rev. C or later)
KDFll-B
M8l89
LSI-l1/23B CPU
KDJll-A
M8l92
LSI-l1/73 CPU
KDJll-B
M8l90
MicroPDP-ll/73 CPU
KXTll-C
M8377
Q-bus Perpherial I/O Processor
KMV11-A
M7500
Q-bus Perpherial Communication Processor
B. Backplanes/Boxes
H9270-Q
4 X 4 Q22/Q22 Backplane
H928l-QA
H9281-QB
H928l-QC
2 X 4 Q22 Dual-height Backplane
2 X 8 Q22 Dual-height Backplane
2 X 12 Q22 Dual-height Backplane
H9275
4 X 9 Q22/Q22 Backplane
BA11-S
H9276
4 X 9 Q22/CD Backplane
Micro/PDP-ll
H9278
4 X 3 Q22/CD and 4 X 5 Q22/Q22 Backplane
C. Memory
MCVll-D
M8631
CMOS Non-volatile Memory
MSV11-L
M8059
MOS Memory (either 128 KB or 256 KB)
MSVll-P
M8067
MOS Memory (either 256 KB or 512 KB)
MSVll-Q
M7551
MOS Memory ( 1 MB)
MXVll-B
M7195
Multifunction Module
MRVll-D
M8578
PROM/ROM Module
AAVll-C
A6006
D/A Converter
ADVll-C
ABOOO
A/D Converter
AXVll-C
A0026
D/A and A/D Combination Converter
BDVll
MB012
Bootstrap, Terminator, Diagnostic
(CS Rev. E or later, ECO M8012-ML005
installed)
D. options
34
uNOTE # 005
Page 3 of 6
DEQNA
M7504
Ethernet Controller
DLVll
M7940
Asynchronous Serial Line Interface
DLVll-E
M80l7
Asynchronous Serial Line Interface
DLVll-F
M8028
Asynchronous Serial Line Interface
DLVll-J
M8043
Four Asynchronous Serial Line Interfaces
(CS Rev. E or later, ECO M8043-MR002
installed)
DHVll
M3l04
8-line Asynchrono~s EIA Multiplexer
DMVll-AD
M8053-MA
Synchronous Communications Interface
DMVll-AF
M8064-MA
Synchronous Communications Interface
DPVll
M8020
programmable Synchronous EIA Line
DRVll
M794l
32 line Parallel Interface
DRVll-J
M8049
64 line Parallel Interface
DRVll-w
M765l
General Purpose DMA Interface (dual)
DUVll
M795l
programmable Synchronous EIA Line
DZQll
M3l06
4-line Asynchronous EIA Multiplexer (dual)
DZVll
M7957
4-line Asynchronous EIA Multiplexer (quad)
FPFll
M8l88
Floating Point Processor
IBV11-A
M7954
IEEE Instrument Bus Interface
IEQll
M8634
DMA IE:EE Instrument Bus Interface
KLESI-QA
M7740
LESI Bus Adaptor (RC25 Interface)
KPVll-A
M80l6
Power-fail and LTC Generator
(KPV11-B and -C are not compatible)
KWVll-C
A4002
Programmable Real-time Clock
LAVll
M7949
LA180 Line Printer Interface
LPVll
M8027
LA180/LP05 Printer Interface
RLV12
M806l
RL01/2 Controller
RQDXl
M8639
Controller for 5.25" Floppy and Winchester
35
uNOTE # 005
Page 4 of .6
RXVll
M7946
RXOl Floppy Disk Interface
TQK25
M7605
Streaming Cartridge Tape Controller
TSv05
M7l96
Magnetic Tape Controller
E. Bus Cable-Cards
II.
M9404
Cable Connector
M9404-YA
Cable Connector with 240-0hm Terminators
M9405
Cable Connector
M9405-YA
Cable Connector with l20-0hm Terminators
Restricted Compatibility Options
Options in this category do not meet one or both of the requirements for
use in a 22-bit system. These options are incompatible with some ~r all
22-bit systems.
A. Processors
KDFll-A
M8l86
LSI-ll/23 CPU
(Prior to etch rev. C, l8-bit addressing only,
and use of BC1,BD1,BE1,BFl for purposes other'
than BDAL18-2l)
KDll-HA
M7270
LSI-ll/2 CPU
(16-bit addressing only, and use of BC1,BD1,
BE1,BFl for purposes other than BDAL18-2l)
KDll-F
M7264
LSI-ll CPU
(16-bit addressing only, and use of DC1,DB1,
DE1,DFl for purposes other than BDAL18-2l)
KXTll-A
M8063
SBC-ll/2l CPU
(16-bit addressing only)
B. Backplanes/Boxes
6 X 9 Backplane
(18-bit addressing only)
DDVll-B
BAll-M
H9270
4 X 4 Backplane
(18-bit addressing only)
BAll-N
H9273-A
4 X~9 Backplane
(18-bit addressing only)
36
uNOTE # 005
Page 5 of 6
BAll-VA
H92S1-A,B,C
VT103
2 X n Dual-height Backplane n - 4, S, and 12
BAll-VA used the H92S1-A
(lS-bit addressing only)
4 X 4 Backplane (part number: 54-1400S)
(18-bit addressing only)
C. Memories
MMV11-A
G653
S KB Core Memory
(16-bit addressing only, Q-bus required on C/D
backplane connectors)
MRV11-AA
M7942
ROM Module
(16-bit addressing only)
MRV11-BA
MS021
UV PROM--RAM
(16-bit addressing only)
MRV11-C
MS04S
PROM/ROt1 Modul e
(lS-bit addressing only)
MSV11-B
M7944
S KB bus refreshed RAM
(16-bit addressing only)
MSV11-C
M7955
32 KB Rl\M
(lS-bit addressing only)
MSV11-D,E MS044/MS045
S KB, 16 KB, 32 KB, 64 KB RAM
(lS-bit addressing only)
MS047
Multifunction Module
(lS-bit addressing only on memory, the memory
can be disabled)
AAV11
A6001
D/A Converter
(Use of BC1 for purposes other than BDAL1S)
ADV11
A012
A/D Converter
(Use of BC1 for purposes other than BDAL1S)
BDV11
MS012
Bootstrap/Terminator
(CS Revision E or earlier lS bits only)
DLV11-J
MS043
Serial Line Interface
(CS Rev. E or earlier incompatible with
KDF11-A and KDF11-B)
DRV11-B
M7950
General Purpose DMA Interface (quad)
(lS-bit DMA only)
MXV11-A
D. Options
37
uNO'!'E # 005
page 6 of 6
KPVll-B,C M80l6-YB,YC
Power-fail/line-time clock/terminator
(Termination for l8-bits only)
KUVll
MS01S
writable Control Store
(For use with KDll-F processor only)
KWVll-A
M7952
Programmable real-time clock
(Use of BCl for purposes other than BDAL18)
REVll
M9400
Terminator, DMA refresh, bootstrap
(Bootstrap for use with KDll-F and KDll-HA
processors only.
Termination for l8-bits only.
DMA refresh may be used in any system.)
RKVll-D
M7269
RK05 Controller Interface
(l6-bit DMA only)
RLVll
M80l3
M80l4
RL01,2 Controller
(18-bit DMA only, use of BCl and BDl for
purposes other than BDALl8 and BDALl9)
RXV2l
M8029
RX02 Floppy Disk Interface
(lS-bit DMA only)
TEVll
M9400-YB
l20-0hm Bus Terminator
(Termination for l8-bits only)
VSVll
M7064
Graphics Display
(lS-bit DMA only)
E. Bus Cable-Cards
M9400-YD
Cable Connector
(lS-bit bus only)
M9400-YE
Cable Connector with 240-0hm Terminators
(18-bit bus only)
M940l
Cable Connector
(lS-bit bus only)
38
uNOTE #006
Differences Between
the LSI-11/73 and LSI-11/23
Title:
Originator: Mike Collins
Date: 23-APR-84
Page 1 of 8
This uNOTE identifies and discusses the differences between
the
LSI-11/23
(KDF11-AA) and the LSI-11/73 (KDJ11-AA). The following table
lists these differences.
Following the table are individual discussions
on these differences.
Some of these differences are discussed from the point
11/23 to 11/73 upgrade.
Table 1
of
view
of
LSI-11/73 versus LSI-11/23
FEATURE
11/73
Odd Address Traps
Yes
Micro ODT
22 Bit
Illegal Halt
Processor Modes
I & D Space
18 Bit
Traps to 10
3
2
2
Floating Point Inst. Set
No
Traps to 4
Yes
General Purpose Reg Sets
11/23
Standard
No
1
Option
Line Time Clock Reg.
Yes
No
On-board Cache Memory
Yes
No
Pipelined Processing
Yes
No
UBMap Signal on the Q-bus
Not Available
Available
Additional Instructions
Available
CSM, TSTSET,
WRTLCK
Not
Available
cont'd
39
an
uNOTE # 006
Page 2 of 8
Table 1 cont'd
LSI-11/73 versus LSI-11/23
11/73
FEATURE
11/23
CPU Error Register
Memory System Error Reg
Cache Control Reg
Hit/Miss Reg
Program Interrupt Req Reg
Line Time Clock Reg
Maintenance Reg
Additional CPU Registers
Not
Available
A discussion of processor speed can
be found in the respective user guides
Processor Speed
User Guide Part #
EK-KDJ1A-UG
User Guide Part #
EK-KDF11-UG
ODD ADDRESS TRAPS
The 11/73 processor will trap to 4 when it encounters an odd address
reference.
i.e.
whenever an address begins on an odd byte boundary
(least significant bit - 1). The 11/23 ignores odd address references
and simply treats the LSB as a zero, effectively 'forcing' all addresses
to begin on even byte boundaries.
Odd address traps do not occur
freque~tly,
however it is possible for code to run on an 11/23 and NOT
run on an 11/73 because of them.
Fixes for these errors
are
straightforward.
MICRO ODT (Octal Debugging Technique)
Both the 11/23 and the 11/73 implement ODT in their microcode.
The
11/23 can use ODT to examine main memory locations from 0 to 256 Kbytes,
but no further.
On the other hand, the 11/73 ODT can examine the full 4
Mbyte range of main memory. When accessing addresses in the I/O page
with an 11/73, a full 22 bit address must be specified.
Example: To look at the first instruction of the bootstrap code with
an 11/73 it is necessary to type:
@17773000/
or @7777777777773000/
NOT @773000/
This is NOT enough because only
18 bits have been specified.
40
uNOTE # 006
Page 3 of 8
ILLEGAL HALT
The 11/23 and the 11/73 respond differently when detecting a halt
instruction in user or supervisor mode.
The 11/23 traps to address 10
whereas the 11/73 traps to address 4. The 11/73 also sets the Illegal
Halt Bit in the CPU ERROR Register to indicate an Illegal Halt occurred.
PROCESSOR MODES
The 11/23 has two processor modes, KERNEL and USER.
KERNEL, SUPERVISOR and USER.
The 11/73 has three
I and D SPACE
The concept of I and D space is used in mapping information into
separate physical memory segments, depending on whether the information
is considered instructions (I) or data (D). The use of I
and D space
allows programs to exist in two virtual segments and effectively doubles
the address available to the user from 64 Kbytes to 128 Kbytes.
The 11/73 has the capability for I and D space whereas the 11/23 does
not.
To implement this feature, many more PAR/PDR pairs are necessary.
The 11/73 has 48 PAR/PDR pairs, the 11/23 has only 16 PAR/PDR pairs.
GENERAL PURPOSE REGISTER SETS
The 11/23 and all previous LSI-11 processors have 1 set of general
purpose registers,
RO thru R7.
Some of these are used for special
purposes.
R7 is used as the progri~m counter and R6 is used as the stack
pointer.
Internal to the 11/23 are 2 registers used for stack pointers,
one for each processor mode).
There are 5 additional registers RO thru
RS.
The 11/73 has two sets of general purpose registers, listed in the table
below. Only eight are visible to the user at any given time.
There are
two groups of six registers (RO thru RS and RO' thru RS').
The group
currently being used is selected by bit 11 in the Processor Status Word
(PSW).
Only one stack pointer is visible to the user at anyone time
and is determined by bits 14 and 15 in the PSW.
Designation
RO
RO'
R1
R1'
R2
R2'
R3
R3'
Register Number
o
1
2
3
4
5
R4
RS
KS]?
PC
6
7
R4'
RS'
SSP
KSP - Kernel Stack Pointer
SSP - Supervisor Stack Pointer
USP = User Stack Pointer
41
USP
uNOTE # 006
Page 4 of 8
FLOATING POINT INSTRUCTION SET
Both the 11/23 and the 11/73 use the FP11 Floating Point Instruction
Set.,
The FP11 Instruction Set is an option for the 11/23 (choice of
either the KEF11 chip or the FPF11 floating point accelerator).
The
FP11 instruction set is part of the J11 microprocessor microcode and is
therefore a standard feature of the 11/73.
LINE TIME CLOCK REGISTER
The original dual height 11/23 CPU does not have an LTC (Line Time
Clock)
register on the board.
In 11/23 based systems the BDV11 boot
module contains the LTC reg.
In order to enable or disable LTC
interrupts under software control, the 11/23 must write to this register
over the Q-bus.
11/23
LTC
REG
1
7 546
Q-bus
The 11/73 has an LTC register on the CPU board.
This means that
whenever the 11/73 wants to enable or disable LTC interrupts under
software control it writes to this on-board register.
The address of
the LTC register (location 177546) is 'trapped' on the board and NEVER
goes out onto the Q-bus. When the 11/73 is used in a system with a
BDV11,
it is recommended that software control over the LTC interrupts
be disabled on the BDV11 (see uNOTE #114).
11/73
177546
I
Q-bus
ON-BOARD CACHE MEMORY
Cache memory systems are designed
42
to
increase
CPU
performance.
The
uNOTE # 006
Page 5 of 8
cache maintains copies of portions of main memory in very high-speed RAM
and thus reduces access times significantly.
The 11/73 is the first Q-bus processor to implement a cache memory
system.
The cache is automatically enabled on power-up and its
operation is transparent to software.
However software can enable or
disable the cache by writing to the Cache Control Register (CCR).
When the cache is enabled, any information fetched from main memory will
be
'cached'
i.e.
placed in the high-speed RAM.
Information fetched
from an I/O device will NOT be 'cached' (i.e.
information fetched from
an address in the I/O page).
CAUTION:
Digital Equipment Corporation does not support a system which
uses shared or dual-ported memory on the Q-bus.
However there are
applications and non-DEC add-on hardware which do
support
such
configurations.
Consider the following:
The system below uses an 11/73, has a certain amount of main memory as
well as dual-ported memory.
The cache is enabled and the following
sequence of events occur:
1.
The 11/73 reads a word
address A which contains
'cached'.
from the dual-ported RAM
the value X.
The value
EXTERNAL
DEVICE
11/73
A: X
A: X
at
is
O THEN GO TO 235
970 LET Y-B
975 LET C1$-SEG$(01$,Y,Y)
980 IF C1$-"A" THEN LET A1-1
985 IF C1$-"*" THEN LET A1-0
990 LET C2$-SEG$(02$,Y,Y)
995 IF C2$-"A" THEN LET A2-1
1000 IF C2$-"*" THEN LET A2-0
1005 LET C3$-SEG$(03$,Y,Y)
1010 IF C3$-"A" THEN LET A3-1
1015 IF C3$-"*" THEN LET A3-0
1020 LET C4$-SEG$(04$,Y,Y)
1025 IF C4$-"A" THEN LET A4-1
1030 IF C4$-"*" THEN LET A4-0
1035 LET C5$=SEG$(05$,Y,Y)
1040 IF C5$-"A" THEN LET A5-1
1045 IF C5$-"*" THEN LET A5-0
1050 LET C6$=SEG$(06$,Y,Y)
1055 IF C6$-"A" THEN LET A6-1
1060 IF C6$_n*n THEN LET A6-0
1065 LET C7$-SEG$(07$,Y,Y)
1070 IF C7$-nAn THEN LET A7-1
1075 IF C7$_n*n THEN LET A7-0
lOBO LET CB$-SEG$(OB$,Y,Y)
lOBS IF CB$_nA n THEN LET FB-1
1090 IF CB$_n*n THEN LET FB-O
1095 LET 09-(A1*1)+(A2*2)+(A3*4)+(A4*B)
1100 LET P9-(A5*1)+(A6*2)+(A7*4)+(FB*B)
1105 LET 09-15-09 \ LET P9-15-P9
1110 IF P9<10 THEN LET T1-0
1115 IF P9<10 THEN GO TO 1155
1120 IF P9-10 THEN LET P9$_nAn
1125 IF P9-11 THEN LET P9$_nBn
1130 IF P9-12 THEN LET P9$-nC n
1135 IF P9-13 THEN LET P9$_nDn
1140 IF P9-14 THEN LET P9$-nEn
1145 IF P9-15 THEN LET P9$-nFn
1150 LET T1-1
1155 IF 09<10 THEN LET TO-O
1160 IF 09<10 THEN GO TO 1200
1165 IF 09-10 THEN LET 09$-nAn
5B
uNOTE i 007
Page 13 of 13
1170
1175
1180
1185
1190
1195
1200
1205
1210
1215
1220
1225
1230
1235
1240
1250
1255
1260
1265
1270
1275
1280
1285
1290
1295
1300
1305
1310
1315
1320
1330
1335
1340
1345
IF 09-11 THEN LET 09$-nBn
IF 09-12 THEN LET 09$-nC n
IF 09-13 THEN LET 09$-"0"
IF 09-14 THEN LET 09$-nEn
IF 09-15 THEN LET 09$-"F"
LET TO-1
IF T1=0 THEN GO TO 1215
IF TO=O THEN GO TO 1240
GO TO 1230
IF TO-1 THEN GO TO 1255
PRINT i4,STR$(P9);STR$(09);L1$
GO TO 1260
PRINT i4,P9$;09$;L1$
GO TO 1260
PRINT i4,P9$;STR$(09);L1$
GO TO 1260
PRINT i4,STR$(P9);09$;L1$
I,ET Y-Y-1
IF Y>O THEN GO TO 975
PRINT i4,Z$
LET Y1-Y1+1
IF Yl-2 THEN LET Sl$-n$A200,"
IF Yl-3 THEN LET Sl$-"$A300,"
IF Y1=4 THEN LET Sl$-n$A400,"
IF Y1=5 THEN LET Sl$-"$A500,"
IF Yl-6 THEN LET Sl$-"$A600,"
PRINT i4,Z$
IF Y1=7 THEN GO TO 1320
IF E1=0 THEN GO TO 91
PRINT i4,H2$
CLOSE
GO TO 1345
PRINT "INPUT LINE IN ERROR"
END
59
60
uNOTE # 008
Title: Memory Management and the LSI-11/73
Date: 22-Jun-84
Originator: Dave Smith
Page 1 of 11
This micronote explains memory management as it applies to
the
LSI-11/73.
It includes descriptions of what memory management is, what
it does, and how it works.
Simply stated, memory management is a method of mappi~g virtual
addresses to physical addresses. The virtual address space 1S the view
of memory as seen by a process running. The physical address space is
the actual physical memory as seen by the entire system. Since ALL
memory references must be mapped, this translation is done in hardware
by using a Memory Management Unit (MMU). Various schemes (dependent
upon the architecture) have been df~veloped to accomplish this, but most
memory management systems provide the following services:
1) Protection
2) Relocation
3) Segmentation
The first two are of great importance in a multiprogramming system since
memory management provides the mf~chanism for assigning memory areas to
user programs and for preventing users from accessing areas that have
been assigned to other users.
This protects the operating system
executive as well as users from accidental or willful memory accesses
outside of a user's assigned memory. Relocation is also important in a
multiprogramming environment since the executive must be able to
relocate the user's program to a free area in physical memory.
The LSI-11/73 Memory Management Unit provides the hardware for complete
memory management by providing all of the above services.
It is
software compatible with the largl~r UNIBUS PDP-11s and other Q-bus
processors.
Since the LSI-11/73 has the PDP-11 architecture and a
16-bit program counter, all 16-bit addresses access a 64Kb virtual
address space. On the LSI-11/73 this addressing limitation can be eased
by using separate sets of memory management registers for instructions
(I-space) and for data (D-space).
By utilizing separate I- and Dspace, the address space can be segmented into two 64Kb segments,
effectively doubling the virtual address space. The LSI-11/73 and the
Q-bus allow 4 Mb of memory to be rl~ferenced. The MMU is necessary to
provide the mapping from the 64Kb virtual address space to the 4 Mb
physical address space.
61
uNOTE # OOS
Page 2 of 11
When the MMU is activated, a 16-bit virtual address is mapped to an
lS-bit or 22-bit physical address.
Th~ MMU uses registers known as
Active Page Registers (APRs). An APR consists of two 16-bit registers
which are called the Page Address Register (PAR) and the Page Descriptor
Register (PDR).
PARs are used in the actual address translation while
PDRs contain access and other information.
Since the LSI-11/73 is
functionally equivalent to the PDP-11/70, it can operate in one of three
modes:
Kernel,
Supervisor, or User and it can use 1- and D- space.
This means that the MMU must provide separate sets of registers for each
mode and within each mode,
sets of registers for I-space and for
D-space. A set of registers consists of eight pairs of PDRs and PARs.
Thus the LSI-11/73 MMU has a total of three sets of 32 16-bit registers.
Mapping is always done in pages of 8Kb (4K words) in length or less.
In
order to map the largest possible virtual address space (64 Kb), the
address space is divided into eight pages of 8Kb each. One APR is used
fo[, each of the eight pages, numbered 0 to 7. The uppermost page in
physical memory is called the I/O page and is usually mapped by a Kernel
Mode APR since it is a privileged area.
PHYSICAL
ADDRESS
SPACE
4 Mb
I/O page
USER MODE
>
<-----
page 7
KERNEL MODE
APRs
APRs
PAR7
PAR7
PAR6
PAR6
PARS
~
>
PARS
PAR4
PAR4
PAR3
PAR3
<-----
PAR2
PAR1
PARO
>
PAR2
PAR1
<
o
62
PARO
uNOTE # 008
Page 3 of 11
The Page Address Register consists solely of the Page Address Field
(PAF).
If 22-bit addressing is enabled, then all 16 bits of the PAR are
used as the PAF.
If only 18-bit addressing is desired then the 12 lower
order bits are the PAF and the 4 higher order bits are unused.
It may
be thought of as a base register containing a base address or as a
relocation register containing a relocation constant.
PAGE ADDRESS REGISTER
(PAR)
o
15
[+--+-;~GE+AD;RE;;-;IE~~~PA;-)-+--+--+--+--+J
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
The Page Descriptor Register contains
length, and expansion direction:
information
about
access,
PAGE DESCRIPTOR REGISTER (PDR)
15 14
08 07 06 05 04 03 02 01 00
+--+--+--+--+--+
Be PAGE LENGTH FIELD I 01
~
+--+--+--+--+--+
PDR <15>
BC
wi 01 olEol
A~~
(Bypass Cache)
Set if memory accessing is wished to be
without utilizing the cache. Useful with
dual-ported memories.
PDR <08:14>
PLF
(Page Length Field)
Specifies the authorized length of the page
in 32 word (or 64 byte) groups.
o
<-->
.
177 (8) <-->
63
32 word page
4096 word page
page
uNOTE # 008
Page 4 of 11
PDR <06>
W
(Written Into)
Useful in determining whether or not a page can
simply be erased or must be saved to be brought
back into memory.
PDR <03>
PDR <01:02>
Page has NOT been written into
Page has been written into
0
1
<->
<->
ED
(Expansion Direction)
0
<->
1
<->
ACF
(Access Control Field)
00
01
10
11
<->
<->
<->
<->
Expands to higher addresses
(Normally used)
Expands to lower address-es
(Can be used for stack segments)
Nonresident
Resident - Read Only
Not Used
Resident - Read/Write
The 16-bit virtual address is divided into three fields:
VIRTUAL ADDRESS (VA)
13 12
15
APF
o
6 5
DIB
BN
<------DISPLACEMENT FIELD (DF)---->
o APF or Active Page Field
These three bits determine which of the eight
APRs are selected.
o BN or Block Number
The PAF determines an 8 Kb page in memory.
The BN is that offset that is added to the base
of ,the page determined by the PAF to obtain the
block within the page to map.
64
uNOTE # 008
Page 5 of 11
o DIB or Displacement In the Block
Tells exactly which one of the 32 words is being
mapped to. The low order 6 bits (DIB) are never
relocated.
The BN and DIB fields are collectively referred to as the
Displacement Field (OF).
If the MMU is not activated then 16-bit virtual addresses are also
16-bit physical addresses and linearly map the 64Kb address space. When
the MMU is activated the 16-bit virtual address (VA)
is no longer
interpreted as a physical address Instead, the physical address (PA) is
constructed using the VA and the PAF (Page Address Field) of the
selected PAR.
The translation of virtual addresses to
accomplished as follows:
22-bit
physical
addresses
1) A set of registers is selected. This is determined by
the space being referenced (Instructions or Data) and by
the mode bits of the Processor status Word (PSW <15:14».
2) The APF field of the virtual address determines which of the
eight pairs in the selected set will be used for the mapping.
3) The PAF of the selected register pair contains the starting
address of the currently active page as a block number.
4) The block number from the virtual address and the block number
from the PAF are added together. The block number from the PAF
is shifted left by six bits in order to perform this addition.
The result is the actual physical block number (bits <21:06>
of the physical address).
5) The DIB of the virtual address is carried along unchanged as
bits <05:00> of the translated address.
65
is
uNOTE # 008
Page 6 of 11
VIRTUAL TO PHYSICAL ADDRESS TRANSLATION
16-BIT VIRTUAL ADDRESS
o
15
[
+-+I+-+-+-+-+-+I+-+-+-+--+]
APF
BN
DIB
+-r--+
+-+-+ +-+-+
+-+_.+-+ +
Selects
APR
PAGE ADDRESS REGISTER
o
15
+--+--+--+--+-+-+-+--+-+-+-+-+-+-+]
[
+--+--+--+--+--+--+~+-+-+-+-:+-+--+<--+--------~
21
[
6
+--+--+-+-+-+-+
+-+-+-+-+-+-+]
BLOCK NUMBER IN PHYSICAL MEMORY
+--+--+--+-+--+--+--+--+--+-+-+-+-+-+
<----------------
22-BIT PHYSICAL ADDRESS (PA)
66
o
5
DIB
[
. +--+-+--+-+
+--+~+--+
+]
------------------------>
uNOTE # 008
Page 7 of 11
There are four memory management registers that are used for memory
fault recovery and abort and status information as well as control of
the MMU.
They are called MMRO, MMR1, MMR2, and MMR3.
Memory Management Register 0 (MMRO)
register.
is
the
main
control
and
status
MEMORY MANAGEMEN'T REGISTER 0 (MMRO)
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
1 1 1 1 01 01 01 01
MMRO <15>
o~:
1 1
:=:IJ
NONRESIDENT ABORT
Set if an attempt is made to access a page
with an ACF of 0 or 2 or if the PSW indicates
mode 2.
MMRO <14>
PAGE LENGTH ABORT
Set if an attempt is made to access a location
whose block numbE!r is outside the area authorized
by the PLF of the PDR for that page.
MMRO <13>
READ ONLY ABORT
Set if an attempt is made to write to a page with
an ACF of 1 (Read Only).
MMRO <06:05>
PROCESSOR MODE
Copy of the PSW <15:14> when abort occurred.
MMRO <04>
PAGE SPACE
1
o
MMRO <03:01>
<->
<->
I)-space
I-space
PAGE NUMBER
page Number of page causing the abort.
Copy of APF of virtual address.
67
uNOTE ~~ 008
Page 8 of 11
ENABLE RELOCATION
MMRO <00>
1
<->
o
<->
ALL addresses are relocated
(MMU activated)
NO addresses are relocated
(MMU disabled)
Memory Management Register 1 (MMR1) is called the Instruction Backup
Register.
It records any autoincrement or autodecrement of any general
purpose register. The lower byte is used for source operands and the
destination
operand
may be in either byte, dependent upon the
instruction.
MEMORY MANAGEMENT REGISTER 1 (MMR1)
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
+--+-+-+--r--+-+--r--+-+--+-+--r--+--+]
[
+-+--+-+~+--+~+--+--+--+~+-.-+
MMR1 <15:11>
AMOUNT CHANGED (2's complement)
MMR1 <10:08>
REGISTER NUMBER
MMR1 <07:03>
AMOUNT CHANGED (2's complement)
MMR1 <02:01>
REGISTER NUMBER
Memory Management Register 2 (MMR2) is known as the Last Virtual program
Counter.
It is loaded with the value of the program Counter at the
beginning of each instruction fetch and is used in instruction fault
recovery_
68
uNOTE # 008
Page 9 of 11
Memory Management Register 3 (MMlt3) is used to select 1S-bit or 22-bit
address mapping and is used to onable/disable the data space for any of
the processor modes.
MEMORY
MANAGEMl~NT
REGI STER 3 (MMR3)
:=:J
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
/ 0/ 0/ 0/ 01 0/ 0/ 0/ 0/ 0/ 0/
MMR3 <05>
1 1 1
UNINTERPRETED
May be set or cleared but is not interpreted.
MMR3 <04>
ENABLE 22-BIT
1
o
MMR3 <03>
o
MMR3 <01>
MMR3 <00>
Mapping is to 22-bit space.
Mapping is to 1S-bit space.
<->
<->
ENABLE CSM (Call Supervisor Mode) INSTRUCTION
1
MMR3 <02>
]~PPING
CSM is recognized.
CSM is ·not recognized.
<->
<->
KERNEL DATA
1
<->
o
<->
SPJ~CE
Enable data space mapping in
Kernel Mode
Disable data space mapping in
Kernel Mode
SUPERVISOR DAT.A SPACE
1
<->
0
<->
Enable data space mapping in
Supervisor Mode
Disable data space mapping in
Supervisor Mode
USER DATA SPACE
1
<->
0
<->
69
Enable data space mapping in
User Mode
Disable data space mapping in
User Mode
uNOTE # 008
Page 10 of 11
Summary:
The LSI-11/73 Memory Management unit provides a powerful,
general
purpose tool for memory management~
It can be used to expand memory in
a simple way and it can be used in a multiprogramming system to provide
all the services necessary for an efficient and secure environment.
The following is a simple MACRO-11 program which illustrates the method
of setting up the registers and performing some mappings.
It writes a
known value to an unmapped location and sets up the MMU registers and
turns on the unit.
It then writes another known value to the same
virtual address which is now mapped. Then it turns the MMU off.
At
this point the two known valuas are in different memory locations .
. TITLE
MMU
;
;
;
Program to demonstrate setting up MMU registers
and to illustrate the mapping that takes place
;
PSW
MMRO
PDRO
PARO
PAR1
PAR7
=
=-
-
-=-
177776
177572
172300
172340
172342
172356
Processor status Word
Memory Management Register 0
Page Descriptor Register 0
Page Address Register 0
Page Address Register 1
Page Address Register 7
; INSURE THAT MMU IS NOT ACTIVATED
START:: CLR
@#MMRO
CLEAR MMRO
; STORE A KNOWN VALUE (152152) IN UNMAPPED LOCATION 20000
MOV
#152152,@#20000
SET PSW TO KERNEL MODE
BIC
#140000,@#PSW
; SET THE PARS SO THAT EACH PAGE MAPS TO ITSELF
LOOPl:
MOV
MOV
CLR
#PARO,R5
#10,R4
R3
MOV
R3, ( R5 ) +
ADD
SOB
#200,R3
R4,LOOPl
i
SET UP PAR POINTER
SET UP PAR COUNTER
SET UP PAR OFFSET VALUE
SET EACH RELOCATION CONSTANT TO
MAP TO ITSELF
UPDATE OFFSET
DO ALL OF THEM
70
uNOTE # 008
Page 11 of 11
;
SET PAR1 TO MAP PAGE 1 TO PAGE 2
MOV
#400,@#PAR1
SET PAR7 TO MAP THE I/O PAGE TO THE TOP OF MEMORY
MOV
#7600,@#PAR7
172356 POINTS TO 760000
SET UP THE PDRS
;
; 77406 (8) - 0 111 111 100 000 110 (2)
,.
RESIDENT - READ/WRITE
UPWARD EXPANDING
NOT WRITTEN INTO
8KB PAGE SIZE
DON'T BYPASS CACHE
;
;
;
;
;
LOOP2:
MOV
MOV
#PDRO,R5
#10,R4
SET UP PDR POINTER
SET UP PDR COUNTER
MOV
SOB
#77406,(R5)+
R4,LOOP2
SET EACH PDR
DO THEM ALL
; ENABLE THE MMU
INC
@#MMRO
; SET BIT 0 OF MMRO
; WRITE A VALUE TO LOCATION 20000. THIS SHOULD BE MAPPED.
MOV
#107010,@#20000; WRITE 107010 TO MAPPED 2000
DISABLE THE MMU
DEC
@#MMRO
; CLEAR BIT 0 OF MMRO
; AT THIS POINT IN THE PROGRAM, ;E:XAMINING PHYSICAL
ADDRESS 20000 SHOWS THE VALUE OF 152152 WHICH WAS PLACED THERE
; ADDRESS 40000 (WHICH 20000 MAPPED TO) HOLDS THE VALUE 107010
HALT
.END
START
71
72
uNOTE # 009
Title: Cache Concepts and the LSI-ll/73
Date: 02-JUL-84
Originator: Charlie Giorgetti
Page 1 of 6
The goal is to introduce the concept of cache and its particular
implementation on the LSI-ll/73 (KDJll-A).
This is not a detailed
discussion of the different cache organizations and their impact on
system performance.
What Is A Cache ?
The purpose of having a cache is to simulate a system having a large
amount of moderately fast memory. To do this the cache system relies on
a small amount of very fast, easily' accessed memory (the cache), a
larger amount of slower, less expensive memory (the backing store), and
the statistics of program behavior.
The goal is to store some of the data and its associated addresses in
the cache and all of the data at its usual addresses (including the
currently cached data) in the backing store. If it can be arranged that
most of the time when the proces.sor needs dat, it is located in fast
memory, then the program will execute more quickly, slowing down only
occasionally for main memory operations.. The placement of data in the
cache should not be a concern to the programmer but is a consequence of
how the cache functions.
Figure 1 is an example of a memory organization showing a cache with
backing store.
If the data needed by the microprocessor (uP) can be
found in the cache then it is accessed much faster due to the local data
path and faster cache memory than by having to access the backing store
on the slower system bus.
c::J
uP
<
CPU Internal Buses C]yrstem
>
Bus
Interface
System Bus
For Memory and I/O Options
<
>
<
Fast Path
to Cache
System Memory
(Backing Store)
Cache
Figure 1 - An Example Memory System with Cache
73
uNOTE # 009
Page 2 of 6
cache memory system can only work if it can successfully predict most
of the time what memory locations the program will require. If a
program accessed data from memory in a completely random fashion, it
would be impossible to predict what data would be needed next. If this
was the case a cache would operate no better then a conventional memory
system.
A
Pr()grams rarely generate random addresses. In many cases the subsequent
memory address referenced is often very near the current address
accessed. This is the principle of program locality. The next address
generated is in the neighborhood of the current address. This behavior
helps makes cache systems feasible.
concept of program locality is not always adhered to, but is a
statement of how many programs behave. Many programs execute code in a
linear fashion or in loops with predictable results in next address
generation.
Jumps and context switching give the appearance of random
address generation. The ability to determine what word a program will
reference next is never completely successful and therefore the correct
"guesses" are a statistical measure of the size and organization of the
cache, and the behavior of the program being executed.
Th~!
The measure of a cache performance is a statistical evaluation of the
number of memory references found versus not found in cache. When
memory is referenced and the address is found in the cache this is known
as a hit.
When it is not it is termed a miss. Cache performance is
usually stated in terms of the hit ratio or the miss ratio where these
are defined as:
Hit Ratio
Miss Ratio
=
=
Number of Cache Hits
Total Number of Memory References
I
-
Hit Ratio
The LSI-11/73 Cache
Impl~mentation
cache organization chosen must be one that can be implemented within
the physical and cost constraints of the design.
ThE~
ThE~ LSI-11/73 implements a direct map cache.
A direct map
organization
has a single unique cache location for a given address and this is where
thE! associated data from backing store are maintained.
This means an
access to cache requires one address comparison to determine if there is
a hit. The significance of this is that a small amount of circuitry is
74
uNOTE # 009
Page 3 of 6
required to perform the comparison operation. The LSI-11/73 has an 8
KByte cache. This means that therle are 4096 unique address locations
each of which stores two bytes of information.
The cache not only maintains the d.ata from backing store but it also
includes other information that is needed to determine if its content is
valid. These are parity detection and valid entry checking.
The
following diagram shows the logical layout of the cache and what each
field and its associated address in the cache is used for.
Binary Cache
Entry Address
P
v
P1
PO
B1
BO
000000000000
000000000001
000000000010
111111111101
111111111110
111111111111
Figure 2
~
LSI-11/73 Cache Layout
The Cache Entry Address is the address of one of 4096 entries within the
cache.
This value has a one-to-one relationship with a field in each
address that is generated by the processor (described in the next
section on how the physical address accesses cache).
Each field has the following meaning:
Tag (TAG) - This nine bit field contains information that is
compared to the address label, described in the next section on
how the physical address accesses cache.
When the physical
address is generated, the address label is compared to the tag
field.
If there is a match it can be considered a hit provided
that there is entry validation and no parity errors.
Cache Data (BO and B1) - These two bytes
stored in cache.
75
are
the
actual
data
uNOTE # 009
Page 4 of 6
Valid Bit (V) in BO and B1 is
bit is set when
which occurs as
The valid bit indicates whether the information
usable as data if a cache hit occurs. The valid
the entry is allocated during a cache update
a result of a miss.
Tag Parity Bit - (P) - Even
stored in the tag field.
parity
calculated
for
the
value
parity Bits (PO and P1) - pO is even parity calculated for the
data byte BO and P1 is odd parity calculated for the data byte
B1.
When the processor generates a physical address,
the on-board cache
control logic must determine if there is a hit by looking at the unique
location in cache. To determine what location to check,
the cache
control logic considers each address generated as being made up of three
unique parts. The following are the three fields of a 22-bit address
(in an unmapped or lS-bit environment the label field is six or four
bits less respectfully):
21 20 19 18 17 16 15 14 13
1<
LABEL
-------->1
12 11 10 09 OS 07 06 05 04 03 02 01
1<-------------
INDEX
----------->1
00
BYTE,
SELEC~
Figure 2 - Components of a 22-bit Address For Cache Address Selection
Each field has the following meaning:
Index - This twelve bit field determines which one of the 4096
cache data entries to compare with for a cache hit. The index
field is the displacement into the cache and corresponds to the
Cache Entry Address.
Label - Once the location in the cache is selected, the nine bit
label field is compared to the tag field stored in the cache
entry under consideration.
If the address label and the tag
field match, the valid bit is set, and there is no parity error,
then a hit has occurred.
Byte Select Bit - This bit determines if the reference is on an
odd or even byte boundary. All Q-bus reads are word only so
this bit has no effect on a cache read. Q-bus writes can access
either words or bytes.
If there is a word write the cache will
be updated if there is a hit.
If there is a miss a new cache
entry will be made.
If there is a byte write, the cache will
only be updated if there is a hit. A miss will not create a new
entry on a byte write.
76
uNOTE # 009
Page 5 of 6
The LSI-ll/73 direct map cache mu:;t update the backing store on a memory
write.
The LSI-ll/73 uses the write through method.
With this
technique, writes to backing store occurs concurrently with cache
writes.
The result is that the backing store always contains the same
data as the cache.
Features Of The LSI-ll/73 Cache
The LSI-l1/73 direct map cache has a number of features that assist in
the performance of the overall system in addition to the speed
enhancement as a result of faster memory access. These features consist
of the following:
o
o
o
o
o
Q-bus OMA monitoring
I/O page reference monitoring
Memory management control of cache access
Program control of cache parameters
Statistical monitoring of cache performance
The LSI-ll/73 cache control logic monitors the Q-bus during OMA
transactions.
When an address that has its data stored in cache is
accessed during OMA, the cache a:nd backing store contents might no
longer be the same.
This is an unacceptable situation. The cache
control logic invalidates a cache entry if the address is used during
OMA.
This also includes addresses used during Q-bus Block Mode OMA
transfers.
Memory referen 7es to the I/O page are not cached since that data is
volatile, meanlng its contents can change without a Q-bus access. Since
the cache could end up with stale data, I/O references are not cached.
There are situations for which using the cache to store information for
faster access is not desirable. An example is a device that resides in
the I/O page, and is true in other instances as well. One situation is
a device that does not reside in the I/O page but can change its
contents without a bus reference, such as dual ported memory.
Another situation is partitioning and tuning an application
for
instruction code execution versus data being manipulated.
In this case
the instruction stream may execute many times over for different data
values.
Speed enhancement can be obtained if the instructions are
cached while the data is not cached. By forcing the data never to be
cached it cannot replace instructions in the cache.
The memory management unit (MMU) of the LSI-l1/73 can assist in this
situation.
Pages of memory allocated for data can be marked to bypass
the cache and therefore not effect instructions that loop many times.
The cache and the MMU work together to achieve the goal of increased
system performance.
The dynamics of cache operation are under program control through use of
the Cache Control Register (CCR), an LSI-ll/73 on-board register. This
77
uNOTE # 009
Page 6 of 6
register can "turn" the cache on or off, force cache parity errors for
diagnostic testing, and invalidate all cache entries. The details of
the CCR are described in the KDJll-A CPU Module User's Guide (part
number EK-KDJ1A-UG-001).
During system design or at run-time the performance enhancements
provided by the cache system can be monitored under program control.
This is accomplished by using another LSI-ll/73 on-board register the
Hit/Miss Register (H~R).
This register tracks the last six memory
references and indicates if a hit or miss took place.
The details of
the HMR are also described in the KDJll-A CPU Module User's Guide.
Summary
Caches are a mechanism that can help improve overall system performance.
The dynamics of a given cache are dictated by the organization and the
behavior of the programs running on the machine. The LSI-ll/73 cache is
designed to be flexible in its use,
simple in implementation, and
enhance application performance.
More detailed discussions on how caches work
and
other
cache
organizations can be found in computer architecture texts that have a
discussion of memory hierarchy.
78
uNOTE
* 010
Title: MicroVAX I/O Programming
Date: 27-JUL-84
Originator: Peter Jonhson
Page 1 of 5
The Qbus MicroVax implements the full Vax memory management, so virtual
addresses are translated to physical addresses - just as they are for
the Vax minicomputers. When memory management is enabled,
system and
process space virtual addresses ,are translated into physical addresses
and sent onto the Qbus. Normally,
the programmmer need not concern
himself with this translation ,as this is completely handled by the
operating system; however, when accessing locations in the I/O space
directly the programmer must concern himself with the mapping since
specific information must be supplied by the programmer to MicroVMS in
order for it to successfully map the user's virtual addresses into the
I/O space. The process of mapping a virtual address to a physical
address must start by determining the physical address that you wish to
access.
In our case this means that we must calculate a Qbus MicroVax
physical address given that we know the address that the Qbus board is
configured to.
In order to do this we must know a few key facts about
the Qbus MicroVax architecture.
1) The Qbus MicroVax I/O space begins at physical 20000000 (hex)
2) The I/O space of a Qbus MicroVax is largely empty containing
only Q22 bus I/O space which is SK bytes long
Given these two pieces of information we now know that the I/O space for
the Qbus MicroVax starts at physical 20000000 (hex) and extends to
20001FFF (hex). This I/O space directly corresponds to the configurable
addresses on Qbus option boards 160000-177777 (oct).
In order to
convert any Qbus option address to a Qbus MicroVax address one simply
subtracts 160000 from the boards configured address to get its offset
into the I/O space and then add this value to the base of the Qbus
MicroVax I/O space. For example, let us consider a board which has been
configured to-166540.
In order to calculate its equivalent Qbus
MicroVax address we would do the following:
79
uNOTE # 010
Page 2 of 5
1) Subtract. off the I/O base address for this board (160000)
166540 (oct)
160000 (oct)
6540 (oct) -->
060 (hex)
2) Add the board's address offset to the Qbus MicroVax I/O space
base address
+
20000000 (hex)
060 (hex)
20000060 (hex)
This addition results in the physical address on the Qbus MicroVax
system that this board would answer to.
Now we have calculated the physical address for the board in the Qbus
MicroVax environment.
This value, however, is in the raw state and is
still not usable by the uVMS software to perform virtual to physical
address translation.
In order for this address to be useful to the
software it must now be converted from a physical address to a page
frame number.
The page is the basic unit of memory mapping and
protection. A page is 512 contiguous byte locations.
A page frame
number (PFN)
is the address of the first byte of a page in physical
memory. This means that the lsb ofa PFN has the resolution of 1 page
or 512 bytes.
It is a simple matter now to convert a physical address
to a PFN. Since the lsb of a PFN is 1 page to convert a physical
address to PFN just shift right the physical address 9 bits, i.e.
shift
off the 9 least significant bits.
physcial 20000060 (hex)
shift right 9 --> PFN 100006 (hex)
The PFN value which we have calculated is sufficient to allow the system
to map a physcial page of addresses into your virtual address space.
The address of the Qbus option resides somewhere in the page which we
have mapped.
It is the responsibility of the programmer to correctly
offset from the beginning of the page in order to access the board i.e.
the programmer _must displace from the base of the mapped page with the
correct virtual address offset.
To determine the offset from the
beginning of the mapped page look to bits 0-9 of the configured address
of the Qbus option board - this is the offset.
In our example the
offset would be:
80
uNOTE # 010
page 3 of 5
166540 (oct)
I I
\ I
I
540
bits 9-0 are the offset
This offset would be used by thE! programmer to access the device
registers on the board. Failure to use the offset will usually result
in an attempt to access non-esxistE!nt locations (analagous to memory
time-outs) which will result in an access violation error being returned
to the user. A sample program follows which illustrates the principles
which have been discussed.
It uses the same board address discussed
earlier so that one can see the code needed to acutally implement the
previous example.
The following program illustrates, in a raw fashion, how one might
actually access the I/O space with software.
It is not meant to
illustrate good or recommended pro9ramming practice but rather to show
the mechanics of accessing the I/O space of a Qbus on MicroVax I.
81
uNOTE # 010
Page 4 of 5
iThis program will allow a user with suitable privilege to access
idevice registers in the I/O space of a uVax. This example shows
icode which is used to extract data from a DRV11 - a general purpose
iparallel interface which resides in I/O space. It is sufficiently
igeneral to allow the concept to be used in other situations where
iaccess to the I/O space from a user process is desireable.
iThis portion of the program is responsible for creating the
ivirtual to physical mapping required to access registers in
ithe I/O space. For this example the device registers are assumed to
istart at 166540. In order for virtual to physical mapping to occur
ithe user must calculate the physcial page frame that the device
iregisters overlap into. (See accompanying text for how to do this)
iCreate and map section directive does the actual work of mapping.
iln order for this system service to work correctly the
iuse must have PFNMAP privilege
.entry
start,A m<>
$crmpsc s inadr .-maprange, retadr - actadr, -
ilnput virtual address range
iVirtual address range acutally
imapped
iNon zero required for page frame
pagcnt • #1, isection
flags -#, iActual page frame of I/O space
vbn - pfn number
ipage which contains device registers
blbs
rO,continue
icheck the return status of create
iand map - if successful branch
pushl
calls
rO
#l,g"'lib$stop
iput status onto stack
itell him what happened and
istop program
82
uNOTE # 010
Page 5 of 5
iAt this point one page of virtual addresses in the user's process
ispace is now mapped into one page of the I/O space. Now the user
ican access device registers by using move instructions.
i •••••• ** Please note that only certain instructions are allowed when
idoing physical I/O to the bus. For example a MOVL instruction is
iNOT legal to the I/O space.
continue:
movl
actadr, r6
;Get starting virtual address from
addl
# . . x160, r6
;system service and put into R6
;Add the displacement into this page
ito access the device registers
iAccess data from the parallel interface
tstb
bgew
movw
(r6)
10$
4(r6), data in buffer
10$:
$exit s code ;; #1
;Test for data transfer request
;If no data exit
;Data is present - store it
;exit gracefully
;data for program •••.•.
maprange:
.long
.long
"'x4.00
"'x800
control status
data in-buffer
.word
.word
o
actadr:
.blkl
2
.long
"'x100006
.end
o
start
83
;holds returned virtual
; address range
;actual pfn of I/O page to
;be mapped
84
uNOTE # 011
Title: LSI-11/73 ADVANCED MEMORY MANAGEMENT
Date: 04-Sep-S4
Originator: Art Bigler
Page 1 of 11
This micronote examines the advanced memory
management
features
available on the DCJ11 based LSI-11/73 series processors (KDJ11-A,
KDJ11-B).
These features include the
standard
virtual
address
relocation within the physical address space and the kernel and user
execution modes, all of which are currently available as options on the
mid-range LSI-11/23 (KDF11-A, KDF11-B) processors.
In addition to these
features, the DCJ11 based processors also provide instruction and data
space (I/O space) memory management and the supervisor execution mode.
The following discussion is intended to further clarify these features.
For information pertaining to address relocation the reader is referred
to micronote OOS, MEMORY MANAGEMENT AND THE LSI-11/73.
1.0
INSTRUCTION/DATA SPACE M:EMORY MANAGEMENT
I/O space memory management is utilized in the DCJ11 based processors IN
ADDITION TO the relocation of virtual addresses within the physical
address space. This provides the ability to place multiple program
images in physical memory while at the same time providing an increased
virtual address space of 128 kb OI' 64 kw by mapping instructions and
data to separate areas of physical memory. The means by which I/O space
memory management is attained involves both hardware and software as
described in the following paragraphs.
I/O SPACE HARDWARE
1.1
The hardware required to implement: I/O space addressing is integrated
into the memory management uni.t and is standard on all DCJ11 based
processors. This includes the following:
1.
Eight (8) additional active page registers (APR'S)
per
execution mode (more about execution modes later). These APR's
are used to map to the data space when I/O space memory
management is enabled.
1.
Additional control and status bits in memory management
registers 0 and 3 (MMRO, MMR3) which are used to control the
enabling and disabling of data space addressing.
INSTRUCTION
SPACE ADDRESSING IS ALWAYS ENABLED.
85
uNOTE # 011
Page 2: of 11
1.1.1
ACTIVE PAGE REGISTERS
The hardware provides a total of sixteen (16) APR's per execution mode,
eight (8) instruction space registers and eight (8) data space registers.
THE APR's are further divided into page descriptor registers (POR'S)
and
page address registers
(PAR's) as described in micronote 008.
The
physical addresses for these registers are contained in the I/O page and
are as follows:
MODE
-
.
-
KERNEL
I
SPACE
PAR's
POR's
PAGE
17772340
17772300
0
17772342
17772302
1
17772344
17772304
2
17772346
17772306
3
17772350
17772310
4
17772352
17772312
5
17772354
17772314
6
17772356
17772316
7
17772360
17772320
0
17772362
17772322
1
17772364
17772324
2
17772366
17772326
3
17772370
17772330
4
17772372
17772332
5
17772374
17772334
6
17772376
17772336
7
I-
I-
KERNEL
I-
0
SPACE
f-
I-
-
TABLE 1a
KERNEL MODE APR'S
86
uNOTE # 011
Page 3 of 11
MODE
-
-
SPVSR
I
SPACE
-
I-
SPVSR
D
SPACE
PAR's
PDR's
PAGE
17772240
17772200
0
17772242
17772202
1
17772244
17772204
2
17772246
17772206
3
17772250
17772210
4
17772252
17772212
5
17772254
17772214
6
17772256
17772216
7
17772260
17772220
0
17772262
17772222
1
17772264
17772224
2
17772266
17772226
3
17772270
17772230
4
17772272
17772232
5
17772274
17772234
6
17772276
17772236
7
I-
I-
TABLE 1b
SUPERVISOR MODE APR'S
87
uNOTE # 011
Page 4 of 11
MODE
POR's
PAR's
PAGE
17777640
17777600
0
17777642
17777602
1
17777644
17777604
2
17777646
17777606
3
17777650
17777610
4
17777652
17777612
5
17777654
17777614
6
17777656
17777616
7
17777660
17777620
0
17777662
17777622
1
17777664
17777624
2
17777666
17777626
3
-17777670
17777630
4
17777672
17777632
5
17777674
17777634
6
17777676
17777636
7
~
~
~
~
USER
I
SPACE
~
~
~
~
~
USER
~
0
SPACE
~
~
~
TABLE 1c
USER MODE APR'S
1.1.2
MEMORY MANAGEMENT REGISTER 0
Memory management register 0 (MMRO) contains control
and
status
information for the memory management unit (MMU). This register is
discussed complete~y in micronote 008, to which the reader is again
refferred for information on those functions which are not directly
applicable to I/O space and supervisor mode.
MMRO contains three (3) status bits which are used in the implementation
of I/O space memory addressing. These bits, 04 through 06, yield MMU
status information whenever a MMU abort occurs and are used
in
88
uNOTE • all
page 5 of 11
conjunction with MMRO bits 01 t:hrough 03 and 13 through 15 to provide
complete execution mode and I/O spcLce status for the page causing the
abort. See figure 1.
Bit 04, the page address space status bit,
associated with the aborted page and
instruction space page and a one (1) for a
space addressing is enabled. If I/O space
bit always reflects a zero (0).
indicates the address space
is equal to a zero (0) for an
data space page whenever I/O
addressing is not enabled this
Bits 05 and 06, the processor mode status bits, indicate the processor
execution mode associated with 1:he page causing the abort. These bits
are coded as follows:
BIT
06 05
EXECUTION MODE
o
0
KERNEL
o
1
SUPERVISOR
1
0
ILLEGAL (causes an abort with bit 15 set)
1
1
USER
For more information on MMU aborts see micronote 008.
89
uNOTE # 011
Page 6 of 11
MMRO
1
5
1
4
1
3
1
2
1
1
1
o
ADDRESS: 17777572
o
9
o
8
o
7
o
6
o
5
o
4
o
o
3
2
o
1
o
o
READ-ONLY
ACCESS VrOLATION
~--ABORT
~-------ABORT
~-----------ABORT
PAGE LENGTH ERROR
NON-RESIDENT
PAGE
ENABLE
ADDRESS
RELOCATION
SPACE (I/D)
BIT #
DESCRIPTION
<15>
<14>
<13>
<12:07> <06:05> <04>
<03:01> <00>
ABORT READ-ONLY ACCESS VIOLATION (R ONLY)
ABORT PAGE LENGTH ERROR (R ONLY)
ABORT NON-RESIDENT (R ONLY)
NOT USED (R ONLY)
PAGE MODE (R ONLY)
PAGE ADDRESS SPACE (I/D) (R ONLY)
PAGE NUMBER (R ONLY)
ENABLE RELOCATION (R/W)
FIGURE 1
MEMORY MANAGEMENT REGISTER 0 (MMRO)
MEMORY MANAGEMENT REGISTER 3
Memory management register 3 (MMR3)
contains control
and
status
information for data space addressing, 22 bit mapping, and the call to
supervisor mode
(CSM)
instruction.
This register,
once again,
is
discussed in detail in micronote 008.
MMR3 contains three (3) control bits which are used in the implementation
of I/D space addressing.
These bits, 00 through 02, individually enable
data space addressing for each of the execution modes.
Bit 00 enables
data space addres$ing for the USER mode, bit 01 enables it for SUPERVISOR
mode, and bit 02 enables it for KERNEL mode.
The desired bits are set to
a one
(1) whenever data space addressing is desired.
MMR3 is cleared
during power-up,
console restart,
and the execution of the RESET
instruction.
See figure 2.
90
uNOTE # 011
Page 7 of 11
ADDRESS: 17772516
MMR3 REGISTER
1
5
0
I
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
0
0
0
0
0
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
UNINTERPRETED------------~
ENABLE 22 BIT
ENABLE CSM
MAPPIN~------~
INSTRUCTION-------~
KERNEL------------------------------~
SUPERVISOR------------------------------~
USER--------------------------------------~-~
BIT #
DESCRIPTION
<15:06> <05>
<04>
<03>
<02>
<01>
<00>
NOT USED (R ONLY)
UNINTERPRETED (R/W)
ENABLE 22 BIT MAPPING (R/W)
ENABLE CSM INSTRUCTION (R/W)
KERNEL DATA SPACE (R/W)
SUPERVISOR "DATA SPACE (R/W)
USER DATA SPACE (R/W)
FIGURE 2
MEMORY MANAGEMENT REGISTER 3
I/O SPACE ADDRESS MAPPING
1.1.4
When I/O space addressing has been enabled the MMU hardware performs the
address mapping (IN ADDITION TO ADDRESS RELOCATION WHICH IS PERFORMED
USING THE APPROPRIATE SET OF APR'S) as follows:
1.
2.
The ~urrent instruction is ALWAYS fetched from the
. space.
The operands are mapped according to table 2.
91
instruction
uNOTE # 011
Page 8 of 11
OPERAND
ADDRESSING
MODE
REGISTER
USED
TYPE
OF
ADDRESSING
I OR D
SPACE
USED
000
ANY
REGISTER
I
001
ANY
REGISTER
DEFERRED
D
010
0 THROUGH 6
AUTOINCREMENT
D
7
IMMEDIATE
I
0 THROUGH 6
AUTOINCREMENT
DEFERRED
D (A)
D (D)
7
ABSOLUTE
I (A)
D (D)
0 THROUGH 6
AUTODECREMENT
D
7
DO NOT USE 11
0 THROUGH 6
AUTODECREMENT
DEFERRED
7
DO NOT USE 11
110
ANY
INDEX
I ( A)
D (D)
111
ANY
INDEX
DEFERRED
I (A)
D (A)
D (D)
011
100
101
D (A)
D (D)
(A) - INDIRECT OR INDEX ADDRESS
(D) =- DATA
TABLE 2
OPERAND ADDRESSING WITH DATA SPACE ENABLED
All address mapping is performed using the I space APR's when data
addressing is not enabled.
space
The most difficult example showing data space
deferred type of addressing.
index
92
addressing
is
the
uNOTE # 011
Page 9 of 11
CLR
@1000(R3)
1.
The instruction
location pc.
is
fetched
2.
The base address 1000 is fetched from the instruction space at
location PC+2.
The index in R3 is added to the base address
forming the address of the indirect address.
3.
The indirect address is fetched from the data space
address calculated in step 2.
4.
The data is fetched from
calculated in step 3.
data
the
instruction
space
using
space
using
at
the
the
address
At the present time I/O space addressing is supported by two (2)
supplied operating systems, RSX-llM-PLUS and ULTRIX-l1.
Digital
1.2
the
from
I/O SPACE SOFTWARE
RSX-11M-PLUS provides linking of tasks which utilize I/O space addressing
via the task builder (TKB) utility. Those programs which include the
data PSECTs in their object files may be task built using the /ID switch.
It should be noted that the task may not make use of the entire 32kw data
space because RSX-llM-PLUS requires that the stack and the task header be
placed in data space.
Other restrictions may apply, consult the task
builder manual for further information.
When using I/O space with other operating systems or in standalone
programs,
the user must do all the mapping within the program. This
implies that the mapping of the operating system must be attended to by
the user program if operating system features are to be utilized.
To make use of data space addressing the program must:
1.
Separate the instruction space from the data space.
(ie.
create different regions in memory for instructions and data)
2.
Load the instruction space and data
appropriate relocation information.
3.
Enable I/O space mapping by setting the MMR3 bit associated
with the execution mode under which the program will run.
The following
~estrictions
space
APR's
with
the
apply to I/O space programs:
1.
The instruction space can only contain instructions,
operands,
absolute addresses, and index words.
reflected in table 2.
immediate
This is
2.
The stack page must be mapped into both
and
93
instruction
data
uNOTE # 011
Page 10 of 11
space if the
off the stack.
MARK instruction is used because it is executed
3.
Instruction space-only pages
cannot
contain
subroutine
parameters which are data. This precludes the mapping of any
pages containing standard PDP-11 calling sequences entirely
into an instruction space page.
4.
The trap catcher technique of putting .+2 in the trap vector
followed by a halt must be mapped into both instruction and
data space.
For further information on I/O space addressing under
ULTRIX-11 consult the appropriate documentation set.
2.0
RSX-11M-PLUS
and
SUPERVISOR MODE
'The DCJ11 based processors provide three (3) execution modes:
KERNEL,
SUPERVISOR, and USER.
They provide for various forms of memory and
processor protection and permit additional features to be implemented in
:multiprogramming environments.
Each mode has its own set of mapping
registers.
KERNEL mode is the most privileged of the modes, allowing the execution
of any instruction and the modification of any area in memory including
the I/O page.
USER mode prohibits the execution of privileged instructions such as HALT
and RESET and the modification of areas in memory that the KERNEL program
does not provide access to.
SUPERVISOR mode has the same privileges as USER mode with its awn set of
mapping
registers,
thus
providing
another level of protection.
SUPERVISOR mode is intended for use in the mapping and execution of
programs to be shared by users while still providing protection from
them. Examples of this are command line processors which are required
for use by all users on a system, while necessitating write protection
from them.
The execution mode is controlled by the state of bits 14 and 15 in the
processor status word (PSW). These bits are changed by the execution of
traps and interrupts, pushing and popping of old PSW's to and from the
stack, and, when in KERNEL mode, the direct manipulation by the program.
Bits 12 and 13 re(lect the execution mode which existed prior to the
event which placed the processor in the current mode. See figure 3.
94
uNOTE 41: 011
Page 11 of 11
The current and previous mode PSW bits are coded as follows:
BIT
15 14
13 12
0
0
1
1
EXECU~rION
0
1
0
1
MODE
KERNE1~
SUPERVISOR
ILLEG1~L
USER
PROCESSOR STATUS WORD (PSW)
1
5
1
4
1
3
1
2
1
1
1
0
0
9
CURRENT PREVIOUS
MODE
MODE
GPR
GROUP
BIT
0
7
0
6
0
5
0
4
PRIORITY
LEVEL
SUSPENDED
INFORMATION
-
TRACE
BIT
CURRENT MODE (R/W)
PREVIOUS MODE (R/W)
GENERAL PURPOSE REGISTER SET (R/W)
NOT USED (R ONLY)
SUSPENDED INFORMATION (R/W)
PROCESSOR PRIORITY LEVEL (R/W)
TRACE BIT (R/W)
NEGATIVE CONDITION CODE (R/W)
ZERO CONDITION CODE (R/W)
OVERFLOW COND:ITION CODE (R/W)
CARRY CONDITION CODE (R/W)
:rIGURE 3
PROCESSOR STATUS WORD
95
0
3
0
2
0
1
CONDITION
CODES
DESCRIPTION
41:
<15: 14>
<13:12>
<11>
<10:09>
<08>
<07:05>
<04>
<03>
<02>
<01>
<00>
0
8
ADDRESS: 17777776
0
0
96
uNOTE
Title:
DMA on The Q-bus
Originator:
* 012
Date: 06-SEP-84
Jack Toto
Page 1 of 4
This Micronote explains the various, types of DMA on
Cycle Mode, Burst Mode and Block Mode.
the
Q-bus;
Single
SINGLE CYCLE MODE:
Single cycle mode DMA like all DMA on ~he Q-bus requires that the DMA
device gain control of the bus through an arbitration cycle. During the
arbitration cycle the DMA device be!comes bus master by first asserting a
DMA request (BDMR).
When the arbiter acknowledges this request it
issues a DMA grant (BDMGO).
In the' event that there is more than one
DMA device in the backplane the grant signal is daisy chained from
device to device.
Eventually the device that issued the DMA request
will latch the grant signal and take control of the bus, and proceed
with the DMA transfer.
Once becoming bus master the device asserts BSACK and is allowed to do
one word tranfer to or from memoI'y, during which time the CPU is idle.
Certain processors such as the KCJ1.1-B have a cache memory with dual tag
store which allows it to process dSlta while DMA transfers are occurring.
Regardless of which processor type is used only one transfer is allowed
in single cycle mode.
If the device must perform additional transfers,
it must go through the bus arbitration cycle again.
~~----------~
SACK
BDAL
ADRS/DATA
ADRS/DATA
1
2
In single cycle mode, the theoretic:al transfer rate across the Q-bus is
1.66 Mbytes/sec (833Kw/sec) A dE!vice such as the DRVll-B or the newer
22-bit compattble DRV11-W can trane;fer data at a rate of 250KW/sec while
in single cycle mode.
97
uNOTE # 012
Page 2 of 4
BURST MODE:
Burst mode DMA can be performed by certain devices such as the DRV11-B.
Once the DMA controller becomes bus master (through the arbitration
routine described in the single cycle section and it has asserted BSACK,
the DMA tranfers can begin.
Each data word that is transfered is
accompanied by an address that the data word is targeted for.
In burst
mode loading an octal value into the 16 bit word count register (WCR)
allows for that number of words (64Kb max) to be transfered under one
sack.
This differs from single mode, in that the word count register
can be loaded with the same value, but each single word transfer will
require a new arbitraion cycle, i.e in order to transfer 64Kb of data it
would require 65,536 arbitration cycles.
SACK
BDAL
--~IADRS/DATA
ADRS/DATA ADRS/DATA .........••.....
(N)~I----
N :- word count;
The theoretical transfer rate across the Q-bus in burst mode remains at
1.66 Mbytes/sec, however a device such as the DRV11-B operating in burst
mode can transfer data at a rate twice that of a DRV11-B operating in
single mode,
or 500Kw/sec.
In burst mode the DMA bus master maintains
control of the bus until it has transferred all of the required data.
Burst mode has the advantage of moving large blocks of memory across the
bus with no delay. The caution here is that no other device
(including
the CPU) has access to the bus during that time. This can have severe
impact on system performance.
DMA COMPROMISE:
Since Single Cycle Mode requires a rearbitration for every data transfer
and Burst Mode can adverseley impact system performance in some cases
DIGITAL EQUIPMENT CORP. has made some compromises with certain DMA
controllers.
Most DIGITAL devices will do a limited Burst Mode
operation. Thes~controllers (for example the RXV21 and RLV12)
are
98
uNOTE # 012
Pag·e 3 of 4
~llowed
up to do four words of data tranfer.
Each word of transfer is
preceeded on the bus by an address that the data word is targeted for.
This allows data to move across the bus with a minimum of rearbitraton.
However, when a group of four t,ransfers is finished,
the DMA devices
must again go through the arbitration cycle in order to allow other
devices the opportunity to use the bus.
If no other bus requests are
pending at a higher priority, then bus mastership will be returned to
the device for the next set of data transfers.
SACK
____----Ir
BDAL
--------1' ADRS/DATA
P..DRS/DATA ARDS/DATA ADRS/DATA ....
' --1 2 3
4
BLOCK MODE:
For increased throughput, Block Mode DMA may be implemented on a device
for use with memories that support this type of transfer. Block Mode
DMA devices are only block mode when operating. They may not operate as
a Single or Burst Mode device. They may, however, appear to operate
dike a single mode device if they are only doing a single word transfer,
and they will always look like a Single Cycle Mode DMA device when used
with non-Block Mode memory.
Once a Block Mode device has arbitrated for the bus, the starting memory
address is asserted,
then data for that address, followed by data for
consecuetive addresses. By eliminating the assertion of the address for
each data word,
the transfer ratE~ is almost doubled.
The DMA device
should monitor the BDMR line.
If thE~ line is not asserted after the
seventh transfer than the device can continue. This allows a maximum of
16 data transfers for one abitration cylce.
If the BDMR line is not
monitored by the DMA device than a maximum data tranfer of 8 words is
allowed after completing one bus arbitration cycle.
Block Mode DMA
transactions can be described as two types, a DATBI (block mode data in)
and DATBO (block mode data out). Both of these cycles are explained in
depth in Micronote #002.
When reading the appropriate micronote
special attention should be paid to the use of BREF and BBS7 signals
when performi~g a DATBO.
99
uNOTI~ # 012
:~age 4 of 4
BOAL----l AORS/OATA/ ......... DEPENDS ON STATE OF BOMR L-_
(1)
* (7)
(16)
I
BDMR~---------------------*-----------------------/\/\/
Block Mode devices such as the DEQNA, RQOXl and the MSV11-P memories can
transfer data across the bus at rates that approach twice that of OMA
devices in Burst Mode. The actual rate is dependent upon the device
itself.
The technical manuals for each of these devices should be
checked for actual performance figures.
100
uNOTE
* 013
Title: Run-time System Performance Evaluation
Using MicroPower/Pascal V 1.5
Date: 09-0ct-84
Originator: Herbert Maehner
Page 1 of 5
In real-time programming, the performance of the run-time system and the
compiler together govern the overall power of the application. The
performance of the MicroPower/Pascal compiler has been extensively
discussed by R.Billig/R.Cronk [1].
The performance of the run-time executive of MicroPower/pascal is
measured in this MicroNote using different LSI-11 CPU-boards and the
KXT11-CA I/O processor.
Data was obtained using Micropower/Pascal
version 1.5.
Test Conditions
Results obtained through a lab experiment are only as precise as the
test environment and may only be referenced giving the exact test
conditions.
The goal was to measure the elapsed time of a given primitive execution
on the Pascal process level, i.e. how long it takes to call/execute a
kernel primitive from a Pascal program.
Generally, the following procedure was used to obtain the elapsed time,
where in some cases more than one output bit has been used to obtain the
desired pulse-width.
WHILE Condition - TRUE DO
BEGIN
out_port.bitO := TRUE;
{ here call/execute given primitive }
Out port.bitO :- FALSE;
END; The whole test was done in a loop as long as the condition was true.
Here, Condit~n is a boolean variable, which is set FALSE by a high
priorty process waiting on a terminal input (READLN).
The Outport.bitO is bitO of a parallel device.
101
The parallel device
was
uNOTE # 013
Pac.;re 2 of 5
either
devi~e
a DRV11 (using LSI 11/23 and LSI 11/73) or the on-board parallel
(using the FALCON plus SBC 11/21 and KXTI1-CA).
The bitO pulse is used as the input to an oscilloscope which has the
capabilities to measure and display time differences and frequencies.
The elapsed time required to execute the various primitives was
obtained.
In addition to the primitive requests some math-functions
times were obtained.
The results are shown in Table 1 at the of this
MicroNote.
Interrupt-Test Conditions
A pascal-program with an embedded interrupt service routine needs DRIVER
privileges in a mapped environment. The test program either connects to
a "normal" ISR or to a prio7 ISR.
The program executed a simple loop
like:
WHILE TRUE DO
BEGIN
Out port.Bit1 := TRUE;
Out-port.Bit1 :- FALSE;
ENDiThe Outport is the parallel device of the type mentioned above.
This is
used to monitor process execution behavior.
Testing the interrupt
response time, we used a square wave generator which triggered an
interrupt on that parallel device.
The ISR was coded as
.ENABL
. MCALL
.MCALL
GBL
MACDF$,PURE$
IMPUR$
Enable global symbols
Set-up pure/impure area
.GLOBL
lNPORT,OUTPRT
port A,B of PPl
MACDF$
PURE$
MACDF$ must be called before the
two assembly directives
. DSABL AMA
PPIINT: :
BlSB
MOVB
MOVB
BICa
RTS
RTS
TEMP:
#l,@#OUTPRT
@#INPORT,@#Temp
@#INPORT,@#Temp
#l,@#OUTPRT
PC
R4
IMPUR$
.WORD 0
.END
set bit 0 output port
dummy read
dummy read
set bit 0 output port
normal lSR return
prio 7 lSR return
reserve one word
102
1];
ISR time
measured
uNOTE # 013
Page 3 of 5
Depending upon the ISR-type either the RTS PC or the RTS R4 must be used
to exit the ISR. The first MACRO-statement within the ISR signaled bitO
of the parallel port. The resultinq interrupt dispatch time was defined
as the pulse width given by the square wave generator edge and the
signaled output port. This includes the hardware ISR dispatch time as
well.
The ISR execution time was given by the pulse width indicated
within ISR source above. Again, all pulses were measured using an
oscilloscope.
The maximum interrupt rate was determined by increasing
the square frequency (whi.ch in turn increases the outpt square wave of
the ISR) until the system lost interrupts.
Using CONNECT SEMAPHORE the interrupt performance
was
similarly
measured.
In this case only a dynamic process was waiting on the
semaphore to be signaled. The results are shown in table 2.
References
1. Rich Billig and Randy Cronk,. A System/Architecture Approach to
Microcomputer Benchmarking, DIGITAL Equipment Corporation,
Sept. 1982, EZ-12053-03/82
2. MicroPower/Pascal Newsletter, Volume 1, No.1, March 1984, p. 23,
DIGITAL Equipment Corporation, Order Number AV-B067A-TK
103
uNOTE # 013
Page 4 of 5
LSI-11/23
w/o FPU
m
u
LSI-11/23
w/ FPU
m
u
LSI-11/73
u
m
SBC
11/21+
Process
creation
deletion
3.1
2.4
5.48
4.19
3.56 5.93
2.55 4.35
1.84 2.64
1.14 1.92
3.96
2.96
2.71
2.06
Schedule +
context Switch
0.56 0.97
0.82 1.27
0.38 0.57
0.69
0.49
0.55 0.96
0.50 0.93
0.55 0.99
0.51 0.95
0.27 0.42
0.25 0.39
0.67
0.63
0.47
0.43
0.61 1.05
0.58 1.01
0.61 1.05
0.58 1.02
0.29 0.43
0.28 0.42
0.72
0.70
0.51
0.49
0.73 1.20
0.71 1.17
0.73 1.18
0.71 1.15
0.36 0.50
0.35 0.49
0.88
0.86
0.62
0.60
0.35 0.64
0.61 0.93
0.36 0.65
0.35 0.65
0.61 0.94
0.36 0.66
0.16 0.25
0.27 0.37
0.17 0.29
0.44
0.75
0.44
0.30
0.52
0.30
0.42 0.84
0.42 0.85
0.20 0.33
0.50
0.35
1.17 2.18
1.46 2.50
1.18 2.20
1.46 2.51
0.59 0.89
0.73 1.11
1.45
1.79
1.01
1.24
1.26 2.28
1.59 2.64
3.09 4.32
1.26 2.31
1.59 2.67
3.09 4.35
0.67 0.96
0.84 1.14
1.74 2.11
1.54
1.94
3.78
1.08
1.35
2.63
Operation
Ring buffer
1 cnaracter
get
put
2 characters
get
put
4 characters
get
put
Signal Semaphr
by descriptor
by name
fast named
Get status
Send + Receive
(by value)
- 1 Byte
- 34 Bytes
Send + Receive
(by reference)
- 10 Bytes
- 100 Bytes
- 500 Bytes
KXT11
-CA
I
TAN
6.84 7.74
1.64 1.68
0.35 0.36
9.00
6.24
SIN
5.13 5.82
1.75 1.78
0.33 0.34
6.80
4.69
COS
6.19 7.00
1.94 1.98
0.39 0.39
8.15
5.64
5.04 5.69
1.45 1.48
0.32 0.33
6.55
4.59
5.34 6.01
1.27 1.31
0.28 0.29
6.95
4.86
EXP
LN
-
Table 1: Micropower/Pascal V1.5 Runtime System
104
(millisE~c)
uNOTE # 013
Page 5 of 5
Notes for Table 1
o
o
o
o
u - without MMU and m - with MMU
FPU = with floating point unit (KEF11)
Send/Receive without context-switch
SBC-ll/21+ using on-board memory only
Operation
LSI-l1/23
m
u
LSI-11/73
m
u
Interrupt dispatchtime (usec)
62
91
42
ISR execution
time (usec)
20
23
Maximal interruptfrequency (kHz)
7.0
sac
11/21+
KXT11
-CA
ISR:
5.1
54
13.4
12.9 10.9
81
61
21
16
4.8
7.5
32
28
21
16
12.8
16.5
PRI07 ISR:
Interrupt dispatchtime (usec)
28.5
60
ISR execution
time (usec)
20
24
Maximal interruptfrequency (kHz)
17.8
9.3
22
38
13.4
26
16
CONNECT SEMAPHORE: (one process waiting on that semaphore)
Interrupt dispatch +
context-switch time
(msec)
0.88 1.36
0.49 0.63
1.15
0.82
Maximal interruptfrequency (kHz)
0.67 0.39
1.20 0.83
0.41
0.75
Table 2: Interrupt Performance
Note for Table 2
Additionally, the system had to service the clock interrupt
at
rate of 50 Hz without the clock driver implemented, i.e.
the interrupt dispatcher discarded the interrupt. The clock
interrupt was enabled because realistically most systems have
the clock enabled.
a
105
106
uNOTE # 014
Title:
Using Fortran Routines In A
VAXELN-Pascal Environment
Originator:
Herbert F. Maehner
This Micronote discusses the VAXELN interface to
following topics are covered are discussed:
1.
Date: 16-0ct-84
Page 1 of 4
VAX-11
Fortran.
The
The VAX-11 Procedure Calling Standard
2. Establishing a COMMON-datal area between a
and Fortran routines
VAXELN
program
VAXELN Procedure Ccllling Standard
VAXELN Pascal (EPascal) does conf:orm to the VAX Procedure Calling
Standard.
The standard allows for three methods of parameter passing :
value, reference, and descriptor, and requires that values be no longer
than a longword.
EPascal does not explicitly support descriptors as
parameters, and other languages may not treat conformant parameters as
EPascal does, but EPascal does nothing to violate the calling standard.
All routines can be described according to the conventions described in
the summary of run-time library E~ntry points [1]. There are principle
differences in passing parameters in Pascal and Fortran:
In pascal, you may pass parameters as
- values, e.g PROCEDURE pass_it (What: INTEGER);
i.e. the value of the parameter will be copied into the
procedure's stack frame with no implications for the source
variable. This is termed pass by value.
or as
- variable, e.g. PROCEDURE pass_it (VAR What: INTEGER);
i.e. the parameter will be rE~ferenced through its address.
An assignment to the parameter within the procedure will
directly~ffect the source variable.
This is termed pass by
reference.
107
uNOTE # 014
Page 2 of 4
In Fortran, you pass parameters as
- values, e.g. SUBROUTINE passit( What)
INTEGER*4 What
i.e. with no implications for the source.
It uses a common
data area to pass variables to the main program. The main
difference to Pascal is, that Fortran use~ pass by reference,
although it is actually a value.
Calling a Fortran routine with parameter passing from a
Pascal
environment, you have to declare the parameters as VAR parameters in
Pascal ( Figure 1 and Figure 2).
COMMON Data Area
As mentioned before, Fortran uses a COMMON data area to pass variables
from procedures to the main part of the program.
In VAX-11 Pascal the
[COMMON] attribute enables the linker to establish the common data
section. VAXELN- Pascal has no such attribute and wouldn't overlay data
sections for common areas. To overcome this restriction you must use
the [EXTERNAL] attribute in VAXELN-Pascal to declare the prospective
data as externally declared and use a MACRO-32 declaration to assign the
Fortran common part to the "global" data area (Figure 3).
References:
1. VMS RUN TIME LIBRARY USER'S GUIDE (Summary of Run Time
Library Entry Points)
2. VAXELN Encyclopedia, Procedures and Functions,
3. VMS MACRO Language Reference Manual
108
uNOTE # 014
Page 3 of 4
MODULE Fortran_TO_pascal;
{ This module is a simple example on, how to use Fortran
routines in VAXELN. }
CONST
Max - 50;
TYPE
Array_type - ARRAY[l .. Max] OF INTEGER;
VAR
AA: [EXTERNAL] Array_type;
PROCEDURE Valaccess (VAR What:INTEGER); EXTERNAL;
FUNCTION Double_it (VAR What: INTEGER):INTEGER; EXTERNAL;
PROGRAM FORTEST(INPUT,OUTPUT);
VAR
what,I,J,K:
INTEGER;
Twenty: [READONLY] INTEGER:-20;
BEGIN
WRITELN('Program start ');
FOR I:-1 TO Max DO AA[I] :== 0; { initialize array}
valaccess(Twenty);
call Fortran routine Valaccess }
FOR I:-21 TO Max DO
BEGIN
What :- I;
{ use Fortran Function to
AA [ I] : - Doubl e i. t (Wha t ) ;
double array value }
END;
{ formated output to screen
}
: - 1;
FOR I:-1 TO 10 DO
BEGIN
FOR J:-l TO 5 DO
BEGIN
WRITE(AA[K):4,'
');
K :- K+1
END;
WRITELN;
END;END;
END; { Bend of module Fortran_to_pascal }
K
Figure 1 : VAXELN main pl:ogram module
109
uNOTE i 014
Page 4 of 4
C
C Fortran SUBROUTINE TO SET THE INDEXED ARRAY VALUE
C THE MAXIMAL INDEX IS PASSED AS A PARAMETER
C
SUBROUTINE VALACCESS(WHAT)
IMPLICIT INTEGER*4 (A-Z)
C
COMMON
/XX$AA/ AA(SO)
C
C
10
DO 10 I-1,What
AA(I) - What-I
CONTINUE
C
RETURN
C
END
C
C
C
C INTEGER FUNCTION TO DOUBLE THE VALUE PASSED AS A PARAMETER
C
INTEGER FUNCTION DOUBLE IT(WHAT)
IMPLICIT INTEGER*4 (A-Z)
DOUBLE IT - WHAT + WHAT
RETURN
C
END
Figure 2: External Fortran routines used
; definition file for common array AA to be accessed by Fortran
subroutine VALACCESS
the P-section name XX$AA must be the same as the one used in the
Fortran routine
AA::
.TITLE COMDAT
.PSECT XX$AA,LONG,PIC,USR,OVR,REL,GBL,SHR,NOEXE,RD,WRT,NOVEC
• LONG 50
.END
Figure 3: MACRO definition module to define the common array
110
uNOTE # 015
Title: Q-Bus Hardware Bootstraps
Date: I6-0ct-84
Originator: Dave Smith
Page 1 of 4
The purpose of this micronote is to provide a comprehensive
Q-Bus hardware bootstraps and the devices they support.
list
of
The tables on the next two pages are organized as follows.
There is a
row for each of the currently supported bootable devices. There is a
column for each hardware bootstrap. The columns span both pages.
In
the heading for each bootstrap w'ill be found any ordering information
and/or references to notes which follow the tables.
When two order
numbers are given, both must be ordered since the boot code is divided
into high byte and low byte ROMs.
The bootstrap devices listed are:
BOOT
DEVICE
DESCRIPTION
BDV11
Bus Terminator, Bootstrap & Diagnostic ROM
used primarily with older LSI-1I configurations
MXV11-A2
Bootstrap ROM set designed for MXV11-A board
MXVI1-B2
Bootstrap ROM set designed for MXV11-BF & MRV1I-D
KDF11-BA
Bootstrap ROM on board PDP-11/23+ systems
KDF11-BE
Bootstrap ROM on board MicroPDP-11/23 systems
KDF11-BF
New Bootstrap ROM for PDP-I1/23+ and MicroPDP-II/23
KXT11-A2
Bootstrap ROM on board Falcon
KXTI1-A5
Bootstrap ROM on board Falcon-Plus
KDJll-S
Bootstrap ROM on board MicroPDP-11/73 CPU
uVAX I
Bootstrap ROM on board MicroVAX I CPU
111
uNOTE it 015
Page 2 of 4
BOOTSTRAP DEVICE SUPPORT
DEVICE
BDV11
MXV11-A2
Rev A
MXV11-B2
KDF11-BA
KDF11-BE
see Note 2
part no
23-339E2
23-340E2
part no.
23-1s7E4
23-1s8E4
see Note 1
RX01
X
X
X
X
X
RX02
X
X
X
X
X
TUs8
see Note 1
X
X
X
X
X
X
X
X
RL01/2
X
MRV11-C
X
X
MRV11-D
RKOs
X
X
RXsO
X
X
RDs1
X
X
RDs2
TSVOs
X
TK2s
RC2s
DEONA
DLV11-E
X
X
X
DLV11-F
X
X
X
DUVl1
X
X
X
DPV11
X
112
uNOTE # 015
page 3 of 4
BOOTSTRAP DEVICE SUPPORT
DEVICE
KDF11-BF
KXT11-A2
KXT11-AS
KDJ11-B
uVAX I
available available
on CPU
on CPU
board only board only
part no
23-183E4
23-184E4
RX01
X
X
X
X
Rx02
X
X
X
X
TUSS
X
X
X
X
RL01/2
X
X
X
MRV11-C
X
MRV11-D
RKOS
X
RXSO
X
X
X
X
RDS1
X
X
X
X
RDS2
X
X
X
TSVOS
X
TK2S
X
RC2S
X
DEQNA
X
X
See note 3 See note 3
X
DLV11-E
X
DLV11-F
X
DUV11
X
DPV11
113
X
uNOTE # 015
page 4 of 4
NOTES:
(1)
The information in the BDVII column refers to the Rev A
chips. There were also Rev 0 chips and an additional TU58
chip that can be added to the board:
Rev 0:
Part numbers 23-010E2, 23-011E2
Does NOT support:
DLVII-F, RX02 as bootable devices
TU58 ROM:
Part number 23-126F3
Inserted into socket XE40. Other ROM must be
Rev A. Allows use of the TU58 DEC tape II as
a bootable device.
(2)
The MXVII-B2 Bootstrap ROMs can be used with the MXV11-BF
multifunction module as well as the MRV11-D ROM module.
It will not work with the MXVI1-A module.
(3)
The RC25 adapter board must be configured at the the DEC
standard base address for the first MSCP controller
(772150). Other MSCP controllers may also reside but
may not be booted.
114
uNOTE # 016
Date: 16-0CT-84
KXT11-CA Software Development Tools
Title:
Page 1 of 8
Originator: Scott Tincher
The KXT11-CA is a single board computer (SSC) which executes the PDP-11
instruction set.
It may be utilized as a stand-alone SSC or interfaced
to the Q-bus as a peripheral processor or as an intelligent I/O
processor
(lOP). This article will describe the software tools
available to develop applications in either the stand-alone mode or the
lOP mode.
The KXT11-CA features:
o
T11 Microprocessor
instruction set
o
32K bytes of on-board static RAM
o
Two 28-pin sockets for up to 16K
additional RAM or 32K bytes of ROM
o
Three serial line units:
o
o
o
which
implements the PDP-11
bytes
of
One asynchronous DL compatible line (RS232)
One synch/asynch line with modem control
(RS449)
One synch/asynch with data and timing only
(RS449)
.
o
20 programmable parallel I/O lines
o
Three 16-bit programmable interval timers
o
2-channel DMA controller
o
Q-bus interface
o
Four diagnostic LEDs
The Q-bus interface of the KXTI1-CA allows up to 14 KXT11-CAs to be
added to a traditional Q-bus system. AS a slave device the KXT11-CA
offloads the arbiter CPU's processing activities by providing real-time
I/O data buffering, preprocessing, and high speed communications.
115
uNOTE i 016
Page 2. of 8
ThE! KXT11-CA is especially suited for applications with critical
interrupt latency requirements or applications that must service a high
frequency of interrupts.
The KXT11-CA may also be used as a
computational engine in applications where it is possible to partition
the application to run in parallel.
The
software
development environment for systems which utilize
is slightly different from that of the traditional Q-bus
The system programmer must develop application programs for
each KXT11-CA in the system in addition to the application code which
runs on the arbiter cpu.
Different software application tools are
available for the arbiter and "onboard" environments.
(When used in
stand-alone mode only the onboard environment need be considered.)
KX1~11-CAs
sysltem~
THE ARBITER ENVIRONMENT
The- arbiter
systems:
system
may
run
o
MicroPower/Pascal
o
RT-11
o
RSX-11M
o
RSX-11M-PLUS
under
any
of
the following operating
Each of these operating systems offers a device handler for the
two-port RAM of the KXT11-CA as well as a utility for loading
application
programs
across
the Q-bus into the KXT11-CA.
A
MicroPower/Pascal application may be coded in Pascal and MACRO-ll.
RT-ll and RSX-ll applications will be coded in MACRO-ll or a high level
language,
such as FORTRAN, which is capable of issuing programmed
requests {RT-ll) or QIO directives (RSX-ll).
USING A MICROPOWER/PASCAL ARBITER SYSTEM
If the arbiter system controlling the application is running in a
MicroPower/pascal environment there are KXTll-CA specific functions
available to aid in program development.
The first component is the KX
device handler.
This handler provides the arbiter-side interface to
the two-port RAM of the KXTll-CA.
The KX handler supports up to 14
KXTll-CAs on the Q-bus.
Two functions are supplied which simplify the
interface between the application program and the KX handler.
These
functions are:
o
KX write data:
Transfer data from an arbiter
butfer
to a KXTll-CA process and return a
completion-status value.
116
uNOTE # 016
page 3 of 8
o
KX read data:
Transfer
proc~ss
to an arbiter
completion-status value.
data from a KXTII-CA
buffer and return a
Micropower/pascal
also
provides
a
function which transfers a
MicroPower/Pascal
.MIM file from the arbiter to a KXT11-CA.
This
function,
KXT LOAD, reads a .MIM file from the arbiter and initiates a
DMA transfer using the DTC of the KXT11-CA to transfer the file to the
KXT11-CA's local memory.
This procedure may be called at any time by
the arbiter's application program - not necessarily at system startup
time.
MicroPower/pascal also supplies the symbolic debugger PASDBG.
supplies the following features:
o
A set of debugger commands and qualifiers that
allow for control of an executing program.
o
Access to the symbol table generated by the
Pascal
compiler,
providing symbolic (Pascal
language) referencing and variable access.
o
Access
to
structures.
o
Control of an application system not configured
for terminal I/O.
o
A method
error.
o
A method for loading a program on the application
system
while
PASDBG is running on a host
computer.
process
for
user
control
control
variables
PASDBG
and
after an execution
USING AN RT-11 OR RSX-11 ARBITER SYSTEM
If the arbiter system controlling the application is running in a RT-11
or RSX-11 environment there are tool kits available to aid in program
development.
They are the KXTII-C/RT-11 Peripheral Processor Tool Kit
(QJV51) and the KXT11-C/RSX-11 Peripheral Processor Tool Kit (QJV52).
There are two major components in each of these tool kits.
the KX device handler and the KUI utility program.
They are
The KX device handler manipulates the two-port RAM of the KXT11-CA so
that it appears to be a standard Q-bus I/O device. The KUI utility
program allows programs to be load~ed into a peripheral processor from
the arbiter, performs debugging operations, starts execution of KXT11-C
programs, and initiates KXT11-CA self tests.
117
UNOTE # 016
Page 4 of 8
The KX handler supplied with the RT-11 tool kit supports up to four
KXT11-CAs where each KXT11-CA appears as two logical units.
More than
four KXT11-CAs may be supported by editing, renaming, and rf~building
the KX handler.
The following
handler:
RT-11
programmed
requests
are
supported
o
.OPEN
associates a user-specified
number
with
a logical unit number
KXT11-CA.
o
.CLOSE
frees a previously opened channel for
use with another device or file.
o
. READ
processor
.READC)
o
.WRITE - transfers data from an arbiter buffer to
a
peripheral
processor.
(.WRITE,
.WRITEW,
. WRITEC) .
by
the KX
channel
of the
transfers
data from a peripheral
to an arbiter buffer.
(.READ, .READW,
The KX handler supplied with the RSX-11 tool kit supports up to 14
KXT11-CAs.
The KX handler assigns a unit number for each data channel
in each KXT11-CA two-port RAM. This handler supplies the following
RSX-11 I/O requests:
o
IO.RVB
Read a virtual block of data from the
device unit unit specified in the macro call.
o
IO.WVB
write a virtual
physical device unit.
o
IO.ATT - Attach a physical device to the control
of the task which issued the request.
o
IO.DET
Detach a physical device from the
control of the task which issued the request.
block
of data to a
Included in the RT-11 and RSX-11 tool kits is the KUI (KXT11-CA User
Interface) utility program.
The KUI program has several commands which
supply the following functions:
o
@ - Process commands from the specified indirect
command file.
o
CLOSE
command.
Close
the
file
118
specified
in the LOG
uNOTE # 016
Page 5 of 8
start
a
program
on
the
specified
o
EXECUTE
KXT11-CA.
o
EXIT
Exit the
operating system.
o
LOAD
Load a program from the arbiter's mass
storage to arbiter memory. Then perform a DMA
operation to transfer the image to the specified
peripheral prQcessor's memory. KUI under RT-11
supports the transfer of .SAV, .LDA, and .MIM
files.
KUI under RSX-11 supports the transfer of
.TSK and .MIM files.
o
LOG
Record all commands, status information,
and messages during this terminal session in the
specified file.
The CLOSE command terminates the
logging session.
o
ODT
Executes the octal debugging tool (ODT).
This tool allows the arbiter system to examine
and modify the contents of registers and memory
local to a KXT11-CA.
ODT may also be used to
start or halt a program.
o
REINIT
Reinitialize the specified peripheral
processor and reboot it's application.
o
RESUME
Causes a
continue execution.
o
SELFTEST
Causes one or more
diagnostic programs to execute.
o
SET
Specifies a peripheral processor as the
target for subsequent commands.
o
SHOW
Displays information about the state of
the peripheral processor.
o
SUSPEND
Used in an indirect command file to
halt execution of the file.
The RESUME command
can return control to the command file.
o
TRAP
performs a trap emulation so that a trap
handling routine can be tested.
KUI utility and return to the
SUSPENDed
119
command
of
file to
several
uNOTft~
# 016
Page 6 of 8
THE ONBOARD PROGRAMMING ENVIRONMENT
The KXTll-CA may be programmed in ei ther MACRO-l1 or MicroPOWEtr/Pascal.
MicroPower/Pascal provides the ability to program the onboard devices
in a high-level language, pascal.
In particular Micropower/pascal
provides the following device handlers:
o
DO:
This handler supports the TU58 tape drive.
It allows the TU58 to be interfaced to any of the
asynchronous I/O channels.
o
KK:
This handler manipulates the two-port RAM
from the KXTll-CA side in the KX/KK protocol.
This protocol allows the KK handler to pass
variable length messages to the arbiter system by
emulating a traditional Q-bus slave device. Two
functions
are
supplied
which simplify the
interface between the user's application code
and the KK handler. These functions are:
o
o
0
KK read data: transfer data from the arbiter
return
to
a
KXTll-CA
buffer
and
a
completion-status value.
0
KK write data: transfer data from a KXTll-CA
burfer
to
return a
the
arbiter
and
completion-status value.
QD:
This handler supports the two-channel DMA
transfer
controller (DTC).
The QD handler
enables the DTC to move data from source to
destination without the aid of the cpu. One
location, source or destination, must be local to
the KXTll-CA. The QD handler may be used for the
following functions:
0
Transfer data to and from Q-bus memory.
0
Transfer data to and from local memory.
0
Search for data.
0
Transfer to and from local I/O devices.
0
Access the Q-bus I/O page.
0
Assure access to a DMA Channel.
XL:
Supports asynchronous communications on the
three serial ports of the KXT11-CA. The first
port is a standard DL device. The second port is
channel A of the multiprotocol chip.
This
120
*
uNOTE
016
Page 7 of 8
channel is supported \{ith full modem controls.
The third port is channel B of the multiprotocol
chip.
This channel is supported as though it
were a standard OL devicE~.
All three channels
may be operated simultaneously.
o
XS:
Supports synchronous operation of channel A
of the multiprotocol chip. The handler provides
the
following
bit-()riented
communication
procedures:
o
Synchronization
(Flag detection)
o
Transparency
o
Invalid frame detection
o
Frame abortion detection
o
Frame
check
checking/calculation
(Bit stuffing)
sequence
(rcs)
The
handler can be used by user-written software as
component in performing bit-oriented protocols
such as X.25, HOLC, SOLC, and others.
a
o
YK: Supports the parallel I/O port and the three
counter-timers.
The
handler provides the
functions of read, write, pattern recognition,
OMA
read,
OMA
write,
counter-timer
set,
counter-timer
read, and counter-timer clear.
Typical parallel port operations are:
o
Transferring a series of bytes or words
through a port with handshake protocol.
o
Setting or reading the bits of external state
lines.
o
Generating a time base to software.
o
Generating a waveform for external output.
o
Counting pulses from an external input.
These Micropower/Pascal device handlers do not support all of the
functions of ehe onboard devices of the KXT11-CA. For this reason, or
because of preference, the application code for the KXT11-CA may also
be written in MACRO-11.
121
uNOTE # 016
:f?age 8 of 8
RELATED DOCUMENTS
For further
information pertaining to the KXT11-CA and it's software
dE!velopment tools please reference the following materials:
KXT11-CA Single-Board Computer User's Guide
EK-KXTCA-UG
KXT11-C Peripheral Processor Software User's Guide
AA-Y61SA-TK
122
uNOTE # 017
Title: LSI 11/23 ECO History
Date: 19-NOV-84
Originator: Bob Hessinger
Page 1 of 8
This micronote documents the ECO and etch revision history of the
KOF11-A (LSI 11/23) module. A quick verify has been included so that
the status of a module may be determined by a visual check.
For the M8186, the revision identifier is a two field alphanumeric
designation stamped on the reverse side of the module handle. The first
field indicates the etch revision.
The second field indicates the'
modifications to this etch.
Hardware revision notation :
A 0
Identifies etch level
Identifies modifications
The M8186 began as hardware revision "AO", as shown above.
That is,
etch revision "A" with no modifications or rework. As ECO's were
released calling for rework, the hardware revision level was updated to
"A1", then "A2", etc. Periodically new etch revisions were released,
incorporating previous modifications.
When these occurred the etch
revision field was updated from "A" to "C", and later from "e" to "0".
For the M8186, no etch revision "B" was released.
123
uNOTE # 017
Page 2 of S
The hardware revision history of the MS1S6 is shown below:
Release
AO
Rework
ECO #1
A1
Rework
ECO #2
A2
NOTE: All modules
shipped are at
rev A3 or greater
Rework
ECO #3
A3
NOTE : New etch
rev C created. No
rev B boards were
built
Relayout
ECO #4
I
I
I
co
A4
Rework
ECO #5
I
I
A6
I
A6
I
.A7
I
.AS
AS
Rework
ECO #6
Rework
ECO #7
Rework
ECO #S
Rework
ECO #9
Rework and
Relayout
ECO #10
AS
Rework
ECO #11
124
NOTE: Rev C layout
incorporates changes
for ECO #5
CO
I
I
C2
I
C2
I
C3
I
C4
C1
C4
NOTE: This was a
documentation change
only
-
DO
DO
NOTE: This was a
documentation
change only
uNOTE # 017
Page 3 of 8
,Jumper Functions on Etch Revision "A", "C" and "D" Modules
Jumper
Description
Function
Shipped
W1
Master Clock
In - Enabled, do not remove
In
W2,W3
DEC Reserved
Factory configured, do not
change (see note 1 )
W2-0ut
W3-In
W4
BEVENT
Out - Enabled
In
W5,W6
Power-up Mode
Mode
0 - PC-24,PS-26
1 - Console ODT
2 - Bootstrap
3 - Reserved
W5
Out
In
Out
In
W6
Out
Out
In
In
Mode 1
W5-In
W6-0ut
W7
Halt/Trap
Option
In - Trap to 10 on Halt
Out - Enter Console ODT
on Halt
Out
W8
Bootstrap
Address
In - Boot to 17773000
Out - Bootstrap address
specified by jumpers W9-W15
In
W9-W1S correspond to address
bits 9-15 respectively.
In - logic 1, Out - logic 0
In
Factory configured, do not
change
In
Factory configured, do not
change
In
Use r Bo,otstrap
Address
W9-W15
W16,W17
DEC Reserved
Etch A only
W18
W19
DEC Reserved
wake-up Circuit
Out - enabled
This jumper is a red wire
across diode D1
In
Out - enabled
This jumper is a red wire
across diode D1
In
Etch C and D only
w18
note 1
Wake-up Circuit
W3 on etch A modules consists of a jumper from E2 pin 5 to
E2 pin 15.
125
uNOTE # 017
Page 4 of 8
W18
01
(W19 - see text)
W17 W1
W16
i
W15
W14
W13
W12
W11
W10
W9
W8
W6
W7
w6
w5
I
I
W2 -
W4 -
I
KOF11-A REV A Jumper Layout
126
uNOTE # 017
Page 5 of 8
01(W18 - see text)
W1-
W15
W14
W13
W12
W11
W10
W9
W8
W6
W7
W4 -
W3
w6
W5
W16
W17
KOF11-A REV C Jumper Layout
127
W2
uNOTE # 017
Page 6 of 8
W18 ·1
Wl - -
W15
W14
W13
W12
Wll
W10
w9
w8
w6
W7
w6
W4 -
wS
W3
W2
W16
W17
KDF11-A REV D Jumper Layout
128
uNOTE # 017
page 7 of 8
The following table details the ECOI'S issued since the M8186 began to
ship to the field.
These ECO's are coded "M8186-MLOXX", where "XX" is
the ECO number shown below :
ECO #
04
Problem
Quick Verify
Too many wires and etch cuts, new etch
needed. Note that the jumper locations
Module handle will be
stamped "Cn" where n
change for etch Revision C.
Note also that etch A boards bring only
18 bits of addressing from the MMU to the
Q-BUS, while etch C boards bring all 22
bits of addressing from the MMU to the
Q-BUS.
indicates
modifications.
05
I/O page addressing scheme differs from
LSI-11/2 processor.
Check for etch cut
to E7 pins 16 and 18
(rev A boards only)
06
The internal wake-up circuit defeats the
power sequencing provided by standard
DEC power supplies.
Red jumper wire is
installed in parallel
with 01.
07
CTL/DAT hybrid (57-00000-00) and MMU IC
(21-15542-00) were not compatible with
KEFI1-AA floating point option. The FP
registers in the MMU were inaccessible,
and the CTL/DAT data path caused
intermittent errors in floating point
instructions.
CTL/DAT should be
57-00000-01 or higher
and,MMU should be
21-15542-01 or higher
for floating point
compatibility.
Coordinate with ECO
M8186-ML009
08
MMU (21-15542-01) was in.cluded as part of
the M8186 module. This documentation
change removes the MMU and makes it an
option which is ordered separately.
Some modules mayor
not have MMUs,
depending on the
options ordered.
129
uNOTE # 017
Page 8 lof 8
ECO :i
09
Problem
Quick Verify
1) No jumper table in print set (doc only)
2) Crystal oscillator may short to adjacent
components
3) Possibility of worst case MMU timing
violations. Chang~ configuration
of W2 and W3 to adjust timing. This
ECO must be installed :
A) When ECO m8186-ML007 is installed
B) When the KEF11 or FPF11 is installed
C) When one of the F-11 chips is replaced
D) Whenever unexplained system crashes
occur
1) Table added
2) Manufacturing
includes nylon
spacer
3) Module will have
W2 removed and W3
in. On rev A
modules w3 is a
wire from E2 pin
5 to E2' pin 15.
10
1) Heavily loaded systems lock up during
worst case timing between DMA and
interrupt arbitration. Symptoms
usually occur with DMA options not
manufactured by DEC.
2) Too many wires and etch cuts, new etch
needed. Note W18 now uses jumper posts.
1) Rev A and Rev C
modules will have
wires on E2 pins
2 and 4.
Rework
included in Rev D.
2) Module handle will
be stamped "Dn"
where n indicates
modifications.
11
Documentation updated.
Documentation only.
130
uNOTE
Title:
programming the KXT11-CA DMA controller
Originator: Scott Tincher
41:
018
Date: 28-DEC-84
Page 1 of 24
The KXT11-CA intelligent
I/O
processor
contains
several
user
pr'ogrammable devices. One of these devices is a DMA transfer controller
(DTC). This article will describe the features of the DTC and provide
some programming examples.
This article is intended for use by
individuals interested in programming the DTC using MACRO-11.
DIGITAL
supplies
a
DTC
device
driver
for
those
programmers
using
MicroPower/pascal. A working knowledge of MACRO-11 and of the KXT11-CA
is assumed.
FEATURES/CAPABILITIES
The DTC is addressable by the local T-11 microprocessor as an I/O
device.
It is capable of performing DMA transfers between any of the
following addresses:
1)
A 16-bit local address to a 16-bit local address
2)
A 16-bit local address to a 22-bit global address
3)
A 22-bit global address to a 16-bit local address
4)
A 22-bit global address to a 22-bit global address
5)
To/From channel A of the multiprotocol SLU
6)
To/From the PIO chip
Word, high byte, and low byte transfers are supported
word transfers are supported across the Q-bus.
locally.
Only
The operations of the DTC are controlled by several internal registers.
It was designed with the capabilty of loading these registers directly
from memory thereby minimizing the amount of processor intervention
necessary to perform a DMA transaction. The area of memory where the
parameters for the DTC are stored is referred to as the chain table.
The local microprocessor need only load the address of the chain table
into the DTC a-nd give a "start" command to initiate a DMA transfer.
131
uNOTE # 018
Page 2 of 24
transactions may be initiated locally by the T11 or by the arbiter
If the transfer is initiated by the arbiter the command words and
transfer parameters are placed in the command registers of the two-port
RA~~
file.
The local CPU will then initiate the DMA transaction using
the parameters supplied by the arbiter.
Dru~
cpu.
DTC consists of two identical channels.
DMA transfers may be
interleaved between these two channels or interleaved between the DTC
and the T-11. It is also possible to select a "hog mode" that allows
thE! DMA transfer to run to completion without interruption.
ThE~
The DTC supports three types of operations:
Transfer, Search, and
Transfer-and-Search. As the name implies, Transfer operations move data
from a source to a destination. Search operations read data from a
source and compare the data to the pattern register. A mask register
allows the user to declare "don't care" bits.
The Transfer-and-Search
operation combines the features of the Transfer and Search functions.
In this type of operation data is transferred between a source and
destination until the data transferred meets the match condition
specified in the Channel Mode register.
ThE~ DTC is capable
of performing multiple DMA transactions without
processor
intervention.
This can be accomplished in two ways:
base-to-current reloading or chaining. Base-to-current reloading allows
thE~
DTC to reload a portion of its registers before initiating a DMA
transfer. The reload operation occurs between internal registers so
there are no memory access related delays. This type of operation is
only practical in applications where data is continuously transferred
between the same addresses.
Chaining allows all of the applicable
registers of the DTC to be reloaded from a new chain table.
Therefore
this is a slower but more flexible alternative.
Upc)n completion of a DMA transfer the DTC may perform any combi.nation of
thE!
following
options:
Interrupt the local processor, perform
base-to-current reloading, or perform a chain reload.
It may also
choose to take no action.
DTC REGISTERS
Among the internal registers of the DTC are two chip-level registers,
thE! Master Mode register and the Command register. These registers
control both channels of the DTC. In addition, each channel of the DTC
is controlled by several channel-level registers.
For the sake of
completeness a brief description of these registers will be included
here.
For a detailed description refer to the KXTII-CA Single Board
computer User's Guide (EK-KXTCA-UG-OOl).
132
*
uNOTE
018
Page 3 of 24
CHIP-LEVEL REGISTERS
Master Mode Register
The Master Mode register controls the chip-level interfaces.
to:
-
Enable/disable
Select DTC/CPU
Enable/disable
Enable/disable
Enable/disable
It is used
the DTC
interleaving
asynch operation
countet/timer interrupt request
interrupt save vector
Command Register
The command register is used to issue commands to the DTC channels
as: Reset, Start Chain, etc.
such
CHANNEL-LEVEL REGISTERS
(Each of the following registers is present in each channel of the DTC)
Current Address Registers A and B (CARA, CARB)
CARA and CARB consist of two words, the segment/tag and the offset.
segment/tag is used to indicate:
The
- Address bits <21:16> of the source (or destination)
- If the source (or destination) resides on the a-bus
- Whether the source (or destination) address should be
incremented, decremented, or held constant
- Whether wait states should be included
The offset is used to indicate:
- Address bits <15:00>
Base Address Registers A and B (BA.RA, BARB)
BARA and BARB are identical to CA~A and CARB. They are used to reload
CARA and CARS if base-to-current reloading is selected after a DMA
operation has terminated.
13:3
uNOTE # 018
Page 4 of 24
Current Operation Count Register (COPC)
This 16-bit register is used to specify the number of words (or bytes)
to be transferred during a DMA operation. The maximum word count is
obtained by programming this register with a zero.
Base Operation Count Register (SOPC)
This register is identical to the COPC register. It is used to
the COPC register when base-to-current reloading is selected.
reload
Pattern and Mask Registers
The Pattern and Mask
registers
are
used
during
Search
and
Transfer-and-Search operations.
The contents of the Pattern register
are compared to the read data to generate a "match" condition. The Mask
register is used to generate "don't care" bits. Setting a bit to '1' in
thE! Mask register specifies that the bit always matches.
Status Register
ThE! status register is a 16-bit read-only register which returns the
status of the following fields: Interrupts status, DTC status, Hardware
interface status, and Completion status.
Interrupt vector and Interrupt Save Registers
The Interrupt vector register contains the vector that is output during
an interrupt acknowledge cycle. When an interrupt occurs the contents
of the Interrupt vector register and a part of the Status register are
stored in the Interrupt Save register. This allows a new vector to be
loaded during chaining so that a new DMA operation can be performed
before an interrupt acknowledge cycle occurs.
Channel Mode Register
ThE! Channel Mode register consists of two words, channel mode
channel mode low. Channel mode low is used to indicate:
high
and
- The operation type (transfer, search,
transfer-and-search,bytes,words)
- Whether CARA (or CARS) defines the source (or destination)
- Transfer type (single, hog mode, interleaved)
134
uNOTE # 018
Page 5 of 24
- Completion options (interrupt CPU, base-to-current reload,
chain reload)
Channel mode high is used to:
- indicate match conditions
- mask the hardware requests for DMA operations
- cause the channel to request the bus for a DMA operation
Chain Address Register
The chain address register consists of two words,
the segment/tag and
the offset.
This register is used to point to the reload word, the
first word in a chain table.
The sE~gment/tag is used to indicate:
whether the reload word resides in Q-bus memory
Whether the reload word resides in the Q-bus I/O page
- Address bits <21:16>
The offset is used to indicate:
- Address bits <15:00>
PROGRAMMING THE DTC
programming the DTC consists of three phases: Chip Initialization, Data
Transfer
(or Search), and Termination.
This section will provide a
general description of these phases.
CHIP INITIALIZATION
The Reset instruction is used to place the DTC in a known state.
A
reset will clear the CIE, IP, SIP and WFB bits and set the CA and NAC
bits in the Channel Status registers.
The Master Mode register will
also be cleared.
Before a DMA operation is initiated the local CPU
loads the Master Mode register and the Chain Address register of the
appropriate channel of the DTC. The DTC fetchs any other parameters
that are necessary from a table located in system memory referred to as
the chain t~ble.
This minimizes the amount of CPU intervention
necessary to perform a DMA operation. ·The relationship of the Chain
Address register to the chain table is shown in Figure 1.
135
uNOTE # 018
page 6 of 24
System
Memory
DTC
Channel 0/1
,....------>
Reload Word
DTC
Register
Data
Chain
Address
Reg.
-
- - - - - - - - New Chain Address
Reload Word
~>
DTC
Register
Data
- Figure 1 The first word in the chain table is the reload word. The reload word
is used to specify which registers are to be loaded for the pending DMA
operation. Bits <9:0> of the reload word correspond to the re9isters of
the DTC as shown in figure 2. Bits <15:10> are not used.
Reload Word
I
x
x
Ix Ix Ix Ix I
9
8
7
6
I
5
4
3
Current ARA
I
Current ARB
Current Op-Count - - - - - - - - - - - - - - '
Base ARA ---------------------------~.
Base ARB
Base Op-Count
Pattern and Mask
Interrupt Vector
Channel Mode -------------------------------------------~
Chain Address
Figure 2 -
136
uNOTE i 018
page 7 of 24
Therefore if a bit in the reload word is set then the corresponding
register is to be reloaded from the chain table. Since all of the
registers are not applicable to each DMA operation the chain table may
be of variable length. (i.e. The pattern and mask registers would not
be used in DMA operations that do not search the data.) It is NOT
correct to select a register in the reload word and subsequently load
that register with a dummy argument such as zero.
The following are
examples of the relationship between th~ reload word and the chain
table.
8
9
x
Ix IxIxIxIxI1 I1
7
1
Ii
Current ARA
6
4
5
3
1
2
0
I0 I0 I0 I0 I0 I1 I0
Segment/Tag
Current ARA
Current ARB
Offset
Segment/Tag
Current ARB
Offset
Current Op-Count
Channel Mode High
Channel Mode Low
9
7
8
x I x I xl x J x 1 x 1 1 l
0
1
Current ARA
Current ARA
6
1
5
I0 I0 I0
Segment/Tag
Offset
Current Op-Count
Pattern Register
Mask Register
Channel Mode High
Channel Mode Low
Chain Address Segment/Ta9
Chain Address Offset
137
4
3
2
1
0
1 1
1 0
1 1
I 1
uNOTE # 018
Page 8 of 24
The DTC has been properly initialized once the chain table(s) have been
created and the Master Mode register and Chain Address Register for the
selected channel have been loaded.
DATA TRANSFER
The DTC may perform a DMA operation once it has been properly
initialized.
A DMA operation may be initiated in one of four ways: by
so1:tware request, by hardware request, by loading a set software request
bit: in the Channel Mode register during chaining, or as the result of a
command from the arbiter.
Software Request: The local CPU may initiate a DMA operation by writing
a 'software request' command followed by a 'start chain' command to the
Command register. The 'software request' command sets the software
request bit in the channel's Mode register. If either the SIP (second
interrupt pending) bit or the NAC (no auto-reload or chain) bit is set
in the channel's status register the DMA operation will not begin. The
SIP bit will be cleared when the channel receives an interrupt
acknowledge.
The NAC bit will be cleared when the channel receives a
'start chain' command. The 'start chain' command initiates the DMA
operation after the registers of the selected channel are loaded from
the chain table. The 'start chain' command is ignored if the SIP bit or
the CA (Chain Abort) bit are set in the channel's status register. The
SIP bit was described above. The CA bit is cleared when the channel's
chain address register is reloaded.
Hardware Request: DMA operations may be started by applying a 'low' on
the channel's DREQ input. No details about this type of request will be
provided since they fall beyond the scope of this note.
Starting After Chaining: If the software request bit of the channel's
Mode register is loaded during chaining the channel will perform the DMA
operation at the end of chaining.
Arbiter Request: The arbiter may interrupt the local CPU to request a
DMA operation.
This is accomplished by passing parameters to load the
chain address register of channel 0 via the two-port RAM.
The arbiter
loads register 2 of the TPR with the offset of the chain address
register and register 3 of the TPR with the segment/tag of the chain
address register.
The DMA operation is then initiated by setting the
DMA Loa d bit (b i t 1) in the TPR comma nd reg i s t e r ( reg i s t e r 0 ) .,
Err 0 r
conditions will be returned in TPR register 1.
Information in tAe channel's Mode register determines what type of DMA
operation will be performed. The Channel Mode register consists of two
\iords, Channel Mode High and Channel Mode Low.
Bits <3:0> of the Channel Mode Low register select the type of DMA
operation. These bits determine whether the data should be transferred,
138
*
uNOTE
018
Page 9 of 24
searched, or transferred-and-searched. Bit 4 is the flip bit.
It is
used to determine which set of current address registers (CARA, CARB)
points to the source.
Bits <6:5> determine the transfer type. The types of DTC transfers are:
single transfer, demand dedicated with bus hold, demand dedicated with
bus release, and channel-to-channel demand interleave. Single transfer
is used with devices which transfer data at irregular intervals. A
single DMA transaction will occur e.ach time a 'software request' command
is issued or the DREQ input is asserted. Demand dedicated with bus hold
is a software hog mode. This mode allows the DMA transaction to run to
completion as long as there is a valid op count and the DREQ input is
asserted. If the DREQ input is not asserted no DMA operations will
occur but the channel will retain bus control. Demand dedicated with
bus release is similar to demand dedicated with bus hold in that a DMA
transaction is allowed to run to completion if DREQ is asserted. If
DREQ is not asserted the DTC must rlelease the bus thus allowing other
devices
to
obtain
the
bus.
The
operation
performed by a
channel-to-channel demand interleavle request depends on the state of bit
2 in the Master Mode register. If MM bit 2 is clear then control may be
passed between each channel of the lDTC without the need to release the
bus.
If MM bit 2 is set then the DTC must share the bus with the local
processor. The DTC will release the bus and then re-request it after
every DMA iteration.
Bits <1:0> of the Channel Mode High register are used to determine
type of match control in Search and Transfer-and-Search. operations.
DTC is capable of generating a termination condition based on
Match', 'Word Match', and 'Byte Match'.
the
The
'No
Bit <4> of the Channel Mode High re9ister causes the channel to request
the bus and perform transfers l~hen it is set by a 'Software Request
Command' or a chain reload.
TERMINATION OPTIONS
Bits <15:7> of the Channel Mode Low register control the termination
options. A DTC operbtion may be terminated in a number of ways. If the
Current Operation Count Register gOles to zero then a Terminal Count (TC)
termination is generated. External logic may assert the End Of Process
(EOP) input of the DTC to generate an EOP termination at any time.
In
addition, during a Search or Transfer-and-Search operation a match
condition may occur which generates a MC termination. Bits <15:7> allow
the DTC to perform a chain reload, a base-to-current reload, or to
interrupt the local processor if a Irc, EOP, or MC termination condition
is encountered.
If bits <15:7> are cleared then no special action is
initiated whe& a TC, EOP, or MC condition is encountered.
139
uNOTEI: 018
Page 10 of 24
EXl\MPLES
ThE~ following example programs were developed
on a PDP-11/23+ system
with 256KB of memory using the RT-11 (version 5.1) operating system with
These examples
the KXT11-C Peripheral Processor Software Toolkit.
assume the programmer is familiar with MACRO-II and the KXTII-C
Peripheral Processor Toolkit.
140
uNOTE # 018
Page 11 of 24
.TITLE EXAM1.MAC
; This program transfers data from local KXT11-C addresses to other
local KXT11-C addresses.
This program should be compiled and linked
on the development system and then downloaded into the KXT11-C using
the KXT11-C Software Toolkit.
Once the program has been compiled and
linked use the following KUI commands to execute it and verify its
; successfullness.
;
;
;
;
.KUI
KUI>SET n
KUI>LOAD EXAM1
KUI>ODT
Where n is the appropriate KXT11-C
Use KUI ODT to verify that the destination
addresses are cleared
.
ODT>AC
KUI>EXECUTE
KUI>ODT
Execute EXAM1
Use KUI ODT to verify that the transfer was
success:Eul
.
ODT>AC
KUI>EXIT
SET UP REGISTER ASSIGNMENTS
START:
174470
174454
174446
174442
MASTER MODE REGISTER
COMMAND REGISTER
CHAN 0 CHAIN ADDRESS SEG/TAG FIELD
CHAN 0 CHAIN ADDRESS OFFSET FIELD
MMREG
CMDREG
CASTFO
CAOFO
-
MOVB
#130,MMREG
LOAD MASTER MODE REG TO DISABLE DTC
CLRB
CMDREG
RESET THE DTC
MOV
MOV
#O,CASTFO
#RELOAD,CAOFO
LOAD THE CHAIN ADDRESS REG SEG/TAG
LOAD THE CHAIN ADDRESS REG OFFSET
MOVB
#131,MMREG
LOAD MASTER MODE REG TO ENABLE DTC
MOVB
#102,CMDREG
SET SOFTWARE REQUEST CHANNEL 0
MOVe-
#240,CMDREG
START CHAIN CHANNEL 0
==
==
STAY HERE WHILE THE USER VERIFIES
THAT THE PROGRAM WAS SUCCESSFUL
BR
; CHAIN LOAD REGION
RELOAD:
.WORD
001602
; RELOAD
141
~qORD
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