Pic32 Reference Manual

pic32_reference_manual

User Manual:

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1. Introduction

2. CPU

3. Memory Organization

4. Prefetch Cache

5. Flash Programming

6. Oscillators

7. Resets

8. Interrupts

9. Watchdog Timer

10. Power Saving Modes

12. Digital I/O Ports

13. Parallel Master Port

14. Timers

15. Input Capture

16. Output Compare

17. 10-bit A/D

18. 12-bit A/D

19. Comparator

20. Comparator Voltage Reference

21. UART

23. SPI

24. I2C

27. USB

29. RTCC

31. DMA

32. Conﬁguration

33. Programming and Debugging

34. CAN

35. Ethernet

37. CTMU

41. Prefetch with L1 Cache

42. Oscillator with Enhanced PLL

46. Serial Quad Interface (SQI)

47. External Bus Interface (EBI)

48. Memory Organization and Permissions

49. Crypto Engine and Random Number Generator

50. microAptiv Core

51. USB OTG

52. Flash Live Update

Introduction

Section 1. Introduction

HIGHLIGHTS

This section of the manual contains the following topics:

1.1 Introduction .................................................................................................................... 1-2

1.2 Family Reference Manual Sections ............................................................................... 1-2

1.3 Device Structure.............................................................................................................1-2

1.4 Development Support .................................................................................................... 1-3

1.5 Style and Symbol Conventions ...................................................................................... 1-4

1.6 Related Documentation ................................................................................................. 1-5

1.7 Revision History .............................................................................................................1-6

PIC32 Family Reference Manual

1.1 INTRODUCTION

Microchip’s PIC32 series of 32-bit microcontrollers are designed to fulfill a customer’s

requirements for enhanced features and performance for their MCU-based applications.

Common attributes among all devices in the PIC32 series are:

•Pin, peripheral and source code compatibility

•Common software and hardware development tools

1.2 FAMILY REFERENCE MANUAL SECTIONS

The collective PIC32 family reference manual sections describe the PIC32 family series of 32-bit

microcontrollers. All sections that comprise the PIC32 Family Reference Manual are available

from the Microchip web site: www.microchip.com. These individual sections explain the PIC32

family architecture and operation of the peripheral modules, but do not cover the specifics of

each device in a particular family. Users should refer to the respective product data sheet for

device-specific details, such as:

•Pinout and packaging details

•Memory map

• List of peripherals included on the device, including multiple instances of peripherals

• Device-specific electrical specifications and characteristics

1.3 DEVICE STRUCTURE

The PIC32 architecture has been broken down into the following functional blocks:

•MCU Core

•System Memory

•System Integration

•Peripherals

1.3.1 MCU Core

The PIC32 MCU core is discussed in Section 2. “CPU” (DS61113).

1.3.2 System Memory

The system memory provides on-chip nonvolatile Flash memory and volatile SRAM memory,

featuring user and protected kernel-segment-partitioning for real-time operating systems.

Refer to the specific device data sheet for the list of applicable family reference manual sections

for this topic.

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all PIC32 devices.

Please consult the note at the beginning of the “Device Overview” chapter in the

current device data sheet to check whether this document supports the device you

are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

Section 1. Introduction

Introduction

1.3.3 System Integration

System integration consists of a comprehensive set of modules and features that connect the

MCU core and peripheral modules into a single operational unit. System integration features also

provide these advantages:

• Decreased system cost, by bringing traditionally off-chip functions into the microcontroller

• Increased design flexibility, by adding a wider range of operating modes

•Increased system reliability, by enhancing the ability to recover from unexpected events

Refer to the specific device data sheet for the list of applicable family reference manual sections

for this topic.

1.3.4 Peripherals

The PIC32 devices have many peripherals that allow it to interface with the external world.

Refer to the specific device data sheet for the list of applicable family reference manual sections

for this topic.

1.4 DEVELOPMENT SUPPORT

Microchip offers a wide range of development tools that allow users to efficiently develop and

debug application code. Microchip’s development tools can be divided into four categories:

•Code generation

•Hardware/software debug

• Device programmer

•Product evaluation boards

As new tools are developed, the latest product briefs and user guides can be obtained from the

Microchip web site (www.microchip.com) or from your local Microchip Sales office.

Microchip offers other references and support to speed the development cycle. These include:

•Application notes

•Reference designs

•Local sales offices with field application support

•Corporate applications support line

•Getting started guides

•“How to” brochures

•MASTERs conferences

•Webinars

•Design centers

These can all be found on the Microchip web site (www.microchip.com). Also, the Microchip web

site lists other sites that may provide useful references.

PIC32 Family Reference Manual

1.5 STYLE AND SYMBOL CONVENTIONS

Throughout the individual family reference manual sections, certain style, format, and font

conventions are used to signal particular distinctions for the affected text. Tab l e 1- 1 lists these

conventions, specific symbols, and non-conventional word definitions and abbreviations.

1.5.1 Document Conventions

Tabl e 1-1 defines some of the symbols, terms and typographic conventions used in this manual.

Table 1-1: Document Conventions

Symbol or Term Description

Set To force a bit or register to a value of logic ‘1’.

Clear To force a bit or register to a value of logic ‘0’.

Reset 1) To force a register/bit to its default state.

2) A condition in which the device places itself after a device Reset

occurs. Some bits will be set to ‘0’ (such as interrupt enable bits), while

others will be set to ‘1’ (such as the I/O data direction bits).

0xnn or nnh Designates the number ‘nn’ in the hexadecimal number system. These

conventions are used in the code examples. For example, the

designation 0x13F or 13Fh may be used.

B‘bbbbbbbb’ Designates the number ‘bbbbbbbb’ in the binary number system. This

convention is used in the text, figures and tables. For example, the desig-

nation B‘10100000’ may be used.

R-M-W Read-Modify-Write. This occurs when a register or port is read, the value

is modified, and that value is then written back to the register or port. This

action can occur from a single instruction (such as bit set, BSET) or a

sequence of instructions.

: (colon) Used to specify a range or the concatenation of registers/bits/pins.

One example is TMR3:TMR2, which is the concatenation of two 16-bit

registers to form a 32-bit timer value.

Concatenation order (left-right) usually specifies a positional relationship

(MSb to LSb, higher to lower).

< > Specifies bit(s) locations in a particular register. One example is SRxMPT

(SPIxSTAT<5>), which specifies the abbreviation of bit and the register

name, and associated bits or bit positions.

MSb, LSb Indicates the Least/Most Significant bit in a field.

MSB, LSB Indicates the Least/Most Significant Byte in a field of bits.

mshw, lshw Most Significant half-word and lease significant half-word. A half-word is

16 bits wide.

msw, lsw Indicates the least/most significant word in a field of bits.

Courier New

Font

Used for code examples, binary numbers and for instruction mnemonics

that appear in the text.

Times New Roman

Font (Italics)

Used for equations.

Note A Note presents information that we want to re-emphasize, either to help

you avoid a common pitfall or to make you aware of operating differences

between some device family members. A Note can be in a box, or when

used in a table or figure, it is located at the bottom of the table or figure.

that the bit is either unimplemented (instead of a name an EM dash (—)

is present) or is not relevant to the particular peripheral module.

Section 1. Introduction

Introduction

1.5.2 Electrical Specifications

The individual family reference manual sections contain references to electrical specifications

and their parameter numbers. Tabl e 1-2 shows the parameter numbering convention for PIC32

devices. A parameter number represents a unique set of characteristics and conditions that is

consistent between every data sheet, although the actual parameter value may vary from device

to device.

To determine the parameter values for a specific device, users should refer to the “Electrical

Specifications” section of the specific device data sheet.

Table 1-2: Electrical Specification Parameter Numbering Convention

1.6 RELATED DOCUMENTATION

Microchip, as well as other sources, offers additional documentation to aid you as you develop

PIC32-based applications. The list below contains the most common documentation, but other

documents may also be available. Please check the Microchip web site (www.microchip.com) for

the latest published technical documentation.

1.6.1 Microchip Documentation

The following PIC32 documentation is available from Microchip. These documents provide

application-specific information that gives actual examples of using, programming, and designing

with PIC32 microcontrollers.

•PIC32 Family Reference Manual Sections

The individual family reference manual sections describe the PIC32 family architecture and

operation of the peripheral modules, but do not cover the specifics of each device in the

family.

•PIC32MX Product Data Sheets

These data sheets contain device-specific information, such as pinout and packaging

details, electrical specifications and memory maps.

• PIC32MX Programming Specification (DS61145)

The programming specification contains detailed descriptions of, and electrical and timing

specifications for, the programming process. Both In-Circuit Serial Programming™ (ICSP™)

and Enhanced ICSP are described in detail.

1.6.2 Third-Party Documentation

Microchip does not review third-party documentation for technical accuracy; however, these

references may be helpful to understand operation of the devices. Refer to the Microchip web

site for available information on third-party documentation.

Parameter Number Format Comment

Dxxx DC Specification

Axxx DC Specification for Analog Peripherals

xxx Timing (AC) Specification

PDxxx Device Programming DC Specification

Pxxx Device Programming Timing (AC) Specification

Legend: ‘xxx’ represents a parameter number.

PIC32 Family Reference Manual

1.7 REVISION HISTORY

Revision A (September 2007)

This is the initial version of this document.

Revision B (October 2007)

Updated document to remove Confidential status.

Revision C (April 2008)

Revised status to Preliminary; Revised Section 1.1.

Revision D (September 2011)

This revision includes the following updates:

• Removed the Preliminary status in the footer

•Added a note box with information on related family reference manual sections

•Updated the bulleted list in 1.1 “Introduction”

• Removed the feature list from 1.3.1 “MCU Core”

• Updated the family reference manual section information in these sections:

-1.3.2 “System Memory”

-1.3.3 “System Integration”

-1.3.4 “Peripherals”

•Updated the Document Conventions in Tabl e 1-1

• In addition, updates to formatting and minor text edits were incorporated throughout the

document

 2007-2011 Microchip Technology Inc. DS61127D-page 1-7

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-599-3

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS61127D-page 28  2011 Microchip Technology Inc.

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CPU for Devices

with M4K® Core

Section 2. CPU for Devices with M4K® Core

HIGHLIGHTS

This section of the manual contains the following topics:

2.1 Introduction................................................................................................................2-2

2.2 Architecture Overview ............................................................................................... 2-3

2.3 PIC32 CPU Details .................................................................................................... 2-6

2.4 Special Considerations When Writing to CP0 Registers ......................................... 2-11

2.5 Architecture Release 2 Details ................................................................................ 2-12

2.6 Split CPU bus .......................................................................................................... 2-12

2.7 Internal System Busses...........................................................................................2-13

2.8 Set/Clear/Invert........................................................................................................ 2-13

2.9 ALU Status Bits........................................................................................................ 2-14

2.10 Interrupt and Exception Mechanism ........................................................................ 2-14

2.11 Programming Model ................................................................................................ 2-14

2.12 Coprocessor 0 (CP0) Registers............................................................................... 2-21

2.13 MIPS16e® Execution ............................................................................................... 2-55

2.14 Memory Model......................................................................................................... 2-55

2.15 CPU Instructions, Grouped By Function.................................................................. 2-56

2.16 CPU Initialization ..................................................................................................... 2-59

2.17 Effects of a Reset .................................................................................................... 2-60

2.18 Related Application Notes ....................................................................................... 2-61

2.19 Revision History....................................................................................................... 2-62

PIC32 Family Reference Manual

2.1 INTRODUCTION

The PIC32 MCU is a complex system-on-chip (SoC) that is based on the M4K® Microprocessor

core from MIPS® Technologies. The M4K® is a state-of-the-art, 32-bit, low-power, RISC proces-

sor core with the enhanced MIPS32® Release 2 Instruction Set Architecture (ISA).

This chapter provides an overview of the CPU features and system architecture of the PIC32

family of microcontrollers that are based on the M4K® processor core.

2.1.1 Key Features

•Up to 1.5 DMIPS/MHz of performance

•Programmable prefetch cache memory to enhance execution from Flash memory (not

available on all devices; refer to the specific device data sheet to determine availability)

•16-bit Instruction mode (MIPS16e

®) for compact code

•Vectored interrupt controller with up to 96 interrupt sources

•Programmable User and Kernel modes of operation

•Atomic bit manipulations on peripheral registers (Single cycle)

• Multiply-Divide unit with a maximum issue rate of one 32 x 16 multiply per clock

•High-speed Microchip ICD port with hardware-based non-intrusive data monitoring and

application data streaming functions

•EJTAG debug port allows extensive third party debug, programming and test tools support

•Instruction controlled power management modes

• Five-stage pipelined instruction execution

•Internal code protection to help protect intellectual property

2.1.2 Related MIPS® Documentation

•MIPS32

® M4K® Processor Core Software User’s Manual – MD00249-2B-M4K-SUM

•MIPS

® Instruction Set – MD00086-2B-MIPS32BIS-AFP

•MIPS16e

® – MD00076-2B-MIPS1632-AFP

•MIPS32

® Privileged Resource Architecture – MD00090-2B-MIPS32PRA-AFP

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all PIC32 devices.

Please consult the note at the beginning of the “CPU” chapter in the current device

data sheet to check whether this document supports the device you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.2 ARCHITECTURE OVERVIEW

The PIC32 family of devices are complex systems-on-a-chip that contain many features.

Included in all processors of the PIC32 family is a high-performance RISC CPU, which can be

programmed in 32-bit and 16-bit modes, and even mixed modes. PIC32 devices contain a

high-performance interrupt controller, DMA controller, USB controller, in-circuit debugger,

high-performance switching matrix for high-speed data accesses to the peripherals, and on-chip

data RAM memory that holds data and programs. The unique prefetch cache and prefetch buffer

for the Flash memory, which hides the latency of the Flash, provides zero Wait state equivalent

performance.

Figure 2-1: PIC32 Block Diagram

JTAG/BSCAN Priority Interrupt

Controller LDO VREG

DMAC ICD

PIC32 CPU

IS DS

EJTAG INT

Bus Matrix

Prefetch Cache Data RAM

Peripheral

Flash Memory

Flash Controller

Clock Control/

Generation Reset Generation

PMP/PSP

PORTS

ADC

RTCC

Timers

Input Capture

PWM/Output

Compare

Dual Compare

SSP/SPI

I2C™

UART

128-bit

USB

Bridge

CAN(1)

Motor Control

PWM(1)

DAC(1)

CTMU(1)

Note 1: This peripheral is not available on all devices. Refer to the specific device data sheet for

availability.

ETH(1)

PIC32 Family Reference Manual

There are two internal busses in PIC32 devices for connection to all peripherals. The main

peripheral bus connects most of the peripheral units to the bus matrix through a peripheral

bridge. There is also a high-speed peripheral bridge that connects the interrupt controller, DMA

controller, in-circuit debugger, and USB peripherals.

The M4K® CPU core is the heart of some PIC32 MCUs. The CPU performs operations under

program control. Instructions are fetched by the CPU, decoded and executed synchronously.

Instructions exist in either Program Flash memory or Data RAM memory.

The PIC32 CPU is based on a load/store architecture and performs most operations on a set of

internal registers. Specific load and store instructions are used to move data between these

internal registers and the outside world.

Figure 2-2: M4K® Microprocessor Core Block Diagram

2.2.1 Busses

There are two separate busses on PIC32 devices. One bus is responsible for the fetching of

instructions to the CPU, and the other is the data path for load and store instructions. Both the

instruction, or I-side bus, and the data, or D-side bus, are connected to the bus matrix unit. The

bus matrix is a switch that allows multiple accesses to occur concurrently in a system. The bus

matrix allows simultaneous accesses between different bus masters that are not attempting

accesses to the same target. The bus matrix serializes accesses between different masters to

the same target through an arbitration algorithm.

Since the CPU has two different data paths to the bus matrix, the CPU is effectively two different

bus masters to the system. When running from Flash memory, load and store operations to

SRAM and the internal peripherals will occur in parallel to instruction fetches from Flash memory.

In addition to the CPU, and depending on the device variant, there are other bus masters in

PIC32 devices:

•DMA controller

•In-Circuit Debugger (ICD) unit

•USB controller

•CAN controller

•Ethernet controller

System

Co-processor

MDU

FMT

MMU

TAP

EJTAG

Power

Management

Off-Chip

Debug I/F

Execution

Core

(RF/ALU/Shift)

On-Chip

Memory

Trace

Off-Chip

Trace I/F

Memory

Interface Dual Memory

I/F

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.2.2 Introduction to the Programming Model

The PIC32 processor has the following features:

•5-stage pipeline

•32-bit Address and Data Paths

•DSP-like Multiply-add and multiply-subtract instructions (MADD, MADDU, MSUB, MSUBU)

•Targeted multiply instruction (MUL)

•Zero and One detect instructions (CLZ, CLO)

•Wait instruction (WAIT)

•Conditional move instructions (MOVZ, MOVN)

• Implements MIPS32® Enhanced Architecture (Release 2)

•Vectored interrupts

•Programmable exception vector base

•Atomic interrupt enable/disable

•General Purpose Register (GPR) shadow sets

•Bit field manipulation instructions

•MIPS16e

® Application Specific Extension improves code density

•Special PC-relative instructions for efficient loading of addresses and constants

•Data type conversion instructions (ZEB, SEB, ZEH, SEH)

•Compact jumps

•Stack frame set-up and tear-down SAVE and RESTORE macro instructions

•Memory Management Unit with simple Fixed Mapping Translation (FMT)

•Processor to/from Coprocessor register data transfers

•Direct memory to/from Coprocessor register data transfers

•Performance-optimized Multiply-Divide Unit (High-performance build-time option)

•Maximum issue rate of one 32 x 16 multiply per clock

•Maximum issue rate of one 32 x 32 multiply every other clock

• Early-in divide control – 11 to 34 clock latency

•Low-Power mode (triggered by WAIT instruction)

• Software breakpoints via the SDBBP instruction

2.2.3 Core Timer

The PIC32 architecture includes a core timer that is available to application programs. This

timer is implemented in the form of two co-processor registers: the Count register, and the

Compare register. The Count register is incremented every two system clock (SYSCLK) cycles.

The incrementing of Count can be optionally suspended during Debug mode. The Compare

Compare register matches the Count register. An interrupt is taken only if it is enabled in the

Interrupt Controller module.

For more information on the core timer, see 2.12 “Coprocessor 0 (CP0) Registers” and

Section 8. “Interrupts.” (DS61108) in the “PIC32 Family Reference Manual”.

PIC32 Family Reference Manual

2.3 PIC32 CPU DETAILS

2.3.1 Pipeline Stages

The pipeline consists of five stages:

•Instruction (I) Stage

•Execution (E) Stage

•Memory (M) Stage

•Align (A) Stage

•Writeback (W) Stage

2.3.1.1 I STAGE – INSTRUCTION FETCH

During I stage:

•An instruction is fetched from the instruction SRAM

•MIPS16e

® instructions are converted into instructions that are similar to MIPS32®

instructions

2.3.1.2 E STAGE – EXECUTION

During E stage:

•Operands are fetched from the register file

•Operands from the M and A stage are bypassed to this stage

• The Arithmetic Logic Unit (ALU) begins the arithmetic or logical operation for

• The ALU calculates the data virtual address for load and store instructions and the MMU

performs the fixed virtual-to-physical address translation

•The ALU determines whether the branch condition is true and calculates the virtual branch

target address for branch instructions

•Instruction logic selects an instruction address and the MMU performs the fixed

virtual-to-physical address translation

• All multiply divide operations begin in this stage

2.3.1.3 M STAGE – MEMORY FETCH

During M stage:

•The arithmetic or logic ALU operation completes

•The data SRAM access is performed for load and store instructions

•A 16 x 16 or 32 x 16 MUL operation completes in the array and stalls for one clock in the M

stage to complete the carry-propagate-add in the M stage

• A 32 x 32 MUL operation stalls for two clocks in the M stage to complete the second cycle

of the array and the carry-propagate-add in the M stage

• Multiply and divide calculations proceed in the MDU. If the calculation completes before the

IU moves the instruction past the M stage, then the MDU holds the result in a temporary

it will not be killed).

2.3.1.4 A STAGE – ALIGN

During A stage:

•A separate aligner aligns loaded data with its word boundary

•A MUL operation makes the result available for writeback. The actual register writeback is

performed in the W stage

•From this stage, load data or a result from the MDU are available in the E stage for

bypassing

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.3.1.5 W STAGE – WRITEBACK

During W stage:

For register-to-register or load instructions, the result is written back to the register file.

The M4K® Microprocessor core implements a “bypass” mechanism that allows the result of an

operation to be sent directly to the instruction that needs it without having to write the result to

the register, and then read it back.

Figure 2-3: Simplified PIC32 CPU Pipeline

The results of using instruction pipelining in the PIC32 core is a fast, single-cycle instruction

execution environment.

Figure 2-4: Single-Cycle Execution Throughput

I Stage E Stage M Stage

A to E Bypass

M to E Bypass

A Stage W Stage

Load Data, HI/LO Data

or CP0 Data

ALU

MStage

ALU

EStage

Bypass

Multiplexers

Rt Read

Rd Write

Reg File

Rt Address

Rs Read

Rs Address

Instruction

EIMAW

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

PIC32 Family Reference Manual

2.3.2 Execution Unit

The PIC32 Execution Unit is responsible for carrying out the processing of most of the instruc-

tions of the MIPS® instruction set. The Execution Unit provides single-cycle throughput for most

instructions by means of pipelined execution. Pipelined execution, sometimes referred to as

“pipelining”, is where complex operations are broken into smaller pieces called stages. Operation

stages are executed over multiple clock cycles.

The Execution Unit contains the following features:

•32-bit adder used for calculating the data address

•Address unit for calculating the next instruction address

•Logic for branch determination and branch target address calculation

•Load aligner

•Bypass multiplexers used to avoid stalls when executing instructions streams where data

producing instructions are followed closely by consumers of their results

•Leading Zero/One detect unit for implementing the CLZ and CLO instructions

•Arithmetic Logic Unit (ALU) for performing bit-wise logical operations

•Shifter and Store Aligner

2.3.3 MDU

The Multiply/Divide unit performs multiply and divide operations. The MDU consists of a 32 x 16

multiplier, result-accumulation registers (HI and LO), multiply and divide state machines, and all

multiplexers and control logic required to perform these functions. The high-performance, pipe-

lined MDU supports execution of a 16 x 16 or 32 x 16 multiply operation every clock cycle;

32 ×32 multiply operations can be issued every other clock cycle. Appropriate interlocks are

implemented to stall the issue of back-to-back 32 x 32 multiply operations. Divide operations are

implemented with a simple 1 bit per clock iterative algorithm and require 35 clock cycles in worst

case to complete. Early-in to the algorithm detects sign extension of the dividend, if it is actual

size is 24, 16, or 8 bit. the divider will skip 7, 15, or 23 of the 32 iterations. An attempt to issue a

subsequent MDU instruction while a divide is still active causes a pipeline stall until the divide

operation is completed.

The M4K® Microprocessor core implements an additional multiply instruction, MUL, which

specifies that lower 32-bits of the multiply result be placed in the register file instead of the HI/LO

LO register, and by supporting multiple destination registers, the throughput of multiply-intensive

operations is increased. Two instructions, multiply-add (MADD/MADDU) and multiply-subtract

(MSUB/MSUBU), are used to perform the multiply-add and multiply-subtract operations. The MADD

instruction multiplies two numbers and then adds the product to the current contents of the HI

and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the

product from the HI and LO registers. The MADD/MADDU and MSUB/MSUBU operations are

commonly used in Digital Signal Processor (DSP) algorithms.

2.3.4 Shadow Register Sets

The PIC32 processor implements a copy of the General Purpose Registers (GPR) for use by

high-priority interrupts. This extra bank of registers is known as a shadow register set. When a

high-priority interrupt occurs the processor automatically switches to the shadow register set

without software intervention. This reduces overhead in the interrupt handler and reduces

effective latency.

The shadow register set is controlled by registers located in the System Coprocessor (CP0) as

well as the interrupt controller hardware located outside of the CPU core.

For more information on shadow register sets, see Section 8. “Interrupts” (DS61108).

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.3.5 Pipeline Interlock Handling

Smooth pipeline flow is interrupted when an instruction in a pipeline stage can not advance due

to a data dependency or a similar external condition. Pipeline interruptions are handled entirely

in hardware. These dependencies, are referred to as “interlocks”. At each cycle, interlock

conditions are checked for all active instructions. An instruction that depends on the result of a

previous instruction is an example of an interlock condition.

In general, MIPS® processors support two types of hardware interlocks:

•Stalls – These interlocks are resolved by halting the entire pipeline. All instructions currently

executing in each pipeline stage are affected by a stall

•Slips – These interlocks allow one part of the pipeline to advance while another part of the

pipeline is held static

In the PIC32 processor core, all interlocks are handled as slips. These slips are minimized by

grabbing results from other pipeline stages by using a method called register bypassing, which

is described below.

As shown in Figure 2-5, the sub instruction has a source operand dependency on register r3 with

the previous add instruction. The sub instruction slips by two clocks waiting until the result of the

add is written back to register r3. This slipping does not occur on the PIC32 family of processors.

Figure 2-5: Pipeline Slip (If Bypassing Was Not Implemented)

Note: To i llu str at e t h e c onc ept o f a p ipe lin e s lip , the fol low ing e xamp le i s w h at wou ld

happen if the PIC32 core did not implement register bypassing.

EIMW

ESLIPIMAWE

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

ESLIP

Add r3, r2, r1

(r3  r2 + r1

Sub r4, r3, r7

(r4  r3 – r7

PIC32 Family Reference Manual

2.3.6 Register Bypassing

As mentioned previously, the PIC32 processor implements a mechanism called register bypass-

ing that helps reduce pipeline slips during execution. When an instruction is in the E stage of the

pipeline, the operands must be available for that instruction to continue. If an instruction has a

source operand that is computed from another instruction in the execution pipeline, register

bypassing allows a shortcut to get the source operands directly from the pipeline. An instruction

in the E stage can retrieve a source operand from another instruction that is executing in either

the M stage or the A stage of the pipeline. As seen in Figure 2-6, a sequence of three instructions

with interdependencies does not slip at all during execution. This example uses both A to E, and

M to E register bypassing. Figure 2-7 shows the operation of a load instruction utilizing A to E

bypassing. Since the result of load instructions are not available until the A pipeline stage, M to

E bypassing is not needed.

The performance benefit of register bypassing is that instruction throughput is increased to the

rate of one instruction per clock for ALU operations, even in the presence of register

dependencies.

Figure 2-6: IU Pipeline M to E Bypass

Figure 2-7: IU Pipeline A to E Data Bypass

EIMW

EI WA

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

Add1

r3 = r2 + r1

Sub2

r4 = r3 – r7

Add3

r5 = r3 + r4EI AM

M to E Bypass A to E Bypass

M to E Bypass

EIMW

EI WA

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

One

Cycle

Load Instruction

Consumer of Load Data Instruction EI AM

Data Bypass from A to E

One Clock

Load Delay

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.4 SPECIAL CONSIDERATIONS WHEN WRITING TO CP0 REGISTERS

In general, the PIC32 core ensures that instructions are executed following a fully sequential pro-

gram model. Each instruction in the program sees the results of the previous instruction. There

are some deviations to this model. These deviations are referred to as “hazards”.

In privileged software, there are two different types of hazards:

•Execution Hazards

• Instruction Hazards

2.4.0.1 EXECUTION HAZARDS

Execution hazards are those created by the execution of one instruction, and seen by the

execution of another instruction. Tab le 2- 1 lists execution hazards.

Table 2-1: Execution Hazards

2.4.0.2 INSTRUCTION HAZARDS

Instruction hazards are those created by the execution of one instruction, and seen by the

instruction fetch of another instruction. Ta ble 2 -2 lists the instruction hazard.

Table 2-2: Instruction Hazards

Created By Seen By Hazard On Spacing

(Instructions)

MTC0 Coprocessor instruction

execution depends on the new

value of the CU0 bit (Status<28>)

CU0 bit (Status<28>) 1

MTC0 ERET EPC, DEPC, ErrorEPC 1

MTC0 ERET Status 0

MTC0, EI, DI Interrupted Instruction IE bit (Status<0>) 1

MTC0 Interrupted Instruction IP1 and IP0 bits

(Cause<1> and <0>)

MTC0 RDPGPR, WRPGPR PSS<3:0> bits

(SRSCtl<9:6>)

MTC0 Instruction is not seeing a Core

Timer interrupt

Compare update that

clears Core Timer Interrupt

MTC0 Instruction affected by change Any other CP0 register 2

Created By Seen By Hazard On

MTC0 Instruction fetch seeing the new value (including a change to

ERL followed by an instruction fetch from the useg segment)

Status

PIC32 Family Reference Manual

2.5 ARCHITECTURE RELEASE 2 DETAILS

The PIC32 CPU utilizes Release 2 of the MIPS® 32-bit processor architecture, and implements

the following Release 2 features:

•Vectored interrupts using and external-to-core interrupt controller:

Provide the ability to vector interrupts directly to a handler for that interrupt.

•Programmable exception vector base:

Allows the base address of the exception vectors to be moved for exceptions that occur

when StatusBEV is ‘0’. This allows any system to place the exception vectors in memory that

is appropriate to the system environment.

•Atomic interrupt enable/disable:

Two instructions have been added to atomically enable or disable interrupts, and return the

previous value of the Status register.

• The ability to disable the Count register for highly power-sensitive applications

•GPR shadow registers:

Provides the addition of GPR shadow registers and the ability to bind these registers to a

vectored interrupt or exception.

•Field, Rotate and Shuffle instructions:

Add additional capability in processing bit fields in registers.

•Explicit hazard management:

Provides a set of instructions to explicitly manage hazards, in place of the cycle-based

SSNOP method of dealing with hazards.

2.6 SPLIT CPU BUS

The PIC32 CPU core has two distinct busses to help improve system performance over a sin-

gle-bus system. This improvement is achieved through parallelism. Load and store operations

occur at the same time as instruction fetches. The two busses are known as the I-side bus which

is used for feeding instructions into the CPU, and the D-side bus used for data transfers.

The CPU fetches instructions during the I pipeline stage. A fetch is issued to the I-side bus and

is handled by the bus matrix unit. Depending on the address, the BMX will do one of the following:

•Forward the fetch request to the Prefetch Cache unit

•Forward the fetch request to the DRM unit or

•Cause an exception

Instruction fetches always use the I-side bus independent of the addresses being fetched. The

BMX decides what action to perform for each fetch request based on the address and the values

in the BMX registers. See 3.5 “Bus Matrix” in Section 3. “Memory Organization” (DS61115).

The D-side bus processes all load and store operations executed by the CPU. When a load or

store instruction is executed the request is routed to the BMX by the D-side bus. This operation

occurs during the M pipeline stage and is routed to one of several targets devices:

•Data Ram

•Prefetch Cache/Flash Memory

• Fast Peripheral Bus (Interrupt controller, DMA, Debug unit, USB, Ethernet, GPIO Ports)

• General Peripheral Bus (UART, SPI, Flash Controller, EPMP/EPSP, RTCC Timers, Input

Capture, PWM/Output Compare, ADC, Dual Compare, I2C, Clock, and Reset)

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.7 INTERNAL SYSTEM BUSSES

The internal busses of the PIC32 processor connect the peripherals to the bus matrix unit. The

bus matrix routes bus accesses from different initiators to a set of targets utilizing several data

paths throughout the device to help eliminate performance bottlenecks.

Some of the paths that the bus matrix uses serve a dedicated purpose, while others are shared

between several targets.

The data RAM and Flash memory read paths are dedicated paths, allowing low-latency access

to the memory resources without being delayed by peripheral bus activity. The high-bandwidth

peripherals are placed on a high-speed bus. These include the Interrupt controller, debug unit,

DMA engine, the USB host/peripheral unit, and other high-bandwidth peripherals (i.e., CAN,

Ethernet engines).

Peripherals that do not require high-bandwidth are located on a separate peripheral bus to save

power.

2.8 SET/CLEAR/INVERT

To provide single-cycle bit operations on peripherals, the registers in the peripheral units can be

accessed in three different ways depending on peripheral addresses. Each register has four dif-

ferent addresses. Although the four different addresses appear as different registers, they are

really just four different methods to address the same physical register.

Figure 2-8: Four Addresses for a Single Physical Register

The base register address provides normal Read/Write access, while the other three provide

special write-only functions.

• Normal access

•Set bit atomic RMW access

•Clear bit atomic RMW access

•Invert bit atomic RMW access

Peripheral reads must occur from the base address of each peripheral register. Reading from a

Set/Clear/Invert address has an undefined meaning, and may be different for each peripheral.

Writing to the base address writes an entire value to the peripheral register. All bits are written.

For example, assume a register contains 0xAAAA5555 before a write of 0x000000FF. After the

write, the register will contain 0x000000FF (assuming that all bits are R/W bits).

Writing to the Set address for any peripheral register causes only the bits written as ‘1’s to be set

in the destination register. For example, assume that a register contains 0xAAAA5555 before a

write of 0x000000FF to the set register address. After the write to the Set register address, the

value of the peripheral register will contain 0xAAAA55FF.

Writing to the Clear address for any peripheral register causes only the bits written as ‘1’s to be

cleared to ‘0’s in the destination register. For example, assume that a register contains

0xAAAA5555 before a write of 0x000000FF to the Clear register address. After the write to the

Clear register address, the value of the peripheral register will contain 0xAAAA5500.

Writing to the Invert address for any peripheral register causes only the bits written as ‘1’s to be

inverted, or toggled, in the destination register. For example, assume that a register contains

0xAAAA5555 before a write of 0x000000FF to the invert register address. After the write to the

Invert register, the value of the peripheral register will contain 0xAAAA55AA.

Peripheral RegisterRegister Address

Clear Bits

Set Bits

Invert Bits

PIC32 Family Reference Manual

2.9 ALU STATUS BITS

Unlike most other PIC® microcontrollers, the PIC32 processor does not use Status register flags.

Condition flags are used on many processors to help perform decision making operations during

program execution. Flags are set based on the results of comparison operations or some arith-

metic operations. Conditional branch instructions on these machines then make decisions based

on the values of the single set of condition codes.

Instead, the PIC32 processor uses instructions that perform a comparison and stores a flag or

value into a General Purpose Register. A conditional branch is then executed with this general

purpose register used as an operand.

2.10 INTERRUPT AND EXCEPTION MECHANISM

The PIC32 family of processors implement an efficient and flexible interrupt and exception han-

dling mechanism. Interrupts and exceptions both behave similarly in that the current instruction

flow is changed temporarily to execute special procedures to handle an interrupt or exception.

The difference between the two is that interrupts are usually a result of normal operation, and

exceptions are a result of error conditions such as bus errors.

When an interrupt or exception occurs, the processor does the following:

1. The PC of the next instruction to execute after the handler returns is saved into a

co-processor register.

2. Cause register is updated to reflect the reason for exception or interrupt.

3. Status register EXL or ERL bit is set to cause Kernel mode execution.

4. Handler PC is calculated from Ebase and SPACING values.

5. Processor starts execution from new PC.

This is a simplified overview of the interrupt and exception mechanism. See Section 8.

“Interrupts” (DS61108) for more information regarding interrupt and exception handling.

2.11 PROGRAMMING MODEL

The PIC32 family of processors is designed to be used with a high-level language such as the C

programming language. It supports several data types and uses simple but flexible addressing

modes needed for a high-level language. There are 32 General Purpose Registers and two

special registers for multiplying and dividing.

There are three different formats for the machine language instructions on the PIC32 processor:

•Immediate or I-type CPU instructions

• Jump or J-type CPU instructions and

•Registered or R-type CPU instructions

Most operations are performed in registers. The register type CPU instructions have three

operands; two source operands and a destination operand.

Having three operands and a large register set allows assembly language programmers and

compilers to use the CPU resources efficiently. This creates faster and smaller programs by

allowing intermediate results to stay in registers rather than constantly moving data to and from

memory.

The immediate format instructions have an immediate operand, a source operand and a

destination operand. The jump instructions have a 26-bit relative instruction offset field that is

used to calculate the jump destination.

Note: Throughout this document, the terms “precise” and “imprecise” are used to describe

exceptions. A precise exception is one in which the EPC (CP0, Register 14, Select

0) can be used to identify the instruction that caused the exception. For imprecise

exceptions, the instruction that caused the exception cannot be identified. Most

exceptions are precise. Bus error exceptions may be imprecise.

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.11.1 CPU Instruction Formats

A CPU instruction is a single 32-bit aligned word. The CPU instruction formats are:

•Immediate (see Figure 2-9)

• Jump (see Figure 2-10)

• Register (see Figure 2-11)

Tabl e 2-3 describes the fields used in these instructions.

Table 2-3: CPU Instruction Format Fields

Figure 2-9: Immediate (I-Type) CPU Instruction Format

Figure 2-10: Jump (J-Type) CPU Instruction Format

Figure 2-11: Register (R-Type) CPU Instruction Format

2.11.2 CPU Registers

The PIC32 architecture defines the following CPU registers:

•Thirty-two 32-bit General Purpose Registers (GPRs)

• Two special purpose registers to hold the results of integer multiply, divide, and

multiply-accumulate operations (HI and LO)

•A special purpose program counter (PC), which is affected only indirectly by certain

instructions; it is not an architecturally visible register

Field Description

opcode 6-bit primary operation code.

rd 5-bit specifier for the destination register.

rs 5-bit specifier for the source register.

rt 5-bit specifier for the target (source/destination) register or used to specify

functions within the primary opcode REGIMM.

immediate 16-bit signed immediate used for logical operands, arithmetic signed operands,

load/store address byte offsets, and PC-relative branch signed instruction

displacement.

instr_index 26-bit index shifted left two bits to supply the low-order 28 bits of the jump

target address.

sa 5-bit shift amount.

function 6-bit function field used to specify functions within the primary opcode

SPECIAL.

31 26 25 21 20 16 15 0

opcode rs rt immediate

655 16

31 26 25 21 20 16 15 11 10 6 5 0

opcode instr_index

626

31 26 25 21 20 16 15 11 10 6 5 0

opcode rs rt rd sa function

655556

PIC32 Family Reference Manual

2.11.2.1 CPU GENERAL PURPOSE REGISTERS

Two of the CPU General Purpose Registers have assigned functions:

• r0 – This register is hard-wired to a value of ‘0’, and can be used as the target register for

any instruction the result of which will be discarded. r0 can also be used as a source when

a ‘0’ value is needed.

• r31 – This is the destination register used by JAL, BLTZAL, BLTZALL, BGEZAL, and

BGEZALL, without being explicitly specified in the instruction word; otherwise, r31 is used

as a normal register

The remaining registers are available for general purpose use.

2.11.2.2 REGISTER CONVENTIONS

Although most of the registers in the PIC32 architecture are designated as General Purpose

Registers, as shown in Ta ble 2 -4, there are some recommended uses of the registers for correct

software operation with high-level languages such as the Microchip C compiler.

Table 2-4: Register Conventions

2.11.2.3 CPU SPECIAL PURPOSE REGISTERS

The CPU contains three special purpose registers:

•PC – Program Counter register

•HI – Multiply and Divide register higher result

•LO – Multiply and Divide register lower result:

-During a multiply operation, the HI and LO registers store the product of integer

multiply

-During a multiply-add or multiply-subtract operation, the HI and LO registers store the

result of the integer multiply-add or multiply-subtract

-During a division, the HI and LO registers store the quotient (in LO) and remainder (in

HI) of integer divide

-During a multiply-accumulate, the HI and LO registers store the accumulated result of

the operation

CPU

Symbolic

r0 zero Always ‘0’(1)

r1 at Assembler Temporary

r2 - r3 v0-v1 Function Return Values

r4 - r7 a0-a3 Function Arguments

r8 - r15 t0-t7 Temporary – Caller does not need to preserve contents

r16 - r23 s0-s7 Saved Temporary – Caller must preserve contents

r24 - r25 t8-t9 Temporary – Caller does not need to preserve contents

r26 - r27 k0-k1 Kernel temporary – Used for interrupt and exception handling

r28 gp Global Pointer – Used for fast-access common data

r29 sp Stack Pointer – Software stack

r30 s8 or fp Saved Temporary – Caller must preserve contents OR

Frame Pointer – Pointer to procedure frame on stack

r31 ra Return Address(1)

Note 1: Hardware enforced, not just convention.

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

Figure 2-12 shows the layout of the CPU registers.

Figure 2-12: CPU Registers

31 0 31 0

r0 (zero) HI

r1 (at) LO

r2 (v0)

r3 (v1)

r4 (a0)

r5 (a1)

r6 (a2)

r7 (a3)

r8 (t0)

r9 (t1)

r10 (t2)

r11 (t3)

r12 (t4)

r13 (t5)

r14 (t6)

r15 (t7)

r16 (s0)

r17 (s1)

r18 (s2)

r19 (s3)

r20 (s4)

r21 (s5)

r22 (s6)

r23 (s7)

r24 (t8)

r25 (t9)

r26 (k0)

r27 (k1)

r28 (gp)

r29 (sp)

r30 (s8 or fp) 31 0

r31 (ra) PC

General Purpose Registers Special Purpose Registers

PIC32 Family Reference Manual

Table 2-5: MIPS16e® Register Usage

Table 2-6: MIPS16e® Special Registers

2.11.3 How to Implement Stack/MIPS® Calling Conventions

The PIC32 CPU does not have hardware stacks. Instead, the processor relies on software to pro-

vide this functionality. Since the hardware does not perform stack operations itself, a convention

must exist for all software within a system to use the same mechanism. For example, a stack can

grow either toward lower address, or grow toward higher addresses. If one piece of software

assumes that the stack grows toward lower address, and calls a routine that assumes that the

stack grows toward higher address, the stack would become corrupted.

Using a system-wide calling convention prevents this problem from occurring. The Microchip C

compiler assumes the stack grows toward lower addresses.

2.11.4 Processor Modes

There are two operational modes and one special mode of execution in the PIC32 family CPUs;

User mode, Kernel mode, and Debug mode. The processor starts execution in Kernel mode, and

if desired, can stay in Kernel mode for normal operation. User mode is an optional mode that

allows a system designer to partition code between privileged and unprivileged software. Debug

mode is normally only used by a debugger or monitor.

One of the main differences between the modes of operation is the memory addresses that soft-

ware is allowed to access. Peripherals are not accessible in User mode. Figure 2-13 shows the

different memory maps for each mode. For more information on the processor’s memory map,

see Section 3. “Memory Organization” (DS61115).

MIPS16e®

Encoding

32-bit MIPS®

Encoding

Symbolic

Name Description

0 16 s0 General Purpose Register

1 17 s1 General Purpose Register

22v0General Purpose Register

33v1General Purpose Register

44a0General Purpose Register

55a1General Purpose Register

66a2General Purpose Register

77a3General Purpose Register

N/A 24 t8 MIPS16e® Condition Code register; implic-

itly referenced by the BTEQZ, BTNEZ, CMP,

CMPI, SLT, SLTU, SLTI, and SLTIU

instructions

N/A 29 sp Stack Pointer register

N/A 31 ra Return Address register

Symbolic

Name Purpose

PC Program counter. The PC-relative instructions can access this register as an

operand.

HI Contains high-order word of multiply or divide result.

LO Contains low-order word of multiply or divide result.

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

Figure 2-13: CPU Modes

useg kuseg kuseg

kseg0

kseg1

kseg2

kseg3

kseg2

kseg1

kseg0

kseg3

dseg

User Mode Kernel Mode Debug ModeVirtual Address

0x7FFF_FFFF

0x8000_0000

0x9FFF_FFFF

0xBFFF_FFFF

0xDFFF_FFFF

0xFF1F_FFFF

0xFF3F_FFFF

0xFFFF_FFFF

0xA000_0000

0xC000_0000

0xE000_0000

0xFF20_0000

0xFF40_0000

0x0000_0000

PIC32 Family Reference Manual

2.11.4.1 KERNEL MODE

In order to access many of the hardware resources, the processor must be operating in Kernel

mode. Kernel mode gives software access to the entire address space of the processor as well

as access to privileged instructions.

The processor operates in Kernel mode when the DM bit in the Debug register is ‘0’ and the

Status register contains one, or more, of the following values:

•UM = 0

•ERL = 1

•EXL = 1

When a non-debug exception is detected, EXL or ERL will be set and the processor will enter

Kernel mode. At the end of the exception handler routine, an Exception Return (ERET) instruction

is generally executed. The ERET instruction jumps to the Exception PC (EPC or ErrorPC

depending on the exception), clears ERL, and clears EXL if ERL= 0.

If UM = 1 the processor will return to User mode after returning from the exception when ERL

and EXL are cleared back to ‘0’.

2.11.4.2 USER MODE

When executing in User mode, software is restricted to use a subset of the processor’s

resources. In many cases it is desirable to keep application-level code running in User mode

where if an error occurs it can be contained and not be allowed to affect the Kernel mode code.

Applications can access Kernel mode functions through controlled interfaces such as the

SYSCALL mechanism.

As seen in Figure 2-13, User mode software has access to the USEG memory area.

To operate in User mode, the Status register must contain each the following bit values:

•UM = 1

•EXL = 0

•ERL = 0

2.11.4.3 DEBUG MODE

Debug mode is a special mode of the processor normally only used by debuggers and system

monitors. Debug mode is entered through a debug exception and has access to all the Kernel

mode resources as well as special hardware resources used to debug applications.

The processor is in Debug mode when the DM bit in the Debug register is ‘1’.

Debug mode is normally exited by executing a DERET instruction from the debug handler.

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.12 COPROCESSOR 0 (CP0) REGISTERS

The PIC32 uses a special register interface to communicate status and control information

between system software and the CPU. This interface is called Coprocessor 0, or CP0. The

features of the CPU that are visible through Coprocessor 0 are:

•Core timer

•Interrupt and exception control

•Virtual memory configuration

•Shadow register set control

•Processor identification

•Debugger control

• Performance counters

System software accesses the registers in CP0 using coprocessor instructions such as MFC0

and MTC0. Tabl e 2-7 describes the CP0 registers found on PIC32 devices.

Table 2-7: CP0 Registers

Number Register Name Function

0-6 Reserved Reserved in the M4K® Microprocessor core.

7HWREna Enables access via the RDHWR instruction to selected

hardware registers in Non-privileged mode.

8 BadVAddr Reports the address for the most recent address-related

exception.

9Count Processor cycle count.

10 Reserved Reserved in the M4K® Microprocessor core.

11 Compare Core timer interrupt control.

12 Status Processor status and control.

IntCtl Interrupt control of vector spacing.

SRSCtl Shadow register set control.

SRSMap Shadow register mapping control.

13 Cause Describes the cause of the last exception.

14 EPC Program counter at last exception.

15 PRID Processor identification and revision

Ebase Exception base address of exception vectors.

16 Config Configuration register.

Config1 Configuration register 1.

Config2 Configuration register 2.

Config3 Configuration register 3.

17-22 Reserved Reserved in the M4K® Microprocessor core.

23 Debug Debug control/exception status.

TraceControl EJTAG trace control.

TraceControl2 EJTAG trace control 2.

UserTraceData User format type trace record trigger.

TraceBPC Control tracing using an EJTAG Hardware breakpoint.

Debug2 Debug control/exception status 1.

24 DEPC Program counter at last debug exception.

25-29 Reserved Reserved in the M4K® Microprocessor core.

30 ErrorEPC Program counter at last error.

31 DeSAVE Debug handler scratchpad register.

PIC32 Family Reference Manual

2.12.1 HWREna Register (CP0 Register 7, Select 0)

The HWREna register contains a bit mask that determines which hardware registers are

accessible via the RDHWR instruction.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — —MASK<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-4 Unimplemented: Read as ‘0’

bit 3-0 MASK<3:0>: Bit Mask bits

1 = Access is enabled to corresponding hardware register

0 = Access is disabled

Each of these bits enables access by the RDHWR instruction to a particular hardware register (which may not

be an actual register). See the RDHWR instruction for a list of valid hardware registers.

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.12.2 BadVAddr Register (CP0 Register 8, Select 0)

BadVAddr is a read-only register that captures the most recent virtual address that caused an

address error exception. Address errors are caused by executing load, store, or fetch operations

from unaligned addresses, and also by trying to access Kernel mode addresses from User mode.

BadVAddr does not capture address information for bus errors, because they are not addressing

errors.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R-x R-x R-x R-x R-x R-x R-x R-x

BadVAddr<31:24>

23:16 R-x R-x R-x R-x R-x R-x R-x R-x

BadVAddr<23:16>

15:8 R-x R-x R-x R-x R-x R-x R-x R-x

BadVAddr<15:8>

7:0 R-x R-x R-x R-x R-x R-x R-x R-x

BadVAddr<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BadVAddr<31:0>: Bad Virtual Address bits

Captures the virtual address that caused the most recent address error exception.

PIC32 Family Reference Manual

2.12.3 Count Register (CP0 Register 9, Select 0)

The Count register acts as a timer, incrementing at a constant rate, whether or not an instruction

is executed, retired, or any forward progress is made through the pipeline. The counter

increments every other clock, if the DC bit in the Cause register is ‘0’.

Count can be written for functional or diagnostic purposes, including at Reset or to synchronize

processors.

By writing the COUNTDM bit in the Debug register, it is possible to control whether Count

continues to increment while the processor is in Debug mode.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

COUNT<31:24>

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

COUNT<23:16>

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

COUNT<15:8>

7:0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

COUNT<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 COUNT<31:0>: Interval Counter bits

This value is incremented every other clock cycle.

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.12.4 Compare Register (CP0 Register 11, Select 0)

The Compare register acts in conjunction with the Count register to implement a timer and timer

interrupt function. Compare maintains a stable value and does not change on its own.

When the value of Count equals the value of Compare, the CPU asserts an interrupt signal to the

system interrupt controller. This signal will remain asserted until Compare is written.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

COMPARE<31:24>

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

COMPARE<23:16>

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

COMPARE<15:8>

7:0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

COMPARE<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 COMPARE<31:0>: Interval Count Compare Value bits

PIC32 Family Reference Manual

2.12.5 Status Register (CP0 Register 12, Select 0)

The read/write Status register contains the operating mode, interrupt enabling, and the diagnostic

states of the processor. The bits of this register combine to create operating modes for the

processor.

2.12.5.1 INTERRUPT ENABLE

Interrupts are enabled when all of the following conditions are true:

•IE = 1

•EXL = 0

•ERL = 0

•DM = 0

If these conditions are met, the settings of the IPL bits enable the interrupts.

2.12.5.2 OPERATING MODES

If the DM bit in the Debug register is ‘1’, the processor is in Debug mode; otherwise, the

processor is in either Kernel mode or User mode.

The CPU Status register bit settings shown in table determine User or Kernel mode:

Table 2-8: CPU Status Register Bits That Determine Processor Mode

Mode Bit/Setting

User (requires all of the following bits and values) UM = 1EXL = 0ERL = 0

Kernel (requires one or more of the following bit values) UM = 0EXL = 1ERL = 1

Note: The Status register CU0 bit (Status<28>) control coprocessor accessibility. If any

coprocessor is unusable, an instruction that accesses it generates an exception.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 R/W-x R/W-0(1) U-0 R/W-x U-0

— — —CU0RP —RE—

23:16 U-0 R/W-1 U-0 R/W-1 R/W-0 U-0 U-0 U-0

—BEV—SRNMI— — —

15:8 U-0 U-0 U-0 R/W-x R/W-x R/W-x U-0 U-0

— — — IPL<2:0> — —

7:0 U-0 U-0 U-0 R/W-x U-0 R/W-x R/W-x R/W-x

— — —UM—ERLEXLIE

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as ‘0’

bit 28 CU0: Coprocessor 0 Usable bit

Controls access to Coprocessor 0

1 = Access allowed

0 = Access not allowed

Coprocessor 0 is always usable when the processor is running in Kernel mode, independent of the state of

the CU0 bit.

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

bit 27 RP: Reduced Power bit

1 = Enables Reduced Power mode

0 = Disables Reduced Power mode

bit 26 Unimplemented: Read as ‘0’

bit 25 RE: Reverse-endian Memory Reference Enable bit

Used to enable reverse-endian memory references while the processor is running in User mode

1 = User mode uses reversed endianness

0 = User mode uses configured endianness

Debug, Kernel, or Supervisor mode references are not affected by the state of this bit.

bit 24-23 Unimplemented: Read as ‘0’

bit 22 BEV: Bootstrap Exception Vector Control bit

Controls the location of exception vectors.

1 = Bootstrap

0 = Normal

bit 21 Unimplemented: Read as ‘0’

bit 20 SR: Soft Reset bit

Indicates that the entry through the Reset exception vector was due to a Soft Reset.

1 = Soft Reset; this bit is always set for any type of reset on the PIC32 core

0 = Not used on PIC32

Software can only write a ‘0’ to this bit to clear it and cannot force a ‘0’ to ‘1’ transition.

bit 19 NMI: Non-Maskable Interrupt bit

Indicates that the entry through the reset exception vector was due to a NMI.

1 = NMI

0 = Not NMI (Soft Reset or Reset)

Software can only write a ‘0’ to this bit to clear it and cannot force a ‘0’ to ‘1’ transition.

bit 18-13 Unimplemented: Read as ‘0’

bit 12-10 IPL<2:0>: Interrupt Priority Level bits

This bit is the encoded (0-7) value of the current IPL. An interrupt will be signaled only if the requested IPL

is higher than this value.

bit 9-5 Unimplemented: Read as ‘0’

bit 4 UM: User Mode bit

This bit denotes the base operating mode of the processor. On the encoding of this bit is:

1 = Base mode is User mode

0 = Base mode in Kernel mode

The processor can also be in Kernel mode if ERL or EXL is set, regardless of the state of the UM bit.

bit 3 Unimplemented: Read as ‘0’

bit 2 ERL: Error Level bit

Set by the processor when a Reset, Soft Reset, NMI or Cache Error exception are taken.

1 = Error level

0 = Normal level

When ERL is set:

•Processor is running in Kernel mode

•Interrupts are disabled

•ERET instruction will use the return address held in the ErrorEPC register instead of the EPC register

•Lower 2

29 bytes of kuseg are treated as an unmapped and uncached region. This allows main

memory to be accessed in the presence of cache errors. The operation of the processor is undefined if

the ERL bit is set while the processor is executing instructions from kuseg.

PIC32 Family Reference Manual

bit 1 EXL: Exception Level bit

Set by the processor when any exception other than Reset, Soft Reset, or NMI exceptions is taken.

1 = Exception level

0 = Normal level

When EXL is set:

•Processor is running in Kernel mode

•Interrupts are disabled

EPC, BD, and SRSCtl will not be updated if another exception is taken.

bit 0 IE: Interrupt Enable bit

Acts as the master enable for software and hardware interrupts:

1 = Interrupts are enabled

0 = Interrupts are disabled

This bit may be modified separately via the DI and EI instructions

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.12.6 IntCtl: Interrupt Control Register (CP0 Register 12, Select 1)

The IntCtl register controls the vector spacing of the PIC32 architecture.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U=0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — —VS<4:4>

7:0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0

VS<2:0> — — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-10 Unimplemented: Read as ‘0’

bit 9-5 VS<4:0>: Vector Spacing bits

These bits specify the spacing between each interrupt vector.

All other values are reserved. The operation of the processor is undefined if a reserved value is written to

these bits.

bit 4-0 Unimplemented: Read as ‘0’

Encoding Spacing Between Vectors

(hex)

Spacing Between Vectors

(decimal)

0x00 0x000 0x 0

0x01 0x020 32

0x02 0x040 64

0x04 0x080 128

0x08 0x100 256

0x10 0x200 512

PIC32 Family Reference Manual

2.12.7 SRSCtl Register (CP0 Register 12, Select 2)

The SRSCtl register controls the operation of GPR shadow sets in the processor.

Table 2-9: Sources for New CSS on an Exception or Interrupt

Exception Type Bit Source Condition Comment

Exception ESS All —

Non-Vectored Interrupt ESS IV bit = 0 (Cause<23>) Treat as exception

Vectored EIC Interrupt EICSS IV bit = 1 (Cause<23>) and,

VEIC bit = 1 (Config3<6>)

Source is external interrupt controller.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 R-0 R-0 R-0 R-1 U-0 U-0

——HSS<3:0>— —

23:16 U-0 U-0 R-x R-x R-x R-x U-0 U-0

— — EICSS<3:0> — —

15:8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0

ESS<3:0> ——PSS<3:2>

7:0 R/W-0 R/W-0 U-0 U-0 R-0 R-0 R-0 R-0

PSS<1:0> ——CSS<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as ‘0’

bit 29-26 HSS<3:0>: High Shadow Set bits

This bit contains the highest shadow set number that is implemented by this processor. A value of ‘0000’ in

these bits indicates that only the normal GPRs are implemented.

1111 = Reserved

•

0100 = Reserved

0011 = Four shadow sets are present

0010 = Reserved

0001 = Two shadow sets are present

0000 = One shadow set (normal GPR set) is present

The value in this bit also represents the highest value that can be written to the ESS<3:0>, EICSS<3:0>,

PSS<3:0>, and CSS<3:0> bits of this register, or to any of the bits of the SRSMap register. The operation

of the processor is undefined if a value larger than the one in this bit is written to any of these other bits.

bit 25-22 Unimplemented: Read as ‘0’

bit 21-18 EICSS<3:0>: External Interrupt Controller Shadow Set bits

EIC Interrupt mode shadow set. This bit is loaded from the external interrupt controller for each interrupt

request and is used in place of the SRSMap register to select the current shadow set for the interrupt.

bit 17-16 Unimplemented: Read as ‘0’

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

bit 15-12 ESS<3:0>: Exception Shadow Set bits

This bit specifies the shadow set to use on entry to Kernel mode caused by any exception other than a vec-

tored interrupt. The operation of the processor is undefined if software writes a value into this bit that is

greater than the value in the HSS<3:0> bits.

bit 11-10 Unimplemented: Read as ‘0’

bit 9-6 PSS<3:0>: Previous Shadow Set bits

Since GPR shadow registers are implemented, this bit is copied from the CSS bit when an exception or

interrupt occurs. An ERET instruction copies this value back into the CSS bit if the BEV bit (Status<22>) = 0.

This bit is not updated on any exception which sets the ERL bit (Status<2>) to ‘1’ (i.e., Reset, Soft Reset,

NMI, cache error), an entry into EJTAG Debug mode, or any exception or interrupt that occurs with the EXL

bit (Status<1>) = 1, or BEV = 1. This bit is not updated on an exception that occurs while ERL = 1.

The operation of the processor is undefined if software writes a value into this bit that is greater than the

value in the HSS<3:0> bits.

bit 5-4 Unimplemented: Read as ‘0’

bit 3-0 CSS<3:0>: Current Shadow Set bits

Since GPR shadow registers are implemented, this bit is the number of the current GPR set. This bit is

updated with a new value on any interrupt or exception, and restored from the PSS bit on an ERET.

Tabl e 2-9 describes the various sources from which the CSS<3:0> bits are updated on an exception or

interrupt.

This bit is not updated on any exception which sets the ERL bit (Status<2>) to ‘1’ (i.e., Reset, Soft Reset,

NMI, cache error), an entry into EJTAG Debug mode, or any exception or interrupt that occurs with EXL bit

(Status<1>) = 1, or BEV = 1. Neither is it updated on an ERET with ERL = 1 or BEV = 1. This bit is not

updated on an exception that occurs while ERL = 1.

The value of the CSS<3:0> bits can be changed directly by software only by writing the PSS<3:0> bits and

executing an ERET instruction.

PIC32 Family Reference Manual

2.12.8 SRSMap: Register (CP0 Register 12, Select 3)

The SRSMap register contains eight 4-bit bits that provide the mapping from an vector number

to the shadow set number to use when servicing such an interrupt. The values from this register

are not used for a non-interrupt exception, or a non-vectored interrupt (IV bit = 0, Cause<23> or

VS<4:0> bit = 0, IntCtl<9:5>). In such cases, the shadow set number comes from the ESS<3:0>

bits (SRSCtl<15:12>).

If the HSS<3:0> bits (SRSCTL29:26) are ‘0’, the results of a software read or write of this register

are unpredictable.

The operation of the processor is undefined if a value is written to any bit in this register that is

greater than the value of the HSS<3:0> bits.

The SRSMap register contains the shadow register set numbers for vector numbers 7-0. The

same shadow set number can be established for multiple interrupt vectors, creating a

many-to-one mapping from a vector to a single shadow register set number.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSV7<3:0> SSV6<3:0>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSV5<3:0> SSV4<3:0>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSV3<3:0> SSV2<3:0>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSV1<3:0> SSV0<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 SSV7<3:0>: Shadow Set Vector 7 bits

Shadow register set number for Vector Number 7

bit 27-24 SSV6<3:0>: Shadow Set Vector 6 bits

Shadow register set number for Vector Number 6

bit 23-20 SSV5<3:0>: Shadow Set Vector 5 bits

Shadow register set number for Vector Number 5

bit 19-16 SSV4<3:0>: Shadow Set Vector 4 bits

Shadow register set number for Vector Number 4

bit 15-12 SSV3<3:0>: Shadow Set Vector 3 bits

Shadow register set number for Vector Number 3

bit 11-8 SSV2<3:0>: Shadow Set Vector 2 bits

Shadow register set number for Vector Number 2

bit 7-4 SSV1<3:0>: Shadow Set Vector 1 bits

Shadow register set number for Vector Number 1

bit 3-0 SSV0<3:0>: Shadow Set Vector 0 bit

Shadow register set number for Vector Number 0

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.12.9 Cause Register (CP0 Register 13, Select 0)

The Cause register primarily describes the cause of the most recent exception. In addition, bits

also control software interrupt requests and the vector through which interrupts are dispatched.

With the exception of the IP1, IP0, DC, and IV bits, all bits in the Cause register are read-only.

Table 2-10: Cause Register EXCCODE<4:0> Bits

Exception Code Value

Mnemonic Description

Decimal Hex

00x00 IntInterrupt

1-3 0x01 —Reserved

4 0x04 AdEL Address error exception (load or instruction fetch)

50x05AdESAddress error exception (store)

60x06IBEBus error exception (instruction fetch)

70x07DBEBus error exception (data reference: load or store)

80x08SysSyscall exception

90x09 BpBreakpoint exception

10 0x0A RI Reserved instruction exception

11 0x0B CPU Coprocessor Unusable exception

12 0x0C Ov Arithmetic Overflow exception

13 0x0D Tr Trap exception

14-31 0x0E-0x1F —Reserved

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R-x R-x R-x R-x R/W-0 U-0 U-0 U-0

BD TI CE<1:0> DC — — —

23:16 R/W-x U-0 U-0 U-0 U-0 U-0 U-0 U-0

IV — — — — — — —

15:8 U-0 U-0 U-0 R-x R-x R-x R/W-x R/W-x

— — — RIPL<2:0> IP1 IP0

7:0 U-0 R-x R-x R-x R-x R-x U-0 U-0

—EXCCODE<4:0>— —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 BD: Branch Delay bit

Indicates whether the last exception taken occurred in a branch delay slot:

1 = In delay slot

0 = Not in delay slot

The processor updates BD only if the EXL bit (Status<1>) was ‘0’ when the exception occurred.

bit 30 TI: Timer Interrupt bit

Timer Interrupt. This bit denotes whether a timer interrupt is pending (analogous to the IP bits for other

interrupt types):

1 = Timer interrupt is pending

0 = No timer interrupt is pending

bit 29-28 CE<1:0>: Coprocessor Exception bits

Coprocessor unit number referenced when a Coprocessor Unusable exception is taken. This bit is loaded

by hardware on every exception, but is unpredictable for all exceptions except for Coprocessor Unusable.

PIC32 Family Reference Manual

bit 27 DC: Disable Count Register bit

In some power-sensitive applications, the Count register is not used and can be stopped to avoid

unnecessary toggling.

1 = Disable counting of Count register

0 = Enable counting of Count register

bit 26-24 Unimplemented: Read as ‘0’

bit 23 IV: Interrupt Vector bit

Indicates whether an interrupt exception uses the general exception vector or a special interrupt vector

1 = Use the special interrupt vector (0x200)

0 = Use the general exception vector (0x180)

If the IV bit (Cause<23>) is ‘1’ and the BEV bit (Status<22>) is ‘0’, the special interrupt vector represents

the base of the vectored interrupt table.

bit 22-13 Unimplemented: Read as ‘0’

bit 12-10 RIPL<2:0>: Requested Interrupt Priority Level bits

This bit is the encoded (7-0) value of the requested interrupt. A value of ‘0’ indicates that no interrupt is

requested.

bit 9-8 IP<1:0>: Software Interrupt Request Control bits

Controls the request for software interrupts

1 = Request software interrupt

0 = No interrupt requested

These bits are exported to the system interrupt controller for prioritization in EIC Interrupt mode with other

interrupt sources.

bit 7 Unimplemented: Read as ‘0’

bit 6-2 EXCCODE<4:0>: Exception Code bits

See Tab l e 2- 10 for the list of Exception codes.

bit 1-0 Unimplemented: Read as ‘0’

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.12.10 EPC Register (CP0 Register 14, Select 0)

The Exception Program Counter (EPC) is a read/write register that contains the address at which

processing resumes after an exception has been serviced. All bits of the EPC register are

significant and are writable.

For synchronous (precise) exceptions, the EPC contains one of the following:

•The virtual address of the instruction that was the direct cause of the exception

•The virtual address of the immediately preceding BRANCH or JUMP instruction, when the

exception causing instruction is in a branch delay slot and the Branch Delay bit in the

Cause register is set

On new exceptions, the processor does not write to the EPC register when the EXL bit in the

Status register is set, however, the register can still be written via the MTC0 instruction.

Since the PIC32 family implements MIPS16e® or microMIPS™ ASE, a read of the EPC register

(via MFC0) returns the following value in the destination GPR:

GPR[rt]  ExceptionPC31..1 || ISAMode0

That is, the upper 31 bits of the exception PC are combined with the lower bit of the ISA<1:0>

bits (Config3<15:14>) and are written to the GPR.

Similarly, a write to the EPC register (via MTC0) takes the value from the GPR and distributes

that value to the exception PC and the ISA<1:0> bits (Config3<15:14>), as follows:

ExceptionPC  GPR[rt]31..1 || 0

ISAMode  2#0 || GPR[rt]0

That is, the upper 31 bits of the GPR are written to the upper 31 bits of the exception PC, and the

lower bit of the exception PC is cleared. The upper bit of the ISA<1:0> bits (Config3<15:14>) is

cleared and the lower bit is loaded from the lower bit of the GPR.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EPC<31:24>

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EPC<23:16>

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EPC<15:8>

7:0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EPC<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 EPC<31:0>: Exception Program Counter bits

PIC32 Family Reference Manual

2.12.11 PRID Register (CP0 Register 15, Select 0)

The Processor Identification (PRID) register is a 32-bit read-only register that contains

information identifying the manufacturer, manufacturer options, processor identification, and

revision level of the processor.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 R-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-1

COMPANYID<23:16>

15:8 R-x R-x R-x R-x R-x R-x R-x R-x

PROCESSORID<15:8>

7:0 R-x R-x R-x R-x R-x R-x R-x R-x

MAJORREV<2:0> MINORREV<2:0> PATCHREV<1:0>

Legend: Legend:

R=Readable bit W=Writable bit P=Programmable bit r=Reserved bit

U=Unimplemented bit n=Bit Value at POR: (‘0’, ‘1’, x=Unknown)

bit 31-24 Unimplemented: Read as ‘0’

bit 23-16 COMPANYID<7:0>: Company Identification bits

In PIC32 devices, these bits contain a value of ‘1’ to indicate MIPS® Technologies, Inc. as the processor

manufacturer/designer.

bit 15-8 PROCESSORID<7:0>: Processor Identification bits

These bits allow software to distinguish between the various types of MIPS® Technologies processors. For

PIC32 devices with the M4K® core, this value is 0x87.

bit 7-5 MAJORREV<2:0>: Processor Major Revision Identification bits

These bits allow software to distinguish between one revision and another of the same processor type. This

number is increased on major revisions of the processor core.

bit 4-2 MINORREV<2:0>: Processor Minor Revision Identification bits

This number is increased on each incremental revision of the processor and reset on each new major

revision.

bit 1-0 PATCHREV<1:0>: Processor Patch Level Identification bits

If a patch is made to modify an older revision of the processor, the value of these bits will be incremented.

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.12.12 Ebase Register (CP0 Register 15, Select 1)

The Ebase register is a read/write register containing the base address of the exception vectors

used when the BEV bit (Status<22>) equals ‘0’, and a read-only CPU number value that may be

used by software to distinguish different processors in a multi-processor system.

The Ebase register provides the ability for software to identify the specific processor within a

multi-processor system, and allows the exception vectors for each processor to be different,

especially in systems composed of heterogeneous processors. Bits 31-12 of the Ebase register

are concatenated with zeros to form the base of the exception vectors when the BEV bit is ‘0’.

The exception vector base address comes from the fixed defaults when the BEV bit is ‘1’, or for

any EJTAG Debug exception. The Reset state of bits 31-12 of the Ebase register initialize the

exception base register to 0x80000000.

Bits 31 and 30 of the Ebase Register are fixed with the value 2#10 to force the exception base

address to be in the kseg0 or kseg1 unmapped virtual address segments.

If the value of the exception base register is to be changed, this must be done with the BEV bit

equal to ‘1’. The operation of the processor is undefined if the Ebase<17:0> bits are written with

a different value when the BEV bit (Status<22>) is ‘0’.

Combining bits 31-20 of the Ebase register allows the base address of the exception vectors to

be placed at any 4 KB page boundary.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — EBASE<17:12>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EBASE<11:4>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R-0 R-0

EBASE<3:0> — —CPUNUM<9:8>

7:0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CPUNUM<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 Unimplemented: Read as ‘1’

bit 30 Unimplemented: Read as ‘0’

bit 29-12 EBASE<17:0>: Exception Vector Base Address bits

In conjunction with bits 31-30, these bits specify the base address of the exception vectors when the BEV

bit (Status<22>) is ‘0’.

bit 11-10 Unimplemented: Read as ‘0’

bit 9-0 CPUNUM<9:0>: CPU Number bits

These bits specify the number of CPUs in a multi-processor system and can be used by software to

distinguish a particular processor from others. In a single processor system, this value is set to ‘0’.

PIC32 Family Reference Manual

2.12.13 Config Register (CP0 Register 16, Select 0)

The Config register specifies various configuration and capabilities information. Most of the fields

in the Config register are initialized by hardware during the Reset exception process, or are

constant.

Table 2-11: Cache Coherency Attributes

K0<2:0> Value Cache Coherency Attribute

2 Uncached

3Cacheable

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 r-1 R-0 R-1 R-0 R/W-0 R/W-1 R/W-0 U-0

—K23<2:0> KU<2:0>—

23:16 U-0 R-0 R-0 r-0 U-0 U-0 U-0 R-1

—UDISB— — — —DS

15:8 R-0 R-0 R-0 R-0 R-0 R-1 R-0 R-1

BE AT<1:0> AR<2:0> MT<2:1>

7:0 R-1 U-0 U-0 U-0 U-0 R/W-0 R/W-1 R/W-0

MT<1> — — — —K0<2:0>

Legend: r = Reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 Reserved: This bit is hardwired to ‘1’ to indicate the presence of the Config1 register.

bit 30-28 K23<2:0>: kseg2 and kseg3 bits

These bits control the cacheability of the kseg2 and kseg3 address segments.

Refer to Ta ble 2 -11 for the bit encoding.

bit 27-25 KU<2:0>: kuseg and useg bits

These bits control the cacheability of the kuseg and useg address segments.

Refer to Ta ble 2 -11 for the bit encoding.

bit 24-23 Unimplemented: Read as ‘0’

bit 22 UDI: User-Defined bit

This bit indicates that CorExtend User-Defined Instructions have been implemented.

1 = User-defined Instructions are implemented

0 = No User-defined Instructions are implemented

bit 21 SB: SimpleBE bit

This bit indicates whether SimpleBE Bus mode is enabled.

1 = Only simple byte enables allowed on internal bus interface

0 = No reserved byte enables on internal bus interface

bit 20 Reserved: This bit is hardwired to ‘0’ to indicate the Fast, High-Performance Multiply/Divide Unit (MDU)

bit 19-17 Unimplemented: Read as ‘0’

bit 16 DS: Dual SRAM bit

1 = Dual instruction/data SRAM internal bus interfaces

0 = Unified instruction/data SRAM internal bus interface

PIC32 devices based on the M4K® core use Dual SRAM-style interfaces internally.

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

bit 15 BE: Big-Endian bit

Indicates the endian mode in which the processor is running, PIC32 is always little-endian.

1 = Big-endian

0 = Little-endian

bit 14-13 AT<1:0>: Architecture Type bits

Architecture type implemented by the processor. This bit is always ‘00’ to indicate the MIPS32®

architecture.

bit 12-10 AR<2:0>: Architecture Revision Level bits

Architecture revision level. This bit is always ‘001’ to indicate MIPS32® Release 2.

111 = Reserved

110 = Reserved

101 = Reserved

100 = Reserved

011 = Reserved

010 = Reserved

001 = Release 2

000 = Release 1

bit 9-7 MT<2:0>: MMU Type bits

111 = Reserved

110 = Reserved

101 = Reserved

100 = Reserved

011 = Fixed mapping

010 = Reserved

001 = Reserved

000 = Reserved

bit 6-3 Unimplemented: Read as ‘0’

bit 2-0 K0<2:0>: Kseg0 bits

Kseg0 coherency algorithm. Refer to Tab l e 2- 11 for the bit encoding.

PIC32 Family Reference Manual

2.12.14 Config1 Register (CP0 Register 16, Select 1)

The Config1 register is an adjunct to the Config register and encodes additional information

about capabilities present on the core. All fields in the Config1 register are read-only.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 r-1 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 U-0 U-0 R-1 R-x U-0

— — — — —CAEP—

Legend: r = Reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 Reserved: This bit is hardwired to a ‘1’ to indicate the presence of the Config2 register.

bit 30-3 Unimplemented: Read as ‘0’

bit 2 CA: Code Compression Implemented bit

1 = MIPS16e® is implemented

0 = No MIPS16e® present

bit 1 EP: EJTAG Present bit

This bit is always set to ‘1’ indicate that the core implements EJTAG.

bit 0 Unimplemented: Read as ‘0’

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.12.15 Config2 (CP0 Register 16, Select 2)

The Config2 register is an adjunct to the Config register and is reserved to encode additional

capabilities information. Config2 is allocated for showing the configuration of level 2/3 caches.

These bits are reset to ‘0’ because L2/L3 caches are not supported by the PIC32 core. All bits in

the Config2 register are read-only.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 r-1 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

Legend: r = Reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 Reserved: This bit is hardwired to a ‘1’ to indicate the presence of the Config3 register.

bit 30-0 Unimplemented: Read as ‘0’

PIC32 Family Reference Manual

2.12.16 Config3 Register (CP0 Register 16, Select 3)

The Config3 register encodes additional capabilities. All fields in the Config3 register are

read-only.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0

— — — — — — —ITL

7:0 U-0 R-1 R-1 U-0 U-0 U-0 U-0 U-0

— VEIC VINT — — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-9 Unimplemented: Read as ‘0’

bit 8 ITL: Indicates that iFlowTrace hardware is present

1 = The iFlowTrace is implemented in the core

0 = The iFlowTrace is not implemented in the core

bit 7 Unimplemented: Read as ‘0’

bit 6 VEIC: External Vectored Interrupt Controller bit

Support for an external interrupt controller is implemented.

1 = Support for EIC Interrupt mode is implemented

0 = Support for EIC Interrupt mode is not implemented

PIC32 devices internally implement a MIPS® “external interrupt controller”; therefore, this bit reads ‘1’.

bit 5 VINT: Vector Interrupt bit

Vectored interrupts implemented. This bit indicates whether vectored interrupts are implemented.

1 = Vector interrupts are implemented

0 = Vector interrupts are not implemented

On the PIC32 core, this bit is always a ‘1’ since vectored interrupts are implemented.

bit 4-0 Unimplemented: Read as ‘0’

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.12.17 Debug Register (CP0 Register 23, Select 0)

The Debug register is used to control the debug exception and provide information about the

cause of the debug exception and when re-entering at the debug exception vector due to a

normal exception in Debug mode. The read-only information bits are updated every time the

debug exception is taken or when a normal exception is taken when already in Debug mode.

Only the DM bit and the VER<2:0> bits are valid when read from non-Debug mode; the values

of all other bits and fields are unpredictable. Operation of the processor is undefined if the Debug

Some of the bits and fields are only updated on debug exceptions and/or exceptions in Debug

mode, as follows:

•DSS, DBP, DDBL, DDBS, DIB, DINT are updated on both debug exceptions and on

exceptions in debug modes

•DEXCCODE<4:0> are updated on exceptions in Debug mode, and are undefined after a

debug exception

•HALT and DOZE are updated on a debug exception, and are undefined after an exception

in Debug mode

•DBD is updated on both debug and on exceptions in debug modes

All bits are undefined when read from Normal mode, except VER<2:0> and DM.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R-0 R-0 R-0 R/W-0 U-0 U-0 R/W-1 R/W-0

DBD DM NODCR LSNM DOZE HALT COUNTDM IBUSEP

23:16 R-0 R-0 R/W-0 R/W-0 R-0 R-0 R-0 R-1

MCHECKP CACHEEP DBUSEP IEXI DDBSIMPR DDBLIMPR VER<2:1>

15:8 R-0 U-0 U-0 U-0 U-0 U-0 R-0 R/W-0

VER DEXCCODE<4:0> NOSST SST

7:0 U-0 R-x R-x R-x R-x R-x R-x R-x

—DIBIMPRDINT DIB DDBSDDBL DBP DSS

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 DBD: Branch Delay Debug Exception bit

Indicates whether the last debug exception or exception in Debug mode, occurred in a branch delay slot:

1 = In delay slot

0 = Not in delay slot

bit 30 DM: Debug Mode bit

Indicates that the processor is operating in Debug mode:

1 = Processor is operating in Debug mode

0 = Processor is operating in non-Debug mode

bit 29 NODCR: Debug Control Register bit

Indicates whether the dseg memory segment is present and the Debug Control Register is accessible:

1 = No dseg present

0 = dseg is present

PIC32 Family Reference Manual

bit 28 LSNM: Load Store Access Control bit

Controls access of load/store between dseg and main memory:

1 = Load/stores in dseg address range goes to main memory

0 = Load/stores in dseg address range goes to dseg

bit 27 DOZE: Low-Power Mode Debug Exception bit

Indicates that the processor was in any kind of low-power mode when a debug exception occurred.

1 = Processor was in a low-power mode when a debug exception occurred

0 = Processor was not in a low-power mode when debug exception occurred

bit 26 HALT: System Bus Clock Stop bit

Indicates that the internal system bus clock was stopped when the debug exception occurred.

1 = Internal system bus clock running

0 = Internal system bus clock stopped

bit 25 COUNTDM: Count Register Behavior bit

Indicates the Count register behavior in Debug mode.

1 = Count register is running in Debug mode

0 = Count register stopped in Debug mode

bit 24 IBUSEP: Instruction Fetch Bus Error Exception Pending bit

Set when an instruction fetch bus error event occurs or if a ‘1’ is written to the bit by software. Cleared when

a Bus Error exception on instruction fetch is taken by the processor, and by Reset. If IBUSEP is set when

IEXI is cleared, a Bus Error exception on instruction fetch is taken by the processor, and IBUSEP is cleared.

bit 23 MCHECKP: Machine Check Exception Pending bit

All Machine Check exceptions are precise on the PIC32 processor so this bit will always read as ‘0’.

bit 22 CACHEEP: Cache Error Pending bit

Cache Errors cannot be taken by the PIC32 core so this bit will always read as ‘0’.

bit 21 DBUSEP: Data Access Bus Error Exception Pending bit

Covers imprecise bus errors on data access, similar to behavior of IBUSEP for imprecise bus errors on an

instruction fetch.

bit 20 IEXI: Imprecise Error Exception Inhibit Control bit

Controls exceptions taken due to imprecise error indications. Set when the processor takes a debug excep-

tion or exception in Debug mode. Cleared by execution of the DERET instruction; otherwise modifiable by

Debug mode software. When IEXI is set, the imprecise error exception from a bus error on an instruction

fetch or data access, cache error, or machine check is inhibited and deferred until the bit is cleared.

bit 19 DDBSIMPR: Debug Data Break Store Exception bit

Indicates that an imprecise Debug Data Break Store exception was taken. All data breaks are precise on

the PIC32 core, so this bit will always read as ‘0’.

bit 18 DDBLIMPR: Debug Data Break Load Exception bit

Indicates that an imprecise Debug Data Break Load exception was taken. All data breaks are precise on the

PIC32 core, so this bit will always read as ‘0’.

bit 17-15 VER<2:0>: EJTAG Version bit

Contains the EJTAG version number.

bit 14-10 DEXCCODE<4:0>: Latest Exception in Debug Mode bit

Indicates the cause of the latest exception in Debug mode. The bit is encoded as the EXCCODE<4:0> bits

in the Cause register for those normal exceptions that may occur in Debug mode. Value is undefined after

a debug exception.

bit 9 NOSST: Singe-step Feature Control bit

Indicates whether the single-step feature controllable by the SST bit is available in this implementation.

1 = No single-step feature available

0 = Single-step feature available

bit 8 SST: Debug Single-step Control bit

Controls if debug single-step exception is enabled.

1 = Debug single step exception enabled

0 = No debug single-step exception enabled

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

bit 7 Unimplemented: Read as ‘0’

bit 6 DIBImpr: Imprecise Debug Instruction Break Exception bit

Indicates that an imprecise debug instruction break exception occurred (due to a complex breakpoint).

Cleared on exception in Debug mode.

bit 5 DINT: Debug Interrupt Exception bit

Indicates that a debug interrupt exception occurred. Cleared on exception in Debug mode.

1 = Debug interrupt exception

0 = No debug interrupt exception

bit 4 DIB: Debug Instruction Break Exception bit

Indicates that a debug instruction break exception occurred. Cleared on exception in Debug mode.

1 = Debug instruction exception

0 = No debug instruction exception

bit 3 DDBS: Debug Data Break Exception on Store bit

Indicates that a debug data break exception occurred on a store. Cleared on exception in Debug mode.

1 = Debug instruction exception on a store

0 = No debug data exception on a store

bit 2 DDBL: Debug Data Break Exception on Load bit

Indicates that a debug data break exception occurred on a load. Cleared on exception in Debug mode.

1 = Debug instruction exception on a load

0 = No debug data exception on a load

bit 1 DBP: Debug Software Breakpoint Exception bit

Indicates that a debug software breakpoint exception occurred. Cleared on exception in Debug mode.

1 = Debug software breakpoint exception

0 = No debug software breakpoint exception

bit 0 DSS: Debug Single-step Exception bit

Indicates that a debug single-step exception occurred. Cleared on exception in Debug mode.

1 = Debug single-step exception

0 = No debug single-step exception

PIC32 Family Reference Manual

2.12.18 TraceControl Register (CP0 Register 23, Select 1)

The TraceControl register enables software trace control and is only implemented on devices

with the EJTAG trace capability.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

TS UT ——TB IO D

(1) E(1)

23:16 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

K(1) —U

(1) — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 U-1 R/W-0 R/W-0 R/W-0 R/W-0

————MODE<2:0> IB

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 TS: Trace Select bit

This bit is used to select between the hardware and the software trace control bits.

1 = Selects the trace control bits

0 = Selects the external hardware trace block signals

bit 30 UT: User Type Select bit

This bit is used to indicate the type of user-triggered trace record.

1 = User type 2

0 = User type 1

bit 29-28 Unimplemented: Read as ‘0’

bit 27 TB: Trace Branch bit

1 = Trace the PC value for all taken branches

0 = Trace the PC value for branch targets with unpredictable static addresses

bit 26 IO: Inhibit Overflow bit

This signal is used to indicate to the core trace logic that slow but complete tracing is desired.

1 = Inhibit FIFO overflow or discard of trace data

0 = Allow FIFO overflow or discard of trace data

bit 25 D: Debug Mode Trace Enable bit(1)

1 = Enable tracing in Debug mode

0 = Disable tracing in Debug mode

bit 24 E: Exception Mode Trace Enable bit(1)

1 = Enable tracing in Exception mode

0 = Disable tracing in Exception mode

bit 23 K: Kernel Mode Trace Enable bit(1)

1 = Enable tracing in Kernel mode

0 = Disable tracing in Kernel mode

bit 22 Unimplemented: Read as ‘0’

Note 1: The ON bit must be set to ‘1’ to enable tracing.

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

bit 21 U: User Mode Trace Enable bit(1)

1 = Enable tracing in User mode

0 = Disable tracing in User mode

bit 20-5 Unimplemented: Read as ‘0’

bit 4 Unimplemented: Read as ‘1’

bit 3-1 MODE<2:0>: Trace Mode Control bits

111 = Trace PC and both load and store address and data

110 = Trace PC and store address and data

101 = Trace PC and load address and data

100 = Trace PC and load data

011 = Trace PC and both load and store addresses

010 = Trace PC and store address

001 = Trace PC and load address

000 = Trace PC

bit 0 ON: Master Trace Enable bit

1 = Tracing is enabled when another trace enable bit is set to ‘1’

0 = Tracing is disabled

Note 1: The ON bit must be set to ‘1’ to enable tracing.

PIC32 Family Reference Manual

2.12.19 TraceControl2 Register (CP0 Register 23, Select 2)

The TraceControl2 register provides additional control and status information. Note that some

fields in the TraceControl2 register are read-only, but have a reset state of “Undefined”. This is

because these values are loaded from the Trace Control Block (TCB). As such, these fields in

the TraceControl2 register will not have valid values until the TCB asserts these values.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 R-1 R-0 R-x R-x R-x R-x R-x

—VALIDMODES<1:0>TBITBU SYP<2:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-7 Unimplemented: Read as ‘0’

bit 6-5 VALIDMODES<1:0>: Valid Trace Mode Select bits

11 = Reserved

10 = PC, load and store address, and load and store data

01 = PC and load and store address tracing only

00 = PC tracing only

bit 4 TBI: Trace Buffers Implemented bit

1 = On-chip and off-chip trace buffers are implemented by the TCB

0 = Only one trace buffer is implemented

bit 3 TBU: Trace Buffers Used bit

1 = Trace data is being sent to an off-chip trace buffer

0 = Trace data is being sent to an on-chip trace buffer

bit 2-0 SYP<2:0>: Synchronization Period bits

The “On-chip” column value is used when the trace data is being written to an on-chip trace buffer (e.g,

TraceControl2TBU = 0). Conversely, the “Off-chip” column is used when the trace data is being written to an

off-chip trace buffer (e.g, TraceControl2TBU = 1).

Bit

Setting On-chip Off-chip

111 = 2227

110 = 2328

101 = 2429

100 = 25210

011 = 26211

010 = 27212

001 = 28213

000 = 29214

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.12.20 UserTraceData Register (CP0 Register 23, Select 3)

A software write to any bits in the UserTraceData register will trigger a trace record to be written

indicating a type 1 or type 2 user format. The type is based on the UT bit in the TraceControl

unpredictable if this register is written in consecutive cycles.

This register is only implemented on devices with the EJTAG trace capability.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATA<31:24>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATA<23:10>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATA<15:6>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DATA: Software Readable/Writable Data bits

When written, this register triggers a user format trace record out of the PDtrace interface that transmits the

Data bit to trace memory.

PIC32 Family Reference Manual

2.12.21 TraceBPC Register (CP0 Register 23, Select 4)

This register is used to control start and stop of tracing using an EJTAG Hardware breakpoint.

The Hardware breakpoint would then be set as a trigger source and optionally also as a Debug

exception breakpoint.

This register is only implemented on devices with both Hardware breakpoints and the EJTAG

trace capability.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

DE — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — —DBPO1DBPO0

15:8 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

IE — — — — — — —

7:0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

——IBPO5IBPO4IBPO3IBPO2IBPO1

IBPO0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 DE: EJTAG Data Breakpoint Trigger Select bit

1 = Enable trigger signals from data breakpoints

0 = Disable trigger signals from data breakpoints

bit 15 IE: EJTAG Instruction Breakpoint Select bit

1 = Enable trigger signals from instruction breakpoints

0 = Disable trigger signals from instruction breakpoints

bit 14-6 Unimplemented: Read as ‘0’

bit 5 IBPO5: Instruction Breakpoint 6 bit

1 = Enable corresponding instruction breakpoint trigger to start tracing

0 = Disable tracing with the trigger signal

bit 4 IBPO4: Instruction Breakpoint 5 bit

1 = Enable corresponding instruction breakpoint trigger to start tracing

0 = Disable tracing with the trigger signal

bit 3 IBPO3: Instruction Breakpoint 4 bit

1 = Enable corresponding instruction breakpoint trigger to start tracing

0 = Disable tracing with the trigger signal

bit 2 IBPO2: Instruction Breakpoint 3 bit

1 = Enable corresponding instruction breakpoint trigger to start tracing

0 = Disable tracing with the trigger signal

bit 1 IBPO1: Instruction Breakpoint 2 bit

1 = Enable corresponding instruction breakpoint trigger to start tracing

0 = Disable tracing with the trigger signal

bit 0 IBPO0: Instruction Breakpoint 1 bit

1 = Enable corresponding instruction breakpoint trigger to start tracing

0 = Disable tracing with the trigger signal

Note 1: Refer to the specific device data sheet for the list of available trigger sources.

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.12.22 Debug2 Register (CP0 Register 23, Select 5)

This register holds additional information about Complex Breakpoint exceptions. This register is

only implemented if complex hardware breakpoints are present.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 r-1 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 U-0 R-x R-x R-x R-x

— — — — PRM DQ TUP PACO

Legend: r = Reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 Reserved: Read as ‘1’

bit 30-4 Unimplemented: Read as ‘0’

bit 3 PRM: Primed bit

Indicates whether a complex breakpoint with an active priming condition was seen on the last debug

exception.

bit 2 DQ: Data Qualified bit

Indicates whether a complex breakpoint with an active data qualifier was seen on the last debug exception.

bit 1 TUP: Tuple Breakpoint bit

Indicates whether a tuple breakpoint was seen on the last debug exception.

bit 0 PACO: Pass Counter bit

Indicates whether a complex breakpoint with an active pass counter was seen on the last debug exception.

PIC32 Family Reference Manual

2.12.23 DEPC Register (CP0 Register 24, Select 0)

The Debug Exception Program Counter (DEPC) register is a read/write register that contains the

address at which processing resumes after a debug exception or Debug mode exception has

been serviced.

For synchronous (precise) debug and Debug mode exceptions, the DEPC register contains

either:

•The virtual address of the instruction that was the direct cause of the debug exception, or

• The virtual address of the immediately preceding branch or jump instruction, when the

debug exception causing instruction is in a branch delay slot, and the Debug Branch Delay

(DBD) bit in the Debug register is set.

For asynchronous debug exceptions (debug interrupt), the DEPC register contains the virtual

address of the instruction where execution should resume after the debug handler code is

executed.

Since some of the devices in the PIC32 family implement the MIPS16e® ASE, a read of the

DEPC register (via MFC0) returns the following value in the destination GPR:

GPR[rt] = DebugExceptionPC31..1 || ISAMode0

That is, the upper 31 bits of the debug exception PC are combined with the lower bit of the

ISA<1:0> bits (Config3<15:14>)and are written to the GPR.

Similarly, a write to the DEPC register (via MTC0) takes the value from the GPR and distributes

that value to the debug exception PC and the ISA<1:0> bits (Config3<15:14>), as follows:

DebugExceptionPC = GPR[rt]31..1 || 0

ISAMode = 2#0 || GPR[rt]0

That is, the upper 31 bits of the GPR are written to the upper 31 bits of the debug exception PC,

and the lower bit of the debug exception PC is cleared. The upper bit of the ISA<1:0> bits

(Config3<15:14>) is cleared and the lower bit is loaded from the lower bit of the GPR.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

DEPC<31:24>

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

DEPC<23:16>

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

DEPC<15:8>

7:0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

DEPC<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DEPC<31:0>: Debug Exception Program Counter bits

The DEPC register is updated with the virtual address of the instruction that caused the debug exception. If

the instruction is in the branch delay slot, then the virtual address of the immediately preceding branch or jump

instruction is placed in this register.

Execution of the DERET instruction causes a jump to the address in the DEPC register.

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.12.24 ErrorEPC (CP0 Register 30, Select 0)

The ErrorEPC register is a read/write register, similar to the EPC register, except that ErrorEPC

is used on error exceptions. All bits of the ErrorEPC register are significant and must be writable.

It is also used to store the program counter on Reset, Soft Reset, and non-maskable interrupt

(NMI) exceptions.

The ErrorEPC register contains the virtual address at which instruction processing can resume

after servicing an error. This address can be:

•The virtual address of the instruction that caused the exception

•The virtual address of the immediately preceding branch or jump instruction when the error

causing instruction is in a branch delay slot

Unlike the EPC register, there is no corresponding branch delay slot indication for the ErrorEPC

Since some of the devices in the PIC32 family implement the MIPS16e® ASE, a read of the

ErrorEPC register (via MFC0) returns the following value in the destination GPR:

GPR[rt] = ErrorExceptionPC31..1 || ISAMode0

That is, the upper 31 bits of the error exception PC are combined with the lower bit of the

ISA<1:0> bits (Config3<15:14>) and are written to the GPR.

Similarly, a write to the ErrorEPC register (via MTC0) takes the value from the GPR and

distributes that value to the error exception PC and the ISA<1:0> bits (Config3<15:14>), as

follows:

ErrprExceptionPC = GPR[rt]31..1 || 0

ISAMode = 2#0 || GPR[rt]0

That is, the upper 31 bits of the GPR are written to the upper 31 bits of the error exception PC,

and the lower bit of the error exception PC is cleared. The upper bit of the ISA<1:0> bits

(Config3<15:14>) is cleared and the lower bit is loaded from the lower bit of the GPR.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

ErrorEPC<31:24>

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

ErrorEPC<23:16>

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

ErrorEPC<15:8>

7:0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

ErrorEPC<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 ErrorEPC<31:0>: Error Exception Program Counter bits

PIC32 Family Reference Manual

2.12.25 DeSAVE Register (CP0 Register 31, Select 0)

The DeSAVE register is a read/write register that functions as a simple memory location. This

save the rest of the context to a predetermined memory area (such as in the EJTAG Probe). This

existence of a valid stack for context saving cannot be assumed.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

DESAVE<31:24>

23:16 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

DESAVE<23:16>

15:8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

DESAVE<15:8>

7:0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

DESAVE<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DESAVE<31:0>: Debug Exception Save bits

Scratch Pad register used by Debug Exception code.

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.13 MIPS16e® EXECUTION

When the core is operating in MIPS16e® mode, instruction fetches only require 16-bits of data to

be returned. However, for improved efficiency, the core will fetch 32-bits of instruction data when-

ever the address is word-aligned. Therefore, for sequential MIPS16e® code, fetches only occur

for every other instruction, resulting in better performance and reduced system power.

2.14 MEMORY MODEL

Virtual addresses used by software are converted to physical addresses by the memory

management unit (MMU) before being sent to the CPU busses. The PIC32 CPU uses a fixed

mapping for this conversion. For more information regarding the system memory model, see

Section 3. “Memory Organization” (DS61115).

Figure 2-14: Address Translation During SRAM Access

2.14.1 Cacheability

The CPU uses the virtual address of an instruction fetch, load or store to determine whether to

access the cache or not. Memory accesses within kseg0, or useg/kuseg can be cached, while

accesses within kseg1 are non-cacheable. The CPU uses the CCA bits in the Config register to

determine the cacheability of a memory segment. A memory access is cacheable if its

corresponding CCA = 0112. For more information on cache operation, see Section 4. “Prefetch

Cache Module” (DS61119).

2.14.1.1 LITTLE ENDIAN BYTE ORDERING

On CPUs that address memory with byte resolution, there is a convention for multi-byte data

items that specify the order of high-order to low-order bytes. Big-endian byte-ordering is where

the lowest address has the MSB. Little-endian ordering is where the lowest address has the LSB

of a multi-byte datum. The PIC32 CPU supports little-endian byte ordering.

Figure 2-15: Big-Endian Byte Ordering

Figure 2-16: Little-Endian Byte Ordering

SRAM

Interface

Instn

SRAM

Data

SRAM

FMT

Instruction

Address

Calculator

Data

Address

Calculator

Virtual

Address

Virtual

Address

Physical

Address

Physical

Address

Higher

Address Word

Address

Lower

Address

Bit #

} 1 word = 4 bytes

31 24 23 16 15 8 70

Higher

Address Word

Address

Lower

Address

Bit #

31 24 23 16 15 8 70

PIC32 Family Reference Manual

2.15 CPU INSTRUCTIONS, GROUPED BY FUNCTION

CPU instructions are organized into the following functional groups:

•Load and store

•Computational

• Jump and branch

•Miscellaneous

•Coprocessor

Each instruction is 32 bits long.

2.15.1 CPU Load and Store Instructions

MIPS® processors use a load/store architecture; all operations are performed on operands held

in processor registers and main memory is accessed only through load and store instructions.

2.15.1.1 TYPES OF LOADS AND STORES

There are several different types of load and store instructions, each designed for a different

purpose:

•Transferring variously-sized fields (for example, LB, SW)

•Trading transferred data as signed or unsigned integers (for example, LHU)

•Accessing unaligned fields (for example, LWR, SWL)

•Atomic memory update (read-modify-write: for instance, LL/SC)

2.15.1.2 LIST OF CPU LOAD AND STORE INSTRUCTIONS

The following data sizes (as defined in the AccessLength field) are transferred by CPU load and

store instructions:

•Byte

•Half-word

•Word

Signed and unsigned integers of different sizes are supported by loads that either sign-extend or

zero-extend the data loaded into the register.

Unaligned words and double words can be loaded or stored in just two instructions by using a

pair of special instructions. For loads a LWL instruction is paired with a LWR instruction. The load

instructions read the left-side or right-side bytes (left or right side of register) from an aligned word

and merge them into the correct bytes of the destination register.

2.15.1.3 LOADS AND STORES USED FOR ATOMIC UPDATES

The paired instructions, Load Linked and Store Conditional, can be used to perform an atomic

read-modify-write of word or double word cached memory locations. These instructions are used

in carefully coded sequences to provide one of several synchronization primitives, including

test-and-set, bit-level locks, semaphores, and sequencers and event counts.

2.15.1.4 COPROCESSOR LOADS AND STORES

If a particular coprocessor is not enabled, loads and stores to that processor cannot execute and

the attempted load or store causes a Coprocessor Unusable exception. Enabling a coprocessor

is a privileged operation provided by the System Control Coprocessor, CP0.

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.15.2 Computational Instructions

Two’s complement arithmetic is performed on integers represented in 2s complement notation.

These are signed versions of the following operations:

•Add

•Subtract

•Multiply

•Divide

The add and subtract operations labelled “unsigned” are actually modulo arithmetic without

overflow detection.

There are also unsigned versions of multiply and divide, as well as a full complement of shift and

logical operations. Logical operations are not sensitive to the width of the register.

MIPS32® provides 32-bit integers and 32-bit arithmetic.

2.15.2.1 SHIFT INSTRUCTIONS

The ISA defines two types of shift instructions:

•Those that take a fixed shift amount from a 5-bit field in the instruction word (for instance,

SLL, SRL)

•Those that take a shift amount from the low-order bits of a general register (for instance,

SRAV, SRLV)

2.15.2.2 MULTIPLY AND DIVIDE INSTRUCTIONS

The multiply instruction performs 32-bit by 32-bit multiplication and creates either 64-bit or 32-bit

results. Divide instructions divide a 64-bit value by a 32-bit value and create 32-bit results. With

one exception, they deliver their results into the HI and LO special registers. The MUL instruction

delivers the lower half of the result directly to a GPR.

• Multiply produces a full-width product twice the width of the input operands; the low half is

loaded into LO and the high half is loaded into HI

•Multiply-Add and Multiply-Subtract produce a full-width product twice the width of the input

operations and adds or subtracts the product from the concatenated value of HI and LO.

The low half of the addition is loaded into LO and the high half is loaded into HI.

• Divide produces a quotient that is loaded into LO and a remainder that is loaded into HI

The results are accessed by instructions that transfer data between HI/LO and the general

registers.

2.15.3 Jump and Branch Instructions

2.15.3.1 TYPES OF JUMP AND BRANCH INSTRUCTIONS DEFINED BY THE ISA

The architecture defines the following jump and branch instructions:

•PC-relative conditional branch

•PC-region unconditional jump

•Absolute (register) unconditional jump

•A set of procedure calls that record a return link address in a general register

2.15.3.2 BRANCH DELAYS AND THE BRANCH DELAY SLOT

All branches have an architectural delay of one instruction. The instruction immediately following

a branch is said to be in the “branch delay slot”. If a branch or jump instruction is placed in the

branch delay slot, the operation of both instructions is undefined.

By convention, if an exception or interrupt prevents the completion of an instruction in the branch

delay slot, the instruction stream is continued by re-executing the branch instruction. To permit

this, branches must be restartable; procedure calls may not use the register in which the return

link is stored (usually GPR 31) to determine the branch target address.

PIC32 Family Reference Manual

2.15.3.3 BRANCH AND BRANCH LIKELY

There are two versions of conditional branches; they differ in the manner in which they handle

the instruction in the delay slot when the branch is not taken and execution falls through.

• Branch instructions execute the instruction in the delay slot

• Branch likely instructions do not execute the instruction in the delay slot if the branch is not

taken (they are said to nullify the instruction in the delay slot)

Although the Branch Likely instructions are included in this specification, software is strongly

encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a

future revision of the MIPS® architecture.

2.15.4 Miscellaneous Instructions

2.15.4.1 INSTRUCTION SERIALIZATION (SYNC AND SYNCI)

In normal operation, the order in which load and store memory accesses appear to a viewer out-

side the executing processor (for instance, in a multiprocessor system) is not specified by the

architecture.

The SYNC instruction can be used to create a point in the executing instruction stream at which

the relative order of some loads and stores can be determined: loads and stores executed before

the SYNC are completed before loads and stores after the SYNC can start.

The SYNCI instruction synchronizes the processor caches with previous writes or other modifi-

cations to the instruction stream.

2.15.4.2 EXCEPTION INSTRUCTIONS

Exception instructions transfer control to a software exception handler in the kernel. There are

two types of exceptions, conditional and unconditional. Conditional exceptions are generated by

the trap instruction, based on the result of a comparison. Unconditional exceptions are gener-

ated using the syscall and break instructions.

2.15.4.3 CONDITIONAL MOVE INSTRUCTIONS

MIPS32® includes instructions to conditionally move one CPU general register to another, based

on the value in a third general register.

2.15.4.4 NOP INSTRUCTIONS

The NOP instruction is actually encoded as an all-zero instruction. MIPS® processors

special-case this encoding as performing no operation, and optimize execution of the instruction.

In addition, SSNOP instruction, takes up one issue cycle on any processor, including super-scalar

implementations of the architecture.

2.15.5 Coprocessor Instructions

2.15.5.1 WHAT COPROCESSORS DO

Coprocessors are alternate execution units, with register files separate from the CPU. In abstrac-

tion, the MIPS® architecture provides for up to four coprocessor units, numbered 0 to 3. Each

level of the ISA defines a number of these coprocessors. Coprocessor 0 is always used for sys-

tem control and coprocessor 1 and 3 are used for the floating point unit. Coprocessor 2 is

reserved for implementation-specific use.

A coprocessor may have two different register sets:

•Coprocessor general registers

•Coprocessor control registers

Each set contains up to 32 registers. Coprocessor computational instructions may use the

registers in either set.

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.15.5.2 SYSTEM CONTROL COPROCESSOR 0 (CP0)

The system controller for all MIPS® processors is implemented as coprocessor 0 (CP0), the

System Control Coprocessor. It provides the processor control, memory management, and

exception handling functions.

2.15.5.3 COPROCESSOR LOAD AND STORE INSTRUCTIONS

Explicit load and store instructions are not defined for CP0; for CP0 only, the move to and from

coprocessor instructions must be used to write and read the CP0 registers. The loads and stores

for the remaining coprocessors are summarized in 2.15.1.4 “Coprocessor Loads and Stores”.

2.16 CPU INITIALIZATION

Software is required to initialize the following parts of the device after a Reset event.

2.16.1 General Purpose Registers

The CPU register file powers up in an unknown state with the exception of r0 which is always ‘0’.

Initializing the rest of the register file is not required for proper operation in hardware. However,

depending on the software environment, several registers may need to be initialized. Some of

these are:

• sp – Stack pointer

•gp – Global pointer

•fp – Frame pointer

2.16.2 Coprocessor 0 State

Miscellaneous CP0 states need to be initialized prior to leaving the boot code. There are various

exceptions that are blocked by ERL = 1 or EXL = 1, and which are not cleared by Reset. These

can be cleared to avoid taking spurious exceptions when leaving the boot code.

Table 2-12: CPU Initialization

2.16.3 Bus Matrix

The BMX should be initialized before switching to User mode or before executing from DRM. The

values written to the bus matrix are based on the memory layout of the application to be run.

CP0 Register Action

Cause WP (Watch Pending), SW0/1 (Software Interrupts) should be cleared.

Config Typically, the K0, KU and K23 fields should be set to the desired Cache

Coherency Algorithm (CCA) value prior to accessing the corresponding

memory regions.

Count(1) Should be set to a known value if Timer Interrupts are used.

Compare(1) Should be set to a known value if Timer Interrupts are used. The write to

Compare will also clear any pending Timer Interrupts (Thus, Count should

be set before Compare to avoid any unexpected interrupts).

Status Desired state of the device should be set.

Other CP0 state Other registers should be written before they are read. Some registers are

not explicitly writable, and are only updated as a by-product of instruction

execution or a taken exception. Uninitialized bits should be masked off after

reading these registers.

Note 1: When the Count register is equal to the Compare register a timer interrupt is

signaled. There is a mask bit in the interrupt controller to disable passing this

interrupt to the CPU if desired.

PIC32 Family Reference Manual

2.17 EFFECTS OF A RESET

2.17.1 Master Clear Reset

The PIC32 core is not fully initialized by a hardware Reset. Only a minimal subset of the

processor state is cleared. This is enough to bring the core up while running in unmapped and

uncached code space. All other processor state can then be initialized by software. Power-up

Reset brings the device into a known state. A Soft Reset can be forced by asserting the MCLR

pin. This distinction is made for compatibility with other MIPS® processors. In practice, both

resets are handled identically.

2.17.1.1 COPROCESSOR 0 STATE

Much of the hardware initialization occurs in Coprocessor 0, which are described in Tabl e 2-1 3.

Table 2-13: Bits Cleared or Set by Reset

2.17.1.2 BUS STATE MACHINES

All pending bus transactions are aborted and the state machines in the SRAM interface unit are

reset when a Reset or Soft Reset exception is taken.

2.17.2 Fetch Address

Upon Reset/Soft Reset, unless the EJTAGBOOT option is used, the fetch is directed to VA

0xBFC00000 (PA 0x1FC00000). This address is in kseg1, which is unmapped and uncached.

2.17.3 Watchdog Timer Reset

The status of the CPU registers after a Watchdog Timer (WDT) event depends on the operational

mode of the CPU prior to the WDT event.

If the device was not in Sleep a WDT event will force registers to a Reset value.

or Set Value Cleared or Set By

Status BEV Cleared 1Reset or Soft Reset

TS Cleared 0Reset or Soft Reset

SR Set 1Reset or Soft Reset

NMI Cleared 0Reset or Soft Reset

ERL Set 1Reset or Soft Reset

RP Cleared 0Reset or Soft Reset

All Configuration

Registers:

Config

Config1

Config2

Config3

Configuration fields

related to static

inputs

Set Input value Reset or Soft Reset

Config K0 Set 010

(uncached)

Reset or Soft Reset

KU Set 010

(uncached)

Reset or Soft Reset

K23 Set 010

(uncached)

Reset or Soft Reset

Debug DM Cleared 0Reset or Soft Reset(1)

LSNM Cleared 0Reset or Soft Reset

IBUSEP Cleared 0Reset or Soft Reset

IEXI Cleared 0Reset or Soft Reset

SSt Cleared 0Reset or Soft Reset

Note 1: Unless EJTAGBOOT option is used to boot into Debug mode.

Section 2. CPU for Devices with M4K® Core

CPU for Devices

with M4K® Core

2.18 RELATED APPLICATION NOTES

This section lists application notes that are related to this section of the manual. These

application notes may not be written specifically for the PIC32 device family, but the concepts are

pertinent and could be used with modification and possible limitations. The current application

notes related to the PIC32 CPU for Devices with M4K® Core include the following:

Title Application Note #

No related application notes at this time. N/A

Note: Please visit the Microchip web site (www.microchip.com) for additional application

notes and code examples for the PIC32 family of devices.

PIC32 Family Reference Manual

2.19 REVISION HISTORY

Revision A (October 2007)

This is the initial released version of this document.

Revision B (April 2008)

Revised status to Preliminary; Revised Section 2.1 (Key Features); Revised Figure 2-1; Revised

U-0 to r-x.

Revision C (May 2008)

Revise Figure 2-1; Added Section 2.2.3, Core Timer; Change Reserved bits from “Maintain as”

to “Write”.

Revision D (August 2011)

This revision includes the following updates:

The document was updated as follows to reflect the addition of the M14K™ Microprocessor core

to certain variants of the PIC32 device family:

•Sections:

-Updated 2.1.1 “Key Features”

-Updated 2.1.2 “Related MIPS® Documentation”

-Updated 2.2.2 “Introduction to the Programming Model”

-Updated 2.3.1.1 “I Stage – Instruction Fetch”

-Updated 2.10 “Interrupt and Exception Mechanism”

- Added 2.14 “microMIPS™ EXECUTION (M14K™ only)”

- Added 2.15 “MCU™ ASE EXTENSION (M14K™ only)”

•Figures:

-Updated Figure2-1: PIC32 Block Diagram

-Updated Figure2-2: M4K

® and M14K™ Microprocessor Core Block Diagram

•Tables:

- Added Table 2-6: microMIPS™ 16-bit Instruction Register Usage (M14K™ Only)

-Updated Table2-8: CP0 Registers

- Added Table 2-14: Performance Countable Events

-Added Table2-15: Event Description

- Updated Table 2-17: Bits Cleared or Set by Reset

• Registers:

- Added Register 2-1, Register 2-10, Register 2-11, Register 2-13, Register 2-22,

- Updated existing registers to reflect only those bits that are implemented for PIC32

devices with either the M4K® or M14K™ Microprocessor core

•Updates to formatting and minor text updates have been incorporated throughout the

document

Revision E (September 2012)

This revision includes the following updates:

•Document title has been changed

• All references to the M14K™ Microprocessor core were removed throughout the docu-

ment. This content will be available in a separate family reference manual section.

•Updates to formatting and minor text updates have been incorporated throughout the

document

 2007-2012 Microchip Technology Inc. DS61113E-page 2-63

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

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Printed on recycled paper.

ISBN: 978-1-62076-539-5

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

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Memory

Organization

Section 3. Memory Organization

HIGHLIGHTS

This section of the manual contains the following topics:

3.1 Introduction................................................................................................................3-2

3.2 Control Registers....................................................................................................... 3-2

3.3 PIC32MX Memory Layout ....................................................................................... 3-13

3.4 PIC32MX Address Map ........................................................................................... 3-15

3.5 Bus Matrix................................................................................................................ 3-29

3.6 I/O Pin Control ......................................................................................................... 3-33

3.7 Operation in Power-Saving and Debug Modes ....................................................... 3-33

3.8 Code Examples ....................................................................................................... 3-34

3.9 Design Tips.............................................................................................................. 3-35

3.10 Related Application Notes ....................................................................................... 3-36

3.11 Revision History....................................................................................................... 3-37

PIC32MX Family Reference Manual

3.1 INTRODUCTION

The PIC32MX microcontrollers provide 4 GB of unified virtual memory address space. All mem-

ory regions, including program memory, data memory, SFRs and Configuration registers reside

in this address space at their respective unique addresses. The program and data memories can

be optionally partitioned into user and kernel memories. In addition, the data memory can be

made executable, allowing the PIC32MX to execute from data memory.

Key features of PIC32MX memory organization include the following:

•32-bit native data width

• Separate User and Kernel mode address spaces

•Flexible program Flash memory partitioning

•Flexible data RAM partitioning for data and program space

• Separate boot Flash memory for protected code

• Robust bus-exception handling to intercept runaway code

•Simple memory mapping with Fixed Mapping Translation (FMT) unit

•Cacheable and non-cacheable address regions

3.2 CONTROL REGISTERS

This section lists the Special Function Registers (SFRs) used for setting the RAM and Flash

memory partitions for data and code (for both User and Kernel mode).

The following is a list of available SFRs:

•BMXCON: Configuration Register

•BMXxxxBA: Memory Partition Base Address Registers

•BMXDRMSZ: Data RAM Size Register

•BMXPFMSZ: Program Flash Size Register

•BMXBOOTSZ: Boot Flash Size Register

3.2.1 BMXCON Register

This register configures program Flash cacheability for DMA accesses, bus error exceptions,

data RAM wait states and arbitration modes.

3.2.2 BMXxxxBA Registers

These registers identify relative base addresses for kernel, User mode data and User mode

program space in RAM.

3.2.3 BMXDRMSZ Register

This read-only register identifies the size of the Data RAM in bytes.

3.2.4 BMXPFMSZ Register

This read-only register identifies the size of the Program Flash Memory in bytes.

3.2.5 BMXBOOTSZ Register

This read-only register identifies the size of the Boot Program Flash Memory in bytes.

Tabl e 3 -1 pr ov ide s a br i ef s um m ar y o f al l me mory organization-related registers. Corresponding

registers appear after the summary, followed by a detailed description of each register.

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply

to all PIC32MX devices.

Please consult the note at the beginning of the “Memory” chapter in the current

device data sheet to check whether this document supports the device you are

using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

Section 3. Memory Organization

Memory

Organization

Table 3-1: Memory Organization SFR Summary

Address

Offset Name Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

0x2000 BMXCON(1,2,3) 31:24 — — — — —BMXCHEDMA— —

23:16 — — — BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS

15:8 — — — — — — — —

7:0 —BMXWSDRM — — —BMXARB<2:0>

0x2010 BMXDKPBA(1,2,3) 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 BMXDKPBA<15:8>

7:0 BMXDKPBA<7:0>

0x2020 BMXDUDBA(1,2,3) 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 BMXDUDBA<15:8>

7:0 BMXDUDBA<7:0>

0x2030 BMXDUPBA(1,2,3) 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 BMXDUPBA<15:8>

7:0 BMXDUPBA<7:0>

0x2040 BMXDRMSZ 31:24 BMXDRMSZ<31:24>

23:16 BMXDRMSZ<23:16>

15:8 BMXDRMSZ<15:8>

7:0 BMXDRMSZ<7:0>

0x2050 BMXPUPBA(1,2,3) 31:24 — — — — — — — —

23:16 — — — — BMXPUPBA<19:16>

15:8 BMXPUPBA<15:8>

7:0 BMXPUPBA<7:0>

0x2060 BMXPFMSZ 31:24 BMXPFMSZ<31:24>

23:16 BMXPFMSZ<23:16>

15:8 BMXPFMSZ<15:8>

7:0 BMXPFMSZ<7:0>

0x2070 BMXBOOTSZ 31:24 BMXBOOTSZ<31:24>

23:16 BMXBOOTSZ<23:16>

15:8 BMXBOOTSZ<15:8>

7:0 BMXBOOTSZ<7:0>

Legend: — = unimplemented, read as ‘0’. Address offset values are shown in hexadecimal.

Note 1: This register has an associated Clear register at an offset of 0x4 bytes. These registers have the same name with CLR appended to the

end of the register name (e.g., BMXCONCLR). Writing a ‘1’ to any bit position in the Clear register will clear valid bits in the associated

2: This register has an associated Set register at an offset of 0x8 bytes. These registers have the same name with SET appended to the end

of the register name (e.g., BMXCONSET). Writing a ‘1’ to any bit position in the Set register will set valid bits in the associated register.

Reads from the Set register should be ignored.

3: This register has an associated Invert register at an offset of 0xC bytes. These registers have the same name with INV appended to the

end of the register name (e.g., BMXCONINV). Writing a ‘1’ to any bit position in the Invert register will invert valid bits in the associated

PIC32MX Family Reference Manual

r-x r-x r-x r-x r-x R/W-0 r-x r-x

— — — — —BMXCHEDMA— —

bit 31 bit 24

r-x r-x r-x R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — —BMXERRIXIBMXERRICDBMXERRDMABMXERRDSBMXERRIS

bit 23 bit 16

r-x r-x r-x r-x r-x r-x r-x r-x

— — — — — — — —

bit 15 bit 8

r-x R/W-1 r-x r-x r-x R/W-0 R/W-0 R/W-1

—BMXWSDRM— — — BMXARB<2:0>

bit 7 bit 0

Legend:

R=Readable bit W=Writable bit P=Programmable bit r=Reserved bit

U=Unimplemented bit n=Bit Value at POR: (‘0’, ‘1’, x=Unknown)

bit 31-27 Reserved: Write ‘0’; ignore read

bit 26 BMXCHEDMA: BMX PFM Cacheability for DMA Accesses bit

1= Enable program Flash memory (data) cacheability for DMA accesses

(requires cache to have data caching enabled)

0=Disable program Flash memory (data) cacheability for DMA accesses

(hits are still read from the cache, but misses do not update the cache)

bit 25-21 Reserved: Write ‘0’; ignore read

bit 20 BMXERRIXI: Enable Bus Error from IXI bit

1= Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus

0=Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus

bit 19 BMXERRICD: Enable Bus Error from ICD Debug Unit bit

1= Enable bus error exceptions for unmapped address accesses initiated from ICD

0=Disable bus error exceptions for unmapped address accesses initiated from ICD

bit 18 BMXERRDMA: Bus Error from DMA bit

1= Enable bus error exceptions for unmapped address accesses initiated from DMA

0=Disable bus error exceptions for unmapped address accesses initiated from DMA

bit 17 BMXERRDS: Bus Error from CPU Data Access bit (disabled in DEBUG mode)

1= Enable bus error exceptions for unmapped address accesses initiated from CPU data access

0=Disable bus error exceptions for unmapped address accesses initiated from CPU data access

bit 16 BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in DEBUG mode)

1= Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access

0=Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access

Note 1: This register has an associated Clear register (BMXCONCLR) at an offset of 0x4 bytes. Writing a ‘1’ to any

bit position in the Clear register will clear valid bits in the associated register. Reads from the Clear register

should be ignored.

2: This register has an associated Set register (BMXCONSET) at an offset of 0x8 bytes. Writing a ‘1’ to any

bit position in the Set register will set valid bits in the associated register. Reads from the Set register should

be ignored.

3: This register has an associated Invert register (BMXCONINV) at an offset of 0xC bytes. Writing a ‘1’ to any

bit position in the Invert register will invert valid bits in the associated register. Reads from the Invert register

should be ignored.

Section 3. Memory Organization

Memory

Organization

bit 15-7 Reserved: Write ‘0’; ignore read

bit 6 BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit

1=Data RAM accesses from CPU have one wait state for address setup

0=Data RAM accesses from CPU have zero wait states for address setup

bit 5-3 Reserved: Write ‘0’; ignore read

bit 2-0 BMXARB<2:0>: Bus Matrix Arbitration Mode bits

111...011 = Reserved (using these Configuration modes will produce undefined behavior)

010 = Arbitration Mode 2

001 = Arbitration Mode 1 (default)

000 = Arbitration Mode 0

Note 1: This register has an associated Clear register (BMXCONCLR) at an offset of 0x4 bytes. Writing a ‘1’ to any

bit position in the Clear register will clear valid bits in the associated register. Reads from the Clear register

should be ignored.

2: This register has an associated Set register (BMXCONSET) at an offset of 0x8 bytes. Writing a ‘1’ to any

bit position in the Set register will set valid bits in the associated register. Reads from the Set register should

be ignored.

3: This register has an associated Invert register (BMXCONINV) at an offset of 0xC bytes. Writing a ‘1’ to any

bit position in the Invert register will invert valid bits in the associated register. Reads from the Invert register

should be ignored.

PIC32MX Family Reference Manual

r-x r-x r-x r-x r-x r-x r-x r-x

— — — — — — — —

bit 31 bit 24

r-x r-x r-x r-x r-x r-x r-x r-x

— — — — — — — —

bit 23 bit 16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0

BMXDKPBA<15:8>

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

BMXDKPBA<7:0>

bit 7 bit 0

Legend:

R=Readable bit W=Writable bit P=Programmable bit r=Reserved bit

U=Unimplemented bit -n=Bit Value at POR: (‘0’, ‘1’, x=Unknown)

bit 31-16 Reserved: Write ‘0’; ignore read

bit 15-11 BMXDKPBA<15:11>: DRM Kernel Program Base Address bits

When non-zero, this value selects the relative base address for kernel program space in RAM

bit 10-0 BMXDKPBA<10:0>: Read-Only bits

Value is always ‘0’, which forces 2 KB increments

Note 1: This register has an associated Clear register (BMXDKPBACLR) at an offset of 0x4 bytes. Writing a ‘1’ to

any bit position in the Clear register will clear valid bits in the associated register. Reads from the Clear

2: This register has an associated Set register (BMXDKPBASET) at an offset of 0x8 bytes. Writing a ‘1’ to

any bit position in the Set register will set valid bits in the associated register. Reads from the Set register

should be ignored.

3: This register has an associated Invert register (BMXDKPBAINV) at an offset of 0xC bytes. Writing a ‘1’ to

any bit position in the Invert register will invert valid bits in the associated register. Reads from the Invert

4: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal

mode data usage.

5: The value in this register must be less than or equal to BMXDRMSZ.

Section 3. Memory Organization

Memory

Organization

r-x r-x r-x r-x r-x r-x r-x r-x

— — — — — — — —

bit 31 bit 24

r-x r-x r-x r-x r-x r-x r-x r-x

— — — — — — — —

bit 23 bit 16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0

BMXDUDBA<15:8>

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

BMXDUDBA<7:0>

bit 7 bit 0

Legend:

R=Readable bit W=Writable bit P=Programmable bit r=Reserved bit

U=Unimplemented bit -n=Bit Value at POR: (‘0’, ‘1’, x=Unknown)

bit 31-16 Reserved: Write ‘0’; ignore read

bit 15-11 BMXDUDBA<15:11>: DRM User Data Base Address bits

When non-zero, the value selects the relative base address for User mode data space in RAM

Note: If non-zero, the value must be greater than BMXDKPBA.

bit 10-0 BMXDUDBA<10:0>: Read-Only bits

Value is always ‘0’, which forces 2 KB increments

Note 1: This register has an associated Clear register (BMXDUDBACLR) at an offset of 0x4 bytes. Writing a ‘1’ to

any bit position in the Clear register will clear valid bits in the associated register. Reads from the Clear

2: This register has an associated Set register (BMXDUDBASET) at an offset of 0x8 bytes. Writing a ‘1’ to

any bit position in the Set register will set valid bits in the associated register. Reads from the Set register

should be ignored.

3: This register has an associated Invert register (BMXDUDBAINV) at an offset of 0xC bytes. Writing a ‘1’ to

any bit position in the Invert register will invert valid bits in the associated register. Reads from the Invert

4: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal

mode data usage.

5: The value in this register must be less than or equal to BMXDRMSZ.

PIC32MX Family Reference Manual

r-x r-x r-x r-x r-x r-x r-x r-x

— — — — — — — —

bit 31 bit 24

r-x r-x r-x r-x r-x r-x r-x r-x

— — — — — — — —

bit 23 bit 16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0

BMXDUPBA<15:8>

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

BMXDUPBA<7:0>

bit 7 bit 0

Legend:

R=Readable bit W=Writable bit P=Programmable bit r=Reserved bit

U=Unimplemented bit -n=Bit Value at POR: (‘0’, ‘1’, x=Unknown)

bit 31-16 Reserved: Write ‘0’; ignore read

bit 15-11 BMXDUPBA<15:11>: DRM User Program Base Address bits

When non-zero, the value selects the relative base address for User mode program space in RAM

Note: If non-zero, BMXDUPBA must be greater than BMXDUDBA.

bit 10-0 BMXDUPBA<10:0>: Read-Only bits

Value is always ‘0’, which forces 2 KB increments

Note 1: This register has an associated Clear register (BMXDUPBACLR) at an offset of 0x4 bytes. Writing a ‘1’ to

any bit position in the Clear register will clear valid bits in the associated register. Reads from the Clear

2: This register has an associated Set register (BMXDUPBASET) at an offset of 0x8 bytes. Writing a ‘1’ to

any bit position in the Set register will set valid bits in the associated register. Reads from the Set register

should be ignored.

3: This register has an associated Invert register (BMXDUPBAINV) at an offset of 0xC bytes. Writing a ‘1’ to

any bit position in the Invert register will invert valid bits in the associated register. Reads from the Invert

4: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal

mode data usage.

5: The value in this register must be less than or equal to BMXDRMSZ.

Section 3. Memory Organization

Memory

Organization

RRRRRRRR

BMXDRMSZ<31:24>

bit 31 bit 24

RRRRRRRR

BMXDRMSZ<23:16>

bit 23 bit 16

RRRRRRRR

BMXDRMSZ<15:8>

bit 15 bit 8

RRRRRRRR

BMXDRMSZ<7:0>

bit 7 bit 0

Legend:

R=Readable bit W=Writable bit P=Programmable bit r=Reserved bit

U=Unimplemented bit -n=Bit Value at POR: (‘0’, ‘1’, x=Unknown)

bit 31-0 BMXDRMSZ<31:0>: Data RAM Memory (DRM) Size bits

Static value that indicates the size of the Data RAM in bytes:

0x00002000 = device has 8 KB RAM

0x00004000 = device has 16 KB RAM

0x00008000 = device has 32 KB RAM

0x00010000 = device has 64 KB RAM

0x00020000 = device has 128 KB RAM

PIC32MX Family Reference Manual

r-x r-x r-x r-x r-x r-x r-x r-x

— — — — — — — —

bit 31 bit 24

r-x r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0

— — — —BMXPUPBA<19:16>

bit 23 bit 16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0

BMXPUPBA<15:8>

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

BMXPUPBA<7:0>

bit 7 bit 0

Legend:

R=Readable bit W=Writable bit P=Programmable bit r=Reserved bit

U=Unimplemented bit -n=Bit Value at POR: (‘0’, ‘1’, x=Unknown)

bit 31-20 Reserved: Write ‘0’; ignore read

bit 19-11 BMXPUPBA<19:11>: Program Flash (PFM) User Program Base Address bits

bit 10-0 BMXPUPBA<10:0>: Read-Only bits

Value is always ‘0’, which forces 2 KB increments

Note 1: This register has an associated Clear register (BMXPUPBACLR) at an offset of 0x4 bytes. Writing a ‘1’ to

any bit position in the Clear register will clear valid bits in the associated register. Reads from the Clear

2: This register has an associated Set register (BMXPUPPBASET) at an offset of 0x8 bytes. Writing a ‘1’ to

any bit position in the Set register will set valid bits in the associated register. Reads from the Set register

should be ignored.

3: This register has an associated Invert register (BMXPUPBAINV) at an offset of 0xC bytes. Writing a ‘1’ to

any bit position in the Invert register will invert valid bits in the associated register. Reads from the Invert

4: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal

mode program usage.

5: The value in this register must be less than or equal to BMXPFMSZ.

Section 3. Memory Organization

Memory

Organization

RRRRRRRR

BMXPFMSZ<31:24>

bit 31 bit 24

RRRRRRRR

BMXPFMSZ<23:16>

bit 23 bit 16

RRRRRRRR

BMXPFMSZ<15:8>

bit 15 bit 8

RRRRRRRR

BMXPFMSZ<7:0>

bit 7 bit 0

Legend:

R=Readable bit W=Writable bit P=Programmable bit r=Reserved bit

U=Unimplemented bit -n=Bit Value at POR: (‘0’, ‘1’, x=Unknown)

bit 31-0 BMXPFMSZ<31:0>: Program Flash Memory (PFM) Size bits

Static value that indicates the size of the PFM in bytes:

0x00008000 = device has 32 KB Flash

0x00010000 = device has 64 KB Flash

0x00020000 = device has 128 KB Flash

0x00040000 = device has 256 KB Flash

0x00080000 = device has 512 KB Flash

PIC32MX Family Reference Manual

RRRRRRRR

BMXBOOTSZ<31:24>

bit 31 bit 24

RRRRRRRR

BMXBOOTSZ<23:16>

bit 23 bit 16

RRRRRRRR

BMXBOOTSZ<15:8>

bit 15 bit 8

RRRRRRRR

BMXBOOTSZ<7:0>

bit 7 bit 0

Legend:

R=Readable bit W=Writable bit P=Programmable bit r=Reserved bit

U=Unimplemented bit -n=Bit Value at POR: (‘0’, ‘1’, x=Unknown)

bit 31-0 BMXBOOTSZ<31:0>: Boot Flash Memory (BFM) Size bits

Static value that indicates the size of the Boot PFM in bytes:

0x00003000 = device has 12 KB boot Flash

Section 3. Memory Organization

Memory

Organization

3.3 PIC32MX MEMORY LAYOUT

The PIC32MX microcontrollers implement two address spaces: virtual and physical. All hardware

resources, such as program memory, data memory and peripherals, are located at their respec-

tive physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute

instructions. Physical addresses are used by peripherals, such as DMA and Flash controllers,

that access memory independently of the CPU.

Figure 3-1: Virtual to Physical Fixed Memory Mapping

Virtual Memory Map Physical Memory Map

0xFFFFFFFF

0xC0000000

0xBFC00000

0xBF800000

0xAFFFFFFF

0xA0000000

0x9FC00000

0x9D000000

0x8FFFFFFF

0x80000000

0x7F000000

0xBD000000

0x7D000000+

BMXPUPBA

0x0FFFFFFF

0x00000000

0xFFFFFFFF

0xBF000000

+BMXDUBA

0xBD000000

+BMXPUPBA

0x4FFFFFFF

0x40000000

0x1FC00000

0x1F800000

0x1D000000

0x0FFFFFFF

BMXDUDBA

0x00000000

Internal Boot Flash

Internal Peripherals

Internal Program Flash

Reserved

Internal RAM

Internal Boot Flash

Internal Program Flash

Reserved

Internal RAM

(User Partition)

Program Flash

(User Partition)

Reserved

Internal RAM

(User Partition)

Internal Flash

(User Partition)

Reserved

Internal Boot Flash

Internal Peripherals

Internal Program Flash

Reserved

Internal RAM

KSEG2/KSEG3KSEG1KSEG0USEG/KUSEG

PIC32MX Family Reference Manual

The entire 4 GB virtual address space is divided into two primary regions: user and kernel space.

The lower 2 GB of space from the User mode segment is called USEG/KUSEG. A User mode

application must reside and execute in the USEG segment. The USEG segment is also available

to all Kernel mode applications, which is why it is also named KUSEG – to indicate that it is avail-

able to both User and Kernel modes. When operating in User mode, the bus matrix must be con-

figured to make part of the Flash and data memory available in the USEG/KUSEG segment. See

3.4 “PIC32MX Address Map” for more details.

Figure 3-2: User/Kernel Address Segments

The upper 2 GB of virtual address space forms the kernel only space. The kernel space is divided

into four segments of 512 MB each: KSEG0, KSEG1, KSEG2 and KSEG3. Only Kernel mode

applications can access kernel space memory. The kernel space includes all peripheral registers.

Consequently, only Kernel mode applications can monitor and manipulate peripherals. Only

KSEG0 and KSEG1 segments point to real memory resources. Segment KSEG2 is available to

the EJTAG probe debugger, as explained in the MIPS documentation (refer to the EJTAG

specification). The PIC32MX only uses KSEG0 and KSEG1 segments. The Boot Flash Memory

(BFM), Program Flash Memory (PFM), Data RAM Memory (DRM) and peripheral SFRs are

accessible from either KSEG0 or KSEG1.

The Fixed Mapping Translation (FMT) unit translates the memory segments into corresponding

physical address regions. Figure 3-1 illustrates the fixed mapping scheme implemented by the

PIC32MX core between the virtual and physical address space. A virtual memory segment may

also be cached, provided the cache module is available on the device. Please note that the

KSEG1 memory segment is not cacheable, while KSEG0 and USEG/KUSEG are cacheable.

The mapping of the memory segments depend on the CPU error level (set by the ERL bit in the

CPU Status register). Error Level is set (ERL = 1) by the CPU on a Reset, Soft Reset or NMI. In

this mode, the processor runs in Kernel mode and USEG/KUSEG are treated as unmapped and

uncached regions, and the mapping in Figure 3-1 does not apply. This mode is provided for

compatibility with other MIPS processor cores that use a TLB-based MMU. The C start-up code

clears the ERL bit to zero, so that when application software starts up, it sees the proper virtual

to physical memory mapping as illustrated in Figure 3-1.

Segments KSEG0 and KSEG1 are always translated to physical address 0x0. This translation

arrangement allows the CPU to access identical physical addresses from two separate virtual

addresses: one from KSEG0 and the other from KSEG1. As a result, the application can choose

to execute the same piece of code as either cached or uncached. See Section 4. “Prefetch

Cache Module” (DS61119) for more details. The on-chip peripherals are visible through KSEG1

segment only (uncached access).

Kernel

Segments

(KSEG0,1,2,3)

User/Kernel

Segment

(USEG/KUSEG)

0xFFFFFFFF

0x80000000

0x7FFFFFFF

0x00000000

Section 3. Memory Organization

Memory

Organization

3.4 PIC32MX ADDRESS MAP

The Program Flash Memory is divided into kernel and user partitions. The kernel program Flash

space starts at physical address 0x1D000000, whereas the user program Flash space starts at

physical address 0xBD000000 + BMXPUDBA register value. Similarly, the internal RAM is also

divided into kernel and user partitions. The kernel RAM space starts at physical address

0x00000000, whereas the user RAM space starts at physical address 0xBF000000 +

BMXDUDBA register value. By default, the full Flash memory and RAM are mapped to Kernel

mode application only.

Please note that the BMXxxxBA register settings must match the memory model of the target

software application. If the linked code does not match the register values, the program may not

run and may generate bus error exceptions on start-up.

3.4.1 Virtual to Physical Address Calculation (and Vice-Versa)

To tra ns l at e the k ern el a d dr e ss ( KSE G0 o r KSEG1) to a physical address, perform a “Bitwise

AND” operation of the virtual address with 0x1FFFFFFF:

•Physical Address = Virtual Address and 0x1FFFFFFF

For physical address to KSEG0 virtual address translation, perform a “Bitwise OR” operation of

the physical address with 0x80000000:

•KSEG0 Virtual Address = Physical Address | 0x80000000

For physical address to KSEG1 virtual address translation, perform a “Bitwise OR” operation of

the physical address with 0xA0000000:

•KSEG1 Virtual Address = Physical Address | 0xA0000000

To translate from KSEG0 to KSEG1 virtual address, perform a “Bitwise OR” operation of the

KSEG0 virtual address with 0x20000000:

•KSEG1 Virtual Address = KSEG0 Virtual Address | 0x20000000

Note: The Program Flash Memory is not writable through its address map. A write to the

PFM address range causes a bus error exception.

PIC32MX Family Reference Manual

Table 3-2: PIC32MX Address Map

Memory Type

Virtual Addresses Physical Addresses Size in Bytes

Begin Address End Address Begin Address End Address Calculation

Kernal Address Space

Boot Flash 0xBFC00000 0xBFC02FFF 0x1FC00000 0x1FC02FFF 12 KB

Peripheral 0xBF800000 0xBF8FFFFF 0x1F800000 0x1F8FFFFF 4 KB

KSEG1

Program

Flash(1,3)

0xBD000000 0xBD000000 +

BMXPUPBA - 1

0x1D000000 0x1D00000 +

BMXPUPBA - 1

BMXPUPBA

KSEG1

Program

RAM(6)

0xA0000000 +

BMXDKPBA

0xA0000000 +

BMXDUDBA - 1

0x00000000 +

BMXDKPBA

0x00000000 +

BMXDUDBA - 1

BMXDUDBA -

BMXDKPBA

KSEG1 Data

RAM(6)

0xA0000000 0xA0000000 +

BMXDKPBA - 1

0x00000000 0x00000000 +

BMXDKPBA - 1

BMXPUPBA

KSEG0

Program

Flash(2,5)

0x9D000000 0x9D000000 +

BMXPUPBA - 1

0x1D000000 0x1D000000 +

BMXPUPBA - 1

BMXPUPBA

KSEG0 Pro-

gram RAM(6)

0x80000000 +

BMXDKPBA

0x80000000 +

BMXDUDBA - 1

0x00000000 +

BMXDKPBA

0x00000000 +

BMXDUDBA - 1

BMXDUDBA -

BMXDKPBA

KSEG0 Data

RAM(6)

0x80000000 0x80000000 +

BMXDKPBA - 1

0x00000000 0x00000000 +

BMXDKPBA - 1

BMXDKPBA

Memory Type

Virtual Addresses Physical Addresses Size in Bytes

Begin Address End Address Begin Address End Address Calculation

User Address Space

USEG/KSEG

Program

RAM(6)

0x7F000000 +

BMXDUPBA

0x7F000000 +

BMXDRMSZ -1(3)

0xBF000000 +

BMXDUPBA

0xBF000000 +

BMXDRMSZ(3) - 1

BMXDRMSZ(3) -

BMXDUPBA

USEG/KSEG

Data RAM(6)

0x7F000000 +

BMXDUDBA

0x7F000000 +

BMXDUPBA - 1

0xBF000000 +

BMXDUDBA

0xBF000000 +

BMXDUPBA - 1

BMXDUPBA -

BMXDUDBA

USEG/KSEG

Program

Flash(6)

0x7D000000 +

BMXPUPBA

0x7D000000 +

BMXPFMSZ(4) - 1

0xBD000000 +

BMXPUPBA

0xBF000000 +

BMXPFMSZ(4) - 1

BMXPFMSZ(4) -

BMXPUPBA

Note 1: Program Flash virtual addresses in the non-cacheable range (KSEG1).

2: Program Flash virtual addresses in the cacheable and prefetchable range (KSEG0).

3: The RAM size varies between PIC32MX device variants.

4: The Flash size varies between PIC32MX device variants.

5: When the BMXPUPBA register is equal to ‘0’, all program Flash is allocated to Kernal mode program

usage. This is the default state at Reset.

6: When the BMXDUDBA, BMXDUPBA, or BMXDKPBA register is equal to ‘0’, all RAM is allocated to Kernal

mode data usage. This is the default state at Reset.

Section 3. Memory Organization

Memory

Organization

3.4.2 Program Flash Memory Partitioning

The Program Flash Memory can be partitioned for User and Kernel mode programs as illustrated

in Figure 3-1.

At Reset, the User mode partition does not exist (BMXPUPBA is initialized to ‘0’). The entire

program Flash memory is mapped to Kernel mode program space starting at virtual address

KSEG1:0xBD000000 (or KSEG0:0x9D000000). To set up a partition for the User mode program,

initialize BMXPUPBA as follows:

•BMXPUPBA = BMXPFMSZ – USER_FLASH_PGM_SZ

The USER_FLASH_PGM_SZ is the partition size of the User mode program. BMXPFMSZ is the

bus matrix register that holds the total size of program Flash memory.

Example:

•Assuming the PIC32MX device has 512Kbytes of Flash memory, the BMXPFMSZ will

contain 0x00080000.

• To create a user Flash program partition of 20 Kbytes (0x5000):

• BMXPUPBA = 0x80000 – 0x5000 = 0x7B000

The size of the user Flash will be 20K and the size left for the kernel Flash will be

512 Kbytes – 20 Kbytes = 492 Kbytes.

The user Flash partition will extend from 0x7D07B000 to 0x7D07FFFF (virtual addresses).

The Kernel mode partition always starts from KSEG1:0xBD000000 or KSEG0:0x9D000000. In

the above example, the kernel partition will extend from 0xBD000000 to 0xBD07AFFF

(492 Kbytes in size).

PIC32MX Family Reference Manual

Figure 3-3: Flash Partitioning

3.4.3 RAM Partitioning

The RAM memory can be divided into four partitions. These are:

•Kernel Data

•Kernel Program

• User Data

•User Program

In order to execute from data RAM, a kernel or user program partition must be defined. At

Power-on Reset (POR), the entire data RAM is assigned to the kernel data partition. This partition

always starts from the base of the data RAM. See Figure 3-4 for details.

Note 1: To pro per ly par tit io n t he R AM, you h ave to program all of the following registers:

BMXDKPBA, BMXDUDBA and BMXDUPBA.

2: The size of the available RAM is given by the BMXDRMSZ register.

Note 1: Kernel Flash Size = BMXPUPBA.

2: User Flash Size = BMXPFMSZ-BMXPUPBA.

3: If BMXPUPBA is ‘0’, then:

K Flash Size = BMXPFMSZ (i.e., all the Flash)

User Flash Size = 0

Physical Address

0x1D000000

Virtual Address

KSEG0: 0x9D000000

+BMXPUPBA

KSEG1: 0xBD000000

KSEG0: 0x9D000000

KSEG1: 0xBD000000

0x7D000000+

BMXPUPBA

0x00000000

0xBD000000+

BMXPUPBA

Kernel Flash Size(1) User Flash Size(2)

Flash Partition for

Kernel Program

(KSEG 0/1)

Optional

Flash Partition for

User Program

(USEG/KUSEG)

Section 3. Memory Organization

Memory

Organization

Figure 3-4: RAM Partitioning

Note 1: Kernel Data RAM Size = BMXDKPBA.

2: Kernel Program RAM Size = BMXDUDBA - BMXDKPBA.

3: User Data RAM Size = BMXDUPBA - BMXDUDBA.

4: User Program RAM Size = BMXDRMSZ - BMXDUPBA.

5: If BMXDKPBA, BMXDUDBA or BMXDUPBA is ‘0’, then:

Kernel Data RAM Size = BMXDRMSZ (i.e., all RAM)

Kernel Program RAM Size = 0

User Data RAM Size = 0

User Program RAM Size = 0

Physical Address

0x00000000

Virtual Address

KSEG0: 0x80000000

+BMXDUDBA

KSEG1: 0xA0000000

KSEG0: 0x80000000

KSEG1: 0xA0000000

0x7F000000

+BMXDUPBA

0x00000000

0xBF000000

+BMXDUPBA

Kernel Program User Program

Optional

Kernel Program Partition

KSEG 0/1

Kernel Data Partition

KSEG 0/1

+BMXDKPBA

KSEG0: 0x80000000

KSEG1: 0xA0000000

0x7F000000

+BMXDUDBA

0x00000000

0xBF000000

+BMXDKPBA

+BMXDUDBA

Kernel Data User Data

Optional

User Program RAM Partition

(USEG/KUSEG)

Optional

User RAM Partition

(USEG/KUSEG)

RAM Size(2) RAM Size(1) RAM Size(4) RAM Size(3)

PIC32MX Family Reference Manual

3.4.3.1 Kernel Data RAM Partition

The kernel data RAM partition is located at virtual address KSEG0:0x80000000,

KSEG1:0xA0000000. It is always active and cannot be disabled.

Please note that if any of the BMXDKPBA, BMXDUDBA or BMXDUPBA register is ‘0’, then the

whole RAM is assigned to kernel data RAM (i.e., the size of the kernel data RAM partition is given

by the BMXDRMSZ register value; see Figure 3-5). Otherwise, the size of the kernel data RAM

partition is given by the value of the BMXDKPBA register (see Figure 3-6).

The kernel data RAM partition exists on Reset and takes up all the available RAM, as the

BMXDKPBA, BMXDUDBA and BMXDUPBA registers default to zero at any Reset.

Figure 3-5: RAM Partitioning When BMXDKPBA, BMXDUDBA or BMXDUPBA = 0

Note: Kernel Data RAM Size = BMXDRMSZ.

Physical Address

Virtual Address

Kernel Data RAM Partition

KSEG0/1

KSEG0: 0x80000000

KSEG1: 0xA0000000

BMXDRMSZ

Kernel Data RAM Size

Section 3. Memory Organization

Memory

Organization

Figure 3-6: Kernel Data RAM Partitioning

Note 1: Kernel Data RAM Size = BMXDKPBA.

2: None of the registers BMXDKPBA, BMXDUDBA or BMXDUPBA = 0.

Physical Address

Virtual Address

BMXDRMSZ

Other Data RAM Partitions

Kernel Data RAM Partition

KSEG0/KSEG1

Kernel Data RAM Size(1)

KSEG0: 0x80000000

KSEG1: 0xA0000000

+BMXDKPBA

KSEG0: 0x80000000

KSEG1: 0xA0000000

PIC32MX Family Reference Manual

3.4.3.2 Kernel Program RAM Partition

The kernel program RAM partition is required if code needs to be executed from data RAM in

Kernel mode.

This partition starts at KSEG0:0x80000000 + BMXDKPBA (KSEG1:0xA0000000 +

BMXDKPBA), and its size is given by BMXDUDBA - BMXDKPBA. See Figure 3-7.

The kernel program RAM partition does not exist on Reset, as the BMXDKPBA and BMXDUDBA

registers default to zero at Reset.

Figure 3-7: Kernel Program RAM Partitioning

Note 1: Kernel Program RAM Size = BMXDUDBA - BMXDKPBA.

2: None of BMXDKPBA, BMXDUDBA or BMXDUPBA = 0.

Physical Address

Virtual Address

BMXDRMSZ

User Data RAM Partitions

Kernel Program RAM Partition

KSEG 0/1

Kernel Data RAM Partition

KSEG0/KSEG1

Kernel Program RAM Size(1) Kernel Data RAM Size

KSEG0: 0x80000000

KSEG1: 0xA0000000

+BMXDKPBA

KSEG0: 0x80000000

KSEG1: 0xA0000000

+BMXDUDBA

KSEG1: 0xA0000000

KSEG0: 0x80000000

Section 3. Memory Organization

Memory

Organization

3.4.3.3 User Data RAM Partition

For User mode applications, a User mode data partition in RAM is required. This partition starts

at address 0x7F000000 + BMXDUDBA, and its size is given by BMXDUPBA - BMXDUDBA (see

Figure 3-8).

The user data RAM partition does not exist on Reset, as the BMXDUDBA and BMXDUPBA

registers default to zero at Reset.

Figure 3-8: User Data RAM Partitioning

Note 1: User Data RAM Size = BMXDUPBA - BMXDUDBA.

2: None of the registers BMXDKPBA, BMXDUDBA or BMXDUPBA = 0.

Physical Address

Virtual Address

BMXDRMSZ

User Program RAM Partitions

User Data RAM Partitions

User Data RAM Size(1)

0x7F000000

+BMXDUDBA

0x7F000000

+BMXDUPBA

PIC32MX Family Reference Manual

3.4.3.4 User Program RAM Partition

The user program partition in data RAM is required if code needs to be executed from data RAM

in User mode. This partition starts at address 0x7F000000 + BMXDUPBA, and its size is given

by BMXDRMSZ – BMXDUPBA. See Figure 3-9.

The User Program RAM partition does not exist on Reset, as the BMXDUPBA register defaults

to zero at Reset.

Figure 3-9: User Program RAM Partitioning

Note 1: User Program RAM Size = BMXDRMSZ - BMXDUPBA.

2: None of the registers BMXDKPBA, BMXDUDBA or BMXDUPBA = 0.

Physical Address

Virtual Address

BMXDRMSZ

User Program RAM Partition

User Data RAM Partition

User Program RAM Size(1)

0x7F000000

+BMXDUDBA

0x7F000000

+BMXDUPBA

Section 3. Memory Organization

Memory

Organization

3.4.3.5 RAM Partitioning Examples

This section provides the following practical examples of RAM partitioning:

•RAM Partitioned as Kernel Data

•RAM Partitioned as Kernel Data and Kernel Program

•RAM Partitioned as Kernel Data and User Data

•RAM Partitioned as Kernel Data, Kernel Program and User Data

•RAM Partitioned as Kernel Data, Kernel Program, User Data and User Program

Example 1. RAM Partitioned as Kernel Data

The entire RAM is partitioned as kernel data RAM after a Reset. No other programming is

required. Setting the BMXDKPBA, BMXDUDBA or BMXDUPBA register to ‘0’ will partition the

entire RAM space to a kernel data partition (see Figure 3-5).

Example 2. RAM Partitioned as Kernel Data and Kernel Program

For this example, assume that the available RAM on the PIC32MX device is 32 KB, of which

8KB kernel data RAM and 24KB of kernel program RAM are needed. In this example, the user

data RAM and user program RAM will have their sizes set to ‘0’.

Please note that a kernel data RAM partition is always required. See Figure 3-10 for details.

The values of the registers are as follows:

•BMXDRMSZ = 0x00008000 (read-only value)

•BMXDKPBA = 0x00002000 (i.e., 8KB kernel data)

•BMXDUDBA = 0x00008000 (i.e., 0x6000 kernel program)

• BMXDUPBA = 0x00008000 (i.e., user data size = 0, and user program size = 0)

Figure 3-10: RAM Partitioning for 8 KB Kernel Data and 16 KB Kernel Program

BMXDKPBA = 0x2000

BMXDUDBA = 0x8000

BMXDUPBA = 0x8000

Note: Only KSEG0 addresses are shown. For KSEG1 addresses, start at 0xA000000.

Physical Address

Virtual Address

BMXDRMSZ

Kernel Data RAM Partition

Kernel Program RAM Partition

Kernel Program RAM Size

= 0x80000000

+BMXDKPBA

KSEG0: 0x80008000

+BMXDUDBA

Kernel Data RAM Size

= 0x00008000

KSEG 0/1

24 KB

KSEG 0/1

8 KB

= 0x80000000

KSEG0: 0x80002000

KSEG0: 0x80000000

PIC32MX Family Reference Manual

Example 3. RAM Partitioned as Kernel Data and User Data

For this example, assume that the available RAM on the PIC32MX device is 32 KB, of which

16 KB of kernel data RAM and 16 KB of user data RAM are needed. In this example, the kernel

program RAM and user program RAM will have their sizes set to ‘0’. See Figure 3-11 for details.

The values of the registers are as follows:

•BMXDRMSZ = 0x00008000 (read-only value)

•BMXDKPBA = 0x00004000 (i.e., 16KB kernel data)

•BMXDUDBA = 0x00004000 (i.e., 0 kernel program)

• BMXDUPBA = 0x00008000 (i.e., user data size = 16 KB, and user program size = 0)

Figure 3-11: RAM Partitioning for 16 KB Kernel Data and 16 KB User Data

BMXDKPBA = 0x4000

BMXDUDBA = 0x4000

BMXDUPBA = 0x8000

Note: Only KSEG0 addresses are shown. For KSEG1 addresses, start at 0xA0000000.

Physical Address

Virtual Address

KSEG0: 0x80004000

= 0x80000000

+BMXDKPBA

KSEG0: 0x80000000

0x7F008000

= 0x7F000000

+BMXDUPBA

0x00000000

Kernel Data RAM Size User Data RAM Size

User Data RAM

16 KB

Kernel Data RAM

16 KB

0x7F004000

= 0x7F000000

+BMXDUDBA

Section 3. Memory Organization

Memory

Organization

Example 4. RAM Partitioned as Kernel Data, Kernel Program and User Data

For this example, assume that the available RAM on the PIC32MX device is 32 KB, and 4 KB of

kernel data RAM, 6 KB of kernel program and 22 KB of user data RAM are needed. In this

example, the user program RAM will have its size set to ‘0’. See Figure 3-12 for details.

The values of the registers are as follows:

•BMXDRMSZ = 0x00008000 (read-only value)

•BMXDKPBA = 0x00001000 (i.e., 4KB kernel data)

•BMXDUDBA = 0x00002800 (i.e., 6KB kernel program)

• BMXDUPBA = 0x00008000 (i.e., user data size = 22 KB, and user program size = 0)

Figure 3-12: RAM Partitioning for 4 KB K-Data, 6 KB K-Program and 22 KB U-Data

BMXDKPBA = 0x1000

BMXDUDBA = 0x2800

BMXDUPBA = 0x8000

Note: Only KSEG0 addresses are shown. For KSEG1 addresses, start at 0xA0000000.

Physical Address

Virtual Address

KSEG0: 0x80002800

= 0x80000000

+BMXDUDBA

KSEG0: 0x80000000

0x7F008000

= 0x7F000000

+BMXDUPBA

0x00000000

Kernel Data User Data RAM Size

User Data RAM

22 KB

Kernel Program RAM

6 KB

0x7F002800

= 0x7F000000

+BMXDUDBA

Kernel Data RAM

4 KB

Kernel Program

RAM Size RAM Size

KSEG0: 0x80001000

= 0x80000000

+BMXDKPBA

PIC32MX Family Reference Manual

Example 5. RAM Partitioned as Kernel Data, Kernel Program, User Data and User Program

For this example, assume that the available RAM on the PIC32MX device is 32 KB, and 6 KB of

kernel data RAM, 5 KB of kernel program RAM, 12 KB of user data RAM and 9 KB of user

program RAM are needed. See Figure 3-13 for details.

The values of the registers are as follows:

•BMXDRMSZ = 0x00008000 (read-only value)

•BMXDKPBA = 0x00001800 (i.e., 6KB kernel data)

•BMXDUDBA = 0x00002C00 (i.e., 5KB kernel program)

•BMXDUPBA = 0x00005C00 (i.e., user data size = 12 KB, and user program size = 9 KB)

Figure 3-13: RAM Partitioning for 6 KB K-Data, 5 KB K-Program, 12 KB U-Data and

9KB U-Program

BMXDKPBA = 0x1800

BMXDUDBA = 0x2c00

BMXDUPBA = 0x5c00

Note: Only KSEG0 addresses are shown. For KSEG1 addresses, start at 0xA0000000.

Physical Address

Virtual Address

KSEG0: 0x80002C00

= 0x80000000

+BMXDUDBA

KSEG0: 0x80000000

0x7F005C00

= 0x7F000000

+BMXDUPBA

0x00000000

Kernel Data User Data

User Program RAM

9 KB

Kernel Program RAM

5 KB

0x7F002C00

= 0x7F000000

+BMXDUDBA

Kernel Data RAM

6 KB

Kernel Program

RAM Size RAM Size

KSEG0: 0x80001800

= 0x80000000

+BMXDKPBA

User Data RAM

12 KB

RAM Size

User Program

RAM Size

0x7F008000

= 0x7F000000

+BMXDRMSZ

Section 3. Memory Organization

Memory

Organization

3.5 BUS MATRIX

The processor supports two modes of operation, Kernel mode and User mode. The Bus Matrix

controls the allocation of memory for each of these modes. It also controls the type of access,

program or data, for a given region of address space.

The Bus Matrix connects master devices, generically called initiators, to slave devices, generi-

cally called targets. The PIC32MX product family can have up to five initiators and three targets

(e.g., Flash, RAM, etc.) on the main bus structure.

Of the five possible initiators, the CPU Instruction Bus (CPU IS), CPU Data Bus (CPU DS),

In-Circuit Debug (ICD) and DMA Controller (DMA) are the default set of initiators and are always

present. The PIC32MX also includes an Initiator Expansion Interface (IXI) to support additional

initiators for future expansion.

The Bus Matrix decodes a general range of addresses that map to a target. The target (memory

or peripherals) may provide additional addresses depending on its functionality.

Tabl e 3 -3 lis ts t he ta rge ts w hich th e ini tia tor s can acc es s.

Table 3-3: Initiator Access Map

Figure 3-14: Bus Matrix Initiators and Targets

Initiator

Target

Flash RAM Peripheral Bus

CPU IS YYN

CPU DS YYY

DMA YYY

IXI YYN

ICD YYY

CPU IS CPU DS DMA Initiator

Expansion Debug

Module

PFM

DRM

Peripherals

Initiators

Tar gets

Program

Memory

Data RAM

Memory

Peripheral

(PBM)

Flash Bus

PIC32MX Family Reference Manual

3.5.1 Initiator Arbitration Modes

Since there can be more than one initiator attempting to access the same target, an arbitration

scheme must be used to control access to the target. The arbitration modes assign priority levels

to all the initiators. The initiator with the higher priority level will always win target access over a

lower priority initiator.

3.5.1.1 Arbitration Mode 0

The fixed priority scheme in Arbitration Mode 0 is illustrated in Figure 3-15. The CPU data and

instruction access are given higher priority than DMA access. This mode can starve the DMA, so

chose this mode when DMA is not being used.

As illustrated in Figure 3-15, each initiator is assigned a fixed priority level. Programming the register

field BMXARB (BMXCON<2:0>) to ‘0’ selects Mode 0 operation.

Figure 3-15: Priority Assignment in Arbitration Mode 0

ICD/Debug

CPU Data

CPU

Instruction

Access

DMA

Initiator

Expansion

Higher Priority

Access

Section 3. Memory Organization

Memory

Organization

3.5.1.2 Arbitration Mode 1

Arbitration Mode 1 is a fixed priority scheme like Mode 0; however, the CPU IS is always the

lowest priority. Figure 3-16 illustrates the priority scheme in Mode 1. Mode 1 arbitration is the

default mode.

Programming the register field BMXARB (BMXCON<2:0>) to ‘1’ selects Mode 1 operation.

Figure 3-16: Priority Assignment in Arbitration Mode 1

ICD/Debug

CPU Data

DMA

Initiator

CPU

Instruction

Higher Priority

Access

Expansion

Access

PIC32MX Family Reference Manual

3.5.1.3 Arbitration Mode 2

Mode 2 arbitration supports rotating priority assignments to all initiators. Instead of a fixed prior-

ity assignment, each initiator is assigned the highest priority in a rotating fashion. In this mode,

the rotating priority is applied with the following exceptions:

1. CPU data is always selected over CPU instruction.

2. ICD is always the highest priority.

3. When the CPU is processing an exception (EXL = 1) or an error (ERL = 1), the arbiter

temporarily reverts to Mode 0.

Figure 3-17: Priority Assignments in Arbitration Mode 2

Note that priority sequence 2 is not selected in the rotating priority scheme if there is a pending

CPU data access. In this case, once the data access is complete, sequence 2 is selected.

Programming the register field BMXARB (BMXCON<2:0>) to ‘2’ selects Mode 2 operation.

3.5.2 Bus Error Exceptions

The Bus Matrix generates a bus error exception on:

• Any attempt to access unimplemented memory

• Any attempt to access an illegal target

•Any attempt to write to program Flash memory

Bus Error Exceptions may be temporarily disabled by clearing the BMXERRxxx bits in the

BMXCON register, which is not recommended.

The Bus Matrix disables bus error exceptions for accesses from CPU IS and CPU DS while in

DEBUG mode.

3.5.3 Break Exact Breakpoint Support

The PIC32MX supports break exact breakpoints by inserting one Wait state to data RAM access.

This method allows the CPU to stop execution just before the breakpoint address instruction.

This is useful in case of breakpointed store instructions. When the Wait state is not used, the

break will still occur at the store instruction, however, the DRM location is updated with the store

value. If the Wait state is enabled the DRM is not updated with the store value.

Priority

Sequence 1

Priority

Sequence 2

Priority

Sequence 3

Priority

Sequence 4

ICD/Debug

CPU Data

Access

CPU

Instruction

Access

DMA

Initiator

Expansion

ICD/Debug ICD/Debug ICD/Debug

CPU

Instruction

Access

CPU

Instruction

Access

CPU

Instruction

Access

CPU Data

Access

CPU Data

Access

DMA

Initiator

Expansion

Initiator

Expansion

Initiator

Expansion

CPU Data

Access

Rotating Priority Sequence

Higher Priority

Section 3. Memory Organization

Memory

Organization

3.6 I/O PIN CONTROL

There are no pins associated with this module.

3.7 OPERATION IN POWER-SAVING AND DEBUG MODES

3.7.1 Memory Operation on Power-up or Brown-out Reset (BOR):

•The contents of data RAM are undefined

•The BMXxxxBA registers are reset to ‘0’

•CPU is switched to Kernel mode

3.7.2 Memory Operation on Reset:

• The data RAM contents are retained. If the device is code-protected, the RAM contents are

cleared

•The BMX base address registers (BMXxxxBA) are set to ‘0’

•CPU is switched to Kernel mode

3.7.3 Memory Operation on Wake-up from Device Sleep or Idle Mode:

• The RAM contents are retained

•The BMX base address register (BMXxxxBA) contents are not changed

•CPU mode is unchanged

PIC32MX Family Reference Manual

3.8 CODE EXAMPLES

Example 3-1: Create a User Mode Partition of 12K in Program Flash

Example 3-2: Create a Kernel Mode Data RAM Partition of 16K; Rest of RAM for

Kernel Program

Example 3-3 can be used to create the following partitions in RAM:

•Kernel mode data = 12K

•Kernel mode program = 6K

•User mode data = 8K

•User mode program = 6K

Example 3-3: Create RAM Partitions

BMXPUPBA = BMXPFMSZ - (12*1024); // User Mode Flash 12K,

// Kernel Mode Flash 500K (512K-12K)

BMXDKPBA = 16*1024;

BMXDUDBA = BMXDRMSZ;

BMXDUPBA = BMXDRMSZ;

BMXDKPBA = 12*1024; // Kernel Data Partition of 12K.

// Start offset of Kernel Program Partition

BMXDUDBA = BMXDKPBA + (6*1024); // Kernel Program Partition of 6K

// Start offset of User Data Partition

BMXDUPBA = BMXDUDBA + (8*1024); // User Data Partition of 8K

// Start offset of User Program Partition.

// This partition will go up to the size of

// RAM (32K). So the partition size will be

// 6K (32K - 8K - 6K - 12K)

Section 3. Memory Organization

Memory

Organization

3.9 DESIGN TIPS

Question 1: At Reset, in which mode is the CPU running?

Answer: The CPU starts in Kernel mode. The entire RAM is mapped to kernel data

segments in KSEG0 and KSEG1. Flash memory is mapped to kernel program

segments in KSEG0 and KSEG1. Also ERL = 1, which should be reset to zero

(normally in the C start-up code).

Question 2: Do I need to initialize the BMX registers?

Answer: Generally, no. You can leave the BMX registers at their default values, which

allows maximum RAM and Flash memories for Kernel mode applications. If you

want to run code from RAM or set up User mode partitions, you will need to

configure the BMX registers.

Question 3: What is the CPU Reset vector address?

Answer: The CPU Reset address is 0xBFC00000.

Question 4: What is a Bus-Error Exception?

Answer: Bus-error exceptions are generated when the CPU tries to access

unimplemented addresses. Also, when the CPU tries to execute a program from

RAM without defining a RAM program partition, a bus-error exception is

generated.

PIC32MX Family Reference Manual

3.10 RELATED APPLICATION NOTES

This section lists application notes that are related to this section of the manual. These applica-

tion notes may not be written specifically for the PIC32MX device family, but the concepts are

pertinent and could be used with modification and possible limitations. The current application

notes related to the Memory Organization of the PIC32MX family include the following:

Title Application Note #

No related application notes at this time. N/A

Note: Please visit the Microchip web site (www.microchip.com) for additional application

notes and code examples for the PIC32MX family of devices.

Section 3. Memory Organization

Memory

Organization

3.11 REVISION HISTORY

Revision A (August 2007)

This is the initial released version of this document.

Revision B (October 2007)

Updated document to remove Confidential status.

Revision C (April 2008)

Revised status to Preliminary; Revised U-0 to r-x.

Revision D (June 2008)

Change Reserved bits from “Maintain as” to “Write”.

Revision E (July 2009)

This revision includes the following updates:

•Minor updates to the text and formatting have been incorporated throughout the document

• Added Notes 1, 2 and 3, which describe the Clear, Set and Invert registers to the following:

-Table3-1: Memory Organization SFR Summary

-Register3-1: BMXCON: Bus Matrix Configuration Register

-Register3-2: BMXDKPBA: Data RAM Kernel Program Base Address Register

-Register3-3: BMXDUDBA: Data RAM User Data Base Address Register

-Register3-4: BMXDUPBA: Data RAM User Program Base Address Register

-Register3-6: BMXPUPBA: Program Flash (PFM) User Program Base Address Register

•Removed all Clear, Set and Invert register descriptions

•Added additional bit value definition (0x0001000) to BMXDRMSZ: Data RAM Size Register

(see Register 3-5)

Revision F (July 2010)

This revision includes the following updates:

•Minor updates to the text and formatting have been incorporated throughout the document

•Added Notes 4 and 5 to the following registers:

- BMXDKPBA: Data RAM Kernel Program Base Address Register (see Register 3-2)

- BMXDUDBA: Data RAM User Data Base Address Register (see Register 3-3)

- BMXDUPBA: Data RAM User Program Base Address Register (see Register 3-4)

- BMXPUPBA: Program Flash (PFM) User Program Base Address Register (see

•Updated the PIC32MX Address Map (see Table3-2)

PIC32MX Family Reference Manual

NOTES:

 2010 Microchip Technology Inc. DS61115F-page 39

Information contained in this publication regarding device

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and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

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Printed on recycled paper.

ISBN: 978-1-60932-385-1

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

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knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

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DS61115F-page 40  2010 Microchip Technology Inc.

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Prefetch Cache

Section 4. Prefetch Cache

HIGHLIGHTS

This section of the manual contains the following major topics:

4.1 Introduction .................................................................................................................... 4-2

4.2 Cache Overview.............................................................................................................4-3

4.3 Control Registers ...........................................................................................................4-7

4.4 Cache Operation.......................................................................................................... 4-23

4.5 Cache Configurations .................................................................................................. 4-23

4.6 Coherency Support ......................................................................................................4-25

4.7 Effects of Reset............................................................................................................4-26

4.8 Operation in Power-Saving Modes .............................................................................. 4-26

4.9 Design Tip.................................................................................................................... 4-26

4.10 Related Application Notes............................................................................................ 4-27

4.11 Revision History ...........................................................................................................4-28

PIC32 Family Reference Manual

4.1 INTRODUCTION

This section describes the features and operation of the Prefetch Cache module in the PIC32

device family. Prefetch cache features increase system performance for most applications.

Program Flash Memory (PFM) cache and the Prefetch Cache module increase performance for

applications that execute out of the cacheable PFM region by implementing the following

features:

• Instruction caching

The sixteen fully associative lockable 16-byte cache lines supply an instruction every clock,

for loops up to 256 bytes long.

•Data caching

Prefetch cache allows the allocation of up to four cache lines for data storage to provide

improved access for PFM-stored constant data.

•Predictive prefetching

The Prefetch Cache module provides instructions once per clock for linear code even with-

out caching by prefetching ahead of the current program counter, hiding the access time of

the PFM.

4.1.1 Additional Prefetch Cache Module Features

The Prefetch Cache module also include the following features:

•Up to four cache lines allocated to data

• Two cache lines with address mask to hold repeated instructions

• Pseudo Least-Recently-Used (LRU) replacement policy

•All cache lines are software-writable

• 16-byte parallel memory fetch

•Predictive instruction prefetch cache

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all PIC32 devices.

Please consult the note at the beginning of the “Prefetch Cache” chapter in the

current device data sheet to check whether this document supports the device you

are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

Section 4. Prefetch Cache

Prefetch Cache

4.2 CACHE OVERVIEW

The Prefetch Cache module is a performance enhancing module included in some processors

of the PIC32 family. When running at high-clock rates, Wait states must be inserted into PFM

read transactions to meet the access time of the PFM. Wait states can be hidden to the core by

prefetching and storing instructions in a temporary holding area that the CPU can access quickly.

Although the data path to the CPU is 32 bits wide, the data path to the PFM is 128 bits wide. This

wide data path provides the same bandwidth to the CPU as a 32-bit path running at four times

the frequency.

There are two main functions that the Prefetch Cache module performs: caching instructions

when they are accessed, and prefetching instructions from the PFM before they are needed.

The cache holds a subset of the cacheable memory in temporary holding spaces known as

cache lines. Each cache line has a tag describing what it is currently holding, and the address

where it is mapped. Normally, the cache lines just hold a copy of what is currently in memory to

make data available to the CPU without Wait states.

CPU requested data may or may not be in the cache. A cache-miss occurs if the CPU requests

cacheable data that is not in the cache. In this case, a read is performed to the PFM at the correct

address, the data is supplied to the cache and to the CPU. A cache-hit occurs if the cache

contains the data that the CPU requests. In the case of a cache-hit, data is supplied to the CPU

without Wait states.

The second main function of the Prefetch Cache module is to prefetch cache instructions. The

module calculates the address of the next cache line and performs a read of the PFM to get the

next 16-byte cache line. This line is placed into a 16-byte-wide prefetch cache buffer in

anticipation of executing straight-line code.

Figure 4-1 shows a block diagram of the Prefetch Cache module. Logically, the Prefetch Cache

module fits between the Bus Matrix (BMX) module and the PFM.

Figure 4-1: Prefetch Cache Block Diagram

Prefetch

Program Flash Memory (PFM)

Prefetch

Tag

Hit Logic

Tag Logic

CTRL

FSM

Bus

Cache

Prefetch

Hit LRU

Miss LRU

Cache Line

RDATA

Cache

Line

Address

Encode

BMX/CPU

RDATA

CTRL

BMX/CPU

Control

PIC32 Family Reference Manual

To ill ust ra te the b asi c ope rat ion o f the p ref et ch ca che , Figure 4-2 shows an example of the CPU

requesting data from physical address 0x1FC01234. The prefetch cache simultaneously

compares this address to all of the tags marked ‘valid’. As the shaded entry below has this

address, and is marked as valid, this is a cache hit. The proper data word from the data array is

then directed to the CPU in a single clock period.

Figure 4-2: Cache Look-up Example(1)

⎫

⎪

⎬

⎪

⎭

0x1FC01234 0x00001000 WORD 3 WORD 0WORD 1WORD 2

WORD 3 WORD 0WORD 1WORD 2

0x00001300

0x00002200

0x0000a030

0x80001230

0x00002210

0x00002230

0x00002220

0x00001200

0x00001230

0x00001320

0x00001330

0x00001310

0x00001340

0x00001350

101

001

101

100

Cache

Data

LVALID

LLOCK

LTYPE

⎫

⎪

⎬

⎪

⎭

HIT

Cache Tags(2)

Note 1: Mask bits are not shown and are assumed to be ‘0’.

2: Bits 3-0 of the address in the Cache Tags register are always implied to be ‘0’.

Section 4. Prefetch Cache

Prefetch Cache

4.2.1 Cache Organization

The cache consists of two arrays: data and tag. A data array consists of program instructions or

program data. The cache is physically tagged and address matches are based on the physical

address, not the virtual address.

Each line in the tag array contains the following information:

•Mask – address mask value

• Tag – tag address to match against

•Valid bit

•Lock bit

•Type – an instruction and/or data type-indicator bit

Each line in the data array contains 16 bytes of program instruction, or program data,

depending on the value of the type-indicator bit.

Figure 4-3 illustrates the organization of a line. It should be noted that the LMASK<10:0> bits

(CHEMSK<15:5>) and the LTYPE bit (CHETAG<1>) are not programmable for every line. The

LTAG<20:0> bits (CHETAG<23:4>) only implement the number of bits needed to fully map to the

size of the PFM. For example, if the PFM size is 512 Kbytes, the LTAG<20:0> bits

(CHETAG<23:4>) only implement bits 15 through 0 (CHETAG<18:4>).

Figure 4-3: Mask Line

Figure 4-4: Tag Line

Figure 4-5: Data Line

31 16 15 5 4 0

U-0 LMASK<10:0> U-0

31 24 23 4 3 2 1 0

LTAGBOOT

U-0 LTAG<20:0>

LVALID

LLOCK

LTYPE

U-0

31 0

WORD 3

31 0

WORD 2

31 0

WORD 1

31 0

WORD 0

PIC32 Family Reference Manual

Cache arrays are shown in Tabl e 4-1. Software can modify the values in both the Tag Line and

the Data Line of the cache. The CHEIDX<3:0> bits (CHEACC<3:0>) select a line for access.

That line can then be modified via the CHETAG, CHEMSK, CHEW0, CHEW1, CHEW2 and

CHEW3 registers.

It is recommended that the cache lines be modified while executing from non-cacheable

addresses, as the cache controller does not protect against modifying the cache while executing

from a cacheable address.

Not all bits are writable. The LMASK<10:0> bits (CHEMSK<15:5>) are only writable for lines A

and B, and the LTYPE bit (CHETAG<1>) is fixed to the instruction setting for lines 0 through B.

Note that lines allocated for Lock and Data affect the selection of the line to replace on a miss.

However, they do not affect the usage order or pseudo-LRU value.

Table 4-1: Cache Arrays

Line

Tag Array

Data Array(2)

Mask Flags

00x000(1) LTAG LVALID LLOCK LTYPE(3) Word 3 Word 2 Word 1 Word 0

10x000(1) LTAG LVALID LLOCK LTYPE(3) Word 3 Word 2 Word 1 Word 0

20x000(1) LTAG LVALID LLOCK LTYPE(3) Word 3 Word 2 Word 1 Word 0

30x000(1) LTAG LVALID LLOCK LTYPE(3) Word 3 Word 2 Word 1 Word 0

40x000(1) LTAG LVALID LLOCK LTYPE(3) Word 3 Word 2 Word 1 Word 0

50x000(1) LTAG LVALID LLOCK LTYPE(3) Word 3 Word 2 Word 1 Word 0

60x000(1) LTAG LVALID LLOCK LTYPE(3) Word 3 Word 2 Word 1 Word 0

70x000(1) LTAG LVALID LLOCK LTYPE(3) Word 3 Word 2 Word 1 Word 0

80x000(1) LTAG LVALID LLOCK LTYPE(3) Word 3 Word 2 Word 1 Word 0

90x000(1) LTAG LVALID LLOCK LTYPE(3) Word 3 Word 2 Word 1 Word 0

ALMASK LTAG LVALID LLOCK LTYPE(3) Word 3 Word 2 Word 1 Word 0

BLMASK LTAG LVALID LLOCK LTYPE(3) Word 3 Word 2 Word 1 Word 0

C0x000(1) LTAG LVALID LLOCK LTYPE Word 3 Word 2 Word 1 Word 0

D0x000(1) LTAG LVALID LLOCK LTYPE Word 3 Word 2 Word 1 Word 0

E0x000(1) LTAG LVALID LLOCK LTYPE Word 3 Word 2 Word 1 Word 0

F0x000(1) LTAG LVALID LLOCK LTYPE Word 3 Word 2 Word 1 Word 0

Note 1: Read-only bit.

2: Read ‘0’ when device is code-protected; otherwise, read/write.

3: Type is fixed as instruction.

Section 4. Prefetch Cache

Prefetch Cache

4.3 CONTROL REGISTERS

The Prefetch Cache module contains the following Special Functions Registers (SFRs):

•CHECON: Cache Control Register(1,2,3)

This register manages configuration of the prefetch cache and controls Wait states.

•CHEACC: Cache Access Register(1,2,3)

This register points to one of the 16 cache lines to access using the CHETAG, CHEMSK,

CHEW0, CHEW1, CHEW2, and CHEW3 registers.

•CHETAG: Cache TAG Register(1,2,3,4)

This register contains the address and type of information stored in a cache line.

•CHEMSK: Cache TAG Mask Register(1,2,3,4)

This register provides a mechanism to ignore the TAG bits in the CHETAG register.

•CHEW0: Cache Word 0 through CHEW3: Cache Word 3(1)

These four registers provide access to the prefetch cache data array.

•CHELRU: Cache LRU Register

This register indicates the pseudo-LRU state of the cache.

•CHEHIT: Cache Hit Statistics Register

This register contains the number of cache hits.

•CHEMIS: Cache Miss Statistics Register

This register contains the number of missed cache operations.

•CHEPFABT: Prefetch Cache Abort Statistics Register

This register contains the number of aborted prefetch cache operations.

Tabl e 4-2 provides a brief summary of prefetch cache-related registers. Corresponding registers

appear after the summary, followed by a detailed description of each register.

Note: Some devices in the PIC32 family do not contain a Prefetch Cache module. For

such devices, all prefetch cache register locations are unimplemented and should

not be accessed. Refer to the specific device data sheet to determine its

availability.

PIC32 Family Reference Manual

Table 4-2: Prefetch Cache SFRs Summary

Name Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

CHECON(1,2,3) 31:24 ——————— —

23:16 ———————CHECOH

15:8 — — — — — — DCSZ<1:0>

7:0 — — PREFEN<1:0> —PFMWS<2:0>

CHEACC(1,2,3) 31:24 CHEWEN —————— —

23:16 ——————— —

15:8 ——————— —

7:0 — — — — CHEIDX<3:0>

CHETAG(1,2,3) 31:24 LTAGBOOT —————— —

23:16 LTAG<19:12>

15:8 LTAG<11:4>

7:0 LTAG<3:0> LVALID LLOCK LTYPE —

CHEMSK(1,2,3) 31:24 ——————— —

23:16 ——————— —

15:8 LMASK<10:3>

7:0 LMASK<2:0> ———— —

CHEW0 31:24 CHEW0<31:24>

23:16 CHEW0<23:16>

15:8 CHEW0<15:8>

7:0 CHEW0<7:0>

CHEW1 31:24 CHEW1<31:24>

23:16 CHEW1<23:16>

15:8 CHEW1<15:8>

7:0 CHEW1<7:0>

CHEW2 31:24 CHEW2<31:24>

23:16 CHEW2<23:16>

15:8 CHEW2<15:8>

7:0 CHEW2<7:0>

CHEW3 31:24 CHEW3<31:24>

23:16 CHEW3<23:16>

15:8 CHEW3<15:8>

7:0 CHEW3<7:0>

CHELRU 31:24 ———————CHELRU<24>

23:16 CHELRU<23:16>

15:8 CHELRU<15:8>

7:0 CHELRU<7:0>>

Legend: — = unimplemented, read as ‘0’.

Note 1: This register has an associated Clear register at an offset of 0x4 bytes. The Clear register has the same name with CLR

appended to the register name (e.g., CHECONCLR). Writing a ‘1’ to any bit position in the Clear register will clear valid

bits in the associated register. Reads from the Clear register should be ignored.

2: This register has an associated Set register at an offset of 0x8 bytes. The Set register has the same name with SET

appended to the register name (e.g., CHECONSET). Writing a ‘1’ to any bit position in the Set register will set valid bits

in the associated register. Reads from the Set register should be ignored.

3: This register has an associated Invert register at an offset of 0xC bytes. The Invert register has the same name with INV

appended to the register name (e.g., CHECONINV). Writing a ‘1’ to any bit position in the Invert register will invert valid

bits in the associated register. Reads from the Invert register should be ignored.

Section 4. Prefetch Cache

Prefetch Cache

CHEHIT 31:24 CHEHIT<31:24>

23:16 CHEHIT<23:16>

15:8 CHEHIT<15:8>

7:0 CHEHIT<7:0>

CHEMIS 31:24 CHEMIS<31:24>

23:16 CHEMIS<23:16>

15:8 CHEMIS<15:8>

7:0 CHEMIS<7:0>

CHEPFABT 31:24 CHEPFABT<31:24>

23:16 CHEPFABT<23:16>

15:8 CHEPFABT<15:8>

7:0 CHEPFABT<7:0>

Table 4-2: Prefetch Cache SFRs Summary (Continued)