PPC440X5 Um

User Manual: PPC440X5

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Title Page

PPC440x5 CPU Core
User’s Manual

Preliminary

SA14-2613-03
July 15, 2003

All Rights Reserved
Printed in the United States of America July 2003
The following are trademarks of International Business Machines Corporation in the United States, or other countries, or
both.
IBM
IBM Logo
CoreConnect
PowerPC
PowerPC logo
PowerPC Architecture
RISCTrace RISCWatch
Other company, product, and service names may be trademarks or service marks of others.
The information contained in this document is subject to change or withdrawal at any time without notice and is
being provided on an "AS IS" basis without warranty or indemnity of any kind, whether express or implied,
including without limitation, the implied warranties of non-infringement, merchantability, or fitness for a
particular purpose. Any products, services, or programs discussed in this document are sold or licensed under
IBM's standard terms and conditions, copies of which may be obtained from your local IBM representative.
Nothing in this document shall operate as an express or implied license or indemnity under the intellectual
property rights of IBM or third parties.
Without limiting the generality of the foregoing, any performance data contained in this document was
determined in a specific or controlled environment and not submitted to any formal IBM test. Therefore, the
results obtained in other operating environments may vary significantly. Under no circumstances will IBM be
liable for any damages whatsoever arising out of or resulting from any use of the document or the information
contained herein.

While the information contained herein is believed to be accurate, such information is preliminary, and should not be
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
Note: This document contains information on products in the sampling and/or initial production phases of
development. This information is subject to change without notice. Verify with your IBM field applications
engineer that you have the latest version of this document before finalizing a design.

IBM Microelectronics Division
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The IBM home page can be found at http://www.ibm.com
The IBM Microelectronics Division home page can be found at http://www.ibm.com/chips
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Contents
Figures ..........................................................................................................................................15
Tables ............................................................................................................................................19
About This Book ..........................................................................................................................23
1. Overview .................................................................................................................................. 27
PPC440x5 Features ...............................................................................................................................
The PPC440x5 as a PowerPC Implementation .....................................................................................
PPC440x5 Organization .........................................................................................................................
Superscalar Instruction Unit ............................................................................................................
Execution Pipelines .........................................................................................................................
Instruction and Data Cache Controllers ...........................................................................................
Instruction Cache Controller (ICC) ..............................................................................................
Data Cache Controller (DCC) ......................................................................................................
Memory Management Unit (MMU) ..................................................................................................
Timers ..............................................................................................................................................
Debug Facilities ...............................................................................................................................
Debug Modes ..............................................................................................................................
Development Tool Support ..........................................................................................................
Core Interfaces .......................................................................................................................................
Processor Local Bus (PLB) .............................................................................................................
Device Control Register (DCR) Interface ........................................................................................
Auxiliary Processor Unit (APU) Port ................................................................................................
JTAG Port ........................................................................................................................................

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2. Programming Model ............................................................................................................... 39
Storage Addressing ................................................................................................................................
Storage Operands ...........................................................................................................................
Effective Address Calculation ..........................................................................................................
Data Storage Addressing Modes ................................................................................................
Instruction Storage Addressing Modes .......................................................................................
Byte Ordering ..................................................................................................................................
Structure Mapping Examples ......................................................................................................
Instruction Byte Ordering .............................................................................................................
Data Byte Ordering ......................................................................................................................
Byte-Reverse Instructions ...........................................................................................................
Registers ................................................................................................................................................
Register Types ................................................................................................................................
General Purpose Registers .........................................................................................................
Special Purpose Registers ..........................................................................................................
Condition Register .......................................................................................................................
Machine State Register ...............................................................................................................
Device Control Registers .............................................................................................................
Instruction Classes .................................................................................................................................
Defined Instruction Class .................................................................................................................
Allocated Instruction Class ..............................................................................................................
Preserved Instruction Class .............................................................................................................
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Preliminary

Reserved Instruction Class .............................................................................................................
Implemented Instruction Set Summary .................................................................................................
Integer Instructions .........................................................................................................................
Integer Storage Access Instructions ...........................................................................................
Integer Arithmetic Instructions ....................................................................................................
Integer Logical Instructions .........................................................................................................
Integer Compare Instructions .....................................................................................................
Integer Trap Instructions .............................................................................................................
Integer Rotate Instructions .........................................................................................................
Integer Shift Instructions .............................................................................................................
Integer Select Instruction ............................................................................................................
Branch Instructions .........................................................................................................................
Processor Control Instructions ........................................................................................................
Condition Register Logical Instructions ......................................................................................
Register Management Instructions .............................................................................................
System Linkage Instructions .......................................................................................................
Processor Synchronization Instruction .......................................................................................
Storage Control Instructions ...........................................................................................................
Cache Management Instructions ................................................................................................
TLB Management Instructions ....................................................................................................
Storage Synchronization Instructions .........................................................................................
Allocated Instructions ......................................................................................................................
Branch Processing ................................................................................................................................
Branch Addressing ..........................................................................................................................
Branch Instruction BI Field ..............................................................................................................
Branch Instruction BO Field ............................................................................................................
Branch Prediction ............................................................................................................................
Branch Control Registers ................................................................................................................
Link Register (LR) .......................................................................................................................
Count Register (CTR) .................................................................................................................
Condition Register (CR) .............................................................................................................
Integer Processing ................................................................................................................................
General Purpose Registers (GPRs) ................................................................................................
Integer Exception Register (XER) ...................................................................................................
Summary Overflow (SO) Field ....................................................................................................
Overflow (OV) Field ....................................................................................................................
Carry (CA) Field ..........................................................................................................................
Processor Control ..................................................................................................................................
Special Purpose Registers General (USPRG0, SPRG0–SPRG7) .................................................
Processor Version Register (PVR) .................................................................................................
Processor Identification Register (PIR) ...........................................................................................
Core Configuration Register 0 (CCR0) ...........................................................................................
Core Configuration Register 1 (CCR1) ...........................................................................................
Reset Configuration (RSTCFG) ......................................................................................................
User and Supervisor Modes ..................................................................................................................
Privileged Instructions .....................................................................................................................
Privileged SPRs ..............................................................................................................................
Speculative Accesses ...........................................................................................................................
Synchronization .....................................................................................................................................
Context Synchronization .................................................................................................................
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Execution Synchronization .............................................................................................................. 81
Storage Ordering and Synchronization ........................................................................................... 81

3. Initialization ............................................................................................................................. 83
PPC440x5 Core State After Reset .........................................................................................................
Reset Types .........................................................................................................................................
Reset Sources ........................................................................................................................................
Initialization Software Requirements ......................................................................................................

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4. Instruction and Data Caches ................................................................................................. 93
Cache Array Organization and Operation .............................................................................................. 93
Cache Line Replacement Policy ...................................................................................................... 94
Cache Locking and Transient Mechanism ...................................................................................... 96
Instruction Cache Controller ................................................................................................................. 100
ICC Operations .............................................................................................................................. 101
Speculative Prefetch Mechanism .................................................................................................. 102
Instruction Cache Coherency ........................................................................................................ 103
Self-Modifying Code .................................................................................................................. 103
Instruction Cache Synonyms ..................................................................................................... 104
Instruction Cache Control and Debug ........................................................................................... 105
Instruction Cache Management and Debug Instruction Summary ............................................ 105
Core Configuration Register 0 (CCR0) ...................................................................................... 105
Core Configuration Register 1 (CCR1) ...................................................................................... 107
icbt Operation ............................................................................................................................ 108
icread Operation ........................................................................................................................ 109
Instruction Cache Parity Operations .......................................................................................... 110
Simulating Instruction Cache Parity Errors for Software Testing .............................................. 111
Data Cache Controller .......................................................................................................................... 112
DCC Operations ............................................................................................................................ 113
Load and Store Alignment ......................................................................................................... 114
Load Operations ........................................................................................................................ 115
Store Operations ....................................................................................................................... 115
Line Flush Operations ............................................................................................................... 117
Data Read PLB Interface Requests .......................................................................................... 118
Data Write PLB Interface Requests .......................................................................................... 119
Storage Access Ordering .......................................................................................................... 120
Data Cache Coherency ................................................................................................................. 120
Data Cache Control and Debug .................................................................................................... 121
Data Cache Management and Debug Instruction Summary ..................................................... 121
Core Configuration Register 0 (CCR0) ...................................................................................... 122
Core Configuration Register 1 (CCR1) ...................................................................................... 122
dcbt and dcbtst Operation ......................................................................................................... 122
dcread Operation ....................................................................................................................... 123
Data Cache Parity Operations ................................................................................................... 125
Simulating Data Cache Parity Errors for Software Testing ....................................................... 126

5. Memory Management ........................................................................................................... 129
MMU Overview ..................................................................................................................................... 129
Support for PowerPC Book-E MMU Architecture .......................................................................... 129
Translation Lookaside Buffer ............................................................................................................... 130

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Page Identification ...............................................................................................................................
Virtual Address Formation ............................................................................................................
Address Space Identifier Convention ............................................................................................
TLB Match Process .......................................................................................................................
Address Translation ............................................................................................................................
Access Control ....................................................................................................................................
Execute Access ............................................................................................................................
Write Access .................................................................................................................................
Read Access .................................................................................................................................
Access Control Applied to Cache Management Instructions ........................................................
Storage Attributes ................................................................................................................................
Write-Through (W) ........................................................................................................................
Caching Inhibited (I) ......................................................................................................................
Memory Coherence Required (M) ................................................................................................
Guarded (G) ..................................................................................................................................
Endian (E) .....................................................................................................................................
User-Definable (U0–U3) ...............................................................................................................
Supported Storage Attribute Combinations ..................................................................................
Storage Control Registers ...................................................................................................................
Memory Management Unit Control Register (MMUCR) ...............................................................
Process ID (PID) ...........................................................................................................................
Shadow TLB Arrays ............................................................................................................................
TLB Management Instructions ............................................................................................................
TLB Search Instruction (tlbsx[.]) ...................................................................................................
TLB Read/Write Instructions (tlbre/tlbwe) .....................................................................................
TLB Sync Instruction (tlbsync) ......................................................................................................
Page Reference and Change Status Management .............................................................................
TLB Parity Operations .........................................................................................................................
Reading TLB Parity Bits with tlbre ................................................................................................
Simulating TLB Parity Errors for Software Testing .......................................................................

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6. Interrupts and Exceptions ................................................................................................... 153
Overview .............................................................................................................................................
Interrupt Classes .................................................................................................................................
Asynchronous Interrupts ...............................................................................................................
Synchronous Interrupts .................................................................................................................
Synchronous, Precise Interrupts ..............................................................................................
Synchronous, Imprecise Interrupts ...........................................................................................
Critical and Non-Critical Interrupts ................................................................................................
Machine Check Interrupts .............................................................................................................
Interrupt Processing ............................................................................................................................
Partially Executed Instructions ......................................................................................................
Interrupt Processing Registers ............................................................................................................
Machine State Register (MSR) .....................................................................................................
Save/Restore Register 0 (SRR0) ..................................................................................................
Save/Restore Register 1 (SRR1) ..................................................................................................
Critical Save/Restore Register 0 (CSRR0) ...................................................................................
Critical Save/Restore Register 1 (CSRR1) ...................................................................................
Machine Check Save/Restore Register 0 (MCSRR0) ..................................................................
Machine Check Save/Restore Register 1 (MCSRR1) ..................................................................
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Data Exception Address Register (DEAR) ....................................................................................
Interrupt Vector Offset Registers (IVOR0–IVOR15) .....................................................................
Interrupt Vector Prefix Register (IVPR) .........................................................................................
Exception Syndrome Register (ESR) ............................................................................................
Machine Check Status Register (MCSR) ......................................................................................
Interrupt Definitions ..............................................................................................................................
Critical Input Interrupt ....................................................................................................................
Machine Check Interrupt ...............................................................................................................
Data Storage Interrupt ...................................................................................................................
Instruction Storage Interrupt ..........................................................................................................
External Input Interrupt ..................................................................................................................
Alignment Interrupt ........................................................................................................................
Program Interrupt ..........................................................................................................................
Floating-Point Unavailable Interrupt ..............................................................................................
System Call Interrupt .....................................................................................................................
Auxiliary Processor Unavailable Interrupt ......................................................................................
Decrementer Interrupt ...................................................................................................................
Fixed-Interval Timer Interrupt ........................................................................................................
Watchdog Timer Interrupt ..............................................................................................................
Data TLB Error Interrupt ................................................................................................................
Instruction TLB Error Interrupt .......................................................................................................
Debug Interrupt ..............................................................................................................................
Interrupt Ordering and Masking ...........................................................................................................
Interrupt Ordering Software Requirements ....................................................................................
Interrupt Order ...............................................................................................................................
Exception Priorities ..............................................................................................................................
Exception Priorities for Integer Load, Store, and Cache Management Instructions ......................
Exception Priorities for Floating-Point Load and Store Instructions ..............................................
Exception Priorities for Allocated Load and Store Instructions ......................................................
Exception Priorities for Floating-Point Instructions (Other) ............................................................
Exception Priorities for Allocated Instructions (Other) ...................................................................
Exception Priorities for Privileged Instructions ..............................................................................
Exception Priorities for Trap Instructions .......................................................................................
Exception Priorities for System Call Instruction .............................................................................
Exception Priorities for Branch Instructions ...................................................................................
Exception Priorities for Return From Interrupt Instructions ............................................................
Exception Priorities for Preserved Instructions ..............................................................................
Exception Priorities for Reserved Instructions ...............................................................................
Exception Priorities for All Other Instructions ................................................................................

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7. Timer Facilities ...................................................................................................................... 203
Time Base ............................................................................................................................................
Reading the Time Base .................................................................................................................
Writing the Time Base ...................................................................................................................
Decrementer (DEC) .............................................................................................................................
Fixed Interval Timer (FIT) .....................................................................................................................
Watchdog Timer ...................................................................................................................................
Timer Control Register (TCR) ..............................................................................................................
Timer Status Register (TSR) ................................................................................................................
Freezing the Timer Facilities ................................................................................................................
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Selection of the Timer Clock Source ................................................................................................... 211

8. Debug Facilities .................................................................................................................... 213
Support for Development Tools ...........................................................................................................
Debug Modes ......................................................................................................................................
Internal Debug Mode ....................................................................................................................
External Debug Mode ...................................................................................................................
Debug Wait Mode .........................................................................................................................
Trace Debug Mode .......................................................................................................................
Debug Events ......................................................................................................................................
Instruction Address Compare (IAC) Debug Event ........................................................................
IAC Debug Event Fields ...........................................................................................................
IAC Debug Event Processing ...................................................................................................
Data Address Compare (DAC) Debug Event ................................................................................
DAC Debug Event Fields ..........................................................................................................
DAC Debug Event Processing .................................................................................................
DAC Debug Events Applied to Instructions that Result in Multiple Storage Accesses .............
DAC Debug Events Applied to Various Instruction Types .......................................................
Data Value Compare (DVC) Debug Event ....................................................................................
DVC Debug Event Fields ..........................................................................................................
DVC Debug Event Processing .................................................................................................
DVC Debug Events Applied to Instructions that Result in Multiple Storage Accesses .............
DVC Debug Events Applied to Various Instruction Types .......................................................
Branch Taken (BRT) Debug Event ...............................................................................................
Trap (TRAP) Debug Event ............................................................................................................
Return (RET) Debug Event ...........................................................................................................
Instruction Complete (ICMP) Debug Event ...................................................................................
Interrupt (IRPT) Debug Event .......................................................................................................
Unconditional Debug Event (UDE) ...............................................................................................
Debug Event Summary .................................................................................................................
Debug Reset .......................................................................................................................................
Debug Timer Freeze ...........................................................................................................................
Debug Registers ..................................................................................................................................
Debug Control Register 0 (DBCR0) ..............................................................................................
Debug Control Register 1 (DBCR1) ..............................................................................................
Debug Control Register 2 (DBCR2) ..............................................................................................
Debug Status Register (DBSR) ...................................................................................................
Instruction Address Compare Registers (IAC1–IAC4) ..................................................................
Data Address Compare Registers (DAC1–DAC2) ........................................................................
Data Value Compare Registers (DVC1–DVC2) ............................................................................
Debug Data Register (DBDR) .......................................................................................................

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9. Instruction Set ....................................................................................................................... 243
Instruction Set Portability ..................................................................................................................... 244
Instruction Formats .............................................................................................................................. 244
Pseudocode ........................................................................................................................................ 245
Operator Precedence .................................................................................................................... 247
Register Usage .................................................................................................................................... 247
Alphabetical Instruction Listing ............................................................................................................ 247
add ................................................................................................................................................. 248
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addc ................................................................................................................................................249
adde ................................................................................................................................................250
addi .................................................................................................................................................251
addic ...............................................................................................................................................252
addic. ..............................................................................................................................................253
addis ...............................................................................................................................................254
addme .............................................................................................................................................255
addze ..............................................................................................................................................256
and ..................................................................................................................................................257
andc ................................................................................................................................................258
andi. ................................................................................................................................................259
andis. ..............................................................................................................................................260
b ......................................................................................................................................................261
bc ....................................................................................................................................................262
bcctr ................................................................................................................................................268
bclr ..................................................................................................................................................271
cmp .................................................................................................................................................275
cmpi ................................................................................................................................................276
cmpl ................................................................................................................................................277
cmpli ...............................................................................................................................................278
cntlzw ..............................................................................................................................................279
crand ...............................................................................................................................................280
crandc .............................................................................................................................................281
creqv ...............................................................................................................................................282
crnand .............................................................................................................................................283
crnor ...............................................................................................................................................284
cror .................................................................................................................................................285
crorc ................................................................................................................................................286
crxor ................................................................................................................................................287
dcba ................................................................................................................................................288
dcbf .................................................................................................................................................289
dcbi .................................................................................................................................................290
dcbst ...............................................................................................................................................291
dcbt .................................................................................................................................................292
dcbtst ..............................................................................................................................................293
dcbz ................................................................................................................................................294
dccci ...............................................................................................................................................295
dcread .............................................................................................................................................296
divw ................................................................................................................................................298
divwu ..............................................................................................................................................299
dlmzb .............................................................................................................................................300
eqv ..................................................................................................................................................301
extsb ...............................................................................................................................................302
extsh ...............................................................................................................................................303
icbi ..................................................................................................................................................304
icbt ..................................................................................................................................................305
iccci .................................................................................................................................................307
icread ..............................................................................................................................................308
isel ..................................................................................................................................................310
isync ...............................................................................................................................................311
lbz ...................................................................................................................................................312
lbzu .................................................................................................................................................313
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lbzux ............................................................................................................................................... 314
lbzx ................................................................................................................................................. 315
lha .................................................................................................................................................. 316
lhau ................................................................................................................................................ 317
lhaux .............................................................................................................................................. 318
lhax ................................................................................................................................................ 319
lhbrx ............................................................................................................................................... 320
lhz .................................................................................................................................................. 321
lhzu ................................................................................................................................................ 322
lhzux ............................................................................................................................................... 323
lhzx ................................................................................................................................................. 324
lmw ................................................................................................................................................. 325
lswi ................................................................................................................................................. 326
lswx ................................................................................................................................................ 328
lwarx ............................................................................................................................................... 330
lwbrx ............................................................................................................................................... 331
lwz .................................................................................................................................................. 332
lwzu ................................................................................................................................................ 333
lwzux .............................................................................................................................................. 334
lwzx ................................................................................................................................................ 335
macchw .......................................................................................................................................... 336
macchws ........................................................................................................................................ 337
macchwsu ...................................................................................................................................... 338
macchwu ........................................................................................................................................ 339
machhw .......................................................................................................................................... 340
machhws ........................................................................................................................................ 341
machhwsu ...................................................................................................................................... 342
machhwu ........................................................................................................................................ 343
maclhw ........................................................................................................................................... 344
maclhws ......................................................................................................................................... 345
maclhwsu ....................................................................................................................................... 346
maclhwu ......................................................................................................................................... 347
mbar ............................................................................................................................................... 348
mcrf ................................................................................................................................................ 350
mcrxr .............................................................................................................................................. 351
mfcr ................................................................................................................................................ 352
mfdcr .............................................................................................................................................. 353
mfmsr ............................................................................................................................................. 354
mfspr .............................................................................................................................................. 355
msync ............................................................................................................................................. 358
mtcrf ............................................................................................................................................... 359
mtdcr .............................................................................................................................................. 360
mtmsr ............................................................................................................................................. 361
mtspr .............................................................................................................................................. 362
mulchw ........................................................................................................................................... 365
mulchwu ......................................................................................................................................... 366
mulhhw ........................................................................................................................................... 367
mulhhwu ......................................................................................................................................... 368
mulhw ............................................................................................................................................. 369
mulhwu ........................................................................................................................................... 370
mullhw ............................................................................................................................................ 371
mullhwu .......................................................................................................................................... 372
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mulli ................................................................................................................................................373
mullw ..............................................................................................................................................374
nand ................................................................................................................................................375
neg ..................................................................................................................................................376
nmacchw ........................................................................................................................................377
nmacchws .......................................................................................................................................378
nmachhw ........................................................................................................................................379
nmachhws ......................................................................................................................................380
nmaclhw .........................................................................................................................................381
nmaclhws ........................................................................................................................................382
nor ..................................................................................................................................................383
or ....................................................................................................................................................384
orc ...................................................................................................................................................385
ori ....................................................................................................................................................386
oris ..................................................................................................................................................387
rfci ...................................................................................................................................................388
rfi .....................................................................................................................................................389
rfmci ................................................................................................................................................390
rlwimi ..............................................................................................................................................391
rlwinm .............................................................................................................................................392
rlwnm ..............................................................................................................................................394
sc ....................................................................................................................................................395
slw ..................................................................................................................................................396
sraw ................................................................................................................................................397
srawi ...............................................................................................................................................398
srw ..................................................................................................................................................399
stb ...................................................................................................................................................400
stbu .................................................................................................................................................401
stbux ...............................................................................................................................................402
stbx .................................................................................................................................................403
sth ...................................................................................................................................................404
sthbrx ..............................................................................................................................................405
sthu .................................................................................................................................................406
sthux ...............................................................................................................................................407
sthx .................................................................................................................................................408
stmw ...............................................................................................................................................409
stswi ................................................................................................................................................410
stswx ...............................................................................................................................................411
stw ..................................................................................................................................................412
stwbrx .............................................................................................................................................413
stwcx. ..............................................................................................................................................414
stwu ................................................................................................................................................416
stwux ..............................................................................................................................................417
stwx ................................................................................................................................................418
subf .................................................................................................................................................419
subfc ...............................................................................................................................................420
subfe ...............................................................................................................................................421
subfic ..............................................................................................................................................422
subfme ............................................................................................................................................423
subfze .............................................................................................................................................424
tlbre .................................................................................................................................................425
tlbsx ................................................................................................................................................427
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tlbsync ............................................................................................................................................ 428
tlbwe ............................................................................................................................................... 429
tw ................................................................................................................................................... 430
twi ................................................................................................................................................... 433
wrtee .............................................................................................................................................. 435
wrteei ............................................................................................................................................. 436
xor .................................................................................................................................................. 437
xori ................................................................................................................................................. 438
xoris ............................................................................................................................................... 439

10. Register Summary ............................................................................................................. 441
Register Categories .............................................................................................................................
Reserved Fields ..................................................................................................................................
Device Control Registers .....................................................................................................................
Alphabetical Register Listing ...............................................................................................................
CCR0 .............................................................................................................................................
CCR1 .............................................................................................................................................
CR..................................................................................................................................................
CSRR0...........................................................................................................................................
CSRR1...........................................................................................................................................
CTR................................................................................................................................................
DAC1–DAC2..................................................................................................................................
DBCR0...........................................................................................................................................
DBCR1...........................................................................................................................................
DBCR2...........................................................................................................................................
DBDR.............................................................................................................................................
DBSR .............................................................................................................................................
DCDBTRH .....................................................................................................................................
DCDBTRL ......................................................................................................................................
DEAR .............................................................................................................................................
DEC ...............................................................................................................................................
DECAR ..........................................................................................................................................
DNV0–DNV3..................................................................................................................................
DTV0–DTV3...................................................................................................................................
DVC1–DVC2..................................................................................................................................
DVLIM ............................................................................................................................................
ESR................................................................................................................................................
GPR0–GPR31 ...............................................................................................................................
IAC1–IAC4 .....................................................................................................................................
ICDBDR .........................................................................................................................................
ICDBTRH .......................................................................................................................................
ICDBTRL........................................................................................................................................
INV0–INV3 .....................................................................................................................................
ITV0–ITV3......................................................................................................................................
IVLIM..............................................................................................................................................
IVOR0–IVOR15 .............................................................................................................................
IVPR...............................................................................................................................................
LR ..................................................................................................................................................
MCSR ............................................................................................................................................
MCSRR0........................................................................................................................................
MCSRR1........................................................................................................................................

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441
445
445
447
448
450
452
453
454
455
456
457
459
461
463
464
466
467
468
469
470
471
472
473
474
475
477
478
479
480
481
482
483
484
485
486
487
488
489
490

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MMUCR..........................................................................................................................................
MSR................................................................................................................................................
PID..................................................................................................................................................
PIR..................................................................................................................................................
PVR ................................................................................................................................................
RSTCFG .........................................................................................................................................
SPRG0–SPRG7 .............................................................................................................................
SRR0 ..............................................................................................................................................
SRR1 ..............................................................................................................................................
TBL .................................................................................................................................................
TBU ................................................................................................................................................
TCR ................................................................................................................................................
TSR ................................................................................................................................................
USPRG0.........................................................................................................................................
XER ................................................................................................................................................

491
492
494
495
496
497
498
499
500
501
502
503
504
505
506

Appendix A. Instruction Summary .......................................................................................... 507
Instruction Formats .............................................................................................................................
Instruction Fields ..........................................................................................................................
Instruction Format Diagrams ........................................................................................................
I-Form .......................................................................................................................................
B-Form .....................................................................................................................................
SC-Form ...................................................................................................................................
D-Form .....................................................................................................................................
X-Form .....................................................................................................................................
XL-Form ...................................................................................................................................
XFX-Form .................................................................................................................................
XO-Form ...................................................................................................................................
M-Form .....................................................................................................................................
Alphabetical Summary of Implemented Instructions ...........................................................................
Allocated Instruction Opcodes ............................................................................................................
Preserved Instruction Opcodes ...........................................................................................................
Reserved Instruction Opcodes ............................................................................................................
Implemented Instructions Sorted by Opcode ......................................................................................

507
508
509
510
510
510
510
511
512
512
512
512
512
543
543
544
544

Appendix B. PPC440x5 Core Compiler Optimizations .......................................................... 553
Index ............................................................................................................................................555
Revision Log ..............................................................................................................................573

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Figures
Figure 1-1.

PPC440x5 Core Block Diagram ............................................................................................. 30

Figure 2-1.

User Programming Model Registers ...................................................................................... 47

Figure 2-2.

Supervisor Programming Model Registers ............................................................................ 49

Figure 2-3.

Link Register (LR) .................................................................................................................. 65

Figure 2-4.

Count Register (CTR) ............................................................................................................ 66

Figure 2-5.

Condition Register (CR) ......................................................................................................... 66

Figure 2-6.

General Purpose Registers (R0-R31) .................................................................................... 69

Figure 2-7.

Integer Exception Register (XER) .......................................................................................... 70

Figure 2-8.

Special Purpose Registers General (USPRG0, SPRG0–SPRG7) ........................................ 73

Figure 2-9.

Processor Version Register (PVR) ......................................................................................... 74

Figure 2-10. Processor Identification Register (PIR) .................................................................................. 74
Figure 2-11. Core Configuration Register 0 (CCR0) .................................................................................. 75
Figure 2-12. Core Configuration Register 1 (CCR1) .................................................................................. 76
Figure 2-13. Reset Configuration ............................................................................................................... 77
Figure 4-1.

Instruction Cache Normal Victim Registers (INV0–INV3) ...................................................... 95

Figure 4-1.

Instruction Cache Transient Victim Registers (ITV0–ITV3) .................................................... 95

Figure 4-1.

Data Cache Normal Victim Registers (DNV0–DNV3) ............................................................ 95

Figure 4-1.

Data Cache Transient Victim Registers (DTV0–DTV3) ......................................................... 95

Figure 4-2.

Instruction Cache Victim Limit (IVLIM) ................................................................................... 97

Figure 4-2.

Data Cache Victim Limit (DVLIM) .......................................................................................... 97

Figure 4-3.

Cache Locking and Transient Mechanism (Example 1)1 ....................................................... 99

Figure 4-4.

Cache Locking and Transient Mechanism (Example 2) ....................................................... 100

Figure 4-5.

Core Configuration Register 0 (CCR0) ................................................................................ 106

Figure 4-6.

Core Configuration Register 1 (CCR1) ................................................................................ 107

Figure 4-7.

Instruction Cache Debug Data Register (ICDBDR) ............................................................. 109

Figure 4-8.

Instruction Cache Debug Tag Register High (ICDBTRH) .................................................... 110

Figure 4-9.

Instruction Cache Debug Tag Register Low (ICDBTRL) ...................................................... 110

Figure 4-10. Data Cache Debug Tag Register High (DCDBTRH) ............................................................ 124
Figure 4-11. Data Cache Debug Tag Register Low (DCDBTRL) ............................................................. 124
Figure 5-1.

Virtual Address to TLB Entry Match Process ....................................................................... 136

Figure 5-2.

Effective-to-Real Address Translation Flow ......................................................................... 137

Figure 5-3.

Memory Management Unit Control Register (MMUCR) ....................................................... 143

Figure 5-4.

Process ID (PID) .................................................................................................................. 147

Figure 5-5.

TLB Entry Word Definitions .................................................................................................. 149

Figure 6-1.

Machine State Register (MSR) ............................................................................................ 159

Figure 6-2.

Save/Restore Register 0 (SRR0) ......................................................................................... 161

Figure 6-3.

Save/Restore Register 1 (SRR1) ......................................................................................... 162

Figure 6-4.

Critical Save/Restore Register 0 (CSRR0) .......................................................................... 162

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Figure 6-5.

Critical Save/Restore Register 1 (CSRR1) ...........................................................................163

Figure 6-6.

Machine Check Save/Restore Register 0 (MCSRR0) ..........................................................163

Figure 6-7.

Machine Check Save/Restore Register 1 (MCSRR1) ..........................................................164

Figure 6-8.

Data Exception Address Register (DEAR) ...........................................................................164

Figure 6-9.

Interrupt Vector Offset Registers (IVOR0–IVOR15) ............................................................165

Figure 6-10. Interrupt Vector Prefix Register (IVPR) ................................................................................166
Figure 6-11. Exception Syndrome Register (ESR) ...................................................................................166
Figure 6-12. Machine Check Status Register (MCSR) .............................................................................168
Figure 7-1.

Relationship of Timer Facilities to the Time Base ................................................................203

Figure 7-2.

Time Base Lower (TBL) ........................................................................................................204

Figure 7-3.

Time Base Upper (TBU) .......................................................................................................204

Figure 7-4.

Decrementer (DEC) ..............................................................................................................206

Figure 7-5.

Decrementer Auto-Reload (DECAR) ....................................................................................206

Figure 7-6.

Watchdog State Machine .....................................................................................................209

Figure 7-7.

Timer Control Register (TCR) ...............................................................................................210

Figure 7-8.

Timer Status Register (TSR) ................................................................................................211

Figure 8-1.

Debug Control Register 0 (DBCR0) .....................................................................................233

Figure 8-2.

Debug Control Register 1 (DBCR1) .....................................................................................234

Figure 8-3.

Debug Control Register 2 (DBCR2) .....................................................................................237

Figure 8-4.

Debug Status Register (DBSR) ............................................................................................238

Figure 8-5.

Instruction Address Compare Registers (IAC1–IAC4) .........................................................240

Figure 8-6.

Data Address Compare Registers (DAC1–DAC2) ...............................................................240

Figure 8-7.

Data Value Compare Registers (DVC1–DVC2) ...................................................................240

Figure 8-8.

Debug Data Register (DBDR) ..............................................................................................241

Figure 10-1. Core Configuration Register 0 (CCR0) .................................................................................448
Figure 10-2. Core Configuration Register 1 (CCR1) .................................................................................450
Figure 10-3. Condition Register (CR) .......................................................................................................452
Figure 10-4. Critical Save/Restore Register 0 (CSRR0) ...........................................................................453
Figure 10-5. Critical Save/Restore Register 1 (CSRR1) ...........................................................................454
Figure 10-6. Count Register (CTR) ...........................................................................................................455
Figure 10-7. Data Address Compare Registers (DAC1–DAC2) ...............................................................456
Figure 10-8. Debug Control Register 0 (DBCR0) .....................................................................................457
Figure 10-9. Debug Control Register 1 (DBCR1) .....................................................................................459
Figure 10-10. Debug Control Register 2 (DBCR2) .....................................................................................461
Figure 10-11. Debug Data Register (DBDR) ..............................................................................................463
Figure 10-12. Debug Status Register (DBSR) ............................................................................................464
Figure 10-13. Data Cache Debug Tag Register High (DCDBTRH) ............................................................466
Figure 10-14. Data Cache Debug Tag Register Low (DCDBTRL) .............................................................467
Figure 10-15. Data Exception Address Register (DEAR) ...........................................................................468

Figures

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Figure 10-16. Decrementer (DEC) ............................................................................................................. 469
Figure 10-17. Decrementer Auto-Reload (DECAR) ................................................................................... 470
Figure 10-18. Data Cache Normal Victim Registers (DNV0–DNV3) .......................................................... 471
Figure 10-19. Data Cache Transient Victim Registers (DTV0–DTV3) ....................................................... 472
Figure 10-20. Data Value Compare Registers (DVC1–DVC2) ................................................................... 473
Figure 10-21. Data Cache Victim Limit (DVLIM) ........................................................................................ 474
Figure 10-22. Exception Syndrome Register (ESR) ................................................................................... 475
Figure 10-23. General Purpose Registers (R0-R31) .................................................................................. 477
Figure 10-24. Instruction Address Compare Registers (IAC1–IAC4) ......................................................... 478
Figure 10-25. Instruction Cache Debug Data Register (ICDBDR) ............................................................. 479
Figure 10-26. Instruction Cache Debug Tag Register High (ICDBTRH) .................................................... 480
Figure 10-27. Instruction Cache Debug Tag Register Low (ICDBTRL) ...................................................... 481
Figure 10-28. Instruction Cache Normal Victim Registers (INV0–INV3) .................................................... 482
Figure 10-29. Instruction Cache Transient Victim Registers (ITV0–ITV3) .................................................. 483
Figure 10-30. Instruction Cache Victim Limit (IVLIM) ................................................................................. 484
Figure 10-31. Interrupt Vector Offset Registers (IVOR0–IVOR15) ............................................................ 485
Figure 10-32. Interrupt Vector Prefix Register (IVPR) ................................................................................ 486
Figure 10-33. Link Register (LR) ................................................................................................................ 487
Figure 10-34. Machine Check Status Register (MCSR) ............................................................................. 488
Figure 10-35. Machine Check Save/Restore Register 0 (MCSRR0) .......................................................... 489
Figure 10-36. Machine Check Save/Restore Register 1 (MCSRR1) .......................................................... 490
Figure 10-37. Memory Management Unit Control Register (MMUCR) ....................................................... 491
Figure 10-38. Machine State Register (MSR) ............................................................................................ 492
Figure 10-39. Process ID (PID) .................................................................................................................. 494
Figure 10-40. Processor Identification Register (PIR) ................................................................................ 495
Figure 10-41. Processor Version Register (PVR) ....................................................................................... 496
Figure 10-42. Reset Configuration ............................................................................................................. 497
Figure 10-43. Special Purpose Registers General (SPRG0–SPRG7) ....................................................... 498
Figure 10-44. Save/Restore Register 0 (SRR0) ......................................................................................... 499
Figure 10-45. Save/Restore Register 1 (SRR1) ......................................................................................... 500
Figure 10-46. Time Base Lower (TBL) ....................................................................................................... 501
Figure 10-47. Time Base Upper (TBU) ....................................................................................................... 502
Figure 10-48. Timer Control Register (TCR) .............................................................................................. 503
Figure 10-49. Timer Status Register (TSR) ................................................................................................ 504
Figure 10-50. User Special Purpose Register General (USPRG0) ............................................................ 505
Figure 10-51. Integer Exception Register (XER) ........................................................................................ 506
Figure A-1.

I Instruction Format .............................................................................................................. 510

Figure A-2.

B Instruction Format ............................................................................................................. 510

Figure A-3.

SC Instruction Format .......................................................................................................... 510

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Figure A-4.

D Instruction Format .............................................................................................................510

Figure A-5.

X Instruction Format .............................................................................................................511

Figure A-6.

XL Instruction Format ...........................................................................................................512

Figure A-7.

XFX Instruction Format .........................................................................................................512

Figure A-8.

XO Instruction Format ..........................................................................................................512

Figure A-9.

M Instruction Format .............................................................................................................512

Figures

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Tables
Table 2-1.

Data Operand Definitions ....................................................................................................... 40

Table 2-2.

Alignment Effects for Storage Access Instructions ................................................................ 40

Table 2-3.

Register Categories ............................................................................................................... 50

Table 2-4.

Instruction Categories

Table 2-5.

Integer Storage Access Instructions ...................................................................................... 57

Table 2-6.

Integer Arithmetic Instructions ................................................................................................ 57

Table 2-7.

Integer Logical Instructions .................................................................................................... 58

Table 2-8.

Integer Compare Instructions ................................................................................................. 58

Table 2-9.

Integer Trap Instructions ....................................................................................................... 58

Table 2-10.

Integer Rotate Instructions ..................................................................................................... 58

Table 2-11.

Integer Shift Instructions ........................................................................................................ 59

Table 2-12.

Integer Select Instruction ....................................................................................................... 59

Table 2-13.

Branch Instructions ................................................................................................................ 59

Table 2-14.

Condition Register Logical Instructions .................................................................................. 60

Table 2-15.

Register Management Instructions ........................................................................................ 60

Table 2-16.

System Linkage Instructions .................................................................................................. 60

Table 2-17.

Processor Synchronization Instruction ................................................................................... 60

Table 2-18.

Cache Management Instructions ........................................................................................... 61

Table 2-19.

TLB Management Instructions ............................................................................................... 61

Table 2-20.

Storage Synchronization Instructions ..................................................................................... 62

Table 2-21.

Allocated Instructions ............................................................................................................. 62

Table 2-22.

BO Field Definition ................................................................................................................. 63

Table 2-23.

BO Field Examples ................................................................................................................ 64

Table 2-24.

CR Updating Instructions ....................................................................................................... 67

Table 2-25.

XER[SO,OV] Updating Instructions ........................................................................................ 71

Table 2-26.

XER[CA] Updating Instructions .............................................................................................. 71

Table 2-27.

Privileged Instructions ............................................................................................................ 78

Table 3-1.

Reset Values of Registers and Other PPC440x5 Facilities ................................................... 84

Table 4-1.

Instruction and Data Cache Array Organization ..................................................................... 94

Table 4-2.

Cache Sizes and Parameters ................................................................................................ 94

Table 4-3.

Victim Index Field Selection ................................................................................................... 96

Table 4-4.

Icread and dcread Cache Line Selection ............................................................................. 109

Table 4-5.

Data Cache Behavior on Store Accesses ............................................................................ 117

Table 5-1.

TLB Entry Fields ................................................................................................................... 131

Table 5-2.

Page Size and Effective Address to EPN Comparison ........................................................ 136

Table 5-3.

Page Size and Real Address Formation .............................................................................. 137

Table 5-4.

Access Control Applied to Cache Management Instructions .............................................. 140

Table 6-1.

Interrupt Types Associated with each IVOR ........................................................................ 165

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Table 6-2.

Interrupt and Exception Types ..............................................................................................169

Table 7-1.

Fixed Interval Timer Period Selection ...................................................................................207

Table 7-2.

Watchdog Timer Period Selection ........................................................................................207

Table 7-3.

Watchdog Timer Exception Behavior ...................................................................................208

Table 8-1.

Debug Events .......................................................................................................................215

Table 8-2.

IAC Range Mode Auto-Toggle Summary .............................................................................219

Table 8-3.

Debug Event Summary ........................................................................................................231

Table 9-1.

Instruction Categories ...........................................................................................................243

Table 9-2.

Allocated Instructions ...........................................................................................................244

Table 9-3.

Operator Precedence ...........................................................................................................247

Table 9-4.

Extended Mnemonics for addi ..............................................................................................251

Table 9-5.

Extended Mnemonics for addic ............................................................................................252

Table 9-6.

Extended Mnemonics for addic. ...........................................................................................253

Table 9-7.

Extended Mnemonics for addis ............................................................................................254

Table 9-8.

Extended Mnemonics for bc, bca, bcl, bcla ..........................................................................263

Table 9-9.

Extended Mnemonics for bcctr, bcctrl ..................................................................................268

Table 9-10.

Extended Mnemonics for bclr, bclrl ......................................................................................272

Table 9-11.

Extended Mnemonics for cmp ..............................................................................................275

Table 9-12.

Extended Mnemonics for cmpi .............................................................................................276

Table 9-13.

Extended Mnemonics for cmpl .............................................................................................277

Table 9-14.

Extended Mnemonics for cmpli ............................................................................................278

Table 9-15.

Extended Mnemonics for creqv ............................................................................................282

Table 9-16.

Extended Mnemonics for crnor .............................................................................................284

Table 9-17.

Extended Mnemonics for cror ...............................................................................................285

Table 9-18.

Extended Mnemonics for crxor .............................................................................................287

Table 9-19.

Extended Mnemonics for mbar .............................................................................................348

Table 9-20.

Extended Mnemonics for mfspr ............................................................................................356

Table 9-21.

FXM Bit Field Correspondence ............................................................................................359

Table 9-22.

Extended Mnemonics for mtcrf .............................................................................................359

Table 9-23.

Extended Mnemonics for mtspr ............................................................................................363

Table 9-24.

Extended Mnemonics for nor, nor. .......................................................................................383

Table 9-25.

Extended Mnemonics for or, or. ...........................................................................................384

Table 9-26.

Extended Mnemonics for ori .................................................................................................386

Table 9-27.

Extended Mnemonics for rlwimi, rlwimi. ..............................................................................391

Table 9-28.

Extended Mnemonics for rlwinm, rlwinm. .............................................................................392

Table 9-29.

Extended Mnemonics for rlwnm, rlwnm. ..............................................................................394

Table 9-30.

Extended Mnemonics for subf, subf., subfo, subfo. ..............................................................419

Table 9-31.

Extended Mnemonics for subfc, subfc., subfco, subfco. ......................................................420

Table 9-32.

Extended Mnemonics for tw .................................................................................................431

Tables

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Table 9-33.

Extended Mnemonics for twi ................................................................................................ 434

Table 10-1.

Register Categories ............................................................................................................. 441

Table 10-2.

Special Purpose Registers Sorted by SPR Number ............................................................ 443

Table 10-3.

Interrupt Types Associated with each IVOR ........................................................................ 485

Table A-1.

PPC440x5 Instruction Syntax Summary .............................................................................. 513

Table A-2.

Allocated Opcodes ............................................................................................................... 543

Table A-3.

Preserved Opcodes ............................................................................................................. 543

Table A-4.

Reserved-nop Opcodes ....................................................................................................... 544

Table A-5.

PPC440x5 Instructions by Opcode ...................................................................................... 545

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About This Book
This user’s manual provides the architectural overview, programming model, and detailed information about
the instruction set, registers, and other facilities of the IBM™ Book-E Enhanced PowerPC™ 440x5
(PPC440x5™) 32-bit embedded controller core.
The PPC440x5 embedded controller core features:
• Book-E Enhanced PowerPC Architecture™
• Dual-issue superscalar pipeline with dynamic branch prediction
• Separate, configurable (up to 32KB each) instruction and data caches, with cache line locking
• DSP acceleration with 24 new integer multiply-accumulate (MAC) instructions
• Memory Management Unit (MMU) with 64-entry TLB and support for page sizes of 1KB–256MB
• 64GB (36-bit) physical address capability
• 128-bit PLB interface, part of the IBM CoreConnect™ on-chip system bus architecture
• JTAG debug interface with extensive integrated debug facilities, including real-time trace

Who Should Use This Book
This book is for system hardware and software developers, and for application developers who need to
understand the PPC440x5. The audience should understand embedded system design, operating systems,
RISC microprocessing, and computer organization and architecture.

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How to Use This Book
This book describes the PPC440x5 device architecture, programming model, registers, and instruction set.
This book contains the following chapters:
• Overview on page 27
• Programming Model on page 39
• Initialization on page 83
• Instruction and Data Caches on page 93
• Memory Management on page 129
• Interrupts and Exceptions on page 153
• Timer Facilities on page 203
• Debug Facilities on page 213
• Instruction Set on page 243
• Register Summary on page 441
This book contains the following appendixes:
• Instruction Summary on page 507
• PPC440x5 Core Compiler Optimizations on page 553
To help readers find material in these chapters, this book contains:
• Contents on page 3.
• Figures on page 15.
• Tables on page 19.
• Index on page 555.

About This Book

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Notation
The manual uses the following notational conventions:
• Active low signals are shown with an overbar (Active_Low)
• All numbers are decimal unless specified in some special way.
• 0bnnnn means a number expressed in binary format.
• 0xnnnn means a number expressed in hexadecimal format.
Underscores may be used between digits.
• RA refers to General Purpose Register (GPR) RA.
• (RA) refers to the contents of GPR RA.
• (RA|0) refers to the contents of GPR RA, or to the value 0 if the RA field is 0.
• Bits in registers, instructions, and fields are specified as follows.
• Bits are numbered most-significant bit to least-significant bit, starting with bit 0.
Note: This document differs from the Book-E architecture specification in the use of bit numbering
for architected registers. Book-E defines the full, 64-bit instruction set architecture, and all registers
are shown as having bit numbers from 0 to 63, with bit 63 being the least significant. This manual
describes a 32-bit subset implementation of the architecture. Architected registers are described as
being 32 bits long, with bits numbered from 0 to 31, and with bit 31 being the least significant. When
this document refers to register bits 0 to 31, they actually correspond to bits 32 to 63 of the same register in the Book-E architecture specification.
• Xp means bit p of register, instruction, or field X
• Xp:q means bits p through q of register, instruction, or field X
• Xp,q,... means bits p, q,... of register, instruction, or field X
• X[p] means a named field p of register X.
• X[p:q] means named fields p through q of register X.
• X[p,q,...] ... means named fields p, q,... of register X.
• ¬X means the ones complement of the contents of X.
• A period (.) as the last character of an instruction mnemonic means that the instruction records status
information in certain fields of the Condition Register as a side effect of execution, as described in
Chapter 9, “Instruction Set.”
• The symbol || is used to describe the concatenation of two values. For example, 0b010 || 0b111 is the
same as 0b010111.
• xn means x raised to the n power.
•

x means the replication of x, n times (that is, x concatenated to itself n – 1 times). n0 and n1 are special
cases:
•

means a field of n bits with each bit equal to 0. Thus 50 is equivalent to 0b00000.

•

means a field of n bits with each bit equal to 1. Thus 51 is equivalent to 0b11111.

• /, //, ///, ... denotes a reserved field in an instruction or in a register.
• ? denotes an allocated bit in a register.

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• A shaded field denotes a field that is reserved or allocated in an instruction or in a register.

Related Publications
The following book describes the Book-E Enhanced PowerPC Architecture:
• Book E: PowerPC Architecture Enhanced for Embedded Applications (www.chips.ibm.com/techlib/products/powerpc/manuals/)
The following CD-ROM contains publications describing the IBM PowerPC 400 family of embedded controllers, including this manual PowerPC PPC440x5 User’s Manual, and application and technical notes.
• IBM PowerPC Embedded Processor Solutions (Order Number SC09-3032)

About This Book

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1. Overview
The IBM™ PowerPC™ 440x5 32-bit embedded processor core, referred to as the PPC440x5 core, implements the Book-E Enhanced PowerPC Architecture.
This chapter describes:
• PPC440x5 core features
• The PPC440x5 core as an implementation of the Book-E Enhanced PowerPC Architecture
• The organization of the PPC440x5 core, including a block diagram and descriptions of the functional units
• PPC440x5 core interfaces

1.1 PPC440x5 Features
The PPC440x5 core is a high-performance, low-power engine that implements the flexible and powerful
Book-E Enhanced PowerPC Architecture.
The PPC440x5 contains a dual-issue, superscalar, pipelined processing unit, along with other functional
elements required by embedded ASIC product specifications. These other functions include memory
management, cache control, timers, and debug facilities. Interfaces for custom co-processors and floating
point functions are provided, along with separate instruction and data cache array interfaces which can be
configured to various sizes (optimized for 32KB). The processor local bus (PLB) system interface has been
extended to 128 bitsand is fully compatible with the IBM CoreConnect on-chip system architecture, providing
the framework to efficiently support system-on-a-chip (SOC) designs.
In addition, the PPC440x5 core is a member of the PowerPC 400 Series of advanced embedded processors
cores, which is supported by the PowerPC Embedded Tools Program. In this program, IBM and many thirdparty vendors offer a full range of robust development tools for embedded applications. Among these are
compilers, debuggers, real-time operating systems, and logic analyzers.
PPC440x5 features include:
• High performance, dual-issue, superscalar 32-bit RISC CPU
• Superscalar implementation of the full 32-bit Book-E Enhanced PowerPC Architecture
• Seven stage, highly-pipelined micro-architecture
• Dual instruction fetch, decode, and out-of-order issue
• Out-of-order dispatch, execution, and completion
• High-accuracy dynamic branch prediction using a Branch History Table (BHT)
• Reduced branch latency using Branch Target Address Cache (BTAC)
• Three independent pipelines
• Combined complex integer, system, and branch pipeline
• Simple integer pipeline
• Load/store pipeline
• Single cycle multiply
• Single cycle multiply-accumulate (DSP instruction set extensions)

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• 9-port (6-read, 3-write) 32x32-bit General Purpose Register (GPR) file
• Hardware support for all CPU misaligned accesses
• Full support for both big and little endian byte ordering
• Extensive power management designed into core for maximum performance/power efficiency
• Primary caches
• Independently configurable instruction and data cache arrays
• Array size offerings: 32KB, 16KB, and 8KB
• Single-cycle access
• 32-byte (eight word) line size
• Highly-associative (64-way for 32KB/16KB, 32-way for 8KB)
• Write-back and write-through operation
• Control over whether stores will allocate or write-through on cache miss
• Extensive load/store queues and multiple line fill/flush buffers
• Non-blocking with up to four outstanding load misses
• Cache line locking supported
• Caches can be partitioned to provide separate regions for “transient” instructions and data
• High associativity permits efficient allocation of cache memory
• Critical word first data access and forwarding
• Cache tags and data are parity protected against soft errors.
• Memory Management Unit
• Separate instruction and data shadow TLBs
• 64-entry, fully-associative unified TLB array
• Variable page sizes (1KB-256MB), simultaneously resident in TLB
• 4-bit extended real address for 36-bit (64 GB) addressability
• Flexible TLB management with software page table search
• Storage attibute controls for write-through, caching inhibited, guarded, and byte order (endianness)
• Four user-definable storage attribute controls (for controlling CodePack™ code compression and
transient data, for example)
• TLB tags and data are parity protected against soft errors.
• Debug facilities
• Extensive hardware debug facilities incorporated into the IEEE 1149.1 JTAG port
• Multiple instruction and data address breakpoints (including range)
• Data value compare
• Single-step, branch, trap, and other debug events
• Non-invasive real-time software trace interface
• Timer facilities
• 64-bit time base
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• Decrementer with auto-reload capability
• Fixed Interval Timer (FIT)
• Watchdog Timer with critical interrupt and/or auto-reset
• Multiple core Interfaces defined by the IBM CoreConnect on-chip system architecture
• PLB interfaces
• Three independent 128-bit interfaces for instruction reads, data reads, and data writes
• Glueless attachment to 32-, 64-, or 128-bit CoreConnect system environments
• Multiple CPU:PLB frequency ratios supported (N:1, N:2, N:3)
• 6.4 GB/sec maximum data rate to CPU
• On-chip memory (OCM) integration capability over the PLB interface
• Auxiliary Processor Unit (APU) Port
• Provides functional extensions to the processor pipelines, including GPR file operations
• 128-bit load/store interface (direct access between APU and the primary data cache)
• Interface can support APU execution of all PowerPC floating point instructions
• Attachment capability for DSP co-processing such as accumulators and SIMD computation
• Enables customer-specific instruction enhancements for multimedia applications
• Device Control Register (DCR) interface for independent access to on-chip control registers
• Avoids contention for high-bandwidth PLB system bus
• Clock and power management interface
• JTAG debug interface

1.2 The PPC440x5 as a PowerPC Implementation
The PPC440x5 core implements the full, 32-bit fixed-point subset of the Book-E Enhanced PowerPC Architecture. The PPC440x5 core fully complies with these architectural specifications. The 64-bit operations of
the architecture are not supported, and the core does not implement the floating point operations, although a
floating point unit (FPU) may be attached (using the APU interface). Within the core, the 64-bit operations and
the floating point operations are trapped, and the floating point operations can be emulated using software.
See Appendix A of the Book-E Enhanced PowerPC Architecture specification for more information on 32-bit
subset implementations of the architecture.
Note: This document differs from the Book-E architecture specification in the use of bit numbering for architected registers. Specifically, Book-E defines the full, 64-bit instruction set architecture, and thus all registers
are shown as having bit numbers from 0 to 63, with bit 63 being the least significant. On the other hand, this
document describes the PPC440x5 core, which is a 32-bit subset implementation of the architecture. Accordingly, all architected registers are described as being 32 bits in length, with the bits numbered from 0 to 31,
and with bit 31 being the least significant. Therefore, when this document makes reference to register bit
numbers from 0 to 31, they actually correspond to bits 32 to 63 of the same register in the Book-E architecture specification.

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1.3 PPC440x5 Organization
The PPC440x5 core includes a seven-stage pipelined PowerPC core, which consists of a three stage, dualissue instruction fetch and decode unit with attached branch unit, together with three independent, 4-stage
pipelines for complex integer, simple integer, and load/store operations, respectively. The PPC440x5 core
also includes a memory management unit (MMU); separate instruction and data cache units; JTAG, debug,
and trace logic; and timer facilities.
Figure 1-1 illustrates the logical organization of the PPC440x5 core:
Figure 1-1. PPC440x5 Core Block Diagram

Instruction Cache
Configurable)

(Size

MMU
64-entry

ITLB

I-Cache Controller

Data Cache
(Size Configurable)

DTLB

128-bit
PLB

Load/Store Queues

D-Cache Controller

MAC

GPR
File

Simple
Integer
Pipe

4KB
BHT

GPR
File

Load
Store
Pipe

Interrupt
and
Timers

Complex
Integer
Pipe

Issue
1

Target
Addr
Cache

Clocks
and
Pwr Mgmt

Issue
0

Branch
Unit

DCR Bus
JTAG
Debug
Trace

Instruction
Unit

1.3.1 Superscalar Instruction Unit
The instruction unit of the PPC440x5 core fetches, decodes, and issues two instructions per cycle to any
combination of the three execution pipelines and/or the APU interface (see “Execution Pipelines” below, and
Auxiliary Processor Unit (APU) Port on page 36). The instruction unit includes a branch unit which provides
dynamic branch prediction using a branch history table (BHT), as well as a branch target address cache
(BTAC). These mechanisms greatly improve the branch prediction accuracy and reduce the latency of taken
branches, such that the target of a branch can usually be executed immediately after the branch itself, with no
penalty.

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1.3.2 Execution Pipelines
The PPC440x5 core contains three execution pipelines: complex integer, simple integer, and load/store.
Each pipeline consists of four stages and can access the nine-ported (six read, three write) GPR file. In order
to improve performance and avoid contention for the GPR file, there are two identical copies of it. One is dedicated to the complex integer pipeline, while the other is shared by the simple integer and the load/store pipelines.
The complex integer pipeline handles all arithmetic, logical, branch, and system management instructions
(such as interrupt and TLB management, move to/from system registers, and so on). This pipeline also
handles multiply and divide operations, and 24 DSP instructions that perform a variety of multiply-accumulate
operations. The complex integer pipeline multiply unit can perform 32-bit × 32-bit multiply operations with
single-cycle throughput and three-cycle latency;16-bit × 32-bit multiply operations have only two-cycle
latency. Divide operations take 33 cycles.
The simple integer pipeline can handle most arithmetic and logical operations which do not update the Condition Register (CR).
The load/store pipeline handles all load, store, and cache management instructions. All misaligned operations are handled in hardware, with no penalty on any operation which is contained within an aligned 16-byte
region. The load/store pipeline supports all operations to both big endian and little endian data regions.
Appendix B, “PPC440x5 Core Compiler Optimizations,” provides detailed information on instruction timings
and performance implications in the PPC440x5 core.
1.3.3 Instruction and Data Cache Controllers
The PPC440x5 core provides separate instruction and data cache controllers and arrays, which allow concurrent access and minimize pipeline stalls. The storage capacity of the cache arrays, which can range from
8KB–32KB each, depends upon the implementation. Both cache controllers have 32-byte lines, and both are
highly-associative, with 64-way set-associativity for 32KB and 16KB sizes, and 32-way set-associativity for
the 8KB size. Both caches support parity checking on the tags and data in the memory arrays, to protect
against soft errors. If a parity error is detected, the CPU will cause a machine check exception.
The PowerPC instruction set provides a rich set of cache management instructions for software-enforced
coherency. The PPC440x5 implementation also provides special debug instructions that can directly read the
tag and data arrays. See Chapter 4, “Instruction and Data Caches,” for detailed information about the instruction and data cache controllers.
The cache controllers connect to the PLB for connection to the IBM CoreConnect system-on-a-chip environment.
1.3.3.1 Instruction Cache Controller (ICC)
The ICC delivers two instructions per cycle to the instruction unit of the PPC440x5 core. The ICC also
handles the execution of the PowerPC instruction cache management instructions for coherency. The ICC
includes a speculative pre-fetch mechanism which can be configured to automatically pre-fetch a burst of up
to three additional lines upon any fetch request which misses in the instruction cache. These speculative prefetches can be abandoned if the instruction execution branches away from the original instruction stream.

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The ICC supports cache line locking, at either an 8-line or 16-line granularity, depending on cache size (16line for 32KB, 8-line for 8KB and 16KB). In addition, the notion of a “transient” portion of the cache is
supported, in which the cache can be configured such that only a limited portion is used for instruction cache
lines from memory pages that are designated by a storage attribute from the MMU as being transient in
nature. Such memory pages would contain code which is unlikely to be reused once the processor moves on
to the next series of instruction lines, and thus performance may be improved by preventing each series of
instruction lines from overwriting all of the “regular” code in the instruction cache.
1.3.3.2 Data Cache Controller (DCC)
The DCC handles all load and store data accesses, as well as the PowerPC data cache management instructions. All misaligned accesses are handled in hardware, with those accesses that are contained within a halfline (16 bytes) being handled as a single request. Load and store accesses which cross a 16-byte boundary
are broken into two separate accesses by the hardware.
The DCC interfaces to the APU port to provide direct load/store access to the data cache for APU load and
store operations. Such APU load and store instructions can access up to 16 bytes (one quadword) in a single
cycle.
The data cache can be operated in a store-in (copy-back) or write-through manner, according to the writethrough storage attribute specified for the memory page by the MMU. The DCC also supports both “storewith-allocate” and “store-without-allocate” operations, such that store operations that miss in the data cache
can either “allocate” the line in the cache by reading it in and storing the new data into the cache, or alternatively bypassing the cache on a miss and simply storing the data to memory. This characteristic can also be
specified on a page-by-page basis by a storage attribute in the MMU.
The DCC also supports cache line locking and “transient” data, in the same manner as the ICC (see Instruction Cache Controller (ICC) on page 31).
The DCC provides extensive load, store, and flush queues, such that up to three outstanding line fills and up
to four outstanding load misses can be pending, and the DCC can continue servicing subsequent load and
store hits in an out-of-order fashion. Store-gathering can also be performed on caching inhibited, writethrough, and “without-allocate” store operations, for up to 16 contiguous bytes. Finally, each cache line has
four separate “dirty” bits (one per doubleword), so that the amount of data flushed on cache line replacement
can be minimized.
1.3.4 Memory Management Unit (MMU)
The PPC440x5 supports a flat, 36-bit (64GB) real (physical) address space. This 36-bit real address is generated by the MMU, as part of the translation process from the 32-bit effective address, which is calculated by
the processor core as an instruction fetch or load/store address.
The MMU provides address translation, access protection, and storage attribute control for embedded applications. The MMU supports demand paged virtual memory and other management schemes that require
precise control of logical to physical address mapping and flexible memory protection. Working with appropriate system level software, the MMU provides the following functions:
• Translation of the 32-bit effective address space into the 36-bit real address space
• Page level read, write, and execute access control
• Storage attributes for cache policy, byte order (endianness), and speculative memory access
• Software control of page replacement strategy
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The translation lookaside buffer (TLB) is the primary hardware resource involved in the control of translation,
protection, and storage attributes. It consists of 64 entries, each specifying the various attributes of a given
page of the address space. The TLB is fully-associative; the entry for a given page can be placed anywhere
in the TLB. The TLB tag and data memory arrays are parity protected against soft errors; if a parity error is
detected, the CPU will cause a machine check exception.
Software manages the establishment and replacement of TLB entries. This gives system software significant
flexibility in implementing a custom page replacement strategy. For example, to reduce TLB thrashing or
translation delays, software can reserve several TLB entries for globally accessible static mappings. The
instruction set provides several instructions for managing TLB entries. These instructions are privileged and
the processor must be in supervisor state in order for them to be executed.
The first step in the address translation process is to expand the effective address into a virtual address. This
is done by taking the 32-bit effective address and appending to it an 8-bit Process ID (PID), as well as a 1-bit
“address space” identifier (AS). The PID value is provided by the PID register (see Chapter 5, “Memory
Management”). The AS identifier is provided by the Machine State Register (MSR, see Chapter 6, “Interrupts
and Exceptions,” which contains separate bits for the instruction fetch address space (MSR[IS]) and the data
access address space (MSR[DS]). Together, the 32-bit effective address, the 8-bit PID, and the 1-bit AS form
a 41-bit virtual address. This 41-bit virtual address is then translated into the 36-bit real address using the
TLB.
The MMU divides the address space (whether effective, virtual, or real) into pages. Eight page sizes (1KB,
4KB, 16KB, 64KB, 256KB, 1MB, 16MB, 256MB) are simultaneously supported, such that at any given time
the TLB can contain entries for any combination of page sizes. In order for an address translation to occur, a
valid entry for the page containing the virtual address must be in the TLB. An attempt to access an address
for which no TLB entry exists causes an Instruction (for fetches) or Data (for load/store accesses) TLB Error
exception.
To improve performance, both the instruction cache and the data cache maintain separate “shadow” TLBs.
The instruction shadow TLB (ITLB) contains four entries, while the data shadow TLB (DTLB) contains eight.
These shadow arrays minimize TLB contention between instruction fetch and data load/store operations. The
instruction fetch and data access mechanisms only access the main 64-entry unified TLB when a miss occurs
in the respective shadow TLB. The penalty for a miss in either of the shadow TLBs is three cycles. Hardware
manages the replacement and invalidation of both the ITLB and DTLB; no system software action is required.
Each TLB entry provides separate user state and supervisor state read, write, and execute permission
controls for the memory page associated with the entry. If software attempts to access a page for which it
does not have the necessary permission, an Instruction (for fetches) or Data (for load/store accesses)
Storage exception will occur.
Each TLB entry also provides a collection of storage attributes for the associated page. These attributes
control cache policy (such as cachability and write-through as opposed to copy-back behavior), byte order
(big endian as opposed to little endian), and enabling of speculative access for the page. In addition, a set of
four, user-definable storage attributes are provided. These attributes can be used to control various systemlevel behaviors, such as instruction compression using IBM CodePack technology. They can also be configured to control whether data cache lines are allocated upon a store miss, and whether accesses to a given
page should use the “normal” or “transient” portions of the instruction or data cache (see Chapter 4, “Instruction and Data Caches,” for detailed information about these features).
Chapter 5, “Memory Management,” describes the PPC440x5 MMU functions.

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1.3.5 Timers
The PPC440x5 contains a Time Base and three timers: a Decrementer (DEC), a Fixed Interval Timer (FIT),
and a Watchdog Timer. The Time Base is a 64-bit counter which gets incremented at a frequency either
equal to the processor core clock rate or as controlled by a separate asynchronous timer clock input to the
core. No interrupt is generated as a result of the Time Base wrapping back to zero.
The DEC is a 32-bit register that is decremented at the same rate at which the Time Base is incremented.
The user loads the DEC register with a value to create the desired interval. When the register is decremented
to zero, a number of actions occur: the DEC stops decrementing, a status bit is set in the Timer Status
Register (TSR), and a Decrementer exception is reported to the interrupt mechanism of the PPC440x5 core.
Optionally, the DEC can be programmed to reload automatically the value contained in the Decrementer
Auto-Reload register (DECAR), after which the DEC resumes decrementing. The Timer Control Register
(TCR) contains the interrupt enable for the Decrementer interrupt.
The FIT generates periodic interrupts based on the transition of a selected bit from the Time Base. Users can
select one of four intervals for the FIT period by setting a control field in the TCR to select the appropriate bit
from the Time Base. When the selected Time Base bit transitions from 0 to 1, a status bit is set in the TSR
and a Fixed Interval Timer exception is reported to the interrupt mechanism of the PPC440x5 core. The FIT
interrupt enable is contained in the TCR.
Similar to the FIT, the Watchdog Timer also generates a periodic interrupt based on the transition of a
selected bit from the Time Base. Users can select one of four intervals for the watchdog period, again by
setting a control field in the TCR to select the appropriate bit from the Time Base. Upon the first transition
from 0 to 1 of the selected Time Base bit, a status bit is set in the TSR and a Watchdog Timer exception is
reported to the interrupt mechanism of the PPC440x5 core. The Watchdog Timer can also be configured to
initiate a hardware reset if a second transition of the selected Time Base bit occurs prior to the first Watchdog
exception being serviced. This capability provides an extra measure of recoverability from potential system
lock-ups.
The timer functions of the PPC440x5 core are more fully described in Chapter 7, “Timer Facilities.”
1.3.6 Debug Facilities
The PPC440x5 debug facilities include debug modes for the various types of debugging used during hardware and software development. Also included are debug events that allow developers to control the debug
process. Debug modes and debug events are controlled using debug registers in the chip. The debug registers are accessed either through software running on the processor, or through the JTAG port.
The debug modes, events, controls, and interfaces provide a powerful combination of debug facilities for
hardware development tools, such as the RISCWatch™ debugger from IBM.
A brief overview of the debug modes and development tool support are provided below. Chapter 8, “Debug
Facilities,” provides detailed information about each debug mode and other debug resources.
1.3.6.1 Debug Modes
The PPC440x5 core supports four debug modes: internal, external, real-time-trace, and debug wait. Each
mode supports a different type of debug tool used in embedded systems development. Internal debug mode
supports software-based ROM monitors, and external debug mode supports a hardware emulator type of
debug. Real-time-trace mode uses the debug facilities to indicate events within a trace of processor execu-

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tion in real time. Debug wait mode enables the processor to continue to service real-time critical interrupts
while instruction execution is otherwise stopped for hardware debug. The debug modes are controlled by
Debug Control Register 0 (DBCR0) and the setting of bits in the Machine State Register (MSR).
Internal debug mode supports accessing architected processor resources, setting hardware and software
breakpoints, and monitoring processor status. In internal debug mode, debug events can generate debug
exceptions, which can interrupt normal program flow so that monitor software can collect processor status
and alter processor resources.
Internal debug mode relies on exception-handling software—running on the processor—along with an
external communications path to debug software problems. This mode is used while the processor continues
executing instructions and enables debugging of problems in application or operating system code. Access to
debugger software executing in the processor while in internal debug mode is through a communications port
on the processor board, such as a serial port or ethernet connection.
External debug mode supports stopping, starting, and single-stepping the processor, accessing architected
processor resources, setting hardware and software breakpoints, and monitoring processor status. In
external debug mode, debug events can architecturally “freeze” the processor. While the processor is frozen,
normal instruction execution stops, and the architected processor resources can be accessed and altered
using a debug tool (such as RISCWatch) attached through the JTAG port. This mode is useful for debugging
hardware and low-level control software problems.
1.3.6.2 Development Tool Support
The PPC440x5 provides powerful debug support for a wide range of hardware and software development
tools.
The OS Open real-time operating system debugger is an example of an operating system-aware debugger,
implemented using software traps.
RISCWatch is an example of a development tool that uses the external debug mode, debug events, and the
JTAG port to support hardware and software development and debugging.
The RISCTrace™ feature of RISCWatch is an example of a development tool that uses the real-time trace
capability of the PPC440x5.

1.4 Core Interfaces
Several interfaces to the PPC440x5 core support the IBM CoreConnect on-chip system architecture, which
simplifies the attachment of on-chip devices. These interfaces include:
• Processor local bus (PLB)
• Device configuration register (DCR) interface
• Auxiliary processor unit (APU) port
• JTAG, debug, and trace ports
• Interrupt interface
• Clock and power management interface
Several of these interfaces are described briefly in the sections below.

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1.4.1 Processor Local Bus (PLB)
There are three independent 128-bit PLB interfaces to the PPC440x5 core. Each of these interfaces includes
a 36-bit address bus and a 128-bit data bus. One PLB interface supports instruction cache reads, while the
other two support data cache reads and writes, respectively. The frequency of each PLB interface can be
independently specified, allowing an IBM CoreConnect system in which the interfaces are not all connected
as part of the same PLB and in which each PLB subsystem operates at its own frequency. Each PLB interface frequency can be configured to any value such that the ratio of the processor core frequency to the PLB
(core:PLB) is n:1, n:2, or n:3, where n is any integer greater than or equal to the denominator of the ratio.
Each of the PLB interfaces supports connection to a PLB subsystem of either 32, 64, or 128 bits. The instruction and data cache controllers handle any dynamic data bus resizing which is required when the subsystem
data width is less than the 128 bits of the PPC440x5 core PLB interfaces.
The data cache PLB interfaces make requests for 32-byte lines, as well as for 1 - 15 bytes within a 16-byte
(quadword) aligned region. A 16-byte line request is used for quadword APU load operations to caching
inhibited pages, and for quadword APU store operations to caching inhibited, write-through, or “without allocate” pages.
The instruction cache controller makes 32-byte line read requests, and also presents quadword burst read
requests for up to three 32-byte lines (six quadwords), as part of its speculative line fill mechanism.
Each of the PLB interfaces fully supports the address pipelining capabilities of the PLB, and in fact can go
beyond the pipeline depth and minimum latency which the PLB supports. Specifically, each interface
supports up to three pipelined request/acknowledge sequences prior to performing the data transfers associated with the first request. For the data cache, if each of the requests must themselves be broken into three
separate transactions (for example, for a misaligned doubleword request to a 32-bit PLB slave), then the
interface actually supports up to nine outstanding request/acknowledge sequences prior to the first data
transfer. Furthermore, each PLB interface tolerates a zero-cycle latency between the request and the
address and data acknowledge (that is, the request, address acknowledge, and data acknowledge may all
occur in the same cycle).
1.4.2 Device Control Register (DCR) Interface
The DCR interface provides a mechanism for the PPC440x5 core to setup other on-chip facilities. For
example, programmable resources in an external bus interface unit may be configured for usage with various
memory devices according to their transfer characteristics and address assignments. DCRs are accessed
through the use of the PowerPC mfdcr and mtdcr instructions.
The interface is interlocked with control signals such that it may be connected to peripheral units that may be
clocked at different frequencies from the processor core. The design allows for future expansion of the noncore facilities without changing the I/O on either the PPC440x5 core or the ASIC peripherals.
The DCR interface also allows the PPC440x5 core to communicate with peripheral devices without using the
PLB interface, thereby avoiding the impact to the primary system bus bandwidth, and without additional
segmentation of the useable address map.
1.4.3 Auxiliary Processor Unit (APU) Port
This interface provides the PPC440x5 core with the flexibility for attaching a tightly-coupled coprocessor-type
macro incorporating instructions which go beyond those provided within the processor core itself. The APU
port provides sufficient functionality for attachment of various coprocessor functions such as a fully-compliant
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PowerPC floating point unit (single or double precision), multimedia engine, DSP, or other custom function
implementing algorithms appropriate for specific system applications. The APU interface supports dual-issue
pipeline designs, and can be used with macros that contain their own register files, or with simpler macros
which use the CPU GPR file for source and/or target operands. APU load and store instructions can directly
access the PPC440x5 data cache, with operands of up to a quadword (16 bytes) in length.
The APU interface provides the capability for a coprocessor to execute concurrently with the PPC440x5 core
instructions that are not part of the PowerPC instruction set. Accordingly, areas have been reserved within
the architected instruction space to allow for these customer-specific or application-specific APU instruction
set extensions.
1.4.4 JTAG Port
The PPC440x5 JTAG port is enhanced to support the attachment of a debug tool such as the RISCWatch
product from IBM. Through the JTAG test access port, and using the debug facilities designed into the
PPC440x5 core, a debug workstation can single-step the processor and interrogate internal processor state
to facilitate hardware and software debugging. The enhancements comply with the IEEE 1149.1 specification
for vendor-specific extensions, and are therefore compatible with standard JTAG hardware for boundaryscan system testing.

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2. Programming Model
The programming model of the PPC440x5 core describes how the following features and operations of the
core appear to programmers:
• Storage addressing (including data types and byte ordering), starting on page 39
• Registers, starting on page 47
• Instruction classes, starting on page 52
• Instruction set, starting on page 55
• Branch processing, starting on page 62
• Integer processing, starting on page 69
• Processor control, starting on page 72
• User and supervisor state, starting on page 78
• Speculative access, starting on page 79
• Synchronization, starting on page 79

2.1 Storage Addressing
As a 32-bit implementation of the Book-E Enhanced PowerPC Architecture, the PPC440x5 core implements
a uniform 32-bit effective address (EA) space. Effective addresses are expanded into virtual addresses and
then translated to 36-bit (64GB) real addresses by the memory management unit (see Memory Management
on page 129 for more information on the translation process). The organization of the real address space into
a physical address space is system-dependent, and is described in the user’s manuals for chip-level products
that incorporate a PPC440x5 core.
The PPC440x5 generates an effective address whenever it executes a storage access, branch, cache
management, or translation look aside buffer (TLB) management instruction, or when it fetches the next
sequential instruction.

2.1.1 Storage Operands
Bytes in storage are numbered consecutively starting with 0. Each number is the address of the corresponding byte.
Data storage operands accessed by the integer load/store instructions may be bytes, halfwords, words, or—
for load/store multiple and string instructions—a sequence of words or bytes, respectively. Data storage operands accessed by auxiliary processor (AP) load/store instructions can be bytes, halfwords, words, doublewords, or quadwords. The address of a storage operand is the address of its first byte (that is, of its lowestnumbered byte). Byte ordering can be either big endian or little endian, as controlled by the endian storage
attribute (see Byte Ordering on page 42; also see Endian (E) on page 142 for more information on the endian
storage attribute).

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Operand length is implicit for each scalar storage access instruction type (that is, each storage access
instruction type other than the load/store multiple and string instructions). The operand of such a scalar
storage access instruction has a “natural” alignment boundary equal to the operand length. In other words,
the ‘natural’ address of an operand is an integral multiple of the operand length. A storage operand is said to
be aligned if it is aligned at its natural boundary: otherwise it is said to be unaligned.
Data storage operands for storage access instructions have the following characteristics.
Table 2-1. Data Operand Definitions
Storage Access Instruction
Type

Operand
Length

Addr[28:31] if aligned

Byte (or String)

8 bits

0bxxxx

Halfword

2 bytes

0bxxx0

Word (or Multiple)

4 bytes

0bxx00

Doubleword (AP only)

8 bytes

0bx000

Quadword (AP only)

16 bytes

0b0000

Note: An “x” in an address bit position indicates that the bit can be 0 or 1 independent of the state of other bits in the address.

The alignment of the operand effective address of some storage access instructions may affect performance,
and in some cases may cause an Alignment exception to occur. For such storage access instructions, the
best performance is obtained when the storage operands are aligned. Table 2-2 summarizes the effects of
alignment on those storage access instruction types for which such effects exist. If an instruction type is not
shown in the table, then there are no alignment effects for that instruction type.
Table 2-2. Alignment Effects for Storage Access Instructions
Storage Access
Instruction Type

Alignment Effects

Integer load/store halfword

Broken into two byte accesses if crosses 16-byte boundary (EA[28:31] = 0b1111); otherwise
no effect

Integer load/store word

Broken into two accesses if crosses 16-byte boundary (EA[28:31] > 0b1100); otherwise no
effect

Integer load/store multiple or string

Broken into a series of 4-byte accesses until the last byte is accessed or a 16-byte boundary is
reached, whichever occurs first. If bytes remain past a 16-byte boundary, resume accessing 4
bytes at a time until the last byte is accessed or the next 16-byte boundary is reached, whichever occurs first; repeat.

AP load/store halfword

Alignment exception if crosses 16-byte boundary (EA[28:31] = 0b1111); otherwise no effect
(see note)

AP load/store word

Alignment exception if crosses 16-byte boundary (EA[28:31] > 0b1100); otherwise no effect
(see note)

AP load/store doubleword

Alignment exception if crosses 16-byte boundary (EA[28:31] > 0b1000); otherwise no effect
(see note)

AP load/store quadword

Alignment exception if crosses 16-byte boundary (EA[28:31] ≠ 0b0000); otherwise no effect

Note: An auxiliary processor can specify that the EA for a given AP load/store instruction must be aligned at the operand-size
boundary, or alternatively, at a word boundary. If the AP so indicates this requirement and the calculated EA fails to meet it, the
PPC440x5 core generates an Alignment exception. Alternatively, an auxiliary processor can specify that the EA for a given AP
load/store instruction should be “forced” to be aligned, by ignoring the appropriate number of low-order EA bits and processing the
AP load/store as if those bits were 0. Byte, halfword, word, doubleword, and quadword AP load/store instructions would ignore 0, 1,
2, 3, and 4 low-order EA bits, respectively.

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Cache management instructions access cache block operands, and for the PPC440x5 core the cache block
size is 32 bytes. However, the effective addresses calculated by cache management instructions are not
required to be aligned on cache block boundaries. Instead, the architecture specifies that the associated loworder effective address bits (bits 27:31 for PPC440x5) are ignored during the execution of these instructions.
Similarly, the TLB management instructions access page operands, and—as determined by the page size—
the associated low-order effective address bits are ignored during the execution of these instructions.
Instruction storage operands, on the other hand, are always four bytes long, and the effective addresses
calculated by Branch instructions are therefore always word-aligned.
2.1.2 Effective Address Calculation
For a storage access instruction, if the sum of the effective address and the operand length exceeds the
maximum effective address of 232–1 (that is, the storage operand itself crosses the maximum address
boundary), the result of the operation is undefined, as specified by the architecture. The PPC440x5 core
performs the operation as if the storage operand wrapped around from the maximum effective address to
effective address 0. Software, however, should not depend upon this behavior, so that it may be ported to
other implementations that do not handle this scenario in the same fashion. Accordingly, software should
ensure that no data storage operands cross the maximum address boundary.
Note that since instructions are words and since the effective addresses of instructions are always implicitly
on word boundaries, it is not possible for an instruction storage operand to cross any word boundary,
including the maximum address boundary.
Effective address arithmetic, which calculates the starting address for storage operands, wraps around from
the maximum address to address 0, for all effective address computations except next sequential instruction
fetching. See Instruction Storage Addressing Modes on page 41 for more information on next sequential
instruction fetching at the maximum address boundary.
2.1.2.1 Data Storage Addressing Modes
There are two data storage addressing modes supported by the PPC440x5 core:
• Base + displacement (D-mode) addressing mode:
The 16-bit D field is sign-extended and added to the contents of the GPR designated by RA or to zero if
RA = 0; the low-order 32 bits of the sum form the effective address of the data storage operand.
• Base + index (X-mode) addressing mode:
The contents of the GPR designated by RB (or the value 0 for lswi and stswi) are added to the contents
of the GPR designated by RA, or to 0 if RA = 0; the low-order 32 bits of the sum form the effective
address of the data storage operand.
2.1.2.2 Instruction Storage Addressing Modes
There are four instruction storage addressing modes supported by the PPC440x5 core:
• I-form branch instructions (unconditional):

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The 24-bit LI field is concatenated on the right with 0b00, sign-extended, and then added to either the
address of the branch instruction if AA=0, or to 0 if AA=1; the low-order 32 bits of the sum form the effective address of the next instruction.
• Taken B-form branch instructions:
The 14-bit BD field is concatenated on the right with 0b00, sign-extended, and then added to either the
address of the branch instruction if AA=0, or to 0 if AA=1; the low-order 32 bits of the sum form the effective address of the next instruction.
• Taken XL-form branch instructions:
The contents of bits 0:29 of the Link Register (LR) or the Count Register (CTR) are concatenated on the
right with 0b00 to form the 32-bit effective address of the next instruction.
• Next sequential instruction fetching (including non-taken branch instructions):
The value 4 is added to the address of the current instruction to form the 32-bit effective address of the
next instruction. If the address of the current instruction is 0xFFFFFFFC, the PPC440x5 core wraps the
next sequential instruction address back to address 0. This behavior is not required by the architecture,
which specifies that the next sequential instruction address is undefined under these circumstances.
Therefore, software should not depend upon this behavior, so that it may be ported to other implementations that do not handle this scenario in the same fashion. Accordingly, if software wishes to execute
across this maximum address boundary and wrap back to address 0, it should place an unconditional
branch at the boundary, with a displacement of 4.
In addition to the above four instruction storage addressing modes, the following behavior applies to
branch instructions:
• Any branch instruction with LK=1:
The value 4 is added to the address of the current instruction and the low-order 32 bits of the result are
placed into the LR. As for the similar scenario for next sequential instruction fetching, if the address of the
branch instruction is 0xFFFF FFFC, the result placed into the LR is architecturally undefined, although
once again the PPC440x5 core wraps the LR update value back to address 0. Again, however, software
should not depend on this behavior, in order that it may be ported to implementations which do not handle this scenario in the same fashion.
2.1.3 Byte Ordering
If scalars (individual data items and instructions) were indivisible, there would be no such concept as “byte
ordering.” It is meaningless to consider the order of bits or groups of bits within the smallest addressable unit
of storage, because nothing can be observed about such order. Only when scalars, which the programmer
and processor regard as indivisible quantities, can comprise more than one addressable unit of storage does
the question of order arise.
For a machine in which the smallest addressable unit of storage is the 64-bit doubleword, there is no question
of the ordering of bytes within doublewords. All transfers of individual scalars between registers and storage
are of doublewords, and the address of the byte containing the high-order eight bits of a scalar is no different
from the address of a byte containing any other part of the scalar.
For the Book-E Enhanced PowerPC Architecture, as for most current computer architectures, the smallest
addressable unit of storage is the 8-bit byte. Many scalars are halfwords, words, or doublewords, which
consist of groups of bytes. When a word-length scalar is moved from a register to storage, the scalar occu-

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pies four consecutive byte addresses. It thus becomes meaningful to discuss the order of the byte addresses
with respect to the value of the scalar: which byte contains the highest-order eight bits of the scalar, which
byte contains the next-highest-order eight bits, and so on.
Given a scalar that contains multiple bytes, the choice of byte ordering is essentially arbitrary. There are 4! =
24 ways to specify the ordering of four bytes within a word, but only two of these orderings are sensible:
• The ordering that assigns the lowest address to the highest-order (“left-most”) eight bits of the scalar, the
next sequential address to the next-highest-order eight bits, and so on.
This ordering is called big endian because the “big end” (most-significant end) of the scalar, considered
as a binary number, comes first in storage. IBM RISC System/6000, IBM System/390, and Motorola
680x0 are examples of computer architectures using this byte ordering.
• The ordering that assigns the lowest address to the lowest-order (“right-most”) eight bits of the scalar, the
next sequential address to the next-lowest-order eight bits, and so on.
This ordering is called little endian because the “little end” (least-significant end) of the scalar, considered
as a binary number, comes first in storage. The Intel x86 is an example of a processor architecture using
this byte ordering.
PowerPC Book-E supports both big endian and little endian byte ordering, for both instruction and data
storage accesses. Which byte ordering is used is controlled on a memory page basis by the endian (E)
storage attribute, which is a field within the TLB entry for the page. The endian storage attribute is set to 0 for
a big endian page, and is set to 1 for a little endian page. See Memory Management on page 129 for more
information on memory pages, the TLB, and storage attributes, including the endian storage attribute.
2.1.3.1 Structure Mapping Examples
The following C language structure, s, contains an assortment of scalars and a character string. The
comments show the value assumed to be in each structure element; these values show how the bytes
comprising each structure element are mapped into storage.
struct {
int a;
/* 0x1112_1314 word */
long long b;
/* 0x2122_2324_2526_2728 doubleword */
char *c;
/* 0x3132_3334 word */
char d[7];
/* 'A','B','C','D','E','F','G' array of bytes */
short e;
/* 0x5152 halfword */
int f;
/* 0x6162_6364 word */
} s;
C structure mapping rules permit the use of padding (skipped bytes) to align scalars on desirable boundaries.
The structure mapping examples below show each scalar aligned at its natural boundary. This alignment
introduces padding of four bytes between a and b, one byte between d and e, and two bytes between e and f.
The same amount of padding is present in both big endian and little endian mappings.

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Big Endian Mapping
The big endian mapping of structure s follows (the data is highlighted in the structure mappings). Addresses,
in hexadecimal, are below the data stored at the address. The contents of each byte, as defined in structure
s, is shown as a (hexadecimal) number or character (for the string elements). The shaded cells correspond to
padded bytes.
11

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

'A'

'B'

'C'

'D'

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x1B

0x1C

0x1D

0x1E

0x1F

0x24

0x25

0x26

0x27

0x04

0x05

0x06

0x07

'E'

'F'

'G'

0x18

0x19

0x1A

0x20

0x21

0x22

0x23

Little Endian Mapping
Structure s is shown mapped little endian.
14

0x00

0x01

0x02

0x03

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

'A'

'B'

'C'

'D'

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x1B

0x1C

0x1D

0x1E

0x1F

0x24

0x25

0x26

0x27

'E'

'F'

'G'

0x18

0x19

0x1A

0x20

0x21

0x22

0x23

2.1.3.2 Instruction Byte Ordering
PowerPC Book-E defines instructions as aligned words (four bytes) in memory. As such, instructions in a big
endian program image are arranged with the most-significant byte (MSB) of the instruction word at the
lowest-numbered address.
Consider the big endian mapping of instruction p at address 0x00, where, for example, p = add r7, r7, r4:
MSB
0x00

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LSB
0x01

0x02

0x03

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On the other hand, in a little endian mapping the same instruction is arranged with the least-significant byte
(LSB) of the instruction word at the lowest-numbered address:
LSB
0x00

MSB
0x01

0x02

0x03

By the definition of PowerPC Book-E bit numbering, the most-significant byte of an instruction is the byte
containing bits 0:7 of the instruction. As depicted in the instruction format diagrams (see Instruction Formats
on page 244), this most-significant byte is the one which contains the primary opcode field (bits 0:5). Due to
this difference in byte orderings, the processor must perform whatever byte reversal is required (depending
on the particular byte ordering in use) in order to correctly deliver the opcode field to the instruction decoder.
In the PPC440x5, this reversal is performed between the memory interface and the instruction cache,
according to the value of the endian storage attribute for each memory page, such that the bytes in the
instruction cache are always correctly arranged for delivery directly to the instruction decoder.
If the endian storage attribute for a memory page is reprogrammed from one byte ordering to the other, the
contents of the memory page must be reloaded with program and data structures that are in the appropriate
byte ordering. Furthermore, anytime the contents of instruction memory change, the instruction cache must
be made coherent with the updates by invalidating the instruction cache and refetching the updated memory
contents with the new byte ordering.
2.1.3.3 Data Byte Ordering
Unlike instruction fetches, data accesses cannot be byte-reversed between memory and the data cache.
Data byte ordering in memory depends upon the data type (byte, halfword, word, and so on) of a specific data
item. It is only when moving a data item of a specific type from or to an architected register (as directed by the
execution of a particular storage access instruction) that it becomes known what kind of byte reversal may be
required due to the byte ordering of the memory page containing the data item. Therefore, byte reversal
during load or store accesses is performed between data cache (or memory, on a data cache miss, for
example) and the load register target or store register source, depending on the specific type of load or store
instruction (that is, byte, halfword, word, and so on).
Comparing the big endian and little endian mappings of structure s, as shown in Structure Mapping Examples
on page 43, the differences between the byte locations of any data item in the structure depends upon the
size of the particular data item. For example (again referring to the big endian and little endian mappings of
structure s):
• The word a has its four bytes reversed within the word spanning addresses 0x00 – 0x03.
• The halfword e has its two bytes reversed within the halfword spanning addresses 0x1C – 0x1D.
Note that the array of bytes d, where each data item is a byte, is not reversed when the big endian and little
endian mappings are compared. For example, the character 'A' is located at address 0x14 in both the big
endian and little endian mappings.
The size of the data item being loaded or stored must be known before the processor can decide whether,
and if so, how to reorder the bytes when moving them between a register and the data cache (or memory).
• For byte loads and stores, including strings, no reordering of bytes occurs, regardless of byte ordering.
• For halfword loads and stores, bytes are reversed within the halfword, for one byte order with respect to
the other.

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• For word loads and stores (including load/store multiple), bytes are reversed within the word, for one byte
order with respect to the other.
• For doubleword loads and stores (AP loads/stores only), bytes are reversed within the doubleword, for
one byte order with respect to the other.
• For quadword loads and stores (AP loads/stores only), bytes are reversed within the quadword, for one
byte order with respect to the other.
Note that this mechanism applies independent of the alignment of data. In other words, when loading a multibyte data operand with a scalar load instruction, bytes are accessed from the data cache (or memory) starting
with the byte at the calculated effective address and continuing with consecutively higher-numbered bytes
until the required number of bytes have been retrieved. Then, the bytes are arranged such that either the byte
from the highest-numbered address (for big endian storage regions) or the lowest-numbered address (for
little endian storage regions) is placed into the least-significant byte of the register. The rest of the register is
filled in corresponding order with the rest of the accessed bytes. An analogous procedure is followed for
scalar store instructions.
For load/store multiple instructions, each group of four bytes is transferred between memory and the register
according to the procedure for a scalar load word instruction.
For load/store string instructions, the most-significant byte of the first register is transferred to or from memory
at the starting (lowest-numbered) effective address, regardless of byte ordering. Subsequent register bytes
(from most-significant to least-significant, and then moving into the next register, starting with the most-significant byte, and so on) are transferred to or from memory at sequentially higher-numbered addresses. This
behavior for byte strings ensures that if two strings are loaded into registers and then compared, the first
bytes of the strings are treated as most significant with respect to the comparison.
2.1.3.4 Byte-Reverse Instructions
PowerPC Book-E defines load/store byte-reverse instructions which can access storage which is specified as
being of one byte ordering in the same manner that a regular (that is, non-byte-reverse) load/store instruction
would access storage which is specified as being of the opposite byte ordering. In other words, a load/store
byte-reverse instruction to a big endian memory page transfers data between the data cache (or memory)
and the register in the same manner that a normal load/store would transfer the data to or from a little endian
memory page. Similarly, a load/store byte-reverse instruction to a little endian memory page transfers data
between the data cache (or memory) and the register in the same manner that a normal load/store would
transfer the data to or from a big endian memory page.
The function of the load/store byte-reverse instructions is useful when a particular memory page contains a
combination of data with both big endian and little endian byte ordering. In such an environment, the Endian
storage attribute for the memory page would be set according to the predominant byte ordering for the page,
and the normal load/store instructions would be used to access data operands which used this predominant
byte ordering. Conversely, the load/store byte-reverse instructions would be used to access the data operands which were of the other (less prevalent) byte ordering.
Software compilers cannot typically make general use of the load/store byte-reverse instructions, so they are
ordinarily used only in special, hand-coded device drivers.

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2.2 Registers
This section provides an overview of the register categories and types provided by the PPC440x5. Detailed
descriptions of each of the registers are provided within the chapters covering the functions with which they
are associated (for example, the cache control and cache debug registers are described in Instruction and
Data Caches on page 93). An alphabetical summary of all registers, including bit definitions, is provided in
Register Summary on page 441
All registers in the PPC440x5 core are architected as 32 bits wide, although certain bits in some registers are
reserved and thus not necessarily implemented. For all registers with fields marked as reserved, these
reserved fields should be written as 0 and read as undefined. The recommended coding practice is to
perform the initial write to a register with reserved fields set to 0, and to perform all subsequent writes to the
register using a read-modify-write strategy: read the register; use logical instructions to alter defined fields,
leaving reserved fields unmodified; and write the register.
All of the registers are grouped into categories according to the processor functions with which they are associated. In addition, each register is classified as being of a particular type, as characterized by the specific
instructions which are used to read and write registers of that type. Finally, most of the registers contained
within the PPC440x5 core are defined by the Book-E Enhanced PowerPC Architecture, although some registers are implementation-specific and unique to the PPC440x5.
Figure 2-1 illustrates the PPC440x5 registers contained in the user programming model, that is, those registers to which access is non-privileged and which are available to both user and supervisor programs.
Figure 2-1. User Programming Model Registers
Integer Processing

Branch Control

General Purpose

Condition Register

GPR0

GPR1

Count Register

GPR2

CTR

•
•
•

Link Register
LR

GPR31
Processor Control
Integer Exception Register
XER
Timer
Time Base

SPR General 4–7
SPRG4
SPRG5
SPRG5

TBL
TBU

SPRG7
User SPR General 0
USPRG0

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Figure 2-2 on page 49 illustrates the PPC440x5 registers contained in the supervisor programming model, to
which access is privileged and which are available to supervisor programs only. See User and Supervisor
Modes on page 78 for more information on privileged instructions and register access, and the user and
supervisor programming models.

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Figure 2-2. Supervisor Programming Model Registers
Processor Control
Machine State Register

Timer
Time Base

Storage Control
Process ID

MSR

TBU

PID

Processor Version Register

TBL

PVR

Timer Control Register

Processor ID Register

TCR

PIR

Timer Status Register

Debug
Debug Status Register

Core Configuration Registers

TSR

DBSR

Decrementer

Debug Data Register

DEC

DBDR

CCR0
CCR1
Reset Configuration
RSTCFG
SPR General
SPRG0
•
•
•
SPRG7
Interrupt Processing
Exception Syndrome Register
ESR
Machine Check Syndrome Register
MCSR
Data Exception Address Register

Decrementer Auto-Reload

Critical Save/Restore Registers
CSRR0
CSRR1
Machine Check Save/Restore Registers
MCSRR0
MCSRR1
Interrupt Vector Prefix Register

DBCR0
DBCR1

IVLIM
Instruction Cache Normal Victim

IVOR0
•
•
•
IVOR15

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Data Address Compares
DAC1

INV0
DAC2
INV1
INV2
INV3
Instruction Cache Transient Victim

Data Value Compares
DVC1
DVC2

ITV0

Instruction Address Compares

ITV1

IAC1

ITV2

IAC2

ITV3

IAC3

Data Cache Victim Limit

IAC4

DVLIM

Cache Debug

Data Cache Normal Victim

Instruction Cache Debug Data Register

DNV0

ICDBDR

DNV1

Instruction Cache Debug Tag Registers

DNV2
DNV3
Data Cache Transient Victim

IVPR
Interrupt Vector Offset Registers

Debug Control Registers

Cache Control
Instruction Cache Victim Limit

Save/Restore Registers

SRR1

MMUCR

DECAR

DEAR

SRR0

MMU Control Register

DTV0
DTV1

ICDBTRH
ICDBTRL
Data Cache Debug Tag Registers
DCDBTRH
DCDBTRL

DTV2
DTV3

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Table 2-3 lists each register category and the registers that belong to each category, along with their types
and a cross-reference to the section of this document which describes them more fully. Registers that are not
part of PowerPC Book-E, and are thus specific to the PPC440x5, are shown in italics in Table 2-3. Unless
otherwise indicated, all registers have read/write access.
Table 2-3. Register Categories
Register Category

Cache Debug

Debug

Interrupt Processing

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Page

User

SPR

User

SPR

DNV0–DNV3

Supervisor

SPR

DTV0–DTV3

Supervisor

SPR

DVLIM

Supervisor

SPR

INV0–INV3

Supervisor

SPR

ITV0–ITV3

Supervisor

SPR

IVLIM

Supervisor

SPR

DCDBTRH, DCDBTRL

Supervisor, read-only

SPR

123

ICDBDR, ICDBTRH, ICDBTRL

Supervisor, read-only

SPR

109

DAC1–DAC2

Supervisor

SPR

240

DBCR0–DBCR2

Supervisor

SPR

233

DBDR

Supervisor

SPR

241

DBSR

Supervisor

SPR

238

DVC1–DVC2

Supervisor

SPR

240

IAC1–IAC4

Supervisor

SPR

239

Supervisor

DCR

GPR0–GPR31

User

GPR

XER

User

SPR

CSRR0–CSRR1

Supervisor

SPR

162

DEAR

Supervisor

SPR

164

ESR

Supervisor

SPR

166

IVOR0–IVOR15

Supervisor

SPR

164

IVPR

Supervisor

SPR

165

MCSR

Supervisor

SPR

168

MCSRR0-MCSRR1

Supervisor

SPR

163

SRR0–SRR1

Supervisor

SPR

161

Device Control Implemented outside core
Integer Processing

Type

User

Branch Control CTR

Cache Control

Model and Access

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Table 2-3. Register Categories
Register Category

Processor Control

Storage Control

Model and Access

Type

Page

CCR0

Supervisor

SPR

105

CCR1

Supervisor

SPR

105

MSR

Supervisor

MSR

159

PIR, PVR

Supervisor, read-only

SPR

RSTCFG

Supervisor, read-only

SPR

SPRG0–SPRG3

Supervisor

SPR

SPRG4–SPRG7

User, read-only; Supervisor

SPR

USPRG0

User

SPR

MMUCR

Supervisor

SPR

143

PID

Supervisor

SPR

146

DEC

Supervisor

SPR

205

DECAR

Supervisor, write-only

SPR

205

User read, Supervisor write

SPR

204

TCR

Supervisor

SPR

209

TSR

Supervisor

SPR

210

Timer TBL, TBU

2.2.1 Register Types
There are five register types contained within and/or supported by the PPC440x5 core. Each register type is
characterized by the instructions which are used to read and write the registers of that type. The following
subsections provide an overview of each of the register types and the instructions associated with them.
2.2.1.1 General Purpose Registers
The PPC440x5 core contains 32 integer general purpose registers (GPRs); each contains 32 bits. Data from
the data cache or memory can be loaded into GPRs using integer load instructions; the contents of GPRs can
be stored to the data cache or memory using integer store instructions. Most of the integer instructions reference GPRs. The GPRs are also used as targets and sources for most of the instructions which read and write
the other register types.
Integer Processing on page 69 provides more information on integer operations and the use of GPRs.
2.2.1.2 Special Purpose Registers
Special Purpose Registers (SPRs) are directly accessed using the mtspr and mfspr instructions. In addition,
certain SPRs may be updated as a side-effect of the execution of various instructions. For example, the
Integer Exception Register (XER) (see Integer Exception Register (XER) on page 70) is an SPR which is
updated with arithmetic status (such as carry and overflow) upon execution of certain forms of integer arithmetic instructions.

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SPRs control the use of the debug facilities, timers, interrupts, memory management, caches, and other
architected processor resources. Table 10-2 on page 443 shows the mnemonic, name, and number for each
SPR, in order by SPR number. Each of the SPRs is described in more detail within the section or chapter
covering the function with which it is associated. See Table 2-3 on page 50 for a cross-reference to the associated document section for each register.
2.2.1.3 Condition Register
The Condition Register (CR) is a 32-bit register of its own unique type and is divided up into eight, independent 4-bit fields (CR0–CR7). The CR may be used to record certain conditional results of various arithmetic
and logical operations. Subsequently, conditional branch instructions may designate a bit of the CR as one of
the branch conditions (see Branch Processing on page 62). Instructions are also provided for performing
logical bit operations and for moving fields within the CR.
See Condition Register (CR) on page 66 for more information on the various instructions which can update
the CR.
2.2.1.4 Machine State Register
The Machine State Register (MSR) is a register of its own unique type that controls important chip functions,
such as the enabling or disabling of various interrupt types.
The MSR can be written from a GPR using the mtmsr instruction. The contents of the MSR can be read into
a GPR using the mfmsr instruction. The MSR[EE] bit can be set or cleared atomically using the wrtee or
wrteei instructions. The MSR contents are also automatically saved, altered, and restored by the interrupthandling mechanism. See Machine State Register (MSR) on page 159 for more detailed information on the
MSR and the function of each of its bits.
2.2.1.5 Device Control Registers
Device Control Registers (DCRs) are on-chip registers that exist architecturally and physically outside the
PPC440x5 core, and thus are not specified by the Book-E Enhanced PowerPC Architecture, nor by this
user’s manual for the PPC440x5 core. Rather, PowerPC Book-E simply defines the existence of the DCR
address space and the instructions that access the DCRs, and does not define any particular DCRs. The
DCR access instructions are mtdcr (move to device control register) and mfdcr (move from device control
register), which move data between GPRs and the DCRs.
DCRs may be used to control various on-chip system functions, such as the operation of on-chip buses,
peripherals, and certain processor core behaviors.

2.3 Instruction Classes
PowerPC Book-E architecture defines all instructions as falling into exactly one of the following four classes,
as determined by the primary opcode (and the extended opcode, if any):
1. Defined
2. Allocated
3. Preserved
4. Reserved (-illegal or -nop)
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2.3.1 Defined Instruction Class
This class of instructions consists of all the instructions defined in PowerPC Book-E. In general, defined
instructions are guaranteed to be supported within a PowerPC Book-E system as specified by the architecture, either within the processor implementation itself or within emulation software supported by the system
operating software.
One exception to this is that, for implementations (such as the PPC440x5) that only provide the 32-bit subset
of PowerPC Book-E, it is not expected (and likely not even possible) that emulation of the 64-bit behavior of
the defined instructions will be provided by the system.
As defined by PowerPC Book-E, any attempt to execute a defined instruction will:
• cause an Illegal Instruction exception type Program interrupt, if the instruction is not recognized by the
implementation; or
• cause an Unimplemented Instruction exception type Program interrupt, if the instruction is recognized by
the implementation and is not a floating-point instruction, but is not supported by the implementation; or
• cause a Floating-Point Unavailable interrupt if the instruction is recognized as a floating-point instruction,
but floating-point processing is disabled; or
• cause an Unimplemented Instruction exception type Program interrupt, if the instruction is recognized as
a floating-point instruction and floating-point processing is enabled, but the instruction is not supported by
the implementation; or
• perform the actions described in the rest of this document, if the instruction is recognized and supported
by the implementation. The architected behavior may cause other exceptions.
The PPC440x5 core recognizes and fully supports all of the instructions in the defined class, with a few
exceptions. First, because the PPC440x5 is a 32-bit implementation, those operations which are defined
specifically for 64-bit operation are not supported at all, and will always cause an Illegal Instruction exception
type Program interrupt.
Second, instructions that are defined for floating-point processing are not supported within the PPC440x5
core, but may be implemented within an auxiliary processor and attached to the core using the AP interface.
If no such auxiliary processor is attached, attempting to execute any floating-point instructions will cause an
Illegal Instruction exception type Program interrupt. If an auxiliary processor which supports the floating-point
instructions is attached, the behavior of these instructions is as defined above and as determined by the
implementation details of the floating-point auxiliary processor.
Finally, there are two other defined instructions which are not supported within the PPC440x5 core. One is a
TLB management instruction (tlbiva, TLB Invalidate Virtual Address) that is specifically intended for coherent
multiprocessor systems. The other is mfapidi (Move From Auxiliary Processor ID Indirect), which is a special
instruction intended to assist with identification of the auxiliary processors which may be attached to a particular processor implementation. Since the PPC440x5 core does not support mfapidi, the means of identifying
the auxiliary processors in a PPC440x5 core-based system are implementation-dependent. Execution of
either tlbiva or mfapidi will cause an Illegal Instruction exception type Program interrupt.
2.3.2 Allocated Instruction Class
This class of instructions contains a set of primary opcodes, as well as extended opcodes for certain primary
opcodes. The specific opcodes are listed in Appendix A.3 on page 543.

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Allocated instructions are provided for purposes that are outside the scope of PowerPC Book-E, and are for
implementation-dependent and application-specific use.
PowerPC Book-E declares that any attempt to execute an allocated instruction results in one of the following
effects:
• Causes an Illegal Instruction exception type Program interrupt, if the instruction is not recognized by the
implementation
• Causes an Auxiliary Processor Unavailable interrupt if the instruction is recognized by the implementation, but allocated instruction processing is disabled
• Causes an Unimplemented Instruction exception type Program interrupt, if the instruction is recognized
and allocated instruction processing is enabled, but the instruction is not supported by the implementation
• Perform the actions described for the particular implementation of the allocated instruction. The implementation-dependent behavior may cause other exceptions.
In addition to supporting the defined instructions of PowerPC Book-E, the PPC440x5 also implements a
number of instructions which use the allocated instruction opcodes, and thus are not part of the PowerPC
Book-E architecture. Table 2-21 on page 62 identifies the allocated instructions that are implemented within
the PPC440x5 core. All of these instructions are always enabled and supported, and thus they always
perform the functions defined for them within this document, and never cause Illegal Instruction, Auxiliary
Processor Unavailable, nor Unimplemented Instruction exceptions.
The PPC440x5 also supports the use of any of the allocated opcodes by an attached auxiliary processor,
except for those allocated opcodes which have been implemented within the PPC440x5 core, as mentioned
above. Also, there is one other allocated opcode (primary opcode 31, secondary opcode 262) that has been
implemented within the PPC440x5 core and is thus not available for use by an attached auxiliary processor.
This is the opcode which was used on previous PowerPC 400 Series embedded controllers for the icbt
(Instruction Cache Block Touch) instruction. The icbt instruction is now part of the defined instruction class
for PowerPC Book-E, and uses a new opcode (primary opcode 31, secondary opcode 22). The PPC440x5
implements the new defined opcode, but also continues to support the previous opcode, in order to support
legacy software written for earlier PowerPC 400 Series implementations. The icbt instruction description in
Instruction Set on page 243 only identifies the defined opcode, although Appendix A Instruction Summary on
page 507 includes both the defined and the allocated opcode in the table which lists all the instructions by
opcode. In order to ensure portability between the PPC440x5 and future PowerPC Book-E implementations,
software should take care to only use the defined opcode for icbt, and avoid usage of the previous opcode
which is now in the allocated class.
2.3.3 Preserved Instruction Class
The preserved instruction class is provided to support backward compatibility with the PowerPC Architecture,
and/or earlier versions of the PowerPC Book-E architecture. This instruction class includes opcodes which
were defined for these previous architectures, but which are no longer defined for PowerPC Book-E.
Any attempt to execute a preserved instruction results in one of the following effects:
• Performs the actions described in the previous version of the architecture, if the instruction is recognized
by the implementation
• Causes an Illegal Instruction exception type Program interrupt, if the instruction is not recognized by the
implementation.

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The only preserved instruction recognized and supported by the PPC440x5 is the mftb (Move From Time
Base) opcode. This instruction was used in the the PowerPC Architecture to read the Time Base Upper
(TBU) and Time Base Lower (TBL) registers. PowerPC Book-E architecture instead defines TBU and TBL as
Special Purpose Registers (SPRs), and thus the mfspr (Move From Special Purpose Register) instruction is
used to read them. In order to enable legacy time base management software to be run on the PPC440x5,
the core also supports the preserved opcode of mftb. However, the mftb instruction is not included in the
various sections of this document that describe the implemented instructions, and software should take care
to use the currently architected mechanism of mfspr to read the time base registers, in order to guarantee
portability between the PPC440x5 and future implementations of PowerPC Book-E.
On the other hand, Appendix A Instruction Summary on page 507 does identify the mftb instruction as an
implemented preserved opcode in the table which lists all the instructions by opcode.
2.3.4 Reserved Instruction Class
This class of instructions consists of all instruction primary opcodes (and associated extended opcodes, if
applicable) which do not belong to either the defined, allocated, or preserved instruction classes.
Reserved instructions are available for future versions of PowerPC Book-E architecture. That is, future
versions of PowerPC Book-E may define any of these instructions to perform new functions or make them
available for implementation-dependent use as allocated instructions. There are two types of reserved
instructions: reserved-illegal and reserved-nop.
Any attempt to execute a reserved-illegal instruction will cause an Illegal Instruction exception type Program
interrupt on implementations (such as the PPC440x5) that conform to the current version of PowerPC BookE. Reserved-illegal instructions are, therefore, available for future extensions to PowerPC Book-E that would
affect architected state. Such extensions might include new forms of integer or floating-point arithmetic
instructions, or new forms of load or store instructions that affect architected registers or the contents of
memory.
Any attempt to execute a reserved-nop instruction, on the other hand, either has no effect (that is, is treated
as a no-operation instruction), or causes an Illegal Instruction exception type Program interrupt, on implementations (such as the PPC440x5) that conform to the current version of PowerPC Book-E. Because implementations are typically expected to treat reserved-nop instructions as true no-ops, these instruction opcodes are
thus available for future extensions to PowerPC Book-E which have no effect on architected state. Such
extensions might include performance-enhancing hints, such as new forms of cache touch instructions. Software would be able to take advantage of the functionality offered by the new instructions, and still remain
backwards-compatible with implementations of previous versions of PowerPC Book-E.
The PPC440x5 implements all of the reserved-nop instruction opcodes as true no-ops. The specific reservednop opcodes are listed in Appendix A.5 on page 544

2.4 Implemented Instruction Set Summary
This section provides an overview of the various types and categories of instructions implemented within the
PPC440x5. In addition, Instruction Set on page 243 provides a complete alphabetical listing of every implemented instruction, including its register transfer language (RTL) and a detailed description of its operation.
Also, Appendix A Instruction Summary on page 507 lists each implemented instruction alphabetically (and by
opcode) along with a short-form description and its extended mnemonic(s).

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Table 2-4 summarizes the PPC440x5 instruction set by category. Instructions within each category are
described in subsequent sections.
Table 2-4. Instruction Categories
Category

Subcategory

Integer

Instruction Types

Integer Storage Access

load, store

Integer Arithmetic

add, subtract, multiply, divide, negate

Integer Logical

and, andc, or, orc, xor, nand, nor, xnor, extend sign, count leading zeros

Integer Compare

compare, compare logical

Integer Select

select operand

Integer Trap

trap

Integer Rotate

rotate and insert, rotate and mask

Integer Shift

shift left, shift right, shift right algebraic
branch, branch conditional, branch to link, branch to count

Branch
Condition Register Logical

crand, crandc, cror, crorc, crnand, crnor, crxor, crxnor

move to/from SPR, move to/from DCR, move to/from MSR,
write to external interrupt enable bit, move to/from CR

Processor Control System Linkage

system call, return from interrupt, return from critical interrupt,
return from machine check interrupt

Processor Synchronization

instruction synchronize

Cache Management

data allocate, data invalidate, data touch, data zero, data flush,
data store, instruction invalidate, instruction touch

Storage Control TLB Management

read, write, search, synchronize

Storage Synchronization

memory synchronize, memory barrier

Allocated Arithmetic

multiply-accumulate, negative multiply-accumulate, multiply
halfword

Allocated Logical

detect left-most zero byte

Allocated Cache Management

data congruence-class invalidate, instruction congruence-class
invalidate

Allocated Cache Debug

data read, instruction read

Allocated

2.4.1 Integer Instructions
Integer instructions transfer data between memory and the GPRs, and perform various operations on the
GPRs. This category of instructions is further divided into seven sub-categories, described below.
2.4.1.1 Integer Storage Access Instructions
Integer storage access instructions load and store data between memory and the GPRs. These instructions
operate on bytes, halfwords, and words. Integer storage access instructions also support loading and storing
multiple registers, character strings, and byte-reversed data, and loading data with sign-extension.
Table 2-5 shows the integer storage access instructions in the PPC440x5. In the table, the syntax “[u]” indicates that the instruction has both an “update” form (in which the RA addressing register is updated with the
calculated address) and a “non-update” form. Similarly, the syntax “[x]” indicates that the instruction has both
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an “indexed” form (in which the address is formed by adding the contents of the RA and RB GPRs) and a
“base + displacement” form (in which the address is formed by adding a 16-bit signed immediate value (specified as part of the instruction) to the contents of GPR RA. See the detailed instruction descriptions in Instruction Set on page 243.
Table 2-5. Integer Storage Access Instructions
Loads
Byte
lbz[u][x]

Halfword
lha[u][x]
lhbrx
lhz[u][x]

Word
lwarx
lwbrx
lwz[u][x]

Stores
Multiple/String
lmw
lswi
lswx

Byte
stb[u][x]

Halfword
sth[u][x]
sthbrx

Word
stw[u][x]
stwbrx
stwcx.

Multiple/String
stmw
stswi
stswx

2.4.1.2 Integer Arithmetic Instructions
Arithmetic operations are performed on integer or ordinal operands stored in registers. Instructions that
perform operations on two operands are defined in a three-operand format; an operation is performed on the
operands, which are stored in two registers. The result is placed in a third register. Instructions that perform
operations on one operand are defined in a two-operand format; the operation is performed on the operand in
a register and the result is placed in another register. Several instructions also have immediate formats in
which one of the source operands is a field in the instruction.
Most integer arithmetic instructions have versions that can update CR[CR0] and/or XER[SO, OV] (Summary
Overflow, Overflow), based on the result of the instruction. Some integer arithmetic instructions also update
XER[CA] (Carry) implicitly. See Integer Processing on page 69 for more information on how these instructions update the CR and/or the XER.
Table 2-6 lists the integer arithmetic instructions in the PPC440x5. In the table, the syntax “[o]” indicates that
the instruction has both an “o” form (which updates the XER[SO,OV] fields) and a “non-o” form. Similarly, the
syntax “[.]” indicates that the instruction has both a “record” form (which updates CR[CR0]) and a “nonrecord” form.
Table 2-6. Integer Arithmetic Instructions
Add
add[o][.]
addc[o][.]
adde[o][.]
addi
addic[.]
addis
addme[o][.]
addze[o][.]

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subf[o][.]
subfc[o][.]
subfe[o][.]
subfic
subfme[o][.]
subfze[o][.]

Multiply

Divide

mulhw[.]
mulhwu[.]
mulli
mullw[o][.]

divw[o][.]
divwu[o][.]

Negate

neg[o][.]

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2.4.1.3 Integer Logical Instructions
Table 2-7 lists the integer logical instructions in the PPC440x5. See Integer Arithmetic Instructions on
page 57 for an explanation of the “[.]” syntax.
Table 2-7. Integer Logical Instructions
And
and[.]
andi.
andis.

And with
complement

andc[.]

Nand

nand[.]

or[.]
ori
oris

Or with
complement

orc[.]

Nor

Xor

nor[.]

xor[.]
xori
xoris

Equivalence

eqv[.]

Extend sign

extsb[.]
extsh[.]

Count
leading
zeros
cntlzw[.]

2.4.1.4 Integer Compare Instructions
These instructions perform arithmetic or logical comparisons between two operands and update the CR with
the result of the comparison.
Table 2-8 lists the integer compare instructions in the PPC440x5.
Table 2-8. Integer Compare Instructions
Arithmetic
cmp
cmpi

Logical
cmpl
cmpli

2.4.1.5 Integer Trap Instructions
Table 2-9 lists the integer trap instructions in the PPC440x5.
Table 2-9. Integer Trap Instructions
Trap
tw
twi

2.4.1.6 Integer Rotate Instructions
These instructions rotate operands stored in the GPRs. Rotate instructions can also mask rotated operands.
Table 2-10 lists the rotate instructions in the PPC440x5. See Integer Arithmetic Instructions on page 57 for an
explanation of the “[.]” syntax.
Table 2-10. Integer Rotate Instructions
Rotate and Insert
rlwimi[.]

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rlwinm[.]
rlwnm[.]

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2.4.1.7 Integer Shift Instructions
Table 2-11 lists the integer shift instructions in the PPC440x5. Note that the shift right algebraic insructions
implicitly update the XER[CA] field. See Integer Arithmetic Instructions on page 57 for an explanation of the
“[.]” syntax.
Table 2-11. Integer Shift Instructions
Shift Left
slw[.]

Shift Right
srw[.]

Shift Right
Algebraic
sraw[.]
srawi[.]

2.4.1.8 Integer Select Instruction
Table 2-12 lists the integer select instruction in the PPC440x5. The RA operand is 0 if the RA field of the
instruction is 0, or is the contents of GPR[RA] otherwise.
Table 2-12. Integer Select Instruction
Integer Select
isel

2.4.2 Branch Instructions
These instructions unconditionally or conditionally branch to an address. Conditional branch instructions can
test condition codes set in the CR by a previous instruction and branch accordingly. Conditional branch
instructions can also decrement and test the Count Register (CTR) as part of branch determination, and can
save the return address in the Link Register (LR).The target address for a branch can be a displacement from
the current instruction address or an absolute address, or contained in the LR or CTR.
See Branch Processing on page 62 for more information on branch operations.
Table 2-13 lists the branch instructions in the PPC440x5. In the table, the syntax “[l]” indicates that the
instruction has both a “link update” form (which updates LR with the address of the instruction after the
branch) and a “non-link update” form. Similarly, the syntax “[a]” indicates that the instruction has both an
“absolute address” form (in which the target address is formed directly using the immediate field specified as
part of the instruction) and a “relative” form (in which the target address is formed by adding the specified
immediate field to the address of the branch instruction).
Table 2-13. Branch Instructions
Branch
b[l][a]
bc[l][a]
bcctr[l]
bclr[l]

2.4.3 Processor Control Instructions
Processor control instructions manipulate system registers, perform system software linkage, and synchronize processor operations. The instructions in these three sub-categories of processor control instructions are
described below.
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2.4.3.1 Condition Register Logical Instructions
These instructions perform logical operations on a specified pair of bits in the CR, placing the result in another
specified bit. The benefit of these instructions is that they can logically combine the results of several comparison operations without incurring the overhead of conditional branching between each one. Software performance can significantly improve if multiple conditions are tested at once as part of a branch decision.
Table 2-14 lists the condition register logical instructions in the PPC440x5.
Table 2-14. Condition Register Logical Instructions
crand
crandc
creqv
crnand

crnor
cror
crorc
crxor

2.4.3.2 Register Management Instructions
These instructions move data between the GPRs and control registers in the PPC440x5.
Table 2-15 lists the register management instructions in the PPC440x5.
Table 2-15. Register Management Instructions
CR
mcrf
mcrxr
mfcr
mtcrf

DCR

MSR
mfmsr
mtmsr
wrtee
wrteei

mfdcr
mtdcr

SPR
mfspr
mtspr

2.4.3.3 System Linkage Instructions
These instructions invoke supervisor software level for system services, and return from interrupts.
Table 2-16 lists the system linkage instructions in the PPC440x5.
Table 2-16. System Linkage Instructions
rfi
rfci
rfmci
sc

2.4.3.4 Processor Synchronization Instruction
Tne processor synchronization instruction, isync, forces the processor to complete all instructions preceding
the isync before allowing any context changes as a result of any instructions that follow the isync. Additionally, all instructions that follow the isync will execute within the context established by the completion of all
the instructions that precede the isync. See Synchronization on page 79 for more information on the
synchronizing effect of isync.
Table 2-17 shows the processor synchronization instruction in the PPC440x5.
Table 2-17. Processor Synchronization Instruction
isync

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2.4.4 Storage Control Instructions
These instructions manage the instruction and data caches and the TLB of the PPC440x5 core. Instructions
are also provided to synchronize and order storage accesses. The instructions in these three sub-categories
of storage control instructions are described below.
2.4.4.1 Cache Management Instructions
These instructions control the operation of the data and instruction caches. Instructions are provided to fill,
flush, invalidate, or zero data cache blocks, where a block is defined as a 32-byte cache line. instructions are
also provided to fill or invalidate instruction cache blocks.
Table 2-18 lists the cache management instructions in the PPC440x5.
Table 2-18. Cache Management Instructions
Data Cache
dcba
dcbf
dcbi
dcbst
dcbt
dcbtst
dcbz

Instruction Cache

icbi
icbt

2.4.4.2 TLB Management Instructions
The TLB management instructions read and write entries of the TLB array, and search the TLB array for an
entry which will translate a given virtual address. There is also an instruction for synchronizing TLB updates
with other processors, but since the PPC440x5 core is intended for use in uni-processor environments, this
instruction performs no operation on the PPC440x5.
Table 2-19 lists the TLB management instructions in the PPC440x5. See Integer Arithmetic Instructions on
page 57 for an explanation of the “[.]” syntax.
Table 2-19. TLB Management Instructions
tlbre
tlbsx[.]
tlbsync
tlbwe

2.4.4.3 Storage Synchronization Instructions
The storage synchronization instructions allow software to enforce ordering amongst the storage accesses
caused by load and store instructions, which by default are “weakly-ordered” by the processor. “Weaklyordered” means that the processor is architecturally permitted to perform loads and stores generally out-oforder with respect to their sequence within the instruction stream, with some exceptions. However, if a
storage synchronization instruction is executed, then all storage accesses prompted by instructions
preceding the synchronizing instruction must be performed before any storage accesses prompted by
instructions which come after the synchronizing instruction. See Synchronization on page 79 for more information on storage synchronization.

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Table 2-17 shows the storage synchronization instructions in the PPC440x5.
Table 2-20. Storage Synchronization Instructions
msync
mbar

2.4.5 Allocated Instructions
These instructions are not part of the PowerPC Book-E architecture, but they are included as part of the
PPC440x5 core. Architecturally, they are considered allocated instructions, as they use opcodes which are
within the allocated class of instructions, which the PowerPC Book-E architecture identifies as being available
for implementation-dependent and/or application-specific purposes. However, all of the allocated instructions
which are implemented within the PPC440x5 core are “standard” for IBM’s family of PowerPC embedded
controllers, and are not unique to the PPC440x5.
The allocated instructions implemented within the PPC440x5 are divided into four sub-categories, and are
shown in Table 2-21. See Integer Arithmetic Instructions on page 57 for an explanation of the “[.]” and “[o]”
syntax.
Table 2-21. Allocated Instructions
Arithmetic
Negative
Multiply-Accumulate

Multiply-Accumulate
macchw[o][.]
macchws[o][.]
macchwsu[o][.]
macchwu[o][.]
machhw[o][.]
machhws[o][.]
machhwsu[o][.]
machhwu[o][.]
maclhw[o][.]
maclhws[o][.]
maclhwsu[o][.]
maclhwu[o][.]

nmacchw[o][.]
nmacchws[o][.]
nmachhw[o][.]
nmachhws[o][.]
nmaclhw[o][.]
nmaclhws[o][.]

Logical

Cache
Management

Cache
Debug

Multiply Halfword

mulchw[.]
mulchwu[.]
mulhhw[.]
mulhhwu[.]
mullhw[.]
mullhwu[.]

dlmzb[.]

dccci
iccci

dcread
icread

2.5 Branch Processing
The four branch instructions provided by PPC440x5 are summarized in Table 2.4.2 on page 59. In addition,
each of these instructions is described in detail in Instruction Set on page 243. The following sections provide
additional information on branch addressing, instruction fields, prediction, and registers.
2.5.1 Branch Addressing
The branch instruction (b[l][a]) specifies the displacement of the branch target address as a 26-bit value (the
24-bit LI field right-extended with 0b00). This displacement is regarded as a signed 26-bit number covering an
address range of ±32MB. Similarly, the branch conditional instruction (bc[l][a]) specifies the displacement as
a 16-bit value (the 14-bit BD field right-extended with 0b00). This displacement covers an address range of
±32KB.

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For the relative form of the branch and branch conditional instructions (b[l] and bc[l], with instruction field
AA = 0), the target address is the address of the branch instruction itself (the Current Instruction Address, or
CIA) plus the signed displacement. This address calculation is defined to “wrap around” from the maximum
effective address (0xFFFFFFFF) to 0x0000 0000, and vice-versa.
For the absolute form of the branch and branch conditional instructions (ba[l] and bca[l], with instruction field
AA = 1), the target address is the sign-extended displacement. This means that with absolute forms of the
branch and branch conditional instructions, the branch target can be within the first or last 32MB or 32KB of
the address space, respectively.
The other two branch instructions, bclr (branch conditional to LR) and bcctr (branch conditional to CTR), do
not use absolute nor relative addressing. Instead, they use indirect addressing, in which the target of the
branch is specified indirectly as the contents of the LR or CTR.
2.5.2 Branch Instruction BI Field
Conditional branch instructions can optionally test one bit of the CR, as indicated by instruction field BO[0]
(see BO field description below). The value of instruction field BI specifies the CR bit to be tested (0-31). The
BI field is ignored if BO[0] = 1. The branch (b[l][a]) instruction is by definition unconditional, and hence does
not have a BI instruction field. Instead, the position of this field is part of the LI displacement field.
2.5.3 Branch Instruction BO Field
The BO field specifies the condition under which a conditional branch is taken, and whether the branch decrements the CTR. The branch (b[l][a]) instruction is by definition unconditional, and hence does not have a BO
instruction field. Instead, the position of this field is part of the LI displacement field.
Conditional branch instructions can optionally test one bit in the CR. This option is selected when BO[0] = 0; if
BO[0] = 1, the CR does not participate in the branch condition test. If the CR condition option is selected, the
condition is satisfied (branch can occur) if the CR bit selected by the BI instruction field matches BO[1].
Conditional branch instructions can also optionally decrement the CTR by one, and test whether the decremented value is 0. This option is selected when BO[2] = 0; if BO[2] = 1, the CTR is not decremented and does
not participate in the branch condition test. If CTR decrement option is selected, BO[3] specifies the condition
that must be satisfied to allow the branch to be taken. If BO[3] = 0, CTR ≠ 0 is required for the branch to
occur. If BO[3] = 1, CTR = 0 is required for the branch to occur.
Table 2-22 summarizes the usage of the bits of the BO field. BO[4] is further discussed in Branch Prediction
on page 64
Table 2-22. BO Field Definition
BO Bit

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Description

BO[0]

CR Test Control
0 Test CR bit specified by BI field for value specified by BO[1]
1 Do not test CR

BO[1]

CR Test Value
0 If BO[0] = 0, test for CR[BI] = 0.
1 If BO[0] = 0, test for CR[BI] = 1.

BO[2]

CTR Decrement and Test Control
0 Decrement CTR by one and test whether the decremented CTR
satisfies the condition specified by BO[3].
1 Do not decrement CTR, do not test CTR.

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Table 2-22. BO Field Definition (continued)
BO Bit

Description

BO[3]

CTR Test Value
0 If BO[2] = 0, test for decremented CTR ≠ 0.
1 If BO[2] = 0, test for decremented CTR = 0.

BO[4]

Branch Prediction Reversal
0 Apply standard branch prediction.
1 Reverse the standard branch prediction.

Table 2-23 lists specific BO field contents, and the resulting actions; z represents a mandatory value of zero,
and y is a branch prediction option discussed in Branch Prediction on page 64
Table 2-23. BO Field Examples
BO Value
0000y

Description
Decrement the CTR, then branch if the decremented CTR ≠ 0 and CR[BI]=0.

0001y

Decrement the CTR, then branch if the decremented CTR = 0 and CR[BI] = 0.

001zy

Branch if CR[BI] = 0.

0100y

Decrement the CTR, then branch if the decremented CTR ≠ 0 and CR[BI] = 1.

0101y

Decrement the CTR, then branch if the decremented CTR=0 and CR[BI] = 1.

011zy

Branch if CR[BI] = 1.

1z00y

Decrement the CTR, then branch if the decremented CTR ≠ 0.

1z01y

Decrement the CTR, then branch if the decremented CTR = 0.

1z1zz

Branch always.

2.5.4 Branch Prediction
Conditional branches might be taken or not taken; if taken, instruction fetching is re-directed to the target
address. If the branch is not taken, instruction fetching simply falls through to the next sequential instruction.
The PPC440x5 core attempts to predict whether or not a branch is taken before all information necessary to
determine the branch direction is available. This action is called branch prediction. The core can then prefetch
instructions down the predicted path. If the prediction is correct, performance is improved because the branch
target instruction is available immediately, instead of having to wait until the branch conditions are resolved. If
the prediction is incorrect, then the prefetched instructions (which were fetched from addresses down the
“wrong” path of the branch) must be discarded, and new instructions fetched from the correct path.
The PPC440x5 core combines the static prediction mechanism defined by PowerPC Book-E, together with a
dynamic branch prediction mechanism, in order to provide correct branch prediction as often as possible. The
dynamic branch prediction mechanism is an implementation optimization, and is not part of the architecture,
nor is it visible to the programming model. Appendix B PPC440x5 Core Compiler Optimizations on page 553
provides additional information on the dynamic branch prediction mechanism.
The static branch prediction mechanism enables software to designate the “preferred” branch prediction via
bits in the instruction encoding. The “default” static branch prediction for conditional branches is as follows:
Predict that the branch is to be taken if ((BO[0] ∧ BO[2]) ∨ s) = 1
where s is bit 16 of the instruction (the sign bit of the displacement for all bc forms, and zero for all bclr and
bcctr forms). In other words, conditional branches are predicted taken if they are “unconditional” (i.e., they do
not test the CR nor the CTR decrement, and are always taken), or if their branch displacement is “negative”
(i.e., the branch is branching “backwards” from the current instruction address). The standard prediction for
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this case derives from considering the relative form of bc, often used at the end of loops to control the number
of times that a loop is executed. The branch is taken each time the loop is executed except the last, so it is
best if the branch is predicted taken. The branch target is the beginning of the loop, so the branch displacement is negative and s = 1. Because this situation is most common, a branch is taken if s = 1.
If branch displacements are positive, s = 0, then the branch is predicted not taken. Also, if the branch instruction is any form of bclr or bcctr except the “unconditional” form, then s = 0, and the branch is predicted not
taken.
There is a peculiar consequence of this prediction algorithm for the absolute forms of bc (bca and bcla). As
described in Branch Addressing on page 62, if s = 1, the branch target is in high memory. If s = 0, the branch
target is in low memory. Because these are absolute-addressing forms, there is no reason to treat high and
low memory differently. Nevertheless, for the high memory case the standard prediction is taken, and for the
low memory case the standard prediction is not taken.
Another bit in the BO field allows software further control over branch prediction. Specifically, BO[4] is the
prediction reversal bit. If BO[4] = 0, the default prediction is applied. If BO[4] = 1, the reverse of the default
prediction is applied. For the cases in Table 2-23 where BO[4] = y, software can reverse the default prediction by setting y to 1. This should only be done when the default prediction is likely to be wrong. Note that for
the “branch always” condition, reversal of the default prediction is not allowed, as BO[4] is designated as z for
this case, meaning the bit must be set to 0 or the instruction form is invalid.
2.5.5 Branch Control Registers
There are three registers in the PPC440x5 which are associated with branch processing, and they are
described in the following sections.
2.5.5.1 Link Register (LR)
The LR is written from a GPR using mtspr, and can be read into a GPR using mfspr. The LR can also be
updated by the “link update” form of branch instructions (instruction field LK = 1). Such branch instructions
load the LR with the address of the instruction following the branch instruction (4 + address of the branch
instruction). Thus, the LR contents can be used as a return address for a subroutine that was entered using a
link update form of branch. The bclr instruction uses the LR in this fashion, enabling indirect branching to any
address.
When being used as a return address by a bclr instruction, bits 30:31 of the LR are ignored, since all instruction addresses are on word boundaries.
Access to the LR is non-privileged.

Figure 2-3. Link Register (LR)
0:31

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Link Register contents

Target address of bclr instruction

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2.5.5.2 Count Register (CTR)
The CTR is written from a GPR using mtspr, and can be read into a GPR using mfspr. The CTR contents
can be used as a loop count that gets decremented and tested by conditional branch instructions that specify
count decrement as one of their branch conditions (instruction field BO[2] = 0). Alternatively, the CTR
contents can specify a target address for the bcctr instruction, enabling indirect branching to any address.
Access to the CTR is non-privileged.

Figure 2-4. Count Register (CTR)
0:31

Used as count for branch conditional with decrement instructions, or as target address for bcctr
instructions

Count

2.5.5.3 Condition Register (CR)
The CR is used to record certain information (“conditions”) related to the results of the various instructions
which are enabled to update the CR. A bit in the CR may also be selected to be tested as part of the condition
of a conditional branch instruction.
The CR is organized into eight 4-bit fields (CR0–CR7), as shown in Figure 2-5. Table 2-24 lists the instructions which update the CR.
Access to the CR is non-privileged.
CR2

CR0
0

CR6

CR4
11 12

CR1

15 16

CR3

19 20

23 24

CR5

27 28

CR7

Figure 2-5. Condition Register (CR)
0:3

CR0

Condition Register Field 0

4:7

CR1

Condition Register Field 1