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User Manual: Motherboard Quanta BD3G DABD3GMB6E0 - Schematics. Free.

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5

4

3

2

BD3G BLOCK DIAGRAM
DDRII-SODIMM1
DDR II 667 MHZ

D

CLOCK GENERATOR

NBGFX_CLK

Griffin Processor

ICS9LPRS476AKLFT

NBGPP_CLK

DDRII-SODIMM2

RTM880N-795

REF 14MHz

PG 3

(638 S1g2 socket)
PG 4,5,6,7

HDMI

PCI-E, 1X (port2)

LVDS

HDMI
LVDS(2ch)

PG 20

S-VIDEO

PCI-E, 1X (port0)
USB2.0 (P3)

21mm X 21mm, 528pin BGA

PG 18

CRT TV LVDS HDMI

PCI-E, 1X (port1)

CRT
PG 18

C

MXM Module

PCI-E X16

PG 21

8040T(10/100)/8055(Giga)

PG 10,11,12,13

PCI-E, 1X (port3)
USB2.0 (P6)

A_LINK (X4)

LAYER 1 : TOP
LAYER 2 : GND
LAYER 3 : IN1
LAYER 4 : IN2
LAYER 5 : VCC
LAYER 6 : BOT

PG 35

+2.5V

+2.5V

+1.5V

+1.5V

+1.2V

+1.2V

+1.8VSUS
+1.8V

PG 24

+SMDDR_VTERM

Mini Card (WLAN)
PG 25

+3VPCU
+3V_S5
+3VSUS
+3V
+5VPCU
+5V

MINI CARD (HD Video Decoder)
PG 25
NEW CARD
PG 25

D

Daughter Board
PG 37

MMB Board

+1.2V_S5

RJ45

PG 24

RX780/RS780M/RS780MC

NB CORE
(1.0~1.2V)

+1.1V_NB

HT_LINK

PG 19

PCB STACK UP

CPU CORE PG 34

PCIE 100MHz
USB 48MHz

SLG8SP628VTR

SBLINK_CLK

PG 8,9

+NB_CORE
+1.35V_VDDHTTX

HOST 200MHz

CPU_CLK

AMD S1g2

PG 8,9

1

CPU_CORE1
CPU_CORE2
CPU VDDNB_CORE

+1.8VSUS
SMDDR
VTERM

USB Board
PG 36

Touch Pad board

3V/5V
Touch Pad board
(with Fingerprinter)

C

PG 33

SBSRC_CLK

SATA0

SATA - HDD1
PG 27

USB2.0 (P2)
SATA1

SATA - HDD2

CCD

USB2.0 (P0)

USB2.0 I/O Ports X1

USB2.0 (P1)

USB2.0 I/O Ports X1

USB2.0 (P7)

USB2.0 I/O Ports X1

(MB)

PG 28

SB700
USB2.0 (P4)

Fingerprint

USB2.0 (P5)

Felica

USB2.0 (P8)

Bluetooth

PG 19

PG 27
SATA4

SATA - ODD

(DB)

PG 28

PG 27

PG 28
PG 28
PG 28

(DB)

PG 28
B

B

SATA2

21mm X 21mm, 528pin BGA

PG ??

Azalia

4.5W(Ext)

CX20561
PORT-A

NAND FLASH CARD

Azalia Audio Codec

4.3W(Int)

IDE /133

PG ??

Device

IDSEL#

REQ#/GNT#

OZ129

AD17

REQ0# / GNT0#

PG 14,15,16,17,18

PCI Bus 33MHz

PCI ROUTING TABLE
Interrupt

PG 22

PORT-B

E - SATA

Speaker Amplifier
G1441R51U

PG 22

LPC

INTE#

H.P/
SPDIF
PG 23

EC

O2Micro OZ129T

WPCE775

MIC
JACK
PG 23

INT.
MIC
PG 23

INT.
S.P.
PG 22

MDC CONN

FM Radio

PG 23

PG 23

MDC
Board

A

A

PG 29

PG 26

RJ11

SPI

PROJECT : BD3G

5

IEEE1394 CN.

Card Reader

PG 26

PG 26

VR
PG 23

FAN
PG 6
4

Keyboard
PG 30

Flash
ROM
PG 29

Touch
Pad
PG 28

CIR

Kill SW

PG 28

Quanta Computer Inc.

PG 30
3

Size

Document Number

Date:

Thursday, May 29, 2008

Rev
2A

BLOCK DIAGRAM
2

Sheet
1

1

of

42

5

4

3

From AC,Battery VIN
+5VPCU +3VPCU
From PWM SYS_HWPG(PCU)
From Power Button NBSWON#
From EC
S5_ON
+5V_S5

From
From
From
From SB to
From

EC
EC
SB
EC
EC

From PWM
From EC

C

From PWM
From EC
From PWM

From EC

From
From
From
From

SB
SB
SB
SB

Items

+3V_S5
+1.2V_S5
>10ms
RSMRST#
>100ms
DNBSWON#
PCIE_WAKE#
SUSB#,SUSC#
SUSON
SUSON
+3VSUS +1.8VSUS SMDDR_VREF SMDDR_VTERM
HWPG_1.8V (SUS)
MAINON
MAINON
+5V +3V +2.5V +1.8V +1.5V +NB_CORE +1.1V_NB +1.35V_VDDHTTX
HWPG_1.5V,HWPG_2.5V,GFXPG(MAIN) HWPG_1.2_NB
VRON
CPU_CORE0, CPU_CORE1, CPU VDDNB_CORE, +1.2V
VRM_PWRGD (CPU)
HWPG
ECPWROK
SB_PWRGD
NB_PWRGD
CPU_PWRGD
PLTRST# PCIRST#
CPU_LDT_RST#
CPU_LDT_STOP#

1

BOM naming rule

BD3G Power On Sequence

D

2

BTO

Name

1

CIR

Function

v

CIR@

2

HDMI port

v

HDM@

3

HDMI transmitter

v

SI@

Silicon image SiI 1392/1932

4

HDMI-CEC

v

CEC@

Renesas R8C/1B

5

Discrete VGA

EV@

External VGA stuff

6

UMA

IV@

Internal VGA stuff

7

New Card

NEW@

8

RJ11

9

v

Description
D

MD@

Modem

RJ45-10/100

40@

Marvell 8040T(10/100)

10

RJ45-1000

55@

Marvell 8055(Giga)

11

Option for RJ45-10/100 and RJ45-1000

40@55@

Option for 8040/8055

12

TV

13

Cardbus

14

FM transmitter

15

Mainstream ID LED

16

Low cost ID LED

17

CCD

v

CCD@

18

INT MIC

v

I_MIC@

19

AMD Hyper Flash

HF@

Only for AMD platform

20

North bridge(690MC/RS780MC)

MC@

Only for AMD platform

21

North bridge(RX780)

RX@

Only for AMD platform

22

PowerXpress

PX@

Only for AMD platform

23

PowerXpress with UMA SKU

PX@IV@

Only for AMD platform

24

PowerXpress with Discrete VGA SKU

PX@EV@

Only for AMD platform

25

Power player/Power Shift

PP@

Only for AMD platform

v

C

TV@
CB@

v

FM@
MID@
LID@

0ns~30ns
99ms~108ms

B

B

EC SMBUS Table

*Note: EC will sampling SUSB# &
SUSC# every 5ms.

Battery

AMD SB700 SMBUS Table
SB700 SDATA0/SCLK0(+3V)

CLK GEN

RAM

V

V

Mini Card (HD-Decoder)

V

EC775 SDATA1/SCLK1(+3VPCU)
Mini-card(WL) New Card

V

HDMI

CPU thermal Sensor

EC EEPROM

EC775 SDATA2/SCLK2(+3VPCU)

V

Touch Sensor

HDMI CEC

V

EC775 SDATA3/SCLK3(+3VPCU)

V

VGA thermal Sensor

V
V

V

V

A

A

SB700 SDATA1/SCLK1(+3V_S5)

V

SB700 SDATA2/SCLK2(+3V_S5)
Power
Reserve MOS ckt

EC775 SDATA4/SCLK4(+3VPCU)
Power

+3V

+3V

+3V

V

V

V

+3V (Atheros)

V

+3V

+3V_S5

V

V

Reserve MOS ckt

+3VPCU

+3V

+3VPCU

+3V

X

V

X

V

+3VPCU

+5VPCU

X

V

PROJECT : BD3G
Quanta Computer Inc.
Size

Document Number

Rev
2A

SYSTEM INFORMATION
Date:
5

4

3

2

Thursday, May 29, 2008
1

Sheet

2

of

42

5

4

3

2

1

CLK_GEN_SLG8SP628
+3V

03

+3V_CLK_VDD

+1.2V

+1.2V_CLK_VDDIO

L22

L23

BK1608HS600
D

BK1608HS600
C242

C236

C233

C219

C232

C535

C218

C231

C235

C221

C230

C234

C222

C216

C217

10u/10V_8

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

10u/10V_8

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

ICS9LPRS480

P/N : ALPRS480000

SLG8SP628

P/N : AL8SP628000

RTM880N-796

P/N : AL000880000

Clock chip has internal serial terminations
for differencial pairs, external resistors are
reserved for debug purpose.

Place within 0.5"
of CLKGEN

R147

U2

+3V

+3V_CLK_48

+3V_CLK_VDD

L21
BK1608HS600
C220
0.1u/10V_4

10/25 modify it

4
16
26
35
40
48
55
56
63

VDDDOT
VDDSRC
VDDATIG
VDDSB_SRC
VDDSATA
VDDCPU
VDDHTT
VDDREF
VDD48

11
17
25
34
47

VDDSRC_IO0
VDDSRC_IO1
VDDATIG_IO
VDDSB_SRC_IO
VDDCPU_IO

50
49

ATIG0T
ATIG0C
ATIG1T
ATIG1C

30
29
28
27

NBGFX_CLKP_R
NBGFX_CLKN_R
MXM_REFCLKP_R
MXM_REFCLKN_R

SB_SRC0T
SB_SRC0C
SB_SRC1T
SB_SRC1C

37
36
32
31

SBLINK_CLKP_R
SBLINK_CLKN_R
SBSRC_CLKP_R
SBSRC_CLKN_R

Q39
*RHU002N06

CLKREQ4#

1

3

CLKREQ_LAN#

24

+3V

2

R300

Q30
*RHU002N06

*10K_4
CLKREQ2#

1

3

B:(10/25) Add WLAN & LAN CLKREQ circuit (BOI request)

CLKREQ_WLAN#

CG_XIN
CG_XOUT

25
7,8,14,25
7,8,14,25

T25
NEW_CLKREQ#
CLKREQ2#

25 NEW_CLKREQ#

GND48
GNDDOT
GNDSRC0
GNDSRC1
GNDATIG
GNDSB_SRC
GNDSATA
GNDCPU
GNDHTT
GNDREF

61
62

X1
X2

2
3

PCLK_SMB
PDAT_SMB
CLK_PD#

B

1
7
10
18
24
33
43
46
52
60

SRC0T
SRC0C
SRC1T
SRC1C
SRC2T
SRC2C
SRC3T
SRC3C
SRC4T
SRC4C

22
21
20
19
15
14
13
12
9
8

NBGPP_CLKP_R
NBGPP_CLKN_R
CLK_PCIE_NEW_R
CLK_PCIE_NEW#_R
CLK_PCIE_MINI_R
CLK_PCIE_MINI#_R
CLK_PCIE_MINI2_R
CLK_PCIE_MINI2#_R
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R

SRC6T/SATAT
SRC6C/SATAC
SRC7T/27M_SS
SRC7C/27M_NS

42
41
6
5

HTT0T/66M
HTT0C/66M

54
53

T33

CLKREQ4#

51

48MHz_0

64

23
45
44
39
38

REF0/SEL_HTT66
REF1/SEL_SATA
REF2/SEL_27

59
58
57

SMBCLK
SMBDAT
PD#
CLKREQ0#
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#

12/8 change from 20p to 33p
C225

33p/50V_4
SLG8SP628

+3V_CLK_VDD
8.2K_4
8.2K_4

NEW_CLKREQ#
CLK_PD#

C223

Y1
14.318MHZ

33p/50V_4
1

R148
R146

CG_XIN

2

1
3

2 0X2
4

RP15

1
3
1
3

2 0X2
4
2 EV@0X2
4

1
3
1
3

2 0X2
4
2 0X2
4

1
3
1
3
1
3
1
3
1
3

2
4
2
4
2
4
2
4
2
4

1
3

2 0X2
4

RP14

RP18
RP17

RP12
RP11
RP2
RP1
RP3

CPUCLKP
CPUCLKN

1

To CPU

MXM_REFCLKP
MXM_REFCLKN
SBLINK_CLKP
SBLINK_CLKN
SBSRC_CLKP
SBSRC_CLKN

To NB

21
21
C

11
11
13
13

To NB

11/4 check RX781 , RX781 not use

To SB

RX780 only

NBGPP_CLKP
NBGPP_CLKN

NEW@0X2 CLK_PCIE_NEW
CLK_PCIE_NEW#
0X2
CLK_PCIE_WLAN
CLK_PCIE_WLAN#
0X2
CLK_PCIE_MINICARD
CLK_PCIE_MINICARD#
CLK_PCIE_LAN
0X2
CLK_PCIE_LAN#

11
11

NBGPP_CLKP
NBGPP_CLKN

11
11

To NB

CLK_PCIE_NEW 25
To New Card
CLK_PCIE_NEW# 25
CLK_PCIE_WLAN 25
To Mini PCIE Slot
CLK_PCIE_WLAN#
25
CLK_PCIE_MINICARD
25
To Mini PCIE Slot
CLK_PCIE_MINICARD#
25
CLK_PCIE_LAN 24
To LAN Controller
CLK_PCIE_LAN# 24

T27
T32
T21
T22
NBHT_REFCLKP_R
NBHT_REFCLKN_R
CLK_48M_USB_R
SEL_HTT66
SEL_SATA
SEL_27

RP13

R446

R141
R138

33_4

NBHT_REFCLKP
NBHT_REFCLKN
CLK_48M_USB

NBHT_REFCLKP
NBHT_REFCLKN
CLK_48M_USB

158/F_4
90.9/F_4

EXT_NB_OSC

EXT_NB_OSC

C541
*10p/50V_4

RX780

10/17 Add 10p for EMI issue (Suggestion by Seligo)

To NB
To SB

11

To NB

NB CLOCK INPUT TABLE

Rb
C201
*10p/50V_4

14

11
11

B

Ra

CG_XOUT

2

4
4

NBGFX_CLKP
NBGFX_CLKN

SBLINK_CLKP
SBLINK_CLKN
SBSRC_CLKP
SBSRC_CLKN

*0X2

CPUCLKP
CPUCLKN

RS780/RX780 for VGA

NBGFX_CLKP
NBGFX_CLKN
MXM_REFCLKP
MXM_REFCLKN

RS780

1.8V

1.1V

Ra

82.5R

158R

Rb

130R

90.9R

2

1

QFN64

TGND0
TGND1
TGND2
TGND3
TGND4
TGND5
TGND6
TGND7
TGND8
TGND9

2

R498
*10K_4

*261/F_4

RP16

65
66
67
68
69
70
71
72
73
74

+1.2V_CLK_VDDIO

+3V

CPUCLKP_R
CPUCLKN_R

CPUK8_0T
CPUK8_0C

C

D

NB CLOCKS

RX780

HT_REFCLKP

100M DIFF

100M DIFF

RS780

HT_REFCLKN

100M DIFF

100M DIFF

REFCLK_P

14M SE (1.8V)

14M SE (1.1V)

REFCLK_N

NC

GFX_REFCLK

100M DIFF

100M DIFF(IN/OUT)*

GPP_REFCLK

100M DIFF

NC or 100M DIFF OUTPUT

GPPSB_REFCLK

100M DIFF

vref

New Card CLKREQ#
RES CHIP 130 1/16W +-1%(0402)L-F -->CS11302FB15
RES CHIP 158 1/16W +-1%(0402) -->CS11582FB00
RES CHIP 90.9 1/16W +-1%(0402) -->CS09092FB15
RES CHIP 82.5 1/16W +-1%(0402) -->CS08252FB11

CLOCKS name

A

RX780

RS780

NBGFX_CLKP
NBGFX_CLKN

RP1001 STUFF

MXM_REFCLKP
MXM_REFCLKN

RP66 STUFF

NBGPP_CLKP
NBGPP_CLKN

SBLINK_CLKP
SBLINK_CLKN

RP1001 STUFF

Clock pin function

100M DIFF

+3V_CLK_VDD

to NB for VGA reference clock
R442
8.2K_4

RP1005 STUFF

RP1003 STUFF

RP66 NC

to M82-S external reference clock -RX780 only

RP1005 NC

to NB for RX780 for PCIEX2 interface reference clock only
RS780 is internal share with AC-LINK clock,RS780 not need

RP1003 STUFF

SEL_SATA
SEL_HTT66
SEL_27

A

1

66 MHz 3.3V single ended HTT clock

SEL_HTT66
R136
*8.2K_4

R445
8.2K_4

R443
8.2K_4

0*

100 MHz differential HTT clock

1*

100 MHz non-spreading differential SRC clock

0

100 MHz spreading differential SRC clock

1

27MHz and 27M SS outputs

0*

100 MHz SRC clock

PROJECT : BD3G

SEL_SATA

to NB for AC-LINK reference clock

Quanta Computer Inc.

SEL_27
Size

Document Number

Date:

Thursday, May 29, 2008

5

4

3

Rev
1A

CLOCK GENERATOR_SLG8SP628

* default
2

Sheet
1

3

of

42

5

4

3

BLM21PG221SN1D(220,100M,2A)_8

+1.2V

L19

+1.2V_VLDT
R469

CPU CLK

LS0805-100M-N
C166
10u/6.3V_8

C170
4.7U/6.3V_6

C167
0.22u/6.3V_4

C168
3300p/50V_4

3
3

0_8

R467

HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7
HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15

D

HT_NB_CPU_CAD_H[15..0]

9 HT_NB_CPU_CAD_H[15..0]

HT_NB_CPU_CAD_L[15..0]

9 HT_NB_CPU_CAD_L[15..0]

HT_NB_CPU_CLK_H[1..0]

9 HT_NB_CPU_CLK_H[1..0]

HT_NB_CPU_CLK_L[1..0]

9 HT_NB_CPU_CLK_L[1..0]

HT_NB_CPU_CTL_H[1..0]

9 HT_NB_CPU_CTL_H[1..0]

HT_NB_CPU_CTL_L[1..0]

9 HT_NB_CPU_CTL_L[1..0]

HT_CPU_NB_CAD_H[15..0]

9 HT_CPU_NB_CAD_H[15..0]

HT_CPU_NB_CAD_L[15..0]

9 HT_CPU_NB_CAD_L[15..0]

HT_CPU_NB_CLK_H[1..0]

9 HT_CPU_NB_CLK_H[1..0]

HT_CPU_NB_CLK_L[1..0]

9 HT_CPU_NB_CLK_L[1..0]

HT_CPU_NB_CTL_H[1..0]

9 HT_CPU_NB_CTL_H[1..0]

HT_CPU_NB_CTL_L[1..0]

9 HT_CPU_NB_CTL_L[1..0]

+1.2V_VLDT
+1.2V_VLDT
+1.2V_VLDT
+1.2V_VLDT

4.7U/6.3V_6
4.7U/6.3V_6
0.22u/6.3V_4
180p/50V_4

D1
D2
D3
D4
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5

HT_NB_CPU_CLK_H0
HT_NB_CPU_CLK_L0
HT_NB_CPU_CLK_H1
HT_NB_CPU_CLK_L1

HT LINK

N1
P1
P3
P4

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15

L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15

J3
J2
J5
K5

HT_NB_CPU_CTL_H0
HT_NB_CPU_CTL_L0
HT_NB_CPU_CTL_H1
HT_NB_CPU_CTL_L1

C

VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3

L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1

L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1

L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1

L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1

AE2
AE3
AE4
AE5

+1.2V_VLDT 4.7U/6.3V_6
+1.2V_VLDT 0.22u/6.3V_4
+1.2V_VLDT 180p/50V_4
+1.2V_VLDT

CPUCLKP
CPUCLKN

AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7
HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15

Y1
W1
Y4
Y3

HT_CPU_NB_CLK_H0
HT_CPU_NB_CLK_L0
HT_CPU_NB_CLK_H1
HT_CPU_NB_CLK_L1

CPUCLKIN

C572
C573
C571

CPUCLKP
CPUCLKN

R133

R130
R129

CPU_LDT_REQ#_CPU

300_4

R460

CPU_PWRGD

300_4

R127

03

+1.8V

A9
A8

CPU_LDT_RST#
CPU_PWRGD
CPU_LDT_STOP#
CPU_LDT_REQ#_CPU

B7
A7
F10
C6

CPU_SIC
CPU_SID
CPU_ALERT

AF4
AF5
AE6

SideBand Temp sense I2C

CPU_HTREF0
44.2/F_4
CPU_HTREF1
44.2/F_4
place them to CPU within 1.5"

R471
R470

+1.2V_VLDT

*0.1u/10V_4

F8
F9

CPUCLKIN
CPUCLKIN#

3900p/25V_4
3900p/25V_4

F6
E6

34 CPU_VDD1_FB_H
34 CPU_VDD1_FB_L

Y6
AB6
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
T16

R128
R134

+1.8VSUS

510/F_4
510/F_4

300_4
300_4
300_4
*300_4
*300_4

+1.8VSUS

R463

THERMDC
THERMDA

VDD0_FB_H
VDD0_FB_L

VDDIO_FB_H
VDDIO_FB_L

VDD1_FB_H
VDD1_FB_L

VDDNB_FB_H
VDDNB_FB_L

DBRDY
TMS
TCK
TRST_L
TDI
TEST23

E9
E8

DBREQ_L
TDO
TEST28_H
TEST28_L
TEST17
TEST16
TEST15
TEST14

TEST25_H
TEST25_L

AB8
AF7
AE7
AE8
AC8
AF8

TEST21
TEST20
TEST24
TEST22
TEST12
TEST27

C2
AA6

TEST7
TEST10
TEST8
TEST29_H
TEST29_L

TEST9
TEST6

A3
A5
B3
B5
C1

5/13 follow AMD design guide 1.03
stuff R675

1/30 leakage issue , change +1.8Vsus to +1.8V

A6
A4

CPU_SVC_R
CPU_SVD_R

AF6
AC7
AA8

CPU_THERMTRIP_L#
CPU_PROCHOT_L#
CPU_MEMHOT_L#

W7
W8

CPU_THERMDC
CPU_THERMDA

W9
Y9

VDDIO_FB_H
VDDIO_FB_L

10/9 AMD suggest
1. pull up CPU_PWRGD to +1.8SUS
2. pop R5563 pull up to +1.8SUS

0_4 H_THERMDC
0_4 H_THERMDA

R113
R111

HT_REF0
HT_REF1

TEST18
TEST19

0_4

12/4 Add 0.1u for AMD CPU

M11
W18

D

THERMTRIP_L
PROCHOT_L
MEMHOT_L

SIC
SID
ALERT_L

H10
G9

CPUTEST25H
CPUTEST25L

CPUTEST21
CPUTEST20
CPUTEST24
CPUTEST22
CPUTEST12
CPUTEST27

R676
R675
R678
R677
R679

300_4

HT_CPU_NB_CTL_H0
HT_CPU_NB_CTL_L0
HT_CPU_NB_CTL_H1
HT_CPU_NB_CTL_L1

RESET_L
PWROK
LDTSTOP_L
LDTREQ_L

AD7

CPUTEST18
CPUTEST19

R671
R672

SVC
SVD

CLKIN_H
CLKIN_L

G10
AA9
AC9
AD9
AF9
CPUTEST23

KEY1
KEY2

VDDA1
VDDA2

R6
P6

34 CPU_VDD0_FB_H
34 CPU_VDD0_FB_L

*300_4
*300_4

+1.8V

C762

U12D
W/S= 15 mil/20mil
+CPUVDDA
+CPUVDDA

11,13 CPU_LDT_RST#
13 CPU_PWRGD
11,13 CPU_LDT_STOP#

SOCKET_638_PIN

300_4
300_4

+CPUVDDA

CPUCLKIN#

169/F_4

C174
C175

R453

R2
R3
T5
R5

CPU_LDT_RST#
CPU_LDT_STOP#

4/24 remove C762 to meet PWRGD timing spec

U12A
C583
C582
C581
C580

1

CPUCLKP
CPUCLKN

Keep trace from resisor to CPU within 0.6"
keep trace from caps to CPU within 1.2"

+1.2V_VLDT

0_8

2

W/S= 15 mil/20mil

+CPUVDDA

+2.5V

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

RSVD10
RSVD9
RSVD8
RSVD7
RSVD6

VDDIO_FB_H 36
VDDIO_FB_L 36

H6
G6

CPU_VDDNB_FB_H
CPU_VDDNB_FB_L

34
34

E10 CPU_DBREQ#
AE9 CPU_TDO
J7
H8

CPUTEST28H
CPUTEST28L

D7
E7
F7
C7

CPUTEST17
CPUTEST16
CPUTEST15
CPUTEST14

T8
T5
T4
T3
*300_4
*300_4

R673
R674

C3
K8

12/7 Add 300ohm to GND for AMD request
C4
CPUTEST29H
CPUTEST29L

C9
C8

C

T10
T7

H18
H19
AA7
D5
C5

SOCKET_638_PIN

CNTR_VREF
C172
R126

+3V

20K/F_4

CNTR_VREF

+1.8VSUS

11

CPU_LDT_RST#

CPU_LDT_RST_HTPA#
3
Q20
BSS138_NL/SOT23

1

14

G3
*SHORT_ PAD1

14

SB_SCLK3

SB_SCLK3

SB_SDATA3

SB_SDATA3

R286

*0_4

R282

*0_4

R473
1K/F_4

R691
300_4

THERM_ALERT#_R

1
3
5
7
9
11
13
15
17
19
21
23

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

CPU_SIC

CPU_SID

C741 *0.1u/10V_4

4/16 change CPU_LDT_RST# shot pad location to G3

2

C796
*100p/50V_4

R468
390_4

2

CPU_LDT_REQ#

0_6

C795
*100p/50V_4

R472
390_4

2

R131
0_4

1

R122

+1.8VSUS

R123
1K/F_4

2
*BSS138_NL/SOT23
3

2/4 pull up R691 CPU_BDREQ# to avoid noise cause system shut down

CNTR_VREF

34.8K/F_4
CNTR_VREF

Q19
CPU_LDT_REQ#_CPU 1

HDT Connector

+1.8VSUS

10/9 AMD suggest
remove MOS and connect directly

+3V

0.1u/10V_4

R132

Q38
1

3

2
4
6
8
10
12
14
16
18
20
22
24
25

KEY

CPU_ALERT

CPU_LDT_RST_HTPA#

for debug only
*BSS138_NL/SOT23

B

CN26

B

2/4 reserve C795,C796 change R122 to 0 0603
*HDT CONN

2

300_4

CPU_MEMHOT_L#

3

2

29,34 CPU_COREPG

Q35
MMBT3904
CPU_MEMHOT#
1

FDV301N

10K/F_4

CPU_PROCHOT_L#

1

*10K_4

Q36

3
MMBT3904

CPU_PROCHOT#

R454

300_4

CPU_THERMTRIP_L#

29

R139

3 R144

1

*0_6

CPU_PROCHOT_SB#

13

100K_6

CPU_SVC
CPU_SVD
CPU_PWRGD_SVID_REG

0_4
0_4
0_4

CPU_SVC 34
CPU_SVD 34
CPU_PWRGD_SVID_REG

34

*220_4
*220_4
*220_4

VID Override Circuit

SVC

SVD

0
0
1
1

0
1
0
1

Voltage Output

1.4V
1.2V
1.0V
0.8V

+3V

CPU Thermal monitor

CPU_THERMTRIP#
SYS_SHDN#

R457
R461
R125
R455
R464
R124

10/26 modify it

Q26

0_4

CPU_SVC_R
CPU_SVD_R
CPU_PWRGD

Serial VID

1K/F_4
1K/F_4

+3V

14

R115
330_4

2/19 change G781 to G786P81U

33

+3V

R107

R110

R106

10K_4

10K_4

200_6

MMBT3904

2

R687

+1.8VSUS

2

300_4

*BAS316

R140
1K_4

R686
R458

2

+1.8VSUS

D3

*10K_4

CPU_MEMHOT# 8,14

+3V
R456

R135

1

R452

R462
R459

+1.8VSUS

Q21

+1.8VSUS

+1.8VSUS

VFIX MODE

10K/F_4

Q11
RHU002N06

Q18
MMBT3904

2

R447

3

+1.8VSUS

1/31 leakage issue ,add R687, no stuff R686
+1.8VSUS

LM86VCC

THER_SHD#

1

3

SYS_SHDN#

+3V

CPU FAN

29

2ND_MBCLK

3

33

C147

1

0.1u/10V_4

R524
+3V
U1

10K_4
+5V

SYSFANON#
R504
*10K_4

2

A

29 2ND_MBDATA

2.2u/6.3V_6

29

VFAN

CN35

U17
CPUFAN#_ON_R 1

3

Q46

4

VO
GND
/FON GND
GND
VSET GND

VIN

3
5
6
7
8

TH_FAN_POWER R508
C753

0_6 TH_FAN_POWER_R

C752

1
2
3

3

1

+3V

+3V

3

15 THERM_ALERT#

D9
D92
2

G995/Pin1- internal pull high (+5V)
D9
D93
3

2
2

1 *VPORTFANSIG

+3V

1 *VPORTTH_FAN_POWER_R

5

4

1

3

1
2

C154

DXN

3

2200p/50V_4

GND

5

H_THERMDC

SDA

DXP

6

ALERT#

*10K_4
THERM_ALERT#_R

OVERT#

2/18 G781 reverse R718 0 ohm for
A
Griffin CPU

*0_4

G786P81U

ADDRESS: 98H

Q13

R116

10/30 change to G781

2/4 reserve D92,D93 for FAN

VCC

R718

*8.2K_4
*2N7002E-LF

FANPWR = 1.6*VSET

R112

SCLK

7

4
R114

5

PTI_CWY030-B0G1Z
10u/10V_8 0.01u/16V_4

ME2N7002D
*0_4
THER_SHD#

8

4

G995

R500

H_THERMDA

Q6
RHU002N06

C750

2

1

FANSIG

2

21

+5V

2

29
+3V

PROJECT : BD3G
10K_4

THER_SHD#

MAX6657,G781P8,W83L771G


Layout Note:Routing 10:10 mils and away
from noise source with ground gard
2

Quanta Computer Inc.

Size

Document Number

Date:

Thursday, May 29, 2008

Rev
1A

S1G2 HT,CTL I/F 1/3
Sheet
1

4

of

42

A

B

+SMDDR_VTERM

R448
R451
T23

39.2/F_4 M_ZP
39.2/F_4 M_ZN

7,8 MEM_MA0_CS#0
7,8 MEM_MA0_CS#1
T37
T30

VTT1
VTT2
VTT3
VTT4

AF10
AE10

MEMZP
MEMZN

MEM_MA_RESET# H16

MEM:CMD/CTRL/CLK VTT5
VTT6
VTT7
VTT8
VTT9

VTT_SENSE
MEMVREF

W17 MEMVREF_CPU

RSVD_M2

B18 MEM_MB_RESET#

T136

MEM_MA1_ODT0
MEM_MA1_ODT1

W26
W23
Y26 MEM_MB1_ODT0

CPU_MA1_CS_L0
CPU_MA1_CS_L1

T20
U19
U20
V20

R142
MEM_MB0_ODT0 7,8
2K/F_4
MEM_MB0_ODT1 7,8
T31

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

V26
W25
U22

MEM_MB0_CS#0 7,8
MEM_MB0_CS#1 7,8
T36

J22
J20

MA_CKE0
MA_CKE1

7,8 MEM_MA_CKE0
7,8 MEM_MA_CKE1
CPU_MA_CLK_H5
CPU_MA_CLK_L5

N19
N20
E16
F16
Y16
AA16
CPU_MA_CLK_H4 P19
CPU_MA_CLK_L4 P20

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB_CKE0
MB_CKE1

J25
H26

MEM_MB_CKE0 7,8
MEM_MB_CKE1 7,8
CPU_MB_CLK_H5
CPU_MB_CLK_HL5

MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15

MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4

MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4

P22
R22
A17
A18
AF18
AF17
R26
R25

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

7,8 MEM_MA_BANK0
7,8 MEM_MA_BANK1
7,8 MEM_MA_BANK2

R20
R23
J21

MA_BANK0
MA_BANK1
MA_BANK2

MB_BANK0
MB_BANK1
MB_BANK2

R24
U26
J26

MEM_MB_BANK0 7,8
MEM_MB_BANK1 7,8
MEM_MB_BANK2 7,8

7,8 MEM_MA_RAS#
7,8 MEM_MA_CAS#
7,8 MEM_MA_WE#

R19
T22
T24

MA_RAS_L
MA_CAS_L
MA_WE_L

MB_RAS_L
MB_CAS_L
MB_WE_L

U25
U24
U23

MEM_MB_RAS# 7,8
MEM_MB_CAS# 7,8
MEM_MB_WE# 7,8

T29
T43
MEM_MA_CLK1_P
MEM_MA_CLK1_N
MEM_MA_CLK7_P
MEM_MA_CLK7_N
T42
T39
7,8 MEM_MA_ADD[0..15]
7
7
7
7

3

MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15

R137
*0_4

2K/F_4
CPU_VTT_SENSE 36

MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1

CPU_MB_CLK_H4
CPU_MB_CLK_L4

MEM:DATA

Reserved

C200
0.1u/10V_4

C208
1000p/50V_4

11/05 change to RC0402-C

T34
T28
MEM_MB_CLK1_P 7
MEM_MB_CLK1_N 7
MEM_MB_CLK7_P 7
MEM_MB_CLK7_N 7
T35
T40
MEM_MB_ADD[0..15] 7,8

SOCKET_638_PIN

2

+SMDDR_VTERM

C534
4.7U/6.3V_6

7 MEM_MB_DM[0..7]

Place close to socket
C546
4.7U/6.3V_6

C545
4.7U/6.3V_6

C536
4.7U/6.3V_6

C186
0.22u/6.3V_4

C539
0.22u/6.3V_4

C544
0.22u/6.3V_4

C193
0.22u/6.3V_4

+SMDDR_VTERM

C542
C190
1000p/50V_4 1000p/50V_4

C538
1000p/50V_4

C184
1000p/50V_4

C183
180p/50V_4

C181
180p/50V_4

04

U12C

R143

Y10 CPU_VTT_SENSE

E

Processor Memory Interface

+SMDDR_VREF

750 mA

RSVD_M1

MB0_ODT0
MB0_ODT1
MB1_ODT0

7 MEM_MB_DATA[0..63]

+1.8VSUS

W10
AC10
AB10
AA10
A10

T19
V22
U21
V19

4

7,8 MEM_MA0_ODT0
7,8 MEM_MA0_ODT1
T41
T38

D10
C10
B10
AD10

D

+SMDDR_VTERM

U12B

PLACE THEM CLOSE TO
CPU WITHIN 1"

+1.8VSUS

C

C543
180p/50V_4

C537
180p/50V_4

Close to CPU within 1500 mils

7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7

MEM_MB_DQS0_P
MEM_MB_DQS0_N
MEM_MB_DQS1_P
MEM_MB_DQS1_N
MEM_MB_DQS2_P
MEM_MB_DQS2_N
MEM_MB_DQS3_P
MEM_MB_DQS3_N
MEM_MB_DQS4_P
MEM_MB_DQS4_N
MEM_MB_DQS5_P
MEM_MB_DQS5_N
MEM_MB_DQS6_P
MEM_MB_DQS6_N
MEM_MB_DQS7_P
MEM_MB_DQS7_N

MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7

A12
B16
A22
E25
AB26
AE22
AC16
AD12

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

E12
C15
E19
F24
AC24
Y19
AB16
Y13

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

MEM_MA_DATA[0..63] 7

MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63

4

3

MEM_MA_DM[0..7] 7

MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7

2

MEM_MA_DQS0_P
MEM_MA_DQS0_N
MEM_MA_DQS1_P
MEM_MA_DQS1_N
MEM_MA_DQS2_P
MEM_MA_DQS2_N
MEM_MA_DQS3_P
MEM_MA_DQS3_N
MEM_MA_DQS4_P
MEM_MA_DQS4_N
MEM_MA_DQS5_P
MEM_MA_DQS5_N
MEM_MA_DQS6_P
MEM_MA_DQS6_N
MEM_MA_DQS7_P
MEM_MA_DQS7_N

7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7

MEM_MA_CLK7_P
MEM_MB_CLK7_P

SOCKET_638_PIN
C540
1.5p/50V_4

C238
1.5p/50V_4

1

1

MEM_MA_CLK7_N
MEM_MB_CLK7_N
MEM_MA_CLK1_P
MEM_MB_CLK1_P
C533
1.5p/50V_4

C532
1.5p/50V_4

PROJECT : BD3G

MEM_MA_CLK1_N

Quanta Computer Inc.

MEM_MB_CLK1_N
Size

Document Number

Rev
1A

S1G2 DDRII MEMORY I/F 2/3
Date:
A

B

C

D

Sheet

Thursday, May 29, 2008
E

5

of

42

5

4

3

2

1

05

U12F
U12E

CPU_CORE0

D

CPU VDDNB_CORE

G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11

VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23

K16
M16
P16
T16
V16

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

3A

+1.8VSUS

2A

C

CPU_CORE1

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

+1.8VSUS

SOCKET_638_PIN

AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

CPU_CORE0

C188
22u/6.3V_8

BOTTOM SIDE DECOUPLING
C197
22u/6.3V_8

C192
22u/6.3V_8

C198
22u/6.3V_8

C179
0.22u/6.3V_4

C180
0.01u/16V_4

C178
180p/50V_4
D

CPU_CORE1

C196
22u/6.3V_8

C187
22u/6.3V_8

C199
22u/6.3V_8

CPU VDDNB_CORE

C207
22u/6.3V_8

C195
22u/6.3V_8

C177
0.22u/6.3V_4

C182
0.01u/16V_4

C191
180p/50V_4

C185
0.01u/16V_4

+1.8VSUS

C194
C206
22u/6.3V_8 22u/6.3V_8

C209
22u/6.3V_8

C212
22u/6.3V_8

C211
C527
0.22u/6.3V_4 0.22u/6.3V_4

C210
180p/50V_4

C250
180p/50V_4

C

DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE
+1.8VSUS

C525
4.7U/6.3V_6

C516
4.7U/6.3V_6

C515
4.7U/6.3V_6

C526
4.7U/6.3V_6

C239
0.22u/6.3V_4

C247
0.22u/6.3V_4

+1.8VSUS

C251
C241
C248
0.22u/6.3V_4 0.22u/6.3V_4 0.01u/16V_4

C245
0.01u/16V_4

C237
180p/50V_4

SOCKET_638_PIN
B

B

PROCESSOR POWER AND GROUND

A

A

PROJECT : BD3G
Quanta Computer Inc.
Size

Document Number

Rev
1A

S1G2 PWR & GND 3/3
Date:
5

4

3

2

Thursday, May 29, 2008

Sheet
1

6

of

42

5

4

3

2

C

5
5
5
5

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

13
31
51
70
131
148
169
188

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

5
5
5
5
5
5
5
5

MEM_MA_DQS0_N
MEM_MA_DQS1_N
MEM_MA_DQS2_N
MEM_MA_DQS3_N
MEM_MA_DQS4_N
MEM_MA_DQS5_N
MEM_MA_DQS6_N
MEM_MA_DQS7_N

11
29
49
68
129
146
167
186

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

30
32
164
166

CK0
CK0
CK1
CK1

79
80

CKE0
CKE1

MEM_MA_RAS#
MEM_MA_CAS#
MEM_MA_WE#
MEM_MA0_CS#0
MEM_MA0_CS#1

108
113
109
110
115

RAS
CAS
WE
S0
S1

5,8 MEM_MA0_ODT0
5,8 MEM_MA0_ODT1

114
119

ODT0
ODT1

5,8
5,8
5,8
5,8
5,8

DIM1_SA0
DIM1_SA1
B

10
26
52
67
130
147
170
185

MEM_MA_DQS0_P
MEM_MA_DQS1_P
MEM_MA_DQS2_P
MEM_MA_DQS3_P
MEM_MA_DQS4_P
MEM_MA_DQS5_P
MEM_MA_DQS6_P
MEM_MA_DQS7_P

5,8 MEM_MA_CKE0
5,8 MEM_MA_CKE1

PDAT_SMB
PCLK_SMB

3,8,14,25 PDAT_SMB
3,8,14,25 PCLK_SMB

198
200

SA0
SA1

195
197

SDA
SCL

199

+3V

C466
0.1u/10V_4

+0.9VSMVREF_DIMM

2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54

MEMHOT_SODIMM#_1
MEM_MA_RESET#1

VDDspd

VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34

196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133

A

R279

0_4

10K/F_4
10K/F_4

107
106
85

BA0
BA1
BA2

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7

10
26
52
67
130
147
170
185

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

13
31
51
70
131
148
169
188

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

5
5
5
5
5
5
5
5

MEM_MB_DQS0_N
MEM_MB_DQS1_N
MEM_MB_DQS2_N
MEM_MB_DQS3_N
MEM_MB_DQS4_N
MEM_MB_DQS5_N
MEM_MB_DQS6_N
MEM_MB_DQS7_N

11
29
49
68
129
146
167
186

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

5
5
5
5

MEM_MB_CLK1_P
MEM_MB_CLK1_N
MEM_MB_CLK7_P
MEM_MB_CLK7_N

30
32
164
166

CK0
CK0
CK1
CK1

5,8 MEM_MB_CKE0
5,8 MEM_MB_CKE1

79
80

CKE0
CKE1

5,8 MEM_MB_RAS#
5,8 MEM_MB_CAS#
5,8 MEM_MB_WE#
5,8 MEM_MB0_CS#0
5,8 MEM_MB0_CS#1

108
113
109
110
115

RAS
CAS
WE
S0
S1

5,8 MEM_MB0_ODT0
5,8 MEM_MB0_ODT1
MEMHOT_SODIMM# 8

114
119

ODT0
ODT1

T122

DIM2_SA0
DIM2_SA1

198
200

SA0
SA1

T123

PDAT_SMB
PCLK_SMB

195
197

SDA
SCL

199
C468
0.1u/10V_4

+0.9VSMVREF_DIMM

1
2

C497
2.2u/6.3V_6

C382
0.1u/10V_4

+1.8VSUS

+SMDDR_VREF

R277
2K/F_4

+0.9VSMVREF_DIMM

R281

*0_4

+0.9VSMVREF_DIMM

R288
2K/F_4

1/18 Change CN23 footprint from
DDR-C-1734071-200P to
DDR-C-1734071-200P-BD3A (SMT open
issue)

DIM1_SA0
DIM1_SA1

MEM_MB_BANK0
MEM_MB_BANK1
MEM_MB_BANK2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

MEM_MB_DQS0_P
MEM_MB_DQS1_P
MEM_MB_DQS2_P
MEM_MB_DQS3_P
MEM_MB_DQS4_P
MEM_MB_DQS5_P
MEM_MB_DQS6_P
MEM_MB_DQS7_P

Only for reserved

H=5.2

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84

5
5
5
5
5
5
5
5

DDR SO-DIMM SOCKET 1.8V

R271
R272

81
82
87
88
95
96
103
104
111
112
117
118

5 MEM_MB_DM[0..7]

+3V

VREF
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20

MEM_MA_NC5

5,8 MEM_MB_BANK[0..2]

MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15

C384
1000p/50V_4

o3

8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54

VDDspd
VREF
VSS0
VSS1
oVSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20

DIM2_SA0
DIM2_SA1

R295
R296

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA45
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA44
MEM_MB_DATA41
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA60
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA61
MEM_MB_DATA57
MEM_MB_DATA62
MEM_MB_DATA63

NC1
NC2
NC3
NC4
NC/TEST

50
69
83
120
163

MEMHOT_SODIMM#_2 R294
MEM_MB_RESET#2
T106

VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34

196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133

MEM_MB_NC5

D

C

MEMHOT_SODIMM#

0_4

B

T104

1/18 Change CN19 footprint from
DDR-C-292564-200P to DDR-C-292564-200P-BD3A
(SMT open issue)

DDR SO-DIMM SOCKET 1.8V
A

H=9.2

10K/F_4
10K/F_4

PROJECT : BD3G

+3V

Quanta Computer Inc.

SMbus address A2

SMbus address A0
5

MEM_MB_DATA[0..63] 5

CN19
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11

50
69
83
120
163

59
60
65
66
71
72
77
78
121
122
127
128
132

C496
C383 1000p/50V_4
C387 0.1u/10V_4
2.2u/6.3V_6

1

NC1
NC2
NC3
NC4
NC/TEST

BA0
BA1
BA2

5
5
5
5
5
5
5
5

MEM_MA_CLK1_P
MEM_MA_CLK1_N
MEM_MA_CLK7_P
MEM_MA_CLK7_N

MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA35
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA52
MEM_MA_DATA49
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA53
MEM_MA_DATA48
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59

SO-DIMM
(REVERSE)

MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33

5 MEM_MA_DM[0..7]

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

5,8 MEM_MB_ADD[0..15]

59
60
65
66
71
72
77
78
121
122
127
128
132

MEM_MA_BANK0 107
MEM_MA_BANK1 106
MEM_MA_BANK2 85

SO-DIMM
(Reverse)

5,8 MEM_MA_BANK[0..2]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33

D

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84

MEM_MA_DATA[0..63] 5

CN23

VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11

5,8 MEM_MA_ADD[0..15]
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15

07

+1.8VSUS
81
82
87
88
95
96
103
104
111
112
117
118

+1.8VSUS

1

Size

Document Number

Date:

Thursday, May 29, 2008

Rev
1A

DDR2 SODIMMS: A/B CHANNEL
4

3

2

Sheet
1

7

of

42

5

4

3

2

MEM_MA_ADD[0..15]

5,7 MEM_MA_ADD[0..15]

MEM_MB_BANK[0..2]

5,7 MEM_MB_BANK[0..2]

+SMDDR_VTERM
MEM_MA_BANK2
MEM_MA_CKE0
MEM_MA_ADD12
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD5
MEM_MA_ADD3
MEM_MA_ADD1
MEM_MA_ADD10
MEM_MA_BANK0
MEM_MA_WE#
MEM_MA_CAS#
MEM_MA0_ODT1
MEM_MA0_CS#1
MEM_MA_ADD15
MEM_MA_CKE1

5,7 MEM_MA_CKE0
D

5,7
5,7
5,7
5,7

MEM_MA_WE#
MEM_MA_CAS#
MEM_MA0_ODT1
MEM_MA0_CS#1

5,7 MEM_MA_CKE1

RP25

3
1
3
1
1
3
1
3
3
1
3
1
3
1
3
1

MEM_MA_ADD7 RP31
MEM_MA_ADD14
MEM_MA_ADD6 RP30
MEM_MA_ADD11

4
2
4
2

3 47_4P2R_4
1
3 47_4P2R_4
1

MEM_MA_ADD2
MEM_MA_ADD4

4
2

3 47_4P2R_4
1

2
4

1 47_4P2R_4
3

RP24
RP20
RP19
RP23
RP22
RP21
RP32

RP27

MEM_MA_BANK1 RP26
MEM_MA_ADD0
MEM_MA0_CS#0 RP29
MEM_MA_RAS#

5,7 MEM_MA0_CS#0
5,7 MEM_MA_RAS#

MEM_MA_ADD13 RP28
MEM_MA0_ODT0

C

5,7 MEM_MA0_ODT0

0.1u/10V_4

C386

0.1u/10V_4

+1.8VSUS

47_4P2R_4
C361

0.1u/10V_4

C341

0.1u/10V_4

C355

0.1u/10V_4

+1.8VSUS

47_4P2R_4
47_4P2R_4

+1.8VSUS

47_4P2R_4
C390

0.1u/10V_4

47_4P2R_4
C491

0.1u/10V_4

C328

0.1u/10V_4

C360

0.1u/10V_4

+1.8VSUS

47_4P2R_4

3 47_4P2R_4
1

4
2

C446

5,7 MEM_MB_CKE0

47_4P2R_4

3 47_4P2R_4
1

4
2

+SMDDR_VTERM

47_4P2R_4

4
2
4
2
2
4
2
4
4
2
4
2
4
2
4
2

C329

0.1u/10V_4

C495

0.1u/10V_4

C369

0.1u/10V_4

C445

0.1u/10V_4

C318

0.1u/10V_4

C444

0.1u/10V_4

C448

08

MEM_MB_ADD[0..15]

5,7 MEM_MB_ADD[0..15]

MEM_MA_BANK[0..2]

5,7 MEM_MA_BANK[0..2]

1

5,7
5,7
5,7
5,7
5,7

MEM_MB_WE#
MEM_MB_CAS#
MEM_MB0_ODT1
MEM_MB0_CS#1
MEM_MB_CKE1

+1.8VSUS

+1.8VSUS

+1.8VSUS

RP40

MEM_MB_ADD7
MEM_MB_ADD14

RP43

RP39
RP38
RP37
RP36
RP35
RP41
RP44

47_4P2R_4

4
2
2
4
4
2
4
2
4
2
4
2
4
2
2
4

3
1
1
3
3
1
3
1
3
1
3
1
3
1
1
3

4
2

3 47_4P2R_4
1

0.1u/10V_4

C440

0.1u/10V_4

C357

0.1u/10V_4

C325

0.1u/10V_4

C356

0.1u/10V_4

C449

0.1u/10V_4

C494

0.1u/10V_4

C441

0.1u/10V_4

C492

0.1u/10V_4

C349

0.1u/10V_4

C493

0.1u/10V_4

C376

0.1u/10V_4

C359

0.1u/10V_4

C340

0.1u/10V_4

C362

0.1u/10V_4

C343

0.1u/10V_4

+1.8VSUS
D

47_4P2R_4
47_4P2R_4

+1.8VSUS

47_4P2R_4
47_4P2R_4

+1.8VSUS

47_4P2R_4
47_4P2R_4

MEM_MB_ADD6
MEM_MB_ADD11

RP42

4
2

3 47_4P2R_4
1

MEM_MB_ADD2
MEM_MB_ADD4

RP48

4
2

3 47_4P2R_4
1

MEM_MB_BANK1
MEM_MB_ADD0

RP47

4
2

3 47_4P2R_4
1

MEM_MB0_CS#0
MEM_MB_RAS#

RP46

4
2

3 47_4P2R_4
1

5,7 MEM_MB0_ODT0

MEM_MB0_ODT0
MEM_MB_ADD13

RP45

2
4

1 47_4P2R_4
3

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

C365
47_4P2R_4

5,7 MEM_MB0_CS#0
5,7 MEM_MB_RAS#
+1.8VSUS

0.1u/10V_4

MEM_MB_CKE0
MEM_MB_BANK2
MEM_MB_ADD12
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD5
MEM_MB_ADD3
MEM_MB_ADD1
MEM_MB_ADD10
MEM_MB_BANK0
MEM_MB_WE#
MEM_MB_CAS#
MEM_MB0_ODT1
MEM_MB0_CS#1
MEM_MB_CKE1
MEM_MB_ADD15

+1.8VSUS

+1.8VSUS

+1.8VSUS

+1.8VSUS

+1.8VSUS
C

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

+1.8VSUS

+1.8VSUS

C513
0.1u/10V_4

C505
0.1u/10V_4

C503
0.1u/10V_4

C498
0.1u/10V_4

C517
0.1u/10V_4

C522
0.1u/10V_4

C499
0.1u/10V_4

PLACE CLOSE TO SOCKET( PER EMI/EMC)

C511
0.1u/10V_4

C519
0.1u/10V_4

C524
0.1u/10V_4

C520
0.1u/10V_4

C470
0.1u/10V_4

PLACE CLOSE TO SOCKET( PER EMI/EMC)

B

B

+3V

+3V

R297
*10K/F_4
R298
*10K/F_4

3

CPU_MEMHOT# 4,14

Close DDR2 socket
+3V

U5

PDAT_SMB
PCLK_SMB

A0
A1
A2

1
2

SDA
SCL

8

O.S

3

GND

C463

3

R299

+VS

0.1u/10V_4

MEMHOT_SODIMM#

*33_4

2
Q28
*2N7002E-G

2
Q29
*2N7002E-G

4

1

3,7,14,25 PDAT_SMB
3,7,14,25 PCLK_SMB

7
6
5

1

+3V

*DS75U+T&R

A

+3V

R291

10K/F_4

Address:92h

MEMHOT_SODIMM#

A

MEMHOT_SODIMM# 7

PROJECT : BD3G
Quanta Computer Inc.
Size

Document Number

DDR2 SODIMMS TERMINATIONS
Date:
5

4

3

2

Thursday, May 29, 2008

Sheet
1

8

of

42

Rev
1A

5

4

3

2

1

08

U14A

D

C

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

PART 1 OF 6

HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15

AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W 21
W 20
V21
V20
U20
U21
U19
U18

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

HT_CPU_NB_CLK_H0
HT_CPU_NB_CLK_L0
HT_CPU_NB_CLK_H1
HT_CPU_NB_CLK_L1

T22
T23
AB23
AA22

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HT_CPU_NB_CTL_H0
HT_CPU_NB_CTL_L0
HT_CPU_NB_CTL_H1
HT_CPU_NB_CTL_L1

M22
M23
R21
R20

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

R655
R476

300/F_4

HT_RXCALP
HT_RXCALN

C23
A24

HYPER TRANSPORT CPU I/F

HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7

HT_RXCALP
HT_RXCALN

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15

HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

H24
H25
L21
L20

HT_NB_CPU_CLK_H0
HT_NB_CPU_CLK_L0
HT_NB_CPU_CLK_H1
HT_NB_CPU_CLK_L1

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

M24
M25
P19
R18

HT_NB_CPU_CTL_H0
HT_NB_CPU_CTL_L0
HT_NB_CPU_CTL_H1
HT_NB_CPU_CTL_L1

HT_TXCALP
HT_TXCALN

B24
B25

HT_TXCALP R475
HT_TXCALN

HT_CPU_NB_CAD_H[15..0]
HT_CPU_NB_CAD_L[15..0]

HT_CPU_NB_CAD_H[15..0]

4

HT_CPU_NB_CAD_L[15..0]

4

HT_CPU_NB_CLK_H[1..0]

4

HT_CPU_NB_CLK_H[1..0]
HT_CPU_NB_CLK_L[1..0]
HT_CPU_NB_CTL_H[1..0]
HT_CPU_NB_CTL_L[1..0]
HT_NB_CPU_CAD_H[15..0]
HT_NB_CPU_CAD_L[15..0]

HT_CPU_NB_CLK_L[1..0]

4

HT_CPU_NB_CTL_H[1..0]

4

HT_CPU_NB_CTL_L[1..0]

4

HT_NB_CPU_CAD_H[15..0]

4

HT_NB_CPU_CAD_L[15..0]

4

HT_NB_CPU_CLK_H[1..0]

4

D

HT_NB_CPU_CLK_H[1..0]
HT_NB_CPU_CLK_L[1..0]
HT_NB_CPU_CTL_H[1..0]
HT_NB_CPU_CTL_L[1..0]

HT_NB_CPU_CLK_L[1..0]

4

HT_NB_CPU_CTL_H[1..0]

4

HT_NB_CPU_CTL_L[1..0]

4

11/4 modify
RS780

signals

RX780

HT_TXCALP
HT_TXCALN

R641
300 ohm 1%

R641
1.21k ohm 1%

R655
300 ohm 1%

R655
1.21k ohm 1%

HT_RXCALP
HT_RXCALN

RES CHIP 1.21K 1/16W +-1%(0402)
P/N : CS21212FB18

RES CHIP 300 1/16W +-1%(0402)
P/N : CS13002FB00
C

R641
300/F_4

RS780(RX780)

This block is for UMA RS780 only , RX780 can
remove all component

A12 version
RS780M AJ067400T05 100-CK2612(216-0674008-00)
RS780MC AJ067400T06 100-CK2613(216-0674010-00)
RX781 AJ067400T10 100-CK2642(215-0674024)
SB700 AJA12FG0T18 100-CK2614(218S7EALA12FG)
U14D

PAR 4 OF 6

B

AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

AD16
AE17
AD17

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

W 12
Y12
AD18
AB13
AB18
V14

MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

V15
W 14

MEM_CKP(NC)
MEM_CKN(NC)

AE12
AD12

SBD_MEM/DVO_I/F

A13 version
RS780M AJ067400T18 100-CK2699(216-0674022)
RS780MC AJ067400T20 100-CK2704(216-0674024)
RX781 AJ067400T21 100-CK2706(215-0674034)
A12 version
SB700 AJA12FG0T18

MEM_COMPP(NC)
MEM_COMPN(NC)

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)

Y17
W18
AD20
AE21

MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)

W17
AE19

IOPLLVDD18(NC)
IOPLLVDD(NC)

AE23
AE24

IOPLLVSS(NC)

AD23

MEM_VREF(NC)

AE18

B

2/1 R480,R479 no stuff when RS780M without
side port / RX781
+1.8_IOPLLVDD18_NB
+1.1V_IOPLLVDD

R480
R479

0_6
0_6

+1.8V
+1.1V_NB

4/24 stuff R480,R479

RS780(RX780)

IOPLLVDD- memory PLL
not applicable to RX780

A

A

PROJECT : BD3G
Quanta Computer Inc.
Size

Document Number

Rev
1A

RS740/RS780-HT LINK I/F 1/5
Date:
5

4

3

2

Thursday, May 29, 2008

Sheet
1

9

of

42

5

4

3

2

1

9

U14B

D

PCIE_RXP0
PCIE_RXN0
PCIE_RXP1
PCIE_RXN1
PCIE_RXP2
PCIE_RXN2
PCIE_RXP3
PCIE_RXN3

25 PCIE_RXP0
25 PCIE_RXN0
25 PCIE_RXP1
25 PCIE_RXN1
24 PCIE_RXP2
24 PCIE_RXN2
25 PCIE_RXP3
25 PCIE_RXN3
C

13
13
13
13
13
13
13
13

PCIE_SB_NB_RX0P
PCIE_SB_NB_RX0N
PCIE_SB_NB_RX1P
PCIE_SB_NB_RX1N
PCIE_SB_NB_RX2P
PCIE_SB_NB_RX2N
PCIE_SB_NB_RX3P
PCIE_SB_NB_RX3N

D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

PART 2 OF 6

PCIE I/F GFX

PEG_RXP15
PEG_RXN15
PEG_RXP14
PEG_RXN14
PEG_RXP13
PEG_RXN13
PEG_RXP12
PEG_RXN12
PEG_RXP11
PEG_RXN11
PEG_RXP10
PEG_RXN10
PEG_RXP9
PEG_RXN9
PEG_RXP8
PEG_RXN8
PEG_RXP7
PEG_RXN7
PEG_RXP6
PEG_RXN6
PEG_RXP5
PEG_RXN5
PEG_RXP4
PEG_RXN4
PEG_RXP3
PEG_RXN3
PEG_RXP2
PEG_RXN2
PEG_RXP1
PEG_RXN1
PEG_RXP0
PEG_RXN0

PCIE I/F GPP

PCIE I/F SB

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

C_PEG_TXP15
C_PEG_TXN15
C_PEG_TXP14
C_PEG_TXN14
C_PEG_TXP13
C_PEG_TXN13
C_PEG_TXP12
C_PEG_TXN12
C_PEG_TXP11
C_PEG_TXN11
C_PEG_TXP10
C_PEG_TXN10
C_PEG_TXP9
C_PEG_TXN9
C_PEG_TXP8
C_PEG_TXN8
C_PEG_TXP7
C_PEG_TXN7
C_PEG_TXP6
C_PEG_TXN6
C_PEG_TXP5
C_PEG_TXN5
C_PEG_TXP4
C_PEG_TXN4
C_PEG_TXP3
C_PEG_TXN3
C_PEG_TXP2
C_PEG_TXN2
C_PEG_TXP1
C_PEG_TXN1
C_PEG_TXP0
C_PEG_TXN0

C587
C586
C589
C588
C591
C590
C593
C592
C595
C594
C600
C596
C605
C603
C607
C606
C609
C608
C611
C610
C613
C612
C615
C614
C624
C617
C654
C653
C662
C660
C647
C627

EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

PCIE_TXP0_C
PCIE_TXN0_C
PCIE_TXP1_C
PCIE_TXN1_C
PCIE_TXP2_C
PCIE_TXN2_C
PCIE_TXP3_C
PCIE_TXN3_C

C453
C452
C530
C531
C744
C743
C680
C740

0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)

AC8
AB8

PEG_TXP15
PEG_TXN15
PEG_TXP14
PEG_TXN14
PEG_TXP13
PEG_TXN13
PEG_TXP12
PEG_TXN12
PEG_TXP11
PEG_TXN11
PEG_TXP10
PEG_TXN10
PEG_TXP9
PEG_TXN9
PEG_TXP8
PEG_TXN8
PEG_TXP7
PEG_TXN7
PEG_TXP6
PEG_TXN6
PEG_TXP5
PEG_TXN5
PEG_TXP4
PEG_TXN4
PEG_TXP3
PEG_TXN3
PEG_TXP2
PEG_TXN2
PEG_TXP1
PEG_TXN1
PEG_TXP0
PEG_TXN0

21 PEG_RXN[15:0]
21 PEG_RXP[15:0]

PEG_RXN[15:0]

PEG_TXN[15:0]

PEG_RXP[15:0]

PEG_TXP[15:0]

PEG_TXN[15:0] 21
PEG_TXP[15:0] 21

BTO

Close to North Bridge

D

Close to North Bridge
C_PEG_TXP15
C_PEG_TXN15

C159
C160

HDM@0.1u/10V_4
HDM@0.1u/10V_4

C_PEG_TXP14
C_PEG_TXN14

C152
C158

HDM@0.1u/10V_4
HDM@0.1u/10V_4

C_PEG_TXP13
C_PEG_TXN13

C145
C150

HDM@0.1u/10V_4
HDM@0.1u/10V_4

C_PEG_TXP12
C_PEG_TXN12

C140
C144

HDM@0.1u/10V_4
HDM@0.1u/10V_4

IV_HDMITX2P 19
IV_HDMITX2N 19
IV_HDMITX1P 19
IV_HDMITX1N 19
IV_HDMITX0P 19
IV_HDMITX0N 19
IV_HDMICLK+ 19
IV_HDMICLK- 19

To HDMI CONN

PCIE_TXP0 25
PCIE_TXN0 25
PCIE_TXP1 25
PCIE_TXN1 25
PCIE_TXP2 24
PCIE_TXN2 24
PCIE_TXP3 25
PCIE_TXN3 25

TO WLAN
TO MINI CARD
TO PCIE-LAN

NOTE:

TO EPRESS CARD

RS780MC no support Graphic / HDMI
C

A_TX0P_C C626
A_TX0N_C C625
A_TX1P_C C649
A_TX1N_C C630
A_TX2P_C C655
A_TX2N_C C656
A_TX3P_C C665
A_TX3N_C C663
NB_PCIECALRP
NB_PCIECALRN

0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
R58
R56

PCIE_NB_SB_TX0P
PCIE_NB_SB_TX0N
PCIE_NB_SB_TX1P
PCIE_NB_SB_TX1N
PCIE_NB_SB_TX2P
PCIE_NB_SB_TX2N
PCIE_NB_SB_TX3P
PCIE_NB_SB_TX3N

1.27K/F_4
2K/F_4

13
13
13
13
13
13
13
13

+1.1V_NB

RS780(RX780)
11/4 modify

RX780/RS740/RS780 difference table (PCIE LINK)
RS740

RX780/RS780

562R (GND)

1.27K (GND)

RS780 Display Port Support (muxed on GFX)
GFX_TX0,TX1,TX2 and TX3

NB_PCIECALRP

DP0
AUX0 and HPD0

GPP4

NC

GPP4

GPP5

NC

GPP5

GFX_TX4,TX5,TX6 and TX7
DP1
B

B

AUX1 and HPD1

A

A

PROJECT : BD3G
Quanta Computer Inc.
Size

Document Number

Date:

Thursday, May 29, 2008

Rev
1A

RS740/RS780-PCIE I/F 2/5
5

4

3

2

Sheet
1

10

of

42

5

4

3

2

1

10

U14C

R31

13 NB_PLTRST#

0_4

INT_TV_C/R
INT_TV_Y/G

R46

G18
G17
E18
F18
E19
F19

IV@140/F_4

R99

IV@150/F_4

R102

IV@150/F_4

INT_CRT_BLU

R79
*2K/F_4

E17
F17
F15

INT_CRT_RED

18 INT_HSYNC
18 INT_VSYNC
18 INT_CRT_DDCDAT
18 INT_CRT_DDCCLK

RX780
R47

INT_TV_C/R
INT_TV_Y/G
INT_TV_COMP

INT_CRT_GRN

18 INT_CRT_BLU

11/4 stuff R5160 for RS780M/MC/RX781

+1.1V_NB

R103

18 INT_CRT_GRN

North Bridge RESET

D

+1.8V_AVDDQ_NB

NB_RST#_IN

*0_4

18 INT_CRT_RED

RS780

+1.8V_AVDDDI_NB

IV@150/F_4
IV@150/F_4
*150/F_4

IV@715/F_6

INT_HSYNC
INT_VSYNC
INT_CRT_DDCDAT
INT_CRT_DDCCLK

A11
B11
E8
F8

DAC_RSET_NB

G14

+1.1V_PLLVDD
+1.8V_PLLVDD18

A12
D14
B12

INT_CRT_DDCDAT
INT_CRT_DDCCLK

*2K/F_4

+1.8V_VDDA18HTPLL

H17

+1.8V_VDDA18PCIEPLL

D7
E7

10/9 add 2K pull up to DDCDAT /DDCCLK for RX780

11/4 no stuff for RS780M/MC/RX781

17 NB_PWRGD_IN

3 NBHT_REFCLKP
3 NBHT_REFCLKN
3

3
3
3
3
3
3

12/22 stuff R48 2.2K for power play

+NB_CORE_ON

R44

*10K/F_4

R48

R50
4.7K_4

RS780

NBHT_REFCLKP
NBHT_REFCLKN

C25
C24

NB_REFCLK_P
NB_REFCLK_N

0_4
0_4

RS780R54

4.7K_4

NBGFX_CLKP
NBGFX_CLKN
NBGPP_CLKP
NBGPP_CLKN
SBLINK_CLKP
SBLINK_CLKN

E11
F11

NBGFX_CLKP
NBGFX_CLKN

T2
T1

NBGPP_CLKP
NBGPP_CLKN

U1
U2

SBLINK_CLKP
SBLINK_CLKN

V4
V3

INT_LVDS_EDIDDATA
INT_LVDS_EDIDCLK
IV_HDMI_DDCDATA
IV_HDMI_DDCCLK

20 INT_LVDS_EDIDDATA
20 INT_LVDS_EDIDCLK
19 IV_HDMI_DDCDATA
19 IV_HDMI_DDCCLK

+3V

2.2K_4

D8
A10
C10
C12

R485
R53

EXT_NB_OSC
+1.1V_NB

C

NB_RST#_IN
NB_PWRGD_IN
NB_LDT_STOP#
NB_ALLOW_LDTSTOP

RS740_DFT_GPIO1

T145
T144
R49

35 +NB_CORE_ON

A9
B9
B8
A8
B7
A7

0_4 STRP_DATA

B10
G11

selects Loading of straps from
EPROM
1 : use default vaule , default
0 : I2C Master can load strap
values from EEPROM
if connected, or use default
values if not connected
RX780 --RS780_AUX_CAL
RS780 -- SUS_ATAT

C8

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)

PART 3 OF 6

C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)
RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)

TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)

DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SDA(PCE_TCALRN)
DAC_SCL(PCE_RCALRN)

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

DAC_RSET(PWM_GPIO1)
VDDLTP18(NC)
VSSLTP18(NC)

PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)
VDDA18HTPLL
VDDA18PCIEPLL1
VDDA18PCIEPLL2
SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP
HT_REFCLKP
HT_REFCLKN

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

A22
B22
A21
B21
B20
A20
A19
B19

INT_TXLOUT0+
INT_TXLOUT0INT_TXLOUT1+
INT_TXLOUT1INT_TXLOUT2+
INT_TXLOUT2T139
T137

B18
A18
A17
B17
D20
D21
D18
D19

INT_TXUOUT0+ 20
INT_TXUOUT0- 20
INT_TXUOUT1+ 20
INT_TXUOUT1- 20
INT_TXUOUT2+ 20
INT_TXUOUT2- 20
T140
T138

B16
A16
D16
D17

INT_TXLCLKOUT+ 20
INT_TXLCLKOUT- 20
INT_TXUCLKOUT+ 20
INT_TXUCLKOUT- 20

A13
B13

+1.8V_VDDLTP18_NB

A15
B15
A14
B14

+1.8V_VDDLT_18_NB

D

+3V_VDLT33_NB

C14
D15
C16
C18
C20
E20
C22

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

I

11/01 exchange LVDS_PWM /LVDS_BLON

REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)
GFX_REFCLKP
GFX_REFCLKN

I/O

GPP_REFCLKP
GPP_REFCLKN

I/O

I

E9
F7
G12

LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)

INT_LVDS_DIGON
20
INT_LVDS_PWM 20
INT_LVDS_BLON 20

GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)
I2C_DATA
I2C_CLK
DDC_DATA/AUX0N(NC)
DDC_CLK/AUX0P(NC)
AUX1P(NC)
AUX1N(NC)

MIS.

TMDS_HPD(NC)
HPD(NC)
TVCLKIN(PWM_GPIO5)
THERMALDIODE_P
THERMALDIODE_N

STRP_DATA
RSVD

R25

*1.27K/F_4

R11

*1.27K/F_4

For RX780 only

R26
IV@0_4

D9
D10

TMDS_HPD0
TMDS_HPD1

D12

SUS_STAT#_NB

AE8
AD8

R_NB_THRMDA
R_NB_THRMDC

C

IV_HDMI_HPD

19

T2
R71

0_4

SUS_STAT#

14

T142
T141

D13 TEST_EN

TESTMODE

R75
1.82K/F_4

AUX_CAL(NC)

R491

Enables Debug Bus acess
through memory T/O pads and GPIO.
1 : Enable RX780 , Default
0 : Disable RX780

1/17 RX781 connect to GND
C104,C110,C646,C98,C136,C103,C118 change to CS00003J951

BLM18PG221SN1D(220,1.4A)_6

RX780
+3V

*3K_4

+3V_AVDD_NB

L2
BLM18PG221SN1D(220,1.4A)_6

AVDD-DAC Analog
not applicable to RX780

RX780

+1.1V_PLLVDD

+1.1V_NB

L52

+1.8V
C646
2.2u/6.3V_6

C104
2.2u/6.3V_6

BLM18PG221SN1D(220,1.4A)_6
+1.8V_VDDLTP18_NB

PLLVDD - Graphics PLL
not applicable to
RX780

L51
C103
2.2u/6.3V_6

+1.8V

VDDLTP18 - LVDS or DVI/HDMI PLL
not applicable to RX780

+1.8V
INT_TV_C/R

R96

B

*3K_4
L12
BLM18PG221SN1D(220,1.4A)_6

Reserved only

+1.8V_PLLVDD18

R76

0_6

C110
C124
10u/6.3V_8

+1.8V_AVDDDI_NB

AVDDI-DAC Digital
not applicable to RX780

BLM21PG221SN1D(220,100M,2A)_8
+1.8V_VDDLT_18_NB

C98
2.2u/6.3V_6

2.2u/6.3V_6

L10
C118

12/22 stuff R65

BLM18PG221SN1D(220,1.4A)_6
+1.8V_AVDDQ_NB
L17

PLLVDD18 - Graphics PLL
not applicable to RX780

RS780
INT_VSYNC

R65

3K_4

R66

*3K_4

RS780
3K_4

R490

*3K_4

VDDLT18 - LVDS or
DVI/HDMI digital
not applicable to
RX780

+3V

VDDA18PCIEPLL -PCIE PLL

R489

1/17 RX781 no stuff them
L2,L12,C124,L52,R76,L17,L51,L10,C115

C115
0.1u/10V_4

AVDDQ-DAC Bandgap Reference
not applicable to RX780

C136
2.2u/6.3V_6

+1.8V

INT_HSYNC

4.7u/6.3V_6

L1

1/31 voltage leakage issue
remove Q5,Q3,R83,R80,R97
stuff R88,R77

RS780
Q5
*BSS138_NL/SOT23

C79
2.2u/6.3V_6

R97

*0_6

+VDDG_NB

+3V

R83
*4.7K_4

1

4,13 CPU_LDT_STOP#

*0_6

+VDDG_NB

20mils width
+1.8V_VDDA18PCIEPLL

BLM18PG221SN1D(220,1.4A)_6

+3V

R100

RX780 +1.8V
+1.8V

2

Enables Debug Bus acess
through memory T/O pads and GPIO.
1 : Enable RS780 , Default
0 : Disable RS780
(RS780 use VSYNC#)

Indicates if memory Side port
is available or not
0: available RS780 , Default
1: Not available RS780
( RS780 use HSYNC#)

20
20
20
20
20
20

RS780(RX780)

RS780_AUX_CAL

B

RS780_AUX_CAL

T143

AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)

CRT/TVOUT

R30

4,13 CPU_LDT_RST#

R95
R89
R84

2/1 follow A13 request change
R103 from 150 to 140 CS11402FB19

F12
E12
F14
G15
H15
H14

PLL PWR
LVTM

rail
or

18
18

RX780

+3V_AVDD_NB

10/26 change to 4 pin S-video conn , no need TV_comp

PM

rail
or

CLOCKs

RX780: Powered from the 1.8-V
and driven by SB600 LDT_RST#,
SB700 LDT_RST# or A_RST#.
RS780: Powered from the 3.3-V
and driven by SB600 LDT_RST#,
SB700 LDT_RST# or A_RST#.

NB_LDT_STOP#

3

L9
+3V_VDLT33_NB

+3V

*BLM21PG221SN1D(220,100M,2A)_8
R88

VDDA18HTPLL -HT LINK PLL

10/19 RS780M Databook rev 1.01 define High disable

L13

RS780

A

+1.8V

20mils width
+1.8V_VDDA18HTPLL

BLM18PG221SN1D(220,1.4A)_6

Q3
*BSS138_NL/SOT23
C131
2.2u/6.3V_6

*2.2u/6.3V_6

+VDDG_NB

4 CPU_LDT_REQ#

13 ALLOW_LDTSTOP

R74

0_4

R80
*4.7K_4

2

A

C108

0_4

1

3

VDDLT33 - LVDS or DVI/HDMI ANALOG
RS740 only

NB_ALLOW_LDTSTOP

PROJECT : BD3G
R77

Quanta Computer Inc.

0_4

RS780

Size

Document Number

Date:

Thursday, May 29, 2008

Rev
1A

RS740/RS780-SYSTEM I/F 3/5
5

4

3

2

Sheet
1

11

of

42

3

PART 6/6

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11

VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27

GROUND

A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25

1

11

RX780/RS780 POWER DIFFERENCE TABLE

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

U14F

D

2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

4

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

5

RS780

PIN NAME

RX780

+1.1V

IOPLLVDD

NC

+1.1V

+1.1V

AVDD

NC

+3.3V

+1.2V

+1.2V

AVDDDI

NC

+1.8V

+1.8V

+1.8V

AVDDQ

NC

+1.8V

VDDG18

+1.8V

+1.8V

PLLVDD

NC

+1.1V

VDD18_MEM

NC

+1.8V

PLLVDD18

NC

+1.8V

VDDPCIE

+1.1V

+1.1V

VDDA18PCIEPLL

+1.8V

+1.8V

PIN NAME

RX780

VDDHT

+1.1V

VDDHTRX
VDDHTTX
VDDA18PCIE

RS780
+1.1V

VDDA18HTPLL

+1.8V

+1.8V

VDDLTP18

NC

+1.8V

+3.3V

VDDLT18

NC

+1.8V

+1.8V

VDDLT33

NC

NC

VDDC

+1.1V

VDD_MEM

NC

+1.8V/1.5V

VDDG33

NC

IOPLLVDD18

NC

+1.1V

D

+1.1V_NB

+1.1V 2A for RS780M
0.6A

C121
4.7U/6.3V_6

VDDHTRX - HT
LINK RX I/O for
RX780/RS780

0.45A

C114
0.1u/10V_4

C116
0.1u/10V_4

C123
0.1u/10V_4

+1.1V_VDDHTRX

L18
BLM21PG221SN1D(220,100M,2A)_8
C143
4.7U/6.3V_6

C125
0.1u/10V_4

C142
0.1u/10V_4

C141
0.1u/10V_4

+1.2V 2A for RS780M+SB700
0.5A

+1.2V_VDDHTTX

L36
+1.2V
BLM21PG221SN1D(220,100M,2A)_8

C601
4.7U/6.3V_6

+1.35V for
A1-1 chip
bug , A1-2
can remove
B

C117
0.1u/10V_4

C126
0.1u/10V_4

C120
0.1u/10V_4

C129
0.1u/10V_4

VDDHTTX - HT
LINK TX I/O for
RX780/RS780

12/14 del L15 stuff L36 for A12

+1.8V 1A for RS780M+SB700
+1.8V

600mA

L3

+1.8V_VDDA18PCIE

BLM21PG221SN1D(220,100M,2A)_8
C95
4.7U/6.3V_6

VDDA18PCIE PCIE TX stage
I/O for
RX780/RS780

VDD18 - RS780 I/O +1.8V
transform

+1.8V

C94
4.7U/6.3V_6

R70

C93
0.1u/10V_4

0_6

C90
0.1u/10V_4

C88
0.1u/10V_4

0_6

VDD18_MEM For UMA RS780 only
Not applicable to RX780
memory I/O transform

C91
0.1u/10V_4

0.005A
C89
1u/10V_4

R484

VDDPCIE - PCIE-E Main power

U14E
+1.1V_VDDHT

L11
BLM21PG221SN1D(220,100M,2A)_8

+1.8V_VDDG18_NB

0.005A

+1.8V_VDD18_MEM

J17
K16
L16
M16
P16
R16
T16

VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

H18
G19
F20
E21
D22
B23
A23

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

AE25
AD24
AC23
AB22
AA21
Y20
W 19
V18
U17
T17
R17
P17
M17

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10
F9
G9
AE11
AD11

C616
*1u/10V_4

PART 5/6

POWER

VDDHT - HT
LINK digital
I/O for
RX780/RS780

C

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDDG18_1(VDD18_1)
VDDG18_2(VDD18_2)
VDD18_MEM1(NC)
VDD18_MEM2(NC)

VDDG33_1(NC)
VDDG33_2(NC)

RS780(RX780)

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

0.7A

+1.1V_VDD_PCIE

C77
0.1u/10V_4

C85
0.1u/10V_4

C86
1u/10V_4

C76
1u/10V_4

R55

0_8

C

+1.1V_NB

C78
4.7U/6.3V_6

2/13 EMI
stuff C804~C807 for +NB_CORE

VDDC - Core Logic power

7A
+NB_CORE
C96
0.1u/10V_4

C100
0.1u/10V_4

C111
0.1u/10V_4

C105
C598
0.1u/10V_4 10u/6.3V_8

C804
0.1u/10V_4

C805
*0.1u/10V_4

C806
0.1u/10V_4

C807
*0.1u/10V_4

5/28 del C805,C807
B

C102
0.1u/10V_4

C109
0.1u/10V_4

C113
0.1u/10V_4

C597
10u/6.3V_8

10/18 follow AMD design guide 1.0
VDD_MEM For UMA RS780 only
Not applicable to RX780
memory I/O transform

1.8V(0.15A)

AE10
AA11
Y11
AD10
AB10
AC10

+1.8V_VDD_MEM

H11
H12

+3V_VDDG33
C92
0.1u/10V_4

R67

*0_6

R57

0_6

RS780
0_6

R27
C99
0.1u/10V_4

+1.8V

3.3V(0.03A)
+3V

VDD33 - 3.3V I/O
Not applicable to RX780

1/17 RX781 no stuff them
R484

A

A

1/17 RX781 connect to GND
C616 change to CS00002JB38

PROJECT : BD3G
Quanta Computer Inc.
Size

Document Number

Rev
1A

RS740/RS780-POWER5/5
Date:
5

4

3

2

Thursday, May 29, 2008

Sheet
1

12

of

42

5

4

3

2

1

12

2/4 reserve C800 PLTRST#
R160
R165

11 NB_PLTRST#
19,21,24,25,27,29 PLTRST#

C800

33_4
33_4

PLTRST#

U6A

L27

R363
R360

562/F_4
2.05K/F_4

BLM18PG221SN1D(220,1.4A)_6

PCIE_PVDD-- PCIE PLL POWER

PCIE_CALRP_SB
PCIE_CALRN_SB
+1.2V_PCIE_PVDD

40mA
C321
10u/6.3V_8

SB700
A_RST#

V23
V22
V24
V25
U25
U24
T23
T22

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N

U22
U21
U19
V19
R20
R21
R18
R17

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N

T25
T24

PCIE_CALRP
PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

C322
1u/10V_4

Part 1 of 5

N25
N24

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN

T80
T71

NB_DISP_CLKP
NB_DISP_CLKN

K23
K22

NB_DISP_CLKP
NB_DISP_CLKN

T119
T118

NB_HT_CLKP
NB_HT_CLKN

M24
M25

NB_HT_CLKP
NB_HT_CLKN

T69
T64

CPU_HT_CLKP
CPU_HT_CLKN

P17
M18

CPU_HT_CLKP
CPU_HT_CLKN

T120
T87

SLT_GFX_CLKP
SLT_GFX_CLKN

M23
M22

SLT_GFX_CLKP
SLT_GFX_CLKN

T110
T108

GPP_CLK0P
GPP_CLK0N

J19
J18

GPP_CLK0P
GPP_CLK0N

T111
T75

GPP_CLK1P
GPP_CLK1N

L20
L19

GPP_CLK1P
GPP_CLK1N

T72
T66

GPP_CLK2P
GPP_CLK2N

M19
M20

GPP_CLK2P
GPP_CLK2N

T65
T60

GPP_CLK3P
GPP_CLK3N

N22
P22

GPP_CLK3P
GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

RTC_X1
T103

Y3

3

10/18 AMD suggest to not connect to GND

100MHZ

CLOCK GENERATOR

B

2
T78

1

4

PCI INTERFACE

SBSRC_CLKP
SBSRC_CLKN

SBSRC_CLKP
SBSRC_CLKN

RTC_X2

R341

T85

J20

P4
P3
P1
P2
T4
T3

PCI_CLK0_R

R396

22_4

PCI_CLK2_R
PCI_CLK3_R
PCI_CLK4_R
PCI_CLK5_R

R369
R394
R424
R408

22_4
22_4
22_4
22_4

PCIRST#

N1

PCIRST#_L

PCLK_OZ129 26
T58
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5

17
17
17
17

A11 default PCICLK5
A12 default GPIO41
PE_GPIO1

C

3
3

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5/GPIO41

25M_X2

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/GPIO70
REQ4#/GPIO71
GNT0#
GNT1#
GNT2#
GNT3#/GPIO72
GNT4#/GPIO73
CLKRUN#
LOCK#

R367

33_4

17,26

SB_GPIO65

R209

8.2K_4

R212

*8.2K_4

R202

100K/F_4

Maybe can remove

All the PCI bus has
build-in Pull-UP/Down
resistors

4/16 change RTC pad location to G1

RTC

VCCRTC

D7

+3VPCU

CH500H-40
D10
CH500H-40

C317

C316

G1
1u/10V_4

R238
1K_6

0.1u/10V_4

*SHORT_PAD

C

R350
0_4

CN24
1 1
2 2
CBE0# 26
CBE1# 26
CBE2# 26
CBE3# 26
FRAME# 26
DEVSEL# 26
IRDY# 26
TRDY# 26
PAR
26
STOP# 26
REQ0#

ACS_85204-0200L

+5VPCU

R571+R667 = (5V - 0.2V-2V)/0.2mA = 14k

R302

Q33
VCCRTC_33 MMBT3904
1
2K/F_4

R301
2K/F_4

26

R332
6.8K_4

PORT_C# 22
GNT0#

26
B

R333
15K_6
R437

INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36

AD3
AC4
AE2
AE3

INTE#
INTF#
INTG#
INTH#

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
SERIRQ

G22
E22
H24
H23
J25
J24
H25
H22
AB8
AD7
V15

LPC_CLK0
LPC_CLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#_SB
LDRQ1#_SB
SB_GPIO65
SERIRQ

C3
C2
B2

RTC_CLK
INTRUDER_ALERT#
VCCRTC

T132

PCIRST# 25,26

AD[0..31]

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
T53
W4
T52
V7
AC3
T131
AD4
T44
AB7
AE6 PORT_C#
T45
AB6
AD2
T133
AE4
T135
AD5
T46
AC6 PE_GPIO1
T134
AE5
CLKRUN#_R
AD6
T54
V5

PCIRST#

D

+3V

2

PCIE_NB_SB_TX0P
PCIE_NB_SB_TX0N
PCIE_NB_SB_TX1P
PCIE_NB_SB_TX1N
PCIE_NB_SB_TX2P
PCIE_NB_SB_TX2N
PCIE_NB_SB_TX3P
PCIE_NB_SB_TX3N

PCIE_NB_SB_TX0P
PCIE_NB_SB_TX0N
PCIE_NB_SB_TX1P
PCIE_NB_SB_TX1N
PCIE_NB_SB_TX2P
PCIE_NB_SB_TX2N
PCIE_NB_SB_TX3P
PCIE_NB_SB_TX3N

+1.2V_PCIE_VDDR

A_RX0P_C
A_RX0N_C
A_RX1P_C
A_RX1N_C
A_RX2P_C
A_RX2N_C
A_RX3P_C
A_RX3N_C

1

0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4

2

10
10
10
10
10
10
10
10

+1.2V

C509
C512
C510
C508
C502
C507
C500
C504

PCIE_SB_NB_RX0P
PCIE_SB_NB_RX0N
PCIE_SB_NB_RX1P
PCIE_SB_NB_RX1N
PCIE_SB_NB_RX2P
PCIE_SB_NB_RX2N
PCIE_SB_NB_RX3P
PCIE_SB_NB_RX3N

PCI CLKS

PLACE THESE
PCIE AC
COUPLING CAPS
CLOSE TO U600

To RS780

D

10
10
10
10
10
10
10
10

N2

PCI EXPRESS INTERFACE

A_RST#_SB

*.1U_4

0_4

R435

0_4

R251
R348

22_4
22_4

CLKRUN# 26,29

T130

INTE#

26

FM_INTX

28

1/17
R301,R302 change from 8.66k to 2k.
R332 change from 4.7K to 6.8K

32.768KHZ
20M_6

X1

RTC_X2

B3

X2

C473
18p/50V_4

+1.8V
+1.8VSUS

R254

*10K/F_4

R349

*10K/F_4

11 ALLOW_LDTSTOP
4 CPU_PROCHOT_SB#
4
CPU_PWRGD
4,11 CPU_LDT_STOP#
4,11 CPU_LDT_RST#

A

ALLOW_LDTSTOP
CPU_PROCHOT_SB#
CPU_PWRGD
CPU_LDT_STOP#
CPU_LDT_RST#

F23
F24
F22
G25
G24

ALLOW_LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#

LPC

A3

RTC

C474
18p/50V_4

RTC_X1

CPU

R339

RTC XTAL

*20M_6

RTCCLK
INTRUDER_ALERT#
VBAT

PCLK_591 17,29
PCLK_DBC 17,25

LAD0
LAD1
LAD2
LAD3
LFRAME#

25,29
25,29
25,29
25,29
25,29

SERIRQ

29

T81
T51
T47

RTC_CLK 17
T107
VCCRTC
A

C486
0.1u/10V_4

SB700

1/31 voltage leakage remove R349

IC CTRL(528P) SB700 A11(218S7EALA11FG)
P/N : AJALA110T00

PROJECT : BD3G
Quanta Computer Inc.
Size

Document Number

Rev
1A

SB700-PCIE/PCI/CPU/LPC 1/4
Date:
5

4

3

2

Thursday, May 29, 2008

Sheet
1

13

of

42

5

+3V_S5

4

3

1

13

*2.2K_4

SB_TEST2

26 PCI_PME#

+3V_S5
D

10/31 add newcard DET#

*10K/F_4 SWI#

+3V SCL0/SDATA0
R166

2.2K_4

PCLK_SMB

R167

2.2K_4

PDAT_SMB

29
29
29

Clock gen
/DDR2 /MINI CARD/NEW CARD

is 3V tolerance
AMD datasheet define it

GATEA20
RCIN#
SCI#
T117
T174

SYS_RST#
PCIE_WAKE#
SWI#
CPU_THERMTRIP#
WD_PWRGD

24,25 PCIE_WAKE#
T114
4 CPU_THERMTRIP#
17 WD_PWRGD

SCL1/SDATA1 is 3V/S5 tolerance
AMD datasheet define it

29

RSMRST#

RSMRST#

SB_SMBCLK1
SB_SMBDATA1

28 FM_CLOCK

R261
R263

28
FM_DATA
22
PCBEEP
3,7,8,25 PCLK_SMB
3,7,8,25 PDAT_SMB

SB_SCLK2
SB_SDATA2

2.2K_4
2.2K_4

+3V_S5
C

R719

10K_4

R230

G-sensor
BOARD_ID1
BOARD_ID0
0_4

R226

0_4

T127

SCL2/SDATA2 is 3V/S5 tolerance
AMD datasheet define it

PDMA66

28

LOW_DET

LOW_DET

USB_OC5#

D29
1

CH501H-40PT
2

CPU_MEMHOT#_IN
USB_OC5#

T102

USB_OC5#

28,29 USBOC#3

D57

T83

1/31 NEW_DET# change from GEVEN5# to GPM1#

25
NEW_DET#
28,29 USBOC#0

4.7K_4

T67
T56
T121

SUS_STAT#

G2

17

ACZ_RST#

HD audio
interface is
3.3V voltage

*SHORT_ PAD1

B

R364

33_4

ACZ_SDOUT_AUDIO
C501

10/25 modify it

22

33_4

ACZ_SYNC_AUDIO
C296

R241

ACZ_BCLK

R285

C309

ACZ_SDIN0_R

+3V

27 HDD_AUX_RST#

BIT_CLK_AUDIO

0_4

22

1/31 voltage leakage
BOARD_ID4 change from GPIO66 to GPIO3

22P/50V_4

33_4

R243

22

*10p/50V_4

BK1005HM121-T_4

R357

ACZ_RST#

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO42
AZ_SDIN1/GPIO43
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
AZ_SYNC
AZ_RST#
AZ_DOCK_RST#/GPM8#

ACZ_RST#_AUDIO
ACZ_SDIN0

H19
H20
H21
F25

IMC_GPIO0
IMC_GPIO1
SPI_CS2#/IMC_GPIO2
IDE_RST#/F_RST#/IMC_GPO3

D22
E24
E25
D23

IMC_GPIO4
IMC_GPIO5
IMC_GPIO6
IMC_GPIO7

22

E6
E7

USB_FSD13P
USB_FSD13N

F7
E8

USB_FDS12P
USB_FSD12N

CLK_48M_USB
R247

CLK_48M_USB

3

11.8K/F_6

D

T77
T94
C339
*10p/50V_4

T73
T82

for EMI

T74
T68
C_USBP7+ R245
C_USBP7- R244

0_4
0_4

To M/B USB/ESATA

E11
F11

USB_HSD9P
USB_HSD9N

A11
B11

USB_HSD8P
USB_HSD8N

C10
D10

USB_HSD7P
USB_HSD7N

G11
H12

USB_HSD6P
USB_HSD6N

E12
E14

USB_HSD5P
USB_HSD5N

C12
D12

BT_USBP8+ 28
BT_USBP8- 28

USB_HSD4P
USB_HSD4N

B12
A12

FP_USBP4+ 28
FP_USBP4- 28

USB_HSD3P
USB_HSD3N

G12 C_USBP3+
G14 C_USBP3-

R265
R267

0_4
0_4

USB_HSD2P
USB_HSD2N

H14 C_USBP2+
H15 C_USBP2-

R283
R284

0_4
0_4

USB_HSD1P
USB_HSD1N

A13
B13

USBP1+ 28
USBP1- 28

To USB BOARD

B14
A14

USBP9+ 28
USBP9- 28

To USB BOARD

USBP7+ 27
USBP7- 27

3/3 del Mini card USB10,Felica USB5 , change BT to port5 ,
ESATA to port 10
NEW_USBP6+ 25
NEW_USBP6- 25

C_USBP0+
C_USBP0-

A18
B18
F21
D21
F19
E20
E21
E19
D19
E18

R274
R280

0_4
0_4

To New Card

USBP0+ 28
USBP0- 28

To M/B USB
10/25 change M.B USB to port 6/7

To Bluetooth

To Finger Printer

WL_USBP3+ 25
WL_USBP3- 25

To WLAN

CCD_USBP2+ 20
CCD_USBP2- 20

To Camera

10/18
SB_SCLK2
SB_SDATA2
SB_SCLK3
SB_SDATA3

C

USB swap for layout route

SB_SCLK2 19
SB_SDATA2 19
SB_SCLK3 4
SB_SDATA3 4

SB_GPIO16
SB_GPIO17

SB_GPIO16 17
SB_GPIO17 17

SPI/LPC define

G20
G21
D25
D24
C25
C24
B25
C23

IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41

B

SB700
15

BOARD_ID3

15

BOARD_ID2

BOARD_ID3

10/25 Board ID define MXM

22

12/21EMI
change R241from 33 to BK1005HM121-T
+3V
stff C309 22p

USB_RCOMP_SB

USB_HSD10P
USB_HSD10N

IMC_GPIO8
IMC_GPIO9
IMC_PWM0/IMC_GPIO10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
IMC_PWM1/IMC_GPIO15
IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17

*10p/50V_4
20K_4

R239

ACZ_SYNC

USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GPM5#
USB_OC4#/IR_RX0/GPM4#
USB_OC3#/IR_RX1/GPM3#
USB_OC2#/GPM2#
USB_OC1#/GPM1#
USB_OC0#/GPM0#

CLK_48M_USB

G8

H11
J10

USB_HSD0P
USB_HSD0N

+1.8V

To Azalia
ACZ_SDOUT

M1
M2
J7
J8
L8
M3
L6
M4
L5

ACZ_SYNC
ACZ_RST#

SYS_RST#

1

0_4

D58
BAS316
ACZ_BCLK
ACZ_SDOUT
ACZ_SDIN0_R
ACZ_SDIN1_R

12/7 add D57,D58 to avoid voltage leakage

+3V

BAS316
R689

B9
B8
A8
A9
E5
F8
E4

USB_FSD12P
USB_FSD12N
USB_HSD11P
USB_HSD11N

RSMRST#

SATA_IS0#/GPIO10
CLK_REQ3#/SATA_IS1#/GPIO6
SMARTVOLT/SATA_IS2#/GPIO4
CLK_REQ0#/SATA_IS3#/GPIO0
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
SCL1/GPOC2#
SDA1/GPOC3#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
LLB#/GPIO66
SHUTDOWN#/GPIO5
DDR3_RST#/GEVENT7#

C8

R257
*10_6

USB_FSD13P
USB_FSD13N

10/26 modify it
11/06 check it

4,8 CPU_MEMHOT#

2

AE18
AD18
AA19
W 17
V17
W 20
W 21
AA18
W 18
K1
K2
AA20
Y18
C1
Y19
G5

PCLK_SMB
PDAT_SMB
SB_SMBCLK1
SB_SMBDATA1
FM_DET

27

4/16 pull up USB_OC5# R719

R358

D3

USB_RCOMP

INTEGRATED uC

2.2K_4
2.2K_4

USBCLK/14M_25M_48M_OSC

USB OC

R362
R361

HD AUDIO

+3V_S5

PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S2/GPM9#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST2
TEST1
TEST0
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#
BLINK/GPM6#
SMBALERT#/THRMTRIP#/GEVENT2#
NB_PWRGD

INTEGRATED uC

R253

E1
E2
H7
F5
G1
H2
H1
K3
H5
H4
H3
Y15
W 15
K4
K24
F1
J2
H6
F2
J6
W 14

RI#
SLP_S2
SUSB#
SUSC#
DNBSWON#
SB_PWRGD_IN
SUS_STAT#
SB_TEST2
SB_TEST1
SB_TEST0
GATEA20
RCIN#
SCI#
KBSMI#

T112
T61
29
SUSB#
29
SUSC#
29
DNBSWON#
17 SB_PWRGD_IN
11
SUS_STAT#

Part 4 of 5

SB700
USB MISC

R255

U6D

11/01 chagne +3VSUS to +3V_S5

USB 1.1

SB_TEST1

USB 2.0

SB_TEST0

*2.2K_4

GPIO

*2.2K_4

R258

ACPI / WAKE UP EVENTS

R249

+3V_S5

2

NC only ,Can't be install

15

MB ID Selection Table

BOARD_ID2

MB ID

BOARD_ID4

BOARD_ID4

R227

*1K_4

R228

*1K_4

R229

+3V

Board ID
R232

10K_4

NEW CARD
CARD BUS

BOARD_ID1

R223

10K_4

CCFL Panel
LED Panel

IV@1K_4

BOARD_ID2

R225

EV@10K_4

W/ MXM
W/O MXM

R248

*1K_4

BOARD_ID3

R246

TV@10K_4

W/ S-VIDEO
W/O S-VIDEO

R343

*1K_4

BOARD_ID4

R342

HDM@10K_4

W/ HDMI
W/O HDMI

BOARD_ID0

R292

ID4

ID3

ID2

ID1

ID0
H
L

R233
A

10K_4
10K_4
LOW_DET
R236
*1K_4

LOW_DET 28

High : Main Strem
Low : Low Cost

FM_DET

FM_DET

28

High : W/O FM
Low : W FM

H
L

A

H
L
H
L

PROJECT : BD3G

H
L

Quanta Computer Inc.

12/4 change PD from 10K to 1K

Size

Document Number

Date:

Thursday, May 29, 2008

Rev
1A

SB700-ACPI/GPIO/USB 2/4
5

4

3

2

Sheet
1

14

of

42

5

4

SATA PORT 0,1,2,3
can support AHCI
mode

3

2

1

14

PLACE SATA AC COUPLING
CAPS CLOSE TO SB700

U6B

C268
C269

SATA_TXP1
SATA_TXN1

27
27
27
27

E-SATA

SATA_RXN1
SATA_RXP1

C255
C252

SATA_TXP2
SATA_TXN2

27
27

C275
C280

SATA_RXN2
SATA_RXP2

SATA_RXN0_C AB10
SATA_RXP0_C AC10

SATA_RX0N
SATA_RX0P

R221
R222

4.99/F_4 SATA_TXP1_C AE10
4.99/F_4 SATA_TXN1_C AD10

SATA_TX1P
SATA_TX1N

SATA_RXN1_C AD11
SATA_RXP1_C AE11

SATA_RX1N
SATA_RX1P

4.99/F_4 SATA_TXP2_C AB12
4.99/F_4 SATA_TXN2_C AC12

SATA_TX2P
SATA_TX2N

0.01u/16V_4
0.01u/16V_4

SATA_TXP2_R
SATA_TXN2_R

0.01u/16V_4
0.01u/16V_4

SATA_TX0P
SATA_TX0N

0.01u/16V_4
0.01u/16V_4

SATA_TXP1_R
SATA_TXN1_R

0.01u/16V_4
0.01u/16V_4

C277
C276

R164
R162

SATA_RXN2_C AE12
SATA_RXP2_C AD12

0.01u/16V_4
0.01u/16V_4

2/22 change SATA ODD from port3 to port4 (solve ODD
post detect fail)

27
27

ODD

C262
C265

SATA_TXP3
SATA_TXN3
27
27

C

SATA_TXP3_R
SATA_TXN3_R

0.01u/16V_4
0.01u/16V_4

SATA_RXN3
SATA_RXP3

C278
C279

R206
R207

4.99/F_4
4.99/F_4

0.01u/16V_4
0.01u/16V_4
T50
T49

SATA PORT 4,5 are
only support IDE
mode

R361
R205

T126
T124

NOTE:

30

PLVDD_SATA--

SATA_TX3P
SATA_TX3N

AB14
AC14

SATA_RX3N
SATA_RX3P

SATA_TXP4_C AE14
SATA_TXN4_C AD14

SATA_TX4P
SATA_TX4N

SATA_RXN4_C
SATA_RXP4_C

AD15
AE15

SATA_RX4N
SATA_RX4P

SATA_TXP5_C
SATA_TXN5_C

AB16
AC16

SATA_TX5P
SATA_TX5N

SATA_RXN5_C
SATA_RXP5_C

AE16
AD16

SATA_RX5N
SATA_RX5P

V12

SATA_CAL

SATA_X1

Y12

SATA_X1

SATA_X2

AA12

SATA_X2

SATA_LED#

W 11

SATA_ACT#/GPIO67

+1.2V_PLLVDD_SATA

AA11

PLLVDD_SATA

+3V_XTLVDD_SATA

W 12

SATA_LED#

R361 IS 1K 1% FOR 25MHz
SATA PLL
XTAL, 4.99K 1% FOR 100MHz POWER
INTERNAL CLOCK

Part 2 of 5

SATA_RX2N
SATA_RX2P

AD13
AE13

SATA_RBIAS_PN

1K/F_4

10/25 modify it
PLACE SATA_CAL
RES VERY CLOSE
TO BALL OF SB700

SB700

AD9
AE9

XTLVDD_SATA

XTLVDD_SATA-- SATA
crystal power
C257

2

SATA_X1
27p/50V_4

12/8 change from 10p to 27p

Y2

B

R161
10M_6

IDE_IORDY
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_DACK#
IDE_DRQ
IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#

AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23

SPI_DI/GPIO12
SPI_DO/GPIO11
SPI_CLK/GPIO47
SPI_HOLD#/GPIO31
SPI_CS#/GPIO32
LAN_RST#/GPIO13
ROM_RST#/GPIO14

PDIORDY
IRQ14
PDA0
PDA1
PDA2
PDDACK#
PDDREQ
PDIOR#
PDIOW#
PDCS1#
PDCS3#
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

G6
D2
D1
F4
F3
U15
J1

D

27

C

T76
T109
T113
T79
T115
T55
T116

ROM_RST#

12/4 change BOARD ID3 from GEVENT7 to GPIO48

BOARD_ID4
BOARD_ID3
BOARD_ID2

FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49
FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52

P5
P8
R8

SB_FANTACH0
SB_FANTACH1
PORT_80_PWR_DWN

TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63
TEMPIN3/TALERT#/GPIO64

C6
B6
A6
A5
B5

TEMPIN0
TEMPIN1
MB_THRMDA_SB
R287

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

A4
B4
C4
D4
D5
D6
A7
B7

SATA_X2

27
27
27
27
27
27
27
27
27
27
27

PDD[0..15]

M8
M5
M7

1

25MHZ
C258

ATA 66/100/133

27
27

SATA2

SATA_RXN0
SATA_RXP0

C261
C259

4.99/F_4 SATA_TXP0_C
4.99/F_4 SATA_TXN0_C

R220
R215

SPI ROM

D

27
27

SATA_TXP0_R
SATA_TXN0_R

0.01u/16V_4
0.01u/16V_4

HW MONITOR

C267
C266

SATA_TXP0
SATA_TXN0

SERIAL ATA

27
27

SATA PWR

SATA1

VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7

BOARD_ID4 14
BOARD_ID3 14
BOARD_ID2 14
T57
T59
T63

0_4

T95
T97
T99
THERM_ALERT# 4

T105
T101
T88
T86
T91
T90
T100
T96

+1.2V

( 1.2V @ 60mA) +1.2V_PLLVDD_SATA

AVDD

F6

AVSS

G7

5mA

+3V_VDD_HWM
C375
0.1u/10V_4

B

+3V

AVDD--H/W monitor
Analog power

27p/50V_4

SB700

11/02 modify it

10/18 AMD suggest to connect to GND

L31

0_6

C366
2.2u/6.3V_6

2/13 EMI
stuff C375,C366 for SB HW MONITOR

77mA

L24
BLM18PG221SN1D(220,1.4A)_6
C290
1u/10V_4

C260
0.1u/10V_4

1mA

+3V

( 3.3V @ 1.2mA)

+3V_XTLVDD_SATA

L26
BLM18PG221SN1D(220,1.4A)_6
A

A

C300
1u/10V_4

Place near
ball

PROJECT : BD3G
Quanta Computer Inc.
Size

Document Number

Rev
1A

SB700-SATA/IDE/HWM/SPI 3/4
Date:
5

4

3

2

Thursday, May 29, 2008

Sheet
1

15

of

42

5

4

3

2

1

PLACE ALL THE DECOUPLING CAPS ON
THIS SHEET CLOSE TO SB AS POSSIBLE.

23

12/14 del R234 stuff R235 for A12
VDD-- S/B CORE power

A10
B10

2

2

1
2

2

+1.2V

C331
*2.2u/6.3V_6

1
C326
0.1u/10V_4

2

C487
0.1u/10V_4

0_6
1

Change to 0603

S5_1.2V--1.2V standby power
R250
2

0_6
1

+1.2V_S5

1

0.22A

0.2A

+3V_S5

C482
10u/6.3V_8

+1.2VALW_R

USB_PHY_1.2V_1
USB_PHY_1.2V_2

1

1

1
2

1

1

1

S5_1.2V_1
S5_1.2V_2

G2
G4

R336
2

1

C284
1u/10V_4

AVDD_SATA_1
AVDD_SATA_4
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7

0_6
1

4/24 internal clk not use
remove C332,C330,C327,C331
change L28 to 0 ohm
S5_3.3--3.3v standby power

2

1
2

C292
1u/10V_4

AA14
AB18
AA15
AA17
AC18
AD17
AE17

SATA I/O

0.2A

1
C295
0.1u/10V_4

2

C304
0.1u/10V_4

2

2

C521
10u/6.3V_8

1

1

1
2

BLM18PG221SN1D(220,1.4A)_6

C327
*0.1u/50V_6

C335
0.1u/10V_4

C342
0.1u/10V_4

+1.2V_USB_PHY_R

+3V_AVDD_USB

AVDDTX--USB Phy
Analog I/O power

1

AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20

A15
B15
C14
D8
D9
D11
D13
D14
D15
E15
F12
F14
G9
H9
H17
J9
J11
J12
J14
J15
K10
K12
K14
K15

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24

J16

AVDDCK_1.2V

K17

+3V_AVDDCK

7mA

+1.2V_AVDDCK

44mA

R436

AVDDC

E9

+3V_AVDDC

2 1K/F_4

1
1
D31

1

AVDDCK_3.3V

4mA

+5V_VREF

C274
1u/10V_4

2

+5V

H18
J17
J22
K25
M16
M17
M21
P16

+3V

CH501H-40PT

16mA

F9

PCIE_CK_VSS_1
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_4
PCIE_CK_VSS_5
PCIE_CK_VSS_6
PCIE_CK_VSS_7
PCIE_CK_VSS_8
AVSSC

SB700

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21
AVSSCK

Part 5 of 5

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

D

C

P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25

B

L17

SB700

C333
0.1u/10V_4

+3V_S5

+3V_AVDDC

+1.2V_USB_PHY_R

AVDDC--USB Analog PLL power

2

2

C389
0.1u/10V_4

1

C485
C481
C478
0.1u/10V_4
0.1u/10V_4
10u/6.3V_8

1
C413
10u/6.3V_8

2

1

USB_PHY_1.2V--USB Phy
digital power

1

0_6
1

1

R334
2

L32
BLM18PG221SN1D(220,1.4A)_6

2

+1.2V_S5

2

C483
0.1u/10V_4

2

1
C379
0.1u/10V_4

2

1
C388
0.1u/10V_4

2

1
2

1
C489
1u/10V_4

2

1
C334
1u/10V_4

2

+1.2V

A

+1.2V_AVDDCK

1
C336
2.2u/6.3V_6

L30
BLM18PG221SN1D(220,1.4A)_6

A

+3V_AVDDCK

AVDDCK_3.3--Analog
system PLL power

2

2

L29
BLM18PG221SN1D(220,1.4A)_6

+3V

AVDDCK_1.2--USB Phy
digital power

PROJECT : BD3G

1

C367
1u/10V_4

2

1

B

V5_VREF

AE7

2

C484
0.1u/10V_4

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDTX_5
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDRX_5

PLL

A16
B16
C16
D16
D17
E17
F15
F17
F18
G15
G17
G18

1
C488
0.1u/10V_4

2

1
C475
10u/6.3V_8

2

1

1
2

C477
10u/6.3V_8

2

+3V_S5

BLM18PG221SN1D(220,1.4A)_6

T10
U10
U11
U12
V11
V14
W9
Y9
Y11
Y14
Y17
AA9
AB9
AB11
AB13
AB15
AB17
AC8
AD8
AE8

V5_VREF--PCI 5V TOLERANCE

0.2A

L33

USB I/O

For support USB wakeup-->3V_S5

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

GROUND

+1.2V_AVDD_SATA

AVDD_SATA--SATA phy power

+1.2V

C281
10u/6.3V_8

2

0.01A

U6E

SB700

C323
1u/10V_4

L28

*0.1u/50V_6

+3VALW_R

A17
A24
B17
J4
J5
L1
L2

C324
1u/10V_4

C330

*2.2u/6.3V_6

2

C308
1u/10V_4

L35

+1.2V

C332

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

2

286mA

L21
L22
L24
L25

R235
1 0_8

CKVDD_1.2V-- Internal
clock Generator I/O
power

1

2

C299
1u/10V_4

PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7

3.3V_S5 I/O

1

1
C303
1u/10V_4

2

C311
1u/10V_4

2

2

2

C302
1u/10V_4

1

1

1

1
2

C

C301
10u/6.3V_8

P18
P19
P20
P21
R22
R24
R25

CORE S5

844mA

A-LINK I/O

PCIE_VDDR--PCIE I/O power
L34

+1.2V

C314
1u/10V_4

POWER

+1.2V_PCIE_VDDR

BLM18PG221SN1D(220,1.4A)_6

CLKGEN I/O

4/24 IDE/FLASH not use
,remove
C287,C288,C297,C293,C294

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

2

VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4

IDE/FLSH I/O

1

Y20
AA21
AA22
AE25

C294
*1u/10V_4

2

1
2

2

+1.2V_CKVDD

0.45A

C288
C297
C293
*1u/10V_4 *1u/10V_4 *1u/10V_4

2

1
2

C287
*10u/6.3V_8

1

VDD33_18--3.3V IDE I/O power
1.8V flash memory I/O power

1 0_8

1

R231 2

+1.8V

C312
1u/10V_4

1

+VDD33_18

1

L15
M12
M14
N13
P12
P14
R11
R15
T16

1

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

2

1.8V : FLASH MEMORY MODE(DEFAULT)
3.3V: IDE MODE

10/18 change to +1.8V

Part 3 of 5

2

C291
1u/10V_4

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12

2

C313
1u/10V_4

2

C305
1u/10V_4

2

C320
1u/10V_4

2

C298
1u/10V_4

2

C307
1u/10V_4

2

C282
10u/6.3V_8

2

D

2

2

100u/6.3V_3528

L9
M9
T15
U9
U16
U17
V8
W7
Y6
AA4
AB5
AB21

604mA

2

+

SB700
CORE S0

1

1

1

1

1

1

1

C285

+1.2V_VCC_SB_R

U6C

0.8A

PCI/GPIO I/O

VDDQ--3.3V I/O power

1

+3V

0_8
1

2

+3.3V_SB_R
R237
2

C337
2.2u/6.3V_6

Quanta Computer Inc.
Size

Document Number

Rev
1A

SB700-PWR/DECOUPLING 4/4
Date:
5

4

3

2

Thursday, May 29, 2008

Sheet
1

16

of

42

4

3

2

+3V

+3V

+3V

+3V_S5
+3V_S5
1

1
2

REQUIRED STRAPS

ACZ_RST#
RTC_CLK
PCLK_DBC
PCLK_591
PCI_CLK5
PCI_CLK4
PCI_CLK3
PCI_CLK2

SB_GPIO17
SB_GPIO16
1

14
14

D

Maybe can be remove -- internla pull up
check AMD

R337
2.2K_4
2

1

R273
*10K/F_4

2

2

R422
10K/F_4

GPIO16

R275
2.2K_4

GPIO17

PCI_CLK2
C

BOOTFAIL
TIMER
ENABLED

PULL
HIGH

1

R242
10K/F_4

R347
10K/F_4

PCI_CLK4

PCI_CLK5

LPC_CLK0

LPC_CLK1

RTC_CLK

AZ_RST#

USE
DEBUG
STRAPS

RESERVED

RESERVED

ENABLE PCI
MEM BOOT

CLKGEN
ENABLED

INTERNAL
RTC

EC
ENABLED

BOOTFAIL
TIMER
DISABLED

IGNORE
DEBUG
STRAPS

DISABLE PCI
MEM BOOT

DEFAULT

DEFAULT

DEFAULT

CLKGEN
DISABLED
DEFAULT

EC
ENABLED

DEBUG STRAPS

GPIO16

GPIO17

FWH

L : 2.2K
pull down

L : 2.2K
pull down

LPC

NC

L : 2.2K
pull down

SPI

L : 2.2K
pull down

NC

NC

NC

2

PCI_CLK3

DEFAULT

PULL
LOW

TYPE

2

1
R256
10K/F_4
2

R398
*10K/F_4
2

R429
*10K/F_4
2

R370
10K/F_4
2

2

R368
10K/F_4

1

1

1

1

1

2

R344
*2.2K_4
2

14
13
13,25
13,29
13
13
13
13

R426
10K/F_4

2

R395
*10K/F_4

2

R365
*10K/F_4

1

1

1

A11 stuff 2.2K
A12 stuff 10K
D

16

OVERLAP COMMON PADS WHERE
POSSIBLE FOR DUAL-OP RESISTORS.

It must ready
refore RSMRST#
+3V

1

1

5

EXT. RTC
(PD on X1,
apply
32KHz to
RTC_CLK)

EC
DISABLED

RSVD

DEFAULT

NB_PWRGD_IN:
RS780/RX780 = 1.8V; RS740 = 3.3V
Do NOT share it with SB_PWRGD when use Internal Clk Gen
(Need SB PLL initialize firstly)

ENABLE PCI
MEM BOOT

SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

+3V_S5

R150

*10K/F_4

+3V

R152

10K/F_4

SB_PWRGD
A11 use external ckt
A12 Asserting SYS_RESET# will de-assert SB PWRGOOD internally
R151

SB_PWRGD_IN

0_4

SB_PWRGD_IN 14

C246
*2.2u/6.3V_6
AD28
AD27
AD26
AD25
AD24
AD23

+1.8V
+1.8V
B

4/10 change R150 to R152 for power sequence
U3

2

1

1

1

1

1
1

13,26
13,26
13,26
13,26
13,26
13,26

1

B

C

3
R427
*10K/F_4
2

R431
*10K/F_4
2

R434
*10K/F_4
2

R430
*10K/F_4
2

R432
*10K/F_4
2

2

R433
*10K/F_4

D6
1

20,29 ECPWROK

CH501H-40PT
2

NC VCC

C249

5

R153
300_4
RX780,RS780

*0.1u/10V_4

A
GND

Y

R154

4

NB_PWRGD_IN

*33_4

NB_PWRGD_IN 11

*NL17SZ17DFT2G
SOT-353
R157

*10K/F_4

+1.8V

Use 2.2K PD.
0_4

NB/SB POWER GOOD CIRCUIT
PCI_AD28
PULL
HIGH

PULL
LOW
A

PCI_AD27

PCI_AD26

PCI_AD25

PCI_AD24

PCI_AD23

USE
LONG
RESET

USE PCI
PLL

USE ACPI
BCLK

USE IDE
PLL

USE DEFAULT
PCIE STRAPS

RESERVED

DEFAULT

DEFAULT

DEFAULT

DEFAULT

DEFAULT

USE
SHORT
RESET

BYPASS
PCI PLL

BYPASS
ACPI
BCLK

BYPASS IDE
PLL

USE EEPROM
PCIE STRAPS

U11
RX780
RS780M

V

V

X

WD_PWRGD 14

0.01u/16V_4

R230 R229 R245 R234

V

R159

C765

WD_PWRGD: Push/Pull when A11SB700, OD when A12SB700.

X

AL17SZ17000

IC(5P) NL17SZ17DFT2G(SOT-353)

SOT-353

ALUC1G17000

IC OTHER(5P) SN74AUC1G17DBVR(SOT23-5)

SOT23-5

12/18 add cap for NB_PWRGD signal
A

4/24 stuff C765 10nf to meet power sequence

PROJECT : BD3G
Quanta Computer Inc.
Size

Document Number

Date:

Thursday, May 29, 2008

Rev
1A

SB700-STRAPS
5

4

3

2

Sheet
1

17

of

42

5

4

TVOUT

3

2

1

BTO
5/8 stuff D9,D11 for S-VIDEO

21

EXT_TV_C/R
C790

12/21 EMI
add 27p for TV_Y/G , TV_C/R

+3V

close to NB & VGA connector
R497

EV@0_4

SYS_TV_Y/G

R496

EV@0_4

SYS_TV_C/R

BTO

+3V

1

EXT_TV_Y/G

1

TVOUT
21

D9
3 TV-CHROMA

C791

D11
3 TV-LUMA

TV@DA204U

11
11

INT_TV_Y/G
INT_TV_C/R
C792
IV@27p/50V_4

R189

IV@0_4

TV@DA204U

R190

IV@0_4

D

2

EV@27p/50V_4

2

EV@27p/50V_4

D

C793
IV@27p/50V_4

L14

TV@BLM18PG181SN1D
TV-CHROMA

SYS_TV_C/R

R105

C149

TV@150/F_4

TV@6p/50V_4

CN22

4

6

C148

L20

4

6

SYS_TV_Y/G

5

5

TV@BLM18PG181SN1D

TV-LUMA

3

3

C214

TV@6p/50V_4

C215

TV@6p/50V_4

2

2

R158

TV@6p/50V_4

TV@150/F_4

1

1

TV@SUYIN_030018FR004S100FR

B:(10/24) change CN22 from 7PIN to 4PIN CONN

10/24 modify it to 4 pin BOI request
10/30 modify footprint to SV-030018FR004S100FR-RVS-4P-H
12/12 update p/n to DFMD04FR006
4/16 update footprint to sv-030018fr004s100fr-4p-h-bl5m

C

C

CRT PORT
2/10 DEL D4,D5 footprint and DEL
CRT_SENSE# net

10/12 fix CRT connect error
1/31 EMI Change L4,L5,L6 from CX0HM121008 to CX8BA470003
C433
+5V

D30
2

SSM14
1

5V_CRT2

1

21 EXT_VGA_BLU
21 EXT_HSYNC
21 EXT_VSYNC
21 EXT_CRT_DDCCLK
21 EXT_CRT_DDCDAT

R195
R194

EV@0_4
EV@0_4
EV@0_4

BLM18BA470SN1_6

CRT_R1

L5

BLM18BA470SN1_6

CRT_G1

CRT_B

L4

BLM18BA470SN1_6

CRT_B1

6
1
7
2
8
3
9
4
10
5

CRT_B

EV@0_4

R197

EV@0_4

VSYNC

R193

EV@0_4

DDCCLK

EV@0_4

L6

CRT_G
CRT_G

R198

R192

CRT_R
CRT_R

R8
150/F_4

HSYNC

C11
6.8p_4

R6
150/F_4

C8
6.8p_4

R4
150/F_4

C5
6.8p_4

C4
6.8p_4

C7
6.8p_4

C10
6.8p_4

DSUB-070549FR015SX03CX-15P-V

DDCDAT

2/13 EMI
C4,C7,C10,C5,C8,C11 change from 10p to 6.8p

A:(8/20) change from 39 to 0 ohm
Because MXM side already be stuff 30ohm

11

T175

12

B

13
14
15

17

21 EXT_VGA_GRN

R196

CN18

25 MIL

FUSE1A6V_POLY-1A-6V

close to NB & VGA connector
21 EXT_VGA_RED
B

10/25 no use sense

0.1u/10V_4

F4

2

16

2/1
RS780M A13 R8 ---> 140 CS11402FB19
MXM
R8 ---> 150 CS11502FB21

A:(8/20) Reserve Diode for ESD solution

U4
5V_CRT2
11 INT_CRT_RED
11 INT_CRT_GRN
11 INT_CRT_BLU
11 INT_HSYNC
11 INT_VSYNC
11 INT_CRT_DDCCLK
11 INT_CRT_DDCDAT

R184

IV@0_4

R183

IV@0_4

R182

IV@0_4

R187

IV@0_4

R186

IV@0_4

R181

IV@0_4

R180

IV@0_4

1

+5V
C25

0.22u/10V_6

7
8
2

+3V
CRT_R1
CRT_G1
CRT_B1

3
4
5
6

VCC_SYNC SYNC_OUT2
SYNC_OUT1
VCC_DDC
BYP
SYNC_IN2
VCC_VIDEO
SYNC_IN1
VIDEO_1
VIDEO_2
VIDEO_3

DDC_IN1
DDC_IN2
DDC_OUT1
DDC_OUT2

GND

16
14

VSYNC1
HSYNC1

15
13

VSYNC
HSYNC

10
11

DDCCLK
DDCDAT

R14
R13

0_4
0_4

L8
L7

VSYNC1_CRT
HSYNC1_CRT

BLM18BA220SN1D_6CRTVSYNC
CRTHSYNC
BLM18BA220SN1D_6
LCD_ON
C14
C13
5V_CRT2

R5

R7

6.8K_4

6.8K_4

9
12

CM2009

H=1.75mm
+3V

+5V

C24
0.1u/10V_4

C18
0.1u/10V_4

DDCCLK

R22

4.7K_4

DDCDAT

R21

4.7K_4

+3V

*10p/50V_4

*10p/50V_4
A:(9/3) default no stuff

A:(8/28) change from 2.7k to 6.8k
Follow AMD check list
CRTDCLK
CRTDDAT
C6

C9

*10p/50V_4

*10p/50V_4

A:(8/27) default no stuff

A:(8/28) change from 2.2k to 4.7k
Follow AMD check list

A

A

PROJECT : BD3G
Quanta Computer Inc.
Size

Document Number

Date:

Thursday, May 29, 2008

Rev
2A

SB600 STRAPS/TV/CRT
5

4

3

2

Sheet
1

18

of

42

5

4

3

2

+3V_S5

BTO (all parts in the page)

SB_SCLK2 14
SB_SDATA2 14

2

CEC_POWER

To SB
C84

*CEC@0.1u/10V_4

CEC-RESET#
CEC-MODE

4
2

VCC
VCC

4
6

CEC-RESET#

T15

CEC-MODE

SCL
SDA
DDCSDA
DDCSCL

XOUT
XIN

3
8

TEST1
TEST0

RESET
MODE

RP10

T11

CEC_SCL

U13

5

3

5
15
14
11

CEC OUT
CEC IN

VSS
NC
NC
NC

HPDET
NC

1
20
18
17
13
12

CEC_SCL
CEC_SDA

1
2
3

4

RP7

CEC_SCL_S
CEC_SDA_S

C67
CEC@FDV301N
*CEC@0.1u/10V_4

HDMI_CEC_SDA
HDMI_CEC_SCL

10
9

CEC_OUT
CEC_IN

19
2

HPDET

3
1

3ND_MBCLK 21,28,29
3ND_MBDATA 21,28,29

CEC_POWER

+3VPCU

R81

Q22

D

D8
CEC@CH500H-40

CEC@10K_4
CEC_IN

CEC_SDA

3

CEC_SDA_S

1

R93
CEC@27K_4

C66
CEC@FDV301N
*CEC@0.1u/10V_4

Q24
CEC

1

CEC@R5F211A4C21SP#W4
CEC@2SK3541

8/30 Change HDMI HPD circuit

To HDMI CONN Pin 13
CEC_POWER

Reserve Test Pad for Debug
REV04 Reserve Test Pad for Debug

R92

C60

CEC@0.1u/10V_4
HPDET

CEC_OUT

U9

5

1/31 DChange U11 from ARBL5SV0000 to ARBL5MV0000

4

1
R78

1
2
3

CEC@27K_4
CEC@2SK3541
Q25

2

*CEC@0_4

3

2

U10

CEC_POWER

*CEC@NL17SZ17

CEC_P

3 CEC@4.7KX2
1
CEC_POWER

4
2

4
2

9/07 Add
To EC

CEC@0_4P2R_S

CEC-RESET#

+5VPCU

CEC_SCL_S

1

3

XIN_CEC
XOUT_CEC

R90
R91

*CEC@G691L308T73UF

3
1
2

Q23

2

1
2

CEC@47K_4
CEC@47K_4

3
1
CEC@4.7KX2

*CEC@0.1u/10V_4

Vcc
Reset#
GND

1
3
*CEC@0_4P2R_S

RP8

7
16

CEC_POWER
C69

R68
CEC@2.2K_4

U11

XOUT_CEC
CEC_POWER

D

R69
CEC@2.2K_4

C56
CEC@0.1u/10V_4

*CEC@8 MHz
*CEC@22p_6

2
4

CEC_P

C55
Y4
CEC@1u/10V_6

C81

RP9

CEC@0_4
R86

*CEC@0_4
R87

XIN_CEC

*CEC@22p_6

11/01 no stuff U13 to avoid leakage

Named to SCLK1 & SDATA1 from SCLK & SDATA

CEC_POWER

C80

1

+3VPCU

CEC_POWER

+3VPCU

REV02 Add C5806

R52

REV02 SWAP net
To EC

CEC@0_4

29

CEC_EC_HP

REV02 Add C5807
C53

21

R61
EV@1K_4

DVI_HPD

REV02 Add R5812,R5813
Named to HDMI_HPD from HDMI_HP
HDMI_HPD
HDM@1.2K_4

R64

1

2/4 reserve C798 PLTRST#

4
2

PLTRST#

PLTRST#

13,21,24,25,27,29

C

3

C

From HDMI conn Pin 19
(Hot Plug Det)

R62
HDM@470K_4

CEC@NL17SZ17

HDM@0.1u/10V_4

5

To IV/EV VGA
Hot Plug Detect

+3V

R82
CEC@100K_4

CEC@NL17SZ17

CEC_POWER
HDM@0.1u/10V_4
U8
5
1
2
4
3

C52

R63
IV@1K_4

11 IV_HDMI_HPD

U7
HDM@TC7SH08FU

C798
PLTRST#

Named to IV_HDMI_HPD from HTPLG

REV02 Modify net to PLTRST#
*.1U_4

HDMI

close to NB & VGA connector
10 IV_HDMITX2P
10 IV_HDMITX2N

IV_HDMITX2P
IV_HDMITX2N

21 EXT_HDMITX2P
21 EXT_HDMITX2N
10 IV_HDMITX1P
10 IV_HDMITX1N

RN19
IV_HDMITX1P
IV_HDMITX1N

RN20
IV_HDMITX0P
IV_HDMITX0N

21 EXT_HDMITX0P
21 EXT_HDMITX0N
10 IV_HDMICLK+
10 IV_HDMICLK-

B

A:(8/21) change net name from
INT_LVDS_EDIDCLK to IV_HDMI_DDCCLK

RN5

RN21
IV_HDMICLK+
IV_HDMICLK-

21 EXT_HDMICLK+
21 EXT_HDMICLK-

11 IV_HDMI_DDCCLK
11 IV_HDMI_DDCDATA

RN6

2
4

1 IV@0X2
3

2
4

1
3

2
4

1 IV@0X2
3

2
4

1
3

10/18 update footpritnt HDMI-C12816-119A5-L-19P-H-BL5

HDMITX2P_C
HDMITX2N_C

12/4 update footprint to HDMI-C12816-119A5-L-19P-V-BL5-1
12/7 update footprint to HDMI-C12816-119A5-L-19P-H-BD3

EV@0X2

1/17 update footprint to HDMI-C12816-119A5-L-19P-H-BL5
CN25

HDMITX1P_C
HDMITX1N_C
HDMITX2P_C

21 EXT_HDMITX1P
21 EXT_HDMITX1N
10 IV_HDMITX0P
10 IV_HDMITX0N

RN7

RN8

RN18
IV_HDMI_DDCCLK RN4
IV_HDMI_DDCDATA
RN17

21 EXT_HDMI_DDCCLK
21 EXT_HDMI_DDCDAT

EV@0X2

2
4

1 IV@0X2
3

2
4

1
3

2
4

1 IV@0X2
3

2
4

1
3

HDMITX0P_C
HDMITX0N_C

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

HDMITX2N_C
HDMITX1P_C

1/31 DEL L56,L57,L58,L59,R465,R474,R493,R495,R486,R488,R478,R483,C226,C227 for
HDMI circuit

HDMITX1N_C
HDMITX0P_C
HDMITX0N_C
HDMICLK+_C

EV@0X2
HDMICLK-_C
CEC

HDMICLK+_C
HDMICLK-_C

HDMI_SCL
HDMI_SDA

EV@0X2

2
4

1 IV@0X2
3

4
2

3 EV@0X2
1

2/13 EMI
stuff C808 for HDMI

HDMI_DDCCLK
HDMI_DDCDATA

DDC5V
HDMI_HPD

D2+
D2 Shield
D2D1+
D1 Shield
D1- SHELL1
D0+ SHELL2
D0 Shield
D0- SHELL3
CK+ SHELL4
CK Shield
CKCE Remote
NC
DDC CLK
DDC DATA
GND
+5V
HP DET

C808
HDM@0.1u/10V_4

20
21
22
23

B

HDM@HDMI-C12816-119A5-L

10/22 add level shift for CEC
R174

IV@750_4

HDMITX2P_C

R175

IV@750_4

HDMITX2N_C

R176

IV@750_4

HDMITX1P_C

R177

IV@750_4

HDMITX1N_C

R185

IV@750_4

HDMITX0P_C

R191

IV@750_4

HDMITX0N_C

R172

IV@750_4

HDMICLK+_C

R173

IV@750_4

HDMICLK-_C

2/4 let layout smooth to modify ckt
3

2/1 change R1,R2 to 6.8K
2/1 change R168,R171,R163,R170 to 4.7K
CEC_POWER

Q64
IV@FDV301N

+5VPCU
HDMITX0N_C
HDMITX0P_C

CEC_POWER

R163
R168

R1

HDMI_DDCCLK

2
Q31
R3

A:(8/27) change from 2k to 39k
(Follow AMD check list)

3
HDM@2SK3541

HDMI_CEC_SCL

*CEC@0_4
+3V

2
Q1
R637

R170

HDM@4.7K_4

HDM@4.7K_4

HDMITX0N_C
HDMITX0P_C

10
9
8
7
6

HDMITX1N_C
HDMITX1P_C

R542

1

2
IV@100K_4

*HDM@RCIamp0514M
ESD5

HDMITX2N_C
HDMITX2P_C

*CEC@0_4

1
2
3
4
5

HDMICLK-_C
HDMICLK+_C

+5VPCU

10
9
GND
7
6

1
2
VCC
4
5

CEC_POWER
R171

10
9
GND
7
6

1
2
VCC
4
5

HDMI_SCL

3
HDM@2SK3541

CEC_POWER

1
2
3
4
5

HDMITX1N_C
HDMITX1P_C

HDM@6.8K_4

1

1

HDM@4.7K_4
HDM@4.7K_4

2

+5V
ESD6

1

+3V

HDMITX2N_C
HDMITX2P_C

10
9
8
7
6

HDMICLK-_C
HDMICLK+_C

11/01 add stitch cap for HDMI

+3V

*HDM@RCIamp0514M
C747

1

1

R2
A

2
Q32
R606

3
HDM@2SK3541
*CEC@0_4

HDMI_CEC_SDA

2
Q2
R665

HDMI_SDA

3
HDM@2SK3541

+5VPCU

HDM@POLY 1.1A
F5

HDMI_SCL
HDMI_SDA

DDC5V

HDMI_HPD

*CEC@0_4

C479
C471
*HDM@10u/10V/X5R_8

Close to HDMI Connector
5

A

HDM@6.8K_4
IV@0.1u/10V_4

ESD4
HDMI_DDCDATA

1
2
3
4
5

1
2
VCC
4
5

10
9
8
7
6

10
9
GND
7
6

HDMI_SCL
HDMI_SDA
DDC5V
HDMI_HPD

*HDM@RCIamp0514M

PROJECT : BD3G

HDM@0.1u/10V/X5R_4 Layout note:
Place close
to HDMI
Conn

Quanta Computer Inc.
Size

Document Number

Date:

Thursday, May 29, 2008

Rev
2A

HDMI + CEC
4

3

2

Sheet
1

19

of

42

3

4

5

6

7

8

LCD TYPE CONNECTOR

HALL SENSOR

VIN

0_8
R403

A

TXUCLKOUTTXUCLKOUT+

RN9

4
2

3 IV@0X2
1

INT_TXUCLKOUT- 11
INT_TXUCLKOUT+ 11

TXUOUT0TXUOUT0+

RN10

4
2

3 IV@0X2
1

INT_TXUOUT0- 11
INT_TXUOUT0+ 11

C26

INT_TXUOUT1- 11
INT_TXUOUT1+ 11

RN11

4
2

3 IV@0X2
1

TXUOUT2TXUOUT2+

RN12

4
2

3 IV@0X2
1

+3V

1 EGA

USBP2+_C

2

1 EGA

USBP2-_C

2

1 VPORT CCD_POWER

10u/25V_1206

MR4
EC2648-B3-F

C424

1000P_4

10/22 update p/n From DFHS40FS825 to DFWF40MS000

2

0.1u/10V_4

INT_TXUOUT2- 11
INT_TXUOUT2+ 11

2

D7
D75
5
D7
D76
6

C21

+

D7
D74
4

LID591#

2

3

TXUOUT1TXUOUT1+

5/7 stuff D74,D75,D76 for CCD

1

INVCC0

R23

100K_4

+3VPCU

1

2

2

1

R12
1K_4

A

D87
CN4
INVCC0

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41

1

VPORT
DISPON

2 EV@0X2
4

EXT_LVDS_TXUCK# 21
EXT_LVDS_TXUCK 21

RN27

1
3

2 EV@0X2
4

EXT_LVDS_TXU#0 21
EXT_LVDS_TXU0 21

1
3

2 EV@0X2
4

EXT_LVDS_TXU#1 21
EXT_LVDS_TXU1 21

1
3

2 EV@0X2
4

EXT_LVDS_TXU#2 21
EXT_LVDS_TXU2 21

RN26

BAS316

LID591#

+3V

29
MIC_GND
Analog MIC

2/4 stuff D87 for LID switch
+3V

R16
R15

I_MIC0_4
I_MIC0_4

BTO

R670
10K_4
Q79
ME2N7002D

CCD_POWER
MIC_GND_R
Analog MIC_R
DISPON
TXLCLKOUT+
TXLCLKOUTTXLOUT0+
TXLOUT0-

2

TXLOUT1+
TXLOUT1-

1

RN25

D27

3

1
3

3

RN28

LVDS_BLON

2

TXLOUT2+
TXLOUT2-

Q80
ME2N7002D

0_4

EC_BLON 29

LCD_EDIDDATA
LCD_EDIDCLK
LCD_VADJ
USBP2+_C
USBP2-_C
TXUCLKOUT+
TXUCLKOUTTXUOUT0+
TXUOUT0TXUOUT1+
TXUOUT1TXUOUT2+
TXUOUT2-

TXLCLKOUT+
TXLCLKOUT-

RN13 4
2

3 IV@0X2
1

INT_TXLCLKOUT+ 11
INT_TXLCLKOUT- 11

TXLOUT2TXLOUT2+

RN14 4
2

3 IV@0X2
1

INT_TXLOUT2- 11
INT_TXLOUT2+ 11

TXLOUT0TXLOUT0+

RN15 4
2

3 IV@0X2
1

INT_TXLOUT0- 11
INT_TXLOUT0+ 11

TXLOUT1TXLOUT1+

RN16 4
2

3 IV@0X2
1

3

1

R684

LCD_VCC

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

*BAS316

2

TXLOUT0+

ACES_88242-40XX_LVDS

11/01 add stitch cap for LVDS
+3V

R10
100K_4

Q4

1

D61

EC_FPBACK# 29
+3V

DTC144EU

LCD PANEL MODULE

INT_TXLOUT1- 11
INT_TXLOUT1+ 11

C48
C73
0.1u/10V_4
0.1u/10V_4

12/4 modify display on ckt to avoid flash when into S3/S4/S5
B

B

2 EV@0X2
4

EXT_LVDS_TXLCK 21
EXT_LVDS_TXLCK# 21

RN24 1
3

2 EV@0X2
4

EXT_LVDS_TXL0 21
EXT_LVDS_TXL#0 21

RN23 1
3

2 EV@0X2
4

EXT_LVDS_TXL1 21
EXT_LVDS_TXL#1 21

RN22 1
3

2 EV@0X2
4

EXT_LVDS_TXL2 21
EXT_LVDS_TXL#2 21

CCD_POWER

C429

0.1u/10V_4

+3V

C428

0.1u/10V_4

C427

0.1u/10V_4

+15V
+3V
R18

65mil

Q51
AO3404

330K_6

+3VPCU

LCD_VCC

2/13 EMI
stuff C427~C432

LCD_VCC

LCDONG 2

C430
100p/50V_4
LCD_EDIDDATA

L49
0_6

3

LCDVCC1

1

C22
R406

65mil

0.01u/25V_4

65mil

100K_4
A:(8/20) Remove switch IC, Modify ckt to original ckt

EMI CAP

3

RN29 1
3

1/17 EnegryStar 4.0 Idle power issue
When BLON= High, Turn ON LCD then turn ON MMB
When BLON= Low, Turn OFF LCD then turn OFF MMB

C17

+3V

C19

C15

0.01u/16V_4

10u/6.3V_6

C431

100p/50V_4

C432

100p/50V_4

LCD_EDIDCLK

R407
0.1u/16V_4

2
22_8

LVDS_DIGON

3

LCDON#

2

LCD_EDIDCLK

R413

LCD_VADJ

2

EV@0_4

Q50

1

R414

11 INT_LVDS_EDIDCLK

LCDDISCHG

2/1 change Panel SDA/SDC pull res R412,R410 from 39K to
4.7K

IV@0_4
+3V

C

ME2N7002D
100K_4

1

21 EXT_LVDS_PNLCLK

3

Q7
ME2N7002D
Q10
PDTC143TT

4.7K_4
A:(8/27) change from 2.2K to 39K

1

R412

R20
C

R410
11 INT_LVDS_PWM

4.7K_4
R409

21 EXT_LVDS_PNLDAT

R411

11 INT_LVDS_EDIDDATA

29

LCD_EDIDDATA

EV@0_4
IV@0_4

A:(8/28) change from 2.2K to 4.7K
Follow AMD check list

EV@0_4

R540

IV@0_4

INT_LVDS_DIGON

C27

1
Q53

2

C29

15K_4

2

*39K_4
17,29 ECPWROK

R537

IV@0_4

R525

EV@0_4

NB_PWRGD_+5V

3
FDV301N

CCD@10u/10V_8

C754
R17
*CCD@4.7K_4

*CCD@1000p_4

C23

0.1u/10V_4

I_MIC@100P_4

11

FDV301N

I_MIC@100P_4

BTO
R721
*0_4

CCD_USBP2- 14
CCD_USBP2+ 14

BTO

R19
*I_MIC@0_4

ADOGND1
12/21 EMI
stuff C23,C20 100p

0.65v 4.8uF (0.1uF +4.7uF)
(2)Please put these caps closed to IC
(3)R4101(pin 19,OC#) value should change to 2k ohm.

+NEW_3V

12/10 Change New card footprint to NCARD-13180151-T-26P-L-BL5S

New card

CN15

New Card's Power Switch

CPPE# : ( Internal Pull Up , active low when card support PCIE )
CPUSB# : ( Internal Pull Up , active low when card support USB )

2

SHDN# : ( Internal Pull Up )
3
1
NEW_SMDATA

*NEW@2N7002E
R574

+3V

2
4

+3V_S5

17

NEW@0_4

+NEW_3V

12
14

+1.5V

A

3

PLTRST#

*NEW@2N7002E
2/4
R565
NEW@0_4
A:(8/23) change to another SMBus channel.
SCL1/SDA1 is dedicated SMbus interface for ASF devices only.

6
20

T154
RCLKEN

NEW_SMCLK

1

PLTRST#

reserve C799 PLTRST#

18
16
7

T160

3.3VIN
3.3VIN

3.3VOUT
3.3VOUT

AUXIN

AUXOUT

1.5VIN
1.5VIN

1.5VOUT
1.5VOUT

SYSRST#
SHDN#
RCLKEN
NC
GND

NEW@G577BSR91U

3
5

+NEW_3V

15

+NEW_3VAUX

11
13

+NEW_1.5V

OMC

AL005538001

Ricoh

AL002231000

TI

10 PCIE_RXP3
10 PCIE_RXN3
3 CLK_PCIE_NEW
3 CLK_PCIE_NEW#

+3V_S5

3

1
+NEW_1.5V

10/31 add newcard det#

NEW_SMDATA
NEW_SMCLK

R580

STBY#
CPPE#
CPUSB#

1
10
9

PERST#
OC#

8
19

T153
R72
R73

CPPE#
CPUSB#
PERST#_R

R570

R573

NEW@47K_4

NEW@0_4
NEW@0_4

NEW_DET# 14

CPUSB#
14 NEW_USBP6+
14 NEW_USBP6-

PERST#

NEW@0_4

C628
*NEW@3300p/50V_4 B:(9/27) Change from +3V_S5 to +3V

+3V_S5

C622

USBP6+_R
USBP6-_R

C633

NEW@0.1u/10V_4
NEW@0.1u/10V_4
NEW@4.7u/6.3V_6
NEW@0.1u/10V_4

C632

29
30

A

+3V

1

NEW Card_CLKREQ#

4
2

*NEW@NC7SZ32P5X

12/10 Change R573 from 28.7K to 0 ohm, Remove C628

NEW@0_4
NEW@0_4

GND1
GND29
PETp0 GND30
PETn0
GND2
PERp0
PERn0
GND3
REFCLK+
REFCLKCPPE#
CLKREQ#
+3.3V1
+3.3V2
PERST#
+3.3VAUX
WAKE#
+1.5V1
+1.5V2
SMB_DATA
SMB_CLK
RESERVED1
RESERVED2
CPUSB#
USB_D+
USB_DGND4

B:(9/27) Add 10k PU to +3V_S5
+3V_S5
R666
+3V_S5
*NEW@10K_4
R598

NEW@130801-1

*NEW@10K_4

Header
Ejector

130801-1
131851-V

+NEW_3V

+NEW_1.5V

DFHD26MR074
FBBL5001010

PROJECT : BD3G

C364

C629

C306

2
C634

C623

C620

C619

C635

C631

NEW@0.1u/10V_4
NEW@0.1u/10V_4
NEW@4.7u/6.3V_6
NEW@0.1u/10V_4

NEW@4.7u/6.3V_6
NEW@0.1u/10V_4
NEW@0.1u/10V_4

NEW@4.7u/6.3V_6
NEW@0.1u/10V_4

(0918) Reserve CLKREQ#
circuit to NEW_CLKREQ# of
clock generator

A:(9/7) per TI FAE suggestion:
(1)Please keep all Input and Output capacitor value > 4.8uF (0.1uF +4.7uF)
5

R268
R269

+1.5V
+NEW_3VAUX

C621

NEW_CLKREQ#

O2 FAE suggest add 47K RES to +3V_S5 2007.08.13
*.1U_4

T89
T84

NEW@0_4

U34

PLTRST#
+3V

PERST#
+NEW_3VAUX

Q75
*NEW@DTC144EU
PCIE_WAKE#

14,24 PCIE_WAKE#

C799

+3V_S5

CPPE#
NEW Card_CLKREQ#
+NEW_3V

R596
NEW@0_4

3 NEW_CLKREQ#

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

3

3,7,8,14 PCLK_SMB

PCLK_SMB

13,19,21,24,27,29

2

Q72

H=0.8mm

U33

GMT

AL027C10003

4

RCLKEN

Quanta Computer Inc.
*NEW@2N7002E

1

1

Thermal GND

3

21

3,7,8,14 PDAT_SMB

SDATA0

AL000577001

10 PCIE_TXP3
10 PCIE_TXN3

5

*NEW@4.7KX2_4

Vendor

3

RP34
Q73

QCI PN

2

4
2

NEW CARD'S POWER SWITCH

Size

Document Number

Date:

Thursday, May 29, 2008

Q76

3

2

Rev
2A

Mini PCIE/Hyberflash
Sheet
1

25

of

42

A

B

C

D

E

CARDREADER POWER

+3V

3

XD_CD#
R722
*10K_4

+3V
+3VARUN
3

R723
*10K_4

C378

C377

4.7u/6.3V_6

0.1u/10V_4

0.1u/10V_4

BK1608HS220_6

+3V

+1.8V

4.7u/6.3V_6

0.1u/10V_4

C371

C402

0.1u/10V_4

4.7u/6.3V_6

C400
0.1u/10V_4

C399

4

5/9 for card reader MS DUO adapter short issue
reserve R723,724,722 ,Q82,Q81,Q83,Q84

Q83

INTE#

AD17

R377

100/F_4

OZ129_IDSEL

A:(8/29) add 100ohm is that reduce the notice form PCI signal.

3

13
13
13
13

28
38
46
55

CBE3#
CBE2#
CBE1#
CBE0#
OZ129_IDSEL
OZ129_CLK

13 PCLK_OZ129
13
DEVSEL#
13
FRAME#
13
IRDY#
13
TRDY#
13
STOP#
A:(8/24) Remove 33 ohm serial resister for PCIRST#
13
PAR
(22 ohm resister alerady be puted in SB600 side)
13
REQ0#
13
GNT0#
13,25 PCIRST#
A:(8/14)Base on AMD platform,
13
INTE#
change net name from INTA# to INTE#
14 PCI_PME#
13,29 CLKRUN#

INTE#
PCI_PME#
CLKRUN#

5
45
42
39
40
41
43
44
17
18
1
11
3
6
106

1

14
15
91
92
120
125
MS_D1/XD_D7
XD_D6
XD_D5
XD_D4
MS_BS/XD_D3
MS_D0/XD_D2
MS_D2/XD_D1
MS_D3/XD_D0
XD_CE#
XD_R/B#
XD_CLE
XD_ALE
XD_WE#
XD_RE#
XD_WPO#
MS_CD#
XD_CD#

IDSEL
PCI_CLK
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
REQ#
GNT#
PCI_RST#
INTA#
PME#
CLKRUN#

NC1
NC2
NC6
NC7
NC5
NC3
NC4
NC8
TEST0
TEST1

MEDIA_ACTV

R352

5.9K/F_4
Y7

83
84

C345

0.01u/16V_4

0.01u/16V_4

1

2

78

18p/50V_4

24.576MHz

76
75
74
72
71

TPBIAS0
TPA0P
TPA0N
TPB0P
TPB0N

4
113
111
112
107
108
110
117
114

MC_PWR_3V#
SD/MS_CLK_L
SD_D3
SD_D2
SD_D1
SD_D0
SD_CMD
SM_WPI#/SD_WP
SD_CD#

95
93
89
87
88
90
94
96
119
100
118
109
105
101
98
99
97

MS_D1/XD_D7
XD_D6
XD_D5
XD_D4
MS_BS/XD_D3
MS_D0/XD_D2
MS_D2/XD_D1
MS_D3/XD_D0
XD_CE#
XD_R/B#
XD_CLE
XD_ALE
XD_WE#
XD_RE#
XD_WPO#
MS_CD#
XD_CD#

C380

12/21 EMI
R308~R329 0ohm(CS00002JB38) change to 33ohm(CS03302JB29)

5 IN 1 CARD READER

1394_XIN
1394_XOUT
1

REF

MC_3V#
SD/MS_CLK
SD_D3
SD_D2
SD_D1
SD_D0
SD_CMD
SM_WPI#/SD_WP
SD_CD#

C/BE3#
C/BE2#
C/BE1#
C/BE0#

C346

0.01u/16V_4

*ME2N7002D
C381

TPBIAS
TPA+
TPATPB+
TPB-

12
16
33
66
68
104
115
116
121
123
124

2

A:(9/7)Correct P/N to 1% resister

XI
XO

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

28 TP_XD_LED

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C351

4.7u/6.3V_6
Q84

1.8VCCD
1.8VCCD
1.8VCCD
1.8VCCD
1.8VCCD
1.8VCCD

19
20
21
22
23
24
25
27
29
30
31
32
34
35
36
37
47
48
49
50
51
52
53
54
57
58
59
60
61
62
63
64

C350

2

18p/50V_4

1/31 hange CN33(5 in 1 card CONN) P/N from DFHS38FR003 to DFHS38FR005

H=1.2mm Better than 50ppm
CN33

12/21 add 0 ohm and 22p for SD/MS CLK
R683

33_4

SD/MS_CLK
C782

XD_CLE
SD_D2
XD_WPO#
XD_CD#
XD_R/B#
XD_ALE
XD_RE#

R324
R328
R327
R320
R321
R325
R322

33_4
33_4
33_4
33_4
33_4
33_4
33_4

XD_CLE_C
SD_D2_C
XD_WPO#_C
XD_CD#_C
XD_R/B#_C
XD_ALE_C
XD_RE#_C

6
9
10
2
3
7
4
1
11

VCC_XD

*22P_4

1/31 According to customer request, we
can't stuff C782(22pF) in SD/MS_CLK
2/13 EMI change R683 from 0 to 33 ohm

MS_CD#

R318

33_4

MS_CD#_C

SD_CMD

R319

33_4

MS_D3/XD_D0
MS_D2/XD_D1

R317
R315

33_4
33_4

SD_CMD_C
SD/MS_CLK_C
MS_D3/XD_D0_C
MS_D2/XD_D1_C

XD_CE#
XD_WE#
SD_D3

R323
R329
R326

33_4
33_4
33_4

XD_CE#_C
XD_WE#_C
SD_D3_C

13
18
19
17
15
14
16
20
5
8
12
21

VCC_XD

CLE_XD
DAT2_SD
-WP_XD
CD_XD
R/-B_XD
ALE_XD
-RE_XD
GND_XD
MS-VSS

GND
GND-SDIO
CLK_SD
MS-BS
VSS_SD
MS-VSS
D1_XD
DAT0_SD
D2_XD
DAT1_SD
D3_XD
D4_XD
D5_XD
D6_XD
D7_XD
VCC_XD
C/D_SD
GND_SD
W/P_SD

MS-VCC
MS-INS
VSS_SD
GND_XD
CMD_SD
MS-SCLK
MS-DATA3
MS-DATA2
-CE_XD
-WE_XD
CD/DAT3_SD
VDD_SD

MS-DATA1
SDIO/MS-DATA0
D0_XD

43
42
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
24
22
23

SD/MS_CLK_C
MS_BS/XD_D3_C
MS_D2/XD_D1_C
SD_D0_C
MS_D0/XD_D2_C
SD_D1_C
MS_BS/XD_D3_C
XD_D4_C
XD_D5_C
XD_D6_C
MS_D1/XD_D7_C
SD_CD#_C
SM_WPI#/SD_WP_C
MS_D1/XD_D7_C
MS_D0/XD_D2_C
MS_D3/XD_D0_C

R316
R311

33_4
33_4

SD/MS_CLK
MS_BS/XD_D3

R314

33_4

SD_D0

R312

33_4

SD_D1

R310
R309
R308

33_4
33_4
33_4

XD_D4
XD_D5
XD_D6

R610

33_4

SD_CD#

R648

33_4

SM_WPI#/SD_WP

R335
R313

33_4
33_4

MS_D1/XD_D7
MS_D0/XD_D2

3

VCC_XD

MXP038-C0-1015

A:(8/29) change from 33 to 0 ohm
connect the socket and chip by wire directly, and keep same length of these signals.
but if these signal over 15 ~cm , please consider to add these damping resistors.

2
8
9
10
13
126
127
128

1394

85
86

12/21 EMI
Don't stuff RN34,RN35(CJ000042N12)
Add L68,L69(CX0900JT005)
TPBIAS0

C372

1394@1u/10V_4

AGND
AGND
AGND
AGND
AGND
AGND

AD17

GNT0#

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

65
69
70
77
80
82

REQ0#

AD[31..0]

PCI_VCC
PCI_VCC
3.3VCCD
3.3VCCD
3.3VCCD
3.3VCCD
3.3VCCA
3.3VCCA
3.3VCCA
3.3VCCA

13,17

26
56
7
102
103
122
67
73
79
81

U20
OZ129T
AD[31..0]

*10K_4

VCC_XD

2

*ME2N7002D
MS_CD#

12/8 change from 22p to 18p

R293

5

3

R724
*10K_4

R725
*10K_4

0.1u/10V_4

VCC_XD
+3V

1u/25V_8

3

C370

OC#

VCC_XD

8
7
6

*ME2N7002D

4

C397

OUT3
OUT2
OUT1

1

L37

C347

2
+3V

+3V

IN1
IN2

MC_PWR_3V#
4
EN#
1
GND
9
GND-C

*ME2N7002D
Q82

XD_CD#_C

2
3

+3V

1

C368

30mil

U18
RT9711BPF
Q81

2

H=1.6mm
L38

R355

R356

1394@56.2/F_4

1394@56.2/F_4

L68
4
1

4
1

2

3
2

3
2

1394@CL-2M2012-121JT

BK1608HS220_6

As close as
possible to OZ129

5/27 some 1394 device can't boot normal
change L38 to BK1608HS220_6

L1394_TPA0+
L1394_TPA0-

TPA0P
TPA0N

CN38
5
L1394_TPB0L1394_TPA0L1394_TPA0+
L1394_TPB0+

TPB0N
TPB0P

1
3
4
2

6

L1394_TPB0L1394_TPB0+
1394@C13141-10405-L

PCLK_OZ129

R353

R354

1394@56.2/F_4

1394@56.2/F_4

L69
1
4

+3V
1394_COM

R376
*22_4

R384

*10K_4

INTE#

R382

*10K_4

PCI_PME#

*10K_4

CLKRUN#

1
4

2
3

2
3

1394@CL-2M2012-121JT

These 1394 signals are high speed
differential pairs and must be kept equal
length with a differential impedance (Zo)
of 110ohms.

C374
R340

2/29 del RN34,RN35

1394@270p/25V_4
1394@5.1K/F_4

C393
*22p/50V_4

R383

2/4 reserve D88~D91 for 1394

Reserve EMI

1

4/10 add D88~D91 for 1394 ESD

Change Pulled-up Resistor on the South Bridge side.

MMC

D8
D88
8

2

1 1394@EGA

L1394_TPB0-

D8
D89
9

2

1 1394@EGA

L1394_TPA0-

D9
D90
0

2

1 1394@EGA

L1394_TPA0+

D9
D91
1

2

1 1394@EGA

L1394_TPB0+

1

PROJECT : BD3G
Quanta Computer Inc.
Size

Document Number

Date:

Thursday, May 29, 2008

Rev
2A

OZ129T (Card Reader/1394)
A

B

C

D

Sheet
E

26

of

42

5

4

3

FLASH
+1.8V

D

PDD[0..15]

CN3
PDDREQ
PDIOW#
PDIOR#
PDIORDY
PDDACK#
IRQ14
PDA1
PDA0
PDCS1#
PDA2
PDCS3#

R289

IDE_RST#_B
PDD7

C443

C438

C437

C403

*1u/10V_4

*1u/10V_4

*1u/10V_4

*22u/6.3V_8

PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0
PDIOW#

+1.8V

11/01 modify it

PDIORDY
PDA1

R217
*10K_4

PLTRST#

NC

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

+1.8V
PERST#
PDD7
GND
PDD6
PDD5
+1.8V
PDD4
PDD3
GND
PDD2
PDD1
PDD0
PDIOW#
+1.8V

25
24
23
22
21

PDA0
PDCS1#

14 HDD_AUX_RST#

42
*0_6

D15
1

*CH501H-40PT
2

D14
1

*CH501H-40PT
2

IDE_RST#_B

PDIORDY#
PDA1
+1.8V
PDA0
PDCS1#

NC

41

NC
PDD8
PDD9
GND
PDD10
PDD11
GND
PDD12
PDD13
GND
PDD14
PDD15
PDREQ
GND
PDIOR#

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6

GND
PDACK#
PIDE_INTR
PDA2
PDCS3#

R345

*0_4

PDD8
PDD9

PDMA66

1

15 PDDREQ
15 PDIOW#
15 PDIOR#
15 PDIORDY
15 PDDACK#
15 IRQ14
15 PDA1
15 PDA0
15 PDCS1#
15 PDA2
15 PDCS3#

13,19,21,24,25,29

SATA ODD

Flash moduel operate at 1.8V
Pin2, 20 is NC for Flash module

+1.8V_FLASH

1

PDD[0..15]

PDD10
PDD11

2

15

2

4/10 remove Flash card ckt

C490

R346

*47n/25V_6

*100K_4

14

9/28 change to SATA ODD conn to BD3G use
10/22 update footprint to SATA-C18534-11305-13P-R
D

PDD12
PDD13
PDD14
PDD15
PDDREQ

CN2

5
4
3
2
1

PDDACK#
IRQ14
PDA2_R
PDCS3#

R303

PDA2

*0_4

10/29 add four stitch cap
+5V

*78319-0011

+1.8VSUS

10/30 use H:5.2 for A-test

C434

*0.01u/16V_4

C447

*0.01u/16V_4

C439

*0.01u/16V_4

C398

*0.01u/16V_4

Check New ODD CONN Pin Define.

14

GND14

PDIOR#

GND1
RXP
RXN
GND2
TXN
TXP
GND3

1
2
3
4
5
6
7

DP
+5V
+5V
RSVD
GND
GND

8
9
10
11
12
13

SATA_TXP3 15
SATA_TXN3 15
SATA_RXN3 15
SATA_RXP3 15

R331

Device Present

+5VSATA_ODD

15

GND15

1K_4

R304

C457

C458

C459

C461

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

10u/10V_8

Co-lay ESATA footprint
2/29 del R572,R569

ESATA

Option SB to ESATA directly
C

2/13 add ESATA re-driver IC
5/5 update re-driver footprint
to tqfn36-5x6-5-37p-0_75h-te1m

R692
1K_4

SATA_RXP2
SATA_RXN2

10K_4

R69
R696
6
1
R69
R698
8
1
R70
R702
2
SATA_RXP2
1
R70
R704
4
SATA_RXN2
1

*0_4
2
*0_4
2
*0_4
2
*0_4
2

SATA_TXP2

R695
1K_4

R706
330_4

28
27
26
25
24
23
22
21
20
19

VDD
AO+
AOGND
AGND
VDD
BI+
BIGND
IREF

11
12
13
14
15
16
17
18

VDD
A+
AGND
AVDD
VDD
BO+
BOGND
VDD

+1.8V

+1.8V

GND
NC2
NC1
SEL0_A
SEL1_A
SEL2_A
SEL3_A
EN_A
EN_B

U43

1
2
3
4
5
6
7
8
9
10

10K_4

R717

CLKIN+
CLKINSEL0_B
SEL1_B
SEL2_B
SEL3_B
OUT+
OUT-

+1.8V

15 SATA_RXP2
15 SATA_RXN2

R694
1K_4

R716

37
36
35
34
33
32
31
30
29

1 *0_4
1 *0_4

2
2

SATA_TXP2
SATA_TXN2

SATA_TXP2
SATA_TXN2

R693
1K_4

SATA_TXN2
R700
R701

15
15

+5V

C18534-11305-L

4/14 change R706 from 0 ohm to 330 , stuff R692,R693,R694

C

0_8

C456

SATA_TXN2_R

*0_4
2
*0_4
2
*0_4
2
*0_4
2

eSATA_TXP2

14
14

eSATA_TXN2

C801
2
2

4700p/25V_4
1 eSATA_TXP2
1 eSATA_TXN2

eSATA_RXP2_R
eSATA_RXN2_R

C802
C811
2
2

4700p/25V_4
4700p/25V_4
1 eSATA_RXP2
1 eSATA_RXN2

eSATA_RXN2

USBPWR0

1
BUSBP7- 2
BUSBP7+ 3
4

+ C604
100u/6.3V_3528

2/26 change ESATA conn usb-2006109-11p
update p/n to DFHS11FR021

5
6
7
8
9
10
11

eSATA_TXP2
eSATA_TXN2
eSATA_RXN2
eSATA_RXP2

4/10 change ESATA conn usb-2006109-11p
update p/n to DFHS11FR023

4700p/25V_4

2/20
1.change C801,C82 from 0.01u to 4.7n
2.RX add C811,C812 4.7n

*470_4

PI2EQX3201

BUSBP7BUSBP7+

L64

28 USBPWR0

eSATA_TXP2_R
eSATA_TXN2_R

RFCM1632100M3
2 2
1 1
3 3
4 4

USBP7USBP7+

USBP7USBP7+

eSATA_RXP2

Close IC, no stub at
high-speed trace on
PCB layout.

C812
R707

R69
R697
7
1
R69
R699
9
1
R70
R703
3
SATA_RXP2_R
1
R70
R705
5
SATA_RXN2_R
1
SATA_TXP2_R

4/10 add D67,D49,D50 for ESATA USB ESD

USB Vcc
DD+
GND
GND
A+
AGND
BShield
B+ Shield
GND Shield
Shield

12
13
14
15

CN31
1-2006190-5

5/29 change ESATA conn p/n to DFHS11FR027

B

B

R710
*1K_4

R711
*1K_4

R712
*0_4

R713
*0_4

2

R709
*1K_4

2

R708
1K_4

1

1

SEL0_X SEL1_X

Eq

SEL2_X

0

0

0dB

0

Swing SEL3_X De-Emphasis
1.0X

0

0dB

0

1

2.5dB

1

1.2X

1

-3.5dB

1

0

4.5dB

1

1

6.5dB

D6
D67
7

1 VPORT USBPWR0

2

D4
D49
9

2

1 EGA

BUSBP7-

D5
D50
0

2

1 EGA

BUSBP7+

2/4 reserve D67 for CN31
4/17 remove D77~D81 for CN34 , change to U44 CM1213-04SO
5/5 add C816 0.01u to U44 +5V for ESD
1/17 Change CN32(2nd SATA CONN) from DFHS22FR064 to DFHS22FR094

SATA HDD

SATA_TXN0

CN34

1
2

GND23

23

GND1
RXP
RXN
GND2
TXN
TXP
GND3

1
2
3
4
5
6
7

2'nd SATA HDD

U44
CM1213-04SO

SATA_TXP0
SATA_TXP0
SATA_TXN0

3

CH1
VN
CH2

CH4
VP
CH3

6

SATA_RXP0

CN32

5
4

A:(9/5) update footprint
A:(9/13) update footprint

+5V
SATA_RXN0

SATA_TXP0 15
SATA_TXN0 15

C816
0.1u/10V_4

SATA_RXN0 15
SATA_RXP0 15
A:(8/17) Add Cap for SATA interface

GND23

23

GND1
RXP
RXN
GND2
TXN
TXP
GND3

1
2
3
4
5
6
7

1/17 Change CN32 footprint from SATA-127043FR022XX27ZR-22P-L-H to SATA-127043FR022G285ZR-22P-L
1/31 Change CN34 (1st SATA) P/N from DFHS22FR063 to DFHS22FR082
1/31 Change CN32 (2nd SATA) P/N from DFHS22FR094 to DFHS22FR083

2/4 reserve D82~D86 for CN32(2ND HDD)
SATA_TXP1
SATA_TXN1

SATA_TXP1 15
SATA_TXN1 15

4/17 remove D82~D86 for CN32 , change to U45 CM1213-04SO
5/5 add C818 0.01u to U45 +5V for ESD

SATA_RXN1 15
SATA_RXP1 15

U45
CM1213-04SO

A:(8/17) Add Cap for SATA interface
SATA_RXN1 1

A

3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
RSVD
GND
12V
12V
12V
GND24

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3.3VSATA1

R609
C658

*0_8

+3V

C651

2/4 del R270,R597 , connect to +5V directly
*4.7u/6.3V_6

*0.1u/10V_4

+5V
C354

C636

C644

C373

0.1u/10V_4 0.1u/10V_4 10u/10V_8150u/6.3V_7343

24

3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
RSVD
GND
12V
12V
12V
GND24

SA@127043FR022GX51ZR

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3.3VSATA2

R338
C358

C363

*4.7u/6.3V_6

*0.1u/10V_4

*0_8

+3V

2
SATA_RXP1

3

CH1
VN
CH2

CH4
VP
CH3

6

SATA_TXN1

5
4

+5V
SATA_TXP1

0.1u/10V_4

+5V
C348

C344

C338

C315

PROJECT : BD3G

0.1u/10V_4 0.1u/10V_4 10u/10V_8150u/6.3V_7343

Quanta Computer Inc.

24
Size

Document Number

Date:

Thursday, May 29, 2008

SA@127043FR022XX27ZR

5

4

A

C818

Rev
2A

SATA / PATA
3

2

Sheet
1

27

of

42

4

3

FM@BL121-08R-TAND

R512

1

+3V

+3V

2

Q69
*FP@AO3413

C555

R515
*FP@4.7K_4

*FP@1000p/50V_4

C552

D

+3V

FP@10u/10V_8

+

C558

C465
FM@0.1u/10V_4
CN1

2/13 EMI
stuff C465

*FP@0.1u/10V_4

FP@0.1u/10V_4

2
D68
2
D69
2
D70

5/8 stuff D68,D69,D70 for
FP

USBP4+_C
FP@EGA
FINGER_POWER
1
FP@VPORT

FP_PWRON 29

1

C228
*0.1u/10V_4

GND

8
6
5
4
3
2
1
7
*BL121-06R-TAND

R667
10K_4

29

R449

2

C476
Q57
*AO3413

BT_RESET
WCS_DAT

WCS_DAT
+3V

C618

2/13 EMI
stuff C618

FELICA_POWER

3

+

1

+5V

+3V

USB_DETACH

BT@0.1u/10V_4

C469

*1000p/50V_4

C467

29

R305

*BT@0_4 BT_RESET

R306

BT@0_4 USB_DETACH

10/29 Add
B:(10/21) change Power board CONN (CN8) footprint & P/N

1/31 Change CN14(BT CONN)
P/N from DFHD10MR011 to
DFHD10MR008

10/19 change to BL123-04R-TAND

Power board

2/13 EMI
stuff C618,C794

BT@88266-100XX-XXX-10P-R

A:(8/29) reserve cap for EMI

TP_LED_ON_C

*0_4

*10u/10V_8
R450
*4.7K_4

3

R669

12

1
2
3
4
5
6
7
8
9
10

BT_USBP8+_C
BT_USBP8-_C
WCS_CLK

WCS_CLK

25

+5V

Q78
MMBT3904

1

TP_LED_ON

CN14

3BT_USBP8-_C
2BT_USBP8+_C

3
2

WCM-2012-900T
25

1/18 Change L72 from CX216900002 to CX163210007(BT circuit)
4/18 Change L72 from CX163210007(BT circuit) to CX201290009
*0_8

4
1

11

4
1

BT_USBP8BT_USBP8+

BL123-04R-TAND

CN8

BT_EN

+5VPCU

*0.1u/10V_4

Wire Cable 1.25mm Pitch
C

1
2
3
4

29,30 NBSWON#
29,30 PWRLED#

C803
BT@100p/50V_4

USB_DETACH: Low USB connect
High USB disconnect

3

D

BL121-14R-TAND-14P-L-BU1

R668
330_4

2

BLUETOOTH MODULE CONNECTOR
L72

14
14

3/3 no Felica request , remove
Q57,C476,R450,Q56

TP_LED_ON_C
BATLED1#
BATLED0#
PWRLED#
SUSLED_EC
IDE_LED#
ACIN
TP_XD_LED

29
BATLED1#
29
BATLED0#
29,30 PWRLED#
29 SUSLED_EC
30 IDE_LED#
29,32 ACIN
26 TP_XD_LED

+3VPCU

A:(8/29) reserve cap for EMI

12/21 del R276,R278 stuff L72

TPDATA_1
TPCLK_1

0_4
0_4

11/08 modify it

FELICA_POWER

A:(8/29) follow EMI suggestion, reserve 10~33pf cap

R108
R109

16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

+5V_TP

2 BLM18PG181SN1D_6

CN12

T177
T176

*FM@10p/50V_4

Q70
*FP@DTC144EU

C157
*10P_4

*10P_4

CN11
L16 1
+5V
+5VPCU
29
TPDATA
29
TPCLK

FP@88266-040XX-XXX-4P-R

C310

2

C156
C151
C155
4.7u/10V_8 0.1u/10V_4

FP@EGA

1

T93

FM_CLOCK

1
2
3
4

USBP4-_C

1

3/3 no Felica request , remove
USB del R178,R179

Felica
3

FP@0_6 USBP4-_C
FP@0_6 USBP4+_C

R200
R199

FP_USBP4FP_USBP4+

A:(8/29) reserve cap for EMI

TPDATA_1
TPCLK_1

6

9

FM_DATA
FM_CLOCK

14 FM_DATA
14 FM_CLOCK

FINGER_POWER

3

14
14

C559

+5V_TP

CN13

FINGER_POWER

8
7
6
5
4
3
2
1

10

FP@0_8

2/13 EMI
stuff C559

FM_INTX
FM_DET
FM_RIGHT
FM_LEFT

FM_INTX
FM_DET
FM_RIGHT
FM_LEFT

1

T/P

Finger Printer

FM
13
14
22
22

2

1/31 Change CN13(FP CONN) P/N from DFHD04MR012 to DFHD04MR021

10/19 change to BL121-08R-TAND

5

5

6
5

C

2/4 stuff D71,D72,D73 for BT
2

FELICA_PWRON

1

A:(9/17) Toshiba recommend:
Felica module power default need control power by EC

29

Q56
*DTC144EU

D71

2

BT@EGA
1

BT_USBP8+_C

D72

2

BT@EGA
1

BT_USBP8-_C

D73

2

BT@VPORT
1

+5VPCU

2/13 EMI
stuff C41

D94
D94

C43

2/10 DEL C42, Add D94
for CN8/Pin2 (ESD
issue) - default no
stuff

Main strem

29,30
29,30
29,30

F6

12
1
2
3
4
5
6
7
8
9
10
11

+3VPCU

MX5
MX2
MY1

29,30
14
29,30
29
29

A:(9/4) P/N not ready
2

MX3
LOW_DET
MX4
FN0#
FN1#

+5VPCU_USB1

1

29

12/21 EMI
add 0.1u for +5VPCU
add 100p for 3ND_MBDATA/CLK

7
1
2
3
4
5
6
8

+3VPCU
+5VPCU

A:(9/17) Follow BL5, change from +5V to +5VPCU
KEY_INT

19,21,29 3ND_MBDATA
19,21,29 3ND_MBCLK

CN7

LID@BL123-10R-TAND-10P-L-BU1

80 mils

POLY_SWITCH
RC1206
DK150TPU072

10/25 update footprint
MID@BL123-06R-6P-R-BL5

CN6

10/29 pin1 change from MX1 to MX5

100p/50V_4

+3V

Low cost

80 mils

PWRLED#

2/13 EMI
stuff C43

0.1u/10V_4

A:(8/29) reserve cap for EMI

+5VPCU

1 *VPORTNBSWON#

2

C41

+5VPCU

3ND_MBDATA

3ND_MBCLK

C783

C784

C785

MID@0.1u/10V_4

MID@100p/50V_4

MID@100p/50V_4

FFC Cable 1.0mm Pitch
B

B

A:(9/4) Add 2A Poly switch on USB power which 2 connector share 1 switch
+3V_S5

2/10 Stuff L64,L65

to CX163210007
A:(9/17) change usb/b OC pin pull-high ckt into MB side

change USB CONN footprint and pin-define (follow USB CONN Standard)

CN36

10/25 modify it

USB

10/19
R307
10K_4

USBOC#0

# Placed common mode chokes within 1.0" of the USB connectors

USBPWR0

C353
*0.1u/10V_4

2/15 Change L70,L71 from CX216900002 to CX201290009

1
2
3
4

BUSBP0BUSBP0+

+ C687
100u/6.3V_3528

5
6
7
8

USB
USBP0USBP0+

C736
1u/10V_6
U39
RT9711BPF

2
3
29

A:(9/13) change PIN2 to OC pin
BUSBP0BUSBP0+

4
1
9

USB_EN#

IN1
IN2
EN#
GND
GND-C

OUT3
OUT2
OUT1

5
OC# C737

USBPWR0

USBPWR0 27
C722
*10u/10V_8

R366

10K_4

+3V_S5

C391
0.1u/10V_4

L70
14
14

USBP9+
USBP9-

3
2

14
14

USBP1+
USBP1-

3
2

2/29 del R608,R607
8
7
6

CN16

+5VPCU

L65

C733
*0.1u/10V_4

RFCM1632100M3
2 2
1 1
3 3
4 4

3
2

4
1

14,29 USBOC#0

4 USBP9+_C
1 USBP9-_C

WCM-2012-900T
L71
3
4 4
2
1 1

29

USBP1+_C
USBP1-_C

USB_EN2#
+5VPCU

WCM-2012-900T

2/13 EMI
stuff C391,C701,C809,C810

A:(9/17) change to +3V_S5

USBP9+_C
USBP9-_C
USBP1+_C
USBP1-_C

C809
100p/50V_4

C810
C701
100p/50V_4 0.1u/10V_4

1
2
3
4
5
6
7
8
9
10

12

USBP0USBP0+

B:(10/16) change USB CONN footprint and pin-define (follow USB CONN Standard)

D66
D66

1 VPORT USBPWR0

2

11

14
14

+5VPCU_USB1

88266-100XX-XXX-10P-R

2/4 reserve D66 for CN36
4/10 add D66

1/31 Change CN16(USB-FFC CONN) P/N from DFHD10MR011 to DFHD10MR008

*0.1u/10V_4

A:(8/31) change U5 location to between the common chokea and the CONN

A

A

A:(9/4) Add 10uF for Cout (no stuff)
USBOC#3 14,29
Please reserve Cin = 1uF(stuff),Cout = 10uF(don't stuff) for Richtek RT9711BPF
Please reserve Cin = 4.7uF(stuff),Cout = 10uF(don't stuff) for GMT solution

10/25 modify it

# ESD suppression components are placed within 0.5" of the user accessible USB connectors
and are located between the common mode chokes and the connectors.

D51
D51

2

1 EGA

BUSBP0-

D52
D52

2

1 EGA

BUSBP0+

PROJECT : BD3G
Quanta Computer Inc.

4/10 add D51,D52 for USB0
D17
D17

2

1 *VPORT+5VPCU

Size

2/15 CN42 co-layout with CN16
4/16 remove CN42 not co-layout with CN16
4

3

2

Document Number

Rev
2A

FP/ TP/ USB /BT/FELICA
Date:

5

Thursday, May 29, 2008

Sheet
1

28

of

42

5

4

3

2

PCLK_591

SM BUS PU
Reserve for EMI

+3VPCU
R501
*22_4

+A3VPCU
L25
BLM18AG601SN1_6

EC_VDD
C564

12/20 avoid leakage reserve D59/D60 to CLKRUN#/PLTRST#

14

8

GATEA20

D12

14
RCIN#
A:(9/4) add diooe for leakage issue

Reserve for EMI

14
To: Back light control circuit (Output)
R682

13,19,21,24,25,27

0_4

D60

PLTRST#

*BAS316

7

28

USB_EN#

123

13

SERIRQ

125

SMBUS Table
Devices

CPU Thermal Sensor
3D Sensor
EC EEPROM

9

USB_EN2#

To internal
KB Con.

Battery

6
124

CEC_EC_HP

C

1

BAS316

20 EC_FPBACK#

28

2

D47

SCI#

19

GATA20_R 121
BAS316
RCIN#_R 122
BAS316
SCI#_uR
29

D13

VGA Board Thermal Sensor
Touch Sensor

30
30
28,30
28,30
28,30
28,30
30
30

MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7

54
55
56
57
58
59
60
61

30
28,30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30

MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17

53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33

MY17

To: Battery connector
32
MBCLK
To: Battery connector
32
MBDATA
To: CPU Thermal Sensor, 3D Sensor, EC EEPROM
4 2ND_MBCLK
To: CPU Thermal Sensor, 3D Sensor, EC EEPROM
4 2ND_MBDATA
To: VGA Board Thermal Sensor, Touch Sensor
19,21,28 3ND_MBCLK
To: VGA Board Thermal Sensor, Touch Sensor
19,21,28 3ND_MBDATA
To: AMD CPU (Output)
R425
4 CPU_PROCHOT#

*0_4
HWPG

Rev03 modify 2007/08/16
1/31 leakage issue ,no stuff R425

To: Touch PAD
+5V
To: Touch PAD
B:(10/23) Add CHG_EN To: Charger (for 15, 17) (Output)
R519
10K_4 TPCLK
To: Finger Printer Con (output)
R526
10K_4 TPDATA
To: Internal KB LED (output)
To: Felica Con (output)

70
69
67
68
119
120
24
28
72
71
10
11
12
13

28
TPCLK
28
TPDATA
32
CHG_EN
28
FP_PWRON
30
FN_F10
28 FELICA_PWRON
8768_32KX1

77

8768_32KX2

79

B

R532

20M_6

GA20
KBRST

LDRQ/GPIO24
GPIO41(VBAT)

PWUREQ/GPIO67
SERIRQ
SMI/GPIO65
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

SCL1/GPIO17
SDA1/GPIO22
SCL2/GPIO73
SDA2/GPIO74
SCL3/GPIO23
SDA3/GPIO31
SCL4/GPO47
SDA4/GPIO53

32KX1/32KCLKIN
32KX2

C575
15p/50V_4

Can try to
change to
0_0603

1
2
C579

32.768KHZ

101
105
106
107

TIMER

FIR
CIR

SPI_DI/GPIO77
SPI_DO/GPO76/SHBM
SPI_SCK/GPIO75
GPIO81
IRRX1/GPIO72/SIN2
IRRX2_IRSL0/GPIO70
IRTX/GPIO71/SOUT2
CIRRXM/GPIO46/TRST
GPIO34/CIRRXL
CIRTX1/GPIO16
CIRTX2/GPIO30
F_SDI/F_SDIO1
F_SDO/SDIO0
F_CS0
F_SCK

CLKOUT/GPIO55
VCC_POR

0_6

VREF

Rev03 modify 2007/08/16

31
63
117
64
26
15
84
83
82
91 DNBSWON#_uR

30

0_4
0_4

CONTRAST 20
KILL_SW 30
BATLED0# 28
BATLED1# 28
SUSON 36,37
MAINON 21,36,37
TP_LED_ON 28
PWRLED# 28,30

To: Control Panel brightness (Output)
To: Enable/Disable WiFi and BT (Input)
To: Battery LED--Full charge (Output)
To: Battery LED--Charging (Output)
To: Control S3 power (Output)
To: Control S1 power (Output)
To: Touch PAD Connector (Output)
To: Power ON LED (Output)

+1.2V_ON 35,37
FANSIG 4
LOM_DISABLE# 24
ACIN
28,32
S5_ON 33,37
VRON 34,35,37

To: FAN connector (Input)
To: LAN IC (Output)
To: ACIN LED and AC detect circuit (Input)
To: Control S5 power (Output)
To: CPU Vcc core PWM IC (Output)

2Eh

2Fh

11

164Eh

164Fh

C794
BT@100p/50V_4

CIRRX2

BADDR0

R509

*10K_4

BADDR1

BT_EN

R510

10K_4

SHBM

RF_EN

R531

10K_4

12/4 stuff R510, remove R509 for BT cause system can't work

H=1.75mm

ID

+3VPCU

U15

2ND_MBCLK
2ND_MBDATA

6
5
7

1
2
3

A0
A1
A2

SCL
SDA
WP

VCC
GND

C

8
4
C562

24LC08BT-I
0.1u/10V_4

ADDRESS: A0H

SPI FLASH

To: Enable WiFi (Output)
To: Battery Charger (Output)
To: South Bridge (Output)

NUMLED 30
CAPSLED 30

H=2.16mm

10/30 change to AKE3GFP0N08

To: South Bridge (Output)
To: South Bridge (Input)
To: South Bridge, be careful the timing (Output)
To: Touch Sensor Board Con. (Input)
To: CIR (Input)
To: Internal KB LED (output)
To: Internal KB LED (output)

RSMRST# 14
SUSC# 14
ECPWROK 17,20
KEY_INT 28

SPI_SDI_uR

R505

33_4

SPI_SDI

SPI_SDO_uR

R514

33_4

SPI_SDO 5

SPI_SCK_uR

R513

33_4

SPI_SCK 6

2

SPI_CS0#_uR

1

R507

+3VPCU

10K_4

+3VPCU

U27
SO

VDD

SI

HOLD

SCK

WP
VSS

CE

8
7

C551

3

0.1u/10V_4

4

EON 8M

AKE3GFP0N08 IC FLASH(8P) W25X80VSSIG(SOIC)

SPI_SDI_uR
SPI_SDO_uR
SPI_CS0#_uR
SPI_SCK_uR

+3VPCU
MY0

Rev13 modify 2007/09/14

85

VCC_POR#

R528

104

VREF_uR

R516

4.7K_4

To: USB Power Switch (Input)

USBOC#3 14,28

R511

10K_4

INTERNAL KEYBOARD STRIP SET

+3VPCU

0_4 +A3VPCU
B

CIR (Copy from PB2A)
WPCE775L:

AJ007750F00

WPCE775C:

AJ007750F01

W/O CIR

For Pin 80

C553

8769AGND

+3VPCU

+5VPCU

+A3VPCU

R661

C254

R662

For WPC8763

8769AGND
A:(9/7) change from L to 0 ohm base on EC FAE suggestion
+3V

11/01 all power good pull up to +3V

R117

+3V

R529
R530

*0_4

+3V

R94

10K_4

+3V

R121

10K_4

37 HWPG_2.5V

SYS_HWPG
+3V

R466

10K_4

+3V

R438

10K_4

+3V

R120

10K_4

+3V

R119

10K_4

CCD_POWERON

20

D42

BAS316

D39

BAS316

D41

BAS316

C739

CIR@0.1u/10V_4

*CIR@0_4

To: CCD Power Switch (Output)

U41
R660
*CIR@10K_4

CIR_VCC

CIRRX2

For WPCE775

Rev03 modify 2007/08/17

HWPG

12/12 pull down 100k for ECPWROK

BTO

3
1
2
4

20 mlis

VCC
OUT
GND
GND
CIR@IR-FM-9038SM-5CN

11/01 to avoid floating

ECPWROK
R680

D40

35 HWPG_1.2V_NB

0_4

CIR@0_4

+5VPCU

R487
10K_4

10K_4

4,34 CPU_COREPG

12/24 change R444 from 100k to 10k for VRON

VRON
100K_4

R444

10K_4
A

12/12 update P/N to BEBK0081D01

BAS316
S5_ON
R101

HWPG_1.8V

37 HWPG_1.5V

D44

BAS316

D38

BAS316

D37

BAS316

100K_4

SUSON
R439

100K_4

R51

+3V

10K_4

37 HWPG_1.1V_NB
21

GFXPG

+3VPCU

10/26 modify it
MAINON

37 HWPG_CPUIO

5

10

15p/50V_4

1. Traces as short as possible
2. NO vias
3. Keep away from high speed signals

36

CORE DEFINED

BADDR0

*0.1u/10V_4

33

XOR TREE TEST MODE

01

Disabled ('1') if using FWH device on LPC.
Enabled ('0') if using SPI flash for both system BIOS and EC firmware

To: Enable BT module (Output)
To: CRT connector and South Bridge (Input)
To: MR sensor (Input)

RF_EN 25
CELL-SET 32
DNBSWON# 14

BAS316

PWROK_EC R535

EC_VBAT

A

BT_EN

Data

00

To: Logo LED (Output)

10/15 to prevent foalting
10/19 rev10 modify 10/19

T24
D48

RSMRST#_uRR214

1u/10V_6
B:(10/24) change C575,C579 from 6.8p to 15p (base on TXC report)

To: RF LED (Output)
To: Mute Audio AMP (Output)
To: Battery Connector (Input)
To: Select VIN is from DC or Battery (Output)

BT_EN 28
CRT_SENSE#
LID591# 20

86
87
90
92

Index

SHBM=0: Enable shared memory with host BIOS

BADDR0

75
73
74
23
14
114
109

*4.7K_4

I/O Address
BADDR1-0

10/19 rev10 modify 10/19

32
118
62
65
22
16
81
66

R218

I/O ADDRESS SETTING

EC_VBAT

111
113
93

TA1/GPIO56
TB1/GPIO14
TA2/GPIO20
TB2/GPIO01
TA3/GPIO51
TB3/GPIO36

D

CRT_SENSE#

To: Battery Charger (Output)
To: FAN Control IC (Output)
To: Battery Charger (Output)
To: SUS LED circuit (Output)

CC-SET 32
VFAN
4
CV-SET 32
SUSLED_EC 28

80

No stuff R218

+3V

A:(8/23) Add PU +3VPCU for 3rd SMBUS

To: Battery Connector (Input)
To: USB Power Switch (Input)
To: Media Board (Input)
To: Media Board (Input)
To: Volume Wheel (Input)
To: Volume Wheel (Input)
To: HW Power Button (Input)
To: South Bridge (Input)

TEMP_MBAT 32
USBOC#0 14,28
FN0#
28
FN1#
28
DIGVOL_UP 23
DIGVOL_DN 23
NBSWON# 28,30
SUSB# 14

SOUT_CR/GPO83/BADDR1
SIN_CR/CIRRX/GPIO87
GPIO06

PS/2

R522

97
98
99
100
108
96
95
94

LED_LOGO 30

SPI

0.1u/10V_4

4.7K_4
4.7K_4
4.7K_4
4.7K_4
4.7K_4
4.7K_4
4.7K_4
4.7K_4

+3VPCU

110
112

FIU

PSCLK1/GPIO37
PSDAT1/GPIO35
PSCLK2/GPIO26
PSDAT2/GPIO27
PSCLK3/GPIO25
PSDAT3/GPIO12

*10K_4

no wake-up
GPO82/TRIS
capability GPO84/BADDR0

A_PWM/GPIO15
B_PWM/GPIO21
C_PWM/GPIO13
D_PWM/GPIO32
PWM
E_PWM/GPIO45
F_PWM/GPIO40/CLKIN48
G_PWM/GPIO66
H_PWM/GPIO33

SMB

R527

RF_LED 30
AMP_MUTE# 22
ID
32
D/C#
32
EC_BLON 20

SER

KBSOUT0/SOUT_CR/JENK
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KB
KBSOUT4
KBSOUT5/TDO
KBSOUT6/RDY
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
KBSOUT16/GPIO60
KBSOUT17/GPIO57

C577

0.1u/10V_4

B:(9/27) Remove R527, already PU 100k to +3VPCU on Battery CONN (CN20/Pin4)

17
20
21
25
27

GPIO42/TCK
GPIO43/TMS
wake-up
GPIO44/TDI
capability
GPIO50/TDO
CIRTX2/GPIO52/RDY

5
18
45
78
89
116

Y9

GPIO

LRESET

R536
33K/F_6

4
3

DA0/GPI94
DA1/GPI95
DA2/GPI96
DA3/GPI97

D/A

LPCPD/GPIO10

EC

GND Shape should
below the Crystal and
have some GND vias

LPC

ECSCI/GPIO54

C560

0.1u/10V_4

Reserve for EMI
Close to EC

4

CLKRUN/GPIO11

VCORF

*BAS316

AD0/GPI90
AD1/GPI91
AD2/GPI92
AD3/GPI93
AD4/GPIO05
AD5/GPIO04
AD6/GPIO03
AD7/GPIO07

A/D

AGND

D59

CLKRUN#

H=1.6mm

LFRAME
LAD0
LAD1
LAD2
LAD3
LCLK

C578

44

0_4

3
126
127
128
1
2

LFRAME#
LAD0
LAD1
LAD2
LAD3
PCLK_591

10u/10V_8

R534
R533
R520
R523
R506
R503
R29
R28

2/10

U26

103

R681

13,25
13,25
13,25
13,25
13,25
13,17

C506

0.1u/10V_4

VDD

C556
0.1u/10V_4

VCORF_uR

C576
0.1u/10V_4

102

C253
0.1u/10V_4

AVCC

C557
0.1u/10V_4

0_6

C514

8769AGND

GND1
GND2
GND3
GND4
GND5
GND6

C523
0.1u/10V_4

VCC1
VCC2
VCC3
VCC4
VCC5

C554
10u/10V_8

D

3

C570

0.1u/10V_4 10u/10V_8

19
46
76
88
115

C550
*10p/50V_4

SMBUS

R477

+3VPCU

MBCLK
MBDATA
2ND_MBCLK
2ND_MBDATA
3ND_MBCLK
3ND_MBDATA
FN0#
FN1#

DNBSWON#_uR
DIGVOL_UP
DIGVOL_DN

+3V

For Pin 102

13,26

1

2/13 EMI
stuff C577,C578,C560

R494
D2

BAS316

D43

EV@BAS316
4

100K_4

BATLED0#
BATLED1#
PWRLED#

R441
R440
R149

PROJECT : BD3G

10K_4
10K_4
10K_4

Quanta Computer Inc.
Size

Document Number

Date:

Thursday, May 29, 2008

Rev
2A

FP/ KB/ TP/ USB /BT/FELICA
3

2

Sheet
1

29

of

42

5

4

3

2

1

2/1 Change R404,R405 from CS13902JB14 (390 ohm) to CS13302JB21(330 ohm)

LOGO LED

+5V

+5V
R404
MID@330_4

1/18 LED7,8 change footprint from LED12-21SYGC-TR8 to
LED27-21-BHC-ZL1M2TY-3C

W-LAN&BT

1/18 change p/n
LED7 BEBL0074Z04 (WIMAX)
LED8 BE0R0053Z00 (WLAN & BT)

R405
MID@330_4

2
MID@99-113UNC/V90/TR8
LED6

390_4

10/25 modify it

IDE LED

RF_LED 29
28

IDE_LED#

IDE_LED#

1

Mainstream --> Orange
Low Cost --> Orange
R156

+3V

WiMAX LED

3

3

D

R664

LOGO_2

LOGO_1

10/16 update LED to right angle

Mainstream --> White
Low Cost --> N/A

RF_LED_R

2

LED12-21SYGC-TR8

1

1

MID@99-113UNC/V90/TR8
LED5

1

3
Q27
MMBT3906
2

2

LED8

10K_4

IDE_LED#_B

R155

0_4

D

SATA_LED# 15

B:(10/25) Modify WiMAX LED circuit (default no stuff)
*LED12-21SYGC-TR8

LED_LOGO

LED_LOGO

2

2

*100_4

2

Q49
MID@ME2N7002D

1

WiMAX_R 1

LED7

1

1

Q48
MID@ME2N7002D
*0.1u/10V_4
C423

R104

+5V

3

2

29

LED_LOGO

Q77
*BSS84
R290

25 WiMAX_LED#

1/18 Change SW4 footprint from
SW-NSS506-212F-CCCD1T-3P to
SW-NSS506-212F-CCCD1T-3P-BD3A (SMT open
issue)

+3V

*10K_4

Kill SW

5/8 stuff D53 for RF_LED ESD

+3VPCU

12/7 change LED5,LED6 footprint and p/n

Use old footprint for A-test.
Must update new footprint in B-test

D26
D53

LOGO_1

1

RF_LED_R

R400
10K_4

1

SW4

3

2

3

LOGO_2

2

WiMAX_R

29

2

*MID@BZ5V6

1

KILL_SW

BZ5V6

3
SW-NSS506-212F-CCCD1T-3P
+3VPCU

A:(9/14) change footprint

D22
DA204U

1

C

C

3

12/12 Change SW4 P/N from DHL00212F05 to DHL00212F07

2

+3VPCU

Keyboard

RP4
MX1
MX6
MX5
MX0

Jumper & LED (debug use)

10
9
8
7
6

1
2
3
4
5

MX7
MX2
MX3
MX4

CN9

R210

330_4 ECPWRLED

LED4
2

1

8
6
4
2

7
5
3
1

PWRLED#

PWRLED# 28,29

100Px4

MY7
MY13
MY8
MY9

CP4

8
6
4
2
100Px4

JP13
B

NBSWON#

28,29 NBSWON#

1

2

100Px4

SHORT PAD

100Px4

100Px4

100Px4
C38

C37

MY3
MY5
MY14
MY6

CP6

8
6
4
2

7
5
3
1

MX7
MX2
MX3
MX4

CP9

8
6
4
2

7
5
3
1

MY10
MY11
MY12
MY15

CP8

8
6
4
2

7
5
3
1

MX0
MX5
MX6
MX1

CP7

8
6
4
2

7
5
3
1

MY2
MY1
MY0
MY4

K_LED_P
MY16

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

LED_G_LTST-C190KGKT

7
5
3
1

8/15 Modify Keyboard pin define

36

10KX8
+3VPCU

1/18 change footprint from 88171-3400L-34P-L to 91504-340N-34P-L

MY17
K_LED_P
MY2
MY1
MY0
MY4
MY3
MY5
MY14
MY6
MY7
MY13
MY8
MY9
MY10
MY11
MY12
MY15
MX7
MX2
MX3
MX4
MX0
MX5
MX6
MX1
K_LED_P
CAPSLED
FN_F10
NUMLED

29

MY17

29

MY2
MY1
MY0
MY4
MY3
MY5
MY14
MY6
MY7
MY13
MY8
MY9
MY10
MY11
MY12
MY15
MX7
MX2
MX3
MX4
MX0
MX5
MX6
MX1
K_LED_P
CAPSLED
FN_F10
NUMLED

C39

C436

100p/50V_4

100p/50V_4

A:(8/29) reserve cap for EMI
29
28,29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
28,29
28,29
28,29
29
28,29
29
29

1/17 Remove CN10 (Keyboard CONN)

B

29
29
29
+3V

35

2/13 EMI
stuff C39,C436

K_LED_P
MY16

R32

150_4 K_LED_P

88171-3400L-34P-R

CP5

100p/50V_4
MY17

Keyboard Side

8/15 Add K_LED_P power

100p/50V_4
MY16

15"

17"

V

V

A:(8/23) Add 0.1u

CAPSLED
K_LED_P
(Pin 31)

FN_F10

A

A:(8/27) Confirm with EC FAE,
MY no need External PU resister

A

V

K_LED_P
(Pin 6)

NUMLED

V

K_LED_P

V

PROJECT : BD3G

(Pin 1)

Quanta Computer Inc.
Size

Document Number

Date:

Thursday, May 29, 2008

Rev
2A

SW/LED/KEYBOARD
5

4

3

2

Sheet
1

30

of

42

5

4

CPU NUT

HOLE25
H-C236D146P2
HOLE32
MD@H-C236D146P2

MDC NUT

1

1

UMA sku

(BOT)

VGA NUT
1

1

NUT P/N Control Table

HOLE23
H-C236D146P2

(BOT)

HOLE15

FBBL5002010

FBBD3021010

HOLE24

FBBL5002010

FBBD3021010

HOLE25

FBBL5002010

FBBD3021010

Mini-PCI-B NUT

1

(BOT)

D

EV sku

1

HOLE24
H-C236D146P2

HOLE18
H-C236D146P2

1

HOLE15
H-TC315BC236D146P2

2

HOLE17
H-C236D146P2

1

HOLE

3

1/18 HOLE 17,18.23 FBBL5004010
change to FBBL5002010

Take care NUT P/N base on IV/EV sku

D

(BOT)

Stitch CAP
10/31 EMI request
2/18 HOLE 15,24.25 FBBD3017010
change to FBBD3021010

HOLE13
H-C236D146P2

HOLE28
HOLE35
*H-C236D126P2 *H-C236D126P2

Mini-PCI-A NUT

2/18 HOLE 13,14 FBBL5008010
change to FBBL5051010

B:(10/17) update footprint

KB NUT

For fix HyperTransport nets
across plane splits

2/18 HOLE 28.35 FBBL5007010
change to FBBL5050010
1

(TOP)

1

1

1
HOLE6
H-C236D146P2

1

CPU_CORE0

(BOT)
1

HOLE5
H-C236D146P2

B:(10/17) update footprint

HOLE14
H-C236D146P2

5/5 remove HOLE28,35 (HD Decoder)

C134

0.01u/16V_4

C133

0.01u/16V_4

C130

0.01u/16V_4

C135

0.01u/16V_4

VIN

4/17 update HOLE13,14 footprint to H-C236D146P2
C768
C769
C770
C771
C772
C773
C774
C775
C776
C777
C778
C779
C780
C781
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4

E-SATA NUT

EMI CAP.

(BOT)

HOLE39
*H-C216D91P2

HOLE16
*H-CT315

VIN

C746
C63
C87
C137
C106
C97
C119
C169
0.1u/10V_4
0.1u/10V_4 0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4 0.1u/10V_4

C529
C270
C472
C758
C755
C756
C31
C30
C74
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4

1

HOLE34
*H-C216D91P2

1

HOLE22
*H-C216D91P2

1

HOLE9
*H-C216D91P2

1

HOLE8
*H-C216D91P2

1

1

HOLE38
*H-C236D91P2

1

HOLE30
*H-C236D91P2

C

VIN

4/21 remove Hole31,37

1

C

+3V

+3V

A:(9/17) Base ON EMI mail(9/13) Item5
HOLE33
*h-sped110p2

HOLE26
*H-C216D91P2

HOLE40
*H-SPED118P2
C244
C243
C204
C202
C162
C138
C749
C112
C742
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4

C12
C65
C2
C416
C451
C1
C71
C72
C50
C62
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4

1

1

1

A:(9/12) Base ON EMI mail(9/13) Item1

B:(10/17) update footprint

10/24 update footprint

+3V

+3VPCU

+3VSUS

+5VPCU

B

B

HOLE43
*H-TSBC315D118P2-8
7
6
8
5
9
4

C450
C454
C224
C480
C409
C460
C455
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4 0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4

1
2
3

1
2
3

HOLE44
*H-TS315BC295D118P2-8
7
6
8
5
9
4

C83
C161
C132
C165
C760
C205
0.1u/10V_4 0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4

B:(10/17) update footprint
HOLE21
HOLE20
*H-C335D118P2-8
*H-C335D118P2-8
7
7
6
6
8
8
5
5
9
9
4
4

HOLE11
*H-C315D118P2-8
6
7
5
8
4
9

1
2
3

HOLE10
*H-C335D118P2-8
6
7
5
8
4
9

1
2
3

1
2
3

HOLE12
*H-C335D118P2-8
6
7
5
8
4
9

1
2
3

1
2
3

HOLE7
*H-C335D146P2-8
6
7
5
8
4
9

+1.5V

C464
C745
C51
C3
C759
C59
0.1u/10V_4 0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4

+1.8V

+3VPCU

C813
C814
0.1u/10V_4
0.1u/10V_4

+1.2V

C164
C547
C122
C748
C32
C33
C75
C34
C70
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4

+5V

+5VPCU

R85
0_8

C273
C213
C574
C107
C146
C528
C163
C127
C585
C584
C139
C271
C462
C442
C171
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4 0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4 0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4

C16
C757
C45
0.1u/10V_4
0.1u/10V_4 0.1u/10V_4
A

1
2
3

1
2
3

HOLE4
*H-C335D118P2-8
6
7
5
8
4
9

1
2
3

1
2
3

1
2
3

HOLE19
*H-C335D118P2-8
6
7
5
8
4
9

HOLE27
HOLE29
*H-C335I248D118P2-8 *H-C335D118P2-8
7
7
6
6
8
8
5
5
9
9
4
4

1
2
3

1
2
3
1
2
3

A

HOLE36
*H-C335D118P2-8
7
6
8
5
9
4

HOLE41
*H-C335D118P2-8
6
7
5
8
4
9

C229
C518
C128
*0.1u/10V_4
*0.1u/10V_4
*0.1u/10V_4

3/3 EMI request add C813,C814
+5V

HOLE42
*H-C276D118P2-8
6
7
5
8
4
9

C240
C549
0.1u/10V_4
0.1u/10V_4

10/31 EMI request
+1.8V
RAMP:(1/16) Follow BL5, update Hole footprint (13pcs)

PROJECT : BD3G
C599
C385
C283
C203
C189
C176
C173
C153
0.1u/10V_4 0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4

Quanta Computer Inc.
Size

Document Number

Rev
2A

HOLE/EMI CAP/ESD PAD
Date:
5

4

3

2

Sheet

Thursday, May 29, 2008
1

31

of

42

5

4

3

VA
PCN4

PF5
LITTLE-10A-1206
1
2

4

0.02_7520
PR148

PD17
PDS1040S-13
1

PL14
HI0805R800R-00_8

3

1

2

12/11

R1

VA2

2

1

PQ39
FDD6685
4

3

PQ38
FDD6685
4

VIN
3

2
3
PL13
HI0805R800R-00_8

PC25
0.1u/50V_6

PR27
220K/F_6

PC109
0.1u/50V_6

PR15
33K_6

PC110
2.2n/50V_6

1

PC5
0.1u/50V_6

1

2.2n/50V_6

2

PC4
0.1u/50V_6

1

PC50

1
PD16
P4SMAJ20A

D

PR40
*10K/F_6
28,29

PD6
ACIN_1

ACIN

2

2

5

3

4

PR47
PR28
220K/F_6

11/02 Addition resistor
1
29

CHG_EN

PR18
10K_6

0_6
D/C#

29

PQ6
IMD2AT108

CSIN_1

2

PR168
PR
168
0_6

*ZD12V
PR41
*6.8K/F_6

6

3

PD4
SW1010CPT

20277-04XX-4P-L

1

PR25
*10K/F_6

PQ5
DMN601K-7

CSIP_1
VIN
PL9
HI0805R800R-00_8

6251EN

PR19
2.2/F_6

PR17
20/F_6

+3VPCU

PR42
4.7_6

PC16
0.1u/50V_6

Discrete

PC23
4.7u/10V_8
1
2

ISL6251_VDDP

ACPRN

23

GND

1

PL7
HI0805R800R-00_8

6251EN

+3VPCU

PC108
0.1u/50V_6

PR141
*10K/F_6
PR136
PR
136
0_6

29

PR7
*100K/F_6

1

2

CELL-SET
PR140
*100K/F_6

PD15
ZD3.6V
2

2

1

PD13
ZD3.6V
PD14
3TEMP_MBAT

29

1

+3VPCU

2

PQ35
*DMN601K-7

1

1

MBCLK

29

PQ34
*DMN601K-7

BAT-V

2

ISL6251_LGATE
PC125
0.01u/50V_6

4
PQ7
FDS6690AS

12

PC40
2.2n/50V_4

PC123

PC120

PC118
2.2n/50V_6

CSOP_1

10u/25V_1206

11
CSON_1

CHLIM

R2

PR36
10K/F_6

10u/25V_1206

2/14

VREF

10

9

VRFE
8

ICM

VCOMP

7

1

PR61
2.2/F_4

13

B

PR37
*514K/F_6

Float = 4.2V / CELL

VADJ

CV-SET

ACLIM

PR38

29

*0_6

VREF
CC-SET

29

R3

PC19
100p/50V_6

PC14
0.01u/50V_6

6251CELLS_2
3

PR137
100_4
MBDATA

A

PR142
*10K/F_6

47p/50V_6

PR35
10K/F_6

PR34
*514K/F_6

PR20
100_4

PR139
*100K/F_6

PC6
0.01u/50V_6

ICMNT
PR143
3.3K/F_6

PC116
0.01u/50V_6

ICMNT

LIM = (1/R2)*(((0.05/VREF=2.39)VACLM)+0.050)
CURRNT LIMIT POINT =(90w/19v)*0.85= 4.026A
4.026A=(1/0.02)((0.05/2.365)Vaclm+0.05)

Vaclm=((33//152)/(33//152+19.6//152))*Vref
A

PC15
*100p/50V_6

2

PR135
100_4

6251LR

1

47p/50V_6

ADDRESS: 16H

ICOMP

6251CELLS_1

6251CELLS_1

BTJ-09HF1G

14

ISL6251_PHASE

PR145
0.03_3720

PL12
6.8uH

3

PC8

ISL6251_VDD

PR138
100K/F_6

2
PC7

PR11
*10K/F_6

6

2

11/5

BUS-15A-1206

18

2

29

EN

6251VCOMP2

1

ID

TEMP_MBAT 29
HI0805R800R-00_8
PL6
BAT-V

ACLIM

3

6251VCOMP1

MBAT+
ID
B/I
TEMP_MBAT

PR14
10K/F_6

CELLS

PF4

12/11

ISL6251_UGATE

ACSET

4

CN20

PQ42
P
Q42
FDS8878

3
2
1
VADJ

6251ICOMP 5

PC107
100p/50V_6
TEMP_MBAT

1

15

DCIN

6251ACSET 2
PR8
10K_4

4

1
24

PR6
82.5K/F_6

PR5
*100K_4

PD5
3 ID

LGATE
PGND

DCIN

+3VPCU

PU4
ISL6251A

ACPRN

PC10
0.1u/50V_6

+3VPCU

10 1
2
11 3
4
5
6
7
12 8
9
13

1

PHASE

C

2

10A
10A
DKA00VFU000 DKA00VFU000

17

PC18
0.1u/50V_8
6251B_1

CSON

PR13
20/F_6

PR10
10/F_6

B

20

UGATE

CSON 22

6251B_2
16

3
2
1

CSON_1

PR26
2.7_6

BOOT

PC124
10u/25V_1206

1

PQ52
DMN601K-7
2

10K Ohm
10K Ohm
CS31003F949 CS31003F949

CSOP

PC29
0.1u/50V_6
PC26
2.2n/50V_6

5
6
7
8

PC12
47n/25V_6

PD7
RB500V

VDDP

CSOP 21

VDD

CSOP_1

1

PF1

ACIN

PR21
100K/F_6

CSIN

2.43K Ohm
10K Ohm
CS31003F949 CS22433F913

PR16
20/F_6

CSIP

PR151
4.7K/F_6

28,29

R3

CSIN

19

CSIP

2

R2

20m Ohm
20m Ohm
CS+020AGM00 CS+020AGM00

1

R1

3

C

5
6
7
8

Input sense resistor and Constant power setting table

UMA

VA3

PC9
2.2u/10V_8
ISL6251_VDD 1
2

PR169
100K/F_6

11/5

11/2

1

PC49
0.1u/50V_6

2

PC143
0.1u/50V_6

D

PC17
3.3n/50V_4

R2=adapter current sense resistnece

2

2

PROJECT : BD3A/BL5A
*DA204U

*DA204U

Quanta Computer Inc.
A:(9/7) Add ESD diode base on EC FAE suggestion

5

CELL-SET = Hi ----> Cells = VDD ---->4S
CELL-SET = Low ----> Cells = GND ---->3S
4

3

2

Size
Custom

Document Number

Date:

Thursday, May 29, 2008

Rev
1A

CHARGER (ISL6251A)
Sheet
1

32

of

42

5

4

MAIND

SUSD

MAIND

36,37

SUSD

37

4

3

1

SYS_SHDN#

2

1

2
ISL6237_3V

12/11

12/11

PR125
0_4

VIN

VIN

D

D

VL
VL

2

+

1

PR114
0_4
PC91
*0.01u/16V_4

3V5V_EN

1

PR119
63.4K/F_4
+

5V_DL

1

4

PC95
0.1u/50V_6
PQ33
PR129
1/F_6

1
2
3

PR120
10K/F_4

FDS6690AS

1

1

+3VPCU

3
2
1

+3VPCU
PR117
196K/F_6
2

3V_LX

5
6
7
8

REFIN2
1

32
31
30
29
28
27
26
25

REFIN2
ILIM2
OUT2
SKIP#
PGOOD2
EN2
DH2
LX2

C

SKIP
DDPWRGD_R
3V5V_EN

4
PR111
0_6

+
PC70

PC73

PC94
0.1u/50V_6

PQ30
FDS6690AS

PR131
1/F_6

1

2
3V_DL

2

PR118
*0_6

0.1u/50V_6

330u/6.3V_6X5.7

0.1u/50V_6
330u/6.3V_6X5.7

PR166
0_6

PC96
0.1u/50V_6

2
PD12
1PS302

SKIP

PR130
0_6

VL

PR123

12/11

PC101
0.1u/50V_6

PR163

PR133
+15V_ALWP

+15V

2
PR132
*200K_4

REFIN2
PR134

*0_6

+3VPCU

*39K/F_4

SUSD
PR108
22_8

PR104
1M_6

4

PR109
22_8

PQ23
*FDC653N_NL

3

+3VPCU
PR110
1M_6

SYS_HWPG 29
B

Iocp=8-(2.48/2)=6.67A
Vth=6.67A*15mOhm=100.05mV
R(Ilim)=(100.05mV*10)/5uA
~200.1K

PR128

+15V

+1.2V_S5

PR126
0_6

1
2
5
6

+3V_S5

1
PC99
0.1u/50V_6

PR127
*10K_6
DDPWRGD_R

2

22_8

+3VPCU

*0_6

1

Iocp=10-(4.18/2)=7.91A
Vth=7.91A*15mOhm=131mV
R(Ilim)=(105mV*10)/5uA
~237K

VIN

3V_DL

3

0_6

L(ripple current)
=(19-3.3)*3.3/(2.2u*0.5M*19)
~2.48A

2
PD11
1PS302

REF

*0_6

OCP:8A

PC97
0.1u/50V_6

L(ripple current)
=(19-5)*5/(2.2u*0.4M*19)
~4.18A

PR121

PC98
1u/16V_6

3
1

OCP:10A

B

PU11
ISL6237

1

10u/25V_1206

LDOREFIN
LDO
VIN
NC
ONLDO
VCC
TON
REF

8
7
6
5
4
3
2
1
PAD
PAD
PAD

PC100

BYP
OUT1
FB1
ILIM1
PGOOD1
EN1
DH1
LX1
PAD
PAD

35
34
33

PC93

2

PC102

9
10
11
2
12
237K/F_6 DDPWRGD_R 13
3V5V_EN
14
15
16
37
36

OCP : 8A

PL4
2.2uH

3
2
1

1
PR122

8
7
6
5

2

5V_LX

*0_6

11/2

17
18
19
20
21
22
23
24

1
2
3

PL5
2.2uH
+5VPCU

PQ29
FDS8878

3V_DH
PR112

+5VPCU

C

REF

BST1
DL1
PVCC
NC
GND
PGND
DL2
BST2

5V_DH

11/2

+5VPCU

1

4
PR113
115K/F_4

PQ32
FDS8878

OCP: 10A

PC85
10u/25V_1206
PC84
2.2n/50V_4

PC90
0.1u/50V_6

8
7
6
5
4

PC86
0.1u/50V_6

5
6
7
8

PC87
*10u/25V_1206

PR115
0_4

PC92
1u/16V_6

2

PC88
0.1u/50V_6

1

PC80
100u/25V_6X7.7

PC81
10u/25V_1206

2

PC82
2.2n/50V_6

2

PR124
39K/F_4
PC83
0.1u/50V_6

PC89
4.7u/10V_8

2

1

PR116
390K_4

+3VSUS

1
2
5
6

+5VPCU

3

3

3

3

S5D
+3VPCU
S5D

PQ22
FDC653N_NL

3

2
PQ28
DMN601K-7

PQ26
DMN601K-7

5
6
7
8

PQ27
DMN601K-7

+3V_S5
MAIND 4

A

4

2
5
6
7
8

PR105
1M_6

1

PQ25
DTC144EU

2

1

2

1

MAIND 4

A

PQ21
FDS8878

3
2
1

PQ31
FDS8884

PROJECT : BD3A/BL5A

3
2
1

S5_ON

1

29,37

+5V

Size

+3V

SYSTEM 5V/3V (ISL6237)
Date:

5

4

3

Document Number

Quanta Computer Inc.

2

Thursday, May 29, 2008

Sheet
1

33

of

42

Rev
1A

B

C

D

3A

2

+

PQ48
SI4914

10/F_6

1.0

1

0.8

2

8

7

PHASE_NB

PR176
44.2K/F_4

PR209
P
R209 PR179
PR179
0_4
0_4
UGATE_NB

38

1

PC126
0.1u/50V_6

PC130
10u/25V_1206
UGATE_0

PC160
10u/25V_1206

PC162
0.1u/50V_6

4

37

40

20A

4

LGATE_0

27

PC112
10u/25V_1206

4

1
2

1

1
UGATE_1

PHASE_1

2

LGATE_1

28

2

29

PC141
2.2u/10V_6

PC147
10u/25V_1206

PC157
0.1u/50V_6

PQ37
AOL1414
UGATE_1

11/2

25

1

PL16
1

2

PC164
0.1u/50V_6

PR238
2.2/F_4

CPU_CORE1

1
2
3

PQ41
AOL1412

PC190
2.2n/50V_4

2
PC173
0.1u/50V_6

+

2

4

2

1

+
LGATE_1

1

2

20A

TOKIN
0.36uH
2

1

26

PR202 1/F_6

ISN_0

2

PR203
0_6

PC135
330u_2V_7343

PC165
330u_2V_7343

2/14

PR215
18.2K/F_4
ISP_1

1

4 CPU_VDD0_FB_H

PC105
330u_2V_7343

VIN

2

PR201
P
R201
0_6

PR205
6.81K/F_4

2

2
PC161
330u_2V_7343

+5VPCU

1

5

31

ISN_1
PC172
0.1u/50V_6

1

1

4

3

0_6

ISN_0

30

ISN_1

ISP_1

0_6

+

2/14

2
1

5/27

PR213
18.2K/F_4

PR189

ISP_0

PR178
P
R178 PR207
PR207 PR187
PR187 PR186
PR186
0_4
0_4
0_4
0_4
PR160
3.92K/F_4

CPU_CORE0
PR212
10/F_6

PQ43
AOL1412

32

24

VW_1

23

21

22

COMP_1

BOOT_1

PR199

1

UGATE_1

VW_0

PC189
2.2n/50V_4

4

COMP_0

ISP_0

Close to
CPU socket

+

1

PHASE_0

3

5

PHASE_NB

UGATE_NB

PGND_NB

LGATE_NB

RTN_NB

OCSET_NB

FSET_NB

VSEN_NB

FB_NB

PHASE_1

13

PC122
1000p/50V_6

2

FB_0

ISP_0

PR177
6.81K/F_4
2
1

PGND_1

FB_1

12

LGATE_1

VDIFF_0

VDIFF_1

11

OCSET

20

2

PC111
2 1200p/50V_4

LGATE_0
PVCC

19

9

PU3
ISL6265

CPU_CORE0

1
2
3

RBIAS

8

5/5

PC106
180p/50V_4

33

2

PC113
0.1u/50V_6

5

ENABLE

7

10
1

1

6

VSEN_1

PR157
10K/F_4

PR210
1K/F_4

PR200
54.9K/F_4

1
UGATE_0

0_4

RTN_1

PC158
4700p/25V_4

PGND_0

18

PR196
255/F_4

PR218
107K/F_4

1

SVC

17

2

PHASE_0

RTN_0

PR185
29,35,37 VRON

*0_4

35
34

3

5

CPU_SVC

Pin 49 is GND Pin

SVD

PR237
2.2/F_4

2

0_4

TOKIN
0.36uH
2

2

0_4

PR191

4

3

PR235

BOOT_0
UGATE_0

16

1

4 CPU_PWRGD_SVID_REG

PR195
CPU_SVD

4

PGOOD
PWROK

VSEN_0

4

11/2

1/F_6

1
2
3

3

PR234
10K_6

BOOT_NB

0_4

15

2

PQ51
DTC144EU

PR190

+3V

PQ46
AOL1414

PL17
1
PR162

2

4,29 CPU_COREPG
+1.8V

OFS/VFIXEN

PR206
1/F_6

36

PR192 *10K/F_4

ISN_0

3

0_4

14

PR188

COMP_NB

1

VIN

+3V

12/11

VCC

GND

1
2
3

39

41

42

43

44

45

46

*0_4

47

PR182

49

0_4

48

PR181
+5VPCU

1

0

1

VIN
LGATE_NB

PR217
11.3K/F_4

2

1

PC166
0.1u/50V_6

1

1.2

2

1.4

1

1

0

0

2

0

12/11

2/14

1

Output

PC159
1000p/50V_6

PC163
33p/50V_4
PC114
1200p/50V_4

VIN

SVD

6

5
PR198

VFIXEN VID Codes

PR211
22.1K/F_4

0_8

2

0.8

5

1

2

1

PC134
1u/25V_8
PR214

1

0.9

2

1.0

0

1

1

1

4

UGATE_NB

1

0

PC167
0.1u/50V_6

PC194
330u_2V_7343

2

1.1

2

0

+5VPCU

2

0

PC140
10u/25V_1206

1

Output

PC171
10u/25V_1206

G1

SVD

S1/D2

SVC

SVC

PR158
10/F_6

PR208 10/F_6

Metal VID Codes

2

PC103
10u/25V_1206

4 CPU_VDDNB_FB_L

4

1

1
4
1

PR219
10/F_6

2

X

G2

O

O

D1

X

X

S2

X

+5V

D1

+3.3V

VIN

4 CPU_VDDNB_FB_H

2

X

1

O

2

VFIX
3

SVI

1

GND

LGATE_NB

CPU VDDNB_CORE

Offset &
Droop
O

OFS/VFIXEN

E

12/11

PL11
2.5uH

1

A

PC104
1000p/50V_6

4 CPU_VDD0_FB_L

PR216
3.92K/F_4

ISN_1

5/27

Parallel
PR194
10/F_6

12/18

1

Close to
CPU socket

2

2

CPU_CORE0

CPU VDDNB_CORE

PC142

PC191

+

PC193
330u_2V_7343

2

330u_2V_7343

1
+

PC169
*330u_2V_7343

+

2

PC168
180p/50V_4

1K/F_4

2

PR197

2

4 CPU_VDD1_FB_L
4 CPU_VDD1_FB_H

1

4.7n/25V_4

1

1

1

PR184
10/F_6

CPU_CORE1

PC170
1200p/50V_4

PR204
255/F_4

1

CPU_CORE1

1

2/14

PR183
10/F_6
PR180
54.9K/F_4

4/10 add PC191,PC193

PROJECT : BD3A/BL5A
Quanta Computer Inc.
A

B

C

D

Size
C

Document Number

Date:

Thursday, May 29, 2008

Rev
1A

OZ826 CPU
Sheet
E

34

of

42

1

2

3

4

5

VIN-1.2V

12/11
VIN

+5VPCU

12/23 delay +NB_CORE

PR68

0.1u/50V_6

PR81
*100K/F_6

PR82
0_6

47K_6

1
2
3
4

TON

UGATE

VOUT

PHASE

VDD

PU6
RT8202

FB
PGOOD

OC
VDDP
LGATE

PQ14
FDS8878

PC52
0.1u/50V_6

1/18 Change PL15 Footprint from CDRH104R to
CDRH104R-BD3A (SMT open issue)

12

PHASE-1.2V

11
10

3
2
1

UGATE-1.2V

PR83

PL15
2.5uH

2/14

8

6.04K/F_6

PR240
*2.2/F_4
LGATE-1.2V

PC192
*2.2n/50V_4

PR72
PC41
*22p/50V_6

3.65K/F_6

12/31

2

Rds*OCP=RILIM*20uA
3
2
1

2/14

GND

GND

5A

+
PC144

4

7
17

12/11

+NB_CORE

9

PQ50

470u_2.5V_7343

PC145
10u/10V_8

PR67
10K/F_6

FDS6690AS

21

NC

18

2

2

TPAD
GND

14

NC
GND

PC45

1u/16V_6

PGND

20

PC43

1

PC42

1

5

GND

19

6

PC51
10u/25V_1206

13

1

29 HWPG_1.2V_NB

BOOT

4

1

16
PC44
0.1u/50V_6

12/11

EN/DEM

4.7u/10V_8

5
6
7
8

15

29,37 +1.2V_ON

A

PC47

PC53
0.1u/50V_8

B:(10/16) change PR81 from 10k(no stuff) to 100k(stuff)
PR79

2

PR71
1M_6

29,34,37 VRON

1

PC48

5
6
7
8

PD10
RB500V

*0_6

2

10_6

4/10 del PR81

PR75
A

B

B

*1n/50V_6

0.01u/50V_6

VOUT=(1+R2/R3)*0.75

1.2V_FB

TON=3.85p*RTON*Vout/(Vin-0.5)

6A OCP --- OC=4.53K
FDS6690AS Rds=15mOhm

Frequency=Vout/(Vin*TON)

12/14 change PR73 from 8.25K to 35.7K

+5VPCU

HI --- 1.0V
LOW ---1.1V

PR73
1.2V_FB
35.7K/F_6

3

PR93
10K/F_6
PR80
0_6

2
1

2/14
PR103

2

1

PQ10
DMN601K-7

PR86
*0_6

100/F_6

3

PC46
0.022u/50V_6

2

+NB_CORE_ON

11

PQ49
DMN601K-7

C

1

C

+NB_CORE

VIN

+1.2V

PR70
22_8

PR76
22_8

3

3

PR69
1M_6

3

12/14 del +1.35V_VDDHTTX
PU15
PC180,PC182,PC179
PR227,PR226,PR225

PR74
1M_6

2

2

2

29,37 +1.2V_ON

1

PQ12
DMN601K-7

1

PQ9
DMN601K-7

1

PQ13
DTC144EU

D

D

PROJECT : BD3A/BL5A
Quanta Computer Inc.
Size

Document Number

Rev
1A

NB_VCC (RT8202)
Date:
1

2

3

4

Thursday, May 29, 2008

Sheet
5

35

of

42

5

4

3

2

1

D

D

12/11
VIN
+1.8VSUS
PR146

5

PC136

2.2/F_6
10u/10V_1206
PU12
TPS51116

2

+SMDDR_VTERM
PC137
10u/10V_8

PC139
10u/10V_8

DIS_MODE
C

PR167
0_6
*0_6

5VIN
PC138
0.033u/50V_6

DIS_MODE

5VIN

19

VBST

20

LL

18
17

VTT

5

GND

DRVL

3

VTTGND

PGND

16

6

MODE

S3

11

VTTREF

S5

12

V5IN

14

PGOOD

13

8

COMP

9

VDDSNS

10

VDDQSET

21
22
23
24
25
26
27

CS

PC128

PR154

4 VDDIO_FB_L

PR232

*0_6

PR233

*0_6

R1

10A
12/11

OCP: 12.44A

+

*0_6

S3_1.8V
S5_1.8V

MAINON 21,29,37

PR153

SUSON

C

2.2/F_6

4

29,37

0_6

5VIN

PQ40
AOL1412
PC117
2.2n/50V_6

PC121
560u/2.5V_6X5.7

PC119
10u/10V_8

15

PC129

2/14

12/11

PR147
5.1K/D_6

5VIN

1

HWPG_1.8V 29

2
4 VDDIO_FB_H
B

PC13
10u/25V_1206

PR144

PR156
0_6

R2

PC11
10u/25V_1206

+1.8VSUS

(10u*PR35)/Rdson+Delta_I/2=Iocp

PR149
0_6

FOR DDR II
+5VPCU

PC115
2.2n/50V_6

2.2uH

*1n/50V_6

0_6

PC127
2.2n/50V_6

0.1u/50V_6
PL10

VTTSNS

PR164
0_6
+1.8VSUS PR65

DRVH

1
2
3

VLDOIN

4

7

+SMDDR_VREF

PR66

1

5

*0_6

1
2
3

PR236

5 CPU_VTT_SENSE

4

GND
GND
GND
GND
GND
GND
GND

2A

PQ36
AOL1414

S3_1.8V

S5_1.8V

PC133
4.7u/6.3V_6

PR165
*110K/F_6

PR161
*76.8K/F_6

S3_1.8V

B

S5_1.8V

11/02
+1.8VSUS

Allen 0929

PC132
*0.1u/50V_6

PC131
*0.1u/50V_6

R1=(100*Vout-R2)K

MAIND

MAIND

PQ19
FDC653N_NL

3

4

33,37

1
2
5
6

if tune Vout PR38 un-mount, PR156 PR165 mount

+1.8V

A

A

PROJECT : BD3A/BL5A
Quanta Computer Inc.
Size

Document Number

Rev
1A

DDR 1.8V(TPS51116)
Date:
5

4

3

2

Sheet

Thursday, May 29, 2008
1

36

of

42

5

4

3

2

1

PQ24
AOL1414
+1.8VSUS

3
2
1

5
PC71

PC72
10u/6.3V_6

+5VPCU

4

0.1u/50V_6

9338DRV

12/11

PU10
RT9025-25PSP

PR100

4

+1.2V
0_6
D

29,33
3,4,12,13,15,16,31,35

2

+1.2V

PGD

DRV

*10K_6

MAINON

21,29,36 MAINON

PR99 0_6

+5VPCU

EN

1

29,35 +1.2V_ON

VCC

VPP PGOOD

1

VEN

6

VIN
GND
GND

VO

+1.2V_S5

D

1A
NC

5
PR222
17.4K/F_6

PC175
10u/10V_8

+

0.8V

Vout1 = (1+Rg/Rh)*0.5

PR98
10K_6

PU9
G9338

0.1u/50V_6

3
8
9

PR96
14K/F_6

5

ADJ

2

PC76
PR97 *0_6

PC75
0.01u/16V_4

2

+3VPCU

4.5A
Rg

9338EN 4

GND

PR101

1

29 HWPG_CPUIO

6

PR221

7

3

0_6

S5_ON

ADJ

PC176
0.1u/25V_6

PC177
10u/4V_8

PC178
0.1u/50V_6

PC174
*0.1u/50V_6
PR220
34K/F_6

Rh

29,34,35 VRON
PC68
0.1u/50V_6

PC69
10u/6.3V_6

PC74

12/11

PC66
560u/2.5V_6X5.7

Vout =0.8(1+R1/R2)
=1.2V

*1u/16V_6

12/11

12/11

12/23 change to +1.2V_ON

12/19 change PR230 from 10K to 0

0_6

29,35 +1.2V_ON

PR230

+1.8VSUS
PR102

VPP PGOOD

2

VEN

3
8
9

VIN
GND
GND

HWPG_1.1V_NB

6

VO

29

MAINON 0_6

2
3
8
9

+1.8VSUS

2A
5

NC

PR228
13K/F_6

C

VPP PGOOD

1

VO

6

VEN
VIN
GND
GND

PC185
10u/10V_8

HWPG_1.5V 29
+1.5V

1.5A
NC

5
PR90
30.1K/F_6

PC60
10u/4V_8

PC188
PC184
0.1u/25V_6
*0.1u/50V_6

PC64
0.1u/50V_6

PC63
*0.1u/50V_6
PR89
34K/F_6

PR229
34K/F_6

12/24 12/18

PC62
10u/10V_8

0.8V

0.8V
PC187
10u/4V_8

PR91

+1.1V_NB

7

100K/F_6

PU8
RT9025-25PSP

4
1

ADJ

PU16
RT9018A

4

7

PC186
0.1u/25V_6

PC61
0.1u/50V_6

ADJ

C

+5VPCU

12/24

+5VPCU

Vout =0.8(1+R1/R2)
=1.5V

Vout =0.8(1+R1/R2)
=1.1V

12/11

B

B

+1.8VSUS

+3VSUS

+SMDDR_VTERM

+5VPCU

+15V
PC56
0.1u/50V_6

PR152
1M_6

PR150
22_8

PR95
*22_8

PR159
22_8

PR94
1M_6

MAINON 0_6
33

2
3
8
9

+3VPCU

3

3

SUSD

PR87

PR155
1M_6

2

2

2

2
PQ45
DMN601K-7

PQ18
DMN601K-7

PC67
*2.2n/50V_4

VIN
GND
GND

1

HWPG_2.5V 29

6

+2.5V

0.25A
NC

5
PR85
73.2K/F_6

PC55
10u/10V_8

0.8V
PC59
10u/4V_8

1

1

PQ20
*DMN601K-7

1

PQ44
DMN601K-7

1

PQ47
DTC144EU

12/11

VO

2

SUSON

1

29,36

VPP PGOOD
VEN

7

3

3

SUSD

3

SUS_ON_G

PU7
RT9025-25PSP

4

ADJ

VIN

PC58
0.1u/50V_6

PC57
*0.1u/50V_6
PR84
34K/F_6

VIN

+3V

PR9
1M_6

A

+5V

PR78
22_8

+1.8V

PR4
22_8

Vout =0.8(1+R1/R2)
=2.5V

+15V

PR88
22_8

PR92
1M_6

A

33,36

3

3

MAIND

3

3

MAIND

3

MAINON_ON_G

2

1

PROJECT : BD3A/BL5A

2

PQ4
DMN601K-7

PQ15
DMN601K-7

PQ17
DMN601K-7

PC65
*2.2n/50V_4

Quanta Computer Inc.

1

2
PQ11
DMN601K-7

1

2

1

PQ16
DTC144EU

1

12/11

PR12
1M_6

2

21,29,36 MAINON

Size

Document Number

Date:

Thursday, May 29, 2008

Rev
1A

Discharge (1.25V/1.5V)
5

4

3

2

Sheet
1

37

of

42

5

4

3

2

1

CPU_CORE0

CPU_CORE1


ISL6265
PU5

CPU VDDNB_CORE
RT8202

+NB_CORE


PU6

D

+5VPCU

D

+5VPCU

FDS8884

+5V


PQ31

VIN

+3VPCU

RT9205

ISL6237

+1.1V_NB


PU16

PU11

+3VPCU

FDC653N

C

ADAPTER
Charger
ISL6251A

+3V_S5


PQ22
FDC653N

+3VSUS


PQ23

+2.5V


PU7
FDS8884

BATTERY

C

RT9025

VIN

PU4

+3V


PQ21
RT9013

+1.2V_S5


PU10

+1.8VSUS

VIN

+1.8VSUS


Below table need be modify (waiting other schematic ready)

FDC653N

+1.8V


PQ19
G9338

+1.2V


PU9
B

TPS51116
PU12

A-test use MAINON + RC delay to replace it

RT9025

+1.5V


PU8

POWER

Distribution

VCC_CORE

CPU

+5VPCU

Battery LED , Power LED , USB , CIR , RTC

+3VPCU

HALL SENSOR , Battery LED , RF LED , kill SW , Jumper LED , KB , Power Board , EC , ID , SPI Flash , CIR

+NB_CORE

RS690M

+5V

CAMERA , Card Reader LED , ODD/HDD LED , Felica , T/P , T/sensor , CRT , HDMI , SB600 , CPU FAN , MXM , Headphone , EC , INT SPK AMP

B

HALL SENSOR , LCD PANEL , LVDS , WLAN , HD Decoder , NEW CARD , KB , KB LED , XD LED , Blue tooth , Touch sensor , Card Reader (OZ129) , ODD/HDD ,

RT9025

+1.35V_VDDHTTX +3V


PU15

HDMI , CRT , TVOUT , REQUIRED STRAPS , DEBUG STRAPS , SB600 , RS690M , DDR , CPU Thermal monitor , CPU FAN , CLK , MXM , VR , FM Tuner MDC ,

The Table NOT READY
Headphone , EC , LAN , Codec(CX 20561)

+3V_S5
SMDDR_VTERM


+3VSUS

SMDDR_VREF


A

WLAN , NEW CARD , SB600 , MXM , LAN
Finger print , SB600

+2.5V

CPU

+1.2V_S5

SB600

+1.8VSUS

SB600 , DDR , CPU , HDT

+1.8V

SB600 , LCD , LVDS , RS690M

+1.2V

SB600 , RS690M , CPU , WLAN , HD Decoder , NEW CARD

+SMDDR_VTERM

DDR , CPU

+SMDDR_VREF

DDR

A

+5V_S5

PROJECT : BD3A
Quanta Computer Inc.
Size

Document Number

Rev
2A

Power Tree
Date:
5

4

3

2

Thursday, May 29, 2008
1

Sheet

38

of

42

5

4

3

NBHT_REFCLK
100MHZ
EXT_NB_OSC
14.318MHZ
SO_DIMM2

SO_DIMM1

EXTERNAL
CLK GEN.
1 PAIR CPU CLK
200MHZ

C

PCI_CLK0
33MHZ

PCIE DEBUG CARD

OZ129T(card reader/1394)
D

24.576MHZ
PCI_CLK5
33MHZ

MXM_REFCLK
100MHZ

MXM module

PCIE_CLK
100MHZ

MINI Card(WLAN)

PCIE_CLK
100MHZ

MINI Card(HD Video Decoder)

PCIE_CLK
100MHZ

NEW Card

PCIE_CLK
100MHZ

1

PCI_CLK1
33MHZ

NBGPP_CLK(RX780 only)
100MHZ
SB PCIE_CLK
100MHZ
SB_OSCIN
14.318MHZ

2 PAIR MEM CLK

2 PAIR MEM CLK

HDMI_CEC
R5F211A4SP5

*8MHZ

NBGFX_CLK(RX780 only)

D

Turion Griffin Dual-Core
Sempron
(638 S1g2 socket)

RX780
RS780M/MC
528 FCBGA

2

KBC
WPCE775

KEYBOARD
TPCLK

TP

32.768KHZ

SB700
528 BGA
BIT_CLK_AUDIO
24MHZ

Azalia Audio Codec
CX20561

C

8040T(10/100)/8055(GIGA)

25MHZ

SBSRC_CLK
100MHZ
USB
48MHZ
B

25MHZ

32.768KHZ

B

14.31818MHZ

PROJECT : BD3A

A

A

Quanta Computer Inc.
Size

Document Number

Rev
2A

Clock distribution diagram
Date:
5

4

3

Thursday, May 29, 2008
2

Sheet

of

39
1

42

5

Model

4

REV DATE
A1A 2007
20071008

BD3G

20071008
20071204
20071204
20071204

D

20071204
20071204
20071204

B2A

20071207
20071207
20071207
20071207

20071207
20071207
20071207
20071207
20071208

20071210
20071210
20071211

C

20071212
20071212
20071212
20071212
20071212
20071212

20071220

20071220
20071221
EMI

B

20071221
20071222
20071222
20080102

C3A

20080117
20080117
20080117
20080117
20080117
20080117
20080117
20080117
20080117
20080117
20080118

A

20080118
20080118
20080118
20080118
20080118
20080118
20080118
20080118

3

2

1

NOTE

CHANGE LIST
FIRST RELEASED : Import BOM ECN
PAGE23:Reverse U42,C761 for VR
PAGE28:Add R667,R668,Q78 for TP_LED
PAGE04:Reverse C762 for AMD engineer CPU use
PAGE19:update CN25 HDMI footprint to HDMI-C12816-119A5-L-19P-V-BL5-1
PAGE15:change BOARD ID3 from GEVENT7 to GPIO48
PAGE14:change BOARD ID PD value from 10K to 1K(R227,R228,R229,R248,R343,R236)
PAGE29:Stuff R510, no-stuff R509 (slove BT module can't bring up issue)
PAGE20: modify display on ckt to avoid flash when into S3/S4/S5 (add Q78,Q80,R670,del Q41,R388)
PAGE19:update CN25 HDMI footprint to HDMI-C12816-119A5-L-19P-H-BD3
PAGE32:update ACIN design
PAGE24:Change R449(0 ohm) to D56(Diode) for leakage issue (3VPCU to 3V_S5)
PAGE23: Slove Audio issue:When plug in-out headphone, headphone has bo sound.
1. Change R652&R651 to C763,C764(10U/6.3V 0603)

ECN Release
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify

PAGE22: Remove D19 to slove Audio issue Switch Mute to Un-mute, sound will delay about 2 seconds.
PAGE14: add D57,D58 to avoid voltage leakage
PAGE30:update LED5,LED6 footprint and PN
PAGE04:add R671~R679 for AMD request
PAGE03:change C223 C225 from 10p to 33p
PAGE15:change C257 C258 from 10p to 27p
PAGE26:change C380 C381 from 22p to 18p
PAGE25:Change New card footprint to NCARD-13180151-T-26P-L-BL5S
PAGE22:stuff R372 for FM
update power
PAGE29: Change U41(CIR) from BEBK0081D00 to BEBK0081D01
PAGE18: Change CN22(S-Video) from DFMD04FR296(Yellow Color) to DFMD04FR006(Black Color)
PAGE30: Change SW4 P/N from DHL00212F05 to DHL00212F07
PAGE31: Update Hole43 H-TSBC315D118P2, Hole 44 H-TS315BC295D118P2
PAGE29: pull down 100k R680 for ECPWROK
A11 to A12 implemen
PAGE12: Del L15 stuff L36
PAGE16: Del R234 stuff R235
PAGE35: Del PU15,PC180,PC182,PC179PR227,PR226,PR225, Change PR73 from 8.25K to 35.7K

D

C

PAGE23: Slove GPRS noise
1. stuff R386/R387/C404/C405 to 0.1U
2. Change L44/41 to BK1608LL121
PAGE29: avoid leakage reserve D59/D60 to CLKRUN#/PLTRST#
PAGE18:add 27p(C790~C793) for TV_Y/G , TV_C/R
PAGE21:stuff C568,C548
PAGE22:stuff R399,R379
PAGE23:Change L43/44 to BK1608LL121
PAGE24:add L74,C766,C767,C789,C788 for +2.5V_1.8V_LAN,add L73 for +1.2V_LAN
PAGE26:add 0 ohm and 22p for SD/MS CLK , R308~R329 0ohm(CS00002JB38) change to 33ohm(CS03302JB29), remove RN34,RN35, stuff L68,L69 for 1394
PAGE28:del R276,R278 stuff L72 , del R613,R612,R624,R626 stuff L70,L71 , add 0.1u for +5VPCU add 100p for 3ND_MBDATA/CLK
PAGE31:stuff all 0.1 cap
update power
PAGE11: stuff R48 2.2K for power play
PAGE24: Per cost down remove LAN eeprom,stuff R381,remove U21,R380,R378

B

PAGE14: NEW_DET# change from Geven3# to GPM1#
Update RX781
PAGE13:Modify RTC circuit. R301,R302 change from 8.66k to 2k. R332 change from 4.7K to 6.8K
PAGE13:Change RTC Battery from VARTA (AHL03001441) to MATSUSHITA (AHL03002005)
PAGE19:Change back HDMI connector(CN25) footprint from HDMI-C12816-119A5-L-19P-H-BD3 to HDMI-C12816-119A5-L-19P-H-BL5(SMT open issue)
PAGE20:for engery star add R684 connect to EC pin27
PAGE24:Change CN28 (RJ45 CONN) from DFTJ12FR024 to DFTJ12FR035
PAGE27:Change CN32(2nd SATA CONN) from DFHS22FR064 to DFHS22FR094
PAGE27:Change CN32 footprint from SATA-127043FR022XX27ZR-22P-L-H to SATA-127043FR022G285ZR-22P-L
PAGE30:Remove CN10 (Keyboard CONN)
PAGE21:Remove R492,R517, Short CN27/Pin189,190 to VIN directly.
PAGE28:Change L72 from CX216900002 to CX163210007(BT circuit)
PAGE08:Change CN19 footprint from DDR-C-292564-200P to DDR-C-292564-200P-BD3A (SMT open issue)
PAGE08:Change CN23 footprint from DDR-C-1734071-200P to DDR-C-1734071-200P-BD3A (SMT open issue)
PAGE30:Change SW4 footprint from SW-NSS506-212F-CCCD1T-3P to SW-NSS506-212F-CCCD1T-3P-BD3A (SMT open issue)
PAGE23:Change CN43 footprint from MDC-1-179373-2-12P-RUV to MDC-1-179373-2-12P-RUV-BD3A (SMT open issue)
PAGE35:Change PL15 Footprint from CDRH104R to CDRH104R-BD3A (SMT open issue)
PAGE22:Add R685 for VISTA WHQL circuit
PAGE24: Change RJ45 footprint from LAN-100073FR012G101ZL-12P to rj45-c100s7-10806-l-12P
PAGE31:HOLE 17,18.23 FBBL5004010 change to FBBL5002010

A

PROJECT : BD3G
Quanta Computer Inc.
Size
Date:

5

4

3

Document Number

Rev
2A

Change list
2

Sheet

Thursday, May 29, 2008
1

40

of

42

5

Model

4

REV DATE
20080118
20080118
20080118

BD3G

20080131
20080131

D

C3A

20080131
20080131
20080131
20080131
20080131
20080131
20080131
20080131
20080131
20080131
20080131
20080131
20080131
20080131
20080131
20080131
20080131
20080201

C

20080201
20080201

20080201
20080201
20080204

20080204
20080205
20080210
20080210
B

20080210
20080210
20080213
20080213
20080213

20080214
20080215
20080215

A

20080215
20080218
20080218

3

2

1

NOTE

CHANGE LIST

PAGE30:change footprint from 88171-3400L-34P-L to 91504-340N-34P-L
PAGE30:LED7,8 change footprint from LED12-21SYGC-TR8 to LED27-21-BHC-ZL1M2TY-3C
PAGE30:change p/n LED7 BEBL0074Z04 (WIMAX),LED8 BE0R0053Z00 (WLAN & BT)
PAGE31:update HOLE42,41,19,4,7,12,10,11,36,27,29,21,20,43,44
voltage leakage issue
PAGE04:modify CPU_PROCHOT# ckt (add R687, no stuff R686,R425), CPU_LDT_REQ#_CPU ,CPU_PWRGD connect to +1.8V
PAGE11:remove Q5,Q3,R83,R80,R97,stuff R88,R77
PAGE14:BOARD_ID4 change from GPIO66 to GPIO3

Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
PAGE14:NEW CARD hot plug issue ,NEW_DET# change from GEVEN5# to GPM1# (SB700 A12 Errata)
Circuit modify
Circuit modify
PAGE19: DEL L56,L57,L58,L59,R465,R474,R493,R495,R486,R488,R478,R483,C226,C227 for HDMI circuit
Circuit modify
PAGE25: add +3V to CN21 pin39,41
Circuit modify
PAGE18: Change L4,L5,L6 to CX8BA470003 to meet CRT spec
PAGE19: Change U11 from ARBL5SV0000 to ARBL5MV0000
Circuit modify
PAGE26:According to customer request, we can't stuff C782 (22pF) in SD/MS_CLK.
Circuit modify
Circuit modify
PAGE25: Change R573 from 28.7K to 0 ohm, Remove C628 for NEW card some device can't work normal
Circuit modify
PAGE14: Change R350 from 1K to 0 ohm (Slove VCCRTC can't reach 0V when clear CMOS.)
Circuit modify
PAGE26: Change CN33(5 in 1 card CONN) P/N from DFHS38FR003 to DFHS38FR005
Circuit modify
PAGE27: Change CN34 (1st SATA) P/N from DFHS22FR063 to DFHS22FR082
Circuit modify
PAGE27: Change CN32 (2nd SATA) P/N from DFHS22FR094 to DFHS22FR083
PAGE20: Change CN5 (I-MIC)P/N from DFHD02MR003 to DFHD02MR016
Circuit modify
Circuit modify
PAGE22: Change CN39(I-MIC CONN) P/N from DFHD02MR003 to DFHD02MR016
PAGE22: Change CN17(SPK CONN) P/N from DFHD04MR012 to DFHD04MR021
Circuit modify
PAGE28: Change CN16(USB-FFC CONN) P/N from DFHD10MR011 to DFHD10MR008
Circuit modify
PAGE28: Change CN13(FP CONN) P/N from DFHD04MR012 to DFHD04MR021
Circuit modify
PAGE28: Change CN14(BT CONN) P/N from DFHD10MR011 to DFHD10MR008
Circuit modify
PAGE22: Change INT-SPK AMP GAIN VALUE. Change R623,R625 from 9.1k to 5.1k 1%,Change R620,R621 from 10k to 16k 1%
Circuit modify
PAGE30: Change R404,R405 from CS13902JB14 (390 ohm) to CS13302JB21(330 ohm)
Circuit modify
RS780M A13 Errata
Circuit modify
PAGE11:change R103 from 150 to 140 CS11402FB01
Circuit modify
PAGE18:RS780M A13 R8 ---> 140 CS11402FB19,MXM R8 ---> 150 CS11502FB21
Circuit modify
PAGE19: change HDMI SCL/SDA pull res R168,R171,R163,R170 to 4.7K ,change R1,R2 to 6.8K
Circuit modify
PAGE20: change Panel SDA/SDC pull res R412,R410 from 39K to 4.7K
Circuit modify
ESD solution
Circuit modify
PAGE23: add Varistor D63,D64,D65 on SPDIF_OUT/HP_JD/+3V_SPD
Circuit modify
Circuit modify
PAGE28: reserve D66 for CN36 , reserve D68,D69,D70 for FP , stuff D71,D72,D73 for BT
Circuit modify
PAGE20:reserve D74,D75,D76 for CCD ,stuff D87 for LID switch
PAGE27:del R270,R597 , connect to +5V directly ,reserve D77~D81 for CN34(1ND HDD) ,reserve D82~D86 for CN32(2ND HDD) ,reserve D67 for CN31 Circuit modify
Circuit modify
PAGE26:reserve D88~D91 for 1394
Circuit modify
PAGE04:reserve D92,D93 for FAN , reserve C795,C796 change R122 to 0 0603
Circuit modify
PAGE13,19,21,25:reserve C797~800 for PLTRST#
PAGE04: pull up R691 CPU_BDREQ# to avoid noise cause system shut down
Circuit modify
PAGE23:Change R714,R715 from 10uF to 0 ohm (Audio HP circuit)
Circuit modify
PAGE18,29: DEL D4,D5 footprint and DEL CRT_SENSE# net, No stuff R218
Circuit modify
PAGE28: DEL C42, Add D94 for CN8/Pin2 (ESD issue) - default no stuff
Circuit modify
PAGE28: Change L70,L71 from CX216900002 to CX163210007
Circuit modify
PAGE28: Stuff L64,L65 to CX163210007
Circuit modify
PAGE27: Add ESATA re-driver IC
Circuit modify
PAGE25: Change the footprint of R33 and R330 from 1206 to 0805
Circuit modify
EMI solution
Circuit modify
Circuit modify
PAGE18: C4,C7,C10,C5,C8,C11 change from 10p to 6.8p
Circuit modify
PAGE28: stuff C391,C701, C559 ,C228,C465,C618,C41,C43, C618,C794,C809,C810
Circuit modify
PAGE20: stuff C427~C432
Circuit modify
PAGE30: stuff C39,C346
Circuit modify
PAGE29: stuff C577,C578,C560
PAGE12: stuff C804~C807 for +NB_CORE
Circuit modify
PAGE25: stuff C40,C36,C54,C58,C289,C352,C319,C272 for WL
Circuit modify
PAGE19: stuff C808 for HDMI
Circuit modify
PAGE15: stuff C375,C366 for SB HW MONITOR
Circuit modify
PAGE22: stuff R627
Circuit modify
PAGE26: change R683 from 0 to 33 ohm
Circuit modify
UPDATE POWER
Circuit modify
PAGE28: CN42 co-layout with CN16
Circuit modify
PAGE31: Remove R98,R145,R118 Hole15,17,18
Circuit modify
PAGE28: Change L70,L71 from CX216900002 to CX201290009
Circuit modify
PAGE31: HOLE 15,24.25 FBBD3017010 change to FBBD3021010
Circuit modify
PAGE31: HOLE 28.35 FBBL5007010 change to FBBL5050010 , HOLE 13,14 FBBL5008010 change to FBBL5051010

D

C

B

A

PROJECT : BD3G
Quanta Computer Inc.
Size

Document Number

Date:

Thursday, May 29, 2008

Rev
3C

Change List02
5

4

3

2

Sheet
1

41

of

42

5

Model

4

REV DATE
20080218
20080219

BD3G

C3A

20080220
20080222
20080226
20080227
20080229

D

20080303
20080303
20080303
20080303
20080410
20080410
20080410
20080410
20080410
20080410
20080410
20080410
20080416
20080416
20080416
20080416
20080416
20080416

C

20080417
20080418
20080421
20080421

20080424
20080424
20080424
20080424
20080424
20080424
20080505

B

20080505
20080505
20080505
20080505
20080505
20080505
20080507
20080508
20080508
20080508
20080509
20080513
20080527
20080527

20080527

A

20080527
20080528
20080529

3

2

1

NOTE

CHANGE LIST

PAGE04: G781 reverse R718 0 ohm for Griffin CPU
PAGE04: change G781 to G786P81U
PAGE27:1.change C801,C82 from 0.01u to 4.7n, 2.RX add C811,C812 4.7n
PAGE15:change SATA ODD from port3 to port4 (solve ODD post detect fail)
PAGE27:change ESATA conn usb-2006109-11p,update p/n to DFHS11FR021
update power include EMI
del co-layout parts
RN34,RN35,R608,R607,R572,R569
PAGE14: del Mini card USB10,Felica USB5 , change BT to port5 , ESATA to port 10
PAGE25: MINI PCI II no need USB , change USB10 to ESATA .and del R169,R188
PAGE28: no Felica request , remove USB del R178,R179,remove Q57,C476,R450,Q56
PAGE31: EMI request add C813,C814
PAGE17: change R150 to R152 for power sequence
PAGE26: add D88~D91 for 1394 ESD
PAGE27: change ESATA conn usb-2006109-11p update p/n to DFHS11FR023
PAGE27: add D67,D49,D50 for ESATA USB ESD
PAGE28: add D51,D52, D66 for USB0
PAGE34: add PC191,PC193 for CPU core
PAGE35: del PR81
PAGE27: remove Flash card ckt
PAGE13: change RTC pad location to G1
PAGE14: pull up USB_OC5# R719
PAGE18: update footprint to sv-030018fr004s100fr-4p-h-bl5m
PAGE23: update footpritnt to knob-xre094-3p-bl5m
PAGE28: remove CN42 not co-layout with CN16
PAGE31: update HOLE13,14 footprint to H-C236D146P2
PAGE27: remove D77~D81 for CN34 , change to U44 CM1213-04SO(AL001213001) ,remove D82~D86 for CN32 , change to U45 CM1213-04SO
PAGE28: Change L72 from CX163210007(BT circuit) to CX201290009
PAGE31: remove Hole31,37
no stuff +3VSUS component
PAGE31: no stuff C229,C518,C128
PAGE33: no stuff PQ23
PAGE37: no stuff PR95,PQ20
PAGE16: IDE/FLASH not use ,remove C287,C288,C297,C293,C294
PAGE16: internal clk not use ,remove C332,C330,C327,C331, change L28 to 0 ohm
To meet ESATA SI
PAGE27: change R706 from 0 ohm to 330 , stuff R692,R693,R694
PAGE16: remove C762 to meet PWRGD timing spec
PAGE9: stuff R480,R479 to meet AMD spec
PAGE17: stuff C765 10nf to meet power sequence
PAGE34: intersil recommand to set OCP to 30A
Change PR218 from CS32052FB21 to CS41072FB11,Change PR157 from CS41002FB28 to CS31002FB26,Change PR160 PR216 from
CS31622FB27 to CS23652FB08
PAGE22: Change CN17 from DFHD04MR021 to DFHD04MRA75
PAGE27: update re-driver footprint to tqfn36-5x6-5-37p-0_75h-te1m
PAGE20: reserve R720,R721 for cost down
PAGE27: add C816 0.1u to U44 +5V for ESD , add C818 0.1u to U45 +5V for ESD
PAGE25: remove CN30 second PCIE (HD Decoder)
PAGE31: remove HOLE28,35 (HD Decoder)
PAGE20: stuff D74,D75,D76 for CCD
PAGE20: reserve CM1293 U46,C819 for CCD ESD protect
PAGE28: stuff D68,D69,D70 for FP
PAGE30: stuff D53 for RF_LED ESD
PAGE26: 5/9 for card reader MS DUO adapter short issue
reserve R723,724,722 ,Q82,Q81,Q83,Q84
PAGE4: follow AMD design guide 1.03 stuff R675
PAGE26: some 1394 device can't boot normal
change L38 to BK1608HS220_6
PAGE34: CPU core adj
1.PR160,PR216 change to 3.92K/F_4
2.PR213,PR215 change to 18.2K/F_4
PAGE33: solve system hang up , when plug adp quickly
change PR113 from 150K_4 to 115K/F_4
PAGE33: avoid right side USB voltage drop
change PR119 to 63.4K , PR120 to 10K
PAGE12: del C805,C807
PAGE27: change ESATA conn p/n to DFHS11FR027

Circuit modify
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Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Circuit modify
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Circuit modify
Circuit modify
Circuit modify
Circuit modify
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Circuit modify
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Circuit modify
Circuit modify
Circuit modify

D

C

B

A

PROJECT : BD3G
Quanta Computer Inc.
Size

Document Number

Rev
3C

Change List03
Date:
5

4

3

2

Thursday, May 29, 2008

Sheet
1

42

of

42

www.s-manuals.com



---

Source Exif Data:

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PDF Version                     : 1.6
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39
Create Date                     : 2011:02:13 13:46:15+01:00
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Modify Date                     : 2014:10:16 21:52:14+03:00
Metadata Date                   : 2014:10:16 21:52:14+03:00
Format                          : application/pdf
Creator                         : 
Title                           : Quanta BD3G - Schematics. www.s-manuals.com.
Subject                         : Quanta BD3G - Schematics. www.s-manuals.com.
Producer                        : Acrobat Distiller 5.0 (Windows)
Document ID                     : uuid:72f5e16e-0da4-4c49-9dc2-fc3d1b4ff93e
Instance ID                     : uuid:edbc014a-e01b-44ac-adbf-b7e217c55636
Page Count                      : 43
Keywords                        : Quanta, BD3G, -, Schematics., www.s-manuals.com.

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