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User Manual: Quanta GM3(B) DA0GM3MB8E0 Pacino Intel Discrete & UMA - Schematics. Free.
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1 2 3 4 5 6 7 8 GM3(B) Pacino Intel Discrete & UMA Block Diagram VER : 3A A Screw Hole blank Page PG 45 FAN & THERMAL Merom or Penryn PG 47 SMSC1423 PG 39 AC/BATT CONNECTOR PG 54 SYSTEM RESET CIRCUIT PG 44 BATT CHARGER PG 46 SLG8SP513V (QFN-64) PG 17 PG 3,4 Crestline 1299 uFCBGA PG 5,6,7,8,9,10 SATA-ODD DMI interface PG 36 SATA-HDD PG 36 IHDA USB2.0 AUDIO/AMP Camera + D-MIC PG 41 LPC MINI-CARD WLAN MINI-CARD WWAN MINI-CARD WPAN CIR TSOP36136TR PG 37 ITE8512 18X8 PG 31 SPI D EXPRESS-CARD Biometric PG 38 KBC USER INTERFACE PG 38 RJ45/Magnetics PG 43 PG 42 PG 11,12,13,14 Audio Jacks x3 PG 41 LAN BCM5784M PG 35 PCIEx2 USB2.0 PCIEx1 USB2.0 USB2.0 676 BGA Audio SPK conn PG 40 PG 25 PG 30 C PG 40 USB conn x 3 PCIEx1 USB2.0 ICH8-M STAC9228/92HD73C B SiI1392 PG 18 IHDA PCIEx1 SATA PG 26 PG 27 HDMI CONN. PG 18,19,20,21,22 USB2.0 x 3 SATA PG 50 HDMI 667 MHZ DDR II PG 15,16 VGA Core CRT CONN. PCI EXPRESS GFX GDDR2 x 8 (256M) PG 23, 24 PG 15,16 DDR2-SODIMM2 PG 49 PG 52 VGA ATI M86-M PG 53 667 MHZ DDR II +3.3V_ALW/+5V_ALW/ +15V_ALW REGULATOR +1.8V_SUS/+1.25V_RUN /+0.9V_DDR_VTT PG 51 DC/DC Panel Connector PCIEx16 B DDR2-SODIMM1 CPU VR PG 48 LVDS +3.3V_SUS/+5V_SUS +5V/+3.3V/+1.8V REGULATOR 800 MHz FSB RUN POWER SW A +1.5V_RUN/+1.05V_VCCP (478 Micro-FCPGA) CLOCK POWER POWER Keyboard 33MHz PCI R5C833 PG 37 PS/2 8-in-1 Card Reader PG 28 C PG 34 PG 33 PG 33 1394 CONN. Card Reader CONN. PG 29 PG 30 D FLASH 2Mbyts Touchpad PG 32 QUANTA COMPUTER PG 37 Title Schematic Block Diagram1 1 2 3 4 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 1 8 62 1 2 3 4 5 6 Table of Contents PAGE A Schematic Block Diagram 2 Front Page 3-4 Merom 5-10 Crestline 11-14 ICH8M 15-16 DDRII SO-DIMM(200P) 17 B C Clock Generator 18-24 VGA 25 HDMI 26 LCD connector 27 CRT 28 Card reader PCI interface 29 Card reader & 1394 30 Express card & card reader conn. 31 SIO 32 Flash/RTC 33 WWAN/WPAN 34 WLAN 35 USB port 36 SATA HDD & ODD 37 TP/KB/MB/CIR 38 switch/LED 39 FAN/Thermal 40-41 Audio/CONN. 42-43 Docking Conn/Q-Switch 44 System Reset Circuit 45-46 Screw hole & Charger POWER PLANE VOLTAGE +PWR_SRC 10V~+19V +RTC_CELL +3.0V~+3.3V Blank page 48 1.05VCCP & 1.5VRUN 49 1.8VSUS & 0.9VTT 50 VGA power circuit 51 CPU_ISL6266 (2phase) 52 D/D ISL6237 3.3V/5V 53 RUN Power Switch 54 DCIN,Batt 55 EMI CAP 56 SMBUS BLOCK 57 Power statu & Block diagram PAGE CONTROL SIGNAL DESCRIPTION 4,26,32,34,48,49,50,51,52,55 MAIN POWER 11,14,31,32 RTC 3,13,26,31,32,34,36,37,38,44,46,49,52,53,54 +3.3V_ALW +3.3V +5V_ALW +5V 35,36,46,48,49,52,53,54 +15V_ALW +15V +3.3V_LAN +3.3V +5V_SUS ACTIVE IN S0~S5 S0~S5 8051 POWER ALWON S0~S5 LCD/CHARGE POWER ALWON S0~S5 26,36,37,52,53 LARGE POWER +5V_ALW S0~S5 42,43 LAN POWER AUX_ON +5V 14,38,50,51,53 SLP_S5# CTRLD POWER SUS_ON +3.3V_SUS +3.3V 3,11,12,13,14,20,30,37,38,43,48,49,50,51,53 SLP_S5# CTRLD POWER 3.3V_SUS_ON +1.8V_SUS +1.8V 6,8,9,15,48,49,50,53,55 SODIMM POWER DDR_ON +0.9V_DDR_VTT +0.9V 16,49,53 SODIMM POWER 0.9V_DDR_VTT_ON SLP_S3# CTRLD POWER RUN_ON 14,20,25,27,36,37,38,39,40,41,53 +5V_RUN +5V +3.3V_RUN +3.3V 6,8,9,11,12,13,14,15,17,19,20,22,25,26,27,28, SLP_S3# CTRLD POWER 30,33,34,36,38,39,40,41,42,53,55 +1.8V_RUN +1.8V 19,20,21,22,23,24,25,38,53 SDVO POWER RUN_ON +1.5V_RUN +1.5V 4,9,14,30,33,34,48,,53,55 CALISTOGA/ICH8 POWER 1.5V_RUN_ON +1.25V_RUN +1.25V 6,9,14,49,53 CALISTOGA/ICH8 POWER 1.25V_RUN_ON +1.05V_VCCP +1.05V 3,4,5,6,8,9,11,14,37,48,55 CPU/CALISTOGA/ICH8 POWER 1.05V_RUN_ON 4,51 CPU CORE POWER IMVP_VR_ON +3.3V 26 LCD Power LCDVCC_TST_EN & ENVDD +5V_MOD +5V 36 Module Power MODC_EN# +5V_HDD +5V 36 HDD Power HDDC_EN# +5V_ALW2 +5V 37,38.52,53 LED power source LDO output +0.7V~+1.5V A 3.3V_RUN_ON +LCDVCC +VCC_CORE 47 8 Power States DESCRIPTION 1 7 B C GND PLANE PAGE 8731AGND DESCRIPTION 46 AGND_0.9V 49 AGND_DC/DC 52 AGND_DC2 48 AGND_DDR 49 AGND_ISL6260 51 ALL GND D D QUANTA COMPUTER Title Index & Power Status 1 2 3 4 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 2 8 62 H_A#[3..16] Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 H_A#14 H_A#9 T180PAD H_A#24 T185PAD H_A#17 T184PAD T182 PAD B 5 H_ADSTB#1 A6 A5 C4 A20M# FERR# IGNNE# 11 11 11 11 D5 C6 B4 A3 STPCLK# LINT0 LINT1 SMI# M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10] H_STPCLK# H_INTR H_NMI H_SMI# H5 F21 E1 H_DEFER# 5 H_DRDY# 5 H_DBSY# 5 H_BR0# 5 F1 IERR# INIT# D20 B3 LOCK# RESET# RS[0]# RS[1]# RS[2]# TRDY# C1 F3 F4 G3 G2 HIT# HITM# G6 E4 BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# H_IERR# PROCHOT# THERMDA THERMDC THERMTRIP# R132 56 H_RESET#_L R121 0 Layout Note: Place R421 close to CPU. R116 51 H_RESET# T148T147 PAD PAD H_RESET# 5 5 H_DSTBN#0 5 H_DSTBP#0 5 H_DINV#0 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5 ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# ITP_DBRESET# R134 D21 A24 B25 Layout Note: Place voltage divider within 0.5" of GTLREF pin T165 PAD H_D#28 T152 PAD T156 PAD ITP_DBRESET# 13 H_PROCHOT# H_THERMDA H_THERMDC 5 H_DSTBN#1 5 H_DSTBP#1 5 H_DINV#1 R60 1K/F +1.05V_VCCP PAD T13 H_THERMDA 39 H_THERMDC 39 H_THERM C7 56 R53 2K/F +1.05V_VCCP H CLK A22 A21 CLK_CPU_BCLK 17 CLK_CPU_BCLK# 17 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# V_CPU_GTLREF AD26 CPU_TEST1 C23 CPU_TEST2 D25 CPU_TEST3 C24 CPU_TEST4 AF26 CPU_TEST5 AF1 CPU_TEST6 A26 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 B22 B23 C21 BSEL[0] BSEL[1] BSEL[2] 6,17 CPU_MCH_BSEL0 6,17 CPU_MCH_BSEL1 6,17 CPU_MCH_BSEL2 +1.05V_VCCP 50 +3.3V_ALW R137 1K/F_NC CPU_TEST1 R127 1K/F_NC CPU_TEST2 C54 H_PROCHOT# 1 R693 2.2K_NC 3 CPU_PROCHOT# +1.05V_VCCP +3.3V_RUN R600 22.6/F_NC 12 ITP_TCK D 11 8 9 17 CLK_CPU_ITP# 17 CLK_CPU_ITP R597 R596 27/F ITP_TCK 649/F ITP_TRST# 10 14 16 18 20 22 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 27 28 26 RESET# DBR# DBA# 25 24 ITP_DBRESET# 23 21 19 17 15 13 4 6 29 30 ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5 R602 H_D#57 H_DSTBN#2 5 H_DSTBP#2 5 H_DINV#2 5 H_D#[0..63] 5 H_DSTBN#3 5 H_DSTBP#3 5 H_DINV#3 5 B Note: H_DPRTSTP need to daisy chain from ICH8 to IMVP6 to CPU. H_DPRSTP# 6,11,51 H_DPSLP# 11 H_DPWR# 5 H_PWRGOOD 11 H_CPUSLP# 5 H_PSI# 51 CPU_TEST3 CPU_TEST5 FSB BCLK 533 133 667 800 BSEL2 BSEL1 BSEL0 0 0 1 166 0 1 1 200 0 1 0 C COMP0 COMP1 COMP2 COMP3 Q29 2N7002W-7-F C976 0.1U 10 R62 54.9/F Signal BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# NC0 NC1 GND_0 GND_1 Layout nopte: Place R412,R354, R408, R409, R350 and R406 close to CPU R59 27.4/F R78 54.9/F R87 27.4/F Comp0,2 connect with Zo=27.4ohm,Comp1,3 connect with Zo=55ohm, make those traces length shorter than 0.5".Trace should be at least 25 mils away from any other toggling signal. ITP disable guidelines 2 H_D#53 PAD T173 T168 PAD A 150 FBO GND0 GND1 GND2 GND3 GND4 GND5 PAD T172 1 Q81 MMST3904-7-F VTT0 VTT1 VTAP BCLKN BCLKP H_D#40 1 C674 0.1U_NC 10 TDI TMS TCK TDO TRST# 2 2 H_THERM 2 3 R130 10M +3.3V_SUS C673 0.1U_NC 10 Resistor Value Connect To Resistor Placement TDI 150 ohm +/- 5% VTT Within 2.0" of the ITP TMS 39 ohm +/- 5% VTT Within 2.0" of the ITP TRST# 680 ohm +/- 5% GND Within 2.0" of the ITP TCK 27 ohm +/- 5% GND Within 2.0" of the ITP TDO Open VTT Within 2.0" of the ITP D QUANTA COMPUTER Title Merom Processor (HOST BUS) ITP700Flex_NC 1 COMP0 COMP1 COMP2 COMP3 PAD T169 H_THERMTRIP# 6,52 32 +1.05V_VCCP 1 R594 150 JITP1 H_RESET# COMP[2] COMP[3] R26 U26 AA1 Y1 COMP[0] 5 H_D#32 1 Layout Note: Place couple 0.1uF Decoupling caps with in 0.1" ITP connector. 0_NC H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_D#[0..63] For the purpose of testability, route these signals through a ground referenced Z0 = 55ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection. Populate ITP700Flex for bringup R598 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 PAD T14 PAD T3 0.1U_NC CPU_TEST4 10 0_NC CPU_TEST6 R138 C 1 2 5 7 3 D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# MISC COMP[1] Place C close to the CPU_TEST4 pin. Make sure CPU_TEST4 routing is reference to GND and away from other noisy signal. 2N7002W-7-F_NC ITP_TDI ITP_TMS ITP_TCK ITP_TDO ITP_TRST# H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 Voltage Level shift H_THERMDC MLX_47387-4784 R595 39/F Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 8 MLX_47387-4784 H_THERMDA C777 2200P_NC Q69 R599 51 D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# H_D#[0..63] H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 +1.05V_VCCP 56 H_D#[0..63] E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 H_D#[0..63] 5 H_D#[0..63] H_HIT# 5 H_HITM# 5 R118 BCLK[0] BCLK[1] +1.05V_VCCP H_INIT# 11 H_LOCK# 5 7 U42B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 +1.05V_VCCP H_RS#0 5 H_RS#1 5 H_RS#2 5 H_TRDY# 5 THERMAL ICH 11 H_A20M# 11 H_FERR# 11 H_IGNNE# ADDR GROUP 1 PAD T177 A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# H_ADS# 5 H_BNR# 5 H_BPRI# 5 H4 H_D#[0..63] 5 H_D#[0..63] H1 E2 G5 2 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_A#[17..35] BR0# CONTROL REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# DEFER# DRDY# DBSY# XDP/ITP SIGNALS K3 H2 K2 J3 L1 H_REQ#[0..4] ADS# BNR# BPRI# 6 DATA GRP 1 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 A 5 H_A#[17..35] 5 DATA GRP 0 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# ADDR GROUP 0 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 T176 PAD 5 H_ADSTB#0 5 H_REQ#[0..4] 4 U42A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 RESERVED 5 H_A#[3..16] 3 DATA GRP 2 2 DATA GRP 3 1 ITP_EN 3 4 R268 Depop 5 +3VRUN Size Document Number GM3 Date: Monday, March 24, 2008 Close to CK410M Pin8 6 7 Rev 2B Sheet 3 8 of 62 1 2 3 4 5 +VCC_CORE 6 7 +VCC_CORE U42D U42C +VCC_CORE C78 10U 4 805 A A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 All use 10U 4V(+-20%,X6S,0805)Pb-Free. C81 10U 4 805 C80 10U 4 805 C79 10U 4 805 C732 10U 4 805 C83 10U 4 805 C84 10U 4 805 C85 10U 4 805 C77 10U 4 805 +VCC_CORE C82 10U 4 805 8 inside cavity, north side, secondary layer. +VCC_CORE C144 10U 4 805 C143 10U 4 805 C142 10U 4 805 C141 10U 4 805 C761 10U 4 805 +VCC_CORE B C140 10U 4 805 C139 10U 4 805 C138 10U 4 805 C137 10U 4 805 C136 10U 4 805 8 inside cavity, south side, secondary layer. +VCC_CORE C729 10U 4 805 C728 10U 4 805 C727 10U 4 805 C726 10U 4 805 C731 10U 4 805 C730 10U 4 805 6 inside cavity, north side, primary layer. +VCC_CORE C C755 10U 4 805 C756 10U 4 805 C757 10U 4 805 C758 10U 4 805 C759 10U 4 805 8 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCA[01] VCCA[02] B26 C26 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] AD6 AF5 AE5 AF4 AE3 AF3 AE2 VCCSENSE AF7 +VCCSENSE VSSSENSE AE7 +VSSSENSE A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 +1.05V_VCCP + C96 220U 4 +1.5V_RUN VID0 VID1 VID2 VID3 VID4 VID5 VID6 51 51 51 51 51 51 51 C194 0.01U 25 +VCCSENSE 51 C781 10U 4 Layout Note: Place C105 near PIN B26. +VSSSENSE 51 MLX_47387-4784 C760 10U 4 805 . +VCC_CORE 6 inside cavity, south side, primary layer. R47 100/F +VCCSENSE +VSSSENSE VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] +PWR_SRC A B C MLX_47387-4784 +1.05V_VCCP C91 0.1U 10 P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] C112 0.1U 10 C87 0.1U 10 C127 0.1U 10 C88 0.1U 10 C128 0.1U 10 Layout out: Place these inside socket cavity on North side secondary. + C733 100U 25 + C766 100U 25 + C736 100U_NC 25 + C720 100U_NC 25 Layout Note: Need to add 100uF cap on PWR_SRC for cap singing. Place on PWR_SRC near +VCC_CORE. . R48 100/F Route VCCSENSE and VSSSENSE traces at 27.4ohms and length matched to within 25 mil. Place PU and PD within 2 inch of CPU. D D QUANTA COMPUTER Title Merom Processor (POWER) 1 2 3 4 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 4 8 62 1 2 3 T154 PAD T164 PAD 4 5 6 H_D#3 H_D#12 H_A#[3..35] U45A H_D#[0..63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_D#28 1 +1.05V_VCCP 2 R733 221/F 2 1 H_SWING C805 0.1U/10V 2 1 R732 100/F B 1 1 +1.05V_VCCP R268 54.9/F 2 2 R272 54.9/F H_SCOMP H_SCOMP# 1 H_RCOMP 2 R734 24.9/F Layout Note: H_RCOMP trace should be 10-mil wide with 20-mil spacing. 2 +1.05V_VCCP 3 H_RESET# 3 H_CPUSLP# H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_SWING H_RCOMP B3 C2 H_SWING H_RCOMP H_SCOMP H_SCOMP# R192 0 1 2 W1 W2 H_SCOMP H_SCOMP# B6 E5 H_CPURST# H_CPUSLP# 1 R720 1K/F E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13 B9 A9 H_A#[3..35] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 3 H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7 H_ADS# 3 H_ADSTB#0 3 H_ADSTB#1 3 H_BNR# 3 H_BPRI# 3 H_BR0# 3 H_DEFER# 3 H_DBSY# 3 CLK_MCH_BCLK 17 CLK_MCH_BCLK# 17 H_DPWR# 3 H_DRDY# 3 H_HIT# 3 H_HITM# 3 H_LOCK# 3 H_TRDY# 3 H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 K5 L2 AD13 AE13 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 M7 K3 AD2 AH11 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 3 3 3 3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 L7 K2 AC2 AJ10 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 3 3 3 3 A B H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 M14 E13 A11 H13 B12 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#_0 H_RS#_1 H_RS#_2 E12 D7 D8 H_RS#0 3 H_RS#1 3 H_RS#2 3 3 3 3 3 T149T150 PAD PAD T159T160 PAD PAD C 3 3 3 3 3 H_AVREF H_DVREF CRESTLINE_1p0_DU C807 0.1U/10V 2 R728 2K/F 1 1 H_REF HOST H_D#27 C 8 T155 PAD 3 H_D#[0..63] A 7 2 U45 QCI PN Layout Note: Place the 0.1 uF decoupling capacitor within 100 mils from GMCH pins. D DIS AJSLA5U0T11 D UMA AJSLA5T0T13 QUANTA COMPUTER Title Crestline (HOST) 1 2 3 4 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 5 8 62 1 2 3 4 5 6 POP FOR UMA U45B Santa Rosa Platform MOW WW15 For 4Gb DRAM support, change Pin-BJ29 to DDR_A_MA14, change Pin-BE24 to DDR_B_MA14. 15,16 DDR_A_MA14 15,16 DDR_B_MA14 PM_EXTTS#0 PM_EXTTS#1 10K 10K +1.05V_VCCP R262 56 THERMTRIP_MCH# 3,17 CPU_MCH_BSEL0 3,17 CPU_MCH_BSEL1 3,17 CPU_MCH_BSEL2 PAD T110 PAD T108 4.02K_NC R243 R258 R246 PAD T23 PAD T24 4.02K_NC 4.02K_NC C 13,51 DPRSLPVR G41 L39 PM_EXTTS#0 L36 PM_EXTTS#1 J36 AW49 PLTRST#_R AV20 THERMTRIP_MCH# N20 G36 R227 0 PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2 PAD T112 PAD T114 PAD T116 PAD T120 PAD T117 PAD T121 PAD T118 PAD T115 PAD T113 PAD T111 PAD T106 PAD T100 PAD T101 PAD T102 PAD T107 PAD T119 BE29 AY32 BD39 BG37 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE3_DIMMB DDR_CKE4_DIMMB SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 BG20 BK16 BG16 BE13 DDR_CS0_DIMMA# 15,16 DDR_CS1_DIMMA# 15,16 DDR_CS2_DIMMB# 15,16 DDR_CS3_DIMMB# 15,16 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 BH18 BJ15 BJ14 BE16 M_ODT0 M_ODT1 M_ODT2 M_ODT3 SM_RCOMP SM_RCOMP# BL15 BK14 SMRCOMPP SMRCOMPN SM_RCOMP_VOH SM_RCOMP_VOL BK31 BL31 SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF_0 SM_VREF_1 AR49 AW4 LCTLA_CLK LCTLB_DATA 0 0 2R240 3.3K/F_UMA 1 +1.8V_SUS 26 26 26 26 UMA_LCD_ACLK-_C UMA_LCD_ACLK+_C UMA_LCD_BCLK-_C UMA_LCD_BCLK+_C R321 20/F 26 UMA_LCD_A026 UMA_LCD_A126 UMA_LCD_A2- SMRCOMPP SMRCOMPN 15,16 15,16 15,16 15,16 26 UMA_LCD_A0+ 26 UMA_LCD_A1+ 26 UMA_LCD_A2+ R318 20/F 26 UMA_LCD_B026 UMA_LCD_B126 UMA_LCD_B2- +V_DDR_MCH_REF 26 UMA_LCD_B0+ 26 UMA_LCD_B1+ 26 UMA_LCD_B2+ DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# B42 C42 H48 H47 MCH_DREFCLK_L MCH_DREFCLK#_L R717 DREF_SSCLK_L R716 DREF_SSCLK#_L R241 R230 PEG_CLK PEG_CLK# K44 K45 CLK_MCH_3GPLL 17 CLK_MCH_3GPLL# 17 DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 AN47 AJ38 AN42 AN46 DMI_MRX_ITX_N0 DMI_MRX_ITX_N1 DMI_MRX_ITX_N2 DMI_MRX_ITX_N3 12 12 12 12 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 AM47 AJ39 AN41 AN45 DMI_MRX_ITX_P0 DMI_MRX_ITX_P1 DMI_MRX_ITX_P2 DMI_MRX_ITX_P3 12 12 12 12 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 AJ46 AJ41 AM40 AM44 DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 12 12 12 12 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 AJ47 AJ42 AM39 AM43 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3 12 12 12 12 MCH_DREFCLK 17 MCH_DREFCLK# 17 DREF_SSCLK 17 DREF_SSCLK# 17 0_UMA 0_UMA 0_UMA 0_UMA L_IBG R197 R198 R188 R189 L41 L43 0_UMA N41 N40 UMA_LCD_ACLK- D46 0_UMA UMA_LCD_ACLK+ C45 0_UMA UMA_LCD_BCLK- D44 0_UMA UMA_LCD_BCLK+ E42 0_UMA R173 R195 R177 UMA_LCD_A0-_R 0_UMA UMA_LCD_A1-_R 0_UMA UMA_LCD_A2-_R 0_UMA R174 R196 R178 UMA_LCD_A0+_R G50 0_UMA UMA_LCD_A1+_R E50 0_UMA UMA_LCD_A2+_R F48 0_UMA R201 R176 R200 UMA_LCD_B0-_R 0_UMA UMA_LCD_B1-_R 0_UMA UMA_LCD_B2-_R 0_UMA R202 R175 R199 UMA_LCD_B0+_R E44 0_UMA UMA_LCD_B1+_R A47 0_UMA UMA_LCD_B2+_R A45 0_UMA PAD T22 15,16 15,16 15,16 15,16 R248 R269 R284 R286 17 0_DU 0_DU 0_DU R290 1K/F C344 0.1U 27 UMA_VGA_BLU 27 UMA_VGA_GRN 27 UMA_VGA_RED 27 UMA_CRT_CLK_DDC 27 UMA_CRT_DAT_DDC 27 UMA_VGAHSYNC R261 0_NC THERMTRIP_MCH# 3,52 H_THERMTRIP# G51 E51 F49 G44 B47 B45 LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 +1.25V_RUN Non-iAMT 27 UMA_VGAVSYNC PM 13 PM_BMBUSY# 3,11,51 H_DPRSTP# 15 PM_EXTTS#0 15 PM_EXTTS#1 13,44 ICH_PWRGD SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4 R213 R187 26 UMA_LCD_DDCCLK 26 UMA_LCD_DDCDAT 26 UMA_ENVDD L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN TVA_DAC TVB_DAC TVC_DAC F27 J27 L27 TVA_RTN TVB_RTN TVC_RTN M35 P33 TV_DCONSEL_0 H32 G32 K29 J29 F29 E29 CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# K33 G35 F33 C32 E33 CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC TV_DCONSEL_1 R269, R284 and R286 DIS: 0 -->CS00002JB38 UMA: 75 -->CS07502FB17 R282 392/F R153 0_UMA UMA_VGA_BLU_R R152 0_UMA UMA_VGA_GRN_R R154 0_UMA UMA_VGA_RED_R UMA_CRT_CLK_DDC_R 0_UMA UMA_CRT_DAT_DDC_R 0_UMA 230/F_UMAUMA_VGAHSYNC_R 1.3K_UMA CRT_TVO_IREF 230/F_UMAUMA_VGAVSYNC_R R149 R150 R155 1 R222 R1511 E27 G27 K27 POP FOR UMA VGA PAD T26 PAD T19 PAD T16 4.02K_NC R214 PAD T27 PAD T21 PAD T20 PAD T18 PAD T15 PAD T25 4.02K_NC R255 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 CFG +3.3V_RUN P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 M_CLK_DDR#0 15 M_CLK_DDR#1 15 M_CLK_DDR#3 15 M_CLK_DDR#4 15 R144 R145 R181 MCH_CLVREF Layout Note: Location of all MCH_CFG strap resistors needs to be close to minmize stub. DMI R253 R247 AW30 BA23 AW25 AW23 0_UMA UMA_BIA_PWM_RJ40 0_UMA PANEL_BKEN_R H39 LCTLA_CLK E39 LCTLB_DATA E40 0_UMA LCD_DDCCLK_R C37 0_UMA LCD_DDCDAT_R D35 0_UMA ENVDD_R K40 R139 R226 26 UMA_BIA_PWM 31 UMA_PANEL_BKEN LCD_DDCCLK_R LCD_DDCDAT_R R159 2.2K_UMA R160 2.2K_UMA POP FOR UMA GRAPHICS VID +3.3V_RUN UMA_LCD_A3-_R UMA_LCD_A3+_R UMA_LCD_B3-_R UMA_LCD_B3+_R SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4 15 15 15 15 TV B 0_UMA 0_UMA 0_UMA 0_UMA ME 26 UMA_LCD_A326 UMA_LCD_A3+ 26 UMA_LCD_B326 UMA_LCD_B3+ R208 R215 R179 R180 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 RSVD H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BJ29 BE24 BH39 AW20 BK20 C48 D47 B44 C44 A35 B37 B36 B34 C34 CLK R322 1K/F MISC C412 2.2U 10 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR3 M_CLK_DDR4 LVDS C399 0.01U 25 AV29 BB23 BA25 AV23 GRAPHICS SM_RCOMP_VOL POP FOR UMA SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4 PCI-EXPRESS R319 3.01K A MUXING SM_RCOMP_VOH RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 DDR P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20 R323 1K/F C390 2.2U 10 8 +VCC_PEG +VCC3G_PCIE_R 12,25,30,33,34,42 PLTRST# R292 0_NC R291 0 N43 M43 PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PCIE_MRX_GTX_N0 J51 R238 L51 PCIE_MRX_GTX_N1_L PCIE_MRX_GTX_N2 N47 PCIE_MRX_GTX_N3 T45 PCIE_MRX_GTX_N4 T50 PCIE_MRX_GTX_N5 U40 PCIE_MRX_GTX_N6 Y44 PCIE_MRX_GTX_N7 Y40 AB51 PCIE_MRX_GTX_N8 PCIE_MRX_GTX_N9 W49 AD44 PCIE_MRX_GTX_N10 AD40 PCIE_MRX_GTX_N11 AG46 PCIE_MRX_GTX_N12 AH49 PCIE_MRX_GTX_N13 AG45 PCIE_MRX_GTX_N14 AG41 PCIE_MRX_GTX_N15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PCIE_MRX_GTX_P0 J50 R245 L50 PCIE_MRX_GTX_P1_L PCIE_MRX_GTX_P2 M47 PCIE_MRX_GTX_P3 U44 PCIE_MRX_GTX_P4 T49 PCIE_MRX_GTX_P5 T41 PCIE_MRX_GTX_P6 W45 PCIE_MRX_GTX_P7 W41 AB50 PCIE_MRX_GTX_P8 PCIE_MRX_GTX_P9 Y48 AC45 PCIE_MRX_GTX_P10 AC41 PCIE_MRX_GTX_P11 AH47 PCIE_MRX_GTX_P12 AG49 PCIE_MRX_GTX_P13 AH45 PCIE_MRX_GTX_P14 AG42 PCIE_MRX_GTX_P15 PCIE_MRX_GTX_N[0..15] 18 PCIE_MRX_GTX_N1 0_DIS A PCIE_MRX_GTX_P[0..15] 18 PCIE_MRX_GTX_P1 0_DIS PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44 PCIE_MTX_GRX_C_N0 PCIE_MTX_GRX_C_N1 PCIE_MTX_GRX_C_N2 PCIE_MTX_GRX_C_N3 PCIE_MTX_GRX_C_N4 PCIE_MTX_GRX_C_N5 PCIE_MTX_GRX_C_N6 PCIE_MTX_GRX_C_N7 PCIE_MTX_GRX_C_N8 PCIE_MTX_GRX_C_N9 PCIE_MTX_GRX_C_N10 PCIE_MTX_GRX_C_N11 PCIE_MTX_GRX_C_N12 PCIE_MTX_GRX_C_N13 PCIE_MTX_GRX_C_N14 PCIE_MTX_GRX_C_N15 C817 C813 C821 C819 C830 C825 C831 C833 C837 C838 C840 C841 C847 C848 C852 C851 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43 PCIE_MTX_GRX_C_P0 PCIE_MTX_GRX_C_P1 PCIE_MTX_GRX_C_P2 PCIE_MTX_GRX_C_P3 PCIE_MTX_GRX_C_P4 PCIE_MTX_GRX_C_P5 PCIE_MTX_GRX_C_P6 PCIE_MTX_GRX_C_P7 PCIE_MTX_GRX_C_P8 PCIE_MTX_GRX_C_P9 PCIE_MTX_GRX_C_P10 PCIE_MTX_GRX_C_P11 PCIE_MTX_GRX_C_P12 PCIE_MTX_GRX_C_P13 PCIE_MTX_GRX_C_P14 PCIE_MTX_GRX_C_P15 C814 C816 C824 C822 C826 C827 C832 C836 C835 C839 C842 C843 C844 C846 C850 C849 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS 0.1U_DIS PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15 CRESTLINE_1p0_DU GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VR_EN E35 A39 C38 B39 E36 CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF AM49 AK50 AT43 AN49 AM50 SDVO_CTRL_CLK SDVO_CTRL_DATA CLK_REQ# ICH_SYNC# TEST_1 TEST_2 T17 T104 T103 T105 T109 PAD PAD PAD PAD PAD R239 R249 R228 0_DU 0_DU 0_DU UMA_VGA_BLU_R UMA_VGA_GRN_R UMA_VGA_RED_R UMA USE RESISTOR 150/F PN:CS11502FB21 DIS USE 0 OHM PN:CS00002JB38 CL_CLK0 13 CL_DATA0 13 ICH_CL_PWROK 13,31 ICH_CL_RST0# 13 MCH_CLVREF R158 R161 R167 R168 R244 R225 R229 R724 R723 R242 R231 0_DIS 0_DIS 0_DIS 0_DIS 0_DIS 0_DIS 0_DIS 0_DIS 0_DIS 0_DIS 0_DIS SDVO_CTRLCLK_L SDVO_CTRLDATA_L POP FOR DIS A37 R32 0_UMA 0_UMA R742 0_UMA PCIE_MRX_GTX_P1_L R743 0_UMA PCIE_MTX_GRX_C_N0 PCIE_MTX_GRX_C_N1 PCIE_MTX_GRX_C_N2 PCIE_MTX_GRX_C_N3 C247 C238 C254 C253 0.1U_UMA 0.1U_UMA 0.1U_UMA 0.1U_UMA PCIE_MTX_GRX_C_P0 PCIE_MTX_GRX_C_P1 PCIE_MTX_GRX_C_P2 PCIE_MTX_GRX_C_P3 C240 C246 C261 C255 0.1U_UMA 0.1U_UMA 0.1U_UMA 0.1U_UMA C SDVO_CTRLCLK 25 SDVO_CTRLDATA 25 SDVOB_INT- 25 SDVOB_INT+ 25 SDVOB_RED- 25 SDVOB_GREEN- 25 SDVOB_BLUE- 25 SDVOB_CLK- 25 SDVOB_RED+ 25 SDVOB_GREEN+ 25 SDVOB_BLUE+ 25 SDVOB_CLK+ 25 DC Blocked Cap. AND POP FOR UMA PLTRST#_R 100 CFG5 D CFG16 CFG19 CFG20 Low=DMIx2 DMI X2 Select High=DMIx4(Default) Low= Reveise Lane PCI Express Graphic Lane High=Normal operation FSB Dynamic Low=Dynamic ODT Disable ODT High=Dynamic ODT Enable(default). Low=Normal(default). DMI Lane Reversal High=Lane Reversed Low=Only SDVO or PCIEx1 is SDVO/PCIE operational (defaults) Concurrent High=SDVO and PCIEx1 are operating Operation simultaneously via PEG port D Title 4 5 6 QUANTA COMPUTER Crestline (VGA,DMI) Low=No SDVO Device Present (default) SDVO_CRTL_DATA SDVO Present. High=SDVO Device Present 3 R143 R142 PCIE_MRX_GTX_N1_L R209 0 CFG9 2 B POP FOR DIS LCD_DDCCLK_R LCD_DDCDAT_R UMA_CRT_CLK_DDC_R UMA_CRT_DAT_DDC_R UMA_VGAHSYNC_R CRT_TVO_IREF UMA_VGAVSYNC_R MCH_DREFCLK_L MCH_DREFCLK#_L DREF_SSCLK_L DREF_SSCLK#_L Layout Note: Place 150 ohm termination resistors close to GMCH. 0_DIS H35 SDVO_CTRLCLK_L R157 0_DIS K36 SDVO_CTRLDATA_LR156 G39 CLK_3GPLLREQ# 17 G40 MCH_ICH_SYNC# 13 R260 20K R296 R251 24.9/F PEG_COMPI PEG_COMPO CRESTLINE_1p0_DU 12 SB_NB_PCIE_RST# 1 PCIE_MTX_GRX_N[0..15] 18 PCIE_MTX_GRX_P[0..15] 18 +3.3V_RUN +1.8V_SUS C377 0.01U 25 7 U45C 7 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 8 6 of 62 3 15 DDR_A_D[0..63] C 15 DDR_B_D[0..63] A MEMORY SYSTEM SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 DDR B AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11 SA_BS_0 SA_BS_1 SA_BS_2 BB19 BK19 BF29 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 SA_CAS# BL17 DDR_A_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 SA_RAS# SA_RCVEN# BE18 AY20 DDR_A_RAS# SA_WE# BA19 8 U45E DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDR_A_BS0 15,16 DDR_A_BS1 15,16 DDR_A_BS2 15,16 DDR_A_CAS# 15,16 DDR_A_DM[0..7] 15 DDR_A_DQS[0..7] DDR_A_DQS#[0..7] DDR_A_MA[0..13] T29 DDR_A_WE# 7 T195 PAD T196 PAD U45D DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 A T203 T188 T190 T192 6 15 15 15,16 DDR_A_RAS# 15,16 PAD DDR_A_WE# 15,16 CRESTLINE_1p0_DU AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 B PAD PAD PAD PAD 5 T201 PAD T200 PAD MEMORY PAD T206 PAD T208 PAD T202 4 DDR_A_D63 DDR_A_D34 DDR_A_D4 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_MA13 DDR_A_MA1 DDR_A_CAS# DDR_A_RAS# DDR_A_WE# SYSTEM 2 DDR 1 SB_BS_0 SB_BS_1 SB_BS_2 AY17 BG18 BG36 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 SB_CAS# BE17 DDR_B_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 SB_RAS# SB_RCVEN# AV16 AY18 DDR_B_RAS# SB_WE# BC17 DDR_B_WE# DDR_B_BS0 15,16 DDR_B_BS1 15,16 DDR_B_BS2 15,16 A DDR_B_CAS# 15,16 DDR_B_DM[0..7] 15 DDR_B_DQS[0..7] 15 DDR_B_DQS#[0..7] 15 DDR_B_MA[0..13] T28 B 15,16 DDR_B_RAS# 15,16 PAD DDR_B_WE# 15,16 C CRESTLINE_1p0_DU D D QUANTA COMPUTER Title Crestline (DDR2) 1 2 3 4 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 7 8 62 5 4 3 2 1 +3.3V_RUN + C820 220U_UMA 2.5 7343 + C834 220U_NC 2.5 7343 + C279 220U_NC 2.5 7343 (3) +1.05V_VCCP Layout Note: Inside GMCH cavity for VCC_AXM. 2 0_0805_UMA C314 0.47U_UMA 603 10 C330 1U_UMA 603 10 C291 10U_UMA 805 6.3 C857 22U_UMA 805 4 Layout Note: Inside GMCH cavity. 2 1 1 +1.05V_VCCP C337 0.1U/10V 1 C308 0.1U_UMA C331 0.1U/10V C320 0.1U/10V 2 C297 0.1U_UMA UMA POP POWER JUMP AND ALL CAP 2 R64 1 1 C318 0.22U/10V C339 0.22U/10V 2 C345 22U/4V 2 2 1 R171 0_0805_DIS 1 R65 0_0805_DIS 1 2 2 Non-iAMT (3) AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33 Layout Note: Place close to GMCH edge. VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6 A3 B2 C1 BL1 BL51 A51 C VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7 AT33 AT31 AK29 AK24 AK23 AJ26 AJ23 B CRESTLINE_1p0_DU 1 1 C372 0.47U/10V C365 1U/10V 2 C367 0.22U/10V 2 1 1 C371 0.22U/10V 2 C362 0.1U/10V 2 C355 0.1U/10V 1 1 C363 1U/10V C438 330U/2.5V Layout Note: Place C233 where LVDS and DDR2 taps. 1 C415 22U/4V 2 + C430 0.1U/10V 2 2 1 VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7 1 1 VCC_SM C422 22U/4V Layout Note: Place on the edge. A Title CRESTLINE_1p0_DU 1 VSS NCTF VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19 R182 0_0805_DIS (3) D +1.05V_VCCP +1.8V_SUS AW45 BC39 BE39 BD17 BD4 AW8 AT6 T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28 POWER VSS SCB +1.05V_VCCP VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VCC AXM 1 C333 0.1U/10V 2 1 2 C300 0.22U/10V 2 1 1 2 C294 0.22U/10V Layout Note: 370 mils from edge. + C263 220U_UMA 2.5 7343 UMA POP POWER JUMP AND C234 &C233 C307 22U/4V VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50 VCC NCTF 2 0_0805_UMA + C829 220U AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37 VCC AXM NCTF 2 2 A VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7 R63 1 2 1 R185 0_0805_UMA VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 D6 1 +VCC_GMCH_L Layout Note: Inside GMCH cavity. Layout Note: 370 mils from edge. 2 2 +1.05V_VCCP R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14 +1.05V_VCCP 1 B VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 VCC GFX NCTF C AU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30 VCC SM POWER +1.8V_SUS 10 2 SDMK0340L-7-F 1 VCC_13 T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31 2 R30 VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83 VCC SM LF VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 U45F R170 1 VCC CORE AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32 VCC GFX D U45G 2 +1.05V_VCCP QUANTA COMPUTER Crestline (VCC,NCTF) 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 8 of 62 3 AN2 VCCD_HPLL U48 VCCD_PEG_PLL 1 2 J41 H42 C293 0.1U 10V 1 2 C295 0.1U 10V UMA POP C493 & RESISTOR 0_UMA 1 R140 2 R841 +1.8V_SUS 2 0_UMA +VCCD_LVDS 1 VCCD_LVDS_1 VCCD_LVDS_2 2 1 1 2 1 1 2 1 1 2 2 VCC_HV_1 VCC_HV_2 C40 B40 Place 0 ohm close to +1.8V_SUS +1.8V_SUS 0_UMA 1 R730 2 +VCC_TX_LVDS_L 1uH+-20%_300mA +VCC_TX_LVDS 2 1 VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5 AD51 W50 W51 V49 V50 VCC_RXR_DMI_1 VCC_RXR_DMI_2 AH50 AH51 C259 0.1U/10V 10V +VCC_PEG L76 1uH/300MA_UMA 805 + C818 C803 220U_UMA 1000P_UMA 7343 50 2.5 VTTLF1 VTTLF2 VTTLF3 A7 F2 AH1 R842 +VCC_TX_LVDS_R 2 0_UMA 1 C UMA POP ALL L39 2 91uH+-20%_1.5A 91nH/1.5A 1 +1.05V_VCCP +VCC_RXR_DMI + C353 220U/4V C289 10U/6.3V +1.05V_VCCP +VTTLF1 +VTTLF2 +VTTLF3 91uH+-20%_1.5A 2V 6.3 L40 2 91nH/1.5A 1 + C354 220U/4V C853 10U/6.3V +VTTLF1 +VTTLF2 +VTTLF3 C316 0.47U/10V C267 0.47U/10V C804 0.47U/10V L49 1uH/300mA 2 +VCC_SM_CK 1 2 C405 22U/10V +1.8V_SUS 1 1uH+-20%_300mA B R314 1/F/0603 C376 0.1U/10V 2 1 C366 1U 603 10 2 1 C423 1U 603 10 2 1 C427 22U 805 10 2 1 2 Non-iAMT 1 2 C328 0.1U 10V +1.25V_RUN C801 1000P_UMA 50 1 1 1 A43 2 +VCC_TX_LVDS_L VCC_TX_LVDS +VCC_SM_CK 1 layout note: close to pin A41 B BK24 BK23 BJ24 BJ23 CRESTLINE_1p0_DU C189 10U_NC 603 6.3 C190 1U_UMA 603 10 VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4 C252 10U/6.3V Place caps close to B23, B21, A21 +1.25V_RUN +3.3V_RUN 1 C361 10U 603 6.3 C341 0.1U 10V +VCCD_LVDS_R R299 1/F 603 AJ50 1 2 1 1 +VCCA_PEG_PLL Non-iAMT VCC_DMI C251 1U/10V 1 VCCD_QDAC +1.25V_RUN B23 B21 A21 2 VCCD_CRT VCCD_TVDAC N28 1 Place caps close to VCC_AXD. 1 M32 L29 +VCCQ_TVDAC_RR +1.25V_RUN +VCCA_PEG_PLL A LVDS +VCCD_CRT_R +VCCD_TVDAC_RR Reserved L pad for 1 20_UMA VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2 L52 C442 inductor. 22U/10V 2 1 R704 VCCA_SM_CK_1 VCCA_SM_CK_2 C360 1U/10V 2 +VCC_TVDACC_RR POWER +3.3V_RUN 22 0 1 +VCC_TVDACB_RR AR29 1 2 1 (1) +1.25V_RUN 1 2 C25 B25 C27 B27 B28 A28 +VCC_TVDACA_RR +VCCD_CRT_R 2 BC29 BB29 +1.25V_RUN DIS POP ALL FB_220ohm+-25%_100MHz _2A_0.1ohm DC VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_NCTF_1 VCCA_SM_NCTF_2 1 +VCCD_LVDS_R +VCCQ_TVDAC_RR +VCCD_CRT_R +VCC_TVDACC_RR +VCC_TVDACB_RR +VCC_TVDACA_RR +VCC_TX_LVDS_L +VCCA_DPLLA +VCCA_DPLLB +VCCA_DAC_BG +VCCA_CRT_DAC +VCCSYNC L38 1 2 BLM21PG221SN1D 805 C347 1U 603 10 AT22 AT21 AT19 AT18 AT17 AR17 AR16 VCC_AXD_NCTF VCC_AXF_1 VCC_AXF_2 VCC_AXF_3 NoniAMT +1.25V_RUN +1.25V_RUN +VCC_AXD_L 2 2 C429 22U 805 10 2 1 1 C418 22U 805 10 2 1 C346 4.7U 805 6.3 VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 + C299 220U/4V 7343 1 0_DIS 0_DIS 0_DIS 0_DIS 0_DIS 0_DIS 0_DIS 0_DIS 0_DIS 0_DIS 0_DIS 0_DIS + C435 100U 7343 2V 2 C R232 R736 R711 R169 R206 R186 R210 R731 R172 R211 R224 R725 2 Non-iAMT 2 1 +1.25V_RUN VCCA_PEG_PLL C290 4.7U 603 6.3 1 U51 AW18 AV19 AU19 AU18 AU17 VTTLF +VCCA_PEG_PLL 2 C274 0.1U 10V HV 1 C236 C243 0.1U_UMA 470U/ESR9_UMA 10 7343 2.5V 1 C352 0.1U 10V + VSSA_PEG_BG VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5 VCC_AXD_6 A CK 0.1Caps should be placed 200 mils with in its pins. 1 +VCCA_DPLLB 10uH/100MA_UMA VCCA_PEG_BG A PEG K49 A SM K50 R184 10_NC Place on the edge. AT23 AU28 AU24 AT29 AT25 AT30 TV C858 22U 1206 10V VSSA_LVDS L15 1 2 1 1 R294 2 0.5/F 603 +VCCA_MPLL_L VCCA_LVDS B41 +3.3V_RUN D TV/CRT C342 0.1U/10V 2 2 C856 22U/10V 1206 +VCC_TX_LVDS_LA41 LVDS 1 1 2 +VCCA_DPLLA 10uH/100MA_UMA 805 C191 + C188 0.1U_UMA 470U/ESR9_UMA 10 7343 2.5V +VCC_HV_L D C296 0.47U/6.3V 2 VCCA_MPLL L13 D8 SDMK0340L-7-F_NC C281 4.7U/6.3V 1 AM2 +VCCA_MPLL 10uH+-20%_100mA +VCCA_HPLL 1 BLM18AG121SN1D 603 L33 BLM18AG121SN1D 603 2 1 +VCCA_MPLL 10V 10V 2 UMA POP ALL 40mA MAx. +1.25V_RUN L30 2 AXD +1.25V_RUN 2 VCCA_HPLL +1.05V_VCCP Place on the edge. 1 VCCA_DPLLB AL2 +VCCA_HPLL FB_120ohm+-25%_100mHz _200mA_0.2ohm DC AXF Non-iAMT 45mA MAx. VCC_HV +1.05V_VCCP 2 VCCA_DPLLA H49 C292 2.2U/6.3V 1 B49 +VCCA_DPLLB U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1 2 +VCCA_DPLLA VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 2 VSSA_DAC_BG VTT VCCA_DAC_BG B32 UMA POP ALL BESIDES C462 D VCCA_CRT_DAC_1 VCCA_CRT_DAC_2 +VCCA_DAC_BG A30 SM CK +VCCA_CRT_DAC 0.1U_UMA 10V C802 C239 22nF/3P_NC VCCSYNC A33 B33 PEG 2 C249 0.1U_UMA 10 1 +1.05V_VCCP J32 DMI R204 3 U45H +VCCSYNC 2 L19 0_UMA 1 R722 2 +VCCA_CRT_DAC 0_0402_UMA 1 CRT +3.3V_RUN +VCCA_CRTDAC BLM18PG181SN1D_UMA 603 2 UMA POP ALL FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC 2 2 4 +3.3V_RUN PLL 5 C394 0.1U 10V +VCC_SM_CK_L C374 10U/6.3V layout shound close to BB29 & BC29 FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC 0_DIS 1 R162 UMA POP ALL BESIDES C466, C467, C463, C454, R441 & D33 C258 22nF/3P_NC 2 +VCCD_TVDAC_RR 1 1 C792 0.1U_DIS 10V 2 C256 0.1U_UMA 10 C779 10U_DIS 603 6.3 2 C241 10U_UMA 805 6.3 +1.5V_RUN 1 +VCC_TVDACA_RR 0_0402_UMA 1 R223 3 2 22nF & 0.1uF for VCC_TVDACA:C_R should be placed with in 250 mils from Crestline. +VCC_TVDAC 2 L16 BLM18PG181SN1D_UMA 603 +3.3V_RUN C780 0.022U_DIS 16 603 DIS POP ALL +VCC_TVBG R729 0.03/F_UMA 2010 C794 C796 22nF/3P_NC 0.1U_UMA 10 0_UMA 1 2 A +VCC_TVDACB_RR R712 3 C795 0.1U_UMA 10 0_UMA 1 +1.5V_RUN C793 22nF/3P_NC UMA POP ALL BESIDES C498 & C 506 A +VCCD_CRT_R C790 0.1U_UMA 10 +3.3V_RUN R707 3 0_0402_UMA 1 2 R710 3 2 +VCCA_DAC_BG +VCCQ_TVDAC_RR C791 22nF/3P_NC +VCC_TVDACC_RR +VCC_TVDAC_L R697 SDMK0340L-7-F_NC 1 10_NC TV DAC Voltage Follower Circuit -700 mV. 5 C250 0.1U_UMA 10 0_UMA 1 2 R191 3 D28 2 L77 C237 22nF/3P_NC +VCCQ_TVDAC BLM18PG181SN1D_UMA R727 0_0402_UMA 3 1 C806 FB_180ohm+-25%_0.1U/10V/0402_UMA C799 100mHz_1500mA_ 22nF/3P_NC 0.09ohm DC Title 4 3 QUANTA COMPUTER Crestline (POWER) 2 +1.5V_RUN 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 9 of 62 5 4 3 2 U45I A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16 D C B A VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 1 U45J VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41 C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50 D C VSS B CRESTLINE_1p0_DU A CRESTLINE_1p0_DU Title QUANTA COMPUTER Crestline (VSS) 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 10 of 62 2 3 4 1 2 3 1 R532 332K/F A R528 0_NC 2 2 2 2 2 2 2 33_UMA 33 33_UMA 33 33_UMA 33 ACZ_SYNC ACZ_RST# Place all series terms close to ICH8 except for SDIN input lines,which should be close to source.Placement of R603, R600, R607 & R612 should equal distance to the T split trace point as R604, R599, R606 & R608 respective. Basically,keep the same distance from T for all series termination resistors. 40 ICH_AZ_CODEC_SDIN0 25 ICH_AZ_HDMI_SDIN1 PAD T133 PAD T63 ACZ_SDOUT R472 2 R507 2 +3.3V_SUS 36 SATA_TX036 SATA_TX0+ 36 SATA_TX136 SATA_TX1+ 36 SATA_TX236 SATA_TX2+ C553 C554 C900 C898 2 2 25 25 2 2 1 3900P 1 3900P SATA_TX0-_C SATA_TX0+_C 1 3900P 1 3900P SATA_TX1-_C SATA_TX1+_C 25 25 C535 C536 1 3900P 1 3900P 2 2 Master HDD 36 SATA_RX036 SATA_RX0+ SATA ODD 36 SATA_RX136 SATA_RX1+ Second HDD 36 SATA_RX236 SATA_RX2+ SATA_TX2-_C SATA_TX2+_C 25 25 Distance between the ICH-8 M and cap on the "P" signal should be identical distance between the ICH-8 M and cap on the "N" signal for same pair. LAN_TXD0 LAN_TXD1 LAN_TXD2 D25 C25 GLAN_COMPI GLAN_COMPO AJ16 AJ15 HDA_BIT_CLK HDA_SYNC AE14 HDA_RST# AJ17 AH17 AH15 AD13 HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 AE13 HDA_SDOUT SATALED# SATA_TX0-_C SATA_TX0+_C AF6 AF5 AH5 AH6 SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA_TX1-_C SATA_TX1+_C AG3 AG4 AJ4 AJ3 SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA_TX2-_C SATA_TX2+_C AF2 AF1 AE4 AE3 SATA2RXN SATA2RXP SATA2TXN SATA2TXP AB7 AC6 SATA_CLKN SATA_CLKP R765 24.9/F 2 1 SATABIAS AG1 AG2 DPRSTP# DPSLP# AF26 AE26 H_DPRSTP# H_DPSLP# FERR# AD24 H_FERR# CPUPWRGD/GPIO49 AG29 IGNNE# AF27 H_IGNNE# 3 INIT# INTR RCIN# AE24 AC20 AH14 H_INIT# 3 H_INTR 3 SIO_RCIN# 31 NMI SMI# AD23 AG28 STPCLK# AA24 THRMTRIP# AE27 TP8 AA23 SATARBIAS# SATARBIAS 2 2 1 1 2 1 RTC LPC SIO_A20GATE HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 H_DPRSTP# H_DPSLP# H_FERR# T62 T56 AF13 AG26 A20GATE A20M# GLAN_DOCK#/GPIO13 LPC_LFRAME# 31,33 PAD PAD R542 56 SIO_A20GATE 31 H_A20M# 3 +3.3V_RUN H_DPRSTP# 3,6,51 H_DPSLP# 3 B H_FERR# 3 R501 10K H_PWRGOOD 3 SIO_RCIN# 2 D21 E20 C20 G9 E6 R560 56_NC SIO_A20GATE SIO_RCIN# R502 10K 1 LAN_RXD0 LAN_RXD1 LAN_RXD2 AF10 17 CLK_PCIE_SATA# 17 CLK_PCIE_SATA Place within 500mils of ICH8 ball C21 B21 C22 1 10K_NC AE10 1 10K_NC AG14 38 SATA_ACT# C LAN_RSTSYNC AH21 ACZ_BIT_CLK ACZ_SYNC ACZ_SDOUT GLAN_CLK C4 LDRQ0# LDRQ1#/GPIO23 R561 56_NC 2 PAD PAD PAD PAD B24 D22 FWH4/LFRAME# 31,33 31,33 31,33 31,33 1 LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 R545 24.9/F 1 2 GLAN_COMP +1.5V_PCIE_ICH ACZ_RST# INTVRMEN LAN100_SLP LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 H_NMI 3 H_SMI# 3 +1.05V_VCCP H_STPCLK# 3 2 1 1 1 1 1 1 INTRUDER# ICH_INTVRMEN AF25 ICH_LAN100_SLP AD21 E5 F5 G8 F6 THERMTRIP#_ICH DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 V1 U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6 IDE_D0 IDE_D1 IDE_D2 IDE_D3 IDE_D4 IDE_D5 IDE_D6 IDE_D7 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15 DA0 DA1 DA2 AA4 AA1 AB3 IDE_DA0 IDE_DA1 IDE_DA2 PAD T85 PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD T129 T128 T36 T126 T39 T52 T131 T53 T47 T127 T37 T35 T42 T123 T122 T59 PAD PAD PAD T40 T130 T124 DCS1# DCS3# Y6 Y5 PAD PAD T51 T44 DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ W4 W3 Y2 Y3 Y1 W5 PAD PAD PAD R425 R766 T38 T41 T125 2 2 T45 IDE_IRQ IDE_DIORDY PAD R559 56 1 R516 R517 R503 R504 R496 R481 ICH_AZ_HDMI_SYNC ICH_AZ_CODEC_SYNC ICH_AZ_HDMI_RST# ICH_AZ_CODEC_RST# ICH_AZ_HDMI_SDOUT ICH_AZ_CODEC_SDOUT ICH_INTRUDER# AD22 R533 10K_NC 2 1 +3.3V_SUS 25 40 25 31,40 25 40 RTCRST# FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 CPU C603 27P/50V_NC RTCX1 RTCX2 AF23 IDE 2 C594 27P/50V_UMA 1 2 1 T86 T84 T71 T83 AG25 AF24 ICH_RTCRST# GLAN_CLK Reserved for Intel Nineveh T80 PAD T135 PAD design. ACZ_BIT_CLK ICH_RTCX1 ICH_RTCX2 LAN / GLAN C628 1U/10V 2 33_UMA 2 33 Low = Internal VR Disabled High = Internal VR Enabled(Default) U48A ICH_RTCRST# ICH_INTRUDER# IHDA 1 2 R506 1 R508 1 25 ICH_AZ_HDMI_BITCLK 40 ICH_AZ_CODEC_BITCLK ICH_LAN100_SLP +1.05V_VCCP R538 20K 1 2 ICH_INTVRMEN ICH8M LAN100 SLP Strap (Internal VR for VccLAN1.05 and VccCL1.05) Low = Internal VR Disabled High = Internal VR Enabled(Default) SATA 1 ICH8M Internal VR Enable Strap (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5) T140 PAD B 2 R548 0_NC +RTC_CELL R535 1M ICH_LAN100_SLP 1 1 C944 12P/50V 2 2 2 A 32.768KHZ 8 +RTC_CELL ICH_INTVRMEN 1 1 2 C945 12P/50V 7 R550 332K/F ICH_RTCX2 2 1 6 +RTC_CELL 10M 1 R815 0 W2 ICH_RTCX1 5 2 R816 2 32.768KHZ 4 1 1 THERMTRIP#_ICH C 1 8.2K 1 4.7K +3.3V_RUN IC,ICH8M,BGA676,12-01,rev1p0_2 2 +3.3V_RUN R482 1K_NC XOR Chain Entrance Strap D HDA SDOUT Description 0 RSVD 0 1 Enter XOR Chain 1 0 Normal Operation (Default) 1 1 Set PCIE port config bit 1 1 2 3 4 QUANTA COMPUTER ACZ_SDOUT ICH_RSVD 13 Title R787 1K_NC ICH8-M (CPU,IDE,SATA,LPC,AC97,LAN) 1 0 1 ICH RSVD 2 D 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 11 8 62 4 Place TX DC blocking caps close ICH8. C946 C954 42 PCIE_TX6-/GLAN_TX42 PCIE_TX6+/GLAN_TX+ 0.1U 0.1U PCIE_TXN2_C PCIE_TXP2_C 2 2 0.1U 0.1U PCIE_TXN3_C PCIE_TXP3_C 2 2 0.1U 0.1U PCIE_TXN4_C PCIE_TXP4_C 2 2 0.1U 0.1U GLAN_TXN_C GLAN_TXP_C 10 10 1 1 10 10 1 1 PAD MiniWLAN 10 10 1 1 T241 34 PCIE_RX234 PCIE_RX2+ T243 33 PCIE_RX333 PCIE_RX3+ PAD MiniWPAN T245 30 PCIE_RX430 PCIE_RX4+ PAD Express Card F27 F26 E29 T250 PADE28 T248 PAD D27 D26 GLAN_TXN_C C29 GLAN_TXP_C C28 10 10 T249 T247 42 PCIE_RX6-/GLAN_RX42 PCIE_RX6+/GLAN_RX+ PAD PAD Giga Bit LOM Boot BIOS Strap GNT0# SPI_CS1# No stuff No stuff 10 No stuff Stuff 01 Stuff No stuff 1 2 ICH_SPI_CS1#_R PCI_GNT0# R546 1K_NC LPC 11 PCI SPI PAD PAD T91 T81 PAD PAD ICH_SPI_CS1#_R USB_OC0_1# 35 USB_OC0_1# 2 1 R451 1K_NC T87 T137 54 USB_OC2_3# OC4# OC5# OC6# OC7# USB_OC8# OC9# B 35 USB_OC8# WWAN Noise - ICH improvements OC6# OC4# OC5# OC7# USB_OC8# USB_OC2_3# USB_OC0_1# OC9# C918 C915 C916 C917 C922 C923 C924 C925 1 1 1 1 1 1 1 1 10 10 10 10 10 10 10 10 28 PCI_AD[0..31] C 2 2 2 2 2 2 2 2 Non-iAMT 1 SPI_CLK SPI_CS0# SPI_CS1# D23 F21 SPI_MOSI SPI_MISO OC0# OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8# OC9# 6 7 8 9 10 +3.3V_SUS 5 4 3 2 1 DMI_MTX_IRX_N0 DMI_MTX_IRX_P0 DMI_MRX_ITX_N0 DMI_MRX_ITX_P0 6 6 6 6 DMI1RXN DMI1RXP DMI1TXN DMI1TXP Y27 Y26 W29 W28 DMI_MTX_IRX_N1 DMI_MTX_IRX_P1 DMI_MRX_ITX_N1 DMI_MRX_ITX_P1 6 6 6 6 DMI2RXN DMI2RXP DMI2TXN DMI2TXP AB26 AB25 AA29 AA28 DMI_MTX_IRX_N2 DMI_MTX_IRX_P2 DMI_MRX_ITX_N2 DMI_MRX_ITX_P2 6 6 6 6 DMI3RXN DMI3RXP DMI3TXN DMI3TXP AD27 AD26 AC29 AC28 DMI_MTX_IRX_N3 DMI_MTX_IRX_P3 DMI_MRX_ITX_N3 DMI_MRX_ITX_P3 6 6 6 6 DMI_CLKN DMI_CLKP T26 T25 CLK_PCIE_ICH# 17 CLK_PCIE_ICH 17 DMI_ZCOMP DMI_IRCOMP Y23 Y24 USB USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2 USBRBIAS# USBRBIAS F2 F3 DMI_COMP USB_OC8# USB_OC2_3# USB_OC0_1# OC9# 1 R529 2 24.9/F ICH_USBP0- 35 ICH_USBP0+ 35 ICH_USBP1- 35 ICH_USBP1+ 35 ICH_USBP2- 54 ICH_USBP2+ 54 ICH_USBP3- 54 ICH_USBP3+ 54 ICH_USBP4- 41 ICH_USBP4+ 41 ICH_USBP5- 33 ICH_USBP5+ 33 ICH_USBP6- 33 ICH_USBP6+ 33 ICH_USBP7- 30 ICH_USBP7+ 30 ICH_USBP8- 35 ICH_USBP8+ 35 ICH_USBP9- 38 ICH_USBP9+ 38 A +1.5V_PCIE_ICH Place within 500mils of ICH8 Side pair Top / left Side pair bottom / left Side pair top/right(DB) Side pair Bot right(DB) PCI Pullups Camera Mini Card (WWAN) Mini Card (WPAN) Express Card B left side signal USB port +3.3V_RUN RP42 PCI_FRAME# PCI_STOP# PCI_DEVSEL# PCI_REQ1# Biometric USBRBIAS Short F2 and F3 at the package and keep length to less than 500mils. Trace Impedance should be 60ohms +/- 15%. +3.3V_SUS OC6# OC4# OC5# OC7# V27 V26 U29 U28 PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP RP49 0.1U_NC 0.1U_NC 0.1U_NC 0.1U_NC 0.1U_NC 0.1U_NC 0.1U_NC 0.1U_NC 6 7 8 9 10 +3.3V_RUN 5 4 3 2 1 +3.3V_RUN RP40 PCI_IRDY# PCI_PERR# PCI_PLOCK# PCI_PIRQB# R763 22.6/F 6 7 8 9 10 +3.3V_RUN PCI_TRDY# PCI_PIRQD# PCI_PIRQB# PCI_SERR# 5 4 3 2 1 PCI_PIRQA# ICH_IRQH_GPIO5 PCI_PIRQC# PCI_REQ0# 10KX8 SB_WPAN_PCIE_RST# SB_WWAN_PCIE_RST# SB_WLAN_PCIE_RST# SB_LOM_PCIE_RST# SB_NB_PCIE_RST# U48B PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 D20 E19 D19 A20 D17 A21 A19 C19 A18 B16 A12 E16 A14 G16 A15 B6 C11 A9 D11 B12 C12 D10 C7 F13 E11 E13 E12 D8 A6 E8 D6 A3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# F9 B5 C5 A10 PIRQA# PIRQB# PIRQC# PIRQD# D T55 PAD 28 PCI_PIRQB# 28 PCI_PIRQC# T132 PAD PERN5 PERP5 PETN5 PETP5 C23 B23 E22 AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18 USB_OC2_3# DMI0RXN DMI0RXP DMI0TXN DMI0TXP 2 PCI_REQ0# PCI_GNT0# PCI_REQ1# PCI_GNT1# SB_WWAN_PCIE_RST# PCI_GNT2# SB_LOM_PCIE_RST# PCI_GNT3# REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 A4 D7 E18 C18 B19 F18 A11 C10 C/BE0# C/BE1# C/BE2# C/BE3# C17 E15 F16 E17 IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# C8 D9 G6 D16 A7 B7 F10 C16 C9 A17 PLTRST# PCICLK PME# AG24 PCI_PLTRST# B10 CLK_PCI_ICH G7 PCI Interrupt I/F PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5 F8 G11 F12 B3 3 PCI_REQ0# 28 PCI_GNT0# 28 PAD T65 PAD T75 SB_WWAN_PCIE_RST# 33 PAD T64 SB_LOM_PCIE_RST# 42 PAD T61 PCI_C_BE0# PCI_C_BE1# PCI_C_BE2# PCI_C_BE3# PCI_IRDY# PCI_RST#_G PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME# SB_WPAN_PCIE_RST# SB_WLAN_PCIE_RST# SB_NB_PCIE_RST# ICH_IRQH_GPIO5 Non-iAMT R474 1K_NC SB_NB_PCIE_RST# 2 0.047U 1 1 1 1 1 20K 20K 20K 20K 20K C Add Buffers as needed for Loading and fanout concerns. U47 2 10 A16 away override strap. PCI_DEVSEL# 28 PCI_PERR# 28 PCI_PLOCK# PCI_SERR# 28 PCI_STOP# 28 PCI_TRDY# 28 PCI_FRAME# 28 +3.3V_SUS C887 1 PCI_IRDY# 28 PCI_PAR 28 4 PCI_RST#_G 1 Low = A16 swap override enabled. High = Default. PCI_RST# 28 TC7SZ32FU(T5L,F,T) +3.3V_SUS C958 1 2 CLK_PCI_ICH T210 PAD T213 T215 T217 T219 T221 T223 PAD PAD PAD PAD PAD PAD T225 T229 T234 T228 T231 T235 T237 PAD PAD PAD PAD PAD PAD PAD SB_WPAN_PCIE_RST# 33 SB_WLAN_PCIE_RST# 34 SB_NB_PCIE_RST# 6 PAD T49 4 2 2 2 2 2 PCI_GNT3# 28 28 28 28 CLK_PCI_ICH 17 ICH_PME# 28,31 R468 R791 R467 R477 R495 BIOS should not enable the internal GPIO pull up resistor. 5 C948 C947 30 PCIE_TX430 PCIE_TX4+ 2 2 10 10 MiniWWAN 8 PCI_AD15 PCI_AD2 PCI_AD3 PCI_AD0 PCI_AD2 PCI_AD21 PCI_AD17 PCI_AD16 PCI_IRDY# PCI_TRDY# PCI_FRAME# PCI_STOP# PCI_DEVSEL# PCI_GNT0# PCI_REQ0# 5 PAD T209 PAD PAD PAD PAD PAD PAD T214 T216 T218 T220 T222 T224 PAD PAD PAD PAD PAD PAD PAD T226 T230 T233 T227 T232 T236 T238 0.047U R772 10_NC C907 8.2P_NC 5 C949 C950 33 PCIE_TX333 PCIE_TX3+ PCIE_TXN1_C PCIE_TXP1_C 2 1 1 0.1U 0.1U U50 2 10 2 1 C951 C952 2 2 7 4 PCI_PLTRST# 1 PLTRST# 6,25,30,33,34,42 TC7SZ32FU(T5L,F,T) D 1 A 1 1 U48D P27 PERN1 P26 PERP1 PCIE_TXN1_C N29 PETN1 PCIE_TXP1_C N28 PETP1 T242 PAD M27 PERN2 M26 PERP2 PCIE_TXN2_C L29 PETN2 PCIE_TXP2_C L28 PETP2 T244 PAD K27 PERN3 K26 PERP3 PCIE_TXN3_C J29 PETN3 PCIE_TXP3_C J28 PETP3 T246 PAD H27 PERN4 H26 PERP4 PCIE_TXN4_C G29 PETN4 PCIE_TXP4_C G28 PETP4 33 PCIE_RX133 PCIE_RX1+ 6 1 34 PCIE_TX234 PCIE_TX2+ C953 C955 5 2 33 PCIE_TX133 PCIE_TX1+ PAD PAD 2 T239 T240 1 3 PCI-Express Direct Media Interface 2 SPI 1 Reserved for 16 EMI.Place resister and cap close to ICH. QUANTA COMPUTER Title ICH8-M (USB,DMI,PCIE,PCI) 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 12 8 62 1 2 +3.3V_SUS 3 4 5 6 7 8 Non-iAMT RP50 1 3 ICH_SMBDATA ICH_SMBCLK 2 4 Place these close to ICH8. 2.2KX2 CLK_ICH_48M Non-iAMT 2 +3.3V_SUS A RP45 ICH_SMLINK0 ICH_SMLINK1 BMBUSY#/GPIO0 AG22 SMBALERT#/GPIO11 AE20 AG18 STP_PCI#/GPIO15 STP_CPU#/GPIO25 CLKRUN# AH11 CLKRUN#/GPIO32 PCIE_WAKE# IRQ_SERIRQ THERM_ALERT# AE17 AF12 AC13 WAKE# SERIRQ THRM# 31,44,51 IMVP_PWRGD IMVP_PWRGD AJ20 VRMPWRGD 12 R267 PCIE_MCARD1_DET# R820 2 SIO_EXT_SMI# SIO_EXT_SCI# PCIE_MCARD2_DET# PCIE_MCARD3_DET# 33 PCIE_MCARD2_DET# 33 PCIE_MCARD3_DET# 34 WLAN_RADIO_DIS# 41 CAMERA_CBL_DET# 17 SATA_CLKREQ# 18 PLTRST_DELAY# 33 WPAN_RADIO_DIS_MINI# 33 WWAN_RADIO_DIS# PLTRST_DELAY# 40 SPKR SPKR 2 R778 6 MCH_ICH_SYNC# +3.3V_RUN PLTRST_DELAY# 0 AJ21 USB_MCARD2_DET# USB_MCARD3_DET# PCIE_MCARD1_DET# PCIE_MCARD2_DET# PCIE_MCARD3_DET# 2 ICH_PWRGD 6,44 DPRSLPVR 6,51 AJ14 BATLOW# AE21 PWRBTN# C2 LAN_RST# AH20 RSV_ICH_LAN_RST# AG27 ICH_RSMRST# RSMRST# CK_PWRGD E1 CLPWROK E3 ICH_BATLOW# R537 2 8.2K 1 B +3.3V_SUS SIO_PWRBTN# 31 PAD T76 ICH_RSMRST# 31 ICH_CL_PWROK AJ25 CL_CLK0 CL_CLK1 F23 AE18 RSV_ICH_CL_CLK1 CL_CLK0 6 PAD T69 CL_DATA0 CL_DATA1 F22 AF19 RSV_ICH_CL_DATA1 CL_DATA0 6 PAD T78 CL_VREF0 CL_VREF1 D24 AH23 CL_VREF0 CL_VREF1 CL_RST# AJ23 MEM_LED/GPIO24 ME_EC_ALERT/GPIO10 EC_ME_ALERT/GPIO14 WOL_EN/GPIO9 AJ27 AJ24 AF22 AG19 PAD PAD T90 6,31 ICH_PWRGD R540 2 1 10K DPRSLPVR R784 1 2 100K ICH_RSMRST# CLK_PWRGD 17 ICH_CL_PWROK SLP_M# Non-iAMT R564 2 1 10K RSV_ICH_LAN_RST# R523 2 1 10K ICH_CL_PWROK R762 2 1 1M RSV_GPIO10 R795 2 1 10K T138 ICH_CL_RST0# 6 RSV_GPIO10 RSV_GPIO14 RSV_WOL_EN PAD PAD PAD 8.2K 1 T136 T92 T77 +3.3V_SUS +3.3V_RUN +3.3V_ALW +3.3V_SUS SPKR 2 4 Q47 1 3 CL_VREF1 MEM_SDATA 15 R534 453/F 1 C621 0.1U 1 CL_VREF0 C926 0.1U_NC Low = Default. High = No Reboot. 10 2N7002W-7-F 10 +3.3V_RUN 2 RSV_WOL_EN SIO_EXT_SMI# USB_MCARD1_DET# R792 453/F_NC 2 30,33,34 ICH_SMBDATA R536 R796 3.24K/F_NC 3.24K/F_NC 2 2 No Reboot strap. +3.3V_SUS R531 3.24K/F RP51 2.2KX2 SPKR C DIS:ALW UMA:SUS Non-iAMT These are for backdrive issue. 14 +3.3V_SUS 1 +3.3V_RUN C577 4.7P_NC 50 ICH_PWRGD DPRSLPVR DPRSLPVR/GPIO16 SMbus address D2 R478 1K_NC 1 10K 1 10K 2 100K AE23 2 +3.3V_RUN 1 10K_NC MCH_ICH_SYNC#_R IRQ_SERIRQ 1 10K THERM_ALERT# 1 10K R522 2 R505 2 R788 1 AH27 PWROK Non-iAMT +3.3V_RUN R781 2 R476 2 R500 2 TP3 S4_STATE#/GPIO26 SIO_SLP_S3# 31 PAD T88 SIO_SLP_S5# 31 R543 2 1 100K 100K 100K 100K 100K MCH_SYNC# AG23 AF21 AD18 R473 10_NC T43 1 2 2 2 2 2 1 1 1 1 1 SPKR SLP_S3# SLP_S4# SLP_S5# PAD 2 R770 R771 R480 R490 R774 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 GPIO12 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 D3 CLK_ICH_14M 17 CLK_ICH_48M 17 1 1 2.2K_NC IMVP_PWRGD AD9 MCH_ICH_SYNC#_R AJ13 1 11 ICH_RSVD R786 2 AJ8 AJ9 AH9 AE16 AC19 AG8 AH12 AE11 AG10 AH25 AD16 AG13 AF9 AJ11 AD10 SUSCLK ICH_SUSCLK 1 3 1 10K 2 USB_MCARD2_DET# USB_MCARD3_DET# 33 USB_MCARD2_DET# 33 USB_MCARD3_DET# 31 SIO_EXT_WAKE# 31 SIO_EXT_SMI# 31 SIO_EXT_SCI# 0_NC 1 4.7K TP7 CLK_ICH_14M CLK_ICH_48M 2 37 KB_LED_DET# 34 PCIE_MCARD1_DET# AJ22 T134 PAD AG9 G5 CLK14 CLK48 1 1 AG12 CLK_ICH_14M 2 SUS_STAT#/LPCPD# SYS_RESET# 50 AJ12 AJ10 AF11 AG11 2 28,31 CLKRUN# 30,33,34,42 PCIE_WAKE# 28,31 IRQ_SERIRQ 39 THERM_ALERT# C564 4.7P_NC 1 F4 AD15 SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37 2 2 RI# 17 H_STP_PCI# 17 H_STP_CPU# 2 1 CLKRUN# Option to " Disable " clkrun. Pulling it down will keep the clks running. C AF17 USB_MCARD1_DET# 34 USB_MCARD1_DET# R777 10_NC R465 ICH_RI# 6 PM_BMBUSY# 1 B SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1 RSV_LPCPD# T48 PAD 3 ITP_DBRESET# R775 8.2K AJ26 AD19 AG21 AC17 AE19 Clocks SATA GPIO +3.3V_RUN ICH_SMBCLK ICH_SMBDATA RSV_ICH_CL_RST1# ICH_SMLINK0 ICH_SMLINK1 SYS GPIO Power MGT 30,33,34 ICH_SMBCLK 30,33,34 ICH_SMBDATA T82 PAD T139 PAD T79 PAD MISC GPIO Controller Link 2 0 ICH_SMLINK0 2 0 ICH_SMLINK1 SMB U48C ICH_SMBCLK R798 1 ICH_SMBDATA R524 1 2 R773 8.2K 100KX2_NC 1 2 4 A R444 10_NC 2 1 3 1 1 1 1 1 1 +3.3V_SUS 2 2 2 2 +3.3V_RUN RSV_ICH_CL_RST1# ICH_RI# SIO_EXT_SCI# PCIE_WAKE# 1 ASF 2.0 10K_NC 10K 10K 1K 2 Non-iAMT R789 R519 R521 R509 D 30,33,34 ICH_SMBCLK 3 Q76 1 D MEM_SCLK 15 QUANTA COMPUTER 2N7002W-7-F Title ICH8-M (PM,GPIO,SMB,CL) 1 2 3 4 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 13 8 62 1 2 3 4 5 +RTC_CELL 1 +1.5V_RUN +VCCSATPLL 1 +1.5V_RUN +VCCSATPLL_L 10 1 2 1 2 1 1 10 C558 0.1U 10 AC12 VCCSUSHDA AD11 VCCSUS1_05[1] VCCSUS1_05[2] J6 AF20 TP_VCCSUS1.05_1 TP_VCCSUS1.05_2 VCCSUS1_5[1] AC16 TP_VCCSUS1.5_1 VCCSUS1_5[2] J7 TP_VCCSUS1.5_2 VCCSUS3_3[01] C3 VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04] VCCSUS3_3[05] VCCSUS3_3[06] AC18 AC21 AC22 AG20 AH28 VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] P6 P7 C1 N7 P1 P2 P3 P4 P5 R1 R3 R5 R6 1 2 2 1 2 10 C550 0.1U_NC 10 10 C566 0.1U_NC C573 0.1U_NC 10 10 Non-iAMT VCCHDA C552 0.1U_NC C589 0.1U +3.3V_SUS +3.3V_RUN 2 VCCLAN3_3[1] VCCLAN3_3[2] A24 VCCGLANPLL +1.5V_PCIE_ICH 10 A26 A27 B26 B27 B28 VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] VCCGLAN1_5[5] 1 C631 4.7U B25 VCCGLAN3_3 2 2 1 1 1 2 1 C562 0.1U_NC C544 0.1U_NC C634 0.1U_NC C541 0.1U_NC 10 10 10 10 VCCCL1_05 G22 TP_VCCCL1.05 VCCCL1_5 A22 +VCCCL1_5 VCCCL3_3[1] VCCCL3_3[2] F20 G21 C559 0.1U +3.3V_RUN C927 0.1U_NC 4 Title 1U_NC 603 K7 L1 L13 L15 L26 L27 L4 L5 M12 M13 M14 M15 M16 M17 M23 M28 M29 M3 N1 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 N4 N5 N6 P12 P13 P14 P15 P16 P17 P23 P28 P29 R11 R12 R13 R14 R15 R16 R17 R18 R28 R4 T12 T13 T14 T15 T16 T17 T2 U12 U13 U14 U15 U16 U17 U23 U26 U27 U3 U5 V13 V15 V28 V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5 AB6 AD5 U4 W24 VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12] A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29 A B C ICH8-M (POWER,GND) Size Document Number GM3 Date: Monday, March 24, 2008 10 5 VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] QUANTA COMPUTER PC187 Non-iAMT 6.3 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] D PAD T89 10 3 10 10 +3.3V_RUN 2 10 C548 0.1U WWAN Noise - ICH improvements 2 10 GLAN POWER F19 G20 1 +1.5V_RUN VCCLAN1_05[1] VCCLAN1_05[2] C607 0.1U 1 VCC1_5_A[25] +3.3V_SUS Non-iAMT 2 W23 TP_VCCSUSLAN1 F17 TP_VCCSUSLAN2 G18 T68 PAD T67 PAD 10 10 2 VCC1_5_A[20] VCC1_5_A[21] VCC1_5_A[22] VCC1_5_A[23] VCC1_5_A[24] PAD T58 1 F1 L6 L7 M6 M7 PAD T70 C569 0.1U 2 1 10 VCCUSBPLL C563 0.1U 2 Non-iAMT C540 0.1U VCC1_5_A[18] VCC1_5_A[19] D1 PAD T50 PAD T73 1 2 2 1 10 C606 0.1U 1 1 2 2 VCC1_5_A[15] VCC1_5_A[16] VCC1_5_A[17] 2 2 G12 G17 H7 USB CORE C545 0.1U +3.3V_RUN 2 VCC1_5_A[13] VCC1_5_A[14] AC7 AD7 +1.5V_RUN 1 AA5 AA6 C626 0.1U 1 603 C625 0.1U VCC1_5_A[11] VCC1_5_A[12] C570 0.1U 2 10 603 +1.5V_RUN AC10 AC9 10 1 6.3 +1.5V_RUN D VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08] VCC1_5_A[09] VCC1_5_A[10] A8 B15 B18 B4 B9 C15 D13 D5 E10 E7 F11 WWAN Noise - ICH improvements805 10 2 C588 1U 603 Place C625 close to A24. AC1 AC2 AC3 AC4 AC5 VCC3_3[14] VCC3_3[15] VCC3_3[16] VCC3_3[17] VCC3_3[18] VCC3_3[19] VCC3_3[20] VCC3_3[21] VCC3_3[22] VCC3_3[23] VCC3_3[24] 10 C585 4.7U +3.3V_RUN 1 C571 10U 10 Non-iAMT VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05] 10 10 2 C901 1U 603 AE7 AF7 AG7 AH7 AJ7 AA3 U7 V7 W1 W6 W7 Y7 C611 0.1U C595 0.1U 10 1206 C574 0.1U C609 0.1U 1 1 +1.5V_RUN 2 2 805 2 1 +VCCSATPLL VCCSATAPLL ATX 10uH+-20%_100mA C C576 1U 2 L84 10uH AJ6 ARX 2 R769 0 VCC3_3[07] VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13] +3.3V_RUN 10 +1.05V_VCCP 1 805 10 close to AC23 & AC24 C643 22U 2 1206 AC8 AD8 AE8 AF8 C640 0.1U 1 1206 VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06] 603 +1.25V_RUN +1.05V_VCCP 2 7343 VCC3_3[02] AD2 6.3 1 10 AF29 25 2 10 VCC3_3[01] C943 10U 1 10 AC23 AC24 +1.5V_RUN 1 1 R817 1+1.5V_DMIPLL_R 2 2 4 C615 2.2U V_CPU_IO[1] V_CPU_IO[2] C942 0.01U 1 C604 22U 1 C619 22U 2 2 C957 220U 2 + AE28 AE29 L88 1uH 2 +1.5V_DMIPLL 2 2 1 1 1 B VCC_DMI[1] VCC_DMI[2] 1uH+-20%_800mA 1 +1.5V_PCIE_ICH R29 805 2 FB_330ohm+-25%_100mHz_ 1.5A_0.09 ohm DC VCCA3GP 805 BLM21PG331SN1D VCCDMIPLL 2 10 BAT54C T/R 1 +1.5V_RUN R469 3 1 2 603 +1.5V_RUN D16 1 2 1 2 C896 1U +1.05V_VCCP 2 603 +ICH_V5REF_SUS 10 L62 U48E 10 1 1 SDMK0340L-7-F VCCPSUS 2 +3.3V_SUS 10 C596 0.1U 2 D29 VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46] VCCPUSB 1 +5V_SUS AA25 AA26 AA27 AB27 AB28 AB29 D28 D29 E25 E26 E27 F24 F25 G24 H23 H24 J23 J24 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T23 T24 T27 T28 T29 U24 U25 V23 V24 V25 W25 Y25 10 1 100 2 C608 1U 1 Non-iAMTR764 V5REF_SUS A13 B13 C13 C14 D14 E14 F14 G14 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18 2 2 A G4 V5REF[1] V5REF[2] C598 0.1U VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26] VCC1_05[27] VCC1_05[28] 1 SDMK0340L-7-F A16 T7 +ICH_V5REF_RUN 603 CORE 1 1 VCCRTC VCCP_CORE D30 1 U48F AD25 10 IDE 10 C629 0.1U PCI 10 1 C618 0.1U 1 C616 1U 8 A23 A5 AA2 AA7 A25 AB1 AB24 AC11 AC14 AC25 AC26 AC27 AD17 AD20 AD28 AD29 AD3 AD4 AD6 AE1 AE12 AE2 AE22 AD1 AE25 AE5 AE6 AE9 AF14 AF16 AF18 AF3 AF4 AG5 AG6 AH10 AH13 AH16 AH19 AH2 AF28 AH22 AH24 AH26 AH3 AH4 AH8 AJ5 B11 B14 B17 B2 B20 B22 B8 C24 C26 C27 C6 D12 D15 D18 D2 D4 E21 E24 E4 E9 F15 E23 F28 F29 F7 G1 E2 G10 G13 G19 G23 G25 G26 G27 H25 H28 H29 H3 H6 J1 J25 J26 J27 J4 J5 K23 K28 K29 K3 K6 2 2 1 100 2 2 +3.3V_RUN 7 +1.05V_VCCP 2 R783 1 +5V_RUN 6 6 7 Rev 2B Sheet of 14 8 62 2 3 4 5 MASTER DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D46 DDR_A_D53 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D60 DDR_A_D56 DDR_A_DM7 DDR_A_D63 DDR_A_D59 D 13 MEM_SDATA 13 MEM_SCLK +3.3V_RUN MEM_SDATA MEM_SCLK TYC_1-1734074-1 SMbus address A0 2 H 5.2 M_ODT0 DDR_A_MA13 7,16 DDR_B_BS0 7,16 DDR_B_WE# M_ODT0 6,16 7,16 DDR_B_CAS# 6,16 DDR_CS3_DIMMB# 6,16 M_ODT3 DDR_B_MA10 DDR_B_BS0 DDR_B_WE# DDR_B_CAS# M_ODT3 DDR_A_D32 DDR_A_D33 DDR_B_D37 DDR_B_D38 DDR_A_DM4 DDR_B_DQS#4 DDR_B_DQS4 DDR_A_D38 DDR_A_D35 DDR_B_D34 DDR_B_D35 DDR_A_D44 DDR_A_D45 DDR_B_D41 DDR_B_D40 DDR_A_DQS#5 DDR_A_DQS5 DDR_B_DM5 DDR_A_D43 DDR_A_D47 DDR_B_D46 DDR_B_D43 DDR_A_D48 DDR_A_D52 DDR_B_D53 DDR_B_D49 M_CLK_DDR1 6 M_CLK_DDR#1 6 DDR_B_DQS#6 DDR_B_DQS6 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D57 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 +3.3V_RUN DDR_B_D54 DDR_B_D50 DDR_B_D56 DDR_B_D57 C504 2.2U_6.3V C508 0.1U_10V DDR_B_DM7 DDR_B_D58 DDR_B_D63 DDR_A_D62 DDR_A_D58 MEM_SDATA MEM_SCLK +3.3V_RUN R392 10K SMbus address A4 R390 10K TYC_2-1734073-2 3 4 5 H 9.2 2 2 1 1 1 2 1 2 1 2 1 2 1 Place these Caps near So-Dimm2. DDR_B_BS1 DDR_B_RAS# DDR_B_BS1 7,16 DDR_B_RAS# 7,16 DDR_CS2_DIMMB# 6,16 M_ODT2 DDR_B_MA13 C872 2.2U_6.3V 1 C874 2.2U_6.3V 2 C873 2.2U_6.3V 1 C870 2.2U_6.3V 2 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 1 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 C871 2.2U_6.3V +1.8V_SUS Place these Caps near So-Dimm1. M_ODT2 6,16 C501 0.1U_10V DDR_B_D32 DDR_B_D36 DDR_B_DM4 +1.8V_SUS C888 0.1U_10V C498 0.1U_10V C500 0.1U_10V C Place these Caps near So-Dimm2. DDR_B_D39 DDR_B_D33 DDR_B_D45 DDR_B_D44 DDR_B_DQS#5 DDR_B_DQS5 C497 0.1U_10V C890 0.1U_10V C496 0.1U_10V C499 0.1U_10V DDR_B_D42 DDR_B_D47 DDR_B_D52 DDR_B_D48 M_CLK_DDR4 6 M_CLK_DDR#4 6 +3.3V_RUN DDR_B_DM6 DDR_B_D51 DDR_B_D55 DDR_B_D60 DDR_B_D61 C523 2.2U_6.3V C520 0.1U_10V DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D59 R411 2 D +3.3V_RUN 1 10K QUANTA COMPUTER R413 10K CLOCK 2,3 CKE 2,3 B 1 DDR_A_BS1 7,16 DDR_A_RAS# 7,16 DDR_CS0_DIMMA# 6,16 C893 2.2U_6.3V DDR_B_MA14 6,16 2 DDR_A_BS1 DDR_A_RAS# C889 2.2U_6.3V +1.8V_SUS 2 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 C891 2.2U_6.3V 1 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_CKE4_DIMMB 6,16 2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 C875 2.2U_6.3V DDR_B_D30 DDR_B_D26 1 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 2 2 7,16 DDR_B_BS2 C892 2.2U_6.3V 2 DDR_B_BS2 DDR_B_DQS#3 DDR_B_DQS3 Place these Caps near So-Dimm1. 1 DDR_A_MA14 6,16 6,16 DDR_CKE3_DIMMB DDR_B_D24 DDR_B_D25 1 1 1 2 DDR_B_D31 DDR_B_D27 DDR_CKE1_DIMMA 6,16 CLOCK 0,1 CKE 0,1 1 DDR_A_D30 DDR_A_D26 +1.8V_SUS 1 DDR_A_D34 DDR_A_D39 DDR_B_DM3 PM_EXTTS#1 6 DDR_B_D18 DDR_B_D19 2 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#3 DDR_A_DQS3 PM_EXTTS#1 DDR_B_DM2 1 C DDR_B_D29 DDR_B_D28 DDR_B_D21 DDR_B_D16 2 DDR_A_D37 DDR_A_D36 DDR_A_D29 DDR_A_D24 M_CLK_DDR3 6 M_CLK_DDR#3 6 DDR_B_D14 DDR_B_D15 1 M_ODT1 DDR_B_D22 DDR_B_D23 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 C467 2.2U_6.3V DDR_B_DM1 2 6,16 M_ODT1 DDR_A_CAS# DDR_A_D18 DDR_A_D22 VSS20 DQ20 DQ21 VSS6 NC3 DM2 VSS21 DQ22 DQ23 VSS24 DQ28 DQ29 VSS25 DQS#3 DQS3 VSS10 DQ30 DQ31 VSS8 CKE1 VDD8 A15 A14 VDD11 A11 A7 A6 VDD4 A4 A2 A0 VDD12 BA1 RAS# S0# VDD1 ODT0 A13 VDD6 NC2 VSS12 DQ36 DQ37 VSS28 DM4 VSS42 DQ38 DQ39 VSS55 DQ44 DQ45 VSS43 DQS#5 DQS5 VSS56 DQ46 DQ47 VSS44 DQ52 DQ53 VSS57 CK1 CK1# VSS45 DM6 VSS32 DQ54 DQ55 VSS35 DQ60 DQ61 VSS7 DQS#7 DQS7 VSS36 DQ62 DQ63 VSS13 SA0 SA1 C471 0.1U_10V 2 7,16 DDR_A_CAS# 6,16 DDR_CS1_DIMMA# DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_B_DQS#2 DDR_B_DQS2 PM_EXTTS#0 6 VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD) DDR_B_D12 DDR_B_D13 1 7,16 DDR_A_BS0 7,16 DDR_A_WE# PM_EXTTS#0 DDR_A_DM2 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DDR_B_D7 DDR_B_D6 2 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_B_D17 DDR_B_D20 DDR_B_DM0 2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_D16 DDR_A_D21 +V_DDR_MCH_REF 1 7,16 DDR_A_BS2 DDR_B_D11 DDR_B_D10 A DDR_B_D0 DDR_B_D1 2 DDR_A_BS2 DDR_A_D15 DDR_A_D10 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 DDR_A_D31 DDR_A_D27 6,16 DDR_CKE0_DIMMA DDR_B_DQS#1 DDR_B_DQS1 M_CLK_DDR0 6 M_CLK_DDR#0 6 VSS46 DQ4 DQ5 VSS15 DM0 VSS5 DQ6 DQ7 VSS16 DQ12 DQ13 VSS17 DM1 VSS53 CK0 CK0# VSS41 DQ14 DQ15 VSS54 2 DDR_A_DM3 DDR_A_DM1 VREF VSS47 DQ0 DQ1 VSS37 DQS#0 DQS0 VSS48 DQ2 DQ3 VSS38 DQ8 DQ9 VSS49 DQS#1 DQS1 VSS39 DQ10 DQ11 VSS50 1 B 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DDR_B_D2 DDR_B_D3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 DDR_A_D28 DDR_A_D25 VSS20 DQ20 DQ21 VSS6 NC3 DM2 VSS21 DQ22 DQ23 VSS24 DQ28 DQ29 VSS25 DQS#3 DQS3 VSS10 DQ30 DQ31 VSS8 CKE1 VDD8 A15 A14 VDD11 A11 A7 A6 VDD4 A4 A2 A0 VDD12 BA1 RAS# S0# VDD1 ODT0 A13 VDD6 NC2 VSS12 DQ36 DQ37 VSS28 DM4 VSS42 DQ38 DQ39 VSS55 DQ44 DQ45 VSS43 DQS#5 DQS5 VSS56 DQ46 DQ47 VSS44 DQ52 DQ53 VSS57 CK1 CK1# VSS45 DM6 VSS32 DQ54 DQ55 VSS35 DQ60 DQ61 VSS7 DQS#7 DQS7 VSS36 DQ62 DQ63 VSS13 SA0 SA1 C509 2.2U_6.3V 1 DDR_A_D23 DDR_A_D19 VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD) DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D8 DDR_B_D9 2 DDR_A_DQS#2 DDR_A_DQS2 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 C510 0.1U_10V 1 DDR_A_D17 DDR_A_D20 DDR_A_D13 DDR_A_D12 2 DDR_A_D11 DDR_A_D14 DDR_A_DM0 2 DDR_A_DQS#1 DDR_A_DQS1 DDR_B_D5 DDR_B_D4 DDR_A_D7 DDR_A_D1 DDR_B_DM[0..7] 7 DDR_B_D[0..63] 7 DDR_B_DQS[0..7] 7 DDR_B_DQS#[0..7] 7 DDR_B_MA[0..13] 7,16 JDIM2 +V_DDR_MCH_REF 1 DDR_A_D9 DDR_A_D8 DDR_A_D4 DDR_A_D0 2 DDR_A_D3 DDR_A_D2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 DDR_A_DQS#0 DDR_A_DQS0 PC4800 DDR2 SDRAM SO-DIMM (200P) DDR_A_D6 DDR_A_D5 VSS46 DQ4 DQ5 VSS15 DM0 VSS5 DQ6 DQ7 VSS16 DQ12 DQ13 VSS17 DM1 VSS53 CK0 CK0# VSS41 DQ14 DQ15 VSS54 8 +1.8V_SUS +V_DDR_MCH_REF 2 +V_DDR_MCH_REF VREF VSS47 DQ0 DQ1 VSS37 DQS#0 DQS0 VSS48 DQ2 DQ3 VSS38 DQ8 DQ9 VSS49 DQS#1 DQS1 VSS39 DQ10 DQ11 VSS50 +1.8V_SUS DDR_A_DM[0..7] 7 DDR_A_D[0..63] 7 DDR_A_DQS[0..7] 7 DDR_A_DQS#[0..7] 7 DDR_A_MA[0..13] 7,16 Title 1 +1.8V_SUS JDIM1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 7 SLAVE +1.8V_SUS A 6 PC4800 DDR2 SDRAM SO-DIMM (200P) 1 DDR2_SO-DIMM (200P) X 2 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 15 8 62 1 2 3 +0.9V_DDR_VTT 4 5 6 7 8 Layout note: Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM. 1 C517 0.1U_10V 2 C530 0.1U_10V 1 1 C491 0.1U_10V 2 C516 0.1U_10V 1 1 C493 0.1U_10V 2 C472 0.1U_10V 1 1 C528 0.1U_10V 2 C470 0.1U_10V 1 1 C531 0.1U_10V 2 C464 0.1U_10V 1 1 C526 0.1U_10V 2 C466 0.1U_10V 1 1 C514 0.1U_10V 2 C465 0.1U_10V 1 1 C527 0.1U_10V 2 C513 0.1U_10V 1 1 C511 0.1U_10V 2 C515 0.1U_10V 1 1 C494 0.1U_10V 2 1 C490 0.1U_10V 1 1 C489 0.1U_10V C468 0.1U_10V 2 C512 0.1U_10V 2 2 C529 0.1U_10V 1 A 1 A B C492 0.1U_10V 2 2 2 2 2 2 2 2 2 2 2 1 2 C469 0.1U_10V 2 1 +0.9V_DDR_VTT B +0.9V_DDR_VTT 7,15 DDR_A_MA[0..13] DDR_B_MA[0..13] RP25 DDR_A_MA11 DDR_A_MA7 2 4 RP36 1 3 1 3 4P2R-S-56 RP26 DDR_A_MA6 DDR_A_MA4 2 4 DDR_A_BS1 DDR_A_RAS# 1 3 2 4 1 3 DDR_A_MA13 M_ODT0 1 3 2 4 1 3 DDR_A_BS2 DDR_A_MA12 2 4 1 3 1 3 Please these resistor closely DIMMA,all trace length<750 mil. DDR_A_MA9 DDR_A_MA8 2 4 DDR_A_MA3 DDR_A_MA5 2 4 DDR_A_BS0 DDR_A_MA10 2 4 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 4P2R-S-56 RP9 2 4 DDR_A_MA2 DDR_A_MA0 1 3 6,15 M_ODT1 6,15 DDR_CS0_DIMMA# 6,15 DDR_CS1_DIMMA# 6,15 DDR_CKE0_DIMMA 6,15 DDR_CKE1_DIMMA 6,15 DDR_A_MA14 R388 DDR_A_MA1 R386 R402 R387 R389 R401 R400 1 1 1 1 1 1 1 2 4 DDR_B_MA3 DDR_B_MA5 2 4 DDR_B_MA9 DDR_B_MA8 2 4 DDR_B_MA1 DDR_B_MA12 2 4 DDR_B_BS0 DDR_B_MA10 2 4 DDR_B_CAS# DDR_B_WE# 2 4 DDR_B_MA4 DDR_B_MA0 M_ODT2 6,15 C Please these resistor closely DIMMB,all trace length<750 mil. DDR_B_BS0 7,15 DDR_B_CAS# 7,15 DDR_B_WE# 7,15 4P2R-S-56 RP37 1 3 4P2R-S-56 2 2 2 2 2 2 2 M_ODT2 DDR_B_MA13 4P2R-S-56 RP31 1 3 2 4 2 4 DDR_B_BS1 7,15 DDR_B_RAS# 7,15 4P2R-S-56 RP30 4P2R-S-56 RP27 T194 PAD D DDR_A_CAS# DDR_A_WE# DDR_B_BS1 DDR_B_RAS# 4P2R-S-56 RP33 4P2R-S-56 RP11 7,15 DDR_A_CAS# 7,15 DDR_A_WE# 2 4 4P2R-S-56 RP32 4P2R-S-56 RP10 7,15 DDR_A_BS0 DDR_B_MA11 DDR_B_MA7 4P2R-S-56 RP34 4P2R-S-56 RP12 C 2 4 4P2R-S-56 RP39 4P2R-S-56 RP13 7,15 DDR_A_BS2 DDR_B_MA6 DDR_B_MA2 4P2R-S-56 RP38 4P2R-S-56 RP29 6,15 M_ODT0 2 4 4P2R-S-56 RP35 4P2R-S-56 RP28 7,15 DDR_A_BS1 7,15 DDR_A_RAS# 7,15 1 3 56 56 56 56 56 56 56 R406 R403 R417 R405 R415 R404 R416 4P2R-S-56 2 2 2 2 2 2 2 1 1 1 1 1 1 1 56 56 56 56 56 56 56 M_ODT3 6,15 DDR_B_BS2 7,15 DDR_CS2_DIMMB# 6,15 DDR_CS3_DIMMB# 6,15 DDR_CKE4_DIMMB 6,15 DDR_CKE3_DIMMB 6,15 DDR_B_MA14 6,15 D QUANTA COMPUTER Title DDR2 RES. ARRAY 1 2 3 4 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 16 8 62 1 2 3 4 5 6 7 8 Add capacitor pads for improving WWAN. C457 C440 C431 C432 C439 CLK_ICH_48M CLK_ICH_14M CLK_PCI_8512 CLK_PCI_PCCARD CLK_PCI_ICH 1 2 27P 1 2 27P_NC 1 50 2 27P_NC 1 50 2 27P_NC 1 50 2 27P_NC 50 50 U19 +CK_VDD_PCI 9 4 23 16 46 62 +CK_VDD_PLL3 +CK_VDD_48 +CK_VDD_SRC A +CK_VDD_MAIN 19 27 33 43 52 56 Y2 2 CLK_XTAL_OUT 1 2 14.318MHZ C443 33P 1 C437 33P 1 2 CLK_XTAL_IN 14.318MHz 50 50 SATA_CLKREQ# CLK_3GPLLREQ# 13 SATA_CLKREQ# 6 CLK_3GPLLREQ# 33 CLK_LPC_DEBUG 28 CLK_PCI_PCCARD 31 CLK_PCI_8512 12 CLK_PCI_ICH 13 CLK_ICH_48M B 1 3,6 CPU_MCH_BSEL0 3,6 CPU_MCH_BSEL1 3,6 CPU_MCH_BSEL2 R365 R364 1 CLK_LPC_DEBUG R363 1 CLK_PCI_PCCARD R354 2 2 22_NC 1 33 CLK_PCI_8512 R353 2 1 33 CLK_PCI_ICH R350 2 1 33 CLK_ICH_48M R375 2 1 33 R372 1 2 BLM18SG260 R374 1 R367 1 L55 CLK_ICH_14M 13 CLK_ICH_14M 13 CLK_PWRGD 475 2 475/F SATA_CLKREQ#_C CLK_3GPLLREQ#_C PCI_PCCARD PCI_SIO 27M_SEL PCI_ICH 2 8.2K 2 8.2K 2 8.2K R366 2 FSA FSB FSC 8 10 11 12 13 14 CR#_A/PCI-0 CR_B/PCI-1 TME/PCI-2 SRC5_EN/PCI-3 27M_SEL/PCI-4 ITP_EN/PCIF-5# 55 63 CLK_LPC_DEBUG FOR DEBUG NEED POP RESISTOR 4 2 3 RP5 1 0 4 2 3 RP7 1 0 4 2 3 RP17 1 0 DOT96_SSC DOT96_SSC# 2 4 1 RP4 3 0_DIS 24 25 27M_NSS 27M_SS 2 4 1 RP8 3 0_DIS SRC-2/SATA SRC-2#/SATA# 28 29 PCIE_SATA PCIE_SATA# 2 4 1 RP16 3 0 CR#_C/SRC-3 CR#_D/SRC-3# 31 32 PCIE_MINI3 PCIE_MINI3# 2 4 1 RP18 3 0 SRC-4 SRC-4# 34 35 MCH_3GPLL MCH_3GPLL# 2 4 1 RP20 3 0 PCI_STOP#/SRC-5 CPU_STOP#/SRC5-5# 45 44 SRC-6 SRC-6# 48 47 PCIE_EXPCARD PCIE_EXPCARD# CR#_F/SRC-7 CR#_E/SRC-7# 51 50 MINI1CLK_REQ#_C CARD_CLK_REQ#_C SRC-9 SRC-9# 37 38 PCIE_MINI2 PCIE_MINI2# SRC-10 SRC-10# 41 42 CR#_H/SRC-11 CR#_G/SRC-11# 40 39 GND 65 CK505 QFN64 GND GND GND GND GND GND GND GND GND 61 60 CPU_BCLK CPU_BCLK# CPU-1 CPU-1# 58 57 MCH_BCLK MCH_BCLK# SRC-8/CPU_ITP SRC-8#/CPU_ITP# 54 53 SRC-0/DOT96 SRC-0#/DOT96# 20 21 SRC-1/SE1 SRC-1#/SE2 CPU-0 CPU-0# VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO 15 18 22 26 30 36 49 59 1 17 64 5 1 33 VDD_PCI VDD_REF VDD_PLL3 VDD_48 VDD_SRC VDD_CPU FSA/USB48 FSB/TEST_MODE FSC/TEST_SEL/REF RESET# CK_PWRGD/PD# CLK_XTAL_OUT CLK_XTAL_IN 2 3 XOUT XIN CLK_SDATA CLK_SCLK 6 7 SDATA SCLK CPU_ITP CPU_ITP# 13 CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3 CLK_MCH_BCLK 5 CLK_MCH_BCLK# 5 A CLK_PCIE_MINI1 34 CLK_PCIE_MINI1# 34 CLK_PCIE_VGA 18 CLK_PCIE_VGA# 18 to ATI VGA CLK_VGA_27M_NSS 19 CLK_VGA_27M_SS 19 CLK_PCIE_SATA 11 CLK_PCIE_SATA# 11 CLK_PCIE_MINI3 33 CLK_PCIE_MINI3# 33 +3.3V_RUN CLK_MCH_3GPLL 6 CLK_MCH_3GPLL# 6 H_STP_PCI# H_STP_CPU# H_STP_PCI# 13 H_STP_CPU# 13 3 RP24 1 0 2 475/F 2 475/F MINI1CLK_REQ# CARD_CLK_REQ# 2 4 1RP21 3 0 PCIE_ICH PCIE_ICH# 2 4 1 RP23 3 0 PCIE_LOM PCIE_LOM# 4 2 3 RP22 1 0 4 2 R394 1 R395 1 CLK_PCIE_EXPCARD 30 CLK_PCIE_EXPCARD# 30 R397 R396 1 10K 1 10K 2 2 Silego need pull up but other? MINI1CLK_REQ# 34 CARD_CLK_REQ# 30 CLK_PCIE_MINI2 33 CLK_PCIE_MINI2# 33 B CLK_PCIE_ICH 12 CLK_PCIE_ICH# 12 CLK_PCIE_LOM 42 CLK_PCIE_LOM# 42 +3.3V_RUN SLG8SP513V CLK_3GPLLREQ# SATA_CLKREQ# CARD_CLK_REQ# MINI1CLK_REQ# PCI_PCCARD POP RESISTOR FOR UMA to MCH DPLL_REF_CLK DOT96_SSC DOT96_SSC# 3 RP6 1 4 2 0_UMA 6 6 1 10K 1 10K 1 10K 1 10K 210K_NC 2 2 2 2 1 to MCH DPLL_REF_SSCLK +3.3V_RUN 27M_SS 27M_NSS UMA without iAMT BLM21PG600SN1D 2 4 2 C485 0.1U 1 1 C473 0.1U 2 1 C462 0.1U 2 C486 0.1U 2 1 1 1 C476 0.1U 2 2 C459 0.1U 2 805 120 ohms@100Mhz 1 +CK_VDD_MAIN C487 CPU_ITP CPU_ITP# 10U_NC 1 3 RP14 1 RP15 3 2 4 0_UMA 0_NC PCI_SIO PCI_ICH DREF_SSCLK# 6 DREF_SSCLK 6 13 R339 10K_NC POP for ITP use C +3.3V_RUN 2 These are for backdrive issue. 10 +CK_VDD_PLL3 2 R340 10K_NC RP3 2.2KX2 Q40 1 1 3 26,31,39 SMBDAT1 C461 0.1U CLK_SDATA +3.3V_RUN 2N7002W-7-F +CK_VDD_48 2.2 2 27M_SEL FSA CPU SRC PCI 1 100 100 33 0 0 1 133 100 33 0 1 1 166 100 33 0 1 0 200 100 33 0 0 0 266 100 33 1 0 0 333 100 33 1 1 0 400 100 33 1 1 1 RSVD 100 33 C 27M_SEL 27M_SEL (PIN13) PIN20 PIN21 0=UMA DOT96T 1 = Disc. GRFX down SRCT0 2 6.3 PIN24 PIN25 DOT96C 96/ 100M_T SRCC0 27Mout 96/ 100M_C 27MSSout D +CK_VDD_SRC 603 2 FSB 0 1 1 +3.3V_RUN C447 4.7U 1 R377 1 R351 10K_DIS R342 10K_UMA 2 2 10 D C448 0.1U 2 2.2 2 1 R358 1 2 10 3 26,31,39 SMBCLK1 C460 0.1U Q39 1 CLK_SCLK QUANTA COMPUTER 1 2.2 2 C446 0.1U PCI_ICH 1 805 120 ohms@100Mhz R391 1 Non-iAMT +CK_VDD_PCI SMbus address D2 FSC 1 1 6.3 10 2 10 4 2 2.2 2 10 210K_NC 210K_NC 3 1 R359 1 10 2 L51 BLM21PG600SN1D 10 1 10 R352 1 R341 1 +3.3V_RUN CLK_CPU_ITP 3 CLK_CPU_ITP# 3 2 L58 MCH_DREFCLK MCH_DREFCLK# R355 R356 R398 R399 R343 2N7002W-7-F Title CLOCK GENERATOR 10 1 2 3 4 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 17 8 62 5 4 3 6 PCIE_MTX_GRX_P[0..15] 6 PCIE_MTX_GRX_N[0..15] 2 1 6 PCIE_MRX_GTX_P[0..15] 6 PCIE_MRX_GTX_N[0..15] U43A PART 1 OF 7 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_N2 D AK33 AJ33 PCIE_RX0P PCIE_RX0N AJ35 AJ34 PCIE_RX1P PCIE_RX1N AH35 AH34 PCIE_RX2P PCIE_RX2N PCIE_MTX_GRX_P3 PCIE_MTX_GRX_N3 AG35 AG34 PCIE_RX3P PCIE_RX3N PCIE_MTX_GRX_P4 PCIE_MTX_GRX_N4 AF33 AE33 PCIE_RX4P PCIE_RX4N AE35 AE34 PCIE_RX5P PCIE_RX5N PCIE_MTX_GRX_P5 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_N11 AD35 AD34 AC35 AC34 AB33 AA33 AA35 AA34 Y35 Y34 W35 W34 PCIE_RX6P PCIE_RX6N PCIE_RX7P PCIE_RX7N PCIE_RX8P PCIE_RX8N PCIE_RX9P PCIE_RX9N PCIE_RX10P PCIE_RX10N PCIE_RX11P PCIE_RX11N P C I E X P R E S S I N T E R F A C E PCIE_TX0P PCIE_TX0N AG31 AG30 PCIE_MRX_GTX_C_P0 PCIE_MRX_GTX_C_N0 PCIE_TX1P PCIE_TX1N AF31 AF30 PCIE_MRX_GTX_C_P1 PCIE_MRX_GTX_C_N1 PCIE_TX2P PCIE_TX2N AF28 AF27 PCIE_MRX_GTX_C_P2 PCIE_MRX_GTX_C_N2 PCIE_TX3P PCIE_TX3N AD31 AD30 PCIE_MRX_GTX_C_P3 PCIE_MRX_GTX_C_N3 PCIE_TX4P PCIE_TX4N AD28 AD27 PCIE_MRX_GTX_C_P4 PCIE_MRX_GTX_C_N4 PCIE_TX5P PCIE_TX5N AB31 AB30 PCIE_MRX_GTX_C_P5 PCIE_MRX_GTX_C_N5 PCIE_TX6P PCIE_TX6N PCIE_TX7P PCIE_TX7N PCIE_TX8P PCIE_TX8N PCIE_TX9P PCIE_TX9N PCIE_TX10P PCIE_TX10N PCIE_TX11P PCIE_TX11N AB28 AB27 AA31 AA30 AA28 AA27 W31 W30 W28 W27 V31 V30 PCIE_MRX_GTX_P0 PCIE_MRX_GTX_P1 PCIE_MRX_GTX_P2 PCIE_MRX_GTX_P3 PCIE_MRX_GTX_P4 PCIE_MRX_GTX_P5 PCIE_MRX_GTX_P6 PCIE_MRX_GTX_P7 PCIE_MRX_GTX_P8 PCIE_MRX_GTX_P9 PCIE_MRX_GTX_P10 PCIE_MRX_GTX_P11 PCIE_MRX_GTX_C_P6 PCIE_MRX_GTX_C_N6 PCIE_MRX_GTX_P12 PCIE_MRX_GTX_P13 PCIE_MRX_GTX_C_P7 PCIE_MRX_GTX_C_N7 PCIE_MRX_GTX_P14 PCIE_MRX_GTX_P15 PCIE_MRX_GTX_C_P8 PCIE_MRX_GTX_C_N8 PCIE_MRX_GTX_N0 PCIE_MRX_GTX_N1 PCIE_MRX_GTX_C_P9 PCIE_MRX_GTX_C_N9 PCIE_MRX_GTX_N2 PCIE_MRX_GTX_N3 PCIE_MRX_GTX_C_P10 PCIE_MRX_GTX_C_N10 PCIE_MRX_GTX_N4 PCIE_MRX_GTX_N5 PCIE_MRX_GTX_C_P11 PCIE_MRX_GTX_C_N11 PCIE_MRX_GTX_N6 PCIE_MRX_GTX_N7 C PCIE_MTX_GRX_P12 PCIE_MTX_GRX_N12 V33 U33 PCIE_RX12P PCIE_RX12N PCIE_TX12P PCIE_TX12N V28 V27 PCIE_MRX_GTX_C_P12 PCIE_MRX_GTX_C_N12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_N13 U35 U34 PCIE_RX13P PCIE_RX13N PCIE_TX13P PCIE_TX13N U31 U30 PCIE_MRX_GTX_C_P13 PCIE_MRX_GTX_C_N13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_P15 PCIE_MTX_GRX_N15 T35 T34 R35 R34 PCIE_RX14P PCIE_RX14N PCIE_RX15P PCIE_RX15N Clock 17 CLK_PCIE_VGA 17 CLK_PCIE_VGA# R718 13 PLTRST_DELAY# 402 0_DIS AJ31 AJ30 PCIE_REFCLKP PCIE_REFCLKN SM Bus AK35 AK34 NC_SMB_DATA NC_SMBCLK AM32 PERSTB PCIE_TX14P PCIE_TX14N PCIE_TX15P PCIE_TX15N U28 U27 R31 R30 PCIE_MRX_GTX_N8 PCIE_MRX_GTX_N9 PCIE_MRX_GTX_N10 PCIE_MRX_GTX_N11 PCIE_MRX_GTX_C_P14 PCIE_MRX_GTX_C_N14 PCIE_MRX_GTX_N12 PCIE_MRX_GTX_N13 PCIE_MRX_GTX_C_P15 PCIE_MRX_GTX_C_N15 PCIE_MRX_GTX_N14 PCIE_MRX_GTX_N15 C213 0.1U_DIS 10 C231 0.1U_DIS 10 C233 0.1U_DIS 10 C211 0.1U_DIS 10 C230 0.1U_DIS 10 C210 0.1U_DIS 10 C208 0.1U_DIS 10 C227 0.1U_DIS 10 C206 0.1U_DIS 10 C226 0.1U_DIS 10 C224 0.1U_DIS 10 C204 0.1U_DIS 10 C220 0.1U_DIS 10 C222 0.1U_DIS 10 C200 0.1U_DIS 10 C201 0.1U_DIS 10 C214 0.1U_DIS 10 C232 0.1U_DIS 10 C234 0.1U_DIS 10 C212 0.1U_DIS 10 C229 0.1U_DIS 10 C209 0.1U_DIS 10 C207 0.1U_DIS 10 C228 0.1U_DIS 10 C205 0.1U_DIS 10 C225 0.1U_DIS 10 C223 0.1U_DIS 10 C203 0.1U_DIS 10 C219 0.1U_DIS 10 C221 0.1U_DIS 10 C199 0.1U_DIS 10 C202 0.1U_DIS 10 PCIE_MRX_GTX_C_P0 PCIE_MRX_GTX_C_P1 PCIE_MRX_GTX_C_P2 PCIE_MRX_GTX_C_P3 PCIE_MRX_GTX_C_P4 D PCIE_MRX_GTX_C_P5 PCIE_MRX_GTX_C_P6 PCIE_MRX_GTX_C_P7 PCIE_MRX_GTX_C_P8 PCIE_MRX_GTX_C_P9 PCIE_MRX_GTX_C_P10 PCIE_MRX_GTX_C_P11 PCIE_MRX_GTX_C_P12 PCIE_MRX_GTX_C_P13 PCIE_MRX_GTX_C_P14 PCIE_MRX_GTX_C_P15 PCIE_MRX_GTX_C_N0 PCIE_MRX_GTX_C_N1 PCIE_MRX_GTX_C_N2 PCIE_MRX_GTX_C_N3 PCIE_MRX_GTX_C_N4 PCIE_MRX_GTX_C_N5 PCIE_MRX_GTX_C_N6 PCIE_MRX_GTX_C_N7 C PCIE_MRX_GTX_C_N8 PCIE_MRX_GTX_C_N9 PCIE_MRX_GTX_C_N10 PCIE_MRX_GTX_C_N11 PCIE_MRX_GTX_C_N12 PCIE_MRX_GTX_C_N13 PCIE_MRX_GTX_C_N14 PCIE_MRX_GTX_C_N15 Calibration PCIE_CALRN AG26 PCIE_CALRP AJ27 NC_DRAM_0 NC_DRAM_1 NC_AC_BATT NC_FAN_TACH AF3 AG9 AK29 AK14 R131 402 2K/F_DIS +PCIE_VDDC R126 1.27K_DIS 402 M86-LP_DIS B B A A Title QUANTA COMPUTER VGA-M82-S (PCIe) 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 18 of 62 5 4 3 2 1 +3.3V_DELAY MEMORY APERTURE SIZE SELECT MEMORY SIZE CFG3 GPIO9 CFG2 GPIO13 CFG1 GPIO12 CFG0 GPIO11 8/15: The strap on VIP[3] is for enabling HD Audio on M86. U43B PART 2 OF 7 0 256MB X 0 0 1 64MB X 0 1 0 512MB X 1 0 0 R104 R103 R110 R111 R93 R98 R97 R94 10K_NC 10K_NC 10K_NC 10K_DIS 10K_NC 10K_NC 10K_NC 10K_NC VIP_0 VIP_1 VIP_2 VIP_3 VIP_4 VIP_5 VIP_6 VIP_7 R88 10K_NC VHAD0 D RAM_ RAM_ RAM_ RAM_ TYPE_CFG3 TYPE_CFG2 TYPE_CFG1 TYPE_CFG0 Memory Straps 1 400 MHz 256MB(16M*16) Hynix 1 1 1 R79 10K_NC PSYNC R74 10K_NC DVALID 400 MHz 256MB(16M*16) Qimonda 1 1 1 0 500 MHz 256MB(16M*16) Hynix 1 1 0 1 500 MHz 256MB(16M*16) Qimonda 1 1 0 0 500 MHz 256MB(16M*16) Samsung 1 0 1 1 +3.3V_DELAY R644 R648 R659 R54 10K_DIS 10K_NC 10K_NC 10K_NC RAM_CFG0 RAM_CFG1 RAM_CFG2 RAM_CFG3 VRAM SIZE +1.8V_RUN R667 R82 R669 R674 10K_DIS 10K_NC 10K_DIS 10K_DIS RAM_TYPE_CFG0 RAM_TYPE_CFG1 RAM_TYPE_CFG2 RAM_TYPE_CFG3 VRAM TYPE C +3.3V_DELAY R651 R661 R650 R662 R645 R660 R646 R649 R58 R148 R61 R666 1 RAM_TYPE_CFG0 RAM_TYPE_CFG1 RAM_TYPE_CFG2 RAM_TYPE_CFG3 10K_DIS GPIO0 10K_DIS GPIO1 10K_NC GPIO2 10K_NC GPIO3 10K_NC GPIO4 10K_NC GPIO5 10K_NC GPIO6 10K_NC HDMI_HD_EN 10K_NC GPIO10 10K_DIS ATI_VGAHSYNC 10K_DIS GFX_CLKREQ# TEMP_FAIL# 2 10K_NC GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 R664 31 ATI_PANEL_BKEN 10K_NC R719 GPIO_23_CLKREQB DRIVES LOW DURING RESET 0_DISATI_PANEL_BKEN_R HDMI_HD_EN RAM_CFG3 GPIO10 RAM_CFG0 RAM_CFG1 RAM_CFG2 11 R665 1 50 GFX_CORE_CNTRL 0_DIS 2 T95 CLK_VGA_27M_SS_R 22 THERMAL_INT# R663 1 0_NC 2 20 TEMP_FAIL# PAD T95 1 R647 TEMP_FAIL# 2 0_DIS T4 PAD T4 20 BB_ENA T5 GFX_CLKREQ# R57 R119 1 2 10K_DIS TEMP_FAIL# T8 T6 T9 T12 T11 T7 T10 T96 T97 T99 T98 1K_DIS +1.8V_RUN B R99 499R/F_DIS PLACE VREF DIVIDER AND CAP CLOSE TO ASIC R95 249R_DIS C94 100nF_DIS R658 1 0_NC 2 CLK_VGA_27M_SS_R VIP / I2C TXCAM_DPA0P TXCAP_DPA0N AN9 AN10 ATI_HDMI_CLK- 25 ATI_HDMI_CLK+ 25 TX0M_DPA1P TX0P_DPA1N AR10 AP10 ATI_HDMI_TX0-_R 25 ATI_HDMI_TX0+_R 25 TX1M_DPA2P TX1P_DPA2N AR11 AP11 ATI_HDMI_TX1-_R 25 ATI_HDMI_TX1+_R 25 ATI_HDMI_TX2-_R 25 ATI_HDMI_TX2+_R 25 AM9 AL9 VHAD_0 VHAD_1 TX2M_DPA3P TX2P_DPA3N AR12 AP12 AJ9 VPHCTL TXCBM_DPB0P TXCBP_DPB0N AR14 AP14 TX3M_DPB1P TX3P_DPB1N AR15 AP15 AL7 AK7 VPCLK0 VIPCLK AM7 PSYNC AJ7 DVALID TX4M_DPB2P TX4P_DPB2N AR16 AP16 AK6 AM6 SDA SCL TX5M_DPB3P TX5P_DPB3N AR17 AP17 AN8 AP8 AG1 AH3 AH2 AH1 AJ3 AJ2 AJ1 AK2 AK1 AL3 AL2 AL1 AM3 AM2 AN2 AP3 AR3 AN4 AR4 AP4 AN5 AR5 AP5 AP6 AR6 AN7 AP7 AR7 DVPCNTL__MVP_0 DPA_PVDD DVPCNTL__MVP_1 DPA_PVSS DVPCNTL_0 INTEGRATED DVPCNTL_1 DPB_PVDD TMDS/DP DVPCNTL_2 DPB_PVSS DVPCLK DVPDATA_0 DPB_VDDR_1 DVPDATA_1 MULTI_GFX DPB_VDDR_2 DVPDATA_2 EXTERNAL DPA_VDDR_3 DVPDATA_3 TMDS DPA_VDDR_4 DVPDATA_4 DVPDATA_5 DPB_VSSR_1 DVPDATA_6 DPB_VSSR_2 DVPDATA_7 DPB_VSSR_3 DVPDATA_8 DPB_VSSR_4 DVPDATA_9 DPB_VSSR_6 DVPDATA_10 DPA_VSSR_5 DVPDATA_11 DPA_VSSR_7 DVPDATA_12 DPA_VSSR_8 DVPDATA_13 DPA_VSSR_9 DVPDATA_14 DPA_VSSR_10 DVPDATA_15 DVPDATA_16 DP_CALR DVPDATA_17 NC_TPVDDC DVPDATA_18 NC_TPVSSC DVPDATA_19 HPD1 DVPDATA_20 DVPDATA_21 DVPDATA_22 R DVPDATA_23 RB AM14 AL14 AG2 AF2 AF1 AE3 AE2 AE1 AD3 AD2 AD1 AD5 AD4 AC3 AC2 AC1 AB3 AB2 AB1 AF5 AF4 AG4 AG3 AD9 AD8 AD7 AB4 AB6 AB7 AB9 AA9 AF8 AF7 AG5 AP9 AR9 AP13 AR13 AD12 GPIO_0 GPIO_1 GENERAL GPIO_2 PURPOSE GPIO_3 I/O GPIO_4 GPIO_5 GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16_SSIN GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BBEN GPIO_22_ROMCSB GPIO_23_CLKREQB GPIO_24_JMODE GPIO_25_TDI GPIO_26_TCK GPIO_27_TMS GPIO_28_TDO GEN_A GEN_B GEN_C GEN_D_HPD4 GEN_E GEN_F GEN_G DAC1 DAC2 AR30 AP30 B BB AR29 AP29 HSYNC VSYNC AN29 AN30 RSET AN31 AVDD AR32 AVSSQ AP32 VDD1DI VSS1DI AR28 AP28 R2 R2B AM19 AL19 G2 G2B AM18 AL18 B2 B2B AM17 AL17 C Y COMP AK19 AK18 AK17 V2SYNC H2SYNC AL15 AM15 A2VDD 2 R694 1 0_DIS ATI_VGAHSYNC DDC2CLK ATI_VGA_GRN 27 ATI_VGA_BLU ATI_VGA_BLU 27 ATI_VGAHSYNC 27 ATI_VGAVSYNC 27 1 499/F_DIS ATI_VGA_BLU ATI_VGA_GRN ATI_VGA_RED +AVDD DIS only R698 R696 150/F_DIS R695 150/F_DIS 150/F_DIS +VDD1DI R695 R696 Layout Note: Place 150 ohm termination resistors close to ATI CHIP. R698 B +A2VDDQ AM29 AL29 ATI_VGA_RED 27 ATI_VGA_GRN 1 0_DIS A2VSSQ AJ21 DPLL_VDDC 2 R700 2R166 ATI_VGA_RED 1 0_DIS +A2VDD R2SET XTALIN XTALOUT 2 R701 AL21 VDD2DI VSS2DI AG19 C AK21 PCIE_PVDD +DPLL_VDDC ATI_HDMI_DET 25 MMST3904-7-F_DIS R85 10K_DIS AM21 DDC1DATA DDC1CLK MMST3904-7-F_DIS Q82 2 R112 150/F_DIS A2VDDQ DDC DP AUX DDC2DATA R90 10K_DIS Q83 2 PLACE OR RESISTORS CLOSE TO ASIC DPLL_PVDD DPLL_PVSS PLL CLOCKS R135 10K_DIS AR31 AP31 AM35 MPVDD MPVSS +DPA_VDDR AG15 AH18 AG18 AG6 +PCIE_PVDD A14 B15 +3.3V_DELAY +DPB_VDDR AN18 AP18 AR18 AN16 AN17 AN15 AN11 AN12 AN13 AN14 +DPLL_PVDD AR33 AP33 +TPVDD AN19 AN20 AP19 AR19 AH22 AG22 XTAIN XTAOUT D AH17 AG17 G GB VREFG HDMI CONN +VDD2DI 2 ATI_LCD_DDCDAT ATI_LCD_DDCCLK R205 1 715/F_DIS ATI_LCD_DDCDAT ATI_LCD_DDCCLK 26 26 R141 2 R165 2 1 2.2K_DIS 1 2.2K_DIS +3.3V_DELAY LVDS AJ15 AH15 DDC3DATA_DP3_AUXN DDC3CLK_DP3_AUXP AJ5 AJ4 DDC4DATA_DP4_AUXN DDC4CLK_DP4_AUXP AH14 AG14 ATI_HDMI_SDA 25 ATI_HDMI_SCL 25 HDMI 1 17 CLK_VGA_27M_SS T5 PAD PAD PADT8 PADT6 PADT9 PADT12 PADT11 PADT7 PADT10 PADT96 PADT97 T99 T98 VIP_0 VIP_1 VIP_2 VIP_3 VIP_4 VIP_5 VIP_6 VIP_7 AR20 AP20 +MPVDD R643 0_NC 2 1 22 OSC_SPREAD PAD AM12 AL12 AJ12 AH12 AM10 AL10 AJ10 AH10 3 0 1 0 3 X 1 128MB R709 100/F_DIS 1 R713 2 R714 22 OSC_OUT 0_DIS 2 1 120/F_DIS R706 CLK_VGA_27M_NSS_R 1 0_NC 2 R699 1 0_NC 2 Y3 1 A 2 R652 10K_NC 22 VGA_THERMDN 22 VGA_THERMDP TS_FDO AK4 AM4 DMINUS DPLUS THERMAL ATI_CRT_DAT_DDC 27 ATI_CRT_CLK_DDC 27 CRT 2 17 CLK_VGA_27M_NSS AG21 M86-LP_DIS R652 A 27MHZ_NC 1M_NC 1 C797 18P_NC 50 2 2 1 R147 C778 18P_NC 50 Title QUANTA COMPUTER VGA-G86GLM (VIDEO) 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 19 of 62 5 4 3 2 1 U43E Part 6 of 7 PART 5 OF 7 C706 10uF_DIS VDDR1_1 VDDR1_2 VDDR1_3 VDDR1_4 VDDR1_5 VDDR1_6 VDDR1_7 VDDR1_8 VDDR1_9 VDDR1_10 VDDR1_11 VDDR1_12 VDDR1_13 VDDR1_14 VDDR1_15 VDDR1_16 VDDR1_17 VDDR1_18 VDDR1_19 VDDR1_20 VDDR1_21 VDDR1_22 VDDR1_23 VDDR1_24 VDDR1_25 VDDR1_26 VDDR1_27 VDDR1_28 VDDR1_29 10uF_DIS C168 1U_DIS C122 1uF_DIS C180 1uF_DIS C103 1uF_DIS C113 1uF_DIS C152 1uF_DIS C133 1uF_DIS C147 1uF_DIS C50 1uF_DIS C63 1uF_DIS C52 1uF_DIS C90 1uF_DIS +VDD_CT AA11 AB11 AD10 AF10 VDD_CT_1 VDD_CT_2 VDD_CT_3 VDD_CT_4 R11 R25 U11 U25 ( 3.3V @ 50MA VDDR3) AE14 AE15 AF12 AE17 +3.3V_DELAY C151 10uF_DIS C153 10uF_DIS C98 1uF_DIS C97 1uF_DIS C165 C89 100nF_DIS 1uF_DIS C102 1uF_DIS C114 1uF_DIS +VDD_MEM_CLK0 +VDD_MEM_CLK1 C162 1uF_DIS VDDR3_1 VDDR3_2 VDDR3_3 VDDR3_4 AP2 AR2 VDDR4_1 VDDR4_2 AN1 AP1 VDDR5_1 VDDR5_2 A25 A32 VDDRHA_1 VDDRHA_2 B25 B32 VSSRHA_1 VSSRHA_2 B2 L1 VDDRHB_1 VDDRHB_2 C2 L2 VSSRHB_1 VSSRHB_2 +VDD_MEM_CLK2 +VDD_MEM_CLK3 +1.8V_RUN VDD_CT_5 VDD_CT_6 VDD_CT_7 VDD_CT_8 W13 AA13 BBN_1 BBN_2 U13 V13 BBP_1 BBP_2 PCI-Express C724 10uF_DIS P O W E R PCIE_VDDR_1 PCIE_VDDR_2 PCIE_VDDR_3 PCIE_VDDR_4 PCIE_VDDR_5 PCIE_VDDR_6 PCIE_VDDR_7 PCIE_VDDR_8 AR34 AL33 AM33 AN33 AN34 AN35 AP34 AP35 +PCIE_VDDR PCIE_VDDC_1 PCIE_VDDC_2 PCIE_VDDC_3 PCIE_VDDC_4 PCIE_VDDC_5 PCIE_VDDC_6 PCIE_VDDC_7 PCIE_VDDC_8 PCIE_VDDC_9 PCIE_VDDC_10 PCIE_VDDC_11 PCIE_VDDC_12 R26 U26 V25 V26 W25 W26 AA25 AD26 AF26 AA26 AB25 AB26 +PCIE_VDDC VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDDC_23 VDDC_24 VDDC_25 VDDC_26 VDDC_27 VDDC_28 VDDC_29 VDDC_30 VDDC_31 VDDC_32 VDDC_33 VDDC_34 VDDC_35 VDDC_36 VDDC_37 VDDC_38 VDDC_39 VDDC_40 VDDC_41 VDDC_42 VDDC_43 VDDC_44 N13 N15 N18 N21 N23 P14 P17 P19 P22 V18 V21 V23 W14 W17 W19 W22 AA15 AA18 AA21 AA23 AB14 AB17 AB19 AB22 AC13 AC15 AC18 AC21 AC23 AE18 AE22 AE19 AE21 R13 R15 R18 R21 R23 U14 U17 U19 U22 V15 W11 VDDCI_1 VDDCI_2 VDDCI_3 VDDCI_4 M12 M24 P11 P25 Core D1 A8 A12 A16 A20 A24 A28 B1 H1 H35 L18 L19 L21 L22 M10 M35 P10 T1 Y1 B35 M1 D35 K10 K12 K24 K26 L14 L15 L17 C215 C725 10uF_DIS I/O Internal +BBP C107 C106 1uF_DIS 1uF_DIS D +VCC_GFX_CORE C721 10uF_DIS C104 1uF_DIS C135 1uF_DIS C146 1uF_DIS C154 1uF_DIS C68 10uF_DIS C161 1uF_DIS C108 1uF_DIS C105 1uF_DIS C158 1uF_DIS C694 10uF_DIS C157 1uF_DIS C156 1uF_DIS C155 1uF_DIS C132 1uF_DIS C722 10uF_DIS C130 1uF_DIS C129 1uF_DIS C131 1uF_DIS C111 1uF_DIS C67 10uF_DIS C159 1uF_DIS C145 1uF_DIS C134 1uF_DIS C126 1uF_DIS C L8 BLM15AG121SN1D_DIS C235 10uF_DIS C93 1uF_DIS C171 1uF_DIS C170 1uF_DIS M86-LP_DIS U43 B +BBP Q9 SI2303BDS-T1-E3_DIS 1 +1.8V_RUN 3 1 2 C42 1U_DIS 2 1 3 2 603 R49 10 Q9 C42 2 CORE GND R49 3 1 R45 10K_DIS Q10 +3.3V_RUN +3.3V_SUS Q20 3 5 2 R123 1 75K/F_DIS 3 4 Q19 2N7002W-7-F_DIS 2 U8 74AHCT1G08GW_NC C160 0.1U_DIS 1 R123 A 1 Q18 2N7002W-7-F_NC 2 3 2 19 TEMP_FAIL# R45 R125 R102 100K_NC A R125 100K_DIS +3.3V_SUS 1 M86-LP_DIS 2 U43 2 1 +3.3V_DELAY 1 100K_DIS+5V_RUN 2 Q10 2N7002W-7-F_DIS 1 19 BB_ENA Q20 SI2303BDS-T1-E3_DIS +VCC_GFX_CORE Q8 2N7002W-7-F_DIS Q8 3 MECH_1 MECH_2 MECH_3 A35 AR1 AR35 U43D +1.8V_RUN Back Bias P6 M9 M26 K28 M32 N14 N17 N19 N22 N33 N3 R5 U8 P13 P15 P18 P21 P23 P26 P29 P30 R1 U5 P9 R10 R14 R17 R19 R22 V3 AK9 U10 U15 U18 U21 U23 V7 W8 V10 V14 V17 V19 V22 V1 AK12 V9 W10 W15 W18 W21 W23 AA6 AA10 AA14 AA17 AA19 AA22 AB8 AB10 AB13 AB15 AB18 AB21 AB23 AC14 AC17 AC19 AC22 AF9 AD6 AB5 AD24 W5 AF6 AF14 AF21 AF22 AK10 AF17 AF18 AF19 AA3 AG12 AJ14 AH21 D4 AF15 AG10 AN6 AK15 AJ17 AJ18 AJ19 AF24 AN32 AK3 AN3 AR8 AM1 AK30 V11 Memory I/O Clock B VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 Memory I/O C A2 A34 C3 C5 A4 C18 A21 C23 C11 C13 C14 A18 A11 C26 C33 F35 R7 G10 F15 H17 G21 D29 A29 G1 F14 J15 E19 E22 E24 D7 G9 F26 G29 D33 M5 G4 E10 E12 F17 G18 G22 F30 J35 J18 H19 J21 F7 J12 J24 J26 K30 J32 F33 K6 K9 K14 K15 K17 K18 K19 K21 K22 M28 K3 L33 PCIE_VSS_1 PCIE_VSS_2 PCIE_VSS_3 PCIE_VSS_4 PCIE_VSS_5 PCIE_VSS_6 PCIE_VSS_7 PCIE_VSS_8 PCIE_VSS_9 PCIE_VSS_10 PCIE_VSS_11 PCIE_VSS_12 PCIE_VSS_13 PCIE_VSS_14 PCIE_VSS_15 PCIE_VSS_16 PCIE_VSS_17 PCIE_VSS_18 PCIE_VSS_19 PCIE_VSS_20 PCIE_VSS_21 PCIE_VSS_22 PCIE_VSS_23 PCIE_VSS_24 PCIE_VSS_25 PCIE_VSS_26 PCIE_VSS_27 PCIE_VSS_28 PCIE_VSS_29 PCIE_VSS_30 PCIE_VSS_31 PCIE_VSS_32 PCIE_VSS_33 PCIE_VSS_34 PCIE_VSS_35 PCIE_VSS_36 PCIE_VSS_37 PCIE_VSS_38 PCIE_VSS_39 PCIE_VSS_40 PCIE_VSS_41 PCIE_VSS_42 PCIE_VSS_43 PCI-Express GND D P33 P34 P35 R27 R28 R29 R32 R33 U29 U32 V29 V32 T33 V34 V35 W29 W32 W33 AA29 AA32 AB29 AB32 Y33 AB34 AB35 AC33 AD29 AD32 AF29 AF32 AD33 AF34 AF35 AG27 AG29 AG32 AG33 AJ29 AJ32 AH33 AL34 AL35 AK32 Q19 OPTIONAL RC NETWORK10 TO FINE TUNE POWER SEQUENCING C160 26,44,48,49,53 RUN_ON R105 0_DIS R120 0_DIS GFX_RUN_ON 50 Title C100 0.1U_DIS 25 603 5 QUANTA COMPUTER VGA-G86GLM (VIDEO) 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 20 of 62 1 5 4 2 2 1 TMDS LVDS +LVDDR +1.1V_GFX_PCIE R129 0_DIS +DPA_VDDR BLM15BD121SN1D_DIS C743 10uF_DIS L68 C745 100nF_DIS ( 1.1V @ 200MA EACH SINGLE LINK) 1uF_DIS C744 1 R129 3 +1.8V_RUN D +1.8V_RUN BLM18PG471SN1D_DIS C183 L12 +LVDDC C185 10uF_DIS C186 100nF_DIS 100nF_DIS +LPVDD C166 L11 (1.8V @ 400MA LVDDC,LVDDR) D L11 BLM15BD121SN1D_DIS C164 10uF_DIS C163 1uF_DIS (1.8V @ 30MA LPVDD) +1.1V_GFX_PCIE C150 10uF_DIS L10 100nF_DIS PLL_CLK +1.1V_GFX_PCIE +1.8V_RUN BLM15BD121SN1D_DIS C752 L69 BLM15BD121SN1D_DIS C244 L21 +DPLL_PVDD C753 10uF_DIS C754 1uF_DIS C257 1uF_DIS (1.8V @ 40MA DPLL_PVDD) +A2VDDQ C764 10uF_DIS C763 1uF_DIS 100nF_DIS C776 10uF_DIS C175 1uF_DIS C178 1uF_DIS C123 1uF_DIS C124 100nF_DIS (PCIE_VDDC 1.1V @ 1A ) +DPLL_VDDC (DPLL_VDDC 1.1V @ 100 MA) C184 100nF_DIS +3.3V_DELAY C109 100nF_DIS ( .95V-1.1V @ 345MA MPVDD) C +A2VDD BLM15BD121SN1D_DIS C771 10uF_DIS ( 1.8V @ 100MA VDD1DI) 1uF_DIS +MPVDD C110 1uF_DIS (1.8V @ 2MA A2VDDQ) DAC(CRT) +VDD1DI BLM15BD121SN1D_DIS C775 L74 C176 1uF_DIS BLM18PG471SN1D_DIS C101 L67 10uF_DIS L73 +1.8V_RUN C177 100nF_DIS 100nF_DIS BLM15BD121SN1D_DIS C765 C174 1uF_DIS ( 1.1V @ 200MA EACH SINGLE LINK) (1.8V @ 40MA PCIE_PVDD) +VCC_GFX_CORE L71 +PCIE_VDDC C245 10uF_DIS BLM15BD121SN1D_DIS C125 L9 10uF_DIS C +1.8V_RUN C148 1uF_DIS 100nF_DIS +PCIE_PVDD C248 10uF_DIS C149 100nF_DIS BLM18PG121SN1D_DIS L18 +1.8V_RUN +DPB_VDDR BLM15BD121SN1D_DIS C769 C770 100nF_DIS 1uF_DIS (3.3V @ 135MA A2VDD) +VDD2DI +1.8V_RUN +AVDD BLM15BD121SN1D_DIS L14 +1.8V_RUN C187 10uF_DIS C193 1uF_DIS 100nF_DIS C192 10uF_DIS C739 100nF_DIS C741 C738 1uF_DIS (1.8V @ 20 MA SINGLE LINK 1X4DP and 40mA for Dual-Link 2X4DP) B +1.8V_RUN +VDD_CT BLM15BD121SN1D_DIS C260 10uF_DIS L22 +1.8V_RUN PLACE ALL DECOUPLING AS CLOSE TO ASIC AS POSSIBLE +TPVDD BLM15BD121SN1D_DIS L65 (1.8V @ 65MA AVDD) BLM18PG471SN1D_DIS C810 L75 C95 100nF_DIS 1uF_DIS C173 +PCIE_VDDR 10uF_DIS C800 1uF_DIS B (VDD_CT 1.8V @ 110MA (VDD_CT) (1.8V @ 400MA PCIE_VDDR) C798 100nF_DIS MEM IO CLK +1.8V_RUN L79 +1.8V_RUN +VDD_MEM_CLK0 BLM15BD121SN1D_DIS C181 10uF_DIS C179 1uF_DIS C182 100nF_DIS C811 10uF_DIS C808 1uF_DIS C809 100nF_DIS +VDD_MEM_CLK1 BLM15BD121SN1D_DIS L78 (1.8V @ MA VDDRHA_1 INCLUDED IN VDDR1) (1.8V @ MA VDDRHA_2 INCLUDED IN VDDR1) A A +1.8V_RUN BLM15BD121SN1D_DIS C717 10uF_DIS L63 +1.8V_RUN +VDD_MEM_CLK2 C718 1uF_DIS C719 100nF_DIS +VDD_MEM_CLK3 BLM15BD121SN1D_DIS C65 10uF_DIS L6 5 C72 1uF_DIS C66 100nF_DIS (1.8V @ MA VDDRHB_1 INCLUDED IN VDDR1) (1.8V @ MA VDDRHB_2 INCLUDED IN VDDR1) 4 Title QUANTA COMPUTER VGA-G86GLM (VIDEO) 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 21 of 62 5 4 3 2 1 U43C U43G Part 3 of 7 23 CKEA0 23 CKEA1 CKEA0 CKEA1 23 CSA0_0# 23 CSA1_0# CSA0_0# CSA1_0# CLKA0 CLKA0# 23 CLKA0 23 CLKA0# CLKA1 CLKA1# 23 CLKA1 23 CLKA1# QSA#[7..0] 23 QSA#[7..0] QSA[7..0] 23 QSA[7..0] DQMA#[7..0] 23 DQMA#[7..0] MDA[63..0] 23 MDA[63..0] MAA[11..0] 23 MAA[11..0] A_BA0 A_BA1 23 A_BA0 23 A_BA1 A_A12 23 A_A12 PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC +1.8V_RUN C R193 100/F_DIS C242 +1.8V_RUN 100nF_DIS R194 100R/F_DIS R740 100/F_DIS R741 100R/F_DIS C815 100nF_DIS N35 N34 AM34 C27 B28 B27 G26 F27 E27 D27 J27 E29 C30 E26 A27 G27 D26 C28 B29 DQMAb_0 DQMAb_1 DQMAb_2 DQMAb_3 DQMAb_4 DQMAb_5 DQMAb_6 DQMAb_7 M29 K33 G30 E33 C22 H21 C17 G17 QSA_0 QSA_1 QSA_2 QSA_3 QSA_4 QSA_5 QSA_6 QSA_7 M30 K34 G31 E34 B22 F21 B17 D17 QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7 QSA_0B QSA_1B QSA_2B QSA_3B QSA_4B QSA_5B QSA_6B QSA_7B M31 K35 G32 E35 A22 E21 A17 E17 QSA#0 QSA#1 QSA#2 QSA#3 QSA#4 QSA#5 QSA#6 QSA#7 ODTA0 ODTA1 C31 C25 ODTA0 ODTA1 CLKA0 CLKA1 A33 A26 CLKA0 CLKA1 24 ODTB0 24 ODTB1 ODTB0 ODTB1 24 RASB0# 24 RASB1# RASB0# RASB1# 24 CASB0# 24 CASB1# CASB0# CASB1# 24 WEB0# 24 WEB1# WEB0# WEB1# 24 CKEB1 CKEB0 CKEB1 24 CSB0_0# 24 CSB1_0# CSB0_0# CSB1_0# 24 CLKB0 24 CLKB0# CLKB0 CLKB0# NC for 16M x16 DDR2 24 CKEB0 A_BA0 A_BA1 DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63 CLKB1 CLKB1# 24 CLKB1 24 CLKB1# QSB#[7..0] 24 QSB#[7..0] QSB[7..0] 24 QSB[7..0] DQMB#[7..0] 24 DQMB#[7..0] MDB[63..0] 24 MDB[63..0] MAB[11..0] 24 MAB[11..0] CLKA0b CLKA1b B33 B26 CLKA0# CLKA1# RASA0b RASA1b A31 D24 RASA0# RASA1# CASA0b CASA1b C32 H26 CASA0# CASA1# CSA0b_0 CSA0b_1 A30 B30 CSA0_0# CSA1b_0 CSA1b_1 G24 H24 CSA1_0# MVREFDA MVREFSA CKEA0 CKEA1 B31 F24 CKEA0 CKEA1 NC_1 WEA0b WEA1b C29 D22 WEA0# WEA1# 24 B_BA0 24 B_BA1 B_BA0 B_BA1 24 B_A12 B_A12 +1.8V_RUN PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC R96 100R_DIS 100R_DIS R107 1K_DIS R146 100nF_DIS C99 NC for 16M x16 DDR2 +1.8V_RUN M86-LP_DIS H15 G14 E14 D14 H12 G12 F12 D10 B13 C12 B12 B11 C9 B9 A9 B8 J10 H10 F10 D9 G7 G6 F6 D6 C8 C7 B7 A7 B5 A5 C4 B4 M3 M2 N2 N1 R3 R2 T3 T2 M8 M7 P5 P4 R9 R8 R6 U4 U3 U2 U1 V2 Y3 Y2 AA2 AA1 U9 U7 U6 V4 W9 W7 W6 W4 DQB_0 DQB_1 DQB_2 DQB_3 DQB_4 DQB_5 DQB_6 DQB_7 DQB_8 DQB_9 DQB_10 DQB_11 DQB_12 DQB_13 DQB_14 DQB_15 DQB_16 DQB_17 DQB_18 DQB_19 DQB_20 DQB_21 DQB_22 DQB_23 DQB_24 DQB_25 DQB_26 DQB_27 DQB_28 DQB_29 DQB_30 DQB_31 DQB_32 DQB_33 DQB_34 DQB_35 DQB_36 DQB_37 DQB_38 DQB_39 DQB_40 DQB_41 DQB_42 DQB_43 DQB_44 DQB_45 DQB_46 DQB_47 DQB_48 DQB_49 DQB_50 DQB_51 DQB_52 DQB_53 DQB_54 DQB_55 DQB_56 DQB_57 DQB_58 DQB_59 DQB_60 DQB_61 DQB_62 DQB_63 B14 A13 AM30 AA8 AA7 AA5 AH19 MEMORY INTERFACE B 23 WEA0# 23 WEA1# WEA0# WEA1# MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 A_A12 MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8 MAA_9 MAA_10 MAA_11 MAA_A12 MAA_BA2 MAA_BA0 MAA_BA1 MAB_0 MAB_1 MAB_2 MAB_3 MAB_4 MAB_5 MAB_6 MAB_7 MAB_8 MAB_9 MAB_10 MAB_11 MAB_A12 MAB_BA2 MAB_BA0 MAB_BA1 H2 H3 J3 J5 J4 J6 G5 J9 F3 F4 J1 J2 J7 F1 G2 G3 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 B_A12 DQMBb_0 DQMBb_1 DQMBb_2 DQMBb_3 DQMBb_4 DQMBb_5 DQMBb_6 DQMBb_7 D12 C10 E7 C6 P3 R4 W3 V8 DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 QSB_0 QSB_1 QSB_2 QSB_3 QSB_4 QSB_5 QSB_6 QSB_7 J14 B10 F9 B6 P2 P8 W2 V6 QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7 QSB_0B QSB_1B QSB_2B QSB_3B QSB_4B QSB_5B QSB_6B QSB_7B H14 A10 E9 A6 P1 P7 W1 V5 QSB#0 QSB#1 QSB#2 QSB#3 QSB#4 QSB#5 QSB#6 QSB#7 read strobe CASA0# CASA1# DQA_0 DQA_1 DQA_2 DQA_3 DQA_4 DQA_5 DQA_6 DQA_7 DQA_8 DQA_9 DQA_10 DQA_11 DQA_12 DQA_13 DQA_14 DQA_15 DQA_16 DQA_17 DQA_18 DQA_19 DQA_20 DQA_21 DQA_22 DQA_23 DQA_24 DQA_25 DQA_26 DQA_27 DQA_28 DQA_29 DQA_30 DQA_31 DQA_32 DQA_33 DQA_34 DQA_35 DQA_36 DQA_37 DQA_38 DQA_39 DQA_40 DQA_41 DQA_42 DQA_43 DQA_44 DQA_45 DQA_46 DQA_47 DQA_48 DQA_49 DQA_50 DQA_51 DQA_52 DQA_53 DQA_54 DQA_55 DQA_56 DQA_57 DQA_58 DQA_59 DQA_60 DQA_61 DQA_62 DQA_63 write strobe 23 CASA0# 23 CASA1# D Part 4 of 7 P27 P28 P31 P32 M27 K29 K31 K32 M33 M34 L34 L35 J33 J34 H33 H34 K27 J29 J30 J31 F29 F32 D30 D32 G33 G34 G35 F34 D34 C34 C35 B34 C24 B24 B23 A23 C21 B21 C20 B20 J22 H22 F22 D21 J19 G19 F19 D19 C19 B19 A19 B18 C16 B16 C15 A15 H18 F18 E18 D18 J17 G15 E15 D15 MEMORY INTERFACE A 23 RASA0# 23 RASA1# RASA0# RASA1# MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63 read strobe ODTA0 ODTA1 write strobe 23 ODTA0 23 ODTA1 D B_BA0 B_BA1 NC for 16M x16 DDR2 ODTB0 ODTB1 ODTB0 ODTB1 D2 K5 CLKB0 CLKB1 A3 K1 CLKB0 CLKB1 CLKB0b CLKB1b B3 K2 CLKB0# CLKB1# RASB0b RASB1b D3 K7 RASB0# RASB1# CASB0b CASB1b C1 K4 CASB0# CASB1# CSB0b_0 CSB0b_1 E1 E2 CSB0_0# CSB1b_0 CSB1b_1 L3 M4 CSB1_0# MVREFDB MVREFSB CKEB0 CKEB1 E3 K8 CKEB0 CKEB1 TESTEN TEST_MCLK TEST_YCLK MEMTEST PLLTEST WEB0b WEB1b F2 M6 WEB0# WEB1# DRAM_RST C NC for 16M x16 DDR2 AA4 M86-LP_DIS U43 +1.8V_RUN R672 100R_DIS R56 4.7K_DIS +3.3V_DELAY R69 R67 R68 4.7K_DIS 240R_DIS 4.7K_DIS 2 +3.3V_DELAY +3.3V_DELAY SDATA 6 ALERT# 5 GND D- 3 THERM# 4 1 D+ 2 VGA_THERMDN 19 MB_THERM# 1 C39 R44 2 1 10K_DIS THERMAL_INT# R43 2 1 10K_DIS +3.3V_DELAY 10K_NC 19 OSC_OUT C34 0.1U_DIS R114 1 2 MB_THERM# R72 10K_NC 50 R115 ADM1032ARM_DIS +3.3V_RUN If U7070, the discrete spread spectrum chip is not used, then pop R8328 in order to pull-down BXTALOUT for EMI reasons. C39 2200P_DIS 19 OSC_SPREAD 10 0_NC 2 R73 10K_NC U6 1 XIN/CLKIN XOUT 8 2 VSS VDD 7 +3VL 3 SO PD# 6 REFCLK 5 C73 10U_NC 805 10 4 SSCLK L7 1 THERMAL_INT# 19 THERMAL_INT# 1 2 2N7002W-7-F_DIS 7 VDD 2 31,37 SMBDAT2 3 SCLK Spread Spectrum VGA_THERMDP 19 2 U1 8 Q7 1 1 2 2N7002W-7-F_DIS B C735 100nF_DIS R39 4.7K_DIS 2 R35 4.7K_DIS R675 100R_DIS THERMAL MONITOR 1 Q6 1 2 3 31,37 SMBCLK2 1 B +3.3V_RUN BLM18AG121SN1D_NC C76 0.1U_NC 10 P1819GF-08SR_NC C34 S0 -1.75% (DOWN) 0 0.85% (CENTER) 1 A A Title QUANTA COMPUTER VGA-M82-S (PCIe) 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 22 of 62 5 4 603 2 2 C120 0.1U_DIS C784 0.1U_DIS 25 C121 0.1U_DIS 10 C747 0.1U_DIS 10 2 1 2 1 1 C787 10U_DIS 2 C788 10U_DIS 1 10 6.3 6.3 10 603 603 603 C115 0.1U_DIS C786 1U_DIS C774 0.1U_DIS C783 0.01U_DIS 25 C772 0.1U_DIS C C773 0.1U_DIS C750 0.1U_DIS C714 0.1U_DIS 10 2 1 2 2 B 1 2 VREF_A3 VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 A1 E1 J9 M9 R1 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 +1.8V_RUN R50 499/F_DIS C55 0.1U_DIS 1 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 C53 470P_DIS R55 499/F_DIS 2 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 R52 56_DIS 50 1 A3 E3 J3 N1 P9 10 10 C58 10U_DIS 1 10 10 C57 10U_DIS 6.3 6.3 10 603 603 603 C117 0.1U_DIS 10 10 C56 1U_DIS C59 0.1U_DIS 10 C60 0.01U_DIS 25 1 25 J2 10 +1.8V_RUN 2 C748 0.01U_DIS VREF 2 VSSDL A2 E2 L1 R3 R7 R8 1 VDDL J7 F7 E8 NC1 NC2 NC3 NC4 NC5 NC6 1 J1 C62 0.1U_DIS LDQS LDQS# QSA6 QSA#6 C119 0.1U_DIS 2 603 2 CLK CLK# QSA7 QSA#7 1 10 603 10 J8 K8 B7 A8 2 6.3 603 C708 1U_DIS 1 C86 10U_DIS 6.3 C711 0.1U_DIS CLKA1 CLKA1# UDQS UDQS# 2 10 10 C709 10U_DIS RAS CAS WE CS CKE ODT 1 C716 0.1U_DIS C118 0.1U_DIS 1 1 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 UDM LDM K7 L7 K3 L8 K2 K9 R51 56_DIS 1 CLKA1 CLKA1# 1 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 +1.8V_RUN 2 VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 A1 E1 J9 M9 R1 R641 499/F_DIS 1 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 2 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 B3 F3 RASA1# CASA1# WEA1# CSA1_0# CKEA1 ODTA1 +1.8V_RUN 2 A3 E3 J3 N1 P9 R715 499/F_DIS C789 0.1U_DIS CLKA1 CLKA1# 2 VREF_A2 1 1 10 DQMA#7 DQMA#6 2 J2 RASA1# CASA1# WEA1# CSA1_0# CKEA1 ODTA1 22 22 R642 499/F_DIS 2 2 VREF 22 22 22 22 22 22 +1.8V_RUN 1 10 A2 E2 L1 R3 R7 R8 BA0 BA1 MDA50 MDA53 MDA51 MDA55 MDA52 MDA49 MDA54 MDA48 MDA58 MDA60 MDA56 MDA62 MDA61 MDA57 MDA63 MDA59 1 VSSDL C715 0.1U_DIS F7 E8 NC1 NC2 NC3 NC4 NC5 NC6 L2 L3 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 1 VDDL J7 2 1 C749 0.1U_DIS LDQS LDQS# QSA5 QSA#5 A_BA0 A_BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 2 J1 +1.8V_RUN QSA4 QSA#4 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 2 CLK CLK# B7 A8 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 1 J8 K8 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 10 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 2 CLKA1 CLKA1# UDQS UDQS# 1 CLKA1 CLKA1# VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 10 1 RAS CAS WE CS CKE ODT 2 UDM LDM K7 L7 K3 L8 K2 K9 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 +1.8V_RUN C198 0.1U_DIS 22 A_A12 2 B3 F3 RASA1# CASA1# WEA1# CSA1_0# CKEA1 ODTA1 10 2 DQMA#4 DQMA#5 10 1 BA0 BA1 MDA45 MDA42 MDA46 MDA47 MDA40 MDA41 MDA43 MDA44 MDA37 MDA34 MDA39 MDA32 MDA33 MDA38 MDA35 MDA36 2 RASA1# CASA1# WEA1# CSA1_0# CKEA1 ODTA1 22 22 B L2 L3 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 2 22 22 22 22 22 22 A_BA0 A_BA1 A_A12 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 2 C195 0.01U_DIS VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 1 10 603 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VREF_A1 U5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 1 22 10 A3 E3 J3 N1 P9 2 6.3 603 J2 A1 E1 J9 M9 R1 R705 499/F_DIS 1 6.3 C217 1U_DIS VREF +1.8V_RUN 2 C218 10U_DIS NC1 NC2 NC3 NC4 NC5 NC6 1 C216 10U_DIS 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 VSSDL C167 0.1U_DIS 10 U41 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 VDDL J7 QSA3 QSA#3 A2 E2 L1 R3 R7 R8 2 C785 0.1U_DIS 10 C MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 CLK CLK# J1 F7 E8 1 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J8 K8 LDQS LDQS# D 1 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 CLKA0 CLKA0# UDQS UDQS# 2 VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 RAS CAS WE CS CKE ODT +1.8V_RUN R128 499/F_DIS C169 0.1U_DIS K7 L7 K3 L8 K2 K9 QSA1 QSA#1 1 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 CLKA0 CLKA0# 1 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 +1.8V_RUN RASA0# CASA0# WEA0# CSA0_0# CKEA0 ODTA0 B7 A8 2 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VREF_A0 UDM LDM G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 2 J2 A1 E1 J9 M9 R1 RASA0# CASA0# WEA0# CSA0_0# CKEA0 ODTA0 22 22 50 BA0 BA1 B3 F3 1 10 1 MDA30 MDA25 MDA28 MDA27 MDA24 MDA31 MDA26 MDA29 MDA12 MDA10 MDA15 MDA8 MDA9 MDA14 MDA11 MDA13 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 1 VREF C197 470P_DIS L2 L3 DQMA#1 DQMA#3 2 VSSDL A3 E3 J3 N1 P9 22 22 22 22 22 22 2 VDDL J7 R133 499/F_DIS 1 10 CLK CLK# J1 R164 56_DIS +1.8V_RUN 2 2 C172 0.1U_DIS 1 C61 0.1U_DIS 1 2 +1.8V_RUN NC1 NC2 NC3 NC4 NC5 NC6 A2 E2 L1 R3 R7 R8 R163 56_DIS A_BA0 A_BA1 1 J8 K8 QSA0 QSA#0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 2 CLKA0 CLKA0# F7 E8 2 CLKA0 CLKA0# LDQS LDQS# 1 22 22 UDQS UDQS# 1 RAS CAS WE CS CKE ODT M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 A_A12 2 K7 L7 K3 L8 K2 K9 1 RASA0# CASA0# WEA0# CSA0_0# CKEA0 ODTA0 QSA2 QSA#2 2 RASA0# CASA0# WEA0# CSA0_0# CKEA0 ODTA0 B7 A8 2 UDM LDM 1 B3 F3 1 DQMA#2 DQMA#0 22 CLKA0 CLKA0# 2 BA0 BA1 2 L2 L3 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 Hynix: AKD5JG-TW09 Samsung: AKD5JG-T507 2 22 22 22 22 22 22 A_BA0 A_BA1 A_A12 GDDR2 16MX16 MEMORY MDA7 MDA1 MDA6 MDA5 MDA0 MDA3 MDA4 MDA2 MDA21 MDA22 MDA19 MDA20 MDA17 MDA18 MDA16 MDA23 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 1 22 A_BA[1..0] 22 A_BA[1..0] D DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 1 QSA[7..0] 22 QSA[7..0] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 2 DQMA#[7..0] 22 DQMA#[7..0] M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 1 22 QSA#[7..0] MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 1 QSA#[7..0] 2 MAA[11..0] 22 MAA[11..0] 2 U44 1 22 MDA[63..0] 3 U10 MDA[63..0] C116 0.1U_DIS 10 A A Title QUANTA COMPUTER VGA-M82-S (VRAM) 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 23 of 62 5 4 603 2 2 C712 0.1U_DIS C45 0.1U_DIS 25 C64 0.1U_DIS 2 1 2 1 1 C693 10U_DIS 2 C686 10U_DIS 1 10 6.3 6.3 10 603 603 603 C46 0.1U_DIS C691 1U_DIS C684 0.1U_DIS C682 0.01U_DIS 25 C713 0.1U_DIS C C699 0.1U_DIS 2 C697 0.1U_DIS 10 25 C703 0.1U_DIS C702 0.1U_DIS 10 2 2 2 R41 499/F_DIS B 1 2 VREF_B3 2 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 A1 E1 J9 M9 R1 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 +1.8V_RUN R40 499/F_DIS C38 0.1U_DIS 1 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 C33 470P_DIS 50 1 A3 E3 J3 N1 P9 R37 56_DIS 10 C24 10U_DIS 1 10 10 1 J2 10 +1.8V_RUN C19 10U_DIS 2 C695 0.01U_DIS VREF 2 VSSDL A2 E2 L1 R3 R7 R8 1 VDDL J7 F7 E8 NC1 NC2 NC3 NC4 NC5 NC6 1 J1 C48 0.1U_DIS LDQS LDQS# QSB7 QSB#7 10 6.3 6.3 10 603 603 603 C704 0.1U_DIS 10 10 C29 1U_DIS C51 0.1U_DIS 10 C47 0.01U_DIS 25 1 603 10 CLK CLK# QSB6 QSB#6 C49 0.1U_DIS 2 10 603 10 J8 K8 B7 A8 1 6.3 603 C698 1U_DIS 1 C688 10U_DIS 6.3 C705 0.1U_DIS CLKB1 CLKB1# UDQS UDQS# 2 10 10 C690 10U_DIS RAS CAS WE CS CKE ODT 2 C692 0.1U_DIS C44 0.1U_DIS 1 1 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 UDM LDM K7 L7 K3 L8 K2 K9 1 CLKB1 CLKB1# 1 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 +1.8V_RUN 2 VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 A1 E1 J9 M9 R1 R636 499/F_DIS 1 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 2 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 B3 F3 RASB1# CASB1# WEB1# CSB1_0# CKEB1 ODTB1 +1.8V_RUN 2 A3 E3 J3 N1 P9 DQMB#6 DQMB#7 R33 56_DIS 1 VREF_B2 1 1 10 R630 499/F_DIS C689 0.1U_DIS CLKB1 CLKB1# 2 J2 RASB1# CASB1# WEB1# CSB1_0# CKEB1 ODTB1 22 22 R637 499/F_DIS BA0 BA1 MDB56 MDB62 MDB59 MDB63 MDB60 MDB57 MDB61 MDB58 MDB49 MDB52 MDB48 MDB55 MDB54 MDB51 MDB53 MDB50 2 VREF +1.8V_RUN 2 2 A2 E2 L1 R3 R7 R8 1 10 F7 E8 NC1 NC2 NC3 NC4 NC5 NC6 22 22 22 22 22 22 L2 L3 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 1 VSSDL C683 0.1U_DIS LDQS LDQS# QSB5 QSB#5 B_BA0 B_BA1 B_A12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 1 VDDL J7 2 1 C685 0.1U_DIS QSB4 QSB#4 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 2 J1 +1.8V_RUN B7 A8 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 2 CLK CLK# A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 10 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 1 J8 K8 VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 C20 0.1U_DIS 2 CLKB1 CLKB1# UDQS UDQS# 1 CLKB1 CLKB1# A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 +1.8V_RUN 10 1 RAS CAS WE CS CKE ODT 2 UDM LDM K7 L7 K3 L8 K2 K9 22 2 B3 F3 RASB1# CASB1# WEB1# CSB1_0# CKEB1 ODTB1 10 2 DQMB#4 DQMB#5 10 1 BA0 BA1 MDB46 MDB43 MDB47 MDB42 MDB41 MDB44 MDB40 MDB45 MDB37 MDB34 MDB39 MDB33 MDB32 MDB38 MDB35 MDB36 2 RASB1# CASB1# WEB1# CSB1_0# CKEB1 ODTB1 22 22 B L2 L3 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 2 22 22 22 22 22 22 B_BA0 B_BA1 B_A12 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 2 C23 0.01U_DIS VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 1 10 603 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VREF_B1 U3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 1 22 10 A3 E3 J3 N1 P9 2 6.3 603 J2 A1 E1 J9 M9 R1 R634 499/F_DIS 1 6.3 C40 1U_DIS VREF +1.8V_RUN 2 C37 10U_DIS NC1 NC2 NC3 NC4 NC5 NC6 1 C27 10U_DIS 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 VSSDL C696 0.1U_DIS 10 U38 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 VDDL J7 QSB1 QSB#1 A2 E2 L1 R3 R7 R8 2 C723 0.1U_DIS 10 C MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 CLK CLK# J1 F7 E8 1 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J8 K8 LDQS LDQS# D 1 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 CLKB0 CLKB0# UDQS UDQS# 2 VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 RAS CAS WE CS CKE ODT +1.8V_RUN R627 499/F_DIS C680 0.1U_DIS K7 L7 K3 L8 K2 K9 QSB3 QSB#3 1 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 CLKB0 CLKB0# 1 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 +1.8V_RUN RASB0# CASB0# WEB0# CSB0_0# CKEB0 ODTB0 B7 A8 2 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VREF_B0 UDM LDM G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 2 J2 A1 E1 J9 M9 R1 RASB0# CASB0# WEB0# CSB0_0# CKEB0 ODTB0 22 22 50 BA0 BA1 B3 F3 1 10 1 MDB15 MDB11 MDB14 MDB10 MDB9 MDB13 MDB8 MDB12 MDB29 MDB27 MDB31 MDB24 MDB25 MDB30 MDB26 MDB28 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 1 VREF C30 470P_DIS L2 L3 DQMB#3 DQMB#1 2 VSSDL A3 E3 J3 N1 P9 22 22 22 22 22 22 2 VDDL J7 R31 499/F_DIS 1 10 CLK CLK# J1 R38 56_DIS +1.8V_RUN 2 2 C710 0.1U_DIS 1 C75 0.1U_DIS 1 2 +1.8V_RUN NC1 NC2 NC3 NC4 NC5 NC6 A2 E2 L1 R3 R7 R8 R34 56_DIS B_BA0 B_BA1 1 J8 K8 QSB0 QSB#0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 2 CLKB0 CLKB0# F7 E8 2 CLKB0 CLKB0# LDQS LDQS# 1 22 22 UDQS UDQS# 1 RAS CAS WE CS CKE ODT M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 B_A12 2 K7 L7 K3 L8 K2 K9 1 RASB0# CASB0# WEB0# CSB0_0# CKEB0 ODTB0 QSB2 QSB#2 2 RASB0# CASB0# WEB0# CSB0_0# CKEB0 ODTB0 B7 A8 2 UDM LDM 1 B3 F3 1 DQMB#2 DQMB#0 22 CLKB0 CLKB0# 2 BA0 BA1 2 L2 L3 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 Hynix: AKD5JG-TW09 Samsung: AKD5JG-T507 2 22 22 22 22 22 22 B_BA0 B_BA1 B_A12 GDDR2 16MX16 MEMORY MDB2 MDB6 MDB3 MDB7 MDB4 MDB0 MDB5 MDB1 MDB17 MDB23 MDB18 MDB20 MDB21 MDB19 MDB22 MDB16 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 1 22 B_BA[1..0] 22 B_BA[1..0] D DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 1 QSB[7..0] 22 QSB[7..0] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 2 DQMB#[7..0] 22 DQMB#[7..0] M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 1 22 QSB#[7..0] MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 1 QSB#[7..0] 2 MAB[11..0] 22 MAB[11..0] 2 U37 1 22 MDB[63..0] 3 U2 MDB[63..0] C687 0.1U_DIS 10 A A Title QUANTA COMPUTER VGA-M82-S (VRAM) 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 24 of 62 5 4 3 2 1 DIS:CXCG900U000 / EXC24CG900U L72 ATI_HDMI_TX2-_L ATI_HDMI_TX2+_L UMA:CXCG240U000 / EXC24CG240U 1 4 2 3 HDMI_TX2HDMI_TX2+ EXC24CG900U_DU 150_NC HDMI_CLK_C C277 0.1U_NC UMA_HDMI_CLK-_R UMA_HDMI_TX0+_R R265 150_NC HDMI_TX0_C C287 0.1U_NC UMA_HDMI_TX0-_R UMA_HDMI_TX2+_R R124 0_UMA ATI_HDMI_TX2+_L HDMI_TX2+ UMA_HDMI_TX1+_R R271 150_NC HDMI_TX1_C C298 0.1U_NC UMA_HDMI_TX1-_R UMA_HDMI_TX2-_R UMA_HDMI_TX1+_R R122 R117 0_UMA 0_UMA ATI_HDMI_TX2-_L ATI_HDMI_TX1+_L HDMI_TX2HDMI_TX1+ UMA_HDMI_TX2+_R R273 150_NC HDMI_TX2_C C305 0.1U_NC UMA_HDMI_TX2-_R UMA_HDMI_TX1-_R UMA_HDMI_TX0+_R R113 R92 0_UMA 0_UMA ATI_HDMI_TX1-_L ATI_HDMI_TX0+_L HDMI_TX1HDMI_TX0+ UMA_HDMI_TX0-_R UMA_HDMI_CLK+_R R86 R106 0_UMA 0_UMA ATI_HDMI_TX0-_L ATI_HDMI_CLK+_L HDMI_TX0HDMI_CLK+ UMA_HDMI_CLK-_R R101 0_UMA ATI_HDMI_CLK-_L HDMI_CLK- 0_UMA 0_UMA ATI_HDMI_DET R671 10K_DIS HDMI_DDC_CLK HDMI_DDC_DATA HDMI_DDC_CLK HDMI_DDC_DATA UMA_HDMI_TX0+_R UMA_HDMI_TX0-_R UMA_HDMI_CLK+_R UMA_HDMI_CLK-_R SDVO_CTRLDATA HDMI_DET_L R278 EXT_SWING C SDI+ SDI- 42 16 +3.3V_RUN VCC VCC VCC VCC VCC 2 43 9 48 38 SDR+ SDR- GND GND 5 10 54 55 SDG+ SDG- AVCC AVCC 21 27 6 SDVOB_BLUE+ 6 SDVOB_BLUE- 57 58 SDB+ SDB- AGND AGND AGND 18 24 30 2 1 1 HDMI_DDC_CLK 3 1 ATI_HDMI_CLK-_L ATI_HDMI_CLK+_L HDMI_DDC_DATA PVCC1 17 PVCC1 C268 1U_UMA PVCC2 AVCC3.3 RSVD 31 32 33 PVCC2 AVCC33V VCC_PWR SDADDC SCLDDC 14 13 SCLROM SDAROM 44 TEST SPDIF/HDSDO LSCL LSDA LINT# 12 11 SVCC0 SVCC1 50 56 GND GND SGND SGND SPVCC 41 45 53 59 62 SPGND 63 L25 1 C280 C276 C273 C340 C288 100P_UMA 1000P_UMA0.1U_UMA 1000P_UMA10U_UMA L26 1 1 2 +1.8V_RUN BLM18AG121SN1D_UMA C270 C269 C266 0.1U_UMA 1000P_UMA1U_UMA 2 2 1 499/F_DIS 1 499/F_DIS ATI_HDMI_CLK+_L ATI_HDMI_CLK-_L C746 C742 0.1U_DIS 0.1U_DIS ATI_HDMI_CLK+ ATI_HDMI_CLK- R692 R688 2 2 1 499/F_DIS 1 499/F_DIS ATI_HDMI_TX2+_L ATI_HDMI_TX2-_L C768 C767 0.1U_DIS 0.1U_DIS ATI_HDMI_TX2+_R ATI_HDMI_TX2-_R R687 R685 2 2 1 499/F_DIS 1 499/F_DIS ATI_HDMI_TX1+_L ATI_HDMI_TX1-_L C762 C751 0.1U_DIS 0.1U_DIS ATI_HDMI_TX1+_R ATI_HDMI_TX1-_R R678 R673 2 2 1 499/F_DIS 1 499/F_DIS ATI_HDMI_TX0+_L ATI_HDMI_TX0-_L C737 C734 0.1U_DIS 0.1U_DIS ATI_HDMI_TX0+_R ATI_HDMI_TX0-_R 2 +3.3V_RUN BLM18AG121SN1D_UMA C311 C310 C323 0.1U_UMA 1000P_UMA1U_UMA +5V_RUN C317 C334 C343 0.1U_UMA 1000P_UMA10U_UMA +3.3V_RUN L32 1 2 +3.3V_RUN BLM18AG121SN1D_UMA C321 1000P_UMA 1 2 3 I/O I/O VN VP I/O I/O 6 5 4 HDMI_TX2+ HDMI_TX2- +5V_RUN SRV05-4_NC U7 HDMI_CLK+ 1 2 3 I/O I/O VN VP I/O I/O 6 5 4 HDMI_TX0+ HDMI_TX0- +5V_RUN SRV05-4_NC Reserve for EMI and close to HDMI CONN ATI_HDMI_DET 19 ATI_HDMI_TX1+_R 19 ATI_HDMI_TX1-_R 19 ATI_HDMI_TX0+_R ATI_HDMI_DET 19 +3.3V_DELAY ATI_HDMI_TX2+_R ATI_HDMI_TX2-_R ATI_HDMI_TX1+_R ATI_HDMI_TX1-_R ATI_HDMI_TX0+_R R66 4.7K_DIS ATI_HDMI_TX0-_R 2 19 ATI_HDMI_TX0-_R L31 HDAVCC 1 0_NC 2 Q12 2N7002W-7-F_DIS 19 ATI_HDMI_TX2+_R ICH_AZ_HDMI_SDOUT 11 ICH_AZ_HDMI_SYNC 11 ICH_AZ_HDMI_SDIN1 11 ICH_AZ_HDMI_RST# 11 0_UMA R681 1 2 19 ATI_HDMI_TX2-_R R285 0_NC 2 B 1 2 +1.8V_RUN BLM18AG121SN1D_UMA AVCC33V ICH_AZ_HDMI_SDIN1_L R680 1 L28 PVCC2 C283 C284 C282 100P_UMA 1000P_UMA10U_UMA 4.7k_UMA R682 R679 HDMI_CLK- 2 +1.8V_RUN BLM18AG121SN1D_UMA 11 ICH_AZ_HDMI_BITCLK R237 HDMI_CLKHDMI_CLK+ C275 10U_UMA SVCC SiI1392_UMA 2 3 U9 HDMI_TX1- 2 +3.3V_RUN BLM18AG121SN1D_UMA PVCC1 SPVCC 0_NC 2 Pop for ATI Graphic HDMI_TX1+ 1 0_NC 2 R677 1 1 4 Q109 FDV301N_DIS 2 +1.8V_RUN BLM18AG121SN1D_UMA C301 10U_UMA OVCC 64 R676 1 EXC24CG900U_DU 3 L27 C302 C286 C303 1000P_UMA 0.1U_UMA 1000P_UMA HDMI_TX0HDMI_TX0+ C Q108 FDV301N_DIS ATI_HDMI_SDA 1 2 3 L66 ATI_HDMI_SCL C272 C271 C348 C325 C324 C322 C335 C327 C351 100P_UMA 1000P_UMA1000P_UMA1000P_UMA1000P_UMA0.1U_UMA 0.1U_UMA 0.1U_UMA 10U_UMA AVCC 1 4 1 1 2 +1.8V_RUN BLM18PG181SN1_UMA L24 HDASYNC HDMI_SDA_R HDMI_SCL_R VCC_PWR A1 39 37 R234 1k_UMA 8 RESET# SDSCL SDSDA 34 4 3 15 HDMI_A1 EXT_RES 40 1 7 6 SDVO_CTRLCLK SDVO_CTRLDATA OVCC HDRST HDSDI 6,12,30,33,34,42 PLTRST# 6 SDVO_CTRLCLK 6 SDVO_CTRLDATA 1k_UMAEXT_RES 49 SDC+ SDC- HDBCLK HDAVCC R277 C71 0.1U_NC 0_NC 2 EXC24CG900U_DU L23 35 36 6 SDVOB_CLK+ 6 SDVOB_CLK- SiI1392 POLY SWITCH 1.1A_NC 1 0_NC 0_NC 2 R686 1 L64 ATI_HDMI_TX0-_L ATI_HDMI_TX0+_L +3.3V_DELAY 2 R845 R684 1 CS26802JB11 CS22202JB18 R80 2.2K_DU 2 L29 51 52 60 61 FOX_QJ1119L-NV13-8F 1 0 1 +5V_RUN 8 6 SDVOB_GREEN+ 6 SDVOB_GREEN- 6 SDVOB_RED+ 6 SDVOB_RED- B 46 47 2 F1 AVCC R76 2.2K_DU HDMI_TX1HDMI_TX1+ 2 +3.3V_RUN BLM18AG121SN1D_UMA ATI_HDMI_SCL ATI_HDMI_SDA 19 ATI_HDMI_SCL 19 ATI_HDMI_SDA A C326 0.1U_UMA 19 ATI_HDMI_CLK+ 19 ATI_HDMI_CLK- 1 S_INT+ S_INT- 0.1U_UMA 0.1U_UMA HDMI_DET 649/F_UMA DIS Used 6.8K UMA Used 2.2K 21 2 3 R100 4.7K_DIS 2 C349 C350 1K_UMA R843 D 1 4 EXC24CG900U_DU 1 6 SDVOB_INT+ 6 SDVOB_INT- HTPLG EXT_SWING 23 22 20 19 TX0+ TX0- TXC+ TXC- 29 28 26 25 TX1+ TX1- TX2+ TX2- U13 R233 HDMI_DET 16 ATI_HDMI_TX1-_L ATI_HDMI_TX1+_L 2 3.3k_UMA FM6 use 5.6K 0_NC 2 L70 2 D3 RB751V-40 3 R236 POP FOR UMA DEPOP FOR DIS SDVO_CTRLCLK 1 +3.3V_RUN 3.3k_UMA 0_NC 2 R690 1 8 1 R668 R670 +5V_RUN 2 HDMI_SCL_R HDMI_SDA_R 20 1 UMA_HDMI_TX1+_R UMA_HDMI_TX1-_R SHELL1 D2+ D2 Shield D2D1+ D1 Shield D1D0+ D0 Shield D0CK+ CK Shield CKCE Remote NC DDC CLK DDC DATA GND +5V HP DET SHELL2 2 8 UMA_HDMI_TX2+_R UMA_HDMI_TX2-_R R235 R689 1 JHD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2 D UMA_HDMI_CLK+_R R256 1 A ATI_HDMI_CLK+ QUANTA COMPUTER ATI_HDMI_CLK- Title SiI 1362 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 1 Rev 2B Sheet 25 of 62 5 4 3 2 1 D D 2 2 1 C677 0.01U 25 1 C672 0.01U 805 1 R592 100K_NC 1 R593 0_UMA 2 ENVDD +3.3V_ALW +15V_ALW 3 UMA_ENVDD 3 25 6 UMA_ENVDD C 0_NC 2 2 R603 1 3 EN_LCDVCC 2 1 Q62 2N7002W-7-F Q64 DDTC124EUA-7-F 1 2 31 LCDVCC_TST_EN Q63 2N7002W-7-F 3 D24 1 ENVDD R591 47K 2 2 R589 47K_NC Support the new imbeded diagnostics. 1 1 1 2 BAT54C T/R B 1 0_NC 1 0_NC 50 50 50 50 50 50 50 50 BACKLITE_DPST LCD_ACLK-_C BACKLITE_DPST 2 2 2 2 2 2 2 2 3.3P_NC 3.3P_NC 3.3P_NC 3.3P_NC 3.3P_NC 3.3P_NC 3.3P_NC 3.3P_NC LCD_A3LCD_A3+ LCD_ACLK-_C LCD_ACLK+_C LCD_A2LCD_A2+ LCD_A3- LCD_A1LCD_A1+ LCD_A3+ LCD_A2- LCD_A0LCD_A0+ LCD_A2+ LCD_DDCCLK LCD_DDCDAT LCD_A1LCD_A1+ +3.3V_RUN LCD_A0- +LCDVCC LCD_A0+ LCD_TST 31 +GFX_PWR_SRC FOR +5V_ALW GFX_PWR_SRC layout note: 40 mil trace for tube type 45 mil for white LED type 65mil for RGB LED type LCD_B0+ LCD_B1+ LCD_B2+ LCD_A0+ LCD_A1+ LCD_A2+ LCD_A3+ LCD_B3+ 1 +LVDDR C12 3.3P_NC +LVDDC C7 3.3P_NC TUNE EMI DESIGN 1 1 2 2 R5 0_NC LCD_BCLK+_C 50 +PWR_SRC +GFX_PWR_SRC 3 2 1 Q4 FDC658AP ATI_LCD_B0+ ATI_LCD_ACLKATI_LCD_ACLK+ ATI_LCD_A3ATI_LCD_A3+ ATI_LCD_A2ATI_LCD_A2+ ATI_LCD_A1ATI_LCD_A1+ ATI_LCD_A0ATI_LCD_A0+ +3.3V_RUN UMA_LCD_B1- 6 UMA_LCD_B1+ 6 UMA_LCD_B0- 6 C676 0.1U 1 ATI_LCD_B0- +LCDVCC UMA_LCD_B2+ 6 1 ATI_LCD_B1+ UMA_LCD_B2- 6 C675 0.047U C671 0.1U UMA_LCD_B0+ 6 10 UMA_LCD_ACLK-_C 6 10 10 UMA_LCD_ACLK+_C 6 UMA_LCD_A3- 6 UMA_LCD_A3+ 6 UMA_LCD_A2- 6 UMA_LCD_A2+ 6 C UMA_LCD_A1- 6 UMA_LCD_A1+ 6 UMA_LCD_A0- 6 Adress : A9H --Contrast AAH --Backlight UMA_LCD_A0+ 6 ATI_LCD_DDCCLK 19 UMA_LCD_DDCCLK 6 ATI_LCD_DDCDAT 19 UMA_LCD_DDCDAT 6 ATI & UMA DIFFERENT LVDS PATH C678 47P_NC 50 50 C679 47P_NC AJ26 AH26 LVDDR_1 LVDDR_2 10K_DIS Control VARY_BL AG7 DIGON AJ6 ATI_BIA_PWM R75 ATI_ENVDD_R 2 B 0_DIS 1 ENVDD AK27 AL27 LVDDC_1 LVDDC_2 AM24 AN28 AN21 AN24 AN25 AM22 AP21 AP26 AM27 AR21 AR26 AM26 AJ22 AJ24 LVSSR_1 LVSSR_2 LVSSR_3 LVSSR_4 LVSSR_5 LVSSR_6 LVSSR_7 LVSSR_8 LVSSR_9 LVSSR_10 LVSSR_11 LVSSR_12 LVSSR_13 LVSSR_14 AL22 AK22 LPVDD LPVSS TXCLK_UP TXCLK_UN TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N AK24 AL24 AN27 AN26 AP27 AR27 AG24 AH24 AK26 AL26 ATI_LCD_BCLK+ ATI_LCD_BCLKATI_LCD_B0+ ATI_LCD_B0ATI_LCD_B1+ ATI_LCD_B1ATI_LCD_B2+ ATI_LCD_B2ATI_LCD_B3+ ATI_LCD_B3- TXCLK_LP TXCLK_LN TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N AR22 AP22 AN23 AN22 AP23 AR23 AP24 AR24 AP25 AR25 ATI_LCD_ACLK+ ATI_LCD_ACLKATI_LCD_A0+ ATI_LCD_A0ATI_LCD_A1+ ATI_LCD_A1ATI_LCD_A2+ ATI_LCD_A2ATI_LCD_A3+ ATI_LCD_A3- 1 1 +LPVDD C17 0.1U 2 2 1 65mil 2 6 5 2 1 4 C18 0.1U ATI_LCD_B1- UMA_LCD_B3+ 6 U43F LCD_BCLK-_C R29 100K ATI_LCD_B2+ UMA_LCD_B3- 6 SMBCLK1 17,31,39 SMBDAT1 17,31,39 INVERTER_CBL_DET# 31 LCD_BAK# 31 PWM_VADJ 31 LCD_CBL_DET# 31 50 65mil LCD_DDCDAT BACKLITE_DPST ATI_LCD_B2- UMA_LCD_BCLK+_C 6 1 LCD_ACLK+_C Populate R65 for DPST implementation only. LCD_DDCCLK PART 7 OF 7 R4 0_NC Populate R341 for platform without DPST support. No Stuff for Discrete DSPT support due to back up plan. LCD_B0+ ATI_LCD_B3+ UMA_LCD_BCLK-_C 6 2 LCD_B0- 2 2 R109 ATI_BIA_PWM 2 R108 6 UMA_BIA_PWM R721 10K_UMA 1 1 1 1 1 1 1 1 LCD_B1+ LCD_ACLK-_C LCD_ACLK+_C ATI_LCD_B3- 2 LCD_B0LCD_B0+ 2 R726 10K_DIS C11 C10 C9 C6 C15 C14 C13 C8 LCD_B1- ATI_LCD_BCLK+ 1 LCD_B2+ LCD_B1LCD_B1+ +3.3V_RUN LCD_B0LCD_B1LCD_B2LCD_A0LCD_A1LCD_A2LCD_A3LCD_B3- LCD_B2- ATI_LCD_BCLK- 2 LCD_B2LCD_B2+ IPX_20323-050ED11 Shunt capacitors on LVDS for improving WWAN. UMA LCD_B3+ 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 0_DIS 2 0_UMA 2 1 2 C670 22U 1 3 1 R588 47 LCDVCC_ON LCD_B3LCD_B3+ R6 R604 R7 R605 R8 R606 R9 R607 R10 R608 R11 R609 R12 R610 R13 R611 R14 R612 R15 R613 R16 R614 R17 R615 R18 R616 R19 R617 R20 R618 R21 R619 R22 R620 R23 R621 R24 R622 R25 R623 R26 R624 R27 R625 2 4 2 2 6 5 2 1 R590 330K LCD_B3- 1 +LCDVCC Q65 FDC655BN LCD_BCLK+_C 2 +3.3V_RUN 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LCD_BCLK-_C LCD_BCLK+_C 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LVDS channel +15V_ALW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LCD_BCLK-_C J1 50 50 603 603 M86-LP_DIS C16 0.1U 50 A 2 A 603 3 1 R28 100K Q5 2N7002W-7-F 2 1 20,44,48,49,53 RUN_ON Title QUANTA COMPUTER LCD CONN & CK-SSCD 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 26 of 62 A B C D E 4 4 +5V_RUN 2 +3.3V_RUN D2 SDM10K45-7-F 3 3 1 2 1 2 1 D27 DA204U_NC 5V_CRT_REF 0_DIS 0_UMA RED_L 603 L5 BLM18BB750SN1D 603 L4 BLM18BB750SN1D RED PAD C32 10P C35 10P 2 11 2 2 C41 22P 1 BLUE 1 1 C36 22P 50 50 50 50 50 PAD 6 UMA_CRT_DAT_DDC 0_UMA 3 1 1 2 R626 ATI_CLK_DDC2_C 1 2 C700 10P_NC 50 L2 BLM18AG121SN1D JVGA_HS 603 U40 L1 BLM18AG121SN1D JVGA_VS VSYNC 603 74AHCT1G125GW 2 ATI & UMA H/V SWITCH 50 C22 10P_NC C26 10P_NC 50 50 1 10 2 1 R628 1 2 VGAVSYNC_R 1 4 2 0_DIS 0_UMA VGAVSYNC_L 2 50 1 R654 R653 C21 10P_NC HSYNC 1 5 19 ATI_VGAVSYNC 6 UMA_VGAVSYNC 2 Place near U24,U25 < 200 mil 1 G_CLK_DDC2_C 3 Q66 BSS138_NL 1 VGAHSYNC_R 10 2 2 4 R629 1 74AHCT1G125GW C707 0.1U 2 G_DAT_DDC2_C +3.3V_RUN U39 0_UMA 2 25 3 6 UMA_CRT_CLK_DDC 1 0_DIS 0_UMA VGAHSYNC_L 2 Suyin_070549FR015S512ZR RP48 2.2KX2 4 2 R32 Q67 BSS138_NL 1 19 ATI_VGAHSYNC 6 UMA_VGAHSYNC R657 R656 25 ATI_DAT_DDC2_C C701 0.01U 2 R655 1K 2 1 5 D1 SDM10K45-7-F 2 1 RP47 2.2KX2 1 ATI & UMA DATA/CLK SWITCH NEED ADD 0 OHM ON GM SIDE C681 0.01U 2 0_DIS ATI_CLK_DDC2_C 3 1 R30 M_ID2# T94 3 1 0_DIS ATI_DAT_DDC2_C 2 19 ATI_CRT_CLK_DDC R633 +CRT_VCC 4 2 19 ATI_CRT_DAT_DDC +CRT_VCC C43 10P 50 +3.3V_RUN +5V_RUN 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 1 1 1 C31 22P 2 R46 150/F 1 R42 150/F 2 R36 150/F L3 BLM18BB750SN1D 1 603 JVGA1 1 BLUE_L 3 M_SEN#_R T2 GREEN 2 0_DIS 0_UMA 2 19 ATI_VGA_BLU 6 UMA_VGA_BLU GREEN_L 2 R631 R632 0_DIS 0_UMA 2 R635 R638 19 ATI_VGA_GRN 6 UMA_VGA_GRN C28 10P 2 R639 R640 3 Layout Note: Setting R,G,B treac impedance to 50 ohm. 19 ATI_VGA_RED 6 UMA_VGA_RED D26 DA204U_NC 2 1 D25 DA204U_NC ATI & UMA RGB SWITCH C25 10P 50 Place near JVGA1 connector < 200 mil 1 1 Title QUANTA COMPUTER CRT&TV CONN A B C D Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet E 27 of 62 A B C D E 1 1 C967 0.01U 2 C654 0.01U 2 C653 0.01U 2 2 C641 0.01U 1 1 1 C933 10U 2 2 1 +3.3V_R5C833 C968 0.01U 1 1 25 25 25 25 +3.3V_R5C833 +3.3V_R5C833 Place the power caps close to the relation pins. 1 25 25 C969 0.47U 2 2 C936 0.01U 61 VCC_RIN 16 34 64 114 120 1 1 1 2 C937 0.01U 2 1 603 VCC_PCI1 VCC_PCI2 VCC_PCI3 VCC_PCI4 VCC_PCI5 VCC_PCI6 C964 0.47U VCC_3V 1 C959 0.01U 10 10 10 603 603 PowerOnReset for VccCore 1 +3.3V_R5C833 GBRST# should be asserted only when system power supply is on. C956 1U 2 1 2 R818 100K 10 603 PCI Bus 12 12 12 12 3 12 PCI_PAR PCI_C_BE3# PCI_C_BE2# PCI_C_BE1# PCI_C_BE0# PCI_AD17 R572 100 12 PCI_REQ0# 12 PCI_GNT0# 12 PCI_FRAME# 12 PCI_IRDY# 12 PCI_TRDY# 12 PCI_DEVSEL# 12 PCI_STOP# 12 PCI_PERR# 12 PCI_SERR# 12 PCI_RST# 17 CLK_PCI_PCCARD 86 R819 2 1 0 AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 PAR C/BE3# C/BE2# C/BE1# C/BE0# IDSEL 124 123 23 24 25 26 29 30 31 REQ# GNT# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# 71 119 GBRST# PCIRST# 121 PCICLK 70 PME# GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 4 13 22 28 54 62 63 68 118 122 AGND1 AGND2 AGND3 AGND4 AGND5 99 102 103 107 111 HWSPND# 69 MSEN 58 XDEN 55 UDIO5 57 UDIO3 UDIO4 65 59 UDIO2 56 2 R825 1 10K 2 +3.3V_R5C833 +3.3V_R5C833 +3.3V_R5C833 R838 10K UDIO1 60 UDIO0/SRIRQ# 72 R839 100K Memory Stick Enable XD Card Enable Serial ROM disable SD Card Enable MMC Card Enable 3 IRQ_SERIRQ 13,31 PCI Bus INTA# 115 PCI_PIRQB# 12 INTB# 116 PCI_PIRQC# 12 TEST 66 1394 Interrupt Media card Interrupt T145 PAD 1 12,31 ICH_PME# 125 126 127 1 2 3 5 6 9 11 12 14 15 17 18 19 36 37 38 39 40 42 43 44 46 47 48 49 50 51 52 53 33 7 21 35 45 8 PCI / OTHER 2 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 805 603 12 PCI_AD[31..0] PCI Bus C961 10U 2 25 2 6.3 VCC_ROUT1 VCC_ROUT2 VCC_ROUT3 VCC_ROUT4 VCC_ROUT5 VCC_MD 25 C941 0.1U 1 10 C966 0.01U 2 2 C960 0.1U +3.3V_R5C833 R836 0 1 2 6.3 1 1 C965 10U +3.3V_RUN 67 2 Place the power caps close to the relation pins. 2 2 1 U49B 10 20 27 32 41 128 1 603 1 25 2 6.3 117 13,31 CLKRUN# R834 100K The ICH schematics need to include a pull-up resistor to implement CLKRUN#, and the ICH schematics must have a pull-down, or constantly drive thesignal low, in order to disable CLKRUN#. 2 CoreLogic CLOCKRUN# CLKRUN# CLK_PCI_PCCARD 1 4 2 1 2 R803 22 4 Refer to DELL M07 schematic X06 C928 1P Title 8 IN 1 CONTROLLER 50 A B QUANTA COMPUTER C D Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet E 28 of 62 A B C D E 80 mils L85 BLM18PG181SN1D 603 AVCC_PHY1 AVCC_PHY2 AVCC_PHY3 AVCC_PHY4 98 106 110 112 TPBIAS0 113 C935 0.1U 10 modify 1 1 +3.3V_R5C833 C636 0.01U 2 C938 10U 2 2 U49A 1 1 2 1 +3.3V_RUN_PHY 1 C635 1000P 603 50 25 Place these caps as close to the R5C833 as possible. 6.3 AS CLOSE AS POSSIBLE TO R5C833 GUARD GND TPBIAS0 C929 0.33U 603 1394_XI 94 C940 22P XI R802 R801 C931 1394_XO 1 R804 C939 22P 56.2/F 56.2/F Y4 24.576MHZ 0 2 95 XO 50 Populate C266 for R5C832 chipset. 4 RICOH_FILO C934 0.01U_NC R793 1 25 96 FIL0 10K/F 2RICOH_REXT101 REXT RICOH_VREF100 VREF IEEE1394/SD 50 2 16 0.01U 25 TPB0N TPBN0 104 TPBP0 105 TPB0P TPAN0 108 TPA0N TPAP0 109 TPA0P 2 R800 R799 C932 0.01U *TPA0P/TPA0N,TPB0P/TPB0N pair trace : As close as possible. *TPA0P/TPA0N,TPB0P/TPB0N pair trace : Same length electrically. *Termination resistor for TPA+/- TPB+/- : As close as possible to its cable driver (device pin out). C930 270P 25 56.2/F 56.2/F R794 5.11K/F 25 5/14:FAE review report say RC533 don't need FILO item, so NC it Circuit area : As small as possible. 87 XD/MMC_DATA7 30 3 3 MDIO16 92 XD/MMC_DATA6 30 2 2 MDIO15 89 XD/MMC_DATA5 30 MDIO14 91 XD/MMC_DATA4 30 MDIO13 90 SD/XD/MS_DATA3 30 MDIO12 93 SD/XD/MS_DATA2 30 MDIO11 81 SD/XD/MS_DATA1 30 MDIO10 82 SD/XD/MS_DATA0 30 MDIO05 75 XD_WP# 30 MDIO08 88 SD/XD/MS_CMD 30 MDIO19 83 XD_ALE 30 MDIO18 85 XD_CLE 30 MDIO02 78 XD_CE# 30 MDIO03 77 MDIO00 80 SD_CD# 30 MDIO01 MS_INS# 79 1 1SS355 2 D33 1 1SS355 0 0 0 2 TPB0- 2 TPB0+ 2 TPA0- 2 TPA0+ L83 DLW21HN181SQ2L_NC 3 3 4 4 +3.3V_R5C833 2 2 1 AS CLOSE AS POSSIBLE TO 1394 CONNECTOR. 1 3 CON1 FOX_UV31413-WS51P-7F R814 10K_NC TPB0- 1 1 TPB0+ 2 2 TPA0- 3 3 TPA0+ 4 4 close to the Chip XD_CDSW# 30 5 6 7 8 MS_INS# 30 2 D32 TPA0P 0 5 6 7 8 SD_CD# TPA0N AS CLOSE AS POSSIBLE TO 1394 CONNECTOR. 1 SD_WP#(XDR/B#) 30 TPB0P 1 2 3 R751 1 R750 1 R752 1 R754 1 TPB0N 1 1 Place these caps as close to the IC as possible. L82 DLW21HN181SQ2L_NC 4 4 MDIO17 97 MDIO09 84 MDIO04 76 MDIO06 74 SD/XD/MS_CLK 30 MC_PWR_CTRL_0 30 PAD T141 RSV MDIO07 73 33 4 4 Title QUANTA COMPUTER IEEE 1394 A B C D Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet E 29 of 62 1 2 4 +1.5V_CARD 0 R421 1 0 6 1 C539 0.1U 10 +1.5V_RUN +3.3V_RUN +3.3V_SUS 12 PCIE_TX412 PCIE_TX4+ AUXIN 3.3VIN_0 3.3VIN_1 1.5VIN_0 1.5VIN_1 20 1 6 SHDN# STBY# SYSRST# 16 7 NC GND0 15 3 5 11 13 AUXOUT 3.3VOUT_0 3.3VOUT_1 1.5VOUT_0 1.5VOUT_1 +3.3V_SUS ExpressSwitch CARD_RESET# PERST# CPPE# CPUSB# OC# 8 10 9 19 RCLKEN 18 EXPRCRD_PWREN# CPUSB# R439 R447 1 100K 1 100K 2 2 C581 0.1U +3.3V_CARD +1.5V_CARD C555 0.1U C546 0.1U 2 C547 0.1U +3.3V_CARDAUX 1 +3.3V_SUS C583 0.1U 2 +3.3V_RUN 1 3.3 +1.5V_RUN 1 EXPRCRD_PWREN# 12 PCIE_RX412 PCIE_RX4+ B +1.5V_CARD R5538D001-TR-F 1 +3.3V_CARD 17 CARD_CLK_REQ# 31 EXPRCRD_PWREN# 17 CLK_PCIE_EXPCARD# 17 CLK_PCIE_EXPCARD EXPRCRD_STDBY# 2 CARD_RESET# PAD PLTRST# 1 +1.5V_CARD 13,33,34,42 PCIE_WAKE# +3.3V_CARDAUX T54 6,12,25,33,34,42 2 13,33,34 ICH_SMBCLK 13,33,34 ICH_SMBDATA 17 2 4 12 14 R452 100K 2 1 +3.3V_SUS 1 603 GND_1 USBUSB+ CPUSB# RSV_0 RSV_1 SMBCLK SMBDATA +1.5V_0 +1.5V_1 WAKE# +3.3VAUX PERST# +3.3V_1 +3.3V_2 CLKREQ# CPPE# REFCLKREFCLK+ GND_2 PERn0 PERp0 GND_3 PETn0 PETp0 GND_4 2 1 6.3 Please the cap near connector. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 USBP7_DUSBP7_D+ CPUSB# C551 0.1U B NC1 NC2 NC3 NC4 10 2 1 2 2 1 CON2 10 +3.3V_CARD A +3.3V_CARD C572 10U +3.3V_CARDAUX U27 2 10 2 Please the cap near connector. C582 0.1U 8 2 A C579 0.1U 7 +1.5V_CARD Max. 650mA, Average 500mA. +3V_CARD Max. 1300mA, Average 1000mA. C542 0.1U 2 R418 1 2 PLW3216S900SQ2T1_NC 5 Express Card USBP7_DUSBP7_D+ 3 2 1 L59 4 1 12 ICH_USBP712 ICH_USBP7+ 3 10 10 Please the cap near pin 12 & 14(1.5VIN). 27 28 29 30 FOX_1CH411BAC-GM 10 Please the cap near pin 2 & 4 (3.3VIN). 10 Please the cap near pin 17 (AUXIN). 10 Please the cap near pin 15 (AUXOUT). 10 Please the cap near pin 3 & 5 (3.3VOUT). Please the cap near pin 11 & 13(1.5VOUT). JAE PX10FS16PH-26P PCI-Express TX and RX direct to connector. +3.3V_RUN_CARD +3.3V_RUN_CARD (65) 29 XD_CDSW# CON5 29 SD_CD# SD_CD# SD_WP# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 XD/MMC_DATA7 XD/MMC_DATA6 XD/MMC_DATA5 XD/MMC_DATA4 SD/XD/MS_DATA3 SD/XD/MS_DATA2 SD/XD/MS_DATA1 C SD/XD/MS_DATA1 SD/XD/MS_CMD SD/XD/MS_DATA0 SD/XD/MS_DATA1 XD/MMC_DATA7 SD/XD/MS_DATA0 XD/MMC_DATA6 SD/XD/MS_DATA2 SD/XD/MS_CLK 2 R767 0 1 C883 C897 270P_NC 2.2U C884 6.3 270P_NC 25 25 SD-CD SD-WP XD-VCC XD-D7 XD-D6 XD-D5 XD-D4 XD-D3 XD-D2 XD-D1 GND SD-DAT1 MS-BS SD-DAT0 MS-DATA1 SD-DAT7 MS-DATA0 SD-DAT6 MS-DATA2 SD-CLK SD-VCC MS-INS SD-DAT5 MS-DATA3 SD-CMD MS-SCLK SD-DAT4 MS-VCC SD-DAT3 SD-DAT2 GND XD-D0 XD-WP XD-WE XD-ALE XD-CLE XD-CE XD-RE XD-R/B XD-CD GND GND 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 2 R768 0 XD/MMC_DATA5 SD/XD/MS_DATA3 SD/XD/MS_CMD SD/XD/MS_CLK XD/MMC_DATA4 1 MS_INS# 29 29 SD_WP#(XDR/B#) 29 XD/MMC_DATA7 29 XD/MMC_DATA6 29 XD/MMC_DATA4 SD/XD/MS_DATA0 XD_WP# SD/XD/MS_CMD XD_ALE XD_CLE XD_CE# SD/XD/MS_CLK SD_WP#(XDR/B#) XD_CDSW# 29 SD/XD/MS_DATA3 29 SD/XD/MS_DATA2 29 SD/XD/MS_DATA1 29 SD/XD/MS_DATA0 29 SD/XD/MS_CMD 29 XD_WP# C899 270P 25 TTN_R015-B10-LV 29 XD_ALE 29 XD_CLE 29 XD_CE# 8 IN1 CARD READER 603 R760 1 +3.3V_RUN_CARD 29 SD/XD/MS_CLK +3.3V_RUN_CARD +3.3V_R5C833 0_NC 2 U46 D Q72 2N7002W-7-F 25 C886 0.01U 25 C894 0.01U R761 150K SD_WP#(XDR/B#) 3 1 2 C903 0.01U 25 C 29 XD/MMC_DATA5 SD/XD/MS_DATA3 SD/XD/MS_DATA2 29 MC_PWR_CTRL_0 SD_WP# D 5 3 IN OUT NC 1 4 EN GND 2 TPS2051BDBV SD Protect QUANTA COMPUTER C885 1U Title C895 0.1U ExpressCard/SmartCard 10 XD_CDSW# 603 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B 10 1 2 3 4 5 6 7 Sheet of 30 8 62 4 2 SDMK0340L-7-F C639 1U 3 11,40 ICH_AZ_CODEC_RST# 17 CLK_PCI_8512 11,33 LPC_LFRAME# 11,33 LPC_LAD0 11,33 LPC_LAD1 11,33 LPC_LAD2 11,33 LPC_LAD3 C CLK_PCI_8512 65 64 63 62 61 60 59 58 KSI7 KSI6 KSI5 KSI4 KSI3/SLIN KSI2/INT KSI1/AFD KSI0/STB 22 13 6 10 9 8 7 LPCRST/WUI4/GPD2 LPCCLK LFRAME LAD0 LAD1 LAD2 LAD3 13,28 CLKRUN# 13,28 IRQ_SERIRQ D21 13 SIO_EXT_SMI# D20 13 SIO_EXT_SCI# D23 11 SIO_A20GATE 26 LCD_TST 2 2 2 SDMK0340L-7-F 1 SDMK0340L-7-F 1 SDMK0340L-7-F 1 93 5 15 23 126 17 D17 2 SDMK0340L-7-F 1 WRST# LCD_BAK# 4 14 16 KBRST/GPB6 WRST PWUREQ/GPC7 19 20 L80HLAT/GPE0 L80LLAT/WUI7/GPE7 11 SIO_RCIN# 26 LCD_BAK# 40 NB_MUTE# 12,28 ICH_PME# 110 111 SMCLK0/GPB3 SMDAT0/GPB4 SMBCLK1 SMBDAT1 115 116 SMCLK1/GPC1 SMDAT1/GPC2 SMBCLK2 SMBDAT2 117 118 SMCLK2/GPF6 SMDAT2/GPF7 38 LED_MASK# 13,44,51 IMVP_PWRGD 85 86 PS2CLK0/GPF0 PS2DAT0/GPF1 44 RESET_OUT# 37 NUM_LED# 87 88 PS2CLK1/GPF2 PS2DAT1/GPF3 37 CLK_TP_SIO 37 DAT_TP_SIO 89 90 PS2CLK2/GPF4 PS2DAT2/GPF5 17,26,39 SMBCLK1 17,26,39 SMBDAT1 22,37 SMBCLK2 22,37 SMBDAT2 PWM LPC IR/UART 2 1 PWM0/GPA0 PWM1/GPA1 PWM2/GPA2 PWM3/GPA3 PWM4/GPA4 PWM5/GPA5 PWM6/GPA6 PWM7/GPA7 24 25 28 29 30 31 32 34 TACH0/GPD6 TACH1/GPD7 47 48 1 3 2 RP46 4 2.2KX2 D HWPG HWPG 44 IMVP6_PROCHOT# 51 KB_DET# 37 LCD_CBL_DET# 26 INVERTER_CBL_DET# 26 PBAT_PRES# 54 LCD_CBL_DET# INVERTER_CBL_DET# ADP_OC SIO_SLP_S5# R683 2 R437 2 1 D15 SMBDAT2 SMBCLK2 1 0_NC 1 0_NC 2 SDMK0340L-7-F SIO_SLP_S5# 13 CIR_ON/OFF# 37 ADAPT_TRIP_SEL 46 SIO_EXT_WAKE# 13 LAN_DISABLE# 42 EXPRCRD_PWREN# 30 ICH_RSMRST# 13 SIO_PWRBTN# 13 R513 R510 2 R460 2 R479 2 R457 1 100K_NC 1 100K 1 100K HWPG RXD/GPB0 TXD/GPB1 CRX0/GPC0 CTX0/GPB2 CRX1/GPH1/ID1 CTX1/GPH2/ID2 108 109 119 123 94 95 FLFRAME/GPG2/LF FLRST/GPG0/TM FLAD3/GPG6 100 106 104 SMBUS LPC/FWH FLASH FLAD2/SO FLAD1/SI FLAD0/SCE FLCLK 103 102 101 105 EC_FLASH_SPI_DO 32 EC_FLASH_SPI_DIN 32 EC_FLASH_SPI_CS# 32 EC_FLASH_SPI_CLK 32 ITE8512_XTAL1 128 ITE8512_XTAL2 2 R551 10 82 83 84 PS_ID 54 5V_ALW_ON 52 SNIFFER_GREEN# SUS_ON C637 2.2P +3.3V_ALW L61 50 BLM18AG121SN1D ITE8512_XTAL2 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 74 75 AVCC AVSS C561 0.1U 2 R455 1 100K Board ID Straps SUS_ON 49,53 USB_R_SIDE_EN# 54 ICH_CL_PWROK 6,13 R459 10K_DIS USB_L_SIDE_EN# R776 10K_NC R470 10K_NC R461 10K_NC BID0 BID1 KSO18 USB_L_SIDE_EN# 38 R458 10K_UMA 35 R475 10K R466 10K B R464 10K MODC_EN 36 UMA CK32KE 1 12 27 49 91 113 122 1 18 21 35 SIO_SLP_S3# 13 ACAV_IN 46 SNIFFER_PWR_SW# RING/PWRFAIL/LPCRST/GPB7 112 USB_SIN_SIDE_EN# PWRSW/GPE4 125 MAIN_PWR_SW# 38 RI1/WUI0/GPD0 RI2/WUI1/GPD1 WUI5/GPE5 GINT/GPD5 33 VGA_IDENTIFY (USB_L_SIDE_EN#) 1 = Discrete Gfx. 0 = UMA. 38 35 CHIPSET_ID1 (KSO18) 0 0 0 0 0 0 LCDVCC_TST_EN 26 IT8512E/IX-L LQFP128-16X16-4-FX2 BID1 1 1 0 0 0 0 BID0 0 1 0 1 0 1 GM3B (UMA) SSI (X00) PT (X01) ST (X02) QT (A00) (A01) GM3 (Dis) SSI (X00) PT (X01) ST (X02) QT (A00) (A01) ITE8512IX_JX 4 ITE8512_XTAL1 2 3 C632 32.768KHZ 18P 50 C624 18P 50 2 1 1 A 2 W1 1 USB_L_SIDE_EN# BID0 BID1 KSO18 C985 1U_NC 0603 10 R735 0.1U Title QUANTA COMPUTER Ultra I/O Controller ITE 8512 ITE8512IX pin12 connect to GND. ITE8512JX pin12 connect to 0.1uF, 1uF. 5 C 100K 603 10 BLM18AG121SN1D 2 R547 0 1 L60 32KHz Clock. A 2 603 CK32K 96 97 98 99 107 R456 2 +3.3V_ALW 1 GPH3/ID3 GPH4/ID4 GPH5/ID5 GPH6/ID6 GPG1/ID7 1 10K_NC 2 38 2 PS/2 EGAD/GPE1 EGCS/GPE2 EGCLK/GPE3 IINP 46 ADAPT_OC 46 +3.3V_ALW LCD_CBL_DET# INVERTER_CBL_DET# WIRELESS_ON/OFF# AUX_EN_WOWL 34 CIRRX 37 RUN_ON_1 44 HDDC_EN 36 IMVP_VR_ON 51 1 2 1 ITE8512IX_JX R554 2 EGPC GPIO CLK_PCI_8512 20 1 0_NC UMA_PANEL_BKEN 6 ATI_PANEL_BKEN 19 1 B R454 1 R453 2 LCD_BAK# FAN1_TACH 39 0_UMA 0_DIS LID_SW# 37 MEDIA_INT# 37 IMVP_VR_ON IMVP_VR_ON +3.3V_RUN 120 124 20_NC 1 100K_NC ADP_OC TMRI0/WUI2/GPC4 TMRI1/WUI3/GPC6 1 R494 2 R511 SUS_ON BREATH_LED# 38 BAT2_LED# 38 FAN1_PWM 39 PWM_VADJ 26 BAT1_LED# 38 KB_BACKLITE_EN 37 CAP_LED# 37 BEEP 40 PANEL_BKEN SIO_SLP_S5# 2 G_thermal & LAN &media button 76 77 78 79 80 81 2 RP44 4 10KX2 Discrete SMBCLK0 SMBDAT0 46,54 SMBCLK0 46,54 SMBDAT0 CHARGE & BAT CLK&LCD$thermal CLKRUN/GPH0/ID0 SERIRQ ECSMI/GPD4 ECSCI/GPD3 GA20/GPB5 LPCPD/WUI6/GPE6 DAC0/GPJ0 DAC1/GPJ1 DAC2/GPJ2 DAC3/GPJ3 DAC4/GPJ4 DAC5/GPJ5 ADC/DAC 1 3 1 WRST# 2 1 39,52 THERM_STP# KSI7 KSI6 KSI5 KSI4 KSI3 KSI2 KSI1 KSI0 KEYBOARD 10 SMBDAT1 SMBCLK1 2 D34 1 66 67 68 69 70 71 72 73 C630 0.1U 2 1 R552 100K ADC0/GPI0 ADC1/GPI1 ADC2/GPI2 ADC3/GPI3 ADC4/GPI4 ADC5/GPI5 ADC6/GPI6 ADC7/GPI7 R553 0_NC 2 RP43 4 2.2KX2 1 2 +3.3V_ALW +3.3V_ALW 1 3 2 603 +3.3V_RUN 26 50 92 114 121 127 SMBDAT0 SMBCLK0 1 Place these caps close to ITE8512. D VSTBY1 VSTBY2 VSTBY3 VSTBY4 VSTBY5 VSTBY6 2 2 10 ITE8512E LQFP-128L +3.3V_ALW 0 1 1 10 C600 0.1U KSO17/GPC5 KSO16/GPC3 KSO15 KSO14 KSO13 KSO12/SLCT KSO11/ERR KSO10/PE KSO9/BUSY KSO8/ACK KSO7/PD7 KSO6/PD6 KSO5/PD5 KSO4/PD4 KSO3/PD3 KSO2/PD2 KSO1/PD1 KSO0/PD0 R556 1 3 11 1 2 2 10 C599 0.1U 57 56 55 54 53 52 51 46 45 44 43 42 41 40 39 38 37 36 VBAT1 VCC 1 10 C612 0.1U 1 1 1 C560 0.1U KSO17 KSO16 KSO15 KSO14 KSO13 KSO12 KSO11 KSO10 KSO9 KSO8 KSO7 KSO6 KSO5 KSO4 KSO3 KSO2 KSO1 KSO0 1 +RTC_CELL 1 6.3 2 2 2 1 C620 10U 2 2 37 KSO[0..18] 37 KSI[0..7] +3.3V_ALW 3 U30 2 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 31 of 62 5 4 3 +3.3V_ALW +3.3V_ALW 1 WP# VSS 4 2 40 GND IN 1 C642 2.2U SHDN 5 25 MAX1615EUK-T+_NC D C633 1U_NC 805 603 JRTC1 10 1 2 50 C593 0.1U OUT 5/3# 2 1 3 SST25VF016B-50-4C-S2AF 3 4 2 7 U34 1 2 D19 SDMK0340L-7-F 8 1 HOLD# VDD 1 C592 22P +PWR_SRC 1 CE# SCK SI SO 2 2 15 2 15 2 15 1 6 5 2 2 R498 1 R497 1 R436 1 R499 10K U28 2 D +3.3V_ALW +RTC_CELL R435 10K EC_FLASH_SPI_CS# EC_FLASH_SPI_CLK EC_FLASH_SPI_DIN EC_FLASH_SPI_DO 1 RTC BATTERY 16Mbit (2M Byte), SPI 31 31 31 31 2 1 2 +RTC_1 1 6.3R562 D18 SDMK0340L-7-F C638 1U 2 1K +RTC 2 1 LTS_AAA-BAT-019-K01 40 RTC-BATTERY 603 10 C C B B A A Title QUANTA COMPUTER Ultra I/O Controller ECE5028 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 32 of 62 1 2 3 4 5 6 7 8 L86 USBP6_DUSBP6_D+ 1 4 2 3 ICH_USBP6- 12 ICH_USBP6+ 12 PLW3216S900SQ2T1_NC 1206 1 R811 MiniCard Robson, UWB connector +3.3V_RUN A +3.3V_RUN 0 1 R810 0 2 2 FOR DEBUG CARD +1.5V_RUN A J8 2 C663 33P_NC R577 100K_NC LPC_LFRAME# 11,31 LPC_LAD3 11,31 LPC_LAD2 11,31 LPC_LAD1 11,31 LPC_LAD0 11,31 2 PLTRST# 6,12,25,30,34,42 2 1R567 WPAN_RADIO_DIS_MINI# 13 SB_WPAN_PCIE_RST# 12 +3.3V_RUN 2 0_NC C648 0.047U 10 10 +3.3V_RUN ICH_SMBCLK 13,30,34 ICH_SMBDATA 13,30,34 C659 0.047U C646 0.1U C658 0.047U + C652 4.7U C656 330U/6.3V_NC 2 C644 0.1U 1 USB_MCARD3_DET# 13 0 2 2 1 USBP6_DUSBP6_D+ R571 1 C647 0.047U 2 0 1 1 +1.5V_RUN 1 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 0_NC 2 0_NC 2 0_NC 2 0_NC 2 0_NC 2 2 COEX2_WLAN_ACTIVE 2 GND3 W_DISABLE# PERST# 3.3VAUX1 GND5 1.5V_2 SMB_CLK SMB_DATA GND8 USB_DUSB_D+ GND10 LED_WWAN# LED_WLAN# LED_WPAN# 1.5V_3 GND11 3.3V_2 R809 R808 R807 R806 R805 1 1 1 1 1 1 12 PCIE_TX312 PCIE_TX3+ 13 PCIE_MCARD3_DET# LED_WPAN# 38 10 10 10 10 6.3 6.3 603 7343 FOX_AS0B226-S52N-7F 1 1 UIM_C8 UIM_C4 GND4 PERn0 PERp0 GND6 GND7 PETn0 PETp0 GND9 RESERVED_3 RESERVED_4 RESERVED_5 RESERVED_6 RESERVED_7 RESERVED_8 RESERVED_9 RESERVED_10 2 4 6 8 10 12 14 16 R568 1 2 0_NC 2 0_NC 12 PCIE_RX312 PCIE_RX3+ FOR DEBUG CARD 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 3.3V_1 GND0 1.5V_1 UIM_PWR UIM_DATA UIM_CLK UIM_RESET UIM_VPP 2 R578 1 R579 1 6,12,25,30,34,42 PLTRST# 17 CLK_LPC_DEBUG WAKE# RESERVED_1 RESERVED_2 CLKREQ# GND1 REFCLKREFCLK+ GND2 1 17 CLK_PCIE_MINI3# 17 CLK_PCIE_MINI3 1 3 5 7 9 11 13 15 2 2 2 1 0 0 2 13,30,34,42 PCIE_WAKE# COEX2_WLAN_ACTIVE R576 1 34 COEX2_WLAN_ACTIVE R575 1 34 COEX1_BT_ACTIVE_MINI T146 PAD B B 50 MiniCard WWAN connector +3.3V_RUN +3.3V_RUN +1.5V_RUN J9 17 CLK_PCIE_MINI2# 17 CLK_PCIE_MINI2 1 3 5 7 9 11 13 15 WAKE# RESERVED_1 RESERVED_2 CLKREQ# GND1 REFCLKREFCLK+ GND2 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 UIM_C8 UIM_C4 GND4 PERn0 PERp0 GND6 GND7 PETn0 PETp0 GND9 RESERVED_3 RESERVED_4 RESERVED_5 RESERVED_6 RESERVED_7 RESERVED_8 RESERVED_9 RESERVED_10 3.3V_1 GND0 1.5V_1 UIM_PWR UIM_DATA UIM_CLK UIM_RESET UIM_VPP 2 4 6 8 10 12 14 16 GND3 W_DISABLE# PERST# 3.3VAUX1 GND5 1.5V_2 SMB_CLK SMB_DATA GND8 USB_DUSB_D+ GND10 LED_WWAN# LED_WLAN# LED_WPAN# 1.5V_3 GND11 3.3V_2 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 +UIM_PWR UIM_DATA UIM_CLK UIM_RESET +UIM_VPP R570 1 12 PCIE_RX112 PCIE_RX1+ PCI-Express TX and RX direct to connector 12 PCIE_TX112 PCIE_TX1+ 13 PCIE_MCARD2_DET# L87 2 USBP5_DUSBP5_D+ PLTRST# 6,12,25,30,34,42 WWAN_RADIO_DIS# 1 4 13 0_NC 2 SB_WWAN_PCIE_RST# +3.3V_RUN 12 ICH_SMBCLK 13,30,34 ICH_SMBDATA 13,30,34 USBP5_DUSBP5_D+ PAD 2 3 ICH_USBP5- 12 ICH_USBP5+ 12 PLW3216S900SQ2T1_NC R813 1206 1 0 R812 1 0 Layout Note: R240 and R244 close to choke as possible to minimize stubs. 2 2 USB_MCARD2_DET# 13 T93 +1.5V_RUN Place caps close to connector. +3.3V_RUN C 1 + C660 0.047U C655 330U + C657 330U/6.3V_NC 2 C651 33P 2 C661 0.047U 2 1 1 C649 33P 2 C645 33P 2 1 1 C650 0.047U 2 2 FOX_AS0B226-S52N-7F 2 1 1 C R569 1 0 1 13,30,34,42 PCIE_WAKE# T142 PAD T144 PAD T143 PAD 6.3 6.3 7343 7343 ESD1 DATA UIM_DATA CLK C2 33P C4 33P SRV05-4.TCT C1 33P 10 2 +UIM_VPP +UIM_PWR C5 33P 1 4 2 +UIM_VPP +UIM_PWR UIM_DATA 2 VPP 6 5 4 1 RST 1 6 5 4 1 3 UIM_CLK 2 UIM_RESET 1 2 3 1 GND 2 VCC 1 2 3 UIM_CLK 6 1 5 2 UIM_RESET JSIM1 +UIM_PWR 50 50 50 50 10 50 50 10 50 10 C3 1U FOX_2WM610A2C-GM-7F Place as close as possible to WWAN connector layout note:10 mil trace and 20 mil space for SIM card and UIM_PWR use 20mil 603 D D QUANTA COMPUTER Title WWAN, WPAN 1 2 3 4 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet 33 of 8 62 1 2 3 4 5 6 7 8 +3.3V_WLAN 4 2 MiniCard WLAN connector +3.3V_WLAN +3.3V_WLAN MINI1CLK_REQ# +1.5V_RUN RP41 2.2KX2 1 3 1 2 J7 C662 220P 50 R790 1 R520 1 MINI1CLK_REQ# 1 3 5 7 9 11 13 15 2 0 2 0 17 CLK_PCIE_MINI1# 17 CLK_PCIE_MINI1 WAKE# RESERVED_1 RESERVED_2 CLKREQ# GND1 REFCLKREFCLK+ GND2 3.3V_1 GND0 1.5V_1 UIM_PWR UIM_DATA UIM_CLK UIM_RESET UIM_VPP 2 4 6 8 10 12 14 16 WLAN_SMBCLK 12 PCIE_RX212 PCIE_RX2+ PCI-Express TX and RX direct to connector 12 PCIE_TX212 PCIE_TX2+ 13 PCIE_MCARD1_DET# Non-iAMT T72 T66 T74 WLAN_ICH_CL_CLK1 WLAN_ICH_CL_DATA1 WLAN_ICH_CL_RST1# PAD PAD PAD UIM_C8 UIM_C4 GND4 PERn0 PERp0 GND6 GND7 PETn0 PETp0 GND9 RESERVED_3 RESERVED_4 RESERVED_5 RESERVED_6 RESERVED_7 RESERVED_8 RESERVED_9 RESERVED_10 GND3 W_DISABLE# PERST# 3.3VAUX1 GND5 1.5V_2 SMB_CLK SMB_DATA GND8 USB_DUSB_D+ GND10 LED_WWAN# LED_WLAN# LED_WPAN# 1.5V_3 GND11 3.3V_2 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 A 3 R446 1 ICH_SMBCLK 13,30,33 0_NC 2 +3.3V_WLAN R483 1 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 Q49 2N7002W-7-F_NC 1 0 2 PLTRST# 6,12,25,30,33,42 WLAN_RADIO_OFF# R484 0_NC 1 2 SB_WLAN_PCIE_RST# +3.3V_WLAN 2 2 A 13,30,33,42 PCIE_WAKE# 33 COEX2_WLAN_ACTIVE 33 COEX1_BT_ACTIVE_MINI 17 MINI1CLK_REQ# WLAN_SMBDATA Q48 2N7002W-7-F_NC 1 3 WLAN_SMBCLK WLAN_SMBDATA R445 1 PAD PAD ICH_SMBDATA 13,30,33 12 T60 T57 USB_MCARD1_DET# 13 0_NC 2 Suport for WoW LED_WLAN_OUT# 38 WLAN_RADIO_OFF# 2 1 D14 SDMK0340L-7-F R440 0_NC 1 2 B FOX_AS0B226-S68N-7F 13 Prevent backdrive when WoW is enabled. B Place caps close to connector. +3.3V_WLAN 10 10 2 C568 0.047U 10 R471 0 1 2 + C610 4.7U C902 330U/6.3V_NC 2 2 C602 0.1U 1 1 1 2 1 2 1 1 2 2 10 C580 0.047U 10 6.3 805 7343 805 C C587 4700P_NC 2 2 2 R485 470K_NC 1 1 4 1 1 1 10 C575 0.1U Q53A 2N7002DW-7-F_NC R442 200K_NC 50 2 R463 100K_NC 10 C565 0.047U 5 6 2 +3.3V_RUN C584 0.047U 3 Q53B 2N7002DW-7-F_NC 31 AUX_EN_WOWL Q54 FDC655BN_NC 6 5 4 2 1 3 R486 100K_NC 2 2 R443 100K_NC C +3.3V_WLAN +3.3V_ALW 1 1 +PWR_SRC 2 1 1 +1.5V_RUN WLAN_RADIO_DIS# 603 D D QUANTA COMPUTER Title WLAN 1 2 3 4 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 34 8 62 7 DATA2_H 4 GND1 8 GND2 Each channel is 1A 6.3 6.3 7343 7343 Place one 150uF cap by each USB connector. C264 0.1U 10 C265 0.1U A SHEIL4 10 + C828 150U SHEIL3 + C262 150U/6.3V_NC TPS2062DR 805 DATA1_H USBP1_D+ 12 0_NC 2 DATA2_L 3 +USB_L_SIDE_PWR 2 0_NC 2 R183 1 6 USBP0_D+ USB_OC0_1# 12 2 R190 1206 1 DATA1_L USBP1_D- +USB_L_SIDE_PWR DLW21HN900SQ2L 10 2 SHEIL2 6 5 V2+ USBP0_D- 11 C823 10U_NC OUT2 OC2# 5 SHEIL1 C812 0.1U EN2# 7 8 V1+ +USB_L_SIDE_PWR 9 USBP1_D+ USBP1_D- 2 3 2 A 1 4 12 ICH_USBP1+ 12 ICH_USBP1- 4 OUT1 OC1# 1 1 L17 EN1# GND +USB_L_SIDE_PWR 1 3 31 USB_L_SIDE_EN# IN 1 1 0_NC 2 2 1 R203 1 U12 2 FS2 455/5A_NC 2 1 8 JUSB2 3-1734062-3 10 1 0_NC 2 9 7 Side pair left +5V_SUS DLW21HN900SQ2L R207 1206 1 6 1 USBP0_D+ USBP0_D- 2 3 5 R212 0_0805 2 1 L20 1 4 12 ICH_USBP0+ 12 ICH_USBP0- 4 10 3 2 2 2 1 10 Place ESD diodes as close as USB connector. U11 USBP1_D+ USBP1_D- 1 2 3 I/O I/O VN VP I/O I/O 6 5 4 USBP0_D+ USBP0_D- +USB_L_SIDE_PWR SRV05-4_NC left side single USB port 9 B B L50 USBP8_DUSBP8_D+ JUSB1 1 2 R329 1 0_NC 2 10 10 C408 0.1U USBP8_DUSBP8_D+ C409 0.1U 1 2 3 4 VCC DATADATA+ GND 10 U17 2 3 IN EN1# Place ESD diodes as close as USB connector. GND 1 OUT1 OC1# 7 8 +USB_SIN_SIDE_PWR OUT2 OC2# 6 5 +USB_SIN_SIDE_PWR C458 10U_NC 4 EN2# + C441 150U/6.3V_NC TPS2062DR 6.3 6.3 7343 7343 805 Each channel is 1A C 6 5 4 USBP8_D+ USBP8_D- +USB_SIN_SIDE_PWR + C867 150U 2 10 I/O I/O VN VP I/O I/O SRV05-4_NC 2 10 U16 1 2 3 USB_OC8# 12 1 C453 0.1U 2 2 1 31 USB_SIN_SIDE_EN# 1 1 0_NC 2 FOX_3Q31804C-RB13B34-8F FS1 455/5A_NC 2 1 +5V_SUS R257 0_0805 2 1 R334 1206 1 1 2 3 DLW21HN900SQ2L 2 1 4 12 ICH_USBP812 ICH_USBP8+ +USB_SIN_SIDE_PWR Place one 150uF cap by each USB connector. C D D QUANTA COMPUTER Title External USB 1 2 3 4 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 35 8 62 1 2 3 4 5 6 7 8 ODD Connector JMOD1 Master CON4 CON6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SATA2_RXN0_C C410 SATA2_RXP0_C C411 1 3900P 1 3900P 2 2 25 25 SATA_RX2- 11 SATA_RX2+ 11 GND1 RXP RXN GND2 TXN TXP GND3 1 2 3 4 5 6 7 3.3V_0 3.3V_1 3.3V_2 GND4 GND5 GND6 5V_0 5V_1 5V_2 GND7 8 9 10 11 12 13 14 15 16 17 GND8 12V_0 12V_1 18 19 20 +3.3V_RUN +5V_HDD DP 5V_0 5V_1 MD GND4 GND5 8 9 10 11 12 13 0.01U/16V 0.01U/16V SATA_RX1- 11 SATA_RX1+ 11 A SATA_TX0+ 11 SATA_TX0- 11 SATA1_RXN0_C C549 SATA1_RXP0_C C543 1 3900P 1 3900P 2 2 25 25 SATA_RX0- 11 SATA_RX0+ 11 +5V_MOD +3.3V_RUN +5V_MOD MLX_47628-1012 +5V_HDD C404 10U_NC C403 1U/10V/0603 10 1 3.3V_0 3.3V_1 3.3V_2 GND4 GND5 GND6 5V_0 5V_1 5V_2 GND7 RSVD GND8 12V_0 12V_1 12V_2 SATA_TX2+ 11 SATA_TX2- 11 C869 C868 C380 0.1U 2 1 2 3 4 5 6 7 SATA_TX1+ 11 SATA_TX1- 11 SATA_RXN1_C SATA_RXP1_C 1 GND1 RXP RXN GND2 TXN TXP GND3 1 2 3 4 5 6 7 2 A GND1 RXP RXN GND2 TXN TXP GND3 1 SATA Connector. 2 Second HDD 10 C381 C382 0.1U 1000P/50V 10 Place caps close to connector. 805 LD2822H-SA9L6 GS12201-1011-9F +3.3V_RUN B del pin18 and pin 22 B +3.3V_RUN C913 1U_10V_0603_NC C912 0.1U/16V_NC C910 0.1U/16V_NC C911 1000P/50V_NC +5V_ALW Place caps close to Master connector. 8 7 6 5 +3.3V_ALW Place caps close to Second HDD connector. C329 C312 C332 C313 10U/10V/0805 1U/10V/0603 0.1U/16V 0.1U/16V 1000P/50V R302 100K C906 C909 C908 +15V_ALW C905 1U/10V/0603 0.1U/16V R749 100K 2 1 MOD_EN_5V 3 1000P/50V 10U/10V/0805 C862 10U 2 805 R324 100K 10 2 C904 1 2 1 +5V_HDD C306 R748 0_NC 4 +5V_HDD Place caps close to SATA1 connector. +5V_RUN +5V_MOD Q70 SI4800BDY-T1-E3 3 2 1 1 C919 10U/10V/0805_NC C402 1000P/50V_NC 2 C398 0.1U/16V_NC 1 C395 1U_10V_0603_NC 0.1U/16V for EMI 805 Q35A 2N7002DW-7-F 1 6 4 5 2 R270 0_NC 60V 1 C866 0.1U C 25 603 2 2 1 4 3 +15V_ALW C319 4.7U R293805 100K 2 1 +3.3V_ALW Q35B 2N7002DW-7-F R295 100K 60V Q36 FDC655BN 6 5 2 1 1 +5V_RUN +5V_HDD 2 +5V_ALW 2 1 31 MODC_EN C 6.3 1 R315 100K 2 HDD_EN_5V 603 1 2 3 R303 100K Q37A 2N7002DW-7-F 1 6 4 5 2 R304 100K 60V Q37B 2N7002DW-7-F 60V C375 0.1U 25 D 2 D 2 1 1 31 HDDC_EN 603 Title QUANTA COMPUTER SATA (HDD&CD_ROM) 1 2 3 4 5 6 7 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 8 36 of 62 1 2 3 4 5 +3.3V_ALW 6 7 8 +3.3V_ALW +5V_RUN KEYBOARD CONNECTOR 2 31 KSO[0..18] Touch Pad 31 KSI[0..7] 1 3 R393 100K JKB1 31 KB_DET# 1 RP19 LID_SW# JTP1 2 4 31 A L56 L57 31 CLK_TP_SIO 31 DAT_TP_SIO 603 BLM11A601S BLM11A601S 1 1 C434 0.047U C477 0.1U 2 1 1 88502-0601 2 1 C436 0.1U 2 50 C474 10P 2 50 C475 10P 2 2 50 1 1 2 1 2 1 +5V_RUN C479 10P 100K 1 2 3 4 5 6 TP_CLK TP_DATA 603 C478 10P R276 2 +3.3V_ALW 10 10 C920 0.047U 10 50 CAP_LED_R NUM_LED_R 8/17:add dioad to protect GPIO port 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 KSI7 KSI6 KSI4 KSI2 KSI5 KSI1 KSI3 KSI0 KSO5 KSO4 KSO7 KSO6 KSO8 KSO3 KSO1 KSO2 KSO0 KSO12 KSO16 KSO15 KSO13 KSO14 KSO9 KSO11 KSO10 KSO17 KSO18 4.7KX2 R275 1 R274 1 2 220 2 220 A HRS_ FH28D-64(32)SB-1SH(86) Media Button +3.3V_ALW 2 1 CP1 +3.3V_ALW +5V_ALW +3.3V_ALW 3 1 KSO10 CP2 8 6 4 2 KSO17 KSO18 100PX4_NC 1 2 3 4 5 6 7 8 9 10 22,31 SMBCLK2 22,31 SMBDAT2 2 2 R266 10K_0402 1 2 7 5 3 1 7 5 3 1 KSO0 KSO12 KSO16 KSO15 8 6 4 2 100PX4_NC 7 5 3 1 KSO13 KSO14 KSO9 KSO11 100PX4_NC JMB1 R259 100K_0402 B 31 MEDIA_INT# CP3 8 6 4 2 DA204U_NC D11 1 38 HDD_LED 38 WLAN_LED 38 BT_LED C278 1U/10V/0603 C285 10U_NC 4 805 5V_PWR CLK DAT INT GND LED1 LED2 LED3 3V_PWR 5V_LED CP5 CP4 8 6 4 2 FOR EMI 7 5 3 1 KSO5 KSO4 KSO7 KSO6 8 6 4 2 100PX4_NC KSO8 KSO3 KSO1 KSO2 100PX4_NC 50 CP7 88501-1001 B 7 5 3 1 50 CP6 8 6 1206 4 2 7 5 3 1 KSI7 KSI6 KSI4 KSI2 8 6 1206 4 2 100PX4_NC 7 5 3 1 KSI5 KSI1 KSI3 KSI0 100PX4_NC 100P CAPS CLOSE TO JKB1 +3.3V_RUN +5V_RUN Consumer IR 2 Key board Illumination R264 100K 2 1 31 CAP_LED# R840 10K 2 2 10 10 2 33_NC 3 R252 1 CAP_LED_R C +KB_LED J4 R263 100K 3 Q30 2N7002W-7-F 1 2 3 4 KB_LED_DEC# LED_PWM +KB_LED 1 2 3 4 Q33 DDTA114YUA-7-F 2 10K 12 13 KB_LED_DET# C921 0.1U 10 3 805 100K_NC 1 88502-0401 47K 1 31 NUM_LED# +3.3V_RUN 1 SIL_TSOP36136TS R283 2 1 +5V_RUN 2 C666 0.1U +3.3V_RUN IRTX VCC GND1 GND2 2 4 3 2 1 C667 4.7U 1 10K 1 2 CIRRX CIR_VCC Q34 DDTA114YUA-7-F 2 1 CIRRX 1 31 1 C 3 Q31 2N7002W-7-F U36 +KB_LED FS3 1206L050YR 2 2 R585 100 47K 1 +3.3V_ALW 1 +3.3V_ALW 2 1 +5V_RUN NUM_LED_R +5V_ALW Q46 SI2304BDS-T1-E3 +3.3V_ALW 3 1 2 LED_PWM 1 3 2 R844 10K_NC Q32 2N7002W-7-F_NC 31 KB_BACKLITE_EN 3 1 2 2 31 CIR_ON/OFF# CIR_VCC 1 Q78 DDTC124EUA-7-F_NC D D QUANTA COMPUTER Title TOUCH PAD, BULE TOOTH & FIR 1 2 3 4 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 37 8 62 A B C Sniffer Switch 1 47K 1 2 2 2 3 R430 HDD_LED_L 1 220 2 220 2 WLAN_LED 37 Sniffer Switch ON/OFF 10 1 +5V_RUN +3.3V_ALW 1 BT_ACT# 3 2 Q60 DTA114YUA 47K 1 33 LED_WPAN# 31 SNIFFER_PWR_SW# 2 10K R280 2 PC73 1U_NC 0 1 SNIFFER1 8/17:add dioad to protect GPIO port 3 Q61 2N7002W-7-F DA204U_NC D13 R281 100K 2 2 1 31 LED_MASK# 0_NC 1 R574 2 1 R573 0 2 2 1 11 SATA_ACT# 4 +3.3V_ALW +3.3V_RUN R566 100K S LSS12P-PC-V-T/R +3.3V_RUN R427 100K SATA_ACT# 3 1 603 R448 WLAN_LED_L1 HDD_LED 37 BT / UWB LED +3.3V_RUN 0 C669 1U_NC 10K Q50 2N7002W-7-F 10K R586 2 2 3 31 WIRELESS_ON/OFF# Q51 DDTA114YUA-7-F 3 1 1 34 LED_WLAN_OUT# Q43 DDTA114YUA-7-F 3WLAN_ACT# G 2 1 47K 2 1 2 1 R449 100K 4 Q42 2N7002W-7-F 1 ON R587 100K 2 2 0_NC 1 R434 2 SATA_ACT# +3.3V_ALW +5V_RUN R433 0 LED_MASK# +5V_RUN SW1 3 1 +3.3V_WLAN 31 E WLAN +3.3V_RUN HDD activity LED. D 3 R565 BT_LED_L 1 603 220 2 Power Switch BT_LED 37 10 3 +3.3V_ALW 1 +3.3V_ALW 2 This circuit is only needed if the platform has the SNIFFER. Power & Suspend. DA204U_NC D12 R288 100K +5V_SUS +5V_SUS 3 +3.3V_SUS R279 10K 3 C336 1U U35 BR_LED# 2 BR_LED 4 3 Q56 2N7002W-7-F 5 2 1 2 R557 100K 1 31 BREATH_LED# POWER_ SW_IN0# 31 MAIN_PWR_SW# 1 BREATH_LED 220 2 R563 JSW1 603 C972 1000P 50 TC7SZ04FU(T5L,F,T) SLED2:AP detection 2 +3.3V_ALW +5V_ALW2 1 31 BAT1_LED# BREATH_LED POWER_ SW_IN0# C973 1000P 50 3 BAT2_ACT# JST_SM07B-SHLS-TF 2 Sniffer LED Q55 DDTA114YUA-7-F Biometric C859 1 2 +1.8V_RUN +3.3V_RUN 10K Q58 2N7002W-7-F 3 J2 1 Q57 DDTA114YUA-7-F R441 100K 1 47K 31 SNIFFER_GREEN# 10K 1 Q45 DDTA114YUA-7-F 2 3 47K R297 1206 1 0 R298 1 0 1 2 3 4 5 6 88501-0601 2 2 3SNIFFER_G_ACT# 2 10K 1 3 3 Q44 2N7002W-7-F FOR RF SPRING SW LED BAT2_LED 54 SNIFFER G_R R431 2 220 1 S_LED1 +3.3V_RUN U14 1 2 3 I/O I/O VN VP I/O I/O 6 5 4 USBP9_D- Title C QUANTA COMPUTER SWITCH, KEYBOARD & LED USBP9_D+ Size Document Number GM3 Date: Monday, March 24, 2008 SRV05-4_NC B USBP9_DUSBP9_D+ PLW3216S900SQ2T1_NC +5V_SUS 2 +3.3V_SUS 2 1 +3.3V_SUS 2 A 1 4 12 ICH_USBP912 ICH_USBP9+ +3.3V_ALW 1 2 12P/50V_NC L37 BAT1_LED 54 31 BAT2_LED# GND SSW1 SLED1 SLED2 GND PLED PSW C974 1000P 50 47K 1 R797 100K Battery status. 2 1 2 +3.3V_ALW 1 2 3 4 5 6 7 SNIFFER1 S_LED1 D Rev 2B Sheet E 38 of 62 2 3 4 R702 0 10 805 C782 0.1U 7 1 MLX_53261-0471 8/17:add diode to protect GPIO port A 10 +5V_RUN R703 4.7K FAN1_TACH 31 +3.3V_RUN 10/20mils U4 1 C70 2200P REM_DIODE1_N 50 50 H_THERMDA H_THERMDC 3 H_THERMDC SCL 10 THERM_SCL DP1 SDA 9 THERM_SDA 3 DN1 ALERT# 8 THERM_ALERT#_C DP2 SYS_SHDN# 7 DN2 GND 6 5 B THERM_STP# 31,52 1 +3.3V_RUN 1 C74 0.1U +3.3V_RUN R89 1M 3 10 2 +3.3V_RUN C 17,26,31 SMBCLK1 3 C92 0.1U 1 THERM_SDA 1 2 2 Q15 2N7002W-7-F Q14 2N7002W-7-F 1 R84 10K 1 3 1 2 2 R71 10K 2 2 1 2 10 Q13 2N7002W-7-F THERM_ALERT# 13 Q11 2N7002W-7-F SYS_SHDN# 2 +3.3V_RUN THERM_ALERT# 3 SMSC_EMC 1423 50 cap should close to thermal IC 1 close to IC 1 C69 2200P B VDD 2 4 2 3 H_THERMDA 1 2 C740 2200P_NC 2 2 2 1 Q68 MMST3904-7-F +3.3V_RUN 1 3 REM_DIODE1_P 17,26,31 SMBDAT1 8 DA204U_NC D5 FAN1_PWM 3 4 3 2 1 3 C196 2.2U 4 3 2 1 FAN1_PWM 31 FAN1_PWM 1 2 1 A J6 +FAN1_VOUT 2 805 2 1 6 +5V_RUN D7 SSM34PT_NC 1 2 +5V_RUN 5 2 1 OTP 85 degree C Q16 2N7002W-7-F R70 +3.3V_RUN THERM_SCL 1 R83 1 10K/F 2 THERM_ALERT#_C 1 2 6.8K/F SYS_SHDN# C D D QUANTA COMPUTER Title FAN & THERMAL 1 2 3 4 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 39 8 62 1 NC/CD_L NC/CD_GND NC/CD_R 13 34 EAPD# R489 0 2 3 DMIC0/VOL_UP/GPIO1 DMIC1/VOL_DN/GPIO2 39 41 37 2 1 1 1 2 2 2 5 1 2 3 2 2 5 1 AMP_HP2_EN 4 EAPD# 2 U24 TC7SZ08FU(T5L,F,T) +5V_RUN PORT_B_L PORT_B_R VREFOUT_B 21 22 28 PORT_C_L PORT_C_R VREFOUT_C 23 24 29 PORT_D_L PORT_D_R VREFOUT_D 35 36 32 PORT_E_L PORT_E_R GPIO4/VREFOUT_E 14 15 31 PORT_F_L PORT_F_R GPIO3/VREFOUT_F 16 17 30 PORT_G_L PORT_G_R 43 44 PORT_H_L PORT_H_R 45 46 PC_BEEP CAP2 VREFFILT 12 33 27 AVSS1 AVSS2 26 42 BLM21PG600SN1D 2 L81 AUD_HP1_L 41 AUD_HP1_R 41 AUD_INT_MIC_IN 41 AUD_FRONT_L AUD_FRONT_R C484 1U 603 10 FB_60ohm+-25%_100MHz _3A_0.05ohm DC C876 10U 805 10 Layout Note: Place close to pin 8. Close to U31 AUD_MIC_L 41 AUD_MIC_R 41 AUD_MIC1_VREFO 41 AUD_HP2_L0 AUD_HP2_R0 C622 AUD_PC_BEEP 1 603 1U R541 2BEEP2 2 10 10K 1 BEEP1 +VDDA C614 0.1U 16 2 1 1 BEEP 31 2 SPKR 13 4 R544 2.2K 603 U33 74LVC1G86GW D 4 7 DMIC_CLK/GPIO0/SPDIF_IN SPDIF_OUT_0 DVSS1 DVSS2 0_NC 92HD73C1X5PRGXB2X 2 3 4 QUANTA COMPUTER AUD_PC_BEEP 5 1 47 48 0_NC 0 C613 10U 805 10 2 41 DMIC_CLK R488 DMIC_DATA R515 R514 1 10 4 AMP_HP2_EN_L +5V_SPK_AMP 1 1 3 EAPD# 1 Q73 2N7002W-7-F 0 0_NC 1 C537 0.1U 0 2 31 NB_MUTE# R487 0_NC U25 TC7SZ08FU(T5L,F,T) SENSEA SENSEB 2 1 2 R491 10K_NC 1 Q71 2N7002W-7-F DMIC_DATA R512 EAPD# R518 DVDD R785 10 2 2 2 1 3 +3.3V_RUN HP2_JD C538 0.1U C PORT_A_L PORT_A_R NC/VREFOUT_A R71,R69 close to U1, Let DVDD width be 10-mils R759 100K R438 0_NC 1 2 +3.3V_RUN 3 SENSE_A SENSE_B 16 5 HDA_BITCLK HDA_SDI HDA_SDO HDA_SYNC HDA_RST# 25 38 B R755 0_NC +3.3V_RUN NB_MUTE# C590 0.1U 10 2.2K_NC 1 3 +5V_SPK_AMP D Layout Note: Place close U23. C878 0.033U 1 6 8 5 10 11 18 19 20 41 DMIC_DATA C495 0.1U 10 R757 2 SPKR_INR- 2 AZ_CODEC_SDIN0 AVDD AVDD C623 1U 10 603 +VDDA C506 1U 603 10 1 0_NC 1000P_NC 2 DVDD_CORE DVDD_CORE DVDD Layout Note: Close to U1 Pin 13 2 C480 10U 805 10 C507 1U 603 10 3 1 2 33 1 9 40 Q59 2N7002W-7-F EAPD# C488 1U 603 10 Layout Note: Place close to pin 18. TPA6040A4 HP1_JD 41 R758 100K +5V_SPK_AMP 1 GND_28 PGND_5 PGND_21 28 5 21 +5V_SPK_AMP 1 30 8 18 2 29 VDD PVDD_8 PVDD_18 1 VOUT AMP_HP1_SHUD# 41 U22 TC7SZ08FU(T5L,F,T) +VDDA SPKR_INLSPKR_INR- 4 1 U31 10 4 2 AUD_HP2_L1 41 AUD_HP2_R1 41 AZALIA (HD) CODEC C597 0.1U 1 EAPD# 2 R525 1 2 2 PVSS CPVSS 10 3 14 13 50 C532 0.1U AMP_HP1_SHUD_L# 4 2 C1P C1N CPGND 16 15 2 C617 1U 10 603 1 2 10 12 11 U23 TC7SZ08FU(T5L,F,T) 1 HP1_JD 1 HPVDD CPVDD HPR SPKR_INLSPKR_INR- 10 NB_MUTE# AUD_SPK_R1 AUD_SPK_R2 20 19 50 1 11 ICH_AZ_CODEC_BITCLK 11 ICH_AZ_CODEC_SDIN0 11 ICH_AZ_CODEC_SDOUT 11 ICH_AZ_CODEC_SYNC 11,31 ICH_AZ_CODEC_RST# AUD_SPK_ENABLE# 1 1 2 2 1 17 9 TPA6040A4 OUTR+ OUTRQFN 32PIN HPL AUD_SPK_L1 AUD_SPK_L2 6 7 1 1 2 C601 1U 10 603 1 1 2 1 2 1 BIAS SPKR_EN# HP_EN REG_EN GAIN1 GAIN2 DVDD R492 C591 1 3 2 1 24 23 22 25 31 32 C877 1U 805 16 +VDDA 50 HP_INL HP_INR OUTL+ OUTL- +VDDA 2 C627 1000P 2 2 1U 16 SPKR_INL+ SPKR_INR+ 27 26 FB_60ohm+-25%_100MHz _3A_0.05ohm DC 2 R549 39.2K/F C482 C483 1 1U 805 603 10 MIC1_JD 41 R493 0_0805 C C481 10U 805 10 Q75 2N7002W-7-F 1 1 1 2 3 2 2 +3.3V_RUN 50 LINRIN- MLX_48227-0401 C865 100P +3.3V_RUN 1 +VDDA 2 50 50 C864 100P R429 0_NC 1 2 C533 0.1U U20 15 C505 1 50 +3.3V_RUN R708 2.2K 2 HP2_OUT_L 1 2.2K 2 HP2_OUT_R 1 R737 10 2 1U 603 AUD_SPK_ENABLE# AMP_HP2_EN REGEN AUD_AMP_GAIN1 AUD_AMP_GAIN2 1AUD_HP2_L0_R 1AUD_HP2_R0_R C914 1000P +3.3V_RUN R539 5.1K/F 603 603 603 603 2 2 0.01U 1206 2 0.01U 1206 2 2 R780 39.2K/F 2 1 50 C863 100P A 2 C519 1 C518 1 3 2 3 2 1 1 1 1 R779 20K/F Q74 2N7002W-7-F 0 0 0 0 REGEN 1 AUD_HP2_L0 AUD_HP2_R0 SENSEB 41 HP2_JD 1 1 1 1 C861 100P 1 2 3 4 C879 0.033U 16 2 1206 2.2U 50C525 2 50C524 2 1206 2.2U R782 5.1K/F B R450 R555 R373 R310 1 1 2 AUD_FRONT_L AUD_FRONT_R Layout Note: Place close U23 pin 23. Layout Note: Close to U1 Pin 34 2 0 805 2 2 2 2 0_NC INTERNAL SPEAKER AMP C882 0.1U 10 R558 1 18 C=1/2*pi*400*amp input R 19 SENSEA 1 R756 SPKR_INL- EMI Request 2 1 1 2 1 2 C880 1U 603 10 R753 100K 15 R407 100K_NC +5V_SPK_AMP C881 1U 603 10 50 1 2 3 4 5 21.6dB 50 5 1 50 J3 AUD_SPK_R1 AUD_SPK_R2 AUD_SPK_L1 AUD_SPK_L2 +5V_SPK_AMP 1 1 50 8 HP2_OUT_R C521 220P 1 15.6dB C522 220P 7 2 10dB 0 HP2_OUT_L C502 47P_NC 6 1 1 C503 47P_NC 5 2 0 1 RIN1 6dB 1 R410 100K A AUD_AMP_GAIN1 AUD_AMP_GAIN2 LIN- GAIN 0 2 2 1 R408 100K 1 R409 100K_NC GAIN2 0 4 2 2 2 GAIN1 2 +5V_SPK_AMP 3 2 2 1 1 Title C605 1U 603 10 Azelia CODEC 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 40 8 62 1 2 3 4 5 6 7 8 +3.3V_RUN Array Microphone & Camera 2 Headphone Jack Stereo MIC Jack R289 100K 1 JCAMERA1 1 2 3 4 5 6 7 8 9 10 USBP4_D+ USBP4_D+3.3V_CCD CAMERA_CBL_DET# A L36 40 DMIC_DATA 40 DMIC_CLK 13 CAMERA_CBL_DET# 0 22 ohm 603 DMIC_DATA_R 603 DMIC_CLK_R CAMERA_CBL_DET# L35 A I-pex 20374-010E-1 1 DMIC_DATA L41 BLM18AG121SN1D +3.3V_CCD +3.3V_RUN 1 1 C364 10U 805 10 2 2 1 2 C373 10U 805 10 JAUDIO1 JACK 2 (MIC) JACK 1 (HP2) JACK 3 (HP) 40 AUD_HP2_L1 40 AUD_HP2_R1 AUD_HP1_L1 AUD_HP1_R1 MIC1_JD HP2_JD HP1_JD 40 MIC1_JD 40 HP2_JD 40 HP1_JD C357 33P_NC 50 B L46 1 4 12 ICH_USBP412 ICH_USBP4+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 40 AUD_MIC_L 40 AUD_MIC_R DMIC_CLK 603 B 40 AUD_MIC1_VREFO C358 33P_NC 50 2 +3.3V_CCD trace width use 25 mils USBP4_DUSBP4_D+ 2 3 PLW3216S900SQ2T1_NC 1 R312 1206 1 R313 0 0 2 2 +VDDA 48227-1501 MIC1_JD R584 100K 8 3 C578 1 1206 D C1P C1N PVSS SVSS MAX4411ETP 2 50 2 2 2 9 11 4 6 8 12 16 20 10 19 2 17 AUD_HP1_L1 AUD_HP1_R1 R583 1K INT_MIC_C_L- +3.3V_RUN C557 1U 805 16 C668 2.2U 805 10 1 INT_MIC_L1- R832 2 10K 1 INT_MIC_L0+ 2 R833 1 INT_MIC_L010K C971 0.1U 10 U51B LM358ADR2G C970 0.1U INT_MIC_IN_OP 2 1 5 7 6 603 1 R837 2 OUTL OUTR NC1 NC2 NC3 NC4 NC5 NC6 SVDD PVDD PGND SGND 1 SHDNR SHDNL 5 7 C987 220P 15 1 14 18 1 3 AUD_HP1_R0 1 50 1 C986 220P 2 2 1 AUD_HP1_L0 2 2.2U 25 INL INR 1 INT_MIC_L1+ C963 0.1U 603 16 AUD_INT_MIC_IN 40 16 2 100K D22 SM05_NC R582 1K 3 40 AMP_HP1_SHUD# 13 15 1 AUD_HP1_L0 AUD_HP1_R0 2 2 AUD_HP1_L21 AUD_HP1_R21 +VDDA D Layout Note: Place close to CODEC. QUANTA COMPUTER 1 2 2.2UF 50V 2 C586 1 1206 U29 1 40 AUD_HP1_R R738 2.2K 2 2.2K 2 R739 2 2 2.2UF 50V 1 C567 1 1206 0 1 1 1 C962 0.1U 603 16 2 1 INT_MIC_2_L40 AUD_HP1_L R826 2 R580 1K INT_MIC_2_L+ 15 1 R835 100K 2 C664 2.2U 805 10 1 1 1 2 1 2 2 INT_MIC_C_L+ C665 2.2U 805 10 2 JP11 HS8102E HP1_JD 1 100K 2 R581 1K 100K R412 2 C U51A LM358ADR2G 1 HP2_JD 1 2 2 +3.3V_RUN +VDDA 8 100K R414 4 1 C 4 2 2 R419 Title C556 2.2U 1206 10 AUDIO CONN 3 4 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet 41 8 of 62 5 4 3 Core Power Decoupling +1.2V_LOM C420 0.1U 10 X7R C392 0.1U 10 X7R C391 0.1U 10 X7R C450 0.1U 10 X7R C445 0.1U 10 X7R C396 0.1U 10 X7R C370 0.1U 10 X7R C369 0.1U 10 X7R +2.5V_LOM D R347 0 805 R371 0_NC 805 C401 0.1U 10 X7R C406 0.1U 10 X7R 5 55 13 20 34 60 L48 BLM18AG601SN1D 1 2 68 BIASVDDH 36 LAN_BIASVDDH XTALVDDH 23 LAN_XTALVDDH AVDDL/AVDDH 45 R349 R346 DC/AVDDH 38 DC/AVDDH 52 VDDC_IO/VDDC VDDC_IO/VDDC VDDC VDDC VDDC VDDC VDDIO Power Decoupling +2.5V_LOM R376 0 805 U15 DC/VDDP +2.5V_LOM VDDIO VDDIO VDDIO VDDIO VDDIO +1.2V_LOM VDDP Power Decoupling 1 +3.3V_LAN R370 0_NC 805 6 15 19 56 61 C456 4.7U 10 X5R 805 2 +2.5V_LOM +3.3V_LAN R301 0_NC 805 C407 0.1U/10V L43 BLM18AG601SN1D 1 2 D C388 0.1U/10V +LAN_AVDDL +LAN_AVDDH L53 BLM18AG601SN1D 1 2 0 0_NC Place one cap close to each of the pins, 38,45, and 52 +3.3V_LAN C417 4.7U 10 X5R 805 C393 0.1U 10 X7R C451 0.1U 10 X7R BCM5784M/5787M +1.2V_LOM L54 BLM18AG601SN1D 1 2 C449 0.1U 10 X7R +LAN_AVDDL C452 L47 BLM18AG601SN1D 1 2 R309 2 2 C397 L45 BLM18AG601SN1D 1 2 LAN_XTALI C421 0.1U/10V +LAN_GPHYPLLVDDL 1 200/FLAN_XTALO Y1 1 4.7U/10V/0805 39 51 4.7U/10V/0805 35 C400 4.7U/10V/0805 30 C385 AVDDL AVDDL 68-Pin QFN C383 27P 50 NPO L44 BLM18AG601SN1D 1 2 +LAN_PCIESDSVDDL C378 GPHY_PLLVDDL 49 50 AVDDH/TRD2_N TRD2_N/TRD2_P TRD2_P/AVDDL 48 47 46 AVDDH_LAN_TRD2N LAN_TRD2N_TRD2P LAN_TRD2P_AVDDL AVDDH/TRD1_N TRD1_N/TRD1_P TRD1_P/AVDDL 42 43 44 AVDDH_LAN_TRD1N LAN_TRD1N_TRD1P LAN_TRD1P_AVDDL TRD0_N TRD0_P 41 40 TRD0- 43 TRD0+ 43 LINKLED# SPD100LED# SPD1000LED# TRAFFICLED# 2 1 67 66 LINKLED# 43 SPD100LED# 43 SPD1000LED# 43 IO_LOM_ACTLED_YEL# 43 PCIE_PLLVDDL 0.1U/10V +LAN_PCIEPLLVDDLR305 R306 0 0_NC R307 R308 0 0_NC 4.7U/10V/0805 C384 C 0.1U/10V TRD3_N TRD3_P 25MHz C368 27P 50 NPO 0.1U/10V C444 TRD3- 43 TRD3+ 43 0.1U/10V 27 33 PCIE_PLLVDDL PCIE_VDDL 24 PCIE_VDDL/GND GPIO2 8 LAN_GPIO T30 +3.3V_LAN 10 R337 R336 0 0_NC +3.3V_LAN 65 63 64 62 LAN_TRD2N_TRD2P TRD2+ TRD2- AVDDH_LAN_TRD1N R360 R338 R328 R327 0_NC 0 0_NC 0 +LAN_AVDDL TRD2+ TRD1+LAN_AVDDH LAN_TRD1N_TRD1P R335 R330 0_NC 0 TRD1+ TRD1- LAN_TRD1P_AVDDL R333 R344 0_NC 0 +LAN_AVDDL TRD1+ TRD2- 43 TRD2+ 43 TRD1- 43 TRD1+ 43 C +3.3V_LAN BCM_WP R381 4.7K SCLK_EECLK SI SO_EEDATA CS# TRD2+LAN_AVDDH 0_NC 0 1 9 7 4 1 UART_MODE GPIO1_SERIALDI GPIO0_SERIALDO PCIE_TXD_P PCIE_TXD_N PCIE_RXD_P PCIE_RXD_N WAKE# PERST# PCIE_REFCLK_P PCIE_REFCLK_N 0_NC 0 R345 R348 R379 4.7K_NC R382 4.7K C414 0.1U 10 X7R U18 2 26 25 31 32 12 10 29 28 2 LAN_PCIETXDP LAN_PCIETXDN 2 2 0.1U 1 10 C386 1 2 0.1U C387 1 R357 R361 R381 & R382: Stuff only if U18 is installed PAD 12 PCIE_RX6+/GLAN_RX+ 12 PCIE_RX6-/GLAN_RX12 PCIE_TX6+/GLAN_TX+ 12 PCIE_TX6-/GLAN_TX13,30,33,34 PCIE_WAKE# 6,12,25,30,33,34 PLTRST# 12 SB_LOM_PCIE_RST# 17 CLK_PCIE_LOM 17 CLK_PCIE_LOM# AVDDH_LAN_TRD2N LAN_TRD2P_AVDDL 0.1U/10V +LAN_PCIEPLLVDDL C379 C416 10mm x 10mm 8 7 6 5 BCM_SCL SI BCM_SDA CS# VCC NC SCL SDA 1 2 3 4 A0 A1 A2 VSS 24LC02BT-I/STG BCM_SCL R380 4.7K SI R369 4.7K CS# R368 4.7K R385 +3.3V_RUN 4.7K R378 4.7K +3.3V_LAN ENERGY_DET T34 T33 PAD T32 PAD T31 PAD 54 53 3 VAUX_PRSNT VMAIN_PRSNT LOW_PWR 58 57 TEST1/SMB_CLK TEST2/SMB_DATA LAN_XTALO LAN_XTALI 22 21 XTALO XTALI LAN_RDAC 37 RDAC R332 2 +2.5V_LOM VDDC_IO/VDDP 17 REGOUT12_IO/REGCTL25 18 R320 C428 0.1U_NC 10 X7R 0 LAN_REGCTL25 1 4.7K_NC REGCTL12 14 1 C419 0.1U 10 X7R 1 LAN_REGCTL12 C425 4.7U 10 X5R 805 Q41 MMJT9435T1G 1 LOMCLK_REQ# 5787M 5784 A CLK_REQ# C455 0.1U 10 X7R Package Body SUPER_IDDQ/GND R325 16 69 NOT INSTALL R574,R576,R529,R562,R564, R569,R571,R573,R585,R505, R578,R580,R582 11 GND Pull-down R331 for 5787M. R575,R577,R527,R534,R563, R568,R570,R572,Q101,C1721, C1722,C1723,C1724,R579,R581, R583,R575,L79,R648,R649 C413 0.1U_NC 10 X7R B C426 10U_NC 10 X7R 805 2 4 1 0_NC Table 1 - Component Stuffing Requirements INSTALL +2.5V_LOM +1.2V_LOM LOMCLK_REQ# R331 2 C424 4.7U_NC 10 X5R 805 Q38 MMJT9435T1G_NC 1 +3.3V_LAN R362 2 R326 1.24K/F +3.3V_LAN +3.3V_LAN 3 1K 1K 2 4 pin 57,58 5784 pull-up 4.7k to 3.3V_LAN 5787M connect SM-BUS to support ASF. LAN_ENERGY_DET 3 2 R384 R383 31 LAN_DISABLE# B 59 PAD 2 LAN_DISABLE# is hign active 1 1 R8093 & R8094: Stuff only if no pull-ups on system side BCM5784 Note:thermal pad 1 20K_NC R8101 is required only if Q1 can not dissipate the required power LAN_DISABLE# 31 5784M 5787M (12) R574,R576,R529,R562,R564, R569,R571,R573,R585,R505, R578,R580,R582 0 R311 2 C454 10U 10 X7R 805 R325 39k 0 R311 20k *20k_NC R575,R577,R527,R534,R563, R568,R570,R572,Q101,C1721, C1722,C1723,C1724,R579,R581, R583,R575,L79,R648,R649 A QUANTA COMPUTER Title LAN 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 42 of 62 A B C D E RJ-45 Connector CON3 TRANSFORM R316 1 42 IO_LOM_ACTLED_YEL# 330 2 +3.3V_LAN RJ45-TX3RJ45-TX3+ RJ45-TX1RJ45-TX2RJ45-TX2+ RJ45-TX1+ RJ45-TX0RJ45-TX0+ +3.3V_LAN 42 TRD1+ 42 TRD1- 42 TRD2+ 42 TRD2- 2 TD0- TDCT 3 TDCT0 TDCT 4 TDCT1 TRD1+ 5 TD1+ 6 TD1- TRD2+ 7 TD2+ TRD2- 8 TD2- TDCT TRD3+ 42 TRD3- 9 TDCT2 TDCT 10 TDCT3 TRD3+ 11 TD3+ TRD3- TX0- 23 RJ45-TX0- TXCT0 22 TXCT0 TXCT1 21 TXCT1 TX1+ 20 RJ45-TX1+ TX1- 19 RJ45-TX1- TX2+ 18 RJ45-TX2+ 12 1:1 1:1 D9 1 42 SPD100LED# 47K 2 CH751H-40PT +3.3V_LAN TX2- 17 RJ45-TX2- 16 TXCT2 TXCT3 15 TXCT3 TX3+ 14 RJ45-TX3+ TX3- 13 RJ45-TX3- R691 D35 1 2 1 2 LED_GND 9 11 LED_GN/AP LED_GP/AN 1 47K 2 G DTA114YUA 2 10K R254 2 330 1 1 3 10 10 10 10 10 10 10 10 C984 7p_NC +3.3V_SUS 2 2 C983 7p_NC 2 1 1 C982 7p_NC 2 C981 7p_NC TRD0+ 2 C980 7p_NC TRD0- 2 C979 7p_NC TRD1+ 1 1 TRD1- 2 C978 7p_NC 10 O 330 1 CH751H-40PT 2 C977 7p_NC R250 2 Q27 CH751H-40PT D10 42 LINKLED# TRD2+ 1 TRD2- 4 +3.3V_LAN D36 2 1 TRD3+ 8 7 6 5 4 3 2 1 4.7K 42 SPD1000LED# TD31:1 MGG3S-00006 or H5120NL 1 TRD3- 3 DTA114YUA 2 8 7 6 5 4 3 2 1 10K TXCT2 1:1 Q28 3 42 RJ45-TX0+ TD0+ TRD0- TRD1- 24 Y CHSGND1 CHSGND2 TRD0- TX0+ LED_YP 14 15 42 1 MEDIA SIDE 3 TRD0+ CHIP SIDE LED_YN 13 1 42 TRD0+ 1 L80 4 12 R317 0_0805 1 FOR EMI requirement and should close to L80 +3.3V_LAN +2.5V_LOM TXCT0 TXCT1 TXCT2 TXCT3 2 2 0603 package. L42 BLM18AG601SN1D_NC 75/F 75/F 75/F 75/F RJ45-TX0+ pop L75 for 5787M. depop L75 for 5784M. C338 1000P 3K NPO 1808 1 1 R300 0_NC R744 R745 R746 R747 2 1 2 C315 0.1U 2 1 1 C356 0.1U 2 C359 0.1U 2 1 TDCT 10 10 10 10 C309 0.1U RJ45-TX1+ RJ45-TX2+ RJ45-TX3+ 3P C845 RJ45-TX0- 3P C854 RJ45-TX1- 3P C855 RJ45-TX2- 3P C860 RJ45-TX3- layout note: cap should close to transformer one cap mapping one pin layout note: cap should close to CONN Reserved for EMI. Reserved for EMI. 2 1 1 Title QUANTA COMPUTER LAN SWITCH A B C D Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet E 43 of 62 1 2 3 4 5 6 7 8 5 +3.3V_ALW U26 74AHCT1G08GW A 13,31,51 IMVP_PWRGD 2 31 RESET_OUT# 1 A 4 6,13 3 ICH_PWRGD Keep Away from high speed buses +3.3V_ALW B B 14 R426 0 49 1.25V_RUN_PWRGD R428 1 2 0 1 48 1.5V_RUN_PWRGD R424 1 2 0 2 U21A 3 U21C SN74AHC08PW 9 8 10 U21B 52 3V_ALW_PWRGD R422 1 52 5V_ALW_PWRGD R420 1 2 0 4 2 0 5 SN74AHC08PW 6 SN74AHC08PW U21D 12 R423 1 48 1.05V_RUN_PWRGD 11 0 2 HWPG 31 13 SN74AHC08PW C C +3.3V_ALW 5 U32 74AHCT1G08GW 49 1.8V_SUS_PWRGD 2 31 RUN_ON_1 1 RUN_ON 20,26,48,49,53 3 4 R527 1 2 0_NC D D R526 1 R530 1 10K_NC 2 10K_NC 2 QUANTA COMPUTER RUN_ON RUN_ON_1 Title System Reset Circuit 1 2 3 4 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 44 8 62 3 TH6 H-C256D130P2 4 5 TH7 H-TC276BC354D126P2 1 TH5 H-TC394BC315D126P2 1 TH4 H-TC394BC315D126P2 1 TH3 H-TC276BC236D126P2 1 1 TH2 H-TC276BC236D126P2 1 TH1 H-C394D126P2 2 1 1 A A 1 TH20 H-C315D157I197P2 TH23 H-TC197BC236D65P2 1 TH19 H-TC276BC236D110P2 1 1 1 TH14 H-C433D433N 1 1 1 TH18 H-C315D157I197P2 TH13 H-C256D126P2 1 TH17 H-C315D157I197P2 TH12 H-C315D126P2 1 TH16 H-TC394BC236D126P2 TH11 H-C315D157I197P2 1 TH15 H-C276D126P2 TH10 H-C315D157I197P2 1 TH9 h-c315d189p2 1 1 TH8 H-TC394BC276D126P2 B B 1 TH30 H-TC394BC315D126P2 TH36 h-o71x118d31x78p2 1 TH32 h-o71x118d31x78p2 1 TH35 h-c236d110p2 TH29 H-TC275BC492D110P2 1 TH28 H-TC197BC236D65P2 1 1 1 TH34 h-c236d110p2 TH27 H-TC197BC236D104P2 1 TH33 H-C118D118N 1 1 TH31 h-tr8x9bc276d126p2 TH26 H-TC197BC236D65P2 1 TH25 H-TC197BC236D104P2 1 1 TH24 H-TC197BC236D65P2 C C D D Title QUANTA COMPUTER Battery Selector 1 2 3 4 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 5 45 of 62 A B C D E +PWR_SRC Id=9.6A@Vgs=10V PQ24 SI4835BDY-T1-E3 PQ4 SI4835BDY-T1-E3 PR27 0.01/F/2512 PC153 PR29 PR28 10K 100K PQ9 2 1 2N7002W-7-F CSSN 1 PC143 0.1U/50V/0603 2200P/50V +DC_IN_SS PR131 470K CSSP 3 4 1 HI1206T161R-10 8 7 6 5 2 4 1 1 2 3 CHGR_IN 4 1 2 3 3 8 7 6 5 +DC_IN_SS +DC_IN_SS FL5 +DC_IN_SS PR150 10K/F PC60 PC58 0.01U/25V 0.01U/25V CCI CSIP 18 CSIN 17 FBSA 15 CCS 3 REF 8731REF PC61 PC59 10U/25V/1206 1 5 6 7 8 PR143 1/0603 DLO PR122 0.01/F/2512 2 PR147 2.2/0805 4 RDS(ON)=21m ohm PQ29 HI1206T161R-10 +VCHGR 54 PC9 PC12 PC17 PC154 1000P/50V SI4812BDY-T1-E3 PR39 FBSB 4 PL3 5.8UH 30% 5.5A 24m(SIL104R-5R8PF) CHG_CS 1 CSIP PC20 PC125 PC129 PC135 PC24 10U/25V/1206_NC CCV 5 0.1U/10V PC157 6 1U/10V/0603 PC56 0.01U/25V 3 0.1U/10V PR48 8.45K/F IINP 20 19 Adress : 12H 8 DLO 3300P/50V Max Charging current setting 4.7A +VCHGR CSIN 100 16 PC54 220P/50V GND IINP IINP 23 LX PGND 12 GNDA_CHG SMBUS Address 12 31 SCL SDA BATSEL 7 31,54 SMBCLK0 31,54 SMBDAT0 LX DAC PC53 0.1U/50V/0603 10 9 14 PC151 PC55 DHI 10U/25V/1206 24 FL4 10U/25V/1206 26 DHI 2 PQ30 SI4800BDY-T1-E3 10U/25V/1206 VCC RDS(ON)=30m ohm 0.1U/50V/0603 VDD PR38 15.8K/F PC50 0.1U/50V/0603 4 1U/10V/0603 2200P/50V ACOK 11 PR40 33/F/0603 1000P/50V 13 21 3300P/50V +3.3V_ALW LDO 4 PR46 BST 25 BST 3 0 LDO 1 2 3 31 ACAV_IN 2200P/50V CSSN ACIN 0.01U/25V PC57 PC150 1U/10V/0603 PC148 5 6 7 8 PR41 10K/F 0/0603 PC147 1 2 3 2 2 DCIN PR47 27 1 8731_ACIN GND 22 49.9K/F CSSP LDO 28 PC51 1U/25V/0805 PR49 PC144 PC152 0.1U/50V/0603 PD12 SDM10K45-7-F PR50 365K/F 10U/25V/1206 2 LDO TABLE 1 PU3 PR145 ADAPTER(W) TRIP CURRENT (A) 3 PR152 PR157 PR153 PR154 0/0603 GNDA_CHG 65 3.17 57.6K 13K 105 N/A 90 4.43 51.1K 17.8K 348 33.2K 130 6.43 32.4K 20.5K 100 27.4K 150 7.43 30.9K 24.9K 432 88.7K 200 230 11.28 (see note3) 9.75 19.1K 32.4K 28K 6.49K 301 115 36.5K N/A +3.3V_ALW +5V_ALW +5V_ALW PR155 100K_NC PC159 4 SEE TABLE 1 3 + 2 - PC160 PC158 4 PC161 100P/50V_NC PR157 17.8K/F_NC 0.01U/25V_NC 0_NC PR151 0.01U/25V_NC 31 ADAPT_TRIP_SEL PC163 ADAPT_OC 31 PR149 100K_NC PU7A 1 3 33.2K/F/0603_NC 100P/50V_NC PR154 8 SEE TABLE 1 PC162 PQ31 2 1 PR148 1M/F_NC SEE TABLE 1 100P/50V_NC PR152 51.1K/F_NC 0.01U/25V_NC SEE TABLE 1 LM393DR2G_NC 2N7002W-7-F_NC PC156 0.1U/10V_NC PR156 1K_NC Note 1: PR96 is popluated if ADAPT_TRIP_SEL is used to program for the next lower adapter. ADAPT_TRIP_SET is floating for the higher adaptor, grounded for the lower adaptor. Note 2: 24.9K at PR96 allows the 65W adaptor seetting to switch down to 45W. 4 Note 3: PR35 must be 5mOhms instead of 10mOhms for the 230W adaptor. PR153 348/F/0603_NC SEE TABLE 1 Title For GPRS immunity place PC41 & PC39 as close to the IC as possible Charger (ISL88731) GNDA_CHG A B C QUANTA COMPUTER D Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet E 46 of 62 1 2 3 4 5 A A BLANK PAGE FOR PAGE NUMBER SAME AS DISCRETE B B C C D D Title 1 2 3 4 QUANTA COMPUTER Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 5 47 of 62 5 4 3 2 1 +PWR_SRC FL6 HI1206T161R-10(160,6A) +DC_PWR_SRC PC164 0.1U/16V_NC VBST 14 2 TON DRVH 13 3 VOUT 4 V5FILT 5 VFB V5DRV PGOOD GND DRVL PGND PC64 1U/10V/0603 10 +1.05V_VCCP_P 6 +5V_ALW 51117DL 9 PQ33 FDS6680AS_DU 4 PC168 0.1U/10V PR58 2.2/F/0603_NC PC62 8 PC66 1U/10V/0603 0.1U/10V_NC PC63 +3.3V_SUS 51117LX 15 7 PR159 100K 12 11 Frequency=300KHz PL7 1.5UH 30% 10A(SIL104R-1R5PF)_DU 2 1 5 6 7 8 9 6 44 1.05V_RUN_PWRGD LL TRIP PC165 0.1U/50V/0603 1 2 3 51117_FB EN_PSV THERM +1.05V_VCCP_P PR53 300/0603 +5V_ALW PR160 0/0603 TPS51117RGYR PU8 1 PQ32 FDS8878_DU 4 +1.05V_VCCP(UMA) TDC : 12.1A OCP : 17.2A Iout_ripple current : 2.605A D PR51 80.6K/F/0603 PR161 10K/F_DU PC71 2200p/50V_NC PR54 0/0603 10 +1.05V_VCCP(DIS) TDC : 7A PC169 OCP : 10A + Iout_ripple current : 2.459A 330U/4V/ESR25 PR158 0 C +1.05V_VCCP 1 2 3 51117DH 26,44,49,53 RUN_ON PC167 10U/25V/1206 0.015U/50V/0603_NC D PC166 10U/25V/1206 PC68 0.1U/50V/0603 5 6 7 8 9 PC69 2200P/50V C 51117_FB PR55 237K/F PR52 200K/F/0603 UMA(12.1A) Discrete(7A) PQ32 FDS8880_NL (BAM88800012) FDS8878 (BAM88780020) PQ33 FDMS8672S (BAM86720000) FDS6680AS (BAM66800061) PL7 SIL105RA-1R3 (CV-13E0MZ00) SIL104R-1R5PF (DC-15A00010) PR161 11K/F (CS31102FB11) 10K/F (CS31002FB26) +1.8V_SUS B B PC82 +3.3V_SUS +3.3V_RUN PR182 100K_NC PU5 10 2 PR183 100K_NC PR66 100K PR64 0/0805 L6935_ADJ 1 44 1.5V_RUN_PWRGD 20,26,44,49,53 RUN_ON PR65 Max current->2.06A 10U/25V/1206 7 0 PC81 0.1U/10V PC83 0.1U/10V PC85 680P/50V 8 9 10 VIN1 VIN2 VIN3 19 5 6 7 20 ADJ PGOOD VBIAS EN SS 2 21 GND GND VOUT1 VOUT2 VOUT3 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 +1.5V_RUN_P 16 17 18 +1.5V_RUN 10 1 3 4 11 12 13 14 15 PC84 R1 0.1U/10V_NC 7 PR68 20K/F PC86 22U/10V/1206 L6935_ADJ L6935TR R2 PR67 10K/F A A VOUT=0.5 x( 1+R1/R2) Title 5 4 3 2 QUANTA COMPUTER Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 48 of 62 5 4 3 UMA(10.25A) 2 Discrete(15.6A) PQ35 FDS8880_NL (BAM88800012) FDS6298 (BAM62980005) PQ34 PHK28NQ03LT (BAM28030Z12) FDMS8672S (BAM86720000) 1 PR169 0_NC S3_1.8V S5_1.8V PC179 0.1U/10V PC178 0.1U/10V +1.8V_SUS(DIS) TDC : 15.6A OCP : 22.4A Iout_ripple current : 4.896A D D 10.5K/F/0603 (CS31053F909) +1.8V_SUS(UMA) TDC : 10.25A OCP : 14.9A Iout_ripple current : 4.868A +1.8V_SUS_P PC171 10U/10V/0805 DIS_MODE PR164 +V_DDR_MCH_REF 0/0603 5VIN PC173 3300P/50V LL 18 +1.8V_LX GND DRVL 17 +1.8V_DL VTTGND PGND 16 S3 11 S3_1.8V PR175 0 S5 12 S5_1.8V PR174 0 VTTSNS 5 3 6 MODE 7 VTTREF 8 COMP 9 VDDSNS 10 V5IN 14 PGOOD 13 CS 15 VDDQSET PC177 1 2 3 VBST VTT 4 0 PC185 0.1U/50V/0603 10U/25V/1206 10U/25V/1206 2.2/0805 0.1U/50V/0603 PC180 2200P/50V C PL8 NEC_MPC1040LR88C_0.88uH +1.8V_SUS_P +1.8V_SUS PC95 PC170 PR170 RUN_ON 20,26,44,48,53 SUS_ON 31,53 5VIN PR173 2.2/0805_NC PQ34 FDMS8672S_DU 4 100K/F +3.3V_ALW + PC181 2200P/50V_NC + 1.8V_SUS_PWRGD 44 21 22 23 24 25 26 27 PR165 0 FOR DDR II 10 PC94 330U/2.5V/ESR15_DIS 10 PC175 10U/10V/0805 PR168 PC186 0.1U/25V/0603 +0.9V_DDR_VTT 19 20 PC184 Frequency=400KHz +1.8V_DH DRVH VLDOIN 2 PC183 5 6 7 8 9 1U/10V/0603 1 2 3 1 C GND GND GND GND GND GND GND PC172 PR171 PQ35 FDS6298_DU 4 PU9 TPS51116_8 +PWR_SRC FL7 HI1206T161R-10 2200P/50V 5 6 7 8 9 +DC2_PWR_SRC 330U/2.5V/ESR15 PR172 13.3K/F/0603 (CS31333F919) PC182 PR163 0 PR172 13.3K/F/0603_DU 1000P/50V_NC DIS_MODE 5VIN +5V_ALW +1.8V_SUS_P PR162 PR177 0_NC PR181 0 PR176 0 OCP Setting (Note1) PC96 4.7U/10V/0805 +5V_ALW2 0_NC B B 18P/50V_NC PC174 0.1U/10V_NC PC176 PR167 100K/F_NC PR166 143K/F_NC (Note 1) Current Limiting Setting : Rtrip(Kohm)=100*(Iocp-0.5*Iripple)*Rds(on) PC75 +1.8V_SUS +1.8V_SUS 10U/4V/0805 Enable Delay 200us +3.3V_SUS PR63 43K/F OUT 9 OUTS 6 IN +1.25V_RUN_P +1.25V_RUN PR59 2 VCC 5 7 PGOOD SHDN 4 REFIN 100K PR60 0 A PC80 PC79 1000P/50V 0.1U/25V/0603 PGND AGND 8 3 REFOUT 1 11 20,26,44,48,53 RUN_ON 10 MAX8794 BP 44 1.25V_RUN_PWRGD PR61 100K/F Max current->0.9A PU4 10 PC77 1U/10V/0603 PC76 10U/4V/0805 PC78 10U/4V/0805 A PC74 PR62 0 0.33U/16V/0603 Title QUANTA COMPUTER 1.8VSUS & 0.9VTT (TPS51116) 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 49 of 62 1 2 3 4 5 +5V_SUS +PWR_SRC FL1 HI1206T161R-10_DIS PR19 10/0603_DIS GFX_+5V_RUN +GPU_PWR_SRC GFX_RUN_ON 20 GFX_RUN_ON A PC3 PC1 10U/25V/1206_DIS 10U/25V/1206_DIS PC18 PC13 2200P/50V_DIS 0.1U/50V/0603_DIS +VCC_GFX_CORE TDC : 13A OCP : 15A Iout_ripple current : 3.9432A PD5 SDM10K45-7-F_DIS PL4 NEC_MPC1040LR88C_0.88uH_DIS +1.1V_RUN_VGA_P ISL88550DL PC155 PR129 2.2/0805_NC 4 + PC149 0.1U/10V_DIS PQ6 FDMS8672S_DIS 14 PC134 1500P/50V_NC PC140 + 10 220U/2.5V/ESR15_DIS 32 33 REFIN 15 VTTI FB EPAD EPAD STBY# EPAD EPAD EPAD VTT 16 7 29 30 31 5 6 7 8 9 VDD GND AVDD OUT PC8 Frequency:300K B GFX_REF PR3 100K 1 POK2 6 13 1 PR9 100K_DIS 2 17 12 +3.3V_SUS VIN PGND2 4 B MAX8632ETI+_DIS UGATE POK1 VTTR PR11 178K/F_DIS ILIM 5 11 Rb ISL88550DH 18 10 140K/F_DIS PR13 ISL88550LX 4 VTTS PC23 0.22U/6.3V_DIS 19 220U/2.5V/ESR15_DIS Ra 20 PHASE 1 2 3 REF 21 BOOT +VCC_GFX_CORE PQ5 FDS6298_DIS 4 5 6 7 8 9 3 LGATE PR22 PC26 1/0603_DIS 0.22U/50V/0603_DIS 1 2 3 OVP/UVP PGND1 TON 2 SS GFX_REF 1 SKIP# TPO PR25 0/0603_NC 9 0/0603_NC 8 PR12 +VCC_GFX_CORE SHDNA# 1 23 PC136 2.2U/10V/0805_DIS 22 25 24 26 28 PU1 PR18 61.9K/F_NC 27 PC33 1U/10V/0603_DIS 2 A 0.047U/10V_DIS 2 +1.8V_SUS PR7 4.99K/F/0603_DIS PC11 10U/6.3V/1206_DIS PC123 PR119 1000P/50V_DIS 24.9K/F/0603_DIS PR26 PR2 49.9K/F/0603_DIS PC14 0.01U/16V_DIS +1.1V_GFX_PCIE 0/0603_DIS PR118 118K/F_DIS PC6 PC7 22U/4V/0805_DIS 22U/4V/0805_DIS PR120 0_DIS PC120 100P/50V_NC PR116 Place near GND pin24 PR117 0/0603_NC 69.8K/F/0603_DIS PR8 100K_DIS GFX_CORE_PWRGD 1U/10V/0603_DIS PC5 GFX_PCIE_PWRGD C C +3.3V_SUS REF 300K 450K PR15 10K_NC 256MB 3 OPEN PR16 10K_DIS PQ1 BSS138_NL_DIS 2 19 GFX_CORE_CNTRL High: 1.1V Low: 0.95V PR123 100K_DIS PC128 0.01U/16V_DIS 1 TON Frequency "for the 128MB sku: No Stuff PR44 for the 256MB sku: Stuff PR44". D D ILIM Iovp=(2*(Rb/(Ra+Rb))*0.1*(1/RDSON)+(I_DELTA/2) SKIP# AVDD = Low-noise, forced-PWM mode. GND = Pulse-skipping operation. The overvoltage limit is 116% of Vout. The undervoltage limit is 70% of Vout. OVP/UVP 1 Title QUANTA COMPUTER VGA DC/DC 2 3 4 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 5 50 of 62 5 4 3 2 1 +PWR_SRC FL2 HI1206T161R-10 +CPU_PWR_SRC +3.3V_SUS 3 PMON 4 RBIAS 147K/F 35 UG1 PHASE1 34 PH1 PGND1 33 LGATE1 32 PVCC 31 LGATE2 30 PGND2 29 5 5 VR_TT# 6 NTC PR21 4.02K/F_NC ISEN1 LG1 +5V_SUS 5 6 7 8 9 2200P/50V 0.1U/50V/0603 10U/25V/1206 10U/25V/1206 10U/25V/1206 10U/25V/1206 330U/2V/ESR9 10K/0603 PR35 1/0603 +CPU_PWR_SRC 10K/0603 NC 25 5 PR136 5 6 7 8 9 5 6 7 8 9 1 2 3 PH2 2 PQ27 NTMFS4119NT1G LG2 5 6 7 8 9 ISEN1 4 PL6 0.36uH_30A_ETQP4LR36WFC 1 PR132 2.2/0805 0.22U/25V/0603 ISL6266_VO 4 + PC67 PC138 1500P/50V +CPU_PWR_SRC PC44 0.22U/25V/0603 PR140 4.53K/F/0603 PC42 5 +VCC_CORE + PC65 PC49 PC45 1 2 3 ISEN2 24 ISEN1 VDD PC37 1500P/50V_NC NTMFS4707NT1G 330U/2V/ESR9 0.01U/50V 5 1/0603 0.1U/50V/0603 PC40 0 23 PR130 1K 10/0603 5 ISEN2 GND 22 21 VSUM VIN 20 19 18 VO DFB DROOP VDIFF PR134 1K 1000P/50V 17 FB2 RTN 12 470P/50V PR128 PC122 2200P/50V 26 FB 4 PQ7 PC121 0.1U/50V/0603 BOOT2 11 4 PC34 0.22U/50V/0603 PC131 10U/25V/1206 UG2 PC132 330U/2V/ESR9 27 PC30 10U/25V/1206_NC UGATE2 PC31 10U/25V/1206_NC COMP 10 NTMFS4707NT1G_NC UG2 PC16 10U/25V/1206 PH2 PC10 2200P/50V 28 C PR23 0.1U/50V/0603 PHASE2 VSEN 5 B + 3 VW VSUM 1K + PR37 4 9 ISL6266_VO PR138 PC139 1500P/50V 2.2/0805_NC OCSET PR135 5 PC47 LG2 8 16 PC141 +VCC_CORE PC48 3.65K/F/0603 PQ8 12.7K/F 15 255/F D 2.2U/10V/0805 1000P/50V 5 PR139 PR30 PR32 ISL6266_VO ISEN2 SOFT 13 PC38 PC21 PC25 ISL6262A 14 ISL6266_VO PR127 PC124 PQ26 NTMFS4119NT1G VSUM 7 0.01U/16V_NC PC39 220P/50V PR31 97.6K/F 1 2 3 PC22 0.22U/50V/0603 PC32 0.015U/16V C 5 PC52 330U/2V/ESR9 BOOT1 PC29 PL5 0.36uH_30A_ETQP4LR36WFC 1 PR133 2.2/0805 36 UGATE1 PC133 4 1 2 3 PR17 31 IMVP6_PROCHOT# PR24 6.81K/F 4 PR10 1/0603 1 2 3 PC127 0.1U/10V 499/F PC36 5 6 7 8 9 1 2 3 37 VID0 38 VID1 39 VID2 40 VID3 41 42 VID4 VID5 44 43 VID6 45 VR_ON DPRSLPVR 46 48 47 LG1 PU2 4.99K/F +3.3V_SUS PC27 MAT ERTJ0EV474J Close to Phase 1 Inductor 2 PQ25 NTMFS4119NT1G PC130 PC35 1500P/50V_NC PH1 5 6 7 8 9 PR125 PR144 NTC_470K_NC DPRSTP# PSI# 4 4 4 4 4 4 4 5 6 7 8 9 CLK_EN# VID6 VID5 VID4 VID3 VID2 VID1 VID0 0 H_PSI# PWR_MON PR126 PGOOD 2 CLK_EN# 49 PR14 3 3V3 GND 13,31,44 IMVP_PWRGD 1 NTMFS4707NT1G_NC IMVP_VR_ON 31 +3.3V_SUS PR124 1.91K/F PQ3 PC28 0.1U/50V/0603 0 DPRSLPVR 6,13 2200P/50V PR6 H_DPRSTP# 3,6,11 3 499/F PC126 4 0 PR5 PR20 PC19 2.2/0805_NC PR4 4 1 2 3 D 4 1 2 3 NTMFS4707NT1G UG1 PC15 0.1U/10V 5 6 7 8 9 PAD PR121 10/0603 0.1U/50V/0603 T1 FL3 HI1206T161R-10 PQ2 PQ28 NTMFS4119NT1G PR36 10/0603 VSUM PR42 3.65K/F/0603 ISEN2 PR43 10K/0603 ISL6266_VO PR45 1/0603 ISEN1 PR44 10K/0603 +5V_SUS B 180P/50V 0.01U/16V PC46 4 +VCCSENSE 4 +VSSSENSE PC146 0.1U/50V/0603 PC41 0.01U/50V PR33 0 0.33U/16V/0603 PC43 PC137 1U/10V/0603 PR137 0/0805 VSUM 0 PR34 Parallel PC142 0.22U/10V/0603 PC145 0.022U/16V PR141 PR142 2.61K/F 11K/F PR146 10K_NTC ISL6266_VO Close to Phase 1 Inductor A A Title QUANTA COMPUTER CPU_Core_2Phase (ISL6266) 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 51 of 62 5 4 3 2 1 DC/DC +3V_ALW/+5V_SUS/+5V_ALW /+15V_ALW PR103 Place these CAPs close to FETs ISL6237_ONLOD 2 390K PR102 150K/F +5V_VCC1 PC189 PC104 4.7U/10V1206 PR108 0_NC PC106 +5V_ALW 2 1 0.1U/50V/0603_NC PC107 PR105 0_NC PR110 0_NC 9 8 7 6 5 PQ37 FDS6680AS_NL PR87 0 4 +5V_DL PC100 0.1U/50V/0603 3 2 1 32 31 30 29 28 27 26 25 PR114 365K/F PC109 5 6 7 8 PAD LDOREFIN LDO VIN NC ONLDO VCC TON REF PR96 1/0603 REFIN2 ILIM2 OUT2 SKIP# PGOOD2 EN2 DH2 LX2 +3.3V_ALWP POK2 +3.3V_EN2 +3.3V_DH SI4812BDY-T1-E3 4 PC115 PR112 0 PQ22 PR113 0_NC PC113 0.1U/50V/0603 C + 330U/6.3V/ESR17 PR107 1/0603 +3.3V_DL SECFB 0.1U/50V/0603 + 330U/6.3V/ESR17 PR88 0_NC PU6 ISL6237 10 PL2 3.3UH +-30% 8A (SIL1045R-3R3) +3.3V_LX 1 2 3 PC190 1 2 3 42 8 7 6 5 4 3 2 1 PC103 1 2 PR99 200K/F +5V_EN1 PAD PAD PAD PAD BYP OUT1 FB1 ILIM1 PGOOD1 EN1 DH1 LX1 PAD PAD BST1 DL1 VDD NC GND PGND DL2 BST2 +5V_LX PQ23 SI4800BDY-T1-E3 4 0_NC 17 18 19 20 21 22 23 24 +5V_ALWP C 41 40 39 38 +5V_ALWP 9 10 11 12 POK1 13 14 15 16 37 36 PAD PAD PAD PL9 3.3UH +-30% 8A (SIL1045R-3R3) 3 2 1 10 +5V_DH 35 34 33 8 7 6 5 PC99 0.1U/50V/0603_NC 4 +3.3V_ALW PC111 PR106 PQ36 FDS8884 Frequency=300KHz 5 6 7 8 PC105 0.1U/50V/0603 Frequency=400KHz PR109 0 D PC192 2200P/50V PR101 0/0603 PR94 10/0603_NC 0.1U/50V/0603 +5V_ALW2 0.1U/10V PC101 1U/10V/0603 10U/25V/1206 PC112 ISL6237_ONLOD PC102 2200P/50V PC188 0.1U/50V/0603 PC110 10U/25V/1206 +5V_ALW TDC : 7.25A OCP : 9.8A Iout_ripple current : 2.84A PC191 10U/25V/1206 +PWR_SRC 10U/25V/1206 D +3.3V_ALW TDC : 6.2A OCP : 8.6A Iout_ripple current : 2.78A Place these CAPs close to FETs No Install for ISL6236 Install 10 ohm for MAX8778 +DC1_PWR_SRC PR178 HI1206T161R-10 0.1U/50V/0603 1 PR179 HI1206T161R-10 +5V_ALW2 PC108 1U/10V/0603 PR111 0 0/0603 PR104 +3.3V_ALWP +3.3V_ALWP PC117 10U/6.3V/0603_NC PD10 1 BAT54S-7-F PC118 2 +15V_ALW 0.1U/50V/0603 B PC114 0.1U/50V/0603 3 PR98 100K POK2 PC116 0.1U/50V/0603 PD11 1 BAT54S-7-F PR115 100K 3V_ALW_PWRGD 44 POK1 B 5V_ALW_PWRGD 44 3 SECFB 2 PC119 0.1U/50V/0603 PR90 +5V_ALW2 PR180 +5V_ALW2 0_NC 39K/F PR89 0 PR92 0 +3.3V_EN2 +5V_EN1 31 5V_ALW_ON 200K/F PR97 A PD9 2 1SS355 1 THERM_STP# 31,39 H_THERMTRIP# 3,6 0 PR91 PR95 A 0_NC Title QUANTA COMPUTER VGA DC/DC 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 52 of 62 4 +3.3V_SUS 0.44A SUS_3.3V_ENABLE 4 PQ16B 2N7002DW-7-F A PC93 4700P PR76 100K_NC 2 2 1 31,49 SUS_ON PQ16A 2N7002DW-7-F 1 5 1 SUS_ON_3.3V# PR77 20K 1 3 0.1U/50V/0603 2 PC92 3 2 PR78 100K 2 PR85 20K PR74 100K_NC 603 603 1 2 PC70 0.033U +1.8V_RUN UMA 4 2 2 3 B PC91 4700P 25 1 1 2 PQ15 2N7002W-7-F PR73 20K Discrete 2 1 PQ10 2N7002W-7-F PR57 20K 0.1U/50V/0603 4 RUN_ENABLE_1.8V PC90 SUS_ENABLE_5V 1 SUS_ON_3.3V# PC72 3 2 PR56 100K 3 2 1 2 9 8 7 6 5 1 B +1.8V_RUN 3.86A(DIS) 0.38A(UMA) PQ11 +1.8V_RUN FDS6298_DU +1.8V_SUS +15V_ALW 3 2 1 0.1U/50V/0603 1 8 7 6 5 PR75 100K +5V_SUS TDC : 1A PQ13 +5V_SUS SI4800BDY-T1-E3 +5V_ALW 2 50 1 50 +15V_ALW RUN_ON# +3.3V_SUS 6 5 2 1 1 1 1 PR72 100K 2 PQ21B 2N7002DW-7-F +3.3V_ALW 2 1 PQ21A 2N7002DW-7-F PC98 4700P +15V_ALW 1 4 2 20,26,44,48,49 RUN_ON +3.3V_ALW 6 4 2 3 5 6 RUN_ON# 5 PQ17 FDC655BN 2 1 1 A RUN_ENABLE +5V_ALW2 +5V_RUN 3.5A +5V_RUN PQ20 SI4800BDY-T1-E3 3 2 PC97 1 8 7 6 5 PR100 100K 2 PR86 100K_NC 2 PR93 100K +5V_ALW +15V_ALW 4 1 +3.3V_ALW 1 +5V_ALW2 3 2 2 0.1U/50V/0603 1 50 PQ11 SI4800BDY-T1-E3 (BAM48000040) FDS6298 (BAM62980005) +3.3V_ALW +3.3V_RUN 603 2 C PC89 4700P +1.8V_SUS +5V_SUS 1 Reserve discharge path 3 2 SUS_ON_3.3V# 2 2 2 Q2 2N7002W-7-F_NC 1 1 Q1 2N7002W-7-F_NC 1 1 +1.25V_RUN Q3 2N7002W-7-F_NC R220 1K_NC 3 2 R218 1K_NC 3 2 R221 1K_NC 3 2 3 1 +0.9V_DDR_VTT 1 1 2 R219 1K_NC R217 10_NC 3 2 +1.5V_RUN R3 1K_NC 3 2 +1.8V_RUN +3.3V_RUN 1 +5V_RUN R216 1K_NC R2 1K_NC 3 2 R1 30/F_NC Reserve discharge path +3.3V_SUS 1 25 3 2 2 2 1 PQ14 2N7002W-7-F 1 PR69 20K 1 PR70 0 2 1 RUN_ON# PC88 1 RUN_ENABLE_3.3V 3 2 PD6 CH751H-40H_NC 1 2 1 PR71 100K C +3.3V_RUN 5.3A 0.1U/50V/0603 1 8 7 6 5 PQ12 FDS8880_NL 3 2 1 4 +15V_ALW D D 2 2 Q24 2N7002W-7-F_NC Q23 2N7002W-7-F_NC 1 2 Q25 2N7002W-7-F_NC 1 1 2 Q22 2N7002W-7-F_NC 1 2 Q26 2N7002W-7-F_NC 1 2 Q21 2N7002W-7-F_NC 1 RUN_ON# Title QUANTA COMPUTER RUN POWER SW 1 2 3 4 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 5 53 of 62 A B 2 PD3 DA204U_NC 3 3 3 3 +3.3V_ALW 1 1 +VCHGR 46 1 C975 1000P 50 20 10 JBAT1 20 20 20 RP1 100X2 PR1 10K SMBUS Address 16 2 1 2 3 4 5 6 7 8 9 BATT1+ BATT2+ SMB_CLK SMB_DAT BATT_PRES# SYSPRES# BATT_VOLT BATT1BATT2- E 50 50 for EMI resquirement, add Reserve on jump on +VCHGR and close to pin1 and 2 of JABT1 Adress : 16H PD4 DA204U_NC 1 PD1 DA204U_NC 2 PD2 DA204U_NC 603 1 0.1U 2 2 1 PC4 D +3.3V_ALW 1 2200P 2 2 1 1 PC2 C 1 3 2 4 1 3 SMBCLK0 31,46 SMBDAT0 31,46 2 4 PBAT_PRES# 31 PBAT_ALARM# RP2 100X2 1775946-2 PD7 DA204U 1 +3.3V_ALW 2 1 +5V_ALW2 PR82 2.2K 2 2 3 PQ19 2N7002W-7-F 20 2 PR81 DB_PSID_R BLM11B102SPT PL1 3 1 1 2 PS_ID 31 100 2 603 +5V_ALW2 +5V_ALW2 PD8 DA204U_NC 2 1 1 PR83 100K/F PR79 10K 3 D31 SSM24PT_NC 2 DB_PSID 40 PR84 PQ18 MMST3904-7-F 3 1 1 1 2 2 1 2 PS_ID_DISABLE# PR80 100_NC 20 2 15K/F 40 3 3 J5 +5V_SUS 12 ICH_USBP212 ICH_USBP2+ ICH_USBP2ICH_USBP2+ 38 BAT1_LED 12 USB_OC2_3# 17 18 19 20 21 22 23 24 25 26 GND GND GND GND GND GND GND GND GND JACK_LED DC DC DC DC DC DC DC DC DC PSID 1 2 3 4 5 6 7 8 9 10 27 28 29 30 31 32 PWR PWR USBUSBUSB+ USB+ GND GND BAT_LED BAT_LED USB_OC USB_EN 11 12 13 14 15 16 +DC_IN_SS DB_PSID ICH_USBP3ICH_USBP3+ +5V_SUS ICH_USBP3- 12 ICH_USBP3+ 12 BAT2_LED 38 USB_R_SIDE_EN# 31 QT110326-3101G-7F 4 4 Title QUANTA COMPUTER DCIN,BATT CONNECTOR 8/15: move the righT side USB and DC-in connector schematic to DB. so change BTB(J14) CONN to 32pin A B C D Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet E 54 of 62 5 4 Reserved for EMI. 1 1 25 +1.05V_VCCP 25 +1.8V_SUS 25 +1.05V_VCCP 25 +3.3V_RUN 603 603 603 603 603 Page 27 PCCARD /CONN Page 31 SIO(MEC5025) GND 1 C534 0.1U_NC D 1 1 C389 0.1U_NC 25 +1.5V_RUN Page 26 SATA (HDD&CD_ROM) 1 PV3 150-265525-C1(H:5.5) GND 1 C433 0.1U_NC PV2 150-265525-C1(H:5.5) 1 1 2 C463 0.1U_NC PV1 150-265525-C1(H:5.5) GND +1.05V_VCCP 2 +1.8V_SUS 2 +1.5V_RUN 2 +1.5V_RUN 2 +PWR_SRC PC87 0.1U_NC 2 26 Stitching caps D 3 Page 38 Azelia CODEC Page 40 LAN(BCM5755M) C C Page 49 1.25V,1.8V,0.9V Page 48 1.5VRUN,1.05V(VTT) Place C860,C216,C1426 close to PQ33. Place C862,C222,C1427 close to PQ73. Page 51 CPU_MAX8786(3phase) Place C867,C254,C1428 close to PQ91. Place C863,C253,C1429 close to PQ92. Page 52 D/D Power B B A A QUANTA COMPUTER Title EMI CAP 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 55 of 62 1 2 3 4 5 6 7 8 30 +3.3V_SUS 32 WWAN, WPAN 7 2.2K A ICH8-M AJ26 ICH_SMBCLK AD19 ICH_SMBDATA 8 2.2K EXPRESS CARD A +3.3V_WLAN WLAN_SMBCLK 30 7002 WLAN_SMBDAT 32 MINICARD-WLAN 7002 +3.3V_ALW +3.3V_WLAN 100 2.2K 110 SMBCLK0 111 SMBDAT0 3 BATTERY 4 2.2K 100 10 CHARGER 9 B B +3.3V_ALW 10K 10K 6 5 +3.3V_RUN 115 SMBCLK1 116 SMBDAT1 7002 LCD 7 6 CLOCK 10 9 THERMAL 7002 +3.3V_RUN SIO ITE8512 C C 2 +3.3V_ALW 2.2K 3 MEDIA BUTTON 2.2K +3.3V_RUN D 117 SMBCLK2 118 SMBDAT2 7002 D 7002 QUANTA COMPUTER 8 +3.3V_RUN 7 M86LP/THERMAL Title SMBUS BLOCK 1 2 3 4 5 6 Size Document Number GM3 Date: Monday, March 24, 2008 7 Rev 2B Sheet of 56 8 62 5 4 3 2 1 POWER STATES S4 ALWAYS STATE# PLANE SLP S3# SLP S4# SLP S5# S0 (Full ON) / M0 HIGH HIGH HIGH 0 Right Top S3 (Suspend to RAM) / M1 LOW HIGH HIGH 1 Right Bottom S4 (Suspend to DISK) / M1 LOW HIGH HIGH 2 Side TOP S5 (SOFT OFF) / M1 LOW HIGH LOW 3 Side Bottom Signal State SUS PLANE RUN PLANE CLOCKS DESTINATION USB PORT# D ICH8-M D S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH 4 Ext. USB TOP S4 (Suspend to DISK) / M-OFF LOW LOW HIGH 5 DIgital Camera S5 (SOFT OFF) / M-OFF LOW LOW LOW 6 Express Card 7 WPAN/Bluetooth 8 Ext. USB Bottom 9 WWAN 1 None 2 None 3 None 4 None PM TABLE C power plane +3.3V_ALW +1.8V_SUS +0.9V_DDR_VTT +3.3V_RTC_LDO +1.8V_LOM +3.3V_WLAN +3.3V_LAN +5V_ALW +15V_ALW +3.3V_RUN_CARD +DC_IN +1.05V_VCCP +2.5V_RUN +DC_IN_SS +1.25V_RUN +5V_MOD +PWR_SRC +3.3V_SUS +1.5V_CARD +5V_RUN +RTC_CELL +5V_SUS +1.5V_RUN +5V_SPK_AMP +3.3V_CARD +CPU_PWR_SRC +3.3V_CARDAUX +VCC_CORE +3.3V_R5C832 +VDDA State ECE 5011 C +3.3V_RUN S0 ON ON ON ON S3 ON ON OFF ON S5 S4/AC ON OFF OFF ON S5 S4/AC don't exist OFF OFF OFF ON PCI EXPRESS B PCI TABLE PCI DEVICE IDSEL REQ#/GNT# PIRQ BCM4401B AD16 REQ#0 / GNT#0 PIRQB R5C833 AD17 REQ#1 / GNT#1 PIRQC: Card reader PIEQD: 1394 A DESTINATION Lane 1 MINI CARD-1 WWAN Lane 2 MINI CARD-2 WLAN Lane 3 MINI CARD-3 WPAN Lane 4 Express Card Lane 5 None Lane 6 None B A Title QUANTA COMPUTER Schematic Block Diagram1 5 4 3 2 Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 57 of 62 5 4 3 2 1 GM3 Power Design Block Diagram 2007/09/06 +5V_SUS SI4835 D +DC_IN +3.3V_SUS Q3 FDS4835 D +DC_IN_SS IMVP_VR_ON Power Jack IMVP_PWRGD CPU POWER ISL6266 Adapter input +VCC_CORE TWO PHASE SOLUTION Charger Pag 51 +5V_VCC1 MAX8731A 5V_ALW_ON +5V_ALW Pag 46 SYSTEM POWER +3.3V_ALW ISL6237 +VCHGR +5V_ALW2 +5V_ALW2(for +3.3V_ALW) +15V_ALW 3V_ALW_PWRGD C C Pag 52 5V_ALW_PWRGD SI4835 +PWR_SRC +5V_ALW Primary Battery SUS_ON DDR POWER +1.8V_SUS TPS51116 1.8VSUS_PWRGD Pag 49 RUN_ON +1.8V_SUS FDS6298 Pag 53 +0.9V_DDR_VTT TPS51116/LDO +1.8V_RUN RUN_ON RUN_ON +1.8V_SUS +5V_ALW SI4800BDY Pag 53 B +5V_RUN B +5V_ALW FDS8880_NL Pag 53 RUN_ON +3.3V_RUN 1.05V_RUN_PWRGD N&S BRIDGE POWER +1.05V_VCCP TPS51117 Pag 48 RUN_ON +1.8V_SUS FDC655BN +3.3V_ALW +1.25V_RUN RUN_ON RUN_ON +3.3V_ALW MAX8794 RUN POWER PLANE SWITCH +3.3V_SUS L6935TR +1.5V_RUN +5V_SUS Pag 53 RUN_ON SUS_ON GFX_RUN_ON SUS POWER A GFX_CORE_PWRGD N&S BRIDGE POWER SI4800BDY +5V_ALW MAX8632ETI+ +5V_SUS Pag 50 Pag 53 GFX_PCIE_PWRGD MAX8632/LDO SUS_ON 5 A +VCC_GFX_CORE 3 2 QUANTA COMPUTER Power Block Diagram +1.1V_GFX_PCIE 4 Title Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet 1 58 of 62 6 Model Item 5 Page Date 4 3 Rev. 2 1 Description Base on David.Lin 070725 1400 release preliminary schematic to check the all part PCB footprint. I found there are some parts not had footprint and update it. The change location as below. Pacino of Intel 1 All 7/25 1A There are some concern need to highlight: 1. D1changed to CH751H-40PT. 2. L84 & L85 need to changed to Dell PSL part. 3. LAN jack need to double check. 4. JKB1, JMOD1, JP1, L15 need to get the spec for create new layout footprint and apply for new P/N. 5. JDIM1 & JDIM2 should be conbined to one JDIM. U12, L27, L28, C225, C226, D4, L9, U3, JDIM2, D1, L84, L85, U14, U18, U22, U23, U25, BT2, CON2, CON3, L34, L35, Q10, U11, U13,ESD1, CON7, D15, D38, D39, D40, JACMER1, JKB1, JMOD1, JP1, L15, M1, Q7, Q67, SW1, U20, U41, FL1, FL3, FL4, FL7, FL8, FL9, FL10, FL11, JDCIN1, PC125, PC139, PC151, PC153, PC161, PL3, PL4, PL10, PL11, PL12, PQ13, PQ24, PQ42, PQ43, PQ44, PQ45, PR84, PU1, PU4, PU9. F 2 39 8/13 1A FAE review schematic and recommend add C8466 & C8356 between REM_DIODE1_P and REM_DIODE1_N. This is just a reservation in case there's any noise coupling issue happening. Then have 2 different filter cap locations (one near EMC1423 and the oyher near the OTP 3904 diode) to try to reduce the noise. Of cource, only one cap can be installed. 3 25 8/13 1A FAE review schematic and recommend add poly switch and 0.1u cap colse to 5V_RUN of HDMI CONN to avoid NB reboot. 4 29 8/15 1A FAE review schematic, NC FILO pin since 5C833 don't need cap to GND 5 19 8/15 1A The strap on VIP[3] 6 54 8/15 1A move the right side USB and DC-in connector schematic to DB. so change BTB(J2) CONN to 32pin 1A 8/15 FAE review schematic: reverse TMDS signal for working property. change voltage allocation resistor to make sure the input clock swing level is at 1.8V F is for enabling HD Audio on M86. so pull to hign. 7 19 8/15 8 39 8/16 9 37-39 8/17 10 52 8/20 1A 11 52 8/20 1A Since FDS8878 Rg too big,change PQ44 to FDS8884. 12 52 8/20 1A Change PR225 to 180K and PR224 to 294K for setting current limit. 13 52 8/20 1A For FAE recommend , 14 49 8/20 1A Change PR85 to 143K for 1.82 output voltage 15 48 8/20 1A Due to output ripple current too big ,cheange PL25 from 0.88uH to 1.5uH. 16 48 8/20 1A PR449 should be cancelled, not necessary 17 48 8/20 1A Change PR452 to 9.09k for OCP 18 48 8/20 1A For FAE recommend. 19 48 8/20 1A Add PC78 for meet output ripple current. 20 48 8/20 1A Change PR102 to 4.53K and PR105 to 49.9k for setting VTT=1.1V. (VTTS =REFIN/2=1V) 21 38 8/22 1A Added LED level shift for support white LED need used 5V drive. 22 22 8/23 1A add level shift circuit to protect thermal IC 23 42 8/23 1A add level shift circuit to provent ALW and LAN plan interconnect 24 13 31 37 40 48 55 8/24 1A Check single net and correct by JM 25 52 8/27 1A Due to SIL1045R-3R8PF will be EOL, change PL11,PL12 to SIL1045R-3R3. 26 37 8/27 1A change KB pin number to 32 pin 27 43 8/28 1A change LED of LAN jack control 28 43 8/28 1A Co-layout SIM card connector and WTB together 29 37 8/28 1A Dell had update K/B pin define to 34 pin and re-define pin definition 30 31 8/28 1A KSO18 is output pin, so change to pin 85, and KB_DET# from pin 85 change to pin 70. 31 39 8/28 1A reverse 1~4 pin definitiom for thermal team design 32 28, 12 8/29 1A change R5c833 PCI_PIRQD# to PCI_PIRQB# for AMD platform signal control requirement 33 37 8/29 1A due to move keyboard light sensor to media button board, add KB_BACKLITE_SET function to media button connector pin 10. 34 37 8/29 1A change keyboard pin number to 32 pin 35 48 8/29 1A For Dell recommend,change 1.5V LDO from MAX8794 to ST L6935. 36 49 8/29 1A For TI FAE recommend,connect PC76 to GND. 37 35 8/30 1A For support power USB function, change power to 5V_ALW 1A 8/16:per SPEC recommend: use 7002 to avoid the leakage current from 3V_SUS. 1A 8/17:add diode to protect below GPIO port,p39---FAN1_PWM p38---SNIFFER1 and POWER_ SW_IN0#, p37---MEDIA_INT 8/20: For FAE suggestion. Charge pump from +5V LDO, might cause high ripple voltage. Add PC116 10U/6.3V/0603. E D 38 39 40 41 31 25,43,38 52 52 53 E PD16 could be deleted. PC447 no stuff, reserved. signal to LINKLED D 8/30 1A change IMVP6_PROCHOT# from pin 88 to GPI 1 for design requirement. and pin88 assign to 5V_ALW_ON 8/30 1A for EMC team requirement, reserve cap, ESD protect, common choke at CON side 8/30 1A Add PC180 for reserve 8/30 1A Due to Pacino need to support USB charger function,change following item. 1.Change power plan from +5V_ALW to +5V_ALW2:pin9 ,pin7,pin19, PC116 and PR156 2.Add a load switch PQ42 for +5V_ALW to +5V_SUS MAX8778 IC. 42 28 8/31 1A refer M08 platform, change to 100 ohm 43 22 9/2 1A Reserve external spread spectrum circuit for ATI graphic using 44 48 9/3 1A change PR455 to 237K from 178K to setting switching operating frequency at around 300 KHz 45 52 9/3 1A For FAE recommend, change PD14 input power from "+5V_ALW2" to "+5V_ALW" and PC116 can be NA. 46 52 9/3 1A For FAE recommend, conncet pin20 to pin19 ISL6237 location. 47 49 9/3 1A Change PC155 to correct net name "+1.8V_SUS_P". 48 20 9/3 1A M86 internal thernal protect function pin is high active, re-design protect logic circuit for it. 49 54 9/3 1A for EMI resquirement, add Reserve on jump on +VCHGR and close to pin1 and 2 of JABT1 50 38 9/3 1A 51 46 9/3 1A Add PC39 for reserve debug noise issue. 52 48 9/3 C B C for ISL6236 (or MAX8778) can populate on Reserve ESD protector at J4 pin1 (+3V_RUN )for Biometric (close to J4 ) 1A Change PU5 pin6 through PR58 to +3.3V_SUS. 53 49 9/3 1A Change PR79 from 10K to 0ohm. 54 50 9/3 1A For reserve EMI sunnber, add PR157 and PC117. 55 48 9/3 1A For DELL recommend , reserve 56 38 9/3 1A For DELL recommend , Add GPIO pin to mask HDD and BT LED active 57 17, 33, 34 9/3 1A for WLAN card using CLK-REQ pin, so change and CLK_PCIE_MINI3 to WPAN. 58 26, 6 9/3 1A add third pair LVDS signal to support 24bit panel 59 31 9/4 1A delete JACK_LED_DET# pin for DC jack design, so move KSO18 to pin99. 60 46 9/5 1A Reserve a 0 ohm PR59 resister for EA test. 61 48 9/5 1A Add PC145 for ST FAE recommend. 62 37 9/6 1A Add KB_BACKLITE_EN control circuit on MB side 63 37 9/6 1A Add 3_ALW at pin 5 for Lid switch IC power pin 64 42 9/6 1A Reserved BCM5784M SUPER_IDDQ circuit. 65 30 9/8 1A add MMC card function at card reader connector PC143 and PC144 for TI controller. B CLK_PCIE_MINI1 to WLAN A A QUANTA COMPUTER Title X00 change list Size Date: 6 5 4 3 Document Number GM3 Monday, March 24, 2008 2 Rev 2B Sheet 59 1 of 62 6 Model Pacino of Intel 5 Item Page Date Rev. 1 12,13, 17,25, 09 9/27 2A 2 52 ,50 10/2 2A 3 8 10/3 2A 4 19 10/3 2A 5 41 6 40 F 7 46 10/15 10/15 52 2A 4 3 2 1 Description modify SST design issue: 1. delete unnecessary 0 ohm resistor 2. select correct frequence for DIS/UMA(R351&R342) 3. CARD_CLK_REQ# pull high 4. PLTRST_DELAY# pull down to avoid floating. 5. NC R451 to set Boot BIOS Strap for LPC interface For second source concern, change below item. 1. Change PD9 from BAS316 to 1SS355 2. Change PD5 from CH501H-40PT to SDM10K45-7-F 3. Change PQ1 from BSS138-7-F to BSS138_NL F use 0805 0 ohm to instead of jump(1/8W, 1.6A per resistor ) pull high the GPIO 0 & GPIO 1 to enable PCIE FULL TX OUTPUT SWING and PCIE TRANSMITTER DE-EMPHASIS function to solve no display problem. The camera pin assignment changed : 2 pin camera power pin and they are 3.3 V .. 2A change resister setting for STA92HD73C chip 10/15 2A Due to SI4810BDY-T1-E3 will be EOL, change PQ29 and PQ22 from SI4810 to SI4812. 8 19 10/16 2A Due to VDDR4 and VDDR5(option reference source voltage) use FAE suggust DVPDATA use 1.8V pull high 9 33 10/17 2A 1.8V_RUN, remove external SIM card CONN that on MB side 10 13 10/17 2A It is multi_function pin(SMBALERT#/GPIO11). Before bios programming, the PIN function is SMBALERT.If it is pull high to 3.3_RUN, the ICH8 will be alert by this pin. It cause the S3 can’t normally sleep when system cold boot first time. so change to SUS power 11 38 10/18 2A Sniffer behavior is reverse, so modify design at PT stage 12 42 10/18 2A change to 5784 design 13 40 10/22 2A change TPA6040A4 symbol design to meet SPEC definition 14 19 10/22 2A FAE suggust: Ground R2B/G2B/B2B and Implement R2SET to GND even if DAC2 is unused. 15 43 10/23 2A for factory requirement---increase pad length for SMT yield rate 16 E E 41 10/24 2A for DELL SPEC---change camera conn pin definition 17 31, 37 10/25 2A modify LED Key board Illumination schematic and remove EC pin 68 reserve 18 44 10/29 2A HWPG monitor change: change 3V/5V_ALW_PWRGD to GFX_PCIE/CORE_PWRGD reserve 19 12,13, 14,31 10/29 2A create +3.3V_S5 and +5V_S5 power at ICH part to fix ITE chip SUS resume problem, and move LID_SW# to pinj 68 and pin 120 for S5_ON using add FSUSB31K8X to control USB signal can be passed above SUS, and USB_SIN_SIDE_EN# can control whether USB can supply power for external device at S5 mode reserve 20 35 10/30 2A 21 53 10/30 2A 22 48 10/30 2A 23 38,54 10/30 2A add 1000p cap and close to connector for EMI C 1.5V_RUN_PWRGD pull-high to RUN_ON for solve glitch issue. 24 35 10/30 2A change LCD connector pin definition for LED panel: 1. change pin 8 form GND to +5V_ALW 2. change pin 16 from GND to LCD_VCC 25 31 11/1 2A change GPIO design 1. delete pin 83 SNIFFER_YELLOW# 2. move 5V_ALW_ON to pin 83 3. swap pin 108 WIRELESS_ON/OFF# and pin 35 SNIFFER_PWR_SW# 26 38 11/1 2A change GPIO design 1. swap WIRELESS_ON/OFF# and SNIFFER_PWR_SW# 2. remove SNIFcircuitFER_YELLOW# 27 31 11/5 2A 28 3 11/5 2A Modify H_THERMTRIP# Voltage Level shift circuit. 29 41 11/6 2A add one GND pin for Audio precision dB value 30 37 11/8 2A add circuit to control CIR power 31 49 11/12 2A Add PR181 for reserve +5V_ALW2. 32 43 11/12 2A for EMI requirement, add 7p cap close to LAN switch 33 37 11/13 2A for DELL requirement, add fuse between +5V_RUN and +KB_LED 34 31 11/13 2A use pin 14(WRST#) to monitor THERM_STP# function 35 25 11/13 2A for Silicon image FAE suggestion: 1. EMI may come from the impedance mis-match, that'll get distorted waveform . Try to replace the common choke with (i.e 22 ohm ) resistor, 2. Try to reduce the source termination resistor (i.e 300 ohm --> 150 ohm) to get cleaner eye . 3. change AVCC33V to 3.3V_RUN 36 25 11/13 37 50 11/13 2A Chnage PR11 to 100Kohm for set correct O.C.P. D reserve For EE request , add two power rail "+3.3V_S5" and "+5V_S5" for south-bridge battery mode. 2A D change GPIO design for fix thermail no function issue 1. NC ADAPT_OC and ADAPT_TRIP_SEL 2. add #V_ALW_ON function at pin 76 C per FAE suggestion:change C525 and C524 to 2.2u for batter Audio precision 38 50 11/13 2A For EE request, set VGA voltage to 0.95V/1.1V. Change PR116 to 69.8K and PR118 to 118K. 39 4 11/13 2A Base on acoustic team test ,add two EC-cap for noice issue. Stuff C733 and C766. 40 52 11/13 2A Base on test result, change PR114 to 294K for set OCP. 41 48 11/13 2A Change PR161 to 11K for set correct OCP. 42 48 11/13 2A For 1.05V jitter issue, chnage below item. UMA: Change output CAP from 390U/2.5V/ESR10 to 330U/4V/ESR25 43 48 11/13 2A Change 1.05V UMA PQ33 from FDS6676AS to FDMS8672S for improve efficiency. 44 49 11/13 2A Base on EA report test , stuff PR171 and PC180 for reduce hiogh side VDS ring. 45 46 11/13 2A Due to software support UL function via "IINP", no stuff UL circuit. 46 13 11/14 2A add 4.7k on PCIE_MCARD1_DET# trace to solve WLAN card detect issue 47 19 11/15 2A change GPIO pin from 3.3V_RUN to 3.3V_delay to solve leakage problem between 3.3V_RUN and 3.3v_delay(4ms) when boot. Discrete: 1. Change output CAP from 390U/2.5V/ESR10 to 330U/4V/ESR25 2. Add PC62 1500PF B B QUANTA COMPUTER Title X01 change list Size Document Number GM3 Date: Monday, March 24, 2008 Rev 2B Sheet of 60 A 62 A 6 5 4 3 2 1 6 Model Pacino of Intel F E D 5 4 2 1 Item Page Date 1 32 11/26 2B Change RTC connector because ME modifyr. 2 31 11/26 2B Exchange 'SNIFFER_PWR_SW#' AND 'WIRELESS_ON/OFF#. per EC limition. 3 31 11/26 2B Change NUM_LED# from SIO pin98 to pin 88 and used Pin 98 for BID only per EC limition. 4 54 11/26 2B Change PSID relation parts to +5V_ALW2 for power saving in S5. 5 38 11/26 2B Change Sniffer Switch power rail from RUN plane to ALW plane. 6 43 11/26 2B Added 7 45 11/27 2B Modify Screw hole base on ME update. 8 17 11/29 2B Link to MCH DPLL clock is wrong. Change to correct link. 9 31 11/30 2B Fine tune GPIO define for EC. 10 37 12/04 2B Change MMB LED power source from 5V_ALW2 plane to 5V_ALW for power saving and avoid LED flash when AC in. 11 22 12/04 2B Check AMD +3.3V_DELAY power plane connection component for AMD new update REF133-7 file. 12 40 12/19 2B Change Audio AMP thermal PAD leave to NC. 13 31 12/26 2B Change SMBus pull hihg resistor form 2.2k to 10k for LED panel flash. 14 37 12/26 2B since we will use WLAN and BT LED to show function at factory side. Change power supply of Cap and Num LED from 5V_ALW2, 3.3V_ALW to 5V_RUN and 3.3V_RUN. 15 19 12/26 2B Change HDMI detect circuit to solve external panel feed back voltage shortage then caude ATI chip can't switch to HMDI mode problem. 16 37 12/26 2B Change the Media board power from 3V_ALW to 5V_ALW2 to solve LED flash issue when AC/Bat plug in. 17 37 12/26 2B 18 48 1/3 2B Change PC85 to 680P for meet sequence. 19 50 1/3 2B Change PR7 to 4.99K for adjust +1.1V_GFX_PCIE rail. 20 53 1/3 2B Change PQ11 from SO8 to power package footprint. 1/3 2B Change PR161 ,PR172 ,PR11 ,PR114 to correct resistance for reliability request. 21 48 49 Rev. 3 Description F LINK1000# for BCM cann't support GLAN LED drived by LINKLED#/SPD100LED#. E D Change the lid switch IC power source from 3.3V_SUS to 3.3V_ALW to avoid system can enter S4 mode but wake up fail problem C C 50 52 22 35 1/4 2B remove USB charge circuit 23 26 1/7 2B pull DPST signal to high for setting 100% duty cycle 24 31 1/7 2B pin12 should reserve 1u cap for ITE8512JX using 25 19 1/7 2B modify HDMI detect circuit to fix the monitor detection problem.. 26 55 1/7 2B create EMI spring 27 31 1/11 2B per TXC report, we should change W1 cap to 18p 28 41 1/11 2B per IDT FAE suggestion, serial 22 ohm on DMIC_CLK can help DMIC performance 29 37 1/11 2B add 10u cap at JMB1, let 3.3V_ALE get lower drop voltage on MMB side. 30 6, 19 1/11 2B EMI demand add 33p cap on RGB signal. B B QUANTA COMPUTER A Title A X02 change list 6 5 4 3 Size Document Number GM3 Date: Monday, March 24, 2008 2 Rev 2B Sheet 61 1 of 62 6 Model Pacino of Intel Item 5 Page Date 4 Rev. 3 2 1 Description 1 25 2/14 3A add level shift to separate the data and CLK of VGA IC and HDMI TV, and also reduce stray capacitance. 2 25 2/14 3A change diode to reduce stray capacitance per WPI suggestion 12,28,31 2/14 3A use pin-22 monitor ICH_AZ_CODEC_RST# to delay NB_MUTE# signal for solve PO noise issue F F 3 4 50 2/20 3A For Reliability calculate , change PR11 from 150K to 178K. 5 51 2/20 3A Due to C4E hung up issue, change v_core power IC from ISL6266A to ISL6262A. Below is change list. 1. PU2: Change PN from AL006266000 to AL006262025 2. PR24: Change PN from CS28252FB15 to CS26812FB13 3. PC39: Change PN from CH11006JB18 to CH12206KB14 4. PC38: Change PN from CH12704JB07 to CH14706KB18 5. PR139: Change PN from CS11002JB32 to CS12552FB18 6. PC141: Change PN from CH22206KB16 to CH21006JB10 7. PC40,PC41: Change PN from CH1336K1B02 to CH31006KB18 8. PR136: Change PN from CS23833F911 to CS24533F921 E D C E 6 48 2/20 3A For 1.05V OVP issue in Vista , no stuff PC62. 7 25 2/20 3A 8 48 2/15 3A Due to L6935 has improved powergood issue, no stuff PR183 and stuff PR66. add HDMI solution per Silicon image suggestion 1. Change R233 to 650 ohm 2. Remove external RC between HDMI +/- signal. add HDMI EMI solution DIS:CXCG900U000 / EXC24CG900U; UMACXCG240U000 / EXC24CG240U 9 35 2/23 3A add common chock for EMI solution Quanta PN: DC09004A014 10 35 2/25 3A cange power jump to 0805 resistor 11 27 2/25 3A add filter CAP for EMI 12 13, 37 2/25 3A by ICH-8 GPIO-17 dectect the LED keyboard connector 13 17 2/26 3A exchange 27SS and 27NSS / DREF_SSCLK# & DREF_SSCLK for follow CLK GEN spec. design. 14 13 2/27 3A ICH_RSMRST# pull down for RTC timer issue when plug in AC 15 40, 41 2/27 3A MUST ADD 2.2K-OHM RESISTORS TO PREVENT AMPLIFIER CLIPPING and ADD 220PF CAPACITORS TO ALLOW PROPER DYNAMIC RANGE MEASUREMENTS 16 19 22/29 3A Add 10k ohm on HDMI_DET to ensure Vin on test fixture input 2.4V the voltage not drop under 2V spec. definition. 17 9 03/03 3A Based on SR_check 1.6, UMA should pull down 75 ohm on TV_DAC pins if disable TV-out function. 18 40 03/05 3A Change C518, C519 from 0.033uF to 0.01uF per Dell audio update requirement. 19 40 03/20 3A Change net name of "AUD_HP2_L1" between R708 & C525 to "AUD_HP2_L0_R" and "AUD_HP2_R1" between R708 & C525 to "AUD_HP2_R0_R" for the original net name same as U20.15 & U20.16 will cause the HP2 no function. B D C B A A QUANTA COMPUTER Title A00 change list Size Date: 6 5 4 3 Document Number GM3 Monday, March 24, 2008 2 Rev 2B Sheet 62 1 of 62 www.s-manuals.com
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