Quanta TWH Schematics. Www.s Manuals.com. Ra 20101115 Schematics
User Manual: Motherboard Quanta TWH DATWHMB18D0 - Schematics. Free.
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^LJƐƚĞŵWŽǁĞƌ;нϯsWhͬнϱsWhͬ нϯs^ϱͬнϱs^ϱͿ h^Ϯ͘ϬWŽƌƚdžϯ ĂŵĞƌĂ ůƵĞƚŽŽƚŚ ;ŽͲ>ĂLJŽƵƚtŝƚŚ h^ϯ͘ϬdžϮͿ WŽǁĞƌ͗ WŽǁĞƌ͗ WĂĐŬĂŐĞ͗ WĂĐŬĂŐĞ͗ W/ 'ĞŶϭdžϭ>ĂŶĞ ZĞĂůƚĞŬZd^ϱϭϯϴ EWϲϭϯϭͬEWϱϵϭϭͬZdϴϮϬϵͬ'ϵϯϯϰ ĂƌĚZĞĂĚĞƌ WƌŽĐĞƐƐŽƌWŽǁĞƌ;нsͺKZ ͬ нϭ͘Ϭϱͺsddͬнs^Ϳ <ĞLJďŽĂƌĚΘ dŽƵĐŚWĂĚ W' Ϯϵ /dϴϭϱϴ ZĞĂůƚĞŬ>Ϯϲϵ s/s>ϴϬϭ ƚŚĞƌŽƐZϴϭϱϭ /ŶƚĞůZĂŵďŽWĞĂŬ ŵďĞĚĚĞĚŽŶƚƌŽůůĞƌ ƵĚŝŽŽĚĞĐ h^ϯ͘ϬŽŶƚƌŽůůĞƌ >EŽŶƚƌŽůůĞƌ ,ĂůƚDŝŶŝĂƌĚ WŽǁĞƌ͗ WŽǁĞƌ͗ WŽǁĞƌ͗ WŽǁĞƌ͗ t>EͬdŽŵďŽ WĂĐŬĂŐĞ͗>YW&ϭϮϴ WĂĐŬĂŐĞ͗>YW&ϰϴ WĂĐŬĂŐĞ͗Y&Eϴϴ WĂĐŬĂŐĞ͗K&Eϰϴ WŽǁĞƌ͗ ^ŝnjĞ͗ϭϰdžϭϰ;ŵŵͿ W' ϯϮ ^ŝnjĞ͗ϳdžϳ;ŵŵͿ W' Ϯϱ ^ŝnjĞ͗ϵ͘ϭϱdžϵ͘ϭϱ;ŵŵͿ W' Ϯϰ ^ŝnjĞ͗ϲdžϲ;ŵŵͿ W' Ϯϳ WĂĐŬĂŐĞ͗ DŽƌĚĞŶŽŶŶ ;KƉƚŝŽŶͿ W' Ϯϲ h^ϯ͘ϬWŽƌƚdžϯ ;ŽͲ>ĂLJŽƵƚtŝƚŚ h^Ϯ͘ϬͿ W' Ϯϰ &EŽŶƚƌŽůůĞƌ W' Ϯϱ A B WŽǁĞƌ͗ WĂĐŬĂŐĞ͗>YW&ϰϴ ^LJƐƚĞŵ/K^ ^W/ZKD W' Ϯϱ >z Zϭ͗dKW >z ZϮ͗^'E >z Zϯ͗/Eϭ;,ŝŐŚͿ >z Zϰ͗/EϮ;>ŽǁͿ >z Zϱ͗^'Eϭ >z Zϲ͗^s >z Zϳ͗^'EϮ >z Zϴ͗Kd ZŝĐŚƚĞŬZdϴϮϬϳ ^LJƐƚĞŵDĞŵŽƌLJWŽǁĞƌ;нϭ͘ϱs^h^ͬ нϬ͘ϳϱsͺZͺsddͿ ^ŝnjĞ͗ϳdžϳ;ŵŵͿ W' Ϯϴ ZŝĐŚƚĞŬZdϴϮϬϵͬZdϵϬϮϱ W,WŽǁĞƌ;нϭ͘Ϭϱͬнϭ͘ϴsͿ ^ŝnjĞ͗ W' ϯϭ KϮDŝĐƌŽKϴϭϮϮ ϮϱD,nj 'WhWŽǁĞƌ;нs'KZ ͬнϯ͘ϯsͺ'&yͬ нϭ͘ϴͺs'ͬнϭ͘ϱͺ'&yͬнϭ͘Ϭϱͺ'&yͿ A WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ Eϱ 5 4 3 2 Size A3 Document Number Rev A ůŽĐŬŝĂŐƌĂŵ Date: Monday, November 15, 2010 1 Sheet 1 of 40 5 4 3 2 Sandy Bridge Processor (DMI,PEG,FDI) G21 E22 F21 D21 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] [6] [6] [6] [6] DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 G22 D22 F20 C21 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] [6] [6] [6] [6] [6] [6] [6] [6] FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 A21 H19 E19 F18 B21 C20 D18 E17 FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] [6] [6] [6] [6] [6] [6] [6] [6] FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 A22 G19 E20 G18 B20 C19 D19 F17 FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] [6] [6] FDI_FSYNC0 FDI_FSYNC1 J18 J17 [6] FDI_INT H20 FDI_INT [6] [6] FDI_LSYNC0 FDI_LSYNC1 J19 H17 FDI0_LSYNC FDI1_LSYNC eDP_COMP INT_eDP_HPD_Q B FDI0_FSYNC FDI1_FSYNC A18 A17 B16 eDP_COMPIO eDP_ICOMPO eDP_HPD C15 D15 eDP_AUX eDP_AUX# C17 F16 C16 G15 eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] C18 E16 D16 F15 eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32 PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 C26 SNB_IVB# AN34 SKTOCC# H_SNB_IVB# SNB_IVB# N.A at SNB EDS #27637 0.7v1 SKTOCC# TP22 TP_CATERR# AL33 CATERR# H_PECI AN33 PECI 56.2/F_4 H_PROCHOT#_R AL32 PROCHOT# AN32 THERMTRIP# TP23 BCLK BCLK# A28 A27 DPLL_REF_SSCLK DPLL_REF_SSCLK# A16 A15 CLK_DPLL_SSCLKP_R CLK_DPLL_SSCLKN_R R8 CPU_DRAMRST# AK1 A5 A4 SM_RCOMP_0 R134 SM_RCOMP_1 R396 SM_RCOMP_2 R395 [29] PEG_RX[0..15] [14] R276 EC_PECI 43_4 R167 [29,39] H_PROCHOT# C1016 9/9 add for PDG update 43P/50V_4 R462 [9,29] PM_THRMTRIP# SM_DRAMRST# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] 11/12 short [6] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 C_PEG_TX#0 C_PEG_TX#1 C_PEG_TX#2 C_PEG_TX#3 C_PEG_TX#4 C_PEG_TX#5 C_PEG_TX#6 C_PEG_TX#7 C_PEG_TX#8 C_PEG_TX#9 C_PEG_TX#10 C_PEG_TX#11 C_PEG_TX#12 C_PEG_TX#13 C_PEG_TX#14 C_PEG_TX#15 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25 C_PEG_TX0 C_PEG_TX1 C_PEG_TX2 C_PEG_TX3 C_PEG_TX4 C_PEG_TX5 C_PEG_TX6 C_PEG_TX7 C_PEG_TX8 C_PEG_TX9 C_PEG_TX10 C_PEG_TX11 C_PEG_TX12 C_PEG_TX13 C_PEG_TX14 C_PEG_TX15 [9] *0_4/S PM_SYNC_R short0402 *0.1U/10V_4 R454 PM_SYNC C1001 8/31 reserved for "boot hang 47" issue R457 H_PWRGOOD [8,14,24,26,27,29] +1.05V_VTT U18 PLTRST# 3 GND OUT 2 IN 1 8/26 A-->B modify CPU_PLTRST# 4 +3VS5 NC VCC UNCOREPW RGOOD PM_DRAM_PWRGD_R V8 R470 *75_4 R460 *43_4 CPU_PLTRST#_R AR33 SM_DRAMPW ROK RESET# 8/26 A-->B modify R459 5 *74LVC1G07GW R463 C502 AP33 10K_4 3/26 DB del for DG update. CPU RESET# PM_SYNC H_PWRGOOD_R 0_4 R456 AM34 PRDY# PREQ# AP29 AP27 XDP_PRDY# XDP_PREQ# TCK TMS TRST# AR26 AR27 AP30 XDP_TCLK XDP_TMS XDP_TRST# TDI TDO AR28 AP26 XDP_TDI_R XDP_TDO DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] 8/26 A-->B modify R491 *10K_4 1 U19 NC VCC PM_DRAM_PWRGD_PU 2 IN R495 *0_4 A R68 R72 *1K_4 *1K_4 FDI_FSYNC can gang all these 4 signals together and tie them with only one 1K resistor to GND (DG V0.5 Ch2.2.9). TP30 TP31 TP67 TP69 TP25 TP66 TP70 TP65 R41 1K_4 R42 [12,13] DDR3_DRAMRST# R43 1K_4 3 GND OUT PM_DRAM_PWRGD_C R125 R123 *0_4 130/F_4 PM_DRAM_PWRGD_R R39 [8] DRAMRST_CNTRL_PCH Q9 2N7002 *0_4/S short0402 11/12 short CPU_DRAMRST# 1 CPU_DRAMRST#_R R488 200/F_4 4 C37 0.047U/10V_4 B R40 4.99K/F_4 8/26 A-->B modify 39_4 2 PM_DRAM_PWRGD_C 0_4 1 R120 *3K/F_4 MAIN_ONG [4,36] Q17 2N7002 [6,7,8,9,10,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39] +3V [6,7,8,9,10,14,24,29,31,33,35,36,38] +3VS5 [4,10,27] +1.5V_CPU [4,29,33,34,38,39] +1.05V_VTT 11/8 add 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15 0.22uF AC coupling Caps for PCIE GEN1/2/3 5 XDP_DBRST# [6] +1.5VSUS *74LVC1G07GW 8/31 change to 0 ohm Embedded Display PLL Clock [14] PEG_TX[0..15] FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1 +3V PM_DRAM_PWRGD [6] R127 PEG x16 disable (UMA only remove) FDI_INT AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7 C *1K_4 DDR3 DRAM RESET C522 *0.1U/10V_4 5 [14] PEG_TX#[0..15] 3/26 DB change Part reference. Ra RP11 *0_4 *0_4 *0_4 XDP_DBRST# Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) 8/26 A-->B modify R71 R69 R70 TP27 TP74 +3VS5 3 eDP_COMP connect to PIN A18 W:4mils/S:15mils/L: 500mils. eDP_COMP connect to PIN A17 W:12mils/S:15mils/L: 500mils. C504 C500 C499 C497 C493 C495 C488 C489 C483 C486 C478 C480 C479 C474 C465 C466 AL35 CPU XDP TP68 TP73 TP71 R453 +1.5V_CPU 3/26 DB del for DG update. TP72 TP28 750/F_4 *0.1U/10V_4 1.5K/F_4 +3VS5 SM_DRAMPWROK Processor Input. 140/F_4 26.1/F_4 200/F_4 SM_RCOMP[0] W:20mils/S:20mils/L: 500mils, SM_RCOMP[1] W:20mils/S:20mils/L: 500mils, SM_RCOMP[2] W:15mils/S:20mils/L: 500mils, PM_THRMTRIP#_R 0_4 10/11 change C_PEG_TX0 C_PEG_TX1 C_PEG_TX2 C_PEG_TX3 C_PEG_TX4 C_PEG_TX5 C_PEG_TX6 C_PEG_TX7 C_PEG_TX8 C_PEG_TX9 C_PEG_TX10 C_PEG_TX11 C_PEG_TX12 C_PEG_TX13 C_PEG_TX14 C_PEG_TX15 D Placement close to EC. Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) FDI disable (DIS only stuff) CLK_CPU_BCLKP [8] CLK_CPU_BCLKN [8] 2 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 [7] CLOCKS [6] [6] [6] [6] PEG_RX#[0..15] [14] DDR3 MISC DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15 JTAG & BPM B28 B26 A24 B23 K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32 3/26 DB for H/W modify. MISC DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] PEG_COMP connect to PIN H22&J22 W:4mils/S:15mils/L: 500mils. PEG_COMP connect to PIN J21 W:12mils/S:15mils/L: 500mils. THERMAL [6] [6] [6] [6] J22 J21 H22 PWR MANAGEMENT DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] PEG_COMP PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO 3 B27 B25 A25 B24 PCI EXPRESS* - GRAPHICS DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 Intel(R) FDI [6] [6] [6] [6] DMI U15B eDP C ϬϮ Sandy Bridge Processor (CLK,MISC,JTAG) U15A D 1 C_PEG_TX#0 C_PEG_TX#1 C_PEG_TX#2 C_PEG_TX#3 C_PEG_TX#4 C_PEG_TX#5 C_PEG_TX#6 C_PEG_TX#7 C_PEG_TX#8 C_PEG_TX#9 C_PEG_TX#10 C_PEG_TX#11 C_PEG_TX#12 C_PEG_TX#13 C_PEG_TX#14 C_PEG_TX#15 C505 C503 C501 C498 C494 C496 C490 C492 C485 C487 C481 C482 C475 C476 C468 C469 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15 CLK_DPLL_SSCLKP_R CLK_DPLL_SSCLKN_R 4 2 CLK_DPLL_SSCLKP [8] CLK_DPLL_SSCLKN [8] +1.05V_VTT +1.05V_VTT R389 R390 10K_4 +1.05V_VTT INT_eDP_HPD_Q H_PROCHOT# XDP_TDO XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TCLK XDP_TRST# 24.9/F_4 eDP_COMP 0_4P2R_04 CLK_DPLL_SSCLKP_R CLK_DPLL_SSCLKN_R Rb R398 Rc R397 *0_4 eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms *0_4 +1.05V_VTT Ra Rb Rc DIS NC Stuff Stuff SG/UMA Stuff NC NC 0.22uF AC coupling Caps for PCIE GEN1/2/3 4 3 1 Processor pull-up (CPU) DP & PEG Compensation 3 R168 R476 R474 R159 R162 R163 R475 62_4 51_4 51_4 51_4 *51_4 51_4 51_4 A 24.9/F_4 PEG_COMP R67 PEG_ICOMPI and RCOMPO signals should be routed within 500 mils typical impedance = 43 mohms PEG_ICOMPO signals should be routed within 500 mils typical impedance = 14.5 mohms 2 WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ Eϱ Size Custom Document Number Rev A WƌŽĐĞƐƐŽƌϭͬϰ;,ŽƐƚͬ'WhͿ Date: Monday, November 15, 2010 1 Sheet 2 of 40 5 4 3 2 1 Ϭϯ Sandy Bridge Processor (DDR3) U15C U15D D M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 C B [12] [12] [12] [12] [12] [12] M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CAS# M_A_RAS# M_A_WE# C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] AE10 AF10 V6 SA_BS[0] SA_BS[1] SA_BS[2] AE8 AD9 AF9 SA_CAS# SA_RAS# SA_W E# SA_CLK[0] SA_CLK#[0] SA_CKE[0] AB6 AA6 V9 M_A_CLKP0 [12] M_A_CLKN0 [12] M_A_CKE0 [12] SA_CLK[1] SA_CLK#[1] SA_CKE[1] AA5 AB5 V10 M_A_CLKP1 [12] M_A_CLKN1 [12] M_A_CKE1 [12] SA_CLK[2] SA_CLK#[2] SA_CKE[2] AB4 AA4 W9 SA_CLK[3] SA_CLK#[3] SA_CKE[3] AB3 AA3 W 10 SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3] AK3 AL3 AG1 AH1 M_A_CS#0 [12] M_A_CS#1 [12] SA_ODT[0] SA_ODT[1] SA_ODT[2] SA_ODT[3] AH3 AG3 AG2 AH2 M_A_ODT0 [12] M_A_ODT1 [12] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] C4 G6 J3 M6 AL6 AM8 AR12 AM15 M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] D4 F6 K3 N6 AL5 AM9 AR11 AM14 M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 [13] M_B_DQ[63:0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 M_A_DQSN[7:0] [12] M_A_DQSP[7:0] [12] M_A_A[15:0] [12] [13] [13] [13] [13] [13] [13] Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) M_B_BS#0 M_B_BS#1 M_B_BS#2 M_B_CAS# M_B_RAS# M_B_WE# C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] AA9 AA7 R6 SB_BS[0] SB_BS[1] SB_BS[2] AA10 AB8 AB9 SB_CAS# SB_RAS# SB_W E# SB_CLK[0] SB_CLK#[0] SB_CKE[0] AE2 AD2 R9 M_B_CLKP0 [13] M_B_CLKN0 [13] M_B_CKE0 [13] SB_CLK[1] SB_CLK#[1] SB_CKE[1] AE1 AD1 R10 M_B_CLKP1 [13] M_B_CLKN1 [13] M_B_CKE1 [13] SB_CLK[2] SB_CLK#[2] SB_CKE[2] AB2 AA2 T9 SB_CLK[3] SB_CLK#[3] SB_CKE[3] AA1 AB1 T10 SB_CS#[0] SB_CS#[1] SB_CS#[2] SB_CS#[3] AD3 AE3 AD6 AE6 M_B_CS#0 [13] M_B_CS#1 [13] SB_ODT[0] SB_ODT[1] SB_ODT[2] SB_ODT[3] AE4 AD4 AD5 AE5 M_B_ODT0 [13] M_B_ODT1 [13] SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] D7 F3 K6 N3 AN5 AP9 AK12 AP15 M_B_DQSN0 M_B_DQSN1 M_B_DQSN2 M_B_DQSN3 M_B_DQSN4 M_B_DQSN5 M_B_DQSN6 M_B_DQSN7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C7 G3 J6 M3 AN6 AP8 AK11 AP14 M_B_DQSP0 M_B_DQSP1 M_B_DQSP2 M_B_DQSP3 M_B_DQSP4 M_B_DQSP5 M_B_DQSP6 M_B_DQSP7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 C DDR SYSTEM MEMORY B [12] M_A_DQ[63:0] DDR SYSTEM MEMORY A D M_B_DQSN[7:0] [13] M_B_DQSP[7:0] [13] B M_B_A[15:0] [13] Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) A A WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ Eϱ 5 4 3 2 Size Custom Document Number Rev A WƌŽĐĞƐƐŽƌϮͬϰ;DĞŵŽƌLJͿ Date: Monday, November 15, 2010 1 Sheet 3 of 40 3 C125 22U/6.3VS_8 C144 22U/6.3VS_8 C157 22U/6.3VS_8 C46 *22U/6.3VS_8 C477 *22U/6.3VS_8 C141 22U/6.3VS_8 C147 22U/6.3VS_8 C197 22U/6.3VS_8 C107 22U/6.3VS_8 C151 22U/6.3VS_8 C467 *22U/6.3VS_8 C430 22U/6.3VS_8 B C461 22U/6.3VS_8 C41 22U/6.3VS_8 C29 22U/6.3VS_8 C53 22U/6.3VS_8 C431 22U/6.3VS_8 C47 *22U/6.3VS_8 22uF_8 x8 Socket TOP cavity 22uF_8 x10 Socket BOT cavity 22uF_8 x8 Socket TOP edge 470uF_7343 x4 3/26 DB change 10U FP to 0805. A C209 22U/6.3VS_8 C472 22U/6.3V_8 C167 22U/6.3V_8 C136 *22U/6.3VS_8 C148 22U/6.3VS_8 C464 22U/6.3VS_8 C193 22U/6.3V_8 C208 22U/6.3V_8 C470 *22U/6.3VS_8 C142 *22U/6.3VS_8 5/14 modify C445 C120 22U/6.3VS_8 *22U/6.3VS_8 C446 *22U/6.3VS_8 C460 *22U/6.3VS_8 C454 22U/6.3VS_8 C457 22U/6.3VS_8 C121 *22U/6.3VS_8 C192 22U/6.3V_8 C511 22U/6.3V_8 C198 *22U/6.3VS_8 C207 22U/6.3V_8 C166 22U/6.3V_8 C158 *22U/6.3VS_8 C512 22U/6.3V_8 C101 22U/6.3VS_8 C168 22U/6.3V_8 22uF_8 x7 Socket TOP cavity 5/4: add C8260/ C8322 22uF_8 x5 Socket BOT cavity 22uF_8 x2 Socket TOP cavity (no stuff) 22uF_8 x5 Socket BOT cavity (no stuff) 330uF_7343 x2 C169 22U/6.3V_8 C471 22U/6.3V_8 Ra R473 *0_4 DIS Ra +1.8V R66 *0_4/S NC SNB: 1.5A B6 A6 A2 VIDALERT# VIDSCLK VIDSOUT AJ29 AJ30 AJ28 H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT C42 10U/6.3V_8 C45 1U/6.3V_4 C44 1U/6.3V_4 + C432 330U/2V_7343 330uF x1, 10uF_8 x1, 1uF_4 x2 Socket BOT edge. *0_8 1 DDR_VTTREF [12,13,32] 3 Q19 2N7002 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VCCPLL1 VCCPLL2 VCCPLL3 MAIND [36] 11/13 C516 mount for S3 black screen issue 5/14 modify AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1 +1.5V_CPU SNB: 5A C134 10U/6.3V_6 C152 10U/6.3V_8 C204 10U/6.3V_6 C153 10U/6.3V_6 4/27: layout modify 330uF x1, 10uF_8 x6 Socket BOT edge. + C173 10U/6.3V_6 C213 10U/6.3V_6 C C516 220U/6.3V_6X4.5ESR18 8/31 C516 FP changed from 330U_2.5V_5.0x5.9ESR10m to 220U/6.3V_6x4.5ESR18 3/26 DB change 10U FP to 0805. SNB: 6A VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 M27 M26 L26 J26 J25 J24 H26 H25 C447 10U/6.3V_8 C31 10U/6.3V_8 +VCCSA C97 10U/6.3V_8 C24 *10U/6.3V_8 330uF x1, 10uF_8 x1 Socket BOT edge, 10uF_8 x2 Socket BOT cavity. 3/26 DB change 10U FP to 0805. VCCSA_SENSE H23 VCCUSA_SENSE_R R388 *0_4/S short0402 VCCUSA_SENSE [33] B 11/12 short FC_C22 VCCSA_VID1 R392 10K_4 R393 10K_4 C22 H_FC_C22 C24 VCCSA_SEL [33] Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) 3/26 DB change 10U FP to 0805. 5/11: Add for intel CRB 9/8 delete JP1 3/26 DB Modify. VCC_SENSE VSS_SENSE R128 AJ35 AJ34 VCCIO_SENSE VSSIO_SENSE B10 A10 100_4 R124 SVID CLK *54.9/F_4 +1.5VSUS +1.5V_CPU H_CPU_SVIDCLK Q40 AON7410 VR_SVID_CLK [39] 3/26 DB Modify. +1.05V_VTT Place PU resistor close to CPU TP53 R121 130/F_4 R118 *130/F_4 SVID DATA Place PU resistor close to VR H_CPU_SVIDDAT Trace Route to Power IC area. R170 220_8 1 2 3 5 +1.05V_VTT MAIND VCCP_SENSE [34] +1.5VSUS +1.05V_VTT +VCC_CORE 100_4 VSSP_SENSE Place PU resistor close to VR Layout note: need routing together and ALERT need between CLK and DATA. VCC_SENSE [39] VSS_SENSE [39] R133 2 C262 *470P/50V_4 VR_SVID_DATA [39] Place PU resistor close to CPU [2,10,12,13,32,33,38] +1.5VSUS [2,10,27] +1.5V_CPU [2,29,33,34,38,39] +1.05V_VTT [33] +VCCSA [39,40] +VCC_GFX [39,40] +VCC_CORE 4 +1.05V_VTT H_CPU_SVIDALRT# 3 R158 43_4 VR_SVID_ALERT# [39] 2 0.1U/10V_4 C517 0.1U/10V_4 C518 0.1U/10V_4 C514 0.1U/10V_4 Q20 2N7002 MAIN_ONG [2,36] A 5/6: modify CPU VDDQ WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ SVID ALERT 75_4 3/26 DB Modify. R166 C515 3/26 DB add for Intel. Placement close to CPU. 3/26 DB Modify. 5/12: modify Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) 5 SM_VREF R157 MAIND +1.05V_VTT +1.05V_VTT_40 CAD Note: +VDDR_REF_CPU should have 10 mil trace width +VDDR_REF_CPU AL1 R165 100K_4 SG/UMA Stuff 100_4 D 2 J23 C138 22U/6.3VS_8 SENSE LINES VCCIO40 C179 22U/6.3VS_8 VCC_AXG_SENSE [39] VSS_AXG_SENSE [39] R138 1 C SNB: 21.5A AK35 AK34 +VCC_GFX 2 C49 22U/6.3VS_8 E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 +VCC_GFX VAXG_SENSE VSSAXG_SENSE 3 C165 22U/6.3VS_8 VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 C450 22U/6.3VS_8 VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 100_4 1 C178 22U/6.3VS_8 C137 22U/6.3VS_8 AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 R136 4 C28 22U/6.3VS_8 C135 22U/6.3VS_8 +1.05V_VTT VREF C58 22U/6.3VS_8 AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 3/26 DB Modify. DDR3 -1.5V RAILS C206 22U/6.3VS_8 C92 22U/6.3VS_8 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 U15G 22uF_8 x2 Socket TOP cavity 22uF_8 x2 Socket BOT cavity 22uF_8 x4 Socket TOP edge 22uF_8 x4 Socket BOT edge 470uF_7343 x2 SA RAIL C51 22U/6.3VS_8 C127 22U/6.3VS_8 PEG AND DDR C108 22U/6.3VS_8 C473 22U/6.3VS_8 SVID C48 22U/6.3VS_8 SNB: 8.5A VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 SENSE LINES D AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 Ϭϰ Sandy Bridge Processor (GRAPHIC POWER) 9/4 all of these 22uF/6.3V capacitors are repleaced by 10uF/6.3V in BOM U15F +VCC_CORE CORE SUPPLY SNB: 55A 1 MISC Sandy Bridge Processor (POWER) 9/4 all of these 22uF/6.3V capacitors are repleaced by 10uF/6.3V in BOM 2 GRAPHICS 4 1.8V RAIL 5 Eϱ Size Custom Document Number Rev A WƌŽĐĞƐƐŽƌϯͬϰ;WŽǁĞƌͿ Date: Monday, November 15, 2010 1 Sheet 4 of 40 4 3 2 Sandy Bridge Processor (GND) U15H D C B AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29 Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) U15E VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS For CPU debug. F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3 CFG0 TP20 TP19 CFG2 TP24 CFG4 CFG5 CFG6 CFG7 [12] SMDDR_VREF_DQ0_M3 [13] SMDDR_VREF_DQ1_M3 R394 *1K_4 [34] H_VTTVID1 R391 11/12 short R387 *1K_4 *0_4/S short0402 AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] AJ31 AH31 AJ33 AH33 RSVD1 RSVD2 RSVD3 RSVD4 AJ26 RSVD5 B4 D1 RSVD6 RSVD7 F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 J20 B18 A19 RSVD24 RSVD25 RSVD26 J15 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 L7 AG7 AE7 AK2 W8 RSVD33 RSVD34 RSVD35 AT26 AM33 AJ27 RSVD37 RSVD38 RSVD39 RSVD40 T8 J16 H16 G16 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 AR35 AT34 AT33 AP35 AR34 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 B34 A33 A34 B35 C35 RSVD51 RSVD52 AJ32 AK32 RSVD53 AH27 RSVD54 RSVD55 AN35 AM35 D RSVD56 RSVD57 RSVD58 TP63 TP64 AT2 AT1 AR1 For rPGA socket, RSVD59 pin should be left NC. B1 B Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) CFG[6:5] (PCIE Port Bifurcation Straps) 0 Normal Operation Lane Reversed CFG4 (DP Presence Strap) Disable; No physical DP attached to eDP Enable; An ext DP device is connected to eDP CFG7 (PEG Defer Training) PEG train immediately following xxRESETB de assertion PEG wait for BIOS training 11: 10: 01: 00: (hh) TWH PEG bus is Lane Reversed (Default) x16 - Device 1 functions 1 and 2 disabled x8, x8 - Device 1 function 1 enabled ; function 2 disabled Reserved - (Device 1 function 1 disabled ; function 2 enabled) x8,x4,x4 - Device 1 functions 1 and 2 enabled A CFG2 R155 1K_4 CFG4 R156 *1K_4 CFG7 R153 *1K_4 CFG5 R141 *1K_4 CFG6 R152 *1K_4 WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ Eϱ 5 C #27636 SNB EDS0.7v1 no function. KEY The CFG signals have a default value of '1' if not terminated on the board. 1 CFG2 (PEG Static Lane Reversal) VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 Sandy Bridge_rPGA_Rev0p61 rpga989-47989-socket DGG^9000014 IC SOCKET RPGA 989P(P1.0,M/H3.0) Processor Strapping A Ϭϱ Sandy Bridge Processor (RESERVED, CFG) U15I AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W 35 W 34 W 33 W 32 W 31 W 30 W 29 W 28 W 27 W 26 U9 U8 U6 U5 U3 U2 1 RESERVED 5 4 3 2 Size Custom Document Number Rev A WƌŽĐĞƐƐŽƌϰͬϰ;'ƌŽƵŶĚͿ Date: Monday, November 15, 2010 1 Sheet 5 of 40 5 4 3 2 1 Cougar Point (DMI,FDI,PM) DMI0TXN DMI1TXN DMI2TXN DMI3TXN [2] [2] [2] [2] DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 AY24 AY20 AY18 AU18 DMI0TXP DMI1TXP DMI2TXP DMI3TXP FDI_INT +1.05V BJ24 DMI_ZCOMP FDI_FSYNC0 49.9/F_4 DMI_COMP BG25 DMI_IRCOMP FDI_FSYNC1 BC10 FDI_FSYNC1 [2] R284 750/F_4 DMI_RBIAS BH21 DMI2RBIAS FDI_LSYNC0 AV14 FDI_LSYNC0 [2] FDI_LSYNC1 BB10 FDI_LSYNC1 [2] C [2] R584 *0_4/S short0402 R590 *0_4 C2003 1U/10V_4 SYS_PWROK [29] EC_PWROK EC_PWROK_R K3 R312 R336 SYS_PWROK_R *0_4/S short0402 *0_4 EC_PWROK_R 0_4 R334 0_4 R630 P12 L22 R578 [29] DNBSWON# R570 PW ROK SUS_STAT# / GPIO61 RSMRST# SUS_PWR_ACK_R *0_4/S short0402 K16 SUSW ARN#/SUSPW RDNACK/GPIO30 E20 PW RBTN# 8/26 A-->B modify B N3 SUSCLK / GPIO62 H20 0_4 DPWROK 0_4 PCIE_WAKE# ACPRESENT / GPIO31 E10 BATLOW # / GPIO72 PM_RI# A10 RI# CLKRUN# CLKRUN# LVD_IBG LVD_VBG LVD_VREFH LVD_VREFL PCH_LA_CLK# PCH_LA_CLK AK39 AK40 LVDSA_CLK# LVDSA_CLK [21] PCH_LA_DATAN0 [21] PCH_LA_DATAN1 [21] PCH_LA_DATAN2 PCH_LA_DATAN0 PCH_LA_DATAN1 PCH_LA_DATAN2 AN48 AM47 AK47 AJ48 LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 [21] PCH_LA_DATAP0 [21] PCH_LA_DATAP1 [21] PCH_LA_DATAP2 PCH_LA_DATAP0 PCH_LA_DATAP1 PCH_LA_DATAP2 AN47 AM49 AK49 AJ47 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 [29] PCH_SUSCLK_L R294 *0_4/S short0402 PCH_SUSCLK [29] PCH_LB_CLK# PCH_LB_CLK AF40 AF39 LVDSB_CLK# LVDSB_CLK PCH_LB_DATAN0 PCH_LB_DATAN1 PCH_LB_DATAN2 AH45 AH47 AF49 AF45 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 [21] PCH_LB_DATAP0 [21] PCH_LB_DATAP1 [21] PCH_LB_DATAP2 PCH_LB_DATAP0 PCH_LB_DATAP1 PCH_LB_DATAP2 AH43 AH49 AF47 AF43 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 [22] PCH_CRT_B [22] PCH_CRT_G [22] PCH_CRT_R TP39 D10 SLP_S5 [29] H4 R330 0_4 SUSC# [29] SLP_S3# F4 R620 0_4 SUSB# [29] SLP_A# [29] SLP_A# G10 R308 *0_4 SLP_SUS# G16 R574 *0_4 PMSYNCH AP14 [22] PCH_DDCCLK [22] PCH_DDCDATA (+3VS5) K14 R670 R669 R671 0_6 PCH_CRT_B 0_6 PCH_CRT_G 0_6 PCH_CRT_R N48 P49 T49 CRT_BLUE CRT_GREEN CRT_RED R673 R672 0_6 0_6 T39 M40 CRT_DDC_CLK CRT_DDC_DATA M47 M49 CRT_HSYNC CRT_VSYNC T43 T42 DAC_IREF CRT_IRTN PCH_HSYNC_R PCH_VSYNC_R R675 R674 0_6 0_6 DAC_IREF 9/9 remove in BOM SLP_SUS# [29] PM_SYNC [2] C1013 *6.8P/50V_4 PCH_CRT_B C1014 *6.8P/50V_4 PCH_CRT_G C1015 *6.8P/50V_4 PCH_CRT_R R227 1K/F_4 R610 10K_4 PM_BATLOW# R350 *8.2K_4 PCIE_WAKE# R613 10K_4 SLP_LAN# R268 *10K_4 SUS_PWR_ACK R577 10K_4 AC_PRESENT_R R270 10K_4 +3V R209 R197 2.2K_4 2.2K_4 CTRL_CLK CTRL_DATA R235 2.37K/F_4 LVD_IBG R204 R203 [22] PCH_HSYNC [22] PCH_VSYNC 33_4 33_4 SDVO_INTN SDVO_INTP AP39 AP40 D P38 M39 SDVO_CLK [22] SDVO_DATA [22] DDPB_AUXN DDPB_AUXP DDPB_HPD AT49 AT47 AT40 DPB_HPD_Q DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49 DPB_LANE0_N DPB_LANE0_P DPB_LANE1_N DPB_LANE1_P DPB_LANE2_N DPB_LANE2_P DPB_LANE3_N DPB_LANE3_P DDPC_CTRLCLK DDPC_CTRLDATA P46 P42 DDPC_AUXN DDPC_AUXP DDPC_HPD AP47 AP49 AT38 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 DDPD_CTRLCLK DDPD_CTRLDATA C M43 M36 DDPD_AUXN DDPD_AUXP DDPD_HPD AT45 AT43 BH41 DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42 [7,10,21,22,23,27,28,36] +5V [2,7,8,9,10,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39] +3V [2,7,8,9,10,14,24,29,31,33,35,36,38] +3VS5 [7,21,27,28,29,30,31] +3VPCU [7,10] +3V_DSW [7,10,29] +3V_RTC INT HDMI disable (DIS only remove) System PWR_OK(CLG) C399 DPB_LANE0_N DPB_LANE0_P DPB_LANE1_N DPB_LANE1_P DPB_LANE2_N DPB_LANE2_P DPB_LANE3_N DPB_LANE3_P IN_D2# IN_D2 IN_D1# IN_D1 IN_D0# IN_D0 IN_CLK# IN_CLK PCH_HSYNC_R PCH_VSYNC_R [22] [22] [22] [22] [22] [22] [22] [22] ** +3VS5 *0.1U/10V_4 DPWROK FOR DSW +3VPCU +3VPCU 5/12: modify 5 PM_RI# 3/26 DB change net name. AM42 AM40 SYS_PWROK 2 +3V_DSW IMVP_PWRGD [39] 4 EC_PWROK 1 R554 *10K_4 R553 *10K_4 D21 DPWROK +3VS5 U8 *TC7SH08FU 3 +3VS5 INT LVDS & CRT disable (DIS only remove) SDVO_STALLN SDVO_STALLP B CougarPoint_Rev_0p7 fcbga989-intel-cougarpoint AJ0QMVY0T01 IC CTRL(989P)COUGARPOINT QMVY TOP B/S PCH Pull-high/low(CLG) AP43 AP45 CougarPoint_Rev_0p7 fcbga989-intel-cougarpoint AJ0QMVY0T01 IC CTRL(989P)COUGARPOINT QMVY TOP B/S 9/8 EMI(near PCH) SLP_LAN# SDVO_TVCLKINN SDVO_TVCLKINP SDVO_CTRLCLK SDVO_CTRLDATA [21] PCH_LB_DATAN0 [21] PCH_LB_DATAN1 [21] PCH_LB_DATAN2 TP44 SLP_S4# SLP_LAN# / GPIO29 L_CTRL_CLK L_CTRL_DATA PCIE_WAKE# [24,26,27] (+3VS5) PM_BATLOW# T45 P39 AF37 AF36 [21] PCH_LB_CLK# [21] PCH_LB_CLK RSMRST# 5/12: modify (+3VS5) SLP_S5# / GPIO63 CTRL_CLK CTRL_DATA 11/12 short N14 (DSW) AC_PRESENT_R R545 G8 (+3VS5) DRAMPW ROK *0_4 R546 B9 [2] DSWVREN (+3VS5) C21 (+3VS5) DPW ROK CLKRUN# / GPIO32 RSMRST# APW ROK A18 E22 (+3V) B13 DNBSWON#_R *0_4/S short0402 R269 SYS_PW ROK DSW VRMEN W AKE# PM_DRAM_PWRGD 11/12 short [29] SUS_PWR_ACK SYS_RESET# L10 RSMRST# [29] AC_PRESENT SUSACK# APWROK_R [2] PM_DRAM_PWRGD [29] C12 XDP_DBRST# XDP_DBRST# 10/11 add SUSACK#_R FDI_FSYNC0 L_DDC_CLK L_DDC_DATA AE48 AE47 [2] R563 System Power Management [29] SUSACK# FDI_INT L_BKLTCTL T40 K47 TP35 [21] PCH_LA_CLK# [21] PCH_LA_CLK AW 16 P45 LVD_IBG AV12 11/12 short SUS_PWR_ACK_R [2] [2] [2] [2] [2] [2] [2] [2] 3/26 DB change net name. L_BKLTEN L_VDD_EN PCH_EDIDCLK PCH_EDIDDAT [21] PCH_DPST_PWM [21] PCH_EDIDCLK [21] PCH_EDIDDATA J47 M45 3 AW 24 AW 20 BB18 AV18 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 [21] PCH_LVDS_BLON [21] PCH_DISP_ON *RB500V-40 8/26 A-->B modify R319 100K_4 3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9 [2] [2] [2] [2] [2] [2] [2] [2] INT. HDMI [2] [2] [2] [2] FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 Digital Display Interface DMI0RXP DMI1RXP DMI2RXP DMI3RXP FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9 CRT DMI0RXN DMI1RXN DMI2RXN DMI3RXN FDI BE24 BC20 BJ18 BJ20 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 U24D DMI [2] [2] [2] [2] D BC24 BE20 BG18 BG20 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 LVDS U24C [2] [2] [2] [2] Ϭϲ Cougar Point (LVDS,DDI) C595 *0.1U/10V_4 D20 INT HDMI Detect Function 2 +3VPCU add cap to timing tune 2 R639 XDP_DBRST# R624 10K_4 R599 *1K_4 RSMRST# SYS_PWROK R547 R313 8.2K_4 10K_4 *100K_4 4/29 modify PCH to Res routeing 50 ohm Impedance. Res to connector filter routeing 37.5ohm Impedance. R202 R201 R200 150/F_4 150/F_4 150/F_4 R506 0_4 R320 DPB_HPD_Q R511 *100K_4 PCH_CRT_R 1 3 Q45 *2N7002 HDMI_HPD_CON R565 330K_4 DSWVREN R568 WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ *330K_4 On Die DSW VR Enable +5V High = Enable (Default) Low = Disable 4 A Q49 *2N7002 [22] +3V_RTC R496 *100K_4 9/10 change from 10K to 100K 9/28 change to NC 5 Q48 *PDTC144EU 9/6 delete a short net in"EC_PWROK" PCH_CRT_B PCH_CRT_G 0_4 1 CLKRUN# PD Res place close to PCH 2 +3V 1 *RB500V-40 A 3 Eϱ 2 Size Custom Document Number Rev A W,ϭͬϲ;,ŽƐƚͬŝƐƉůĂLJͿ Date: Monday, November 15, 2010 1 Sheet 6 of 40 5 4 3 Cougar Point (HDA,JTAG,SATA) L34 HDA_SYNC SPKR T10 SPKR ACZ_RST# K34 HDA_RST# HDA_SDIN0 TP1004 G34 HDA_SDIN1 C34 A36 C36 *0_4/S HDA_DOCK_EN# / GPIO33 (+3VS5) N32 AM10 AM8 AP11 AP10 SATA_RXN1_C SATA_RXP1_C SATA_TXN1_C SATA_TXP1_C SATA2RXN SATA2RXP SATA2TXN SATA2TXP AD7 AD5 AH5 AH4 SATA3RXN SATA3RXP SATA3TXN SATA3TXP AB8 AB10 AF3 AF1 SATA4RXN SATA4RXP SATA4TXN SATA4TXP Y7 Y5 AD3 AD1 Y3 Y1 AB3 AB1 JTAG_TCK SATA5RXN SATA5RXP SATA5TXN SATA5TXP TP50 PCH_JTAG_TMS H7 JTAG_TMS SATAICOMPO Y11 TP51 PCH_JTAG_TDI_R K5 JTAG_TDI SATAICOMPI Y10 TP52 PCH_JTAG_TDO_R H1 JTAG_TDO *10K_4 PCH_SPI_SI [29] PCH_SPI_SO PCH Strap Table Pin Name SPKR SATA1RXN SATA1RXP SATA1TXN SATA1TXP J3 PCH_SPI_CS0# PCH_SPI_CS1# PCH_SPI_SI PCH_SPI_SO SPI_CLK Y14 SPI_CS0# T1 SPI_CS1# V4 SPI_MOSI JTAG SPI_MISO No reboot mode setting R302 AB13 SATA3_COMP R303 49.9/F_4 SATA3RBIAS AH1 SATA3_RBIAS R606 750/F_4 SATALED# (+3V) SATA0GP / GPIO21 P3 R640 10K_4 V14 R321 10K_4 Sampled PWROK 0 = Default (weak pull-down 20K) 1 = Setting to No-Reboot mode +3V_RTC_2 1K_4 +3V_RTC_1 GNT1# GNT0# 1 0 1 0 PWROK Boot Location ESI strap (Server only) PWROK Intel Anti-Theft HDD protection Only for Interposer PWROK 0 = Disable (Internal pull-down 20kohm) Flash Descriptor Security PWROK weak pull-down 20kohm RSMRST 0 = Support by 1.8V (weak pull-down) 1 = Support by 1.5V PWROK D10 BAT54C R520 SPKR +3V R636 R518 R514 GPIO33 *1K_4 *1K_4 10K_4 R503 C389 1U/6.3V_4 C387 1U/6.3V_4 J1 *SOLDERJUMPER-2 C 4/20 DB add. HDA Bus(CLG) 10K_4 33_4 *0_6 SRTC_RST# R280 PCH JTAG Debug(CLG) 5/3 : modify +3VS5 Q46 2N7002K 3 ACZ_SYNC 1 4/29: modify 10P/50V_4 C557 +3V PCI_GNT3# [8] Bios request, for can't boot Capella R566 R347 *210/F_4 [23] ACZ_RST#_AUDIO R522 33_4 ACZ_RST# [23] ACZ_SDOUT_AUDIO R535 33_4 ACZ_SDOUT R343 *210/F_4 R358 *210/F_4 PCH_JTAG_TMS PCH_JTAG_TDI_R PCH_JTAG_TDO_R PCH_JTAG_TCK_R R331 *100/F_4 R327 *100/F_4 R346 *100/F_4 R329 *51_4 B R540 10/13 remove all R (Intel confirmed) Vender Size P/N EON 4MB AKE39FN0Q00 (EN25F32-100HIP) 4MB AKE391P0N00 (W25Q32BVSSIG) 4/23. Winbond Socket 330K_4 PCH SPI ROM(CLG) DG008000031 +3V +3V_RTC U22 8/26 A-->B modify *1K_4 PCH_SPI_CS0# PCH_SPI_CLK PCH_SPI_SI PCH_SPI_SO GPIO33_E [29] [Need external pull-down for LPC BIOS] Default weak pull-up on GNT0/1# R603 R628 R548 *0_4 *0_4 *0_4 PCH_SPI1_CLK_R PCH_SPI1_SI_R PCH_SPI1_SO_R BBS_BIT0 *1K_4 *1K_4 BBS_BIT1 [8] NV_ALE [8] 1 6 5 2 CE# SCK SI SO HOLD# 7 3 W P# VSS 4 C645 *22P/50V_4 VDD 8 R517 *3.3K_4 C559 *0.1U/10V_4 *SPI Flash Socket USE GPIO PIN 4/29 modify +1.8V +1.8V R608 R616 R607 R215 4.7K_4 1K_4 Integrated Clock Chip Enable RSMRST# Should be pull-down (weak pull-up 20K) R611 On-die PLL Voltage Regulator RSMRST# 0 = Disable 1 = Enable (Default) R617 *1K_4 iTPM function Disable APWROK 0 = Default (weak pull-down 20K) 1 = Enable R604 1K_4 3 *1K_4 R549 *3.3K_4 [8]N.A at CPT EDS 0.7 NV_CLE H_SNB_IVB# [2] [10] +V3.3A_1.5A_HDA_IO [2,6,8,9,10,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39] +3V [6,21,27,28,29,30,31] +3VPCU [6,10] +3V_DSW [6,10,29] +3V_RTC [4,10,36,38] +1.8V ACZ_SYNC ACZ_SDOUT R544 GPIO33_E PCH_SPI_SI +3V *1K_4 2.2K_4 +3VS5 8/26 A-->B modify 0 = Override 1 = Default (weak pull-up 20K) [29] 4 ACZ_BCLK 33_4 +5V 10/8 Intel PDG R602 R513 NV_ALE DMI Termination voltage J2 *SOLDERJUMPER-2 SRTC_RST# R2005 1M_4 +3V SPI LPC GNT2# / GPIO53 On-Die PLL VR Voltage Select C390 1U/6.3V_4 R297 20K/F_4 11/12 short R242 [23] BIT_CLK_AUDIO [23] ACZ_SYNC_AUDIO PCH_INVRMEN Should not be pull-down (weak pull-up 20K) 5 *0_6/S Circuit PWROK SPI_MOSI +3VPCU R286 10/8 add for EMI +1.05V Configuration HDA_DOCK_EN#/GPIO33 Different from Calpella FOR DSW 9/3 delete MDC function support "ACZ_BCLK"-R246-"BIT_CLK_MDC" "ACZ_SYNC"-R214-"ACZ_SYNC_MDC" "ACZ_RST#"-R527-"ACZ_RST#_MDC" "ACZ_SDOUT"-R539-"ACZ_SDOUT_MDC" 0 = Override 1 = Default (weak pull-up 20K) GPIO28 *0_6 BBS_BIT0 P1 Should be always pull-up GPIO8 37.4/F_4 SATA3COMPI ALWAYS HDA_SDO +3V_DSW R273 +3V_RTC_0 R275 C2001 10P/50V_4 Flash Descriptor Security Only for Interposer Boot BIOS Selection 0 [bit-0] RTC_RST# 20K/F_4 3/26 DB modify for placement. SATA_COMP Integrated 1.05V VRM enable HDA_SYNC R298 RTC_RST# INTVRMEN NV_CLE +3V_RTC RTC Power trace width 20mils. AB12 SATA1GP / GPIO19 PWROK 30mils 5/12: modify CN17 BAT_CONN PWROK GPIO19 RTC Circuitry(RTC) ODD (SATA1 1.5Gb/s) DG recommended that AC coupling capacitors should be close to the connector (<100 mils) for optimal signal quality. Top-Block Swap Override Boot BIOS Selection 1 [bit-1] D RTC_X2 HDD0 (SATA3 6.0Gb/s) SATA_RXN1 [28] SATA_RXP1 [28] SATA_TXN1 [28] SATA_TXP1 [28] 8/31 delete excess AC coupling C C635,C634,C409,C410 C404,C405,C633,C632 GNT3# / GPIO55 Different from Calpella SATA_RXN0 [28] SATA_RXP0 [28] SATA_TXN0 [28] SATA_TXP0 [28] 8/26 A-->B modify 0 = "top-block swap" mode 1 = Default (weak pull-up 20K) GNT1# / GPIO51 R567 10M_4 [29] CougarPoint_Rev_0p7 fcbga989-intel-cougarpoint AJ0QMVY0T01 IC CTRL(989P)COUGARPOINT QMVY TOP B/S Strap description Different from Calpella +3V SERIRQ SATA3RCOMPO (+3V) U3 Y5 32.768KHZ 8.2K_4 SATA_LED# [27] SPI [29] SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C PCH_JTAG_TCK_R R641 +3VPCU AM3 AM1 AP7 AP5 HDA_DOCK_RST# / GPIO13 T3 18P/50V_4 TP37 TP36 R324 SATA0RXN SATA0RXP SATA0TXN SATA0TXP TP47 PCH_SPI_CLK C601 2 1 HDA_SDO 11/12 short [29] PCH_SPI_CS0# A HDA_SDIN3 (+3V) GPIO33 [29] PCH_SPI_CLK B SERIRQ HDA_SDIN2 A34 C SERIRQ RTC_X1 1 ACZ_SYNC E34 USB3_SMI# PCH_DRQ#0 PCH_DRQ#1 V5 18P/50V_4 2 HDA_BCLK 9/3 delete net "ACZ_SDIN1" [26] E36 K36 C602 1 N34 R652 LDRQ0# LDRQ1# / GPIO23 INTVRMEN ACZ_SDIN0 10/11 mount [27,29] (+3V) ACZ_BCLK ACZ_SDOUT LFRAME# 2 C17 D36 3 4 INTRUDER# PCH_INVRMEN FW H4 / LFRAME# 2 SRTCRST# K22 [27,29] [27,29] [27,29] [27,29] 1 G22 SM_INTRUDER# LAD0 LAD1 LAD2 LAD3 LPC RTCRST# RTC D20 SRTC_RST# C38 A38 B37 C37 2 [23] RTCX2 RTC_RST# LAD0 LAD1 LAD2 LAD3 FW H0 / FW H1 / FW H2 / FW H3 / SATA 6G SPKR RTCX1 C20 SATA [23] 1M_4 A20 RTC_X2 Ϭϳ RTC Clock 32.768KHz 3/26 DB change net name. RTC_X1 IHDA R281 +3V_RTC 1 4/29 DB change net name. U24A D 2 *1K_4 +V3.3A_1.5A_HDA_IO 4/29 reserve. ICC_EN# A WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ [9] PLL_ODVR_EN [9] Eϱ +3V 2 Size Custom Document Number Rev A W,Ϯͬϲ;,ͬZdͬ^dͬ^W/Ϳ Date: Monday, November 15, 2010 1 Sheet 7 of 40 5 4 3 2 Cougar Point-M (PCI,USB,NVRAM) 10 9 8 7 6 MPC_PWR_CTRL# LCD_BK 1 2 3 4 5 PCH_GPIO4 BT_COMBO_EN# 10K_10P8R_6 3/26 DB change Part reference. +3VS5 RP13 10 9 8 7 6 USB_OC4# USB_OC1# USB_OC2# USB_OC3# USB_OC6# USB_OC0# USB_OC7# USB_OC5# 1 2 3 4 5 B21 M20 AY16 BG46 TP21 TP22 TP23 TP24 NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 NV_ALE NV_CLE NV_RCOMP NV_RB# 10K_10P8R_6 MPC_PWR_CTRL# Low = MPC ON High = MPC OFF (Default) MPC_PWR_CTRL# R521 *1K_4 C PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# [27] BT_COMBO_EN# [7] BBS_BIT1 [7] PCI_GNT3# [21] LCD_BK K40 K38 H38 G38 BT_COMBO_EN# C46 C44 E40 BBS_BIT1 D47 E42 F46 PCI_GNT3# MPC_PWR_CTRL# LCD_BK G42 G40 C42 D44 PCH_GPIO4 DGPU_IDLE_INT# [17] DGPU_IDLE_INT# Bios swap GPIO 11/8 delete R2001 4/23. PCI_PME# TP46 K10 PCI_PLTRST# B C6 CLK_PCI_TPM_R CLK_PCI_CARD_R R230 22_4 TP76 TP34 CLK_PCI_FB H49 H43 J48 K42 H40 CLK_PCI_FB_R 9/5 remove R213 in BOM R213 [27] CLK_33M_DEBUG C1011 18P/50V_4 NV_WE#_CK0 NV_WE#_CK1 AV5 AY1 REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 (+3V) (+3V) (+3V) (+3V) (+3V) (+3V) (+3V) C355 C358 0.1U/10V_4 0.1U/10V_4 PCIE_TXN2_LAN_C PCIE_TXP2_LAN_C PERN2 PERP2 PETN2 PETP2 PCIE_TXN3_USB3_C PCIE_TXP3_USB3_C BG36 BJ36 AV34 AU34 BF36 BE36 AY34 BB34 8/26 A-->B modify BG37 BH37 AY36 BB36 NV_ALE NV_CLE NV_ALE NV_CLE [7] [7] AT12 BF3 USBRBIAS# C33 (+3VS5) (+3VS5) (+3VS5) (+3VS5) (+3VS5) (+3VS5) (+3VS5) (+3VS5) PLTRST# CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 USBP1USBP1+ USBP2USBP2+ USBP4USBP4+ [23] [23] [26] [26] [26] [26] USBP12USBP12+ [25] [25] USB2.0 EXTERNAL USB2.0 USB2.0 USB2.0/USB3.0 COMBO USB2.0 USB2.0/USB3.0 COMBO Bluetooth J2 CLK_PCH_SRC2N CLK_PCH_SRC2P AB49 AB47 9/3 delete BT function (USB) delete net "USB8+/-" CLK_PCIE_REQ2# 2 1 5 [13,17,29] MBDATA2 2 CLK_PCIE_REQ3# R587 3 CLK_PCIE_REQ4# R541 22.6/F_4 USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7# [9] 4/23. V45 V46 L14 BOARD_ID0 R638 R323 SMB_PCH_DAT 3 Q44 2N7002 1 R487 4.7K_4 R486 4.7K_4 +3V [2,14,24,26,27,29] SMB_PCH_CLK 3 SMB_RUN_DAT [12,13] 2 R338 100K_4 1 SMB_RUN_CLK [12,13] Q43 2N7002 [9] AB42 AB40 CLK_PEGB_REQ# E6 V40 V42 BOARD_ID2 T13 K12 +3V AK14 AK13 TP41 TP38 10K_4 10K_4 CLK_PCH_ITPN CLK_PCH_ITPP R597 R612 R287 10K_4 10K_4 10K_4 CLK_PEGB_REQ# CLK_PEGA_REQ# R360 R344 *10K_4 *10K_4 G12 SMB_ME0_DAT DRAMRST_CNTRL_PCH C13 SML1ALERT#_R E14 SMB_ME1_CLK M16 SMB_ME1_DAT M7 CL_CLK_R TP43 T11 CL_DAT_R TP48 P10 CL_RST#_R TP49 M10 CLK_PEGA_REQ# CLKOUT_PEG_A_N CLKOUT_PEG_A_P AB37 AB38 CLK_PCH_PEGAN CLK_PCH_PEGAP CLKOUT_DMI_N CLKOUT_DMI_P AV22 AU22 CLK_CPU_BCLKN [2] CLK_CPU_BCLKP [2] CLKOUT_DP_N CLKOUT_DP_P AM12 AM13 CLK_DPLL_SSCLKN [2] CLK_DPLL_SSCLKP [2] (+3VS5) (+3VS5) SML1DATA / GPIO75 CL_CLK1 CL_DATA1 CL_RST1# (+3VS5) CLKOUT_PCIE0N CLKOUT_PCIE0P D [2] TP40 C PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P CLOCKS PCIECLKRQ1# / GPIO18 CLKOUT_PCIE2N CLKOUT_PCIE2P CLKIN_DMI_N CLKIN_DMI_P BF18 BE18 CLK_BUF_PCIE_3GPLL# CLK_BUF_PCIE_3GPLL BJ30 BG30 CLK_BUF_BCLK_N CLK_BUF_BCLK_P G24 E24 CLK_BUF_DREFCLK# CLK_BUF_DREFCLK AK7 AK5 CLK_BUF_DREFSSCLK# CLK_BUF_DREFSSCLK K45 CLK_PCH_14M H45 CLK_PCI_FB PCIECLKRQ2# / GPIO20 CLKIN_GND1_N CLKIN_GND1_P CLKOUT_PCIE3N CLKOUT_PCIE3P PCIECLKRQ3# / GPIO25 CLKIN_DOT_96N CLKIN_DOT_96P CLKOUT_PCIE4N CLKOUT_PCIE4P CLKIN_SATA_N CLKIN_SATA_P 3/26 DB del external clock generator. PCIECLKRQ4# / GPIO26 REFCLK14IN CLKOUT_PCIE5N CLKOUT_PCIE5P CLKIN_PCILOOPBACK C311 18P/50V_4 PCIECLKRQ5# / GPIO44 CLKOUT_PEG_B_N CLKOUT_PEG_B_P XTAL25_IN XTAL25_OUT V47 V49 R206 1M_4 XTAL25_IN XTAL25_OUT Y1 25MHZ B 8/26 A-->B modify change FP C312 18P/50V_4 PEG_B_CLKRQ# / GPIO56 Rb R328 R1111 *10K_4 10K_4 CLK_BUF_BCLK_N CLK_BUF_BCLK_P R556 R558 10K_4 10K_4 CLK_BUF_PCIE_3GPLL# CLK_BUF_PCIE_3GPLL CLK_BUF_DREFCLK# CLK_BUF_DREFCLK CLK_BUF_DREFSSCLK# CLK_BUF_DREFSSCLK CLK_PCH_14M R291 R295 R258 R262 R315 R314 R216 10K_4 10K_4 10K_4 10K_4 10K_4 10K_4 10K_4 CLKOUT_PCIE6N CLKOUT_PCIE6P XCLK_RCOMP PCIECLKRQ6# / GPIO45 (+3VS5) PCIECLKRQ7# / GPIO46 (+3VS5) CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P CougarPoint_Rev_0p7 fcbga989-intel-cougarpoint WLAN [27] CLK_PCIE_WLANP [27] PCIE_CLKREQ_WLAN# Y47 XCLK_RCOMP R502 K43 CLK_FLEX0 R211 22_4 F47 CLK_FLEX1 R205 22_4 (+3V) CLKOUT_PCIE7N CLKOUT_PCIE7P PCIE Clock [27] CLK_PCIE_WLANN CLKOUTFLEX0 / GPIO64 (+3V) CLKOUTFLEX1 / GPIO65 (+3V) CLKOUTFLEX2 / GPIO66 (+3V) CLKOUTFLEX3 / GPIO67 LAN [24] CLK_PCIE_LANN [24] CLK_PCIE_LANP [24] PCIE_CLKREQ_LAN# GPU [14] CLK_PCIE_VGA# [14] CLK_PCIE_VGA [14] PCIE_CLKREQ_VGA# [26] CLK_PCIE_USB3N [26] CLK_PCIE_USB3P K49 CLK_FLEX3 AJ0QMVY0T01 IC CTRL(989P)COUGARPOINT QMVY TOP B/S CLK_25M_USB3.0 [26] *22_4 C2002 10P/50V_4 TP2002 10/8 add for EMI Remove Ra, Rb for UMA & SG. 9/11 add R1015, exchange 27M net 27MHz support DIS only. 10/8 remove 27M circuit 3/26 DB change Part reference. RP7 1 0_4P2R_04 3 R621 2 CLK_PCH_SRC0N 4 CLK_PCH_SRC0P 0_4 CLK_PCIE_REQ0# RP6 3 0_4P2R_04 1 R637 RP5 2 0_4P2R_04 4 R345 RP8 2 0_4P2R_04 4 4 CLK_PCH_SRC2N 2 CLK_PCH_SRC2P 0_4 CLK_PCIE_REQ1# 1 CLK_PCH_PEGAN 3 CLK_PCH_PEGAP 0_4 CLK_PEGA_REQ# 1 3 SMBus/Pull-up(CLG) +3VS5 R333 1K_4 DRAMRST_CNTRL_PCH R282 R351 R337 R634 R292 R289 10K_4 2.2K_4 2.2K_4 2.2K_4 2.2K_4 10K_4 SMBALERT# SMB_PCH_CLK SMB_PCH_DAT SMB_ME0_CLK SMB_ME0_DAT SML1ALERT#_R [2,6,7,9,10,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39] +3V [2,6,7,9,10,14,24,29,31,33,35,36,38] +3VS5 2 A WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ CLK_PCH_PEGBN CLK_PCH_PEGBP 11/11 delete R359 3 +1.05V CLK_48M_CR [25] R3025 Rb 3/26 DB change Part reference. USB3.0 90.9/F_4 H47 CLK_FLEX2 3/26 DB change Part reference. CLOCK TERMINATION for FCIM 4 SMB_ME0_CLK (+3VS5) CLK_PCH_PEGBN CLK_PCH_PEGBP [27] INT_BT_COMBO_EN# CLK_PCIE_REQ0# CLK_PCIE_REQ3# CLK_PCIE_REQ4# Ra DRAMRST_CNTRL_PCH (+3VS5) +3VS5 CLK_PEGA_REQ# CLK_PEGB_REQ# modify R352 0_4 5 L12 A12 C8 (+3VS5) SML1ALERT# / PCHHOT# / GPIO74 (+3VS5) 2.2K_4 SMB_ME1_DAT SML0CLK (+3VS5) USB_BIAS SG : Rb ; UMA : Ra 2 4/29 PLTRST# A8 Card Reader PLTRST# U9 *TC7SH08FU V10 2.2K_4 +3VS5 (+3VS5) SML0ALERT# / GPIO60 (+3V) SMB_ME1_CLK Q51 2N7002 4 M1 Y37 Y36 CLK_REQ/Strap Pin(CLG) R586 SMB_PCH_DAT (+3VS5) AA48 AA47 WLAN CLK_PCIE_REQ1# CLK_PCIE_REQ2# 3 2 *0.1U/10V_4 1 PERN8 PERP8 PETN8 PETP8 Camera 10/10 R638 mount +3VS5 C406 BE38 BC38 AW38 AY38 V38 V37 2N7002 1 SMB_PCH_CLK C9 (+3V) 9/4 Change net name "BOARD_ID1" to "INT_BT_COMBO_EN#" SMBus/Pull-up(CLG) H14 SML0DATA PERN5 PERP5 PETN5 PETP5 PERN7 PERP7 PETN7 PETP7 CLK_PCIE_REQ0# Bios swap GPIO A14 K20 B17 C16 L16 A16 D14 C14 SMBCLK SML1CLK / GPIO58 BG40 BJ40 AY40 BB40 Y43 Y45 B33 SMBALERT# PEG_A_CLKRQ# / GPIO47 CLK_PCIE_REQ1# [21] [21] [27] [27] SMBALERT# / GPIO11 E12 SMBDATA PERN4 PERP4 PETN4 PETP4 PERN6 PERP6 PETN6 PETP6 Y40 Y39 HM65 Port6 & Port7 are disable TP1001 TP1002 USBP9USBP9+ USBP10USBP10+ (+3VS5) PERN3 PERP3 PETN3 PETP3 BJ38 BG38 AU36 AV36 CLK_PCH_SRC0N CLK_PCH_SRC0P C1012 18P/50V_4 +3V 3 0.1U/10V_4 0.1U/10V_4 BE34 BF34 BB32 AY32 AY5 BA2 C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32 USBRBIAS Q50 PLTRST# PCIE_RXN3_USB3 PCIE_RXP3_USB3 PCIE_TXN3_USB3 PCIE_TXP3_USB3 PME# [13,17,29] MBCLK2 PCI_PLTRST# C345 C353 PCIE_TXN1_C PCIE_TXP1_C AT8 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P GNT1# / GPIO51 (+3V) GNT2# / GPIO53 (+3V) GNT3# / GPIO55 (+3V) 4/20 modify A PCIE_RXN2_LAN PCIE_RXP2_LAN PCIE_TXN2_LAN PCIE_TXP2_LAN 0.1U/10V_4 0.1U/10V_4 8/26 A-->B modify PIRQA# PIRQB# PIRQC# PIRQD# 9/8 EMI(near PCH) PLTRST#(CLG) h^ϯ͘Ϭ [26] [26] [26] [26] C385 C379 AV10 CougarPoint_Rev_0p7 fcbga989-intel-cougarpoint AJ0QMVY0T01 IC CTRL(989P)COUGARPOINT QMVY TOP B/S 22_4 CLK_PCI_EC_R [24] [24] [24] [24] LAN AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 *22_4 CLK_PCI_LPC_R R225 [29] CLK_33M_KBC NV_RE#_WRB0 NV_RE#_WRB1 USB MPC Switch Control TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40 PCI BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30 WLAN PERN1 PERP1 PETN1 PETP1 2 RP12 AT10 BC8 BG34 BJ34 AV32 AU32 1 3/26 DB change Part reference. +3V NV_DQS0 NV_DQS1 PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1 Link D TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 [27] [27] [27] [27] SMBUS 8.2K_4 8.2K_4 8.2K_4 8.2K_4 AY7 AV7 AU3 BG4 Controller R198 R531 R234 R238 NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 FLEX CLOCKS +3V PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# Ϭϴ U24B NVRAM BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45 RSVD PCI/USBOC# Pull-up(CLG) 1 Cougar Point-M (PCI-E,SMBUS,CLK) U24E PCI-E* 11/8 change net name to "PCH_GPIO4" delete "DGPU_IDLE_INT#" pull-hi Eϱ Size Custom Document Number Rev A W,ϯͬϲ;ůŽĐŬͬW/ͬW/ ͬh^Ϳ Date: Monday, November 15, 2010 1 Sheet 8 of 40 5 4 3 ʹΠΦΘΒΣ͑ΠΚΟΥ͙͑ͺ͝·΄΄ΐͿʹ΅ͷ͝΄·͵͚ RF_PWR_OFF# 100_4 [7] ICC_EN# [27] Reserve TP1003 RF_OFF# [28] ODD_PRSNT# [14,29,37] DGPU_PWROK R627 *0_4 R676 0_4 8/26 A-->B modify [14,29] DGPU_HOLD_RST# R677 0_4 [7] PLL_ODVR_EN R618 0_4 R353 0_4 C [29] SATA5GP (+3V) A42 TACH1 / GPIO1 SIO_EXT_SCI# H36 TACH2 / GPIO6 BT_OFF# E38 TACH3 / GPIO7 ICC_EN# C10 GPIO8 (+3V) TACH5 / GPIO69 (+3V) (+3V) TACH6 / GPIO70 (+3V) (+3V) TACH7 / GPIO71 (+3V) LAN_PHY_PW R_CTRL / GPIO12 RF_OFF# G2 GPIO15 ODD_PRSNT#_R U2 (+3VS5) A20GATE (+3VS5) SATA4GP / GPIO16 (+3V) TACH0 / GPIO17 (+3V) BIOS_REC T5 SCLOCK / GPIO22 BOARD_ID5 E8 GPIO24 / MEM_LED (+3V) GPIO27 P8 GPIO28 BOARD_ID3 K1 STP_PCI# / GPIO34 BOARD_ID4 K4 PECI RCIN# GPIO24 GPIO69 R525 R524 1.5K/F_4 *1.5K/F_4 +3V C41 INIT3_3V# R3017 10K/F_4 3/26 DB del external clock generator. DGPU_OPT_DIS# 11/12 modify Delete net "GPIO70",connect DGPU optimus / discrete circuit SATA2GP / GPIO36 SATA3GP / GPIO37 MFG_MODE N2 EC_RCIN# P5 SLOAD / GPIO38 DGPU_PRSNT# M3 SDATAOUT0 / GPIO39 TEST_SET_UP V13 SDATAOUT1 / GPIO48 AK11 NC_3 AH10 NC_4 AK10 NC_5 P37 H_PWRGOOD [2] PCH_THRMTRIP# VSS_NCTF_15 BG2 V3 SATA5GP / GPIO49 SV_DET D6 GPIO57 390_4 MFG-TEST PM_THRMTRIP# [2,29] VSS_NCTF_16 BG48 VSS_NCTF_17 BH3 VSS_NCTF_18 BH47 VSS_NCTF_19 BJ4 (+3V) VSS_NCTF_1 A44 VSS_NCTF_2 VSS_NCTF_20 BJ44 A45 VSS_NCTF_3 VSS_NCTF_21 BJ45 VSS_NCTF_22 BJ46 VSS_NCTF_4 GPIO Pull-up/Pull-down(CLG) +3VS5 20101012 modify: MFG_MODE 1. Delete TACH0. 2. GPIO70 connect DGPU optimus / discrete setting. R626 10K_4 R601 LAN_DISABLE#_R R595 10K_4 SIO_EXT_SCI# SIO_EXT_SMI# BT_OFF# EC_A20GATE EC_RCIN# SATA5GP R228 R523 R512 R325 R355 R605 10K_4 10K_4 10K_4 10K_4 10K_4 10K_4 GPIO71 ODD_PRSNT#_R DGPU_PWROK R530 R642 R217 1.5K/F_4 10K_4 *10K_4 DGPU_PWROK GPIO27 R226 R296 *0_4 +3V 0_4 Bios swap GPIO 4/23. +3V DG rev0.9 suggest to TS_VSS connect to GND 4/23. (+3V) SATA5GP R311 +3V R307 (+3V) (+3V) D EC_RCIN# [29] T14 AH8 (+3V) R3018 *10K/F_4 EC_A20GATE [29] NC_2 (+3V) DGPU_OPT_DIS#: High : Optimus. Low: Discrete. AU16 NC_1 (+3V) V8 S_GPIO R365 R364 10K_4 *0_4 VSS_NCTF_5 VSS_NCTF_23 BJ5 A6 VSS_NCTF_6 VSS_NCTF_24 BJ6 B3 VSS_NCTF_7 VSS_NCTF_25 C2 VSS_NCTF_8 VSS_NCTF_26 BD1 VSS_NCTF_9 VSS_NCTF_27 D1 BD49 VSS_NCTF_10 VSS_NCTF_28 D49 BE1 VSS_NCTF_11 VSS_NCTF_29 E1 BE49 VSS_NCTF_12 VSS_NCTF_30 E49 BF1 VSS_NCTF_13 VSS_NCTF_31 F1 BF49 VSS_NCTF_14 VSS_NCTF_32 F49 C *10K_4 10K_4 4/29 modify 9/3 update net name from "DGPU_VC_EN" to "DGPU_PWROK" +3VS5 +3V RF_OFF# R596 1K_4 Intel ME Crypto Transport Layer Security (TLS) cipher suite BIOS_REC *0_4 BIOS RECOVERY R354 10K_4 High = Disable (Default) Low = Enable Low = Disable (Default) High = Enable C48 11/13 delete "GPIO70" and R528 10/10 double pull high R341 A5 B47 B GPIO71 P4 AY10 GPIO35 M5 GPIO36 5/11 stuff R9144 DGPU_OPT_DIS# A40 THRMTRIP# (+3V) FDI_OVRVLTG A46 DGPU_PWR_EN B41 AY11 (+3VS5) NCTF GPIO17 DGPU_HOLD_RST# +3V PROCPW RGD (+3VS5) DGPU_PWROK *10K_4 (DSW) DGPU_PWR_EN_R A4 R529 (+3VS5) E16 PLL_ODVR_EN_R OPTIMUS POWER control pin GPIO68 (+3V) C4 D40 C40 Ϭϵ Clock Gen Power OK (CLG) (+3VS5) LAN_DISABLE#_R GPIO27 [29,37,38] DGPU_PWR_EN TACH4 / GPIO68 CPU/MISC 9/3 delete net "BT_OFF#" BMBUSY# / GPIO0 SIO_EXT_SMI# 4/29 modify [29] SIO_EXT_SCI# D T7 GPIO [29] SIO_EXT_SMI# R363 1 +3V [27] 9/6 add "RF_PWR_OFF#" control from PCH U24F S_GPIO 2 +3V R339 *0_4 TEST_SET_UP R322 10K_4 +3VS5 R594 100K_4 SV_DET R619 SV_SET_UP TEST DETECT High = Strong (Default) Low = Default B *10K_4 CougarPoint_Rev_0p7 IC CTRL(989P)COUGARPOINT QMVY TOP B/S fcbga989-intel-cougarpoint AJ0QMVY0T01 10/11 no need pull high BOARD ID SETTING %RDUG,' /* ,' ,' ,' ,' DGPU_PWR_EN_R ,' /* &% 80$ 'LV 80$'LV 4/+7:+ 4/&6:+ A ,' 1 x 0 x 0 x <(6 12 0'& 12 <(6 'REO\ <(6 12 2SWLXPV 5 [8] BOARD_ID0 [8] BOARD_ID2 +3V R340 *200K/F_4 100K_4 FDI_OVRVLTG R342 *1K_4 BOARD_ID0 BOARD_ID2 9/6 delete net "BOARD_ID1" Low = Tx, Rx terminated to same voltage (DC Coupling Mode) (DEFAULT) DMI TERMINATION VOLTAGE OVERRIDE R632 *10K_4 BOARD_ID0 R631 10K_4 R356 *10K_4 BOARD_ID1 R357 *10K_4 R589 10K_4 BOARD_ID2 R609 *10K_4 R598 *10K_4 BOARD_ID3 R623 *10K_4 R622 10K_4 BOARD_ID4 R635 *10K_4 R348 *10K_4 BOARD_ID5 R349 *10K_4 FDI TERMINATION VOLTAGE OVERRIDE LOW - Tx, Rx terminated to same voltage +3VS5 A GFX Present +3V +3VS5 4/29 modify Rb R600 *100K_4 DGPU_PRSNT# +3V Ra R625 SG UMA Stuff Ra Rb NC Rb Ra 10K_4 [2,6,7,8,10,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39] [2,6,7,8,10,14,24,29,31,33,35,36,38] Eϱ 3 +3V +3VS5 WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ 10/11 correct board ID 4 +3V R326 2 Size Custom Document Number Rev A W,ϰͬϲ;'W/KͿ Date: Monday, November 15, 2010 1 Sheet 9 of 40 3 2 1 Cougar Point-M (POWER) V12 DCPSUSBYP *0.1U/10V_4 +3V_SUS_CLKF33 T38 10/8 remove for leakage *0_6/S +1.05V_VCCEPW R249 1.01A (60mils) 0.002/F_1206 AA21 VCCASW [2] AA24 VCCASW [3] AA26 VCCASW [4] AA27 VCCASW [5] AA29 C351 1U/6.3V_4 C369 1U/6.3V_4 C352 1U/6.3V_4 AA31 AC26 C C340 22U/6.3VS_8 C341 22U/6.3VS_8 11/12 short R335 +1.05V VCCASW [10] AC31 VCCASW [11] VCCASW [13] W 21 VCCASW [14] W 23 VCCASW [15] W 24 VCCASW [16] +VCCAFDI_VRM +1.05V_VCCA_A_DPL C542 1U/6.3V_4 R557 *0_6/S +VCCDIFFCLK +VCCDIFFCLKN 55mA (10mils) +V1.05V_SSCVCC *0_6 +VCCSST C384 0.1U/10V_4 +V1.05M_VCCSUS V_PROC_IO=1mA (10mils) A C617 0.1U/10V_4 T17 V19 C382 0.1U/10V_4 C375 0.1U/10V_4 119mA (20mils) C350 1U/6.3V_4 +3VS5 R267 VCCSUS3_3[9] V23 VCCSUS3_3[10] V24 USB +3V_VCCPUSB C361 1U/6.3V_4 *0_6/S C370 10U/6.3VS_6 VCCSUS3_3[6] P24 +3V_VCCAUBG VCCIO[34] T26 +VCCAUPLL R259 V5REF_SUS M26 VCCSUS3_3[1] V5REF *0_6/S +VCCA_USBSUS AN24 +3V_VCCPSUS +1.05V_PCH_VCCDPLL_EXP R274 +1.05V +1.05V_VCCAPLL_EXP L31 C604 *10U/6.3V_6 +1.05V BJ22 +1.05V_VCCIO R257 119mA (15mils) P20 +3V_VCCPSUS AN16 VCCIO[15] AN17 VCCIO[16] *0_6/S C330 1U/6.3V_4 +3VS5 C334 1U/6.3V_4 C366 1U/6.3V_4 AA16 VCC3_3[8] W 16 VCC3_3[4] T34 266mA (20mils) +3V_VCCPCORE +3V R332 *0_6/S C329 10U/6.3VS_6 +3V C403 0.1U/10V_4 AJ2 C356 1U/6.3V_4 +3V C344 1U/6.3V_4 +3V_VCC_EXP AN21 VCCIO[17] AN26 VCCIO[18] AN27 VCCIO[19] AP21 VCCIO[20] AP23 VCCIO[21] AP24 VCCIO[22] VCCIO[13] AH14 VCCIO[6] AF14 C600 0.1U/10V_4 +V1.05S_SATA3 R318 *0_8/S +1.05V C402 1U/6.3V_4 +VCCAFDI_VRM (Mobile 1.5V) +1.5V_CPU +1.05V AK1 +V1.1LAN_VCCAPLL AF11 +VCCAFDI_VRM L35 *10uH/100mA_8 R500 0_6 R501 *0_6 +1.05V +1.05V C652 *10U/6.3V_6 VCCIO[23] AT24 VCCIO[24] AN33 VCCIO[25] AC16 VCCIO[3] AC17 VCCIO[4] AD17 VCCASW [22] +1.05V_VCCIO1 R362 AN34 VCCIO[26] BH29 VCC3_3[3] +VCCAFDI_VRM AP16 VCCVRM[2] VccAFDIPLL R316 *0_8 BG6 R304 0_8 AP17 *0_6/S +1.05V VCCASW [21] T19 VCCSUSHDA CougarPoint_Rev_0p7 fcbga989-intel-cougarpoint AJ0QMVY0T01 IC CTRL(989P)COUGARPOINT QMVY TOP B/S VCCALVDS AK36 VSSALVDS AK37 5 +1.05V 65mA (10mils) *0_6 +3V 0_4 R562 *0_4 +VCC_TX_LVDS Ra L29 0.1uH/250mA_8 VCCTX_LVDS[1] AM37 VCCTX_LVDS[2] AM38 VCCTX_LVDS[3] AP36 R551 *0_4 VCCTX_LVDS[4] AP37 C584 22U/6.3VS_8 C581 0.01U/25V_4 C582 0.01U/25V_4 Rb +1.05V_VCCA_B_DPL L27 10uH/100MA_8 +V3.3A_1.5A_HDA_IO VCC3_3[7] V34 +1.8V R550 *0_4 R552 0_4 +1.5VSUS +3VS5 C333 0.1U/10V_4 42mA (10mils) AT16 VCCDMI[1] AT20 VCCCLKDMI AB36 C575 *1U/6.3V_4 *0_6 +3V_SUS_CLKF33 R537 1/F_4 +3V_SUS_CLKF33_R 3 +VCC_DMI_CCI R591 *1/F_4 R592 0_4 +1.05V R279 *0_4/S +1.1V_VCC_DMI_CCI C376 1U/6.3V_4 C619 *10U/6.3V_6 VCCPNAND[1] AG16 VCCPNAND[2] AG17 R317 VCCPNAND[3] AJ16 C401 0.1U/10V_4 VCCPNAND[4] AJ17 +VCCP_NAND +1.8V 11/12 short *0_8/S B 20mA (10mils) +3V_VCCME_SPI +3V R643 V1 *0_6/S C646 1U/6.3V_4 R241 10_4 +5V 1U/6.3V_4 *220U/2.5V_3528 D9 C332 1U/6.3V_4 V5REF= 1mA C586 RB500V-40 +3V 1U/6.3V_4 *220U/2.5V_3528 +5V_PCH_VCC5REFSUS VCC5REFSUS=1mA C568 1U/6.3V_4 C567 10U/6.3VS_6 L28 10uH/100MA_8 +1.05V +1.1V_VCC_DMI +VCCAFDI_VRM 20mA (10mils) R536 C *0_6/S VCCDMI[2] 5/14 modify +3V +3V R243 VCCVRM[3] VCCSPI C543 C576 C580 0.1U/10V_4 V33 8mA (10mils) 10mA (10mils) P32 VCC3_3[6] +5V_PCH_VCC5REF +1.05V_VCCA_A_DPL L25 10uH/100MA_8 [6,7,21,22,23,27,28,36] +5V [21,23,26,31,32,33,34,35,36,37,38,39,40] +5VS5 [2,6,7,8,9,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39] +3V [2,6,7,8,9,14,24,29,31,33,35,36,38] +3VS5 [6,7] +3V_DSW [6,7,29] +3V_RTC 4 0.01U/25V_4 R489 Rb +1.1V_VCC_DMI_CCI L33 *10uH/100mA_8 Eϱ 2 R560 D22 C589 0.1U/10V_4 10_4 +5VS5 RB500V-40 +3VS5 A WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ 20mA (10mils) [4,7,36,38] +1.8V [2,4,12,13,32,33,38] +1.5VSUS [6,7,8,35] +1.05V C524 R561 CougarPoint_Rev_0p7 fcbga989-intel-cougarpoint AJ0QMVY0T01 IC CTRL(989P)COUGARPOINT QMVY TOP B/S C540 V21 0.1U/10V_4 190 mA (15mils) VCCIO[27] AU20 +1.05V C412 1U/6.3V_4 T21 VCCASW [23] 10U/6.3VS_6 C525 +VCCALVDS C616 1U/6.3V_4 +1.05V_VCCDPLL_FDI +1.05V_VCCEPW DCPSUS[1] DCPSUS[2] D C523 +3V_VCC_GIO +1.05V_VCCAPLL_FDI DCPSST HCB1608KF-181T15/1.5A_6 1mA (10mils) 160mA (15mils) AF13 AH13 AP26 0_8 +3V C338 0.1U/10V_4 VCCIO[2] U47 +3V L24 1mA (10mils) SG & UMA : Ra DIS : Rb 0.002/F_1206 R290 P22 VCC3_3[1] VCCVRM[1] VSSADAC VCCAPLLEXP 2.925 A (140mils) N20 N22 VCCAPLLSATA U48 +5V_PCH_VCC5REF P34 VCCSUS3_3[4] VCCIO[5] VCCIO[28] *1uH/25mA_6 VCCSUS3_3[3] VCCSUS3_3[5] VCCADAC Ra *1U/6.3V_4 11/12 short VCCSUS3_3[2] AN19 ϭϬ +VCCA_DAC_1_2 +3V_LDO VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17] *0_6/S +1.05V C365 AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31 +3V_LDO 1 Vout 60mA (10mils) R564 VCCADPLLB VCCRTC +1.05V +5V_PCH_VCC5REFSUS AN23 C349 1U/6.3V_4 *0_6/S C346 0.1U/10V_4 VCC3_3[2] VCCADPLLA V_PROC_IO C360 0.1U/10V_4 R264 1.01A (60mils) A22 C386 1U/6.3V_4 T24 VCCIO[12] VCCSSC C613 0.1U/10V_4 +3V_RTC VCCRTC<1mA (10mils) T23 VCCSUS3_3[8] VCCVRM[4] AG33 BJ8 C621 4.7U/6.3V_6 VCCSUS3_3[7] DCPRTC VCCIO[7] VCCDIFFCLKN[1] VCCDIFFCLKN[2] VCCDIFFCLKN[3] V16 0.002/F_1206 C400 0.1U/10V_4 +VTT_VCCPCPU *0_4/S short0402 T29 VCCASW [20] AF17 AF33 AF34 AG34 95mA (10mils) C374 *1U/6.3V_4 +1.05V R588 BF47 8mA (10mils) C592 1U/6.3V_4 R293 BD47 65mA (10mils) +1.05V_VCCA_B_DPL +1.05V VCCASW [19] 160mA (20mils) B +1.05V VCCASW [18] W 31 Y49 T27 VCCIO[33] C571 1U/6.3V_4 VCCASW [17] W 29 +VCCRTCEXT N16 C388 0.1U/10V_4 *0_6/S VCCASW [12] AD31 W 33 R504 VCCASW [8] VCCASW [9] *0_6/S C407 1U/6.3V_4 VCCASW [7] AC29 W 26 +1.05V VCCASW [6] AC27 AD29 VCCIO[32] DCPSUS[4] CPU +1.05V P28 VCCASW [1] RTC R569 AA19 PCI/GPIO/LPC C367 *1U/6.3V_4 +1.05V DCPSUS[3] SATA AL24 C603 *10U/6.3V_6 VCCIO[14] MISC +VCCSUS1 *10uH/100mA_8 AL29 HDA +VCCDPLL_CPY L30 VCCIO[31] VCCAPLLDMI2 Clock and Miscellaneous BH23 +VCCAPLL_CPY_PCH P26 VCC3_3[5] 4/29: modify +1.05V VCCIO[30] CRT PCH_VCCDSW C383 0.1U/10V_4 VCCIO[29] VCCDSW 3_3 LVDS 5/12: modify VCCACLK U24G HVCMOS 3mA (10mils) C408 D T16 +1.05V_PCH_VCC R301 DMI +VCCPDSW +1.05V *0_8/S NAND / SPI *0_4 R543 VCCIO 0_4 R288 N26 Vin C3009 *1U/6.3V_4 FDI R283 AD49 3 COUGAR POINT (POWER) 1.3 A (60mils) + +3VS5 +VCCACLK +3V_DSW +1.05V *0_8 + R508 VCC CORE +1.05V_VCCUSBCORE U24J +1.05V U3001 *G910T21U +5V 11/12 add for CRT wave noise GND 4 2 5 Size Custom Document Number Rev A W,ϱͬϲ;WŽǁĞƌͿ Date: Monday, November 15, 2010 1 Sheet 10 of 40 5 4 3 IBEX PEAK-M (GND) 2 1 ϭϭ IBEX PEAK-M (GND) U24I U24H AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3 D C B A VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W 34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W 17 W 19 W2 W 27 W 48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28 H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3 VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW 14 AW 18 AW 2 AW 22 AW 26 AW 28 AW 32 AW 34 AW 36 AW 40 AW 48 AV11 AY12 AY22 AY28 D C B CougarPoint_Rev_0p7 A WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ CougarPoint_Rev_0p7 Eϱ 5 4 3 2 Size Custom Document Number Rev A W,ϲͬϲ;'ƌŽƵŶĚͿ Date: Monday, November 15, 2010 1 Sheet 11 of 40 4 D R160 R164 10K_4 10K_4 [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CS#0 M_A_CS#1 M_A_CLKP0 M_A_CLKN0 M_A_CLKP1 M_A_CLKN1 M_A_CKE0 M_A_CKE1 M_A_CAS# M_A_RAS# M_A_WE# [8,13] SMB_RUN_CLK [8,13] SMB_RUN_DAT [3] [3] 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15 DIMM0_SA0 DIMM0_SA1 SMB_RUN_CLK SMB_RUN_DAT 109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200 BA0 BA1 BA2 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# W E# SA0 SA1 SCL SDA 116 120 ODT0 ODT1 M_A_DM2 11 28 46 63 136 153 170 187 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7 M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7 12 29 47 64 137 154 171 188 10 27 45 62 135 152 169 186 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7 M_A_ODT0 M_A_ODT1 M_A_DM1 C [3] M_A_DQSP[7:0] [3] M_A_DQSN[7:0] 2 M_A_DQ[63:0] [3] JDIM1A M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 PC2100 DDR3 SDRAM SO-DIMM (204P) [3] M_A_A[15:0] 3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 M_A_DQ4 M_A_DQ5 M_A_DQ7 M_A_DQ6 M_A_DQ1 M_A_DQ0 M_A_DQ3 M_A_DQ2 M_A_DQ9 M_A_DQ8 M_A_DQ15 M_A_DQ10 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ11 M_A_DQ21 M_A_DQ16 M_A_DQ19 M_A_DQ18 M_A_DQ20 M_A_DQ17 M_A_DQ23 M_A_DQ22 M_A_DQ25 M_A_DQ24 M_A_DQ30 M_A_DQ26 M_A_DQ28 M_A_DQ29 M_A_DQ31 M_A_DQ27 M_A_DQ36 M_A_DQ37 M_A_DQ34 M_A_DQ38 M_A_DQ32 M_A_DQ33 M_A_DQ35 M_A_DQ39 M_A_DQ41 M_A_DQ45 M_A_DQ47 M_A_DQ46 M_A_DQ40 M_A_DQ44 M_A_DQ42 M_A_DQ43 M_A_DQ49 M_A_DQ48 M_A_DQ54 M_A_DQ55 M_A_DQ53 M_A_DQ52 M_A_DQ50 M_A_DQ51 M_A_DQ61 M_A_DQ60 M_A_DQ62 M_A_DQ63 M_A_DQ56 M_A_DQ57 M_A_DQ59 M_A_DQ58 1 JDIM1B 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 199 VDDSPD 77 122 125 NC1 NC2 NCTEST PM_EXTTS#0 198 30 EVENT# RESET# +SMDDR_VREF_DQ0 +SMDDR_VREF_DIMM 1 126 VREF_DQ VREF_CA +3V +3V R177 [13] PM_EXTTS#0 [2,13] DDR3_DRAMRST# SMDDR_VREF_DQ0_M1 R36 SMDDR_VREF_DQ0_M3 R32 [5] SMDDR_VREF_DQ0_M3 0_6 *0_6 ϭϮ +1.5VSUS 2.48A 10K_4 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 PC2100 DDR3 SDRAM SO-DIMM (204P) 5 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 D C VTT1 VTT2 203 204 GND GND 205 206 +0.75V_DDR_VTT DDR3-DIMM0_H=5.2_RVS DDR-78279-001-RVS-204P DGMK4000125 IC SOCKET DDRIII SO-DIMM(204P,H5.2,RVS) DDR3-DIMM0_H=5.2_RVS DDR-78279-001-RVS-204P DGMK4000125 IC SOCKET DDRIII SO-DIMM(204P,H5.2,RVS) B B +1.5VSUS Place these Caps near So-Dimm0. +1.5VSUS ZĞŵŽǀĞDϮ^ŽůƵƚŝŽŶ;/ŶƚĞůϰϯϲϵϵϲŽĐͿ A VREF DQ0 M1 Solution +0.75V_DDR_VTT C126 1U/6.3V_4 C287 1U/6.3V_4 C171 1U/6.3V_4 C288 1U/6.3V_4 C177 1U/6.3V_4 C286 1U/6.3V_4 C163 1U/6.3V_4 C285 1U/6.3V_4 C155 10U/6.3VS_6 C284 10U/6.3V_6 C139 10U/6.3VS_6 C289 *10U/6.3V_6 C119 10U/6.3VS_6 C124 10U/6.3VS_6 C61 10U/6.3VS_6 C123 10U/6.3VS_6 C146 *10U/6.3V_6 C140 10U/6.3V_8 C149 10U/6.3V_8 R34 1K/F_4 DDR_VTTREF +1.5VSUS SMDDR_VREF_DQ0_M1 R115 10K_4 R35 1K/F_4 [4,13,32] DDR_VTTREF R119 +SMDDR_VREF_DIMM *0_6 R111 10K_4 C181 0.1U/10V_4 C164 2.2U/6.3V_6 +SMDDR_VREF_DQ0 C26 0.1U/10V_4 C23 2.2U/6.3V_6 C273 0.1U/10V_4 C265 2.2U/6.3V_6 A WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ 4/27: layout modify 3 C180 470P/50V_4 [2,6,7,8,9,10,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39] +3V [6,7,21,27,28,29,30,31] +3VPCU [2,4,10,13,32,33,38] +1.5VSUS [13,32,36] +0.75V_DDR_VTT +3V 11/13 delete C513 4 *0_6 +SMDDR_VREF_DIMM 8/31 C513 FP changed from 330U_2.5V_5.0x5.9ESR10m to 220U/6.3V_6x4.5ESR18 5 R33 Eϱ 2 Size Custom Document Number Rev A ^LJƐƚĞŵDĞŵŽƌLJϭͬϮ;ϱ͘Ϯ,Ϳ Date: Monday, November 15, 2010 1 Sheet 12 of 40 4 10K_4 10K_4 M_B_BS#0 M_B_BS#1 M_B_BS#2 M_B_CS#0 M_B_CS#1 M_B_CLKP0 M_B_CLKN0 M_B_CLKP1 M_B_CLKN1 M_B_CKE0 M_B_CKE1 M_B_CAS# M_B_RAS# M_B_WE# 109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200 BA0 BA1 BA2 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# W E# SA0 SA1 SCL SDA 116 120 ODT0 ODT1 M_B_DM2 11 28 46 63 136 153 170 187 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 M_B_DQSP0 M_B_DQSP1 M_B_DQSP2 M_B_DQSP3 M_B_DQSP4 M_B_DQSP5 M_B_DQSP6 M_B_DQSP7 M_B_DQSN0 M_B_DQSN1 M_B_DQSN2 M_B_DQSN3 M_B_DQSN4 M_B_DQSN5 M_B_DQSN6 M_B_DQSN7 12 29 47 64 137 154 171 188 10 27 45 62 135 152 169 186 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7 DIMM1_SA0 DIMM1_SA1 [8,12] SMB_RUN_CLK [8,12] SMB_RUN_DAT [3] [3] M_B_ODT0 M_B_ODT1 C M_B_DM1 [3] M_B_DQSP[7:0] [3] M_B_DQSN[7:0] DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 M_B_DQ5 M_B_DQ4 M_B_DQ3 M_B_DQ2 M_B_DQ0 M_B_DQ1 M_B_DQ6 M_B_DQ7 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ10 M_B_DQ8 M_B_DQ9 M_B_DQ11 M_B_DQ15 M_B_DQ20 M_B_DQ21 M_B_DQ18 M_B_DQ22 M_B_DQ17 M_B_DQ16 M_B_DQ19 M_B_DQ23 M_B_DQ25 M_B_DQ29 M_B_DQ27 M_B_DQ26 M_B_DQ28 M_B_DQ24 M_B_DQ31 M_B_DQ30 M_B_DQ36 M_B_DQ37 M_B_DQ35 M_B_DQ34 M_B_DQ33 M_B_DQ32 M_B_DQ39 M_B_DQ38 M_B_DQ44 M_B_DQ40 M_B_DQ42 M_B_DQ43 M_B_DQ45 M_B_DQ41 M_B_DQ46 M_B_DQ47 M_B_DQ49 M_B_DQ48 M_B_DQ54 M_B_DQ55 M_B_DQ52 M_B_DQ53 M_B_DQ50 M_B_DQ51 M_B_DQ61 M_B_DQ56 M_B_DQ62 M_B_DQ63 M_B_DQ57 M_B_DQ60 M_B_DQ59 M_B_DQ58 JDIM2B 2.48A 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 +3V 199 VDDSPD 77 122 125 NC1 NC2 NCTEST PM_EXTTS#0 198 30 EVENT# RESET# +SMDDR_VREF_DQ1 1 126 VREF_DQ VREF_CA 10/10 double pull high R175 +3V *10K_4 [2,12] DDR3_DRAMRST# SMDDR_VREF_DQ1_M1 R38 SMDDR_VREF_DQ1_M3 R37 [5] SMDDR_VREF_DQ1_M3 0_6 *0_6 +SMDDR_VREF_DIMM 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 D C VTT1 VTT2 203 204 GND GND 205 206 +0.75V_DDR_VTT DDR3-DIMM1_H=9.2_RVS DDR-AS0A626-UARN-7F-204P DGMK4000126 IC SOCKET DDRIII SO-DIMM(204P,H9.2,RVS) DDR3 Thermal Sensor 10/13 remove U23 [8,17,29] MBCLK2 DDR3-DIMM1_H=9.2_RVS DDR-AS0A626-UARN-7F-204P DGMK4000126 IC SOCKET DDRIII SO-DIMM(204P,H9.2,RVS) B ϭϯ +1.5VSUS [8,17,29] MBDATA2 [12] PM_EXTTS#0 C577 MBCLK2 8 SCLK VCC 1 MBDATA2 7 SDA DXP 2 PM_EXTTS#0 6 ALERT# DXN 3 PM_EXTTS#0_EC 4 OVERT# GND 5 *0.01U/25V_4 +3V DDR_THERMDA 3 +3V R174 R176 [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15 1 C588 *2200P/50V_4 R555 +3V *10K_4 B *G780P81U VREF DQ1 M1 Solution Place these Caps near So-Dimm1. +1.5VSUS ZĞŵŽǀĞDϮ^ŽůƵƚŝŽŶ;/ŶƚĞůϰϯϲϵϵϲŽĐͿ +0.75V_DDR_VTT +1.5VSUS A +SMDDR_VREF_DIMM C170 1U/6.3V_4 C281 1U/6.3V_4 C200 0.1U/10V_4 C87 1U/6.3V_4 C282 1U/6.3V_4 C191 2.2U/6.3V_6 C184 1U/6.3V_4 C280 1U/6.3V_4 C159 1U/6.3V_4 C283 1U/6.3V_4 C113 10U/6.3VS_6 C290 10U/6.3V_6 C30 0.1U/10V_4 C182 10U/6.3VS_6 C279 *10U/6.3V_6 C27 2.2U/6.3V_6 C122 10U/6.3VS_6 C102 10U/6.3VS_6 C154 10U/6.3VS_6 C264 0.1U/10V_4 C145 10U/6.3VS_6 C278 2.2U/6.3V_6 C174 *10U/6.3V_6 C103 10U/6.3V_8 C133 10U/6.3V_8 R28 1K/F_4 [4,12,32] DDR_VTTREF 4 3 R30 SMDDR_VREF_DQ1_M1 *0_6 +SMDDR_VREF_DQ1 +3V R29 1K/F_4 A [2,6,7,8,9,10,12,14,21,22,23,24,25,26,27,28,29,34,36,37,39] +3V [6,7,21,27,28,29,30,31] +3VPCU [2,4,10,12,32,33,38] +1.5VSUS [12,32,36] +0.75V_DDR_VTT WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ Eϱ 5 Q47 *MMBT3904-7-F 2 DDR_THERMDC 1 D 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 2 M_B_DQ[63:0] [3] JDIM2A M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 PC2100 DDR3 SDRAM SO-DIMM (204P) [3] M_B_A[15:0] 3 PC2100 DDR3 SDRAM SO-DIMM (204P) 5 2 Size Custom Document Number Rev A ^LJƐƚĞŵDĞŵŽƌLJϮͬϮ;ϵ͘Ϯ,Ϳ Date: Monday, November 15, 2010 1 Sheet 13 of 40 4 5 ϱϬϬŵ 22U/6.3V_8 10U/6.3V_6 4.7U/6.3V_6 1U/6.3V_4 1U/6.3V_4 0.1U/10V_4 0.1U/10V_4 ϭϲϬϬŵ A +1.05V_GFX C115 C131 C129 C231 C212 C100 C199 C236 C89 C88 C98 C104 +3V_GFX C91 C194 C185 C201 C99 B +3V_GFX 22U/6.3V_8 10U/6.3V_6 4.7U/6.3V_6 1U/6.3V_4 1U/6.3V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 D U17A AK16 AK17 AK21 AK24 AK27 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 AG11 AG12 AG13 AG15 AG16 AG17 AG18 AG22 AG23 AG24 AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22 AJ24 AJ25 AJ27 AK18 AK20 AK23 AK26 AL16 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14 PEX_IOVDDQ_15 PEX_IOVDDQ_16 PEX_IOVDDQ_17 PEX_IOVDDQ_18 PEX_IOVDDQ_19 PEX_IOVDDQ_20 PEX_IOVDDQ_21 PEX_IOVDDQ_22 PEX_IOVDDQ_23 PEX_IOVDDQ_24 PEX_IOVDDQ_25 PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N AP17 AN17 AN19 AP19 AR19 AR20 AP20 AN20 AN22 AP22 AR22 AR23 AP23 AN23 AN25 AP25 AR25 AR26 AP26 AN26 AN28 AP28 AR28 AR29 AP29 AN29 AN31 AP31 AR31 AR32 AR34 AP34 PEG_TX15 PEG_TX#15 PEG_TX14 PEG_TX#14 PEG_TX13 PEG_TX#13 PEG_TX12 PEG_TX#12 PEG_TX11 PEG_TX#11 PEG_TX10 PEG_TX#10 PEG_TX9 PEG_TX#9 PEG_TX8 PEG_TX#8 PEG_TX7 PEG_TX#7 PEG_TX6 PEG_TX#6 PEG_TX5 PEG_TX#5 PEG_TX4 PEG_TX#4 PEG_TX3 PEG_TX#3 PEG_TX2 PEG_TX#2 PEG_TX1 PEG_TX#1 PEG_TX0 PEG_TX#0 PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N AL17 AM17 AM18 AM19 AL19 AK19 AL20 AM20 AM21 AM22 AL22 AK22 AL23 AM23 AM24 AM25 AL25 AK25 AL26 AM26 AM27 AM28 AL28 AK28 AK29 AL29 AM29 AM30 AM31 AM32 AN32 AP32 C_PEG_RX15 C_PEG_RX#15 C_PEG_RX14 C_PEG_RX#14 C_PEG_RX13 C_PEG_RX#13 C_PEG_RX12 C_PEG_RX#12 C_PEG_RX11 C_PEG_RX#11 C_PEG_RX10 C_PEG_RX#10 C_PEG_RX9 C_PEG_RX#9 C_PEG_RX8 C_PEG_RX#8 C_PEG_RX7 C_PEG_RX#7 C_PEG_RX6 C_PEG_RX#6 C_PEG_RX5 C_PEG_RX#5 C_PEG_RX4 C_PEG_RX#4 C_PEG_RX3 C_PEG_RX#3 C_PEG_RX2 C_PEG_RX#2 C_PEG_RX1 C_PEG_RX#1 C_PEG_RX0 C_PEG_RX#0 PEX_REFCLK PEX_REFCLK_N AR16 AR17 CLK_PCIE_VGA CLK_PCIE_VGA# PEX_TSTCLK_OUT PEX_TSTCLK_OUT_N AJ17 AJ18 PEX_TSTCLK PEX_TSTCLK# R110 *200_4 AM16 VGA_RST# R108 0_4 PEX_CLKREQ_N AR13 PEX_CLKREQ# R436 10K/F_4 PEX_TERMP (NC) PEX_TERMP AG21 AH21 PEX_TERMP R107 *0_4/S R106 2.49K/F_4 TESTMODE AP35 TESTMODE R482 10K/F_4 W '/ŶƚĞƌĨĂĐĞ 4.7U/6.3V_6 1U/6.3V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 J9 J10 J11 J12 J13 L10 0_6 C132 4.7U/6.3V_6 C224 0.1U/10V_4 C128 0.01U/16V_4 AG19 F7 PEX_SVDD_3V3_2 PEX_SVDD_3V3_NC AA4 AA8 AA28 AB4 AB5 AB7 AC5 AD6 AD28 AD29 AE29 AF6 AG6 AG29 AH12 AH24 AH25 AH26 AH29 AJ5 AK15 AL7 A2 C5 E7 G11 G12 G14 G15 G24 G25 G27 G28 H10 H11 H12 H15 H21 H24 H25 H26 H32 J25 J26 L8 L29 M29 P6 P29 R28 R29 U7 V6 Y4 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 NC_43 NC_44 NC_45 NC_46 NC_47 NC_48 NC_49 NC_50 NC_51 NC_52 NC_53 NC_54 ϭϮΕϭϲŵŝůƐǁŝĚƚŚ C 11/10 add VDD33_1 VDD33_2 VDD33_3 VDD33_4 VDD33_5 PEX_RST_N PEG_TX15 [2] PEG_TX#15 [2] PEG_TX14 [2] PEG_TX#14 [2] PEG_TX13 [2] PEG_TX#13 [2] PEG_TX12 [2] PEG_TX#12 [2] PEG_TX11 [2] PEG_TX#11 [2] PEG_TX10 [2] PEG_TX#10 [2] PEG_TX9 [2] PEG_TX#9 [2] PEG_TX8 [2] PEG_TX#8 [2] PEG_TX7 [2] PEG_TX#7 [2] PEG_TX6 [2] PEG_TX#6 [2] PEG_TX5 [2] PEG_TX#5 [2] PEG_TX4 [2] PEG_TX#4 [2] PEG_TX3 [2] PEG_TX#3 [2] PEG_TX2 [2] PEG_TX#2 [2] PEG_TX1 [2] PEG_TX#1 [2] PEG_TX0 [2] PEG_TX#0 [2] C161 C175 C162 C176 C195 C187 C196 C188 C202 C210 C211 C203 C222 C215 C223 C216 C229 C226 C227 C230 C233 C238 C234 C239 C247 C250 C248 C251 C259 C263 C257 C254 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 +3V_GFX +3V_GFX R433 R430 10K/F_4 R441 *10K/F_4 R429 0_4 [9,29,37] DGPU_PW ROK PEX_CLKREQ# [8] ϭϰ Q35 *DTC144EUA 2 A +3V For Discrete [2,8,24,26,27,29] R81 0_4 PLTRST# C143 0.1U/10V_4 2 4 [9,29] DGPU_HOLD_RST# PEGX_RST# 1 U5 MC74VHC1G08DFT2G R109 100K/F_4 R98 *0_4 PEG_RX15 [2] PEG_RX#15 [2] PEG_RX14 [2] PEG_RX#14 [2] PEG_RX13 [2] PEG_RX#13 [2] PEG_RX12 [2] PEG_RX#12 [2] PEG_RX11 [2] PEG_RX#11 [2] PEG_RX10 [2] PEG_RX#10 [2] PEG_RX9 [2] PEG_RX#9 [2] PEG_RX8 [2] PEG_RX#8 [2] PEG_RX7 [2] PEG_RX#7 [2] PEG_RX6 [2] PEG_RX#6 [2] PEG_RX5 [2] PEG_RX#5 [2] PEG_RX4 [2] PEG_RX#4 [2] PEG_RX3 [2] PEG_RX#3 [2] PEG_RX2 [2] PEG_RX#2 [2] PEG_RX1 [2] PEG_RX#1 [2] PEG_RX0 [2] PEG_RX#0 [2] B NVVDD Settling Time C CLK_PCIE_VGA [8] CLK_PCIE_VGA# [8] PEGX_RST# +3V_GFX 3(;B567WLPLQJ L9 PBY160808T-301Y-N_6 C106 4.7U/6.3V_6 C111 1U/6.3V_4 C110 0.1U/10V_4 PEX_PLLVDD PEX_PLLVDD (NC) PEX_PLL_HVDD_NC AG14 AH15 AG20 VDD_SENSE_1 VDD_SENSE_2 VDD_SENSE_3 AD20 D35 P7 VGPU_CORE_SENSE GND_SENSE_1 GND_SENSE_2 GND_SENSE_3 AD19 E35 R7 VSS_GPU_SENSE [37] *0_4/S Power Sequence +3VS5 Q34 DTC144EUA 2 11/12 short R122 10K/F_4 PCIE_CLKREQ_VGA# 1 C114 C186 C130 C112 C60 C59 C217 8 5 +1.05V_GFX 7 3 For Discrete 6 1 3 3 2 3 1 I/O 3.3V +1.05V_GFX ϭϭϬŵ ϭϮΕϭϲŵŝůƐǁŝĚƚŚ 10/12 for N12E PEX_RST D [37] Trise >= 1uS Tfail <=500nS WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ N12x N12P AJ0N12P0T04 1 2 [15,16,37,38] +1.05V_GFX [16,17,22,37,38] +3V_GFX 3 4 5 6 Size A3 Eϱ Document Number 7 Rev A 'Whϭͬϱ;W 'Ϳ Date: Monday, November 15, 2010 Sheet 8 14 of 40 1 2 3 4 5 6 7 8 ϭϱ U17B A [19] FBA_CMD[30:0] B [19] VMA_DM[7:0] [19] VMA_W DQS[7:0] [19] VMA_RDQS[7:0] C U30 V30 U31 V32 T35 U33 W32 W33 W31 W34 U34 U35 U32 T34 T33 W30 AB30 AA30 AB31 AA32 AB33 Y32 Y33 AB34 AB35 Y35 W35 Y34 Y31 Y30 W29 Y29 FBA_CMD0 (FBA_CMD25) FBA_CMD1 (FBA_CMD23) D DKZz/ͬ& FBA_CMD2 FBA_CMD3 (FBA_CMD0) FBA_CMD4 (FBA_CMD10) FBA_CMD5 (FBA_CMD26) FBA_CMD6 (FBA_CMD14) FBA_CMD7 FBA_CMD8 (FBA_CMD1) FBA_CMD9 (FBA_CMD22) FBA_CMD10 (FBA_CMD20) FBA_CMD11 (FBA_CMD24) FBA_CMD12 (FBA_CMD18) FBA_CMD13 (FBA_CMD9) FBA_CMD14 (FBA_CMD29) FBA_CMD15 (FBA_CMD8) FBA_CMD16 (FBA_CMD27) FBA_CMD17 (FBA_CMD15) FBA_CMD18 (FBA_CMD11) FBA_CMD19 (FBA_CMD16) FBA_CMD20 (FBA_CMD28) FBA_CMD21 (FBA_CMD3) FBA_CMD22 (FBA_CMD17) FBA_CMD23 (FBA_CMD5) FBA_CMD24 (FBA_CMD4) FBA_CMD25 (FBA_CMD21) FBA_CMD26 (FBA_CMD6) FBA_CMD27 (FBA_CMD13) FBA_CMD28 (FBA_CMD19) FBA_CMD29 (FBA_CMD12) FBA_CMD30 FBA_CMD31 (NC) VMA_DM0 VMA_DM1 VMA_DM2 VMA_DM3 VMA_DM4 VMA_DM5 VMA_DM6 VMA_DM7 P32 H34 J30 P30 AF32 AL32 AL34 AF35 FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 VMA_W DQS0 VMA_W DQS1 VMA_W DQS2 VMA_W DQS3 VMA_W DQS4 VMA_W DQS5 VMA_W DQS6 VMA_W DQS7 L34 H35 J32 N31 AE31 AJ32 AJ34 AC33 FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 VMA_RDQS0 VMA_RDQS1 VMA_RDQS2 VMA_RDQS3 VMA_RDQS4 VMA_RDQS5 VMA_RDQS6 VMA_RDQS7 L35 G35 H31 N32 AD32 AJ31 AJ35 AC34 FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7 AA27 AA29 AA31 AB27 AB29 AC27 AD27 AE27 AJ28 B18 E21 G17 G18 G22 G8 G9 H29 J14 J15 FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 +1.5V_GFX C256 C243 C240 C205 C218 C235 C246 C314 C241 C317 C245 C244 U17C FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 4.7U/6.3V_6 4.7U/6.3V_6 1U/6.3V_4 1U/6.3V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 FBA_D00 FBA_D01 FBA_D02 FBA_D03 FBA_D04 FBA_D05 FBA_D06 FBA_D07 FBA_D08 FBA_D09 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 L32 N33 L33 N34 N35 P35 P33 P34 K35 K33 K34 H33 G34 G33 E34 E33 G31 F30 G30 G32 K30 K32 H30 K31 L31 L30 M32 N30 M30 P31 R32 R30 AG30 AG32 AH31 AF31 AF30 AE30 AC32 AD30 AN33 AL31 AM33 AL33 AK30 AK32 AJ30 AH30 AH33 AH35 AH34 AH32 AJ33 AL35 AM34 AM35 AF33 AE32 AF34 AE35 AE34 AE33 AB32 AC35 VMA_DQ0 VMA_DQ1 VMA_DQ2 VMA_DQ3 VMA_DQ4 VMA_DQ5 VMA_DQ6 VMA_DQ7 VMA_DQ8 VMA_DQ9 VMA_DQ10 VMA_DQ11 VMA_DQ12 VMA_DQ13 VMA_DQ14 VMA_DQ15 VMA_DQ16 VMA_DQ17 VMA_DQ18 VMA_DQ19 VMA_DQ20 VMA_DQ21 VMA_DQ22 VMA_DQ23 VMA_DQ24 VMA_DQ25 VMA_DQ26 VMA_DQ27 VMA_DQ28 VMA_DQ29 VMA_DQ30 VMA_DQ31 VMA_DQ32 VMA_DQ33 VMA_DQ34 VMA_DQ35 VMA_DQ36 VMA_DQ37 VMA_DQ38 VMA_DQ39 VMA_DQ40 VMA_DQ41 VMA_DQ42 VMA_DQ43 VMA_DQ44 VMA_DQ45 VMA_DQ46 VMA_DQ47 VMA_DQ48 VMA_DQ49 VMA_DQ50 VMA_DQ51 VMA_DQ52 VMA_DQ53 VMA_DQ54 VMA_DQ55 VMA_DQ56 VMA_DQ57 VMA_DQ58 VMA_DQ59 VMA_DQ60 VMA_DQ61 VMA_DQ62 VMA_DQ63 FBA_CLK0 FBA_CLK0_N FBA_CLK1 FBA_CLK1_N T32 T31 AC31 AC30 VMA_CLK0 VMA_CLK0# VMA_CLK1 VMA_CLK1# (FBA_DEBUG) FBA_DEBUG0 (NC) FBA_DEBUG1 FB_VREF_NC [20] FBC_CMD[30:0] [20] VMC_DM[7:0] [20] VMC_W DQS[7:0] [20] VMC_RDQS[7:0] FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8 FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28 FBC_CMD29 FBC_CMD30 F18 E19 D18 C17 F19 C19 B17 E20 B19 D20 A19 D19 C20 F20 B20 G21 F22 F24 F23 C25 C23 F21 E22 D21 A23 D22 B23 C22 B22 A22 A20 G20 FBB_CMD0 (FBC_CMD25) FBB_CMD1 (FBC_CMD23) FBC_CMD2 FBB_CMD3 (FBC_CMD0) FBB_CMD4 (FBC_CMD10) FBB_CMD5 (FBC_CMD26) FBB_CMD6 (FBC_CMD14) FBC_CMD7 FBB_CMD8 (FBC_CMD1) FBB_CMD9 (FBC_CMD22) FBB_CMD10 (FBC_CMD20) FBB_CMD11 (FBC_CMD24) FBB_CMD12 (FBC_CMD18) FBB_CMD13 (FBC_CMD9) FBB_CMD14 (FBC_CMD29) FBB_CMD15 (FBC_CMD8) FBB_CMD16 (FBC_CMD27) FBB_CMD17 (FBC_CMD15) FBB_CMD18 (FBC_CMD11) FBB_CMD19 (FBC_CMD16) FBB_CMD20 (FBC_CMD28) FBB_CMD21 (FBC_CMD3) FBB_CMD22 (FBC_CMD17) FBB_CMD23 (FBC_CMD5) FBB_CMD24(FBC_CMD4) FBB_CMD25 (FBC_CMD21) FBB_CMD26 (FBC_CMD6) FBB_CMD27 (FBC_CMD13) FBB_CMD28 (FBC_CMD19) FBB_CMD29 (FBC_CMD12) FBC_CMD30 FBC_CMD31 (NC) VMC_DM0 VMC_DM1 VMC_DM2 VMC_DM3 VMC_DM4 VMC_DM5 VMC_DM6 VMC_DM7 A16 D10 F11 D15 D27 D34 A34 D28 FBC_DQM0 FBC_DQM1 FBC_DQM2 FBC_DQM3 FBC_DQM4 FBC_DQM5 FBC_DQM6 FBC_DQM7 VMC_W DQS0 VMC_W DQS1 VMC_W DQS2 VMC_W DQS3 VMC_W DQS4 VMC_W DQS5 VMC_W DQS6 VMC_W DQS7 C14 A10 E10 D14 E26 D32 A32 B26 FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7 VMC_RDQS0 VMC_RDQS1 VMC_RDQS2 VMC_RDQS3 VMC_RDQS4 VMC_RDQS5 VMC_RDQS6 VMC_RDQS7 B14 B10 D9 E14 F26 D31 A31 A26 FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3 FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6 FBC_DQS_RN7 J16 J17 J20 J21 J22 J23 J24 J29 N27 P27 R27 T27 U27 U29 V27 V29 V34 W27 Y27 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 FBVDDQ_38 +1.5V_GFX VMA_CLK0 [19] VMA_CLK0# [19] VMA_CLK1 [19] VMA_CLK1# [19] 15mils width FBA_DEBUG FBA_DEBUG1 +FB_VREF1 T30 T29 J27 R151 R147 *10K/F_4 *10K/F_4 TP32 +1.5V_GFX +1.5V_GFX 15mils width FB_DLLAVDD1 (NC) FB_DLLAVDD2 (NC) FB_DLLAVDD3 AG27 AF28 J19 +FB_DLLAVDD R149 *0_4/S R135 *0_4/S FB_PLLAVDD1 (NC) FB_PLLAVDD2 (NC) FB_PLLAVDD3 AF27 AE28 J18 +FB_PLLAVDD R148 *0_4/S R132 *0_4/S L12 C260 C275 C268 C270 C272 PBY160808T-30Y-N_6 +1.05V_GFX 10U/6.3V_6 1U/6.3V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 N12x FBC_D00 FBC_D01 FBC_D02 FBC_D03 FBC_D04 FBC_D05 FBC_D06 FBC_D07 FBC_D08 FBC_D09 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63 B13 D13 A13 A14 C16 B16 A17 D16 C13 B11 C11 A11 C10 C8 B8 A8 E8 F8 F10 F9 F12 D8 D11 E11 D12 E13 F13 F14 F15 E16 F16 F17 D29 F27 F28 E28 D26 F25 D24 E25 E32 F32 D33 E31 C33 F29 D30 E29 B29 C31 C29 B31 C32 B32 B35 B34 A29 B28 A28 C28 C26 D25 B25 A25 VMC_DQ0 VMC_DQ1 VMC_DQ2 VMC_DQ3 VMC_DQ4 VMC_DQ5 VMC_DQ6 VMC_DQ7 VMC_DQ8 VMC_DQ9 VMC_DQ10 VMC_DQ11 VMC_DQ12 VMC_DQ13 VMC_DQ14 VMC_DQ15 VMC_DQ16 VMC_DQ17 VMC_DQ18 VMC_DQ19 VMC_DQ20 VMC_DQ21 VMC_DQ22 VMC_DQ23 VMC_DQ24 VMC_DQ25 VMC_DQ26 VMC_DQ27 VMC_DQ28 VMC_DQ29 VMC_DQ30 VMC_DQ31 VMC_DQ32 VMC_DQ33 VMC_DQ34 VMC_DQ35 VMC_DQ36 VMC_DQ37 VMC_DQ38 VMC_DQ39 VMC_DQ40 VMC_DQ41 VMC_DQ42 VMC_DQ43 VMC_DQ44 VMC_DQ45 VMC_DQ46 VMC_DQ47 VMC_DQ48 VMC_DQ49 VMC_DQ50 VMC_DQ51 VMC_DQ52 VMC_DQ53 VMC_DQ54 VMC_DQ55 VMC_DQ56 VMC_DQ57 VMC_DQ58 VMC_DQ59 VMC_DQ60 VMC_DQ61 VMC_DQ62 VMC_DQ63 FBC_CLK0 FBC_CLK0_N FBC_CLK1 FBC_CLK1_N E17 D17 D23 E23 VMC_CLK0 VMC_CLK0# VMC_CLK1 VMC_CLK1# (FBC_DEBUG) FBB_DEBUG0 (NC) FBB_DEBUG1 G19 G16 FBC_DEBUG FBC_DEBUG1 R137 *10K/F_4 R129 *10K/F_4 +1.5V_GFX +1.5V_GFX FB_CAL_PD_VDDQ (NC) FB_CAL_PD_VDDQ FB_CAL_PU_GND (NC) FB_CAL_PU_GND K27 K28 L27 L28 FB_CAL_PD_VDDQ R144 *0_4/S FB_CAL_PU_GND R145 *0_4/S R139 40.2/F_4 +1.5V_GFX R140 40.2/F_4 FB_CAL_TERM_GND (NC) FB_CAL_TERM_GND M27 M28 FB_CAL_TERM_GND R146 *0_4/S R142 40.2/F_4 D DKZz/ͬ& A FBA_CMD2 R498 10K/F_4 FBA_CMD3 R181 10K/F_4 FBA_CMD5 R189 10K/F_4 FBA_CMD18 R516 10K/F_4 FBA_CMD19 R179 10K/F_4 FBC_CMD2 R438 10K/F_4 FBC_CMD3 R117 10K/F_4 FBC_CMD5 R150 10K/F_4 FBC_CMD18 R130 10K/F_4 FBC_CMD19 R172 10K/F_4 &Žƌ&Ğƌŵŝ VMA_DQ[63:0] VMA_DQ[63:0] [19] VMC_DQ[63:0] VMC_DQ[63:0] [20] C VMC_CLK0 [20] VMC_CLK0# [20] VMC_CLK1 [20] VMC_CLK1# [20] N12x 10/12 for N12E D N12P AJ0N12P0T04 10/12 for N12E N12P AJ0N12P0T04 11/12 short D 11/12 short WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ [14,16,37,38] +1.05V_GFX [19,20,37,38] +1.5V_GFX 1 2 B 3 4 5 6 Size A3 Eϱ Document Number 7 Rev A 'WhϮͬϱ;DĞŵŽƌLJͿ Date: Monday, November 15, 2010 Sheet 8 15 of 40 1 2 3 4 5 6 7 8 ϭϲ U17D R93 10K/F_4 IFPAB_PLLVDD IFPAB_IOVDD R102 *0_4/S R104 A 10K/F_4 R103 *0_4/S 11/12 for N12E, short R74 R92 10K/F_4 IFPCD_PLLVDD 10K/F_4 IFPCD_IOVDD AK9 IFPAB_PLLVDD /&Wͬͺ>s^ AG9 AH10 AG10 AH11 IFPA_IOVDD IFPA_IOVDD (NC) IFPB_IOVDD IFPB_IOVDD (NC) AJ11 IFPAB_RSET AJ9 AC6 IFPC_PLLVDD IFPD_PLLVDD AJ8 AK8 IFPC_IOVDD IFPD_IOVDD AK7 AB6 IFPC_RSET IFPD_RSET R400 10K/F_4 IFPEF_PLLVDD 10K/F_4 IFPEF_IOVDD AJ6 IFPEF_PLLVDD AE7 AD7 IFPE_IOVDD IFPF_IOVDD AL1 IFPEF_RSET R432 +1.05V_GFX D L6 C90 C95 C109 C94 C96 10K/F_4 DACA_VDD 10K/F_4 AJ12 AP13 AN13 AN8 AP8 AP10 AN10 AR11 AR10 AN11 AP11 IFPC_L0 IFPC_L0_N IFPC_L1 IFPC_L1_N IFPC_L2 IFPC_L2_N IFPC_L3 IFPC_L3_N AP2 AN3 AM7 AM6 AL5 AM5 AM3 AM4 AP1 AR2 IFPD_AUX_I2CX_SCL IFPD_AUX_I2CX_SDA_N IFPD_L0 IFPD_L0_N IFPD_L1 IFPD_L1_N IFPD_L2 IFPD_L2_N IFPD_L3 IFPD_L3_N AP4 AN4 AR8 AR7 AP7 AN7 AN5 AP5 AR5 AR4 /&W ͬ&ͺW IFPE_AUX_I2CY_SCL IFPE_AUX_I2CY_SDA_N IFPE_L0 IFPE_L0_N IFPE_L1 IFPE_L1_N IFPE_L2 IFPE_L2_N IFPE_L3 IFPE_L3_N AE4 AD4 AH6 AH5 AH4 AG4 AF4 AF5 AE6 AE5 IFPF_AUX_I2CZ_SCL IFPF_AUX_I2CZ_SDA_N IFPF_L0 IFPF_L0_N IFPF_L1 IFPF_L1_N IFPF_L2 IFPF_L2_N IFPF_L3 IFPF_L3_N AF3 AF2 AL2 AL3 AJ3 AJ2 AJ1 AH1 AH2 AH3 DACA_VDD ͬͺZd DACA_RED DACA_GREEN DACA_BLUE AM15 AM14 AL14 DACA_HSYNC DACA_VSYNC AM13 AL13 AK12 DACA_VREF AK13 DACA_RSET AG7 DACB_VDD AK6 DACB_VREF AH7 DACB_RSET DACB_RED DACB_GREEN DACB_BLUE AK4 AL4 AJ4 NV_PLLVDD R76 *0_4/S AE9 AE8 PLLVDD PLLVDD (NC) DACB_HSYNC DACB_VSYNC AM1 AM2 SP_PLLVDD R75 *0_4/S AF9 AF8 SP_PLLVDD SP_PLLVDD (NC) VID_PLLVDD R402 *0_4/S AD9 AD8 VID_PLLVDD VID_PLLVDD (NC) DACB_VDD PBY160808T-30Y-N_6 10U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 IFPB_TXC IFPB_TXC_N IFPB_TXD4 IFPB_TXD4_N IFPB_TXD5 IFPB_TXD5_N IFPB_TXD6 IFPB_TXD6_N IFPB_TXD7 IFPB_TXD7_N IFPC_AUX_I2CW_SCL C R94 AM11 AM12 AM8 AL8 AM10 AM9 AK10 AL10 AK11 AL11 /&WͬͺdD^ IFPC_AUX_I2CW_SDA_N B R435 IFPA_TXC IFPA_TXC_N IFPA_TXD0 IFPA_TXD0_N IFPA_TXD1 IFPA_TXD1_N IFPA_TXD2 IFPA_TXD2_N IFPA_TXD3 IFPA_TXD3_N 10/12 for N12E I2CA_SCL I2CA_SDA yd>/E G1 G4 I2CB_SCL I2CB_SDA G3 G2 XTAL_IN XTAL_OUT XTAL_OUTBUFF XTAL_SSIN B1 B2 D1 D2 A 10/8 remove 27M clcok buffer circuit s EdhZ&ƵŶĐƚŝŽŶ;EϭϮ KŶůLJͿ 9/28 Nvidia announce - N12E no support Ventura N12E only support Dual Core CPU (35W) 10/7 remove all ventura circuit C I2CA_SCL I2CA_SDA R3001 R3002 2.2K_4 2.2K_4 11/10 add R3001,R3002 for NV N12E_SCL N12E_SDA R417 R416 2.2K_4 2.2K_4 CLK_27M_VGA_2 XTALOUT R420 10K/F_4 R421 10K/F_4 Y4 2 2 +3V_GFX 27MHZ 1 9/11 min stub D 10/8 remove R1016 C439 C442 18P/50V_4 18P/50V_4 N12P AJ0N12P0T04 9/11 stuff XTAL solution 1 +3V_GFX WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ N12x 11/12 short 3 4 B 5 [14,15,37,38] +1.05V_GFX [14,17,22,37,38] +3V_GFX 6 Size A3 Eϱ Document Number 7 Rev A 'Whϯͬϱ;ŝƐƉůĂLJͿ Date: Monday, November 15, 2010 Sheet 8 16 of 40 1 2 3 4 5 6 7 13*6(6 6WUDS .3XOO+LJK 520B&/. N3XOO+LJK MIOA_VREF_NC MIOA_CLKIN_NC MIOA_CLKOUT_NC MIOA_CLKOUT_NC_N N4 R4 T4 MIOA_D0_NC MIOA_D1_NC MIOA_D2_NC MIOA_D3_NC MIOA_D4_NC MIOA_D5_NC MIOA_D6_NC MIOA_D7_NC MIOA_D8_NC MIOA_D9_NC MIOA_D10_NC MIOA_D11_NC MIOA_D12_NC MIOA_D13_NC MIOA_D14_NC N1 P4 P1 P2 P3 T3 T2 T1 U4 U1 U2 U3 R6 T6 N6 MIOA_HSYNC_NC MIOA_VSYNC_NC MIOA_CTL3_NC MIOA_DE_NC N3 L3 P5 N2 A U5 T5 MIOB_VDDQ R91 10K/F_4 B MIOA_CAL_PD_VDDQ_NC MIOA_CAL_PU_GND_NC AA9 AB9 W9 Y9 MIOB_VDDQ1_NC MIOB_VDDQ2_NC MIOB_VDDQ3_NC MIOB_VDDQ4_NC AF1 MIOB_VREF_NC AA7 AA6 D/K JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST JTAG_TRST# AP14 AR14 AN14 AN16 AP16 C +3V_GFX R87 R86 2.2K_4 DGPU_EDIDCLK 2.2K_4 DGPU_EDIDDATA HDCP_SCL HDCP_SDA GFx_SCL GFx_SDA E3 E4 F4 G5 D5 E5 F6 G6 E2 E1 I2CC_SCL I2CC_SDA NC (I2CD_SCL_NC) NC (I2CD_SDA_NC NC (I2CE_SCL_NC) NC (I2CE_SDA_NC) I2CH_SCL I2CH_SDA I2CS_SCL I2CS_SDA R83 R85 +3V_GFX THERM+ THERM- B5 B4 THERMDP THERMDN A7 B7 C7 D6 D7 NC NC NC NC NC 2.2K_4 2.2K_4 TP11 TP6 11/8 for N12E 11/12 short R410 D R411 40.2K/F_4 STRAP_REF0 R409 *0_4/S R412 *0_4/S 40.2K/F_4 STRAP_REF1 STRAP0 STRAP1 STRAP2 N9 R8 M8 M9 W5 W7 V7 (HDA_SYNC_NC) (HDA_SDO_NC) (HDA_SDI_NC) (HDA_RST_N_NC) (HDA_BCLK_NC) Y1 Y2 Y3 AB3 AB2 AB1 AC4 AC1 AC2 AC3 AE3 AE2 U6 W6 Y6 MULTI_STRAP_REF0_GND MULTI_STRAP_REF0_GND (NC) MULTI_STRAP_REF1_GND (NC) MULTI_STRAP_REF1_GND STRAP0 STRAP1 STRAP2 MIOB_CLKIN R401 3 10K/F_4 Q38 2N7002 ROM_SI Hynix 64Mx16 -->15K PD Samsung 64Mx16 -->20K PD Hynix 128Mx16 -->35K PD Samsung 128Mx16 -->45K PD STRAP2 N11P-GS (DID=0DF0) ---> 5k PD N12P-GS (DID=0DF4) --->25K PD N12E-GE (DID=0DCE)--->35K PU ROM_SCLK ROM_CS_N ROM_SI ROM_SO D4 C3 D3 C4 ROM_SCLK SPDIF_NC A5 SPDIF_VGA BUFRST_N A4 GND (NC) HDA_FUSE_SRC K9 K8 VGA_OVT# ALERT DGPU_IDLE# GFx_CORE_CNTRL0 GFx_CORE_CNTRL1 R407 1%; 45.3K/F_4 *35.7K/F_4 *35.7K/F_4 ROM_SI ROM_SO ROM_SCLK 15K/F_4 STRAP0 STRAP1 STRAP2 R399 R78 R419 10K/F_4 *15K/F_4 /RJLFDO 6WUDSSLQJ%LW SMB_ALT_ADDR VGA_DEVICE SLOT_CLK_CFG PEX_PLL_EN_TERM 520B6, RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0] ;;;; 675$3 PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0] 675$3 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0] 675$3 USER[3] USER[2] USER[1] USER[0] RAMCFG [3:0] 0000 0001 0010 0011 0101 0110 XXXX XXXX DESCRIPTION DDR3 64Mx16x8, 128bit, 1GB,800MHz DDR3 64Mx16x8, 128bit, 1GB,800MHz DDR3 64Mx16x8, 128bit, 1GB,800MHz IDGH1G-04A1F1C-16X H5TQ1G63BFR-12C K4W1G1646E-HC12 DDR3 64Mx16x8, 128bit, 1GB,667MHz DDR3 64Mx16x8, 128bit, 1GB,667MHz Hynix Samsung H5TQ1G63AFR-14C K4W1G1646D-EC12 R440 *10K/F_4 JTAG_TDI R442 *10K/F_4 VGA_OVT# R84 10K/F_4 ALERT R89 10K/F_4 JTAG_TCK R439 *10K/F_4 JTAG_TRST# R443 *10K/F_4 DGPU_DPST_PW M R415 *2K/F_4 3 GPIO MBCLK2 [8,13,29] Q41 2N7002 +3V_GFX R485 4.7K_4 *0_4/S 1 Q42 2N7002 3 R484 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ACTIVE I/O N/A N/A HIGH HIGH HIGH N/A N/A N/A LOW LOW N/A N/A N/A N/A N/A N/A IN OUT OUT OUT OUT OUT OUT I/O I/O OUT OUT IN OUT OUT MBDATA2 [8,13,29] Size Custom Eϱ 5 6 3'. 3'. 3'. C USAGE Hot plug detect for IFP link C PANEL BACKLIGHT PWM PANEL POWER ENABLE PANEL BACKLIGHT ENABLE NVVDD VID0 NVVDD VID1 NVVDD VID2 11/13 OVERT ALERT FBVREF SELECT SLI SYNC0 PWR_LEVEL11/13 MEM_VID or power supply control PS CONTROL WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ *0_4 11/8 change for GPU temp detect 4 ROM_SI GPIO ASSIGNMENTS ** *0_4 1 Vendor P/N Vendor Reserved Qimonda Hynix Samsung Reserved JTAG_TMS R481 4.7K_4 GFx_SDA B VRAM Configuration Table R483 GFx_SCL /RJLFDO 6WUDSSLQJ%LW SUB_VENDOR '&dž^DƵƐ/ƐŽůĂƚŝŽŶ *36K/F_4 /RJLFDO 6WUDSSLQJ%LW N12P AJ0N12P0T04 3 *2K/F_4 35.7K/F_4 20K/F_4: CS32002FB29 RES CHIP 20K 1/16W +-1%(0402) /RJLFDO 6WUDSSLQJ%LW +3V_GFX 11/11 for N12E 11/12 short 2 R404 FB_0_BAR_SIZE N12x 1 R408 R406 25.5K/F_4 20K/F_4 ROM_SI ROM_SO R79 R405 A R82 *4.99K/F_4 XCLK_417 [37] [37] DGPU_OVT# [29] TP1 TP7 TP16 R88 10K/F_4 +3V_GFX TP10 TP8 TP56 TP55 TP2 R414 10K/F_4 +3V_GFX TP18 TP9 TP4 TP17 TP13 TP14 R77 R403 R418 R422 *4.99K/F_4 PCI_DEVIDE[4] TP58 TP57 TP54 TP3 TP5 TP12 +3V_GFX 520B6&/. AKD58GGT^01 AKD5LZGTW00 AKD5LGGT502 DGPU_DPST_PW M DGPU_DISP_ON DGPU_LVDS_BLON GFx_CORE_CNTRL0 GFx_CORE_CNTRL1 +3V_GFX 4.99K/F_4: CS24992FB26 [RES CHIP 4.99K 1/16W +1%(0402)] 10K/F_4: CS31002FB26 [RES CHIP 10K 1/16W +1% (0402)] 15K/F_4: CS31502FB24 [RES CHIP 15K 1/16W +1% (0402)] 20K/F_4: CS32002FB29 [RES CHIP 20K 1/16W +-1%(0402)] 30.1K/F_4: CS33012FB18 [RES CHIP 30.1K 1/16W +-1%(0402)] 35.7K/F_4: CS33572FB13 [RES CHIP 35.7K 1/16W +-1%(0402)] 45.3K/F_4: CS34532FB18 [RES CHIP 45.3K 1/16W +-1% (0402)] 520B62 STRAP1 N11P-GS -->35K PD N12P-GS waiting PUN update N12E-GE waiting PUN update K1 K2 K3 H3 H2 H1 H4 H5 H6 J7 K4 K5 H7 J4 J6 L1 L2 L4 M4 L7 L5 K6 L6 M6 M7 ϭϳ Default: Hynix VRAM ROM_SCLK N11P-GS (DID=0DF0) ---> 15k PU N12P-GS (DID=0DF4) --->15K PU N12E-GE (DID=0DCE) --->15K PD W1 W2 W3 Y5 . . . . . . . . DGPU_IDLE_INT# [8] STRAP0 -->45K PU GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 (NC) GPIO24 D/^ϮͺZKD 1 ROM_SO --> 10K PD MIOB_D0_NC MIOB_D1_NC MIOB_D2_NC MIOB_D3_NC MIOB_D4_NC MIOB_D5_NC MIOB_D6_NC MIOB_D7_NC MIOB_D8_NC MIOB_D9_NC MIOB_D10_NC MIOB_D11_NC MIOB_D12_NC MIOB_D13_NC MIOB_D14_NC JTAG_TCK JTAG_TMS D/^ͺ'W/Kͬ/Ϯͬ:d'ͬd, Z JTAG_TDI JTAG_TDO JTAG_TRST_N 10K/F_4 +3V_GFX AE1 V4 W4 MIOB_CAL_PD_VDDQ_NC MIOB_CAL_PU_GND_NC R413 DGPU_IDLE# MIOB_CLKIN_NC MIOB_CLKOUT_NC MIOB_CLKOUT_NC_N MIOB_HSYNC_NC MIOB_VSYNC_NC MIOB_CTL3_NC MIOB_DE_NC TP60 TP62 TP15 TP61 TP59 MIOA_CLKIN 2 N5 D/K 2 10K/F_4 MIOA_VDDQ1_NC MIOA_VDDQ2_NC MIOA_VDDQ3_NC MIOA_VDDQ4_NC 2 R90 P9 R9 T9 U9 13*646 6WUDS .3XOOGRZQ 520B&/. N3XOO+LJK /RJLFDO6WUDS%LW0DSSLQJ 389'' 3' U17E MIOA_VDDQ 8 Document Number Date: Monday, November 15, 2010 7 Rev A 'Whϰͬϱ;D/Kͬ'W/KͿ Sheet 8 17 of 40 D 1 2 3 4 5 6 7 8 ϭϴ U17G B C N12x N12P AJ0N12P0T04 +VGACORE C723 C724 C725 C726 0.1U/10V_4 0.1U/10V_4 1U/6.3V_4 4.7U/6.3V_6 +VGACORE D C727 C728 C729 10U/6.3V_8 10U/6.3V_8 47U/6.3V_8 +VGACORE A C693 C694 C695 C696 C697 C698 C699 C700 C704 C705 C706 C707 C708 C710 22U/6.3V_8 B EϭϮ Ͳ' ͗ϯϵϱ͕ϯϵϲ͕ϯϵϳ͕ϯϵϴ͕ϯϵϵ͕ϰϬϬ͕ϰϬϭ͕ϰϬϮ͕ϰϬϯ͕ϰϬϰ͕ϰϬϱ͕ϰϬϲ͕ϰϬϳ͕ϰϬϴ͕ϰϬϵ͕ϰϭϬ͕ϰϭϭƐƚƵĨĨϬ͘ϭhͬϭϬsͺϰ͘ EϭϮ Ͳ' ͗ϰϭϮ^ƚƵĨĨϰϳhͬϲ͘ϯsͺϴ EϭϮ Ͳ' ;'ϯͲϭϮϴͿ^ƚƵĨĨ +VGACORE C711 C712 C713 C714 C715 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *1U/6.3V_4 *1U/6.3V_4 +VGACORE C C716 C717 C718 C719 C720 C721 *1U/6.3V_4 *1U/6.3V_4 *1U/6.3V_4 *1U/6.3V_4 *1U/6.3V_4 *4.7U/6.3V_6 *4.7U/6.3V_6 C722 9/28 need check for N12E D WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ [37] 3 C703 C709 0.47U/10V_4 0.47U/10V_4 0.47U/10V_4 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 N12P AJ0N12P0T04 2 C702 +VGACORE N12x 1 C701 0.01U/16V_4 0.01U/16V_4 0.01U/16V_4 0.01U/16V_4 0.01U/16V_4 0.01U/16V_4 0.01U/16V_4 0.01U/16V_4 0.022U/16V_4 0.022U/16V_4 0.022U/16V_4 2 'Whs P21 P23 P25 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T12 T14 T16 T18 T20 T22 T24 V11 V13 V15 V17 V19 V21 V23 V25 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18 Y20 Y22 Y24 1 VDD_057 VDD_058 VDD_059 VDD_060 VDD_061 VDD_062 VDD_063 VDD_064 VDD_065 VDD_066 VDD_067 VDD_068 VDD_069 VDD_070 VDD_071 VDD_072 VDD_073 VDD_074 VDD_075 VDD_076 VDD_077 VDD_078 VDD_079 VDD_080 VDD_081 VDD_082 VDD_083 VDD_084 VDD_085 VDD_086 VDD_087 VDD_088 VDD_089 VDD_090 VDD_091 VDD_092 VDD_093 VDD_094 VDD_095 VDD_096 VDD_097 VDD_098 VDD_099 VDD_100 VDD_101 VDD_102 VDD_103 VDD_104 VDD_105 VDD_106 VDD_107 VDD_108 VDD_109 VDD_110 VDD_111 EϭϮWͲ'^;'ϮͲϭϮϴͿ^ƚƵĨĨ 2 VDD_001 VDD_002 VDD_003 VDD_004 VDD_005 VDD_006 VDD_007 VDD_008 VDD_009 VDD_010 VDD_011 VDD_012 VDD_013 VDD_014 VDD_015 VDD_016 VDD_017 VDD_018 VDD_019 VDD_020 VDD_021 VDD_022 VDD_023 VDD_024 VDD_025 VDD_026 VDD_027 VDD_028 VDD_029 VDD_030 VDD_031 VDD_032 VDD_033 VDD_034 VDD_035 VDD_036 VDD_037 VDD_038 VDD_039 VDD_040 VDD_041 VDD_042 VDD_043 VDD_044 VDD_045 VDD_046 VDD_047 VDD_048 VDD_049 VDD_050 VDD_051 VDD_052 VDD_053 VDD_054 VDD_055 VDD_056 E9 E12 E15 E18 E24 E27 E30 F2 F5 F31 F34 J2 J5 J31 J34 L9 M2 M5 M11 M13 M15 M17 M19 M21 M23 M25 M31 M34 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 P12 P14 P16 P18 P20 P22 P24 R2 R5 R31 R34 T11 T13 T15 T17 T19 T21 T23 T25 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 V2 V5 V9 V12 V14 V16 V18 V20 V22 V24 V31 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25 1 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB25 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AD12 AD14 AD16 AD18 AD22 AD24 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 M12 M14 M16 M18 M20 M22 M24 P11 P13 P15 P17 P19 GND_97 GND_98 GND_99 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 'Wh'E 2 U17F A GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 1 +VGACORE AA2 AA5 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA34 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AC9 AD11 AD13 AD15 AD17 AD2 AD5 AD21 AD23 AD25 AD31 AD34 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AG2 AG31 AG34 AK2 AG5 AK31 AK34 AK5 AK14 AL6 AL9 AL12 AL15 AL18 AL21 AL24 AL27 AL30 AN2 AN34 AP3 AP6 AP9 AP12 AP15 AP18 AP21 AP24 AP27 AP30 AP33 B3 B6 B9 B12 B15 B21 B24 B27 B30 B33 C2 C34 E6 4 5 +VGACORE 6 Size A3 Eϱ Document Number 7 Rev A 'Whϱͬϱ;WŽǁĞƌͬ'ƌŽƵŶĚͿ Date: Monday, November 15, 2010 Sheet 8 18 of 40 5 4 3 [15] VMA_DQ[63..0] [15] VMA_DM[7..0] [15] VMA_WDQS[7..0] [15] VMA_RDQS[7..0] D [15] [15] [15] [15] [15] [15] [15] [15] [15] [15] [15] [15] [15] [15] [15] [15] FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14 [15] FBA_CMD12 [15] FBA_CMD27 [15] FBA_CMD26 [15] VMA_CLK0 [15] VMA_CLK0# [15] FBA_CMD3 C [15] [15] [15] [15] [15] FBA_CMD2 FBA_CMD0 FBA_CMD30 FBA_CMD15 FBA_CMD13 [15] FBA_CMD5 M8 H1 VREFCA VREFDQ FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 FBA_CMD12 FBA_CMD27 FBA_CMD26 M2 N8 M3 BA0 BA1 BA2 VMA_CLK0 VMA_CLK0# FBA_CMD3 J7 K7 K9 CK CK CKE FBA_CMD2 FBA_CMD0 FBA_CMD30 FBA_CMD15 FBA_CMD13 K1 L2 J3 K3 L3 ODT CS RAS CAS WE VMA_WDQS2 VMA_RDQS2 F3 G3 DQSL DQSL VMA_DM2 VMA_DM0 E7 D3 DML DMU VMA_WDQS0 VMA_RDQS0 C7 B7 DQSU DQSU FBA_CMD5 T2 RESET L8 ZQ VMA_ZQ1 Should be 240 Ohms +-1% R185 243/F_4 J1 L1 J9 L9 B NC#J1 NC#L1 NC#J9 NC#L9 VRAM8 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 VMA_DQ16 VMA_DQ22 VMA_DQ18 VMA_DQ23 VMA_DQ19 VMA_DQ20 VMA_DQ17 VMA_DQ21 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 VMA_DQ7 VMA_DQ2 VMA_DQ5 VMA_DQ1 VMA_DQ6 VMA_DQ0 VMA_DQ4 VMA_DQ3 VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 VREFC_VMA1 VREFD_VMA1 M8 H1 VREFCA VREFDQ FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 FBA_CMD12 FBA_CMD27 FBA_CMD26 M2 N8 M3 BA0 BA1 BA2 VMA_CLK0 VMA_CLK0# FBA_CMD3 J7 K7 K9 CK CK CKE A1 A8 C1 C9 D2 E9 F1 H2 H9 FBA_CMD2 FBA_CMD0 FBA_CMD30 FBA_CMD15 FBA_CMD13 K1 L2 J3 K3 L3 ODT CS RAS CAS WE VMA_WDQS3 VMA_RDQS3 F3 G3 DQSL DQSL VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VMA_DM3 VMA_DM1 E7 D3 DML DMU VMA_WDQS1 VMA_RDQS1 C7 B7 DQSU DQSU FBA_CMD5 T2 RESET L8 ZQ VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 B1 B9 D1 D8 E2 E8 F9 G1 G9 +1.5V_GFX VMA_ZQ2 Should be 240 Ohms +-1% R490 243/F_4 J1 L1 J9 L9 96-BALL SDRAM DDR3 VRAM _DDR3 ϭϵ NC#J1 NC#L1 NC#J9 NC#L9 VRAM4 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 VMA_DQ30 VMA_DQ26 VMA_DQ29 VMA_DQ28 VMA_DQ31 VMA_DQ25 VMA_DQ27 VMA_DQ24 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 VMA_DQ12 VMA_DQ10 VMA_DQ15 VMA_DQ8 VMA_DQ13 VMA_DQ11 VMA_DQ14 VMA_DQ9 VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 A1 A8 C1 C9 D2 E9 F1 H2 H9 VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 B1 B9 D1 D8 E2 E8 F9 G1 G9 [15] VMA_CLK1 [15] VMA_CLK1# [15] FBA_CMD19 +1.5V_GFX [15] FBA_CMD18 [15] FBA_CMD16 VREFC_VMA3 VREFD_VMA3 M8 H1 VREFCA VREFDQ FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 FBA_CMD12 FBA_CMD27 FBA_CMD26 M2 N8 M3 BA0 BA1 BA2 VMA_CLK1 VMA_CLK1# FBA_CMD19 J7 K7 K9 CK CK CKE FBA_CMD18 FBA_CMD16 FBA_CMD30 FBA_CMD15 FBA_CMD13 K1 L2 J3 K3 L3 ODT CS RAS CAS WE VMA_WDQS5 VMA_RDQS5 F3 G3 DQSL DQSL VMA_DM5 VMA_DM4 E7 D3 DML DMU VMA_WDQS4 VMA_RDQS4 C7 B7 DQSU DQSU FBA_CMD5 T2 RESET L8 ZQ VMA_ZQ3 Should be 240 Ohms +-1% R180 243/F_4 J1 L1 J9 L9 96-BALL SDRAM DDR3 VRAM _DDR3 +1.5V_GFX VMA_CLK0 1 CHANNEL A: 256MB/512MB DDR3 VRAM3 VREFC_VMA1 VREFD_VMA1 2 E3 F7 F2 F8 H3 H8 G2 H7 VMA_DQ45 VMA_DQ43 VMA_DQ44 VMA_DQ41 VMA_DQ47 VMA_DQ40 VMA_DQ46 VMA_DQ42 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 VMA_DQ36 VMA_DQ39 VMA_DQ32 VMA_DQ38 VMA_DQ33 VMA_DQ37 VMA_DQ34 VMA_DQ35 VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 VREFC_VMA3 VREFD_VMA3 M8 H1 VREFCA VREFDQ FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 FBA_CMD12 FBA_CMD27 FBA_CMD26 M2 N8 M3 BA0 BA1 BA2 VMA_CLK1 VMA_CLK1# FBA_CMD19 J7 K7 K9 CK CK CKE A1 A8 C1 C9 D2 E9 F1 H2 H9 FBA_CMD18 FBA_CMD16 FBA_CMD30 FBA_CMD15 FBA_CMD13 K1 L2 J3 K3 L3 ODT CS RAS CAS WE VMA_WDQS7 VMA_RDQS7 F3 G3 DQSL DQSL VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VMA_DM7 VMA_DM6 E7 D3 DML DMU VMA_WDQS6 VMA_RDQS6 C7 B7 DQSU DQSU FBA_CMD5 T2 RESET L8 ZQ VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 B1 B9 D1 D8 E2 E8 F9 G1 G9 +1.5V_GFX VMA_ZQ4 Should be 240 Ohms +-1% R497 243/F_4 J1 L1 J9 L9 96-BALL SDRAM DDR3 VRAM _DDR3 +1.5V_GFX R505 1.33K/F_4 NC#J1 NC#L1 NC#J9 NC#L9 VRAM7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 [15] FBA_CMD17 [15] FBA_CMD1 FBA_CMD17 TP29 FBA_CMD1 TP33 NC#J1 NC#L1 NC#J9 NC#L9 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 VMA_DQ58 VMA_DQ63 VMA_DQ56 VMA_DQ61 VMA_DQ59 VMA_DQ57 VMA_DQ60 VMA_DQ62 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 VMA_DQ51 VMA_DQ53 VMA_DQ50 VMA_DQ52 VMA_DQ48 VMA_DQ54 VMA_DQ49 VMA_DQ55 VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 A1 A8 C1 C9 D2 E9 F1 H2 H9 VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 B1 B9 D1 D8 E2 E8 F9 G1 G9 D +1.5V_GFX C B 96-BALL SDRAM DDR3 VRAM _DDR3 +1.5V_GFX R188 1.33K/F_4 +1.5V_GFX R187 1.33K/F_4 R507 1.33K/F_4 VMA_CLK1 R178 VREFC_VMA1 160/F_4 VMA_CLK0# Fermi : Change to 160 ohm 1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402) 2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402) R499 1.33K/F_4 C530 VREFD_VMA1 R182 1.33K/F_4 0.1U/10V_4 R183 160/F_4 VREFC_VMA3 VMA_CLK1# C295 0.1U/10V_4 R186 1.33K/F_4 VREFD_VMA3 C297 R515 1.33K/F_4 0.1U/10V_4 Fermi : Change to 160 ohm 1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402) 2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402) C544 0.1U/10V_4 +1.5V_GFX +1.5V_GFX A C527 +1.5V_GFX +1.5V_GFX C528 C555 C318 C519 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 C531 C554 C316 C553 C521 C294 10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 A 10U/6.3V_8 C556 C551 C296 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 C535 C537 C300 C529 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 C291 10U/6.3V_8 C539 10U/6.3V_8 C292 C293 C301 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 C520 C315 0.1U/10V_4 0.1U/10V_4 +1.5V_GFX C532 C538 C541 C552 C526 Samsung 900MHz 1G AKD5LGHT500 10U/6.3V_8 WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ 10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 Eϱ 5 4 3 [15,20,37,38] +1.5V_GFX 2 Size Custom Document Number Rev A 'WhDĞŵŽƌLJϭͬϮ;ZϯͿ Date: Monday, November 15, 2010 1 Sheet 19 of 40 5 4 3 [15] VMC_DQ[63..0] [15] VMC_DM[7..0] [15] VMC_WDQS[7..0] [15] VMC_RDQS[7..0] D [15] [15] [15] [15] [15] [15] [15] [15] [15] [15] [15] [15] [15] [15] [15] [15] FBC_CMD9 FBC_CMD11 FBC_CMD8 FBC_CMD25 FBC_CMD10 FBC_CMD24 FBC_CMD22 FBC_CMD7 FBC_CMD21 FBC_CMD6 FBC_CMD29 FBC_CMD23 FBC_CMD28 FBC_CMD20 FBC_CMD4 FBC_CMD14 [15] FBC_CMD12 [15] FBC_CMD27 [15] FBC_CMD26 [15] VMC_CLK0 [15] VMC_CLK0# [15] FBC_CMD3 C [15] [15] [15] [15] [15] FBC_CMD2 FBC_CMD0 FBC_CMD30 FBC_CMD15 FBC_CMD13 [15] FBC_CMD5 M8 H1 VREFCA VREFDQ FBC_CMD9 FBC_CMD11 FBC_CMD8 FBC_CMD25 FBC_CMD10 FBC_CMD24 FBC_CMD22 FBC_CMD7 FBC_CMD21 FBC_CMD6 FBC_CMD29 FBC_CMD23 FBC_CMD28 FBC_CMD20 FBC_CMD4 FBC_CMD14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 FBC_CMD12 FBC_CMD27 FBC_CMD26 M2 N8 M3 BA0 BA1 BA2 VMC_CLK0 VMC_CLK0# FBC_CMD3 J7 K7 K9 CK CK CKE FBC_CMD2 FBC_CMD0 FBC_CMD30 FBC_CMD15 FBC_CMD13 K1 L2 J3 K3 L3 ODT CS RAS CAS WE VMC_WDQS2 VMC_RDQS2 F3 G3 DQSL DQSL VMC_DM2 VMC_DM0 E7 D3 DML DMU VMC_WDQS0 VMC_RDQS0 C7 B7 DQSU DQSU FBC_CMD5 T2 RESET L8 ZQ VMC_ZQ1 Should be 240 Ohms +-1% R426 243/F_4 J1 L1 J9 L9 B NC#J1 NC#L1 NC#J9 NC#L9 VRAM1 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 VMC_DQ22 VMC_DQ21 VMC_DQ23 VMC_DQ16 VMC_DQ20 VMC_DQ17 VMC_DQ18 VMC_DQ19 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 VMC_DQ3 VMC_DQ6 VMC_DQ0 VMC_DQ7 VMC_DQ1 VMC_DQ5 VMC_DQ2 VMC_DQ4 VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 M8 H1 VREFCA VREFDQ FBC_CMD9 FBC_CMD11 FBC_CMD8 FBC_CMD25 FBC_CMD10 FBC_CMD24 FBC_CMD22 FBC_CMD7 FBC_CMD21 FBC_CMD6 FBC_CMD29 FBC_CMD23 FBC_CMD28 FBC_CMD20 FBC_CMD4 FBC_CMD14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 FBC_CMD12 FBC_CMD27 FBC_CMD26 M2 N8 M3 BA0 BA1 BA2 VMC_CLK0 VMC_CLK0# FBC_CMD3 J7 K7 K9 CK CK CKE A1 A8 C1 C9 D2 E9 F1 H2 H9 FBC_CMD2 FBC_CMD0 FBC_CMD30 FBC_CMD15 FBC_CMD13 K1 L2 J3 K3 L3 ODT CS RAS CAS WE VMC_WDQS3 VMC_RDQS3 F3 G3 DQSL DQSL VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VMC_DM3 VMC_DM1 E7 D3 DML DMU VMC_WDQS1 VMC_RDQS1 C7 B7 DQSU DQSU FBC_CMD5 T2 RESET L8 ZQ VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 B1 B9 D1 D8 E2 E8 F9 G1 G9 VMC_ZQ2 Should be 240 Ohms +-1% R116 243/F_4 J1 L1 J9 L9 96-BALL SDRAM DDR3 VRAM _DDR3 NC#J1 NC#L1 NC#J9 NC#L9 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 VMC_DQ24 VMC_DQ30 VMC_DQ26 VMC_DQ28 VMC_DQ25 VMC_DQ31 VMC_DQ27 VMC_DQ29 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 VMC_DQ8 VMC_DQ14 VMC_DQ9 VMC_DQ12 VMC_DQ11 VMC_DQ13 VMC_DQ10 VMC_DQ15 VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 A1 A8 C1 C9 D2 E9 F1 H2 H9 VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 B1 B9 D1 D8 E2 E8 F9 G1 G9 [15] VMC_CLK1 [15] VMC_CLK1# [15] FBC_CMD19 +1.5V_GFX [15] FBC_CMD18 [15] FBC_CMD16 VREFC_VMC3 VREFD_VMC3 M8 H1 VREFCA VREFDQ FBC_CMD9 FBC_CMD11 FBC_CMD8 FBC_CMD25 FBC_CMD10 FBC_CMD24 FBC_CMD22 FBC_CMD7 FBC_CMD21 FBC_CMD6 FBC_CMD29 FBC_CMD23 FBC_CMD28 FBC_CMD20 FBC_CMD4 FBC_CMD14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 FBC_CMD12 FBC_CMD27 FBC_CMD26 M2 N8 M3 BA0 BA1 BA2 VMC_CLK1 VMC_CLK1# FBC_CMD19 J7 K7 K9 CK CK CKE FBC_CMD18 FBC_CMD16 FBC_CMD30 FBC_CMD15 FBC_CMD13 K1 L2 J3 K3 L3 ODT CS RAS CAS WE VMC_WDQS4 VMC_RDQS4 F3 G3 DQSL DQSL VMC_DM4 VMC_DM5 E7 D3 DML DMU VMC_WDQS5 VMC_RDQS5 C7 B7 DQSU DQSU FBC_CMD5 T2 RESET L8 ZQ VMC_ZQ3 Should be 240 Ohms +-1% R171 243/F_4 J1 L1 J9 L9 96-BALL SDRAM DDR3 VRAM _DDR3 +1.5V_GFX VMC_CLK0 ϮϬ VRAM2 VREFC_VMC1 VREFD_VMC1 +1.5V_GFX 1 CHANNEL B: 256MB/512MB DDR3 VRAM5 VREFC_VMC1 VREFD_VMC1 2 NC#J1 NC#L1 NC#J9 NC#L9 VRAM6 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 VMC_DQ36 VMC_DQ34 VMC_DQ39 VMC_DQ32 VMC_DQ37 VMC_DQ35 VMC_DQ38 VMC_DQ33 VREFC_VMC3 VREFD_VMC3 M8 H1 VREFCA VREFDQ FBC_CMD9 FBC_CMD11 FBC_CMD8 FBC_CMD25 FBC_CMD10 FBC_CMD24 FBC_CMD22 FBC_CMD7 FBC_CMD21 FBC_CMD6 FBC_CMD29 FBC_CMD23 FBC_CMD28 FBC_CMD20 FBC_CMD4 FBC_CMD14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 VMC_DQ42 VMC_DQ47 VMC_DQ41 VMC_DQ45 VMC_DQ44 VMC_DQ43 VMC_DQ40 VMC_DQ46 VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 B2 D9 G7 K2 K8 N1 N9 R1 R9 FBC_CMD12 FBC_CMD27 FBC_CMD26 M2 N8 M3 BA0 BA1 BA2 VMC_CLK1 VMC_CLK1# FBC_CMD19 J7 K7 K9 CK CK CKE VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 A1 A8 C1 C9 D2 E9 F1 H2 H9 FBC_CMD18 FBC_CMD16 FBC_CMD30 FBC_CMD15 FBC_CMD13 K1 L2 J3 K3 L3 ODT CS RAS CAS WE VMC_WDQS6 VMC_RDQS6 F3 G3 DQSL DQSL VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VMC_DM6 VMC_DM7 E7 D3 DML DMU VMC_WDQS7 VMC_RDQS7 C7 B7 DQSU DQSU FBC_CMD5 T2 RESET L8 ZQ VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 B1 B9 D1 D8 E2 E8 F9 G1 G9 +1.5V_GFX Should be 240 Ohms +-1% R131 243/F_4 J1 L1 J9 L9 96-BALL SDRAM DDR3 VRAM _DDR3 +1.5V_GFX R434 1.33K/F_4 VMC_CLK1 R61 160/F_4 NC#J1 NC#L1 NC#J9 NC#L9 E3 F7 F2 F8 H3 H8 G2 H7 VMC_DQ49 VMC_DQ48 VMC_DQ55 VMC_DQ53 VMC_DQ52 VMC_DQ50 VMC_DQ54 VMC_DQ51 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 VMC_DQ61 VMC_DQ58 VMC_DQ62 VMC_DQ59 VMC_DQ60 VMC_DQ56 VMC_DQ63 VMC_DQ57 VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 A1 A8 C1 C9 D2 E9 F1 H2 H9 VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 B1 B9 D1 D8 E2 E8 F9 G1 G9 D +1.5V_GFX C B 96-BALL SDRAM DDR3 VRAM _DDR3 +1.5V_GFX R101 1.33K/F_4 VMC_ZQ4 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 +1.5V_GFX R479 1.33K/F_4 R478 1.33K/F_4 R173 160/F_4 VREFC_VMC1 VREFD_VMC1 VREFC_VMC3 VMC_CLK0# VREFD_VMC3 VMC_CLK1# Fermi : Change to 160 ohm 1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402) 2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402) R97 1.33K/F_4 C189 0.1U/10V_4 R427 1.33K/F_4 Fermi : Change to 160 ohm 1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402) 2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402) C453 0.1U/10V_4 R480 1.33K/F_4 C510 0.1U/10V_4 R477 1.33K/F_4 C507 0.1U/10V_4 +1.5V_GFX A +1.5V_GFX C276 C455 C509 C57 5 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 A C491 10U/6.3V_8 C225 10U/6.3V_8 C459 10U/6.3V_8 C436 C267 C484 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 [15] +1.5V_GFX C160 C274 C172 C441 C253 C456 C277 C269 4 +1.5V_GFX 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 C219 C443 C508 C271 C56 C437 C506 C220 [15] 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 FBC_CMD17 FBC_CMD1 FBC_CMD17 FBC_CMD1 TP26 [15,19,37,38] +1.5V_GFX TP21 WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ Samsung 900MHz 1G AKD5LGHT500 3 2 Eϱ Size Custom Document Number Rev A 'WhDĞŵŽƌLJϮͬϮ;ZϯͿ Date: Monday, November 15, 2010 1 Sheet 20 of 40 4 3 R13 R12 h^ĂŵĞƌĂŽŶŶĞĐƚŽƌ R14 R8 U1 3 VIN VOUT *0_6 0_6 4 CN7 +3V +5V +3.6V_CAM +3VLCD_CON C10 1000P/50V_4 +3V C15 1 D Zϭ SHDN R15 *215K/F/04 *1U/6.3V_4 C14 2 GND SET 5 *4.7U/6.3V_6 *IC(5P) G913C (SOT23-5)EP R16 *100K/F_4 sŽƵƚсϭ͘Ϯϱ;ϭнZϭͬZϮͿ ZϮ EDIDCLK EDIDDATA [6] PCH_LA_DATAN0 [6] PCH_LA_DATAP0 TXLOUT0TXLOUT0+ [6] PCH_LA_DATAN1 [6] PCH_LA_DATAP1 TXLOUT1TXLOUT1+ [6] PCH_LA_DATAN2 [6] PCH_LA_DATAP2 TXLOUT2TXLOUT2+ TXLCLKOUTTXLCLKOUT+ [6] PCH_LA_CLK# [6] PCH_LA_CLK D/ L23 L22 [23] DIGITAL_D1 [23] DIGITAL_CLK 2 3 USBP9USBP9+ CON_USBP9CON_USBP9+ 1 4 L21 W CM2012-90 D Z DIGITAL_D1_R DIGITAL_CLK_R C11 C16 C TXUOUT0TXUOUT0+ [6] PCH_LB_DATAN1 [6] PCH_LB_DATAP1 TXUOUT1TXUOUT1+ [6] PCH_LB_DATAN2 [6] PCH_LB_DATAP2 TXUOUT2TXUOUT2+ TXUCLKOUTTXUCLKOUT+ DIGITAL_D1_R DIGITAL_CLK_R [6] PCH_LB_CLK# [6] PCH_LB_CLK 8/26 A-->B modify +3.6V_CAM [6] PCH_LB_DATAN0 [6] PCH_LB_DATAP0 8/26 A-->B modify DPST_PW M_R [6] PCH_DPST_PW M 0.01U/16V_4 *4.7U/6.3V_6 +3.6V_CAM 8/26 A-->B modify CON_USBP9CON_USBP9+ 11/11 changed from +3VPCU *10P/50V_4 *10P/50V_4 33P/50V_4 33P/50V_4 CON_USBP9CON_USBP9+ DIGITAL_D1 DIGITAL_CLK 8/26 A-->B modify +5VS5 +12VALW 14.5v 330K_6 Q1 AO3404 1 1 R1 R9 C13 C12 LCDONG C1 +3VLCD 2 1 3 1 R5 C3 [29] LID_CONTROL D2 0_4 PN_BLON R3 LVDS_BLON R2 1K/F_4 C *0.01U/16V_4 0.1U/10V_4 *10U/6.3V_8 +VIN_BLIGHT 1 2 L2 FBM2125 HM330-T +VIN_BLIGHT 3 +VIN 3 Q4 2N7002 2 C420 C6 C7 *10U/25V_12 0.1U/50V_6 0.01U/25V_4 B 100K/F_4 22P/50V_4 RB501V-40 BLON_CON R7 [6] PCH_LVDS_BLON C8 C9 C4 LCDDISCHG 2 100K/F_4 G_4 1 R11 G_3 L1 PBY201209T-4A/08 C5 0.1U/50V_6 1 DISP_ON [6] PCH_DISP_ON G_2 22_8 C2 0.027U/25V_6 LCDON# B +VIN_BLIGHT G_1 +3VLCD_CON 1 2 Q3 2N7002 Q5 DTC144EUA *4.7U/6.3V_6 *0.1U/10V_4 DPST_PW M_R BLON_CON D GS12401-1011-9F R6 2 *0_4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 0.1U/10V_4 2 100K/F_4 R10 PW M_VADJ +3V AO3404 ID current 5.8A 2 C422 C421 C424 C423 [29] 3 [8] [8] SBK160808T-301Y-N SBK160808T-301Y-N Ϯϭ EDIDCLK EDIDDATA [6] PCH_EDIDCLK [6] PCH_EDIDDATA +5V 1 G_0 +3V 2 2.2K_4 2.2K_4 G_5 5 D1 *RB501V-40 47K_4 LID_EC# +3VPCU [28,29] A A 100K/F_4 3 R4 LCD_BK WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ 2 Q2 *DTC144EUA [2,6,7,8,9,10,12,13,14,22,23,24,25,26,27,28,29,34,36,37,39] +3V [6,7,27,28,29,30,31] +3VPCU [6,7,10,22,23,27,28,36] +5V [30,31,32,33,34,35,36,37,38,40] +VIN 1 [8] 5 4 3 2 Eϱ Size Custom Document Number Rev A >ŽŶŶĞĐƚŽƌ;>s^Ϳ Date: Monday, November 15, 2010 1 Sheet 21 of 40 5 4 3 2 1 ϮϮ 16 CRT PORT 40 MIL D +5VCRT 1 FUSE1A6V_POLY 0.1U/10V_4 F1 2 +5V PCH_CRT_R L4 BLM18BA470SN1D CRT_R_CON [6] PCH_CRT_G L5 BLM18BA470SN1D CRT_G_CON [6] PCH_CRT_B L3 BLM18BA470SN1D CRT_B_CON [6] 40 mils C20 +5VCRT +5VCRT SSM14 spec is 40V 1A C43 C39 C40 C34 C36 150/F_4 6.8P/50V_4 150/F_4 6.8P/50V_4 150/F_4 6.8P/50V_4 C38 11 6.8P/50V_4 6.8P/50V_4 6.8P/50V_4 17 R44 R45 R46 6 1 7 2 8 3 9 4 10 5 12 CRT_DDCDATA_CON C33 *470P/50V_4 13 CRT_HSYNC_CON C32 *47P/50V_6 14 CRT_VSYNC_CON C25 *47P/50V_6 15 CRT_DDCCLK_CON C22 *470P/50V_4 D CRT CONN CN9 EMI [6] CRT_VSYNC PCH_VSYNC /ƐŽůĂƚŝŽŶ U3 2 4 CRT_HSYNC PCH_HSYNC 2 U4 2N7002 1 R47 2.2K_4 R56 2.2K_4 4 CRT_HSYNC_CON [6] PCH_DDCDATA CRT_DDCDATA M74VHC1GT125DF2G CRT_DDCCLK_CON *0_4/S short0402 4.7K_4 R51 3 R50 +5VCRT +3V 0.1U/10V_4 [6] CRT_DDCCLK 2 5 5 1 1 +5V C35 *0_4 Q10 CRT_VSYNC_CON [6] PCH_DDCCLK C R48 M74VHC1GT125DF2G 2 ƌŝǀĞŶ^ƚƌŽŶŐ 1 2 D3 R53 3 Q13 R57 C 1+5VCRT2 RB501V-40 R52 4.7K_4 *0_4/S CRT_DDCDATA_CON short0402 2N7002 *0_4 HDMI PORT CN13 +5V_HDMIC ,D/^DƵƐ/ƐŽůĂƚŝŽŶ +3V B D/^ŽůƵƚŝŽŶ +3V 2.2K_4 [6] HDMI_SCL_R SDVO_CLK C221 *0.01U/16V_4 2 R126 1 3 R169 R161 R154 R143 *0_4 *0_4 *0_4 *0_4 C_TX2_HDMIC_TX1_HDMIC_TX0_HDMIC_TXC_HDMI- HDMI_SCLK Q16 FDV301N +3V C_TX2_HDMI+ C_TX1_HDMI+ C_TX0_HDMI+ C_TXC_HDMI+ for EMI request +3V +5V 2.2K_4 2 R112 Q15 FDV301N R449 [6] HDMI_SDA_R SDVO_DATA 1 3 0_4 HDMI_SDATA *0_4 [29] +3V_GFX 3 A +3V 1 Q18 2N7002 2 R472 R471 680/F_4 C_TX2_HDMI+ 680/F_4 C_TX2_HDMI- R469 R466 680/F_4 C_TX1_HDMI+ 680/F_4 C_TX1_HDMI- R464 R461 680/F_4 C_TX0_HDMI+ 680/F_4 C_TX0_HDMI- R458 R455 680/F_4 C_TXC_HDMI+ 680/F_4 C_TXC_HDMI- [6] HDMI_HPD_CON 2 R113 110K/F_4 SHELL1 D2+ D2 Shield D2D1+ D1 Shield D1D0+ D0 Shield D0CK+ CK Shield CKCE Remote NC DDC CLK DDC DATA GND +5V HP DET SHELL2 20 B 21 HDMI CONN 220P/50V_4 11/11 pin 13,17 -> NC for HDMI 7-13 test issue 2 BAV99W A B-stage change WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ 9/1 change to 680ohm 8/31UMA/OPTIMUS-680 ohm, DISCRETE-499 ohm 5 0.1U/10V_4 C_TX2_HDMI+ 10/8 add for EMI 3 R452 *348K/F_4 R465 10K_4 C266 +3V 1 HDMI_HPD 1 HDMI_HPD_3V HDMI_DET_P 2 DGPU_CL_HDMIP 2 1 Q39 MMBT3904-7-F HDMI_HPD IN_D2 D4 R451 150K/F_4 1 3 R450 +3V IN_D2 1 2 IN_D2# C261 0.1U/10V_4 C_TX2_HDMI3 [6] IN_D2# IN_D1 C_TX1_HDMI+ C258 0.1U/10V_4 4 [6] IN_D1 5 IN_D1# C255 0.1U/10V_4 C_TX1_HDMI6 [6] IN_D1# IN_D0 C252 0.1U/10V_4 C_TX0_HDMI+ 7 [6] IN_D0 8 IN_D0# C_TX0_HDMIC249 0.1U/10V_4 9 [6] IN_D0# IN_CLK C242 0.1U/10V_4 C_TXC_HDMI+ 10 [6] IN_CLK 11 IN_CLK# C_TXC_HDMIC237 0.1U/10V_4 12 [6] IN_CLK# CH751H-40GP 13 5V_HSMBCK R468 D19 2 2.2K_4 1 14 5V_HSMBDT R467 2.2K_4 HDMI_SCLK 15 2 1 HDMI_SDATA D18 CH751H-40GP 16 C228 *10P/50V_4 17 C232 *10P/50V_4 18 19 F2 +5V_HDMIC 2 1 +5V FUSE1A6V_POLY HDMI_DET_N HDMI_DET_C R114 10K/F_4 L11 BLM18BA470SN1D C214 [6] 4 Eϱ 3 2 Size Custom Document Number Rev A Zdͬ,D/ŽŶŶĞĐƚŽƌ Date: Monday, November 15, 2010 1 Sheet 22 of 40 A B C D E +5V 5V_AMP_PWR39 C685 0.1U/10V_4 +3V +5V L37 HCB1608K-181T15 4 +5V_AVDD +5V_AVDD L34 /ŶƚĞƌŶĂů^ƉĞĂŬĞƌ HCB1608K-181T15 INT SPEAKER CONN 5V_AMP_PWR46 C659 *0.1U/10V_4 C689 C673 1U/10V_4 1 C690 4.7U/6.3V_6 Ϯϯ +5V 5V_AMP_PWR39 C631 4.7U/6.3V_6 4.7U/6.3V_6 C644 1U/10V_4 C618 1U/10V_4 C639 *0.1U/10V_4 C615 10U/6.3V_8 L_SPK+ L_SPKR_SPKR_SPK+ C688 5V_AMP_PWR46 2 L36 HCB1608K-181T15 0.1U/10V_4 L20 L19 L18 L17 SBK160808T-221Y-N SBK160808T-221Y-N SBK160808T-221Y-N SBK160808T-221Y-N C686 0.1U/10V_4 C416 4 C417 C418 680P/50V_4 680P/50V_4 680P/50V_4 +3V 1 2 3 4 CN19 +5V_AVDD AGND C691 4.7U/6.3V_6 L_SPK+_R L_SPK-_R R_SPK-_R R_SPK+_R AGND C419 680P/50V_4 SPDIFO2/EAPD SPDIFO 25 38 AVDD2 39 PVDD1 AVDD1 LINE1-R LINE1-L 24 23 MIC1-R MIC1-L 22 21 MONO-OUT Sense B 20 18 MIC2-R MIC2-L 17 16 LINE2-R LINE2-L 15 14 Sense A 13 ALC269Q-VB6-GR GPIO0/DMIC-DATA 3 GPIO1/DMIC-CLK R371 R661 4.7K_4 4.7K_4 C1002 EXT_MIC_L EXT_MIC_R C1003 150P/50V_4 150P/50V_4 ALC269_VREF 1 C653 C656 EXT_MIC_R1 C411 EXT_MIC_L1 C643 AGND 2 4.7U/6.3V_6 1U/10V_4 AGND 2.2U/6.3V_6 EXT_MIC_R2 R660 EXT_MIC_L2 2.2U/6.3V_6 R368 9/5 add de-pop circuit, add C1002,C1003,C1004 Q1005,Q1006,Q1007 R1007,R1008,R1009,R1010,R1011,R1012,R1013,R1014 1K_4 EXT_MIC_R EXT_MIC_L 1K_4 R1007 R1010 7 49 42 43 ALC269Q-VB6-GR 9/5 "PD#" circuit modify 1.delete R650,R372,R373,Q27,Q28,D16,D17,D15 2.add Q1002,Q1003,Q1004,R1004,R1005,R1006 2 +5V AGND Q1005 ME2303T1 *220K_4 ADC_EAPD# 2 SENSE_A R1008 HP_VOLMUTE 0.047U/25V_4 10U/6.3V_8 20K/F_4 C667 2.2U/10V_6 Q1006 AP2302GN 1K/F_4 4.7K_4 2 C1004 R1014 Q1007 R1013 4.7K_4 C661 C666 R615 *0_4 R1012 R1009 *0_4 10/5 change VB6 R1011 *0_4 3 PD# PCBEEP 3 +3V 1 2 4 12 27 CPVEE JDREF LDO_CAP HD_APD#_P4 AMP_BEEP 29 VREF 34 19 28 R654 C668 MIC2-VREFO VREFOUT_AL VREFOUT_AR 3 47 48 DMIC_CLK_R 100/F_4 10P/50V_4 31 30 1K/F_4 1U/10V_4 2 2 AP2302GN 1 SPK-RSPK-R+ [21] DIGITAL_D1 MIC1_VREF_L MIC1-VREFO-R EARP_R EARP_L 3 44 45 10P/50V_4 ALC269_CBN C670 2.2U/10V_6 EARP_R1 R375 30_4 EARP_L1 R374 30_4 1 R_SPKR_SPK+ C674 33 32 1 SPK-L+ SPK-L- ADC_EAPD# HP-OUT-R HP-OUT-L 2 RESET# 40 41 TP80 [21] DIGITAL_CLK 11 L_SPK+ L_SPK- AGND ALC269_CBP 35 ALC269_CPVEE 0_4 0_4 0_4 0_4 *0_4/S SDATA-IN SYNC Analog 3 8 10 AVSS2 AVSS1 C655 *10P/50V_4 ACZ_RST#_AUDIO [7] ACZ_RST#_AUDIO 36 BIT-CLK Digital R645 22_4 HD_SDIN0 ACZ_SYNC_AUDIO [7] ACZ_SDIN0 [7] ACZ_SYNC_AUDIO R384 R668 R579 R583 R383 6 CBP CBN SDATA-OUT DVSS2 PGND PVSS1 PVSS2 [7] BIT_CLK_AUDIO 5 37 26 BIT_CLK_AUDIO C663 *10P/50V_4 PVDD2 9 1 *10P/50V_4 ACZ_SDOUT_AUDIO [7] ACZ_SDOUT_AUDIO DVDD-IO DVDD1 U28 C664 46 9/8 EMI need change to 680p AGND AGND AGND R1004 1K/J_4 R1005 4.7K/F_4 +5V R662 HD_APD#_P4 R1006 SENSE_MIC 2 VOLMUTE# 3 [29] R376 47K_4 2N7002E 3 3 Q1002 CN18 SENSE_A +5VS5 11/12 short 20K/F_4 Q30 DMN601K-7 R361 *0_4/S [8] [8] HDA_BEEP1 2 ** +3V *4.7K/F_4 SENSE_A HP_VOLMUTE Q1004 ACZ_RST#_AUDIO R377 47K_4 2 SENSE_PHONE 3 3 1 1 39.2K/F_4 Q33 DMN601K-7 220P/50V_4 SPKR [29] PC_BEEP_EC 2 [7] EXT_MIC_L EXT_MIC_R R369 *10K/F_4 R366 *150K/F_4 U10 *NC7SZ86 C414 0.1U/10V_4 AMP_BEEP HDA_BEEP2 4 3 R663 2N7002E 2 C415 *0.1U/10V_4 1 AGND 9/8 EMI(near CN18) DUAL USB CONN R370 100K_4 0.1U/10V_4 C413 R367 10K/F_4 2 WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ 2N7002E 1 1 10/11 R361 mount, other unmount Eϱ AGND B C D 1 AGND 10/8 change net name A SENSE_PHONE SENSE_MIC EARP_L EARP_R C1005 5 1 1 1 2 +5V USBP1+ USBP1- [26,29] USB_ENABLE# Q1003 VOLMUTE# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 8/26 A-->B modify Size Custom Document Number Rev A ƵĚŝŽŽĚĞĐ;ZĞĂůƚĞŬͺ>ϮϲϵͿ Date: Monday, November 15, 2010 E Sheet 23 of 40 5 4 10/5 AR8151-AL008151005 C578 C587 C597 C593 C572 2 10U/6.3V_8 10U/6.3V_8 1000P/50V_4 1U/6.3V_4 0.1U/10V_4 C591 C579 AVDDL AVDDL AVDDL AVDDL C590 C585 C594 C566 +3VS5 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 R239 10/11 add D2002 *0_4 3 *0_4 PCIE_WAKE#_R / 0_4 7 1 *RB501V-40 5 4.7K_4 CKREQ_G# 6 7 2.37K/F_4 RBIAS C 10/5 add R2004 for LAN wake up 2 3 4 XTLO_LAN_C 33P/50V_4 2XTLI_LAN_C 25MHZ SMCLK SMDATA 8 XTLO XTLI AR8151-AL1A-R 33P/50V_4 MDI0+ MDI0MDI1+ MDI1MDI2+ MDI2MDI3+ MDI3- Q2001 2N7002E 2 AVDDL_REG AVDDL AVDDL AVDDL AVDDL VDD33 39 38 23 1 [8] PCIE_CLKREQ_LAN# CKREQ_G# 3 R2006 *0_4 LAN_GLINK100# LAN_TX# 10/11 add L15 LX VDDCT C324 C337 C335 C377 6 13 19 31 34 1 25 26 37 24 1 LED_LINK10/100n LED_ACTn CLKREQn/LED2 AR8151 Y2 C325 11 12 14 15 17 18 20 21 VDDCT_REG/CKRn RBIAS 7 TRXP0 TRXN0 TRXP1 TRXN1 TRXP2 TRXN2 TRXP3 TRXN3 $WKHURV PERSTn WAKEn 10 8/26 A-->B modify 9/28 delete short net REFCLKP REFCLKN TX_P TX_N RX_P RX_N *0_8 TEST_RST TESTMODE GND1 AVDDH C598 C583 AVDDH C569 AVDDH C599 1U/6.3V_4 0.1U/10V_4 DVDDL 0.1U/10V_4 DVDDL LX 40 5 4.7uh_C_1A AVDD_CEN C562 C563 C331 C565 C564 0.1U/10V_4 0.1U/10V_4 10U/6.3V_8 1000P/50V_4 0.1U/10V_4 LAN_GLINK100# LAN_TX# LAN_GLED# LAN_YLED C 8/26 A-->B modify 28 27 41 C462 C86 1000P/50V_4 1000P/50V_4 GND GND GND GND GND GND GND GND GND +3VLANVCC R233 R2002 R2004 2 D2002 R542 33 32 30 29 35 36 D +3VLANVCC +3V 8/26 A-->B modify 42 43 44 45 46 47 48 49 50 [29] LAN_REST# [2,8,14,26,27,29] PLTRST# [29] LAN_S5_WAKE# [6,26,27] PCIE_WAKE# 0.1U/10V_4 PCIE_RXP2_LAN_L 0.1U/10V_4 PCIE_RXN2_LAN_L AVDDH AVDDH AVDDH_REG C364 C363 DVDD_REG DVDDL CLK_PCIE_LANP CLK_PCIE_LANN PCIE_RXP2_LAN PCIE_RXN2_LAN PCIE_TXP2_LAN PCIE_TXN2_LAN 16 22 9 [8] [8] [8] [8] [8] [8] U6 11/15 delete R253,R255 Ϯϰ 1U/6.3V_4 0.1U/10V_4 R559 ** 1 Atheros Lan PLACE NEAR LAN IC PIN6 +3VLANVCC AVDDL AVDDL ** D 3 1U/6.3V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 C463 1000P/50V_4 CN11 LAN_YLED R446 330/F_4 12 11 LED_GRE_P LED_GRE_N 10/11 +/- change LAN_TX# B PLACE NEAR LAN IC SIDE C336 C328 C348 C339 C373 C357 C381 A C380 1000P/50V_4 R237 R244 0.1U/10V_4 49.9/F_4 MDI0+ 49.9/F_4 MDI0- 1000P/50V_4 R251 R256 0.1U/10V_4 49.9/F_4 MDI1+ 49.9/F_4 MDI1- 1000P/50V_4 R263 R285 0.1U/10V_4 49.9/F_4 MDI2+ 49.9/F_4 MDI2- 1000P/50V_4 R271 R272 0.1U/10V_4 49.9/F_4 MDI3+ 49.9/F_4 MDI3- 8/31 change R from 0805 to 0402 7 C5455 $ 1 6 ) 2 C548 C547 C5465 C560 C549 C5580 C533 C550( 5 1U/6.3V_4 AVDD_CEN_T L26 PBY160808T-601Y-N_1A LAN_MX3+ 8 LAN_MX37 LAN_MX26 LAN_MX15 LAN_MX1+ 4 LAN_MX2+ 3 LAN_MX0+ 2 LAN_MX01 C55 1000P/50V_4 10 LAN_GLED# 9 5.1K/F_4 +3VLANVCC R60 330/F_4 RX1RX1+ RX0TX1TX1+ RX0+ TX0TX0+ B GND1 14 GND 13 LED_YEL_P LED_YEL_N AVDD_CEN RJ45_CONN U21 *1000P/50V_4 0.1U/10V_4 *1000P/50V_4 0.1U/10V_4 *1000P/50V_4 0.1U/10V_4 *1000P/50V_4 0.1U/10V_4 8/31 exchange RJ45 LED color MDI0+ MDI0MDI1+ MDI1MDI2+ MDI2MDI3+ MDI3- 2 3 5 6 8 9 11 12 TD1+ TD1TD2+ TD2TD3+ TD3TD4+ TD4- MX1+ MX1MX2+ MX2MX3+ MX3MX4+ MX4- 23 22 20 19 17 16 14 13 LAN_MX0+ LAN_MX0LAN_MX1+ LAN_MX1LAN_MX2+ LAN_MX2LAN_MX3+ LAN_MX3- AVDD_CEN_T AVDD_CEN_T AVDD_CEN_T AVDD_CEN_T 1 4 7 10 TCT1 TCT2 TCT3 TCT4 MCT1 MCT2 MCT3 MCT4 24 21 18 15 TERM1 TERM2 TERM3 TERM4 R492 R510 R519 R526 LFE9276A-R D3A: only UMA sku support 1G,If support 10/100 in UMA SKU, R55,R56 5 R105 4 3 75/F_8 75/F_8 75/F_8 75/F_8 F K D Q change J H 5 G TERM9 Re Rd C362 A 1500P/3KV_1808 WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ to 0-ohm Eϱ 2 Size Custom Document Number Rev A >EŽŶƚƌŽůůĞƌ;ƚŚĞƌŽƐͺZϴϭϱϭͿ Date: Monday, November 15, 2010 1 Sheet 24 of 40 A B C D 4 U26 5 4 17 +3VCARD +3V 8/26 A-->B modify +3V [8] [8] [8] C650 0.1U/10V_4 USBP12USBP12+ 2 3 R585 *0_4/S RTS5138_CLK_IN 24 C627 *5.6P/50V_4 CLK_48M_CR C657 4.7U/6.3V_6 R614 1 C649 C637 +3VCARD RTS5138_RREF 1 26.19K/F_4 *100P/50V_4 RTS5138_VREG6 1U/10V_4 25 C648 2.2U/10V_6 R633 150K/F_4 DM DP RT5138 CLK_IN RREF V18 GND SP1 SP2 SP3 SP4 SP5 SP6 SP7 SP8 SP9 SP10 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 7 C611 0.1U/10V_4 C641 0.1U/10V_4 SP12 SP13 SP14 XD_D4 XD_D5 XD_D6 SP12 SP13 SP14 SD_WP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SD_D2 SD_D3 SD_CMD MS_CLK +3VCARD MS_CLK_R MS_D3 MS_INS# MS_D2 MS_D0 R572 33_4 SD_D3 SD_D2 MS_D3 MS_D2 MS_D0 4 MS_D1 MS_BS XD-R/B XD-RE XD-CE XD-CLE XD-ALE XD-WE XD-WP XD-D0 XD-D1 SD-DAT2 SD-DAT3 SD-CMD 4IN1-GND1 MS-VCC MS-SCLK MS-DATA3 MS-INS MS-DATA2 MS-DATA0 SD_CLK_R C612 Ϯϱ MS_CLK MS_INS# SD_D1 SD_D0 SD_D7 SD_CD# SD_D6 SD_CLK SD_D5 SD_CMD CN4 C608 *0.1U/10V_4 MS_CLK_R XD_RDY XD_RE# XD_CE# XD_CLE XD_ALE XD_WE# XD_WP XD_D0 XD_D1 XD_D2 Share Pin RTS5138 +3VCARD 3 SP1 SP2 SP3 SP4 SP5 SP6 SP7 SP8 SP9 SP10 SP11 SP12 SP13 SP14 XD_D7 XD_CD# CARD_3V3 3V3_IN GPIO0 SP1 SP2 SP3 SP4 SP5 SP6 SP7 SP8 SP9 SP10 E C609 MS-DATA1 MS-BS 4IN1-GND2 SD-VCC SD-CLK SD-DAT0 XD-D2 XD-D3 XD-D4 SD-DAT1 XD-D5 XD-D6 XD-D7 XD-VCC XD-CD-SW SD-WP-SW SD-CD-SW 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 SHIELD1-GND SHIELD2-GND SHIELD3-GND SHIELD4-GND 37 38 41 42 MS_D1 MS_BS SD_CLK_R SD_D0 +3VCARD 33_4 R573 SD_CLK SD_D1 3 SD_WP SD_CD# CONN_CARDREADER_CM3S-015 *10p/50V_4 +3VCARD R571 *10K/F_4 C628 *270P/25V_4 *10p/50V_4 XD_WP ^LJƐƚĞŵ^ĐƌĞǁ,ŽůĚ XD_RDY HS1 *H-C315D110P2 HS2 *H-C315D110P2 9/9 ME modify FP HS3 *H-C236D110P2 HS4 *O-TWH-4 HS5 *h-tc472bc315d110p2 HS6 *H-C315D110P2 HS7 *h-tc472bc315d110p2 HL1 *H-C394D157P2 H5 H3 *H-TS394BC315D110P2 *H-TS394BC315D110P2 H1 *h-tr315x295br394x295d110p2 H6 H7 *O-TWH-2 *H-C110D110N 1 H2 *H-C110D110N H8 *O-TWH-3 P2 P3 P4 P5 P6 P7 P8 B2 1 1 1 1 1 1 1 1 1 1 1 1 1 P10 P11 P13 P12 P14 B3 1 1 1 1 1 1 P9 1 1 1 WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ Eϱ B 1 ^LJƐƚĞŵWĂĚ;ƵƚƚŽŶͿ 1 NL1 *H-C256D161P2 9/6 delete MDC function ND1,ND2 A H10 *O-TWH-3 1 NS1 *H-C256D67P2 1 NP2 *H-C256D122P2 1 NP1 *H-C256D122P2 1 W,Eh^ĐƌĞǁ,ŽůĚ 1 1 1 1 DEh^ĐƌĞǁ,ŽůĚ H9 *O-TWH-3 P1 1 HG3 *H-TC276BC197D150P2 1 HG2 *H-TC276BC197D150P2 1 HG1 *H-TC276BC197D150P2 1 HC4 *H-TC276BC197D150P2 1 HC3 *H-TC276BC197D150P2 ^LJƐƚĞŵWĂĚ;dŽƉͿ 1 1 1 1 H4 *H-TS394BC315D110P2 'WhƌĂĐŬĞƚ HC2 *H-TC276BC197D150P2 1 WhƌĂĐŬĞƚ HC1 *H-TC276BC197D150P2 1 1 1 2 1 2 C D Size Custom Document Number Rev A ƵĚŝŽŽĚĞĐ;ZĞĂůƚĞŬͺ>ϮϲϵͿ Date: Monday, November 15, 2010 E Sheet 25 of 40 5 4 3 2 1 +1.05V +3V_VL801 R3023 R1109 +3VSUS 0_8 +1.0VL C687 *0_8 +1.1V_VL801 C1109 +3.3VAUX L32 R1107 +1.0VE 0_8 L1101 HCB1608KF-181T15_6 L1102 HCB1608KF-181T15_6 +1.0VE 0.1U/10V_4 HCB1608KF-181T15_6 +3VSUS C623 C1102 C1103 0.1U/10V_4 3 +1.0VL 0.01U/16V_4 1 1 C1105 3 C1107 C1110 C1106 10U/6.3VS_6 D [8] PCIE_TXP3_USB3 [8] PCIE_TXN3_USB3 30 31 0.1U/10V_4 PCIE_RXP3_USB3_C PCIE_RXN3_USB3_C 0.1U/10V_4 PEXRX0+ PEXRX0- 33 34 PEXTX0+ PEXTX0- 10K/F_4 PLTRST#_VL801 60 PEXRST# 51 PEXCPPE# [2,8,14,24,27,29] C678 R659 PLTRST# PEXCPPE# TP1104 R582 0_4 ** [6,24,27] PCIE_WAKE# 2 25 63 R1101 R1102 R1103 6.04K 3.01K 4.7K_4 SPICS# SPISCLK SPISI SPISO R683 [8] CLK_25M_USB3.0 *0_4 87 88 8/26 A-->B modify B 37 38 39 40 R593 SSREXT PEXREXT TESTEN 69 68 USBHPE1# USBHOC1# 46 50 R3010 USBHP2USBHP2+ 84 83 USB30P1USB30P1+ SSRX2SSRX2+ 81 80 USB30_RX1USB30_RX1+ SSTX2SSTX2+ 78 77 USB30_TX1USB30_TX1+ USBHPE2# USBHOC2# 43 49 SSXI SSXO VSS_OSC 55 56 57 2 +3.3VAUX SSRX3SSRX3+ 8 7 SSTX3SSTX3+ 5 4 10K/F_4 R649 +3.3VAUX USB_HPE# 10K/F_4 +1.0VL C630 C626 C677 C665 C669 C647 C620 C692 C660 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 C640 C671 C680 0.01U/16V_4 0.01U/16V_4 0.01U/16V_4 42 48 USBHP4USBHP4+ 21 20 SSRX4SSRX4+ 18 17 SSTX4SSTX4+ 15 14 USBHPE4# USBHOC4# 41 47 GPIO3 RMTWKEN# LOPWREN# 18P/50V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 C683 C672 0.01U/16V_4 0.01U/16V_4 C682 C636 0.01U/16V_4 0.01U/16V_4 C676 C684 0.01U/16V_4 0.01U/16V_4 USB3.0 X 2/USB2.0 COMBO R194 0_4 1 4 2 3 USB 3.0 *WCM2012-90 R190 0_4 USB30_TX2USB30_TX2+ *0_4 CN14 USB3.0 CONN +5VSUS_USBP0 USB30P1-_C USB30P1+_C RP4 R653 [8] [8] USB_HPE# 10K/F_4 C RP3 USB30_RX2USB30_RX2+ +3.3VAUX 4 1 USBP2USBP2+ 3 2 *WCM2012-90 R208 *0_4 8/26 A-->B modify USB30_TX1USB30_TX1+ USB30_RX1USB30_RX1+ 0.1U/10V_4 USB30_TX1-_C 0.1U/10V_4 USB30_TX1+_C C302 C298 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+ USB30P1-_C C536 USB30P1+_C C534 1 2 *Clamp-Diode B R3011 10K/F_4 GPIO3 R3012 10K/F_4 LOPWREN# R3013 10K/F_4 +3.3VAUX 1 2 *Clamp-Diode R245 0_4 RMTWKEN# USB30P2USB30P2+ *10K/F_4 R3015 *10K/F_4 R248 R3016 10K/F_4 C614 *220U/6.3V_6X4.5ESR18 CN16 USB3.0 CONN +5VSUS_USBP0 USB30P2-_C USB30P2+_C 3 2 *WCM2012-90 R252 *0_4 8/26 A-->B modify USB30_RX2USB30_RX2+ +5VSUS_USBP0 8 7 6 5 C606 C607 C610 + USB30_TX2USB30_TX2+ + USB30P2-_C C574 USB30P2+_C C573 470P/50V_4 0.1U/10V_4 1 2 1 2 0.1U/10V_4 USB30_TX2-_C 0.1U/10V_4 USB30_TX2+_C C326 C327 1 2 3 4 5 6 7 8 9 *Clamp-Diode 1 2 3 4 5 6 7 8 9 VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+ 13 12 11 10 C596 G547E2P81U C605 1U/6.3V_4 1 *2.2U/6.3V_6 OUT3 OUT2 OUT1 OC USBP4USBP4+ 1 0_4 VIN1 VIN2 EN GND 4 1 USB 3.0 *0_4 RP10 2 2 3 4 1 1 R3009 [23,29] USB_ENABLE# *0_4 2 R3008 2 3 R3014 U25 USB_HPE# 1 4 *WCM2012-90 R240 0_4 +5VS5 R3021 *100K/F_4 1 1 C638 C675 C642 RP9 Q3004 2 C3011 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 +3.3VAUX 1 *0.1U/10V_4 C651 C662 C629 USB30P1USB30P1+ C625 2 R3020 *100K/F_4 +3V_VL801 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 R199 +3.3VAUX 2 *0_4 C3010 +1.0VE C654 C658 C681 +3.3VAUX [8] [8] PLTRST#_VL801 R3019 Q1101 USB30P2USB30P2+ 11 10 USBHPE3# USBHOC3# PORT4 C3004 *1U/6.3V_4 +3.3VAUX 2 24 26 29 32 35 SPICS# SPISCLK SPISI SPISO 2 25MHZ 18P/50V_4 SSTX1SSTX1+ PORT3 1M/F_4 1 SSRX1SSRX1+ USBHP3USBHP3+ Y6 C624 VCCA33REG25 VCCA33REG12 VCCA33PEXRX VCCA33PEXM VCCA33PEXTX VCCA10SSRX3 VCCA10SSRX4 VCCA10SSRX1 VCCA10SSRX2 VCCA10SSM 23 36 53 65 66 67 JTAGCK SMI# PEXW AKE# SMCLK SMDAT GND GND_PAD +3.3VAUX 52 58 59 61 62 0_4 4.7K_4 10K/F_4 10K/F_4 10K/F_4 0_4 *4.7K_4 *4.7K_4 *0_4 13 89 R646 R644 R1104 R1105 R1113 R656 R651 R655 USB3_SMI# VSUSUSB [7] 75 74 PORT2 10K/F_4 *10K/F_4 1 R3024 GPIO3 RMTWKEN# LOPWREN# R658 +3.3VAUX C PEXCPPE# R1108 D 0.01U/16V_4 0.01U/16V_4 C1104 *1U/6.3V_4 72 71 VIA VL801 *0_4 PEXCPPE# C1108 *1U/6.3V_4 USBHP1USBHP1+ PORT1 11/15 add for S3 issue debug R1110 0.1U/10V_4 13 12 11 10 C679 [8] PCIE_RXP3_USB3 [8] PCIE_RXN3_USB3 8/26 A-->B modify Q1102 *ME2303T1 13 12 11 10 PEXCLK+ PEXCLK- *ME2303T1 13 12 11 10 27 28 VDD VDD VDD VDD VDD VDD VCCA33SSM VCCA33SS3 VCCA33SS3 VCCA33SS4 VCCA33SS4 VSUS33 VSUS33 VSUS33 VSUS33 VCCA33SS1 VCCA33SS1 VCCA33SS2 VCCA33SS2 [8] CLK_PCIE_USB3P [8] CLK_PCIE_USB3N 6 16 70 79 86 0.1U/10V_4 3 9 12 19 22 44 45 54 64 73 76 82 85 0.01U/16V_4 U27 220U/6.3V_6X4.5ESR18 470P/50V_4 11/10 modify *ME2303T1 A Q3005 3 2 R3022 *100K/F_4 PEXCPPE# C3012 *0.1U/10V_4 10/5 5 Support flash MX25L512, MX25L5121E, SST25VF512, SST25VF010A EN25F05, EN25F10 4 +3V_VL801 R1106 SPICS# SPISCLK SPISI SPISO 1 6 5 2 10K/F_4 3 *Clamp-Diode 11/10 cost down U1101 *ME2303T1 3 A Ϯϲ 11/12 add +3V check ?? +3V_VL801 CE# SCK SI SO VDD 8 HOLD# 7 W P# VSS 4 WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ C1101 [2,6,7,8,9,10,12,13,14,21,22,23,24,25,27,28,29,34,36,37,39] 0.1U/10V_4 EN25F05 3 +3V [10,21,23,31,32,33,34,35,36,37,38,39,40] +5VS5 [36] +3VSUS [33] +1.1V_VL801 2 Eϱ Size Custom Document Number Rev A h^ϯ͘ϬŽŶƚƌŽůůĞƌ;d/ͺdh^ϳϯϮϬͿ Date: Monday, November 15, 2010 1 Sheet 26 of 40 A B C 9/4 1.change net name "+MINIEC_5V" to "INT_BT_OFF#" 2.add R1003, net name "INT_BT_OFF#" DŝŶŝĂƌĚ t>Eͬd;KƉƚŝŽŶͿ D E Ϯϳ +1.5V_CPU +3V +1.5V_CPU C425 C427 C429 +3V_WLAN_P 10U/6.3VS_6 0.1U/10V_4 0.01U/16V_4 +3V_WLAN_P R21 C19 C17 C428 C426 *0_8 10U/6.3VS_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 CN8 9/3 delete BT function (USB) delete net "BLUELED", R18 WLAN_LED# R19 R680 10K/F_4 +3V_WLAN_P *0_4 USBP10+ USBP10- [8] [8] 1 RF_LINK# [29] Q6 10K/F_4 1 RB501V-40 RF_PWR_OFF# [9] RF_PWR_OFF# RF_OFF# [9] [29] RF_PWR_ON R17 0_4 R20 *0_4 R25 *100K/F_4 Q7 DTC144EUA 2 Avoid leakage issue 9/6 power changed from +3V to +3V_WLAN_P 9/6 R17-stuff, R20-unstuff +3V_WLAN_P PIN44 2 LAD0 LAD1 LAD2 LAD3 LFRAME# R386 D24 2 LAD0 [7,29] LAD1 [7,29] LAD2 [7,29] LAD3 [7,29] LFRAME# [7,29] 4 ME2303T1 9/6 add "RF_PWR_OFF#" control from PCH 11/11 mount +3V_WLAN_P WLANE_PLTRST# 3 R22 4.7K_4 DŝŶŝĂƌĚZĞƐĞƚ WLAN_LED# 1 Q54 +3V MLX_67910-5700 R24 *0_4 3 WLANE_PLTRST# R23 100/F_4 PLTRST# 2 WLAN_RST_OUT 4 3 1 C18 0.1U/10V_4 +3V_WLAN_P PIN7 5 D/W/ yWͲϭϳϳϱϴϯϴͲϭͲϱϮW 3 RF_LINK# 2N7002 R196 +3V_WLAN_P PLTRST# PLTRST# [2,8,14,24,26,29] 3 2 52 2 24 41 39 44 46 42 38 36 32 30 22 20 16 14 12 10 8 50 40 34 26 18 4 9 +3.3V +3.3V +3.3Vaux Reserved Reserved LED_WLAN# LED_WPAN# LED_WWAN# USB_D+ USB_DSMB_DATA SMB_CLK PERST# W_DISABLE# Reserved Reserved Reserved Reserved Reserved GND GND GND GND GND GND GND 2 +1.5V +1.5V +1.5V Reserved Reserved Reserved Reserved Reserved Reserved PETp0 PETn0 PERp0 PERn0 REFCLK+ REFCLKCLKREQ# BT_CHCLK BT_DATA WAKE# Reserved Reserved GND GND GND GND GND 3 4 1 6 28 48 R266 *0_6 INT_BT_OFF# 51 +5V R681 *0_4 49 [29] EC_DEBUG1 47 0_4 INT_BT_OFF# R1003 45 19 [8] CLK_33M_DEBUG PLTRST# 17 33 9/28 modify[8] PCIE_TXP1 31 [8] PCIE_TXN1 25 [8] PCIE_RXP1 23 [8] PCIE_RXN1 13 [8] CLK_PCIE_WLANP 11 [8] CLK_PCIE_WLANN R682 *0_4 REQ_WLAN# 7 [8] PCIE_CLKREQ_WLAN# R27 *0_4 BT_COMBO_EN#15 [8] BT_COMBO_EN# 3 MINICAR_PME# 1 43 37 35 29 27 21 15 EC debug pin 10K/F_4 REQ_WLAN# 1 Q52 3 PCIE_CLKREQ_WLAN# 2N7002 U2 MC74VHC1G08DFT2G +3V_WLAN_P PIN5 ^ƵƉƉŽƌƚtĂŬĞ&ƵŶĐƚŝŽŶ;ZĞƐĞƌǀĞͿ R265 10K/F_4 +3VPCU LGE mini-pcie power status WLAN Bluetooth +3V_WLAN_P [6,24,26] PCIE_WAKE# &Žƌ D/^ƵŐŐĞƐƚŝŽŶ 1 MINICAR_PME# *DTC144EUA 3 Q8 CLK_33M_DEBUG R26 C21 *0_4 *33P/50V_4 2 Radio-ON Radio-ON Power-ON Radio-ON Radio-OFF Power-ON Radio-OFF Radio-ON Power-ON Radio-OFF Radio-OFF Power-OFF 3 BT_COMBO_EN#1 Q53 BT_COMBO_EN# 2 DTC144EUA 1 *10K/F_4 2 R31 2 +3V_WLAN_P PIN19,51 ;KƌĂŶŐĞͿ LED1 [29] [29] 4 BATLOW# 3 MBATLED0# R381 2 R382 1 R1001 10K/F_4 DŽŶŶĞĐƚŽƌ;KƉƚŝŽŶͿ 150_6 +3VPCU 39_6 INT_BT_OFF# 3 19-22SURSYGC/S530-A2/TR8 Q1001 ;tŚŝƚĞͿ ;tŚŝƚĞͿ 9/3 delete MDC function R538, C570 CN15 C308, R192, R193, C307, C309, C306, C305 "ACZ_SDOUT_MDC" "ACZ_SYNC_MDC" "ACZ_SDIN1" "ACZ_RST#_MDC" "BIT_CLK_MDC" LED2 [7] SATA_R_LED1 SATA_LED# R380 150_6 +3V ;tŚŝƚĞͿ R379 *0_4 LED3 RF_LED# 3 RF_LINK# RFON_R_LED1 R385 150_6 +3V Q29 DTC144EUA 1 3 [29] 2 Q32 ME2303T1 R1002 *0_4 9/4 Intel COMBO card control circuit 1.add R1001,R1002,Q1001 2.add net name"INT_BT_COMBO_EN#" -> "INT_BT_OFF#" 9/3 delete BT function (USB) delete net "BLUELED", Q31 Eϱ B 1 WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ RF_LINK# A INT_BT_COMBO_EN# 2 DTC144EUA 1 R378 1 10K/F_4 2 +3V_WLAN_P [8] INT_BT_COMBO_EN# 1 > ^ƚĂƚƵƐ C D Size Custom Document Number Rev A ƵĚŝŽŽĚĞĐ;ZĞĂůƚĞŬͺ>ϮϲϵͿ Date: Monday, November 15, 2010 E Sheet 27 of 40 A B C 7 NBSWON1# 220P/50V_4 C448 WŝŶϭ͗нϯsWh;>/^t/d,WtZͿ WŝŶϮ͗WKt Z> WŝŶϯ͗>/^t/d, WŝŶϰ͗'E WŝŶϱ͗'E WŝŶϲ͗WKt ZKEη WŝŶϳ͗E WŝŶϴ͗E 8 4 C1008 CN10 +5V_FAN [29] PWR_LED# [21,29] LID_EC# [29] 2.2U/6.3V_6 0.1U/10V_4 1 2 3 4 5 6 C1009 C1010 CN2 PWR BTN CONN 220P/50V_4 220P/50V_4 WͬE͗&&ϬϲDZϬϬϭ WͬE͗&&Ϭϲ&ZϬϲϮ [29] 1 2 3 0.1U/10V_4 FAN1SIG R437 +3V Ϯϴ ͲƐƚĂŐĞĐŚĂŶŐĞĨŽŽƚƉƌŝŶƚƚŽ>ϭϮϭͲϭϮZͲdEͲϭϮWͲ> C449 +3VPCU E dŽƵĐŚWĂĚŽŶŶĞĐƚŽƌ Wh&E WŽǁĞƌŽƚƚŽŶŽŶŶĞĐƚŽƌ C93 D C452 C451 4.7K_4 1 2 3 ϮϱŵŝůƐ 4 4 FAN CONN [29] [29] 1U/6.3V_4 4.7K_4 4.7K_4 TPCLK L8 TPDATA L7 TPCLK TPDATA 0.1U/10V_4 0.1U/10V_4 CN3 R58 R59 WͬE͗&,ϬϯDZϬϮϲ WͬE͗&,ϬϯDZϬϮϵ 1000P/50V_4 C118 C105 +5V +3V 4 BLM18BA470SN1 BLM18BA470SN1 TPCLK-1 TPDATA-1 U13 2 +5V +5V THERM_OVER# 10K/F_4 R423 [29] 9/8 EMI(near CN2) VIN VO GND /FON GND GND VSET GND 1 4 VFAN +5V_FAN 3 5 6 7 8 G991PV11 TP_L TP_R C116 C117 10P/50V_4 10P/50V_4 8/31 exchange TP_L and TP_R SW2 3 4 6 TP_R TP_L 1 2 5 SW1 3 4 6 C1006 1 2 5 ^d,ŽŶŶĞĐƚŽƌ R231 *0_8 TOUCH PAD CONN WͬE͗&&ϭϮ&ZϮϵϯ dŽŶŶĞĐƚŽƌ +5V 25 26 220P/50V_4 9/8 EMI(near CN3) TMG-533-S-V-TR +3V C1007 220P/50V_4 TMG-533-S-V-TR +3V_HDD1 23 24 12 11 10 9 8 7 6 5 4 3 2 1 3 3 J3 SATA HDD C299 C303 C310 C313 +5V: 2 A(4 Pin) +3V_HDD1 1 22 +3V: 2 A(4 Pin) *10U/6.3V_8 10U/6.3VS_6 4.7U/6.3V_6 0.1U/10V_4 Gnd : (5 Pin) 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C320 C323 +5V SATA_TXP0_D C371 SATA_TXN0_D C368 0.01U/16V_4 0.01U/16V_4 SATA_RXN0_D C354 SATA_RXP0_D C347 0.01U/16V_4 0.01U/16V_4 8/31 delete BT function (USB) delete CN20, net "BT_OFF#","BLUELED","USB8+","USB8-" SATA_TXP0 [7] SATA_TXN0 [7] <ĞLJďŽĂƌĚŽŶŶĞĐƚŽƌ SATA_RXN0 [7] SATA_RXP0 [7] +3VPCU 26 +3V_HDD1 *10U/6.3V_8 *0.1U/10V_4 RP1 MY4 MY5 MY6 MY7 10 9 8 7 6 1 2 3 4 5 10 9 8 7 6 10P8R-8.2K RP2 1 2 3 4 5 2 +5V ^dKŽŶŶĞĐƚŽƌ +5V MY12 MY13 MY14 MY15 +5V_ODD +12VALW R55 2 1 Q14 *AO3404 +5V_ODD 3 1 2 2 C50 *0.027U/25V_6 [7] SATA_RXN1 [7] SATA_RXP1 [9] ODD_PRSNT# +5V_ODD C156 C150 EJECT# EJECT# 0.01U/16V_4 0.01U/16V_4 SATA_TXP1_D SATA_TXN1_D 2 3 0.01U/16V_4 SATA_RXN1_D 0.01U/16V_4 SATA_RXP1_D 1 2 R80 1K/F_4 5 6 8 9 10 11 1 4 7 12 13 1 R73 +5V_ODD 3 1 Q11 *2N7002 CN12 C190 C183 2 R49 1 *0_4 ϭϮϬŵŝůƐ 1 2 Q12 *2N7002 C433 C434 C435 C440 C438 C65 C85 C73 C64 220P/50V_4 220P/50V_4 220P/50V_4 220P/50V_4 MX4 MX6 MX3 MX2 C68 C70 C67 C66 220P/50V_4 220P/50V_4 220P/50V_4 220P/50V_4 MY5 MY6 MY3 MY7 C74 C75 C72 C76 220P/50V_4 220P/50V_4 220P/50V_4 220P/50V_4 MY8 MY9 MY10 MY11 C77 C78 C79 C80 220P/50V_4 220P/50V_4 220P/50V_4 220P/50V_4 10U/6.3VS_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 2 ODD_EJECT# *0_4 TXP TXN MX7 MX0 MX5 MX1 C71 C62 C69 C63 220P/50V_4 220P/50V_4 220P/50V_4 220P/50V_4 RXN RXP DP +5V +5V MD GND1 GND2 GND3 GND GND MY12 MY13 MY14 MY15 C81 C82 C83 C84 220P/50V_4 220P/50V_4 220P/50V_4 220P/50V_4 S1 14 14 16 16 [29] [29] MY[0..15] MX[0..7] MY[0..15] MX[0..7] S7 P1 17 17 15 15 1 CN1 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 2 6906-25 WͬE͗&&Ϯϰ&ZϬϯϬ 1 WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ 2 EJECT# *10K/F_4 [2,4,10,27] +1.5V_CPU [2,6,7,8,9,10,12,13,14,21,22,23,24,25,26,27,29,34,36,37,39] +3V [6,7,10,21,22,23,27,36] +5V 9/6 "EJECT#" pull high to 3V B MY2 MY15 MY14 MY13 MY12 MY11 MY10 MY9 MY8 MY7 MY6 MY5 MY4 MY3 MX7 MX6 MY2 MX5 MX4 MX3 MX2 MY1 MY0 MX1 MX0 P6 SATA ODD +3V 1 R64 A MY1 MY2 MY4 MY0 10P8R-8.2K SATA_TXP1 SATA_TXN1 [7] [7] R54 *22_8 [29] 1 ODD_PD 2 [29] MY11 MY10 MY9 MY8 9/6 R55 stuff 8/26 A-->B modify 3 R65 *330K_6 0_8 C52 0.1U/10V_4 MY3 MY2 MY1 MY0 27 8/31 exchange net name RXN and RXP C D Eϱ Size Custom Document Number Rev A ƵĚŝŽŽĚĞĐ;ZĞĂůƚĞŬͺ>ϮϲϵͿ Date: Monday, November 15, 2010 E Sheet 28 of 40 5 4 3 2 1 Ϯϵ +3V_RTC +3V_ECACC L14 BK1608HS220-T +3VPCU R305 *0_4 C322 1U/6.3V_4 [22] HDMI_HPD [28] [28] TPDATA TPCLK [28] CB/LG ODD_PD TPDATA TPCLK CB/LG [31,32,33,34,35,37,38] HWPG [21] LID_CONTROL [27] RF_PWR_ON 1 2 GPIO33_E D2001 *RB501V-40 10/11 add [27] EC_DEBUG1 [23,26] USB_ENABLE# EC_SCK EC_SO EC_SI EC_CE# [28] [28] B [28] [6] PCH_SUSCLK EJECT# MY[0..15] MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15 MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7 MX[0..7] R299 *0_4 86 85 PS2DAT2/WUI21/GPF5 PS2CLK2/WUI20/GPF4 80 104 33 88 81 87 108 109 DAC4/DCD0#/GPJ4 DSR0#/GPG6 GINT/CTS0#/GPD5 PS2DAT1/RTS0#/GPF3 DAC5/RIG0#/GPJ5 PS2CLK1/DTR0#/GPF2 RXD/SIN0/GPB0 TXD/SOUT0/GPB1 106 105 GPG0 FSCK 103 102 101 100 FMISO FMOSI FSCE# SSCE0#/GPG2 EC_CK32K 128 EC_CK32KE 2 1 R300 0_4 4 IT8518E 2 127 [6] KSO16/SMOSI/GPC3 KSO17/SMISO/GPC5 56 57 EC_PWROK [6] SUSACK# [6] L80HLAT/BAO/WUI24/GPE0 L80LLAT/WUI7/GPE7 19 20 107 99 98 97 96 95 94 93 Ra R207 H_PROCHOT#_Q R210 *10K_4 TWH Ra NC Rb 117 118 110 111 115 116 C391 *10P/50V_4 Q24 2N7002 R221 100K_4 SUSON [32,33,36] LAN_REST# [24] MBATLED0 H_SI R236 H_SO R232 H_CLK R229 H_SCE# R218 0_4 0_4 0_4 0_4 +3VPCU PCH_SPI_SI [7] PCH_SPI_SO [7] PCH_SPI_CLK [7] PCH_SPI_CS0# [7] MAINON [30,32,33,34,35,36,37,38] RF_LINK# [27] CLKRUN# [6] PWR_LED# [28] R277 10K_4 BATLOW# [27] PWR_LED C 2 BATLOW Q26 2N7002E EC_PECI_R R260 SLP_SUS# MBCLK MBDATA MBCLK2 MBDATA2 MBCLK MBDATA MBCLK2 MBDATA2 [6] [30] [30] For [8,13,17] [8,13,17] 43_4 EC_PECI 2 Q21 2N7002E C372 0.1U/10V_4 [2] MBATLED0# [27] Battery charge/charge and cap board For PCH SMB/DDR Thermal IC/VGA MBATLED0 2 Q25 2N7002 UART PWM PWM0/GPA0 PWM1/GPA1 PWM2/GPA2 PWM3/GPA3 PWM4/GPA4 PWM5/GPA5 PWM6/SSCK/GPA6 PWM7/GPA7 24 25 28 29 30 31 32 34 TACH0/GPD6 TACH1/TMA1/GPD7 47 48 FAN1SIG S5_ON 120 124 SUSC# [6] LAN_S5_WAKE# [24] TMR0/WUI2/GPC4 TMR1/WUI3/GPC6 Num LK SATA5GP LAN_POWER [36] TP45 AC_PRESENT [6] SATA5GP [9] PWM_VADJ [21] SUS_PWR_ACK [6] VOLMUTE# [23] PC_BEEP_EC [23] thermal shutdown circuit [28] [31] MBCLK R247 MBDATA R250 LAN_S5_WAKE# R278 10K_4 10K_4 *10K_4 10/9 remove 125 18 21 WUI5/GPE5 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 35 112 WAKE UP KBMX NBSWON1# PWR_LED ADC0/GPI0 ADC1/GPI1 ADC2/GPI2 ADC3/GPI3 ADC4/WUI28/GPI4 ADC5/WUI29/GPI5 ADC6/WUI30/GPI6 ADC7/WUI31/GPI7 NBSWON1# [28] LID_EC# [21,28] ACIN [30] SUSB# 66 67 68 69 70 71 72 73 CLOCK R195 C398 *10P/50V_4 IT8502_AGND For SG/DIS 8/26 A-->B modify R224 R223 R212 DGPU_HOLD_RST# [9,14] VFAN [28] DNBSWON# [6] 10K/F_4 *0_4 DGPU_OVT# [17] +1.05V_VTT 220P/50V_4 1 PM_THRMTRIP# [2,9] *MMBT3904-7-F SPI FLASH MX25L3205DM2I-12G: AKE39FP0Z00 W25X32VSSIG: AKE39ZP0N00 DGPU_PWROK [9,14,37] Socket: DG008000031 +3VPCU *100K_4 *0_4 For SG/DIS Mount for Optimus DGPU_PWR_EN [9,37,38] 8/26 A-->B modify U20 EC_CE# EC_SCK R533 EC_SI R532 EC_SO R494 7/27:Add R399 for EC request +3VS5 +3VPCU 47_4 47_4 15_4 R493 1 EC_SCK_R 6 EC_SI_R 5 EC_SO_R 2 10K_4 3 CE# SCK SI SO VDD HOLD# WP# VSS 8 7R534 4 10K_4 C561 0.1U/10V_4 A SPI Flash Socket WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ C394 0.1U/10V_4 D6 DGPU_HOLD_RST# RB501V-40 1 OVT_DETC 2 Mount for Optimus IT8502_AGND 4 R184 *4.7K/F_4 C304 8/26 A-->B modify 3 1 VGA_OVT# *RB501V-40 10/11 add TP78 TP79 DGPU_PR_EN_E 76 *0_4 77 R679 78 RB501V-40 79 D8 2 D5 PV Change 3 GFX_HWPG [39] SYS_I [30] AD_AIR [30] TEMP_MBAT [30] EC_GPXD1 1 EC_PWROK RB501V-40 EC_CT_UP Q22 1U/10V_4 +3V 2 D7 B *MMBT3904-7-F SYS_SHDN-1# *10K_4 *10K_4 10K_4 10K_4 [6] For UMA only DAC0/GPJ0 DAC1/GPJ1 DAC2/GPJ2 DAC3/GPJ3 R220 R219 R254 R261 TP77 C2004 A/D D/A TPCLK TPDATA MBCLK2 MBDATA2 R191 10K/F_4 Q23 2 OVT_DETC +3V 9/28 remove R219,R220 PWRSW/GPE4 RI1#/WUI0/GPD0 RI2#/WUI1/GPD1 EC_WRST +3VPCU BK1608HS121-T 5 H_PROCHOT# [2,39] 2 *32.768KHZ L13 0_4 3 H_PROCHOT#_EC NBSWON1# SMCLK2/WUI22/GPF6/PECI SMDAT2/WUI23/GPF7 SMCLK0/GPB3 SMDAT0/GPB4 SM_BUS SMCLK1/GPC1 SMDAT1/GPC2 PS/2 D C321 0.1U/10V_4 3 VSTBY 3 74 VBAT AVCC SLP_A# SBUSY/GPG1/ID7 HMOSIGPH6/ID6 HMISO/GPH5/ID5 HSCK/GPH4/ID4 HSCE#/WUI19/GPH3/ID3 CTX1/WUI18/GPH2/SMDAT3/ID2 CRX1/WUI17/GPH1/SMCLK3/ID1 CLKRUN#/WUI16/GPH0/ID0 FLASH KSO0/PD0 KSO1/PD1 KSO2/PD2 KSO3/PD3 KSO4/PD4 KSO5/PD5 KSO6/PD6 KSO7/PD7 KSO8/ACK# KSO9/BUSY KSO10/PE KSO11/ERR# KSO12/SLCT KSO13 KSO14 KSO15 KSI0/STB# KSI1/AFD# KSI2/INIT# KSI3/SLIN# KSI4 KSI5 KSI6 KSI7 CK32K CK32KE EGAD/WUI25/GPE1 GPIO PS2DAT0/TMB1/GPF1 PS2CLK0/TMB0/GPF0 Y3 A [39] IT8518/BX 90 89 36 37 38 39 40 41 42 43 44 45 46 51 52 53 54 55 58 59 60 61 62 63 64 65 VRON 82 C342 0.1U/10V_4 +3VPCU 10K_4 CB/LG 1 GPC0 TMA0/GPB2 BATLOW 84 83 C359 0.1U/10V_4 1 H_PROCHOT#_EC HDMI_HPD C396 0.1U/10V_4 2 [7] 119 123 D/C# RSMRST# C343 0.1U/10V_4 1 [30] [6] Rb R222 EGCLK/WUI27/GPE3 EGCS#/WUI26/GPE2 VCORE TP42 Select Pin C397 0.1U/10V_4 TWH Select 12 D12 EC_RCIN# LPC GA20/GPB5 SERIRQ ECSMI#/GPD4 ECSCI#/GPD3 WRST# KBRST#/GPB6 PWUREQ#/BBO/GPC7 AVSS RB501V-40 RB501V-40 EC_WRST RB501V-40 LPCPD#/WUI6/GPE6 75 C D13 D14 17 126 5 15 23 14 4 16 VSS VSS VSS VSS VSS [9] RB501V-40 VSS SLP_S5 D11 LAD0 LAD1 LAD2 LAD3 LPCRST#/WUI4/GPD2 LPCCLK LFRAME# 1 [6] [9] EC_A20GATE [7] SERIRQ [9] SIO_EXT_SMI# [9] SIO_EXT_SCI# 10 9 8 7 22 13 6 27 49 91 113 122 [7,27] LAD0 [7,27] LAD1 [7,27] LAD2 [7,27] LAD3 [2,8,14,24,26,27] PLTRST# [8] CLK_33M_KBC [7,27] LFRAME# VCC VSTBY VSTBY VSTBY VSTBY VSTBY U7 C395 0.1U/10V_4 BK1608HS121-T +3VPCU C378 0.1U/10V_4 11 26 50 92 114 121 R309 470K_4 EC_WRST IT8502_AGND L16 0.1U/10V_4 2 C393 IT8502_AGND +3v_STBY C392 0.1U/10V_4 1 R306 0_4 C319 1000P/50V_4 3 +3VPCU 12 MILS 3 +3V Layout Note: Place all capacitors close to IT8502N. +3VPCU *0_4/S 1 +3VPCU 1 2 D +VCC_RTC R310 3 1 +VCC_RTC 3 2 Eϱ Size Custom Document Number ŵďĞĚĚĞĚŽŶƚƌŽůůĞƌ;/d ͺ/dϴϱϬϮͿ Date: Monday, November 15, 2010 1 Sheet 29 of Rev A 40 5 4 3 2 1 ϯϬ PR17 PR2 330_4 8681_VDDP 12 8681B_2 1 BAS316/DG +VAD_2 DCIN 1 2 PQ38 AON7702 VAC 17 PR10 0_4 2 PC19 0.01U/50V_4 2 1 2 PC270 1 8681ICHM 1 PC158 0.1U/25V_4 PR159 *0_2/S PR163 *0_2/S PR22 10/F_4 8681ICHP PD15 RB501V-40 2 8681ICSP1 2 8681ICHM1 PR25 10/F_4 B 3ODFHWKLVFDS FORVHWR,& 2 1 SYS_I [29] PC8 0.01U/50V_4 2 1 8681IAC 1 PC1 0.47U/10V_4 2 1 PV_Update 2010/11/12 PC148 PR11 10/F_4 2 Place this cap close to EC PC17 1U/10V_4 2 PR24 12.4K/F_4 4 2 1 PC123 0.1U/10V_4 ICHM GND AD_AIR 5 1 1 ICHP COMP 1 PC149 PC161 2200P/50V_4 PC3 1U/25V_8 8 1 5 4 10_8 COMP [29] PR169 2.2_8 OZ8681 PR9 PR16 75K/F_4 B 8681LR 16 8681LDR IAC 2 14 8681LX 7 +VAD_1 1 BAS316/DG PC269 1500P/50V_4 PR160 RL1206-R020 '%8SGDWH PL9 10UH/4A 1500P/50V_4 2 PD7 LDR PC147 0.1U/25V_4 '%8SGDWH PQ37 AON7410 10U/25V_8 PV_Update 2010/11/15 +VAD_1 PD4 PU1 PC151 0.1U/25V_4 4 13 8681HDR ACAV PR7 100K/F_4 2 1 PC152 1000P/50V_4 10U/25V_8 BAS316/DG +VA 100K/F_4 LX PC155 4.7U/25V_8 2 HDR PC156 4.7U/25V_8 3 2 1 1 +VIN_CHG PC4 8681B_1 0.1U/50V_6 8681_ACAV 9 1 1 2 PD12 RB501V-40 PR154 2_6 5 8681_ACAV 2 PR8 2 PL5 +VIN UPB201212T-800Y-N C PC13 1U/10V_4 BAS316/DG ACIN_PG ISN 2 1 BST SDL PD1 UDZ5V6B-7-F 20101013 for EMI +VIN_CHG 1 1 2 SCL 15 11 PC122 0.01U/25V_4 3ODFHWKLVFDS FORVHWR(& PR23 100/F_4 1 2 VDDA MBDATA IACM 2 IACP MBCLK PD2 UDZ5V6B-7-F VDDP SDL 8681_VDDA 1 6 10 PC18 2 1 3 SCL IACP 1 1 PC9 1U/10V_4 IACM ACIN_PG 1M_4 PC2 0.01U/25V_4 2 CSIN CSIP PR20 PR4 1K/F_4 1U/10V_4 1 1 2 ACIN_1 2 PR26 10/F_4 PR5 *0_4/S [36] PR3 10K/F_4 PC6 68P/50V_4 '%8SGDWH PC11 2 1 PR27 10/F_4 PR6 *0_4/S 1 PD6 10 9 TEMP_MBAT [29] 3ODFHWKLV=96FORVHWR )DU)DUDZD\9,1 8681_VDDA 2.2U/10V_6 6 5 ACOK_IN 3DUDOOHO 3 2 1 MAINON MBCLK PC7 68P/50V_4 2 1 2 2 1 PD8 1SS355 2 PQ4 MMBT3904-7-F ACAVD 4 PD5 [29,32,33,34,35,36,37,38] ACOK# 1 PQ1 IMD2 PR166 *0_2/S 2 PR14 PR21 *100K/F_4 *0_4/S 2 PR15 100K/F_4 1 PQ3 DMN601K-7 1 FKDQJH31DQG IRRWRULQWZLOOFKDQJHVPDOOHU QH[WORW 1 C 2 IDEA_G 3 2 2 PR153 1M_4 1 +VAD MMDT2907A PR167 *0_2/S 2 PR12 100K/F_4 +VAD 2 Q2 PR158 1M_4 8681_VDDP 1 220K_4 220K_4 MBDATA [29] 2 +VAD PR18 100/F_4 1 3 4 PR157 3 5 3 2 1 6 1 2 1K_6 PR155 2 2 2 [29] 3 4 5 6 7 10 8 9 D +3VPCU PD18 P4SMAJ20A PR19 20K/F_4 Q1 +VA 1 1 PR1 330_4 2 BATDIS_G 3 4 5 6 7 8 B_TEMP_MBAT *100/F_4 PQ32 PR156 PC145 0.1U/25V_4 +VIN PR165 RC2512-R010 1 +VH28 2 PC146 0.1U/25V_4 SMD SMC BATDIS_G PC10 1U/25V_8 ACOK_IN &KHFN'&B,1SLQDVVLJQPHQW PL3 UPB201212T-800Y-N 1 PC159 0.1U/25V_4 BATT+ 8 7 6 5 2 PC160 0.1U/25V_4 2 XSGDWH 1 2 3 4 3 PC142 0.1U/25V_4 PD13 P4SMAJ20A CN5 BP07061-BA015 1 1 2 2 PQ34 P1003EVG +PRWSRC 1 PL8 UPB201212T-800Y-N 4 PL4 UPB201212T-800Y-N 1 1 3 5 1 2 3 5 PQ33 P0603BDG 1 J1-1 4 2 4 6 +VAD PQ35 FDMC4435BZ +VA PL6 UPB201212T-800Y-N CN6 DC/B TO M/B 1 D +BATCHG 'R1RWDGGWHVWSRLQWRQ%$7',6B*VLJQDO 3ODFHWKLV=96FORVHWR LGHDGLRGH 723'&B-$&. : : PC5 0.01U/50V_4 ACOK_IN PR13 0_4 2 2 PQ2 PDTC144EU +PRWSRC D/C#_S6A 1 2 D/C# [29] BAS316/DG 1 ACOK# PR279 100K_4 +VAD PC15 *10U/6.3V_8 1 ACIN_PG PD3 D/^ƵŐŐĞƐƚŝŽŶ +3VPCU PR278 *0_4 +VIN PR280 *0_4 ACIN C3006 0.1U/25V_4 C3007 0.1U/25V_4 C3008 0.1U/25V_4 PC150 22U/25V_1206 A 2 3 C3005 0.1U/25V_4 PC143 22U/25V_1206 PR281 1M_4 2 3 [29] PQ75 DMN601K-7 PV_Update 2010/11/12 PR282 1M_4 1 2 ACIN_PG WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ PQ76 DMN601K-7 11/10 add for EMI 1 A 1 3 PV_Update 2010/11/15 [36] [36] [36] [36] 5 4 3 2 +BATCHG +VAD_1 +VH28 +VA Eϱ Size Custom Document Number Rev ADate: Monday, November 15, 2010 1 Sheet 30 of 40 5 4 3 2 1 DC/DC +3V_ALW/+5V_ALW/+5V_ALW2 /+15V_ALW ϯϭ D D 3ODFHWKHVH&$3V FORVHWR)(7V 3ODFHWKHVH&$3V FORVHWR)(7V +VIN +VIN_3VS5 PL2 +VIN_5VS5 UPB201212T-800Y-N PL11 UPB201212T-800Y-N +VIN +5VPCU +VIN PC179 0.1U/25V_4 PC186 PC178 2200P/50V_4 PC42 4.7U/25V_8 PC43 4.7U/25V_8 PC174 0.1U/25V_4 4.7U/6.3V_6 PC141 0.1U/25V_4 PC144 4.7U/25V_8 PC14 4.7U/25V_8 PR195 10_8 +3VPCU +2VREF +VIN +5VPCU PC64 5 6 7 8 PHASE2 11 3V_PHASE2 VOUT1 FB1 LGATE2 12 3V_LGATE2 PGOOD 23 PGOOD PR67 137K/F_4 2_6 OUT2 7 FB2 5 PC65 3 2 1 PR103 +3VS5 PL13 2.2UH/8A 0.1U/25V_4 +3.3V_ALWP PR208 PR201 2.2_8 *0_2/S 4 3V_FB2 + PC184 PC207 1500P/50V_4 PQ50 AO4712 3 2 1 PR73 15.4K/F_4 5GV RQ PRKP PR63 0_4 PR76 10K/F_4 [29,32,33,34,35,37,38] PC205 330U/6.3V_6X5.8 PR93 5GV RQ PRKP 0_4 B C 1 5V_FB1 24 2 3V_UGATE2 2 17 3 REF VREG5 VREG3 9 0.1U/10V_4 LGATE1 1 2 3 10 BOOT2 5 6 7 8 19 PQ40 AO4712 PC166 1500P/50V_4 UGATE2 SKIPSEL GND GND PHASE1 5V_LGATE1 1 PC157 0.1U/10V_4 4 570 ENC 20 PQ44 AO4496 TONSEL BOOT1 5V_PHASE1 4 +3.3 Volt +/- 5% Countinue current:4A Peak current:6A OCP minimum:7.5A PR81 0_4 14 25 15 PR168 2.2_8 UGATE1 18 1 2 PC163 330U/6.3V_6X5.8 21 5V_BST1 22 *0_2/S + EN 2_6 8 7 6 5 PR175 PR59 0.1U/25V_4 1 2 3 PL7 2.2UH/8A PC36 13 ENTRIP2 5V_UGATE1 PQ36 AO4496 PR82 *0_4 4 6 8205EN 4.7U/6.3V_6 PU4 4 +5VS5 16 PR101 *665K/F_4 PR97 *330K/F_4 VIN PC154 0.1U/25V_4 8 7 6 5 PC153 2200P/50V_4 PC50 1U/6.3V_4 8 PC185 0.1U/25V_4 ENTRIP1 C +5V +/- 5% Countinue current:4A Peak current:6A OCP minimum:7.5A PR92 6.8K/F_4 +3VPCU B PR84 *0_4 HWPG 3 +3VS5 PR86 10K/F_4 S5_ON PR62 10K_4 PR179 PR74 0_4 2 +3VPCU 3 PC47 0.1U/10V_4 2 PQ8 *PDTC144EU 2 PR94 137K/F_4 PQ42 *2N7002K 1 S5_ON 1 [29] PQ41 *2N7002K 1 3 *100K_4 A A WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ +5VPCU 5 4 3 2 Eϱ Size Custom Document Number Rev A Date: Monday, November 15, 2010 1 Sheet 31 of 40 1 2 3 4 5 ϯϮ 977$ PL22 +VIN UPB201212T-800Y-N 2 +VIN_DDR 1 1 +0.75V_DDR_VTT PC262 4.7U/25V_8 PC132 4.7U/25V_8 PC260 2200P/50V_4 PR140 *0_4 VTTSNS VTT 24 VLDOIN 23 +1.5VSUS PC263 *0.1U/50V_6 9686 3 GND VBST 22 8207BST 8207BSTR 4 MODE DRVH 21 8207DRVH LL 20 8207LX DRVL 19 8207DRVL PR139 2_6 PC129 1 2 G 4 S 0.1U/25V_4 COMP 18 8 VDDQSNS CS_GND 17 9 VDDQSET CS 16 G 4 5,/,0 ,/,0[5'6 21 X$ PQ73 RJK03D3D + 1 PGND S 1 2 3 NC 1 5 PR134 2.2_8 D 7 1 6 2 B V5FILT 2 PC135 0.033U/10V_4 +1.5VSUS 2 VTTREF 1 [4,12,13] DDR_VTTREF 2&3PLQLPXP$ PL21 1UH/15A 0_4 5 3HDNFXUUHQW $ PQ74 RJK03B9D PR260 *0_2/S PC130 2200P/50V_4 2 P$ &RXQWLQXHFXUUHQW $ D PR135 +1.5VSUS PC261 0.1U/25V_4 1 2 3 2 1 PC264 0.1U/25V_4 25 PC133 10U/6.3V_8 5 VTTGND GND PU11 1 PC131 10U/6.3V_8 2 A 2 A PC245 0.1U/10V_4 B PC247 390U/2.5V_6X5.8ESR10 PR136 8207CS +5VS5 7.5K/F_4 10 S3 V5IN 15 11 S5 V5FILT 14 PR274 0_4 PR275 619K/F_4 5'6RQ PRKP 12 NC PGOOD 13 3ODFHWKLVVKRUWSDG FORVHWRRXWSXW&$3 V5FILT 1 8207TON +VIN PC265 1 1U/6.3V_4 8207S5 SUSON DDRPG 2 [29,33,36] 2 57/*4: PC134 1U/6.3V_4 PR137 10_6 HWPG [29,31,33,34,35,37,38] PR141 0_4 C 1 C 1 2 PR142 10K/F_4 2 PR143 10K/F_4 3ODFHWKLV)%SDUWVFORVHWR,& PD11 D 2 D MAINON [29,30,33,34,35,36,37,38] WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ 1 RB501V-40 1 2 PC136 0.1U/10V_4 1 2 PR144 100K/F_4 1 [12,13,36] +0.75V_DDR_VTT [2,4,10,12,13,33,38] +1.5VSUS [10,21,23,26,31,33,34,35,36,37,38,39,40] +5VS5 [21,30,31,33,34,35,36,37,38,40] +VIN 2 3 Eϱ 4 Size Custom Document Number Rev A Date: Monday, November 15, 2010 Sheet 5 32 of 40 5 4 3 2 1 ϯϯ D D VCCSA (0.9V) +/- 5% Countinue current 3A~6A PQ13 RJK03B9D +VCCSA PC85 *10U/6.3V_8 PC79 *10U/6.3V_8 PC80 *10U/6.3V_8 + 2 PC78 *10U/6.3V_8 4 PC77 10U/6.3V_8 3 2 1 G 5 1 S D +1.05V_VTT PR211 PC217 390U/2.5V_6X5.8ESR10 +5VS5 PR213 0_4 [29,31,32,34,35,37,38] 22K/F_4 PU12 4 HWPG [34] 1.05V_VTT_PWRGD PR202 100/F_4 +5VS5 PC204 *0.22U/10V_4 PGD 1 EN 6 VCC DRV * PR210 1/F_4 5 ADJ 3 GND 2 PR212 0_4 PC208 0.022U/25V_4 PV_Update 2010/11/15 PC210 1U/6.3V_4 PR209 PR205 VCCUSA_SENSE [4] C 8.06K/F_4 C 0_4 PC268 PR206 40.2K/F_4 +3VS5 PR207 13K/F_4 *100P/50V_4 VCCSA 0 0.9V 1 0.8V '%8SGDWH PR199 10K/F_4 PV_Update 2010/11/15 2 PQ47 DMN601K-7 3 PR188 1K/F_4 1 PC183 0.01U/16V_4 PR187 *10K/F_4 1 2 [4] VCCSA_SEL PV_Update 2010/11/15 3 VCCSA_SEL PQ45 MMBT3904-7-F USB3.0 POWER +1.1V +/- 5% Countinue current:650mA Peak current:2A B +1.5VSUS +VCCSA PU10 3 PR126 *22_8 PR130 [29,32,36] SUSON *10K/F_4 3 PR64 *1M_4 +5VS5 [29,30,32,34,35,36,37,38] 3 PQ7 *2N7002K PR58 *1M_4 2 MAINON PC116 1U/6.3V_4 10K/F_4 NC 5 * 2 EN 4 VDD 1 PGOOD +1.1V_VL801 VOUT 6 GND 8 GND1 9 11/12 add 1.05V_ADJ 9/13 add for VL801 power control 1 1.05V_VTT_PWRGD PC124 0.33U/6.3V_4 R1112 2 VIN PC118 0.1U/10V_4 ADJ PC119 10U/6.3V_8 PC115 10U/6.3V_8 PC117 10U/6.3V_8 PC120 0.1U/10V_4 7 +VIN B PR131 38.3K/F_4 PR133 HWPG PQ10 *2N7002K PR132 100K/F_4 1 0_4 9R 55 5 5 .RKP A A WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ Eϱ 5 4 3 2 Size Custom Document Number Rev A Date: Monday, November 15, 2010 1 Sheet 33 of 40 5 4 3 2 1 ϯϰ D D 10/8 update +5VS5 +VIN_1.05V_VTT PR28 PL10 UPB201212T-800Y-N +VIN 10_6 PC20 1U/6.3V_4 RTTON PQ43 RJK03B9D PL12 1UH/15A PR38 600 mils 232K/F_4 FB 3 PR204 PR85 2.2_8 D G 4 S 1 2 3 RTDL PR31 PC24 PR29 5'6RQ PRKP *10K/F_4 5,/,0 ,/,0,7[56(16(X$ + PC196 0.1U/10V_4 + PC213 390U/2.5V_6X5.8ESR10 PC206 *390U/2.5V_6X5.8ESR10 PR57 *0_4 3 *100P/50V_4 PC55 1500P/50V_4 10K/F_4 RTFB1 PR37 4.02K/F_4 PQ46 RJK03D3D PC199 *0.1U/10V_4 *0_2/S 1 DL C +1.05V_VTT 1 16 S 2 TON D 2 PAD 5 RTLX 8 PC164 0.1U/25V_4 G 4 1 2 3 13 9 VDDP PHASE 11 BST 2 EN/DEM 17 14 PC31 *0.33U/6.3V_4 RTDH RT8209A PC181 4.7U/25V_8 VCCP_SENSE_R 10/F_4 NC PC182 4.7U/25V_8 +1.05V Volt +/- 5% Countinue current:10A Peak current: 12A OCP minimum: 15A 5 MAINON 5 15 PC26 0.1U/25V_4 12 VOUT [29,30,32,33,35,36,37,38] RTEN PGOOD PGND PR53 CS 4 PC169 0.1U/25V_4 RTBST DH 1 [33] 1.05V_VTT_PWRGD 10 7 RTILIM HWPG_S2A VDD PR164 0_4 GND BAS316/DG PU2 NC PR36 7.5K/F_4 1 PR51 2_6 6 C 2 RTVDD PR162 100K_4 PD14 HWPG RTBST_1 RTFB +3V [29,31,32,33,35,37,38] PC170 2200P/50V_4 PC162 1U/6.3V_4 PR161 1 Vo=0.75(R1+R2)/R2 B 2 *1K/F_4 PQ39 *MMBT3904-7-F H_VTTVID1 [5] B H_VTTVID1=Low, 1V H_VTTVID1=High, 1.05V VCCP_SENSE_1 PR52 0_4 VCCP_SENSE [4] A A WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ Eϱ 5 4 3 2 Size Custom Document Number Rev A Date: Monday, November 15, 2010 1 Sheet 34 of 40 5 4 3 2 1 ϯϱ D D +VIN_1.05V PR265 10_6 PL1 +VIN UPB201212T-800Y-N PR266 +5VS5 1 RT8238DL 5 0.1U/25V_4 PR261 PR129 2.2_8 +1.05V +/- 5% Countinue current:6A Peak current: 8A OCP minimum: 10A C +1.05V PL20 2.2UH/8A 3 2 1 RT8238LX PC128 0.1U/25V_4 PC125 *4.7U/25V_8 PQ23 AON7410 4 PC256 8238BST-1 5 RT8238TON 11 VCC PAD 0_4 PC249 0.1U/10V_4 + PQ22 AON7702 4 RT8238FB +5VS5 2 PC255 4.7U/25V_8 1 13 BOOST 8238BST PR264 2_6 PC126 0.1U/25V_4 PC258 *100P/50V_4 2 PC259 *0.1U/10V_4 8 RT8238DH PGOOD RT8238A PHASE EN LGATE 12 PR271 0_4 3 4 3 2 1 RT8238EN MAINON UGATE FB [29,30,32,33,34,36,37,38] RT8238PG 9 PR272 0_4 HWPG CS MODE [29,31,32,33,34,37,38] RT8238ILIM 10 GND PR273 10K_4 PU15 7 PR268 130K/F_4 PV_Update 2010/11/15 TON '%8SGDWH PC127 2200P/50V_4 6 C RT8238VCC +3VS5 5 360K/F_4 PC257 1U/6.3V_4 PC121 1500P/50V_4 PC248 390U/2.5V_6X5.8ESR10 PR270 0_4 5GVRQ PRKP PR269 11K/F_4 B PR267 10K/F_4 B 9R 55 5 A A WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ Eϱ 5 4 3 2 Size Custom Document Number Rev A Date: Monday, November 15, 2010 1 Sheet 35 of 40 5 4 3 +VAD G5934VIN_1 ϯϲ 1 1 2 *RB501V-40 PR113 0_4 PR117 22_6 2 PR116 *22_6 PD10 2 1 1 +BATCHG 1 +VH28 PD9 +VA 2 D 1 [29] LAN_POWER 16 DCAP 1 ACIN_PG PC87 0.47u/25V_6 [30] 1 PR112 *0_4/S 2 +VAD_1 ON1 PG 2 17 G5934VOUT PV_Update 2010/11/15 2 VOUT 18 G5934CP CN VIN 19 G5934CN 20 G5934VIN PC88 0.1U/25V_4 PC86 1U/35V_6 2 PC89 0.1U/25V_4 2 1 D_CAP *RB501V-40 CP D G5934PG 15 2 MAINON ON2 VSENSE G5934VSENSE 14 2 [29,30,32,33,34,35,37,38] 1 PR114 750K/F_4 3 SUSON 38 3 ON3 REG PR115 100K/F_4 13 1 [29,32,33] +12VALW PC90 1U/16V_4 4 ON4 DISC3 +3V 1 +3VSUS 6 PR30 *0_4/S 2 1 +5V C PR120 *0_4/S +5VS5 21 GND DRIVER2 DRIVER1 2 G5934DISC2 MAIND $ PQ5 AO4496 1 +0.75V_DDR_VTT +VIN PR123 *22_8 +5V PR119 1M_4 PR138 22_8 PC22 *10U/6.3V_8 PC21 0.1U/10V_4 PQ15 *DMN601K-7 2 2 +3VS5 PQ14 DMN601K-7 MAIND 1 2 5 6 PQ6 ME3424D 1 B MAIN_ONG $ [2,4] 9/28 add +3VSUS 1 +3VS5 PC25 0.1U/10V_4 PQ11 ME3424D LAN_ON 1 2 5 6 PC23 *10U/6.3V_8 PC53 0.1U/10V_4 3 [12,13,32] +0.75V_DDR_VTT [24] +3VLANVCC [2,4,10,12,13,32,33,38] +1.5VSUS [30] +BATCHG [21,28,38] +12VALW [10,21,23,26,31,32,33,34,35,37,38,39,40] +5VS5 $ +3VLANVCC [2,6,7,8,9,10,14,24,29,31,33,35,38] +3VS5 [30] +VAD_1 [30] +VH28 [4,7,10,38] +1.8V [21,30,31,32,33,34,35,37,38,40] +VIN [6,7,10,21,22,23,27,28] +5V [30] +VA 1 PC45 2200P/50V_4 4 4 MAIND_G PC63 0.1U/10V_4 3 2 [4] 1 B PC29 2200P/50V_4 PQ24 DMN601K-7 PR122 1M_4 1 +3V 11/10 add 2 3 2 2 1 PR121 *0_4/S SUSD +1.8V 3 2 1 1 2 3 PC69 *10U/6.3V_8 PC12 0.1U/10V_4 4 PC16 2200P/50V_4 1 2 G5934DISC3 5 6 7 8 PC52 2200P/50V_4 PC68 0.1U/10V_4 7 3 $ G5934DISC4 MAIND3.3V 4 DISC2 10 PQ12 AO4496 12 PC51 0.1U/10V_4 9 DISC1 DISC4 5 8 1 DRIVER3 2 8 7 6 5 +3VLANVCC G5934DISC1 11 +3VS5 DRIVER4 PR118 *0_4/S C 3 MAINON 2 A PC35 *10U/6.3V_8 PC44 0.1U/10V_4 A WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ Eϱ 5 4 3 2 Size Custom Document Number Rev A Date: Monday, November 15, 2010 1 Sheet 36 of 40 5 4 3 2 1 ϯϳ ciucuit default is N12E VGA PQ17 PQ19 PQ16 PQ18 type PR252 N12E peak 53.4A POP(SMT) 1.37K N12P D NA(no SMT) peak 35.32A 806 ohm D (CS18062FB29) Nvideo N12E CNTRL1 GPIO6 Nvideo N12P CNTRL0 CNTRL1 CNTRL0 GPIO6 GPIO5 N11E-GE GPIO5 N11E-GE 0 0 0.9125V 0 0 1V 0 1 0.8625V 0 1 0.975V 1 0 0.8125V 1 0 0.825V 1 1 N/A 1 1 N/A Update 2011/11/12 PL26 UPB201212T-800Y-N +VIN_VGA +VIN PL27 4 S 2 CSN LDR2 RSN VDDP MAINON RSP 4 GNDP 2= PC101 1500P/50V_4 +5VS5 13 LDR1 VIN BST1 12 PC239 1000P/50V_4 GNDA D PQ16 RJK03B9 5 PQ18 RJK03D3 PC241 1500P/50V_4 PC99 330U_2V_7343 8112RSP_1 1 8112RSN_1 1 2 2 *short PR247 *0_4 +3V_GFX 1 3 PQ20 *DDTA124EUA-7-F 1 2 DGPU_VC_EN [38] +3V PR276 0_4 R3006 3 2 *4.7K_4 4.7K_4 R3005 PQ66 *DTC144EUA 2 PC94 330U_2V_7343 PR248 *0_4 PR277 10K/F_4 1 + + 2 S PQ67 RJK03D3 8122AGND HWPG B PR253 2.2_8 D G 4 S PR235 PQ65 2N7002E-G DGPU_PWR_EN 2 PC103 0.1U/10VC_4 +3V 8122AGND [29,31,32,33,34,35,38] +VGACORE PL17 0.36uH/25A_11 DGPU_PWROK Q3003 DGPU_PGOK-1 [9,14,29] R3007 100K/F_4 2 +1.05V_GFX A DGPU_POK4 Q3001 2 A 3 1000P/50V_4 DGPU_POK2 2 C3002 *1000P/50V_4 1 R3004 4.7K_4 1 MMBT3904-7-F C3001 *1000P/50V_4 +1.5V_GFX DTC144EUA C3003 1 R3003 4.7K_4 3 1 9/3 update net name 3 3 PC224 1000P/50VB_4 8122AGND PR237 10K/F_4 1 PR254 30.1K/F_4 2 4 1 2 3 1 [17] GFX_CORE_CNTRL1 S PQ63 RJK03B9 G 8112LDR1 2 PC98 4.7U/25V_8 G 4 S D 8122AGND PR231 130K/F_4 PC97 4.7U/25V_8 1 PR227 324K/F_4 20101014 for VGA Voltage PC230 4.7U/25V_8 8112LX1 PQ62 2N7002E-G 20101009 for EE initial setting PC229 4.7U/25V_8 1 2 PC92 0.1U/25V_4 D G 4 1 2 3 9 5 PR229 88.7K/F_4 5 HDR1 LX1 PG 8 21 PC227 0.22U/25V_6 8112HDR1 PC91 2200P/50V_4 PR255 1K/F_4 PR243 220K_6 NTC 2 8112VDDA PR232 49.9K/F_4 8122AGND [17] GFX_CORE_CNTRL0 PR244 34.8K/F_4 1 PR239 2_6 8122AGND 2 8112CSP +VIN_VGA 5 3 PR226 681K/F_4 PR252 1.37K/F_4 8112CSN 1 2 3 PC225 1000P_4 PR236 10K/F_4 8122VSET 1 8122AGND PD16 RB501V-40 11 8112BST12 PC93 330U_2V_7343 +VGACORE PR242 51/F_4 PC234 1U/10VC_4 1 2 3 8122AGND 10 20101014 for VGA Voltage 8112PG PC273 0.47U/10V_4 PC226 1000P/50V_4 6 2 PR230 180K/F_4 1 +3V 18112VIN 5 2 PR234 100K/F_4 TSET +VIN_VGA VSET 8112VDDA 9''$ 9 PC100 330U_2V_7343 0.018U/25V_4 14 1 ON/SKIP 7 47K/F_4 PD19 RB501V-40 1 2 1 1 1 2 3 PQ19 RJK03D3 + PC237 0.01U/25V_4 2 2 PU13 2 1 PC102 0.1U/10VC_4 PR250 30.1K/F_4 2 S 2 BST2 HDR2 PQ68 RJK03D3 PC240 15 8122TSET PR240 20101009 for EE initial setting G 4 S PD17 RB501V-40 1 274/F_4 3 DGPU_PWR_EN 20101009 for EE timing B 8112RSP PR238 *0_4 1 2 2 [29,30,32,33,34,35,36,38] [9,29,38] G 4 1 16 18 17 19 2 0.22U/25V_6 8112LDR2 + PR124 2.2_8 D 1 2 3 2_6 PR246 [14] VGPU_CORE_SENSE 1 2 3 D 1 1 8122AGND 8112RSN C 5 PC238 1 2 8112RSP_1 PR249 1 2 0_4 8122AGND 2 +VGACORE 2 1 1 +VGA_CORE +/- 5% Countinue current:43.55A Peak current:65.3A OCP minimum 70A PL18 0.36uH/25A_11 2 PR245 51/F_4 2 8112RSN_1 LX2 20 1 [14] VSS_GPU_SENSE 1 VDDA CSP PC233 0.01U/25V_4 PC219 0.1U/25V_4 1 2 8112CSN PC228 220P/50V_4 PQ17 RJK03B9 1 PR251 8112CSP PR241 0_4 S PQ64 RJK03B9 5 8112VDDA 2 PC223 0.1U/25V_4 8112LX2 8112BST2 1 PC232 4.7U/25V_8 G 4 1 2 3 PC235 1U/10VC_4 8122AGND 8122AGND C PC236 22P/50V_4 PC231 4.7U/25V_8 D G 8112HDR2 9''$ 9 PC95 4.7U/25V_8 2 PC96 4.7U/25V_8 PC221 0.1U/25V_4 5 PC222 2200P/50V_4 D SI:load line 0.9mV/A=>0.14mV/A UPB201212T-800Y-N 1 PR230=160K(CS41602FB00) PR232=49.9K PR226=1.43M(CS51432FB10) PR227=182K(CS41822FB18) 5 PR230=180K PR232=49.9K PR226=681K PR227=324K Q3002 MMBT3904-7-F WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ 11/10 add for DGPU_PWROK circuit 5 4 3 Eϱ 2 Size C Document Number Rev A Date: Monday, November 15, 2010 1 Sheet 37 of 40 1 2 3 4 5 6 VGA Core 8 ϯϴ PC220 0.1U/10V_4 5 +1.05V_VTT 7 D G 4 1 +VIN 2 3VGFX_OND PQ9 DMN601K-7 2 PC215 *10U/6.3V_8 PC140 0.1U/10V_4 PQ25 ME3424D 4 PC138 2200P/50V_4 2 +3V_GFX $ 1 3 PC216 0.1U/10V_4 3 3 PQ26 DMN601K-7 PR146 1M_4 1 2 5 6 PR125 22_8 3 3 PR145 22_8 A +1.05V_GFX +3VS5 2010_1009 for EE VGA timing PR150 1M_4 $ S PQ59 RJK0392DPA +12VALW +1.05V_GFX 2 +3V_GFX 1 2 3 A 2 1 1 PQ27 DMN601K-7 PC139 *10U/6.3V_8 PC137 0.1U/10V_4 DGPU_PR_EN_G 1 PQ28 DTC144EUA 1 PR149 1M_4 2 [9,29,37] DGPU_PWR_EN 11/10 add B B +12VALW +1.5VSUS PC113 0.1U/10V_4 +1.5V_GFX PR148 1M_4 PR147 22_8 D G PR151 1M_4 PQ29 DMN601K-7 4 PQ21 RJK0392DPA PQ31 DTC144EUA +1.5V_GFX 1 PQ30 DMN601K-7 2 1 1 PR152 1M_4 2 1 [37] DGPU_VC_EN $ S PC112 2200P/50V_4 2 3 2 3 3 1.5VGFX_OND 1 2 3 +VIN 5 2010_1009 for EE VGA timing PC109 *10U/6.3V_8 PC110 0.1U/10V_4 DGPU_VC_EN_G C C +1.8V +/- 5% Countinue current:0.8A Peak current:2A +3VS5 PU5 3 VIN NC +5VS5 PC41 *0.33U/6.3V_4 2 EN 4 VDD 1 PGOOD 8 9 7 PC54 1U/6.3V_4 GND GND1 1.8VADJ PC70 PC66 PR106 127K/F_4 PR79 [29,31,32,33,34,35,37] PC67 0.1U/10V_4 9025EN 10K/F_4 ADJ PR71 MAINON +1.8V 6 10U/6.3V_8 VOUT [29,30,32,33,34,35,36,37] 5 * PC37 0.1U/10V_4 10U/6.3V_8 PC40 10U/6.3V_8 9025PGD HWPG PR104 100K/F_4 0_4 9R 55 5 5 .RKP D D WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ Size Custom Eϱ 1 2 3 4 5 6 Document Number 7 Rev A Date: Monday, November 15, 2010 Sheet 8 38 of 40 1.Alert trace routing between data and clock trace 2.Refer to ground 3.Keep out 20 mils 9/9 modify PR35 130/F_4 PR33 *75/F_4 B~4350 PC271 0.1U/10V_4 PR34 54.9/F_4 2 1.21K/F_4 PC171 5600P/25V_4 SDIO VR_SVID_ALERT# PC173 680P/50V_4 PC165 PR176 PC176 24.9/F_4 SCLK 6131SAGND 1 PR65 PR72 75K/F_4 165K/F_4 20101014 for load line 1 PR194 PC39 3.01K/F_4 3300P/50V_4 1 PR186 PR61 20101014 for transient 20K/F_4 PC38 100/F_4 VSS_SENSE PR54 0_4 PR48 0_4 1 CSP2 2 150K/F_6 1200P/50V_4 PR55 CSP1 2 150K/F_6 PC175 PR182 1K/F_4 PR181 10/F_4 22P/50V_4 100P/50V_4 PR173 PR178 24.9K/F_4 387&2/6( WR9&25( 3KDVH ,QGXFWRU 220K_6 NTC PR214 PR184 6131SAGND [4] ϯϵ '%8SGDWH +1.05V_VTT PR193 CSP3 2 150K/F_6 CSSUM 470P/50V_4 *0_4/S PR171 10K/F_4 +1.05V_VTT 6131SAGND 1014 change PN IMVP_PWRGD PR43 75/F_4 [2,29] H_PROCHOT# [4] VR_SVID_DATA [4] VR_SVID_CLK [4] VR_SVID_ALERT# [6] IMVP_PWRGD [29] GFX_HWPG VRON +5VS5 PR32 TSENSEA 0_4 0_4 SDIO SCLK IMVP_PWRGD GFX_HWPG VRENABLE PR40 0_4 6131_VCC 2_6 PR177 10K/F_4 6131SAGND +VIN_VCC_CORE TSENSEA PR39 1K/F_4 PC167 1 PR215 2 PR180 100K_4 NTC 6131SAGND DROOPA PR44 *0_4 PR80 10/F_4 CSN2 PR83 10/F_4 CSN3 PR96 *0_4 PR102 *0_4 PR100 DRON VR1_PWM3 [40] [40] CSN1 [40] CSP1 [40] 47n/10V_4 VR1_PWM2 [40] VR1_PWMA [40] +5VS5 6.98K/F_4 PR91 *100K/F_4 PR90 20.5K/F_4 6131SAGND PR191 10K/F_4 PR190 10K/F_4 6131SAGND 6131SAGND +5VS5 9/28 try 100K for boot PC58 2-phase POP 6131SAGND CSNA 1000P/50V_4 CSSUMA PR98 *0_4 CSNA [40] CSPA [40] 47n/10V_4 CSCOMPA PC48 1200P/50V_4 PR69 PUT COLSE TO V_GT HOT SPOT CSP3 PC59 [40] VR1_PWM1 [40] 6131SAGND 6131SAGND [40] 6.98K/F_4 PR99 PWMA PR89 10K/F_4 '%8SGDWH [40] CSN3 47n/10V_4 VR1_PWM2 6131SAGND CSP2 PC60 PC57 6131SAGND PUT COLSE TO VCORE HOT SPOT PR95 6.98K/F_4 CSN2 CSPP2 CSN3 CSPP3 CSN1 CSPP1 DRON 41.2K/F_4 [40] 47n/10V_4 4&:&38 9,' 9 ,FF0D[ $ 5B// PRKP 2&3a$ 2-phase POP PR192 CSN2 PC56 CSPPA PR70 *0_4 6131SAGND 6131SAGND CSN1 +5VS5 39 38 37 36 35 34 33 32 31 30 29 28 27 CSN2 CSP2 CSN3 CSP3 CSN1 CSP1 DRON PW M1/ADDR PW M3/VBOOT PW M2/ISHED IMAX PW MA/IMAXA VBOOTA 14 15 16 17 18 19 20 21 22 23 24 25 26 1U/6.3V_4 PR174 *14K/F_4 6131SAGND 8.25K/F_4 2 8.25K/F_4 PC172 0.1U/10V_4 1 100K_4 NTC PR170 0.1U/10V_4 PC168 PR216 VSP TSENSE VRHOT# SDIO SCLK ALERT# VR_RDY VR_RDYA ENABLE VCC ROSC VRMP TSENSEA 0.01U/50V_4 PC27 1 2 3 4 5 6 7 8 9 10 11 12 13 PR78 [29] TSENSE PR42 PR41 VSP TSENSE PU3 NCP6131S 6131SAGND VSNA VSPA FBA DIFFOUTA TRBSTA COMPA ILIMA DROOPA CSCOMPA IOUTA CSSUMA CSPA CSNA GFX_HWPG 10/F_4 PC46 IMONA PR172 10K/F_4 6131SAGND PR75 1000P/50V_4 PR189 IMON VR1_CSREF +3V 0_4 DROOPA +3V 100/F_4 VSN TRBST DIFFOUT FB COMP CPUILIM PR47 +VCC_CORE 53 51 50 52 49 48 47 46 45 44 43 42 41 40 VCC_SENSE EPAD VSN TRBST DIFFOUT FB COMP ILIM DROOP CSCOMP CSSUM IOUT CSREF NC2 NC1 [4] CSCOMP PC30 1000P/50V_4 PR88 PR87 69.8K/F_4 CSPA VR1_PWM2 6.98K/F_4 6131SAGND COMPA 14K/F_4 PC49 DIFFOUTA PC32 PR56 10/F_4 68P/50V_4 PR60 1K/F_4 PR45 100/F_4 2 PC33 PR46 [4] VSS_AXG_SENSE PR50 [4] VCC_AXG_SENSE FBA 0_4 0_4 PC28 1000P/50V_4 PR66 3.01K/F_4 PR49 +VCC_GFX 100P/50V_4 PC34 3300P/50V_4 270P/25V_4 PR68 PR77 75K/F_4 165K/F_4 2010 1012 for FAE suggestion change 0603size 2phase 35W /3phase 45W option circuit default is 45W CPU 1 PR258 220K_6 NTC B~4350 PR96 component PR98 387&2/6( 729B*7 ,QGXFWRU PR80 PR186 PR95 PR109 PC73 PR111 PC76 PU8 PQ57 PQ58 PL16 PR217 PR198 PC197 PC56 PR61 100/F_4 2phase Change to 0ohm POP IMON 6131SAGND 6131SAGND PR183 24K/F_4 3Phase 45WCPU NA POP POP(SMT) 20K 0.1U/10V_4 PC180 0.1U/10V_4 PR185 24.3K/F_4 (CS00002JB38) (CS31212FB28) OCP 65A IMONA PC177 12.1K NA(NO SMT) 35WCPU OCP 105A WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ 6131SAGND 6131SAGND Eϱ Size Custom Document Number Rev A Date: Monday, November 15, 2010 Sheet 39 of 40 ϰϬ '%8SGDWH PL24 UPB201212T-800Y-N +VIN_VCC_CORE 1 PC74 0.22U/25V_6 PC203 4.7U/25V_8 5 D PU6 PR105 DRON 3 49.9/F_4 4 +5VS5 SW PWM VREG_SW1_HG 7 VREG_SW1_OUT GND 6 EN VCC LG 4 S PQ54 RJK03B9D D VREG_SW1_LG 5 PC71 2.2U/6.3V_6 PC267 0.1U/25V_4 + PC266 470U/25V_EC_10H Reserve for Acoustic PL14 0.36uH PR224 2.2_8 G S 1 2 3 9 PQ53 *RJK03B9D D G 4 PAD PC209 0.1U/25V_4 G S 1 2 3 8 1 2 3 NCP5911 HG PC200 4.7U/25V_8 5 VR1_PWM1 BST 5 2 [39] G 4 1 VREG_BST1 PC201 4.7U/25V_8 D 4 PR219 *0_2/S S PQ60 RJK03D3D 1 2 3 10/8 update PC202 4.7U/25V_8 2 PC211 2200P/50V_4 VREG_BSTRC1 2_6 5 PR107 +VIN PL23 UPB201212T-800Y-N PQ61 *RJK03D3D PC218 1500P/50V_4 PR220 *0_2/S CSN1 [39] CSP1 [39] Parallel routing +VIN_VCC_CORE 1 2 3 4.7U/25V_8 4.7U/25V_8 4.7U/25V_8 0.1U/25V_4 PC192 2200P/50V_4 '%8SGDWH 2010_1009 for SMT change footprint +VCC_CORE PQ49 *RJK03B9D PL15 D PR196 2.2_8 D G S 1 2 3 9 4 PC104 0.1U/10V_4 PR223 *0_2/S G 4 S PQ56 RJK03D3D PQ48 *RJK03D3D PC195 1500P/50V_4 PR218 *0_2/S CSN3 [39] + CSP3 [39] + PC81 330u_2.5V_7343 1 1 1 0.36uH VREG_SW3_LG 5 1 VREG_SW3_OUT 7 PAD PC75 2.2U/6.3V_6 PC191 + PC82 *330u_2.5V_7343 + PC83 330u_2.5V_7343 2 LG PC189 2 VCC PC188 2 4 SW GND 6 EN PC61 2 49.9/F_4 +5VS5 NCP5911 HG PWM S PQ55 RJK03B9D PC62 5 DRON BST 4 S 1 2 3 [39] 3 4 VREG_SW3_HG 8 5 2 PR110 DRON D G 1 2 3 PU7 VREG_BST3 1 VR1_PWM3 D G 4.7U/25V_8 0.22U/25V_6 10/8 update [39] 5 VREG_BSTRC3 2_6 5 PC72 PR108 PC84 *330u_2.5V_7343 Parallel routing 35W CPU NA PV_Update 2010/11/15 +VIN_VCC_CORE S 1 2 3 GND 6 EN VCC LG 5 D VREG_SW2_LG PC76 2.2U/6.3V_6 1 2 3 9 0.1U/25V_4 0.36uH PR198 2.2_8 G S '%8SGDWH PL16 D G 4 PAD PQ52 *RJK03B9D 4 PQ57 RJK03D3D S 1 1 2 3 VREG_SW2_OUT PC193 2200P/50V_4 + PQ51 *RJK03D3D PR222 *0_2/S + PC242 330u_2.5V_7343 2 4 7 4 PQ58 RJK03B9D PC194 1 3 49.9/F_4 +5VS5 G S PC190 2 DRON SW PWM VREG_SW2_HG 5 PR111 8 1 2 3 VR1_PWM2 NCP5911 HG 5 2 [39] G 4 BST PC198 4.7U/25V_8 PU8 VREG_BST2 1 PC214 D 4.7U/25V_8 D 10/15 update PC212 4.7U/25V_8 0.22U/25V_6 5 5 VREG_BSTRC2 2_6 4.7U/25V_8 PC73 PR109 PC243 330u_2.5V_7343 PR217 CSN2 [39] CSP2 [39] 0_4 PC197 1500P/50V_4 PR221 *0_2/S 9/9 modify Parallel routing PL28 UPB201212T-800Y-N 2.2U/6.3V_6 0.1U/25V_4 PC246 2200P/50V_4 2 PC252 PC187 0.1U/25V_4 LG 9 5 4 0.36uH PR256 2.2_8 D G G S 4 PQ69 RJK03D3D S DEL PC106, PC108 (Update 20101112) PC107 0.1U/10V_4 PR257 *0_2/S PQ70 RJK03D3D PC244 1500P/50V_4 PR259 *0_2/S + CSNA [39] PC105 *330U_2.5V_7343 + CSPA [39] Parallel routing 1 D VREG_SWA_LG +VCC_GFX PL19 + PC272 390U/2.5V_6X5.8ESR10 9/9 add + PC274 390U/2.5V_6X5.8ESR10 2 GND 6 EN PQ72 RJK03B9D 1 S 2 VREG_SWA 1 VREG_SWA_HG 7 1 2 3 8 1 PWM VCC PAD PC254 PC111 2 4 PC114 2 3 SW 5 PR263 49.9/F_4 NCP5911 HG 1 2 3 DRON +5VS5 BST +VIN G 4 5 2 VR1_PWMA D Del PQ72 1 2 3 1 [39] 0.22U/25V_6 PC250 *4.7U/25V_8 2_6 PU14 10/8 update PC251 4.7U/25V_8 5 PV_Update 2010/11/13 4.7U/25V_8 PC253 4.7U/25V_8 Discrete Only NA PR262 PL25 UPB201212T-800Y-N 1 PV_Update 2010/11/12 PC275 390U/2.5V_6X5.8ESR10 PV_Update 2010/11/12 WZK: d͗dt, YƵĂŶƚĂŽŵƉƵƚĞƌ/ŶĐ͘ Eϱ Size C Document Number Rev A Date: Monday, November 15, 2010 Sheet 40 of 40 www.s-manuals.com
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.5 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Producer : Acrobat Distiller 10.0.0 (Windows) Modify Date : 2016:07:07 12:59:32+03:00 Create Date : 2012:01:22 20:01:31+07:00 Creator Tool : PDFCreator Version 0.9.5 Metadata Date : 2016:07:07 12:59:32+03:00 Document ID : 90c2013c-f5d9-11df-0000-08f41a795a3e Instance ID : uuid:0f02f27d-c551-4fcb-9b9e-2b7ee753e815 Format : application/pdf Title : Quanta TWH - Schematics. www.s-manuals.com. Creator : Description : Subject : Quanta TWH - Schematics. www.s-manuals.com. Page Count : 41 Keywords : Quanta, TWH, -, Schematics., www.s-manuals.com. Warning : [Minor] Ignored duplicate Info dictionaryEXIF Metadata provided by EXIF.tools