REG101 Datasheet. Www.s Manuals.com. Rd Ti

User Manual: Marking of electronic components, SMD Codes RO, RO***, RO1, RO1A, RO1B, RO1C, RO1D, RO1E, RO1G, RO1N. Datasheets 2SA1204, 2SA1664, 2SC2715, APE8858Y-HF, KTC3879, REG101NA-2.5, REG101NA-2.8, REG101NA-2.85, REG101NA-3, REG101NA-3.3, REG101NA-5, REG101NA-A.

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REG101
REG

101

SBVS026D – JULY 2001 – REVISED SEPTEMBER 2005

DMOS
100mA Low-Dropout Regulator
FEATURES

DESCRIPTION

● NEW DMOS TOPOLOGY:
Ultra Low Dropout Voltage:
60mV typ at 100mA
Output capacitor NOT required for stability
● FAST TRANSIENT RESPONSE
● VERY LOW NOISE: 23µVrms

The REG101 is a family of low-noise, low-dropout linear
regulators with low ground pin current. Its new DMOS
topology provides significant improvement over previous
designs, including low dropout voltage (only 60mV typ at
full load), and better transient performance. In addition, no
output capacitor is required for stability, unlike conventional
low-dropout regulators that are difficult to compensate and
require expensive low ESR capacitors greater than 1µF.
Typical ground pin current is only 500µA (at IOUT = 100mA)
and drops to 10nA when not in enabled mode. Unlike regulators with PNP pass devices, quiescent current remains relatively constant over load variation and under dropout conditions.
The REG101 has very low output noise (typically 23µVrms
for VOUT = 3.3V with CNR = 0.01µF), making it ideal for use
in portable communications equipment. Accuracy is maintained over temperature, line, and load variations. Key
parameters are tested over the specified temperature range
(–40°C to +85°C).
The REG101 is well protected—internal circuitry provides a
current limit that protects the load from damage. Thermal
protection circuitry keeps the chip from being damaged by
excessive temperature. The REG101 is available in the
SOT23-5 and the SO-8 packages.

● HIGH ACCURACY: ±1.5% max
● HIGH EFFICIENCY:
IGND = 500µA at IOUT = 100mA
Not Enabled: IGND = 10nA
● 2.5V, 2.8V, 2.85V, 3.0V, 3.3V, 5.0V, AND
ADJUSTABLE OUTPUT VERSIONS
● OTHER OUTPUT VOLTAGES AVAILABLE
UPON REQUEST
● FOLDBACK CURRENT LIMIT
● THERMAL PROTECTION
● SMALL SURFACE-MOUNT PACKAGES:
SOT23-5 and SO-8

APPLICATIONS
●
●
●
●
●
●

PORTABLE COMMUNICATION DEVICES
BATTERY-POWERED EQUIPMENT
PERSONAL DIGITAL ASSISTANTS
MODEMS
BAR-CODE SCANNERS
BACKUP POWER SUPPLIES
Enable

Enable
VOUT

VIN
+

0.1µF

NR

REG101
(Fixed Voltage
Versions)

+

COUT(1)

VIN

VOUT
+

REG101-A

+

COUT(1)

Adj

Gnd

NR = Noise Reduction

0.1µF

R1

Gnd

R2

NOTE: (1) Optional.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2000-2005, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

www.ti.com

ABSOLUTE MAXIMUM RATINGS(1)
Supply Input Voltage, VIN ....................................................... –0.3V to 12V
Enable Input Voltage, VEN ....................................................... –0.3V to VIN
Feedback Voltage, VFB ........................................................ –0.3V to 6.0V
NR Pin Voltage, VNR ............................................................. –0.3V to 6.0V
Output Short-Circuit Duration ...................................................... Indefinite
Operating Temperature Range (TJ) ................................ –55°C to +125°C
Storage Temperature Range (TA) ................................... –65°C to +150°C
Lead Temperature (soldering, 3s, SOT23-5, and SO-8) ..................... +240°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.

ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.

PACKAGE/ORDERING INFORMATION(1)
VOUT(2)

PRODUCT
REG101xx-yyyy/zzz

XX is package designator.
YYYY is typical output voltage (5 = 5.0V, 2.85 = 2.85V, A = Adjustable).
ZZZ is package quantity.

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.
(2) Output voltages from 2.5V to 5.1V in 50mV increments are available; minimum order quantities apply. Contact factory for details and availability.

PIN CONFIGURATIONS
Top View
SO-8

SOT23-5

VOUT(2)

1

8

VIN(3)

VIN

1

VOUT(2)

2

7

VIN(3)

GND

2

NR/Adjust(1)

3

6

NC

Enable

3

GND

4

5

Enable

5

VOUT

4

NR/Adjust(1)

(N Package)

(U Package)

NOTE: (1) For REG101A-A: voltage setting resistor pin. All other models: noise reduction capacitor pin.
(2) Both pin 1 and pin 2 must be connected.
(3) Both pin 7 and pin 8 must be connected.

2

REG101
SBVS026D

ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TJ = –40°C to +85°C.
At TJ = +25°C, VIN = VOUT + 1V (VOUT = 2.5V for REG101-A), VENABLE = 1.8V, IOUT = 2mA, CNR = 0.01µF, and COUT = 0.1µF(1), unless otherwise noted.
REG101NA
REG101UA
PARAMETER
OUTPUT VOLTAGE
Output Voltage
REG101-2.5
REG101-2.8
REG101-2.85
REG101-3.0
REG101-3.3
REG101-5
REG101-A
Reference Voltage
Adjust Pin Current
Accuracy
Over Temperature
vs Temperature
Includes Line and Load
Over Temperature
DC DROPOUT VOLTAGE(2)
For all models
Over Temperature
VOLTAGE NOISE
Without CNR
With CNR (all fixed voltage models)
OUTPUT CURRENT
Current Limit(3)
Over Temperature
Short-Circuit Current

CONDITION

2.5
VREF
IADJ

TEMPERATURE RANGE
Specified Range
Operating Range
Storage Range
Thermal Resistance
SOT23-5 Surface Mount
SO-8 Surface Mount

UNITS

50
±0.8

IOUT = 2mA to 100mA, VIN = (VOUT + 0.4V) to 10V
VIN = (VOUT + 0.6V) to 10V
VDROP

Vn

IOUT = 2mA
IOUT = 100mA
IOUT = 100mA

4
60

f = 10Hz to 100kHz
CNR = 0, COUT = 0
CNR = 0.01µF, COUT = 10µF

ICL
ISC
IOUT = 100mA

IENABLE

10
100
130

mV
mV
mV

1
±1.5
±2.2
±2.0

µVrms
µVrms

23µVrms/V • VOUT
7µVrms/V • VOUT
130
110

VENABLE

±2.7

V
V
V
V
V
V
V
V
µA
%
%
ppm/°C
%
%

5.5
1.267
0.2
±0.5

dVOUT/dT

170
60

mA
mA
mA

65

dB

1.8
–0.2
VENABLE = 1.8V to VIN, VIN = 1.8V to 6.5(4)
VENABLE = 0V to 0.5V
COUT = 1.0µF, RLOAD = 33Ω
COUT = 1.0µF, RLOAD = 33Ω

1
2
200
1.5

220
240

VIN
0.5
100
100

IGND

V
V
nA
nA
µs
ms

°C
°C

160
140

Enable Pin Low
INPUT VOLTAGE
Operating Input Voltage Range(5)
Specified Input Voltage Range
Over Temperature

MAX

2.5
2.8
2.85
3.0
3.3
5

THERMAL SHUTDOWN
Junction Temperature
Shutdown
Reset from Shutdown
GROUND PIN CURRENT
Ground Pin Current

TYP

VOUT

RIPPLE REJECTION
f = 120Hz
ENABLE CONTROL
VENABLE High (output enabled)
VENABLE Low (output disabled)
IENABLE High (output enabled)
IENABLE Low (output disabled)
Output Disable Time
Output Enable Time

MIN

500
650
0.2

µA
µA
µA

1.8
VOUT + 0.4
VOUT + 0.6

10
10
10

V
V
V

–40
–55
–65

+85
+125
+150

°C
°C
°C

IOUT = 2mA
IOUT = 100mA
VENABLE ≤ 0.5V

400
500
0.01

VIN
VIN > 1.8V
VIN > 1.8V
TJ
TJ
TA

θJA
θJA

Junction-to-Ambient
Junction-to-Ambient

200
150

°C/W
°C/W

NOTES: (1) The REG101 does not require a minimum output capacitor for stability. However, transient response can be improved with proper capacitor selection.
(2) Dropout voltage is defined as the input voltage minus the output voltage that produces a 2% change in the output voltage from the value at VIN = VOUT + 1V at fixed
load.
(3) Current limit is the output current that produces a 10% change in output voltage from VIN = VOUT + 1V and IOUT = 2mA.
(4) For VENABLE > 6.5V, see typical characteristic “IENABLE vs VENABLE”.
(5) The REG101 no longer regulates when VIN < VOUT + VDROP (MAX). In drop-out, the impedance from VIN to VOUT is typically less than 1Ω at TJ = +25°C.

REG101
SBVS026D

3

TYPICAL CHARACTERISTICS
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.

OUTPUT VOLTAGE CHANGE vs IOUT
(VIN = VOUT + 1V, Output Voltage % Change
Referred to IOUT = 50mA at +25°C)

LOAD REGULATION vs TEMPERATURE
(VIN = VOUT + 1V)
0.0%

0.80

Output Voltage Change (%)

Output Voltage Change (%)

0.60
0.40
+25°C

0.20

+125°C

0.00
–0.20
–0.40
–55°C

–0.1%

10mA < IOUT < 100mA

–0.2%

–0.3%
2mA < IOUT < 1000mA

–0.60
–0.80
0

10

20

30

40

50

60

70

80

90

–0.4%
–50

100

–25

0

0.10

15

0.08
IOUT = 2mA

5

IOUT = 50mA

0
–5
–10
IOUT = 100mA

–15

1

2

3

75

100

125

IOUT = 100mA

0.06
0.04
0.02
(VOUT + 1V) < VIN < 10V

0.00
–0.02
–0.04
–0.06
–0.08

–20
0

50

LINE REGULATION vs TEMPERATURE

20
Output Voltage Change (%)

Output Voltage Change (mV)

LINE REGULATION
(Referred to VIN = VOUT + 1V at IOUT = 50mA)

10

25

Temperature (°C)

IOUT (mA)

4

5

6

7

8

–0.10
–50

(VOUT + 0.4V) < VIN < 10V
–25

0

VIN – VOUT (V)

25

50

75

100

125

Temperature (°C)

DC DROPOUT VOLTAGE vs TEMPERATURE

DC DROPOUT VOLTAGE vs IOUT
100

100

DC Dropout Voltage (mV)

DC Dropout Voltage (mV)

IOUT = 100mA
80
+125°C
60
+25°C
40
–55°C
20

0
0

10

20

30

40

50

60

IOUT (mA)

4

70

80

90

100

80

60

40

20

0
–50

–25

0

25

50

75

100

125

Temperature (°C)

REG101
SBVS026D

TYPICAL CHARACTERISTICS (Cont.)
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.

OUTPUT VOLTAGE ACCURACY HISTOGRAM

OUTPUT VOLTAGE DRIFT HISTOGRAM

18

30

16

Percentage of Units (%)

Percentage of Units (%)

25
14
12
10
8
6
4

20
15
10
5

2
0

0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

Error (%)

VOUT Drift (ppm/°C)

OUTPUT VOLTAGE vs TEMPERATURE
(Output Voltage % Change Referred
to IOUT = 50mA at +25°C)

GROUND PIN CURRENT, NOT ENABLED
vs TEMPERATURE
1µ

0.50

VENABLE = 0.5V
VIN = VOUT + 1V

0.30

100n

IOUT = 2mA

0.20
0.10
0.00

IGND (A)

Output Voltage Change (%)

0.40

IOUT = 50mA

–0.10

10n

–0.20

1n

–0.30

IOUT = 100mA

–0.40
–0.50
–50

–25

0

25

50

75

100

100p
–50

125

–25

0

25

50

75

100

125

Temperature (°C)

Temperature (°C)

GROUND PIN CURRENT vs IOUT

GROUND PIN CURRENT vs TEMPERATURE

600

600
VOUT = 5V

VOUT = 5.0V

500

IOUT = 100mA

575
550

VOUT = 3.3V
300

IGND (µA)

IGND (µA)

400

VOUT = 2.5V

200

525
VOUT = 3.3V
500
475
450
VOUT = 2.5V

100

425

VIN = VOUT + 1V
0
0

10

20

30

40

50
IOUT (mA)

REG101
SBVS026D

60

70

80

90

100

VIN = VOUT + 1V
400
–50
–25
0

25

50

75

100

125

Temperature (°C)

5

TTYPICAL CHARACTERISTICS (Cont.)
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.

RIPPLE REJECTION vs FREQUENCY

RIPPLE REJECTION vs (VIN – VOUT)

80

30
IOUT = 2mA

REG101-3.3
25
IOUT = 2mA
COUT = 10µF

60
50
IOUT = 100mA

Ripple Rejection (dB)

Ripple Rejection (dB)

70

IOUT = 100mA
COUT = 10µF

40
30
20
COUT = 0µF

10

20
15
10
Frequency = 100kHz
COUT = 10µF
IOUT = 100mA

5

0

0
10

100

1k

10k

100k

1M

10M

0

0.1

0.2

0.3

Frequency (Hz)

0.4

0.5

RMS NOISE VOLTAGE vs COUT
REG101-5.0

1

100

Noise Voltage (µVrms)

Noise Voltage (µVrms)

0.9

REG101-5.0

40
REG101-3.3
30
20
REG101-2.5
10

CNR = 0.01µF
10Hz < BW < 100kHz

0

90
REG101-3.3
80

REG101-2.5

70
60
50
40
CNR = 0µF
10Hz < BW < 100kHz

30
20
1

0.1

10

1

10

COUT (µF)

COUT = 1µF

COUT = 0µF

eN (µV/√Hz)

1

IOUT = 100mA
CNR = 0.01µF

1

COUT = 1µF
0.1
COUT = 0µF

COUT = 10µF

0.01

COUT = 10µF

0.01
10

100

1k
Frequency (Hz)

10k

1k

NOISE SPECTRAL DENSITY
10

IOUT = 100mA
CNR = 0µF

0.1

100
CNR (pF)

NOISE SPECTRAL DENSITY

eN (µV/√Hz)

0.8

110

50

6

0.7

RMS NOISE VOLTAGE vs CNR

60

10

0.6

VIN - VOUT (V)

10k

100k

10

100

1k

10k

100k

Frequency (Hz)

REG101
SBVS026D

TYPICAL CHARACTERISTICS (Cont.)
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.

CURRENT LIMIT vs TEMPERATURE

FOLDBACK CURRENT LIMIT
180

3.5

160

3.0

ICL

140

2.5
2.0

IOUT (mA)

ICL

1.5

VIN = VOUT + 1V
120
100
80

1.0

ISC

ISC

60

0.5
0
40

60

80

100

120

140

160

180

40
–50

–25

0

25

50

LOAD TRANSIENT RESPONSE

LINE TRANSIENT RESPONSE

COUT = 0µF

VOUT

COUT = 10µF
VOUT

IOUT

100mA
10mA

COUT = 0

VOUT

VOUT

5.3V
VIN

10µs/div

50µs/div

TURN-ON

TURN-OFF

250µs/div

COUT = 1.0µF
RLOAD = 33Ω

VOUT

COUT = 0µF
RLOAD = 1600Ω

VENABLE

1V/div

REG101-3.3
VIN = VOUT + 1V
CNR = 0.01µF

COUT = 10µF
RLOAD = 33Ω

1V/div

VOUT

COUT = 10µF
RLOAD = 33Ω

1V/div

1V/div

REG101-3.3
IOUT = 100mA

4.3V

COUT = 0µF
RLOAD = 33Ω

125

COUT = 10µF

COUT = 0µF
RLOAD = 1600Ω

SBVS026D

100

Output Current (mA)

REG101-3.3
VIN = 4.3V

REG101

75

Temperature (°C)

50mV/div

20

200mV/div

200mV/div

0

50mV/div

Output Voltage (V)

REG101-3.3

VENABLE
REG101-3.3
CNR = 0.01µF
200µs/div

7

TYPICAL CHARACTERISTICS (Cont.)
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.

IENABLE vs VENABLE

POWER UP/POWER DOWN

10µ

VOUT = 3.0V
RLOAD = 30Ω

500mV/div

IENABLE (A)

1µ

100n
T = +25°C
T = +125°C

VIN

10n

VOUT

T = –55°C
1n
6

7

8

9

10

1s/div

VENABLE (V)

RMS NOISE VOLTAGE vs CADJ

ADJUST PIN CURRENT vs TEMPERATURE
0.350

80
REG101–A

0.300

VOUT = 3.3V
0.250

COUT = 0.1µF
10Hz < frequency < 100kHz

60

IADJ (µA)

Vn (µVrms)

70

50
40

0.150
0.100

30

0.050
0.000

20
10

200mV/div

0.200

100

1k

10k

–50

100k

10mA

8

25

50

75

100

LOAD TRANSIENT-ADJUSTABLE VERSION

LINE TRANSIENT-ADJUSTABLE VERSION

COUT = 0

VOUT

50mV/div

COUT = 10µF

125

COUT = 0

VOUT

COUT = 10µF

VOUT

VOUT
REG101–A

100mA

0

Temperature (°C)

50mV/div

200mV/div

–25

CADJ (pF)

VIN = 4.3V

5.3V

VOUT = 3.3V
IOUT

REG101–A
IOUT = 100mA
CFB = 0.01µF
VOUT = 3.3V

VIN

4.3V

REG101
SBVS026D

BASIC OPERATION

the input supply voltage. This is recommended to improve
ripple rejection by reducing input voltage ripple.

The REG101 series of LDO (Low Drop-Out) linear regulators offers a wide selection of fixed output voltage versions
and an adjustable output version. The REG101 belongs to a
family of new generation LDO regulators that utilize a
DMOS pass transistor to achieve ultra-low dropout performance and freedom from output capacitor constraints. Ground
pin current remains under 650µA over all line, load, and
temperature conditions. All versions have thermal and overcurrent protection, including foldback current limit.
The REG101 does not require an output capacitor for regulator stability and is stable over most output currents and
with almost any value and type of output capacitor up to
10µF or more. For applications where the regulator output
current drops below several milliamps, stability can be
enhanced by: adding a 1kΩ to 2kΩ load resistor; using
capacitance values less than 10µF; or keeping the effective
series resistance greater than 0.05Ω including the capacitor’s
ESR and parasitic resistance in printed circuit board traces,
solder joints, and sockets.

Figure 1 shows the basic circuit connections for the fixed
voltage models. Figure 2 gives the connections for the
adjustable output version (REG101A) and example resistor
values for some commonly used output voltages. Values for
other voltages can be calculated from the equation shown in
Figure 2.
INTERNAL CURRENT LIMIT
The REG101 internal current limit has a typical value of
170mA. A foldback feature limits the short-circuit current to
a typical short-circuit value of 60mA. This helps to protect
the regulator from damage under all load conditions. A
characteristic of VOUT versus IOUT is given in Figure 3 and
in the Typical Characteristics section.

FOLDBACK CURRENT LIMIT
3.5

Although an input capacitor is not required, it is good analog
design practice to connect a 0.1µF low ESR capacitor across

REG101

In
0.1µF

REG101-3.3
Output Voltage (V)

Enable
VIN

3.0

Gnd

NR

2.0

ICL

1.5
1.0
ICL

VOUT

Out

2.5

0.5

COUT

0

CNR
0.01µF

0

20

40

60

80

100

120

140

160

180

Output Current (mA)
Optional

FIGURE 1. Fixed Voltage Nominal Circuit for REG101.

FIGURE 3. Foldback Current Limit of the REG101-3.3 at
25°C.

Enable
3

EXAMPLE RESISTOR VALUES

5

VOUT

1

VIN

REG101
4

0.1µF

IADJ

2 Gnd

R1

CFB
0.01µF

COUT

VOUT (V)

R1 (W)(1)

R2 (Ω)(1)

2.5

11.3k
1.13k

11.5k
1.15k

3.0

15.8k
1.58k

11.5k
1.15k

3.3

18.7k
1.87k

11.5k
1.15k

5.0

34.0k
3.40k

11.5k
1.15k

Load
Adj
R2

Optional
Pin numbers for SOT23 package.

NOTE: (1) Resistors are standard 1% values.

VOUT = (1 + R1/R2) • 1.267V
To reduce current through divider, increase resistor
values (see table at right).
As the impedance of the resistor divider increases,
IADJ (~200nA) may introduce an error.
CFB improves noise and transient response.

FIGURE 2. Adjustable Voltage Circuit for REG101A.

REG101
SBVS026D

9

OUTPUT NOISE
A precision band-gap reference is used for the internal
reference voltage, VREF. This reference is the dominant
noise source within the REG101 and it generates approximately 29µVrms in the 10Hz to 100kHz bandwidth at the
reference output. The regulator control loop gains up the
reference noise, so that the noise voltage of the regulator is
approximately given by:

RMS NOISE VOLTAGE vs CNR
110
100
REG101-5.0
Noise Voltage (µVrms)

ENABLE
The Enable pin is active HIGH and compatible with standard TTL-CMOS levels. Inputs below 0.5V (max) turn the
regulator off and all circuitry is disabled. Under this condition, ground pin current drops to approximately 10nA. When
a pull-up resistor is used, and operation down to VIN = 1.8V
is required, use values < 50kΩ.

90
REG101-3.3
80

REG101-2.5

70
60
50
40
CNR = 0µF
10Hz < BW < 100kHz

30
20
1

100

10

10k

1k

CNR (pF)

FIGURE 5. Output Noise versus Noise Reduction Capacitor.
R + R2
V
VN = 29 µVrms 1
= 29 µVrms • OUT
R2
VREF

Since the value of VREF is 1.267V, this relationship reduces to:
VN = 23

µVrms
• VOUT
V

Connecting a capacitor, CNR, from the Noise Reduction (NR)
pin to ground, as shown in Figure 4, forms a low-pass filter for
the voltage reference. For CNR = 10nF, the total noise in the
10Hz to 100kHz bandwidth is reduced by approximately a
factor of 2.8 for VO = 3.3V. This noise reduction effect is
shown in Figure 5 and as “RMS Noise Voltage vs CNR” in the
Typical Characteristics section.
Noise can be further reduced by carefully choosing an
output capacitor, COUT. Best overall noise performance is

achieved with very low (< 0.22µF) or very high (> 2.2µF)
values of COUT. See “RMS Noise Voltage vs COUT” in the
Typical Characteristics section.
The REG101 utilizes an internal charge pump to develop an
internal supply voltage sufficient to drive the gate of the
DMOS pass element above VIN. The charge-pump switching noise (nominal switching frequency = 2MHz) is not
measurable at the output of the regulator over most values of
COUT and IOUT.
The REG101 adjustable version does not have the noisereduction pin available, however, the adjust pin is the summing junction of the error amplifier. A capacitor, CFB,
connected from the output to the adjust pin will reduce both
the output noise and the peak error from a load transient. See
the typical characteristics for output noise performance.

VIN

NR
(fixed output
versions only)

Low Noise
Charge Pump
CNR
(optional)

Enable

VREF
(1.26V)

DMOS
Pass
Transistor
VOUT

Over Current
Over Temp
Protection

R1

R2

Adj
(Adjustable
Versions)

REG101
NOTE: R1 and R2 are internal
on fixed output versions.

FIGURE 4. Block Diagram.
10

REG101
SBVS026D

DROP-OUT VOLTAGE
The REG101 uses an N-channel DMOS as the “pass”
element. When the input voltage is within a few tens of
millivolts of the output voltage, the DMOS device behaves
like a resistor. Therefore, for low values of VIN to VOUT, the
regulator’s input-to-output resistance is the RdsON of the
DMOS pass element (typically 600mΩ). For static (DC)
loads, the REG101 will typically maintain regulation down
to VIN to VOUT voltage drop of 60mV at full rated output
current. In Figure 6, the bottom line (DC dropout) shows the
minimum VIN to VOUT voltage drop required to prevent
drop-out under DC load conditions.
For large step changes in load current, the REG101 requires
a larger voltage drop across it to avoid degraded transient
response. The boundary of this “transient drop-out” region is
shown as the top line in Figure 6. Values of VIN to VOUT
voltage drop above this line insure normal transient response.
In the transient dropout region between “DC” and “Transient”, transient response recovery time increases. The time
required to recover from a load transient is a function of both
the magnitude and rate of the step change in load current and
the available “headroom” VIN to VOUT voltage drop. Under
worst-case conditions (full-scale load change with VIN to
VOUT voltage drop close to DC dropout levels), the REG101
can take several hundred microseconds to re-enter the specified window of regulation.

140

Dropout Voltage (mV)

120
Full Scale IOUT
Transient

100
80
60

TRANSIENT RESPONSE
The REG101 response to transient line and load conditions
improves at lower output voltages. The addition of a capacitor (nominal value 0.47µF) from the output pin to ground
may improve the transient response. In the adjustable version, the addition of a capacitor, CFB (nominal value 10nF),
from the output to the adjust pin will also improve the
transient response.
THERMAL PROTECTION
The REG101 has thermal shutdown circuitry that protects
the regulator from damage. The thermal protection circuitry
disables the output when the junction temperature reaches
approximately 160°C, allowing the device to cool. When the
junction temperature cools to approximately 140°C, the
output circuitry is again enabled. Depending on various
conditions, the thermal protection circuit may cycle on and
off. This limits the dissipation of the regulator, but may have
an undesirable effect on the load.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an inadequate heat
sink. For reliable operation, junction temperature should be
limited to 125°C, maximum. To estimate the margin of
safety in a complete design (including heat sink), increase
the ambient temperature until the thermal protection is
triggered. Use worst-case loads and signal conditions. For
good reliability, thermal protection should trigger more than
35°C above the maximum expected ambient condition of
your application. This produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the REG101 has been
designed to protect against overload conditions. It was not
intended to replace proper heat sinking. Continuously running the REG101 into thermal shutdown will degrade reliability.

40
DC
20
0
0

25

50

75

100

125

150

IOUT (mA)

FIGURE 6. Transient and DC Dropout.

REG101
SBVS026D

11

POWER DISSIPATION
The REG101 is available in two different package configurations. The ability to remove heat from the die is different
for each package type and, therefore, presents different
considerations in the printed circuit board (PCB) layout. The
PCB area around the device that is free of other components
moves the heat from the device to the ambient air. While it
is difficult to impossible to quantify all of the variables in a
thermal design of this type, performance data for several
configurations are shown in Figure 7.
Power dissipation depends on input voltage, load condition,
and duty cycle. Power dissipation is equal to the product of
the average output current times the voltage across the
output element, VIN to VOUT voltage drop.

Power dissipation can be minimized by using the lowest
possible input voltage necessary to assure the required
output voltage.
REGULATOR MOUNTING
Solder pad footprint recommendations for the various
REG101 devices are presented in the Application Bulletin
AB-132, “Solder Pad Recommendations for Surface-Mount
Devices” (SBFA015), available from the Texas Instruments
web site (www.ti.com).

PD = (VIN – VOUT ) • I OUT(AVG)

1.2
CONDITIONS
SOT23-5
SO-8

Power Dissipation (W)

1.0
0.8
0.6

PACKAGE

θJA

SOT23-5
SO-8

200°C/W
150°C/W

0.4
0.3
0
0

25

50

75

100

125

Ambient Temperature (°C)

FIGURE 7. Maximum Power Dissipation versus Ambient Temperature for the Various Packages.

12

REG101
SBVS026D

PACKAGE OPTION ADDENDUM

www.ti.com

17-May-2014

PACKAGING INFORMATION
Orderable Device

Status
(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan

Lead/Ball Finish

MSL Peak Temp

(2)

(6)

(3)

Op Temp (°C)

Device Marking
(4/5)

REG101NA-2.5/250

ACTIVE

SOT-23

DBV

5

250

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1G

REG101NA-2.5/250G4

ACTIVE

SOT-23

DBV

5

250

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1G

REG101NA-2.5/3K

ACTIVE

SOT-23

DBV

5

3000

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1G

REG101NA-2.5/3KG4

ACTIVE

SOT-23

DBV

5

TBD

Call TI

Call TI

REG101NA-2.8/250

ACTIVE

SOT-23

DBV

5

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

REG101NA-2.8/250G4

ACTIVE

SOT-23

DBV

5

TBD

Call TI

Call TI

REG101NA-2.85/250

ACTIVE

SOT-23

DBV

5

250

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1N

REG101NA-2.85/3K

ACTIVE

SOT-23

DBV

5

3000

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1N

REG101NA-2.85/3KG4

ACTIVE

SOT-23

DBV

5

TBD

Call TI

Call TI

REG101NA-3.3/250

ACTIVE

SOT-23

DBV

5

250

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1C

REG101NA-3.3/250G4

ACTIVE

SOT-23

DBV

5

250

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1C

REG101NA-3.3/3K

ACTIVE

SOT-23

DBV

5

3000

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1C

REG101NA-3.3/3KG4

ACTIVE

SOT-23

DBV

5

3000

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1C

REG101NA-3/250

ACTIVE

SOT-23

DBV

5

250

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

R01D

REG101NA-3/250G4

ACTIVE

SOT-23

DBV

5

250

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

R01D

REG101NA-3/3K

ACTIVE

SOT-23

DBV

5

3000

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

R01D

REG101NA-3/3KG4

ACTIVE

SOT-23

DBV

5

3000

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

R01D

250

Addendum-Page 1

RO1E

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

17-May-2014

Orderable Device

Status
(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan

Lead/Ball Finish

MSL Peak Temp

(2)

(6)

(3)

Op Temp (°C)

Device Marking
(4/5)

REG101NA-5/250

ACTIVE

SOT-23

DBV

5

250

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1B

REG101NA-5/250G4

ACTIVE

SOT-23

DBV

5

250

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1B

REG101NA-5/3K

ACTIVE

SOT-23

DBV

5

3000

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1B

REG101NA-5/3KG4

ACTIVE

SOT-23

DBV

5

3000

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1B

REG101NA-A/250

ACTIVE

SOT-23

DBV

5

250

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1A

REG101NA-A/250G4

ACTIVE

SOT-23

DBV

5

250

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1A

REG101NA-A/3K

ACTIVE

SOT-23

DBV

5

3000

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1A

REG101NA-A/3KG4

ACTIVE

SOT-23

DBV

5

3000

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

RO1A

REG101NA2.85/250G4

ACTIVE

SOT-23

DBV

5

TBD

Call TI

Call TI

REG101UA-2.5

ACTIVE

SOIC

D

8

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

REG
101U25

REG101UA-2.5G4

ACTIVE

SOIC

D

8

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

REG
101U25

REG101UA-2.8

ACTIVE

SOIC

D

8

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

REG
101U28

REG101UA-2.8/2K5

OBSOLETE

SOIC

D

8

TBD

Call TI

Call TI

REG
101U28

REG101UA-2.8/2K5G4

OBSOLETE

SOIC

D

8

REG101UA-2.85

ACTIVE

SOIC

D

8

REG101UA-2.85G4

ACTIVE

SOIC

D

REG101UA-2.8G4

ACTIVE

SOIC

REG101UA-3

ACTIVE

REG101UA-3.3

ACTIVE

TBD

Call TI

Call TI

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

8

TBD

Call TI

Call TI

D

8

TBD

Call TI

Call TI

SOIC

D

8

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

REG
101U30

SOIC

D

8

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

REG
101U33

75

Addendum-Page 2

REG
101285

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

17-May-2014

Orderable Device

Status
(1)

Package Type Package Pins Package
Drawing
Qty
2500

Eco Plan

Lead/Ball Finish

MSL Peak Temp

(2)

(6)

(3)

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

TBD

Call TI

Call TI

Op Temp (°C)

Device Marking
(4/5)

REG101UA-3.3/2K5

ACTIVE

SOIC

D

8

REG
101U33

REG101UA-3.3/2K5G4

ACTIVE

SOIC

D

8

REG101UA-3.3G4

ACTIVE

SOIC

D

8

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

REG
101U33

REG101UA-3G4

ACTIVE

SOIC

D

8

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

REG
101U30

REG101UA-5

ACTIVE

SOIC

D

8

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

REG
101U50

REG101UA-5/2K5

ACTIVE

SOIC

D

8

2500

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

REG
101U50

REG101UA-5/2K5G4

ACTIVE

SOIC

D

8

2500

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

REG
101U50

REG101UA-5G4

ACTIVE

SOIC

D

8

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

REG
101U50

REG101UA-A

ACTIVE

SOIC

D

8

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

REG
101UA

REG101UA-AG4

ACTIVE

SOIC

D

8

75

Green (RoHS
& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

REG
101UA

(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

Addendum-Page 3

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

17-May-2014

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 4

PACKAGE MATERIALS INFORMATION
www.ti.com

26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)

REG101NA-2.5/250

SOT-23

DBV

5

250

179.0

8.4

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

3.2

3.2

1.4

4.0

8.0

Q3

REG101NA-2.5/3K

SOT-23

DBV

5

3000

179.0

8.4

3.2

3.2

1.4

4.0

8.0

Q3

REG101NA-2.8/250

SOT-23

DBV

5

250

179.0

8.4

3.2

3.2

1.4

4.0

8.0

Q3

REG101NA-2.85/250

SOT-23

DBV

5

250

179.0

8.4

3.2

3.2

1.4

4.0

8.0

Q3

REG101NA-2.85/3K

SOT-23

DBV

5

3000

179.0

8.4

3.2

3.2

1.4

4.0

8.0

Q3

REG101NA-3.3/250

SOT-23

DBV

5

250

179.0

8.4

3.2

3.2

1.4

4.0

8.0

Q3

REG101NA-3.3/3K

SOT-23

DBV

5

3000

179.0

8.4

3.2

3.2

1.4

4.0

8.0

Q3

REG101NA-3/250

SOT-23

DBV

5

250

179.0

8.4

3.2

3.2

1.4

4.0

8.0

Q3

REG101NA-3/3K

SOT-23

DBV

5

3000

179.0

8.4

3.2

3.2

1.4

4.0

8.0

Q3

REG101NA-5/250

SOT-23

DBV

5

250

179.0

8.4

3.2

3.2

1.4

4.0

8.0

Q3

REG101NA-5/3K

SOT-23

DBV

5

3000

179.0

8.4

3.2

3.2

1.4

4.0

8.0

Q3

REG101NA-A/250

SOT-23

DBV

5

250

179.0

8.4

3.2

3.2

1.4

4.0

8.0

Q3

REG101NA-A/3K

SOT-23

DBV

5

3000

179.0

8.4

3.2

3.2

1.4

4.0

8.0

Q3

REG101UA-3.3/2K5

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

REG101UA-5/2K5

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

26-Jan-2013

*All dimensions are nominal

Device

Package Type

Package Drawing

Pins

SPQ

Length (mm)

Width (mm)

Height (mm)

REG101NA-2.5/250

SOT-23

DBV

REG101NA-2.5/3K

SOT-23

DBV

5

250

203.0

203.0

35.0

5

3000

203.0

203.0

35.0

REG101NA-2.8/250

SOT-23

DBV

5

250

203.0

203.0

35.0

REG101NA-2.85/250

SOT-23

DBV

5

250

203.0

203.0

35.0

REG101NA-2.85/3K

SOT-23

DBV

5

3000

203.0

203.0

35.0

REG101NA-3.3/250

SOT-23

DBV

5

250

203.0

203.0

35.0

REG101NA-3.3/3K

SOT-23

DBV

5

3000

203.0

203.0

35.0

REG101NA-3/250

SOT-23

DBV

5

250

203.0

203.0

35.0

REG101NA-3/3K

SOT-23

DBV

5

3000

203.0

203.0

35.0

REG101NA-5/250

SOT-23

DBV

5

250

203.0

203.0

35.0

REG101NA-5/3K

SOT-23

DBV

5

3000

203.0

203.0

35.0

REG101NA-A/250

SOT-23

DBV

5

250

203.0

203.0

35.0

REG101NA-A/3K

SOT-23

DBV

5

3000

203.0

203.0

35.0

REG101UA-3.3/2K5

SOIC

D

8

2500

367.0

367.0

35.0

REG101UA-5/2K5

SOIC

D

8

2500

367.0

367.0

35.0

Pack Materials-Page 2

IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
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www.s-manuals.com



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