RT8231A, RT8231B Datasheet. Www.s Manuals.com. R05 Richtek

User Manual: Marking of electronic components, SMD Codes 24, 2481D, 24=**, 24A, 24C, 24N025S, 24T, 24V, 24Y. Datasheets 1.5SMC24AT3, BSC024N025S G, BZV49-C24, DTC114ECA, DTC114EEB, DTC114EUA, MP2481DH, PSOT24, PSOT24C, RN47A4, RT8231AGQW, SMS24T1, TK71524AS, ZD24-AE3, ZD24-CL2.

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RT8231A/B
Complete DDR Memory Power Supply Controller
General Description
The RT8231A/B provides a complete power supply for
DDR2/DDR3/DDR3L/LPDDR3/DDR4 memory systems. It
integrates a synchronous PWM Buck controller with a
1.5A sink/source tracking linear regulator and buffered low
noise reference.

RT8231A/B supports all of the sleep state controls placing
VTT at high-Z in S3 and discharging VDDQ, VTT and
VTTREF (soft-off) in S4/S5.
The RT8231A/B provides protections including OVP, UVP,
and thermal shutdown. The RT8231A/B is available in the
WQFN-20L 3x3 package.

The PWM controller provides the low quiescent current,
high efficiency, excellent transient response, and high DC
output accuracy needed for stepping down high-voltage
batteries to generate low-voltage chipset RAM supplies
in notebook computers. The constant on-time PWM
control scheme handles wide input/output voltage ratios
with ease and provides 100ns “instant-on” response to
load transients while maintaining a relatively constant
switching frequency.

Applications





DDR2/DDR3/DDR3L/LPDDR3/DDR4 Memory Power
Supplies
Notebook computers
SSTL18, SSTL15 and HSTL bus termination

Pin Configurations

The RT8231A/B achieves high efficiency at a reduced cost
by eliminating the current-sense resistor found in
traditional current mode PWMs. Efficiency is further
enhanced by its ability to drive very large synchronous
rectifier MOSFETs. The Buck conversion allows this device
to directly step down high-voltage batteries for the highest
possible efficiency.

VTT
VLDOIN
BOOT
UGATE
PHASE

(TOP VIEW)

20 19 18 17 16

VTTGND
VTTSNS
GND
VTTREF
VDDQ

The 1.5A sink/source LDO maintains fast transient
response only requiring a 10μF ceramic output capacitor.
In addition, the LDO supply input is available externally
to significantly reduce the total power losses. The

GND

3
4

12
11

9 10

FB
S3
S5
TON
PGOOD

LGATE
PGND
CS
VDD
VID

WQFN-20L 3x3

Simplified Application Circuit
VIN
VVDD

PGOOD
VTT

VDD

TON
RT8231A/B
UGATE
BOOT
PGOOD
PHASE

VTT
VTTSNS
CS
S3
S5
VID

FB
VTTREF
VDDQ
GND

DS8231A/B-05 March 2015

VVDDQ

LGATE

VLDOIN

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1

RT8231A/B
Features




PWM Controller
 Adjustable Current Limit with Low-Side RDS(ON)
Sensing
 Low Quiescent Supply Current
 Quick Load-Step Response within 100ns
 1% VVDDQ Accuracy Over Line and Load
 Adjustable 0.675V to 3.3V Output Range for 1.8V
(DDR2), 1.5V (DDR3), 1.35V (DDR3L), 1.2V (LPDDR3)
and 1.2V (DDR4)
 4.5V to 26V Battery Input Range
 Resistor Adjustable Frequency
 Over-/Under-Voltage Protection
 Internal Voltage Ramp Soft-Start
 Drives Large Synchronous Rectifier MOSFETs
 Power Good Indicator
1.5A LDO (VTT), Buffered Reference (VTTREF)
 Capable to Sink and Source Up to 1.5A
 LDO Input Available to Optimize Power Losses
 Requires Only 10μ
μF Ceramic Output Capacitor
 Integrated Divider Tracks 1/2 VDDQ for both VTT
and VTTREF
 Accuracy ±20mV for both VTTREF and VTT
 Supports High-Z in S3 and Soft-Off in S4/S5
RoHS Compliant and Halogen Free

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Ordering Information
RT8231A/B
Package Type
QW : WQFN-20L 3x3 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
VDDQ and VTT Discharge Control
A : Tracing Mode
B : Non-Tracking Mode
Note :
Richtek products are :


RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.



Suitable for use in SnPb or Pb-free soldering processes.

Marking Information
RT8231AGQW
24= : Product Code

24=YM
DNN

YMDNN : Date Code

RT8231BGQW
3T= : Product Code

3T=YM
DNN

YMDNN : Date Code

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DS8231A/B-05 March 2015

RT8231A/B
Functional Pin Description
Pin No.

Pin Name

Pin Function

VTTGND

Power Ground for the VTT LDO.

VTTSNS

Voltage Sense Input for the VTT LDO. Connect to the terminal of the VTT_LDO
output capacitor.

GND

The exposed pad must be soldered to a large PCB and connected to GND for
maximum power dissipation.

VTTREF

VTTREF Buffered Reference Output.

VDDQ

Reference Input for VTT and VTTREF.

Feedback Voltage Input. Connect to a resistive voltage divider from VDDQ to
GND to adjust the output voltage.

VTT LDO Enable Control Input. Do not leave this pin floating.

PWM Enable Control Input. Do not leave this pin floating.

TON

Set the UGATE On-Time Through a Pull-Up Resistor Connecting to VIN.

PGOOD

Power Good Open-Drain Output. In high state when VDDQ output voltage is
within the target range.

VID

Internal Reference Voltage Setting.

VDD

Supply Voltage Input for the Analog Supply and LGATE Gate Driver.

Current Limit Threshold Setting Input. Connect to GND through the voltage
setting resistor.

PGND

Power Ground for Low-Side MOSFET.

LGATE

Low-Side Gate Driver Output for VDDQ.

PHASE

Switch Node. External inductor connection for VDDQ and behave as the current
sense comparator input for Low-Side MOSFET RDS(ON) sensing.

UGATE

High-Side Gate Driver Output for VDDQ.

BOOT

Bootstrap Supply for High-Side Gate Driver.

VLDOIN

Power Supply for VTT LDO.

VTT

Power Output for the VTT LDO.

3, 21
(Exposed Pad)

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RT8231A/B
Function Block Diagram
Buck Controller
TRIG
VDDQ

On-Time

TON

1-SHOT
VREF

BOOT

+
+
-

Comp

UGATE

PHASE
+

115%VREF
FB

Latch
S1
Q

0.45V

Min. TOFF
TRIG

LGATE
PGND
DEM

85% VREF
SS Int

VDD

SS Timer

Reference
Voltage
Selector

VDD

5µA

Thermal
Shutdown

1/10

VREF

VID

PGOOD

VTT LDO
VDDQ

S5
S3

Non-Tracking
Discharge

VTTREF

Thermal
Shutdown

VLDOIN
+
-

+
-

GND

+
-

VTTSNS

VTT
+
-

VTTGND

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DS8231A/B-05 March 2015

RT8231A/B
Operation
The RT8231A/B is a constant on-time synchronous stepdown controller. In normal operation, the high-side
N-MOSFET is turned on when the output voltage is lower
than VREF, and is turned off after the internal one-shot
timer expires. While the high-side N-MOSFET is turned
off, the low-side N-MOSFET is turned on to conduct the
inductor current until next cycle begins.
Soft-Start (SS)
For internal soft-start function, an internal current source
charges an internal capacitor to build the soft-start ramp
voltage. The output voltage will track the internal ramp
voltage during soft-start interval.
PGOOD
The power good output is an open-drain architecture. When
the soft-start is finished, the PGOOD open-drain output
will be high impedance.
Current Limit
The current limit circuit employs a unique “valley” current
sensing algorithm. If the magnitude of the current sense
signal at PHASE is above the current limit threshold, the
PWM is not allowed to initiate a new cycle. The current
limit threshold can be set with an external voltage setting
resistor on the CS pin.

DS8231A/B-05 March 2015

Over-Voltage Protection (OVP) & Under-Voltage
Protection (UVP)
The output voltage is continuously monitored for overvoltage and under-voltage protection. When the output
voltage exceeds its set voltage threshold( 115% of VOUT),
UGATE goes low and LGATE is forced high. When the
feedback voltage is less than 0.45V, under-voltage
protection is triggered and then both UGATE and LGATE
gate drivers are forced low. The controller is latched until
VDD is re-supplied and exceeds the POR rising threshold
voltage or S5 is reset.
VTT Linear Regulator and VTTREF
This VTT linear regulator employs ultimate fast response
feedback loop so that small ceramic capacitors are enough
for keeping track of VTTREF within 40mV at all conditions,
including fast load transient. The VTTREF block consists
of on-chip 1/2 divider, LPF and buffer. This regulator also
has sink and source capability up to 10mA. Bypass
VTTREF to GND with a 33nF ceramic capacitor for stable
operation.

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RT8231A/B
Absolute Maximum Ratings

(Note 1)

Supply Input Voltage, TON to GND -----------------------------------------------------------------------------------BOOT to PHASE --------------------------------------------------------------------------------------------------------- PHASE to GND
DC ----------------------------------------------------------------------------------------------------------------------------< 20ns ---------------------------------------------------------------------------------------------------------------------- LGATE to GND
DC ----------------------------------------------------------------------------------------------------------------------------< 20ns ---------------------------------------------------------------------------------------------------------------------- UGATE to PHASE
DC ----------------------------------------------------------------------------------------------------------------------------< 20ns ---------------------------------------------------------------------------------------------------------------------- VDD, CS, S3, S5, VTTSNS, VDDQ, VID, VTTREF, VTT, VLDOIN, FB, PGOOD to GND --------------- PGND, VTTGND to GND ------------------------------------------------------------------------------------------------ Other Pins ------------------------------------------------------------------------------------------------------------------ Power Dissipation, PD @ TA = 25°C
WQFN-20L 3x3 ----------------------------------------------------------------------------------------------------------- Package Thermal Resistance (Note 2)
WQFN-20L 3x3, θJA ------------------------------------------------------------------------------------------------------WQFN-20L 3x3, θJC ----------------------------------------------------------------------------------------------------- Junction Temperature ---------------------------------------------------------------------------------------------------- Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------ Storage Temperature Range ------------------------------------------------------------------------------------------- ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------------


Recommended Operating Conditions





−0.3V to 32V
−0.3V to 6V
−0.3V to 32V
−8V to 38V
−0.3V to 6V
−2.5V to 7.5V
−0.3V to 6V
−5V to 7.5V
−0.3V to 6V
−0.3V to 0.3V
−0.3V to 6.5V
3.33W
30°C/W
7.5°C/W
150°C
260°C
−65°C to 150°C
2kV

(Note 4)

Input Voltage, VIN --------------------------------------------------------------------------------------------------------Control Voltage, VDD ----------------------------------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------------------------

4.5V to 26V
4.5V to 5.5V
−40°C to 125°C
−40°C to 85°C

Electrical Characteristics
(VDD = 5V, VIN = 12V, RTON = 620kΩ, TA = 25°C, unless otherwise specified)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

PWM Controller
Quiescent Supply Current

FB Forced abov e the Regulation Point,
VS5 = 5V, VS3 = 0V, Not Switching

135

A

TON Operating Current

RTON = 620k, VIN = 12V

A

IVLDOIN BIAS Current

VS5 = VS3 = 5V, VTT = No Load

A

IVLDOIN Standby Current

VS5 = 5V, VS3 = 0, VTT = No Load

0.1

A

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DS8231A/B-05 March 2015

RT8231A/B
Parameter

Shutdown Current
(VS5 = VS3 = 0V)

FB Error Comparator
Threshold

Symbol

ISHDN

VREF

Test Conditions

Min

Typ

Max

Unit

VDD

0.1

A

TON

0.1

A

S5/S3

1

0.1

A

VLDOIN

0.1

A

VID

0.5

A

VREF = 0.675V/0.75V

1

0.675

3.3

320

400

480

kHz

250

400

550



4.5

5.5

A

GND  PHASE

5

GND  PHASE, RCS = 160k
VFB Falling. For both VID is high or
low.
FB Forced below UV Threshold

0.4

0.45

0.5

s

With Respect to Error Comparator
Threshold

110

115

120

s

3.9

4.2

4.5

VDDQ Voltage Range
Switch Frequency

fSW

RTON = 620k, VIN = 12V,
VDDQ = 1.5V, IOUT = 20A

(Note 5)

Minimum Off-Time
VDDQ Shutdown Discharge
Resistance

VS5 = 0V, VS3 = 0V

Current Sensing
CS Pin Source Current
Zero Crossing Threshold
Fault Protection
Current Limit (Positive)
Output UV Threshold

VUVP

UVP Latch Delay
OVP Threshold

VOVP

OVP Latch Delay

FB Forced above OV Threshold

VDD POR Threshold

Rising Edge, Hysteresis = 120mV,
PWM Disabled below this Level

Voltage Ramp Soft-Start Time

From S5 Going High to VFB = 0.675V

UV Blank Time

From S5 Signal Going High

165

C

Thermal Shutdown

TSD

Driver On-Resistance
UGATE Gate Driver Source

RUGATEsr

BOOT PHASE Forced to 5V

2.5



UGATE Gate Driver Sink

RUGATEsk

BOOT  PHASE Forced to 5V

1.5



LGATE Gate Driver Source

RLGATEsr

DL, High State

2.5



LGATE Gate Driver Sink

RLGATEsk

DL, Low State

0.8

1.6



LGATE Rising (Phase = 1.5V)

UGATE Rising

VDD to BOOT, 10mA

Dead Time
Internal Boost Charging Switch
On-Resistance

DS8231A/B-05 March 2015

ns


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RT8231A/B
Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Logic-High

Logic-Low

0.8

1

750

300

20

15

10

Logic I/O
S3, S5 Input
Voltage
Logic Input Current

S3, S5 = VDD / GND

Logic-High
VID Input
Threshold Voltage Logic-Low

V
A
mV

PGOOD (Upper Side Threshold Decide by OV Threshold)
Trip Threshold (Falling)

Measured at FB, with Respect to
Reference, No Load. Hysteresis = 2%

Fault Propagation Delay

Falling Edge, FB Forced below
PGOOD Trip Threshold

s

Output Low Voltage

ISINK = 1mA

0.4

High State, Forced to 5V

A

VDDQ = VLDOIN = 1.2V/1.35V/1.5V/
1.8V, |IVTT | = 0A

20

VDDQ = VLDOIN = 1.2V/1.35V/1.5V/
1.8V, |IVTT | < 1A

30

VDDQ = VLDOIN = 1.2V/1.35V,
|IVTT | < 1.2A

40

VDDQ = VLDOIN = 1.5V/1.8V,
|IVTT | < 1.5A

40

Leakage Current

I LEAK

VTT LDO

VTT Output Tolerance

VVTTTOL

VTT Source Current Limit

I VTTOCLSRC

VTT = 0V

1.6

2.6

3.6

VTT Sink Current Limit

I VTTOCLSNK

VTT = VDDQ

1.6

2.6

3.6

VTT Leakage Current

I VTTLK

10

A

VTTSNS Leakage Current

I VTTSNSLK

V
S5 = 5V, S3 = 0V, VTT =  VDDQ 
 2

ISINK = 1mA

1

A

VTT Discharge Current

I DSCHRG

VDDQ = 0V, VTT = 0.5V, S5 = S3 = 0V

VTTREF Output Voltage

VVTTREF

V

VVTT = VVTTREF =  VDDQ  ,
2


VVDDQ = 1.5V

0.75

VLDOIN = VVDDQ = 1.5V,
|IVTTREF| < 10mA

15

VLDOIN = VVDDQ = 1.8V,
|IVTTREF| < 10mA

18

VDDQ/2, VTTREF Output
Voltage Tolerance

VVTTREFTOL

VTTREF Source Current Limit

I VTTREFOCL

VVTTREF = 0V

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is a registered trademark of Richtek Technology Corporation.

DS8231A/B-05 March 2015

RT8231A/B
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Not production tested. Test condition refer to electrical characteristics using application circuit.

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RT8231A/B
Typical Application Circuit
(Optional)

VVDD

C1
1µF

R1
100k

C2
10µF

VDD

TON
UGATE

10 PGOOD
20 VTT

PGOOD
VTT
0.675V

RT8231A/B

R2
270k

VTT Control
VDDQ Control

VTTSNS

BOOT
PHASE

9
17
18

7 S3
8 S5

FB 6
VTTREF 4

VDDQ

VTTGND

PGND
3,
GND
21 (Exposed Pad)

VLDOIN
VID

R4
0

L1
1µH

C4
0.1µF

LGATE

C3
10µF x 2

Q1
886N03LS

13 CS

VIN

R3
620k

Q2
886N03LS

R5
16k

C5
220µF
C9

R6
20k

C6
33nF

VVDDQ
1.35V

19
11

Low

Figure 1. Typical Application Circuit with POSCAP Solution

(Optional)

VVDD

C1
1µF

R1
100k

VTT Control
VDDQ Control

C2
10µF

VDD

R2
270k

TON
UGATE

10 PGOOD
20 VTT

PGOOD
VTT
0.675V

RT8231A/B

VTTSNS

BOOT
PHASE

9
17
18

7 S3
8 S5

FB 6
VTTREF 4

VTTGND

PGND
3,
GND
21 (Exposed Pad)

VDDQ
VLDOIN
VID

R4
0
C4
0.1µF

LGATE

Q2
886N03LS

C3
10µF x 2

Q1
886N03LS

13 CS

VIN

R3
620k

C6
33nF

L1
1µH

VVDDQ
1.35V

R7
C7

R5
16k

C5
22µF x 4
C9

R6
20k

19
11

Low

Figure 2. Typical Application Circuit with Pure MLCC Solution

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RT8231A/B
Typical Operating Characteristics
Switching Frequency vs. Load Current

Switching Frequency vs. Load Current

450

500

DDR3L, VIN = 7.4V, VDDQ = 1.35V,
S3 = GND, S5 = 5V, RTON = 620kΩ

Switching Frequency (kHz)1

500

400
350
300
250
200
150
100
50
0

450

DDR3L, VIN = 12V, VDDQ = 1.35V,
S3 = GND, S5 = 5V, RTON = 620kΩ

400
350
300
250
200
150
100
50
0

0.01

0.1

0.01

Load Current (A)

DDR3L, VIN = 19V, VDDQ = 1.35V,
S3 = GND, S5 = 5V, RTON = 620kΩ

400
350
300
250
200
150
100
50

450

DDR4, VIN = 7.4V, VDDQ = 1.2V,
S3 = GND, S5 = 5V, RTON = 620kΩ

400
350
300
250
200
150
100
50

0
0.01

0.1

0.01

Load Current (A)

Switching Frequency vs. Load Current
500

DDR4, VIN = 12V, VDDQ = 1.2V,
S3 = GND, S5 = 5V, RTON = 620kΩ

Switching Frequency (kHz)1

450

0.1

Load Current(A)

Switching Frequency vs. Load Current
500

Switching Frequency (kHz)1

450

Load Current (A)

Switching Frequency vs. Load Current
500

0.1

400
350
300
250
200
150
100
50

450

DDR4, VIN = 19V, VDDQ = 1.2V,
S3 = GND, S5 = 5V, RTON = 620kΩ

400
350
300
250
200
150
100
50

0
0.01

0.1

Load Current (A)
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DS8231A/B-05 March 2015

0.01

0.1

Load Current (A)
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RT8231A/B
Efficiency vs. Load Current
100

Efficiency (%)

Efficiency vs. Load Current
100

60
50
40
30
20
10
0
0.001

60
50
40
30
20
10

DDR3L, VIN = 7.4V, VDDQ = 1.35V, S3 = S5 = 5V
0.010

0.100

1.000

0
0.001

10.000

DDR3L, VIN = 12V, VDDQ = 1.35V, S3 = S5 = 5V
0.010

Load Current (A)

Efficiency (%)

100

60
50
40
30
20

60
50
40
30
20
10

DDR3L, VIN = 19V, VDDQ = 1.35V, S3 = S5 = 5V
0.010

0.100

1.000

0
0.001

10.000

DDR4, VIN = 7.4V, VDDQ = 1.2V, S3 = S5 = 5V
0.010

Load Current (A)

60
50
40
30

10.000

60
50
40
30
20

DDR4, VIN = 12V, VDDQ = 1.2V, S3 = S5 = 5V
0.010

0.100

1.000

Load Current (A)
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1.000

Efficiency vs. Load Current
100

Efficiency (%)

Efficiency vs. Load Current

0
0.001

0.100

Load Current (A)

100

10.000

Efficiency vs. Load Current

0
0.001

1.000

Load Current (A)

100

0.100

10.000

10
0
0.001

DDR4, VIN = 19V, VDDQ = 1.2V, S3 = S5 = 5V
0.010

0.100

1.000

10.000

Load Current (A)
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RT8231A/B
VDDQ Output Voltage vs. Load Current
1.25

1.39

1.24

1.38

1.23

Output Voltage (V)

VDDQ Output Voltage vs. Load Current
1.40

1.37
1.36
1.35
1.34
1.33
1.32

1.22
1.21
1.20
1.19
1.18
1.17

1.31

1.16

DDR3L, VIN = 12V, VDDQ = 1.35V, S3 = S5 = 5V

1.30

DDR4, VIN = 12V, VDDQ = 1.2V, S3 = S5 = 5V

1.15
0.01

0.1

0.01

0.1

VTT Output Voltage vs. Load Current

0.700

0.625

0.695

0.620

0.690

0.615

Output Voltage (V)

VTT Output Voltage vs. Load Current

0.685
0.680
0.675
0.670
0.665
0.660

0.610
0.605
0.600
0.595
0.590
0.585

0.655

DDR3L, VIN = 12V, VTT = 0.675V, S3 = S5 = 5V

0.650

-1.5 -1.2 -0.9 -0.6 -0.3

0.3

0.6

0.9

1.2

0.580

DDR4, VIN = 12V, VTT = 0.6V, S3 = S5 = 5V

0.575

1.5

-1.5 -1.2 -0.9 -0.6 -0.3

Quiescent Current vs. Input Voltage
148

0.9

146

0.8

Shutdown Current (µA)

1.0

144
142
140
138
136
134

No Switching, S3 = GND, S5 = 5V

130
4

DS8231A/B-05 March 2015

0.3

0.6

0.9

1.2

1.5

Shutdown Current vs. Input Voltage

150

132

Load Current (A)

Quiescent Current (µA)

Load Current (A)

0.7
0.6
0.5
0.4
0.3
0.2
0.1

S3 = S5 = GND

0.0
4

Input Voltage (V)

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RT8231A/B
VTT Voltage vs. Temperature
0.625

1.24

0.620

1.23

0.615

1.22

0.610

VTT Voltage (V)

VDDQ Voltage (V)

VDDQ Voltage vs. Temperature
1.25

1.21
1.20
1.19
1.18
1.17

0.605
0.600
0.595
0.590
0.585

1.16

DDR4, VIN = 12V, VDDQ = 1.2V, S3 = S5 = 5V

1.15
-50

-25

100

0.580

DDR4, VIN = 12V, VTT = 0.6V, S3 = S5 = 5V

0.575

125

-50

Temperature (°C)

VDDQ
(1V/Div)

VTT
(1V/Div)

S5
(5V/Div)

PHASE
(10V/Div)
PGOOD
(5V/Div)

100

125

VIN = 12V, VDDQ = 1.2V, S3 = S5 = 5V, ILoad = 10A

Time (1ms/Div)

Tracking Discharge Shutdown

Non-Tracking Discharge Shutdown

VDDQ
(1V/Div)
VTT
(1V/Div)

VTTREF
(1V/Div)

S5
(5V/Div)

No Load, VIN = 12V, VDDQ = 1.2V, S3 = S5 = 5V

Time (200μs/Div)

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14

VDDQ Start Up

VDDQ
(1V/Div)

No Load, VIN = 12V, VDDQ = 1.2V, S3 = S5 = 5V

Temperature (°C)

VDDQ and VTT Start Up

PGOOD
(5V/Div)

-25

No Load, VIN = 12V, VDDQ = 1.2V, S3 = S5 = 5V

Time (200μs/Div)

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DS8231A/B-05 March 2015

RT8231A/B
VTT Load Transient Response

VDDQ Load Transient Response

DDR4, VIN = 12V

VDDQ
(50mV/Div)

VTT
(20mV/Div)

UGATE
(20V/Div)

VTTREF
(20mV/Div)

LGATE
(5V/Div)
DDR4, VIN = 12V

IL
(10A/Div)

IVTT
(2A/Div)
VDDQ = 1.2V, S3 = S5 = 5V, ILoad = −1.5A to 1.5A

VDDQ = 1.2V, S3 = S5 = 5V, ILoad = 0.1A to 10A

Time (40μs/Div)

Time (50μs/Div)

Over Voltage Protection

Under Voltage Protection

VDDQ
(1V/Div)

PHASE
(5V/Div)

UGATE
(20V/Div)

LGATE
(5V/Div)

PGOOD
(5V/Div)

No Load, VIN = 12V, VDDQ = 1.2V, S3 = S5 = 5V

Time (40μs/Div)

DS8231A/B-05 March 2015

VIN = 12V, VDDQ = 1.2V, S3 = S5 = 5V

Time (40μs/Div)

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RT8231A/B
Application Information
The RT8231A/B PWM controller provides the high
efficiency, excellent transient response, and high DC output
accuracy needed for stepping down high voltage batteries
to generate low voltage chipset RAM supplies in notebook
computers. Richtek's Mach ResponseTM technology is
specifically designed for providing 100ns “instant-on”
response to load steps while maintaining a relatively
constant operating frequency and inductor operating point
over a wide range of input voltages. The topology solves
the poor load transient response timing problems of fixedfrequency current mode PWMs, and avoids problems
caused by widely varying switching frequencies in
conventional constant-on-time and constant- off-time PWM
schemes. The DRV TM mode PWM modulator is
specifically designed to have better noise immunity for
such a single output application.
The 1.5A sink/source LDO maintains fast transient
response, only requiring 10μF of ceramic output
capacitance. In addition, the LDO supply input is available
externally to significantly reduce the total power losses.
The RT8231A/B supports all of the sleep state controls,
placing VTT at high-Z in S3 and discharging VDDQ, VTT
and VTTREF (soft-off) in S4/S5.
PWM Operation
The Mach ResponseTM DRVTM mode controller relies on
the output filter capacitor's Effective Series Resistance
(ESR) to act as a current-sense resistor, so the output
ripple voltage provides the PWM ramp signal. Referring to
the function block diagrams of the RT8231A/B, the
synchronous high-side MOSFET is turned on at the
beginning of each cycle. After the internal one-shot timer
expires, the MOSFET will be turned off. The pulse width
of this one-shot is determined by the converter's input
and output voltages to keep the frequency fairly constant
over the entire input voltage range. Another one-shot sets
a minimum off-time (400ns typ.).
On-Time Control
The on-time one-shot comparator has two inputs. One
input looks at the output voltage, while the other input
samples the input voltage and converts it to a current.
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16

This input voltage proportional current is used to charge
an internal on-time capacitor. The on-time is the time
required for the voltage on this capacitor to charge from
zero volts to VVDDQ, thereby making the on-time of the
high-side switch directly proportional to the output voltage
and inversely proportional to the input voltage. This
implementation results in a nearly constant switching
frequency without the need of a clock generator, as shown
below :

tON  3.85p x RTON x VVDDQ / (VIN  0.5) + RTON x 1 
And then the switching frequency is :
f  VVDDQ / (VIN x t ON )

where RTON is the resistor connected from VIN to the TON
pin. Note that the setting on-time must be longer than
100ns (typ.) of the minimum on-time and shorter than 3μs
(typ.) of the maximum on-time.
Diode Emulation Mode
In diode emulation mode, the RT8231A/B automatically
reduces switching frequency at light load conditions to
maintain high efficiency. As the output current decreases
from heavy load condition, the inductor current will also
be reduced and eventually come to the point where its
valley touches zero current, which is the boundary between
continuous conduction and discontinuous conduction
modes. To emulate the behavior of diodes, the low-side
MOSFET allows only partial negative current to flow when
the inductor freewheeling current reaches negative. As the
load current is further decreased, it takes longer and longer
time to discharge the output capacitor to the level that
requires the next “ON” cycle. The on-time is kept the
same as that in the heavy load condition. In contrast, when
the output current increases from light load to heavy load,
the switching frequency increases to the preset value as
the inductor current reaches the continuous condition. The
transition load point to the light load operation is shown in
Figure 3 and can be calculated as follows :
V  VVDDQ
ILOAD(SKIP)  IN
x tON
2L
where tON is the on-time.

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RT8231A/B
IL

The RT8231A/B uses the on resistance of the synchronous
rectifier as the current sense element and supports
temperature compensated MOSFET RDS(ON) sensing. The

Slope = (VIN - VVDDQ) / L
IPEAK

ILOAD = IPEAK / 2

tON

Figure 3. Boundary Condition of CCM/DCM
The switching waveforms may appear noisy and
asynchronous when light load causes diode-emulation
operation, but this is a normal operating condition that
results in high light load efficiency. Trade offs in DEM
noise vs. light load efficiency is made by varying the
inductor value. Generally, low inductor values produce a
broader efficiency vs. load curve, while higher values result
in higher full load efficiency (assuming that the coil
resistance remains fixed) and less output voltage ripple.
The disadvantages for using higher inductor values include
larger physical size and degraded load transient response
(especially at low input voltage levels).
Current Limit Setting for VDDQ (CS)
The RT8231A/B provides cycle-by-cycle current limit
control. The current limit circuit employs a unique “valley”
current sensing algorithm. If the magnitude of the current
sense signal at PHASE is above the current limit
threshold, the PWM is not allowed to initiate a new cycle
(Figure 4). The actual peak current is greater than the
current limit threshold by an amount equal to the inductor
ripple current. Therefore, the exact current limit
characteristic and maximum load capability are a function
of the sense resistance, inductor value, battery and output
voltage.
IL
IPEAK
ILOAD
ILIM

DS8231A/B-05 March 2015

setting resistor, RILIM, between the CS pin and VDD sets
the current limit threshold. The CS pin sources an internal
5μA (typ.) current source at room temperature. This current
has a 4700ppm/°C temperature slope to compensate the
temperature dependency of RDS(ON). When the voltage
drop across the low-side MOSFET equals the voltage
across the RILIM setting resistor, the positive current limit
will activate. The high-side MOSFET will not be turned on
until the voltage drop across the low-side MOSFET falls
below the current limit threshold.
Choose a current limit setting resistor via the following
equation :

RLIMIT  ILIMIT x RDS(ON)  10/ 5μA
And then the CS pin voltage is
VCS = RLIMIT x 5μA
Note that the VCS should be set from 0.4V to 3V.
Carefully observe the PCB layout guidelines to ensure
that noise and DC errors do not corrupt the current-sense
signal seen by PHASE and PGND.
Current Protection for VTT
The LDO has an internally fixed constant over-current limit
of 2.6A while operating at normal condition. From then
on, when the output voltage exceeds 20% of its set
voltage, the internal power good signal will transit from
high to low.
MOSFET Gate Driver (UGATE, LGATE)
The high-side driver is designed to drive high current, low
RDS(ON) N-MOSFET(s). When configured as a floating
driver, 5V bias voltage is delivered from the VDD supply.
The average drive current is proportional to the gate charge
at VGS = 5V times switching frequency. The instantaneous
drive current is supplied by the flying capacitor between
the BOOT and PHASE pins.
A dead-time to prevent shoot through is internally
generated between high-side MOSFET off to low-side
MOSFET on, and low-side MOSFET off to high-side
MOSFET on.
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RT8231A/B
The low-side driver is designed to drive high current, low
RDS(ON) N-MOSFET(s). The internal pull down transistor
that drives LGATE low is robust, with a 0.8Ω typical onresistance. A 5V bias voltage is delivered from the VDD
supply. The instantaneous drive current is supplied by the
flying capacitor between VDD and PGND.
For high current applications, some combinations of highand low-side MOSFETs may cause excessive gate drain
coupling, which leads to efficiency killing, EMI producing
shoot through currents. This is often remedied by adding
a resistor in series on BOOT, which increases the turnon rising time of the high-side MOSFET without degrading
the turn-off time (Figure 5).
VIN

BOOT

UGATE

begins once the chip is enabled. During soft-start, internal
bandgap circuit gradually ramps up the reference voltage
from zero. The maximum reference value is set externally
as described in Table 1.
The soft-start function of VTT is achieved by the current
limit and VTTREF voltage through the internal RC delay
ramp up after S3 is high. During VTT startup, the current
limit level is 2.6A. This allows the output to start up
smoothly and safely under enough source/sink ability.
While TSS is the rising period of VTT , the formula used
to calculated this rising period is TSS = (VTT x CVTT)/
IVTTOCL, it's base on the value of output capacitor CVTT, the
settled output voltage VTT and the output current limit
IVTTOCL.
VDDQ

VTTREF

TSS

PHASE

Figure 5. Increasing the UGATE Rise Time
VTT

Power Good Output (PGOOD)
The power good output is an open drain output that requires
a pull-up resistor. When the output voltage is 15% below
its set voltage, PGOOD will be pulled low. It is held low
until the output voltage returns to 87% of its set voltage
once more. During soft-start, PGOOD is actively held low
and only allowed to be pulled high after soft-start is over
and the output reaches 87% of its set voltage. There is a
5μs delay built into PGOOD circuitry to prevent false
transition.
POR Protection
The RT8231A/B has a VDD supply power on reset
protection (POR). When the VDD voltage is higher than
4.2V (typ.), VDDQ, VTT and VTTREF will be activated.
This is a non-latch protection.
Soft-Start
The RT8231A/B provides an internal soft-start function to
prevent large inrush current and output voltage overshoot
when the converter starts up. Soft-start (SS) automatically
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18

TSS = (VTT x CVTT)/IVTTOCL

Output Over-Voltage Protection (OVP)
The output voltage can be continuously monitored for overvoltage condition. If the output exceeds 15% of its set
voltage threshold, over voltage protection will be triggered
and the LGATE low-side gate driver will be forced high.
This activates the low-side MOSFET switch which rapidly
discharges the output capacitor and reduces the output
voltage. There is a 5μs latch delay built into the overvoltage protection circuit. The RT8231A/B will be latched
if the output voltage remains above the OV threshold after
the latch delay period. The latched OVP will pull low
PGOOD and can only be released by VDD power on reset
or S5.
Note that latching the LGATE high will cause the output
voltage to dip slightly negative when energy has been
previously stored in the LC tank circuit. For loads that
cannot tolerate a negative voltage, place a power Schottky
diode across the output to act as a reverse polarity clamp.
If the over voltage condition is caused by a shorted highis a registered trademark of Richtek Technology Corporation.

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RT8231A/B
side switch, turning the low-side MOSFET on 100% will
create an electrical shorted circuit between the battery
and GND, to blow the fuse and disconnecting the battery
from the output.
Output Under-Voltage Protection (UVP)
The output voltage can be continuously monitored for undervoltage condition. When UVP is enabled, the under voltage
protection is triggered if the FB is less than 0.45V. Then,
both UGATE and LGATE gate drivers will be forced low
until next VDD or S5 reset. During soft-start, the UVP has
a blanking time around 5ms.
Thermal Protection
The RT8231A/B features a thermal protection function. If
the temperature exceeds the threshold, 165°C (typ.), the
PWM output, VTTREF and VTT will be shut down. The
RT8231A/B is latched once thermal shutdown is triggered
and can only be released by VDD power on reset or S5.
Output Voltage Setting (FB)
Connect a resistive voltage divider at FB between VDDQ
and GND to adjust the respective output voltage between
0.675V and 3.3V (Figure 6). Choose R2 to be
approximately 10kΩ and solve for R1 using the equation
as follows :
  R1  
VVDDQ (Valley)  VREF x  1  

  R2  
where VREF is 0.75V or 0.675V depends on the VID setting
in Table 1.
Note that when the RT8231A/B operates from CCM to
DEM, the reference voltage will add 10mV offset.
VIN
VVDDQ
UGATE
PHASE
LGATE
R1
VDDQ
FB
R2
GND

DS8231A/B-05 March 2015

Table 1. VID and Reference Voltage Setting

VID

Reference Voltage (V)

High

0.675

Low

0.75

When the reference voltage is changed from 0.75V to
0.675V, the OVP latch will be masked for 120μs to prevent
an unexpected shutdown.
VTT Linear Regulator and VTTREF
The RT8231A/B integrates a high performance low dropout
linear regulator that is capable of sourcing and sinking
currents up to 1.5A. This VTT linear regulator employs
ultimate fast response feedback loop so that small ceramic
capacitors are enough for keeping track of VTTREF within
40mV at all conditions, including fast load transient. To
achieve tight regulation with minimum effect of wiring
resistance, a remote sensing terminal, VTTSNS, should
be connected to the positive node of the VTT output
capacitor(s) as a separate trace from the VTT pin. For
stable operation, total capacitance of the VTT output
terminal can be equal to or greater than 10μF. It is
recommended to attach two 10μF ceramic capacitors in
parallel to minimize the effect of ESR and ESL. If ESR of
the output capacitor is greater than 2mΩ, insert an RC
filter between the output and VTTSNS input to achieve
loop stability. The RC filter time constant should be almost
the same or slightly lower than the time constant made
by the output capacitor and its ESR. The VTTREF block
consists of on-chip 1/2 divider, LPF and buffer. This regulator
also has sink and source capability up to 10mA. Bypass
VTTREF to GND with a 33nF ceramic capacitor for stable
operation.
Output Management by S3, S5 Control
In DDR2/DDR3 memory applications, it is important to
always keep VDDQ higher than VTT/VTTREF, even during
start-up and shutdown. The RT8231A/B provides this
management by simply connecting both S3 and S5
terminals to the sleep-mode signals such as SLP_S3 and
SLP_S5 in notebook PC system. All VDDQ, VTTREF and
VTT are turned on at S0 state (S3 = S5 = high). In S3
state (S3 = low, S5 = high), VDDQ and VTTREF voltages
are kept on while VTT is turned off and left at high
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RT8231A/B
impedance (high-Z) state. The VTT output is floated and
does not sink or source current in this state. In S4/S5
states (S3 = S5 = low), all of the three outputs are disabled
and discharged to ground. The code of each state
represents the following: S0 = full ON, S3 = suspend to
RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF.
(See Table 2)
Table 2. S3 and S5 truth table
STATE S3

VDDQ

VTTREF

VTT

Off (Hi-Z)

S4/S5

Off
Off
Off
(Discharge) (Discharge) (Discharge)

VDDQ and VTT Discharge Control
The RT8231A/B discharges VDDQ, VTTREF and VTT
outputs when S5 is low or in the S4/S5 state. The two
discharge modes can be selected from different part no.
as shown in Table 3.
Table 3. Discharge Selection

Part No.

Discharge Mode

RT8231A

Tracking discharge

RT8231B

Non-tracking discharge

When in tracking discharge mode, the RT8231A
discharges outputs through the internal VTT regulator
transistors and VTT output tracks half of the VDDQ voltage
during this discharge. Note that the VDDQ discharge
current flows via VLDOIN to VTTGND; thus VLDOIN must
be connected to VDDQ in this mode. The internal LDO
can handle up to 1.5A and discharge quickly.
When in non-tracking discharge mode, the RT8231B
discharges outputs using internal MOSFETs which are
connected to VDDQ and VTT. The current capability of
these MOSFETs is limited to discharge slowly. Note that
the VDDQ discharge current flows from VDDQ to GND in
this mode. In order to discharge smoothly, the RT8231B
provides a special function that the low-side MOSFET
will switch periodically as phase pin with remaining
voltage.

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20

Output Inductor Selection
The switching frequency (on-time) and operating point (%
ripple or LIR) determine the inductor value as follows :
t
x (VIN  VVDDQ )
L  ON
LIR x ILOAD(MAX)
where LIR is the ratio of the peak-to-peak ripple current to
the maximum average inductor current.
Find a low loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite cores
are often the best choice, although powdered iron is
inexpensive and can work well at 200kHz. The core must
be large enough and not saturate at the peak inductor
current (IPEAK) :
IPEAK  ILOAD(MAX)  (LIR /2) x ILOAD(MAX) 
This inductor ripple current also impacts transient-response
performance, especially at low VIN − VVDDQ differences.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output filter
capacitors by a sudden load step. The peak amplitude of
the output transient (VSAG) is also a function of the output
transient. VSAG also features a function of the maximum
duty factor, which can be calculated from the on-time and
minimum off-time :

VSAG


(ILOAD )2 x L x (tON  tOFF(MIN) )

2 x COUT x  VIN x tON  VVDDQ x (tON  tOFF(MIN) )
where minimum off-time, tOFF(MIN), is 400ns typically.
Output Capacitor Selection
The output filter capacitor must have low enough ESR to
meet output ripple and load-transient requirements, yet
have high enough ESR to satisfy stability requirements.
Also, the capacitance must be high enough to absorb the
inductor energy going from a full-load to no-load condition
without tripping the OVP circuit.
For CPU core voltage converters and other applications
where the output is subject to violent load transients, the
output capacitor's size depends on how much ESR is
needed to prevent the output from dipping too low under a
load transient. Ignoring the sag due to finite capacitance :
VPP
ESR 
ILOAD(MAX)
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RT8231A/B
In non-CPU applications, the output capacitor's size
depends on how much ESR is needed to maintain an
acceptable level of output voltage ripple :

Maximum Power Dissipation (W)1

ESR 

3.6

VPP
LIR x ILOAD(MAX)

where VP−P is the peak-to-peak output voltage ripple.
Organic semiconductor capacitor(s) or specialty polymer
capacitor(s) are recommended.
The amount of overshoot due to stored inductor energy
can be calculated as :
VSOAR 

where IPEAK is the peak inductor current.

3.0
2.4
1.8
1.2
0.6
0.0
0

(IPEAK ) x L
2 x COUT x VVDDQ

Four-Layer PCB

100

125

Ambient Temperature (°C)

Figure 7. Derating Curve of Maximum Power Dissipation

Thermal Considerations

Layout Considerations

For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :

Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to the converter
instability. Certain points must be considered before
starting a layout for the RT8231A/B.


Keep current limit setting network as close as possible
to the IC. Routing of the network should avoid coupling
to high voltage switching node.

where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.



Connections from the drivers to the respective gate of
the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance.

For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-20L 3x3 package, the thermal resistance, θJA, is
30°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :



All sensitive analog traces and components such as
VDDQ, FB, PGND, PGOOD, CS, VDD, and TON should
be placed away from high voltage switching nodes such
as PHASE, LGATE, UGATE, and BOOT to avoid
coupling. Use internal layer(s) as ground plane(s) and
shield the feedback trace from power traces and
components.

P D(MAX) = (125°C − 25°C) / (30°C/W) = 3.33W for
WQFN-20L 3x3 package



VLDOIN should be connected to VDDQ output with short
and wide trace. If different power source is used for
VLDOIN, an input bypass capacitor should be placed as
close as possible to the pin with short and wide trace.



The output capacitor for VTT should be placed close to
the pin with short and wide connection in order to avoid
additional ESR and/or ESL of the trace.

PD(MAX) = (TJ(MAX) − TA) / θJA

The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curves in Figure 7 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.

DS8231A/B-05 March 2015

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21

RT8231A/B


It is strongly recommended to connect VTTSNS to the
positive node of VTT output capacitor(s) as a separate
trace from the high current power line to avoid additional
ESR and/or ESL. If it is needed to sense the voltage of
the point of the load, it is recommended to attach the
output capacitor(s) at that point. It is also recommended
to minimize any additional ESR and/or ESL of ground
trace between the GND pin and the output capacitor(s).



Current sense connections must always be made using
Kelvin connections to ensure an accurate signal, with
the current limit resistor located at the device.



Power sections should connect directly to ground
plane(s) using multiple vias as required for current
handling (including the chip power ground connections).
Power components should be placed as close to the IC
as possible to minimize loops and reduce losses.

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is a registered trademark of Richtek Technology Corporation.

DS8231A/B-05 March 2015

RT8231A/B
Outline Dimension

DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.

Symbol

Dimensions In Millimeters

Dimensions In Inches

Min

Max

Min

Max

0.700

0.800

0.028

0.031

0.000

0.050

0.000

0.002

0.175

0.250

0.007

0.010

0.150

0.250

0.006

0.010

2.900

3.100

0.114

0.122

1.650

1.750

0.065

0.069

2.900

3.100

0.114

0.122

1.650

1.750

0.065

0.069

e
L

0.400
0.350

0.016
0.450

0.014

0.018

W-Type 20L QFN 3x3 Package

Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

DS8231A/B-05 March 2015

www.richtek.com
23

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