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RT9173D
Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator
General Description

Features

The RT9173D is a simple, cost-effective and high-speed
linear regulator designed to generate termination voltage
in double data rate (DDR) memory system to comply with
the JEDEC SSTL_2 and SSTL_18 or other specific
interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices
requirements. The regulator is capable of actively sinking
or sourcing continuous 2A or up to 3A transient peak
current while regulating an output voltage to within 40mV.
The output termination voltage cab be tightly regulated to
track 1/2VDDQ by two external voltage divider resistors or
the desired output voltage can be pro-grammed by externally
forcing the REFEN pin voltage.

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The RT9173D also incorporates a high-speed differential
amplifier to provide ultra-fast response in line/load transient.
Other features include extremely low initial offset voltage,
excellent load regulation, current limiting in bi-directions
and on-chip thermal shut-down protection.

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The RT9173D are available in the SOP-8 (Exposed Pad)
surface mount packages.

Ordering Information
RT9173D

Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
Note :

Sink and Source Current
` 2A Continuous Current
` Peak 3A for DDRI and DDRII
` Peak 2.5A for DDRIII
Integrated Power MOSFETs
Generates Termination Voltage for SSTL_2,
SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces
High Accuracy Output Voltage at Full-Load
Output Adjustment by Two External Resistors
Low External Component Count
Shutdown for Suspend to RAM (STR) Functionality
with High-Impedance Output
Current Limiting Protection
On-Chip Thermal Protection
Available in SOP-8 (Exposed Pad) Packages
VIN and VCNTL No Power Sequence Issue
RoHS Compliant and 100% Lead (Pb)-Free

Applications
z
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Package Type
SP : SOP-8 (Exposed Pad-Option 1)

Ideal for DDR-I, DDR-II and DDR-III VTT Applications

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Desktop PCs, Notebooks, and Workstations
Graphics Card Memory Termination
Set Top Boxes, Digital TVs, Printers
Embedded Systems
Active Termination Buses
DDR-I, DDR-II and DDR-III Memory Systems

Pin Configurations

Richtek products are :
`

ments of IPC/JEDEC J-STD-020.
`

(TOP VIEW)

RoHS compliant and compatible with the current requireSuitable for use in SnPb or Pb-free soldering processes.

8

VIN
GND

2

REFEN

3

VOUT

7

GND
6
9
4
5

NC
NC
VCNTL
NC

SOP-8 (Exposed Pad)

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RT9173D
Typical Application Circuit
VCNTL = 3.3V
VIN = 2.5V/1.8V/1.5V

RTT
R1

VIN

2N7002
EN

VCNTL

R2

CSS

CCNTL

CIN

RT9173D
REFEN
VOUT
GND

COUT

GND

R1 = R2 = 100kΩ, RTT = 50Ω / 33Ω / 25Ω
COUT(MIN) = 10μF (Ceramic) + 1000μF under the worst case testing condition
CSS = 1μF, CIN = 470μF (Low ESR), CCNTL = 47μF

Test Circuit
2.5V/1.8V/1.5V

VIN
1.25V/0.9V/0.75V

3.3V

VCNTL

RT9173D
REFEN
VOUT

VOUT

GND

Figure 1. Test Circuit for Typical Operating Characteristics Curves

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DS9173D-07 April 2011

RT9173D
Functional Pin Description
VIN (Pin 1)

VOUT (Pin 4)

Input voltage which supplies current to the output pin.
Connect this pin to a well-decoupled supply voltage. To
prevent the input rail from dropping during large load
transient, a large, low ESR capacitor is recommended to
use. The capacitor should be placed as close as possible
to the VIN pin.

Regulator output. VOUT is regulated to REFEN voltage
that is used to terminate the bus resistors. It is capable of
sinking and sourcing current while regulating the output
rail. To maintain adequate large signal transient response,
typical value of 1000μF AL electrolytic capacitor with 10μF
ceramic capacitors are recommended to reduce the effects
of current transients on VOUT.

GND [Pin 2, Exposed pad (9)]

VCNTL (Pin 6)

Common Ground (Exposed pad is connected to GND).
The GND pad area should be as large as possible and
using many vias to conduct the heat into the buried GND
plate of PCB layer.

VCNTL supplies the internal control circuitry and provides
the drive voltage. The driving capability of output current is
proportioned to the VCNTL. Connect this pin to 3.3V bias
supply to handle large output current with at least 10μF
capacitor from this pin to GND.

REFEN (Pin 3)
Reference voltage input and active low shutdown control
pin. Two resistors dividing down the VIN voltage on the pin
to create the regulated output voltage. Pulling the pin to
ground turns off the device by an open-drain, such as
2N7002, signal N-MOSFET.

NC (Pin 5, 7, 8)
No Internal Connect.

Function Block Diagram
VCNTL

VIN

Current Limit
Thermal Protection

+

REFEN

VOUT

EA

GND

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RT9173D
Absolute Maximum Ratings
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(Note 1)

Input Voltage, VIN ---------------------------------------------------------------------------------------------------Control Voltage, VCNTL ---------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) ---------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------------SOP-8 (Exposed Pad), θJC ---------------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Mode) ----------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------

Recommended Operating Conditions
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6V
6V
1.33W
75°C/W
28°C/W
125°C
260°C
–65°C to 150°C
2kV
200V

(Note 4)

Input Voltage, VIN ---------------------------------------------------------------------------------------------------- 2.5V to 1.5V ± 5%
Control Voltage, VCNTL ---------------------------------------------------------------------------------------------- 5V or 3.3V ± 5%
Ambient Temperature Range -------------------------------------------------------------------------------------- −40°C to 85°C
Junction Temperature Range -------------------------------------------------------------------------------------- −40°C to 125°C

Electrical Characteristics
(VIN = 2.5V/1.8V/1.5V, VCNTL = 3.3V, VREFEN = 1.25V/0.9V/0.75V, COUT = 10μF (Ceramic), TA = 25° C, unless otherwise specified)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Input
VCNTL Operation Current

ICNTL

IOUT = 0A

--

1

2.5

mA

Standby Current (Note 5)

ISTBY

V REFEN < 0.2V (Shutdown),
RLOAD = 180Ω

--

50

90

μA

Output Offset Voltage (Note 6)

VOS

IOUT = 0A

−20

--

+20

mV

Load Regulation (Note 7)

ΔV LOAD

−20

--

+20

mV

--

3.4

--

A

Output (DDR / DDR II / DDR III)

IOUT = +2A
IOUT = −2A

Protection
Current limit

ILIM

V IN = 2.5V/1.8V/1.5V

Thermal Shutdown Temperature

TSD

3.3V ≤ VCNTL ≤ 5V

125

170

--

°C

Thermal Shutdown Hysteresis

ΔTSD

3.3V ≤ VCNTL ≤ 5V

--

35

--

°C

VIH

Enable

0.6

--

--

VIL

Shutdown

--

--

0.2

REFEN Shutdown
Shutdown Threshold

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RT9173D
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity test board (4 Layers,
2S2P) of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for SOP-8 (Exposed
Pad) package.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on
REFEN pin (VIL < 0.2V). It is measured with VIN = VCNTL = 5V.
Note 6. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN.
Note 7. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load
regulation in the load range from 0A to 2A.

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RT9173D
Typical Operating Characteristics
Output Voltage vs. Temperature

Output Voltage vs. Temperature
0.77

0.92

VIN = 1.5V

0.915

Output Voltage (V)

0.765

Output Voltage (V)

VIN = 1.8V

0.76
0.755
0.75

0.91
0.905
0.9
0.895

0.745

0.89

0.74
-50

-25

0

25

50

75

100

-50

125

-25

0

Temperature (°C)

100

125

Shutdown Threshold vs. Temperature

VIN = 2.5V

VCNTL = 5V, Turn On

0.55

Shutdown Threshold (V)

Output Voltage (V)

75

0.6

1.265
1.26
1.255
1.25
1.245

VCNTL = 5V, Turn Off

0.5
0.45
0.4

VCNTL = 3.3V, Turn On

0.35

VCNTL = 3.3V, Turn Off
0.3
0.25

1.24
-50

-25

0

25

50

75

100

-50

125

-25

0

Temperature (°C)

4

VIN

75

100

125

Vcntl Current vs. Temperature

VIN = 1.8V, VCNTL = 3.3V
VIN = 1.8V, VCNTL = 5V
= 2.5V, VCNTL = 3.3V

0.55

VIN = 2.5V, VCNTL = 5V

3.5
3

VIN = 1.5V, VCNTL = 5V
2.5

50

0.6

Vcntl Current (mA)

4.5

25

Temperature (°C)

VIN Current vs. Temperature
5

V IN Current (mA)

50

Temperature (°C)

Output Voltage vs. Temperature
1.27

25

0.5

VIN

VIN = 1.8V, VCNTL = 3.3V
VIN = 1.8V, VCNTL = 5V
VIN = 2.5V, VCNTL = 3.3V
= 2.5V, VCNTL = 5V

0.45
0.4

VIN = 1.5V, VCNTL = 5V
VIN = 1.5V, VCNTL = 3.3V

0.35

VIN = 1.5V, VCNTL = 3.3V

2

0.3
-50

-25

0

25

50

Temperature (°C)

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75

100

125

-50

-25

0

25

50

75

100

125

Temperature (°C)

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RT9173D
Sink Current Limit vs. Temperature

Source Current Limit vs. Temperature
4.5

VIN = 1.8V, VCNTL = 5V
VIN = 1.8V, VCNTL = 3.3V
VIN = 2.5V, VCNTL = 5V
VIN = 2.5V,
VCNTL = 3.3V

4

3.5

3

Sink Current Limit (A)

Source Current Limit (A)

4.5

VIN = 1.5V, VCNTL = 5V
VIN = 1.5V, VCNTL = 3.3V

2.5

-25

0

25

50

75

100

3.5

3

VIN = 1.5V, VCNTL = 5V
VIN = 1.5V, VCNTL = 3.3V

2.5

0

25

50

75

100

Temperature (°C)

0.9VTT @ 2A Transient Response

0.9VTT @ 2A Transient Response

Sink

Output Voltage
Transient (mV)

VIN = 1.8V, VCNTL = 3.3V, VOUT = 0.9V

20
0

Output Current
(A)

-20
2
1
Swing Frequency : 1kHz

VIN = 1.8V, VCNTL = 3.3V, VOUT = 0.9V

Source

20
0
-20
2
1
0

Swing Frequency : 1kHz

Time (250μs/Div)

0.75VTT @ 2A Transient Response

0.75VTT @ 2A Transient Response

20
0
-20
2
1
Swing Frequency : 1kHz

Time (250μs/Div)

DS9173D-07 April 2011

Sink

Output Voltage
Transient (mV)

VIN = 1.5V, VCNTL = 3.3V, VOUT = 0.75V

125

40

Time (250μs/Div)

40

0

-25

Temperature (°C)

40

0

-50

125

Output Current
(A)

Output Current
(A)

Output Voltage
Transient (mV)

-50

Output Voltage
Transient (mV)

VIN

2

2

Output Current
(A)

4

VIN = 1.8V, VCNTL = 3.3V
VIN = 2.5V, VCNTL = 3.3V
VIN = 2.5V, VCNTL = 5V
= 1.8V, VCNTL = 5V

VIN = 1.5V, VCNTL = 3.3V, VOUT = 0.75V

Source

40
20
0
-20
2
1
0

Swing Frequency : 1kHz

Time (250μs/Div)

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RT9173D

20
0

Output Current
(A)

-20
2
1
0

12
Output Short Circuit (A)

Sink

Output Voltage
Transient (mV)

VIN = 2.5V, VCNTL = 3.3V, VOUT = 1.25V

40

1.25VTT @ 2A Transient Response

Swing Frequency : 1kHz

20
0
-20
2
1
0

Swing Frequency : 1kHz

Output Short-Circuit Protection

Output Short-Circuit Protection

VIN = 1.5V, VCNTL = 3.3V

Sink

12

8
6
4
2
0

VIN = 1.5V, VCNTL = 3.3V

Source

10
8
6
4
2
0

Time (1ms/Div)

Time (1ms/Div)

Output Short-Circuit Protection

Output Short-Circuit Protection

VIN = 1.8V, VCNTL = 3.3V

10
8
6
4
2

12

VIN = 1.8V, VCNTL = 3.3V

Source

10
8
6
4
2
0

0

Time (1ms/Div)

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Sink

Output Short Circuit (A)

Output Short Circuit (A)

Source

Time (250μs/Div)

10

12

VIN = 2.5V, VCNTL = 3.3V, VOUT = 1.25V

40

Time (250μs/Div)

Output Short Circuit (A)

Output Current
(A)

Output Voltage
Transient (mV)

1.25VTT @ 2A Transient Response

Time (1ms/Div)

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RT9173D
Output Short-Circuit Protection

Output Short-Circuit Protection
VIN = 2.5V, VCNTL = 3.3V

10
8
6
4
2

12

Source

VIN = 2.5V, VCNTL = 3.3V

10
8
6
4
2
0

0

Time (1ms/Div)

DS9173D-07 April 2011

Sink

Output Short Circuit (A)

Output Short Circuit (A)

12

Time (1ms/Div)

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RT9173D
Application Information
Consideration while designs the resistance of voltage
divider
Make sure the sinking current capability of pull-down NMOS
if the lower resistance was chosen so that the voltage on
VREFEN is below 0.2V.
In addition, the capacitor and voltage divider form the lowpass filter. There are two reasons doing this design; one is
for output voltage soft-start while another is for noise
immunity.
How to reduce power dissipation on Notebook PC or
the dual channel DDR SDRAM application?
In notebook application, using RichTek's Patent
“ Distributed Bus Terminator Topology” with choosing
RichTek's product is encouraged.

General Regulator
The RT9173D could also serves as a general linear
regulator. The RT9173D accepts an external reference
voltage at REFEN pin and provides output voltage regulated
to this reference voltage as shown in Figure 3, where
VOUT = VEXT x R2/(R1+R2)
As other linear regulator, dropout voltage and thermal issue
should be specially considered. Figure 4 and 5 show the
RDS(ON) over temperature of RT9173D in PSOP-8 (Exposed
Pad) package. The minimum dropout voltage could be
obtained by the product of RDS(ON) and output current. For
thermal consideration, please refer to the relative sections.

RDS(ON) vs. Temperature
0.40
0.35

R0

BUS(0)

R1
BUS(1)
RT9173D

R2

VOUT

BUS(2)

R3

R DS(ON) (Ω)

Distributed Bus Terminating Topology
Terminator Resistor

0.30
0.25
0.20

BUS(3)

R4

0.15

BUS(4)

REFEN
R5

BUS(5)

0.10

R6

-50

BUS(6)
RT9173D

R7

VOUT

VCNTL = 3.3V

-25

0

BUS(7)

R8

50

75

100

125

100

125

Figure 4

BUS(8)

R9

25

Temperature (°C)

BUS(9)

RDS(ON) vs. Temperature
0.40
R(2N)

BUS(2N)

0.35

R(2N+1)

BUS(2N+1)

R DS(ON) (Ω)

Figure 2
VEXT

R1

R2

VCNTL

VIN

RT9173D
REFEN
VOUT
GND

VCNTL = 5V

VOUT

0.30
0.25
0.20
0.15
0.10
-50

-25

0

25

50

75

Temperature (°C)

Figure 3
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Figure 5
DS9173D-07 April 2011

RT9173D
Input Capacitor and Layout Consideration
Place the input bypass capacitor as close as possible to
the RT9173D. A low ESR capacitor larger than 470uF is
recommended for the input capacitor. Use short and wide
traces to minimize parasitic resistance and inductance.
Inappropriate layout may result in large parasitic inductance
and cause undesired oscillation between RT9173D and the
preceding power converter.
Thermal Consideration

Ambient
Molding Compound
Gold Line

Die Pad

Case (Exposed Pad)

Figure 6. SOP-8 (Exposed Pad) Package Sectional
Drawing

RT9173D regulators have internal thermal limiting circuitry
designed to protect the device during overload conditions.
For continued operation, do not exceed maximum operation
junction temperature 125°C. The power dissipation
definition in device is:
PD = (VIN - VOUT) x IOUT + VIN x IQ
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula:

Lead Frame

RGOLD-LINE

RLEAD FRAME

RPCB

path 1

Junction

RDIE

RDIE-ATTACH RDIE-PAD
path 2

RPCB

Case
(Exposed Pad)

Ambient

RMOLDING-COMPOUND
path 3

Figure 7. Thermal Resistance Equivalent Circuit

PD(MAX) = ( TJ(MAX) -TA ) /θJA
Where T J(MAX) is the maximum operation junction
temperature 125°C, TA is the ambient temperature and the
θJA is the junction to ambient thermal resistance. The
junction to ambient thermal resistance (θJA is layout
dependent) for SOP-8 package (Exposed Pad) is 75°C/W
on standard JEDEC 51-7 (4 layers, 2S2P) thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by following formula:
PD(MAX) = (125°C - 25°C) / 75°C/W = 1.33W
Figure 6 show the package sectional drawing of SOP-8
(Exposed Pad). Every package has several thermal
dissipation paths. As show in Figure 7, the thermal
resistance equivalent circuit of SOP-8 (Exposed Pad). The
path 2 is the main path due to these materials thermal
conductivity. We define the exposed pad is the case point
of the path 2.

The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package design and the PCB design.
However, the package design has been decided. If possible,
it's useful to increase thermal performance by the PCB
design. The thermal resistance can be decreased by
adding copper under the expose pad of SOP-8 package.
About PCB layout, the Figure 8 show the relation between
thermal resistance θJA and copper area on a standard
JEDEC 51-7 (4 layers, 2S2P) thermal test board at
TA = 25°C.We have to consider the copper couldn't stretch
infinitely and avoid the tin overflow. We use the “dog-bone”
copper patterns on the top layer as Figure 9.
As shown in Figure 10, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard SOP-8
(Exposed Pad) pad of 2 oz. copper (Figure 10.a), θJA is
75°C/W. Adding copper area of pad under the SOP-8
(Exposed Pad) (Figure 10.b) reduces the θJA to 64°C/W.
Even further, increasing the copper area of pad to 70mm2
(Figure 10.e) reduces the θJA to 49°C/W.

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RT9173D
θJA vs. Copper Area
100
90

θ JA (°C/W)

80
70
60
50

Figure 10 (b). Copper Area = 10mm2, θJA = 64°C/W

40
30
0

10

20

30

40

50

60

70

2

Copper Area (mm )

Figure 8

Exposed Pad

Figure 10 (c). Copper Area = 30mm2, θJA = 54°C/W

Figure 9.Dog-Bone layout

Figure 10 (d). Copper Area = 50mm2, θJA = 51°C/W

Figure 10 (a). Minimum Footprint, θJA = 75°C/W

Figure 10 (e). Copper Area = 70mm2, θJA = 49°C/W

W≦2.28mm

Figure 10. Thermal Resistance vs. Different Cooper Area
Layout Design

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RT9173D
Outline Information
H

A

M
EXPOSED THERMAL PAD
(Bottom of Package)

Y
J

X

B

F

C
I
D

Dimensions In Millimeters

Symbol

Dimensions In Inches

Min

Max

Min

Max

A

4.801

5.004

0.189

0.197

B

3.810

4.000

0.150

0.157

C

1.346

1.753

0.053

0.069

D

0.330

0.510

0.013

0.020

F

1.194

1.346

0.047

0.053

H

0.170

0.254

0.007

0.010

I

0.000

0.152

0.000

0.006

J

5.791

6.200

0.228

0.244

M

0.406

1.270

0.016

0.050

X

2.000

2.300

0.079

0.091

Y

2.000

2.300

0.079

0.091

X

2.100

2.500

0.083

0.098

Y

3.000

3.500

0.118

0.138

Option 1
Option 2

8-Lead SOP (Exposed Pad) Plastic Package

Richtek Technology Corporation

Richtek Technology Corporation

Headquarter

Taipei Office (Marketing)

5F, No. 20, Taiyuen Street, Chupei City

5F, No. 95, Minchiuan Road, Hsintien City

Hsinchu, Taiwan, R.O.C.

Taipei County, Taiwan, R.O.C.

Tel: (8863)5526789 Fax: (8863)5526611

Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design,
specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed
by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

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Keywords                        : RT9173D, -, Datasheet., www.s-manuals.com.
Warning                         : [Minor] Ignored duplicate Info dictionary

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