Realtek RTL8111C GR Datasheet 1.1 R1.1
User Manual: Datasheets RTL8111, RTL8111B-GR, RTL8111C-GR, RTL8111D-GR, RTL8111D-VB-GR, RTL8111DL-GR, RTL8111DL-VB-GR, RTL8111E-VL-CG.
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INTEGRATED GIGABIT ETHERNET CONTROLLER
FOR PCI EXPRESS™ APPLICATIONS
DATASHEET
Rev. 1.1
09 February 2007
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
RTL8111C-GR
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express ii Track ID: JATR-1076-21 Rev. 1.1
COPYRIGHT
©2007 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date Summary
1.0 2006/12/12 First release.
1.1 2007/02/09
Changed Figure 1, Pin Assignments, page 3.
Changed Table 8, Power & Ground, page 7.
Removed SMBus table.
Added Table 9, GPIO Pins, page 7.
Changed Table 10, NC (Not Connected) Pins, page 4.
Renamed VDD12 to DVDD12.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express iii Track ID: JATR-1076-21 Rev. 1.1
Table of Contents
1. General Description .................................................................................................... 1
2. Features ........................................................................................................................2
3. System Applications .................................................................................................... 2
4. Pin Assignments........................................................................................................... 3
4.1. PACKAGE IDENTIFICATION ...............................................................................................................3
5. Pin Descriptions........................................................................................................... 4
5.1. POWER MANAGEMENT/ISOLATION...................................................................................................4
5.2. PCI EXPRESS INTERFACE .................................................................................................................4
5.3. EEPROM.........................................................................................................................................5
5.4. TRANSCEIVER INTERFACE ................................................................................................................5
5.5. CLOCK..............................................................................................................................................6
5.6. REGULATOR & REFERENCE ..............................................................................................................6
5.7. LEDS...............................................................................................................................................6
5.8. POWER & GROUND...........................................................................................................................7
5.9. GPIO................................................................................................................................................7
5.10. NC (NOT CONNECTED) PINS ............................................................................................................7
6. Functional Description................................................................................................ 8
6.1. PCI EXPRESS BUS INTERFACE ..........................................................................................................8
6.1.1. PCI Express Transmitter.........................................................................................................................................8
6.1.2. PCI Express Receiver .............................................................................................................................................8
6.2. LED FUNCTIONS ..............................................................................................................................8
6.2.1. Link Monitor...........................................................................................................................................................8
6.2.2. Rx LED ...................................................................................................................................................................9
6.2.3. Tx LED ...................................................................................................................................................................9
6.2.4. Tx/Rx LED ............................................................................................................................................................10
6.2.5. LINK/ACT LED .................................................................................................................................................... 11
6.3. PHY TRANSCEIVER........................................................................................................................12
6.3.1. PHY Transmitter ...................................................................................................................................................12
6.3.2. PHY Receiver........................................................................................................................................................12
6.4. NEXT PAGE ....................................................................................................................................13
6.5. EEPROM INTERFACE ....................................................................................................................13
6.6. POWER MANAGEMENT ...................................................................................................................14
6.7. VITAL PRODUCT DATA (VPD) .......................................................................................................16
6.8. MESSAGE SIGNALED INTERRUPT (MSI) .........................................................................................17
6.8.1. MSI Capability Structure in PCI Configuration Space.........................................................................................17
6.8.2. Message Control...................................................................................................................................................18
6.8.3. Message Address ..................................................................................................................................................18
6.8.4. Message Upper Address .......................................................................................................................................19
6.8.5. Message Data .......................................................................................................................................................19
6.9. MSI-X............................................................................................................................................20
6.9.1. MSI-X Capability Structure in PCI Configuration Space.....................................................................................20
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express iv Track ID: JATR-1076-21 Rev. 1.1
6.9.2. Message Control...................................................................................................................................................21
6.9.3. Table Offset/BIR ...................................................................................................................................................21
6.9.4. PBA Offset/PBA BIR.............................................................................................................................................22
6.9.5. Message Address for MSI-X Table Entries ...........................................................................................................22
6.9.6. Message Upper Address for MSI-X Table Entries ................................................................................................23
6.9.7. Message Data for MSI-X Table Entries ................................................................................................................23
6.9.8. Vector Control for MSI-X Table Entries ...............................................................................................................23
6.9.9. Pending Bits for MSI-X PBA Entries....................................................................................................................23
6.10. RECEIVE-SIDE SCALING (RSS).......................................................................................................24
6.10.1. Receive-Side Scaling (RSS) Initialization.............................................................................................................24
6.10.2. RSS Operation ......................................................................................................................................................25
7. Characteristics ........................................................................................................... 26
7.1. ABSOLUTE MAXIMUM RATINGS .....................................................................................................26
7.2. RECOMMENDED OPERATING CONDITIONS......................................................................................26
7.3. CRYSTAL REQUIREMENTS ..............................................................................................................26
7.4. THERMAL CHARACTERISTICS .........................................................................................................27
7.5. DC CHARACTERISTICS ...................................................................................................................27
7.6. AC CHARACTERISTICS ...................................................................................................................28
7.6.1. Serial EEPROM Interface Timing ........................................................................................................................28
7.7. PCI EXPRESS BUS PARAMETERS ....................................................................................................30
7.7.1. Differential Transmitter Parameters.....................................................................................................................30
7.7.2. Differential Receiver Parameters .........................................................................................................................31
7.7.3. REFCLK Parameters............................................................................................................................................31
7.7.4. Auxiliary Signal Timing Parameters ....................................................................................................................35
8. Mechanical Dimensions ............................................................................................ 36
9. Ordering Information ............................................................................................... 36
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express v Track ID: JATR-1076-21 Rev. 1.1
List of Tables
Table 1. Power Management/Isolation .....................................................................................................4
Table 2. PCI Express Interface .................................................................................................................4
Table 3. EEPROM ....................................................................................................................................5
Table 4. Transceiver Interface ..................................................................................................................5
Table 5. Clock...........................................................................................................................................6
Table 6. Regulator & Reference ...............................................................................................................6
Table 7. LEDs...........................................................................................................................................6
Table 8. Power & Ground.........................................................................................................................7
Table 9. GPIO Pins ...................................................................................................................................7
Table 10. NC (Not Connected) Pins ...........................................................................................................7
Table 11. EEPROM Interface...................................................................................................................13
Table 12. Message Control .......................................................................................................................18
Table 13. Message Address ......................................................................................................................18
Table 14. Message Upper Address ...........................................................................................................19
Table 15. Message Data............................................................................................................................19
Table 16. Message Control .......................................................................................................................21
Table 17. Table Offset/BIR ......................................................................................................................21
Table 18. PBA Offset/PBA BIR...............................................................................................................22
Table 19. Message Address for MSI-X Table Entries..............................................................................22
Table 20. Message Upper Address for MSI-X Table Entries...................................................................23
Table 21. Message Data............................................................................................................................23
Table 22. Vector Control for MSI-X Table Entries..................................................................................23
Table 23. Pending Bits for MSI-X PBA Entries.......................................................................................23
Table 24. Absolute Maximum Ratings.....................................................................................................26
Table 25. Recommended Operating Conditions.......................................................................................26
Table 26. Crystal Requirements ...............................................................................................................26
Table 27. Thermal Characteristics............................................................................................................27
Table 28. DC Characteristics....................................................................................................................27
Table 29. EEPROM Access Timing Parameters ......................................................................................29
Table 30. Differential Transmitter Parameters .........................................................................................30
Table 31. Differential Receiver Parameters..............................................................................................31
Table 32. REFCLK Parameters ................................................................................................................31
Table 33. Auxiliary Signal Timing Parameters ........................................................................................35
Table 34. Ordering Information................................................................................................................36
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express vi Track ID: JATR-1076-21 Rev. 1.1
List of Figures
Figure 1. Pin Assignments........................................................................................................................3
Figure 2. Rx LED .....................................................................................................................................9
Figure 3. Tx LED......................................................................................................................................9
Figure 4. Tx/Rx LED..............................................................................................................................10
Figure 5. LINK/ACT LED .....................................................................................................................11
Figure 6. Message Capability Structure..................................................................................................17
Figure 7. MSI-X Capability Structure ....................................................................................................20
Figure 8. MSI-X Table Structure............................................................................................................20
Figure 9. MSI-X PBA Structure .............................................................................................................20
Figure 10. Serial EEPROM Interface Timing ..........................................................................................28
Figure 11. Single-Ended Measurement Points for Absolute Cross Point and Swing...............................33
Figure 12. Single-Ended Measurement Points for Delta Cross Point ......................................................33
Figure 13. Single-Ended Measurement Points for Rise and Fall Time Matching....................................33
Figure 14. Differential Measurement Points for Duty Cycle and Period .................................................34
Figure 15. Differential Measurement Points for Rise and Fall Time .......................................................34
Figure 16. Differential Measurement Points for Ringback ......................................................................34
Figure 17. Reference Clock System Measurement Point and Loading....................................................35
Figure 18. Auxiliary Signal Timing..........................................................................................................35
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 1 Track ID: JATR-1076-21 Rev. 1.1
1. General Description
The Realtek RTL8111C-GR Gigabit Ethernet controller combines a triple-speed IEEE 802.3 compliant
Media Access Controller (MAC) with a triple-speed Ethernet transceiver, PCI Express bus controller, and
embedded memory. With state-of-the-art DSP technology and mixed-mode signal technology, the
RTL8111C-GR offers high-speed transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only)
cable. Functions such as Crossover Detection & Auto-Correction, polarity correction, adaptive
equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are
implemented to provide robust transmission and reception capability at high speeds.
The RTL8111C-GR is compliant with the IEEE 802.3u specification for 10/100Mbps Ethernet and the
IEEE 802.3ab specification for 1000Mbps Ethernet. It also supports an auxiliary power auto-detect
function, and will auto-configure related bits of the PCI power management registers in PCI configuration
space.
Advanced Configuration Power management Interface (ACPI)—power management for modern
operating systems that are capable of Operating System-directed Power Management (OSPM)—is
supported to achieve the most efficient power management possible. PCI MSI (Message Signaled
Interrupt) and MSI-X are also supported.
In addition to the ACPI feature, remote wake-up (including AMD Magic Packet™ and Microsoft®
Wake-up frame) is supported in both ACPI and APM (Advanced Power Management) environments. To
support WOL from a deep power down state (e.g., D3cold, i.e. main power is off and only auxiliary
exists), the auxiliary power source must be able to provide the needed power for the RTL8111C-GR.
The RTL8111C-GR is fully compliant with Microsoft® NDIS5, NDIS6(IPv4, IPv6, TCP, UDP)
Checksum and Segmentation Task-offload(Large send and Giant send) features, and supports IEEE 802
IP Layer 2 priority encoding and IEEE 802.1Q Virtual bridged Local Area Network (VLAN). The above
features contribute to lowering CPU utilization, especially benefiting performance when in operation on a
network server.
The RTL8111C-GR supports Receive Side Scaling (RSS) to hash incoming TCP connections and
load-balance received data processing across multiple CPUs. RSS improves the number of transactions
per second and number of connections per second, for increased network throughput.
The device also features inter-connect PCI Express technology. PCI Express is a high-bandwidth, low pin
count, serial, interconnect technology that offers significant improvements in performance over
conventional PCI and also maintains software compatibility with existing PCI infrastructure. The device
embeds an adaptive equalizer in the PCIe PHY for ease of system integration and excellent link quality.
The equalizer enables the length of the PCB traces to reach 40 inches.
The RTL8111C-GR is suitable for multiple market segments and emerging applications, such as desktop,
mobile, workstation, server, communications platforms, and embedded applications.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 2 Track ID: JATR-1076-21 Rev. 1.1
2. Features
Integrated 10/100/1000 transceiver
Auto-Negotiation with Next Page
capability
Supports PCI Express™ 1.1
Supports pair swap/polarity/skew
correction
Crossover Detection & Auto-Correction
Wake-on-LAN and remote wake-up
support
Microsoft® NDIS5, NDIS6 Checksum
Offload (IPv4, IPv6, TCP, UDP) and
Segmentation Task-offload (Large send
and Giant send) support
Supports Full Duplex flow control
(IEEE 802.3x)
Fully compliant with IEEE 802.3,
IEEE 802.3u, IEEE 802.3ab
Supports IEEE 802.1P Layer 2 Priority
Encoding
Supports IEEE 802.1Q VLAN tagging
Serial EEPROM
Transmit/Receive on-chip buffer
support
Supports power down/link down power
saving
Supports PCI MSI (Message Signaled
Interrupt) and MSI-X
Supports Receive-Side Scaling (RSS)
64-pin QFN package (Green package)
Embeds an adaptive equalizer in PCI
express PHY (PCB traces to reach 40
inches)
3. System Applications
PCI Express™ Gigabit Ethernet on Motherboard, Notebook, or Embedded system
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 3 Track ID: JATR-1076-21 Rev. 1.1
4. Pin Assignments
123456789
10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
MDIP0
MDIN0
MDIP1
MDIN1
SROUT12
MDIP2
MDIN2
MDIP3
MDIN3 ISOLATEB
EESK
EEDI/AUX
EEDO
EECS
NC
VDD33
VDD33
VDD33
VDD33
CLKREQB
DVDD12
DVDD12
DVDD12
DVDD12
AVDD12
DVDD12
FB12
AVDD12
AVDD12
AVDD12
EVDD12
EVDD12
ENSR
AVDD33
AVDD33
EGND
EGND
NC
NC
NC
NC
OGPIO
IGPIO
LLLLLLL TXXXV
RTL8111C
LED3
LED2
LED1
LED0
CKTAL2
CKTAL1
RSET
VDDSR
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DVDD12
HSON
HSOP
REFCLK_N
REFCLK_P
HSIN
HSIP
PERSTB
LANWAKEB
65 GND (Exposed Pad)
NC
NC
NC
NC
Figure 1. Pin Assignments
4.1.
Package Identification
‘Green’ package is indicated by a ‘G’ in the location marked ‘T’ in Figure 1.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 4 Track ID: JATR-1076-21 Rev. 1.1
5. Pin Descriptions
The signal type codes below are used in the following tables:
I: Input S/T/S: Sustained Tri-State
O: Output O/D: Open Drain
T/S: Tri-State bi-directional input/output pin
5.1.
Power Management/Isolation
Table 1. Power Management/Isolation
Symbol Type Pin No Description
LANWAKEB O/D 19 Power Management Event: Open drain, active low.
Used to reactivate the PCI Express slot’s main power rails and reference clocks.
ISOLATEB I 36
Isolate Pin: Active low.
Used to isolate the RTL8111C-GR from the PCI Express bus. The RTL8111C-GR
will not drive its PCI Express outputs (excluding LANWAKEB) and will not
sample its PCI Express input as long as the Isolate pin is asserted.
5.2.
PCI Express Interface
Table 2. PCI Express Interface
Symbol Type Pin No Description
REFCLK_P I 26
REFCLK_N I 27
PCI Express Differential Reference Clock Source: 100MHz ± 300ppm.
HSOP O 29
HSON O 30
PCI Express Transmit Differential Pair.
HSIP I 23
HSIN I 24
PCI Express Receive Differential Pair.
PERSTB I 20
PCI Express Reset Signal: Active low.
When the PERSTB is asserted at power-on state, the RTL8111C-GR returns
to a pre-defined reset state and is ready for initialization and configuration
after the de-assertion of the PERSTB.
CLKREQB O/D 33
Reference clock request signal. This signal is used by the RTL8111C-GR to
request starting of the PCI Express reference clock.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 5 Track ID: JATR-1076-21 Rev. 1.1
5.3.
EEPROM
Table 3. EEPROM
Symbol Type Pin No Description
EESK O 48 Serial data clock.
EEDI/AUX O/I 47
EEDI: Output to serial data input pin of EEPROM.
AUX: Input pin to detect if Aux. Power exists or not on initial power-on.
This pin should be connected to EEPROM. To support wakeup from ACPI
D3cold or APM power-down, this pin must be pulled high to Aux. Power
via a resistor. If this pin is not pulled high to Aux. Power, the
RTL8111C-GR assumes that no Aux. Power exists.
EEDO I 45 Input from serial data output pin of EEPROM.
EECS O 44 EECS: EEPROM chip select.
5.4.
Transceiver Interface
Table 4. Transceiver Interface
Symbol Type Pin No Description
MDIP0 I/O 3
MDIN0 I/O
4
In MDI mode, this is the first pair in 1000Base-T, i.e. the BI_DA+/- pair, and is
the transmit pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the receive
pair in 10Base-T and 100Base-TX.
MDIP1 I/O 6
MDIN1 I/O
7
In MDI mode, this is the second pair in 1000Base-T, i.e. the BI_DB+/- pair, and
is the transmit pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the transmit
pair in 10Base-T and 100Base-TX.
MDIP2 I/O 9
MDIN2 I/O 10
In MDI mode, this is the third pair in 1000Base-T, i.e. the BI_DC+/- pair.
In MDI crossover mode, this pair acts as the BI_DD+/- pair.
MDIP3 I/O 12
MDIN3 I/O 13
In MDI mode, this is the fourth pair in 1000Base-T, i.e. the BI_DD+/- pair.
In MDI crossover mode, this pair acts as the BI_DC+/- pair.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 6 Track ID: JATR-1076-21 Rev. 1.1
5.5.
Clock
Table 5. Clock
Symbol Type Pin No Description
CKTAL1 I 60 Input of 25MHz clock reference.
CKTAL2 O 61 Output of 25MHz clock reference.
5.6.
Regulator & Reference
Table 6. Regulator & Reference
Symbol Type Pin No Description
SROUT12 O 1 Switching regulator 1.2V output. Connect to 5uH inductor.
FB12 I 5 Feedback pin for switching regulator.
ENSR I 62
3.3V: Enable switching regulator.
0 V: disable switching regulator.
VDDSR Power 63 Digital 3.3V power supply for switching regulator.
RSET I 64 Reference. External resistor reference.
5.7.
LEDs
Table 7. LEDs
Symbol Type Pin No Description
LED0 O 57
LED1 O 56
LED2 O 55
LED3 O 54
LEDS1-0 00 01 10 11
LED0 Tx/Rx Tx/Rx Tx LINK10/ACT
LED1 LINK100
LINK10/100/
1000 LINK LINK100/
ACT
LED2 LINK10 LINK10/100 Rx FULL
LED3 LINK1000 LINK1000 FULL
LINK1000/
ACT
Note 1: During power down mode, the LED signals are logic high.
Note 2: LEDS1-0’s initial value comes from the 93C46. If there is no 93C46, the
default value of the (LEDS1, LEDS0) = (1, 1).
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 7 Track ID: JATR-1076-21 Rev. 1.1
5.8.
Power & Ground
Table 8. Power & Ground
Symbol Type Pin No Description
VDD33 Power 16, 37, 46, 53 Digital 3.3V power supply.
DVDD12 Power 21, 32, 38, 43, 49, 52 Digital 1.2V power supply.
AVDD12 Power 8, 11, 14, 58 Analog 1.2V power supply.
EVDD12 Power 22, 28 Analog 1.2V power supply.
AVDD33 Power 2, 59 Analog 3.3V power supply.
EGND Power 25, 31 Analog Ground.
GND Power 65 Ground (Exposed Pad).
Note: Refer to the most updated schematic circuit for correct configuration.
5.9.
GPIO
Table 9. GPIO Pins
Symbol Type Pin No Description
IGPIO I 50 Input GPIO Pin.
OGPIO O 51
Output GPIO Pin. This pin reflects the link up or link down state.
High: Link up
Low: Link down.
5.10.
NC (Not Connected) Pins
Table 10. NC (Not Connected) Pins
Symbol Type Pin No Description
NC -
15, 17, 18, 34, 35, 39,
40, 41, 42 Not Connected.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 8 Track ID: JATR-1076-21 Rev. 1.1
6. Functional Description
6.1.
PCI Express Bus Interface
The RTL8111C-GR is compliant with PCI Express Base Specification Revision 1.1, and runs at a 2.5GHz
signaling rate with X1 link width, i.e., one transmit and one receive differential pair. The RTL8111C-GR
supports four types of PCI Express messages: interrupt messages, error messages, power management
messages, and hot-plug messages. To ease PCB layout constraints, PCI Express lane polarity reversal and
link reversal are also supported.
6.1.1. PCI Express Transmitter
The RTL8111C-GR’s PCI Express block receives digital data from the Ethernet interface and performs
data scrambling with Linear Feedback Shift Register (LFSR) and 8B/10B coding technology into 10-bit
code groups. Data scrambling is used to reduce the possibility of electrical resonance on the link, and
8B/10B coding technology is used to benefit embedded clocking, error detection, and DC balance by
adding an overhead to the system through the addition of 2 extra bits. The data code groups are passed
through its serializer for packet framing. The generated 2.5Gbps serial data is transmitted onto the PCB
trace to its upstream device via a differential driver.
6.1.2. PCI Express Receiver
The RTL8111C-GR’s PCI Express block receives 2.5Gbps serial data from its upstream device to
generate parallel data. The receiver’s PLL circuits are re-synchronized to maintain bit and symbol lock.
Through 8B/10B decoding technology and data de-scrambling, the original digital data is recovered and
passed to the RTL8111C-GR’s internal Ethernet MAC to be transmitted onto the Ethernet media.
6.2.
LED Functions
The RTL8111C-GR supports four LED signals in four different configurable operation modes. The
following sections describe the various LED actions.
6.2.1. Link Monitor
The Link Monitor senses link integrity, such as LINK10, LINK100, LINK1000, LINK10/100/1000,
LINK10/ACT, LINK100/ACT, or LINK1000/ACT. Whenever link status is established, the specific link
LED pin is driven low. Once a cable is disconnected, the link LED pin is driven high, indicating that no
network connection exists.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 9 Track ID: JATR-1076-21 Rev. 1.1
6.2.2. Rx LED
In 10/100/1000Mbps mode, blinking of the Rx LED indicates that receive activity is occurring.
Power On
Receiving
Packet?
LED = High
LED = High for 40 ms
LED = Low for 40 ms
No
Yes
Figure 2. Rx LED
6.2.3. Tx LED
In 10/100/1000Mbps mode, blinking of the Tx LED indicates that transmit activity is occurring.
Power On
Transmitting
Packet?
LED = High
LED = High for 40 ms
LED = Low for 40 ms
No
Yes
Figure 3. Tx LED
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 10 Track ID: JATR-1076-21 Rev. 1.1
6.2.4. Tx/Rx LED
In 10/100/1000Mbps mode, blinking of the Tx/Rx LED indicates that both transmit and receive activity is
occurring.
Power On
Tx/Rx Packet?
LED = High
LED = High for 40 ms
LED = Low for 40 ms
No
Yes
Figure 4. Tx/Rx LED
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 11 Track ID: JATR-1076-21 Rev. 1.1
6.2.5. LINK/ACT LED
In 10/100/1000Mbps mode, blinking of the LINK/ACT LED indicates that the RTL8111C-GR is linked
and operating properly. When this LED is high for extended periods, it indicates that a link problem
exists.
Power On
Link?
LED = High
LED = Low
LED = Low for 40 ms
No
Yes
Tx/Rx
Packet?
Yes
No
LED = High for 40 ms
Figure 5. LINK/ACT LED
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 12 Track ID: JATR-1076-21 Rev. 1.1
6.3.
PHY Transceiver
6.3.1. PHY Transmitter
Based on state-of-the-art DSP technology and mixed-mode signal processing technology, the
RTL8111C-GR operates at 10/100/1000Mbps over standard CAT.5 UTP cable (100/1000Mbps), and
CAT.3 UTP cable (10Mbps).
GMII (1000Mbps) Mode
The RTL8111C-GR’s PCS layer receives data bytes from the MAC through the GMII interface and
performs the generation of continuous code-groups through 4D-PAM5 coding technology. These code
groups are passed through a waveform-shaping filter to minimize EMI effect, and are transmitted onto the
4-pair CAT5 cable at 125MBaud/s through a D/A converter.
MII (100Mbps) Mode
The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25MHz (TXC), are converted into
5B symbol code through 4B/5B coding technology, then through scrambling and serializing, are
converted to 125Mhz NRZ and NRZI signals. After that, the NRZI signals are passed to the MLT3
encoder, then to the D/A converter and transmitted onto the media.
MII (10Mbps) Mode
The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5MHz (TXC), are serialized into
10Mbps serial data. The 10Mbps serial data is converted into a Manchester-encoded data stream and is
transmitted onto the media by the D/A converter.
6.3.2. PHY Receiver
GMII (1000Mbps) Mode
Input signals from the media pass through the sophisticated on-chip hybrid circuit to separate the
transmitted signal from the input signal for effective reduction of near-end echo. Afterwards, the received
signal is processed with state-of-the-art technology, e.g., adaptive equalization, BLW (Baseline Wander)
correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5
decoding. Then, the 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of
125MHz. The Rx MAC retrieves the packet data from the receive MII/GMII interface and sends it to the
Rx Buffer Manager.
MII (100Mbps) Mode
The MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing
recovery, MLT3 and NRZI decoder, descrambler, 4B/5B decoder, and is then presented to the MII
interface in 4-bit-wide nibbles at a clock speed of 25MHz.
MII (10Mbps) Mode
The received differential signal is converted into a Manchester-encoded stream first. Next, the stream is
processed with a Manchester decoder and is de-serialized into 4-bit-wide nibbles. The 4-bit nibbles are
presented to the MII interface at a clock speed of 2.5MHz.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 13 Track ID: JATR-1076-21 Rev. 1.1
6.4.
Next Page
If 1000Base-T mode is advertised, three additional Next Pages are automatically exchanged between the
two link partners. Users can set PHY Reg4.15 to 1 to manually exchange extra Next Pages via Reg7 and
Reg8 as defined in IEEE 802.3ab.
6.5.
EEPROM Interface
The RTL8111C-GR requires the attachment of an external EEPROM. The 93C46/93C56 is a
1K-bit/2K-bit EEPROM. The EEPROM interface permits the RTL8111C-GR to read from, and write
data to, an external serial EEPROM device.
Values in the external EEPROM allow default fields in PCI configuration space and I/O space to be
overridden following a power-on or software EEPROM auto-load command. The RTL8111C-GR will
auto-load values from the EEPROM. If the EEPROM is not present, the RTL8111C-GR initialization
uses default values for the appropriate Configuration and Operational Registers. Software can read and
write to the EEPROM using bit-bang accesses via the 9346CR Register, or using PCI VPD (Vital Product
Data). The interface consists of EESK, EECS, EEDO, and EEDI.
The correct EEPROM (i.e. 93C46/93C56) must be used in order to ensure proper LAN function.
Table 11. EEPROM Interface
EEPROM Description
EECS 93C46/93C56 chip select.
EESK EEPROM serial data clock.
EEDI/Aux
Input data bus/Input pin to detect whether Aux. Power exists on initial power-on.
This pin should be connected to EEPROM. To support wakeup from ACPI D3cold or
APM power-down, this pin must be pulled high to Aux. Power via a resistor. If this pin is
not pulled high to Aux. Power, the RTL8111C-GR assumes that no Aux. Power exists.
EEDO Output data bus.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 14 Track ID: JATR-1076-21 Rev. 1.1
6.6.
Power Management
The RTL8111C-GR is compliant with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), PCI
Express Active State Power Management (ASPM), and Network Device Class Power Management
Reference Specification (V1.0a), such as to support an Operating System-directed Power Management
(OSPM) environment.
The RTL8111C-GR can monitor the network for a Wakeup Frame, a Magic Packet, and notify the system
via a PCI Express Power Management Event (PME) Message, Beacon, or LANWAKEB pin when such a
packet or event occurs. Then the system can be restored to a normal state to process incoming jobs.
When the RTL8111C-GR is in power down mode (D1 ~ D3):
• The Rx state machine is stopped. The RTL8111C-GR monitors the network for wakeup events such as
a Magic Packet and Wakeup Frame in order to wake up the system. When in power down mode, the
RTL8111C-GR will not reflect the status of any incoming packets in the ISR register and will not
receive any packets into the Rx on-chip buffer.
• The on-chip buffer status and packets that have already been received into the Rx on-chip buffer
before entering power down mode are held by the RTL8111C-GR.
• Transmission is stopped. PCI Express transactions are stopped. The Tx on-chip buffer is held.
• After being restored to D0 state, the RTL8111C-GR transmits data that was not moved into the Tx
on-chip buffer during power down mode. Packets that were not transmitted completely last time are
re-transmitted.
The D3cold_support_PME bit (bit15, PMC register) and the Aux_I_b2:0 bits (bit8:6, PMC register) in
PCI configuration space depend on the existence of Aux power. If aux. power is absent, the above 4 bits
are all 0 in binary.
Example:
If EEPROM D3c_support_PME = 1:
• If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC
(if EEPROM PMC = C3 F7, then PCI PMC = C3 F7)
• If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the
above 4 bits are all 0’s (if EEPROM PMC = C3 F7, then PCI PMC = 03 76)
In the above case, if wakeup support is desired when main power is off, it is suggested that the EEPROM
PMC be set to C3 F7 (Realtek EEPROM default value).
If EEPROM D3c_support_PME = 0:
• If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC
(if EEPROM PMC = C3 77, then PCI PMC = C3 77)
• If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the
above 4 bits are all 0’s (if EEPROM PMC = C3 77, then PCI PMC = 03 76)
In the above case, if wakeup support is not desired when main power is off, it is suggested that the
EEPROM PMC be set to 03 76.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 15 Track ID: JATR-1076-21 Rev. 1.1
Magic Packet Wakeup occurs only when the following conditions are met:
• The destination address of the received Magic Packet is acceptable to the RTL8111C-GR, e.g., a
broadcast, multicast, or unicast packet addressed to the current RTL8111C-GR adapter.
• The received Magic Packet does not contain a CRC error.
• The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the
corresponding wake-up method (message, beacon, or LANWAKEB) can be asserted in the current
power state.
• The Magic Packet pattern matches, i.e. 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in
any part of a valid Ethernet packet.
A Wakeup Frame event occurs only when the following conditions are met:
• The destination address of the received Wakeup Frame is acceptable to the RTL8111C-GR, e.g., a
broadcast, multicast, or unicast address to the current RTL8111C-GR adapter.
• The received Wakeup Frame does not contain a CRC error.
• The PMEn bit (CONFIG1#0) is set to 1.
• The 16-bit CRCA of the received Wakeup Frame matches the 16-bit CRC of the sample Wakeup
Frame pattern given by the local machine’s OS. Or, the RTL8111C-GR is configured to allow direct
packet wakeup, e.g., a broadcast, multicast, or unicast network packet.
Note: 16-bit CRC: The RTL8111C-GR supports eight long wakeup frames (covering 128 mask bytes from
offset 0 to 127 of any incoming network packet).
The corresponding wake-up method (message, beacon, or LANWAKEB) is asserted only when the
following conditions are met:
• The PMEn bit (bit0, CONFIG1) is set to 1.
• The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
• The RTL8111C-GR may assert the corresponding wake-up method (message, beacon, or
LANWAKEB) in the current power state or in isolation state, depending on the PME_Support
(bit15-11) setting of the PMC register in PCI Configuration Space.
• A Magic Packet, LinkUp, or Wakeup Frame has been received.
• Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears
this bit and causes the RTL8111C-GR to stop asserting the corresponding wake-up method (message,
beacon, or LANWAKEB) (if enabled).
When the RTL8111C-GR is in power down mode, e.g., D1-D3, the IO and MEM accesses to the
RTL8111C-GR are disabled. After a PERSTB assertion, the device’s power state is restored to D0
automatically if the original power state was D3cold. There is almost no hardware delay at the device’s
power state transition. When in ACPI mode, the device does not support PME (Power Management
Enable) from D0 (this is the Realtek default setting of the PMC register auto-loaded from EEPROM). The
setting may be changed from the EEPROM, if required.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 16 Track ID: JATR-1076-21 Rev. 1.1
6.7.
Vital Product Data (VPD)
Bit 31 of the Vital Product Data (VPD) capability structure in the RTL8111C-GR’s PCI Configuration
Space is used to issue VPD read/write commands and is also a flag used to indicate whether the transfer
of data between the VPD data register and the 93C46/93C56/93C66 has completed or not.
Write VPD register: (write data to the 93C46/93C56/93C66)
Set the flag bit to 1 at the same time the VPD address is written to write VPD data to EEPROM. When
the flag bit is reset to 0 by the RTL8111C-GR, the VPD data (4 bytes per VPD access) has been
transferred from the VPD data register to EEPROM.
Read VPD register: (read data from the 93C46/93C56/93C66)
Reset the flag bit to 0 at the same time the VPD address is written to retrieve VPD data from EEPROM.
When the flag bit is set to 1 by the RTL8111C-GR, the VPD data (4 bytes per VPD access) has been
transferred from EEPROM to the VPD data register.
Note1: Refer to the PCI 2.3 Specifications for further information.
Note2: The VPD address must be a DWORD-aligned address as defined in the PCI 2.3 Specifications.
VPD data is always consecutive 4-byte data starting from the VPD address specified.
Note3: Realtek reserves offset 60h to 7Fh in EEPROM mainly for VPD data to be stored.
Note4: The VPD function of the RTL8111C-GR is designed to be able to access the full range of the
93C46/93C56/93C66 EEPROM.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 17 Track ID: JATR-1076-21 Rev. 1.1
6.8.
Message Signaled Interrupt (MSI)
6.8.1. MSI Capability Structure in PCI Configuration Space
Figure 6. Message Capability Structure
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 18 Track ID: JATR-1076-21 Rev. 1.1
6.8.2. Message Control
Table 12. Message Control
Bits RW Field Description
15:8 RO Reserved Reserved. Always return 0
7 RO 64-bit address capable 1: The RTL8111C is capable of generating a 64-bit
message address.
0: The RTL8111C is NOT capable of generating a 64-bit
message address.
This bit is read only and the RTL8111C is set to 1.
System software (e.g., BIOS, OS) indicates to the RTL8111C-GR
the number of allocated messages/vectors (equal to or less than
the number of requested messages/vectors).
This field after PCI reset is ‘000’.
Encoding Number of Messages/Vectors
000 1
001 2
010 4
011 8
100 16
101 32
110 Reserved
6:4 RW Multiple Message Enable
111 Reserved
Indication to system software (e.g., BIOS, OS) of the number of
RTL8111C-GR requested vectors.
The RTL8111C-GR supports only one vector messages/vectors.
Encoding Number of Messages/Vectors
000 1
3:1 RO Multiple Message Capable
Others Reserved
0 RW MSI Enable 1: Enable MSI (Also the INTx pin is disabled automatically, MSI
and INTx are mutually exclusive), this bit is set by system
software.
0: Disable MSI (Default value after power-on or PCI reset)
6.8.3. Message Address
Table 13. Message Address
Bits RW Field Description
31:02 RW Message Address System-specified message/vector address.
Low DWORD aligned address for MSI memory write transaction.
01:00 RO Reserved Always return ‘00’.
This bit is read only.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 19 Track ID: JATR-1076-21 Rev. 1.1
6.8.4. Message Upper Address
Table 14. Message Upper Address
Bits RW Field Description
31:00 RW Message Upper Address System-specified message/vector upper address.
Upper 32 bits of a 64-bit message/vector address.
This register is effective only when the DAC function is enabled,
i.e., 64-bit addressing is enabled; bit7 in Message Control register
is set.
If the contents of this register are 0, the RTL8111C-GR only
performs 32-bit addressing for the memory write of the
messages/vectors.
This bit is read/write.
6.8.5. Message Data
Table 15. Message Data
Bits RW Field Description
15:00 RW Message Data If the Message Enable bit is set, the message/vector data is driven
onto the lower word of the memory write transaction’s data phase.
This bit is read/write.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 20 Track ID: JATR-1076-21 Rev. 1.1
6.9.
MSI-X
6.9.1. MSI-X Capability Structure in PCI Configuration Space
Figure 7. MSI-X Capability Structure
Figure 8. MSI-X Table Structure
Figure 9. MSI-X PBA Structure
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 21 Track ID: JATR-1076-21 Rev. 1.1
6.9.2. Message Control
Table 16. Message Control
Bits RW Field Description
15 RW MSI-X Enable If 1 and the MSI Enable bit in the MSI Message Control register
is 0, the function is permitted to use MSI-X to request service and
is prohibited from using its INTx# pin. System configuration
software sets this bit to enable MSI-X. A device driver is
prohibited from writing this bit to mask a function’s service
request.
If 0, the function is prohibited from using MSI-X to request
service.
This bit’s state after reset is 0 (MSI-X is disabled).
This bit is read/write.
14 RW Function Mask If 1, all of the vectors associated with the function are masked,
regardless of their per-vector Mask bit states.
If 0, each vector’s Mask bit determines whether the vector is
masked or not.
Setting or clearing the MSI-X Function Mask bit has no effect on
the state of the per-vector Mask bits. This bit’s state after reset is 0
(unmasked).
This bit is read/write.
13:11 RO Reserved Always returns 0 on a read. A write operation has no effect.
10:00 RO Table Size System software reads this field to determine the
MSI-X Table Size N, which is encoded as N-1. The
RTL8111C-GR value is ‘00000000001’, indicating a table size of
2.
6.9.3. Table Offset/BIR
Table 17. Table Offset/BIR
Bits RW Field Description
31:03 RW Table Offset Used as an offset from the address contained by one of the
function’s Base Address registers to point to the base of the
MSI-X Table. The lower 3 BIR bits are masked off (set to zero)
by software to form a 32bit QWORD-aligned offset.
This field is read only.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 22 Track ID: JATR-1076-21 Rev. 1.1
Bits RW Field Description
02:00 RO BIR Indicates which one of a function’s Base Address registers,
located beginning at 10h in Configuration Space, is used to map
the function’s MSI-X Table into Memory Space.
BIR Value Base Address register
0 10h
1 14h
2 18h
3 1Ch
4 20h
5 24h
6 Reserved
7 Reserved
For a 64-bit Base Address register, the BIR indicates the lower
DWORD. With PCI-to-PCI bridges, BIR values 2 through 5 are
also reserved. The function’s Base Address registers of
RTL8111C-GR located beginning at 20h.
This field is read only.
6.9.4. PBA Offset/PBA BIR
Table 18. PBA Offset/PBA BIR
Bits RW Field Description
31:03 RO PBA Offset Used as an offset from the address contained by one of the
function’s Base Address registers to point to the base of the
MSI-X PBA. The lower 3 PBA BIR bits are masked off (set to
zero) by software to form a 32-bit QWORD-aligned offset.
This field is read only.
02:00 RO PBA BIR Indicates which one of a function’s Base Address registers,
located beginning at 10h in Configuration Space, is used to map
the function’s MSI-X PBA into Memory Space. The PBA BIR
value definitions are identical to those for the MSI-X Table BIR.
This field is read only.
6.9.5. Message Address for MSI-X Table Entries
Table 19. Message Address for MSI-X Table Entries
Bits RW Field Description
31:02 RW Message Address System-specified message lower address.
For MSI-X messages, the contents of this field from an MSI-X
Table entry specifies the lower portion of the DWORD aligned
address for the memory write transaction.
This field is read/write.
01:00 RW Message Address For proper DWORD alignment, software must always write
zeroes to these two bits; otherwise the result is undefined.
The state of these bits after reset must be 0.
These bits are permitted to be read only or read/write.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 23 Track ID: JATR-1076-21 Rev. 1.1
6.9.6. Message Upper Address for MSI-X Table Entries
Table 20. Message Upper Address for MSI-X Table Entries
Bits RW Field Description
31:00 RW Message Upper Address System-specified message upper address bits.
This field is read/write.
6.9.7. Message Data for MSI-X Table Entries
Table 21. Message Data
Bits RW Field Description
31:00 RW Message Data System-specified message data.
For MSI-X messages, the contents of this field are taken from an
MSI-X Table entry.
In contrast to message data used for MSI messages, the low-order
message data bits in MSI-X messages are not modified by the
function.
This field is read/write.
6.9.8. Vector Control for MSI-X Table Entries
Table 22. Vector Control for MSI-X Table Entries
Bits RW Field Description
31:01 RW Reserved After reset, the state of these bits must be 0. However, for
potential future use, software must preserve the value of these
reserved bits when modifying the value of other Vector Control
bits. If software modifies the value of these reserved bits, the
result is undefined.
00 RW Mask Bit When this bit is set, the function is prohibited from sending a
message using this MSI-X Table entry. However, any other
MSI-X Table entries programmed with the same vector will still
be capable of sending an equivalent message unless they are also
masked. This bit’s state after reset is 1 (entry is masked). This bit
is read/write.
6.9.9. Pending Bits for MSI-X PBA Entries
Table 23. Pending Bits for MSI-X PBA Entries
Bits RW Field Description
63:00 RW Pending Bits For each Pending Bit that is set, the function has a pending
message for the associated MSI-X Table entry. Pending bits that
have no associated MSI-X Table entry are reserved. After reset,
the state of reserved Pending bits must be 0. Software should
never write, and should only read Pending Bits. If software writes
to Pending Bits, the result is undefined.
Each Pending Bit’s state after reset is 0 (no message pending).
These bits are permitted to be read only or read/write.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 24 Track ID: JATR-1076-21 Rev. 1.1
6.10.
Receive-Side Scaling (RSS)
The RTL8111C-GR is compliant with the new Network Driver Interface Specification (NDIS) 6.0
Receive-Side Scaling (RSS) technology for the Microsoft Windows family of operating systems. RSS
allows packet receive-processing from a network adapter to be balanced across the number of available
computer processors, increasing perfromance on multi CPU platforms.
6.10.1. Receive-Side Scaling (RSS) Initialization
During RSS initialization, the Windows operating system will inform the RTL8111C-GR to store the
following parameters: hash function, hash type, hash bits, indirection table, BaseCPUNumber, and the
secret hash key.
Hash Function
The default hash function is the Toeplitz hash function.
Hash Type
The hash types indicate which field of the packet needs to be hashed to get the hash result. There are
several combinations of these fields, mainly, TCP/IPv4, IPv4, TCP/IPv6, IPv6, and IPv6 extension
headers.
• TCP/IPv4 requires hash calculations over the IPv4 source address, the IPv4 destination address, the
source TCP port and the destination TCP port.
• IPv4 requires hash calculations over the IPv4 source address and the IPv4 destination address.
• TCP/IPv6 requires hash calculations over the IPv6 source address, the IPv6 destination address, the
source TCP port and the destination TCP port.
• IPv6 requires hash calculations over the IPv6 source address and the IPv6 destination address
(Note: The RTL8111C-GR does not support the IPv6 extension header hash type in RSS).
Hash Bits
Hash bits are used to index the hash result into the indirection table
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 25 Track ID: JATR-1076-21 Rev. 1.1
Indirection Table
The Indirection Table stores values that are added to the BaseCPUNumber to enable RSS interrupts to be
restricted from some CPUs. The OS will update the Indirection Table to rebalance the load.
BaseCPUNumber
The lowest number CPU to use for RSS. BaseCPUNumber is added to the result of the indirection table
lookup.
Secret hash key
The key used in the Toeplitz function. For different hash types, the key size is different.
6.10.2. RSS Operation
After the parameters are set, the RTL8111C-GR will start hash calculation on each incoming packet and
forward each packet to its correct queue according to the hash result. If the incoming packet is not in the
hash type, it will be forwarded to the primary queue. The hash result plus the BaseCPUNumber will be
indexed into the indirection table to get the correct CPU number. The RTL8111C-GR uses three methods
to inform the system of incoming packets: inline interrupt, MSI, and MSIX. Periodically the OS will
update the indirection table to rebalance the load across the CPUs.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 26 Track ID: JATR-1076-21 Rev. 1.1
7. Characteristics
7.1.
Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to
the device, or device reliability will be affected. All voltages are specified reference to GND unless
otherwise specified.
Table 24. Absolute Maximum Ratings
Symbol Description Minimum Maximum Unit
VDD33, AVDD33 Supply Voltage 3.3V -0.3 +0.5 V
AVDD12, DVDD12 Supply Voltage 1.2V -0.3 +0.4 V
EVDD12 Supply Voltage 1.2V TBD TBD -
DCinput Input Voltage -0.3 Corresponding Supply Voltage + 0.5 V
DCoutput Output Voltage -0.3 Corresponding Supply Voltage + 0.5 V
Storage Temperature -55 +125 °C
* Refer to the most updated schematic circuit for correct configuration.
7.2.
Recommended Operating Conditions
Table 25. Recommended Operating Conditions
Description Pins Minimum Typical Maximum Unit
VDD33, AVDD33 2.97 3.3 3.63 V
AVDD12,
DVDD12 1.1 1.2 1.32 V
Supply Voltage VDD
EVDD12 1.14 1.2 1.26 V
Ambient Operating
Temperature TA - 0 - 70 °C
Maximum Junction
Temperature - - - 125 °C
* Refer to the most updated schematic circuit for correct configuration.
7.3.
Crystal Requirements
Table 26. Crystal Requirements
Symbol Description/Condition Minimum Typical Maximum Unit
Fref Parallel resonant crystal reference frequency,
fundamental mode, AT-cut type. - 25 - MHz
Fref Stability Parallel resonant crystal frequency stability,
fundamental mode, AT-cut type. Ta=25°C. -50 - +50 ppm
Fref Tolerance
Parallel resonant crystal frequency tolerance,
fundamental mode, AT-cut type.
Ta=-20°C ~+70°C.
-30 - +30 ppm
Fref
Duty Cycle Reference clock input duty cycle. 40 - 60 %
CL Load Capacitance. - TBD - pF
ESR Equivalent Series Resistance. - TBD -
DL Drive Level. - TBD 0.5 mW
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 27 Track ID: JATR-1076-21 Rev. 1.1
7.4.
Thermal Characteristics
Table 27. Thermal Characteristics
Parameter Minimum Maximum Units
Storage Temperature -55 +125 °C
Ambient Operating
Temperature 0 70 °C
7.5.
DC Characteristics
Table 28. DC Characteristics
Symbol Parameter Conditions Minimum Typical Maximum Units
VDD33,
AVDD33 3.3V Supply Voltage - 2.97 3.3 3.63 V
EVDD12,
AVDD12 1.2V Supply Voltage - 1.1 1.2 1.32 V
DVDD12 1.2V Supply Voltage - 1.1 1.2 1.32 V
Vo h Minimum High Level
Output Voltage Ioh = -4mA 0.9 * VDD33 - VDD33 V
Vo l Maximum Low Level
Output Voltage Iol= 4mA 0 - 0.1 * VDD33 V
Vih Minimum High Level
Input Voltage - 1.8 - - V
Vil Maximum Low Level
Input Voltage - - - 0.8 V
Iin Input Current Vin = VDD33 or
GND 0 - 0.5 µA
Icc33
Average Operating
Supply Current from
3.3V
At 1Gbps with
heavy network
traffic
- TBD - mA
Icc12
Average Operating
Supply Current from
1.8V
At 1Gbps with
heavy network
traffic
- TBD - mA
* Refer to the most updated schematic circuit for correct configuration.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 28 Track ID: JATR-1076-21 Rev. 1.1
7.6.
AC Characteristics
7.6.1. Serial EEPROM Interface Timing
93C46(64*16)/93C56(128*16)
EESK
EECS
EEDI
EEDO
110An A2 A0A1
Dn D1 D0
EESK
(Read)
(Write)
(Read)
(Write)
0
tcs
EESK
EECS
EEDI
EEDO
110An A0 ...
Dn
tcs
...
BUSY READY
High Impedance
High Impedance
twp
EECS
EEDI
EEDO
EEDO
(Read)
(Program) STATUS VALID
tsk
tskh tskl
tcss
tdis tdih
tdos tdoh
tcsh
tsv
D0
Figure 10. Serial EEPROM Interface Timing
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 29 Track ID: JATR-1076-21 Rev. 1.1
Table 29. EEPROM Access Timing Parameters
Symbol Parameter EEPROM Type Min. Max. Unit
tcs Minimum CS Low Time 9346 1000 - ns
twp Write Cycle Time 9346 - 10 ms
tsk SK Clock Cycle Time 9346 4 - µs
tskh SK High Time 9346 1000 - ns
tskl SK Low Time 9346 1000 - ns
tcss CS Setup Time 9346 200 - ns
tcsh CS Hold Time 9346 0 - ns
tdis DI Setup Time 9346 400 - ns
tdih DI Hold Time 9346 400 - ns
tdos DO Setup Time 9346 2000 - ns
tdoh DO Hold Time 9346 - 2000 ns
tsv CS to Status Valid 9346 - 1000 ns
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 30 Track ID: JATR-1076-21 Rev. 1.1
7.7.
PCI Express Bus Parameters
7.7.1. Differential Transmitter Parameters
Table 30. Differential Transmitter Parameters
Symbol Parameter Min Typical Max Units
UI Unit Interval2 399.88 400 400.12 ps
VTX-DIFFp-p Differential Peak to Peak Output Voltage 0.800 - 1.2 V
VTX-DE-RATIO De-Emphasized Differential Output Voltage (Ratio) -3.0 -3.5 -4.0 dB
TTX-EYE Minimum Tx Eye Width 0.75 - - UI
TTX-EYE-MEDIAN-
to-MAX-JITTER
Maximum time between the jitter median and
maximum deviation from the median
- - 0.125 UI
TTX-RISE, TTX-FALL D+/D- Tx Output Rise/Fall Time 0.125 - - UI
VTX-CM-ACp RMS AC Peak Common Mode Output Voltage - - 20 mV
VTX-CM-DCACTIVE-
IDLEDELTA
Absolute Delta of DC Common Mode Voltage During
L0 and Electrical Idle
0 - 100 mV
VTX-CM-DCLINE-
DELTA
Absolute Delta of DC Common Mode Voltage between
D+ and D-
0 - 25 mV
VTX-IDLE-DIFFp Electrical Idle Differential Peak Output Voltage 0 - 20 mV
VTX-RCV-DETECT The amount of voltage change allowed during
Receiver Detection
- - 600 mV
VTX-DC-CM The TX DC Common Mode Voltage 0 - 3.6 V
ITX-SHORT TX Short Circuit Current Limit - - 90 mA
TTX-IDLE-MIN Minimum time spent in Electrical Idle 50 - - UI
TTX-IDLE- SETTO-IDLE Maximum time to transition to a valid Electrical Idle
after sending an Electrical Idle ordered set
- - 20 UI
TTX-IDLE-TOTO-
DIFF-DATA
Maximum time to transition to valid TX specifications
after leaving an Electrical Idle condition
- - 20 UI
RLTX-DIFF Differential Return Loss 10 - - dB
RLTX-CM Common Mode Return Loss 6 - - dB
ZTX-DIFF-DC DC Differential TX Impedance 80 100 120
LTX-SKEW Lane-to-Lane Output Skew - - 500+2
UI
ps
CTX AC Coupling Capacitor 75 - 200 nF
Tcrosslink Crosslink Random Timeout 0 - 1 ms
Note1: Refer to PCI Express Base Specification, rev.1.1, for correct measurement environment setting of each parameter.
Note2: The data rate can be modulated with an SSC (Spread Spectrum Clock) from +0 to -0.5% of the nominal data rate
frequency, at a modulation rate in the range not exceeding 30 kHz – 33 kHz. The +/- 300 ppm requirement still
holds, which requires the two communicating ports be modulated such that they never exceed a total of 600 ppm
difference.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 31 Track ID: JATR-1076-21 Rev. 1.1
7.7.2. Differential Receiver Parameters
Table 31. Differential Receiver Parameters
Symbol Parameter Min. Typical Max. Units
UI Unit Interval 399.88 400 400.12 ps
VRX-DIFFp-p Differential Input Peak to Peak Voltage 0.175 - 1.200 V
TRX-EYE Minimum Receiver Eye Width 0.4 - - UI
TRX-EYE-MEDIAN-to-
MAX-JITTER
Maximum time between the jitter median and
maximum deviation from the median
- - 0.3 UI
VRX-CM-ACp AC Peak Common Mode Input Voltage - - 150 mV
RLRX-DIFF Differential Return Loss 10 - - dB
RLRX-CM Common Mode Return Loss 6 - - dB
ZRX-DIFF-DC DC Differential Input Impedance 80 100 120
ZRX--DC DC Input Impedance 40 50 60
ZRX-HIGH-IMP-DC Powered Down DC Input Impedance 200 k - -
VRX-IDLE-DET-DIFFp-p Electrical Idle Detect Threshold 65 - 175 mV
TRX-IDLE-DET-
DIFFENTERTIME
Unexpected Electrical Idle Enter Detect Threshold
Integration Time
- - 10 ms
LRX-SKEW Total Skew - - 20 ns
Note: Refer to PCI Express Base Specification, rev.1.1, for correct measurement environment setting of each parameter.
7.7.3. REFCLK Parameters
Table 32. REFCLK Parameters
Symbol Parameter 100MHz Input
Min Max
Units Note
Rise Edge Rate Rising Edge Rate 0.6 4.0 V/ns 2,3
Fall Edge Rate Falling Edge Rate 0.6 4.0 V/ns 2,3
VIH Differential Input High Voltage +150 - mV 2
VIL Differential Input Low Voltage - -150 mV 2
VCROSS Absolute crossing point voltage +250 +550 mV 1,4,5
VCROSS DELTA Variation of VCROSS over all rising clock
edges
- +140 mV 1,4,9
VRB Ring-back Voltage Margin -100 +100 mV 2,12
TSTABLE Time before VRB is allowed 500 - ps 2,12
TPERIOD AVG Average Clock Period Accuracy -300 +2800 ppm 2,10,13
TPERIOD ABS Absolute Period (including Jitter and
Spread Spectrum)
9.847 10.203 ns 2,6
TCCJITTER Cycle to Cycle jitter - 150 ps 2
VMAX Absolute Max input voltage - +1.15 V 1,7
VMIN Absolute Min input voltage - -0.3 V 1,8
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 32 Track ID: JATR-1076-21 Rev. 1.1
Symbol Parameter 100MHz Input
Min Max
Units Note
Duty Cycle Duty Cycle 40 60 % 2
Rise-Fall Matching Rising edge rate (REFCLK+) to falling
edge rate (REFCLK-) matching
- 20 % 1,14
ZC-DC Clock source DC impedance 40 60 1,11
Note1: Measurement taken from single ended waveform.
Note2: Measurement taken from differential waveform.
Note3: Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-).
The signal must be monotonic through the measurement region for rise and fall time. The 300 mV measurement
window is centered on the differential zero crossing. See Figure 14, page 34.
Note4: Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the
falling edge of REFCLK-. See Figure 10, page 28.
Note5: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
Refers to all crossing points for this measurement. See Figure 10, page 28.
Note6: Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative
PPM tolerance, and spread spectrum modulation. See Figure 13, page 33.
Note7: Defined as the maximum instantaneous voltage including overshoot. See Figure 10, page 28.
Note8: Defined as the minimum instantaneous voltage including undershoot. See Figure 10, page 28.
Note9: Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the
maximum allowed variance in VCROSS for any particular system. See Figure 11, page 33.
Note10: Refer to Section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding PPM
considerations.
Note11: System board compliance measurements must use the test load card described in Figure16. REFCLK+ and
REFCLK- are to be measured at the load capacitors CL. Single ended probes must be used for measurements
requiring single ended measurements. Either single ended probes with math or differential probe can be used for
differential measurements. Test load CL = 2 pF.
Note12: TSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after
rising/falling edges before it is allowed to droop back into the VRB ±100 mV differential range. See Figure 15.
Note13: PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of
100.000000 MHz exactly or 100 Hz. For 300 PPM then we have a error budget of 100 Hz/PPM * 300 PPM = 30
kHz. The period is to be measured with a frequency counter with measurement window set to 100 ms or greater.
The ±300 PPM applies to systems that do not employ Spread Spectrum or that use common clock source. For
systems employing Spread Spectrum there is an additional 2500 PPM nominal shift in maximum period resulting
from the 0.5% down spread resulting in a maximum average period specification of +2800 PPM
Note14: Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a
±75 mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The
median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate
calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-, the
maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 12, page 33.
Note15: Refer to PCI Express Card Electromechanical Specification, rev.1.1, for correct measurement environment
setting of each parameter.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 33 Track ID: JATR-1076-21 Rev. 1.1
Figure 11. Single-Ended Measurement Points for Absolute Cross Point and Swing
Figure 12. Single-Ended Measurement Points for Delta Cross Point
Figure 13. Single-Ended Measurement Points for Rise and Fall Time Matching
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 34 Track ID: JATR-1076-21 Rev. 1.1
Figure 14. Differential Measurement Points for Duty Cycle and Period
Figure 15. Differential Measurement Points for Rise and Fall Time
Figure 16. Differential Measurement Points for Ringback
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 35 Track ID: JATR-1076-21 Rev. 1.1
Figure 17. Reference Clock System Measurement Point and Loading
7.7.4. Auxiliary Signal Timing Parameters
Table 33. Auxiliary Signal Timing Parameters
Symbol Parameter Min Max Units
TPVPERL Power stable to PERSTB inactive 100 - ms
TPERST-CLK REFCLK stable before PERSTB inactive 100 - µs
TPERST PERSTB active time 100 - µs
TFAIL Power level invalid to PWRGD inactive - 500 ns
TWKRF LANWAKEB rise – fall time - 100 ns
3.3 Vaux
3.3/12V
PERSTB
REFCLK
PCI-E Link
Power Stable
Inactive Active Inactive
Wakeup Event
T
T
TPERST
TFAIL
Clock not
Stable
PVPERL
PERST-CLK
Active
Clock Stable Clock Stable
Power Stable
Figure 18. Auxiliary Signal Timing
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 36 Track ID: JATR-1076-21 Rev. 1.1
8. Mechanical Dimensions
9. Ordering Information
Table 34. Ordering Information
Part Number Package Status
RTL8111C-GR 64-Pin QFN ‘Green’ package Production
Note: See page 3 for package ID information.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
NOTE: RTL8111C’s exposed pad size is L/F 3
