Sim SE Command Reference CR306SE Cmds
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ModelSim ® Advanced Verification and Debugging SE Command Reference Version 6.0b Published: 15/Nov/04 CR-2 This document is for information and instruction purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made. The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever. MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. RESTRICTED RIGHTS LEGEND 03/97 U.S. Government Restricted Rights. The SOFTWARE and documentation have been developed entirely at private expense and are commercial computer software provided with restricted rights. Use, duplication or disclosure by the U.S. Government or a U.S. Government subcontractor is subject to the restrictions set forth in the license agreement provided with the software pursuant to DFARS 227.7202-3(a) or as set forth in subparagraph (c)(1) and (2) of the Commercial Computer Software - Restricted Rights clause at FAR 52.227-19, as applicable. Contractor/manufacturer is: Mentor Graphics Corporation 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. This is an unpublished work of Mentor Graphics Corporation. Contacting ModelSim Support Telephone: 503.685.0820 Toll-Free Telephone: 877-744-6699 Website: www.model.com Support: www.model.com/support ModelSim SE Command Reference Technical support and updates CR-3 Technical support and updates Support Model Technology online and email technical support options, maintenance renewal, and links to international support contacts: www.model.com/support/default.asp Mentor Graphics support: www.mentor.com/supportnet Updates Access to the most current version of ModelSim: www.model.com/downloads/default.asp Latest version email Place your name on our list for email notification of news and updates: www.model.com/products/informant.asp ModelSim SE Command Reference CR-4 Where to find our documentation ModelSim documentation is available from our website at www.model.com/support or in the following formats and locations: Document Format How to get it ModelSim Installation & Licensing Guide paper shipped with ModelSim PDF select Help > Documentation; also available from the Support page of our web site: www.model.com ModelSim Quick Guide (command and feature quick-reference) paper shipped with ModelSim PDF select Help > Documentation, also available from the Support page of our web site: www.model.com ModelSim Tutorial PDF, HTML select Help > Documentation; also available from the Support page of our web site: www.model.com ModelSim User’s Manual PDF, HTML select Help > Documentation ModelSim Command Reference PDF, HTML select Help > Documentation ModelSim GUI Reference PDF, HTML select Help > Documentation Foreign Language Interface Reference PDF, HTML select Help > Documentation Std_DevelopersKit User’s Manual PDF www.model.com/support/documentation/BOOK/sdk_um.pdf The Standard Developer’s Kit is for use with Mentor Graphics QuickHDL. Command Help ASCII type help Error message help ASCII type verror Tcl Man Pages (Tcl manual) HTML select Help > Tcl Man Pages, or find contents.htm in \modeltech\docs\tcl_help_html Technotes HTML select Technotes dropdown on www.model.com/support ModelSim SE Command Reference [command name]at the prompt in the Transcript pane at the Transcript or shell prompt CR-5 Table of Contents Technical support and updates CR-3 bookmark add wave CR-71 Where to find our documentation CR-4 bookmark delete wave CR-72 bookmark goto wave CR-73 Syntax and conventions (CR-9) Documentation conventions CR-10 File and directory pathnames CR-11 Design object names CR-12 Wildcard characters CR-17 ModelSim variables CR-17 Simulation time units CR-18 Comments in argument files CR-18 Command shortcuts CR-18 Command history shortcuts CR-19 Numbering conventions CR-20 GUI_expression_format CR-22 bookmark list wave CR-74 bp CR-75 cd CR-78 cdbg CR-79 change CR-81 change_menu_cmd CR-83 check contention add CR-84 check contention config CR-86 check contention off CR-87 check float add CR-88 check float config CR-89 check float off CR-90 check stable off CR-91 Commands (CR-31) check stable on CR-92 checkpoint CR-93 Command reference table CR-32 compare add CR-94 .main clear CR-43 compare annotate CR-98 abort CR-44 compare clock CR-99 add button CR-45 compare configure CR-101 add dataflow CR-47 compare continue CR-103 add list CR-48 compare delete CR-104 add watch CR-51 compare end CR-105 add wave CR-52 compare info CR-106 add_menu CR-56 compare list CR-107 add_menucb CR-58 compare options CR-108 add_menuitem CR-59 compare reload CR-112 add_separator CR-60 compare reset CR-113 add_submenu CR-61 compare run CR-114 alias CR-62 compare savediffs CR-115 assertion fail CR-63 compare saverules CR-116 assertion pass CR-65 compare see CR-117 assertion report CR-67 compare start CR-119 batch_mode CR-69 compare stop CR-121 bd CR-70 compare update CR-122 ModelSim SE Command Reference CR-6 Table of Contents configure CR-123 fcover save CR-175 context CR-127 find CR-176 coverage clear CR-128 force CR-180 coverage exclude CR-129 gdb dir CR-183 coverage reload CR-131 getactivecursortime CR-184 coverage report CR-132 getactivemarkertime CR-185 coverage save CR-135 help CR-186 dataset alias CR-136 history CR-187 dataset clear CR-137 lecho CR-188 dataset close CR-138 left CR-189 dataset info CR-139 log CR-191 dataset list CR-140 lshift CR-193 dataset open CR-141 lsublist CR-194 dataset rename CR-142 macro_option CR-195 dataset save CR-143 mem display CR-196 dataset snapshot CR-144 mem list CR-198 delete CR-146 mem load CR-199 describe CR-147 mem save CR-202 disablebp CR-148 mem search CR-204 disable_menu CR-149 modelsim CR-206 disable_menuitem CR-150 next CR-207 do CR-151 noforce CR-208 down CR-152 nolog CR-209 drivers CR-154 notepad CR-211 dumplog64 CR-155 noview CR-212 echo CR-156 nowhen CR-213 edit CR-157 onbreak CR-214 enablebp CR-158 onElabError CR-215 enable_menu CR-159 onerror CR-216 enable_menuitem CR-160 pause CR-217 environment CR-161 play CR-218 examine CR-162 pop CR-219 exit CR-166 power add CR-220 fcover clear CR-167 power report CR-221 fcover comment CR-168 power reset CR-222 fcover configure CR-169 precision CR-223 fcover reload CR-171 printenv CR-224 fcover report CR-173 profile clear CR-225 ModelSim SE Command Reference CR-7 profile interval CR-226 toggle add CR-279 profile off CR-227 toggle disable CR-281 profile on CR-228 toggle enable CR-282 profile option CR-229 toggle report CR-283 profile reload CR-230 toggle reset CR-284 profile report CR-231 transcribe CR-285 project CR-233 transcript CR-286 property list CR-234 transcript file CR-287 property wave CR-235 tssi2mti CR-288 push CR-237 unsetenv CR-289 pwd CR-238 up CR-290 quietly CR-239 vcd add CR-292 quit CR-240 vcd checkpoint CR-293 radix CR-241 vcd comment CR-294 readers CR-242 vcd dumpports CR-295 record CR-243 vcd dumpportsall CR-297 report CR-244 vcd dumpportsflush CR-298 restart CR-246 vcd dumpportslimit CR-299 restore CR-248 vcd dumpportsoff CR-300 resume CR-249 vcd dumpportson CR-301 right CR-250 vcd file CR-302 run CR-252 vcd files CR-304 sccom CR-254 vcd flush CR-306 scgenmod CR-258 vcd limit CR-307 search CR-260 vcd off CR-308 searchlog CR-262 vcd on CR-309 seetime CR-264 vcd2wlf CR-310 setenv CR-265 vcom CR-311 shift CR-266 vcover convert CR-319 show CR-267 vcover merge CR-320 simstats CR-268 vcover report CR-322 splitio CR-270 vcover stats CR-325 status CR-271 vdel CR-327 step CR-272 vdir CR-328 stop CR-273 verror CR-329 tb CR-274 vgencomp CR-330 tcheck_set CR-275 view CR-332 tcheck_status CR-277 virtual count CR-334 ModelSim SE Command Reference CR-8 Table of Contents virtual define CR-335 wave create CR-397 virtual delete CR-336 wave edit CR-400 virtual describe CR-337 wave export CR-403 virtual expand CR-338 wave import CR-404 virtual function CR-339 wave modify CR-405 virtual hide CR-342 when CR-407 virtual log CR-343 where CR-412 virtual nohide CR-345 wlf2log CR-413 virtual nolog CR-346 wlf2vcd CR-415 virtual region CR-348 wlfman CR-416 virtual save CR-349 wlfrecover CR-420 virtual show CR-350 write cell_report CR-421 virtual signal CR-351 write format CR-422 virtual type CR-354 write list CR-424 vlib CR-356 write preferences CR-425 vlog CR-358 write report CR-426 vmake CR-369 write timing CR-427 vmap CR-370 write transcript CR-428 vopt CR-371 write tssi CR-429 vsim CR-373 write wave CR-431 vsim CR-392 vsource CR-393 wave CR-394 ModelSim SE Command Reference Index CR-9 Syntax and conventions Chapter contents Documentation conventions . . . . . . . . . . . . CR-10 File and directory pathnames . . . . . . . . . . . . CR-11 Design object names . . . . . . . . . . Object name syntax . . . . . . . . . SystemC class/structure/union member specification. Specifying names . . . . . . . . . . Escaping brackets and spaces in array slices . . . Environment variables and pathnames . . . . Name case sensitivity . . . . . . . . . Extended identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wildcard characters . . . . . . . . . . . . . . CR-17 ModelSim variables . . . . . . . . . . . . . . CR-17 Simulation time units . . . . . . . . . . . . . . CR-18 Comments in argument files . . . . . . . . . . . . CR-18 Command shortcuts . CR-12 CR-12 CR-13 CR-14 CR-15 CR-15 CR-15 CR-16 . . . . . . . . . . . . . CR-18 Command history shortcuts . . . . . . . . . . . . CR-19 Numbering conventions . . . . VHDL numbering conventions . Verilog numbering conventions . . . . . . . . . . . . . . . . . . . . . . . . . . CR-20 . CR-20 . CR-21 GUI_expression_format . . . . . . . . . . Expression typing . . . . . . . . . . . Expression syntax . . . . . . . . . . . Signal and subelement naming conventions . . . . Grouping and precedence . . . . . . . . . Concatenation of signals or subelements . . . . . Record field and SystemC class/structure/union members Searching for binary signal values in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . CR-22 CR-22 CR-23 CR-27 CR-27 CR-27 CR-29 CR-29 ModelSim SE Command Reference CR-10 Syntax and conventions Documentation conventions This manual uses the following conventions to define ModelSim command syntax. Syntax notation Description < > angled brackets surrounding a syntax item indicate a userdefined argument; do not enter the brackets in commands [ ] square brackets generally indicate an optional item; if the brackets surround several words, all must be entered as a group; the brackets are not entereda { } braces indicate that the enclosed expression contains one or more spaces yet should be treated as a single argument, or that the expression contains square brackets for an index; for either situation, the braces are entered ... an ellipsis indicates items that may appear more than once; the ellipsis itself does not appear in commands | the vertical bar indicates a choice between items on either side of it; do not include the bar in the command monospaced type monospaced type is used in command examples # comments included with commands are preceded by the number sign (#); useful for adding comments to DO files (macros) a. One exception to this rule is when you are using Verilog syntax to designate an array slice. For example, add wave {vector1[4:0]} The square brackets in this case denote an index. The braces prevent the Tcl interpreter from treating the text within the square brackets as a Tcl command. Note: Neither the prompt at the beginning of a line nor the key that ends a line is shown in the command examples. ModelSim SE Command Reference File and directory pathnames CR-11 File and directory pathnames Several ModelSim commands have arguments that point to files or directories. For example, the -y argument to vlog specifies the Verilog source library directory to search for undefined modules. Spaces in file pathnames must be escaped or the entire path must be enclosed in quotes. For example: vlog top.v -y C:/Documents\ and\ Settings/projects/dut or vlog top.v -y "C:/Documents and Settings/projects/dut" ModelSim SE Command Reference CR-12 Syntax and conventions Design object names Design objects are organized hierarchically. Each of the following objects creates a new level in the hierarchy: • VHDL component instantiation statement, block statement, and package • Verilog module instantiation, named fork, named begin, task and function • SystemC module instantiation Object name syntax The syntax for specifying object names in ModelSim is as follows: [ ][ ][ ] [ ] where datasetName is the logical name of the WLF file in which the object exists. The currently active simulation is the “sim” dataset. Any loaded WLF file is referred to by the logical name specified when the WLF file was loaded. See Chapter 8 - WLF files (datasets) and virtuals for more information. datasetSeparator is the character used to terminate the dataset name. The default is ’:’, though a different character (other than ’\’) may be specified as the dataset separator via the DatasetSeparator (UM-531) variable in the modelsim.ini file. The default is ':'. This character must be different than the pathSeparator character. pathSeparator is the character used to separate hierarchical object names. Normally, '/' is used for VHDL and '.' is used for Verilog, although other characters (except '\') may be specified via the PathSeparator (UM-533) variable in the modelsim.ini file. This character must be different than the datasetSeparator. Both '.' and '/' can be used for SystemC. hierarchicalPath is a set of hierarchical instance names separated by a path separator and ending in a path separator prior to the objectName. For example, /top/proc/clk. objectName is the name of an object in a design. elementSelection indicates some combination of the following: Array indexing - Single array elements are specified using either parentheses "()" or square brackets "[]" around a single number. Array slicing - Slices (or part-selects) of arrays are specified using either parentheses "()" or square brackets "[]" around a range specification. A range is two numbers separated by one of the following: " to ", " downto ", ":". See "Escaping brackets and spaces in array ModelSim SE Command Reference Design object names CR-13 slices" (CR-15) for important information about using square brackets in ModelSim commands. Record field selection - A record field is specified using a period "." followed by the name of the field. C++ class, structure, and union member selection - A class, structure, or union member is specified using the record field specification syntax, described just above. SystemC class/structure/union member specification You can specify members of SystemC structures and classes using HDL record syntax. The syntax for specifying members of a base class using ModelSim is different than C++. In C++, it is not necessary to specify the base class: . Whereas, in ModelSim you must include the name of the base class: . . Example Let’s say you have a base class and a descendant class: class dog { private: int value; }; class beagle : public dog { private: int value; dog d; }; You have an sc_signal<> of type beagle somewhere in your code: sc_signal spot; Legal names for viewing this signal are: spot spot.* spot.value spot.dog spot.dog.* spot.dog.value Now, to examine the member value of the base class dog, you would type: exa spot.dog.value To examine the member value of member d, you would type: exa spot.d.value To examine the member value, you would type: exa spot.value ModelSim SE Command Reference CR-14 Syntax and conventions Specifying names We distinguish between four "types" of object names: simple, relative, fully-rooted, and absolute. A simple name does not contain any hierarchy. It is simply the name of an object (e.g., clk or data[3:0]) in the current context. A relative name does not start with a path separator and may or may not include a dataset name or a hierarchical path (e.g., u1/data or view:clk). A relative name is relative to the current context in the current or specified dataset. A fully-rooted name starts with a path separator and includes a hierarchical path to an object (e.g., /top/u1/clk).There is a special case of a fully-rooted name where the top-level design unit name can be unspecified (e.g., /u1/clk). In this case, the first top-level instance in the design is assumed. An absolute name is an exactly specified hierarchical name containing a dataset name and a fully rooted name (e.g., sim:/top/u1/clk). The current dataset is used when accessing objects where a dataset name is not specified as part of the name. The current dataset is determined by the dataset currently selected in the Structure window or by the last dataset specified in an environment command (CR-161). The current context in the current or specified dataset is used when accessing objects with relative or simple names. The current context is either the current process, if any, or the current instance if there is no current process or the current process is not in the current instance. The situation of the current process not being in the current instance can occur, for example, by selecting a different instance in the Structure tab or by using the environment command (CR-161) to set the current context to a different instance. Here are some examples of object names and what they specify: Syntax Description clk specifies the object clk in the current context /top/clk specifies the object clk in the top-level design unit. /top/block1/u2/clk specifies the object clk, two levels down from the top-level design unit block1/u2/clk specifies the object clk, two levels down from the current context array_sig[4] specifies an index of an array object {array_sig(1 to 10)} specifies a slice of an array object in VHDL or SystemC; see "Escaping brackets and spaces in array slices" (CR-15) for more information {mysignal[31:0]} specifies a slice of an array object in Verilog or SystemC; see "Escaping brackets and spaces in array slices" (CR-15) for more information record_sig.field specifies a field of a record, a C++ class or structure member, or a C++ base class ModelSim SE Command Reference Design object names CR-15 Escaping brackets and spaces in array slices Because ModelSim is a Tcl-based tool, you must use curly braces (’{}’) to "escape" square brackets and spaces when specifying array slices. For example: toggle add {data[3:0]} or toggle add {data(3 to 0)} For complete details on Tcl syntax, see "Tcl command syntax" (UM-474). Further details As a Tcl-based tool, ModelSim commands follow Tcl syntax. One problem people encounter with ModelSim commands is the use of square brackets (’[]’) or spaces when specifying array slices. As shown on the previous page, square brackets are used to specify slices of arrays (e.g., data[3:0]). However, in Tcl, square brackets signify command substitution. Consider the following example: set aluinputs [find -in alu/*] ModelSim evaluates the find command first and then sets variable aluinputs to the result of the find command. Obviously you don’t want this type of behavior when specifying an array slice, so you would use curly brace escape characters: add wave {/s/abc/data_in[10:1]} You must also use the escape characters if using VHDL syntax with spaces: add wave {/s/abc/data_in(10 downto 1)} Environment variables and pathnames You can substitute environment variables for pathnames in any argument that requires a pathname. For example: vlog -v $lib_path/und1 Assuming you have defined $lib_path on your system, vlog will locate the source library file und1 and search it for undefined modules. See "Environment variables" (UM-521) for more information. Note: Environment variable expansion does not occur in files that are referenced via the -f argument to vcom, vlog, or vsim. Name case sensitivity Name case sensitivity is different for VHDL and Verilog. VHDL names are not case sensitive except for extended identifiers in VHDL 1076-1993 or later. In contrast, all Verilog names are case sensitive. Names in ModelSim commands are case sensitive when matched against case sensitive identifiers, otherwise they are not case sensitive. SystemC names are case sensitive. ModelSim SE Command Reference CR-16 Syntax and conventions Extended identifiers The following are supported formats for extended identifiers for any command that takes an identifier. {\ext ident!\ } \\ext\ ident\!\\ ModelSim SE Command Reference # Note that trailing space before closing brace is required # All non-alpha characters escaped Wildcard characters CR-17 Wildcard characters Wildcard characters can be used in HDL object names in some simulator commands. Conventions for wildcards are as follows: Syntax Description * matches any sequence of characters ? matches any single character [] matches any one of the enclosed characters; a hyphen can be used to specify a range (for example, a-z, A-Z, 0-9); can be used only with the find command (CR-176) You can use the WildcardFilter Tcl preference variable to filter matching objects for the add wave, add log, add list, and find commands. Note: A wildcard character will never match a path separator. For example, /dut/* will match /dut/siga and /dut/clk. However, /dut* won’t match either of those. ModelSim variables ModelSim variables can be referenced in simulator commands by preceding the name of the variable with the dollar sign ($) character. ModelSim uses global Tcl variables for simulator state variables, simulator control variables, simulator preference variables, and user-defined variables (see "Preference variables located in Tcl files" (UM-540) for more information). See Appendix B - ModelSim variables in the User’s Manual for more information on variables. The report command (CR-244) returns a list of current settings for either the simulator state or simulator control variables. ModelSim SE Command Reference CR-18 Syntax and conventions Simulation time units You can specify the time unit for delays in all simulator commands that have time arguments. For example: force clk 1 50 ns, 1 100 ns -repeat 1 us run 2 ms Note that all the time units in a ModelSim command need not be the same. Unless you specify otherwise as in the examples above, simulation time is always expressed using the resolution units that are specified by the UserTimeUnit variable. See UserTimeUnit (UM-534). By default, the specified time units are assumed to be relative to the current time unless the value is preceded by the character @, which signifies an absolute time specification. Comments in argument files Argument files may be loaded with the -f argument of the vcom, vlog, sccom and vsim commands. The -f argument specifies a file that contains more command line arguments. Comments within the argument files follow these rules: • All text in a line beginning with // to its end is treated as a comment. • All text bracketed by /* ... */ is treated as a comment. Also, program arguments can be placed on separate lines in the argument file, with the newline characters treated as space characters. There is no need to put '\' at the end of each line. Command shortcuts • You may abbreviate command syntax, but there’s a catch — the minimum number of characters required to execute a command are those that make it unique. Remember, as we add new commands some of the old shortcuts may not work. For this reason ModelSim does not allow command name abbreviations in macro files. This minimizes your need to update macro files as new commands are added. • Multiple commands may be entered on one line if they are separated by semi-colons (;). For example: ModelSim> vlog -nodebug=ports level3.v level2.v ; vlog -nodebug top.v The return value of the last function executed is the only one printed to the transcript. This may cause some unexpected behavior in certain circumstances. Consider this example: vsim -c -do "run 20 ; simstats ; quit -f" top You probably expect the simstats results to display in the Transcript window, but they will not, because the last command is quit -f. To see the return values of intermediate commands, you must explicitly print the results. For example: vsim -do "run 20 ; echo [simstats]; quit -f" -c top ModelSim SE Command Reference Command shortcuts CR-19 Command history shortcuts The simulator command history may be reviewed, or commands may be reused, with these shortcuts at the ModelSim/VSIM prompt: Shortcut Description !! repeats the last command !n repeats command number n; n is the VSIM prompt number (e.g., for this prompt: VSIM 12>, n =12) !abc repeats the most recent command starting with "abc" ^xyz^ab^ replaces "xyz" in the last command with "ab" up and down arrows scrolls through the command history with the keyboard arrows click on prompt left-click once on a previous ModelSim or VSIM prompt in the transcript to copy the command typed at that prompt to the active cursor his or history shows the last few commands (up to 50 are kept) ModelSim SE Command Reference CR-20 Syntax and conventions Numbering conventions Numbers in ModelSim can be expressed in either VHDL or Verilog style. You can use two styles for VHDL numbers and one for Verilog. VHDL numbering conventions VHDL Style 1 The first of two VHDL number styles is: [ - ] [ radix # ] value [ # ] Element Description - indicates a negative number; optional radix can be any base in the range 2 through 16 (2, 8, 10, or 16); by default, numbers are assumed to be decimal; optional value specifies the numeric value, expressed in the specified radix; required # is a delimiter between the radix and the value; the first # sign is required if a radix is used, the second is always optional A ‘-’ can also be used to designate a "don’t care" element when you search for a signal value or expression in the List or Wave window. If you want the ‘-’ to be read as a "don’t care" element, rather than a negative sign, be sure to enclose the number in double quotes. For instance, you would type "-0110--" as opposed to -0110--. If you don’t include the double quotes, ModelSim will read the ‘-’ as a negative sign. Examples 16#FFca23# 2#11111110 -23749 VHDL Style 2 The second VHDL number style is: base "value" Element Description base specifies the base; binary: B, octal: O, hex: X; required value specifies digits in the appropriate base with optional underscore separators; default is decimal; required Examples B"11111110" X"FFca23" ModelSim SE Command Reference Numbering conventions CR-21 Searching for VHDL arrays in the Wave and List windows Searching for signal values in the Wave or List window may not work correctly for VHDL arrays if the target value is in decimal notation. You may get an error that the value is of incompatible type. Since VHDL does not have a radix indicator for decimal, the target value may get misinterpreted as a scalar value. Prefixing the value with the Verilog notation 'd should eliminate the problem, even if the signal is VHDL. Verilog numbering conventions Verilog numbers are expressed in the style: [ - ] [ size ] [ base ] value Element Description - indicates a negative number; optional size the number of bits in the number; optional base specifies the base; binary: ‘b or ‘B, octal: ‘o or ‘O, decimal: ‘d or ‘D, hex: ‘h or ‘H; optional value specifies digits in the appropriate base with optional underscore separators; default is decimal; required A ‘-’ can also be used to designate a "don’t care" element when you search for a signal value or expression in the List or Wave windows. If you want the ‘-’ to be read as a "don’t care" element, rather than a negative sign, be sure to enclose the number in double quotes. For instance, you would type "-0110--" as opposed to 7'b-0110--. If you don’t include the double quotes, ModelSim will read the ‘-’ as a negative sign. Examples ’b11111110 ’Hffca23 -23749 8’b11111110 21’H1fca23 DOS pathnames require a backslash (\), but ModelSim will accept either a backslash or the forward slash (/). It does this because by default ModelSim PE uses backslashes as pathname separators. Therefore it cannot recognize extended identifiers. You can change this behavior so that backslashes on comment lines are used for extended identifiers, but then you can only use forward slashes when you need pathname delimiters. To do this, "uncomment" the following line in the modelsim.ini file and set its value to zero. BackslashesArePathnameDelimiters = 0 This will allow command lines that can reference signals, variables, and design unit names that use extended identifiers; for example: examine \clock 2x\ ModelSim SE Command Reference CR-22 Syntax and conventions GUI_expression_format The GUI_expression_format is an option of several simulator commands that operate within the ModelSim GUI environment. The expressions help you locate and examine objects within the List and Wave windows (expressions may also be used through the Edit > Search menu in both windows). The commands that use the expression format are: compare add (CR-94), compare clock (CR-99), compare configure (CR-101), configure (CR-123), down (CR-152), examine (CR-162), left (CR-189), right (CR-250), searchlog (CR262), up (CR-290), virtual function (CR-339), and virtual signal (CR-351) Expression typing GUI expressions are typed. The supported types consist of the following scalar and array types. Scalar types The scalar types are as follows: boolean, integer, real, time (64-bit integer), enumeration, and signal state. Signal states are represented by the nine VHDL std_logic states: ’U’ ’X’ ’0’ ’1’ ’Z’ ’W’ ’L’ ’H’ and ’-’. Verilog states 0, 1, x, and z are mapped into these states and the Verilog strengths are ignored. Conversion is done automatically when referencing Verilog nets or registers. SystemC scalar types supported are: all the C/C++ types except class, structure, union, and array, as well as SystemC types sc_logic and sc_bit. Array types The supported array types are signed and unsigned arrays of signal states. This would correspond to the VHDL std_logic_array type. Verilog registers are automatically converted to these array types. The array type can be treated as either UNSIGNED or SIGNED, as in the IEEE std_logic_arith package. Normally, referencing a signal array causes it to be treated as UNSIGNED by the expression evaluator; to cause it to be treated as SIGNED, use casting as described below. Numeric operations supported on arrays are performed by the expression evaluator via ModelSim’s built-in numeric_standard (and similar) package routines. The expression evaluator selects the appropriate numeric routine based on SIGNED or UNSIGNED properties of the array arguments and the result. The enumeration types supported are any VHDL enumerated type. Enumeration literals may be used in the expression as long as some variable of that enumeration type is referenced in the expression. This is useful for sub-expressions of the form: (/memory/state == reading) The supported SystemC aggregate types are the C/C++ array types: union, class, structure, and array. Also supported are the SystemC array types: sc_bv , sc_lv , sc_int , etc. ModelSim SE Command Reference GUI_expression_format CR-23 Expression syntax GUI expressions generally follow C-language syntax, with both VHDL-specific and Verilog-specific conventions supported. These expressions are not parsed by the Tcl parser, and so do not support general Tcl; parentheses should be used rather than curly braces. Procedure calls are not supported. A GUI expression can include the following elements: Tcl macros, constants, array constants, variables, array variables, signal attributes, operators, and casting. Tcl macros Macros are useful for pre-defined constants or for entire expressions that have been previously saved. The substitution is done only once, when the expression is first parsed. Macro syntax is: $ Substitutes the string value of the Tcl global variable . Constants Type Values boolean value true false TRUE FALSE integer [0-9]+ real number |([ ]. [exp]) where the optional [exp] is: (e|E)[+|-][09]+ time integer or real optionally followed by time unit enumeration VHDL user-defined enumeration literal single bit constants expressed as any of the following: 0 1 x X z Z U H L W ’U’ ’X’ ’0’ ’1’ ’Z’ ’W’ ’L’ ’H’ ’-’ 1’b0 1’b1 Array constants, expressed in any of the following formats Type Values VHDL # notation # [#] Example: 16#abc123# VHDL bitstring "(U|X|0|1|Z|W|L|H|-)*" Example: "11010X11" Verilog notation [-][ ]’(b|B|o|O|d|D|h|H) (where includes 0-9, a-f, A-F, and ’-’) Example: 12’hc91 (This is the preferred notation because it removes the ambiguity about the number of bits.) Based notation 0x..., 0X..., 0o..., 0O..., 0b..., OB... ModelSim automatically zero fills unspecified upper bits. ModelSim SE Command Reference CR-24 Syntax and conventions Variables Variable Type Name of a signal The name may be a simple name, a VHDL or Verilog style extended identifier, or a VHDL or Verilog style path. The signal must be one of the following types: -- VHDL signal of type INTEGER, REAL, or TIME -- VHDL signal of type std_logic or bit -- VHDL signal of type user-defined enumeration -- Verilog net, Verilog register, Verilog integer, or Verilog real -- SystemC primitive channels of type scalar (e.g. bool, int, etc.) NOW Returns the value of time at the current location in the WLF file as the WLF file is being scanned (not the most recent simulation time). Array variables Variable Type Name of a signal -- VHDL signals of type bit_vector or std_logic_vector -- Verilog register -- Verilog net array -- SystemC primitive channels of type vector (e.g. sc_bv, sc_int, etc.) A subrange or index may be specified in either VHDL or Verilog syntax. Examples: mysignal(1 to 5), mysignal[1:5], mysignal (4), mysignal [4] Signal attributes ’event ’rising ’falling ’delayed() ’hasX The ’delayed attribute lets you assign a delay to a VHDL signal. To assign a delay to a signal in Verilog, use “#” notation in a sub-expression (e.g., #-10 /top/signalA). The hasX attribute lets you search for signals, nets, or registers that contains an X (unknown) value. See "Examples" (CR-26) below for further details on ’delayed and ’hasX. ModelSim SE Command Reference GUI_expression_format CR-25 Operators Operator Description Operator Description && boolean and sll/SLL shift left logical || boolean or sla/SLA shift left arithmetic ! boolean not srl/SRL shift right logical == equal sra/SRA shift right arithmetic != not equal ror/ROR rotate right === exact equal rol/ROL rotate left !== exact not equal + arithmetic add < less than - arithmetic subtract <= less than or equal * arithmetic multiply > greater than / arithmetic divide >= greater than or equal mod/MOD arithmetic modulus not/NOT/~ unary bitwise inversion rem/REM arithmetic remainder and/AND/& bitwise and | OR reduction nand/NAND bitwise nand ^ XOR reduction or/OR/| bitwise or nor/NOR bitwise nor xor/XOR bitwise xor xnor/XNOR bitwise xnor Note: Arithmetic operators use the std_logic_arith package. ModelSim SE Command Reference CR-26 Syntax and conventions Casting Casting Description (bool) convert to boolean (boolean) convert to boolean (int) convert to integer (integer) convert to integer (real) convert to real (time) convert to 64-bit integer (std_logic) convert to 9-state signal value (signed) convert to signed vector (unsigned) convert to unsigned vector (std_logic_vector) convert to unsigned vector Examples /top/bus & $bit_mask This expression takes the bitwise AND function of signal /top/bus and the array constant contained in the global Tcl variable bit_mask. clk’event && (/top/xyz == 16’hffae) This expression evaluates to a boolean true when signal clk changes and signal /top/xyz is equal to hex ffae; otherwise is false. clk’rising && (mystate == reading) && (/top/u3/addr == 32’habcd1234) Evaluates to a boolean true when signal clk just changed from low to high and signal mystate is the enumeration reading and signal /top/u3/addr is equal to the specified 32-bit hex constant; otherwise is false. (/top/u3/addr and 32’hff000000) == 32’hac000000 Evaluates to a boolean true when the upper 8 bits of the 32-bit signal /top/u3/addr equals hex ac. /top/signalA'delayed(10ns) This expression returns /top/signalA delayed by 10 ns. /top/signalA'delayed(10 ns) && /top/signalB This expression takes the logical AND of a delayed /top/signalA with /top/signalB. virtual function { (#-10 /top/signalA) && /top/signalB} mySignalB_AND_DelayedSignalA This evaluates /top/signalA at 10 simulation time steps before the current time, and takes the logical AND of the result with the current value of /top/signalB. The '#' notation uses positive numbers for looking into the future, and negative numbers for delay. This notation does not support the use of time units. ModelSim SE Command Reference GUI_expression_format CR-27 ((NOW > 23 us) && (NOW < 54 us)) && clk’rising && (mode == writing) Evaluates to a boolean true when WLF file time is between 23 and 54 microseconds, clk just changed from low to high, and signal mode is enumeration writing. searchlog -expr {dbus'hasX} {0 ns} dbus Searches for an ’X’ in dbus. This is equivalent to the expression: {dbus(0) == 'x' || dbus(1) == 'x'} . . .. This makes it possible to search for X values without having to write a type specific literal. Signal and subelement naming conventions ModelSim supports naming conventions for VHDL and Verilog signal pathnames, VHDL array indexing, Verilog bit selection, VHDL subrange specification, and Verilog part selection. All supported naming conventions for VHDL and Verilog are valid for SystemC designs. Examples in Verilog and VHDL syntax: top.chip.vlogsig /top/chip/vhdlsig vlogsig[3] vhdlsig(9) vlogsig[5:2] vhdlsig(5 downto 2) All of the above examples are valid for SystemC. Grouping and precedence Operator precedence generally follows that of the C language, but we recommend liberal use of parentheses. Concatenation of signals or subelements Elements in the concatenation that are arrays are expanded so that each element in the array becomes a top-level element of the concatenation. But for elements in the concatenation that are records, the entire record becomes one top-level element in the result. To specify that the records be broken down so that their subelements become top-level elements in the concatenation, use the concat_flatten directive. Currently we do not support leaving full arrays as elements in the result. (Please let us know if you need that option.) If the elements being concatenated are of incompatible base types, a VHDL-style record will be created. The record object can be expanded in the Objects and Wave windows just like an array of compatible type elements. Concatenation syntax for VHDL & & ... Concatenation syntax for Verilog &{ , , ... } &{ { }, , ... } Note that the concatenation syntax begins with "&{" rather than just "{". Repetition multipliers are supported, as illustrated in the second line. The repetition element itself may be an arbitrary concatenation subexpression. ModelSim SE Command Reference CR-28 Syntax and conventions Concatenation directives A concatenation directive (as illustrated below) can be used to constrain the resulting array range of a concatenation or influence how compound objects are treated. By default, the concatenation will be created with a descending index range from (n-1) downto 0, where n is the number of elements in the array. (concat_range 31:0) # Verilog syntax (concat_range (31:0)) # Also Verilog syntax (concat_range (31 downto 0)) # VHDL syntax The concat_range directive completely specifies the index range. (concat_ascending) The concat_ascending directive specifies that the index start at zero and increment upwards. (concat_flatten) The concat_flatten directive flattens the signal structure hierarchy. (concat_noflatten) The concat_noflatten directive groups signals together without merging them into one big array. The signals become elements of a record and retain their original names. When expanded, the new signal looks just like a group of signals. The directive can be used hierarchically with no limits on depth. (concat_sort_wild_ascending) The concat_sort_wild_ascending directive gathers signals by name in ascending order (the default is descending). (concat_reverse) The concat_reverse directive reverses the bits of the concatenated signals. Examples &{ "mybusbasename*" } Gathers all signals in the current context whose names begin with "mybusbasename", sorts those names in descending order, and creates a bus with index range (n-1) downto 0, where n is the number of matching signals found. (Note that it currently does not derive the index name from the tail of the one-bit signal name.) (concat_range 13:4)&{ "mybusbasename*" } Specifies the index range to be 13 downto 4, with the signals gathered by name in descending order. (concat_ascending)&{ "mybusbasename*" } Specifies an ascending range of 0 to n-1, with the signals gathered by name in descending order. (concat_ascending)((concat_sort_wild_ascending)&{"mybusbasename*" }) Specifies an ascending range of 0 to n-1, with the signals gathered by name in ascending order. (concat_reverse)(bus1 & bus2) Specifies that the bits of bus1 and bus2 be reversed in the output virtual signal. ModelSim SE Command Reference GUI_expression_format CR-29 Record field and SystemC class/structure/union members Arbitrarily-nested arrays and records are supported, but operators will only operate on one field at a time. That is, the expression {a == b} where a and b are records with multiple fields, is not supported. This would have to be expressed as: {(a.f1 == b.f1) && (a.f2 == b.f2)...} Examples: vhdlsig.field1 vhdlsig.field1.subfield1 vhdlsig.(5).field3 vhdlsig.field4(3 downto 0) Searching for binary signal values in the GUI When you use the GUI to search for signal values displayed in 4-state binary radix, you should be aware of how ModelSim maps between binary radix and std_logic. The issue arises because there is no “un-initialized” value in binary, while there is in std_logic. So, ModelSim relies on mapping tables to determine whether a match occurs between the displayed binary signal value and the underlying std_logic value. This matching algorithm applies only to searching via the GUI. It does not apply to VHDL or Verilog testbenches. For comparing VHDL std_logic/std_ulogic objects, ModelSim uses the table shown below. An entry of “0” in the table is “no match”; an entry of “1” is a “match”; an entry of “2” is a match only if you set the Tcl variable STDLOGIC_X_MatchesAnything to 1. Note that X will match a U, and - will match anything. Search Entry Matches as follows: U X 0 1 Z W L H - U 1 1 0 0 0 0 0 0 1 X 1 1 2 2 2 2 2 2 1 0 0 2 1 0 0 0 1 0 1 1 0 2 0 1 0 0 0 1 1 Z 0 2 0 0 1 0 0 0 1 W 0 2 0 0 0 1 0 0 1 L 0 2 1 0 0 0 1 0 1 H 0 2 0 1 0 0 0 1 1 - 1 1 1 1 1 1 1 1 1 ModelSim SE Command Reference CR-30 Syntax and conventions For comparing Verilog net values, ModelSim uses the table shown below. An entry of “2” is a match only if you set the Tcl variable “VLOG_X_MatchesAnything” to 1. Search Entry Matches as follows: 0 1 Z X 0 1 0 0 2 1 0 1 0 2 Z 0 0 1 2 X 2 2 2 1 This table also applies to SystemC types: sc_bit, sc_bv, sc_logic, sc_int, sc_uint, sc_bigint, sc_biguint. ModelSim SE Command Reference CR-31 Commands Chapter contents Command reference table . . . . . . . . . . . . . CR-32 The commands here are entered either in macro files or on the command line of the Main window. Some commands are automatically entered on the command line when you use the ModelSim graphical user interface. Note that in addition to the simulation commands documented in this section, you can use the Tcl commands described in the Tcl man pages (use the Main window menu selection: Help > Tcl Man Pages). Command syntax See "Syntax and conventions" (CR-9) for complete command syntax information. Note: ModelSim commands are case sensitive. Type them as they are shown in this reference. ModelSim SE Command Reference CR-32 Command reference table Command reference table The following table provides a brief description of each ModelSim command. Command details, arguments, and examples can be found at the page numbers given in the Command name column. Command name Action .main clear (CR-43) clears the Main window transcript abort (CR-44) halts the execution of a macro file interrupted by a breakpoint or error add button (CR-45) adds a user-defined button to the Main window button bar add dataflow (CR-47) adds the specified object to the Dataflow window add list (CR-48) lists VHDL signals and variables, and Verilog nets and registers, and their values in the List window add log also known as the log command; see log (CR-191) add watch (CR-51) adds signals or variables to the Monitor window add wave (CR-52) adds VHDL signals and variables, and Verilog nets and registers to the Wave window add_menu (CR-56) adds a menu to the menu bar of the specified window, using the specified menu name add_menucb (CR-58) creates a checkbox within the specified menu of the specified window add_menuitem (CR-59) creates a menu item within the specified menu of the specified window add_separator (CR-60) adds a separator as the next item in the specified menu path in the specified window add_submenu (CR-61) creates a cascading submenu within the specified menu path of the specified window alias (CR-62) creates a new Tcl procedure that evaluates the specified commands assertion fail (CR-63) configures fail tracking for PSL assertions assertion pass (CR-65) configures pass tracking for PSL assertions assertion report (CR-67) produces a textual summary of PSL assertion results batch_mode (CR-69) returns a 1 if ModelSim is operating in batch mode, otherwise returns a 0 bd (CR-70) deletes a breakpoint bookmark add wave (CR-71) adds a bookmark to the specified Wave window bookmark delete wave (CR-72) deletes bookmarks from the specified Wave window bookmark goto wave (CR-73) zooms and scrolls a Wave window using the specified bookmark ModelSim SE Command Reference Command reference table CR-33 Command name Action bookmark list wave (CR-74) displays a list of available bookmarks bp (CR-75) sets a breakpoint cd (CR-78) changes the ModelSim local directory to the specified directory cdbg (CR-79) provides command-line equivalents of the menu options that are available for "C Debug" (UM-399) change (CR-81) modifies the value of a VHDL variable or Verilog register variable change_menu_cmd (CR-83) changes the command to be executed for a specified menu item label, in the specified menu, in the specified window check contention add (CR-84) enables contention checking for the specified nodes check contention config (CR-86) writes checking messages to a file check contention off (CR-87) disables contention checking for the specified nodes check float add (CR-88) enables float checking for the specified nodes check float config (CR-89) writes checking messages to a file check float off (CR-90) disables float checking for the specified nodes check stable off (CR-91) disables stability checking check stable on (CR-92) enables stability checking on the entire design checkpoint (CR-93) saves the state of your simulation compare add (CR-94) compares signals in a reference design against signals in a test design compare annotate (CR-98) marks a compare difference as "ignore" or tags it with a text message compare clock (CR-99) defines a clock to be used with clocked-mode comparisons compare configure (CR-101) modifies options for compare signals or regions compare continue (CR-103) continues difference computation that had been suspended compare delete (CR-104) deletes a signal or region from the current comparison compare end (CR-105) closes the currently open comparison compare info (CR-106) lists the results of the comparison compare list (CR-107) lists all the compare add commands currently in effect compare options (CR-108) sets defaults for options used in other compare commands compare reload (CR-112) reloads a comparison previously saved with the compare savediffs command compare reset (CR-113) clears the current compare differences compare run (CR-114) runs the comparison on selected signals ModelSim SE Command Reference CR-34 Command reference table Command name Action compare savediffs (CR-115) saves comparison differences to a file that can be reloaded later compare saverules (CR-116) saves comparison setup information to a file that can be reloaded later compare see (CR-117) displays a comparison difference in the Wave window compare start (CR-119) starts a new dataset comparison compare stop (CR-121) halts active difference computation compare update (CR-122) updates the comparison differences configure (CR-123) invokes the List or Wave widget configure command for the current default List or Wave window context (CR-127) provides several operations on a context’s name coverage clear (CR-128) clears all coverage data obtained during previous run commands coverage exclude (CR-129) loads an exclusion filter file; or, allows you to exclude specific coverage reload (CR-131) seeds the coverage statistics with the output of a previous coverage save command coverage report (CR-132) produces a textual output of the coverage statistics that have been gathered up to this point coverage save (CR-135) saves current coverage statistics to a file that can be reloaded later, preserving instance-specific information dataset alias (CR-136) assigns an additional name to a dataset dataset clear (CR-137) clears the current simulation WLF file dataset close (CR-138) closes a dataset dataset info (CR-139) reports information about the specified dataset dataset list (CR-140) lists the open dataset(s) dataset open (CR-141) opens a dataset and references it by a logical name dataset rename (CR-142) changes the logical name of an opened dataset dataset save (CR-143) saves data from the current WLF file to a specified file dataset snapshot (CR-144) saves data from the current WLF file at a specified interval delete (CR-146) removes objects from either the List or Wave window describe (CR-147) displays information about the specified HDL object disablebp (CR-148) turns off breakpoints and when commands disable_menu (CR-149) disables the specified menu within the specified window ModelSim SE Command Reference Command reference table CR-35 Command name Action disable_menuitem (CR-150) disables the specified menu item within the specified menu path of the specified window do (CR-151) executes commands contained in a macro file down (CR-152) searches for signal transitions or values in the specified List window drivers (CR-154) displays in the Main window the current value and scheduled future values for all the drivers of a specified VHDL signal or Verilog net dumplog64 (CR-155) dumps the contents of the vsim.wlf file in a readable format echo (CR-156) displays a specified message in the Main window edit (CR-157) invokes the editor specified by the EDITOR environment variable enablebp (CR-158) turns on breakpoints and when commands turned off by the disablebp command (CR-148) enable_menu (CR-159) enables a previously-disabled menu enable_menuitem (CR-160) enables a previously-disabled menu item environment (CR-161) displays or changes the current dataset and region environment examine (CR-162) examines one or more objects, and displays current values (or the values at a specified previous time) in the Main window exit (CR-166) exits the simulator and the ModelSim application fcover clear (CR-167) clears the active functional coverage database fcover comment (CR-168) adds comment meta-data to the active functional coverage database fcover configure (CR-169) enables, disables, and sets coverage targets for PSL coverage directives fcover reload (CR-171) reloads a previously saved functional coverage database fcover report (CR-173) reports results of a functional coverage analysis fcover save (CR-175) saves the active functional coverage database to a file find (CR-176) displays the full pathnames of all objects in the design whose names match the name specification you provide force (CR-180) applies stimulus to VHDL signals and Verilog nets gdb dir (CR-183) sets the source directory for FLI/PLI/VPI C source code when using C Debug getactivecursortime (CR-184) gets the time of the active cursor in the Wave window getactivemarkertime (CR-185) gets the time of the active marker in the List window help (CR-186) displays in the Main window a brief description and syntax for the specified command history (CR-187) lists the commands executed during the current session ModelSim SE Command Reference CR-36 Command reference table Command name Action lecho (CR-188) takes one or more Tcl lists as arguments and pretty-prints them to the Main window left (CR-189) searches left (previous) for signal transitions or values in the specified Wave window log (CR-191) creates a wave log format (WLF) file containing simulation data for all objects whose names match the provided specifications lshift (CR-193) takes a Tcl list as an argument and shifts it in-place one place to the left, eliminating the left-most element lsublist (CR-194) returns a sublist of the specified Tcl list that matches the specified Tcl glob pattern macro_option (CR-195) controls the speed and delay of macro (DO file) playback, plus the level of debugging feedback mem display (CR-196) displays the memory contents of a selected instance to the screen mem list (CR-198) displays a flattened list of all memory instances in the current or specified context after a design has been elaborated mem load (CR-199) updates the simulation memory contents of a specified instance mem save (CR-202) saves the contents of a memory instance to a file in any of the supported formats: Verilog binary, Verilog hex, and MTI memory pattern data mem search (CR-204) finds and prints to the screen the first occurring match of a specified memory pattern in the specified memory instance modelsim (CR-206) starts the ModelSim GUI without prompting you to load a design; valid only for Windows platforms next (CR-207) continues a search; see the search command (CR-260) noforce (CR-208) removes the effect of any active force (CR-180) commands on the selected object nolog (CR-209) suspends writing of data to the WLF file for the specified signals notepad (CR-211) opens a simple text editor noview (CR-212) closes a window in the ModelSim GUI nowhen (CR-213) deactivates selected when (CR-407) commands onbreak (CR-214) specifies command(s) to be executed when running a macro that encounters a breakpoint in the source code onElabError (CR-215) specifies one or more commands to be executed when an error is encountered during elaboration onerror (CR-216) specifies one or more commands to be executed when a running macro encounters an error ModelSim SE Command Reference Command reference table CR-37 Command name Action pause (CR-217) interrupts the execution of a macro play (CR-218) plays a sequence of keyboard and mouse actions that were previously saved to a file with the record command (CR-243) pop (CR-219) moves one level up the C callstack power add (CR-220) specifies the signals or nets to track for power information power report (CR-221) writes out the power information for the specified signals or nets power reset (CR-222) resets power information to zero for the signals or nets specified with the power add command (CR-220) precision (CR-223) determines how real numbers display in the GUI printenv (CR-224) echoes to the Main window the current names and values of all environment variables profile clear (CR-225) clears any statistical performance or memory allocation data that has been gathered during previous run commands profile interval (CR-226) selects the frequency with which the profiler collects samples during a run command profile off (CR-227) disables runtime statistical performance and memory allocation profiling profile on (CR-228) enables runtime profiling of where your simulation is spending its time and where memory is allocated profile option (CR-229) allows various profiling options to be changed profile reload (CR-230) reads in raw profile data from an external file created during memory allocation profiling profile report (CR-231) produces a textual output of the profiling statistics that have been gathered up to this point project (CR-233) performs common operations on new projects property list (CR-234) changes one or more properties of the specified signal, net, or register in the List window (GR-153) property wave (CR-235) changes one or more properties of the specified signal, net, or register in the Wave window (GR-211) push (CR-237) moves one level down the C callstack pwd (CR-238) displays the current directory path in the Main window quietly (CR-239) turns off transcript echoing for the specified command quit (CR-240) exits the simulator radix (CR-241) specifies the default radix to be used ModelSim SE Command Reference CR-38 Command reference table Command name Action readers (CR-242) displays the names of all readers of the specified object record (CR-243) starts recording a replayable trace of all keyboard and mouse actions report (CR-244) displays the value of all simulator control variables, or the value of any simulator state variables relevant to the current simulation restart (CR-246) reloads the design elements and resets the simulation time to zero restore (CR-248) restores the state of a simulation that was saved with a checkpoint command (CR-93) during the current invocation of vsim resume (CR-249) resumes execution of a macro file after a pause command (CR-217) or a breakpoint right (CR-250) searches right (next) for signal transitions or values in the specified Wave window run (CR-252) advances the simulation by the specified number of timesteps sccom (CR-254) compiles SystemC design units scgenmod (CR-258) creates a VHDL entity’s or Verilog module’s equivalent SystemC foreign module declaration, writing it to standard output search (CR-260) searches the specified window for one or more objects matching the specified pattern(s) searchlog (CR-262) searches one or more of the currently open logfiles for a specified condition seetime (CR-264) scrolls the List or Wave window to make the specified time visible setenv (CR-265) sets an environment variable shift (CR-266) shifts macro parameter values down one place show (CR-267) lists objects and subregions visible from the current environment simstats (CR-268) reports performance-related statistics about active simulations splitio (CR-270) operates on a VHDL inout or out port to create a new signal having the same name as the port suffixed with “__o” status (CR-271) lists all currently interrupted macros step (CR-272) steps to the next HDL statement stop (CR-273) stops simulation in batch files; used with the when command (CR-407) tb (CR-274) displays a stack trace for the current process in the Transcript pane tcheck_set (CR-275) modifies a timing check’s reporting or X generation status tcheck_status (CR-277) prints the current status of timing checks to the Transcript pane toggle add (CR-279) enables collection of toggle statistics for the specified nodes ModelSim SE Command Reference Command reference table CR-39 Command name Action toggle disable (CR-281) disables collection of toggle statistics for the specified nodes toggle enable (CR-282) re-enables collection of toggle statistics for the specified nodes toggle report (CR-283) displays to the Transcript pane a list of all nodes that have not transitioned to both 0 and 1 at least once toggle reset (CR-284) resets the toggle counts to zero for the specified nodes transcribe (CR-285) displays a command in the Transcript pane, then executes the command transcript (CR-286) controls echoing of commands executed in a macro file; also works at top level in batch mode transcript file (CR-287) sets or queries the pathname for the transcript file tssi2mti (CR-288) converts a vector file in Fluence Technology (formerly TSSI) Standard Events Format into a sequence of force (CR-180) and run (CR-252) commands unsetenv (CR-289) deletes an environment variable up (CR-290) searches for signal transitions or values in the specified List window vcd add (CR-292) adds the specified objects to the VCD file vcd checkpoint (CR-293) dumps the current values of all VCD variables to the VCD file vcd comment (CR-294) inserts the specified comment in the VCD file vcd dumpports (CR-295) creates a VCD file that captures port driver data vcd dumpportsall (CR-297) creates a checkpoint in the VCD file that shows the current values of all selected ports vcd dumpportsflush (CR-298) flushes the VCD buffer to the VCD file vcd dumpportslimit (CR-299) specifies the maximum size of the VCD file vcd dumpportsoff (CR-300) turns off VCD dumping and records all dumped port values as x vcd dumpportson (CR-301) turns on VCD dumping and records the current values of all selected ports vcd file (CR-302) specifies the filename and state mapping for the VCD file created by a vcd add command (CR-292) vcd files (CR-304) specifies the filename and state mapping for the VCD file created by a vcd add command (CR-292); supports multiple VCD files vcd flush (CR-306) flushes the contents of the VCD file buffer to the VCD file vcd limit (CR-307) specifies the maximum size of the VCD file vcd off (CR-308) turns off VCD dumping and records all VCD variable values as x vcd on (CR-309) turns on VCD dumping and records the current values of all VCD variables vcd2wlf (CR-310) translates VCD files into WLF files ModelSim SE Command Reference CR-40 Command reference table Command name Action vcom (CR-311) compiles VHDL design units vcover convert (CR-319) converts a 5.7 coverage file to a 5.8 format vcover merge (CR-320) merges multiple code or functional coverage data files offline vcover report (CR-322) reports on multiple code or functional coverage data files offline vcover stats (CR-325) produces summary statistics from multiple coverage data files vdel (CR-327) deletes a design unit from a specified library vdir (CR-328) lists the contents of a design library verror (CR-329) prints a detailed description of a message number vgencomp (CR-330) writes a Verilog module’s equivalent VHDL component declaration to standard output view (CR-332) opens a ModelSim window and brings it to the front of the display virtual count (CR-334) counts the number of currently defined virtuals that were not read in using a macro file virtual define (CR-335) prints the definition of a virtual signal or function in the form of a command that can be used to re-create the object virtual delete (CR-336) removes the matching virtuals virtual describe (CR-337) prints a complete description of the data type of one or more virtual signals virtual expand (CR-338) produces a list of all the non-virtual objects contained in the virtual signal(s) virtual function (CR-339) creates a new signal that consists of logical operations on existing signals and simulation time virtual hide (CR-342) causes the specified real or virtual signals to not be displayed in the Objects window virtual log (CR-343) causes the sim-mode dependent signals of the specified virtual signals to be logged by the simulator virtual nohide (CR-345) redisplays a virtual previously hidden with virtual hide virtual nolog (CR-346) stops the logging of the specified virtual signals virtual region (CR-348) creates a new user-defined design hierarchy region virtual save (CR-349) saves the definitions of virtuals to a file virtual show (CR-350) lists the full path names of all the virtuals explicitly defined virtual signal (CR-351) creates a new signal that consists of concatenations of signals and subelements virtual type (CR-354) creates a new enumerated type ModelSim SE Command Reference Command reference table CR-41 Command name Action vlib (CR-356) creates a design library vlog (CR-358) compiles Verilog design units vmake (CR-369) creates a makefile that can be used to reconstruct the specified library vmap (CR-370) defines a mapping between a logical library name and a directory vopt (CR-371) produces an optimized version of your design vsim (CR-373) loads a new design into the simulator vsim (CR-392) returns information about the current vsim executable vsource (CR-393) specifies an alternative file to use for the current source file wave (CR-394) commands for manipulating cursors, for zooming, and for adjusting the wave display view in the Wave window wave create (CR-397) creates an editable waveform that can be used to create stimulus and drive simulation wave edit (CR-400) edits a created waveform wave export (CR-403) exports created waveforms to a stimulus file wave import (CR-404) imports an EVCD file previously created with a wave export command wave modify (CR-405) modifies the parameters of a created waveform when (CR-407) instructs ModelSim to perform actions when the specified conditions are met where (CR-412) displays information about the system environment wlf2log (CR-413) translates a ModelSim WLF file to a QuickSim II logfile wlf2vcd (CR-415) translates a ModelSim WLF file to a VCD file wlfman (CR-416) outputs information about or a new WLF file from an existing WLF file wlfrecover (CR-420) attempts to repair an incomplete WLF file write cell_report (CR-421) creates a report of cell instances in the design that are optimized write format (CR-422) records the names and display options in a file of the objects currently being displayed in the List or Wave window write list (CR-424) records the contents of the most recently opened or specified List window in a list output file write preferences (CR-425) saves the current GUI preference settings to a Tcl preference file write report (CR-426) prints a summary of the design being simulated write transcript (CR-428) writes the contents of the Main window transcript to the specified file ModelSim SE Command Reference CR-42 Command reference table Command name Action write tssi (CR-429) records the contents of the default or specified List window in a “TSSI format” file write wave (CR-431) records the contents of the most currently opened or specified Wave window in PostScript format ModelSim SE Command Reference .main clear CR-43 .main clear The .main clear command clears the Transcript pane. The behavior is the same as selecting Edit > Clear when the Transcript pane is active. Syntax .main clear Arguments None. See also Main window (GR-14) ModelSim SE Command Reference CR-44 abort abort The abort command halts the execution of a macro file interrupted by a breakpoint or error. When macros are nested, you may choose to abort the last macro only, abort a specified number of nesting levels, or abort all macros. The abort command may be used within a macro to return early. Syntax abort [ | all] Arguments | all An integer giving the number of nested macro levels to abort; all aborts all levels. Optional. Default is 1. See also onbreak (CR-214), onElabError (CR-215), onerror (CR-216) ModelSim SE Command Reference add button CR-45 add button The add button command adds a user-defined button to the Main window button bar. New buttons are added to the right end of the bar. You can also add buttons via the GUI (see "Customize Toolbar dialog" (GR-106)). Returns the path name of the button widget created. Syntax add button [Disable | NoDisable] [{