SPARCV9 Manual
User Manual:
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- The SPARC Architecture Manual
- Contents
- Table 1— Double- and Quadwords in Memory & Registers
- Table 2— Signed Integer, Unsigned Integer, and Tagged Format Ranges
- Table 3— Floating-Point Single-Precision Format Definition
- Table 4— Floating-Point Double-Precision Format Definition
- Table 5— Floating-Point Quad-Precision Format Definition
- Table 6— Window Addressing
- Table 7— Floating-Point Register Number Encoding
- Table 8— Floating-Point Condition Codes (fccn) Fields of FSR
- Table 9— Rounding Direction (RD) Field of FSR
- Table 10— Floating-Point Trap Type (ftt) Field of FSR
- Table 11— Allowed Accesses to ASIs
- Table 12— Address Space Identifiers (ASIs)
- Table 13— Control Transfer Characteristics
- Table 14— Exception and Interrupt Requests, Sorted by TT Value
- Table 15— Exception and Interrupt Requests, Sorted by Priority (0 = Highest; 31 = Lowest)
- Table 16— Trap Received While in execute_state
- Table 17— Trap Received While in RED_state
- Table 18— Reset Received While in error_state
- Table 19— Ordering Relationships Selected by Mask
- Table 20— Sequencing Barrier Selected by Mask
- Table 21— Opcode Superscripts
- Table 22— Instruction Set
- Table 23— UDIV / UDIVcc Overflow Detection and Value Returned
- Table 24— SDIV / SDIVcc Overflow Detection and Value Returned
- Table 25— MEMBAR mmask Encodings
- Table 26— MEMBAR cmask Encodings
- Table 27— Untrapped Floating-Point Results
- Table 28— Untrapped Floating-Point Underflow
- Table 29— Implementation Dependencies
- Table 30— op[1:0]
- Table 31— op2[2:0](op=0)
- Table 32— op3[5:0](op=2)
- Table 33— op3[5:0](op=3)
- Table 34— opf[8:0](op=2,op3=3416=FPop1)
- Table 35— Context Used for Data Access
- Table 36— Context Used for Instruction Access
- Table 37— Mapping Synthetic to SPARC-V9 Instructions
- Table 38— Register Allocation within a Window
- Table 39— Prefetch Cost Tradeoffs
- Table 40— Cache Break-Even Points