STM32F0x1/STM32F0x2/STM32F0x8 Advanced ARM® Based 32 Bit MCUs Stm32f0x2 Reference Manual
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- 1 Documentation conventions
- 2 System and memory overview
- 3 Embedded Flash memory
- 3.1 Flash main features
- 3.2 Flash memory functional description
- 3.3 Memory protection
- 3.4 Flash interrupts
- 3.5 Flash register description
- 3.5.1 Flash access control register (FLASH_ACR)
- 3.5.2 Flash key register (FLASH_KEYR)
- 3.5.3 Flash option key register (FLASH_OPTKEYR)
- 3.5.4 Flash status register (FLASH_SR)
- 3.5.5 Flash control register (FLASH_CR)
- 3.5.6 Flash address register (FLASH_AR)
- 3.5.7 Flash Option byte register (FLASH_OBR)
- 3.5.8 Write protection register (FLASH_WRPR)
- 3.5.9 Flash register map
- 4 Option byte
- 5 Power control (PWR)
- 6 Reset and clock control (RCC)
- 6.1 Reset
- 6.2 Clocks
- Figure 10. Clock tree (STM32F03x and STM32F05x devices)
- Figure 11. Clock tree (STM32F04x, STM32F07x and STM32F09x devices)
- 6.2.1 HSE clock
- 6.2.2 HSI clock
- 6.2.3 HSI48 clock
- 6.2.4 PLL
- 6.2.5 LSE clock
- 6.2.6 LSI clock
- 6.2.7 System clock (SYSCLK) selection
- 6.2.8 Clock security system (CSS)
- 6.2.9 ADC clock
- 6.2.10 RTC clock
- 6.2.11 Independent watchdog clock
- 6.2.12 Clock-out capability
- 6.2.13 Internal/external clock measurement with TIM14
- 6.3 Low-power modes
- 6.4 RCC registers
- 6.4.1 Clock control register (RCC_CR)
- 6.4.2 Clock configuration register (RCC_CFGR)
- 6.4.3 Clock interrupt register (RCC_CIR)
- 6.4.4 APB peripheral reset register 2 (RCC_APB2RSTR)
- 6.4.5 APB peripheral reset register 1 (RCC_APB1RSTR)
- 6.4.6 AHB peripheral clock enable register (RCC_AHBENR)
- 6.4.7 APB peripheral clock enable register 2 (RCC_APB2ENR)
- 6.4.8 APB peripheral clock enable register 1 (RCC_APB1ENR)
- 6.4.9 RTC domain control register (RCC_BDCR)
- 6.4.10 Control/status register (RCC_CSR)
- 6.4.11 AHB peripheral reset register (RCC_AHBRSTR)
- 6.4.12 Clock configuration register 2 (RCC_CFGR2)
- 6.4.13 Clock configuration register 3 (RCC_CFGR3)
- 6.4.14 Clock control register 2 (RCC_CR2)
- 6.4.15 RCC register map
- 7 Clock recovery system (CRS)
- 8 General-purpose I/Os (GPIO)
- 8.1 Introduction
- 8.2 GPIO main features
- 8.3 GPIO functional description
- Table 23. Port bit configuration table (continued)
- 8.3.1 General-purpose I/O (GPIO)
- 8.3.2 I/O pin alternate function multiplexer and mapping
- 8.3.3 I/O port control registers
- 8.3.4 I/O port data registers
- 8.3.5 I/O data bitwise handling
- 8.3.6 GPIO locking mechanism
- 8.3.7 I/O alternate function input/output
- 8.3.8 External interrupt/wakeup lines
- 8.3.9 Input configuration
- 8.3.10 Output configuration
- 8.3.11 Alternate function configuration
- 8.3.12 Analog configuration
- 8.3.13 Using the HSE or LSE oscillator pins as GPIOs
- 8.3.14 Using the GPIO pins in the RTC supply domain
- 8.4 GPIO registers
- 8.4.1 GPIO port mode register (GPIOx_MODER) (x =A..F)
- 8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..F)
- 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..F)
- 8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..F)
- 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A..F)
- 8.4.6 GPIO port output data register (GPIOx_ODR) (x = A..F)
- 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..F)
- 8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..B)
- 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..F)
- 8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..F)
- 8.4.11 GPIO port bit reset register (GPIOx_BRR) (x =A..F)
- 8.4.12 GPIO register map
- 9 System configuration controller (SYSCFG)
- 9.1 SYSCFG registers
- 9.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1)
- 9.1.2 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)
- 9.1.3 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)
- 9.1.4 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)
- 9.1.5 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)
- 9.1.6 SYSCFG configuration register 2 (SYSCFG_CFGR2)
- 9.1.7 SYSCFG interrupt line 0 status register (SYSCFG_ITLINE0)
- 9.1.8 SYSCFG interrupt line 1 status register (SYSCFG_ITLINE1)
- 9.1.9 SYSCFG interrupt line 2 status register (SYSCFG_ITLINE2)
- 9.1.10 SYSCFG interrupt line 3 status register (SYSCFG_ITLINE3)
- 9.1.11 SYSCFG interrupt line 4 status register (SYSCFG_ITLINE4)
- 9.1.12 SYSCFG interrupt line 5 status register (SYSCFG_ITLINE5)
- 9.1.13 SYSCFG interrupt line 6 status register (SYSCFG_ITLINE6)
- 9.1.14 SYSCFG interrupt line 7 status register (SYSCFG_ITLINE7)
- 9.1.15 SYSCFG interrupt line 8 status register (SYSCFG_ITLINE8)
- 9.1.16 SYSCFG interrupt line 9 status register (SYSCFG_ITLINE9)
- 9.1.17 SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10)
- 9.1.18 SYSCFG interrupt line 11 status register (SYSCFG_ITLINE11)
- 9.1.19 SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12)
- 9.1.20 SYSCFG interrupt line 13 status register (SYSCFG_ITLINE13)
- 9.1.21 SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14)
- 9.1.22 SYSCFG interrupt line 15 status register (SYSCFG_ITLINE15)
- 9.1.23 SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16)
- 9.1.24 SYSCFG interrupt line 17 status register (SYSCFG_ITLINE17)
- 9.1.25 SYSCFG interrupt line 18 status register (SYSCFG_ITLINE18)
- 9.1.26 SYSCFG interrupt line 19 status register (SYSCFG_ITLINE19)
- 9.1.27 SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20)
- 9.1.28 SYSCFG interrupt line 21 status register (SYSCFG_ITLINE21)
- 9.1.29 SYSCFG interrupt line 22 status register (SYSCFG_ITLINE22)
- 9.1.30 SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23)
- 9.1.31 SYSCFG interrupt line 24 status register (SYSCFG_ITLINE24)
- 9.1.32 SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25)
- 9.1.33 SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26)
- 9.1.34 SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27)
- 9.1.35 SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28)
- 9.1.36 SYSCFG interrupt line 29 status register (SYSCFG_ITLINE29)
- 9.1.37 SYSCFG interrupt line 30 status register (SYSCFG_ITLINE30)
- 9.1.38 SYSCFG register maps
- 9.1 SYSCFG registers
- 10 Direct memory access controller (DMA)
- 10.1 Introduction
- 10.2 DMA main features
- 10.3 DMA functional description
- 10.3.1 DMA transactions
- 10.3.2 Arbiter
- 10.3.3 DMA channels
- 10.3.4 Programmable data width, data alignment and endians
- 10.3.5 Error management
- 10.3.6 DMA interrupts
- Table 28. DMA interrupt requests
- DMA controller
- Table 29. Summary of the DMA requests for each channel on STM32F03x, STM32F04x and STM32F05x devices
- Table 30. Summary of the DMA requests for each channel on STM32F07x devices (continued)
- DMA1/DMA2 controllers on STM32F09x devices
- Table 31. Summary of the DMA1 requests for each channel on STM32F09x devices (continued)
- Table 32. Summary of the DMA2 requests for each channel on STM32F09x devices
- 10.4 DMA registers
- 10.4.1 DMA interrupt status register (DMA_ISR and DMA2_ISR)
- 10.4.2 DMA interrupt flag clear register (DMA_IFCR and DMA2_IFCR)
- 10.4.3 DMA channel x configuration register (DMA_CCRx and DMA2_CCRx) (x = 1..7 for DMA and x = 1..5 for DMA2, where x = channel number)
- 10.4.4 DMA channel x number of data register (DMA_CNDTRx and DMA2_CNDTRx) (x = 1..7 for DMA and x = 1..5 for DMA2, where x = channel number)
- 10.4.5 DMA channel x peripheral address register (DMA_CPARx and DMA2_CPARx) (x = 1..7 for DMA and x = 1..5 for DMA2, where x = channel number)
- 10.4.6 DMA channel x memory address register (DMA_CMARx and DMA2_CMARx) (x = 1..7 for DMA and x = 1..5 for DMA2, where x = channel number)
- 10.4.7 DMA channel selection register (DMA_CSELR and DMA2_CSELR)
- 10.4.8 DMA register map
- 11 Interrupts and events
- 11.1 Nested vectored interrupt controller (NVIC)
- 11.2 Extended interrupts and events controller (EXTI)
- 11.3 EXTI registers
- 12 Cyclic redundancy check calculation unit (CRC)
- 13 Analog-to-digital converter (ADC)
- 13.1 Introduction
- 13.2 ADC main features
- 13.3 ADC pins and internal signals
- 13.4 ADC functional description
- 13.4.1 Calibration (ADCAL)
- 13.4.2 ADC on-off control (ADEN, ADDIS, ADRDY)
- 13.4.3 ADC clock (CKMODE)
- 13.4.4 Configuring the ADC
- 13.4.5 Channel selection (CHSEL, SCANDIR)
- 13.4.6 Programmable sampling time (SMP)
- 13.4.7 Single conversion mode (CONT=0)
- 13.4.8 Continuous conversion mode (CONT=1)
- 13.4.9 Starting conversions (ADSTART)
- 13.4.10 Timings
- 13.4.11 Stopping an ongoing conversion (ADSTP)
- 13.5 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN)
- 13.6 Data management
- 13.7 Low-power features
- 13.8 Analog window watchdog (AWDEN, AWDSGL, AWDCH, AWD_HTR/LTR, AWD)
- 13.9 Temperature sensor and internal reference voltage
- 13.10 Battery voltage monitoring
- 13.11 ADC interrupts
- 13.12 ADC registers
- 13.12.1 ADC interrupt and status register (ADC_ISR)
- 13.12.2 ADC interrupt enable register (ADC_IER)
- 13.12.3 ADC control register (ADC_CR)
- 13.12.4 ADC configuration register 1 (ADC_CFGR1)
- 13.12.5 ADC configuration register 2 (ADC_CFGR2)
- 13.12.6 ADC sampling time register (ADC_SMPR)
- 13.12.7 ADC watchdog threshold register (ADC_TR)
- 13.12.8 ADC channel selection register (ADC_CHSELR)
- 13.12.9 ADC data register (ADC_DR)
- 13.12.10 ADC common configuration register (ADC_CCR)
- 13.12.11 ADC register map
- 14 Digital-to-analog converter (DAC)
- 14.1 Introduction
- 14.2 DAC main features
- 14.3 DAC output buffer enable
- 14.4 DAC channel enable
- 14.5 Single mode functional description
- 14.6 Dual-mode functional description (STM32F07x and STM32F09x devices)
- 14.7 Noise generation(STM32F07x and STM32F09x devices)
- 14.8 Triangle-wave generation (STM32F07x and STM32F09x devices)
- 14.9 DMA request
- 14.10 DAC registers
- 14.10.1 DAC control register (DAC_CR)
- 14.10.2 DAC software trigger register (DAC_SWTRIGR)
- 14.10.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)
- 14.10.4 DAC channel1 12-bit left-aligned data holding register (DAC_DHR12L1)
- 14.10.5 DAC channel1 8-bit right-aligned data holding register (DAC_DHR8R1)
- 14.10.6 DAC channel2 12-bit right-aligned data holding register (DAC_DHR12R2)
- 14.10.7 DAC channel2 12-bit left-aligned data holding register (DAC_DHR12L2)
- 14.10.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
- 14.10.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD)
- 14.10.10 Dual DAC 12-bit left-aligned data holding register (DAC_DHR12LD)
- 14.10.11 Dual DAC 8-bit right-aligned data holding register (DAC_DHR8RD)
- 14.10.12 DAC channel1 data output register (DAC_DOR1)
- 14.10.13 DAC channel2 data output register (DAC_DOR2)
- 14.10.14 DAC status register (DAC_SR)
- 14.10.15 DAC register map
- 15 Comparator (COMP)
- 16 Touch sensing controller (TSC)
- 16.1 Introduction
- 16.2 TSC main features
- 16.3 TSC functional description
- 16.3.1 TSC block diagram
- 16.3.2 Surface charge transfer acquisition overview
- 16.3.3 Reset and clocks
- 16.3.4 Charge transfer acquisition sequence
- 16.3.5 Spread spectrum feature
- 16.3.6 Max count error
- 16.3.7 Sampling capacitor I/O and channel I/O mode selection
- 16.3.8 Acquisition mode
- 16.3.9 I/O hysteresis and analog switch control
- 16.4 TSC low-power modes
- 16.5 TSC interrupts
- 16.6 TSC registers
- 16.6.1 TSC control register (TSC_CR)
- 16.6.2 TSC interrupt enable register (TSC_IER)
- 16.6.3 TSC interrupt clear register (TSC_ICR)
- 16.6.4 TSC interrupt status register (TSC_ISR)
- 16.6.5 TSC I/O hysteresis control register (TSC_IOHCR)
- 16.6.6 TSC I/O analog switch control register (TSC_IOASCR)
- 16.6.7 TSC I/O sampling control register (TSC_IOSCR)
- 16.6.8 TSC I/O channel control register (TSC_IOCCR)
- 16.6.9 TSC I/O group control status register (TSC_IOGCSR)
- 16.6.10 TSC I/O group x counter register (TSC_IOGxCR) (x = 1..8)
- 16.6.11 TSC register map
- 17 Advanced-control timers (TIM1)
- 17.1 TIM1 introduction
- 17.2 TIM1 main features
- 17.3 TIM1 functional description
- 17.3.1 Time-base unit
- 17.3.2 Counter modes
- Figure 62. Counter timing diagram, internal clock divided by 1
- Figure 63. Counter timing diagram, internal clock divided by 2
- Figure 64. Counter timing diagram, internal clock divided by 4
- Figure 65. Counter timing diagram, internal clock divided by N
- Figure 66. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 67. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- Figure 68. Counter timing diagram, internal clock divided by 1
- Figure 69. Counter timing diagram, internal clock divided by 2
- Figure 70. Counter timing diagram, internal clock divided by 4
- Figure 71. Counter timing diagram, internal clock divided by N
- Figure 72. Counter timing diagram, update event when repetition counter is not used
- Figure 73. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
- Figure 74. Counter timing diagram, internal clock divided by 2
- Figure 75. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
- Figure 76. Counter timing diagram, internal clock divided by N
- Figure 77. Counter timing diagram, update event with ARPE=1 (counter underflow)
- Figure 78. Counter timing diagram, Update event with ARPE=1 (counter overflow)
- 17.3.3 Repetition counter
- 17.3.4 Clock sources
- 17.3.5 Capture/compare channels
- 17.3.6 Input capture mode
- 17.3.7 PWM input mode
- 17.3.8 Forced output mode
- 17.3.9 Output compare mode
- 17.3.10 PWM mode
- 17.3.11 Complementary outputs and dead-time insertion
- 17.3.12 Using the break function
- 17.3.13 Clearing the OCxREF signal on an external event
- 17.3.14 6-step PWM generation
- 17.3.15 One-pulse mode
- 17.3.16 Encoder interface mode
- 17.3.17 Timer input XOR function
- 17.3.18 Interfacing with Hall sensors
- 17.3.19 TIMx and external trigger synchronization
- 17.3.20 Timer synchronization
- 17.3.21 Debug mode
- 17.4 TIM1 registers
- 17.4.1 TIM1 control register 1 (TIM1_CR1)
- 17.4.2 TIM1 control register 2 (TIM1_CR2)
- 17.4.3 TIM1 slave mode control register (TIM1_SMCR)
- 17.4.4 TIM1 DMA/interrupt enable register (TIM1_DIER)
- 17.4.5 TIM1 status register (TIM1_SR)
- 17.4.6 TIM1 event generation register (TIM1_EGR)
- 17.4.7 TIM1 capture/compare mode register 1 (TIM1_CCMR1)
- 17.4.8 TIM1 capture/compare mode register 2 (TIM1_CCMR2)
- 17.4.9 TIM1 capture/compare enable register (TIM1_CCER)
- 17.4.10 TIM1 counter (TIM1_CNT)
- 17.4.11 TIM1 prescaler (TIM1_PSC)
- 17.4.12 TIM1 auto-reload register (TIM1_ARR)
- 17.4.13 TIM1 repetition counter register (TIM1_RCR)
- 17.4.14 TIM1 capture/compare register 1 (TIM1_CCR1)
- 17.4.15 TIM1 capture/compare register 2 (TIM1_CCR2)
- 17.4.16 TIM1 capture/compare register 3 (TIM1_CCR3)
- 17.4.17 TIM1 capture/compare register 4 (TIM1_CCR4)
- 17.4.18 TIM1 break and dead-time register (TIM1_BDTR)
- 17.4.19 TIM1 DMA control register (TIM1_DCR)
- 17.4.20 TIM1 DMA address for full transfer (TIM1_DMAR)
- 17.4.21 TIM1 register map
- 18 General-purpose timers (TIM2 and TIM3)
- 18.1 TIM2 and TIM3 introduction
- 18.2 TIM2 and TIM3 main features
- 18.3 TIM2 and TIM3 functional description
- 18.3.1 Time-base unit
- 18.3.2 Counter modes
- Figure 110. Counter timing diagram, internal clock divided by 1
- Figure 111. Counter timing diagram, internal clock divided by 2
- Figure 112. Counter timing diagram, internal clock divided by 4
- Figure 113. Counter timing diagram, internal clock divided by N
- Figure 114. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 115. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded)
- Figure 116. Counter timing diagram, internal clock divided by 1
- Figure 117. Counter timing diagram, internal clock divided by 2
- Figure 118. Counter timing diagram, internal clock divided by 4
- Figure 119. Counter timing diagram, internal clock divided by N
- Figure 120. Counter timing diagram, Update event when repetition counter is not used
- Figure 121. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
- Figure 122. Counter timing diagram, internal clock divided by 2
- Figure 123. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
- Figure 124. Counter timing diagram, internal clock divided by N
- Figure 125. Counter timing diagram, Update event with ARPE=1 (counter underflow)
- Figure 126. Counter timing diagram, Update event with ARPE=1 (counter overflow)
- 18.3.3 Clock sources
- 18.3.4 Capture/compare channels
- 18.3.5 Input capture mode
- 18.3.6 PWM input mode
- 18.3.7 Forced output mode
- 18.3.8 Output compare mode
- 18.3.9 PWM mode
- 18.3.10 One-pulse mode
- 18.3.11 Clearing the OCxREF signal on an external event
- 18.3.12 Encoder interface mode
- 18.3.13 Timer input XOR function
- 18.3.14 Timers and external trigger synchronization
- 18.3.15 Timer synchronization
- Figure 147. Master/Slave timer example
- Figure 148. Gating timer 2 with OC1REF of timer 1
- Figure 149. Gating timer 2 with Enable of timer 1
- Figure 150. Triggering timer 2 with update of timer 1
- Figure 151. Triggering timer 2 with Enable of timer 1
- Figure 152. Triggering timer 1 and 2 with timer 1 TI1 input
- 18.3.16 Debug mode
- 18.4 TIM2 and TIM3 registers
- 18.4.1 TIM2 and TIM3 control register 1 (TIM2_CR1 and TIM3_CR1)
- 18.4.2 TIM2 and TIM3 control register 2 (TIM2_CR2 and TIM3_CR2)
- 18.4.3 TIM2 and TIM3 slave mode control register (TIM2_SMCR and TIM3_SMCR)
- 18.4.4 TIM2 and TIM3 DMA/Interrupt enable register (TIM2_DIER and TIM3_DIER)
- 18.4.5 TIM2 and TIM3 status register (TIM2_SR and TIM3_SR)
- 18.4.6 TIM2 and TIM3 event generation register (TIM2_EGR and TIM3_EGR)
- 18.4.7 TIM2 and TIM3 capture/compare mode register 1 (TIM2_CCMR1 and TIM3_CCMR1)
- 18.4.8 TIM2 and TIM3 capture/compare mode register 2 (TIM2_CCMR2 and TIM3_CCMR2)
- 18.4.9 TIM2 and TIM3 capture/compare enable register (TIM2_CCER and TIM3_CCER)
- 18.4.10 TIM2 and TIM3 counter (TIM2_CNT and TIM3_CNT)
- 18.4.11 TIM2 and TIM3 prescaler (TIM2_PSC and TIM3_PSC)
- 18.4.12 TIM2 and TIM3 auto-reload register (TIM2_ARR and TIM3_ARR)
- 18.4.13 TIM2 and TIM3 capture/compare register 1 (TIM2_CCR1 and TIM3_CCR1)
- 18.4.14 TIM2 and TIM3 capture/compare register 2 (TIM2_CCR2 and TIM3_CCR2)
- 18.4.15 TIM2 and TIM3 capture/compare register 3 (TIM2_CCR3 and TIM3_CCR3)
- 18.4.16 TIM2 and TIM3 capture/compare register 4 (TIM2_CCR4 and TIM3_CCR4)
- 18.4.17 TIM2 and TIM3 DMA control register (TIM2_DCR and TIM3_DCR)
- 18.4.18 TIM2 and TIM3 DMA address for full transfer (TIM2_DMAR and TIM3_DMAR)
- 18.4.19 TIM2 and TIM3 register map
- 19 General-purpose timer (TIM14)
- 19.1 TIM14 introduction
- 19.2 TIM14 main features
- 19.3 TIM14 functional description
- 19.3.1 Time-base unit
- 19.3.2 Counter modes
- Figure 156. Counter timing diagram, internal clock divided by 1
- Figure 157. Counter timing diagram, internal clock divided by 2
- Figure 158. Counter timing diagram, internal clock divided by 4
- Figure 159. Counter timing diagram, internal clock divided by N
- Figure 160. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 161. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 19.3.3 Clock source
- 19.3.4 Capture/compare channels
- 19.3.5 Input capture mode
- 19.3.6 Forced output mode
- 19.3.7 Output compare mode
- 19.3.8 PWM mode
- 19.3.9 Debug mode
- 19.4 TIM14 registers
- 19.4.1 TIM14 control register 1 (TIM14_CR1)
- 19.4.2 TIM14 interrupt enable register (TIM14_DIER)
- 19.4.3 TIM14 status register (TIM14_SR)
- 19.4.4 TIM14 event generation register (TIM14_EGR)
- 19.4.5 TIM14 capture/compare mode register 1 (TIM14_CCMR1)
- 19.4.6 TIM14 capture/compare enable register (TIM14_CCER)
- 19.4.7 TIM14 counter (TIM14_CNT)
- 19.4.8 TIM14 prescaler (TIM14_PSC)
- 19.4.9 TIM14 auto-reload register (TIM14_ARR)
- 19.4.10 TIM14 capture/compare register 1 (TIM14_CCR1)
- 19.4.11 TIM14 option register (TIM14_OR)
- 19.4.12 TIM14 register map
- 20 General-purpose timers (TIM15/16/17)
- 20.1 TIM15/16/17 introduction
- 20.2 TIM15 main features
- 20.3 TIM16 and TIM17 main features
- 20.4 TIM15/16/17 functional description
- 20.4.1 Time-base unit
- 20.4.2 Counter modes
- Figure 172. Counter timing diagram, internal clock divided by 1
- Figure 173. Counter timing diagram, internal clock divided by 2
- Figure 174. Counter timing diagram, internal clock divided by 4
- Figure 175. Counter timing diagram, internal clock divided by N
- Figure 176. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 177. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 20.4.3 Repetition counter
- 20.4.4 Clock sources
- 20.4.5 Capture/compare channels
- 20.4.6 Input capture mode
- 20.4.7 PWM input mode (only for TIM15)
- 20.4.8 Forced output mode
- 20.4.9 Output compare mode
- 20.4.10 PWM mode
- 20.4.11 Complementary outputs and dead-time insertion
- 20.4.12 Using the break function
- 20.4.13 One-pulse mode
- 20.4.14 TIM15 external trigger synchronization
- 20.4.15 Timer synchronization (TIM15)
- 20.4.16 Debug mode
- 20.5 TIM15 registers
- 20.5.1 TIM15 control register 1 (TIM15_CR1)
- 20.5.2 TIM15 control register 2 (TIM15_CR2)
- 20.5.3 TIM15 slave mode control register (TIM15_SMCR)
- 20.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER)
- 20.5.5 TIM15 status register (TIM15_SR)
- 20.5.6 TIM15 event generation register (TIM15_EGR)
- 20.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1)
- 20.5.8 TIM15 capture/compare enable register (TIM15_CCER)
- 20.5.9 TIM15 counter (TIM15_CNT)
- 20.5.10 TIM15 prescaler (TIM15_PSC)
- 20.5.11 TIM15 auto-reload register (TIM15_ARR)
- 20.5.12 TIM15 repetition counter register (TIM15_RCR)
- 20.5.13 TIM15 capture/compare register 1 (TIM15_CCR1)
- 20.5.14 TIM15 capture/compare register 2 (TIM15_CCR2)
- 20.5.15 TIM15 break and dead-time register (TIM15_BDTR)
- 20.5.16 TIM15 DMA control register (TIM15_DCR)
- 20.5.17 TIM15 DMA address for full transfer (TIM15_DMAR)
- 20.5.18 TIM15 register map
- 20.6 TIM16 and TIM17 registers
- 20.6.1 TIM16 and TIM17 control register 1 (TIM16_CR1 and TIM17_CR1)
- 20.6.2 TIM16 and TIM17 control register 2 (TIM16_CR2 and TIM17_CR2)
- 20.6.3 TIM16 and TIM17 DMA/interrupt enable register (TIM16_DIER and TIM17_DIER)
- 20.6.4 TIM16 and TIM17 status register (TIM16_SR and TIM17_SR)
- 20.6.5 TIM16 and TIM17 event generation register (TIM16_EGR and TIM17_EGR)
- 20.6.6 TIM16 and TIM17 capture/compare mode register 1 (TIM16_CCMR1 and TIM17_CCMR1)
- 20.6.7 TIM16 and TIM17 capture/compare enable register (TIM16_CCER and TIM17_CCER)
- 20.6.8 TIM16 and TIM17 counter (TIM16_CNT and TIM17_CNT)
- 20.6.9 TIM16 and TIM17 prescaler (TIM16_PSC and TIM17_PSC)
- 20.6.10 TIM16 and TIM17 auto-reload register (TIM16_ARR and TIM17_ARR)
- 20.6.11 TIM16 and TIM17 repetition counter register (TIM16_RCR and TIM17_RCR)
- 20.6.12 TIM16 and TIM17 capture/compare register 1 (TIM16_CCR1 and TIM17_CCR1)
- 20.6.13 TIM16 and TIM17 break and dead-time register (TIM16_BDTR and TIM17_BDTR)
- 20.6.14 TIM16 and TIM17 DMA control register (TIM16_DCR and TIM17_DCR)
- 20.6.15 TIM16 and TIM17 DMA address for full transfer (TIM16_DMAR and TIM17_DMAR)
- 20.6.16 TIM16 and TIM17 register map
- 21 Basic timer (TIM6/TIM7)
- 21.1 TIM6/TIM7 introduction
- 21.2 TIM6/TIM7 main features
- 21.3 TIM6/TIM7 functional description
- 21.3.1 Time-base unit
- 21.3.2 Counter modes
- Figure 200. Counter timing diagram, internal clock divided by 1
- Figure 201. Counter timing diagram, internal clock divided by 2
- Figure 202. Counter timing diagram, internal clock divided by 4
- Figure 203. Counter timing diagram, internal clock divided by N
- Figure 204. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded)
- Figure 205. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 21.3.3 Clock source
- 21.3.4 Debug mode
- 21.4 TIM6/TIM7 registers
- 21.4.1 TIM6/TIM7 control register 1 (TIMx_CR1)
- 21.4.2 TIM6/TIM7 control register 2 (TIMx_CR2)
- 21.4.3 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER)
- 21.4.4 TIM6/TIM7 status register (TIMx_SR)
- 21.4.5 TIM6/TIM7 event generation register (TIMx_EGR)
- 21.4.6 TIM6/TIM7 counter (TIMx_CNT)
- 21.4.7 TIM6/TIM7 prescaler (TIMx_PSC)
- 21.4.8 TIM6/TIM7 auto-reload register (TIMx_ARR)
- 21.4.9 TIM6/TIM7 register map
- 22 Infrared interface (IRTIM)
- 23 Independent watchdog (IWDG)
- 24 System window watchdog (WWDG)
- 25 Real-time clock (RTC)
- 25.1 Introduction
- 25.2 RTC main features
- 25.3 RTC implementation
- 25.4 RTC functional description
- 25.4.1 RTC block diagram
- 25.4.2 GPIOs controlled by the RTC
- 25.4.3 Clock and prescalers
- 25.4.4 Real-time clock and calendar
- 25.4.5 Programmable alarm
- 25.4.6 Periodic auto-wakeup
- 25.4.7 RTC initialization and configuration
- 25.4.8 Reading the calendar
- 25.4.9 Resetting the RTC
- 25.4.10 RTC synchronization
- 25.4.11 RTC reference clock detection
- 25.4.12 RTC smooth digital calibration
- 25.4.13 Time-stamp function
- 25.4.14 Tamper detection
- 25.4.15 Calibration clock output
- 25.4.16 Alarm output
- 25.5 RTC low-power modes
- 25.6 RTC interrupts
- 25.7 RTC registers
- 25.7.1 RTC time register (RTC_TR)
- 25.7.2 RTC date register (RTC_DR)
- 25.7.3 RTC control register (RTC_CR)
- 25.7.4 RTC initialization and status register (RTC_ISR)
- 25.7.5 RTC prescaler register (RTC_PRER)
- 25.7.6 RTC wakeup timer register (RTC_WUTR)
- 25.7.7 RTC alarm A register (RTC_ALRMAR)
- 25.7.8 RTC write protection register (RTC_WPR)
- 25.7.9 RTC sub second register (RTC_SSR)
- 25.7.10 RTC shift control register (RTC_SHIFTR)
- 25.7.11 RTC timestamp time register (RTC_TSTR)
- 25.7.12 RTC timestamp date register (RTC_TSDR)
- 25.7.13 RTC time-stamp sub second register (RTC_TSSSR)
- 25.7.14 RTC calibration register (RTC_CALR)
- 25.7.15 RTC tamper and alternate function configuration register (RTC_TAFCR)
- 25.7.16 RTC alarm A sub second register (RTC_ALRMASSR)
- 25.7.17 RTC backup registers (RTC_BKPxR)
- 25.7.18 RTC register map
- 26 Inter-integrated circuit (I2C) interface
- 26.1 Introduction
- 26.2 I2C main features
- 26.3 I2C implementation
- 26.4 I2C functional description
- 26.4.1 I2C1 block diagram
- 26.4.2 I2C2 block diagram
- 26.4.3 I2C clock requirements
- 26.4.4 Mode selection
- 26.4.5 I2C initialization
- 26.4.6 Software reset
- 26.4.7 Data transfer
- 26.4.8 I2C slave mode
- 26.4.9 I2C master mode
- 26.4.10 I2C_TIMINGR register configuration examples
- 26.4.11 SMBus specific features
- 26.4.12 SMBus initialization
- 26.4.13 SMBus: I2C_TIMEOUTR register configuration examples
- 26.4.14 SMBus slave mode
- 26.4.15 Wakeup from Stop mode on address match
- 26.4.16 Error conditions
- 26.4.17 DMA requests
- 26.4.18 Debug mode
- 26.5 I2C low-power modes
- 26.6 I2C interrupts
- 26.7 I2C registers
- 26.7.1 Control register 1 (I2C_CR1)
- 26.7.2 Control register 2 (I2C_CR2)
- 26.7.3 Own address 1 register (I2C_OAR1)
- 26.7.4 Own address 2 register (I2C_OAR2)
- 26.7.5 Timing register (I2C_TIMINGR)
- 26.7.6 Timeout register (I2C_TIMEOUTR)
- 26.7.7 Interrupt and status register (I2C_ISR)
- 26.7.8 Interrupt clear register (I2C_ICR)
- 26.7.9 PEC register (I2C_PECR)
- 26.7.10 Receive data register (I2C_RXDR)
- 26.7.11 Transmit data register (I2C_TXDR)
- 26.7.12 I2C register map
- 27 Universal synchronous asynchronous receiver transmitter (USART)
- 27.1 Introduction
- 27.2 USART main features
- 27.3 USART extended features
- 27.4 USART implementation
- 27.5 USART functional description
- 27.5.1 USART character description
- 27.5.2 USART transmitter
- 27.5.3 USART receiver
- Start bit detection
- Character reception
- For code example refer to the Appendix section A.19.5: USART receive byte code example.Break character
- Idle character
- Overrun error
- Selecting the clock source and the proper oversampling method
- Table 103. Noise detection from sampled data
- Framing error
- Configurable stop bits during reception
- 27.5.4 USART baud rate generation
- 27.5.5 Tolerance of the USART receiver to clock deviation
- 27.5.6 USART auto baud rate detection
- 27.5.7 Multiprocessor communication using USART
- 27.5.8 Modbus communication using USART
- 27.5.9 USART parity control
- 27.5.10 USART LIN (local interconnection network) mode
- 27.5.11 USART synchronous mode
- 27.5.12 USART Single-wire Half-duplex communication
- 27.5.13 USART Smartcard mode
- 27.5.14 USART IrDA SIR ENDEC block
- 27.5.15 USART continuous communication in DMA mode
- 27.5.16 RS232 hardware flow control and RS485 driver enable using USART
- 27.5.17 Wakeup from Stop mode using USART
- 27.6 USART low-power modes
- 27.7 USART interrupts
- 27.8 USART registers
- 27.8.1 Control register 1 (USART_CR1)
- 27.8.2 Control register 2 (USART_CR2)
- 27.8.3 Control register 3 (USART_CR3)
- 27.8.4 Baud rate register (USART_BRR)
- 27.8.5 Guard time and prescaler register (USART_GTPR)
- 27.8.6 Receiver timeout register (USART_RTOR)
- 27.8.7 Request register (USART_RQR)
- 27.8.8 Interrupt and status register (USART_ISR)
- 27.8.9 Interrupt flag clear register (USART_ICR)
- 27.8.10 Receive data register (USART_RDR)
- 27.8.11 Transmit data register (USART_TDR)
- 27.8.12 USART register map
- 28 Serial peripheral interface / inter-IC sound (SPI/I2S)
- 28.1 Introduction
- 28.2 SPI main features
- 28.3 I2S main features
- 28.4 SPI/I2S implementation
- 28.5 SPI functional description
- 28.5.1 General description
- 28.5.2 Communications between one master and one slave
- 28.5.3 Standard multi-slave communication
- 28.5.4 Multi-master communication
- 28.5.5 Slave select (NSS) pin management
- 28.5.6 Communication formats
- 28.5.7 Configuration of SPI
- 28.5.8 Procedure for enabling SPI
- 28.5.9 Data transmission and reception procedures
- 28.5.10 SPI status flags
- 28.5.11 SPI error flags
- 28.5.12 NSS pulse mode
- 28.5.13 TI mode
- 28.5.14 CRC calculation
- 28.6 SPI interrupts
- 28.7 I2S functional description
- 28.8 I2S interrupts
- 28.9 SPI and I2S registers
- 28.9.1 SPI control register 1 (SPIx_CR1)
- 28.9.2 SPI control register 2 (SPIx_CR2)
- 28.9.3 SPI status register (SPIx_SR)
- 28.9.4 SPI data register (SPIx_DR)
- 28.9.5 SPI CRC polynomial register (SPIx_CRCPR)
- 28.9.6 SPI Rx CRC register (SPIx_RXCRCR)
- 28.9.7 SPI Tx CRC register (SPIx_TXCRCR)
- 28.9.8 SPIx_I2S configuration register (SPIx_I2SCFGR)
- 28.9.9 SPIx_I2S prescaler register (SPIx_I2SPR)
- 28.9.10 SPI/I2S register map
- 29 Controller area network (bxCAN)
- 29.1 Introduction
- 29.2 bxCAN main features
- 29.3 bxCAN general description
- 29.4 bxCAN operating modes
- 29.5 Test mode
- 29.6 Behavior in debug mode
- 29.7 bxCAN functional description
- 29.8 bxCAN interrupts
- 29.9 CAN registers
- 29.9.1 Register access protection
- 29.9.2 CAN control and status registers
- 29.9.3 CAN mailbox registers
- CAN TX mailbox identifier register (CAN_TIxR) (x = 0..2)
- CAN mailbox data length control and time stamp register (CAN_TDTxR) (x = 0..2)
- CAN mailbox data low register (CAN_TDLxR) (x = 0..2)
- CAN mailbox data high register (CAN_TDHxR) (x = 0..2)
- CAN receive FIFO mailbox identifier register (CAN_RIxR) (x = 0..1)
- CAN receive FIFO mailbox data length control and time stamp register (CAN_RDTxR) (x = 0..1)
- CAN receive FIFO mailbox data low register (CAN_RDLxR) (x = 0..1)
- CAN receive FIFO mailbox data high register (CAN_RDHxR) (x = 0..1)
- 29.9.4 CAN filter registers
- 29.9.5 bxCAN register map
- 30 Universal serial bus full-speed device interface (USB)
- 31 HDMI-CEC controller (HDMI-CEC)
- 32 Debug support (DBG)
- 32.1 Overview
- 32.2 Reference ARM documentation
- 32.3 Pinout and debug port pins
- 32.4 ID codes and locking mechanism
- 32.5 SWD port
- 32.6 Core debug
- 32.7 BPU (Break Point Unit)
- 32.8 DWT (Data Watchpoint)
- 32.9 MCU debug component (DBGMCU)
- 33 Device electronic signature
- Appendix A Code examples
- A.1 Introduction
- A.2 Flash operation code example
- A.2.1 Flash memory unlocking sequence code
- A.2.2 Main Flash programming sequence code example
- A.2.3 Page erase sequence code example
- A.2.4 Mass erase sequence code example
- A.2.5 Option byte unlocking sequence code example
- A.2.6 Option byte programming sequence code example
- A.2.7 Option byte erasing sequence code example
- A.3 Clock controller
- A.4 GPIO
- A.5 DMA
- A.6 Interrupts and event
- A.7 ADC
- A.7.1 ADC Calibration code example
- A.7.2 ADC enable sequence code example
- A.7.3 ADC disable sequence code example
- A.7.4 ADC Clock selection code example
- A.7.5 Single conversion sequence code example - Software trigger
- A.7.6 Continuous conversion sequence code example - Software trigger
- A.7.7 Single conversion sequence code example - Hardware trigger
- A.7.8 Continuous conversion sequence code example - Hardware trigger
- A.7.9 DMA one shot mode sequence code example
- A.7.10 DMA circular mode sequence code example
- A.7.11 Wait mode sequence code example
- A.7.12 Auto Off and no wait mode sequence code example
- A.7.13 Auto Off and wait mode sequence code example
- A.7.14 Analog watchdog code example
- A.7.15 Temperature configuration code example
- A.7.16 Temperature computation code example
- A.8 DAC
- A.8.1 Independent trigger without wave generation code example
- A.8.2 Independent trigger with single LFSR generation code example
- A.8.3 Independent trigger with different LFSR generation code example
- A.8.4 Independent trigger with single triangle generation code example
- A.8.5 Independent trigger with different triangle generation code example
- A.8.6 Simultaneous software start code example
- A.8.7 Simultaneous trigger without wave generation code example
- A.8.8 Simultaneous trigger with single LFSR generation code example
- A.8.9 Simultaneous trigger with different LFSR generation code example
- A.8.10 Simultaneous trigger with single triangle generation code example
- A.8.11 Simultaneous trigger with different triangle generation code example
- A.8.12 DMA initialization code example
- A.9 Timers
- A.9.1 Upcounter on TI2 rising edge code example
- A.9.2 Up counter on each 2 ETR rising edges code example
- A.9.3 Input capture configuration code example
- A.9.4 Input capture data management code example
- A.9.5 PWM input configuration code example
- A.9.6 PWM input with DMA configuration code example
- A.9.7 Output compare configuration code example
- A.9.8 Edge-aligned PWM configuration example
- A.9.9 Center-aligned PWM configuration example
- A.9.10 ETR configuration to clear OCxREF code example
- A.9.11 Encoder interface code example
- A.9.12 Reset mode code example
- A.9.13 Gated mode code example
- A.9.14 Trigger mode code example
- A.9.15 External clock mode 2 + trigger mode code example
- A.9.16 One-Pulse mode code example
- A.9.17 Timer prescaling another timer code example
- A.9.18 Timer enabling another timer code example
- A.9.19 Master and slave synchronization code example
- A.9.20 Two timers synchronized by an external trigger code example
- A.9.21 DMA burst feature code example
- A.10 IRTIM code example
- A.11 bxCAN code example
- A.12 DBG code example
- A.13 HDMI-CEC code example
- A.14 I2C code example
- A.14.1 I2C configured in master mode to receive code example
- A.14.2 I2C configured in master mode to transmit code example
- A.14.3 I2C configured in slave mode code example
- A.14.4 I2C master transmitter code example
- A.14.5 I2C master receiver code example
- A.14.6 I2C slave transmitter code example
- A.14.7 I2C slave receiver code example
- A.14.8 I2C configured in master mode to transmit with DMA code example
- A.14.9 I2C configured in slave mode to receive with DMA code example
- A.15 IWDG code example
- A.16 RTC code example
- A.16.1 RTC calendar configuration code example
- A.16.2 RTC alarm configuration code example
- A.16.3 RTC WUT configuration code example
- A.16.4 RTC read calendar code example
- A.16.5 RTC calibration code example
- A.16.6 RTC tamper and time stamp configuration code example
- A.16.7 RTC tamper and time stamp code example
- A.16.8 RTC clock output code example
- A.17 SPI code example
- A.18 TSC code example
- A.19 USART code example
- A.19.1 USART transmitter configuration code example
- A.19.2 USART transmit byte code example
- A.19.3 USART transfer complete code example
- A.19.4 USART receiver configuration code example
- A.19.5 USART receive byte code example
- A.19.6 USART LIN mode code example
- A.19.7 USART synchronous mode code example
- A.19.8 USART single-wire half-duplex code example
- A.19.9 USART smartcard mode code example
- A.19.10 USART IrDA mode code example
- A.19.11 USART DMA code example
- A.19.12 USART hardware flow control code example
- A.20 WWDG code example
- Revision history