STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx And STM32F107xx Advanced Arm® Based 32 Bit MCUs Reference Manual Stm32f103
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STM32F1_ReferenceManual
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User Manual:
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Page Count: 1134 [warning: Documents this large are best viewed by clicking the View PDF Link!]
- 1 Overview of the manual
- 2 Documentation conventions
- 3 Memory and bus architecture
- 3.1 System architecture
- 3.2 Memory organization
- 3.3 Memory map
- Table 3. Register boundary addresses
- 3.3.1 Embedded SRAM
- 3.3.2 Bit banding
- 3.3.3 Embedded Flash memory
- Table 4. Flash module organization (low-density devices)
- Table 5. Flash module organization (medium-density devices)
- Table 6. Flash module organization (high-density devices)
- Table 7. Flash module organization (connectivity line devices)
- Table 8. XL-density Flash module organization
- Reading the Flash memory
- Programming and erasing the Flash memory
- Flash access control register (FLASH_ACR)
- 3.4 Boot configuration
- 4 CRC calculation unit
- 5 Power control (PWR)
- 6 Backup registers (BKP)
- 7 Low-, medium-, high- and XL-density reset and clock control (RCC)
- 7.1 Reset
- 7.2 Clocks
- 7.3 RCC registers
- 7.3.1 Clock control register (RCC_CR)
- 7.3.2 Clock configuration register (RCC_CFGR)
- 7.3.3 Clock interrupt register (RCC_CIR)
- 7.3.4 APB2 peripheral reset register (RCC_APB2RSTR)
- 7.3.5 APB1 peripheral reset register (RCC_APB1RSTR)
- 7.3.6 AHB peripheral clock enable register (RCC_AHBENR)
- 7.3.7 APB2 peripheral clock enable register (RCC_APB2ENR)
- 7.3.8 APB1 peripheral clock enable register (RCC_APB1ENR)
- 7.3.9 Backup domain control register (RCC_BDCR)
- 7.3.10 Control/status register (RCC_CSR)
- 7.3.11 RCC register map
- 8 Connectivity line devices: reset and clock control (RCC)
- 8.1 Reset
- 8.2 Clocks
- 8.3 RCC registers
- 8.3.1 Clock control register (RCC_CR)
- 8.3.2 Clock configuration register (RCC_CFGR)
- 8.3.3 Clock interrupt register (RCC_CIR)
- 8.3.4 APB2 peripheral reset register (RCC_APB2RSTR)
- 8.3.5 APB1 peripheral reset register (RCC_APB1RSTR)
- 8.3.6 AHB Peripheral Clock enable register (RCC_AHBENR)
- 8.3.7 APB2 peripheral clock enable register (RCC_APB2ENR)
- 8.3.8 APB1 peripheral clock enable register (RCC_APB1ENR)
- 8.3.9 Backup domain control register (RCC_BDCR)
- 8.3.10 Control/status register (RCC_CSR)
- 8.3.11 AHB peripheral clock reset register (RCC_AHBRSTR)
- 8.3.12 Clock configuration register2 (RCC_CFGR2)
- 8.3.13 RCC register map
- 9 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
- 9.1 GPIO functional description
- Table 20. Port bit configuration table
- Table 21. Output MODE bits
- 9.1.1 General-purpose I/O (GPIO)
- 9.1.2 Atomic bit set or reset
- 9.1.3 External interrupt/wakeup lines
- 9.1.4 Alternate functions (AF)
- 9.1.5 Software remapping of I/O alternate functions
- 9.1.6 GPIO locking mechanism
- 9.1.7 Input configuration
- 9.1.8 Output configuration
- 9.1.9 Alternate function configuration
- 9.1.10 Analog configuration
- 9.1.11 GPIO configurations for device peripherals
- 9.2 GPIO registers
- 9.2.1 Port configuration register low (GPIOx_CRL) (x=A..G)
- 9.2.2 Port configuration register high (GPIOx_CRH) (x=A..G)
- 9.2.3 Port input data register (GPIOx_IDR) (x=A..G)
- 9.2.4 Port output data register (GPIOx_ODR) (x=A..G)
- 9.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G)
- 9.2.6 Port bit reset register (GPIOx_BRR) (x=A..G)
- 9.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G)
- 9.3 Alternate function I/O and debug configuration (AFIO)
- 9.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15
- 9.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1
- 9.3.3 CAN1 alternate function remapping
- 9.3.4 CAN2 alternate function remapping
- 9.3.5 JTAG/SWD alternate function remapping
- 9.3.6 ADC alternate function remapping
- Table 38. ADC1 external trigger injected conversion alternate function remapping
- Table 39. ADC1 external trigger regular conversion alternate function remapping
- Table 40. ADC2 external trigger injected conversion alternate function remapping
- Table 41. ADC2 external trigger regular conversion alternate function remapping
- 9.3.7 Timer alternate function remapping
- Table 42. TIM5 alternate function remapping
- Table 43. TIM4 alternate function remapping
- Table 44. TIM3 alternate function remapping
- Table 45. TIM2 alternate function remapping
- Table 46. TIM1 alternate function remapping
- Table 47. TIM9 remapping
- Table 48. TIM10 remapping
- Table 49. TIM11 remapping
- Table 50. TIM13 remapping
- Table 51. TIM14 remapping
- 9.3.8 USART alternate function remapping
- 9.3.9 I2C1 alternate function remapping
- 9.3.10 SPI1 alternate function remapping
- 9.3.11 SPI3/I2S3 alternate function remapping
- 9.3.12 Ethernet alternate function remapping
- 9.4 AFIO registers
- 9.4.1 Event control register (AFIO_EVCR)
- 9.4.2 AF remap and debug I/O configuration register (AFIO_MAPR)
- 9.4.3 External interrupt configuration register 1 (AFIO_EXTICR1)
- 9.4.4 External interrupt configuration register 2 (AFIO_EXTICR2)
- 9.4.5 External interrupt configuration register 3 (AFIO_EXTICR3)
- 9.4.6 External interrupt configuration register 4 (AFIO_EXTICR4)
- 9.4.7 AF remap and debug I/O configuration register2 (AFIO_MAPR2)
- 9.5 GPIO and AFIO register maps
- 9.1 GPIO functional description
- 10 Interrupts and events
- 10.1 Nested vectored interrupt controller (NVIC)
- 10.2 External interrupt/event controller (EXTI)
- 10.3 EXTI registers
- 11 Analog-to-digital converter (ADC)
- 11.1 ADC introduction
- 11.2 ADC main features
- 11.3 ADC functional description
- 11.4 Calibration
- 11.5 Data alignment
- 11.6 Channel-by-channel programmable sample time
- 11.7 Conversion on external trigger
- 11.8 DMA request
- 11.9 Dual ADC mode
- 11.9.1 Injected simultaneous mode
- 11.9.2 Regular simultaneous mode
- 11.9.3 Fast interleaved mode
- 11.9.4 Slow interleaved mode
- 11.9.5 Alternate trigger mode
- 11.9.6 Independent mode
- 11.9.7 Combined regular/injected simultaneous mode
- 11.9.8 Combined regular simultaneous + alternate trigger mode
- 11.9.9 Combined injected simultaneous + interleaved
- 11.10 Temperature sensor
- 11.11 ADC interrupts
- 11.12 ADC registers
- 11.12.1 ADC status register (ADC_SR)
- 11.12.2 ADC control register 1 (ADC_CR1)
- 11.12.3 ADC control register 2 (ADC_CR2)
- 11.12.4 ADC sample time register 1 (ADC_SMPR1)
- 11.12.5 ADC sample time register 2 (ADC_SMPR2)
- 11.12.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)
- 11.12.7 ADC watchdog high threshold register (ADC_HTR)
- 11.12.8 ADC watchdog low threshold register (ADC_LTR)
- 11.12.9 ADC regular sequence register 1 (ADC_SQR1)
- 11.12.10 ADC regular sequence register 2 (ADC_SQR2)
- 11.12.11 ADC regular sequence register 3 (ADC_SQR3)
- 11.12.12 ADC injected sequence register (ADC_JSQR)
- 11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4)
- 11.12.14 ADC regular data register (ADC_DR)
- 11.12.15 ADC register map
- 12 Digital-to-analog converter (DAC)
- 12.1 DAC introduction
- 12.2 DAC main features
- 12.3 DAC functional description
- 12.4 Dual DAC channel conversion
- 12.4.1 Independent trigger without wave generation
- 12.4.2 Independent trigger with same LFSR generation
- 12.4.3 Independent trigger with different LFSR generation
- 12.4.4 Independent trigger with same triangle generation
- 12.4.5 Independent trigger with different triangle generation
- 12.4.6 Simultaneous software start
- 12.4.7 Simultaneous trigger without wave generation
- 12.4.8 Simultaneous trigger with same LFSR generation
- 12.4.9 Simultaneous trigger with different LFSR generation
- 12.4.10 Simultaneous trigger with same triangle generation
- 12.4.11 Simultaneous trigger with different triangle generation
- 12.5 DAC registers
- 12.5.1 DAC control register (DAC_CR)
- 12.5.2 DAC software trigger register (DAC_SWTRIGR)
- 12.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)
- 12.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
- 12.5.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
- 12.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
- 12.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
- 12.5.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
- 12.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD)
- 12.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD)
- 12.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD)
- 12.5.12 DAC channel1 data output register (DAC_DOR1)
- 12.5.13 DAC channel2 data output register (DAC_DOR2)
- 12.5.14 DAC register map
- 13 Direct memory access controller (DMA)
- 13.1 DMA introduction
- 13.2 DMA main features
- 13.3 DMA functional description
- 13.4 DMA registers
- 13.4.1 DMA interrupt status register (DMA_ISR)
- 13.4.2 DMA interrupt flag clear register (DMA_IFCR)
- 13.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7, where x = channel number)
- 13.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number)
- 13.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number)
- 13.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number)
- 13.4.7 DMA register map
- 14 Advanced-control timers (TIM1 and TIM8)
- 14.1 TIM1 and TIM8 introduction
- 14.2 TIM1 and TIM8 main features
- 14.3 TIM1 and TIM8 functional description
- 14.3.1 Time-base unit
- 14.3.2 Counter modes
- 14.3.3 Repetition counter
- 14.3.4 Clock selection
- 14.3.5 Capture/compare channels
- 14.3.6 Input capture mode
- 14.3.7 PWM input mode
- 14.3.8 Forced output mode
- 14.3.9 Output compare mode
- 14.3.10 PWM mode
- 14.3.11 Complementary outputs and dead-time insertion
- 14.3.12 Using the break function
- 14.3.13 Clearing the OCxREF signal on an external event
- 14.3.14 6-step PWM generation
- 14.3.15 One-pulse mode
- 14.3.16 Encoder interface mode
- 14.3.17 Timer input XOR function
- 14.3.18 Interfacing with Hall sensors
- 14.3.19 TIMx and external trigger synchronization
- 14.3.20 Timer synchronization
- 14.3.21 Debug mode
- 14.4 TIM1 and TIM8 registers
- 14.4.1 TIM1 and TIM8 control register 1 (TIMx_CR1)
- 14.4.2 TIM1 and TIM8 control register 2 (TIMx_CR2)
- 14.4.3 TIM1 and TIM8 slave mode control register (TIMx_SMCR)
- 14.4.4 TIM1 and TIM8 DMA/interrupt enable register (TIMx_DIER)
- 14.4.5 TIM1 and TIM8 status register (TIMx_SR)
- 14.4.6 TIM1 and TIM8 event generation register (TIMx_EGR)
- 14.4.7 TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1)
- 14.4.8 TIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2)
- 14.4.9 TIM1 and TIM8 capture/compare enable register (TIMx_CCER)
- 14.4.10 TIM1 and TIM8 counter (TIMx_CNT)
- 14.4.11 TIM1 and TIM8 prescaler (TIMx_PSC)
- 14.4.12 TIM1 and TIM8 auto-reload register (TIMx_ARR)
- 14.4.13 TIM1 and TIM8 repetition counter register (TIMx_RCR)
- 14.4.14 TIM1 and TIM8 capture/compare register 1 (TIMx_CCR1)
- 14.4.15 TIM1 and TIM8 capture/compare register 2 (TIMx_CCR2)
- 14.4.16 TIM1 and TIM8 capture/compare register 3 (TIMx_CCR3)
- 14.4.17 TIM1 and TIM8 capture/compare register 4 (TIMx_CCR4)
- 14.4.18 TIM1 and TIM8 break and dead-time register (TIMx_BDTR)
- 14.4.19 TIM1 and TIM8 DMA control register (TIMx_DCR)
- 14.4.20 TIM1 and TIM8 DMA address for full transfer (TIMx_DMAR)
- 14.4.21 TIM1 and TIM8 register map
- 15 General-purpose timers (TIM2 to TIM5)
- 15.1 TIM2 to TIM5 introduction
- 15.2 TIMx main features
- 15.3 TIMx functional description
- 15.3.1 Time-base unit
- 15.3.2 Counter modes
- 15.3.3 Clock selection
- 15.3.4 Capture/compare channels
- 15.3.5 Input capture mode
- 15.3.6 PWM input mode
- 15.3.7 Forced output mode
- 15.3.8 Output compare mode
- 15.3.9 PWM mode
- 15.3.10 One-pulse mode
- 15.3.11 Clearing the OCxREF signal on an external event
- 15.3.12 Encoder interface mode
- 15.3.13 Timer input XOR function
- 15.3.14 Timers and external trigger synchronization
- 15.3.15 Timer synchronization
- 15.3.16 Debug mode
- 15.4 TIMx registers
- 15.4.1 TIMx control register 1 (TIMx_CR1)
- 15.4.2 TIMx control register 2 (TIMx_CR2)
- 15.4.3 TIMx slave mode control register (TIMx_SMCR)
- 15.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)
- 15.4.5 TIMx status register (TIMx_SR)
- 15.4.6 TIMx event generation register (TIMx_EGR)
- 15.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)
- 15.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)
- 15.4.9 TIMx capture/compare enable register (TIMx_CCER)
- 15.4.10 TIMx counter (TIMx_CNT)
- 15.4.11 TIMx prescaler (TIMx_PSC)
- 15.4.12 TIMx auto-reload register (TIMx_ARR)
- 15.4.13 TIMx capture/compare register 1 (TIMx_CCR1)
- 15.4.14 TIMx capture/compare register 2 (TIMx_CCR2)
- 15.4.15 TIMx capture/compare register 3 (TIMx_CCR3)
- 15.4.16 TIMx capture/compare register 4 (TIMx_CCR4)
- 15.4.17 TIMx DMA control register (TIMx_DCR)
- 15.4.18 TIMx DMA address for full transfer (TIMx_DMAR)
- 15.4.19 TIMx register map
- 16 General-purpose timers (TIM9 to TIM14)
- 16.1 TIM9 to TIM14 introduction
- 16.2 TIM9 to TIM14 main features
- 16.3 TIM9 to TIM14 functional description
- 16.3.1 Time-base unit
- 16.3.2 Counter modes
- 16.3.3 Clock selection
- 16.3.4 Capture/compare channels
- 16.3.5 Input capture mode
- 16.3.6 PWM input mode (only for TIM9/12)
- 16.3.7 Forced output mode
- 16.3.8 Output compare mode
- 16.3.9 PWM mode
- 16.3.10 One-pulse mode
- 16.3.11 TIM9/12 external trigger synchronization
- 16.3.12 Timer synchronization (TIM9/12)
- 16.3.13 Debug mode
- 16.4 TIM9 and TIM12 registers
- 16.4.1 TIM9/12 control register 1 (TIMx_CR1)
- 16.4.2 TIM9/12 slave mode control register (TIMx_SMCR)
- 16.4.3 TIM9/12 Interrupt enable register (TIMx_DIER)
- 16.4.4 TIM9/12 status register (TIMx_SR)
- 16.4.5 TIM9/12 event generation register (TIMx_EGR)
- 16.4.6 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1)
- 16.4.7 TIM9/12 capture/compare enable register (TIMx_CCER)
- 16.4.8 TIM9/12 counter (TIMx_CNT)
- 16.4.9 TIM9/12 prescaler (TIMx_PSC)
- 16.4.10 TIM9/12 auto-reload register (TIMx_ARR)
- 16.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1)
- 16.4.12 TIM9/12 capture/compare register 2 (TIMx_CCR2)
- 16.4.13 TIM9/12 register map
- 16.5 TIM10/11/13/14 registers
- 16.5.1 TIM10/11/13/14 control register 1 (TIMx_CR1)
- 16.5.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER)
- 16.5.3 TIM10/11/13/14 status register (TIMx_SR)
- 16.5.4 TIM10/11/13/14 event generation register (TIMx_EGR)
- 16.5.5 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1)
- 16.5.6 TIM10/11/13/14 capture/compare enable register (TIMx_CCER)
- 16.5.7 TIM10/11/13/14 counter (TIMx_CNT)
- 16.5.8 TIM10/11/13/14 prescaler (TIMx_PSC)
- 16.5.9 TIM10/11/13/14 auto-reload register (TIMx_ARR)
- 16.5.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1)
- 16.5.11 TIM10/11/13/14 register map
- 17 Basic timers (TIM6 and TIM7)
- 17.1 TIM6 and TIM7 introduction
- 17.2 TIM6 and TIM7 main features
- 17.3 TIM6 and TIM7 functional description
- 17.4 TIM6 and TIM7 registers
- 17.4.1 TIM6 and TIM7 control register 1 (TIMx_CR1)
- 17.4.2 TIM6 and TIM7 control register 2 (TIMx_CR2)
- 17.4.3 TIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER)
- 17.4.4 TIM6 and TIM7 status register (TIMx_SR)
- 17.4.5 TIM6 and TIM7 event generation register (TIMx_EGR)
- 17.4.6 TIM6 and TIM7 counter (TIMx_CNT)
- 17.4.7 TIM6 and TIM7 prescaler (TIMx_PSC)
- 17.4.8 TIM6 and TIM7 auto-reload register (TIMx_ARR)
- 17.4.9 TIM6 and TIM7 register map
- 18 Real-time clock (RTC)
- 18.1 RTC introduction
- 18.2 RTC main features
- 18.3 RTC functional description
- 18.4 RTC registers
- 18.4.1 RTC control register high (RTC_CRH)
- 18.4.2 RTC control register low (RTC_CRL)
- 18.4.3 RTC prescaler load register (RTC_PRLH / RTC_PRLL)
- 18.4.4 RTC prescaler divider register (RTC_DIVH / RTC_DIVL)
- 18.4.5 RTC counter register (RTC_CNTH / RTC_CNTL)
- 18.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL)
- 18.4.7 RTC register map
- 19 Independent watchdog (IWDG)
- 20 Window watchdog (WWDG)
- 21 Flexible static memory controller (FSMC)
- 21.1 FSMC main features
- 21.2 Block diagram
- 21.3 AHB interface
- 21.4 External device address mapping
- 21.5 NOR Flash/PSRAM controller
- Table 104. Programmable NOR/PSRAM access parameters
- 21.5.1 External memory interface signals
- 21.5.2 Supported memories and transactions
- 21.5.3 General timing rules
- 21.5.4 NOR Flash/PSRAM controller asynchronous transactions
- Asynchronous static memories (NOR Flash memory, PSRAM, SRAM)
- Mode 1 - SRAM/PSRAM (CRAM)
- Mode A - SRAM/PSRAM (CRAM) OE toggling
- Mode 2/B - NOR Flash
- Mode C - NOR Flash - OE toggling
- Mode D - asynchronous access with extended address
- Muxed mode - multiplexed asynchronous access to NOR Flash memory
- WAIT management in asynchronous accesses
- 21.5.5 Synchronous transactions
- 21.5.6 NOR/PSRAM control registers
- 21.6 NAND Flash/PC Card controller
- Table 129. Programmable NAND/PC Card access parameters
- 21.6.1 External memory interface signals
- 21.6.2 NAND Flash / PC Card supported memories and transactions
- 21.6.3 Timing diagrams for NAND and PC Card
- 21.6.4 NAND Flash operations
- 21.6.5 NAND Flash prewait functionality
- 21.6.6 Computation of the error correction code (ECC) in NAND Flash memory
- 21.6.7 PC Card/CompactFlash operations
- 21.6.8 NAND Flash/PC Card control registers
- PC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4)
- FIFO status and interrupt register 2..4 (FSMC_SR2..4)
- Common memory space timing register 2..4 (FSMC_PMEM2..4)
- Attribute memory space timing registers 2..4 (FSMC_PATT2..4)
- I/O space timing register 4 (FSMC_PIO4)
- ECC result registers 2/3 (FSMC_ECCR2/3)
- 21.6.9 FSMC register map
- 22 Secure digital input/output interface (SDIO)
- 22.1 SDIO main features
- 22.2 SDIO bus topology
- 22.3 SDIO functional description
- 22.4 Card functional description
- 22.4.1 Card identification mode
- 22.4.2 Card reset
- 22.4.3 Operating voltage range validation
- 22.4.4 Card identification process
- 22.4.5 Block write
- 22.4.6 Block read
- 22.4.7 Stream access, stream write and stream read (MultiMediaCard only)
- 22.4.8 Erase: group erase and sector erase
- 22.4.9 Wide bus selection or deselection
- 22.4.10 Protection management
- 22.4.11 Card status register
- 22.4.12 SD status register
- 22.4.13 SD I/O mode
- 22.4.14 Commands and responses
- 22.5 Response formats
- 22.6 SDIO I/O card-specific operations
- 22.7 CE-ATA specific operations
- 22.8 HW flow control
- 22.9 SDIO registers
- 22.9.1 SDIO power control register (SDIO_POWER)
- 22.9.2 SDI clock control register (SDIO_CLKCR)
- 22.9.3 SDIO argument register (SDIO_ARG)
- 22.9.4 SDIO command register (SDIO_CMD)
- 22.9.5 SDIO command response register (SDIO_RESPCMD)
- 22.9.6 SDIO response 1..4 register (SDIO_RESPx)
- 22.9.7 SDIO data timer register (SDIO_DTIMER)
- 22.9.8 SDIO data length register (SDIO_DLEN)
- 22.9.9 SDIO data control register (SDIO_DCTRL)
- 22.9.10 SDIO data counter register (SDIO_DCOUNT)
- 22.9.11 SDIO status register (SDIO_STA)
- 22.9.12 SDIO interrupt clear register (SDIO_ICR)
- 22.9.13 SDIO mask register (SDIO_MASK)
- 22.9.14 SDIO FIFO counter register (SDIO_FIFOCNT)
- 22.9.15 SDIO data FIFO register (SDIO_FIFO)
- 22.9.16 SDIO register map
- 23 Universal serial bus full-speed device interface (USB)
- 23.1 USB introduction
- 23.2 USB main features
- 23.3 USB functional description
- 23.4 Programming considerations
- 23.5 USB registers
- 24 Controller area network (bxCAN)
- 24.1 bxCAN introduction
- 24.2 bxCAN main features
- 24.3 bxCAN general description
- 24.4 bxCAN operating modes
- 24.5 Test mode
- 24.6 Debug mode
- 24.7 bxCAN functional description
- 24.8 bxCAN interrupts
- 24.9 CAN registers
- 24.9.1 Register access protection
- 24.9.2 CAN control and status registers
- 24.9.3 CAN mailbox registers
- CAN TX mailbox identifier register (CAN_TIxR) (x=0..2)
- CAN mailbox data length control and time stamp register (CAN_TDTxR) (x=0..2)
- CAN mailbox data low register (CAN_TDLxR) (x=0..2)
- CAN mailbox data high register (CAN_TDHxR) (x=0..2)
- CAN receive FIFO mailbox identifier register (CAN_RIxR) (x=0..1)
- CAN receive FIFO mailbox data length control and time stamp register (CAN_RDTxR) (x=0..1)
- CAN receive FIFO mailbox data low register (CAN_RDLxR) (x=0..1)
- CAN receive FIFO mailbox data high register (CAN_RDHxR) (x=0..1)
- 24.9.4 CAN filter registers
- 24.9.5 bxCAN register map
- 25 Serial peripheral interface (SPI)
- 25.1 SPI introduction
- 25.2 SPI and I2S main features
- 25.3 SPI functional description
- 25.3.1 General description
- 25.3.2 Configuring the SPI in slave mode
- 25.3.3 Configuring the SPI in master mode
- 25.3.4 Configuring the SPI for half-duplex communication
- 25.3.5 Data transmission and reception procedures
- Rx and Tx buffers
- Start sequence in master mode
- Start sequence in slave mode
- Handling data transmission and reception
- Transmit-only procedure (BIDIMODE=0 RXONLY=0)
- Bidirectional transmit procedure (BIDIMODE=1 and BIDIOE=1)
- Unidirectional receive-only procedure (BIDIMODE=0 and RXONLY=1)
- Bidirectional receive procedure (BIDIMODE=1 and BIDIOE=0)
- Continuous and discontinuous transfers
- 25.3.6 CRC calculation
- 25.3.7 Status flags
- 25.3.8 Disabling the SPI
- In master or slave full-duplex mode (BIDIMODE=0, RXONLY=0)
- In master or slave unidirectional transmit-only mode (BIDIMODE=0, RXONLY=0) or bidirectional transmit mode (BIDIMODE=1, BIDIOE=1)
- In master unidirectional receive-only mode (MSTR=1, BIDIMODE=0, RXONLY=1) or bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0)
- In slave receive-only mode (MSTR=0, BIDIMODE=0, RXONLY=1) or bidirectional receive mode (MSTR=0, BIDIMODE=1, BIDOE=0)
- 25.3.9 SPI communication using DMA (direct memory addressing)
- 25.3.10 Error flags
- 25.3.11 SPI interrupts
- 25.4 I2S functional description
- 25.4.1 I2S general description
- 25.4.2 Supported audio protocols
- 25.4.3 Clock generator
- Table 183. Audio-frequency precision using standard 8 MHz HSE (high- density and XL-density devices only)
- Table 184. Audio-frequency precision using standard 25 MHz and PLL3 (connectivity line devices only)
- Table 185. Audio-frequency precision using standard 14.7456 MHz and PLL3 (connectivity line devices only)
- 25.4.4 I2S master mode
- 25.4.5 I2S slave mode
- 25.4.6 Status flags
- 25.4.7 Error flags
- 25.4.8 I2S interrupts
- 25.4.9 DMA features
- 25.5 SPI and I2S registers
- 25.5.1 SPI control register 1 (SPI_CR1) (not used in I2S mode)
- 25.5.2 SPI control register 2 (SPI_CR2)
- 25.5.3 SPI status register (SPI_SR)
- 25.5.4 SPI data register (SPI_DR)
- 25.5.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I2S mode)
- 25.5.6 SPI RX CRC register (SPI_RXCRCR) (not used in I2S mode)
- 25.5.7 SPI TX CRC register (SPI_TXCRCR) (not used in I2S mode)
- 25.5.8 SPI_I2S configuration register (SPI_I2SCFGR)
- 25.5.9 SPI_I2S prescaler register (SPI_I2SPR)
- 25.5.10 SPI register map
- 26 Inter-integrated circuit (I2C) interface
- 26.1 I2C introduction
- 26.2 I2C main features
- 26.3 I2C functional description
- 26.4 I2C interrupts
- 26.5 I2C debug mode
- 26.6 I2C registers
- 26.6.1 I2C Control register 1 (I2C_CR1)
- 26.6.2 I2C Control register 2 (I2C_CR2)
- 26.6.3 I2C Own address register 1 (I2C_OAR1)
- 26.6.4 I2C Own address register 2 (I2C_OAR2)
- 26.6.5 I2C Data register (I2C_DR)
- 26.6.6 I2C Status register 1 (I2C_SR1)
- 26.6.7 I2C Status register 2 (I2C_SR2)
- 26.6.8 I2C Clock control register (I2C_CCR)
- 26.6.9 I2C TRISE register (I2C_TRISE)
- 26.6.10 I2C register map
- 27 Universal synchronous asynchronous receiver transmitter (USART)
- 27.1 USART introduction
- 27.2 USART main features
- 27.3 USART functional description
- 27.3.1 USART character description
- 27.3.2 Transmitter
- 27.3.3 Receiver
- 27.3.4 Fractional baud rate generation
- 27.3.5 USART receiver’s tolerance to clock deviation
- 27.3.6 Multiprocessor communication
- 27.3.7 Parity control
- 27.3.8 LIN (local interconnection network) mode
- 27.3.9 USART synchronous mode
- 27.3.10 Single-wire half-duplex communication
- 27.3.11 Smartcard
- 27.3.12 IrDA SIR ENDEC block
- 27.3.13 Continuous communication using DMA
- 27.3.14 Hardware flow control
- 27.4 USART interrupts
- 27.5 USART mode configuration
- 27.6 USART registers
- 28 USB on-the-go full-speed (OTG_FS)
- 28.1 OTG_FS introduction
- 28.2 OTG_FS main features
- 28.3 OTG_FS functional description
- 28.4 OTG dual role device (DRD)
- 28.5 USB peripheral
- 28.6 USB host
- 28.7 SOF trigger
- 28.8 OTG low-power modes
- 28.9 Dynamic update of the OTG_FS_HFIR register
- 28.10 USB data FIFOs
- 28.11 Peripheral FIFO architecture
- 28.12 Host FIFO architecture
- 28.13 FIFO RAM allocation
- 28.14 USB system performance
- 28.15 OTG_FS interrupts
- 28.16 OTG_FS control and status registers
- 28.16.1 CSR memory map
- 28.16.2 OTG_FS global registers
- OTG_FS control and status register (OTG_FS_GOTGCTL)
- OTG_FS interrupt register (OTG_FS_GOTGINT)
- OTG_FS AHB configuration register (OTG_FS_GAHBCFG)
- OTG_FS USB configuration register (OTG_FS_GUSBCFG)
- OTG_FS reset register (OTG_FS_GRSTCTL)
- OTG_FS core interrupt register (OTG_FS_GINTSTS)
- OTG_FS interrupt mask register (OTG_FS_GINTMSK)
- OTG_FS Receive status debug read/OTG status read and pop registers (OTG_FS_GRXSTSR/OTG_FS_GRXSTSP)
- OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)
- OTG_FS Host non-periodic transmit FIFO size register (OTG_FS_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_FS_DIEPTXF0)
- OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_HNPTXSTS)
- OTG_FS general core configuration register (OTG_FS_GCCFG)
- OTG_FS core ID register (OTG_FS_CID)
- OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)
- OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXFx) (x = 1..3, where x is the FIFO_number)
- 28.16.3 Host-mode registers
- OTG_FS Host configuration register (OTG_FS_HCFG)
- OTG_FS Host frame interval register (OTG_FS_HFIR)
- OTG_FS Host frame number/frame time remaining register (OTG_FS_HFNUM)
- OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)
- OTG_FS Host all channels interrupt register (OTG_FS_HAINT)
- OTG_FS Host all channels interrupt mask register (OTG_FS_HAINTMSK)
- OTG_FS Host port control and status register (OTG_FS_HPRT)
- OTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx) (x = 0..7, where x = Channel_number)
- OTG_FS Host channel-x interrupt register (OTG_FS_HCINTx) (x = 0..7, where x = Channel_number)
- OTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx) (x = 0..7, where x = Channel_number)
- OTG_FS Host channel-x transfer size register (OTG_FS_HCTSIZx) (x = 0..7, where x = Channel_number)
- 28.16.4 Device-mode registers
- OTG_FS device configuration register (OTG_FS_DCFG)
- OTG_FS device control register (OTG_FS_DCTL)
- OTG_FS device status register (OTG_FS_DSTS)
- OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)
- OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
- OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
- OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
- OTG_FS device VBUS discharge time register (OTG_FS_DVBUSDIS)
- OTG_FS device VBUS pulsing time register (OTG_FS_DVBUSPULSE)
- OTG_FS device IN endpoint FIFO empty interrupt mask register: (OTG_FS_DIEPEMPMSK)
- OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
- OTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, where x = Endpoint_number)
- OTG_FS device control OUT endpoint 0 control register (OTG_FS_DOEPCTL0)
- OTG_FS device endpoint-x control register (OTG_FS_DOEPCTLx) (x = 1..3, where x = Endpoint_number)
- OTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) (x = 0..3, where x = Endpoint_number)
- OTG_FS device endpoint-x interrupt register (OTG_FS_DOEPINTx) (x = 0..3, where x = Endpoint_number)
- OTG_FS device IN endpoint 0 transfer size register (OTG_FS_DIEPTSIZ0)
- OTG_FS device OUT endpoint 0 transfer size register (OTG_FS_DOEPTSIZ0)
- OTG_FS device endpoint-x transfer size register (OTG_FS_DIEPTSIZx) (x = 1..3, where x = Endpoint_number)
- OTG_FS device IN endpoint transmit FIFO status register (OTG_FS_DTXFSTSx) (x = 0..3, where x = Endpoint_number)
- OTG_FS device OUT endpoint-x transfer size register (OTG_FS_DOEPTSIZx) (x = 1..3, where x = Endpoint_number)
- 28.16.5 OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)
- 28.16.6 OTG_FS register map
- 28.17 OTG_FS programming model
- 29 Ethernet (ETH): media access control (MAC) with DMA controller
- 29.1 Ethernet introduction
- 29.2 Ethernet main features
- 29.3 Ethernet pins
- 29.4 Ethernet functional description: SMI, MII and RMII
- 29.5 Ethernet functional description: MAC 802.3
- 29.5.1 MAC 802.3 frame format
- 29.5.2 MAC frame transmission
- 29.5.3 MAC frame reception
- 29.5.4 MAC interrupts
- 29.5.5 MAC filtering
- 29.5.6 MAC loopback mode
- 29.5.7 MAC management counters: MMC
- 29.5.8 Power management: PMT
- 29.5.9 Precision time protocol (IEEE1588 PTP)
- Reference timing source
- Transmission of frames with the PTP feature
- Reception of frames with the PTP feature
- System Time correction methods
- Programming steps for system time generation initialization
- Programming steps for system time update in the Coarse correction method
- Programming steps for system time update in the Fine correction method
- PTP trigger internal connection with TIM2
- PTP pulse-per-second output signal
- 29.6 Ethernet functional description: DMA controller operation
- 29.7 Ethernet interrupts
- 29.8 Ethernet register descriptions
- 29.8.1 MAC register description
- Ethernet MAC configuration register (ETH_MACCR)
- Ethernet MAC frame filter register (ETH_MACFFR)
- Ethernet MAC hash table high register (ETH_MACHTHR)
- Ethernet MAC hash table low register (ETH_MACHTLR)
- Ethernet MAC MII address register (ETH_MACMIIAR)
- Ethernet MAC MII data register (ETH_MACMIIDR)
- Ethernet MAC flow control register (ETH_MACFCR)
- Ethernet MAC VLAN tag register (ETH_MACVLANTR)
- Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)
- Ethernet MAC PMT control and status register (ETH_MACPMTCSR)
- Ethernet MAC interrupt status register (ETH_MACSR)
- Ethernet MAC interrupt mask register (ETH_MACIMR)
- Ethernet MAC address 0 high register (ETH_MACA0HR)
- Ethernet MAC address 0 low register (ETH_MACA0LR)
- Ethernet MAC address 1 high register (ETH_MACA1HR)
- Ethernet MAC address1 low register (ETH_MACA1LR)
- Ethernet MAC address 2 high register (ETH_MACA2HR)
- Ethernet MAC address 2 low register (ETH_MACA2LR)
- Ethernet MAC address 3 high register (ETH_MACA3HR)
- Ethernet MAC address 3 low register (ETH_MACA3LR)
- 29.8.2 MMC register description
- Ethernet MMC control register (ETH_MMCCR)
- Ethernet MMC receive interrupt register (ETH_MMCRIR)
- Ethernet MMC transmit interrupt register (ETH_MMCTIR)
- Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)
- Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)
- Ethernet MMC transmitted good frames after a single collision counter register (ETH_MMCTGFSCCR)
- Ethernet MMC transmitted good frames after more than a single collision counter register (ETH_MMCTGFMSCCR)
- Ethernet MMC transmitted good frames counter register (ETH_MMCTGFCR)
- Ethernet MMC received frames with CRC error counter register (ETH_MMCRFCECR)
- Ethernet MMC received frames with alignment error counter register (ETH_MMCRFAECR)
- MMC received good unicast frames counter register (ETH_MMCRGUFCR)
- 29.8.3 IEEE 1588 time stamp registers
- Ethernet PTP time stamp control register (ETH_PTPTSCR)
- Ethernet PTP subsecond increment register (ETH_PTPSSIR)
- Ethernet PTP time stamp high register (ETH_PTPTSHR)
- Ethernet PTP time stamp low register (ETH_PTPTSLR)
- Ethernet PTP time stamp high update register (ETH_PTPTSHUR)
- Ethernet PTP time stamp low update register (ETH_PTPTSLUR)
- Ethernet PTP time stamp addend register (ETH_PTPTSAR)
- Ethernet PTP target time high register (ETH_PTPTTHR)
- Ethernet PTP target time low register (ETH_PTPTTLR)
- 29.8.4 DMA register description
- Ethernet DMA bus mode register (ETH_DMABMR)
- Ethernet DMA transmit poll demand register (ETH_DMATPDR)
- EHERNET DMA receive poll demand register (ETH_DMARPDR)
- Ethernet DMA receive descriptor list address register (ETH_DMARDLAR)
- Ethernet DMA transmit descriptor list address register (ETH_DMATDLAR)
- Ethernet DMA status register (ETH_DMASR)
- Ethernet DMA operation mode register (ETH_DMAOMR)
- Ethernet DMA interrupt enable register (ETH_DMAIER)
- Ethernet DMA missed frame and buffer overflow counter register (ETH_DMAMFBOCR)
- Ethernet DMA current host transmit descriptor register (ETH_DMACHTDR)
- Ethernet DMA current host receive descriptor register (ETH_DMACHRDR)
- Ethernet DMA current host transmit buffer address register (ETH_DMACHTBAR)
- Ethernet DMA current host receive buffer address register (ETH_DMACHRBAR)
- 29.8.5 Ethernet register maps
- 29.8.1 MAC register description
- 30 Device electronic signature
- 31 Debug support (DBG)
- 31.1 Overview
- 31.2 Reference Arm® documentation
- 31.3 SWJ debug port (serial wire and JTAG)
- 31.4 Pinout and debug port pins
- 31.5 STM32F10xxx JTAG TAP connection
- 31.6 ID codes and locking mechanism
- 31.7 JTAG debug port
- 31.8 SW debug port
- 31.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP
- 31.10 Core debug
- 31.11 Capability of the debugger host to connect under system reset
- 31.12 FPB (Flash patch breakpoint)
- 31.13 DWT (data watchpoint trigger)
- 31.14 ITM (instrumentation trace macrocell)
- 31.15 ETM (Embedded trace macrocell)
- 31.16 MCU debug component (DBGMCU)
- 31.17 TPIU (trace port interface unit)
- 31.17.1 Introduction
- 31.17.2 TRACE pin assignment
- 31.17.3 TPUI formatter
- 31.17.4 TPUI frame synchronization packets
- 31.17.5 Transmission of the synchronization frame packet
- 31.17.6 Synchronous mode
- 31.17.7 Asynchronous mode
- 31.17.8 TRACECLKIN connection inside the STM32F10xxx
- 31.17.9 TPIU registers
- 31.17.10 Example of configuration
- 31.18 DBG register map
- 32 Revision history