STM32F3xxx And STM32F4xxx Cortex M4 Programming Manual Stm32f4
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- Table 1. Applicable products and tools
- 1 About this document
- 2 The Cortex-M4 processor
- 2.1 Programmers model
- 2.1.1 Processor mode and privilege levels for software execution
- 2.1.2 Stacks
- 2.1.3 Core registers
- Figure 2. Processor core registers
- Table 3. Core register set summary
- Figure 3. APSR, IPSR and EPSR bit assignments
- Figure 4. PSR bit assignments
- Table 4. PSR register combinations
- Table 5. APSR bit definitions
- Table 6. IPSR bit definitions
- Table 7. EPSR bit definitions
- Figure 5. PRIMASK bit assignments
- Table 8. PRIMASK register bit definitions
- Figure 6. FAULTMASK bit assignments
- Table 9. FAULTMASK register bit definitions
- Figure 7. BASEPRI bit assignments
- Table 10. BASEPRI register bit assignments
- Table 11. CONTROL register bit definitions
- 2.1.4 Exceptions and interrupts
- 2.1.5 Data types
- 2.1.6 The Cortex microcontroller software interface standard (CMSIS)
- 2.2 Memory model
- Figure 8. Memory map
- 2.2.1 Memory regions, types and attributes
- 2.2.2 Memory system ordering of memory accesses
- 2.2.3 Behavior of memory accesses
- 2.2.4 Software ordering of memory accesses
- 2.2.5 Bit-banding
- 2.2.6 Memory endianness
- 2.2.7 Synchronization primitives
- 2.2.8 Programming hints for the synchronization primitives
- 2.3 Exception model
- 2.4 Fault handling
- 2.5 Power management
- 2.1 Programmers model
- 3 The STM32 Cortex-M4 instruction set
- 3.1 Instruction set summary
- 3.2 CMSIS intrinsic functions
- 3.3 About the instruction descriptions
- 3.4 Memory access instructions
- 3.5 General data processing instructions
- Table 28. Data processing instructions
- 3.5.1 ADD, ADC, SUB, SBC, and RSB
- 3.5.2 AND, ORR, EOR, BIC, and ORN
- 3.5.3 ASR, LSL, LSR, ROR, and RRX
- 3.5.4 CLZ
- 3.5.5 CMP and CMN
- 3.5.6 MOV and MVN
- 3.5.7 MOVT
- 3.5.8 REV, REV16, REVSH, and RBIT
- 3.5.9 SADD16 and SADD8
- 3.5.10 SHADD16 and SHADD8
- 3.5.11 SHASX and SHSAX
- 3.5.12 SHSUB16 and SHSUB8
- 3.5.13 SSUB16 and SSUB8
- 3.5.14 SASX and SSAX
- 3.5.15 TST and TEQ
- 3.5.16 UADD16 and UADD8
- 3.5.17 UASX and USAX
- 3.5.18 UHADD16 and UHADD8
- 3.5.19 UHASX and UHSAX
- 3.5.20 UHSUB16 and UHSUB8
- 3.5.21 SEL
- 3.5.22 USAD8
- 3.5.23 USADA8
- 3.5.24 USUB16 and USUB8
- 3.6 Multiply and divide instructions
- 3.7 Saturating instructions
- 3.8 Packing and unpacking instructions
- 3.9 Bitfield instructions
- 3.10 Floating-point instructions
- Table 35. Floating-point instructions
- 3.10.1 VABS
- 3.10.2 VADD
- 3.10.3 VCMP, VCMPE
- 3.10.4 VCVT, VCVTR between floating-point and integer
- 3.10.5 VCVT between floating-point and fixed-point
- 3.10.6 VCVTB, VCVTT
- 3.10.7 VDIV
- 3.10.8 VFMA, VFMS
- 3.10.9 VFNMA, VFNMS
- 3.10.10 VLDM
- 3.10.11 VLDR
- 3.10.12 VLMA, VLMS
- 3.10.13 VMOV immediate
- 3.10.14 VMOV register
- 3.10.15 VMOV scalar to ARM core register
- 3.10.16 VMOV ARM core register to single precision
- 3.10.17 VMOV two ARM core registers to two single precision
- 3.10.18 VMOV ARM Core register to scalar
- 3.10.19 VMRS
- 3.10.20 VMSR
- 3.10.21 VMUL
- 3.10.22 VNEG
- 3.10.23 VNMLA, VNMLS, VNMUL
- 3.10.24 VPOP
- 3.10.25 VPUSH
- 3.10.26 VSQRT
- 3.10.27 VSTM
- 3.10.28 VSTR
- 3.10.29 VSUB
- 3.11 Miscellaneous instructions
- 4 Core peripherals
- 4.1 About the STM32 Cortex-M4 core peripherals
- 4.2 Memory protection unit (MPU)
- Table 38. Memory attributes summary
- 4.2.1 MPU access permission attributes
- 4.2.2 MPU mismatch
- 4.2.3 Updating an MPU region
- 4.2.4 MPU design hints and tips
- 4.2.5 MPU type register (MPU_TYPER)
- 4.2.6 MPU control register (MPU_CTRL)
- 4.2.7 MPU region number register (MPU_RNR)
- 4.2.8 MPU region base address register (MPU_RBAR)
- 4.2.9 MPU region attribute and size register (MPU_RASR)
- 4.2.10 MPU register map
- 4.3 Nested vectored interrupt controller (NVIC)
- Table 45. NVIC register summary
- 4.3.1 Accessing the Cortex-M4 NVIC registers using CMSIS
- 4.3.2 Interrupt set-enable registers (NVIC_ISERx)
- 4.3.3 Interrupt clear-enable registers (NVIC_ICERx)
- 4.3.4 Interrupt set-pending registers (NVIC_ISPRx)
- 4.3.5 Interrupt clear-pending registers (NVIC_ICPRx)
- 4.3.6 Interrupt active bit registers (NVIC_IABRx)
- 4.3.7 Interrupt priority registers (NVIC_IPRx)
- 4.3.8 Software trigger interrupt register (NVIC_STIR)
- 4.3.9 Level-sensitive and pulse interrupts
- 4.3.10 NVIC design hints and tips
- 4.3.11 NVIC register map
- 4.4 System control block (SCB)
- Table 50. Summary of the system control block registers
- 4.4.1 Auxiliary control register (ACTLR)
- 4.4.2 CPUID base register (CPUID)
- 4.4.3 Interrupt control and state register (ICSR)
- 4.4.4 Vector table offset register (VTOR)
- 4.4.5 Application interrupt and reset control register (AIRCR)
- 4.4.6 System control register (SCR)
- 4.4.7 Configuration and control register (CCR)
- 4.4.8 System handler priority registers (SHPRx)
- 4.4.9 System handler control and state register (SHCSR)
- 4.4.10 Configurable fault status register (CFSR; UFSR+BFSR+MMFSR)
- 4.4.11 Usage fault status register (UFSR)
- 4.4.12 Bus fault status register (BFSR)
- 4.4.13 Memory management fault address register (MMFSR)
- 4.4.14 Hard fault status register (HFSR)
- 4.4.15 Memory management fault address register (MMFAR)
- 4.4.16 Bus fault address register (BFAR)
- 4.4.17 Auxiliary fault status register (AFSR)
- 4.4.18 System control block design hints and tips
- 4.4.19 SCB register map
- 4.5 SysTick timer (STK)
- 4.6 Floating point unit (FPU)
- Table 56. Cortex-M4F floating-point system registers
- 4.6.1 Coprocessor access control register (CPACR)
- 4.6.2 Floating-point context control register (FPCCR)
- 4.6.3 Floating-point context address register (FPCAR)
- 4.6.4 Floating-point status control register (FPSCR)
- 4.6.5 Floating-point default status control register (FPDSCR)
- 4.6.6 Enabling the FPU
- 4.6.7 Enabling and clearing FPU exception interrupts
- 5 Revision history