STM32H743/753 Advanced ARM® Based 32 Bit MCUs Reference Manual Stm32h743
User Manual:
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- 1 Documentation conventions
- 2 Memory and bus architecture
- 3 Embedded Flash memory (FLASH)
- 3.1 Introduction
- 3.2 FLASH main features
- 3.3 FLASH functional description
- 3.3.1 FLASH block diagram
- 3.3.2 FLASH internal signals
- 3.3.3 FLASH architecture and integration in the system
- 3.3.4 Flash memory architecture and usage
- 3.3.5 FLASH system performance enhancements
- 3.3.6 FLASH data protection schemes
- 3.3.7 Overview of FLASH operations
- 3.3.8 FLASH read operations
- 3.3.9 FLASH program operations
- 3.3.10 FLASH erase operations
- 3.3.11 FLASH parallel operations
- 3.3.12 Flash memory error protections
- 3.3.13 Flash bank and register swapping
- 3.3.14 FLASH reset and clocks
- 3.4 FLASH option bytes
- 3.5 FLASH protection mechanisms
- 3.6 FLASH low-power modes
- 3.7 FLASH error management
- 3.7.1 Introduction
- 3.7.2 Write protection error (WRPERR)
- 3.7.3 Programming sequence error (PGSERR)
- 3.7.4 Strobe error (STRBERR)
- 3.7.5 Inconsistency error (INCERR)
- 3.7.6 Operation error (OPERR)
- 3.7.7 Error correction code error (SNECCERR/DBECCERR)
- 3.7.8 Read protection error (RDPERR)
- 3.7.9 Read secure error (RDSERR)
- 3.7.10 Option byte change error (OPTCHANGEERR)
- 3.7.11 Miscellaneous HardFault errors
- 3.8 FLASH interrupts
- 3.9 FLASH registers
- 3.9.1 FLASH access control register (FLASH_ACR)
- 3.9.2 FLASH key register for bank 1 (FLASH_KEYR1)
- 3.9.3 FLASH option key register (FLASH_OPTKEYR)
- 3.9.4 FLASH control register for bank 1 (FLASH_CR1)
- 3.9.5 FLASH status register for bank 1 (FLASH_SR1)
- 3.9.6 FLASH clear control register for bank 1 (FLASH_CCR1)
- 3.9.7 FLASH option control register (FLASH_OPTCR)
- 3.9.8 FLASH option status register (FLASH_OPTSR_CUR)
- 3.9.9 FLASH option status register (FLASH_OPTSR_PRG)
- 3.9.10 FLASH option clear control register (FLASH_OPTCCR)
- 3.9.11 FLASH protection address for bank 1 (FLASH_PRAR_CUR1)
- 3.9.12 FLASH protection address for bank 1 (FLASH_PRAR_PRG1)
- 3.9.13 FLASH secure address for bank 1 (FLASH_SCAR_CUR1)
- 3.9.14 FLASH secure address for bank 1 (FLASH_SCAR_PRG1)
- 3.9.15 FLASH write sector protection for bank 1 (FLASH_WPSN_CUR1R)
- 3.9.16 FLASH write sector protection for bank 1 (FLASH_WPSN_PRG1R)
- 3.9.17 FLASH register boot address FLASH_BOOT_CURR)
- 3.9.18 FLASH register boot address FLASH_BOOT_PRGR)
- 3.9.19 FLASH CRC control register for bank 1 (FLASH_CRCCR1)
- 3.9.20 FLASH CRC start address register for bank 1 (FLASH_CRCSADD1R)
- 3.9.21 FLASH CRC end address register for bank 1 (FLASH_CRCEADD1R)
- 3.9.22 FLASH CRC data register (FLASH_CRCDATAR)
- 3.9.23 FLASH ECC fail address for bank 1 (FLASH_ECC_FA1R)
- 3.9.24 FLASH key register for bank 2 (FLASH_KEYR2)
- 3.9.25 FLASH control register for bank 2 (FLASH_CR2)
- 3.9.26 FLASH status register for bank 2 (FLASH_SR2)
- 3.9.27 FLASH clear control register for bank 2 (FLASH_CCR2)
- 3.9.28 FLASH protection address for bank 2 (FLASH_PRAR_CUR2)
- 3.9.29 FLASH protection address for bank 2 (FLASH_PRAR_PRG2)
- 3.9.30 FLASH secure address for bank 2 (FLASH_SCAR_CUR2)
- 3.9.31 FLASH secure address for bank 2 (FLASH_SCAR_PRG2)
- 3.9.32 FLASH write sector protection for bank 2 (FLASH_WPSN_CUR2R)
- 3.9.33 FLASH write sector protection for bank 2 (FLASH_WPSN_PRG2R)
- 3.9.34 FLASH CRC control register for bank 2 (FLASH_CRCCR2)
- 3.9.35 FLASH CRC start address register for bank 2 (FLASH_CRCSADD2R)
- 3.9.36 FLASH CRC end address register for bank 2 (FLASH_CRCEADD2R)
- 3.9.37 FLASH ECC fail address for bank 2 (FLASH_ECC_FA2R)
- 3.10 FLASH register map and reset values
- 4 Secure memory management
- 5 Power control (PWR)
- 5.1 Introduction
- 5.2 PWR main features
- 5.3 PWR block diagram
- 5.4 Power supplies
- 5.5 Power supply supervision
- 5.6 Power management
- 5.7 Low-power modes
- 5.8 PWR register description
- 5.8.1 PWR control register 1 (PWR_CR1)
- 5.8.2 PWR control status register 1 (PWR_CSR1)
- 5.8.3 PWR control register 2 (PWR_CR2)
- 5.8.4 PWR control register 3 (PWR_CR3)
- 5.8.5 PWR CPU control register (PWR_CPUCR)
- 5.8.6 PWR D3 domain control register (PWR_D3CR)
- 5.8.7 PWR wakeup clear register (PWR_WKUPCR)
- 5.8.8 PWR wakeup flag register (PWR_WKUPFR)
- 5.8.9 PWR wakeup enable and polarity register (PWR_WKUPEPR)
- 5.8.10 PWR register map
- 6 Low-power D3 domain
- 7 Reset and Clock Control (RCC)
- 7.1 RCC main features
- 7.2 RCC block diagram
- 7.3 RCC pins and internal signals
- 7.4 RCC reset block functional description
- 7.5 RCC clock block functional description
- 7.5.1 Clock naming convention
- 7.5.2 Oscillators description
- 7.5.3 Clock Security System (CSS)
- 7.5.4 Clock output generation (MCO1/MCO2)
- 7.5.5 PLL description
- 7.5.6 System clock (sys_ck)
- 7.5.7 Handling clock generators in Stop and Standby mode
- 7.5.8 Kernel clock selection
- 7.5.9 General clock concept overview
- 7.5.10 Peripheral allocation
- 7.5.11 Peripheral clock gating control
- 7.5.12 CPU and bus matrix clock gating control
- 7.6 RCC Interrupts
- 7.7 RCC register description
- 7.7.1 Register mapping overview
- 7.7.2 RCC Source Control Register (RCC_CR)
- 7.7.3 RCC Internal Clock Source Calibration Register (RCC_ICSCR)
- 7.7.4 RCC Clock Recovery RC Register (RCC_CRRCR)
- 7.7.5 RCC Clock Configuration Register (RCC_CFGR)
- 7.7.6 RCC Domain 1 Clock Configuration Register (RCC_D1CFGR)
- 7.7.7 RCC Domain 2 Clock Configuration Register (RCC_D2CFGR)
- 7.7.8 RCC Domain 3 Clock Configuration Register (RCC_D3CFGR)
- 7.7.9 RCC PLLs Clock Source Selection Register (RCC_PLLCKSELR)
- 7.7.10 RCC PLLs Configuration Register (RCC_PLLCFGR)
- 7.7.11 RCC PLL1 Dividers Configuration Register (RCC_PLL1DIVR)
- 7.7.12 RCC PLL1 Fractional Divider Register (RCC_PLL1FRACR)
- 7.7.13 RCC PLL2 Dividers Configuration Register (RCC_PLL2DIVR)
- 7.7.14 RCC PLL2 Fractional Divider Register (RCC_PLL2FRACR)
- 7.7.15 RCC PLL3 Dividers Configuration Register (RCC_PLL3DIVR)
- 7.7.16 RCC PLL3 Fractional Divider Register (RCC_PLL3FRACR)
- 7.7.17 RCC Domain 1 Kernel Clock Configuration Register (RCC_D1CCIPR)
- 7.7.18 RCC Domain 2 Kernel Clock Configuration Register (RCC_D2CCIP1R)
- 7.7.19 RCC Domain 2 Kernel Clock Configuration Register (RCC_D2CCIP2R)
- 7.7.20 RCC Domain 3 Kernel Clock Configuration Register (RCC_D3CCIPR)
- 7.7.21 RCC Clock Source Interrupt Enable Register (RCC_CIER)
- 7.7.22 RCC Clock Source Interrupt Flag Register (RCC_CIFR)
- 7.7.23 RCC Clock Source Interrupt Clear Register (RCC_CICR)
- 7.7.24 RCC Backup Domain Control Register (RCC_BDCR)
- 7.7.25 RCC Clock Control and Status Register (RCC_CSR)
- 7.7.26 RCC AHB3 Reset Register (RCC_AHB3RSTR)
- 7.7.27 RCC AHB1 Peripheral Reset Register(RCC_AHB1RSTR)
- 7.7.28 RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR)
- 7.7.29 RCC AHB4 Peripheral Reset Register (RCC_AHB4RSTR)
- 7.7.30 RCC APB3 Peripheral Reset Register (RCC_APB3RSTR)
- 7.7.31 RCC APB1 Peripheral Reset Register (RCC_APB1LRSTR)
- 7.7.32 RCC APB1 Peripheral Reset Register (RCC_APB1HRSTR)
- 7.7.33 RCC APB2 Peripheral Reset Register (RCC_APB2RSTR)
- 7.7.34 RCC APB4 Peripheral Reset Register (RCC_APB4RSTR)
- 7.7.35 RCC Global Control Register (RCC_GCR)
- 7.7.36 RCC D3 Autonomous mode Register (RCC_D3AMR)
- 7.7.37 RCC Reset Status Register (RCC_RSR)
- 7.7.38 RCC AHB3 Clock Register (RCC_AHB3ENR)
- 7.7.39 RCC AHB1 Clock Register (RCC_AHB1ENR)
- 7.7.40 RCC AHB2 Clock Register (RCC_AHB2ENR)
- 7.7.41 RCC AHB4 Clock Register (RCC_AHB4ENR)
- 7.7.42 RCC APB3 Clock Register (RCC_APB3ENR)
- 7.7.43 RCC APB1 Clock Register (RCC_APB1LENR)
- 7.7.44 RCC APB1 Clock Register (RCC_APB1HENR)
- 7.7.45 RCC APB2 Clock Register (RCC_APB2ENR)
- 7.7.46 RCC APB4 Clock Register (RCC_APB4ENR)
- 7.7.47 RCC AHB3 Sleep Clock Register (RCC_AHB3LPENR)
- 7.7.48 RCC AHB1 Sleep Clock Register (RCC_AHB1LPENR)
- 7.7.49 RCC AHB2 Sleep Clock Register (RCC_AHB2LPENR)
- 7.7.50 RCC AHB4 Sleep Clock Register (RCC_AHB4LPENR)
- 7.7.51 RCC APB3 Sleep Clock Register (RCC_APB3LPENR)
- 7.7.52 RCC APB1 Low Sleep Clock Register (RCC_APB1LLPENR)
- 7.7.53 RCC APB1 High Sleep Clock Register (RCC_APB1HLPENR)
- 7.7.54 RCC APB2 Sleep Clock Register (RCC_APB2LPENR)
- 7.7.55 RCC APB4 Sleep Clock Register (RCC_APB4LPENR)
- 7.8 RCC register map
- 8 Clock recovery system (CRS)
- 9 Hardware semaphore (HSEM)
- 9.1 Hardware semaphore introduction
- 9.2 Hardware semaphore main features
- 9.3 HSEM functional description
- 9.4 HSEM registers
- 9.4.1 HSEM register semaphore x (HSEM_Rx)
- 9.4.2 HSEM read lock register semaphore x (HSEM_RLRx)
- 9.4.3 HSEM interrupt enable register (HSEM_CnIER)
- 9.4.4 HSEM interrupt clear register (HSEM_CnICR)
- 9.4.5 HSEM interrupt status register (HSEM_CnISR)
- 9.4.6 HSEM masked interrupt status register (HSEM_CnMISR)
- 9.4.7 HSEM clear register (HSEM_CR)
- 9.4.8 HSEM interrupt clear register (HSEM_KEYR)
- 9.4.9 HSEM register map
- 10 General-purpose I/Os (GPIO)
- 10.1 Introduction
- 10.2 GPIO main features
- 10.3 GPIO functional description
- 10.3.1 General-purpose I/O (GPIO)
- 10.3.2 I/O pin alternate function multiplexer and mapping
- 10.3.3 I/O port control registers
- 10.3.4 I/O port data registers
- 10.3.5 I/O data bitwise handling
- 10.3.6 GPIO locking mechanism
- 10.3.7 I/O alternate function input/output
- 10.3.8 External interrupt/wakeup lines
- 10.3.9 Input configuration
- 10.3.10 Output configuration
- 10.3.11 I/O compensation cell
- 10.3.12 Alternate function configuration
- 10.3.13 Analog configuration
- 10.3.14 Using the HSE or LSE oscillator pins as GPIOs
- 10.3.15 Using the GPIO pins in the backup supply domain
- 10.4 GPIO registers
- 10.4.1 GPIO port mode register (GPIOx_MODER) (x =A to K)
- 10.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A to K)
- 10.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A to K)
- 10.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to K)
- 10.4.5 GPIO port input data register (GPIOx_IDR) (x = A to K)
- 10.4.6 GPIO port output data register (GPIOx_ODR) (x = A to K)
- 10.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A to K)
- 10.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A to K)
- 10.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A to K)
- 10.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A to J)
- 10.4.11 GPIO register map
- 11 System configuration controller (SYSCFG)
- 11.1 Introduction
- 11.2 SYSCFG main features
- 11.3 SYSCFG registers
- 11.3.1 SYSCFG peripheral mode configuration register (SYSCFG_PMCR)
- 11.3.2 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)
- 11.3.3 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)
- 11.3.4 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)
- 11.3.5 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)
- 11.3.6 SYSCFG configuration register (SYSCFG_CFGR)
- 11.3.7 SYSCFG compensation cell control/status register (SYSCFG_CCCSR)
- 11.3.8 SYSCFG compensation cell value register (SYSCFG_CCVR)
- 11.3.9 SYSCFG compensation cell code register (SYSCFG_CCCR)
- 11.3.10 SYSCFG package register (SYSCFG_PKGR)
- 11.3.11 SYSCFG user register 0 (SYSCFG_UR0)
- 11.3.12 SYSCFG user register 2 (SYSCFG_UR2)
- 11.3.13 SYSCFG user register 3 (SYSCFG_UR3)
- 11.3.14 SYSCFG user register 4 (SYSCFG_UR4)
- 11.3.15 SYSCFG user register 5 (SYSCFG_UR5)
- 11.3.16 SYSCFG user register 6 (SYSCFG_UR6)
- 11.3.17 SYSCFG user register 7 (SYSCFG_UR7)
- 11.3.18 SYSCFG user register 8 (SYSCFG_UR8)
- 11.3.19 SYSCFG user register 9 (SYSCFG_UR9)
- 11.3.20 SYSCFG user register 10 (SYSCFG_UR10)
- 11.3.21 SYSCFG user register 11 (SYSCFG_UR11)
- 11.3.22 SYSCFG user register 12 (SYSCFG_UR12)
- 11.3.23 SYSCFG user register 13 (SYSCFG_UR13)
- 11.3.24 SYSCFG user register 14 (SYSCFG_UR14)
- 11.3.25 SYSCFG user register 15 (SYSCFG_UR15)
- 11.3.26 SYSCFG user register 16 (SYSCFG_UR16)
- 11.3.27 SYSCFG user register 17 (SYSCFG_UR17)
- 11.3.28 SYSCFG register maps
- 12 Block interconnect
- 13 MDMA controller (MDMA)
- 13.1 MDMA introduction
- 13.2 MDMA main features
- 13.3 MDMA functional description
- 13.3.1 MDMA block diagram
- 13.3.2 MDMA internal signals
- 13.3.3 MDMA overview
- 13.3.4 MDMA channel
- 13.3.5 Source, destination and transfer modes
- 13.3.6 Pointer update
- 13.3.7 MDMA buffer transfer
- 13.3.8 Request arbitration
- 13.3.9 FIFO
- 13.3.10 Block transfer
- 13.3.11 Block repeat mode
- 13.3.12 Linked list mode
- 13.3.13 MDMA transfer completion
- 13.3.14 MDMA transfer suspension
- 13.3.15 Error management
- 13.4 MDMA interrupts
- 13.5 MDMA registers
- 13.5.1 MDMA global interrupt/status register (MDMA_GISR0)
- 13.5.2 MDMA channel x interrupt/status register (MDMA_CxISR)
- 13.5.3 MDMA channel x interrupt flag clear register (MDMA_CxIFCR)
- 13.5.4 MDMA channel x error status register (MDMA_CxESR)
- 13.5.5 MDMA channel x control register (MDMA_CxCR)
- 13.5.6 MDMA channel x transfer configuration register (MDMA_CxTCR)
- 13.5.7 MDMA channel x block number of data register (MDMA_CxBNDTR)
- 13.5.8 MDMA channel x source address register (MDMA_CxSAR)
- 13.5.9 MDMA channel x destination address register (MDMA_CxDAR)
- 13.5.10 MDMA channel x block repeat address update register (MDMA_CxBRUR)
- 13.5.11 MDMA channel x link address register (MDMA_CxLAR)
- 13.5.12 MDMA channel x trigger and bus selection register (MDMA_CxTBR)
- 13.5.13 MDMA channel x mask address register (MDMA_CxMAR)
- 13.5.14 MDMA channel x mask data register (MDMA_CxMDR)
- 13.5.15 MDMA register map
- 14 Direct memory access controller (DMA)
- 14.1 DMA introduction
- 14.2 DMA main features
- 14.3 DMA functional description
- 14.3.1 DMA block diagram
- 14.3.2 DMA internal signals
- 14.3.3 DMA overview
- 14.3.4 DMA transactions
- 14.3.5 DMA request mapping
- 14.3.6 Arbiter
- 14.3.7 DMA streams
- 14.3.8 Source, destination and transfer modes
- 14.3.9 Pointer incrementation
- 14.3.10 Circular mode
- 14.3.11 Double-buffer mode
- 14.3.12 Programmable data width, packing/unpacking, endianness
- 14.3.13 Single and burst transfers
- 14.3.14 FIFO
- 14.3.15 DMA transfer completion
- 14.3.16 DMA transfer suspension
- 14.3.17 Flow controller
- 14.3.18 Summary of the possible DMA configurations
- 14.3.19 Stream configuration procedure
- 14.3.20 Error management
- 14.4 DMA interrupts
- 14.5 DMA registers
- 14.5.1 DMA low interrupt status register (DMA_LISR)
- 14.5.2 DMA high interrupt status register (DMA_HISR)
- 14.5.3 DMA low interrupt flag clear register (DMA_LIFCR)
- 14.5.4 DMA high interrupt flag clear register (DMA_HIFCR)
- 14.5.5 DMA stream x configuration register (DMA_SxCR)
- 14.5.6 DMA stream x number of data register (DMA_SxNDTR)
- 14.5.7 DMA stream x peripheral address register (DMA_SxPAR)
- 14.5.8 DMA stream x memory 0 address register (DMA_SxM0AR)
- 14.5.9 DMA stream x memory 1 address register (DMA_SxM1AR)
- 14.5.10 DMA stream x FIFO control register (DMA_SxFCR)
- 14.5.11 DMA register map
- 15 Basic direct memory access controller (BDMA)
- 15.1 Introduction
- 15.2 BDMA main features
- 15.3 BDMA implementation
- 15.4 BDMA functional description
- 15.5 BDMA interrupts
- 15.6 BDMA registers
- 15.6.1 BDMA interrupt status register (BDMA_ISR)
- 15.6.2 BDMA interrupt flag clear register (BDMA_IFCR)
- 15.6.3 BDMA channel x configuration register (BDMA_CCRx)
- 15.6.4 BDMA channel x number of data to transfer register (BDMA_CNDTRx)
- 15.6.5 BDMA channel x peripheral address register (BDMA_CPARx)
- 15.6.6 BDMA channel x memory 0 address register (BDMA_CM0ARx)
- 15.6.7 BDMA channel x memory 1 address register (BDMA_CM1ARx)
- 15.6.8 BDMA register map and reset values
- 16 DMA request multiplexer (DMAMUX)
- 16.1 Introduction
- 16.2 DMAMUX main features
- 16.3 DMAMUX implementation
- 16.4 DMAMUX functional description
- 16.5 DMAMUX interrupts
- 16.6 DMAMUX registers
- 16.6.1 DMAMUX1 request line multiplexer channel x configuration register (DMAMUX1_CxCR)
- 16.6.2 DMAMUX2 request line multiplexer channel x configuration register (DMAMUX2_CxCR)
- 16.6.3 DMAMUX1 request line multiplexer interrupt channel status register (DMAMUX1_CSR)
- 16.6.4 DMAMUX2 request line multiplexer interrupt channel status register (DMAMUX2_CSR)
- 16.6.5 DMAMUX1 request line multiplexer interrupt clear flag register (DMAMUX1_CFR)
- 16.6.6 DMAMUX2 request line multiplexer interrupt clear flag register (DMAMUX2_CFR)
- 16.6.7 DMAMUX1 request generator channel x configuration register (DMAMUX1_RGxCR)
- 16.6.8 DMAMUX2 request generator channel x configuration register (DMAMUX2_RGxCR)
- 16.6.9 DMAMUX1 request generator interrupt status register (DMAMUX1_RGSR)
- 16.6.10 DMAMUX2 request generator interrupt status register (DMAMUX2_RGSR)
- 16.6.11 DMAMUX1 request generator interrupt clear flag register (DMAMUX1_RGCFR)
- 16.6.12 DMAMUX2 request generator interrupt clear flag register (DMAMUX2_RGCFR)
- 16.6.13 DMAMUX register map
- 17 Chrom-Art Accelerator™ controller (DMA2D)
- 17.1 DMA2D introduction
- 17.2 DMA2D main features
- 17.3 DMA2D functional description
- 17.4 DMA2D pins and internal signals
- 17.4.1 DMA2D control
- 17.4.2 DMA2D foreground and background FIFOs
- 17.4.3 DMA2D foreground and background pixel format converter (PFC)
- 17.4.4 DMA2D foreground and background CLUT interface
- 17.4.5 DMA2D blender
- 17.4.6 DMA2D output PFC
- 17.4.7 DMA2D output FIFO
- 17.4.8 DMA2D output FIFO byte reordering
- 17.4.9 DMA2D AXI master port timer
- 17.4.10 DMA2D transactions
- 17.4.11 DMA2D configuration
- 17.4.12 YCbCr support
- 17.4.13 DMA2D transfer control (start, suspend, abort and completion)
- 17.4.14 Watermark
- 17.4.15 Error management
- 17.4.16 AXI dead time
- 17.5 DMA2D interrupts
- 17.6 DMA2D registers
- 17.6.1 DMA2D control register (DMA2D_CR)
- 17.6.2 DMA2D Interrupt Status Register (DMA2D_ISR)
- 17.6.3 DMA2D interrupt flag clear register (DMA2D_IFCR)
- 17.6.4 DMA2D foreground memory address register (DMA2D_FGMAR)
- 17.6.5 DMA2D foreground offset register (DMA2D_FGOR)
- 17.6.6 DMA2D background memory address register (DMA2D_BGMAR)
- 17.6.7 DMA2D background offset register (DMA2D_BGOR)
- 17.6.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR)
- 17.6.9 DMA2D foreground color register (DMA2D_FGCOLR)
- 17.6.10 DMA2D background PFC control register (DMA2D_BGPFCCR)
- 17.6.11 DMA2D background color register (DMA2D_BGCOLR)
- 17.6.12 DMA2D foreground CLUT memory address register (DMA2D_FGCMAR)
- 17.6.13 DMA2D background CLUT memory address register (DMA2D_BGCMAR)
- 17.6.14 DMA2D output PFC control register (DMA2D_OPFCCR)
- 17.6.15 DMA2D output color register (DMA2D_OCOLR)
- 17.6.16 DMA2D output memory address register (DMA2D_OMAR)
- 17.6.17 DMA2D output offset register (DMA2D_OOR)
- 17.6.18 DMA2D number of line register (DMA2D_NLR)
- 17.6.19 DMA2D line watermark register (DMA2D_LWR)
- 17.6.20 DMA2D AXI master timer configuration register (DMA2D_AMTCR)
- 17.6.21 DMA2D register map
- 18 Nested Vectored Interrupt Controllers
- 19 Extended interrupt and event controller (EXTI)
- 19.1 EXTI main features
- 19.2 EXTI block diagram
- 19.3 EXTI functional description
- 19.4 EXTI event input mapping
- 19.5 EXTI functional behavior
- 19.6 EXTI registers
- 19.6.1 EXTI rising trigger selection register (EXTI_RTSR1)
- 19.6.2 EXTI falling trigger selection register (EXTI_FTSR1)
- 19.6.3 EXTI software interrupt event register (EXTI_SWIER1)
- 19.6.4 EXTI D3 pending mask register (EXTI_D3PMR1)
- 19.6.5 EXTI D3 pending clear selection register low (EXTI_D3PCR1L)
- 19.6.6 EXTI D3 pending clear selection register high (EXTI_D3PCR1H)
- 19.6.7 EXTI rising trigger selection register (EXTI_RTSR2)
- 19.6.8 EXTI falling trigger selection register (EXTI_FTSR2)
- 19.6.9 EXTI software interrupt event register (EXTI_SWIER2)
- 19.6.10 EXTI D3 pending mask register (EXTI_D3PMR2)
- 19.6.11 EXTI D3 pending clear selection register low (EXTI_D3PCR2L)
- 19.6.12 EXTI D3 pending clear selection register high (EXTI_D3PCR2H)
- 19.6.13 EXTI rising trigger selection register (EXTI_RTSR3)
- 19.6.14 EXTI falling trigger selection register (EXTI_FTSR3)
- 19.6.15 EXTI software interrupt event register (EXTI_SWIER3)
- 19.6.16 EXTI D3 pending mask register (EXTI_D3PMR3)
- 19.6.17 EXTI D3 pending clear selection register low (EXTI_D3PCR3L)
- 19.6.18 EXTI D3 pending clear selection register high (EXTI_D3PCR3H)
- 19.6.19 EXTI interrupt mask register (EXTI_CPUIMR1)
- 19.6.20 EXTI event mask register (EXTI_CPUEMR1)
- 19.6.21 EXTI pending register (EXTI_CPUPR1)
- 19.6.22 EXTI interrupt mask register (EXTI_CPUIMR2)
- 19.6.23 EXTI event mask register (EXTI_CPUEMR2)
- 19.6.24 EXTI pending register (EXTI_CPUPR2)
- 19.6.25 EXTI interrupt mask register (EXTI_CPUIMR3)
- 19.6.26 EXTI event mask register (EXTI_CPUEMR3)
- 19.6.27 EXTI pending register (EXTI_CPUPR3)
- 19.6.28 EXTI register map
- 20 Cyclic redundancy check calculation unit (CRC)
- 21 Flexible memory controller (FMC)
- 21.1 FMC main features
- 21.2 FMC block diagram
- 21.3 FMC internal signals
- 21.4 AHB interface
- 21.5 AXI interface
- 21.6 External device address mapping
- 21.7 NOR Flash/PSRAM controller
- 21.8 NAND Flash controller
- 21.8.1 External memory interface signals
- 21.8.2 NAND Flash supported memories and transactions
- 21.8.3 Timing diagrams for NAND Flash memories
- 21.8.4 NAND Flash operations
- 21.8.5 NAND Flash prewait feature
- 21.8.6 Computation of the error correction code (ECC) in NAND Flash memory
- 21.8.7 NAND Flash controller registers
- 21.9 SDRAM controller
- 21.10 FMC register map
- 22 Quad-SPI interface (QUADSPI)
- 22.1 Introduction
- 22.2 QUADSPI main features
- 22.3 QUADSPI functional description
- 22.3.1 QUADSPI block diagram
- 22.3.2 QUADSPI pins and internal signals
- 22.3.3 QUADSPI command sequence
- 22.3.4 QUADSPI signal interface protocol modes
- 22.3.5 QUADSPI indirect mode
- 22.3.6 QUADSPI status flag polling mode
- 22.3.7 QUADSPI memory-mapped mode
- 22.3.8 QUADSPI Free running clock mode
- 22.3.9 QUADSPI Flash memory configuration
- 22.3.10 QUADSPI delayed data sampling
- 22.3.11 QUADSPI configuration
- 22.3.12 QUADSPI usage
- 22.3.13 Sending the instruction only once
- 22.3.14 QUADSPI error management
- 22.3.15 QUADSPI busy bit and abort functionality
- 22.3.16 nCS behavior
- 22.4 QUADSPI interrupts
- 22.5 QUADSPI registers
- 22.5.1 QUADSPI control register (QUADSPI_CR)
- 22.5.2 QUADSPI device configuration register (QUADSPI_DCR)
- 22.5.3 QUADSPI status register (QUADSPI_SR)
- 22.5.4 QUADSPI flag clear register (QUADSPI_FCR)
- 22.5.5 QUADSPI data length register (QUADSPI_DLR)
- 22.5.6 QUADSPI communication configuration register (QUADSPI_CCR)
- 22.5.7 QUADSPI address register (QUADSPI_AR)
- 22.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR)
- 22.5.9 QUADSPI data register (QUADSPI_DR)
- 22.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR)
- 22.5.11 QUADSPI polling status match register (QUADSPI _PSMAR)
- 22.5.12 QUADSPI polling interval register (QUADSPI _PIR)
- 22.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR)
- 22.5.14 QUADSPI register map
- 23 Delay block (DLYB)
- 24 Analog-to-digital converters (ADC)
- 24.1 Introduction
- 24.2 ADC main features
- 24.3 ADC functional description
- 24.3.1 ADC block diagram
- 24.3.2 ADC pins and internal signals
- 24.3.3 Clocks
- 24.3.4 ADC1/2/3 connectivity
- 24.3.5 Slave AHB interface
- 24.3.6 ADC deep-power-down mode (DEEPPWD) & ADC voltage regulator (ADVREGEN)
- 24.3.7 Single-ended and differential input channels
- 24.3.8 Calibration (ADCAL, ADCALDIF, ADCALLIN, ADC_CALFACT)
- 24.3.9 ADC on-off control (ADEN, ADDIS, ADRDY)
- 24.3.10 Constraints when writing the ADC control bits
- 24.3.11 Channel selection (SQRx, JSQRx)
- 24.3.12 Channel preselection register (ADC_PCSEL)
- 24.3.13 Channel-wise programmable sampling time (SMPR1, SMPR2)
- 24.3.14 Single conversion mode (CONT=0)
- 24.3.15 Continuous conversion mode (CONT=1)
- 24.3.16 Starting conversions (ADSTART, JADSTART)
- 24.3.17 Timing
- 24.3.18 Stopping an ongoing conversion (ADSTP, JADSTP)
- 24.3.19 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN)
- 24.3.20 Injected channel management
- 24.3.21 Discontinuous mode (DISCEN, DISCNUM, JDISCEN)
- 24.3.22 Queue of context for injected conversions
- 24.3.23 Programmable resolution (RES) - fast conversion mode
- 24.3.24 End of conversion, end of sampling phase (EOC, JEOC, EOSMP)
- 24.3.25 End of conversion sequence (EOS, JEOS)
- 24.3.26 Timing diagrams example (single/continuous modes, hardware/software triggers)
- 24.3.27 Data management
- 24.3.28 Managing conversions using the DFSDM
- 24.3.29 Dynamic low-power features
- 24.3.30 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy)
- 24.3.31 Oversampler
- 24.3.32 Dual ADC modes
- 24.3.33 Temperature sensor
- 24.3.34 VBAT supply monitoring
- 24.3.35 Monitoring the internal voltage reference
- 24.4 ADC interrupts
- 24.5 ADC registers (for each ADC)
- 24.5.1 ADC interrupt and status register (ADC_ISR)
- 24.5.2 ADC interrupt enable register (ADC_IER)
- 24.5.3 ADC control register (ADC_CR)
- 24.5.4 ADC configuration register (ADC_CFGR)
- 24.5.5 ADC configuration register 2 (ADC_CFGR2)
- 24.5.6 ADC sample time register 1 (ADC_SMPR1)
- 24.5.7 ADC sample time register 2 (ADC_SMPR2)
- 24.5.8 ADC channel preselection register (ADC_PCSEL)
- 24.5.9 ADC watchdog threshold register 1 (ADC_LTR1)
- 24.5.10 ADC watchdog threshold register 1 (ADC_HTR1)
- 24.5.11 ADC regular sequence register 1 (ADC_SQR1)
- 24.5.12 ADC regular sequence register 2 (ADC_SQR2)
- 24.5.13 ADC regular sequence register 3 (ADC_SQR3)
- 24.5.14 ADC regular sequence register 4 (ADC_SQR4)
- 24.5.15 ADC regular Data Register (ADC_DR)
- 24.5.16 ADC injected sequence register (ADC_JSQR)
- 24.5.17 ADC offset register (ADC_OFRy)
- 24.5.18 ADC injected data register (ADC_JDRy)
- 24.5.19 ADC analog watchdog 2 configuration register (ADC_AWD2CR)
- 24.5.20 ADC analog watchdog 3 configuration register (ADC_AWD3CR)
- 24.5.21 ADC watchdog lower threshold register 2 (ADC_LTR2)
- 24.5.22 ADC watchdog higher threshold register 2 (ADC_HTR2)
- 24.5.23 ADC watchdog lower threshold register 3 (ADC_LTR3)
- 24.5.24 ADC watchdog higher threshold register 3 (ADC_HTR3)
- 24.5.25 ADC differential mode selection register (ADC_DIFSEL)
- 24.5.26 ADC calibration factors register (ADC_CALFACT)
- 24.5.27 ADC calibration factor register 2 (ADC_CALFACT2)
- 24.6 ADC common registers
- 24.6.1 ADC x common status register (ADCx_CSR) (x=1/2 or 3)
- 24.6.2 ADC x common control register (ADCx_CCR) (x=1/2 or 3)
- 24.6.3 ADC x common regular data register for dual mode (ADCx_CDR) (x=1/2 or 3)
- 24.6.4 ADC x common regular data register for 32-bit dual mode (ADCx_CDR2) (x=1/2 or 3)
- 24.6.5 ADC register map
- 25 Digital-to-analog converter (DAC)
- 25.1 Introduction
- 25.2 DAC main features
- 25.3 DAC implementation
- 25.4 DAC functional description
- 25.4.1 DAC block diagram
- 25.4.2 DAC pins and internal signals
- 25.4.3 DAC channel enable
- 25.4.4 DAC data format
- 25.4.5 DAC conversion
- 25.4.6 DAC output voltage
- 25.4.7 DAC trigger selection
- 25.4.8 DMA requests
- 25.4.9 Noise generation
- 25.4.10 Triangle-wave generation
- 25.4.11 DAC channel modes
- 25.4.12 DAC channel buffer calibration
- 25.4.13 Dual DAC channel conversion (if available)
- 25.5 DAC low-power modes
- 25.6 DAC interrupts
- 25.7 DAC registers
- 25.7.1 DAC control register (DAC_CR)
- 25.7.2 DAC software trigger register (DAC_SWTRGR)
- 25.7.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)
- 25.7.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
- 25.7.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
- 25.7.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
- 25.7.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
- 25.7.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
- 25.7.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD)
- 25.7.10 Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD)
- 25.7.11 Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD)
- 25.7.12 DAC channel1 data output register (DAC_DOR1)
- 25.7.13 DAC channel2 data output register (DAC_DOR2)
- 25.7.14 DAC status register (DAC_SR)
- 25.7.15 DAC calibration control register (DAC_CCR)
- 25.7.16 DAC mode control register (DAC_MCR)
- 25.7.17 DAC channel 1 sample and hold sample time register (DAC_SHSR1)
- 25.7.18 DAC channel 2 sample and hold sample time register (DAC_SHSR2)
- 25.7.19 DAC sample and hold time register (DAC_SHHR)
- 25.7.20 DAC sample and hold refresh time register (DAC_SHRR)
- 25.7.21 DAC register map
- 26 Voltage reference buffer (VREFBUF)
- 27 Comparator (COMP)
- 27.1 Introduction
- 27.2 COMP main features
- 27.3 COMP functional description
- 27.3.1 COMP block diagram
- 27.3.2 COMP pins and internal signals
- 27.3.3 COMP reset and clocks
- 27.3.4 Comparator LOCK mechanism
- 27.3.5 Window comparator
- 27.3.6 Hysteresis
- 27.3.7 Comparator output blanking function
- 27.3.8 Comparator output on GPIOs
- 27.3.9 Comparator output redirection
- 27.3.10 COMP power and speed modes
- 27.4 COMP low-power modes
- 27.5 COMP interrupts
- 27.6 SCALER function
- 27.7 COMP registers
- 28 Operational amplifiers (OPAMP)
- 28.1 Introduction
- 28.2 OPAMP main features
- 28.3 OPAMP functional description
- 28.4 OPAMP low-power modes
- 28.5 OPAMP PGA gain
- 28.6 OPAMP registers
- 28.6.1 OPAMP1 control/status register (OPAMP1_CSR)
- 28.6.2 OPAMP1 trimming register in normal mode (OPAMP1_OTR)
- 28.6.3 OPAMP1 trimming register in high-speed mode (OPAMP1_HSOTR)
- 28.6.4 OPAMP option register (OPAMP_OR)
- 28.6.5 OPAMP2 control/status register (OPAMP2_CSR)
- 28.6.6 OPAMP2 trimming register in normal mode (OPAMP2_OTR)
- 28.6.7 OPAMP2 trimming register in high-speed mode (OPAMP2_HSOTR)
- 28.6.8 OPAMP register map
- 29 Digital filter for sigma delta modulators (DFSDM)
- 29.1 Introduction
- 29.2 DFSDM main features
- 29.3 DFSDM implementation
- 29.4 DFSDM functional description
- 29.4.1 DFSDM block diagram
- 29.4.2 DFSDM pins and internal signals
- 29.4.3 DFSDM reset and clocks
- 29.4.4 Serial channel transceivers
- 29.4.5 Configuring the input serial interface
- 29.4.6 Parallel data inputs
- 29.4.7 Channel selection
- 29.4.8 Digital filter configuration
- 29.4.9 Integrator unit
- 29.4.10 Analog watchdog
- 29.4.11 Short-circuit detector
- 29.4.12 Extreme detector
- 29.4.13 Data unit block
- 29.4.14 Signed data format
- 29.4.15 Launching conversions
- 29.4.16 Continuous and fast continuous modes
- 29.4.17 Request precedence
- 29.4.18 Power optimization in run mode
- 29.5 DFSDM interrupts
- 29.6 DFSDM DMA transfer
- 29.7 DFSDM channel y registers (y=0..7)
- 29.7.1 DFSDM channel y configuration register (DFSDM_CHyCFGR1)
- 29.7.2 DFSDM channel y configuration register (DFSDM_CHyCFGR2)
- 29.7.3 DFSDM channel y analog watchdog and short-circuit detector register (DFSDM_CHyAWSCDR)
- 29.7.4 DFSDM channel y watchdog filter data register (DFSDM_CHyWDATR)
- 29.7.5 DFSDM channel y data input register (DFSDM_CHyDATINR)
- 29.8 DFSDM filter x module registers (x=0..3)
- 29.8.1 DFSDM filter x control register 1 (DFSDM_FLTxCR1)
- 29.8.2 DFSDM filter x control register 2 (DFSDM_FLTxCR2)
- 29.8.3 DFSDM filter x interrupt and status register (DFSDM_FLTxISR)
- 29.8.4 DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR)
- 29.8.5 DFSDM filter x injected channel group selection register (DFSDM_FLTxJCHGR)
- 29.8.6 DFSDM filter x control register (DFSDM_FLTxFCR)
- 29.8.7 DFSDM filter x data register for injected group (DFSDM_FLTxJDATAR)
- 29.8.8 DFSDM filter x data register for the regular channel (DFSDM_FLTxRDATAR)
- 29.8.9 DFSDM filter x analog watchdog high threshold register (DFSDM_FLTxAWHTR)
- 29.8.10 DFSDM filter x analog watchdog low threshold register (DFSDM_FLTxAWLTR)
- 29.8.11 DFSDM filter x analog watchdog status register (DFSDM_FLTxAWSR)
- 29.8.12 DFSDM filter x analog watchdog clear flag register (DFSDM_FLTxAWCFR)
- 29.8.13 DFSDM filter x extremes detector maximum register (DFSDM_FLTxEXMAX)
- 29.8.14 DFSDM filter x extremes detector minimum register (DFSDM_FLTxEXMIN)
- 29.8.15 DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR)
- 29.8.16 DFSDM register map
- 30 Digital camera interface (DCMI)
- 30.1 DCMI introduction
- 30.2 DCMI main features
- 30.3 DCMI clocks
- 30.4 DCMI functional overview
- 30.5 Data format description
- 30.6 DCMI interrupts
- 30.7 DCMI register description
- 30.7.1 DCMI control register (DCMI_CR)
- 30.7.2 DCMI status register (DCMI_SR)
- 30.7.3 DCMI raw interrupt status register (DCMI_RIS)
- 30.7.4 DCMI interrupt enable register (DCMI_IER)
- 30.7.5 DCMI masked interrupt status register (DCMI_MIS)
- 30.7.6 DCMI interrupt clear register (DCMI_ICR)
- 30.7.7 DCMI embedded synchronization code register (DCMI_ESCR)
- 30.7.8 DCMI embedded synchronization unmask register (DCMI_ESUR)
- 30.7.9 DCMI crop window start (DCMI_CWSTRT)
- 30.7.10 DCMI crop window size (DCMI_CWSIZE)
- 30.7.11 DCMI data register (DCMI_DR)
- 30.7.12 DCMI register map
- 31 LCD-TFT display controller (LTDC)
- 31.1 Introduction
- 31.2 LTDC main features
- 31.3 LTDC functional description
- 31.4 LTDC programmable parameters
- 31.5 LTDC interrupts
- 31.6 LTDC programming procedure
- 31.7 LTDC registers
- 31.7.1 LTDC synchronization size configuration register (LTDC_SSCR)
- 31.7.2 LTDC back porch configuration register (LTDC_BPCR)
- 31.7.3 LTDC active width configuration register (LTDC_AWCR)
- 31.7.4 LTDC total width configuration register (LTDC_TWCR)
- 31.7.5 LTDC global control register (LTDC_GCR)
- 31.7.6 LTDC shadow reload configuration register (LTDC_SRCR)
- 31.7.7 LTDC background color configuration register (LTDC_BCCR)
- 31.7.8 LTDC interrupt enable register (LTDC_IER)
- 31.7.9 LTDC interrupt status register (LTDC_ISR)
- 31.7.10 LTDC Interrupt Clear Register (LTDC_ICR)
- 31.7.11 LTDC line interrupt position configuration register (LTDC_LIPCR)
- 31.7.12 LTDC current position status register (LTDC_CPSR)
- 31.7.13 LTDC current display status register (LTDC_CDSR)
- 31.7.14 LTDC layer x control register (LTDC_LxCR)
- 31.7.15 LTDC layer x window horizontal position configuration register (LTDC_LxWHPCR)
- 31.7.16 LTDC layer x window vertical position configuration register (LTDC_LxWVPCR)
- 31.7.17 LTDC layer x color keying configuration register (LTDC_LxCKCR)
- 31.7.18 LTDC layer x pixel format configuration register (LTDC_LxPFCR)
- 31.7.19 LTDC layer x constant alpha configuration register (LTDC_LxCACR)
- 31.7.20 LTDC layer x default color configuration register (LTDC_LxDCCR)
- 31.7.21 LTDC layer x blending factors configuration register (LTDC_LxBFCR)
- 31.7.22 LTDC layer x color frame buffer address register (LTDC_LxCFBAR)
- 31.7.23 LTDC layer x color frame buffer length register (LTDC_LxCFBLR)
- 31.7.24 LTDC layer x color frame buffer line number register (LTDC_LxCFBLNR)
- 31.7.25 LTDC layer x CLUT write register (LTDC_LxCLUTWR)
- 31.7.26 LTDC register map
- 32 JPEG codec (JPEG)
- 32.1 Introduction
- 32.2 JPEG codec main features
- 32.3 JPEG codec block functional description
- 32.4 JPEG codec interrupts
- 32.5 JPEG codec registers
- 32.5.1 JPEG codec control register (JPEG_CONFR0)
- 32.5.2 JPEG codec configuration register 1 (JPEG_CONFR1)
- 32.5.3 JPEG codec configuration register 2 (JPEG_CONFR2)
- 32.5.4 JPEG codec configuration register 3 (JPEG_CONFR3)
- 32.5.5 JPEG codec configuration register 4-7 (JPEG_CONFR4-7)
- 32.5.6 JPEG control register (JPEG_CR)
- 32.5.7 JPEG status register (JPEG_SR)
- 32.5.8 JPEG clear flag register (JPEG_CFR)
- 32.5.9 JPEG data input register (JPEG_DIR)
- 32.5.10 JPEG data output register (JPEG_DOR)
- 32.5.11 JPEG codec register map
- 33 True random number generator (RNG)
- 34 Cryptographic processor (CRYP)
- 34.1 Introduction
- 34.2 CRYP main features
- 34.3 CRYP functional description
- 34.3.1 CRYP block diagram
- 34.3.2 CRYP internal signals
- 34.3.3 CRYP DES/TDES cryptographic core
- 34.3.4 CRYP AES cryptographic core
- 34.3.5 CRYP procedure to perform a cipher operation
- 34.3.6 CRYP busy state
- 34.3.7 Preparing the CRYP AES key for decryption
- 34.3.8 CRYP stealing and data padding
- 34.3.9 CRYP suspend/resume operations
- 34.3.10 CRYP DES/TDES basic chaining modes (ECB, CBC)
- 34.3.11 CRYP AES basic chaining modes (ECB, CBC)
- 34.3.12 CRYP AES counter mode (AES-CTR)
- 34.3.13 CRYP AES Galois/counter mode (GCM)
- 34.3.14 CRYP AES Galois message authentication code (GMAC)
- 34.3.15 CRYP AES Counter with CBC-MAC (CCM)
- 34.3.16 CRYP data registers and data swapping
- 34.3.17 CRYP key registers
- 34.3.18 CRYP initialization vector registers
- 34.3.19 CRYP DMA interface
- 34.3.20 CRYP error management
- 34.4 CRYP interrupts
- 34.5 CRYP processing time
- 34.6 CRYP registers
- 34.6.1 CRYP control register (CRYP_CR)
- 34.6.2 CRYP status register (CRYP_SR)
- 34.6.3 CRYP data input register (CRYP_DIN)
- 34.6.4 CRYP data output register (CRYP_DOUT)
- 34.6.5 CRYP DMA control register (CRYP_DMACR)
- 34.6.6 CRYP interrupt mask set/clear register (CRYP_IMSCR)
- 34.6.7 CRYP raw interrupt status register (CRYP_RISR)
- 34.6.8 CRYP masked interrupt status register (CRYP_MISR)
- 34.6.9 CRYP key register 0L (CRYP_K0LR)
- 34.6.10 CRYP key register 0R (CRYP_K0RR)
- 34.6.11 CRYP key register 1L (CRYP_K1LR)
- 34.6.12 CRYP key register 1R (CRYP_K1RR)
- 34.6.13 CRYP key register 2L (CRYP_K2LR)
- 34.6.14 CRYP key register 2R (CRYP_K2RR)
- 34.6.15 CRYP key register 3L (CRYP_K3LR)
- 34.6.16 CRYP key register 3R (CRYP_K3RR)
- 34.6.17 CRYP initialization vector register 0L (CRYP_IV0LR)
- 34.6.18 CRYP initialization vector register 0R (CRYP_IV0RR)
- 34.6.19 CRYP initialization vector register 1L (CRYP_IV1LR)
- 34.6.20 CRYP initialization vector register 1R (CRYP_IV1RR)
- 34.6.21 CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR)
- 34.6.22 CRYP context swap GCM registers (CRYP_CSGCMxR)
- 34.6.23 CRYP register map
- 35 Hash processor (HASH)
- 35.1 Introduction
- 35.2 HASH main features
- 35.3 HASH functional description
- 35.4 HASH interrupts
- 35.5 HASH processing time
- 35.6 HASH registers
- 35.6.1 HASH control register (HASH_CR)
- 35.6.2 HASH data input register (HASH_DIN)
- 35.6.3 HASH start register (HASH_STR)
- 35.6.4 HASH digest registers (HASH_HR0..7)
- 35.6.5 HASH interrupt enable register (HASH_IMR)
- 35.6.6 HASH status register (HASH_SR)
- 35.6.7 HASH context swap registers (HASH_CSRx)
- 35.6.8 HASH register map
- 36 High-Resolution Timer (HRTIM)
- 36.1 Introduction
- 36.2 Main features
- 36.3 Functional description
- 36.3.1 General description
- 36.3.2 HRTIM pins and internal signals
- 36.3.3 Clocks
- 36.3.4 Timer A..E timing units
- 36.3.5 Master timer
- 36.3.6 Set/reset events priorities and narrow pulses management
- 36.3.7 External events global conditioning
- 36.3.8 External event filtering in timing units
- 36.3.9 Delayed Protection
- 36.3.10 Register preload and update management
- 36.3.11 Events propagation within or across multiple timers
- 36.3.12 Output management
- 36.3.13 Burst mode controller
- 36.3.14 Chopper
- 36.3.15 Fault protection
- 36.3.16 Auxiliary outputs
- 36.3.17 Synchronizing the HRTIM with other timers or HRTIM instances
- 36.3.18 ADC triggers
- 36.3.19 DAC triggers
- 36.3.20 HRTIM Interrupts
- 36.3.21 DMA
- 36.3.22 HRTIM initialization
- 36.3.23 Debug
- 36.4 Application use cases
- 36.5 HRTIM registers
- 36.5.1 HRTIM Master Timer Control Register (HRTIM_MCR)
- 36.5.2 HRTIM Master Timer Interrupt Status Register (HRTIM_MISR)
- 36.5.3 HRTIM Master Timer Interrupt Clear Register (HRTIM_MICR)
- 36.5.4 HRTIM Master Timer DMA / Interrupt Enable Register (HRTIM_MDIER)
- 36.5.5 HRTIM Master Timer Counter Register (HRTIM_MCNTR)
- 36.5.6 HRTIM Master Timer Period Register (HRTIM_MPER)
- 36.5.7 HRTIM Master Timer Repetition Register (HRTIM_MREP)
- 36.5.8 HRTIM Master Timer Compare 1 Register (HRTIM_MCMP1R)
- 36.5.9 HRTIM Master Timer Compare 2 Register (HRTIM_MCMP2R)
- 36.5.10 HRTIM Master Timer Compare 3 Register (HRTIM_MCMP3R)
- 36.5.11 HRTIM Master Timer Compare 4 Register (HRTIM_MCMP4R)
- 36.5.12 HRTIM Timerx Control Register (HRTIM_TIMxCR)
- 36.5.13 HRTIM Timerx Interrupt Status Register (HRTIM_TIMxISR)
- 36.5.14 HRTIM Timerx Interrupt Clear Register (HRTIM_TIMxICR)
- 36.5.15 HRTIM Timerx DMA / Interrupt Enable Register (HRTIM_TIMxDIER)
- 36.5.16 HRTIM Timerx Counter Register (HRTIM_CNTxR)
- 36.5.17 HRTIM Timerx Period Register (HRTIM_PERxR)
- 36.5.18 HRTIM Timerx Repetition Register (HRTIM_REPxR)
- 36.5.19 HRTIM Timerx Compare 1 Register (HRTIM_CMP1xR)
- 36.5.20 HRTIM Timerx Compare 1 Compound Register (HRTIM_CMP1CxR)
- 36.5.21 HRTIM Timerx Compare 2 Register (HRTIM_CMP2xR)
- 36.5.22 HRTIM Timerx Compare 3 Register (HRTIM_CMP3xR)
- 36.5.23 HRTIM Timerx Compare 4 Register (HRTIM_CMP4xR)
- 36.5.24 HRTIM Timerx Capture 1 Register (HRTIM_CPT1xR)
- 36.5.25 HRTIM Timerx Capture 2 Register (HRTIM_CPT2xR)
- 36.5.26 HRTIM Timerx Deadtime Register (HRTIM_DTxR)
- 36.5.27 HRTIM Timerx Output1 Set Register (HRTIM_SETx1R)
- 36.5.28 HRTIM Timerx Output1 Reset Register (HRTIM_RSTx1R)
- 36.5.29 HRTIM Timerx Output2 Set Register (HRTIM_SETx2R)
- 36.5.30 HRTIM Timerx Output2 Reset Register (HRTIM_RSTx2R)
- 36.5.31 HRTIM Timerx External Event Filtering Register 1 (HRTIM_EEFxR1)
- 36.5.32 HRTIM Timerx External Event Filtering Register 2 (HRTIM_EEFxR2)
- 36.5.33 HRTIM Timerx Reset Register (HRTIM_RSTxR)
- 36.5.34 HRTIM Timerx Chopper Register (HRTIM_CHPxR)
- 36.5.35 HRTIM Timerx Capture 1 Control Register (HRTIM_CPT1xCR)
- 36.5.36 HRTIM Timerx Capture 2 Control Register (HRTIM_CPT2xCR)
- 36.5.37 HRTIM Timerx Output Register (HRTIM_OUTxR)
- 36.5.38 HRTIM Timerx Fault Register (HRTIM_FLTxR)
- 36.5.39 HRTIM Control Register 1 (HRTIM_CR1)
- 36.5.40 HRTIM Control Register 2 (HRTIM_CR2)
- 36.5.41 HRTIM Interrupt Status Register (HRTIM_ISR)
- 36.5.42 HRTIM Interrupt Clear Register (HRTIM_ICR)
- 36.5.43 HRTIM Interrupt Enable Register (HRTIM_IER)
- 36.5.44 HRTIM Output Enable Register (HRTIM_OENR)
- 36.5.45 HRTIM Output Disable Register (HRTIM_ODISR)
- 36.5.46 HRTIM Output Disable Status Register (HRTIM_ODSR)
- 36.5.47 HRTIM Burst Mode Control Register (HRTIM_BMCR)
- 36.5.48 HRTIM Burst Mode Trigger Register (HRTIM_BMTRGR)
- 36.5.49 HRTIM Burst Mode Compare Register (HRTIM_BMCMPR)
- 36.5.50 HRTIM Burst Mode Period Register (HRTIM_BMPER)
- 36.5.51 HRTIM Timer External Event Control Register 1 (HRTIM_EECR1)
- 36.5.52 HRTIM Timer External Event Control Register 2 (HRTIM_EECR2)
- 36.5.53 HRTIM Timer External Event Control Register 3 (HRTIM_EECR3)
- 36.5.54 HRTIM ADC Trigger 1 Register (HRTIM_ADC1R)
- 36.5.55 HRTIM ADC Trigger 2 Register (HRTIM_ADC2R)
- 36.5.56 HRTIM ADC Trigger 3 Register (HRTIM_ADC3R)
- 36.5.57 HRTIM ADC Trigger 4 Register (HRTIM_ADC4R)
- 36.5.58 HRTIM Fault Input Register 1 (HRTIM_FLTINR1)
- 36.5.59 HRTIM Fault Input Register 2 (HRTIM_FLTINR2)
- 36.5.60 HRTIM Burst DMA Master timer update Register (HRTIM_BDMUPR)
- 36.5.61 HRTIM Burst DMA Timerx update Register (HRTIM_BDTxUPR)
- 36.5.62 HRTIM Burst DMA Data Register (HRTIM_BDMADR)
- 36.5.63 HRTIM register map
- 37 Advanced-control timers (TIM1/TIM8)
- 37.1 TIM1/TIM8 introduction
- 37.2 TIM1/TIM8 main features
- 37.3 TIM1/TIM8 functional description
- 37.3.1 Time-base unit
- 37.3.2 Counter modes
- 37.3.3 Repetition counter
- 37.3.4 External trigger input
- 37.3.5 Clock selection
- 37.3.6 Capture/compare channels
- 37.3.7 Input capture mode
- 37.3.8 PWM input mode
- 37.3.9 Forced output mode
- 37.3.10 Output compare mode
- 37.3.11 PWM mode
- 37.3.12 Asymmetric PWM mode
- 37.3.13 Combined PWM mode
- 37.3.14 Combined 3-phase PWM mode
- 37.3.15 Complementary outputs and dead-time insertion
- 37.3.16 Using the break function
- 37.3.17 Bidirectional break inputs
- 37.3.18 Clearing the OCxREF signal on an external event
- 37.3.19 6-step PWM generation
- 37.3.20 One-pulse mode
- 37.3.21 Retriggerable one pulse mode (OPM)
- 37.3.22 Encoder interface mode
- 37.3.23 UIF bit remapping
- 37.3.24 Timer input XOR function
- 37.3.25 Interfacing with Hall sensors
- 37.3.26 Timer synchronization
- 37.3.27 ADC synchronization
- 37.3.28 DMA burst mode
- 37.3.29 Debug mode
- 37.4 TIM1/TIM8 registers
- 37.4.1 TIM1/TIM8 control register 1 (TIMx_CR1)
- 37.4.2 TIM1/TIM8 control register 2 (TIMx_CR2)
- 37.4.3 TIM1/TIM8 slave mode control register (TIMx_SMCR)
- 37.4.4 TIM1/TIM8 DMA/interrupt enable register (TIMx_DIER)
- 37.4.5 TIM1/TIM8 status register (TIMx_SR)
- 37.4.6 TIM1/TIM8 event generation register (TIMx_EGR)
- 37.4.7 TIM1/TIM8 capture/compare mode register 1 (TIMx_CCMR1)
- 37.4.8 TIM1/TIM8 capture/compare mode register 2 (TIMx_CCMR2)
- 37.4.9 TIM1/TIM8 capture/compare enable register (TIMx_CCER)
- 37.4.10 TIM1/TIM8 counter (TIMx_CNT)
- 37.4.11 TIM1/TIM8 prescaler (TIMx_PSC)
- 37.4.12 TIM1/TIM8 auto-reload register (TIMx_ARR)
- 37.4.13 TIM1/TIM8 repetition counter register (TIMx_RCR)
- 37.4.14 TIM1/TIM8 capture/compare register 1 (TIMx_CCR1)
- 37.4.15 TIM1/TIM8 capture/compare register 2 (TIMx_CCR2)
- 37.4.16 TIM1/TIM8 capture/compare register 3 (TIMx_CCR3)
- 37.4.17 TIM1/TIM8 capture/compare register 4 (TIMx_CCR4)
- 37.4.18 TIM1/TIM8 break and dead-time register (TIMx_BDTR)
- 37.4.19 TIM1/TIM8 DMA control register (TIMx_DCR)
- 37.4.20 TIM1/TIM8 DMA address for full transfer (TIMx_DMAR)
- 37.4.21 TIM1/TIM8 capture/compare mode register 3 (TIMx_CCMR3)
- 37.4.22 TIM1/TIM8 capture/compare register 5 (TIMx_CCR5)
- 37.4.23 TIM1/TIM8 capture/compare register 6 (TIMx_CCR6)
- 37.4.24 TIM1 alternate function option register 1 (TIM1_AF1)
- 37.4.25 TIM1 Alternate function register 2 (TIM1_AF2)
- 37.4.26 TIM8 Alternate function option register 1 (TIM8_AF1)
- 37.4.27 TIM8 Alternate function option register 2 (TIM8_AF2)
- 37.4.28 TIM1 timer input selection register (TIM1_TISEL)
- 37.4.29 TIM8 timer input selection register (TIM8_TISEL)
- 37.4.30 TIM1 register map
- 37.4.31 TIM8 register map
- 38 General-purpose timers (TIM2/TIM3/TIM4/TIM5)
- 38.1 TIM2/TIM3/TIM4/TIM5 introduction
- 38.2 TIM2/TIM3/TIM4/TIM5 main features
- 38.3 TIM2/TIM3/TIM4/TIM5 functional description
- 38.3.1 Time-base unit
- 38.3.2 Counter modes
- 38.3.3 Clock selection
- 38.3.4 Capture/Compare channels
- 38.3.5 Input capture mode
- 38.3.6 PWM input mode
- 38.3.7 Forced output mode
- 38.3.8 Output compare mode
- 38.3.9 PWM mode
- 38.3.10 Asymmetric PWM mode
- 38.3.11 Combined PWM mode
- 38.3.12 Clearing the OCxREF signal on an external event
- 38.3.13 One-pulse mode
- 38.3.14 Retriggerable one pulse mode (OPM)
- 38.3.15 Encoder interface mode
- 38.3.16 UIF bit remapping
- 38.3.17 Timer input XOR function
- 38.3.18 Timers and external trigger synchronization
- 38.3.19 Timer synchronization
- 38.3.20 DMA burst mode
- 38.3.21 Debug mode
- 38.4 TIM2/TIM3/TIM4/TIM5 registers
- 38.4.1 TIMx control register 1 (TIMx_CR1)
- 38.4.2 TIMx control register 2 (TIMx_CR2)
- 38.4.3 TIMx slave mode control register (TIMx_SMCR)
- 38.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)
- 38.4.5 TIMx status register (TIMx_SR)
- 38.4.6 TIMx event generation register (TIMx_EGR)
- 38.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)
- 38.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)
- 38.4.9 TIMx capture/compare enable register (TIMx_CCER)
- 38.4.10 TIMx counter (TIMx_CNT)
- 38.4.11 TIMx prescaler (TIMx_PSC)
- 38.4.12 TIMx auto-reload register (TIMx_ARR)
- 38.4.13 TIMx capture/compare register 1 (TIMx_CCR1)
- 38.4.14 TIMx capture/compare register 2 (TIMx_CCR2)
- 38.4.15 TIMx capture/compare register 3 (TIMx_CCR3)
- 38.4.16 TIMx capture/compare register 4 (TIMx_CCR4)
- 38.4.17 TIMx DMA control register (TIMx_DCR)
- 38.4.18 TIMx DMA address for full transfer (TIMx_DMAR)
- 38.4.19 TIM2 alternate function option register 1 (TIM2_AF1)
- 38.4.20 TIM3 alternate function option register 1 (TIM3_AF1)
- 38.4.21 TIM4 alternate function option register 1 (TIM4_AF1)
- 38.4.22 TIM5 alternate function option register 1 (TIM5_AF1)
- 38.4.23 TIM2 timer input selection register (TIM2_TISEL)
- 38.4.24 TIM3 timer input selection register (TIM3_TISEL)
- 38.4.25 TIM4 timer input selection register (TIM4_TISEL)
- 38.4.26 TIM5 timer input selection register (TIM5_TISEL)
- 38.4.27 TIMx register map
- 39 General-purpose timers (TIM12/TIM13/TIM14)
- 39.1 TIM12/TIM13/TIM14 introduction
- 39.2 TIM12/TIM13/TIM14 main features
- 39.3 TIM12/TIM13/TIM14 functional description
- 39.3.1 Time-base unit
- 39.3.2 Counter modes
- 39.3.3 Clock selection
- 39.3.4 Capture/compare channels
- 39.3.5 Input capture mode
- 39.3.6 PWM input mode (only for TIM12)
- 39.3.7 Forced output mode
- 39.3.8 Output compare mode
- 39.3.9 PWM mode
- 39.3.10 Combined PWM mode (TIM12 only)
- 39.3.11 One-pulse mode
- 39.3.12 Retriggerable one pulse mode (OPM) (TIM12 only)
- 39.3.13 UIF bit remapping
- 39.3.14 Timer input XOR function
- 39.3.15 TIM12 external trigger synchronization
- 39.3.16 Slave mode – combined reset + trigger mode
- 39.3.17 Timer synchronization (TIM12)
- 39.3.18 Debug mode
- 39.4 TIM12 registers
- 39.4.1 TIM12 control register 1 (TIMx_CR1)
- 39.4.2 TIM12 slave mode control register (TIMx_SMCR)
- 39.4.3 TIM12 Interrupt enable register (TIMx_DIER)
- 39.4.4 TIM12 status register (TIMx_SR)
- 39.4.5 TIM12 event generation register (TIMx_EGR)
- 39.4.6 TIM12 capture/compare mode register 1 (TIMx_CCMR1)
- 39.4.7 TIM12 capture/compare enable register (TIMx_CCER)
- 39.4.8 TIM12 counter (TIMx_CNT)
- 39.4.9 TIM12 prescaler (TIMx_PSC)
- 39.4.10 TIM12 auto-reload register (TIMx_ARR)
- 39.4.11 TIM12 capture/compare register 1 (TIMx_CCR1)
- 39.4.12 TIM12 capture/compare register 2 (TIMx_CCR2)
- 39.4.13 TIM12 timer input selection register (TIM12_TISEL)
- 39.4.14 TIM12 register map
- 39.5 TIM13/TIM14 registers
- 39.5.1 TIM13/TIM14 control register 1 (TIMx_CR1)
- 39.5.2 TIM13/TIM14 Interrupt enable register (TIMx_DIER)
- 39.5.3 TIM13/TIM14 status register (TIMx_SR)
- 39.5.4 TIM13/TIM14 event generation register (TIMx_EGR)
- 39.5.5 TIM13/TIM14 capture/compare mode register 1 (TIMx_CCMR1)
- 39.5.6 TIM13/TIM14 capture/compare enable register (TIMx_CCER)
- 39.5.7 TIM13/TIM14 counter (TIMx_CNT)
- 39.5.8 TIM13/TIM14 prescaler (TIMx_PSC)
- 39.5.9 TIM13/TIM14 auto-reload register (TIMx_ARR)
- 39.5.10 TIM13/TIM14 capture/compare register 1 (TIMx_CCR1)
- 39.5.11 TIM13 timer input selection register (TIM13_TISEL)
- 39.5.12 TIM14 timer input selection register (TIM14_TISEL)
- 39.5.13 TIM13/TIM14 register map
- 40 General-purpose timers (TIM15/TIM16/TIM17)
- 40.1 TIM15/TIM16/TIM17 introduction
- 40.2 TIM15 main features
- 40.3 TIM16/TIM17 main features
- 40.4 TIM15/TIM16/TIM17 functional description
- 40.4.1 Time-base unit
- 40.4.2 Counter modes
- 40.4.3 Repetition counter
- 40.4.4 Clock selection
- 40.4.5 Capture/compare channels
- 40.4.6 Input capture mode
- 40.4.7 PWM input mode (only for TIM15)
- 40.4.8 Forced output mode
- 40.4.9 Output compare mode
- 40.4.10 PWM mode
- 40.4.11 Combined PWM mode (TIM15 only)
- 40.4.12 Complementary outputs and dead-time insertion
- 40.4.13 Using the break function
- 40.4.14 One-pulse mode
- 40.4.15 Retriggerable one pulse mode (OPM) (TIM15 only)
- 40.4.16 UIF bit remapping
- 40.4.17 Timer input XOR function (TIM15 only)
- 40.4.18 External trigger synchronization (TIM15 only)
- 40.4.19 Slave mode – combined reset + trigger mode
- 40.4.20 DMA burst mode
- 40.4.21 Timer synchronization (TIM15)
- 40.4.22 Debug mode
- 40.5 TIM15 registers
- 40.5.1 TIM15 control register 1 (TIM15_CR1)
- 40.5.2 TIM15 control register 2 (TIM15_CR2)
- 40.5.3 TIM15 slave mode control register (TIM15_SMCR)
- 40.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER)
- 40.5.5 TIM15 status register (TIM15_SR)
- 40.5.6 TIM15 event generation register (TIM15_EGR)
- 40.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1)
- 40.5.8 TIM15 capture/compare enable register (TIM15_CCER)
- 40.5.9 TIM15 counter (TIM15_CNT)
- 40.5.10 TIM15 prescaler (TIM15_PSC)
- 40.5.11 TIM15 auto-reload register (TIM15_ARR)
- 40.5.12 TIM15 repetition counter register (TIM15_RCR)
- 40.5.13 TIM15 capture/compare register 1 (TIM15_CCR1)
- 40.5.14 TIM15 capture/compare register 2 (TIM15_CCR2)
- 40.5.15 TIM15 break and dead-time register (TIM15_BDTR)
- 40.5.16 TIM15 DMA control register (TIM15_DCR)
- 40.5.17 TIM15 DMA address for full transfer (TIM15_DMAR)
- 40.5.18 TIM15 alternate register 1 (TIM15_AF1)
- 40.5.19 TIM15 input selection register (TIM15_TISEL)
- 40.5.20 TIM15 register map
- 40.6 TIM16/TIM17 registers
- 40.6.1 TIM16/TIM17 control register 1 (TIMx_CR1)
- 40.6.2 TIM16/TIM17 control register 2 (TIMx_CR2)
- 40.6.3 TIM16/TIM17 DMA/interrupt enable register (TIMx_DIER)
- 40.6.4 TIM16/TIM17 status register (TIMx_SR)
- 40.6.5 TIM16/TIM17 event generation register (TIMx_EGR)
- 40.6.6 TIM16/TIM17 capture/compare mode register 1 (TIMx_CCMR1)
- 40.6.7 TIM16/TIM17 capture/compare enable register (TIMx_CCER)
- 40.6.8 TIM16/TIM17 counter (TIMx_CNT)
- 40.6.9 TIM16/TIM17 prescaler (TIMx_PSC)
- 40.6.10 TIM16/TIM17 auto-reload register (TIMx_ARR)
- 40.6.11 TIM16/TIM17 repetition counter register (TIMx_RCR)
- 40.6.12 TIM16/TIM17 capture/compare register 1 (TIMx_CCR1)
- 40.6.13 TIM16/TIM17 break and dead-time register (TIMx_BDTR)
- 40.6.14 TIM16/TIM17 DMA control register (TIMx_DCR)
- 40.6.15 TIM16/TIM17 DMA address for full transfer (TIMx_DMAR)
- 40.6.16 TIM16 alternate function register 1 (TIM16_AF1)
- 40.6.17 TIM16 input selection register (TIM16_TISEL)
- 40.6.18 TIM17 alternate function register 1 (TIM17_AF1)
- 40.6.19 TIM17 input selection register (TIM17_TISEL)
- 40.6.20 TIM16/TIM17 register map
- 41 Basic timers (TIM6/TIM7)
- 41.1 TIM6/TIM7 introduction
- 41.2 TIM6/TIM7 main features
- 41.3 TIM6/TIM7 functional description
- 41.4 TIM6/TIM7 registers
- 41.4.1 TIM6/TIM7 control register 1 (TIMx_CR1)
- 41.4.2 TIM6/TIM7 control register 2 (TIMx_CR2)
- 41.4.3 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER)
- 41.4.4 TIM6/TIM7 status register (TIMx_SR)
- 41.4.5 TIM6/TIM7 event generation register (TIMx_EGR)
- 41.4.6 TIM6/TIM7 counter (TIMx_CNT)
- 41.4.7 TIM6/TIM7 prescaler (TIMx_PSC)
- 41.4.8 TIM6/TIM7 auto-reload register (TIMx_ARR)
- 41.4.9 TIM6/TIM7 register map
- 42 Low-power timer (LPTIM)
- 42.1 Introduction
- 42.2 LPTIM main features
- 42.3 LPTIM implementation
- 42.4 LPTIM functional description
- 42.4.1 LPTIM block diagram
- 42.4.2 LPTIM pins and internal signals
- 42.4.3 LPTIM input and trigger mapping
- 42.4.4 LPTIM reset and clocks
- 42.4.5 Glitch filter
- 42.4.6 Prescaler
- 42.4.7 Trigger multiplexer
- 42.4.8 Operating mode
- 42.4.9 Timeout function
- 42.4.10 Waveform generation
- 42.4.11 Register update
- 42.4.12 Counter mode
- 42.4.13 Timer enable
- 42.4.14 Timer counter reset
- 42.4.15 Encoder mode
- 42.4.16 Debug mode
- 42.5 LPTIM low-power modes
- 42.6 LPTIM interrupts
- 42.7 LPTIM registers
- 42.7.1 LPTIM interrupt and status register (LPTIM_ISR)
- 42.7.2 LPTIM interrupt clear register (LPTIM_ICR)
- 42.7.3 LPTIM interrupt enable register (LPTIM_IER)
- 42.7.4 LPTIM configuration register (LPTIM_CFGR)
- 42.7.5 LPTIM control register (LPTIM_CR)
- 42.7.6 LPTIM compare register (LPTIM_CMP)
- 42.7.7 LPTIM autoreload register (LPTIM_ARR)
- 42.7.8 LPTIM counter register (LPTIM_CNT)
- 42.7.9 LPTIM configuration register 2 (LPTIM_CFGR2)
- 42.7.10 LPTIM3 configuration register 2 (LPTIM3_CFGR2)
- 42.7.11 LPTIM register map
- 43 System window watchdog (WWDG)
- 44 Independent watchdog (IWDG)
- 45 Real-time clock (RTC)
- 45.1 Introduction
- 45.2 RTC main features
- 45.3 RTC functional description
- 45.3.1 RTC block diagram
- 45.3.2 RTC pins and internal signals
- 45.3.3 GPIOs controlled by the RTC
- 45.3.4 Clock and prescalers
- 45.3.5 Real-time clock and calendar
- 45.3.6 Programmable alarms
- 45.3.7 Periodic auto-wakeup
- 45.3.8 RTC initialization and configuration
- 45.3.9 Reading the calendar
- 45.3.10 Resetting the RTC
- 45.3.11 RTC synchronization
- 45.3.12 RTC reference clock detection
- 45.3.13 RTC smooth digital calibration
- 45.3.14 Time-stamp function
- 45.3.15 Tamper detection
- 45.3.16 Calibration clock output
- 45.3.17 Alarm output
- 45.4 RTC low-power modes
- 45.5 RTC interrupts
- 45.6 RTC registers
- 45.6.1 RTC time register (RTC_TR)
- 45.6.2 RTC date register (RTC_DR)
- 45.6.3 RTC control register (RTC_CR)
- 45.6.4 RTC initialization and status register (RTC_ISR)
- 45.6.5 RTC prescaler register (RTC_PRER)
- 45.6.6 RTC wakeup timer register (RTC_WUTR)
- 45.6.7 RTC alarm A register (RTC_ALRMAR)
- 45.6.8 RTC alarm B register (RTC_ALRMBR)
- 45.6.9 RTC write protection register (RTC_WPR)
- 45.6.10 RTC sub second register (RTC_SSR)
- 45.6.11 RTC shift control register (RTC_SHIFTR)
- 45.6.12 RTC timestamp time register (RTC_TSTR)
- 45.6.13 RTC timestamp date register (RTC_TSDR)
- 45.6.14 RTC time-stamp sub second register (RTC_TSSSR)
- 45.6.15 RTC calibration register (RTC_CALR)
- 45.6.16 RTC tamper configuration register (RTC_TAMPCR)
- 45.6.17 RTC alarm A sub second register (RTC_ALRMASSR)
- 45.6.18 RTC alarm B sub second register (RTC_ALRMBSSR)
- 45.6.19 RTC option register (RTC_OR)
- 45.6.20 RTC backup registers (RTC_BKPxR)
- 45.6.21 RTC register map
- 46 Inter-integrated circuit (I2C) interface
- 46.1 Introduction
- 46.2 I2C main features
- 46.3 I2C implementation
- 46.4 I2C functional description
- 46.4.1 I2C block diagram
- 46.4.2 I2C clock requirements
- 46.4.3 Mode selection
- 46.4.4 I2C initialization
- 46.4.5 Software reset
- 46.4.6 Data transfer
- 46.4.7 I2C slave mode
- 46.4.8 I2C master mode
- 46.4.9 I2C_TIMINGR register configuration examples
- 46.4.10 SMBus specific features
- 46.4.11 SMBus initialization
- 46.4.12 SMBus: I2C_TIMEOUTR register configuration examples
- 46.4.13 SMBus slave mode
- 46.4.14 Wakeup from Stop mode on address match
- 46.4.15 Error conditions
- 46.4.16 DMA requests
- 46.4.17 Debug mode
- 46.5 I2C low-power modes
- 46.6 I2C interrupts
- 46.7 I2C registers
- 46.7.1 I2C2 control register 1 (I2C_CR1)
- 46.7.2 I2C2 control register 2 (I2C_CR2)
- 46.7.3 I2C2 own address 1 register (I2C_OAR1)
- 46.7.4 I2C2 own address 2 register (I2C_OAR2)
- 46.7.5 I2C2 timing register (I2C_TIMINGR)
- 46.7.6 I2C2 timeout register (I2C_TIMEOUTR)
- 46.7.7 I2C2 interrupt and status register (I2C_ISR)
- 46.7.8 I2C2 interrupt clear register (I2C_ICR)(
- 46.7.9 I2C2 PEC register (I2C_PECR)
- 46.7.10 I2C2 receive data register (I2C_RXDR)
- 46.7.11 I2C2 transmit data register (I2C_TXDR)
- 46.7.12 I2C register map
- 47 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmitter (UART)
- 47.1 USART introduction
- 47.2 USART main features
- 47.3 USART extended features
- 47.4 USART implementation
- 47.5 USART functional description
- 47.5.1 USART block diagram
- 47.5.2 USART signals
- 47.5.3 USART character description
- 47.5.4 USART FIFOs and thresholds
- 47.5.5 USART transmitter
- 47.5.6 USART receiver
- 47.5.7 USART baud rate generation
- 47.5.8 Tolerance of the USART receiver to clock deviation
- 47.5.9 USART Auto baud rate detection
- 47.5.10 USART multiprocessor communication
- 47.5.11 USART Modbus communication
- 47.5.12 USART parity control
- 47.5.13 USART LIN (local interconnection network) mode
- 47.5.14 USART synchronous mode
- 47.5.15 USART single-wire Half-duplex communication
- 47.5.16 USART receiver timeout
- 47.5.17 USART Smartcard mode
- 47.5.18 USART IrDA SIR ENDEC block
- 47.5.19 Continuous communication using USART and DMA
- 47.5.20 RS232 Hardware flow control and RS485 Driver Enable
- 47.5.21 USART low-power management
- 47.6 USART interrupts
- 47.7 USART registers
- 47.7.1 USART control register 1 (USART_CR1)
- 47.7.2 USART control register 2 (USART_CR2)
- 47.7.3 USART control register 3 (USART_CR3)
- 47.7.4 USART baud rate register (USART_BRR)
- 47.7.5 USART guard time and prescaler register (USART_GTPR)
- 47.7.6 USART receiver timeout register (USART_RTOR)
- 47.7.7 USART request register (USART_RQR)
- 47.7.8 USART interrupt and status register (USART_ISR)
- 47.7.9 USART interrupt flag clear register (USART_ICR)
- 47.7.10 USART receive data register (USART_RDR)
- 47.7.11 USART transmit data register (USART_TDR)
- 47.7.12 USART prescaler register (USART_PRESC)
- 47.7.13 USART register map
- 48 Low-power universal asynchronous receiver transmitter (LPUART)
- 48.1 LPUART introduction
- 48.2 LPUART main features
- 48.3 LPUART functional description
- 48.3.1 LPUART block diagram
- 48.3.2 LPUART signals
- 48.3.3 LPUART character description
- 48.3.4 LPUART FIFOs and thresholds
- 48.3.5 LPUART transmitter
- 48.3.6 LPUART receiver
- 48.3.7 LPUART baud rate generation
- 48.3.8 Tolerance of the LPUART receiver to clock deviation
- 48.3.9 LPUART multiprocessor communication
- 48.3.10 LPUART parity control
- 48.3.11 LPUART single-wire Half-duplex communication
- 48.3.12 Continuous communication using DMA and LPUART
- 48.3.13 RS232 Hardware flow control and RS485 Driver Enable
- 48.3.14 LPUART low-power management
- 48.4 LPUART interrupts
- 48.5 LPUART registers
- 48.5.1 Control register 1 (LPUART_CR1)
- 48.5.2 Control register 2 (LPUART_CR2)
- 48.5.3 Control register 3 (LPUART_CR3)
- 48.5.4 Baud rate register (LPUART_BRR)
- 48.5.5 Request register (LPUART_RQR)
- 48.5.6 Interrupt and status register (LPUART_ISR)
- 48.5.7 Interrupt flag clear register (LPUART_ICR)
- 48.5.8 Receive data register (LPUART_RDR)
- 48.5.9 Transmit data register (LPUART_TDR)
- 48.5.10 Prescaler register (LPUART_PRESC)
- 48.5.11 LPUART register map
- 49 Serial peripheral interface (SPI)
- 49.1 Introduction
- 49.2 SPI main features
- 49.3 SPI implementation
- 49.4 SPI functional description
- 49.4.1 SPI block diagram
- 49.4.2 SPI signals
- 49.4.3 SPI communication general aspects
- 49.4.4 Communications between one master and one slave
- 49.4.5 Standard multi-slave communication
- 49.4.6 Multi-master communication
- 49.4.7 Slave select (SS) pin management
- 49.4.8 Communication formats
- 49.4.9 Configuration of SPI
- 49.4.10 Procedure for enabling SPI
- 49.4.11 SPI data transmission and reception procedures
- 49.4.12 Procedure for disabling the SPI
- 49.4.13 Data packing
- 49.4.14 Communication using DMA (direct memory addressing)
- 49.5 SPI specific modes and control
- 49.6 Low-power mode management
- 49.7 SPI wakeup and interrupts
- 49.8 I2S main features
- 49.9 I2S functional description
- 49.9.1 I2S general description
- 49.9.2 Pin sharing with SPI function
- 49.9.3 Bits and fields usable in I2S/PCM mode
- 49.9.4 Slave and master modes
- 49.9.5 Supported audio protocols
- 49.9.6 Additional Serial Interface Flexibility
- 49.9.7 Start-up sequence
- 49.9.8 Stop sequence
- 49.9.9 Clock generator
- 49.9.10 Internal FIFOs
- 49.9.11 FIFOs status flags
- 49.9.12 Handling of underrun situation
- 49.9.13 Handling of overrun situation
- 49.9.14 Frame error detection
- 49.9.15 DMA Interface
- 49.9.16 Programing examples
- 49.9.17 Slave I2S Philips standard, receive
- 49.10 I2S wakeup and interrupts
- 49.11 SPI/I2S registers
- 49.11.1 SPI/I2S control register 1 (SPI2S_CR1)
- 49.11.2 SPI control register 2 (SPI_CR2)
- 49.11.3 SPI configuration register 1 (SPI_CFG1)
- 49.11.4 SPI configuration register 2 (SPI_CFG2)
- 49.11.5 SPI/I2S interrupt enable register (SPI2S_IER)
- 49.11.6 SPI/I2S status register (SPI2S_SR)
- 49.11.7 SPI/I2S interrupt/status flags clear register (SPI2S_IFCR)
- 49.11.8 SPI/I2S transmit data register (SPI2S_TXDR)
- 49.11.9 SPI/I2S receive data register (SPI2S_RXDR)
- 49.11.10 SPI polynomial register (SPI_CRCPOLY)
- 49.11.11 SPI transmitter CRC register (SPI_TXCRC)
- 49.11.12 SPI receiver CRC register (SPI_RXCRC)
- 49.11.13 SPI underrun data register (SPI_UDRDR)
- 49.11.14 SPI/I2S configuration register (SPI_I2SCFGR)
- 49.12 SPI register map and reset values
- 50 Serial audio interface (SAI)
- 50.1 Introduction
- 50.2 SAI main features
- 50.3 SAI functional description
- 50.3.1 SAI block diagram
- 50.3.2 SAI pins and internal signals
- 50.3.3 Main SAI modes
- 50.3.4 SAI synchronization mode
- 50.3.5 Audio data size
- 50.3.6 Frame synchronization
- 50.3.7 Slot configuration
- 50.3.8 SAI clock generator
- 50.3.9 Internal FIFOs
- 50.3.10 PDM Interface
- 50.3.11 AC’97 link controller
- 50.3.12 SPDIF output
- 50.3.13 Specific features
- 50.3.14 Error flags
- 50.3.15 Disabling the SAI
- 50.3.16 SAI DMA interface
- 50.4 SAI interrupts
- 50.5 SAI registers
- 50.5.1 Global configuration register (SAI_GCR)
- 50.5.2 Configuration register 1 (SAI_ACR1)
- 50.5.3 Configuration register 1 (SAI_BCR1)
- 50.5.4 Configuration register 2 (SAI_ACR2)
- 50.5.5 Configuration register 2 (SAI_BCR2)
- 50.5.6 Frame configuration register (SAI_AFRCR)
- 50.5.7 Frame configuration register (SAI_BFRCR)
- 50.5.8 Slot register (SAI_ASLOTR)
- 50.5.9 Slot register (SAI_BSLOTR)
- 50.5.10 Interrupt mask register (SAI_AIM)
- 50.5.11 Interrupt mask register (SAI_BIM)
- 50.5.12 Status register (SAI_ASR)
- 50.5.13 Status register (SAI_BSR)
- 50.5.14 Clear flag register (SAI_ACLRFR)
- 50.5.15 Clear flag register (SAI_BCLRFR)
- 50.5.16 Data register (SAI_ADR)
- 50.5.17 Data register (SAI_BDR)
- 50.5.18 PDM control register (SAI_PDMCR)
- 50.5.19 PDM delay register (SAI_PDMDLY)
- 50.5.20 SAI register map
- 51 SPDIF receiver interface (SPDIFRX)
- 51.1 SPDIFRX interface introduction
- 51.2 SPDIFRX main features
- 51.3 SPDIFRX functional description
- 51.3.1 SPDIFRX pins and internal signals
- 51.3.2 S/PDIF protocol (IEC-60958)
- 51.3.3 SPDIFRX decoder (SPDIFRX_DC)
- 51.3.4 SPDIFRX tolerance to clock deviation
- 51.3.5 SPDIFRX synchronization
- 51.3.6 SPDIFRX handling
- 51.3.7 Data reception management
- 51.3.8 Dedicated control flow
- 51.3.9 Reception errors
- 51.3.10 Clocking strategy
- 51.3.11 DMA Interface
- 51.3.12 Interrupt Generation
- 51.3.13 Register protection
- 51.4 Programming procedures
- 51.5 SPDIFRX interface registers
- 51.5.1 Control register (SPDIFRX_CR)
- 51.5.2 Interrupt mask register (SPDIFRX_IMR)
- 51.5.3 Status register (SPDIFRX_SR)
- 51.5.4 Interrupt flag clear register (SPDIFRX_IFCR)
- 51.5.5 Data input register (SPDIFRX_FMT0_DR)
- 51.5.6 Data input register (SPDIFRX_FMT1_DR)
- 51.5.7 Data input register (SPDIFRX_FMT2_DR)
- 51.5.8 Channel status register (SPDIFRX_CSR)
- 51.5.9 Debug information register (SPDIFRX_DIR)
- 51.5.10 SPDIFRX interface register map
- 52 Single Wire Protocol Master Interface (SWPMI)
- 52.1 Introduction
- 52.2 SWPMI main features
- 52.3 SWPMI functional description
- 52.3.1 SWPMI block diagram
- 52.3.2 SWPMI pins and internal signals
- 52.3.3 SWP initialization and activation
- 52.3.4 SWP bus states
- 52.3.5 SWPMI_IO (internal transceiver) bypass
- 52.3.6 SWPMI Bit rate
- 52.3.7 SWPMI frame handling
- 52.3.8 Transmission procedure
- 52.3.9 Reception procedure
- 52.3.10 Error management
- 52.3.11 Loopback mode
- 52.4 SWPMI low-power modes
- 52.5 SWPMI interrupts
- 52.6 SWPMI registers
- 52.6.1 SWPMI Configuration/Control register (SWPMI_CR)
- 52.6.2 SWPMI Bitrate register (SWPMI_BRR)
- 52.6.3 SWPMI Interrupt and Status register (SWPMI_ISR)
- 52.6.4 SWPMI Interrupt Flag Clear register (SWPMI_ICR)
- 52.6.5 SWPMI Interrupt Enable register (SMPMI_IER)
- 52.6.6 SWPMI Receive Frame Length register (SWPMI_RFL)
- 52.6.7 SWPMI Transmit data register (SWPMI_TDR)
- 52.6.8 SWPMI Receive data register (SWPMI_RDR)
- 52.6.9 SWPMI Option register (SWPMI_OR)
- 52.6.10 SWPMI register map and reset value table
- 53 Management data input/output (MDIOS)
- 53.1 MDIOS introduction
- 53.2 MDIOS main features
- 53.3 MDIOS functional description
- 53.4 MDIOS registers
- 53.4.1 MDIOS configuration register (MDIOS_CR)
- 53.4.2 MDIOS write flag register (MDIOS_WRFR)
- 53.4.3 MDIOS clear write flag register (MDIOS_CWRFR)
- 53.4.4 MDIOS read flag register (MDIOS_RDFR)
- 53.4.5 MDIOS clear read flag register (MDIOS_CRDFR)
- 53.4.6 MDIOS status register (MDIOS_SR)
- 53.4.7 MDIOS clear flag register (MDIOS_CLRFR)
- 53.4.8 MDIOS input data register x (MDIOS_DINRx)
- 53.4.9 MDIOS output data register x (MDIOS_DOUTRx)
- 53.4.10 MDIOS register map
- 54 Secure digital input/output MultiMediaCard interface (SDMMC)
- 54.1 SDMMC main features
- 54.2 SDMMC bus topology
- 54.3 SDMMC operation modes
- 54.4 SDMMC functional description
- 54.5 Card functional description
- 54.6 Hardware flow control
- 54.7 Ultra-high-speed phase I (UHS-I) voltage switch
- 54.8 SDMMC registers
- 54.8.1 SDMMC power control register (SDMMC_POWER)
- 54.8.2 SDMMC clock control register (SDMMC_CLKCR)
- 54.8.3 SDMMC argument register (SDMMC_ARGR)
- 54.8.4 SDMMC command register (SDMMC_CMDR)
- 54.8.5 SDMMC command response register (SDMMC_RESPCMDR)
- 54.8.6 SDMMC response x register (SDMMC_RESPxR)
- 54.8.7 SDMMC data timer register (SDMMC_DTIMER)
- 54.8.8 SDMMC data length register (SDMMC_DLENR)
- 54.8.9 SDMMC data control register (SDMMC_DCTRL)
- 54.8.10 SDMMC data counter register (SDMMC_DCNTR)
- 54.8.11 SDMMC status register (SDMMC_STAR)
- 54.8.12 SDMMC interrupt clear register (SDMMC_ICR)
- 54.8.13 SDMMC mask register (SDMMC_MASKR)
- 54.8.14 SDMMC acknowledgment timer register (SDMMC_ACKTIMER)
- 54.8.15 SDMMC data FIFO register (SDMMC_FIFOR)
- 54.8.16 SDMMC DMA control register (SDMMC_IDMACTRLR)
- 54.8.17 SDMMC IDMA buffer size register (SDMMC_IDMABSIZER)
- 54.8.18 SDMMC IDMA buffer 0 base address register (SDMMC_IDMABASE0R)
- 54.8.19 SDMMC IDMA buffer 1 base address register (SDMMC_IDMABASE1R)
- 54.8.20 SDMMC register map
- 55 FD controller area network (FDCAN)
- 55.1 Introduction
- 55.2 FDCAN main features
- 55.3 FDCAN functional description
- 55.3.1 Operating modes
- 55.3.2 Message RAM
- 55.3.3 FIFO acknowledge handling
- 55.3.4 Bit timing
- 55.3.5 Clock calibration on CAN
- 55.3.6 TTCAN operations (FDCAN1 only)
- 55.3.7 TTCAN configuration
- 55.3.8 Message scheduling
- 55.3.9 TTCAN gap control
- 55.3.10 Stop watch
- 55.3.11 Local time, cycle time, global time, and external clock synchronization
- 55.3.12 TTCAN error level
- 55.3.13 TTCAN message handling
- 55.3.14 TTCAN interrupt and error handling
- 55.3.15 Level 0
- 55.3.16 Synchronization to external time schedule
- 55.3.17 FDCAN Rx buffer and FIFO element
- 55.3.18 FDCAN Tx buffer element
- 55.3.19 FDCAN Tx event FIFO element
- 55.3.20 FDCAN standard message ID filter element
- 55.3.21 FDCAN extended message ID filter element
- 55.3.22 FDCAN trigger memory element
- 55.4 FDCAN registers
- 55.4.1 FDCAN core release register (FDCAN_CREL)
- 55.4.2 FDCAN Endian register (FDCAN_ENDN)
- 55.4.3 FDCAN data bit timing and prescaler register (FDCAN_DBTP)
- 55.4.4 FDCAN test register (FDCAN_TEST)
- 55.4.5 FDCAN RAM watchdog register (FDCAN_RWD)
- 55.4.6 FDCAN CC control register (FDCAN_CCCR)
- 55.4.7 FDCAN nominal bit timing and prescaler register (FDCAN_NBTP)
- 55.4.8 FDCAN timestamp counter configuration register (FDCAN_TSCC)
- 55.4.9 FDCAN timestamp counter value register (FDCAN_TSCV)
- 55.4.10 FDCAN timeout counter configuration register (FDCAN_TOCC)
- 55.4.11 FDCAN timeout counter value register (FDCAN_TOCV)
- 55.4.12 FDCAN error counter register (FDCAN_ECR)
- 55.4.13 FDCAN protocol status register (FDCAN_PSR)
- 55.4.14 FDCAN transmitter delay compensation register (FDCAN_TDCR)
- 55.4.15 FDCAN interrupt register (FDCAN_IR)
- 55.4.16 FDCAN interrupt enable register (FDCAN_IE)
- 55.4.17 FDCAN interrupt line select register (FDCAN_ILS)
- 55.4.18 FDCAN interrupt line enable register (FDCAN_ILE)
- 55.4.19 FDCAN global filter configuration register (FDCAN_GFC)
- 55.4.20 FDCAN standard ID filter configuration register (FDCAN_SIDFC)
- 55.4.21 FDCAN extended ID filter configuration register (FDCAN_XIDFC)
- 55.4.22 FDCAN extended ID and mask register (FDCAN_XIDAM)
- 55.4.23 FDCAN high priority message status register (FDCAN_HPMS)
- 55.4.24 FDCAN new data 1 register (FDCAN_NDAT1)
- 55.4.25 FDCAN new data 2 register (FDCAN_NDAT2)
- 55.4.26 FDCAN Rx FIFO 0 configuration register (FDCAN_RXF0C)
- 55.4.27 FDCAN Rx FIFO 0 status register (FDCAN_RXF0S)
- 55.4.28 FDCAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A)
- 55.4.29 FDCAN Rx buffer configuration register (FDCAN_RXBC)
- 55.4.30 FDCAN Rx FIFO 1 configuration register (FDCAN_RXF1C)
- 55.4.31 FDCAN Rx FIFO 1 status register (FDCAN_RXF1S)
- 55.4.32 FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A)
- 55.4.33 FDCAN Rx buffer element size configuration register (FDCAN_RXESC)
- 55.4.34 FDCAN Tx buffer configuration register (FDCAN_TXBC)
- 55.4.35 FDCAN Tx FIFO/queue status register (FDCAN_TXFQS)
- 55.4.36 FDCAN Tx buffer element size configuration register (FDCAN_TXESC)
- 55.4.37 FDCAN Tx buffer request pending register (FDCAN_TXBRP)
- 55.4.38 FDCAN Tx buffer add request register (FDCAN_TXBAR)
- 55.4.39 FDCAN Tx buffer cancellation request register (FDCAN_TXBCR)
- 55.4.40 FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO)
- 55.4.41 FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF)
- 55.4.42 FDCAN Tx buffer transmission interrupt enable register (FDCAN_TXBTIE)
- 55.4.43 FDCAN Tx buffer cancellation finished interrupt enable register (FDCAN_ TXBCIE)
- 55.4.44 FDCAN Tx event FIFO configuration register (FDCAN_TXEFC)
- 55.4.45 FDCAN Tx event FIFO status register (FDCAN_TXEFS)
- 55.4.46 FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA)
- 55.4.47 FDCAN TT trigger memory configuration register (FDCAN_TTTMC)
- 55.4.48 FDCAN TT reference message configuration register (FDCAN_TTRMC)
- 55.4.49 FDCAN TT operation configuration register (FDCAN_TTOCF)
- 55.4.50 FDCAN TT matrix limits register (FDCAN_TTMLM)
- 55.4.51 FDCAN TUR configuration register (FDCAN_TURCF)
- 55.4.52 FDCAN TT operation control register (FDCAN_TTOCN)
- 55.4.53 FDCAN TT global time preset register (FDCAN_TTGTP)
- 55.4.54 FDCAN TT time mark register (FDCAN_TTTMK)
- 55.4.55 FDCAN TT interrupt register (FDCAN_TTIR)
- 55.4.56 FDCAN TT interrupt enable register (FDCAN_TTIE)
- 55.4.57 FDCAN TT interrupt line select register (FDCAN_TTILS)
- 55.4.58 FDCAN TT operation status register (FDCAN_TTOST)
- 55.4.59 FDCAN TUR numerator actual register (FDCAN_TURNA)
- 55.4.60 FDCAN TT local and global time register (FDCAN_TTLGT)
- 55.4.61 FDCAN TT cycle time and count register (FDCAN_TTCTC)
- 55.4.62 FDCAN TT capture time register (FDCAN_TTCPT)
- 55.4.63 FDCAN TT cycle sync mark register (FDCAN_TTCSM)
- 55.4.64 FDCAN TT trigger select register (FDCAN_TTTS)
- 55.4.65 FDCAN register map and reset value table
- 55.5 CCU registers
- 55.5.1 Clock calibration unit core release register (FCCAN_CCU_CREL)
- 55.5.2 Calibration configuration register (FCCAN_CCU_CCFG)
- 55.5.3 Calibration status register (FCCAN_CCU_CSTAT)
- 55.5.4 Calibration watchdog register (FCCAN_CCU_CWD)
- 55.5.5 Clock calibration unit interrupt register (FCCAN_CCU_IR)
- 55.5.6 Clock calibration unit interrupt enable register (FCCAN_CCU_IE)
- 55.5.7 CCU register map and reset value table
- 56 USB on-the-go high-speed (OTG_HS)
- 56.1 Introduction
- 56.2 OTG main features
- 56.3 OTG implementation
- 56.4 OTG functional description
- 56.5 OTG dual role device (DRD)
- 56.6 USB peripheral
- 56.7 USB host
- 56.8 SOF trigger
- 56.9 OTG low-power modes
- 56.10 Dynamic update of the OTG_HFIR register
- 56.11 USB data FIFOs
- 56.12 OTG_HS interrupts
- 56.13 OTG_HS control and status registers
- 56.14 OTG_HS registers
- 56.14.1 OTG control and status register (OTG_GOTGCTL)
- 56.14.2 OTG interrupt register (OTG_GOTGINT)
- 56.14.3 OTG AHB configuration register (OTG_GAHBCFG)
- 56.14.4 OTG USB configuration register (OTG_GUSBCFG)
- 56.14.5 OTG reset register (OTG_GRSTCTL)
- 56.14.6 OTG core interrupt register (OTG_GINTSTS)
- 56.14.7 OTG interrupt mask register (OTG_GINTMSK)
- 56.14.8 OTG receive status debug read/OTG status read and pop registers (OTG_GRXSTSR/OTG_GRXSTSP)
- 56.14.9 OTG receive FIFO size register (OTG_GRXFSIZ)
- 56.14.10 OTG host non-periodic transmit FIFO size register (OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0)
- 56.14.11 OTG non-periodic transmit FIFO/queue status register (OTG_HNPTXSTS)
- 56.14.12 OTG general core configuration register (OTG_GCCFG)
- 56.14.13 OTG core ID register (OTG_CID)
- 56.14.14 OTG core LPM configuration register (OTG_GLPMCFG)
- 56.14.15 OTG host periodic transmit FIFO size register (OTG_HPTXFSIZ)
- 56.14.16 OTG device IN endpoint transmit FIFO size register (OTG_DIEPTXFx) (x = 1..8, where x is the FIFO number)
- 56.14.17 Host-mode registers
- 56.14.18 OTG host configuration register (OTG_HCFG)
- 56.14.19 OTG host frame interval register (OTG_HFIR)
- 56.14.20 OTG host frame number/frame time remaining register (OTG_HFNUM)
- 56.14.21 OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS)
- 56.14.22 OTG host all channels interrupt register (OTG_HAINT)
- 56.14.23 OTG host all channels interrupt mask register (OTG_HAINTMSK)
- 56.14.24 OTG host port control and status register (OTG_HPRT)
- 56.14.25 OTG host channel x characteristics register (OTG_HCCHARx) (x = 0..15, where x = Channel number)
- 56.14.26 OTG host channel x split control register (OTG_HCSPLTx) (x = 0..15, where x = Channel number)
- 56.14.27 OTG host channel x interrupt register (OTG_HCINTx) (x = 0..15, where x = Channel number)
- 56.14.28 OTG host channel x interrupt mask register (OTG_HCINTMSKx) (x = 0..15, where x = Channel number)
- 56.14.29 OTG host channel x transfer size register (OTG_HCTSIZx) (x = 0..15, where x = Channel number)
- 56.14.30 OTG host channel x DMA address register (OTG_HCDMAx) (x = 0..15, where x = Channel number)
- 56.14.31 Device-mode registers
- 56.14.32 OTG device configuration register (OTG_DCFG)
- 56.14.33 OTG device control register (OTG_DCTL)
- 56.14.34 OTG device status register (OTG_DSTS)
- 56.14.35 OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK)
- 56.14.36 OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK)
- 56.14.37 OTG device all endpoints interrupt register (OTG_DAINT)
- 56.14.38 OTG all endpoints interrupt mask register (OTG_DAINTMSK)
- 56.14.39 OTG device VBUS discharge time register (OTG_DVBUSDIS)
- 56.14.40 OTG device VBUS pulsing time register (OTG_DVBUSPULSE)
- 56.14.41 OTG device threshold control register (OTG_DTHRCTL)
- 56.14.42 OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK)
- 56.14.43 OTG device each endpoint interrupt register (OTG_DEACHINT)
- 56.14.44 OTG device each endpoint interrupt mask register (OTG_DEACHINTMSK)
- 56.14.45 OTG device each IN endpoint-1 interrupt mask register (OTG_HS_DIEPEACHMSK1)
- 56.14.46 OTG device each OUT endpoint-1 interrupt mask register (OTG_HS_DOEPEACHMSK1)
- 56.14.47 OTG device IN endpoint x control register (OTG_DIEPCTLx) (x = 0..8, where x = endpoint number)
- 56.14.48 OTG device IN endpoint x interrupt register (OTG_DIEPINTx) (x = 0..8, where x = Endpoint number)
- 56.14.49 OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0)
- 56.14.50 OTG device IN endpoint x DMA address register (OTG_DIEPDMAx) (x = 0..8, where x = endpoint number)
- 56.14.51 OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) (x = 0..8, where x = endpoint number)
- 56.14.52 OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) (x = 1..8, where x = endpoint number)
- 56.14.53 OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0)
- 56.14.54 OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) (x = 0..8, where x = Endpoint number)
- 56.14.55 OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0)
- 56.14.56 OTG device OUT endpoint x DMA address register (OTG_DOEPDMAx) (x = 0..8, where x = endpoint number)
- 56.14.57 OTG device OUT endpoint x control register (OTG_DOEPCTLx) (x = 1..8, where x = endpoint number)
- 56.14.58 OTG device OUT endpoint x transfer size register (OTG_DOEPTSIZx) (x = 1..8, where x = Endpoint number)
- 56.14.59 OTG power and clock gating control register (OTG_PCGCCTL)
- 56.14.60 OTG_HS register map
- 56.15 OTG_HS programming model
- 57 Ethernet (ETH): media access control (MAC) with DMA controller
- 57.1 Ethernet introduction
- 57.2 Ethernet main features
- 57.3 Ethernet pins and internal signals
- 57.4 Ethernet architecture
- 57.5 Ethernet functional description: MAC
- 57.5.1 Double VLAN processing
- 57.5.2 Source Address and VLAN insertion, replacement, or deletion
- 57.5.3 Packet filtering
- 57.5.4 IEEE 1588 timestamps
- 57.5.5 IPv4 ARP offload
- 57.5.6 TCP segmentation offload
- 57.5.7 Loopback
- 57.5.8 Flow control
- 57.5.9 Checksum offload engine
- 57.5.10 MAC management counters
- 57.5.11 Interrupts generated by the MAC
- 57.5.12 MAC and MMC register descriptions
- 57.6 Ethernet functional description: PHY interfaces
- 57.7 Ethernet low-power modes
- 57.8 Ethernet interrupts
- 57.9 Ethernet programming model
- 57.9.1 DMA initialization
- 57.9.2 MTL initialization
- 57.9.3 MAC initialization
- 57.9.4 Performing normal receive and transmit operation
- 57.9.5 Stopping and starting transmission
- 57.9.6 Programming guidelines for MII link state transitions
- 57.9.7 Programming guidelines for IEEE 1588 timestamping
- 57.9.8 Programming guidelines for Energy Efficient Ethernet (EEE)
- 57.9.9 Programming guidelines for flexible pulse-per-second (PPS) output
- 57.9.10 Programming guidelines for TSO
- 57.9.11 Programming guidelines to perform VLAN filtering on the receive
- 57.10 Descriptors
- 57.11 Ethernet registers
- 58 HDMI-CEC controller (HDMI-CEC)
- 59 Debug infrastructure
- 59.1 Introduction
- 59.2 Debug infrastructure features
- 59.3 Debug infrastructure functional description
- 59.4 Debug access port functional description
- 59.5 Trace and debug subsystem functional description
- 59.5.1 System ROM tables
- 59.5.2 Global timestamp generator (TSG)
- 59.5.3 Cross trigger interfaces (CTI) and matrix (CTM)
- 59.5.4 Trace funnel (CSTF)
- 59.5.5 Embedded trace FIFO (ETF)
- 59.5.6 Trace port interface unit (TPIU)
- 59.5.7 Serial wire output (SWO) and SWO trace funnel (SWTF)
- 59.5.8 Microcontroller debug unit (DBGMCU)
- 59.6 Cortex-M7 debug functional description
- 59.7 References for debug infrastructure
- 60 Device electronic signature
- 61 Revision history