Vax780_doc Digital Equipment Corporation VAX 11/780 Vax780 Doc
User Manual: Digital Equipment Corporation VAX-11/780 Simulator ation
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VAX-11/780 Simulator Usage
01-Dec-08
COPYRIGHT NOTICE
The following copyright notice applies to the SIMH source, binary, and documentation:
Original code published in 1993-2008, written by Robert M Supnik
Copyright (c) 1993-2008, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a copy of this
software and associated documentation files (the "Software"), to deal in the Software
without restriction, including without limitation the rights to use, copy, modify, merge,
publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
to whom the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all copies or
substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL ROBERT M SUPNIK BE LIABLE FOR
ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not be used in
advertising or otherwise to promote the sale, use or other dealings in this Software
without prior written authorization from Robert M Supnik.
1
2
Simulator Files ............................................................................................................. 3
VAX780 Features......................................................................................................... 4
2.1
CPU and System Devices .................................................................................... 5
2.1.1
CPU ............................................................................................................... 5
2.1.2
Translation Buffer (TLB) ................................................................................ 7
2.1.3
SBI Controller (SBI) ....................................................................................... 7
2.1.4
Memory Controllers (MCTL0, MCTL1)........................................................... 7
2.1.5
Time-Of-Day Clock (TODR)........................................................................... 8
2.1.6
Interval Timer (TMR)...................................................................................... 8
2.1.7
Unibus Adapter (UBA) ................................................................................... 8
2.1.8
Massbus Adapters (MBA0, MBA1) ................................................................ 9
2.2
I/O Device Addressing .......................................................................................... 9
2.3
Programmed I/O Devices ................................................................................... 10
2.3.1
Console Input (TTI)...................................................................................... 10
2.3.2
Console Output (TTO) ................................................................................. 11
2.3.3
RX01 Console Floppy Disk (RX) ................................................................. 11
2.3.4
Line Printer (LPT) ........................................................................................ 12
2.4
Disks ................................................................................................................... 12
2.4.1
RP04/05/06/07, RM02/03/05/80 Disk Pack Drives (RP) .............................. 12
2.4.2
RL11/RL01/RL02 Cartridge Disk (RL) ......................................................... 13
2.4.3
RK611/RK06/RK07 Cartridge Disk (HK)...................................................... 14
2.4.4
UDA50 MSCP Disk Controllers (RQ, RQB, RQC, RQD) ............................. 15
2.5
Tapes.................................................................................................................. 17
2.5.1
TM03/TE16/TU45/TU77 Magnetic Tapes (TU)............................................ 17
2.5.2
TS11 Magnetic Tape (TS) ........................................................................... 17
2.5.3
TUK50 TMSCP Disk Controller (TQ) ........................................................... 18
2.6
Communications Devices ................................................................................... 20
2.6.1
DZ11 Terminal Multiplexer (DZ) .................................................................. 20
2.7
CR11 Card Reader (CR) .................................................................................... 21
3 Symbolic Display and Input........................................................................................ 23
This memorandum documents the DEC VAX-11/780 simulator.
1 Simulator Files
To compile the VAX-11/780, you must define VM_VAX, VAX780, and USE_INT64 as part of the compilation
command line. To enable extended file support (files greater than 2GB), you must define USE_ADDR64 as
part of the command line as well.
sim/
scp.h
sim_console.h
sim_defs.h
sim_ether.h
sim_fio.h
sim_rev.h
sim_sock.h
sim_tape.h
sim_timer.h
sim_tmxr.h
scp.c
sim_console.c
sim_ether.c
sim_fio.c
sim_sock.c
sim_tape.c
sim_timer.c
sim_tmxr.c
sim/vax/
vax_defs.h
vax780_defs.h
vax_cis.c
vax_cmode.c
vax_cpu.c
vax_cpu1.c
vax_fpa.c
vax_mmu.c
vax_octa.c
vax_sys.c
vax_syscm.c
vax780_mba.c
vax780_mem.c
vax780_sbi.c
vax780_stddev.c
vax780_syslist.c
vax780_uba.c
sim/pdp11/
pdp11_cr_dat.h
pdp11_mscp.h
pdp11_uqssp.h
pdp11_xu.h
pdp11_cr.c
pdp11_dz.c
pdp11_hk.c
pdp11_lp.c
pdp11_rl.c
pdp11_rp.c
pdp11_rq.c
pdp11_ry.c
pdp11_tq.c
pdp11_ts.c
pdp11_tu.c
pdp11_xu.c
Additional files are:
sim/vax/
vmb.exe
standard boot code
2 VAX780 Features
The VAX780 simulator is configured as follows:
device name(s)
simulates
CPU
TLB
SBI
MCTL0,MTCL1
VAX-11/780 CPU
translation buffer
system bus controller
memory controllers, MS780C with 4MB memory each,
or MS780E with 8MB-64MB each
DW780 Unibus adapter
RH780 Massbus adapters
time-of-day clock
interval timer
console terminal
console RX01 floppy disk
DZ11 8-line terminal multiplexer (up to 4)
CR11 card reader
LP11 line printer
RP04/05/06/07, RM02/03/05/80 Massbus disks, up to
eight
RK611/RK06(7) cartridge disk controller with eight
drives
RL11/RL01(2) cartridge disk controller with four drives
UDA50 MSCP controller with four drives
second UDA50 MSCP controller with four drives
third UDA50 MSCP controller with four drives
fourth UDA50 MSCP controller with four drives
RX211 floppy disk controller with two drives
TS11 magnetic tape controller with one drive
TUK50 TMSCP magnetic tape controller with four drives
TM03 tape formatter with eight TE16/TU45/TU77 drives
DEUNA/DELUA Ethernet controller
second DEUNA/DELUA Ethernet controller
UBA
MBA0,MBA1
TODR
TMR
TTI,TTO
RX
DZ
CR
LPT
RP
HK
RL
RQ
RQB
RQC
RQD
RY
TS
TQ
TU
XU
XUB
The DZ, LPT, RP, RL, RQ, RQB, RQC, RQD, RY, TS, TQ, TU, XU, and XUB devices can be set
DISABLED. RQB, RQC, RQD, VH, XU, and XUB are disabled by default.
The VAX780 simulator implements several unique stop conditions:
-
Change mode to interrupt stack
-
Illegal vector (bits<1:0> = 2 or 3)
Unexpected exception during interrupt or exception
Process PTE in P0 or P1 space instead of system space
Unknown IPL
Infinite loop (BRB/W to self at IPL 1F)
The LOAD command supports a simple binary format, consisting of a stream of binary bytes without origin or
checksum, for loading memory. The DUMP command is not implemented.
2.1 CPU and System Devices
2.1.1 CPU
CPU options include the size of main memory and the treatment of the HALT instruction.
SET
SET
SET
SET
SET
SET
CPU
CPU
CPU
CPU
CPU
CPU
8M
16M
32M
48M
64M
128M
set
set
set
set
set
set
memory
memory
memory
memory
memory
memory
size
size
size
size
size
size
=
=
=
=
=
=
8MB
16MB
32MB
48MB
64MB
128MB
The CPU implements a show command to display the I/O address map:
SHOW CPU IOSPACE
show I/O space address map
The CPU also implements a command to display a virtual to physical address translation:
SHOW {-kesu} CPU VIRTUAL=n
show translation for address n
in kernel/exec/supervisor/user mode
Notes on memory size:
-
The first version of the VAX-11/780 used MS780C controllers, which supported 1-4MB of
memory per controller. This is the only memory controller recognized by VMS V1. MS780E
controllers supported 4MB-64MB per controller.
The controller type is set automatically based on memory size.
Initial memory size is 8MB.
Memory can be loaded with a binary byte stream using the LOAD command. The LOAD command
recognizes three switches:
-o
-r
-s
origin argument follows file name
load ROM in memory controller 0
load ROM in memory controller 1
These switches are recognized when examining or depositing in CPU memory:
-b
-w
-l
-d
-o
-h
examine/deposit bytes
examine/deposit words
examine/deposit longwords
data radix is decimal
data radix is octal
data radix is hexadecimal
-m
-p
-r
-v
-k
-e
-s
-u
examine (only) VAX instructions
examine/deposit PDP-11 (compatibility mode) instructions
examine (only) RADIX50 encoded data
interpret address as virtual, current mode
interpret address as virtual, kernel mode
interpret address as virtual, executive mode
interpret address as virtual, supervisor mode
interpret address as virtual, user mode
CPU registers include the visible state of the processor as well as the control registers for the interrupt
system.
name
size
comments
PC
R0 .. R14
AP
FP
SP
PSL
CC
KSP
ESP
SSP
USP
IS
SCBB
PCBB
P0BR
P0LR
P1BR
P1LR
SBR
SLR
SISR
ASTLVL
MAPEN
PME
TRPIRQ
CRDERR
MEMERR
PCQ[0:63]
32
32
32
32
32
32
4
32
32
32
32
32
32
32
32
22
32
22
32
22
16
4
1
1
8
1
1
32
WRU
8
program counter
R0 to R14
alias for R12
alias for R13
alias for R14
processor status longword
condition codes, PSL<3:0>
kernel stack pointer
executive stack pointer
supervisor stack pointer
user stack pointer
interrupt stack pointer
system control block base
process controll block base
P0 base register
P0 length register
P1 base register
P1 length register
system base register
system length register
software interrupt summary register
AST level register
memory management enable
performance monitor enable
trap/interrupt pending
correctible read data error flag
memory error flag
PC prior to last PC change or interrupt;
most recent PC change first
interrupt character
The CPU attempts to detect when the simulator is idle. When idle, the simulator does not use any resources
on the host system. Idle detection is controlled by the SET IDLE and SET NOIDLE commands:
SET CPU IDLE{=VMS|ULTRIX|NETBSD|FREEBSD|32V}
SET CPU NOIDLE
disable idle detection
enable idle detection
Idle detection is disabled by default. Idle detection is operating system specific. If idle detection is enabled
with an incorrect operating system setting, simulator performance will be severely diminished. The default
operating system setting is VMS.
The CPU can maintain a history of the most recently executed instructions. This is controlled by the SET
CPU HISTORY and SHOW CPU HISTORY commands:
SET CPU HISTORY
SET CPU HISTORY=0
SET CPU HISTORY=n
SHOW CPU HISTORY
SHOW CPU HISTORY=n
clear history buffer
disable history
enable history, length = n
print CPU history
print first n entries of CPU history
The maximum length for the history is 65536 entries.
2.1.2 Translation Buffer (TLB)
The translation buffer consists of two units, representing the system and user translation buffers,
respectively. It has no registers. Each translation buffer entry consists of two 32b words, as follows:
word n
word n+1
tag
cached PTE
An invalid entry is indicated by a tag of 0xFFFFFFFF.
2.1.3 SBI Controller (SBI)
The SBI is the VAX-11/780 system bus. The simulated SBI implements these registers:
name
size
comments
NREQ14
NREQ15
NREQ16
NREQ17
WCSA
WCSD
MBRK
SBIFS
SBISC
SBIMT
SBIER
SBITMO
16
16
16
16
16
32
13
32
32
32
32
32
Nexus IPL14 interrupt requests
Nexus IPL15 interrupt requests
Nexus IPL16 interrupt requests
Nexus IPL17 interrupt requests
writeable control store address
writeable control store data
microbreak register
SBI fault status
SBI silo compare
SBI maintenance register
SBI error status
SBI timeout address
2.1.4 Memory Controllers (MCTL0, MCTL1)
The memory controllers implement the registers for the MS780C (8MB memory) or MS780E (16MB or
greater memory). Each controller implements these registers:
name
size
comments
CRA
CRB
CRC
CRD
ROM[0:1023]
32
32
32
32
32
control register
control register
control register
control register
bootstrap ROM
ROM can be loaded from a file with the commands
A
B
C
D (MS780E only)
LOAD -R
LOAD -S
load MCTL0 ROM
load MCTL1 ROM
2.1.5 Time-Of-Day Clock (TODR)
The TODR tracks time since an arbitrary start in 1 microsecond intervals. It has these registers:
name
size
comments
TODR
TIME
32
24
time-of-day register
delay between ticks
The TODR register autocalibrates against real-world time.
2.1.6 Interval Timer (TMR)
The interval timer implements the VAX architectural timer, with 1 microsecond intervals. It has these
registers:
name
size
comments
ICCS
ICR
NICR
INT
32
32
32
1
interval timer control and status
interval count register
next interval count register
interrupt request
For standard VMS intervals (10 milliseconds), the interval timer autocalibrates against real-world time.
2.1.7 Unibus Adapter (UBA)
The Unibus adapter (UBA) simulates the DW780. It recognizes these options:
SET UBA AUTOCONFIGURE
SET UBA NOAUTOCONFIGURE
enable autoconfiguration
disable autoconfiguration
and this SHOW command:
SHOW UBA IOSPACE
display IO address space assignments
The UBA also implements a command to display a Unibus address to physical address translation:
SHOW UBA VIRTUAL=n
show translation for Unibus address n
Finally, the UBA implements main memory examination and modification via the Unibus map. The data
width is always 16b:
EX UBA 0/10
examine main memory words corresponding
to Unibus addresses 0-10
The UBA has these registers:
name
size
comments
IPL14
IPL15
IPL16
IPL17
CNFR
CR
SR
DR
INT
NEXINT
AIIP
UIIP
FMER
FUBAR
BRSVR0
BRSVR1
BRSVR2
BRSVR3
BRRVR4
BRRVR5
BRRVR6
BRRVR7
DPR[0:15]
MAP[0:495]
AITIME
UITIME
32
32
32
32
32
32
32
32
1
1
1
1
32
32
32
32
32
32
32
32
32
32
32
32
24
24
Unibus IPL14 interrupt requests
Unibus IPL15 interrupt requests
Unibus IPL16 interrupt requests
Unibus IPL17 interrupt requests
configuration register
control register
status register
diagnostic register
internal UBA interrupt request
UBA Nexus interrupt request
adapter initialization in progress flag
Unibus initialization in progress flag
failing memory address
failing UBA map register
spare register 0
spare register 1
spare register 2
spare register 3
vector register, IPL 14
vector register, IPL 15
vector register, IPL 16
vector register, IPL 17
data path registers 0 to 15
map registers 0 to 495
adapter initialization time
Unibus initialization time
2.1.8 Massbus Adapters (MBA0, MBA1)
The Massbus adapters (MBA0, MBA1) simulate RH780's. MBA0 is assigned to the RP disk drives, MBA1 to
the TU tape drives. Each MBA has these registers:
name
size
comments
CNFR
CR
SR
VA
BC
DR
SMR
MAP[0:255]
NEXINT
32
32
32
17
32
32
32
32
1
configuration register
control register
status register
virtual address register
byte count register
diagnostic register
selected map register
map registers
MBA Nexus interrupt request
2.2 I/O Device Addressing
Unibus I/O space is not large enough to allow all possible devices to be configured simultaneously at fixed
addresses. Instead, many devices have floating addresses; that is, the assigned device address depends
on the presence of other devices in the configuration:
DZ11
RL11
RX11/RX211
DEUNA/DELUA
MSCP disk
all instances have
first instance has
first instance has
first instance has
first instance has
floating addresses
fixed address, rest
fixed address, rest
fixed address, rest
fixed address, rest
floating
floating
floating
floating
TMSCP tape
first instance has fixed address, rest floating
To maintain addressing consistency as the configuration changes, the simulator implements DEC's standard
I/O address and vector autoconfiguration algorithms for devices DZ, RL, RY, XU, RQ, and TQ. This allows
the user to enable or disable devices without needing to manage I/O addresses and vectors.
Autoconfiguration cannot solve address conflicts between devices with overlapping fixed addresses. For
example, with default I/O page addressing, the PDP-11 can support either a TUK50 or a TS11, but not both,
since they use the same I/O addresses.
In addition to autoconfiguration, most devices support the SET ADDRESS command, which
allows the I/O page address of the device to be changed, and the SET VECTOR command,
which allows the vector of the device to be changed. Explicitly setting the I/O address of a device that
normally uses autoconfiguration DISABLES autoconfiguration for that device and for the entire system. As a
consequence, the user may have to manually configure all other autoconfigured devices, because the
autoconfiguration algorithm no longer recognizes the explicitly configured device. A device can be reset to
autoconfigure with the SET AUTOCONFIGURE command. Autoconfiguration can be restored for
the entire system with the SET CPU AUTOCONFIGURE command.
The current I/O map can be displayed with the SHOW CPU IOSPACE command. Addresses that have set by
autoconfiguration are marked with an asterisk (*).
All devices support the SHOW ADDRESS and SHOW VECTOR commands, which
display the device address and vector, respectively.
2.3 Programmed I/O Devices
2.3.1 Console Input (TTI)
The terminal interfaces (TTI, TTO) can be set to one of three modes, 7P, 7B or 8B:
mode
input characters
output characters
7P
high-order bit cleared
7B
8B
high-order bit cleared
no changes
high-order bit cleared,
non-printing characters suppressed
high-order bit cleared
no changes
The default mode is 8B.
When the console terminal is attached to a Telnet session, it recognizes BREAK. If BREAK is entered, and
BDR<7> is set, control returns to the console firmware; otherwise, BREAK is treated as a normal terminal
input condition.
The terminal input (TTI) polls the console keyboard for input. It implements these registers:
name
size
comments
BUF
CSR
INT
ERR
DONE
IE
POS
8
16
1
1
1
1
32
last data item processed
control/status register
interrupt pending flag
error flag (CSR<15>)
device done flag (CSR<7>)
interrupt enable flag (CSR<6>)
number of characters input
TIME
24
input polling interval (if 0, the keyboard
is polled synchronously with the TODR)
2.3.2 Console Output (TTO)
The terminal output (TTO) writes to the simulator console window. It implements these registers:
name
size
comments
BUF
CSR
INT
ERR
DONE
IE
POS
TIME
8
16
1
1
1
1
32
24
last data item processed
control/status register
interrupt pending flag
error flag (CSR<15>)
device done flag (CSR<7>)
interrupt enable flag (CSR<6>)
number of characters input
time from I/O initiation to interrupt
2.3.3 RX01 Console Floppy Disk (RX)
RX01 options include the ability to set units write enabled or write locked:
SET RXn LOCKED
SET RXn WRITEENABLED
set unit n write locked
set unit n write enabled
The RX01 implements a special command, FLOAD, for loading VAX executables from an RT11-formatted
console floppy disk image:
FLOAD {}
FLOAD searches the floppy disk image attached to the RX01 for the named file and then loads it into VAX11/780 memory starting at the origin. If no origin is specified, the default origin is 200 (hex).
The RX01 implements these registers:
name
size
comments
FNC
ES
ECODE
TA
SA
STATE
BPTR
CTIME
STIME
XTIME
STOP_IOE
DBUF[0:127]
8
8
8
8
8
4
7
24
24
24
1
8
function select
error status
error code
track address
sector address
protocol state
data buffer pointer
command initiation delay
seek time delay, per track
transfer time delay, per byte
stop on I/O error
data buffer
Error handling is as follows:
error
not attached
STOP_IOE
1
processed as
report error and stop
0
disk not ready
RX01 data files are buffered in memory; therefore, end of file and OS I/O errors cannot occur.
2.3.4 Line Printer (LPT)
The line printer (LPT) writes data to a disk file. The POS register specifies the number of the next data item
to be written. Thus, by changing POS, the user can backspace or advance the printer.
The line printer implements these registers:
name
size
comments
BUF
CSR
INT
ERR
DONE
IE
POS
TIME
STOP_IOE
8
16
1
1
1
1
32
24
1
last data item processed
control/status register
interrupt pending flag
error flag (CSR<15>)
device done flag (CSR<7>)
interrupt enable flag (CSR<6>)
position in the output file
time from I/O initiation to interrupt
stop on I/O error
Error handling is as follows:
error
STOP_IOE
processed as
not attached
1
0
report error and stop
out of paper
OS I/O error
x
report error and stop
2.4 Disks
All VAX-11/780 disks, and the TUK50 MSCP tape, support a special form of the boot command, with the
following syntax:
BOOT {/R5:}
For example,
BOOT RP0/R5:1
The optional switch, /R5, specifies that R5 is to be loaded with the specified value prior to booting. If the
switch is omitted, R5 is loaded with 0.
2.4.1 RP04/05/06/07, RM02/03/05/80 Disk Pack Drives (RP)
The RP controller implements the Massbus family of large disk drives. RP options include the ability to set
units write enabled or write locked, to set the drive type to one of six disk types, or autosize, and to write a
DEC standard 044 compliant bad block table on the last track:
SET RPn LOCKED
set unit n write locked
SET
SET
SET
SET
SET
SET
SET
SET
SET
RPn
RPn
RPn
RPn
RPn
RPn
RPn
RPn
RPn
WRITEENABLED
RM03
RM05
RM80
RP04
RP06
RP07
AUTOSIZE
BADBLOCK
set unit n write enabled
set type to RM03
set type to RM05
set type to RM80
set type to RP04
set type to RP06
set type to RP07
set type based on file size at attach
write bad block table on last track
The type options can be used only when a unit is not attached to a file. The bad block option can be used
only when a unit is attached to a file. Units can be set ENABLED or DISABLED. The RP controller supports
the BOOT command.
The RP controller implements the registers listed below. Registers suffixed with [0:7] are replicated per
drive.
name
size
comments
CS1[0:7]
DA[0:7]
DS[0:7]
ER1[0:7]
OF[0:7]
DC[0:7]
ER2[0:7]
ER3[0:7]
EC1[0:7]
EC2[0:7]
MR[0:7]
MR2[0:7]
HR[0:7]
STIME
RTIME
STOP_IOE
16
16
16
16
16
16
16
16
16
16
16
16
16
24
24
1
current operation
desired surface, sector
drive status
drive errors
offset
desired cylinder
error status 2
error status 3
ECC syndrome 1
ECC syndrome 2
maintenance register
maintenance register 2 (RM only)
holding register (RM only)
seek time, per cylinder
rotational delay
stop on I/O error
Error handling is as follows:
error
STOP_IOE
processed as
not attached
1
0
report error and stop
disk not ready
end of file
x
assume rest of disk is zero
OS I/O error
x
report error and stop
2.4.2 RL11/RL01/RL02 Cartridge Disk (RL)
RL11 options include the ability to set units write enabled or write locked, to set the drive type to RL01,
RL02, or autosize, and to write a DEC standard 044 compliant bad block table on the last track:
SET
SET
SET
SET
RLn
RLn
RLn
RLn
LOCKED
WRITEENABLED
RL01
RL02
set
set
set
set
unit
unit
type
type
n write locked
n write enabled
to RL01
to RL02
SET RLn AUTOSIZE
SET RLn BADBLOCK
set type based on file size at attach
write bad block table on last track
The type options can be used only when a unit is not attached to a file. The bad block option can be used
only when a unit is attached to a file. Units can be set ENABLED or DISABLED. The RL11 supports the
BOOT command.
The RL11 implements these registers:
name
size
comments
RLCS
RLDA
RLBA
RLBAE
RLMP,RLMP1,RLMP2
INT
ERR
DONE
IE
STIME
RTIME
STOP_IOE
16
16
16
6
16
1
1
1
1
24
24
1
control/status
disk address
memory address
memory address extension (RLV12)
multipurpose register queue
interrupt pending flag
error flag (CSR<15>)
device done flag (CSR<7>)
interrupt enable flag (CSR<6>)
seek time, per cylinder
rotational delay
stop on I/O error
Error handling is as follows:
error
STOP_IOE
processed as
not attached
1
0
report error and stop
disk not ready
end of file
x
assume rest of disk is zero
OS I/O error
x
report error and stop
2.4.3 RK611/RK06/RK07 Cartridge Disk (HK)
RK611 options include the ability to set units write enabled or write locked, to set the drive type to RK06,
RK07, or autosize, and to write a DEC standard 044 compliant bad block table on the last track:
SET
SET
SET
SET
SET
SET
HKn
HKn
HKn
HKn
HKn
HKn
LOCKED
WRITEENABLED
RK06
RK07
AUTOSIZE
BADBLOCK
set unit n write locked
set unit n write enabled
set type to RK06
set type to RK07
set type based on file size at attach
write bad block table on last track
The type options can be used only when a unit is not attached to a file. The bad block option can be used
only when a unit is attached to a file. Units can be set ENABLED or DISABLED. The RK611 supports the
BOOT command.
The RK611 implements these registers:
name
size
comments
HKCS1
16
control/status 1
HKWC
HKBA
HKDA
HKCS2
HKDS[0:7]
HKER[0:7]
HKDB[0:2]
HKDC
HKOF
HKMR
HKSPR
INT
ERR
DONE
IE
STIME
RTIME
STOP_IOE
16
16
16
16
16
16
16
16
8
16
16
1
1
1
1
24
24
1
word count
bus address
desired surface, sector
control/status 2
drive status, drives 0 to 7
drive errors, drives 0 to 7
data buffer silo
desired cylinder
offset
maintenance register
spare register
interrupt pending flag
error flag (CSR<15>)
device done flag (CSR1<7>)
interrupt enable flag (CSR1<6>)
seek time, per cylinder
rotational delay
stop on I/O error
Error handling is as follows:
error
STOP_IOE
processed as
not attached
1
0
report error and stop
disk not ready
end of file
x
assume rest of disk is zero
OS I/O error
x
report error and stop
2.4.4 UDA50 MSCP Disk Controllers (RQ, RQB, RQC, RQD)
The simulator implements four MSCP disk controllers, RQ, RQB, RQC, RQD. Initially, RQB, RQC, and
RQD are disabled. Each RQ controller simulates an UDA50 MSCP disk controller with four drives. RQ
options include the ability to set units write enabled or write locked, and to set the drive type to one of many
disk types:
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
set
SET
SET
SET
SET
SET
SET
RQn LOCKED
RQn WRITEENABLED
RQn RX50
RQn RX33
RQn RD51
RQn RD52
RQn RD53
RQn RD54
RQn RD31
RQn RA81
RQn RA82
RQn RA71
RQn RA72
RQn RA90
RQn RA92
RQn RRD40
RQn RAUSER{=n}
-L RQn RAUSER{=n}
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
set
unit
unit
type
type
type
type
type
type
type
type
type
type
type
type
type
type
type
type
n write locked
n write enabled
to RX50
to RX33
to RD51
to RD52
to RD53
to RD54
to RD31
to RA81
to RA82
to RA71
to RA72
to RA90
to RA92
to RRD40 (CD ROM)
to RA82 with n MB's
to RA82 with n LBN's
The type options can be used only when a unit is not attached to a file. RAUSER is a "user specified" disk;
the user can specify the size of the disk in either MB (1000000 bytes) or logical block numbers (LBN's, 512
bytes each). The minimum size is 5MB; the maximum size is 2GB without extended file support, 1TB with
extended file support.
Units can be set ENABLED or DISABLED. The RQ controllers support the BOOT command.
Each RQ controller implements the following special SHOW commands:
SHOW
SHOW
SHOW
SHOW
SHOW
SHOW
SHOW
RQn TYPE
RQ RINGS
RQ FREEQ
RQ RESPQ
RQ UNITQ
RQ ALL
RQn UNITQ
show
show
show
show
show
show
show
drive type
command and response rings
packet free queue
packet response queue
unit queues
all ring and queue state
unit queues for unit n
Each RQ controller implements these registers:
name
size
comments
SA
S1DAT
CQBA
CQLNT
CQIDX
RQBA
RQLNT
RQIDX
FREE
RESP
PBSY
CFLGS
CSTA
PERR
CRED
HAT
HTMO
CPKT[0:3]
PKTQ[0:3]
UFLG[0:3]
INT
ITIME
16
16
22
8
8
22
8
8
5
5
5
16
4
9
5
17
17
5
5
16
1
1
QTIME
XTIME
PKTS[33*32]
24
24
16
status/address register
step 1 init host data
command queue base address
command queue length
command queue index
request queue base address
request queue length
request queue index
head of free packet list
head of response packet list
number of busy packets
controller flags
controller state
port error number
host credits
host available timer
host timeout value
current packet, units 0 to 3
packet queue, units 0 to 3
unit flags, units 0 to 3
interrupt request
response time for initialization steps
(except for step 4)
response time for 'immediate' packets
response time for data transfers
packet buffers, 33W each, 32 entries
While VMS is not timing sensitive, most of the BSD-derived operating systems (NetBSD, OpenBSD, etc)
are. The QTIME and XTIME parameters are set to values that allow these operating systems to run
correctly.
Error handling is as follows:
error
processed as
not attached
disk not ready
end of file
assume rest of disk is zero
OS I/O error
report error and stop
2.5 Tapes
2.5.1 TM03/TE16/TU45/TU77 Magnetic Tapes (TU)
The TU controller implements the Massbus family of 800/1600bpi magnetic tape drives. TU options include
the ability to set the drive type to one of three drives (TE16, TU45, or TU77), and to set the drives write
enabled or write locked.
SET
SET
SET
SET
SET
TUn
TUn
TUn
Tun
Tun
TE16
TU45
TU77
LOCKED
WRITEENABLED
set
set
set
set
set
unit
unit
unit
unit
unit
n
n
n
n
n
drive
drive
drive
write
write
type to TE16
type to TU45
type to TU77
locked
enabled
Magnetic tape units can be set to a specific reel capacity in MB, or to unlimited capacity:
SET TUn CAPAC=m
SHOW TUn CAPAC
set unit n capacity to m MB (0 = unlimited)
show unit n capacity in MB
Units can be set ENABLED or DISABLED. The TU controller does not support the BOOT command.
The TU controller implements the following registers:
name
size
comments
CS1
FC
FS
ER
CC
MR
TC
TIME
UST
POS
STOP_IOE
6
16
16
16
16
16
16
24
17
32
1
current operation
frame count
formatter status
formatter errors
check character
maintenance register
tape control register
operation execution time
unit status, drives 0 to 7
position, drive 0 to 7
stop of I/O error
Error handling is as follows:
error
processed as
not attached
tape not ready; if STOP_IOE, stop
end of file
bad tape
OS I/O error
parity error; if STOP_IOE, stop
2.5.2 TS11 Magnetic Tape (TS)
TS options include the ability to make the unit write enabled or write locked.
SET TS LOCKED
SET TS WRITEENABLED
set unit write locked
set unit write enabled
The TS drive can be set to a specific reel capacity in MB, or to unlimited capacity:
SET TS0 CAPAC=m
SHOW TS0 CAPAC
set capacity to m MB (0 = unlimited)
show capacity in MB
The TS11 does not support the BOOT command.
The TS controller implements these registers:
name
size
comments
TSSR
TSBA
TSDBX
CHDR
CADL
CADH
CLNT
MHDR
MRFC
MXS0
MXS1
MXS2
MXS3
MXS4
WADL
WADH
WLNT
WOPT
WXOPT
ATTN
BOOT
OWNC
OWNM
TIME
POS
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
1
1
1
1
24
32
status register
bus address register
data buffer extension register
command packet header
command packet low address or count
command packet high address
command packet length
message packet header
message packet residual frame count
message packet extended status 0
message packet extended status 1
message packet extended status 2
message packet extended status 3
message packet extended status 4
write char packet low address
write char packet high address
write char packet length
write char packet options
write char packet extended options
attention message pending
boot request pending
if set, tape owns command buffer
if set, tape owns message buffer
delay
position
Error handling is as follows:
error
processed as
not attached
tape not ready
end of file
bad tape
OS I/O error
fatal tape error
2.5.3 TUK50 TMSCP Disk Controller (TQ)
The TQ controller simulates the TUK50 TMSCP disk controller. TQ options include the ability to set units
write enabled or write locked, and to specify the controller type and tape length:
SET
SET
SET
SET
SET
SET
TQn LOCKED
TQn WRITEENABLED
TQ TK50
TQ TK70
TQ TU81
TQ TKUSER{=n}
set unit n write locked
set unit n write enabled
set controller type to TK50
set controller type to TK70
set controller type to TU81
set controller type to TK50 with tape
capacity of n MB
User-specified capacity must be between 50 and 2000 MB. The TUK50 supports the BOOT command.
Regardless of the controller type, individual units can be set to a specific reel capacity in MB, or to unlimited
capacity:
SET TQn CAPAC=m
SHOW TQn CAPAC
set unit n capacity to m MB (0 = unlimited)
show unit n capacity in MB
The TQ controller implements the following special SHOW commands:
SHOW
SHOW
SHOW
SHOW
SHOW
SHOW
SHOW
TQ TYPE
TQ RINGS
TQ FREEQ
TQ RESPQ
TQ UNITQ
TQ ALL
TQn UNITQ
show
show
show
show
show
show
show
controller type
command and response rings
packet free queue
packet response queue
unit queues
all ring and queue state
unit queues for unit n
The TQ controller implements these registers:
name
size
comments
SA
S1DAT
CQBA
CQLNT
CQIDX
RQBA
RQLNT
RQIDX
FREE
RESP
PBSY
CFLGS
CSTA
PERR
CRED
HAT
HTMO
CPKT[0:3]
PKTQ[0:3]
UFLG[0:3]
POS[0:3]
OBJP[0:3]
INT
ITIME
16
16
22
8
8
22
8
8
5
5
5
16
4
9
5
17
17
5
5
16
32
32
1
1
status/address register
step 1 init host data
command queue base address
command queue length
command queue index
request queue base address
request queue length
request queue index
head of free packet list
head of response packet list
number of busy packets
controller flags
controller state
port error number
host credits
host available timer
host timeout value
current packet, units 0 to 3
packet queue, units 0 to 3
unit flags, units 0 to 3
tape position, units 0 to 3
object position, units 0 to 3
interrupt request
response time for initialization steps
(except for step 4)
QTIME
XTIME
PKTS[33*32]
24
24
16
response time for 'immediate' packets
response time for data transfers
packet buffers, 33W each, 32 entries
Error handling is as follows:
error
processed as
not attached
tape not ready
end of file
end of medium
OS I/O error
fatal tape error
2.6 Communications Devices
2.6.1 DZ11 Terminal Multiplexer (DZ)
The DZ11 is an 8-line terminal multiplexer. Up to 4 DZ11's (32 lines) are supported. The number of lines
can be changed with the command
SET DZ LINES=n
set line count to n
The line count must be a multiple of 8, with a maximum of 32.
The DZ11 supports three character processing modes, 7P, 7B, and 8B:
mode
input characters
output characters
7P
high-order bit cleared
7B
8B
high-order bit cleared
no changes
high-order bit cleared,
non-printing characters suppressed
high-order bit cleared
no changes
The default is 8B.
The DZ11 supports logging on a per-line basis. The command
SET DZ LOG=line=filename
enables logging for the specified line to the indicated file. The command
SET DZ NOLOG=line
disables logging for the specified line and closes any open log file. Finally, the command
SHOW DZ LOG
displays logging information for all DZ lines.
The terminal lines perform input and output through Telnet sessions connected to a user-specified port. The
ATTACH command specifies the port to be used:
ATTACH {-am} DZ
set up listening port
where port is a decimal number between 1 and 65535 that is not being used for other TCP/IP activities. The
optional switch -m turns on the DZ11's modem controls; the optional switch -a turns on active disconnects
(disconnect session if computer clears Data Terminal Ready). Without modem control, the DZ behaves as
though terminals were directly connected; disconnecting the Telnet session does not cause any operating
system-visible change in line status.
Once the DZ is attached and the simulator is running, the DZ will listen for connections on the specified port.
It assumes that the incoming connections are Telnet connections. The connection remains open until
disconnected by the simulated program, the Telnet client, a SET DZ DISCONNECT command, or a DETACH
DZ command.
Other special DZ commands:
SHOW DZ CONNECTIONS
SHOW DZ STATISTICS
SET DZ DISCONNECT=linenumber
show current connections
show statistics for active connections
disconnects the specified line.
The DZ11 implements these registers:
name
size
comments
CSR[0:3]
RBUF[0:3]
LPR[0:3]
TCR[0:3]
MSR[0:3]
TDR[0:3]
SAENB[0:3]
RXINT
TXINT
MDMTCL
AUTODS
16
16
16
16
16
16
1
4
4
1
1
control/status register, boards 0 to 3
receive buffer, boards 0 to 3
line parameter register, boards 0 to 3
transmission control register, boards 0 to 3
modem status register, boards 0 to 3
transmit data register, boards 0 to 3
silo alarm enabled, boards 0 to 3
receive interrupts, boards 3 to 0
transmit interrupts, boards 3 to 0
modem control enabled
autodisconnect enabled
The DZ11 does not support save and restore. All open connections are lost when the simulator shuts down
or the DZ is detached.
2.7 CR11 Card Reader (CR)
The card reader (CR) implements a single controller (the CR11) and card reader (e.g., Documation M200,
GDI Model 100) by reading a file and presenting lines or cards to the simulator. Card decks may be
represented by plain text ASCII files, card image files, or column binary files. The CR11 controller is also
compatible with the CM11-F, CME11, and CMS11.
Card image files are a file format designed by Douglas W. Jones at the University of Iowa to support the
interchange of card deck data. These files have a much richer information carrying capacity than plain
ASCII files. Card Image files can contain such interchange information as card-stock color, corner cuts,
special artwork, as well as the binary punch data representing all 12 columns. Complete details on the
format, as well as sample code, are available at Prof. Jones's site: http://www.cs.uiowa.edu/~jones/cards/.
Examples of the CR11 include the M8290 and M8291 (CMS11). All card readers use a common vector at
0230 and CSR at 177160. Even though the CR11 is normally configured as a BR6 device, it is configured
for BR4 in this simulation.
The card reader supports ASCII, card image, and column binary format card “decks.” When reading plain
ASCII files, lines longer than 80 characters are silently truncated. Card image support is included for 80
column Hollerith, 82 column Hollerith (silently ignoring columns 0 and 81), and 40 column Hollerith (marksense) cards. Column binary supports 80 column card images only. All files are attached read-only (as if
the -R switch were given).
ATTACH –A CR
ATTACH –B CR
ATTACH –I CR
file is ASCII text
file is column binary
file is card image format
If no flags are given, the file extension is evaluated. If the filename ends in .TXT, the file is treated as ASCII
text. If the filename ends in .CBN, the file is treated as column binary. Otherwise, the CR driver looks for a
card image header. If a correct header is found the file is treated as card image format, otherwise it is
treated as ASCII text.
The correct character translation MUST be set if a plain text file is to be used for card deck input. The
correct translation SHOULD be set to allow correct ASCII debugging of a card image or column binary input
deck. Depending upon the operating system in use, how it was generated, and how the card data will be
read and used, the translation must be set correctly so that the proper character set is used by the driver.
Use the following command to explicitly set the correct translation:
SET TRANSLATION={DEFAULT|026|026FTN|029|EBCDIC}
This command should be given after a deck is attached to the simulator. The mappings above are
completely described at http://www.cs.uiowa.edu/~jones/cards/codes.html. Note that DEC typically used
029 or 026FTN mappings.
DEC operating systems used a variety of methods to determine the end of a deck (recognizing that 'hopper
empty' does not necessarily mean the end of a deck. Below is a summary of the various operating system
conventions for signaling end of deck:
RT-11:
12-11-0-1-6-7-8-9 punch in column 1
RSTS/E:
12-11-0-1 or 12-11-0-1-6-7-8-9 punch in column 1
RSX:
12-11-0-1-6-7-8-9 punch
VMS:
12-11-0-1-6-7-8-9 punch in first 8 columns
TOPS:
12-11-0-1 or 12-11-0-1-6-7-8-9 punch in column 1
Using the AUTOEOF setting, the card reader can be set to automatically generate an EOF card consisting
of the 12-11-0-1-6-7-8-9 punch in columns 1-8. When set to CD11 mode, this switch also enables automatic
setting of the EOF bit in the controller after the EOF card has been processed. [The CR11 does not have a
similar capability.] By default AUTOEOF is enabled.
SET CR AUTOEOF
SET CR NOAUTOEOF
The default card reader rate for the CR11 is 285 cpm. The reader rate can be set to its default value or to
anywhere in the range 200 to 1200 cpm. This rate may be changed while the unit is attached.
SET CR RATE={DEFAULT|200 to 1200}
It is standard operating procedure for operators to load a card deck and press the momentary action RESET
button to clear any error conditions and alert the processor that a deck is available to read. Use the
following command to simulate pressing the card reader RESET button,
SET CR RESET
Another common control of physical card readers is the STOP button. An operator could use this button to
finish the read operation for the current card and terminate reading a deck early. Use the following
command to simulate pressing the card reader STOP button.
SET CR STOP
The simulator does not support the BOOT command. The simulator does not stop on file I/O errors. Instead
the controller signals a reader check to the CPU.
The CR controller implements these registers:
name
BUF
CRS
CRB1
CRB2
CRM
CDST
CDCC
CDBA
CDDB
BLOWER
INT
ERR
IE
POS
TIME
size
8
16
16
16
16
16
16
16
16
2
1
1
1
32
24
comments
ASCII value of last column processed
CR11 status register
CR11 12-bit Hollerith character
CR11 8-bit compressed character
CR11 maintenance register
CD11 control/status register
CD11 column count
CD11 current bus address
CD11 data buffer, 2nd status
blower state value
interrupt pending flag
error flag (CRS<15>)
interrupt enable flag (CRS<6>)
file position - do not alter
delay time between columns
3 Symbolic Display and Input
The VAX simulator implements symbolic display and input. Display is controlled by command line switches:
-a,-c
-m
-p
-r
display
display
display
display
as ASCII data
instruction mnemonics
compatibility mode mnemonics
RADIX50 encoding
Input parsing is controlled by the first character typed in or by command line switches:
' or -a
" or -c
-p
alphabetic
numeric
ASCII characters (determined by length)
ASCII string (maximum 60 characters)
compatibility mode instruction mnemonic
instruction mnemonic
octal number
VAX instruction input uses standard VAX assembler syntax. Compatibility mode instruction input uses
standard PDP-11 assembler syntax.
The syntax for VAX specifiers is as follows:
syntax
specifier
displacement
#s^n, #n
[Rn]
Rn
(Rn)
-(Rn)
(Rn)+
#i^n, #n
@(Rn)+
@#addr
{+/-}b^d(Rn)
b^d
@{+/-}b^d(Rn)
@b^d
{+/-}w^d(Rn)
w^d
@{+/-}w^d(Rn)
@w^d
{+/-}l^d(Rn)
l^d
@{+/-}l^d(Rn)
@l^d
0n
4n
5n
6n
7n
8n
8F
9n
9F
An
AF
Bn
BF
Cn
CF
Dn
DF
En
EF
Fn
FF
n
addr
{+/-}d
d - PC
{+/-}d
d - PC
{+/-}d
d - PC
{+/-}d
d - PC
{+/-}d
d - PC
{+/-}d
d - PC
comments
short literal, integer only
indexed, second specifier follows
PC illegal
PC illegal
PC illegal
immediate
absolute
byte displacement
byte PC relative
byte displacement deferred
byte PC relative deferred
word displacement
word PC relative
word displacement deferred
word PC relative deferred
long displacement
long PC relative
long displacement deferred
long PC relative deferred
If no override is given for a literal (s^ or i^) or for a displacement or PC relative address (b^, w^, or l^), the
simulator chooses the mode automatically.
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