Vostro 3300 Unlocked

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5

4

3

2

1

D

D

Winery13 CALPELLA DIS N11M-GE1 Schematics
uFCPGA Mobile Arrandale
Intel Ibex Peak-M
C

C

2010-01-13
REV : A00
B

B

DY : Nopop Component
UMA : Pop when schematic is UMA
DIS : Pop when schematic is DIS

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

Cover Page

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

1

of

88

5

4

D

2

1

CPU DC/DC

Winery CALPELLA Block Diagram

PCB LAYER
L1:
L2:
L3:
L4:
L5:
L6:
L7:
L8:

3

Top
GND
Signal
Signal
VCC
Signal
GND
Bottom

Clock Generator
SLG8SP585

Project code
Part Number
PCB P/N
Revision

VRAM

Intel CPU

DDRIII
1066

100MHz/
2.5Gbps

800/1066MHz
DDR III 1066 Channel B

OUTPUTS

+PWR_SRC

+VCC_CORE

SYSTEM DC/DC

PCIe x 16

800/1066MHz

Arrandale

Bandwidth
:8GB

INPUTS

+15V_ALW
+3.3V_RTC_LDO
+5V_ALW
+3.3V_ALW

TPS2231R

Slot 1

INPUTS

34

OUTPUTS
+1.5V_SUS
+0.75V_DDR_VTT
+V_DDR_REF

+PWR_SRC

19

New Card

SYSTEM DC/DC
34

(FPC Cable to Connect)

RGB CRT
8,9,10,11,12,13,14

10/100/1000LOM

PCIE x 1

CRT

RGB CRT

55

RGB CRT

USB 2.0 x 2

LVDS

74

DMIx4
2.5 GT/s

LVDS

FDI(UMA)
2.7 GT/s

100MHz
2.5Gbps

RGB CRT

B

PCIE x 1

64

WLAN 802.11a/b/g/n

Right Side:
USB x 1

USB 2.0 x 1

USB 2.0

High Definition Audio

480Mbps

SATA ports (6)

+VCC_GFX_CORE

63

INPUTS

OUTPUTS

+DC_IN
+PBATT

+PWR_SRC

SYSTEM DC/DC

Free fall sensor

SM Bus

USB 2.0 x 1

Bluetooth

40

73

400KHz

AZALIA

Azalia
CODEC

USB 2.0 x 1

Biometric

LPC Bus

78

+1.05V_VTT

LDO
INPUTS

24MHz

51

OUTPUTS

+3.3V_ALW

+1.8V_RUN

KBC
SM Bus

NUVOTON
NPCE781BA0DX

SPI

IDT
92HD81UA30

SATA
3Gbps

SATA,USB

OP AMP

HP OUT

B

APL5930

20,21,22,23,24,25,26,27,28

SPI

MIC IN

49

OUTPUTS

+PWR_SRC

ACPI 1.1
PCI/PCI BRIDGE

INPUTS

33MHz
Digital Mic Array

45

TPS51218

PCIE ports (8)

USB2.0 x 1

OUTPUTS

+PWR_SRC

BQ24745

480Mbps

LPC I/F
73

INPUTS

Mini-Card

ETHERNET (10/100/1000Mb)

32

CAMERA

USB 2.0 x 1

USB 2.0

14 USB 2.0/1.1 ports

REALTEK
RTS5138

86

TPS51218

CHARGER

Intel
PCH

CardReader
(3 in 1)
SD/MMC/MMC+
33

C

(On daughter board)

PCIE

LVDS

+CPU_GFXCORE

SYSTEM DC/DC

Left Side:
USB x 1

USB 2.0 x 1

OUTPUTS

+PWR_SRC

Mini-Card

PCIE x 1

53

ADP3211

WWAN/ WiMAX?

Switchable

LCD
(Single Chanel) 54

RJ45
CONN

35

RTL8111DL

50

TPS51116

Power SW

INPUTS
LVDS

Thermal & Fan

37

EMC2102

LDO

39,58

51

RT9025

Capacity Board

INPUTS

OUTPUTS

+3.3V_ALW

+1.8V_RUN_GPU

78

A

A

1st Samsung

Flash ROM
256kB 62
USB,ESATA
Multi-Port x1

1CH SPEAKER

63

ODD
HDD59

Touch
PAD

68

Int.
KB

Wistron Corporation

68

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Flash ROM

4MB

Title

62

60

5

D

OUTPUTS

SYSTEM DC/DC

18

PCIE x 1 & USB 2.0 x 1

C

46

RT8205B

Slot 0

DDRIII
1066

47,48

INPUTS

7

Nvidia
N11M-GE1(40nm)
80,81,82,83

91.4EX01.001
48.4EX01.001
09288
A00

+PWR_SRC

DDRIII 1066 Channel A

VRAM(gDDR3)
64Mbx16x4 (512MB)484,85

:
:
:
:

ISL62883

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

Block Diagram

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

2

of

88

5

4

3

2

1

D

D

+PWR_SRC

Adapter

TPS51116PWPRG4
50

ISL62883

ADP3211

Ε48

TPS51218

47

AO4407A
45

86

+V_DDR_REF

49

+0.75V_DDR_VTT

+1.5V_SUS

Charger
BQ24745
+PBATT

Battery

TPS51218DSCR

53

+VCC_CORE

+CPU_GFXCORE

+VCC_GFX_CORE

For Intel GPU

For NVIDIA GPU

+1.05V_VTT

FDS8880
87

45

Arrandale

: 1.05V

FDS8880

+1.5V_RUN_GPU

87

RT8205B
46

+1.05V_GFX_PCIE

AO3420

C

C

52

+5V_ALW

+5V_ALW2

42

+5V_ALW
+15V_ALW

AO4468

+3.3V_ALW_2
+1.5V_CPU

+3.3V_ALW

+3.3V_RTC_LDO

+1.5V_RUN

TPS2062AD

AO4468

I/O BD

+5V_USB2

+5V_RUN

For USB2

B

TPS2062AD

42

AO3403

63

+5V_USB1

TPS2231R

I/O BD

AO4468
34

+3.3V_LAN

+3.3V_CARDAUX

APL5930

+3.3V_RUN

RT9025
51

42

+1.8V_RUN

AO3434
51

TPS2231R
87

34

+1.8V_RUN_GPU

+3.3V_RUN_GPU

+1.5V_CARD

For USB1 & ESATA1

B

RTL8111DL

SI3456BDV

I/O BD

54

+1.2V_LOM

+LCDVDD

TPS2231R
34

+3.3V_CARD

Power Shape
Regulator

LDO

Switch

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Power Block Diagram

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

Rev

Winery13 MB DIS

Date: Wednesday, January 13, 2010

Sheet
1

A00
3

of

88

5

4

3

+3.3V_RUN

Θ

Θ

Θ Θ

+3.3V_RUN+3.3V_RUN

PCH

+3.3V_RUN

Θ

SRN2K2J-1-GP

PCH
D

SMBCLK

SMB_CLK

SMBDATA

SMB_DATA

ΘΘ

23

SRN2K2J-1-GP

ΘΘ
ΘΘ

+3.3V_RUN

SCL

18

SMBus Address:A0

SMB_DATA

B0

A

GND

S

LDDC_CLK_CON
LDDC_DATA_CON

07

Θ Θ

L_DDC_DATA
LDDC_DATA

Minicard
WLAN
PCH_SMBCLK
PCH_SMBDATA

ΘΘ

PCH_SMBCLK
PCH_SMBDATA

SMB_CLK
SMB_DATA

64

SMB_CLK
SMB_DATA

B1

VCC

B0

A

GND

54

S

CRT_DDC_CLK
CRT_DDC_DATA

+3.3V_RUN

Θ Θ

I/O BD

+3.3V_RUN

Θ

+3.3V_RUN

SRN2K2J-1-GP
SRN2K2J-1-GP

ΘΘ

LCD Conn.

NC7SB3157P6X-1GP

Minicard
WWAN

PCH_SMBCLK
PCH_SMBDATA

ΘΘ

+3.3V_RUN

SMBus address:D2

ΘΘ

D

SRN2K2J-1-GP

19

Clock
Generator

34

C

Θ

VCC

SMBus Address:A2

ΘΘ
SMB_DATA

+3.3V_RUN
B1

NC7SB3157P6X-1GP

PCH_SMBCLK
SCL
PCH_SMBDATA SDA

SMB_CLK

L_DDC_DATA

DIMM 2

PCH_SMBCLK
SMBCLK
PCH_SMBDATA SMBDATA

SMB_CLK

Θ Θ

L_DDC_CLK
LDDC_CLK

L_DDC_CLK

PCH_SMBDATA SDA

Express
Card

SRN2K2J-1-GP

SRN2K2J-1-GP

DIMM 1

PCH_SMBCLK

2N7002SPT

1

Switchable Graphic SMBus Block Diagram

PCH SMBus Block Diagram
+3.3V_ALW

2

Free fall
sensor
SCL/SPC
SDA/SDI/SDO

GMCH_DDCCLK
CRT_CLK_DDC

40

DY

+3.3V_RUN

Θ Θ

B1

VCC

B0

A

GND

S

DDC_CLK_CON2

+5V_CRT_RUN

Θ

Θ

+3.3V_RUN_GPU

Θ

NC7SB3157P6X-1GP

SRN2K2J-1-GP

DDC_CLK_CON

KBC SMBus Block Diagram

N11M-GE1

+5V_RUN

B

PSCLK1

TPDATA
TPCLK
+3.3V_RTC_LDO

CRT CONN
55

+3.3V_RUN

Θ Θ

GMCH_DDCDATA
CRT_DAT_DDC

B1

VCC

B0

A

GND

S

DDC_DATA_CON

DDC_DATA_CON2

Θ

NC7SB3157P6X-1GP

TouchPad Conn.

SRN10KJ-5-GP

PSDAT1

ΘΘ

2N7002DW-1-GP

I2CC_SCL
I2CC_SDA

Θ

C

ΘΘ

TPDATA

TPDATA

TPCLK

TPCLK

68
B

I2CA_SCL
I2CA_SDA

Θ

BQ24745
SCL
SDA

45

SMBus address:12
SRN4K7J-8-GP

SCL1

BAT_SCL

SDA1

BAT_SDA

ΘΘ

Θ
Θ

Battery Conn.
PBAT_SMBCLK1
PBAT_SMBDAT1

Θ

+3.3V_RTC_LDO

Θ
KBC_SCL1

GPIO74/SDA2

KBC_SDA1

Θ
Θ

Remove HDMI

IFPC_AUX_I2CW_SCL

+3.3V_RUN

Θ

SRN4K7J-8-GP

A

GPIO73/SCL2

44

DAT_SMB

SMBus address:16

SRN100J-3-GP

KBC
NPCE781

CLK_SMB

SRN4K7J-8-GP
+3.3V_RUN

Θ
Θ

IFPC_AUX_I2CW_SDA#

Thermal

THERM_SCL

SMCLK

THERM_SDA

SMDATA

39

A

SMBus address:7A
1st Samsung

2N7002DW-1-GP

Capacity
Board

THERM_SCL
THERM_SDA

SCL
SDA

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

(On daughter board)

Title

SMBus address:0A

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
C
Date:

SMBUS Block Diagram

Document Number

Rev

A00

Winery13 MB DIS
Sheet

Wednesday, January 13, 2010
1

4

of

88

A

B

C

Thermal Block Diagram

D

E

Audio Block Diagram

1

1

SPEAKER
SPKR_PORT_D_LSPKR_PORT_D_L+

AUD_SPK_L-

AUD_SPK_L-_C

AUD_SPK_L+

AUD_SPK_L+_C
0R3-0-U-V-GP

DP1

EMC2102_DP1

60
MMBT3904-3-GP
SC470P50V3JN-2GP

2

DN1

Q3905

EMC2102_DN1

2

Close to PCH

Thermal
EMC2102
DP2

VGA_THERMDA

DPLUS

VGA_THERMDC

AUD_HP1_JACK_L

HP1_PORT_B_R

AUD_HP1_JACK_R

HP
OUT

Codec
92HD81

60

GPU

SC470P50V3JN-2GP
DN2

HP1_PORT_B_L

DMINUS

54

DIS

HP0_PORT_A_L

AUD_EXT_MIC_L

HP0_PORT_A_R

AUD_EXT_MIC_R

VREFOUT_A_OR_F

AUD_VREFOUT_B

MIC
IN
60

3

3

DP3

T8_THERMDC

33R2J-2-GP
DMIC_CLK/GPIO1

AUD_DMIC_CLK

AUD_DMIC_CLK_G

MMBT3904-3-GP
DMIC0/GPIO2

SC470P50V3JN-2GP
DN3

Q3901

T8_THERMDA

AUD_DMIC_IN0
33R2J-2-GP

AUD_DMIC_IN0_R

Digital
MIC
Array
73

HW T8 sensor

39

30

4

4

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Thermal/Audio Block Diagram

A

http://laptop-motherboard-schematic.blogspot.com/
B

C

D

Size
Document Number
Custom

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
E

5

of

88

A

PCH Strapping
Name
SPKR

4

INIT3_3V#
GNT3#/
GPIO55

INTVRMEN

GNT0#,
GNT1#

B

C

Calpella Schematic Checklist Rev1.6

D

Processor Strapping Calpella

Schematics Notes
Reboot option at power-up
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kȍ
- 10-kȍ weak pull-up resistor.
Intel suggest 1K resistor (Fonseca)
Internal pull-up. Leave as "No Connect"
Default Mode: Internal pull-up.
Low (0) = Top Block Swap Mode
Note: Connect to ground with 4.7-kȍ weak pull-down resistor.
CRB uses a 1 kȍ; do not stuff resistor.

E

Schematic Checklist Rev1.6

Pin Name

Strap Description

Configuration (Default value for each bit is
1 unless specified otherwise)

Default
Value

CFG[4]

Embedded
DisplayPort
Presence

1: Disabled - No Physical Display Port attached to
Embedded DisplayPort.
0: Enabled - An external Display Port device is
connected to the Embedded Display Port.

1

CFG[3]

PCI-Express Static
Lane Reversal

1: Normal Operation.
0: Lane Numbers Reversed

1

PCI-Express
Configuration
Select

1: Single PCI-Express Graphics
0: Bifurcation enabled

CFG[0]

4

15 -> 0, 14 -> 1, ...
1

High (1) = Integrated VRM is enabled
Low (0) = Integrated VRM is disabled
Note: CRB uses a 330-kȍ resistor.
Default (SPI): Leave both GNT0# and GNT1# floating. No pull up
required.
Boot from PCI:
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-kȍ
Connect GNT1# to ground with 1-kȍ pull-down
pull-down resistor.
resistor. Leave GNT0# Floating.

GNT2#/
GPIO53

3

SPI_MOSI

NV_ALE

NC_CLE
HAD_DOCK_EN#
/GPIO[33]

Enable Intel Anti-Theft Technology:Connect to Vcc3_3
with 8.2-kȍ weak pull-up resistor.
Disable Intel Anti-Theft Technology:Left floating, no pull-down
required.

LANE1

Card reader

LANE2

MiniCard WLAN

LANE3

LAN

DMI termination voltage. Weak internal pull-up. Do not pull low.

LANE4

MiniCard WWAN

LANE5

New Card

Low (0)- Flash Descriptor Security will be overridden. Also, when
this signals is sampled on the rising edge of PWROK then it will also
disable Intel ME and its features.
High (1)-:Security measure defined in the Flash Descriptor
will be enabled.

HDA_SDO

HDA_SYNC

GPIO15

3

PCIE Routing

Enable Intel Anti-Theft Technology:Connect to +NVRAM_Vccq with
8.2-kȍ weak pull-up resistor.[CRB has it pulled up with 1-kȍ
no-stuff resistor]
Disable Intel Anti-Theft Technology:Leave floating (internal pull-down)

Platform design should provide appropriate pull-up or pull-down
depending on the desired settings. If a jumper option is used to
tie this signal to GND as required by the functional strap,
the signal should be pulled low through a weak pull-down in order
to avoid asserting HDA_DOCK_EN# inadvertently.
Note:CRB recommends 1-kȍ pull-down for FD Override.
There is an internal pull-up of 20 kȍ for HDA_DOCK_EN# which is only
enabled at boot/reset for strapping functions.

2

1

Default - Internal pull-up.
Low (0)= Configures DMI for ESI compatible operation (for servers
only. Not for mobile/desktops).

USB Table
USB
Pair

Device

0

USB1

1

USB for ESATA

2

USB2

3

RESERVE

4

WLAN

Weak internal pull-down. Do not pull high.
Sampled at rising edge of RSMRST#.

5

WWAN

Weak internal pull-down. Do not pull high.
Sampled at rising edge of RSMRST#.

7
8

BlUETOOTH

Low (0)-Intel ME Crypto Transport Layer Security (TLS) cipher suite
with no confidentiality
High (1)-:Intel ME Crypto Transport Layer Security (TLS) cipher suite
with confidentiality
Note:
This is an unmuxed signal.
This signal has a weak internal pull-down of 20 Kȍ which is enabled
when PWROK is low.
Sampled at rising edge of RSMRST#.
CRB has a 1-kȍ pull-up on this signal to +3.3VA rail.

9

Card Reader

10

Biometric

11

CAMERA

12

New Card

13

RESERVED

6

2

RESERVED

(Not available for HM55)

RESERVED

(Not available for HM55)

1

1st Samsung

GPIO8

Weak internal pull-up. Do not pull low.
Sampled at rising edge of RSMRST#.

GPIO27

Default = Do not connect (floating). Internal pull-up.
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.

Wistron Corporation

http://laptop-motherboard-schematic.blogspot.com/

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Document Number
Custom

Table of Content

Rev

A00

Winery13 MB DIS

Date: Wednesday, January 13, 2010

Sheet

6

of

88

5

4

3

2

1

SSID = Clock GEN
D

D

+1.05V_VTT

2
1

RN
RN

3
4

[23] CLK_CPU_BCLK#
[23] CLK_CPU_BCLK

RN704
0R4P2R-PAD

11
10

SRC_1/SATA#
SRC_1/SATA

1
2

R701 2

+3.3V_RUN
1 2K2R2J-2-GP

R703 2

1 33R2J-2-GP

SDA
SCL

31
32

1 33R2J-2-GP
1 33R2J-2-GP

CLK_VGA_27M [81]

DY

D

S

CLK_PCH_14M [23]
EC701
SC4D7P50V2CN-1GP

Q701
2N7002A-7-GP

1ST: 84.2N702.E31
2ND: 84.2N702.D31

PCH_SMBDATA [18,19,23,40,64,76]
PCH_SMBCLK [18,19,23,40,64,76]

CLK_XTAL_IN

B

X701

1

CLK_XTAL_OUT

2

1

X-14D31818M-37GP
C714
SC12P50V2JN-3GP

2

1st Silego 71.08585.003
2nd ICS
71.93197.003

C715
SC12P50V2JN-3GP

CLK_VGA_27M

DY
CLK_VGA_27M_RC

2

1st: HARMONY 82.30005.901
2nd: ITTI 82.30005.C51
3rd: TXC 82.30005.B81

DY
FSC

FSC

0

1

DY C718
SC4D7P50V2CN-1GP
1

R707
10KR2J-3-GP

2

2 1

R749
0R2J-2-GP

1

+1.05V_VTT

R704
4K7R2J-2-GP

VR_CLKEN# [47]

R705
10KR2J-3-GP
CK_PW RGD

CLK_XTAL_IN
CLK_XTAL_OUT

9

8

2

12

DY
DY

VSS_SATA

CPU_1#
CPU_1
VSS_27

19
20

VSS_DOT

1
1

TP_CPU_1#
TP_CPU_1

VSS_SRC

28
27

VSS_CPU

1

CPU_STOP#
CK_PW RGD
FSC

XTAL_IN
XTAL_OUT

VSS_REF

2

16
25
30

CPU_0#
CPU_0

21

2

R706 2
R710 2

22
23

SLG8SP585VTR-GP

1

1
2

18

15

1

5
VDD_27

29
VDD_REF

VDD_DOT

17
VDD_SRC

VDD_CPU_IO

CLK_27M
CLK_27M_SS

CLK_CPU_BCLK1#
CLK_CPU_BCLK1

33

B

6
7

4
3

GND

TP701
TP702

CLK_PCIE_SATA1#
CLK_PCIE_SATA1

CPU_STOP#
CKPWRGD/PD#
REF_0/CPU_SEL

26

TPAD14-GP
TPAD14-GP

1
2

SRC_2#
SRC_2

+3.3V_RUN_SL585

G

RN703
0R4P2R-PAD

14
13

Mount

Mount DY

2

[23] CLK_PCIE_SATA#
[23] CLK_PCIE_SATA

CLK_IN_DMI#
CLK_IN_DMI

DY

NON-SS

1

RN

3
4

27MHZ
27MHZ_SS

SS

2

2
1

DOT_96#
DOT_96

R710

1

RN702
0R4P2R-PAD

[23] CLKIN_DMI#
[23] CLKIN_DMI

4
3

C

R706

2

CLK_MCH_DREFCLK1#
CLK_MCH_DREFCLK1

C712
SCD1U10V2KX-5GP

1

3
4

C711
SCD1U10V2KX-5GP

VGA 27M

2

2
1

RN

RN701
0R4P2R-PAD

C710
SC10U10V5ZY-1GP

+1.05V_RUN_SL585_IO

VDD_SRC_IO

1

A00-0104-1
[23] DREFCLK#
[23] DREFCLK

24
VDD_CPU

U701

A00-0104-1
C709
SC1U6D3V2KX-GP

DY

+3.3V_RUN_SL585

C

+1.05V_RUN_SL585_IO

1 R709
2
0R0603-PAD-2-GP

C708
SCD1U10V2KX-5GP

2

1

C707
SCD1U10V2KX-5GP

2

C705
SCD1U10V2KX-5GP

1
2

1

C704
SCD1U10V2KX-5GP

SC-1130-1
change C701 to 4.7pF for RF

2

2

DY

2

1

1

1

A00-0104-1

2

C701
SC4D7P50V2CN-1GP

C703
SCD1U10V2KX-5GP

+3.3V_RUN_SL585

1 R708
2
0R0603-PAD-2-GP

C702
SC10U10V5ZY-1GP

+3.3V_RUN

133MHz
1

SPEED

100MHz
(Default)

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Clock Generator SLG8SP585

Document Number

Rev

Winery13 MB DIS
Date:

W ednesday, January 13, 2010

Sheet
1

7

of

A00
88

5

4

3

2

1

SSID = CPU
D

D
1 OF 9

DMI_RX#0
DMI_RX#1
DMI_RX#2
DMI_RX#3

[22]
[22]
[22]
[22]

DMI_PTX_CRXP0
DMI_PTX_CRXP1
DMI_PTX_CRXP2
DMI_PTX_CRXP3

B24
D23
B23
A22

DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3

[22]
[22]
[22]
[22]

DMI_CTX_PRXN0
DMI_CTX_PRXN1
DMI_CTX_PRXN2
DMI_CTX_PRXN3

D24
G24
F23
H23

DMI_TX#0
DMI_TX#1
DMI_TX#2
DMI_TX#3

[22]
[22]
[22]
[22]

DMI_CTX_PRXP0
DMI_CTX_PRXP1
DMI_CTX_PRXP2
DMI_CTX_PRXP3

D25
F24
E23
G23

DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3

[22]
[22]
[22]
[22]
[22]
[22]
[22]
[22]

FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7

FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7

E22
D21
D19
D18
G21
E19
F21
G18

FDI_TX#0
FDI_TX#1
FDI_TX#2
FDI_TX#3
FDI_TX#4
FDI_TX#5
FDI_TX#6
FDI_TX#7

[22]
[22]
[22]
[22]
[22]
[22]
[22]
[22]

FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7

FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7

D22
C21
D20
C18
G22
E20
F20
G19

FDI_TX0
FDI_TX1
FDI_TX2
FDI_TX3
FDI_TX4
FDI_TX5
FDI_TX6
FDI_TX7

[22] FDI_FSYNC0
[22] FDI_FSYNC1

F17
E17

FDI_FSYNC0
FDI_FSYNC1

[22] FDI_INT

C17

FDI_INT

[22] FDI_LSYNC0
[22] FDI_LSYNC1

F18
D17

FDI_LSYNC0
FDI_LSYNC1

Calpella Platform Design Guide
Revision 1.6
Page 89

2.4 Arrandale Graphics Disable Guideline
It applies to Arrandale and Clarksfield discrete graphic designs.
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Arrandale. The GFX_IMON,
FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT signals on
the Arrandale side should be tied to GND (through 1-kȍ ±5% resistors).

PCI EXPRESS -- GRAPHICS

A24
C23
B22
A21

B26
A26
B27
A25

PEG_IRCOMP_R

PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
PEG_RX#9
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

PCIE_MRX_GTX_N15
PCIE_MRX_GTX_N14
PCIE_MRX_GTX_N13
PCIE_MRX_GTX_N12
PCIE_MRX_GTX_N11
PCIE_MRX_GTX_N10
PCIE_MRX_GTX_N9
PCIE_MRX_GTX_N8
PCIE_MRX_GTX_N7
PCIE_MRX_GTX_N6
PCIE_MRX_GTX_N5
PCIE_MRX_GTX_N4
PCIE_MRX_GTX_N3
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_N1
PCIE_MRX_GTX_N0

PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

PCIE_MRX_GTX_P15
PCIE_MRX_GTX_P14
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_P12
PCIE_MRX_GTX_P11
PCIE_MRX_GTX_P10
PCIE_MRX_GTX_P9
PCIE_MRX_GTX_P8
PCIE_MRX_GTX_P7
PCIE_MRX_GTX_P6
PCIE_MRX_GTX_P5
PCIE_MRX_GTX_P4
PCIE_MRX_GTX_P3
PCIE_MRX_GTX_P2
PCIE_MRX_GTX_P1
PCIE_MRX_GTX_P0

PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9
PEG_TX#10
PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

PCIE_MTX_GRX_C_N15
PCIE_MTX_GRX_C_N14
PCIE_MTX_GRX_C_N13
PCIE_MTX_GRX_C_N12
PCIE_MTX_GRX_C_N11
PCIE_MTX_GRX_C_N10
PCIE_MTX_GRX_C_N9
PCIE_MTX_GRX_C_N8
PCIE_MTX_GRX_C_N7
PCIE_MTX_GRX_C_N6
PCIE_MTX_GRX_C_N5
PCIE_MTX_GRX_C_N4
PCIE_MTX_GRX_C_N3
PCIE_MTX_GRX_C_N2
PCIE_MTX_GRX_C_N1
PCIE_MTX_GRX_C_N0

C829
C827
C832
C812
C803
C811
C828
C810
C823
C804
C831
C825
C821
C813
C806
C816

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

PCIE_MTX_GRX_N15
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N0

PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

PCIE_MTX_GRX_C_P15
PCIE_MTX_GRX_C_P14
PCIE_MTX_GRX_C_P13
PCIE_MTX_GRX_C_P12
PCIE_MTX_GRX_C_P11
PCIE_MTX_GRX_C_P10
PCIE_MTX_GRX_C_P9
PCIE_MTX_GRX_C_P8
PCIE_MTX_GRX_C_P7
PCIE_MTX_GRX_C_P6
PCIE_MTX_GRX_C_P5
PCIE_MTX_GRX_C_P4
PCIE_MTX_GRX_C_P3
PCIE_MTX_GRX_C_P2
PCIE_MTX_GRX_C_P1
PCIE_MTX_GRX_C_P0

C826
C822
C818
C815
C808
C802
C820
C805
C817
C801
C814
C824
C830
C809
C807
C819

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP

PCIE_MTX_GRX_P15
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P0

Intel(R) FDI

B

DMI_PTX_CRXN0
DMI_PTX_CRXN1
DMI_PTX_CRXN2
DMI_PTX_CRXN3

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS

DMI

C

[22]
[22]
[22]
[22]

CLARKSFIELD

CPU1A

R801 1
R802 1

2 49D9R2F-GP
2 750R2F-GP

EXP_RBIAS
PCIE_MRX_GTX_N[0..15]

PCIE_MRX_GTX_P[0..15]

PCIE_MRX_GTX_N[0..15] [80]

PCIE_MRX_GTX_P[0..15] [80]

C

PCIE_MTX_GRX_N[0..15]

PCIE_MTX_GRX_N[0..15] [80]

B
PCIE_MTX_GRX_P[0..15]

PCIE_MTX_GRX_P[0..15] [80]

CLARKUNF

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

http://laptop-motherboard-schematic.blogspot.com/

Size

CPU (PCIE/DMI/FDI)

Document Number

Rev

Winery13 MB DIS
Date:

W ednesday, January 13, 2010

Sheet

8

of

A00
88

3

Check
2
SA 07/01
1.assign GPIO EC_GPIO91 ??

SB-1022
RN901 change to 22 ohm

2 OF 9

H_PROCHOT_R#

1

2

1

2

R903

TPAD14-GP

AT24

COMP2

H_COMP1

G16

COMP1

H_COMP0

AT26

COMP0

20R2F-GP

R905

49D9R2F-GP

R906

D

H_COMP2

49D9R2F-GP
TP901

SKTOCC#_R

1

AH24

H_CATERR#

[25] H_PECI

DY

[25,37,42]

H_PROCHOT_R#

2

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

H_THRMTRIP#

THERMTRIP#

SB-1026
1. remove 1K ohm for remove XDP
AP26

RESET_OBS#

AL15

[22] H_PM_SYNC

PM_SYNC

AN14

C
H_PWRGOOD

VCCPW RGOOD_1

AN27

VCCPW RGOOD_0

[22] PM_DRAM_PWRGD

AK13

SM_DRAMPW ROK

[49] H_VTTPWRGD

AM15

VTTPW RGOOD

AM26

TAPPW RGOOD

[25,42] H_PWRGOOD

TPAD14-GP

1 TP_TAPPWRGOOD

TP903
R913

PLT_RST#

1

PLT_RST#_R

2

1K6R2F-GP

AL14

AR30
AT30

BCLK_CPU_P_R
BCLK_CPU_N_R

2
1

Check

3
4

PEG_CLK
PEG_CLK#

E16
D16

PEG_CLK_R
PEG_CLK#_R

DPLL_REF_SSCLK
DPLL_REF_SSCLK#

A18
A17

DPLL_REF_SSCLK_R
DPLL_REF_SSCLK#_R

1
2
2
1

RN901
SRN22J-7-GP

BCLK_CPU_P [25]
BCLK_CPU_N [25]

3
4

CLK_EXP_P [23]
CLK_EXP_N [23]

SRN1KJ-7-GP
RN904

F6
AL1
AM1
AN1

PM_EXT_TS#0
PM_EXT_TS#1

AN15
AP15

SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

4
3

AT28
AP27

TCK
TMS
TRST#

AN28
AP28
AT27

TDI
TDO
TDI_M
TDO_M

AT29
AR27
AR29
AP29

DBR#

AN25

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

SB-1103
change Q901 to 84.00138.F31

D

D

DDR3_DRAMRST# [18,19]

Vgs(th)<=1.5V

1
2

PM_EXTTS#0_C
PM_EXTTS#1_C

1ST: 84.00138.E31
2ND:

R935

SRN10KJ-5-GP
1
4
2
3
RN906
0R4P2R-PAD

1
PM_EXTTS#0 [18]
PM_EXTTS#1 [19]

DY

SM_DRAMRST#

1

2

R988
100KR2J-1-GP

2

SB-1023
pop R988 for S3
reduce function

0R2J-2-GP

Calpella Platform S3 Power Reduction Platform
S3 Power Reduction CRB Implementation
Design Details Revision 0.1

A00-0104-1

Check
PRDY#
PREQ#

2
10KR2J-3-GP

+1.05V_VTT

SM_DRAMRST#
RN905

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

DDR_RST_GATE#1
R937
R934
1KR2J-1-GP

Q901
BSS138-7-F-GP

S
SM_DRAMRST#

+1.5V_SUS

A00-0104-1
4 RN903
3 0R4P2R-PAD

+3.3V_ALW

C915
SCD047U10V2KX-2GP

R923
XDP_TRST# 1

DDR3 Compensation Signals

2
51R2J-2-GP

XDP_TDO_R
TDI_M
1 R908
2
TDO_M
0R0402-PAD-2-GP
H_DBR#_R

1 R909
2
0R0402-PAD-2-GP

A00-0104-1

SM_RCOMP_0

R907 1

2 100R2F-L1-GP-U

SM_RCOMP_1

R910 1

2 24D9R2F-L-GP

SM_RCOMP_2

R911 1

2 130R2F-1-GP

C

XDP_DBRESET# [22]

+1.05V_VTT

R928
XDP_TDO_R

RSTIN#

2

1
51R2J-2-GP

1

[21,34,36,37,64,70,76,80]

PWR MANAGEMENT

TP902
1 TP_RESET_OBS#
TPAD14-GP

DDR_RST_GATE# [25]

A16
B16

RN

[47] H_PROCHOT#

R936
0R2J-2-GP
1

AK14

BCLK_ITP
BCLK_ITP#

THERMAL

SSID = CPU

SKTOCC#

BCLK
BCLK#

1

2 68R2-GP

2

2

R933 1

1

CLOCKS

H_CATERR#

COMP3

RN

2 49D9R2F-GP

AT23

MISC

R902 1

H_COMP3
20R2F-GP

DDR3
MISC

2

JTAG & BPM

1
R901

1

CPU1B

Processor Pullups

CLARKSFIELD

+1.05V_VTT

1

SB-1020-1
DY R935, POP C915,R934, Q901

2

4
Processor Compensation Signals

G

5

R915
750R2F-GP

CLARKUNF

2

Check
Normal
+3.3V_ALW

R920

R977

AUB

1.27k

3k

1.6k(DY)

CFD

1.1k

3k

1.5k(DY)

R919

+1.5V_CPU

B

1

2 10KR2J-3-GP
R919
1K27R2F-L-GP

U927

[37,49,52] VTT_PWRGD

1

B

2

A

3

GND

VCC

5

Y

4

74LVC1G08GW-1-GP

R977
VTT_PWRGD_R3 2

DY
2

U927_B

B

1

S3 Power Reduction circuit

PM_DRAM_PWRGD

1

R989 1

1K6R2F-GP

R920

R977

AUB

1.1k(DY)

R919

0.75k

1.6k

CFD

1.1k(DY)

0.75k

1.5k

R920
750R2F-GP

2

1ST: 73.01G08.L04
2ND:

SB-1020-1
POP R977 for S3 redution
DY R919, change R920 to 0.75K

Remove XDP function for layout concern

A

1st Samsung

A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Size

CPU (THERMAL/CLOCK/PM )

Document Number

Rev

Winery13 MB DIS
Date:

5

4

3

2

http://laptop-motherboard-schematic.blogspot.com/

Sheet

Wednesday, January 13, 2010

1

9

of

A00
88

5

4

3

2

SSID = CPU

C

B

[18] M_A_BS0
[18] M_A_BS1
[18] M_A_BS2

AC3
AB2
U7

[18] M_A_CAS#
[18] M_A_RAS#
[18] M_A_W E#

AE1
AB3
AE9

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

SA_CK1
SA_CK#1
SA_CKE1

Y6
Y5
P6

M_CLK_DDR1 [18]
M_CLK_DDR#1 [18]
M_CKE1 [18]

SA_CS#0
SA_CS#1

AE2
AE8

M_CS0# [18]
M_CS1# [18]

SA_ODT0
SA_ODT1

AD8
AF9

M_ODT0 [18]
M_ODT1 [18]

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

B9
D7
H7
M7
AG6
AM7
AN10
AN13

M_B_DQ[63..0]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_CLK_DDR0 [18]
M_CLK_DDR#0 [18]
M_CKE0 [18]

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DM[7..0] [18]
M_A_DQS#[7..0] [18]
M_A_DQS[7..0] [18]

SA_BS0
SA_BS1
SA_BS2

SA_CAS#
SA_RAS#
SA_WE#

SA_DQS#0
SA_DQS#1
SA_DQS#2
SA_DQS#3
SA_DQS#4
SA_DQS#5
SA_DQS#6
SA_DQS#7

C9
F8
J9
N9
AH7
AK9
AP11
AT13

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

C8
F9
H9
M9
AH8
AK10
AN11
AR13

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_A[15..0] [18]

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5
AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10

CLARKSFIELD

A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G8
K7
J8
G7
G10
J7
J10
L7
M6
M8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14

[19] M_B_DQ[63..0]

AA6
AA7
P7

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

[19] M_B_BS0
[19] M_B_BS1
[19] M_B_BS2

AB1
W5
R7

SB_BS0
SB_BS1
SB_BS2

[19] M_B_CAS#
[19] M_B_RAS#
[19] M_B_W E#

AC5
Y7
AC6

SB_CAS#
SB_RAS#
SB_WE#

SB_CK0
SB_CK#0
SB_CKE0

W8
W9
M3

M_CLK_DDR2 [19]
M_CLK_DDR#2 [19]
M_CKE2 [19]

SB_CK1
SB_CK#1
SB_CKE1

V7
V6
M2

M_CLK_DDR3 [19]
M_CLK_DDR#3 [19]
M_CKE3 [19]

SB_CS#0
SB_CS#1

AB8
AD6

M_CS2# [19]
M_CS3# [19]

SB_ODT0
SB_ODT1

AC7
AD1

M_ODT2 [19]
M_ODT3 [19]

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

D4
E1
H3
K1
AH1
AL2
AR4
AT8

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7

D5
F4
J4
L4
AH2
AL4
AR5
AR8

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

C5
E3
H4
M5
AG2
AL5
AP5
AR7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

D

M_B_DM[7..0] [19]
M_B_DQS#[7..0] [19]
M_B_DQS[7..0] [19]

DDR SYSTEM MEMORY - B

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

CLARKSFIELD

M_A_DQ[63..0]

SA_CK0
SA_CK#0
SA_CKE0

DDR SYSTEM MEMORY A

[18] M_A_DQ[63..0]

4 OF 9

CPU1D
3 OF 9

CPU1C

D

1

M_B_A[15..0] [19]

C

B

CLARKUNF
CLARKUNF

A

1st Samsung

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Document Number

CPU (DDR)

Rev

Winery13 MB DIS
Date:

W ednesday, January 13, 2010

Sheet
1

10

of

A00
88

5

4

3

2

1

SSID = CPU
CPU1E

5 OF 9

RSVD#AJ13
RSVD#AJ12

1

CFG0

1
1

SA_DIMM_VREF#
SB_DIMM_VREF#

1:Single PEG
0:Bifurcation enabled

2

DY

TP1116
TP1117

PCI-Express Configuration Select
R1101
3KR2F-GP

DIS

‫ޏ‬5%

CFG0

CFG3
CFG4

CFG3

1

CFG3 - PCI-Express Static Lane Reversal
R1102
3KR2F-GP

CFG3
2

C

1 :Normal Operation
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...

DW
07/10 Reversal
1.PCI-Express Static Lane Reversal

AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16

RSVD#AP25
RSVD#AL25
RSVD#AL24
RSVD#AL22
RSVD#AJ33
RSVD#AG9
RSVD#M27
RSVD#L28
SA_DIMM_VREF
SB_DIMM_VREF
RSVD#G25
RSVD#G17
RSVD#E31
RSVD#E30

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
RSVD_TP_86

CFG4

1

CFG4 - Display Port Presence
CFG4

2

DY

R1103
3KR2F-GP

B19
A19
TPAD14-GP
TPAD14-GP

1:Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port

TP1119
TP1120

1
1

TP_H_RSVD17_R A20
TP_H_RSVD18_R B20

U9
T9
AC9
AB9

RSVD#AH25
RSVD#AK26
RSVD#AL26
RSVD_NCTF_37
RSVD#AJ26
RSVD#AJ27

RSVD#AL28
RSVD#AL29
RSVD#AP30
RSVD#AP32
RSVD#AL27
RSVD#AT31
RSVD#AT32
RSVD#AP33
RSVD#AR33

RESERVED

CFG0

AP25
AL25
AL24
AL22
AJ33
AG9
M27
L28
J17
H17
G25
G17
E31
E30

CLARKSFIELD

D

LVDS Switching

J29
J28

B

Switchable GFX, just like integrated GFX only, to enable LVDS it is required that the
OEM set the LDVS (L_DDC_DATA) strap to present (pulled up) and the eDP strap
(CFG[4]) to disabled (not pulled down).
4.8.3.2

D

AH25
AK26
AL26
AR2
AJ26
AJ27

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33

C

RSVD#AR32
RSVD_TP#E15
RSVD_TP#F15
KEY
RSVD#D15
RSVD#C15
RSVD#AJ15
RSVD#AH15

AR32
E15
F15
A2
D15
C15
AJ15
AH15

TP_RSVD64_R
TP_RSVD65_R

1
1

TP1121
TP1122

TPAD14-GP
TPAD14-GP

RSVD#B19
RSVD#A19
RSVD#A20
RSVD#B20
SA_CK2
SA_CK#2
SA_CKE2
SA_CS#2
SA_ODT2
SA_CK3
SA_CK#3
SA_CKE3
SA_CS#3
SA_ODT3

RSVD#U9
RSVD#T9
RSVD#AC9
RSVD#AB9

Calpella Platform Design Guide
Revision 1.6
4.8.3.1

AJ13
AJ12

SB_CK2
SB_CK#2
SB_CKE2
SB_CS#2
SB_ODT2
SB_CK3
SB_CK#3
SB_CKE3
SB_CS#3
SB_ODT3

RSVD#J29
RSVD#J28

eDP Switching

eDP for Switchable GFX can only be driven out of Port D of PCH. To configure Port D for
embedded DP it is required to set the DDPD_CTRLDATA strap high to 3.3V Core rail
through 2.2 kȍ ±5% resistor, LVDS (L_DDC_DATA) strap as no connect and the eDP
strap CFG[4] as no connect.
Page 482,486

VSS

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

B

AP34

CLARKUNF

DW
CFG7(Reserved) - Temporarily used for early
Clarksfield samples.
CFG7

A

DW30 Only support Arrandale,
CFG7 no need pull down

07/02 Added
1.Added display Switchable strap commentariat

Clarksfield (only for early samples pre-ES1) Connect to GND with 3.01K Ohm/5% resistor.
Note: Only temporary for early CFD sample
(rPGA/BGA) [For details please refer to the
WW33 MoW and sighting report].
For a common M/B design (for AUB and CFD),
the pull-down resistor shouble be used. Does
not impact AUB functionality.

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

CPU (RESERVED)

Document Number

Rev

A00

Winery13 MB DIS
Date:

Wednesday, January 13, 2010

Sheet
1

11

of

88

5

4

3

CPU1F

2

1

6 OF 9

SSID = CPU
+VCC_CORE

1

1

2

2

2

2

2

2

1

1

1

1

1
2

1
2

1

1

C1221

DY
2

1
2

1

DY
2

1.1V RAIL POWER

2

CLARKSFIELD

D

The decoupling capacitors, filter
recommendations and sense resistors on the
CPU/PCH Rails are specific to the CRB
Implementation. Customers need to follow the
recommendations in the Calpella Platform
Design Guide.

C1222

2

DY

C1234

1

C1233

2

1

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

C

Please note that the VTT Rail
Values are
Arrandale VTT=1.05V;
Clarksfield VTT=1.1V
PSI#

CPU VIDS

POWER

VID
VID
VID
VID
VID
VID
VID
PROC_DPRSLPVR

VTT_SELECT

AN33

H_VTTVID1 = Low, 1.1V
H_VTTVID1 = High, 1.05V

PSI# [47]

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

G15

TP_H_VTTVID1

CPU_VID[6..0]

[47]

SA
PM_DPRSLPVR

07/01 Check
1.DPRSLPVR ??

[47]

B

1

TP1203

TPAD14-GP

1

+VCC_CORE

AJ34
AJ35

R1201
100R2F-L1-GP-U

IMVP_IMON [47]

VCC_SENSE
VSS_SENSE

VCC_SENSE [47]
VSS_SENSE [47]

1

VCC_SENSE
VSS_SENSE

AN35

2

ISENSE

VTT_SENSE
VSS_SENSE_VTT

B15
A15

TP_VSS_SENSE_VTT 1

R1204
100R2F-L1-GP-U

VTT_SENSE [49]
TP1202
TPAD14-GP

2

1
2
1
2

1
2
1
2

1
2
1
2
1
2
1
2

1
2
1
2
1
2
1
2

1
2
1
2
1
2
1
2

1
2
1
2
1
2
1
2

1
2
1
2
1
2
1
2

1
2
1
2
1
2

DY
SC1U6D3V2KX-GP

1

C1205

SC22U6D3V5MX-2GP

2

C1204
SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

1

C1219

+1.05V_VTT

C1211

SC10U6D3V5KX-1GP

2

C1218
SC10U6D3V5KX-1GP

B

C1217

SC10U6D3V5MX-3GP

SC-1207-1
pop C1243 and change size to 0603 for EMI

C1216

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

C1243
SCD1U50V3KX-GP

C1203

SC10U6D3V5MX-3GP

C1242

DY

C1202

+1.05V_VTT

VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0

CPU CORE SUPPLY

C1241

DY

C1232

DY

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
C1240

C1231

DY

C1201

SC10U6D3V5KX-1GP

C1230

+1.05V_VTT

SC10U6D3V5KX-1GP

C1224

DY

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

SC10U6D3V5KX-1GP

DY

SC10U6D3V5KX-1GP

C1239

C1210
SC10U6D3V5KX-1GP

C1229
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
C1238

C1223
SC22U6D3V5MX-2GP

C1228

C1220
SC22U6D3V5MX-2GP

C1215
SC10U6D3V5KX-1GP

C1237

DY

C1209
SC10U6D3V5KX-1GP

C1227
SC22U6D3V5MX-2GP

C1236

DY

C1214
SC10U6D3V5KX-1GP

C1235

DY

C1226
SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

C

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1225

C1213

DY

C1208
SC10U6D3V5KX-1GP

C1212

DY

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

DY

C1207

18A
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0

SC10U6D3V5KX-1GP

C1206

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

SC10U6D3V5KX-1GP

48A (Arburdale)

+VCC_CORE
D

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

SENSE LINES

PROCESSOR CORE POWER

A

A

1st Samsung
CLARKUNF

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

http://laptop-motherboard-schematic.blogspot.com/
Date:

5

CPU (VCC_CORE)

Document Number

4

3

2

Wednesday, January 13, 2010

Rev

A00

Winery13 MB DIS
Sheet
1

12

of

88

2

1

DYC1377

+1.5V_SUS

GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON

AR25
AT25
AM24

GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
GFX_VID5
GFX_VID6

1

[53]
[53]
[53]
[53]
[53]
[53]
[53]

GFX_VR_EN [53]
TP1303TPAD14-GP

TP_GFX_DPRSLPVR1

GFX_IMON [53]

C1307

1

C1306

DY
2

C1305

2

C1304

1

1

C1303

2

C1302

1

1

1

VCCPLL
VCCPLL
VCCPLL

L26
L27
M26

C1301

2

VTT1
VTT1
VTT1
VTT1
VTT1
VTT1

J22
J20
J18
H21
H20
H19

1

VTT0
VTT0
VTT0
VTT0

P10
N10
L10
K10

+1.5V_CPU

3A
2

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

1

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

SC10U6D3V5KX-1GP

TC1301
SE330U2D5VDM-2GP
C

C1310
SC10U6D3V5MX-3GP

1

+1.05V_VTT

1
2

DY

C1311
SC10U6D3V5KX-1GP

2

- 1.5V RAILS

For no use switch graphic function

DDR3

SENSE
LINES

AM22
AP22
AN22
AP23
AM23
AP24
AN24

2

GRAPHICS VIDs

CLARKSFIELD

GFX_VID
GFX_VID
GFX_VID
GFX_VID
GFX_VID
GFX_VID
GFX_VID

SC10U6D3V5KX-1GP

1

SCD1U10V2KX-4GP

+1.5V_SUS

D

SCD1U10V2KX-4GP

1

+1.5V_SUS

VCC_AXG_SENSE [53]
VSS_AXG_SENSE [53]

SCD1U16V2KX-3GP

2

AR22
AT22

SCD1U10V2KX-4GP

VTT1
VTT1
VTT1

VAXG_SENSE
VSSAXG_SENSE

SCD1U16V2KX-3GP

DY

C1309
SC10U6D3V5KX-1GP

FDI

C1308
SC10U6D3V5MX-3GP

J24
J23
H25

+1.5V_SUS

DYC1379

SCD1U10V2KX-4GP

Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9.pdf"
document.

SC1U10V2KX-1GP

+1.05V_VTT

GRAPHICS

C

VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG

POWER

1
2

1
2

2

1

1

DY

2

1

C1330
SCD1U16V2KX-3GP

2

1

C1323
SC10U6D3V5MX-3GP

DY

C1325
SC1U6D3V2KX-GP

2

1

C1328
SC10U6D3V5MX-3GP

DY

C1329
SC10U6D3V5MX-3GP

2

C1326
SC10U6D3V5MX-3GP

2

C1327
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SE330U2VDM-L-GP

DY

1

C1324

2

1

D

TC1303

7 OF 9

CPU1G

AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16

2

22A

+1.5V_CPU

DYC1378

SCD1U10V2KX-4GP

2

2

SCD1U10V2KX-4GP

2

DYC1376

+CPU_GFXCORE

+1.5V_CPU

1

1

SSID = CPU

+1.5V_CPU

1

+1.5V_CPU

2

3

2

4

2

5

1

1

C1317

2

2

DYSC10U6D3V5MX-3GP
B

+1.8V_RUN

1

C1321
SC2D2U6D3V3KX-GP

C1322
SC10U6D3V5MX-3GP

2

1

C1320
SC4D7U6D3V5KX-3GP

SC1U25V5KX-1GP

2

C1319

2

1

1

C1318

2

1

1.35A
SC1U25V5KX-1GP

CLARKUNF

C1316
SC10U6D3V5KX-1GP

2

VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1

1.8V

1
2

1

C1315
SC10U6D3V5KX-1GP

DY
2

1

C1314
SC10U6D3V5MX-3GP

2

C1313
SC10U6D3V5KX-1GP

2

C1312
SC10U6D3V5KX-1GP

B

K26
J27
J26
J25
H27
G28
G27
G26
F26
E26
E25

PEG & DMI

1

18A

1.1V

+1.05V_VTT
+1.05V_VTT

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

CPU (VCC_GFXCORE)

Document Number

Rev

Winery13 MB DIS
Date:

W ednesday, January 13, 2010

Sheet
1

13

of

A00
88

4

C

B

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

9 OF 9

CPU1I

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

K27
K9
K6
K3
J32
J30
J21
J19
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11
H8
H5
H2
G34
G31
G20
G9
G6
G3
F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11
E8
E5
E2
D33
D30
D26
D9
D6
D3
C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11
B8
B6
B4
A29
A27
A23
A9

CLARKUNF

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

1

CLARKSFIELD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CLARKSFIELD

D

8 OF 9

CPU1H

AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35

2

D

C

VSS

NCTF

SSID = CPU

3

NCYF TEST PIN:
A35,AT1,AT35,B1,A3,A33,A34,
AP1,AP35,AR1,AR35,AT2,AT3,
AT33,AT34,C1,C35,B35

5

VSS_NCTF
VSS_NCTF
VSS_NCTF

AR34
B34
B2

VSS_NCTF#A35
VSS_NCTF#AT1
VSS_NCTF#AT35
VSS_NCTF#B1
RSVD_NCTF#A3
RSVD_NCTF#A33
RSVD_NCTF#A34
RSVD_NCTF#AP1
RSVD_NCTF#AP35
RSVD_NCTF#AR1
RSVD_NCTF#AR35
RSVD_NCTF#AT2
RSVD_NCTF#AT3
RSVD_NCTF#AT33
RSVD_NCTF#AT34
RSVD_NCTF#C1
RSVD_NCTF#C35
RSVD_NCTF#B35

A35
AT1
AT35
B1
A3
A33
A34
AP1
AP35
AR1
AR35
AT2
AT3
AT33
AT34
C1
C35
B35

TP_MCP_VSS_NCTF2
TP_MCP_VSS_NCTF3
TP_MCP_VSS_NCTF4
TP_MCP_VSS_NCTF1

1
1
1
1

TP1402
TP1406
TP1405
TP1401

B

For layout request

CLARKUNF

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU (VSS)
Size

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Document Number

Rev

Winery13 MB DIS
Date:

W ednesday, January 13, 2010

Sheet
1

14

of

A00
88

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

Document Number

Reserved

Rev

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

15

of

A00
88

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

Document Number

Reserved

Rev

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

16

of

A00
88

5

4

3

2

1

D

D

C

C

(Blank)

B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

(Reserve)

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

17

of

88

5

4

3

2

1

DM1

C1875
SCD1U10V2KX-4GP
2
1

C1874
SCD1U10V2KX-4GP
2
1

C1873
SCD1U10V2KX-4GP
2
1

C1872
SCD1U10V2KX-4GP
2
1

+1.5V_SUS

Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9.
pdf" document.

[10] M_ODT0
[10] M_ODT1

116
120
126
1

DY

+0.75V_DDR_VTT

[9,19] DDR3_DRAMRST#

30
203
204

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

R1801
10KR2J-3-GP

SMBUS address:A0

198

PCH_SMBDATA [7,19,23,40,64,76]
PCH_SMBCLK [7,19,23,40,64,76]
PM_EXTTS#0 [9]

DW
07/02 Reserve
1.Added SA0_DM1 pull-up resistor
07/07
2.Reserve pull-hi,lo resistor

+3.3V_RUN

199
197
201
77
122
125

1

M_ODT0
M_ODT1

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

PCH_SMBDATA
PCH_SMBCLK

1

12
29
47
64
137
154
171
188

SA0
SA1
NC#1
NC#2
NC#/TEST

200
202

R1802
10KR2J-3-GP

2

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

VDDSPD

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

2

10
27
45
62
135
152
169
186

1

1

C1809
SC2D2U6D3V3KX-GP

2

2

C1817
SCD1U10V2KX-5GP

2

C1810
SCD1U10V2KX-5GP
A

1

+V_DDR_REF

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

EVENT#

11
28
46
63
136
153
170
187

SA0_DM1
SA1_DM1

SA0_DM1
SA1_DM1

C1806
SCD1U10V2KX-5GP

DY

C1807
SC2D2U6D3V3KX-GP

C

+1.5V_SUS

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206

put near connector
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
B

1

DG:
1uF*4 (per SO-DIMM)
10uF*3 (two close to VR and one between the two SO-DIMM)

SDA
SCL

M_CLK_DDR1 [10]
M_CLK_DDR#1 [10]

C1818
DUMMY-C2

DY

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

M_CLK_DDR0 [10]
M_CLK_DDR#0 [10]

M_CLK_DDR1
M_CLK_DDR#1

2

C1823
SC10U6D3V5MX-3GP
2
1

C1815
SC1U6D3V2KX-GP
2
1

C1814
SC1U6D3V2KX-GP
2
1

DY

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

M_CLK_DDR0
M_CLK_DDR#0

102
104

C1820
DUMMY-C2

B

C1813
SC1U6D3V2KX-GP
2
1

C1801
SC1U6D3V2KX-GP
2
1

DY

BA0
BA1

101
103

1

TC1803
ST330U2D5VBM-1-GP
2
1

C1816
SC10U6D3V5KX-1GP
2
1

C1811
SC10U6D3V5KX-1GP
2
1

C1804
SC10U6D3V5KX-1GP
2
1

C1803
SC10U6D3V5KX-1GP
2
1

C1802
SC10U6D3V5KX-1GP
2
1

C1812
SC10U6D3V5KX-1GP
2
1

Layout Note:
Put between two SO-DIMM

+0.75V_DDR_VTT

CK1
CK1#

Height 5.2mm

Layout Note:
Put close to VTT1,VTT2.

DY

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

CK0
CK0#

2

+1.5V_SUS
C

109
108

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

CKE0
CKE1

M_CKE0 [10]
M_CKE1 [10]

1

Layout Note:
Place near DM1

M_A_BS0
M_A_BS1

M_CS0# [10]
M_CS1# [10]

73
74

M_A_RAS# [10]
M_A_WE# [10]
M_A_CAS# [10]

2

[10] M_A_BS0
[10] M_A_BS1

CS0#
CS1#

114
121

1

[10] M_A_BS2

RAS#
WE#
CAS#

D

2

[10] M_A_A[15..0]

NP1
NP2
110
113
115

1

[10] M_A_DQS[7..0]

NP1
NP2

C1819
DUMMY-C2

[10] M_A_DM[7..0]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

2

[10] M_A_DQ[63..0]

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79

1

[10] M_A_DQS#[7..0]

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_BS2

C1821
DUMMY-C2

SSID = MEMORY

2

D

A

1st Samsung

Wistron Corporation

DDR3-204P-25-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

http://laptop-motherboard-schematic.blogspot.com/

DDRIII-SODIMM SLOT1

Size
Document Number
Custom
Date:

5

4

3

2

Sheet
1

Rev

A00

Winery13 MB DIS

Wednesday, January 13, 2010

18

of

88

3

2

B

C1979
SCD1U10V2KX-4GP
2
1

C1978
SCD1U10V2KX-4GP
2
1

C1977
SCD1U10V2KX-4GP
2
1

C1976
SCD1U10V2KX-4GP
2
1

+1.5V_SUS

Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9.
pdf" document.
[10] M_ODT2
[10] M_ODT3

+V_DDR_REF

C1914
SC2D2U6D3V3KX-GP

ODT0
ODT1
VREF_CA
VREF_DQ

1

1

C1910
SCD1U10V2KX-5GP

DY
2

2

C1907
SCD1U10V2KX-5GP

2

A

1

126
1

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

30

[9,18] DDR3_DRAMRST#

RESET#

+0.75V_DDR_VTT

203
204

VTT1
VTT2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

1

PCH_SMBDATA
PCH_SMBCLK

198

1

2

1

200
202

R1901
10KR2J-3-GP

EC1901
SCD1U25V3KX-GP

D

2

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

2

11
28
46
63
136
153
170
187

SA1_DM2
SA0_DM2

DY

1

116
120

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

M_CLK_DDR3 [10]
M_CLK_DDR#3 [10]

1

M_ODT2
M_ODT3

NC#1
NC#2
NC#/TEST

M_CLK_DDR3
M_CLK_DDR#3

R1902

DY 10KR2J-3-GP

2

12
29
47
64
137
154
171
188

SA0
SA1

M_CLK_DDR2 [10]
M_CLK_DDR#2 [10]

102
104

R1904
10KR2J-3-GP

SMBUS address:A4

PCH_SMBDATA [7,18,23,40,64,76]
PCH_SMBCLK [7,18,23,40,64,76]
+3.3V_RUN
PM_EXTTS#1 [9]

199
197
201
77
122
125

SA0_DM2
SA1_DM2

C1906
SCD1U10V2KX-5GP

DY

C1921
SC2D2U6D3V3KX-GP

+1.5V_SUS

Note:
If SA0_DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
If SA0_DIM0 = 1, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA2
If SA0_DIM0 = 0, SA1_DIM0 = 1
SO-DIMMA SPD Address is 0xA4

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206

C

put near connector
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR3
M_CLK_DDR#3

1

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

EVENT#
VDDSPD

101
103

M_CLK_DDR2
M_CLK_DDR#2

1

10
27
45
62
135
152
169
186

SDA
SCL

R1903
10KR2J-3-GP
DY

2

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

M_CKE2 [10]
M_CKE3 [10]

+3.3V_RUN

C1903
DUMMY-C2

DG:
1uF*4 (per SO-DIMM)
10uF*3 (two close to VR and one between the two SO-DIMM)

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

73
74

+3.3V_RUN

2

DY

BA0
BA1

M_CS2# [10]
M_CS3# [10]

1

DY

C1909
SC1U6D3V2KX-GP
2
1

C1918
SC1U6D3V2KX-GP
2
1

C1917
SC1U6D3V2KX-GP
2
1

Layout Note:
Put close to VTT1,VTT2.

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

114
121

C1902
DUMMY-C2

TC1903
ST330U2D5VBM-1-GP
2
1

C1920
SC10U6D3V5KX-1GP
2
1

C1919
SC10U6D3V5KX-1GP
2
1

DY

109
108

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

CK1
CK1#

Height 9.2mm

C1908
SC1U6D3V2KX-GP
2
1

+0.75V_DDR_VTT

C1916
SC10U6D3V5MX-3GP
2
1

C1911
SC10U6D3V5KX-1GP
2
1

C

C1905
SC10U6D3V5KX-1GP
2
1

+1.5V_SUS

C1913
SC10U6D3V5KX-1GP
2
1

Layout Note:
Place near DM2

M_B_BS0
M_B_BS1

CK0
CK0#

M_B_RAS# [10]
M_B_WE# [10]
M_B_CAS# [10]

2

[10] M_B_BS0
[10] M_B_BS1

CKE0
CKE1

110
113
115

1

[10] M_B_A[15..0]

CS0#
CS1#

Change CONN
2009/06/01

2

[10] M_B_BS2

RAS#
WE#
CAS#

NP1
NP2

1

[10] M_B_DQS[7..0]

NP1
NP2

C1904
DUMMY-C2

[10] M_B_DM[7..0]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

2

[10] M_B_DQ[63..0]

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79

1

[10] M_B_DQS#[7..0]
D

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_BS2

2

DM2

SSID = MEMORY

1

C1901
DUMMY-C2

4

2

5

B

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

DDR3-204P-24-GP
Title

DDRIII-SODIMM SLOT2

Size
Document Number
Custom

http://laptop-motherboard-schematic.blogspot.com/

Date:

5

4

3

2

Sheet
1

Rev

A00

Winery13 MB DIS

Wednesday, January 13, 2010

19

of

88

5

4

3

2

1

DW
LCDVDD_EN_PCH 1

D

R2011
0R0402-PAD-2-GP
U2001D
T48 L_BKLTEN
2PANEL_BKEN_PCHR
LCDVDD_EN_PCH
T47 L_VDD_EN

Y48

[54] LBKLT_CTL_PCH
[54] L_DDC_CLK
[54] L_DDC_DATA

TPAD14-GP

4
3

SRN10KJ-5-GP
TP2001
1

LCTLA_CLK
LCTLB_DATA

1

L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG

AT43
AT42

LVD_VREFH
LVD_VREFL

[74] MCH_LVDSA_CLK#
[74] MCH_LVDSA_CLK

AV53
AV51

LVDSA_CLK#
LVDSA_CLK

[74] MCH_LVDSA_DAT0#
[74] MCH_LVDSA_DAT1#
[74] MCH_LVDSA_DAT2#

BB47
BA52
AY48
AV47

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

[74] MCH_LVDSA_DAT0
[74] MCH_LVDSA_DAT1
[74] MCH_LVDSA_DAT2

BB48
BA50
AY49
AV48

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

AP48
AP47

LVDSB_CLK#
LVDSB_CLK

AY53
AT49
AU52
AT53

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

AY51
AT48
AU50
AT51

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

AA52
AB53
AD53

CRT_BLUE
CRT_GREEN
CRT_RED

R2002
2K37R2F-GP

2

L_DDC_CLK
L_DDC_DATA

AB46
V48

LIBG
AP39
TP_LVDS_VBG AP41

Place near PCH

4 OF 10

L_BKLTCTL

AB48
Y45
RN2001

1
2

+3.3V_RUN

2

C

37.5 ohm trace to 150R resistor
50 ohm trace to filter

2
1

Place near PCH

[74] GMCH_HSYNC
[74] GMCH_VSYNC

1

2

CRT_IREF

V51
V53

CRT_DDC_CLK
CRT_DDC_DATA

Y53
Y51

CRT_HSYNC
CRT_VSYNC

AD48
AB51

R2004
1KR2J-1-GP

DAC_IREF
CRT_IRTN

BJ46
BG46

SDVO_STALLN
SDVO_STALLP

BJ48
BG48

SDVO_INTN
SDVO_INTP

BF45
BH45

D

T51
T53

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

BG44
BJ44
AU38

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

DDPC_CTRLCLK
DDPC_CTRLDATA

Y49
AB49

DDPC_AUXN
DDPC_AUXP
DDPC_HPD

BE44
BD44
AV40

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

DDPD_CTRLCLK
DDPD_CTRLDATA

CRT

B

[55] GMCH_DDCCLK
[55] GMCH_DDCDATA

R2005
150R2F-1-GP

1

R2006
150R2F-1-GP

1

R2007
150R2F-1-GP

2

MCH_BLUE
MCH_GREEN
MCH_RED

2

[74] MCH_BLUE
[74] MCH_GREEN
[74] MCH_RED

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_CTRLCLK
SDVO_CTRLDATA

Digital Display Interface

1

[37] PANEL_BKEN_PCH
[54] LCDVDD_EN_PCH

DY

R2003
100KR2J-1-GP

A00-0104-1

LVDS

07/05
1. LCD brightness control are separated by GPU,PCH,EC
2. LCD Power Enable control are separated by GPU,PCH,EC
3. LCD Backlight On/Off Status are separated by GPU,PCH,EC
07/07
4. Dummy R2003

SSID = PCH

C

U50
U52

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

BC46
BD46
AT38

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

B

IBEXPEAK-M-GP-NF

SB-1023
change R2004 from 0.5% to 5%.

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PCH (LVDS/CRT/DDI)
Size

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Document Number

Rev

Winery13 MB DIS
Date:

W ednesday, January 13, 2010

Sheet
1

20

of

A00
88

5

4

3

07/02 Added
1. using the single buffers for 4 device with
equivalent capability.
2.Rename PCI_PLTRST#

+3.3V_RUN

DGPU_SELECT#
INT_PIRQD#
PCI_STOP#
INT_PIRQA#

+3.3V_RUN

C2101
SCD1U10V2KX-4GP

RN2102
D

+3.3V_RUN

1
2
3
4
5

10
9
8
7
6

U2101

+3.3V_RUN

INT_PIRQB#
PCI_PLOCK#
PCI_REQ1#
PCI_TRDY#

2

PCI_PERR#
PCI_REQ0#
PCI_REQ3#
PCI_FRAME#

1

SRN8K2J-2-GP-U

[9,34,36,37,64,70,76,80]

PLT_RST#

SRN8K2J-2-GP-U

5

VCC

4

Y

1

A

2

GND

3

DY

PLTRST#_PCH

74LVC1G08GW -1-GP

SB-1022
DY U2101; POP R2104

+3.3V_RUN

1
2
3
4

B

1
R2104

2
0R2J-2-GP

DGPU_PW M_SELECT#
EDID_SELECT_R#
PCH_GPIO4
INT_PIRQE#

8
7
6
5
RN2103
SRN10KJ-7GP

SB-1022
DY U2102; POP R2105

+3.3V_RUN

U2102
C

5
4

[54,55] EDID_SELECT#

B

1

A

2

GND

3

VCC
Y

DY

INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#

EDID_SELECT_R#

1

74LVC1G08GW -1-GP

2

DY

1
R2105

[37,54,74] DGPU_SELECT#

2
0R2J-2-GP

TPAD14-GP TP2116
TPAD14-GPTP2116

C2112
SC220P50V2KX-3GP

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

AY9
BD1
AP15
BD8

J50
G42
H47
G34

C/BE0#
C/BE1#
C/BE2#
C/BE3#

G38
H51
B37
A44

PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ0#
REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54

PCI_GNT0#

F48
K45
F36
H53

GNT0#
GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55

B41
K53
A36
A48

BOOT BIOS Strap
TPAD14-GP TP2108
TPAD14-GPTP2108

PCI_GNT#0 PCI_GNT#1

0

0

0

1

1

K6

BOOT BIOS Location
PCI_SERR#
PCI_PERR#

LPC

1

PCIRST#

Reserved

1

0

PCI

1

1

SPI(Default)

E44
E50

PCI_IRDY#

A42
H44
F46
C46

PCI_DEVSEL#
PCI_FRAME#

B

TPAD14-GP TP2115
TPAD14-GPTP2115

[70]
[23]
[37]
[36]

PCLK_FW H
CLK_PCI_FB
PCLK_KBC
PCLK_TPM

R2110 1
R2108 1
R2111 1
R2112 1

DY
DY

2
2
2
2

22R2J-2-GP
22R2J-2-GP
22R2J-2-GP
22R2J-2-GP

1

SERR#
PERR#

D49

PCI_STOP#
PCI_TRDY#

D41
C48

STOP#
TRDY#

PCH_PME#

M7

PME#

D5

PCLK_FW H_R
CLK_PCI_FB_R
PCLK_KBC_R
PCLK_TPM_R

N52
P53
P46
P51
P48

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

NV_ALE
NV_CLE

BD3
AY6

TP_NV_ALE
TP_NV_CLE

1
1

TP2124
TP2125

TPAD14-GP
TPAD14-GP

NV_RCOMP

AU2

TP_NV_RCOMP1

TP2130

TPAD14-GP

NV_RB#

AV7

NV_WR#0_RE#
NV_WR#1_RE#

AY8
AY5

IRDY#
PAR
DEVSEL#
FRAME#

PCI_PLOCK#

PLTRST#_PCH

NV_DQS0
NV_DQS1
NV_DQ0/NV_IO0
NV_DQ1/NV_IO1
NV_DQ2/NV_IO2
NV_DQ3/NV_IO3
NV_DQ4/NV_IO4
NV_DQ5/NV_IO5
NV_DQ6/NV_IO6
NV_DQ7/NV_IO7
NV_DQ8/NV_IO8
NV_DQ9/NV_IO9
NV_DQ10/NV_IO10
NV_DQ11/NV_IO11
NV_DQ12/NV_IO12
NV_DQ13/NV_IO13
NV_DQ14/NV_IO14
NV_DQ15/NV_IO15

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PCIRST#

SSID = PCH

AV9
BG8

NV_WE#_CK0
NV_WE#_CK1

F51
A46
B45
M53

DGPU_PW M_SELECT#
R2121
PCI_GNT3#
0R2J-2-GP
1
2 INT_PIRQE#
W W AN_RF_EN
PCH_GPIO4
EDID_SELECT_R#

[40] HDD_FALL_INT1
[76] W W AN_RF_EN

5 OF 10

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PCI_REQ0#
PCI_REQ1#
DGPU_SELECT#
PCI_REQ3#

1

[54] DGPU_PW M_SELECT#

U2001E

H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36

NVRAM

10
9
8
7
6

USB

+3.3V_RUN

1
2
3
4
5

PCI

PCI_DEVSEL#
PCI_IRDY#
PCI_SERR#
INT_PIRQC#

2

DW

RN2101

PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

NV_CLE

Set to Vss when low.
Set to Vcc when high.
Low = Default

unused NV_SLE strap

AV11
BF5

Port 0 for debug port

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

USBRBIAS#

B25

USBRBIAS

D25

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14

N16
J16
F16
L16
E14
G16
F12
T15

PLOCK#

D

DMI Termination Voltage

TP_USB_PN3
TP_USB_PP3

TP_USB_PN6
TP_USB_PP6
TP_USB_PN7
TP_USB_PP7

TP_USB_PN13
TP_USB_PP13

C

USB_PN0 [63]
USB_PP0 [63]
USB_PN1 [63]
USB_PP1 [63]
USB_PN2 [76]
USB_PP2 [76]
TP2122
TP2123
USB_PN4 [64]
USB_PP4 [64]
USB_PN5 [76]
USB_PP5 [76]
TP2118
TP2119
TP2120
TP2121
USB_PN8 [73]
USB_PP8 [73]
USB_PN9 [32]
USB_PP9 [32]
USB_PN10 [78]
USB_PP10 [78]
USB_PN11 [73]
USB_PP11 [73]
USB_PN12 [34]
USB_PP12 [34]
TP2128
TP2129

USB_RBIAS_PN

1

USB
Pair
1

USB for ESATA

2

USB2

3

RESERVE

4

WLAN

5

WWAN
RESERVED

(Not available for HM55)

RESERVED

7

R2106
22D6R2F-L1-GP
USB_OC#0_1
USB_OC#2_3
USB_OC#4_5
USB_OC#6_7
USB_OC#8_9
USB_OC#10_11
USB_OC#12_13
PCH_OC7#

USB1

6

2

Device

0

(Not available for HM55)

8

BlUETOOTH

9

Card Reader

10

Biometric

11

CAMERA

12

New Card

13

RESERVED

B

USB_OC#0_1 [22,63]
USB_OC#2_3 [76]

Pull up in page 22
for layout convenience
SB
swap net for layout

USB_OC#12_13 [23]

IBEXPEAK-M-GP-NF

Calpella Platform Design Guide
Revision 1.6

A16 swap override Strap/Top-Block
Swap Override jumper
PCI_GNT#3

Table 111.

Low = A16 swap
override/Top-Block
Swap Override enabled
High = Default

Pull up in page 23 for layout convenience

Overcurrent Pin Example Configuration

Page 233

These OC7# pins are not used for USB overcurrent protection and should be configured as GPIOs.
The unused USB ports can be left as no connect.
RP2101

A

PCH_OC7#
USB_OC#2_3
USB_OC#6_7
USB_OC#4_5

R2109
PCI_GNT3#

1

DY

2

+3.3V_ALW

4K7R2J-2-GP

1
2
3
4
5

10
9
8
7
6

1st Samsung
PM_RI#
USB_OC#8_9
PEG_B_CLKRQ#
USB_OC#10_11

A

+3.3V_ALW
PM_RI# [22]

Wistron Corporation

PEG_B_CLKRQ# [23]

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

SRN10KJ-L3-GP
Title

SB
swap net for layout

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

PCH (PCI/USB/NVRAM)
Size

Document Number

Rev

Winery13 MB DIS
Date:

W ednesday, January 13, 2010

Sheet
1

21

of

A00
88

4

3

SSID = PCH

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

[8]
[8]
[8]
[8]

DMI_CTX_PRXP0
DMI_CTX_PRXP1
DMI_CTX_PRXP2
DMI_CTX_PRXP3

BD24
BG22
BA20
BG20

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

[8]
[8]
[8]
[8]

DMI_PTX_CRXN0
DMI_PTX_CRXN1
DMI_PTX_CRXN2
DMI_PTX_CRXN3

BE22
BF21
BD20
BE18

[8]
[8]
[8]
[8]

DMI_PTX_CRXP0
DMI_PTX_CRXP1
DMI_PTX_CRXP2
DMI_PTX_CRXP3

BD22
BH21
BC20
BD18

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

+1.05V_VTT

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

R2204

1

2

DMI_IRCOMP_R
+3.3V_RUN

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7

FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7

[8]
[8]
[8]
[8]
[8]
[8]
[8]
[8]

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7

FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7

[8]
[8]
[8]
[8]
[8]
[8]
[8]
[8]

FDI_INT

BJ14

FDI_INT

FDI_INT

FDI_FSYNC0

BF13

FDI_FSYNC0

FDI_FSYNC0

FDI_FSYNC1

BH13

FDI_FSYNC1

FDI_FSYNC1

[8]

FDI_LSYNC0

BJ12

FDI_LSYNC0

FDI_LSYNC0

[8]

FDI_LSYNC1

BG14

FDI_LSYNC1

FDI_LSYNC1

[8]

+3.3V_ALW
RN2201
USB_OC#0_1
SUS_PW R_ACK

[21,63] USB_OC#0_1

3
4

2
1
SRN10KJ-5-GP
D

PM_BATLOW #_R

1

2

1

2

1

2

R2201
PCIE_W AKE#

10KR2J-3-GP

R2202
AC_PRESENT_EC

1KR2J-1-GP

R2217

10KR2J-3-GP

Option to " Disable " clkrun.
Pulling it down will keep the clks running.

[8]

+3.3V_RUN
[8]

R2214
10KR2J-3-GP

1

1

49D9R2F-GP

FDI

BC24
BJ22
AW20
BJ20

DMI

D

DMI_CTX_PRXN0
DMI_CTX_PRXN1
DMI_CTX_PRXN2
DMI_CTX_PRXN3

1

3 OF 10

U2001C
[8]
[8]
[8]
[8]

2

2

5

PM_CLKRUN#

2
[9] XDP_DBRESET#

XDP_DBRESET#

1

R2205
10KR2J-3-GP

Remove XDP
pull-up ?

T6

SYS_RESET#

WAKE#

J12

M6

SYS_PWROK

CLKRUN#/GPIO32

Y1

PM_CLKRUN#

SUS_STAT#/GPIO61

P8

TP_SUS_STAT# 1

SUSCLK/GPIO62

F3

PCH_SUSCLK

SLP_S5#/GPIO63

E4

PCH_SLP_S5#

SLP_S4#

H7

PM_SLP_S4#_R

1
R2211

SLP_S3#

P12

PM_SLP_S3#_R

1
R2212

SLP_M#

K8

SIO_SLP_M#_R

1

N2

PM_SLP_DSW #

1

BJ10

H_PM_SYNC

R2215
10KR2J-3-GP

PCIE_W AKE# [34,76]

A00-0104-1
[37] PM_PW ROK

R2207 1

2 0R0402-PAD-2-GP

R2208 1

2 10KR2J-3-GP

PM_PW RGD

B17
K5

R2209 1

2 10KR2J-3-GP

LAN_RST#1
PM_DRAM_PW RGD

[9] PM_DRAM_PW RGD
[37] RSMRST#_KBC
[37] SUS_PW R_DN_ACK

LAN_RST#
DRAMPWROK

2
0R2J-2-GP

1
R2218

SUS_PW R_ACK
2
0R0402-PAD-2-GP

M1

SUS_PWR_DN_ACK/GPIO30

1
R2213

PM_PW RBTN#_R
2
0R0402-PAD-2-GP

P5

PWRBTN#

AC_PRESENT_EC 1
R2216

[37] AC_PRESENT_EC

D9
C16

MEPWROK

1
R2210

A00-0104-1
[37] PM_PW RBTN#

PM_RSMRST#_R

A10

PWROK

System Power Management

AC_PRESENT
2
0R0402-PAD-2-GP
PM_BATLOW #_R

B

PM_RI#

[21] PM_RI#

RSMRST#

P7

ACPRESENT/GPIO31

A6

BATLOW#/GPIO72

F14

RI#

DY
C

2

C

PM_CLKRUN# [37]

Close to PCH

TP2205TPAD14-GP

1
R2219

2
0R0402-PAD-2-GP

PCH_SUSCLK_2102 [39]

A00-0104-1
1

1
R2220

TP2202TPAD14-GP

2
0R0402-PAD-2-GP

2
0R0402-PAD-2-GP

PCH_SUSCLK_KBC

[37]

PM_SLP_S4# [34,37,50]

A00-0104-1
2
0R0402-PAD-2-GP

PM_SLP_S3# [34,37,42,50,51,86]

TP2203TPAD14-GP

TP23

TP2204TPAD14-GP

PMSYNCH

H_PM_SYNC

[9]

B

F6

SLP_LAN#/GPIO29

IBEXPEAK-M-GP-NF

Pull up in page 23 for layout convenience

2

KBC_PW R

R2221

SB-31

1

DY10KR2J-3-GP
U2213_56

U2213

4

3

5

2

DY

6

PM_RSMRST#_R
3V_5V_POK [37,46]

1
DMN66D0LDW -7-GP
1st Samsung

A

A

Wistron Corporation

R2203
PM_RSMRST#_R

1

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

2

10KR2J-3-GP
Title

PCH (DM I/FDI/PM)
Size

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Document Number

Rev

Winery13 MB DIS
Date:

W ednesday, January 13, 2010

Sheet
1

22

of

A00
88

5

4

3

2

1

+3.3V_ALW
RN2301
SML0ALERT#
SML1ALERT#

1
2

SSID = PCH
U2001B

C2303
C2309

2
2

1 SCD1U10V2KX-5GP
1 SCD1U10V2KX-5GP

AU30
AT30
PCIE_ITXN3_LRXN3_C AU32
PCIE_ITXP3_LRXP3_C AV32

PERN3
PERP3
PETN3
PETP3

C2302
C2311

2
2

1 SCD1U10V2KX-5GP
1 SCD1U10V2KX-5GP

BA32
BB32
PCIE_ITXN4_MRXN4_C BD32
PCIE_ITXP4_MRXP4_C BE32

PERN4
PERP4
PETN4
PETP4

WWAN

1 SCD1U10V2KX-5GP
1 SCD1U10V2KX-5GP

BF33
BH33
PCIE_ITXN5_NRXN5_C BG32
PCIE_ITXP5_NRXP5_C BJ32

PERN5
PERP5
PETN5
PETP5

New
Card

1
2

4
3

CLK_PCIE_MINI1_1#
CLK_PCIE_MINI1_1

RN2304
0R4P2R-PAD

[76] CLK_PCIE_LAN#
[76] CLK_PCIE_LAN

AM47
AM48

MINI1_CLKREQ#

RN

[64] MINI1_CLKREQ#
1
2

4
3

N4

CLK_PCIE_LAN1#
CLK_PCIE_LAN1

AH42
AH41

CLKREQ#_LAN

[76] CLKREQ#_LAN
RN2309
0R4P2R-PAD

[76] CLK_PCIE_MINI2#
[76] CLK_PCIE_MINI2

PERN8
PERP8
PETN8
PETP8

NEW CARD_CLKREQ# U4

2
1

3
4

A8

CLK_PCIE_MINI2_1#
CLK_PCIE_MINI2_1

B

AM51
AM53

MINI2_CLKREQ#
RN

M9
AJ50
AJ52

PCIECLKRQ5#

H6
AK53
AK51

PEG_B_CLKRQ#

[21] PEG_B_CLKRQ#

P13

2
1

SML1ALERT#

E10

KBC_SCL1

SML1DATA/GPIO75

G12

KBC_SDA1

1
2

M14

SML1CLK/GPIO58

SMBus

PCIECLKRQ0#/GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCIECLKRQ1#/GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P

T13

CL_CLK

1

T11

CL_DATA

1

CL_RST1#

T9

PEG_A_CLKRQ#/GPIO47

H1

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ#/GPIO56

TPAD14-GP

TP2302

TPAD14-GP

TP2303

TPAD14-GP

RN2303
2
1

R2304
10KR2J-3-GP

PEG_CLKREQ#

CLKOUT_DMI_N
CLKOUT_DMI_P

AN4
AN2

CLK_EXP_N
CLK_EXP_P

CLKOUT_DP_N/CLKOUT_BCLK1_N
CLKOUT_DP_P/CLKOUT_BCLK1_P

AT1
AT3

3
4
SRN2K2J-1-GP

PCH_SMB_DATA

RN2327
0R4P2R-PAD

A00-0104-1
1
2

4
3

CLK_PCIE_VGA# [80]
CLK_PCIE_VGA [80]

6

1

5

2

4

CLK_EXP_N [9]
CLK_EXP_P [9]

PCH_SMBDATA [7,18,19,40,64,76]

1ST: 84.DMN66.03F
2ND: 84.27002.F3F

3
Q2301
DMN66D0LDW -7-GP

C

PCH_SMBCLK [7,18,19,40,64,76]

PCH_SMB_CLK

AW24
BA24

CLKIN_DMI#
CLKIN_DMI

CLKIN_DMI# [7]
CLKIN_DMI [7]

CLKIN_BCLK_N
CLKIN_BCLK_P

AP3
AP1

CLK_CPU_BCLK#
CLK_CPU_BCLK

CLK_CPU_BCLK# [7]
CLK_CPU_BCLK [7]

CLKIN_DOT_96N
CLKIN_DOT_96P

F18
E18

DREFCLK#
DREFCLK

DREFCLK# [7]
DREFCLK [7]

AH13
AH12

CLK_PCIE_SATA#
CLK_PCIE_SATA

CLK_PCIE_SATA# [7]
CLK_PCIE_SATA [7]

REFCLK14IN

P41

CLK_PCH_14M

CLK_PCH_14M [7]

CLKIN_PCILOOPBACK

J42

CLK_PCI_FB

CLK_PCI_FB

XTAL25_IN
XTAL25_OUT

AH51
AH53

XTAL25_IN
XTAL25_OUT

XCLK_RCOMP

AF38

XCLK_RCOMP

CLKIN_DMI_N
CLKIN_DMI_P

PCIECLKRQ4#/GPIO26

PCIECLKRQ5#/GPIO44

+3.3V_RUN

+3.3V_ALW
TP2301

1

CLK_PCIE_VGA1#
CLK_PCIE_VGA1

CLKOUT_PCIE4N
CLKOUT_PCIE4P

CLKOUT_PCIE5N
CLKOUT_PCIE5P

CL_RST#

AD43
AD45

CLKOUT_PCIE3N
CLKOUT_PCIE3P
PCIECLKRQ3#/GPIO25

4
3

CL_CLK1

CLKIN_SATA_N/CKSSCD_N
CLKIN_SATA_P/CKSSCD_P

PCIECLKRQ2#/GPIO20

SB-1020

KBC_SDA1 [37]

CL_DATA1

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_PCIE0N
CLKOUT_PCIE0P

KBC_SCL1 [37]

PEG_CLKREQ#

Q2305
2N7002A-7-GP

G

[25,51] DGPU_1D8V_PGOOD

1ST: 84.2N702.E31
2ND: 84.2N702.D31

un-stuff 25M X'tal without HDMI/eDP/DP
SC-1125-1
C2313 pop 0 ohm if no use 25MHz XTAL

[21]

+1.05V_VTT
C2313
XTAL25_IN
1
R2306

2
90D9R2F-1-GP

DY

CLKOUTFLEX0/GPIO64

T45

TP_CLK_OUTFLEX0

1

TP2307
TPAD14-GP

CLKOUTFLEX1/GPIO65

P43

TP_CLK_PCI_LPC

1

TP2305
TPAD14-GP

XTAL25_OUT

CLKOUTFLEX2/GPIO66

T42

TP_CLK_PCH_REF14

1

TP2306
TPAD14-GP

SB-1104
pop for 25MHz

CLKOUTFLEX3/GPIO67

N50

CLK48M/EDID_SEL

1
R2307

2
0R0402-PAD-2-GP

DY

XTAL-25MHZ-67GP

RN2305
0R4P2R-PAD

[64] CLK_PCIE_MINI1#
[64] CLK_PCIE_MINI1

BG34
BJ34
BG36
BJ36

AM43
AM45

SML1ALERT#/GPIO74

PCH_SMB_DATA

D

CLK_PCIE_NEW 1#
CLK_PCIE_NEW 1

RN

[34] NEW CARD_CLKREQ#

PERN7
PERP7
PETN7
PETP7

LAN

Remove XDP
pull-up

S

4
3

SML0_DATA

D

PCH_SMB_CLK

1

1
2

SML0_CLK

G8

PCH_SMB_DATA [34]

X2301

RN2311
0R4P2R-PAD

[34] CLK_PCIE_NEW #
[34] CLK_PCIE_NEW

AT34
AU34
AU36
AV36

P9

RN

A00-0104-1

PERN6
PERP6
PETN6
PETP6

AK48
AK47

C6

SML0ALERT#/GPIO60

2

PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW.
PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN

BA34
AW34
BC34
BD34

WLAN

RN

C

SML0CLK
SML0DATA

RN2302
SRN2K2J-1-GP

RN2313
SRN2K2J-1-GP

PCH_SMB_CLK [34]

R2380
1MR2J-1-GP
2
1

2
2

SML0ALERT#

+3.3V_ALW

1

C2308
C2304

J14

1
10KR2J-3-GP

3
4

PERN2
PERP2
PETN2
PETP2

2
R2301

2

PCIE_IRXN5_NTXN5
PCIE_IRXP5_NTXP5
PCIE_ITXN5_NRXN5
PCIE_ITXP5_NRXP5

PCH_SMB_DATA

Link

[34]
[34]
[34]
[34]

AW30
BA30
PCIE_ITXN2_MRXN2_C BC30
PCIE_ITXP2_MRXP2_C BD30

Controller

PCIE_IRXN4_MTXN4
PCIE_IRXP4_MTXP4
PCIE_ITXN4_MRXN4
PCIE_ITXP4_MRXP4

C8

PEG

[76]
[76]
[76]
[76]

PCH_SMB_CLK

SMBDATA

1 SCD1U10V2KX-5GP
1 SCD1U10V2KX-5GP

PCI-E*

[76] PCIE_IRXN3_LRTXN3
[76] PCIE_IRXP3_LRTXP3
[76] PCIE_ITXN3_LRXN3
[76] PCIE_ITXP3_LRXP3

SMBALERT#

H14

SMBCLK

2
2

C2318
C2310

B9

SMBALERT#/GPIO11

From CLK BUFFER

PCIE_IRXN2_MTXN2
PCIE_IRXP2_MTXP2
PCIE_ITXN2_MRXN2
PCIE_ITXP2_MRXP2

+3.3V_ALW

2 OF 10

PERN1
PERP1
PETN1
PETP1

Clock Flex

[64]
[64]
[64]
[64]

SB-1020
+3.3V_ALW

SRN10KJ-5-GP

BG30
BJ30
BF29
BH29
D

4
3

2

1

B

0R2J-2-GP

2

DY1

C2307
SC18P50V2JN-1-GP

CLK_PCH_48M [32]

A00-0104-1

IBEXPEAK-M-GP-NF

Pull up in page 21 for layout convenience
SB-1020
move EDID_SELECT# from GPIO66 to GPIO5

+3.3V_RUN
1

+3.3V_ALW

1ST: 84.03904.H11
2ND: 84.03904.L06

A

[76] MINI2_CLKREQ_R#

2

1

2

R2333
10KR2J-3-GP

SB
swap net for layout

RN2307
8
7
6
5

Q2306_1
Q2306
MMBT3904-7-F-GP
MINI2_CLKREQ#
3

1
2
3
4

DY

2 0R2J-2-GP

8
7
6
5
SRN10KJ-6-GP

5

USB_OC#12_13 [21]

SRN10KJ-7GP
+3.3V_RUN

A

1st Samsung

SB-1026
swap net for layout

RN2308
R2309 1

PCIECLKRQ5#
USB_OC#12_13
CLKREQ#_LAN
MINI2_CLKREQ#

1
2
3
4

NEW CARD_CLKREQ#
KB_DET_R#
GPO_DSM
MINI1_CLKREQ#

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

KB_DET_R# [25]
GPO_DSM [24,76]
Title

SB-1023
RN2308 change to 2*1 size

PCH (PCI-E/SMBUS/CLOCK/CL)
Size

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Document Number

Rev

Winery13 MB DIS
Date:

W ednesday, January 13, 2010

Sheet
1

23

of

A00
88

5

4

3

2

1

PCH_RTCX1
PCH_RTCX2

1
2
R2401
10MR2J-L-GP

+RTC_CELL
R2402
20KR2J-L2-GP
1
2

SSID = PCH

X2401
1

C2403
SC12P50V2JN-3GP

+RTC_CELL

[30] PCH_AZ_CODEC_BITCLK

Flash Descriptor Security
Override/ ME Debug Mode

[30] PCH_AZ_CODEC_SYNC

RTCRST#

D17

SRTCRST#

2

This strap should only be asserted low via
external pull down in manufacturing/debug
environments ONLY.

[30] PCH_AZ_CODEC_RST#

DY

2
1KR2J-1-GP

ACZ_BIT_CLK

A30

HDA_BCLK

2 33R2J-2-GP

ACZ_SYNC_R

D29

HDA_SYNC

R2408 1

2 33R2J-2-GP

ACZ_RST#_R

P1

ME_UNLOCK_R#
R2409 1

2 33R2J-2-GP ACZ_SDATAOUT_R

R2417 1
2
0R0402-PAD-2-GP

[37] ME_UNLOCK#

ME_UNLOCK_R#

A00-0104-1

+3.3V_RUN

NO REBOOT STRAP
No Reboot Strap R23

1
R2410

DY

2 SB_SPKR
1KR2J-1-GP

Low = Default
HDA_SPKR High = No Reboot

B

C34

LDRQ0#
LDRQ1#/GPIO23

A34
F34

SERIRQ

AB9

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AK7
AK6
AK11
AK9

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AH6
AH5
AH9
AH8

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AF11
AF9
AF7
AF6

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

AH3
AH1
AF3
AF1

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

AD9
AD8
AD6
AD5

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

AD3
AD1
AB3
AB1

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN#/GPIO33

J30

HDA_DOCK_RST#/GPIO13

1

PCH_JTAG_TCK

M3

JTAG_TCK

TP2405

1

PCH_JTAG_TMS

K3

JTAG_TMS

TP2406

1

PCH_JTAG_TDI

K1

JTAG_TDI

TP2407

1

PCH_JTAG_TDO

J2

JTAG_TDO

TP2408

1

PCH_JTAG_RST#

J4

TRST#

LPC_LFRAME# [36,37,70]

INT_SERIRQ [25,36,37]

SATA_ITXN0_HRXN0_C C2405 1
SATA_ITXP0_HRXP0_C C2406 1

2 SCD01U25V2KX-3GP
2 SCD01U25V2KX-3GP

SATA_IRXN0_HTXN0_C [59]
SATA_IRXP0_HTXP0_C [59]
SATA_ITXN0_HRXN0 [59]
SATA_ITXP0_HRXP0 [59]

2 SCD01U25V2KX-3GP
2 SCD01U25V2KX-3GP

SATA_IRXN1_OTXN1_C [59]
SATA_IRXP1_OTXP1_C [59]
SATA_ITXN1_ORXN1 [59]
SATA_ITXP1_ORXP1 [59]

ODD

SATAICOMPO

AF16

SATAICOMPI

AF15

SATA_ITXN1_ORXN1_C C2407 1
SATA_ITXP1_ORXP1_C C2408 1

C

ESATA
ESATA_IRX_DTX_N4_C [63]
ESATA_IRX_DTX_P4_C [63]
ESATA_ITX_DRX_N4 [63]
ESATA_ITX_DRX_P4 [63]

+1.05V_VTT
SATAICOMP

1
R2412

2
37D4R2F-GP

[62] PCH_SPI_CLK

R2413

1

2 0R2J-2-GP SPI_CLK_R

BA2

SPI_CLK

[62] PCH_SPI_CS0#

R2414

1

2 0R2J-2-GP SPI_CS#0_R

AV3

SPI_CS0#

AY3

SPI_CS1#

SATALED#

T3

AY1

SPI_MOSI

SATA0GP/GPIO21

Y9

GPO_DSM

GPO_DSM [23,76]

AV1

SPI_MISO

SATA1GP/GPIO19

V1

PCH_GPIO19

PCH_GPIO19 [25]

[62] PCH_SPI_DO

R2415

1

2 0R2J-2-GP SPI_MOSI_R

[62] PCH_SPI_DI

07/02 Change
1.Change R2410 to dummy

C30

FWH4/LFRAME#

SC-1208-1
change R2413,R2414,R2415 from 15ohm to 0 ohm

D

LPC_LAD[0..3] [36,37,70]

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

D33
B33
C32
A32

HDD

SPKR

TP2404

SB-1026
1. remove R2411 pull high INT_SERIRQ to RN2501.1

DW

INTVRMEN

2 33R2J-2-GP

[30] PCH_SDIN_CODEC

[30] PCH_SDOUT_CODEC

A14

R2407 1

C

1
R2419

INTRUDER#

R2405 1

[30] SB_SPKR

ME_UNLOCK#

A16

LPC

C14

SRTCRST#
SM_INTRUDER#
1MR2J-1-GP
PCH_INTVRMEN
2
330KR2F-L-GP

1
R2406
1
R2404

2

07/23 Added
1.Added "ME in Manufacturing Mode" strap
2.Added CardReader_Wake# to sent Card detect signal for PCH . ( Only For JMB380 )

PCH_RTCRST#

RTC

G2401
GAP-OPEN
1

DW

C2404
SC1U6D3V3KX-2GP

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

IHDA

1st: EPSON 82.30001.861
2nd: QUARTECH 82.30001.A81
3rd: KDS 82.30001.691

1

2

R2403
20KR2J-L2-GP
1
2

RTCX1
RTCX2

SATA

+RTC_CELL

SB-18

B13
D13

LPC_LAD[0..3]

1 OF 10

U2001A
PCH_RTCX1
PCH_RTCX2

JTAG

X-32D768KHZ-46GP

B

SPI

3
2

C2402
SC12P50V2JN-3GP

2

D

2

2

C2401
SC1U6D3V3KX-2GP
1

4

1

1

INTVRMEN- Integrated SUS
1.1V VRM Enable
High - Enable internal VRs

SATA_LED# [66]

IBEXPEAK-M-GP-NF

DW
07/10 assign GPIO
1.assign GPIO GPIO_DSM,Felic_DETECT#

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PCH (SPI/RTC/LPC/SATA/IHDA)
Size

Document Number

Rev

Winery13 MB DIS
5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Date: W ednesday, January 13, 2010

Sheet
1

24

of

A00
88

5

4

3

2

1

1
R2555
2K2R2J-2-GP

R2552
10KR2J-3-GP

SSID = PCH

R2503
10KR2J-3-GP

D37

TACH2/GPIO6

ECSW I#

J32

TACH3/GPIO7

ECSMI#

F10

GPIO8

A00-0104-1

[54] LCD_CBL_DET#

DGPU_HOLD_RST#

[80] DGPU_HOLD_RST#
2
2 0R0402-PAD-2-GP
0R0402-PAD-2-GP
2
100R2J-2-GP

1
R2505
1
R2506
1
R3749

[86] GFX_CORE_PGOOD
[23,51] DGPU_1D8V_PGOOD

DGPU_PW ROK
LCD_CBL_DET_R#

DW

TPAD14-GP

TP2508

1

R2507
10KR2J-3-GP
2DGPU_PW ROK

2
R2525
10KR2J-3-GP
[68] KB_DET#

R2548
1

[9] DDR_RST_GATE#

STP_PCI#/GPIO34

PCH_GPIO15

1
R2532

2
1KR2J-1-GP

PCIECLKRQ6#

1
R2521

2
10KR2J-3-GP
TPAD14-GP

SBswap net for layout

TP2512

1

SRN10KJ-5-GP

TPAD14-GP
TPAD14-GP

TP2510
TP2509

1
1

BD10

AW22

V3

SLOAD/GPIO38

TP3

BB22

P3

SDATAOUT0/GPIO39

TP4

AY45

PCIECLKRQ6#

H3

PCIECLKRQ6#/GPIO45

TP5

AY46

DDR_RST_GATE#

F1

PCIECLKRQ7#/GPIO46

TP6

AV43

SDATAOUT1/GPIO48

TP7

AV45

SATA5GP/GPIO49

TP8

AF13

GPIO57

TP9

M18

TP10

N18

TP11

AJ24

TP12

AK41

TP13

AK42

TP14

M32

TP15

N32

TP16

M30

TP17

N30

TP18

H12

PCH_NCTF_2

PCH_NCTF_3

PCH_NCTF_1
PCH_NCTF_4

A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53

SB-1023

KBRCIN#

[37]

H_PW RGOOD [9,42]
PCH_THERMTRIP_R

1
R2511
56R2J-4-GP

2

H_THRMTRIP# [9,37,42]

PCH

SATACLKREQ#/GPIO35
BA22

F8

R2509
56R2J-4-GP

H_PECI [9]

Placed Within 2" from

TP2

4
3
+3.3V_RUN

BE10

THRMTRIP#

TP1

+3.3V_ALW

1
2

PROCPWRGD

SATA3GP/GPIO37

AB6

+1.05V_VTT

T1

SATA2GP/GPIO36

RN2504
ECSMI#
PCH_GPIO57

BG10

AB7

2
10KR2J-3-GP

1

PECI
RCIN#

AB13

+3.3V_ALW

TP2511

SCLOCK/GPIO22

M11

For layout request

TPAD14-GP

Y7

STP_PCI#

07/10 Added
1.Changed PCH GPIO DDR_RST_GATE from GPIO57 to GPIO46 , Bason on design guide
07/23 Added
1.Added Finger Printer Detect Pin, control by PCH
2.Change KB_DET signal from EC to PCH control
3.Change LCD_CBL_DET signal from EC to PCH control

B

BCLK_CPU_P [9]

GPIO28

PCH_GPIO57

1
R2530

BCLK_CPU_N [9]

AM1

TURBO_BOOST_ALERT# AA4

[37] TURBO_BOOST_ALERT#

PCH_GPIO28

AM3

CLKOUT_BCLK0_P/CLKOUT_PCIE8P

GPIO27

FFS_INT2_R

[40] FFS_INT2_R

KA20GATE [37]

CLKOUT_BCLK0_N/CLKOUT_PCIE8N

V13

2100R2J-2-GP KB_DET_R#

[23] KB_DET_R#

U2

TACH0/GPIO17

AB12

PCH_GPIO38

1

DY

A20GATE

D

SATA4GP/GPIO16

PCH_GPIO28

DGPU_PW R_EN#

AF48
AF47

F38

V6

[37] DGPU_PW R_EN#

CLKOUT_PCIE7N
CLKOUT_PCIE7P

AA2

PCH_GPIO27

DGPU_PRSNT#
R2526
10KR2J-3-GP
1
2 PCH_GPIO27

GPIO15

GPIO24

PCH_GPIO35

C

LAN_PHY_PWR_CTRL/GPIO12

T7

H10

+3.3V_RUN

07/02 Change
1.Change CLK_SATA_OE# to pull-down

K9

AH45
AH46

1

PCH_GPIO15

MISC

BIO_DET#

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CPU

1

[37] ECSMI#

TACH1/GPIO1

DY
2

C2501
SC47P50V2JN-3GP

BMBUSY#/GPIO0

C38

GPIO

[78] BIO_DET#

SB-32
[37] ECSW I#

Y3

ECSCI#

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31

NCTF

[81] DEEPIDLE_W AKE_INT_R#

[37] ECSCI#

RSVD

2

1 2

1

DEEP_IDLE#

Q2515
3
2
MMBT3904-7-F-GP

D

1

6 OF 10

U2001F
Q2515_1

2

2

1

+3.3V_RUN_GPU +3.3V_RUN_GPU +3.3V_RUN

TP19

AA23

NC_1

AB45

NC_2

AB38

NC_3

AB42

NC_4

AB41

NC_5

T39

INIT3_3V#
TP24

P6

C

B

INIT3_3V#

1

TP2506TPAD14-GP

C10

IBEXPEAK-M-GP-NF

DY

R2517 1

+3.3V_RUN

2 10KR2J-3-GP
+3.3V_RUN

2 10KR2J-3-GP

SRN10KJ-5-GP
ECSW I#
ECSCI#

A

2
1

+3.3V_RUN

+3.3V_RUN

SRN10KJ-5-GP
PCH_GPIO19
PCH_GPIO38

2
1

DGPU_PRSNT#

3
4
RN2503

A

Wistron Corporation

INT_SERIRQ

[78] BIO_DET#

INT_SERIRQ
FFS_INT2_R
DGPU_PW R_EN#
BIO_DET#

1
2
3
4

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

R2528
10KR2J-3-GP

RN2501

SB-1026
[24,36,37]
swap net for layout

8
7
6
5

Title

PCH (GPIO/CPU)
Size

SB-1023
RN2501 change to 2*1 size

http://laptop-motherboard-schematic.blogspot.com/
SRN10KJ-6-GP

5

1st Samsung

1

[24] PCH_GPIO19

DYR2527
10KR2J-3-GP

3
4
RN2502

2

STP_PCI#

1

DGPU_HOLD_RST# R2516 1

1 10KR2J-3-GP

2

LCD_CBL_DET_R# R2520 2

4

3

2

Document Number

Rev

Winery13 MB DIS
Date:

W ednesday, January 13, 2010

Sheet
1

25

of

A00
88

5

4

3

2

1

SSID = PCH

357mA

TP2601

BJ18

VCCFDIPLL

AM23

1

1
2

2

5

C2607
SCD1U10V2KX-5GP

C2628
SC10U6D3V5MX-3GP

DY

VCCIO

IN

1

GND

2

SHDN#

3

OUT

DY
4

NC#4

C2629
SC1U10V3KX-3GP

DY
C

MAX8511EXK33-T-GP

+VCC_VRM

VCCVRM

AT24

VCCDMI

AT16

VCCDMI

AU16

VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

35mA

+1.05VS_VCC_DMI

+1.05V_VTT

1 R2601 2
0R0402-PAD-2-GP
C2613
SC1U10V3KX-3GP

58mA

A00-0104-1
+3.3V_RUN

156mA

FDI

+1.05V_VTT

+3.3V_RUN

1

VCCVRM[1]

1

VCC3_3

AT22

+5V_RUN
U2601

2

AN35

+3.3V_CRT_LDO

357mA

1

VCCIO
VCCIO

L2604
IND-D1UH-21-GP

2

AN30
AN31

3.062A

C2626
SC10U6D3V5MX-3GP

59mA

2

AD35

+1.8V_RUN

2

1

AB35

VCC3_3

HVCMOS

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

DY

C2624

1

2

VCC3_3

357mA

AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27

1

AB34

A00-0104-1

2

VCC3_3

<1mA

1

VCCAPLLEXP

+3.3V_RUN
R2609
2
1
0R0603-PAD-2-GP

DY2

C2625

+3.3V_RUN

A00-0104-1
D

SCD1U10V2KX-5GP
+1.8VS_VCCTX_LVDS

1

VCCTX_LVDS

59mA VCCTX_LVDS

1
2
BLM18PG181SN1D-GP
C2603
SC10U6D3V5MX-3GP

C2623
1

156mA
1

BJ24

R2606

2
1 +VCC_VRM
0R0402-PAD-2-GP
VCCFDIPLL
1
TPAD14-GP

AH39

C2615
SCD1U10V2KX-5GP

B

VCCME3_3
VCCME3_3
VCCME3_3
VCCME3_3

85mA

85mA

AM8
AM9
AP11
AP9

PCH_VCCME3_3

1

A00-0104-1
B

VSSA_LVDS

2

LVDS

VCCIO

NAND / SPI

+1.8V_RUN

AH38

VCCTX_LVDS
VCCTX_LVDS

AK24

2

C2614
SCD1U10V2KX-4GP

1

+3.3V_RUN

VCCALVDS

C2605

1 R2602 2
0R0402-PAD-2-GP

2

1
2

1

C2612
SC1U10V3KX-3GP

2

1

C2611
SC1U10V3KX-3GP

2

C2610
SC1U10V3KX-3GP

2

1

C2609
SC1U10V3KX-3GP

SC10U6D3V5KX-1GP

2

C2608

1

3.062A

AF51

AP43
AP45
AT46
AT45

DMI

+1.05V_VTT
C

AF53

VSSA_DAC

+3VS_VCCA_LVD

<1mA

PCI E*

SB-21

VSSA_DAC

C2604

SCD01U16V2KX-3GP

VCCAPLLEXP

AE52

SCD01U16V2KX-3GP

1 TPAD14-GP

AE50

VCCADAC

2

CRT

1.432A

+1.05V_VTT

TP2602

VCCADAC

1

VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE

VCC CORE

2

2

DY

AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31

L2603
+VCCA_DAC_1_2
SCD1U10V2KX-5GP

D

C2602
SC1U6D3V2KX-GP

7 OF 10

SCD01U16V2KX-3GP

C2601
SC10U6D3V5KX-1GP

1

1

1.432A

69mA

+3.3V_CRT_LDO

POWER

U2001G

2

+1.05V_VTT

SB-20

+3.3V_RUN

C2622
SCD1U10V2KX-5GP

2

IBEXPEAK-M-GP-NF

A00-0104-1
R2605
2
1
0R0402-PAD-2-GP

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PCH (POWER1)
Size

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Document Number

Rev

Winery13 MB DIS
Date:

W ednesday, January 13, 2010

Sheet
1

26

of

A00
88

4

3

POWER

U2001J
TP2701

SB-15

VCCACLK
1
TPAD14-GP

VCCACLK

AP53

VCCACLK

1

+1.05V_VTT

10 OF 10

VCCIO
VCCIO
VCCIO
VCCIO

V24
V26
Y24
Y26

VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

VCCSUS3_3

U23

VCCIO

V23

V5REF_SUS

F24

52mA

C2706

DYSC1U10V2KX-1GP
2

SSID = PCH

AP51

2

1

5

VCCME

AF42

VCCME

1

VCCME

Y42

VCCME

AU24

VCCVRM

BB51
BB53

VCCADPLLA
VCCADPLLA

68mA

BD51
BD53

VCCADPLLB
VCCADPLLB

69mA

AH23
AJ35
AH35

VCCIO
VCCIO
VCCIO

AF34

VCCIO

AH34

VCCIO

AF32

VCCIO

1

1

+5VALW _PCH_VCC5REFSUS

V12

DCPSST

Y22

DCPSUS

2
R2701
100R2J-2-GP

<1mA

V5REF

K49

VCC3_3

J38

VCC3_3

L38

VCC3_3

M36

VCC3_3

N36

VCC3_3

P36

VCC3_3

U35

VCC3_3

AD13

+5VS_PCH_VCC5REF

1

+3.3V_RUN

VCCSATAPLL
VCCSATAPLL

C2724
SCD1U10V2KX-4GP

P18

VCCSUS3_3

U19

VCCSUS3_3

U20

VCCSUS3_3

196mA

U22

VCCSUS3_3

V15

VCC3_3

V16

VCC3_3

Y16

VCC3_3

C2727
SCD1U10V2KX-4GP

2

1

2

+3.3V_RUN

SATA

1

163mA

1

AU18

V_CPU_IO

<1mA
V_CPU_IO

2

C2730
SCD1U16V2KX-3GP

2

C2729
SCD1U16V2KX-3GP

1

AT18

2

1

<1mA

CPU

+1.05V_VTT

+3.3V_RUN

C2716
SCD1U10V2KX-4GP

AK3
AK1

VCCSATAPLL

1
TPAD14-GP

VCCIO

AH22

VCCVRM

AT20

TP2702

C2717
SCD1U10V2KX-4GP

SB-16

VCCIO

AH19

VCCIO

AD20

VCCIO

AF22

VCCIO
VCCIO
VCCIO
VCCIO

AD19
AF20
AF19
AH20

VCCIO
VCCIO
VCCIO
VCCIO

AB19
AB20
AB22
AD22

VCCME
VCCME
VCCME
VCCME

AA34
Y34
Y35
AA35

+VCC_VRM

B

C2725
SC1U6D3V2KX-GP

+1.05V_VTT

IBEXPEAK-M-GP-NF

6mA

VCCSUSHDA

L30

6mA
1

2mA

C2733

2

1

VCCRTC

R2707

1

A00-0104-1

2
0R0402-PAD-2-GP

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

C2731
SC1U6D3V2KX-GP
Title

+3VS_+1.5VS_HDA_IO
Size

http://laptop-motherboard-schematic.blogspot.com/
4

1st Samsung

+3.3V_ALW

2

2

C2732

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

2mA

1

A12

HDA

+RTC_CELL

RTC

A

5

C2715
SC1U6D3V2KX-GP

2

2

1

2

+1.05VALW _INT_VCCSUS

+3.3V_ALW

C2728
SC10U6D3V5KX-1GP

2
R2702
100R2J-2-GP

+1.05V_VTT

C2723
SCD1U10V2KX-4GP

C2726
SCD1U10V2KX-4GP

C

1

B

+5V_RUN

D2702
CH751H-40PT-GP

C2712
SC1U6D3V2KX-GP

1

+VCCSST

+5V_ALW
+3.3V_RUN

+1.05V_VTT

1
2

1

C2720
SC1U6D3V2KX-GP

2

1
2

C2719
SC1U6D3V2KX-GP

DCPRTC

C2709
SCD1U10V2KX-4GP

2

68mA +1.05VS_VCCA_A_DPL
69mA +1.05VS_VCCA_B_DPL

+1.05V_VTT

C2718
SC1U6D3V2KX-GP

V9

<1mA

07/10 Change resistor Value
1.R2701,R2702 value corrected to 100 Ohms following PDG doc

D2701
CH751H-40PT-GP

2

Y41

DW

1

1
2

C2714
SC1U6D3V2KX-GP

2

2

DY

1

1

C2735
SC10U6D3V5MX-3GP

VCCME

+VCC_VRM

C2713
SCD1U10V2KX-4GP

+1.05VS_VCCA_B_DPL
2
IND-10UH-218-GP

VCCME

Y39

+3.3V_ALW
+3.3V_ALW

1

+VCCRTCEXT

L2703

1

V42

C2711
SC1U6D3V2KX-GP

2

2

DY

VCCME

PCI/GPIO/LPC

C2734
SC10U6D3V5MX-3GP

V41

Clock and Miscellaneous

+1.05VS_VCCA_A_DPL
2
IND-10UH-218-GP

1

1

1

L2702

C

VCCME

PCI/GPIO/LPC

+1.05V_VTT

DY

V39

2

2

C2710
SC1U6D3V2KX-GP

1

1

C2704
SC10U6D3V5KX-1GP

SB-17

DY

163mA

1.849A

2

VCCME

AF41

1

VCCME

AF43

2

C2708
SC1U6D3V2KX-GP

2

C2705
SC10U6D3V5KX-1GP

1

1.849A

2

VCCME

AD41

USB

+1.05V_VTT

2

VCCME

AD39

1

AD38

2

C2707
SCD1U10V2KX-4GP

D

C2703
SCD1U10V2KX-4GP

1

DCPSUSBYP

1

Y20

1

DCPSUSBYP

+3.3V_ALW

2

D

320mA

1

VCCLAN

2

VCCLAN

AF24

2

AF23

3

2

Document Number

PCH (POWER2)

Rev

Winery13 MB DIS
Date:

W ednesday, January 13, 2010

Sheet
1

27

of

A00
88

5

4

3

SSID = PCH

D

8 OF 10

U2001H

C

B

AB16

VSS

AA19
AA20
AA22
AM19
AA24
AA26
AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47
AB5
AB8
AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AD7
AE2
AE4
AF12
Y13
AH49
AU4
AF35
AP13
AN34
AF45
AF46
AF49
AF5
AF8
AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AH7
AJ19
AJ2
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AT5
AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

IBEXPEAK-M-GP-NF
A

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

1

9 OF 10

U2001I

AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42

2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

D

C

B

1st Samsung

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

IBEXPEAK-M-GP-NF

PCH (VSS)
Size

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Document Number

Rev

Winery13 MB DIS
Date:

W ednesday, January 13, 2010

Sheet
1

28

of

A00
88

5

4

3

2

1

D

D

C

C

(Blank)

B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

(Reserve)

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

29

of

88

5

4

3

2

1

A00-0104-1

+AVDD

SSID = AUDIO
1

Close to codec

Close to codec
AUD_DVDDCORE

1

+PVDD

C3016
SC10U6D3V5MX-3GP

A00-0104-1

U3001

10

PCH_AZ_CODEC_RST#

11

1

AMP_MUTE#

2
AMP_MUTE#

PORT_C_L
PORT_C_R
VREFOUT_C

19
20
24

DMIC_CLK/GPIO1
DMIC0/GPIO2

SPKR_PORT_D_L+
SPKR_PORT_D_L-

40
41

SPKR_PORT_D_RSPKR_PORT_D_R+

43
44

PORT_E_L
PORT_E_R

15
16

PORT_F_L
PORT_F_R

17
18

PC_BEEP

12

MONO_OUT

25

DMIC1/GPIO0/SPDIF_OUT_1

48

SPDIF_OUT_0

47

EAPD

CAP-

Internal pull up 60K
check external pull up??

CAP+

7

DVSS

33
30
26

AVSS
AVSS
AVSS

CAP2

22

AUD_CAP2

VREFFILT

21

AUD_VREFFLT

42

PVSS

V-

34

AUD_V_B

49

GND

VREG

37

AUD_VREG

U3002
AUD_DMIC_CLK_Y

5

VCC

4

Y

DY

OE#
A
GND

1
2
3

1

74LVC1G125DC-GP

92HD79B1A5NLGXTAX-GP

B

R3014
2 33R2J-2-GP

1

AUD_DMIC_CLK

1

[73] AUD_DMIC_CLK_G
EC3001
SC22P50V2JN-4GP

AUD_HP1_JACK_L
AUD_HP1_JACK_R

AUD_HP1_JACK_L
AUD_HP1_JACK_R

[60]
[60]

2

C

R3016

SB_SPKR_R
1
2
SCD1U10V2KX-4GP 120KR2F-L-GP
KBC_BEEP_R 1
2
1
2
SCD1U10V2KX-4GP
R3024
C3018
499KR2F-1-GP

AUD_PC_BEEP

AUD_PC_BEEP
Trace width>15 mils

2

2

DY

0R2J-2-GP
R3017

2 60D4R2F-GP
2 60D4R2F-GP

1
1

C3010
2
1

36

+3.3V_RUN

AUD_VREFOUT_B [60]
R3023
R3019

SC-1204-5
connect U3001 pin17, pin18 to pin12 net and change R3016 to 120K for vendor request

35

PUMP_CAPP

2
0R0805-PAD-2-GP

AUD_SPK_L+ [60]
AUD_SPK_L- [60]

1
C3024
SC2D2U25V5KX-1GP

L3003

1

AUD_EXT_MIC_L [60]
AUD_EXT_MIC_R [60]

AUD_SPK_L+
AUD_SPK_L-

2

PUMP_CAPN

1

AUD_HP1_JACK_L_C
AUD_HP1_JACK_R_C

C3011
SC10U6D3V5MX-3GP

2

31
32

1

HP1_PORT_B_L
HP1_PORT_B_R

2

AUD_EXT_MIC_L
AUD_EXT_MIC_R
AUD_VREFOUT_B

1

HDA_RST#

46

[37] AMP_MUTE#

28
29
23

HDA_SYNC

2
4

R3020
10KR2J-3-GP

HP0_PORT_A_L
HP0_PORT_A_R
VREFOUT_A_OR_F

1

HDA_SDO

PCH_AZ_CODEC_SYNC

AUD_DMIC_CLK
AUD_DMIC_IN0

[73] AUD_DMIC_IN0
C

5

AUD_SENSE_A
AUD_SENSE_B

C3017
SC1U10V3KX-3GP

2
0R0805-PAD-2-GP

From SB
SB_SPKR [24]
KBC_BEEP [37]

From EC

C3013
SC1U6D3V2KX-GP

+3.3V_RUN

HDA_SDI

PCH_SDOUT_CODEC

13
14

2

[24] PCH_AZ_CODEC_RST#

HDA_BITCLK

8

SENSE_A
SENSE_B

C3014
SCD1U10V2KX-4GP

C3021
SC10U6D3V5MX-3GP

[24] PCH_AZ_CODEC_SYNC

6

PCH_SDIN_CODEC_C0

39
45

1

[24] PCH_SDOUT_CODEC

PCH_AZ_CODEC_BITCLK

PVDD
PVDD

2

C3012
SC4D7P50V2CN-1GP

2 33R2J-2-GP

DVDD_IO

C3023
SC4D7U6D3V3KX-GP

1
2

DY

R3013 1

[24] PCH_SDIN_CODEC

DVDD

3

1

[24] PCH_AZ_CODEC_BITCLK

9

AVDD
AVDD

C3025
SC10U6D3V5MX-3GP

PCH_AZ_CODEC_BITCLK

DVDD_CORE

27
38

2

DVDDIO

1

1

1

1
C3027
SCD1U10V2KX-4GP

+5V_RUN

L3005

2

2

C3019
SCD1U10V2KX-4GP

2

C3009
SC1U6D3V2KX-GP

2

1

1

D

1

D

2
0R0805-PAD-2-GP

C3022
SC1U10V3KX-3GP

2

A00-0104-1
0R0402-PAD-2-GP
R3011

C3015
SCD1U10V2KX-4GP

2

2

+3.3V_RUN

1

1
+3.3V_RUN

+5V_RUN

L3004

B

2

DY
Close to codec
$]DOLD,)(0,

1

+AVDD

PCH_SDOUT_CODEC

2

R3012
47R2J-2-GP

+AVDD

AUD_SENSE_A

R3015
100KR2J-1-GP

C3026
SC1KP50V2KX-1GP

AUD_SENSE_B

1
R3022
20KR2F-L-GP

R3021
39K2R2F-L-GP

2

2

C3020
SCD1U10V2KX-4GP

1st Samsung

A

Wistron Corporation

2

DY

A

1

1

2

PCH_AZ_CODEC_SDOUT1

2

1

2

DY

Place this block
close to Audio Codec Pin13

1

1

R3018
2K49R2F-GP

EXT_MIC_JD# [60]

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Close to Pin14
Title

AUD_HP1_JD#

[60]

Revised HP/MIC detect circuit
2009/06/03

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

Document Number

AUDIO CODEC_92HD81
Sheet
1

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

30

of

88

5

4

3

2

1

D

D

C

C

(Blank)

B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

(Reserve)

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

31

of

88

5

D

4

3

2

1

D

SSID = SDIO
+3.3V_RUN_CARD

2

1

SD_D2 [33]
SD_D3 [33]

C3206
SCD1U10V2KX-4GP

2

SD_D2
SD_D3

PCH GPIO67(48M) confirm with SW

1

+3.3V_RUN_CARD trace = 40mil

[23] CLK_PCH_48M

C3207
SC10U6D3V5MX-3GP

RREF trace =15mils

090721-1

1 R3201 2
6K2R2F-GP

C3204
SC4D7U6D3V3KX-GP

24
23
22
21
20
19

C3202
SC1U10V2KX-1GP

25

RREF
DM
DP
3V3_IN
CARD_3V3
V18
GND

Close to chip

U3201
RTS5138-GR-GP

SP10
GPIO0
SP9
SP8
SP7
SP6

18
17
16
15
14
13

SD_CMD

SD_CMD [33]
SD_CLK

SD_CLK [33]

SD_CD#

SD_CD# [33]
C

7
8
9
10
11
12

2

2

1

DY

1

1

2

+3.3V_RUN_CARD
C3203
SCD1U10V2KX-4GP

V18

1
2
3
4
5
6

[21] USB_PN9
[21] USB_PP9

CLK_IN
XD_D7
SP14
SP13
SP12
SP11

090721-1

C

RREF

SC100P50V2JN-3GP

XD_CD#
SP1
SP2
SP3
SP4
SP5

C3201
1 DY2
+3.3V_RUN

V18 trace =15mils

SD_D0
SD_D1

SD_D0 [33]
SD_D1 [33]

SD_W P

SD_W P [33]

B

B

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CardReader/RTS5138

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

Rev

A00

Winery13 MB DIS

Date:

W ednesday, January 13, 2010

Sheet
1

32

of

88

5

4

3

2

1

SD/MMC/MMC+ Card Reader

SSID = SDIO
D

D

+3.3V_RUN_CARD

+3.3V_RUN_CARD
CARD1

NP1
NP2

1ST: 20.I0045.001
2ND:

C3304
SC2D2U10V3KX-1GP

1

C3303
SCD01U16V2KX-3GP

C3305
SC10U6D3V5MX-3GP

2

C3302

DY SCD1U16V2KX-3GP DY SCD1U16V2KX-3GP

SD_W P [32]

1

C3301

1

3
6
13

SD_CLK_R
SD_CMD_R

SD_CD# [32]

1

VSS1
VSS2
GND

NP1
NP2

SD_D3_R

2

DAT0
DAT1
DAT2

CD
CD/DAT3
CD/WP/GND
WP
CLK
CMD
EMPTY

1

VDD

2

7
8
9

Close to +3.3V_RUN_CARD

2

SD_D0_R
SD_D1_R
SD_D2_R

10
1
11
12
5
2
14

2

4

CARD-PUSH-9P-1-GP-U

C

C

Close to CARD1

EC3307
SC6D8P50V2CN-GP

1

EC3306
SC6D8P50V2CN-GP

EC3308
SC6D8P50V2CN-GP

2

EC3305
SC6D8P50V2CN-GP

1

EC3304

DY SC220P50V2KX-3GP

2

EC3303
SC6D8P50V2CN-GP

1

EC3302
SC6D8P50V2CN-GP

2

2

EC3301
SC6D8P50V2CN-GP

1

2
33R2J-2-GP

2

2 33R2J-2-GP

1

SD_CMD R3306 1

SD_D0_R
SD_D1_R
SD_D2_R
SD_D3_R
SD_W P
SD_CLK_R
SD_CD#
SD_CMD_R

2

SD_CLK R3305 1

[32] SD_CMD

33R2J-2-GP
33R2J-2-GP
33R2J-2-GP
33R2J-2-GP

1

[32] SD_CLK

2
2
2
2

1

R3301 1
R3302 1
R3303 1
R3304 1

2

SD_D0
SD_D1
SD_D2
SD_D3

1

SD_D0
SD_D1
SD_D2
SD_D3

2

[32]
[32]
[32]
[32]

SC-1207-1
pop EC3301,EC3302,EC3303,EC3305,EC3306,EC3307,EC3308 and change from 100p to 6.8p for EMI

SSID = 1394
B

B

Remove 1394

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

CARD READER CONN

Document Number

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

33

of

88

5

D

4

3

2

1

SSID = ExpressCard

+1.5V_CARD Max. 650mA, Average 500mA.
+3.3V_CARD Max. 1300mA, Average 1000mA
+3.3V_CARDAUX Max. 275mA

D

SB-26
NEW 1

27
1

NEW CARD_OC#

For 2nd Source 74.05538.073
C

16
14
13
5
4

NC#16
NC#14
NC#13
NC#5
NC#4

15
17
11
12
3
2
+3.3V_CARDAUX
+3.3V_ALW
+1.5V_CARD

PCH_SMB_CLK
PCH_SMB_DATA

[23] PCH_SMB_CLK
[23] PCH_SMB_DATA
+1.5V_CARD

PCIE_W AKE#

[22,76] PCIE_W AKE#
+3.3V_CARDAUX

SHDN#
PERST#
CPUSB#
CPPE#
SYSRST#

PERST#

+3.3V_CARD

20
8
9
10
6

PERST#
CPUSB#
CPPE#
NRST

PM_SLP_S4# [22,37,50]

RN3401

4
3

DY

1
2

[23] CLK_PCIE_NEW #
[23] CLK_PCIE_NEW

R3401 2

1 0R2J-2-GP

C3410 2

1 SC22P50V2JN-4GP

PLT_RST# [9,21,36,37,64,70,76,80]

DY

TPS2231RGP-GP-U

1ST: 74.02231.073
2ND: 74.09716.073

+3.3V_RUN
+3.3V_CARD
+1.5V_RUN

NEW CARD_CLKREQ#
CPPE#
CLK_PCIE_NEW #
CLK_PCIE_NEW

[23] NEW CARD_CLKREQ#
+3.3V_ALW

SRN100KJ-6-GP

AUXOUT
AUXIN
1.5VOUT
1.5VIN
3.3VOUT
3.3VIN

+1.5V_RUN
+1.5V_CARD
+3.3V_CARD
+3.3V_RUN

TP3401
PM_SLP_S3# [22,37,42,50,51,86]

21
19
18
1
THERMAL_PAD
OC#
RCLKEN
STBY#

7
GND

U3401

USB12_N
USB12_P
CPUSB#

[23] PCIE_IRXN5_NTXN5
[23] PCIE_IRXP5_NTXP5

PCIE_IRXN5_NTXN5
PCIE_IRXP5_NTXP5

[23] PCIE_ITXN5_NRXN5
[23] PCIE_ITXP5_NRXP5

PCIE_ITXN5_NRXN5
PCIE_ITXP5_NRXP5

C

28

SB-1021
pop and change L3401 to 120 ohm;
DY R3402, R3403 for EMI

PTW O-CON26-6-GP

+1.5V_CARD Max. 650mA, Average 500mA.
+3.3V_CARD Max. 1300mA, Average 1000mA
+3.3V_CARDAUX Max. 275mA

1ST: 20.K0370.026
2ND: 20.K0315.026

A00-0107-1
remove R3402, R3403 for no co-lay after XB
USB12_N

[21] USB_PN12
B

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

B

+3.3V_CARDAUX

1

2

L3401
DLW 21HN121SQ2L-1GP

1ST: 68.00201.201
2ND:

C3409
SCD1U10V2KX-5GP

3

4

2

C3406
SCD1U10V2KX-5GP

2

1

+3.3V_CARD

C3405
SC10U6D3V5MX-3GP

2

C3402
SCD1U10V2KX-5GP

2

C3401
SCD1U10V2KX-5GP

1

+1.5V_RUN

2

1

+3.3V_ALW

1

1

Lay out close to Chip

USB12_P

[21] USB_PP12

1

C3407
SC10U6D3V5MX-3GP

0715 Add commom choke

C3408
SCD1U10V2KX-5GP

2

1

C3404
SC4D7U6D3V5KX-3GP

+1.5V_CARD

2

1
2

C3403
SCD1U10V2KX-5GP

2

1

+3.3V_RUN

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

Document Number

ExpressCard

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

34

of

88

5

4

3

2

1

D

D

C

C

(Blank)

B

B

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

Document Number

(Reserve)

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

35

of

88

5

4

3

2

1

SSID = User.Interface

D

D

TPM board CONN
TPM1

+3.3V_RUN

11
1

SB-1022
Add R3601

C

[9,21,34,37,64,70,76,80]

PLT_RST#

PLT_RST#

R3601 1
0R2J-2-GP

DY

2

[24,37,70]
[24,37,70]
[24,37,70]
[24,37,70]
[24,37,70]

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#

[24,25,37] INT_SERIRQ
[21] PCLK_TPM

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLT_RST#_TPM
INT_SERIRQ
PCLK_TPM

2
3
4
5
6
7
8
9
10

C

DY

12
ACES-CON10-4-GP

SC-1125-1
remove TPM AFTP
B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

TPM

Size
Document Number
Custom

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

36

of

88

5

4
+3.3V_RUN_GPU

+3.3V_RUN_GPU

3

2

KBC_PWR

A00-0104-1

1

SSID = KBC

R3745

DY

1

1
+3.3V_RTC_LDO

100KR2J-1-GP
+3.3V_RTC_LDO

KBC_PWR

1

DY

R3716
2K2R2J-2-GP

SB-22

[22,34,42,50,51,86]

PM_SLP_S3#

AC_IN_L#

R3751 1

2

[69] LID_CLOSE#

1

[87] 1D5V_VGA_ON

2

UMA R3729
2K2R2J-2-GP

Remove
HDD_FALL_INT1

[66] PWRLED#
[66] PWR_BTN_LED#
[68] KB_BL_CTRL
[43] AD_OFF
[22] RSMRST#_KBC
[22,34,50] PM_SLP_S4#
[66] NUM_LOCK_LED#
[22,46] 3V_5V_POK
[22] PM_PWROK
[62] EC_SPI_WP#_R
[54]
[47]
[43]
[86]
[24]
[63,76]

BLON_OUT
IMVP_VR_ON
PSID_DISABLE#
GFX_CORE_EN
ME_UNLOCK#
USB_PWR_EN#

R3706 1
2
0R0402-PAD-2-GP
R3719 1
2
0R0402-PAD-2-GP

KBC_PWRBTN_EC#
AC_IN_R#
100R2J-2-GP
2
LID_CLOSE#
PCB_VER0
SW_UMA_ID
1D5V_VGA_ON
PCB_VER1
PWRLED#
PWR_BTN_LED#
KB_BL_CTRL
AD_OFF
RSMRST#_KBC
PM_SLP_S4#
NUM_LOCK_LED#
3V_5V_POK
PM_PWROK_R
EC_SPI_WP#_R
EC_PWR_SHDN#
BLON_OUT
IMVP_VR_ON_R
PSID_DISABLE#
GFX_CORE_EN
ME_UNLOCK#
USB_PWR_EN#

64
95
93
94
119
6
109
120
65
66
16
17
20
21
22
23
24
25
26
27
28
73
74
75
110

D/A

GPIO01/TB2
GPIO03
GPIO06
GPIO07
GPIO23
GPIO24
GPIO30
GPIO31
GPIO32/D_PWM
GPIO33/H_PWM
GPIO40/F_PWM
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO45/E_PWM
GPIO46/TRST#
GPIO47
GPIO50/TDO
GPIO51
GPIO52/RDY#
GPIO53
GPIO70
GPIO71
GPIO72
GPO82/TRIS#

GPIO

2

1

G

KBC_SCL1
KBC_SDA1

2

KBC_PWR

PANEL_BKEN

SB-1020

2

PANEL_BKEN_GPU

[81]

1

PANEL_BKEN_PCH

[20]

KBC_THERMTRIP#
1
R3709

2
100KR2J-1-GP

KBC_PWRBTN#

2
100KR2J-1-GP

DY

C

+3.3V_RTC_LDO

1
R3734

+3.3V_RUN

[21,54,74]

[64]

E51_TxD
E51_RxD

VTT_PWRGD_G34

+3.3V_RUN

4
5
6

DGPU_SELECT#

A
VCC
S

[22]
ECSWI#_KBC

[76]
VTT_PWRGD [9,49,52]

A00-0104-1

3
2
1

B0
GND
B1

ECSMI#_KBC

C3710
SC1U10V3KX-3GP

1ST: 73.03157.C0H
2ND: 73.03157.E0J

A

1

[22] PCH_SUSCLK_KBC

R3733
2K2R2J-2-GP

SW_UNSW_ID

D3703
K

D3701
K

A

1
2

2
1

[87] 3.3V_RUN_GPU_EN
[87] 1.05V_GFX_ON
[66] SCR_LOCK_LED#
[54] LCD_TST
[68] TPDATA
[68] TPCLK

[62] EC_SPI_DI
[62] SPI_DIO
[62] EC_SPI_CS#
[62] EC_SPI_CLK

1ST: 84.03904.H11
2ND: 84.03904.L06

10KR2J-3-GP

2
10KR2J-3-GP

2
10KR2J-3-GP

DY

2

DY

2

10KR2J-3-GP
10KR2J-3-GP

2
10KR2J-3-GP

2
100KR2J-1-GP

SB-34

77

SW_UNSW_ID
AMP_MUTE#

79
30

63
117
SHBM_LCDTST_EN31
32
118
62

[47] IMVP_VR_PWRGD
[22] PM_PWRBTN#
[54] SHBM_LCDTST_EN
[30] KBC_BEEP
[66] BATT_ORANGE_LED
[54] LBKLT_CTL_EC

R3707 2
0R0402-PAD-2-GP

3.3V_RUN_GPU_EN
1.05V_GFX_ON
SCR_LOCK_LED#
LCD_TST_R
TPDATA
TPCLK

1

13
12
11
10
71
72

EC_SPI_DI
EC_SPI_CS#
EC_SPI_CLK

R3753 1

2 0R2J-2-GP

R3735 1

2 0R2J-2-GP

+1.05V_VTT

86
87
90
EC_SPI_CLK_C 92
EC_SPI_DO

B

2 OF 2

U3701B
KBC_XI

32KX1/32KCLKIN

32KX2
GPIO55/CLKOUT
GPIO14/TB1
GPIO20/TA2
GPIO56/TA1
GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM

GPIO12/PSDAT3
GPIO25/PSCLK3
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1

KBSOUT0/JENK#
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT4/JEN0#
KBSOUT5/TDO
KBSOUT6/RDY#
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17

53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33

KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
TP_KCOL171

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

54
55
56
57
58
59
60
61

KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7

VCC_POR#

85

ECRST#

KBC

PS/2

A00-0104-1

CAPA2_INT_R#

3

1

[78] CAPA_INT#

Q3709_1

10KR2J-3-GP

2

ECSMI# [25]

1
2
1

Q3709
MMBT3904-7-F-GP

R3728
1
R3714
SHBM_LCDTST_EN
1
R3717
BLUETOOTH_EN
1
R3731
PANEL_BKEN
1
R3739

ECSCI# [25]

100KR2J-1-GP

2

1

KCOL0

A

2

[30] AMP_MUTE#

SB-34

R3727
4K7R2J-2-GP

S5_ENABLE

ECSWI# [25]

10KR2J-3-GP

2

R3741
10R2J-2-GP

KBC_PWR

DY

[20]

2

BAS16XV2T1G-GP-U

C3710 need place near pin 44.

A00-0104-1

[81]

PANEL_BKEN_PCH

BAS16XV2T1G-GP-U

1
NPCE781BA0DX-GP

D3702
K

PANEL_BKEN_GPU

TURBO_BOOST_ALERT# 1
R3752
WIRELESS_ON#/OFF 1
R3740
KB_BL_DET#
1
R3750
KA20GATE
1
R3743
KBRCIN#
1
R3742

BAS16XV2T1G-GP-U
ECSCI#_KBC

1ST: 83.01621.01F
2ND:

KBC_VCORF

44

2
1AGND 103

PM_LAN_ENABLE
1
2
S5_ENABLE [42]
R3723
0R0402-PAD-2-GP

AGND

GND
GND
GND
GND
GND
GND

E51_TxD [64]
E51_RxD [64]
AC_PRESENT_EC

+3.3V_RUN

F_SDI
F_SDO
F_CS0#
F_SCK

FIU

KCOL[0..16]

[68]

KROW[0..7]

[68]

TP3701

KBC_PWR

A

U3704

1

NPCE781BA0DX-GP

1
R3737
2K2R2J-2-GP

2
C3716

DY

VCC

3

2ECRST#

1

1st Samsung

RESET#

R3724
10KR2J-3-GP

G690L293T73UF-GP

B

E

1
SCD1U10V2KX-5GP

[9,25,42]

H_THRMTRIP#

E

[39,42] PURE_HW_SHUTDOWN#

C KBC_THERMTRIP#

A00-0105-1
Add reset IC U3704 to prevent SPI ROM data lost

1

2

R3702
0R2J-2-GP

DY

ECRST#_CB
Q3702
CH3906PT-GP

1ST: 84.03904.P11
2ND: 84.03904.T11

1ST: 84.03906.H11
2ND: 84.03906.R11

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

C3707
SC1U10V3KX-3GP
Title

http://laptop-motherboard-schematic.blogspot.com/
Q3701
CH3904PT-GP

Wistron Corporation

1

THERMTRIP_GATE 2

GND

2

2

C3704
SC4D7P50V2CN-1GP

KBC Nuvoton NPCE781BA0DX

C

2

DY
1

2
1

A

DY R3736
4K7R2J-2-GP

2
1

DY

3

BATT_WHITE_LED [66]

R3756
2K2R2J-2-GP

PCLK_KBC_RC

E51_TxD

3
4

SRN4K7J-8-GP

SC-1125-2
add U3703 mux for panel backlight enable signal select

KBC_SDA1 [23]
KBC_SCL1 [23]
BAT_SDA [44,45]
BAT_SCL [44,45]

BLUETOOTH_EN [73]
WIFI_RF_EN [64]
WIRELESS_ON#/OFF

114
14
15

GPIO16
GPIO34
GPIO36

SER/IR






R3726
0R2J-2-GP

07/07 Change
1.Change Power rail

2
1
SRN4K7J-8-GP

BAT_SDA
BAT_SCL

KBC_PWR

DY

3
4

1

PLT_RST# [9,21,34,36,64,70,76,80]

D3712

Pull High : Switch Board
Pull Low : UnSwitch Board

2

07/07 Dummy
1.Dummy R3736

10KR2J-3-GP

C3717
SC470P50V2KX-3GP

ECSMI#_KBC

111
113
112

GPO83/SOUT_CR/BADDR1
GPIO87/SIN_CR
GPO84/BADDR0

R3738
2K2R2J-2-GP

DW

DW

2

RN3701

R3730
0R0402-PAD-2-GP

.%&&/.
PCLK_KBC
(0,

DY
RN3702

A00-0104-1

NC7SB3157P6X-1GP

0%9(56,21
,'
9(5
9(5





1

+3.3V_ALW

1
2
0R0402-PAD-2-GP

DY

[24,36,70]

INT_SERIRQ [24,25,36]
PM_CLKRUN# [22]
KBRCIN# [25]
KA20GATE [25]

BATT_WHITE_LED

84
83
82
91

GPIO77
GPIO76/SHBM
GPIO75
GPIO81

SPI

VCORF

6$
6%
6&


PLT_RST1#_1

2

2

DY
2

2

DY

10KR2J-3-GP
R3711

R3708
10KR2J-3-GP

1

1

PCB_VER0
PCB_VER1

THERM_SCL [39,78]

U3703

116
89
78
45
18
5
1

1
2

R3701
10KR2J-3-GP

10KR2J-3-GP
R3732

B

E51_RxD
R3725

[66]

LPC_LAD[0..3]

KBC_SDA1
KBC_SCL1

81

GPIO66/G_PWM

DW
+3.3V_RUN

1

BAT54C-7-F-GP

SP

A00-0104-1

07/10 assign GPIO
1.assign GPIO TUCHPANEL_STP#

6

KBC_SDA1

+3.3V_RUN

SB-22

PCLK_KBC [21]
LPC_LFRAME# [24,36,70]

ECSCI#_KBC
PANEL_BKEN
ECSWI#_KBC

68
67
69
70

GPIO74/SDA2
GPIO73/SCL2
GPIO22/SDA1
GPIO17/SCL1

SMB

2

1

4

80

VDD

LPC

3

5

KBC_ON#

D

Q3706
2N7002A-7-GP

CAP_LOCK_LED#

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

4

2

GPI94
GPI95
GPI96
GPI97

A/D

KBC_SCL1

AC_IN# [45]

R3720

CAP_LOCK_LED#
PLT_RST1#_1

124
7
2
3
126
127
128
1
125
8
122
121
29
9
123

D

U3702

[39,78] THERM_SDA

DMN66D0LDW-7-GP

DY

S

BAT_IN# [44]

GPIO10/LPCPD#
LRESET#
LCLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
SERIRQ
GPIO11/CLKRUN#
KBRST#
GA20
ECSCI#/GPIO54
GPIO65/SMI#
GPIO67/PWUREQ#

3

2

1

Pull High : Discrete
internal Pull Low for UMA

VREF
GPI90/AD0
GPI91/AD1
GPI92/AD2
GPI93/AD3
GPIO05
GPIO04

1 OF 2

2 1

SUS_PWR_DN_ACK
101
KB_BL_DET_R#105
R3712 1
100R2J-2-GP
2
DGPU_PWR_EN#
106
CAPA2_INT_R#
107

[22] SUS_PWR_DN_ACK
[68] KB_BL_DET#
[25] DGPU_PWR_EN#

2

1
97
98
99
100
TURBO_BOOST_ALERT#108
KBC_THERMTRIP#
96

[43] PS_ID_EC
[25] TURBO_BOOST_ALERT#

07/23
1. Added R3712 100 Ohm damping resistor
2. Added R3713 100 Ohm damping resistor
3. Added R3751 100 Ohm damping resistor

C DIS

KBC_PWR

D3705
BAT54C-U-GP

DY
C3714
SC4D7U10V3KX-GP

GPIO41

102
AVCC

115
88
76
46
19
VCC
VCC
VCC
VCC
VCC

1
2

C3715
SCD1U10V2KX-4GP

1
2

C3706
SC2D2U6D3V3KX-GP

1
2

1
2

C3708
SCD1U10V2KX-4GP

1
2

2

C3713
SCD1U10V2KX-4GP

1

C3711
SCD1U10V2KX-4GP

1
2

C3712
SCD1U10V2KX-4GP

2

1

C3702
SC2D2U6D3V3KX-GP

C3701
SCD1U10V2KX-4GP

AD_IA_KBC
1.8_GFX_ON
THERMTRIP_VGA_R#

[45] AD_IA_KBC
[51] 1.8_GFX_ON

DY

EC_PWR_SHDN#

U3701A

104

KBC_PWR

KBC_PWR

C3703
SCD1U10V2KX-4GP

AGND

WD

SI2301CDS-T1-GE3-GP
Q3704

VBAT

2

1ST: 68.00084.881
2ND:

DY

DY

+3.3V_RUN

07/10 Added
1.Added circuit ,
For prevent electric leakage

2

1

+3.3V_RUN

G

1
2
0R0402-PAD-2-GP

D

Put 0.1uf close to VCC-GND pin pair.

KBC_ON#

R3755

2

10KR2J-3-GP
AC_IN_L#

1

L3701
BLM18AG601SN-3GP

KBC_PWR

R3744
10KR2J-3-GP

DY

A00-0104-1

R3754

1ST: 84.03904.H11
2ND: 84.03904.L06

DW

KBC_PWR

D

2

[78] KBC_PWRBTN#

THERMTRIP_VGA_R#

S

1

[81] THERMTRIP_VGA#

A00-0104-1

3

EC3701
SCD1U16V2KX-3GP

1

1

1

2

KBC_PWRBTN#
3 DY
D3704
BAT54C-U-GP

2

R3747
0R0805-PAD-2-GP

R3722
10KR2J-3-GP

1

Q3714_1
Q3714
MMBT3904-7-F-GP

R3721
10KR2J-3-GP

2

+3.3V_RTC_LDO

2

2

2

1

R3748
2K2R2J-2-GP

2

SB-1020

SC-1118-1
change power rail to KBC_PWR

KBC_PWR

R3746

1
2 KBC_PWRBTN_EC#
0R0402-PAD-2-GP

Size
Document Number
Custom

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet

37

of

88

5

4

3

2

1

D

D

C

C

(Blank)

B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

(Reserve)

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

38

of

88

5

4

3

+5V_RUN

SSID = Thermal

2

1

+3.3V_RUN

1

C3909
SCD1U10V2KX-5GP

R3907
10KR2J-3-GP

SB-1023

2

2

2

1

1

25mil
C3910
SC4D7U6D3V5KX-3GP

D

EMC2102_FAN_TACH_1

EMC2102_FAN_TACH_1

EMC2102_FAN_DRIVE

EMC2102_FAN_DRIVE

25mil

[58]

D

[58]

RN3901

3
4

2
1

+3.3V_RUN

SRN4K7J-8-GP

DW

THERM_SCL [37,78]
THERM_SDA [37,78]

07/10 Del
1. Not reserve S5 power source rail for EMC2102 ??

DN1

EMC2102_DP1

3

DP1

VGA_THERMDC

4

DN2

VGA_THERMDA

5

T8_THERMDC

6

T8_THERMDA

7

23

22

SMCLK

SMDATA

25

24
VDD_5Vb

26

21

GND

20

ALERT#

19

TP_ALERT#

CLK_IN

18

CLK_32K

DP2

CLK_SEL

17

EMC2102_CLK_SEL

DN3

RESET#

16

TP_EM2102_RESET# 1

NC#15

15

EMC2102

2

DW

DY

1

EMC2102_SHDN

POWER_OK#

THERMTRIP#

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN
R3917
10KR2J-3-GP

G

Q3903
2N7002A-7-GP

2

GND = Fan is OFF
OPEN = Fan is at 60% full-scale
+3.3V = Fan is at 75% full-scale

D

PURE_HW_SHUTDOWN#

TRIP_SET Pin Voltage
V_DEGREE=(((Degree-75)/21)
T8 shutdown is set 86 deg-C.

[37,42]

V_DEGREE

1ST: 84.2N702.E31
2ND: 84.2N702.D31

1

C3903
SC470P50V2JN-GP

C3903 must be
near EMC2102

C

R3902
10KR2F-2-GP

C3904
SCD1U10V2KX-5GP

SC-1204-1
R3904
2K37R2F-GP

2

3.HW T8 sensor ( CPU )

1

1

C3901
SC470P50V2JN-GP

B

1
C3902
SCD1U10V2KX-5GP

1

2

S
1

2
1

SRN10KJ-5-GP
KBC_PWR

2

2

E

3
4

2

R3914
10KR2J-3-GP

1ST: 84.03904.P11
2ND: 84.03904.T11

TPAD14-GP

R3910
10KR2J-3-GP

EMC2102_FAN_mode

0R2J-2-GP

1

DY

10KR2J-3-GP

2

1

C3901 must be near Q3901

B

C

GND = Internal Oscillator Selected
+3.3V = External 32.768kHz Clock Selected

1ST: 74.02102.A73
2ND: 74.07922.0B3

SHDN#_G
2

DY

SYS_SHDN#

CPU Sensor
Layout notice :
Both VGA_THERMDA and THERMDC routing
10 mil trace width and 10 mil spacing.

CH3904PT-GP
Q3901

+3.3V_RUN

2

1

R3916

B

1

1

+3.3V_RUN

2

3.

TPAD14-GP

RN3902

10KR2J-3-GP

07/23 Removed
1.Removed SYSTEM Sensor Critical

TP3903

TP3904

EMC2102_PWROK
EMC2102_THERMTRIP#

R3903

C3906 must be
near EMC2102

1

R3906

EMC2102-DZK-GP

14

13

8

GND = Channel 1
OPEN = Channel 3
+3.3V = Disabled

12

2

NC#8

C3906
SC470P50V2JN-GP

SYS_SHDN#

DP3
TRIP_SET

1

FANb

NC#21

[81] VGA_THERMDC

[81] VGA_THERMDA

FANa

28
TACH

VDD_3V

2

FAN_MODE

2. GPU Sensor

1
EMC2102_DN1

11

C

C3914 must be
near EMC2102

10

C3914
SC470P50V2JN-GP

VDD_5Va

1

2

2

C3912
SC470P50V2JN-GP

Layout notice:
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

C

U3901

C3905
SCD1U16V2KX-3GP

SHDN_SEL

DY

B

1

CH3904PT-GP
Q3905

1

E

C3912 must be near Q3905

9

1 EMC2102_VDD_3D3
R3908
49D9R2F-GP
2

2

29

+3.3V_RUN

Q3905 must be near WWAN

GND

1ST: 84.03904.P11
2ND: 84.03904.T11

27

1. WWAN

32K suspend clock output

2

Layout notice :
Both DN3 and DP3 routing 10 mil
trace width and 10 mil spacing.

DW

1ST: 84.2N702.E31
2ND: 84.2N702.D31

07/28 Removed
1. Removed U3902 AND gate.

Q3902
2N7002A-7-GP
R3913

D

S

CLK_32K_R

1

CLK_32K

2

10R2J-2-GP

A

1st Samsung

1

[22] PCH_SUSCLK_2102

DY
2

G

A

Wistron Corporation

C3911
SC4D7P50V2CN-1GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

RUN_POWER_ON

5

Thermal/Fan Controllor EMC2102

[42,52]

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

39

of

88

5

4

3

2

1

SSID = User.Interface

D

D

Free Fall Sensor
Note
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
- design PCB pad based on our sensor LGA pad size (add 0.1mm)
- solder stencil opening to 90% of the PCB pad size
- mount the sensor near the center of mass of the NB as possible as you can
1
2

C4001
SC10U6D3V5MX-3GP

2

1

+3.3V_RUN

C4002
SCD1U10V2KX-4GP

+3.3V_RUN

C

C

[7,18,19,23,64,76]

PCH_SMBCLK

14

[7,18,19,23,64,76]

PCH_SMBDATA

13

SDA/SDI/SDO

12

SDO

2 HDD_FALL_SDO
DY 0R2J-2-GP

7

1
1

2
INT1

8

HDD_FALL_INT1

INT2

9

FFS_INT2_R

GND
GND
GND
GND

2
4
5
10

CS

HDD_FALL_INT1

[21]
+3.3V_RUN

RESERVED#3
RESERVED#11

+5V_RUN

R4008
100KR2J-1-GP

G

3
11

SCL/SPC

06/25 Check
1.HDD_FALL_INT1 [ GPIO Table ]??

1

1
R4001

SA
R4004
100KR2J-1-GP

1ST: 84.2N702.E31
2ND: 84.2N702.D31

2

+3.3V_RUN

DY

VDD_IO

6
VDD

U4001

D4001
DE351DLTR8-GP

S

FFS_INT2_L

K

A

FFS_INT2 [59]

SDM20U30-7-GP

09/0422
(#1) Just pull +3.3V_RUN ~ Ref. Rothschild
(#2) FAE/ DY is ok, chip internal pull-up resistors
(#3) From spec, Slave ADdress(SAD) is 001110xb
Pull HIGH SAD is 0011101b
Pull GND SAD is 0011100b

B

D

Q4001
2N7002A-7-GP

1ST: 83.R2003.08M
2ND:
B

FFS_INT2_R

A

[25]

SB-1023

A

1st Samsung

Note
(1) Keep all signals are the same trace width. (included VDD, GND).
(2) No VIA under IC bottom.

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

Free Fall Sensor

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

40

of

88

5

4

3

2

1

D

D

C

C

(Blank)

B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

(Reserve)

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

41

of

88

5

4

3

2

1

SSID = Reset.Suspend
Remove +3.3V_DELAY power rail
H_THRMTRIP#

R4214
H_PWRGD_R

2

B

C4208
DY SCD1U10V2KX-4GP

D

DY

Q4201
CHT2222APT-GP

2

1KR2J-1-GP

C

DY

1

1

[9,25] H_PWRGOOD

[9,25,37]

E

D

2009/05/25

1ST: 83.01621.01F
2ND:

D4201

A

[46] 3V_5V_EN

K

PURE_HW_SHUTDOWN#

[37,39]

1

BAS16XV2T1G-GP-U

1
R4203

2
1KR2J-1-GP

S5_ENABLE [37]

2

DY R4209
200KR2J-L1-GP

C

C

+3.3V_RTC_LDO

1

Peak current:5.3A
Design current: 3.7A

R4201
100KR2J-1-GP

+5V_ALW

2

+5V_RUN

1
2
3
4

R4205
[52] PS_S3CNTRL

PS_S3CNTRL

RUN_POWER_ON

2 10KR2J-3-GP

1

RUN_ON_5V

+15V_ALW

D
D
D
D

8
7
6
5

1

AO4468-GP

2

B

Peak current: 8191mA
Design current: 5734.6mA

1

6

5

4

R4206
100KR2J-1-GP

+3.3V_RUN

[22,34,37,50,51,86]

RUN_POWER_ON

PM_SLP_S3#

1ST: 84.04468.037
2ND: 84.08884.037

11.6A
Rds=14m ohm

2

1

2

3
Q4202
DMN66D0LDW-7-GP

B

C4204
SC6800P25V2KX-1GP

U4201
S
S
S
G

[39,52]

+3.3V_ALW

1
2
3
4

R4211

2 10KR2J-3-GP RUN_ON_3D3V

8
7
6
5

11.6A
Rds=14m ohm

2

C4203
SCD01U25V2KX-3GP

D
D
D
D

AO4468-GP

1

1

U4202
S
S
S
G

1ST: 84.04468.037
2ND: 84.08884.037

SB-1023

Peak current: 1650mA
Design current: 1155mA
+1.5V_RUN

R4213
A

214K7R2F-L-GP

C4206
SCD01U25V2KX-3GP

2

1

1

1
2
3
RUN_ON_1D5VR 4

+1.5V_SUS
U4204
S
S
S
G

D
D
D
D

8
7
6
5

http://laptop-motherboard-schematic.blogspot.com/
4

3

Wistron Corporation

11.6A
Rds=14m ohm
1ST: 84.04468.037
2ND: 84.08884.037

5

A

1st Samsung

AO4468-GP

2

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Power Plane Enable

Size
Document Number
Custom

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

42

of

88

5

4

3

2

1

+5V_ALW

1
PSID_DISABLE#_R

1

DY

2

PSID_DISABLE#

[37]

PR4304
2K2R2J-2-GP

D

D

PR4302
1

S

PD4301
BAV99-4-GP

2

PQ4303
FDV301N-NL-GP

3

1

G

0R2J-2-GP

PS_ID

D

+3.3V_ALW

1

+3.3V_ALW

PR4301

1

3

C

PR4309
100KR2J-1-GP

PD4302
BAV99-4-GP

2

PQ4304
CH3904PT-GP

B

DY

PR4303
10KR2J-3-GP

E
1

PSID_PRO

2

D

2

PR4306
15KR2J-1-GP

1

2

2

SSID = DCIN

2

PS_ID_EC [37]

33R2J-2-GP

PR4310
[76] PS_ID_R2

PS_ID_R2

1

DY

2

33R2J-2-GP

1

PC4306
SCD01U25V2KX-3GP

C

PC4301
SC10U25V6KX-1GP

2

1

PC4305
SCD01U25V2KX-3GP

2

PC4304
SCD01U25V2KX-3GP

2

AO4407A-GP

1

8
7
6
5

2

PR4308
240KR3-GP

D
D
D
D

1

PC4302
SC1U25V5KX-1GP

PU4301
S
S
S
G

2

1

PC4303
SC1P50V2CN-1GP

1

This cap should be used
only as last resort for
EMI suppression.

+DC_IN_SS

1
2
3
4

2

C

+DC_IN

2

1

SC-1130-1
pop PC4303 for RF

Id=-12A
Qg=-25nC
Rdson=10~38mohm

PQ4302

DY

R1

R2

AD_OFF_L

2 GND

B

E
C

PDTA124EU-1-GP

AD_OFF_R

2

1
IN

DY
R1

[37] AD_OFF

3 OUT

R2

PQ4301

PR4307
47KR3J-L-GP

1

DDTC124EUA-7F-GP

B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

DCIN

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

43

of

88

5

4

3

2

1

SSID = BATT
Batt Connecter

D

D

BATT1

PBAT_ALARM#
PBAT_PRES1#
PBAT_SMBDAT1
PBAT_SMBCLK1

1

AFTP4406

1

AFTP4403

PR4402 1

PR4401

2

1

KBC_PW R

470KR2J-2-GP

PRN4401
SRN100J-3-GP
4
1
3
2

2 100R2J-2-GP

BAT_IN# [37]
BAT_SDA [37,45]
BAT_SCL [37,45]

2

PC4402
SCD1U50V3KX-GP

1

+PBATT

FOX-CON9-5-GP

PC4401
SC2200P50V2KX-2GP

2

1

BATT_SENSE [45]

PG4401
GAP-CLOSE-PW R-3-GP

2

11
10
9
8
7
6
5
4
3
2
1

1

GND
GND
GND2
GND1
BAT_ALERT
SYS_PRES#
BATT_PRS#
DAT_SMB
CLK_SMB
BATT2+
BATT1+

1ST: 20.80962.009
2ND: 20.81283.009
C

C

AFTP4401
AFTP4402
AFTP4404
AFTP4405

3

BAT_SCL

3

BAT_SDA

3

BAT_IN#

2

PD4403
BAV99-4-GP

1

2

1

PD4401
BAV99-4-GP

PD4402
BAV99-4-GP

2

1
1
1
1

1

PBAT_PRES1#
PBAT_SMBDAT1
PBAT_SMBCLK1
+PBATT

+3.3V_RTC_LDO

B

B

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

Document Number

Batt Connecter

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

44

of

88

5

4

3

2

1

SSID = Charger
1

1

PR4531
0R0402-PAD-2-GP
2

BAT_SENSE 1

1

2

GAP-CLOSE-PWR-3-GP

CHG_AGND
CHG_AGND

DY

1

EC4501
SCD1U25V2ZY-1GP

2

1
2

PD4502
1SMA18AT3G-GP

PC4523
SCD1U50V3KX-GP
A
K

PC4533
SC10U25V6KX-1GP
2
1

PC4530
SC10U25V6KX-1GP
2
1

PC4524
SC10U25V6KX-1GP
2
1

PR4505
0R0402-PAD-2-GP

BQ24745_CSON

BATT_SENSE [44]

DY
1

PR4521
1K8R6J-GP

DY

EC4502
SC2200P50V2KX-2GP

PC4546
SCD1U50V3KX-GP

PC4512
SC10U25V6KX-1GP
2
1

1
2

BQ24745_CSOP

2
PR4532
0R0402-PAD-2-GP

1
PR4509

1
2
0R0402-PAD-2-GP

DY

SB-1103

BQ24745_PR4505

2

15

PC4541
1
2

VFB

2

GND

16

1

2

PC4534
SC1U6D3V2KX-GP

PU4504
BQ24745RHDR-GP

CHG_AGND

NC#16

PC4544
SCD1U25V2ZY-1GP

PC4529
SCD01U50V2KX-1GP

FBO
EAI
EAO
VREF
CE
GND

29

1
2

DY

DY

PC4515
PC4537
SCD1U50V3KX-GP SCD01U50V2KX-1GP

DY

1

PC4525
SC56P50V2JN-2GP

2

2

2

1

DY

1

6
BQ24745_EAI
5
BQ24745_EAO
4
BQ24745_REF
3
1
2 BQ24745_CE 7
PR4510
12
0R0402-PAD-2-GP

2
1
PC4511
SC10U25V6KX-1GP
2
1

17

VICM

2009/06/24

+PBATT

PR4519
1
2
D01R2512F-3-GP

2

1

CSON

BQ24745_CSOP_1

+VCHGR1

PL4501

1

2

18

C

Charger Current=1.4~3.6A

SB-1103
1. change PL4501 to 68.5R610.201

L-5D6UH-GP

G
S
S
S

19

CSOP

PC4532
SC10U25V6KX-1GP
2
1

1
2

DY

4
3
2
1

8

PGND

PU4503
SI4800BDY-T1-GP

PC4517
SC3300P50V3KX-1GP
BQ24745_LX1

1
2
PC4536
SC220P50V2JN-3GP

SCD1U50V3KX-GP

NC#14

GAP-CLOSE-PWR-3-GP
PG4512
1
2

1

BQ24745_PHASE_GND
BQ24745_LGATE_1

5
6
7
8

20

DY

D
D
D
D

LGATE

SDA

1
2
PC4522
SCD1U50V3KX-GP

G
S
S
S

PHASE

23

4
3
2
1

BQ24745_CHARGER_UGATE
PR4536
0R0603-PAD-2-GP
1
2

GAP-CLOSE-PWR-3-GP
PG4506
1
2

PG4503
1
2

GAP-CLOSE-PWR-3-GP
PG4510
1
2
PC4528
SC1U6D3V2KX-GP

1

24

PR4537
200KR2F-L-GP
1
2

PC4526
SCD1U10V2KX-4GP

PC4516
1
SC220P50V2JN-3GP

PR4539
1BQ24745_FBO1
2
1
4K7R2J-2-GP

BQ24745_VICM
BQ24745_FBO

PC4540
PR4526
1
2SC2200P50V2KX-2GP
2
1PR4526_01
2 7K5R2F-1-GP
1
PC4518
SC150P50V2JN-3GP
1
2

2

UGATE

PC4514
SCD1U50V3KX-GP
1
2

14

2

PR4506
1
8K45R2F-2-GP

DY

PR4534
PD4501
CHG_AGND
0R0603-PAD-2-GP
BQ24745_BOOT_1
1
2BQ24745_BST1 K
A
1
2
BQ24745_LDO
PC4531
SD103AWS-1-GP SCD1U50V3KX-GP

DY

PC4543
SCD1U50V3KX-GP

9

25
21

DY

PG4507
GAP-CLOSE-PWR-3-GP
1
2

SCL

BOOT
VDDP

DY

PG4502
GAP-CLOSE-PWR-3-GP
1
2

10

27
26

DY

CHG_AGND

CHAGER_SRC

PU4505
SI4800BDY-T1-GP

ACOK

CSSN
ICOUT

SCD1U50V3KX-GP
BQ24745_CSSN
BQ24745_ICOUT

DY

Id=-12A
Qg=-25nC
Rdson=10~38mohm

PR4514
470KR2J-2-GP

5
6
7
8

BAT_SDA_1
1
GAP-CLOSE-PWR-3-GP

VDDSMB

13

+PBATT

8
7
6
5

CHAGER_SRC

28

CSSP

CHG_AGND

B

1

PR4533_02

1
ACIN

ICREF

DCIN

2

BAT_SCL_1
1
GAP-CLOSE-PWR-3-GP

2
PG4508

[37,44] BAT_SDA

PR4524
0R0402-PAD-2-GP

PC4520
BQ24745_CSSP1
2

2

PR4530
1
2
0R0402-PAD-2-GP

22

BQ24745_ACIN

PR4515
0R0402-PAD-2-GP
BQ24745_ACOK
1
2

2
PG4505

2

2

2

1

1
CHG_AGND

PR4524_03

D
D
D
D

DY

CHG_AGND

BQ24745_DCIN

11

[37,44] BAT_SCL

2009/08/04

[37] AD_IA_KBC

PC4513
SCD1U10V2KX-4GP

ACAV_IN

CHG_AGND

+3.3V_RTC_LDO

2

PR4528
10KR2F-2-GP
2
1

DY

PR4504
15K8R3F-GP
2
1

PC4548
SCD01U50V2KX-1GP

1

BQ24745_LDO

PR4511
2 10KR2F-2-GP
1

BQ24745_REF

2

C

PR4502 48K7R3F-1-GP
2
1

2

PC4521
SCD1U50V3KX-GP

1

PR4538
0R2J-2-GP

1
2
PC4519
SCD1U50V3KX-GP

DMN66D0LDW-7-GP

1
0R0402-PAD-2-GP

DY

PR4533
0R0402-PAD-2-GP

PR4522

2

2

1

6

PU4502
AO4407A-GP
S
D
S
D
S
D
G
D

D

2

1

+DC_IN_SS

PR4503
33R3J-2-GP
2
1

5

1
2
3
4

PG4509
PG4501
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP

1
2
PC4545
SCD1U50V3KX-GP

2

1
2
PR4508
D01R2512F-4-GP

2

4

PR4512
100KR2J-1-GP

2
1

A00-0104-1

3

+PWR_SRC

2

316KR3F-2-GP

PQ4502

BQ24745_ACOK

2

PQ4502_05

PR4520

PQ4502_03

1

+DC_IN_SS

Id=-12A
PR4513_03
Qg=-25nC
Rdson=10~38mohm
PR4513
10KR2F-2-GP

D

1
2
3
4

AO4407A-GP

PR4527
1
2
10KR2J-3-GP

+DC_IN_SS

PU4501
S
S
S
G

D
D
D
D

1

+SDC_IN

8
7
6
5

B

CHG_AGND

CHG_AGND

This Resistor
must be 1%
tolerance.

1

+3.3V_RTC_LDO

PQ4504
2N7002A-7-GP

G

A

1st Samsung

ACAV_IN

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

S

2

A

D

1

[37] AC_IN#

PC4527
SCD1U25V3KX-GP

2

PR4523
100KR2J-1-GP

2009/6/9

5

Title

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

CHARGER BQ24745

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

45

of

88

A

B

C

D

E

+3.3V_ALW_2

GAP-CLOSE-PWR

VOUT1

1
2
PD3904_1
3

1
2

1

2

1

PD3903_04

1

2

1

2

2

2

1
1

1

2

51125_DRVL1

1

1

2

2

2

S

+5V_PWR

SB-1103

13

51125_ENTIP2 6
3

DY

G

15

DY

PC4621
SC560P50V-GP

DY

1

PC4601

DY
2

PTC4604

1

PTC4602

PR4611
0R2J-2-GP

51125_VCLK

DY
RT8205BGQW-GP

GAP-CLOSE-PWR
PG4619
1
2
GAP-CLOSE-PWR
PG4601
1
2

GAP-CLOSE-PWR
PG4629
1
2

GAP-CLOSE-PWR
PG4621
1
2

GAP-CLOSE-PWR
PG4631
1
2

GAP-CLOSE-PWR
PG4622
1
2

GAP-CLOSE-PWR
PG4633
1
2

GAP-CLOSE-PWR
PG4632
1
2

GAP-CLOSE-PWR
SC-1130-1
change PC4601 pull up to +5V_ALW for layout.

1

18

GAP-CLOSE-PWR
PG4617
1
2

GAP-CLOSE-PWR
PG4628
1
2

1

25

S

PG4620

2

51125_ENTIP1

2D2R5F-2-GP

1

3V_5V_POK

DYPR4607

2

23
1

PU4605

1

51125_FB1

2

51125_VO1

2

PR4612
33KR2F-GP

GAP-CLOSE-PWR

51125_FB1_R
2

1 2

VREG3
PR4621
1
0R2J-2-GP

A00-1218-1
pop PR4619; dummy PR4618 by power to improve +15V_Pump Power on issue

TONSEL

CH1

CH2

200kHz

265kHz

245kHz

305kHz

VREG3

300kHz

375kHz

VREG5

365kHz

460kHz

+3.3V_ALW_2

2

1

PR4620
0R0402-PAD-2-GP
2

VREG3 or VREG5

VREF(2V)

Operating
Mode

OOA Auto Skip

Auto Skip

EN0

Close to VFB Pin (pin2)

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 2.2uH PCMC063T-2R2MN Cyntec 20 mohm Isat =14Arms 68.2R210.20B
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081
H/S: SiS412DN 24mohm/30mOhm@4.5Vgs/ 84.00412.037
L/S: Si7716ADN 13.5mOhm/16.5mOhm@4.5Vgs/ 84.06690.E37

+3.3V_RTC_LDO

SKIPSEL

Operating
Mode

1

2

2
1

PC4626

2

PR4615
21K5R2F-GP

3V_5V_POK [22,37]

1

VREF

DY

PR4614
100KR2J-1-GP

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 3.3UH PCMB104T-3R3MS Cyntec 11.8mohm Isat =16Arms 68.3R310.20C
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081
H/S: SiS412DN 24mohm/30mOhm@4.5Vgs/ 84.00412.037
L/S: Si7716ADN 13.5mOhm/16.5mOhm@4.5Vgs/ 84.06690.E37
GND

PC4623
SC18P50V2JN-1-GP

+3.3V_RTC_LDO

+5V_ALW2

1

17

TPS51125:ASM
RT8205B :DY

3D3V_AUX_S5_5_51125 8

2

2009/10/21 X01

PR4618
1
0R2J-2-GP
PR4619
0R0402-PAD-2-GP
1
2

DY

2

24

2

+3.3V_ALW_2

LG1_CP

GAP-CLOSE-PWR-3-GP

PR4617
1
0R2J-2-GP

DY

SKIPSEL

PG4623
1

PR4616
0R0402-PAD-2-GP
2

2

GND

SC10U10V5KX-2GP

Close to VFB Pin (pin5)

2

PGND

TONSEL

PC4625
SC4D7U10V5KX-4GP

51125_VREF

REF

1

2
1

+3.3V_ALW_2

1

ENTRIP1

VREG5

14
51125_SKIPSEL

+3.3V_ALW_2

51125_VREF

PGOOD

ENTRIP2

1

TPS51125:DY
RT8205B :ASM

4

EN

2

2009/10/21 X01

51125_TONSEL

FB1

151125_LL1_R
2

2 51125_EN
DY820KR2F-GP

FB2

2

5

3

GAP-CLOSE-PWR
PG4616
1
2

GAP-CLOSE-PWR
PG4625
1
2

+5V_ALW

1
2
IND-3D3UH-57GP

D

PG4612
2

GAP-CLOSE-PWR
PG4624
1
2

A00-1218-1
changePL4602 from 2.2U to 3.3U by power

PL4602

4
3
2
1

7

51125_FB2

2

PR4610
0R2J-2-GP

51125_VO2

1
PR4608

51125_VREF
1

G

2

S

1

5
6
7
8

19

G

1

VOUT2

51125_LL1

51125_VBST1_1

PG4614
2

GAP-CLOSE-PWR
PG4615
1
2

+PWR_SRC_5V

1

5
6
7
8

LGATE1

20

2

4
3
2
1

1

1

16
VIN

2

2

1
2

8
7
6
5
D
D
D
D
1
2
3
4

1

LGATE2

51125_DRVH1

8
7
6
5
D
D
D
D
S
S
S
G

151125_LL2_R
2

1
2
3
4

1

PU4604

1

2

PHASE1

51125_VBST1 1

21

+5V_ALW
1

+PWR_SRC

2009/08/24

ST100U6D3VBM-5GP

1

12

PHASE2

22

DY

ST220U6D3VDM-15GP

2

51125_DRVL2

UGATE1

SC22U6D3V5MX-2GP
PC4628

2

11

BOOT1

UGATE2

DIS(Auburndale)
Design Current =6.58A
10.34A290KHz
200K -->340KHz
100K -->380KHz
39K -->430KHz

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.8mohm Isat=25Arms 68.R5610.10D
O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01
H/S: SiS406DN/ POWERPAK-8/ 11.5mOhm/14.5mOhm @4.5Vgs/ 84.00406.037
L/S: SiS402DN/ POWERPAK-8/ 6.4mOhm/8mohm@4.5Vgs/ 84.00402.037

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

TPS51218_+1.05V_VTT
Size
Document Number
Custom
Date:
5

4

3

2

http://laptop-motherboard-schematic.blogspot.com/

Rev

Winery13 MB DIS

Wednesday, January 13, 2010
1

Sheet

49

A00
of

88

5

4

3

2

1

SB-1020-1
DY PR5012

SSID = PWR.Plane.Regulator_1D5V/0D75V
+5V_ALW

1

[22,34,37,42,51,86]

SB-1103

PR5012 1

PM_SLP_S3#

2 0R2J-2-GP

DY

0D75V_EN

0D75V_EN [52]

PR5006
5D1R3J-GP
+5V_ALW
D

2

2

+PWR_SRC_1D5V

DY

13

[49,51] RUNPWROK

1D5V_EN

11

0D75V_EN 10

23

15

DH

VTTEN

LX

8

TPS51116_VDDQSNS

9

TPS51116_VDDQSET
+5V_ALW

1

2

On

Off(Hi-Z)

S4/S5

Lo

Lo

Off

Off

Off

On

PC5015
SC330P50V3KX-GP
TPS51116_VDDQSNS

SB-1104

1
2

VVDDQSNS/2

1.8
Adjustable

VVDDQSNS/2

1
2

1
2

1
2

2

DY

GAP-CLOSE-PWR
PG5022
1
2

2009/08/18

GAP-CLOSE-PWR

PC5016
SC18P50V2JN-1-GP

2

2

V5IN
FB Resistors

GAP-CLOSE-PWR
PG5021
1
2

PTC5002

DY

1

VTTREF and VTT
VVDDQSNS/2

2.5

PTC5001

NOTE
DDR
DDR2
1.5 V < VVDDQ < 3 V

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.8mohm Isat=25Arms 68.R5610.10D
O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L0
H/S: SiS406DN/ POWERPAK-8/ 11.5mOhm/14.5mOhm @4.5Vgs/ 84.00406.037
L/S: SiS402DN/ POWERPAK-8/ 6.4mOhm/8mohm@4.5Vgs/ 84.00402.037
Switching freq-->400KHz

1st Samsung

PR5010
30KR2F-GP

A

Wistron Corporation

2

VDDQ (V)

PC5014
SCD1U10V2KX-4GP

1

PR5009
30K9R2F-GP

A

GND

PC5013
SC4D7U6D3V5KX-3GP

DY

TPS51116_VDDQSET

VDDQSET

PC5007
SC4D7U25V5KX-GP

2
1

2

2
1

2
1

5
6
7
8

1

TPS51116_PHS_SET

PG5016
GAP-CLOSE-PWR-3-GP

On

On

PR5008
2D2R5F-2-GP

1

On

Hi

4
3
2
1

4
3
2
1

Hi

Lo

2

IND-1D5UH-34-GP

DY

B

GAP-CLOSE-PWR
PG5020
1
2

1

4
3
2
1
5
6
7
8

1

PC5011
SC10U6D3V5MX-3GP

2

1
2

Hi

S3

PU5008

SIS402DN-T1-GE3-GP
S
S
S
G

S0

GAP-CLOSE-PWR
PG5019
1
2

SE220U2VDM-8GP

PU5001

DY

VTT

GAP-CLOSE-PWR
PG5013
1
2

PL5001

1

SIS402DN-T1-GE3-GP
S
S
S
G

VTTREF

GAP-CLOSE-PWR
PG5012
1
2

SE220U2VDM-8GP

GAP-CLOSE-PWR

GAP-CLOSE-PWR
PG5011
1
2

+1.5V_SUS_P

TPS51116_PHS

2

PC5012
SCD1U25V3KX-GP
D
D
D
D

PC5010
SC10U6D3V5MX-3GP

1
2

TPS51116_VBST1 1

GAP-CLOSE-PWR
PG5015
1
2

D
D
D
D

PC5009
SC10U6D3V5MX-3GP

1
2

PC5008
SCD1U10V2KX-4GP

TPS51116_UGT

PC5006
SCD1U50V3KX-GP

SIS406DN-T1-GE3-GP
S
S
S
G

+0.75V_DDR_VTT
PG5014
1
2

PU5009

PC5005
SC10U25V6KX-1GP

D
D
D
D

PU5003

DY

PC5021
SCD033U16V3KX-GP

DIS(Auburndale)
Design Current = 11.82A
18.57AB1 -iGPU PCH (UMA)
L=>B0 -dGPU GPU (DIS)

+3.3V_RUN

U5448

LCD1

2

2

LCD_CBL_DET#

2
1

1

1

VGA_TXAOUT0VGA_TXAOUT0+

2
+3.3V_RUN
33R2J-2-GP

1

R5406 1
R5413 1

2

1
R5404

BLON_OUT_R
LCD_TST_L
LDDC_CLK_CON
LDDC_DATA_CON
LCD_DET_G
LCD_CBL_DET#

C5406
SCD1U10V2KX-4GP

DY R5410
10KR2J-3-GP

2

+3.3V_EEPROM
LCD_BRIGHTNESS

LCD POWER

C5403
SC10U6D3V5KX-1GP

1

+3.3V_RUN
C5402
SCD1U10V2KX-4GP

2

1

+LCDVDD

1
NP1
31

33

DY

NC7SB3157P6X-1GP

1ST: 73.03157.C0H
2ND: 73.03157.E0J

3
2
1

B0
GND
B1

A
VCC
S

4
5
6

NC7SB3157P6X-1GP

ENVDD_M
DGPU_SELECT# [21,37,74]

1ST: 73.03157.C0H
2ND: 73.03157.E0J

H=>B1 -iGPU PCH (UMA)
L=>B0 -dGPU GPU (DIS)

LCD_BRIGHTNESS
BLON_OUT_R

1st Samsung

1

EC5401
SC33P50V2JN-3GP

2

DY

For EMI request

Wistron Corporation

R5407
10KR2J-3-GP

DY
2

1

EC5402
SC33P50V2JN-3GP

LCD_TST

1

34

DY

2

35

LDDC_CLK_CON

+LCDVDD

2

36

4
5
6

EC5404
SCD1U50V3KX-GP

1

32
NP2
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2

A
VCC
S

NC7SB3157P6X-1GP

2

JAE-CON30-5-GP-U

37

1

LVDS CONNECTOR

B0
GND
B1

2

+3.3V_RUN

U5445

EC5403
SCD1U25V2ZY-1GP

SC-1207-1
pop EC5403 for EMI

LDDC_DATA_CON
LDDC_CLK_CON

EDID_SELECT#

[21,55] EDID_SELECT#

C5405
SCD1U25V3KX-GP

1ST: 73.03157.C0H
2ND: 73.03157.E0J

1

H=>B1 -iGPU PCH (UMA)
L=>B0 -dGPU GPU (DIS)

1

A
VCC
S

1

B0
GND
B1

2

[20] L_DDC_DATA

1

3
2
1

[81] LDDC_DATA

F5401
POLYSW-1D1A24V-1-GP
2
1

LDDC_DATA_CON

2

+3.3V_RUN

U5444

2

[20] L_DDC_DATA
[20] L_DDC_CLK

http://laptop-motherboard-schematic.blogspot.com/

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

LCD/Inverter Connector

Size
Document Number
Custom

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet

54

of

88

5

4

3

2

SSID = VIDEO
A00-1218-1
change L5501, L5502, L5503 to 0R

2

A00-1218-1
change R5504, R5505, R5506 from 0R to 33R by EMI

+5V_RUN
D5504
B0530W S-7-F-GP
K
A

A00-0104-1
change CRT1 from 20.20431.015 to 20.20401.015

1

+5V_CRT_RUN

1

C5510
SCD01U16V2KX-3GP

CRT1

R5504
[74] M_RED

1

[74] M_GREEN

1

16
2

M_RED_C
33R2J-2-GP

1

2 L5502
0R3J-0-U-GP

CRT_R

2

M_GREEN_C
33R2J-2-GP

1

2 L5501
0R3J-0-U-GP

CRT_G

D

6
1

CRT_R

D

11

R5505

C5507
SC8P250V2CC-GP

+3.3V_RUN_GPU

+3.3V_RUN_GPU

1

DDC_CLK_CON

DW

2

DW
07/14 Change
1.Change CRT1 CONN PN from
20.20431.015 to 20.20401.015 base on ME emm files.
C

3
4

3
4

B

1

1

2

DY
2

+3.3V_RUN

C5520
SC10P50V2JN-4GP

A00-1218-1
change C5520 from 22p to 10p by EMI

DDC_DATA_CON2

4
5
6

+5V_CRT_RUN
DDC_DATA_CON
DDC_CLK_CON
CRT_R
CRT_G
CRT_B
JVGA_HS
JVGA_VS

DDC_DATA_CON
DDC_CLK_CON
C5519
SC22P50V2JN-4GP

A
VCC
S

1
1
1
1
1
1
1
1

C5504
SC33P50V2JN-3GP

RN5513
SRN2K2J-1-GP

UMA/DIS CRT DDC CLK/DAT select circuit

B0
GND
B1

AFTP5503
AFTP5501
AFTP5509
AFTP5507
AFTP5506
AFTP5508
AFTP5504
AFTP5505

C5502
SC33P50V2JN-3GP

+5V_CRT_RUN

[81] CRT_DAT_DDC
[81] CRT_CLK_DDC

U5542

C5506
SC8P250V2CC-GP

1ST: 20.20401.015
2ND: 20.20479.015

2
1

2
1
[20] GMCH_DDCDATA
[20] GMCH_DDCCLK

2

DY DY

+3.3V_RUN_GPU

RN5511
SRN2K2J-1-GP

3
4

RN5510
SRN2K2J-1-GP

[20] GMCH_DDCDATA

JVGA_VS [74]

15

07/07 Change
1.Change CRT DDC CLK/DAT Circuit

Close GPU

3
2
1

JVGA_HS [74]

JVGA_VS

2
1

1

D5503
BAV99-4-GP

DY

C5501
SC8P250V2CC-GP

*Pi-filter & 150 Ohm pull-down
resistors should be as close
as to CRT CONN.
* RGB signal will hit 75 Ohm
first, then pi-filter, finally
CRT CONN.

3

D5502
BAV99-4-GP

+3.3V_RUN

Close PCH

[81] CRT_DAT_DDC

JVGA_HS

14

17

Layout Note:

C5512
SC8P250V2CC-GP

2

3

CRT_B

DY

+3.3V_RUN_GPU

DDC_DATA_CON

13

1

1

2

2

2

C5508
SC8P250V2CC-GP

2

3
2

1

1

2

R5503
150R2F-1-GP

D5501
BAV99-4-GP

B

AFTP5502

12

VIDEO-15-127-GP-U

CRT_G

DY

CRT_B

2

DY

1

R5501
150R2F-1-GP

C

2 L5503
0R3J-0-U-GP

1

1

DY

2

1

DY

C5509
SC8P250V2CC-GP

CRT_R

M_BLUE_C
33R2J-2-GP

CRT_B

2

2

1

1

1

1
2
R5502
150R2F-1-GP

2

1

1

[74] M_BLUE

+5V_CRT_RUN

1

CRT_G

R5506

7
2
8
3
9
4
10
5

EDID_SELECT#

5V @ CRT side

+3.3V_RUN

NC7SB3157P6X-1GP

[21,54] EDID_SELECT#

Q5517

EDID_SELECT#
DDC_DATA_CON2
U5543

[81] CRT_CLK_DDC
A

[20] GMCH_DDCCLK

3
2
1

B0
GND
B1

A
VCC
S

4

3

5

2

6

1

DDC_DATA_CON

+3.3V_RUN

4
5
6

DDC_CLK_CON2
EDID_SELECT#



DMN66D0LDW -7-GP

A

DDC_CLK_CON2

NC7SB3157P6X-1GP

Wistron Corporation

DDC_CLK_CON

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

H=>B1 -iGPU PCH (UMA)
L=>B0 -dGPU GPU (DIS)

5

Title

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

CRT Connector

Document Number

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

55

of

88

5

4

3

2

1

D

D

C

C

(Blank)

B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

(Reserve)

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

56

of

88

5

4

3

2

1

D

D

(Blank)
C

C

B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

HDMI Connector

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

57

of

88

5

4

3

2

1

D

D

SSID = Thermal

Fan Connector

C

AFTP5803

1

EMC2102_FAN_TACH_1

AFTP5802

1

EMC2102_FAN_DRIVE

C

FAN1
[39] EMC2102_FAN_TACH_1

EMC2102_FAN_TACH_1

[39] EMC2102_FAN_DRIVE

EMC2102_FAN_DRIVE

5
3
2
AFTP5801

1

1
4

C5801
SC22U6D3V5MX-2GP

D5801
SDMK0340L-7-F-GP

FOX-CON3-6-GP-U

A

2

1

K

*Layout* 25 mil

1ST: 20.D0210.103
2ND: 20.F0714.003

B

B

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

Document Number

FAN

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

58

of

88

SSID = SATA

SATA HDD Connector

SATA HDD Interface comment
******************************
S1:GND
S2:RX+
S3:RXS4:GND
S5:TXS6:TX+
S7:GND
******************************
P1------------ 3.3V
P2------------ 3.3V
P3------------ 3.3V
P4:GND
P5:GND / Dell Detected Pin
P6:GND
P7------------ 5V
P8------------ 5V
P9------------ 5V
P10--- GND
P11:Dell: FFS_INT for supported HDD
P12:GND
P13------------ 12V
P14------------ 12V
P15------------ 12V
******************************

HDD1

23
S1
S2
S4
SATA_IRXN0_HTXN0

S5
SATA_IRXP0_HTXP0 2

S6
S7

+3.3V_RUN

1

SATA_IRXP0_HTXP0_C [24]

C5914
SCD01U25V2KX-3GP

P1
P2
P3
P4
+5V_RUN

P5

+5V_RUN

P6
P7
P8
P9
P10

FFS_INT2

P11

FFS_INT2 [40]

P12
P13
P14
P15
24
SKT-SATA7P+15P-24-GP-U

Close to CONN
5V power pin

1

C5901
SCD1U10V2KX-5GP

DY
2

1

DY
2

1

C5907
SCD1U10V2KX-5GP

+3.3V_RUN

2

1

+5V_RUN

C5902
SC10U6D3V5MX-3GP

1ST: 22.10300.451
2ND:

Close to CONN
3.3V power pin

SSID = SATA

ODD Connector
ODD1

[24] SATA_ITXP1_ORXP1
[24] SATA_ITXN1_ORXN1

1 SCD01U25V2KX-3GP
1 SCD01U25V2KX-3GP

SATA_IRXN1_OTXN1
SATA_IRXP1_OTXP1

+5V_RUN
C5915
SC10U6D3V5MX-3GP

1

SATA_RX- and SATA_RX+ Trace
Length match within 20 mil

2
2

2

C5911
C5912

1

[24] SATA_IRXN1_OTXN1_C
[24] SATA_IRXP1_OTXP1_C

2

2

C5913
SCD01U25V2KX-3GP
+3.3V_RUN

2

1

C5903
SC10U6D3V5MX-3GP

[24] SATA_IRXN0_HTXN0_C

SATA_ITXP0_HRXP0 [24]

S3

[24] SATA_ITXN0_HRXN0

C5908
SCD1U10V2KX-4GP

S1
S2
S3
S4
S5
S6
S7
P1
P2
P3
P4
P5
P6
7
8
NP1
NP2

GND
A+
AGND
BB+
GND
DP
+5V
+5V
MD
GND
GND
GND
GND
NP1
NP2
SKT-SATA7P+6P-38-GP-U
1st Samsung

Wistron Corporation

1ST: 62.10065.531
2ND: 62.10065.D21

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

http://laptop-motherboard-schematic.blogspot.com/

Size
A3
Date:

Document Number

HDD/ODD Connector

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet

59

of

88

5

4

3

SSID = AUDIO

2

1

SSID = AUDIO
AFTP6004
AFTP6002

1
1

AUD_SPK_L-_C
AUD_SPK_L+_C

MIC IN

Speaker Connector

AUD_VREFOUT_B

2

1ST: 20.F0693.002
2ND: 20.F1165.002

MLX-CON2-7-GP-U

[30] AUD_EXT_MIC_R

AFTP6005

1
C6014
1
C6015

2
SC1U25V5KX-1GP
2
SC1U25V5KX-1GP

LIN1
MIC_IN_L_2 1
L6002
MIC_IN_R_2 1
L6003

6
1
2
3
4
5

MIC_IN_L_C

2
BLM18BD601SN1D-GP

MIC_IN_R_C

2
BLM18BD601SN1D-GP

600ohm 100MHz
200mA 0.5ohm DC

SB-02

1

2

1
[30] AUD_EXT_MIC_L

AUDIO-JK186-GP

1

DY

4

EC6001
SC100P50V2JN-3GP

1

AUD_SPK_L+_C

[30] EXT_MIC_JD#

EC6002
SC100P50V2JN-3GP

2

2

1

1

D

1ST: 22.10265.301
2ND:

EXT_MIC_JD#

2

2

DY

AUD_SPK_L-_C

R6004
4K7R2J-2-GP

2

1

AUD_SPK_L+

2

2

R6006 1
0R0603-PAD-2-GP
R6007 1
0R0603-PAD-2-GP

EC6003
MLVG0402220NV05-GP

[30] AUD_SPK_L+

AUD_SPK_L-

EC6008
MLVG0402220NV05-GP

[30] AUD_SPK_L-

R6003
4K7R2J-2-GP

SPK1
3

C6001
SC1U6D3V2KX-GP

2

A00-0104-1

1

1

[30] AUD_VREFOUT_B

check cable pin define

D

SC-1207-1
pop EC6001 and EC6002 for EMI

AFTP6009
AFTP6020
AFTP6018
AFTP6019

C

1
1
1
1

EXT_MIC_JD#
GND
MIC_IN_L_C
MIC_IN_R_C

C

Delete Audio De-pop Circuit
2009/07/24

SSID = AUDIO
Head Phone

2009/06/03

[30] AUD_HP1_JD#

1ST: 22.10265.301
2ND:

AUD_HP1_JD#

LOUT1

[30] AUD_HP1_JACK_L
[30] AUD_HP1_JACK_R

AUD_HP1_JACK_L
AUD_HP1_JACK_R

L6004
L6001

B

1
1

6
1
2
3
4
5

AUD_HP_JACK_L_1
AUD_HP_JACK_R_1

2
2 BLM18BD601SN1D-GP
BLM18BD601SN1D-GP

2

1
EC6004
SCD01U16V2KX-3GP

2

C6003
SC1000P50V3JN-GP-U

1

1

B

AUDIO-JK186-GP

2

2

C6002
SC1000P50V3JN-GP-U

1

600ohm 100MHz
200mA 0.5ohm DC

EC6005
SCD01U16V2KX-3GP

SC-1208-1
change EC6004,EC6005 from 0.1U to 0.01U

AFTP6014
AFTP6017
AFTP6015
AFTP6016

1 AUD_HP1_JD#
1 GND
1 AUD_HP_JACK_L_1
1 AUD_HP_JACK_R_1

Added HP circuit 2009/05/26

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

SPEAKER/MIC/AUDIO JACK

Document Number

Sheet
1

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

60

of

88

5

4

3

2

1

D

D

C

C

(Blank)

B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

(Reserve)

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

61

of

88

5

4

3

SSID = Flash.ROM

2

1

SSID = RBATT

D

D

SPI FLASH ROM (2M bits) for KBC
EC_SPI_CS#
EC_SPI_HOLD#

1

1
2

KBC_PW R

1

RN6201
SRN100KJ-6-GP
1
2

2

4
3

KBC_PW R

RTC Connector

2

DY

+3.3V_RTC_LDO
+3.3V_RTC_LDO

C6201
C6203
C6204
SC4D7U10V3KX-GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP

1

C

+RTC_CELL

A00-0104-1
change RCT1 from 20.D0210.102 to 20.D0075.102

R6201
100KR2J-1-GP

1

+RTC_VCC
RTC1

CS#
SO
WP#
GND

VCC
HOLD#
SCK
SI

8
7
6
5

SPI_DIO

EC6202
SC4D7P50V2CN-1GP

C6202
SC1U10V3KX-3GP

BAT54CW -1-GP

1st 83.BAT54.B81
2nd 83.BAT54.A81

1

3
1

2

1KR2J-1-GP

2
4
AFTP6202

1
FOX-CON2-7-GP

Width=20mils

AT25DF021-SSH-T-GP

2

2

EC_SPI_CLK [37]
SPI_DIO [37]

RTC_PW R

2

1

EC_SPI_HOLD#

1

1
2
3
4

2

EC_SPI_CS#
SPI_DO
EC_SPI_W P#

2 0R2J-2-GP
2 0R2J-2-GP

1

R6205 1
R6204 1

U6203

1st 20.D0075.102
2nd 20.F0714.002

2

[37] EC_SPI_CS#
[37] EC_SPI_DI
[37] EC_SPI_W P#_R

R6202

1

2

3
KBC_PW R

C

D6201

EC6201

1st 72.25021.001 SC4D7P50V2CN-1GP
2nd 72.25205.B01

EC6203
SC4D7P50V2CN-1GP
AFTP6201

1

+RTC_VCC

B

B

SPI FLASH ROM (32M bits) for PCH
+3.3V_RUN
PCH_SPI_W P#
PCH_SPI_HOLD_0#

1

RN6202
SRN4K7J-8-GP
4
3

1

1
2

+3.3V_RUN

C6206
SCD1U16V2KX-3GP

2

2

DY
C6205
SC4D7U10V3KX-GP

1

+3.3V_RUN

R6207
4K7R2J-2-GP

+3.3V_RUN

U6202

2

SC-1208-1
change R6206 from 15ohm to 0 ohm

CS#
SO
WP#
GND

VCC
HOLD#
SCK
SI

PCH_SPI_HOLD_0#
PCH_SPI_CLK [24]
PCH_SPI_DO [24]
1st Samsung

AT25DF321-SU-GP

DY
2

2

DY

PCH_SPI_DI_R
PCH_SPI_W P#

EC6205
SC4D7P50V2CN-1GP

5

1st 72.25321.001
2nd 72.25325.A01

DY

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

EC6204
EC6206
SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP

http://laptop-motherboard-schematic.blogspot.com/
4

A

1

1

A

2
R6206
0R2J-2-GP

8
7
6
5

2

1

1
2
3
4

1

[24] PCH_SPI_CS0#
[24] PCH_SPI_DI

3

2

Size
A3
Date:

EEPROM/RTC Connector

Document Number

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

62

of

88

5

4

3

2

1

SSID = USB
USB & ESATA Power SW
SB-1021
1. pop and change TR6304 to 90 ohm for EMI;
DY R6302, R6308

USB_OC#0_1 [21,22]
U6303

+5V_USB1
USB_P0-

[21] USB_PN0

USB1

1ST: 68.00201.141
2ND: 68.02012.201

USB_P0USB_P0+

2
3
4
6
8

3

DLW21HN900SQ2LGP-U
TR6304
4

D

7
5
1

2

1

1
2

1
2

1

SC-1207-1
pop R6307 for EMI

1ST: 74.02062.B71
2ND: 74.00546.07D

TC6303
ST100U6D3VBML1GP

SC-1207-1
change C6302 to D1U for EMI

C6305
SC1U10V3KX-3GP

TPS2062AD-GP

2

C6302
SCD1U50V3KX-GP

at least 80 mil

8
7
6
5

2

D

OC1#
OUT1
OUT2
OC2#

2

1

[37,76] USB_PWR_EN#

GND
IN
EN1#
EN2#

C6306
SCD1U10V2KX-4GP

1
2
3
4

1

at least 80 mil

+5V_USB1

R6307
100KR2J-1-GP

+5V_ALW

SKT-USB-257-GP-U
USB_P0+

[21] USB_PP0

1ST: 22.10321.001
2ND: 22.10321.181

Remove ESD diode, confirmed with EMI
A00-0106-1
remove R6302, R6308 for no co-lay after XB
AFTP6317
AFTP6316
AFTP6321
AFTP6320

1
1
1
1

USB_P0USB_P0+
+5V_USB1
GND

C

C

SSID = ESATA

A00

ESATA Power
[21] USB_PN1

R6301
1
2
0R0603-PAD-2-GP

USB_P1-

[21] USB_PP1

R6306
1
2
0R0603-PAD-2-GP

USB_P1+

Share one power SW with USB port 1
Remove ESD diode, confirmed with EMI
+5V_USB1

A00-0106-1
remove TR6301 for no co-lay after XB

+3.3V_RUN

+3.3V_RUN

2

2

2

DY

B

1

1

D0
D1
R6316

DY

DY

C6319
SCD01U50V2KX-1GP

R6315

C6318
SC1U10V3KX-3GP
2
1

1

R6314

DY 4K7R2F-GPDY 4K7R2F-GP

C6317
SCD1U10V2KX-4GP
2
1

ASM

1

1

+3.3V_RUN

ESATA_ITX_DRX_PU
ESATA_ITX_DRX_NU

6
7

ESATA_IRX_DTX_PU
ESATA_IRX_DTX_NU

10
9

USB_P1+
USB_P1-

3
2

2

2
1

3
4
RN

2

ESATA_ITX_DRX_PU_C

R6304
1
2
0R0603-PAD-2-GP

ESATA_ITX_DRX_PU

ESATA_ITX_DRX_NU_C

R6310
1
2
0R0603-PAD-2-GP

ESATA_ITX_DRX_NU

ESATA_IRX_DTX_PU_L

R6311
1
2
0R0603-PAD-2-GP

1 R6313 U6301_REPEATER_EN
10R2J-2-GP

DY
U6301

6
10
20
16

CAPS CLOSE TO ESATA1

VCC
VCC
VCC
VCC

EN
TX_0P
TX_0N

DY

1
2
C6309
SCD01U50V2KX-1GP ESATA_ITX_DRX_P4_R
1
ESATA_ITX_DRX_N4_R
1
2
2
C6310
SCD01U50V2KX-1GP
ESATA_IRX_DTX_P4 11
1ESATA_IRX_DTX_P4_L
1
2
R6320
0R2J-2-GP ESATA_IRX_DTX_N4 12
1ESATA_IRX_DTX_N4_L
1
2
R6321
0R2J-2-GP
D0
9
D1
8

DY

ESATA_IRX_DTX_PU_L C6315 2
SCD01U50V2KX-1GP
ESATA_IRX_DTX_NU_L C6316 2
SCD01U50V2KX-1GP

D+
D-

4
5
8
11
12
13
14
15

AFTP6306
1

B

DY

RN6301
0R4P2R-PAD

[24] ESATA_ITX_DRX_N4

B+
B-

GND
GND
GND
GND
GND
GND
GND
GND

1ST: 22.10321.F71
2ND:

A00-0104-1

[24] ESATA_ITX_DRX_P4

A+
A-

ASM

R6317

+3.3V_RUN

VBUS

SKT-USB-ESATA-1-GP

DY 0R2J-2-GPDY 0R2J-2-GP
2

ESATA1
1

DY
DY

CAPS CLOSE TO ESATA1

RX_0P
RX_0N

TX_1P
TX_1N

DY

RX_1P
RX_1N
D0
D1

GND
GND
GND
GND
GND
GND

ESATA_ITX_DRX_PU_L 1

5
4

ESATA_ITX_DRX_NU_L 1

DY
DY

2R6318
0R2J-2-GP
2R6319
0R2J-2-GP

ESATA_ITX_DRX_PU_R1

ESATA_ITX_DRX_PU_C
2 C6311
SCD01U50V2KX-1GP
ESATA_ITX_DRX_NU_C
2 C6312
SCD01U50V2KX-1GP
C6313
2
ESATA_IRX_DTX_P4_C [24]
SCD01U16V2KX-3GP
2
ESATA_IRX_DTX_N4_C [24]
C6314
SCD01U16V2KX-3GP

ESATA_ITX_DRX_NU_R1

ESATA_IRX_DTX_P4_C_L

1

ESATA_IRX_DTX_N4_C_L

1

DY
DY

3
13
17
18
19
21

+5V_USB1
USB_P1USB_P1+

1
1
1

ESATA_IRX_DTX_PU

R6312
ESATA_IRX_DTX_NU_L

7
15
14

AFTP6308
AFTP6309
AFTP6302

1
2
0R0603-PAD-2-GP

ESATA_IRX_DTX_NU

A00-0106-1
remove TR6302, TR6303 for no co-lay after XB

RN

SN75LVCP412RTJR-GP
A

A

RN6302
0R4P2R-PAD

4
3

1
2
1st Samsung

A00-0104-1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

USB/ESATA Port

Size
Document Number
Custom

Rev

A00

Winery13 MB DIS

Date: Wednesday, January 13, 2010
1

Sheet

63

of

88

5

4

3

2

1

SSID = Wireless

D

D

Mini Card Connector(802.11a/b/g/n)
+1.5V_RUN

+3.3V_RUN

W LAN1

53
NP1
2

1
+5V_ALW

DY
2

2

DY

1

C6404
SC10U6D3V5MX-3GP

1

1

+1.5V_RUN

C6402
SCD1U16V2KX-3GP

2

C6405
SC10U6D3V5MX-3GP

1

+3.3V_RUN

DY

C6403
SCD1U10V2KX-5GP

[23] CLK_PCIE_MINI1#
[23] CLK_PCIE_MINI1

2

DY

[73] W LAN_ACT
[73] BT_ACT
[23] MINI1_CLKREQ#

R6404 1
R6403 1

[37] E51_RXD
[37] E51_TXD

2 0R2J-2-GP
2 0R2J-2-GP

DY
DY

E51_RXD_R
E51_TXD_R

[23] PCIE_IRXN2_MTXN2
[23] PCIE_IRXP2_MTXP2

C6406
SCD1U10V2KX-5GP

[23] PCIE_ITXN2_MRXN2
[23] PCIE_ITXP2_MRXP2

2

C6401
SCD1U16V2KX-3GP

2

C

1

1

+3.3V_RUN

+3.3V_RUN

2

1

W LAN_ACT
R6402
EC6401
SC220P50V2KX-3GP

1

+5V_ALW

DY

2

+5V_MINI_DEBUG

0R3J-0-U-GP

3
5
7
9
11
13
15

4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
NP2

C

PLT_RST#

W IFI_RF_EN [37]
PLT_RST# [9,21,34,36,37,70,76,80]
+3.3V_RUN

PCH_SMBCLK
PCH_SMBDATA

R6406
USB_P4-

1

2

USB_PN4 [21]

0R0603-PAD-2-GP
PCH_SMBCLK [7,18,19,23,40,76]
PCH_SMBDATA [7,18,19,23,40,76]

USB_P4USB_P4+

LED_W LAN_W IMAX_OUT# [66,76]
R6405
USB_P4+

1

2

USB_PP4 [21]

0R0603-PAD-2-GP

54

1ST: 62.10043.841
2ND: 20.F1519.052

SKT-MINI52P-41-GP

A00-0107-1
remove L6401 for no co-lay after XB

B

B

AFTP6402
AFTP6403

1
1

E51_RXD
E51_TXD

SB-09
SB-28

2

+3.3V_RUN

R6407
1KR2J-1-GP

ON OFF
1
2
3

NP1
1

TP6404
TPAD14-GP
1

2
3
NP2

W IRELESS_ON#/OFF_R 1

R6408

2

W IRELESS_ON#/OFF

[37]

1

10R2J-2-GP

SW -SLIDE67-GP

C6407
SC1U6D3V2KX-GP

2

1ST: 62.40083.001
2ND: 62.40018.441

1

SW 1

1st Samsung

A

A

Wistron Corporation
TP6405
TPAD14-GP

1

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

W IRELESS_ON#/OFF_R
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

MINICARD(WLAN)/ITP CONN

Document Number

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

64

of

88

5

4

3

2

1

D

D

C

C

(Blank)

B

B

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

WWAN Connector

Document Number

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

65

of

88

5

4

3

2

1

SSID = LED

D

D

PWR BTN LED
[37] PWR_BTN_LED#

PWR_BTN_LED#

2
R6628

1PWR_BTN_LED_R#
20KR2J-L2-GP

PWR_BTN_LED_R#

SCR_LOCK_LED#

2
R6620

1 SCRL_LED_R#
20KR2J-L2-GP

SCRL_LED_R#

CAP_LOCK_LED# 2
R6621

1 CAP_LED_R#
20KR2J-L2-GP

CAP_LED_R#

[78]

NUM_LOCK_LED# 2
R6622

1 NUM_LED_R#
20KR2J-L2-GP

NUM_LED_R#

[78]

[78]

For LED & Capacity board:
LED Type

Color

BATTERY LED1

Power rail

SCRLK LED

Amber(Multi-color) ALW

SCRL LED

White

ALW

CAP LED

White

ALW

NUM LED

White

ALW

PWR BTN LED

White

ALW

SATA ACT LED1

White

RUN

BT ACT LED

White

RUN

WLAN/WWAN ACT LED

White

RUN

[37] SCR_LOCK_LED#

[78]

CAPS LED
[37] CAP_LOCK_LED#

NUM LED
[37] NUM_LOCK_LED#
C

C

Bluetooth LED
[73] BT_ACTIVE_K#

LED_BT_ACT_K_R#
1
20KR2J-L2-GP

2
R6623

LED_BT_ACT_K_R#

[78]

SB-1024

WWAN LED
[64,76]

BT_ACTIVE_K#

LED_WWAN_OUT#

WLAN WIMAX_LED
LED Location from left to right
[64,76]

2
R6634

LED_WLAN_WIMAX_OUT#

1
20KR2J-L2-GP

WLAN_WIMAX_LED_R#

[78]

POWER

For LED&Capacity board:

+5V_ALW

BATTERY
LED6601

Orange
BAT_O_LED

C
BAT_O_LED_R

B

R6612
1
2BATT_LED_WHITE_R
560R2J-3-GP

3

1

BATT_LED_ORANGE

2

R1
0R0402-PAD-2-GP

E
R2

0R0402-PAD-2-GP

DY

PDTC124EU-1-GP

1ST: 84.00124.H1K
2ND: 84.00124.S1K

White
BAT_W_LED

C

BAT_W_LED_R

B

1

EC6607
SCD1U10V2KX-4GP

1ST: 84.00124.H1K
2ND: 84.00124.S1K

white

1ST: 83.00326.G70
2ND: 83.01222.K70

SB-03
LED6602
1A

K2
LED-Y-74-GP

DY

BREATH POWER LED

white
1ST: 83.00110.J70
2ND: 83.01221.R70

+5V_ALW

Q6608
R2
B

R1

[37] PWRLED#

2PWR2_LED_R

0R0402-PAD-2-GP

R2
PDTC124EU-1-GP

R6631
20KR2J-L2-GP
1
2 POWER_LED_R#

R6608
1
330R2J-3-GP

R1
E

0R0402-PAD-2-GP

BATT_LED_WHITE

2

B

LED-OW-3-GP

DY

1

[37] BATT_WHITE_LED

2

PWR2_LED

R6629

Q6609
R6632
1

BATTERY
Pin1(+) and Pin2(-)= orange
Pin1(+) and Pin3(-)= white

3

2

BATT_LED_WHITE

EC6610
SCD1U10V2KX-4GP
2
1

1

2

EC6609
SCD1U10V2KX-4GP
2
1

[37] BATT_ORANGE_LED

R6611
1
2BATT_LED_ORANGE_R
330R2J-3-GP

1

R6617

Q6607
R6630

BATT_LED_ORANGE

A00-0104-1

2

B

A00-0104-1

E

POWER_LED_L

C

DDTA143ECA-7-F-GP

Remove HDD LED

R6619

1

PWR2_LED

2

0R0402-PAD-2-GP

1ST: 84.00143.K11
SB-01
2ND:

HD LED

white

A

A

+5V_RUN

Q6606
R2

R6625
1

2

SATA_ACT_C# B

R1

[24] SATA_LED#

E
C

R6626
HDD_LED

1

2

SATA1_ACT_LED

SATA1_ACT_LED

20KR2J-L2-GP
DDTA143ECA-7-F-GP

1ST: 84.00143.K11
2ND:

0R2J-2-GP

[78]
1st Samsung

For LED & Capacity board

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A2
Date:

LED

Document Number

Rev

A00

Winery13 MB DIS
Wednesday, January 13, 2010
1

Sheet

66

of

88

5

4

3

2

1

D

D

C

C

(Blank)

B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

(Reserve)

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

67

of

88

5

4

3

SSID = KBC

2

1

SSID = Touch.Pad

Internal KeyBoard Connector
TouchPad Connector
D

KB1

1

AFTP6862

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

AFTP6837
AFTP6836
AFTP6839
AFTP6838
AFTP6841
AFTP6840
AFTP6842
AFTP6843
AFTP6844
AFTP6845
AFTP6847
AFTP6846
AFTP6849
AFTP6848
AFTP6851
AFTP6850
AFTP6853
AFTP6852
AFTP6855
AFTP6854
AFTP6857
AFTP6856
AFTP6859
AFTP6858
AFTP6860

D

+5V_RUN

+5V_RUN

31

C

KROW[0..7]

[37]

KCOL[0..16]

[37]

2

C6805
SCD1U10V2KX-5GP

1

2
1

KB_DET# [25]

RN6802
SRN10KJ-5-GP

TPAD1

5

3
4

KROW7
KROW6
KROW4
KROW2
KROW5
KROW1
KROW3
KROW0
KCOL5
KCOL4
KCOL7
KCOL6
KCOL8
KCOL3
KCOL1
KCOL2
KCOL0
KCOL12
KCOL16
KCOL15
KCOL13
KCOL14
KCOL9
KCOL11
KCOL10

1
2
3
4

[37] TPCLK
[37] TPDATA

1
1

KB_DET#

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

C6804
SC33P50V2JN-3GP

2
2

1

C6806
SC33P50V2JN-3GP

AFTP6835

1

6

ACES-CON4-10-GP-U

AFTP6815
AFTP6816
AFTP6817

1
1
1

+5V_RUN
TPCLK
TPDATA

1ST: 20.K0320.004
2ND: 20.K0382.004
C

32
ACES-CON30-3-GP

+5V_RUN

EC6805 1

2SCD1U25V2ZY-1GP

TPCLK

EC6806 1

2SCD1U25V2ZY-1GP

TPDATA

EC6807

2SCD1U25V2ZY-1GP

DY
DY
1
DY

1ST: 20.K0421.030
2ND: 20.K0259.030

KB Backlight CONN
B

B

+5V_RUN
KBBL1

5
R6815
1KR2J-1-GP
1
2CN7_P2
KB_BL_DET#
KB_BL_CTRL#

[37] KB_BL_DET#

AFTP6833
AFTP6832
AFTP6834
AFTP6861

1
2
3
4

1
1
1
1

+5V_RUN
CN7_P2
KB_BL_DET#
KB_BL_CTRL#

6
1
2
3

+5V_RUN

+5V_RUN

1

C6812
SCD1U10V2KX-5GP

DY
2

SC-1208-1
change Change Q6808 to 84.06402.B3D

1ST: 84.06402.B3D
2ND: 84.03456.D3D

1

AO6402A-GP

1

R6803
100KR2J-1-GP

1ST: 20.K0320.004
2ND: 20.K0382.004

ACES-CON4-10-GP-U

D 6
D 5
S 4

2

2

[37] KB_BL_CTRL

Q6808
D
D
G

For EMI
A

+5V_RUN

EC6801 1

2SCD1U25V2ZY-1GP

CN7_P2

EC6802

2SCD1U25V2ZY-1GP

KB_BL_DET#

EC6803

KB_BL_CTRL# EC6804

DY
1
DY
1
DY
1
DY

A

1st Samsung

C6895
SC4D7U10V5KX-1GP

Wistron Corporation

Place near CON5

2SCD1U25V2ZY-1GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

2SCD1U25V2ZY-1GP

Title

Keyboard/Touch Pad

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

68

of

88

5

4

3

2

1

SSID = User.Interface
Hall Sensor Connector
D

D

+3.3V_ALW

+3.3V_ALW

1

2

C6902
SCD1U10V2KX-5GP

1

DY R6903 2009/05/28

HALL1

R6903

1

VDD

3

OUTPUT

[37] LID_CLOSE#

1

2

DY 100KR2J-1-GP

VSS
LID_CLOSE#

1
R6901

LID_CLOSE#_1
2
10R2J-2-GP

C6901
SCD047U10V2KX-2GP

2

1ST: 74.06781.07B
2ND: 74.09132.A7B

2

EM-6781-T30-GP

C

C

B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

Hall sensor

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

69

of

88

5

4

3

2

1

SSID = DEBUG PORT

D

D

GOLDEN FINGER FOR DEBUG BOARD
+3.3V_RUN

C

G7001
[9,21,34,36,37,64,76,80]

PLT_RST#

1

PLT_RST#_GAP

2
GAP-OPEN

[24,36,37]
[24,36,37]
[24,36,37]
[24,36,37]
[24,36,37]

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#

[21] PCLK_FWH

SB-1021
DY DBT1 and add G7001

DBT1

1
2
3
4
5
6
7
8
9
10
11
12

C

DY

MLX-CON10-7-GP

B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Debug port

Size
Document Number
Custom

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

70

of

88

5

4

3

2

1

D

D

C

C

(Blank)

B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

(Reserve)

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

71

of

88

5

4

3

2

1

D

D

C

C

(Blank)

B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

Braidwood

Rev

A00

Winery13 MB DIS

Date: Wednesday, January 13, 2010

Sheet
1

72

of

88

5

4

3

2

1

SSID = User.Interface
For EMI

Camera Connector
D

D

4

3

USB_PP11 [21]
CAMERA1

9
1

+3.3V_CAMERA
R7301
0R3J-0-U-GP

1

2
1

1

L7301
DLW 21HN900SQ2LGP-U

CAMERA_USB1+
CAMERA_USB1AUD_DMIC_IN0_R

+3.3V_CAMERA

2

R7300

1 33R2J-2-GP

AUD_DMIC_IN0

AUD_DMIC_CLK_G

1ST: 68.02012.20G
2ND:

[30]

AUD_DMIC_CLK_G

[30]

2

+3.3V_RUN

1

2
3
4
5
6
7
8

Camera Power

C7305
SC4D7U6D3V3KX-GP

USB_PN11 [21]

1

AUD_DMIC_CLK_G
AUD_DMIC_IN0_R
+3.3V_CAMERA
CAMERA_USB1CAMERA_USB1+

EC7303

SC-1208-1
pop L7301 for EMI

DY

A00-0107-1
remove R7302, R7303 for no co-lay after XB

2

1
1
1
1
1

DY

MLVG0402220NV05-GP

EC7302

1ST: 20.F0779.008
2ND: 20.F1261.008
AFTP7302
AFTP7303
AFTP7304
AFTP7305
AFTP7306

1

AFTP7307

ACES-CON8-3-GP-U

MLVG0402220NV05-GP
2
1

2

DY

2

10
EC7304
SCD1U16V2KX-3GP

C

C

For ESD

Bluetooth cable conn.

SSID = User.Interface

BT1

Assign BT_DET# GPIO
2009/06/09

BLUETOOTH_EN
BT_LED

4
6
8
10
12
14
NP2
16

BT_ACT
+3.3V_RUN

USB_PP8
USB_PN8

C7302
SC2D2U10V3KX-1GP

1

B

AFTP6039

1

AFTP6031
AFTP6032
AFTP6033
AFTP6034
AFTP6035
AFTP6036
AFTP6037
AFTP6038

R7308
10KR2J-3-GP

2

DY

DY
2

1

R7307
100KR2J-1-GP

ACES-CONN14D-GP
EC7306
SC220P50V2KX-3GP
2
1

B

USB_PP8
USB_PN8
BT_ACT
BLUETOOTH_EN
W LAN_ACT

[21] USB_PP8
[21] USB_PN8
[64] BT_ACT
[37] BLUETOOTH_EN
[64] W LAN_ACT

3
5
7
9
11
13

1

W LAN_ACT

15
NP1
2

1

2

BLUETOOTH_DET#

1
1
1
1
1
1
1
1

BLUETOOTH_DET#
W LAN_ACT
BLUETOOTH_EN
BT_LED
BT_ACT
+3.3V_RUN
USB_PP8
USB_PN8

1ST: 20.F1500.014
2ND: 20.F0987.014

BT LED control signal 2009/05/26

pin define check

Close to BT1

+5V_RUN

BT_ACTIVE_K#

3

2

2
[66] BT_ACTIVE_K#

5

Q7302
MMBT3904-7-F-GP

1

BT_LED

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

1ST: 84.03904.H11
2ND: 84.03904.L06

http://laptop-motherboard-schematic.blogspot.com/
4

3

A

SB-25

2

Remove R7301
2009/06/09

C7303
SCD1U10V2KX-4GP

1

R7309
100KR2J-1-GP
A

C7304
SC2D2U6D3V3KX-GP
2
1

1

+3.3V_RUN

2

Size
A3
Date:

Camera CONN

Document Number

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

73

of

88

5

4

3

2

1

SSID = VIDEO
UMA/DIS LVDS signal select circuit
2
8
16
18
20
30
40
42

[20]
[20]
[20]
[20]
[20]
[20]
[20]
[20]

MCH_LVDSA_DAT2
MCH_LVDSA_DAT2#
MCH_LVDSA_DAT1
MCH_LVDSA_DAT1#
MCH_LVDSA_DAT0
MCH_LVDSA_DAT0#
MCH_LVDSA_CLK
MCH_LVDSA_CLK#

29
28
27
26
25
24
23
22

BTMDS2+
BTMDS2TMDS2+
BTMDS1+
TMDS2BTMDS1TMDS1+
BTMDS0+
TMDS1BTMDS0TMDS0+
BTMDSCLK+
TMDS0BTMDSCLK- TMDSCLK+
TMDSCLK-

3
4
6
7
11
12
14
15

DGPU_1D8V_SEL#

9

SB-1026
modify DGPU SEL circuit

SEL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C

TS3DV421RUAR-GP

C7403
SCD1U10V2KX-4GP

D

C7404
SCD1U10V2KX-4GP

VGA_TXAOUT2+ [54]
VGA_TXAOUT2- [54]
VGA_TXAOUT1+ [54]
VGA_TXAOUT1- [54]
VGA_TXAOUT0+ [54]
VGA_TXAOUT0- [54]
VGA_TXACLK+ [54]
VGA_TXACLK- [54]

1
5
10
13
17
19
21
39
41

C

43

GND

H=>BTMDS -iGPU PCH (UMA)
L=>ATMDS -dGPU GPU (DIS)

C7401
SCD1U10V2KX-4GP

1

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

2

ATMDS2+
ATMDS2ATMDS1+
ATMDS1ATMDS0+
ATMDS0ATMDSCLK+
ATMDSCLK-

2

38
37
36
35
34
33
32
31

2

VGA_LVDSA_DAT2
VGA_LVDSA_DAT2#
VGA_LVDSA_DAT1
VGA_LVDSA_DAT1#
VGA_LVDSA_DAT0
VGA_LVDSA_DAT0#
VGA_LVDSA_CLK
VGA_LVDSA_CLK#

1

+1.8V_RUN

[81]
[81]
[81]
[81]
[81]
[81]
[81]
[81]

1

U7411

D

71.03412.B0G

C7407
SCD1U10V2KX-4GP

2

1

+5V_CRT_RUN

UMA/DIS CRT Hsync/Vsync select circuit

B

+3.3V_RUN

B

Hsync & Vsync level shift

DGPU_SELECT
DGPU_SELECT#

UMA/DIS CRT signal select circuit

2

DY

1

14

1

+5V_CRT_RUN
EC7401
SCD1U25V2ZY-1GP

2

[20] GMCH_VSYNC

U7408A
SSAHCT125PWR-GP
VSYNC_5
3

C7408
SCD1U10V2KX-4GP

2

SB-1026
modify DGPU SEL circuit

5

1

[81] VGA_VSYNC

DGPU_SELECT 2

7

RN7445
VSYNC_5 1
HSYNC_5 2

DGPU_SELECT

4
3

JVGA_VS [55]
JVGA_HS [55]

SRN33J-5-GP-U

14

1

M_GREEN [55]

YC

9

M_RED [55]

YD

12

OE#

15

PI5C3257QE-GP

2ND = 73.03257.C0B

H=>IA1 -iGPU PCH (UMA)
L=>IA0 -dGPU GPU (DIS)

8

HSYNC_5

A

1st Samsung

Wistron Corporation

7

14

+5V_CRT_RUN

13

1

M_BLUE [55]

7

2

6

5

4

YB

U7408C
SSAHCT125PWR-GP

9

[20] GMCH_HSYNC
R7487
20KR2F-L-GP

YA

+5V_CRT_RUN

10

DGPU_SELECT#

+1.8V_RUN

2

3

VSYNC_5

6

DGPU_SELECT# H=> -iGPU PCH (UMA)
L=> -dGPU GPU (DIS)

Q7410
DMN66D0LDW-7-GP

4

[81] VGA_BLUE
[20] MCH_BLUE
[81] VGA_GREEN
[20] MCH_GREEN
[81] VGA_RED
[20] MCH_RED

U7408B
SSAHCT125PWR-GP

7

R7485
20KR2F-L-GP

A

4

14

+5V_CRT_RUN
+3.3V_RUN

+5V_CRT_RUN
U7435
16 VCC
1 S
2 IA0
3 IA1
5 IB0
6 IB1
11 IC0
10 IC1
14 ID0
13 ID1
8 GND

1
DGPU_SELECT#

12

[81] VGA_HSYNC

11

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

HSYNC_5

7

Title
DGPU_1D8V_SEL#

[21,37,54] DGPU_SELECT#

5

U7408D
SSAHCT125PWR-GP

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

PX Swith-1

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

74

of

88

5

4

3

2

1

D

D

C

C

(Blank)
B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

Document Number

(Reserve)

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

75

of

88

DC_IN baord
D

3

2

+DC_IN
+3.3V_RUN
CON
+5V_ALW
+1.5V_RUN
Please reoute 300 mil at least. +3.3V_ALW

:
:
:
:
:

19.5V/85W
3300mA
1000mA
500mA
58mA

1

Place near BTB1
+DC_IN

1

4

D

C7620

DYSC4D7U25V5MX-1DLGP
2

5

+DC_IN
BTB1

1

52

86%3257

[21] USB_PP2
[21] USB_PN2
[21] USB_OC#2_3
[37,63] USB_PWR_EN#
[23] CLKREQ#_LAN
[37] PM_LAN_ENABLE
[23,24] GPO_DSM
[43] PS_ID_R2

C

1

2

PCIE_IRXP4_MTXP4 [23]
PCIE_IRXN4_MTXN4 [23]

::$13&,(

CLK_PCIE_MINI2#
CLK_PCIE_MINI2

::$1&/.

[23]
[23]

::$186%

USB_PP5 [21]
USB_PN5 [21]
MINI2_CLKREQ_R# [23]
PCH_SMBDATA [7,18,19,23,40,64]
PCH_SMBCLK [7,18,19,23,40,64]
LED_WWAN_OUT# [64,66]
WWAN_RF_EN [21]
PLT_RST# [9,21,34,36,37,64,70,80]
PCIE_WAKE# [22,34]

::$160%86

C7621
SCD1U25V2ZY-1GP

+3.3V_RUN

DY

C7601
SC4D7U25V5KX-GP

C

+3.3V_RUN

C7602
SCD1U10V2KX-5GP

2

+3.3V_RUN
+1.5V_RUN
+3.3V_ALW

::$13&,(

1

/$13&,(

[23] PCIE_IRXN3_LRTXN3
[23] PCIE_IRXP3_LRTXP3

PCIE_ITXP4_MRXP4 [23]
PCIE_ITXN4_MRXN4 [23]

2

[23] PCIE_ITXN3_LRXN3
[23] PCIE_ITXP3_LRXP3

50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4

1

/$13&,(

49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3

2

NP2

/$1&/.

[23] CLK_PCIE_LAN#
[23] CLK_PCIE_LAN

+5V_ALW

+DC_IN

NP1
51
ACES-CONN50A-2-GP

SC-1130
pop C7614 for RF

1

+5V_ALW

Remove AFTP test point
Confirmed with AFTE.

C7614
SC1P50V2CN-1GP

2

1ST: 20.F1631.050
2ND:

1

+5V_ALW

C7615
SCD1U10V2KX-5GP

B

2

B

C7618
SCD1U10V2KX-5GP

2

1

+1.5V_RUN

C7619
SCD1U10V2KX-5GP

2

1

+3.3V_ALW

A

A



Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

DC_IN Board BTB Connector

Size
Document Number
Custom

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

76

of

88

5

4

3

2

1

D

D

C

C

(Blank)

B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Audio BD/IO BD CONN

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

77

of

88

5

4

3

2

1

SSID = User.Interface
A00-1223-1
1. dummy FP1 pin6, pin7 for power pin short to GND when plug in cable issue
2. add damping resister R7804

FP_VDD
FP1

LED&Capacity board CONN

5
4
3
2

Close to MEDIA1
+5V_RUN

1

+5V_RUN
+5V_ALW

SB-06
ACES-CON5-10-GP
[37] KBC_PWRBTN#

1ST: 20.K0315.005
2ND: 20.K0392.005

C

A00-0107-1
remove EL7801 for no co-lay after XB

AFTP7802
AFTP7803
AFTP7804
1
AFTP7805
1

1
1

R7803 1

[66]
[66]
[66]
[66]
[66]
[66]

2 100R2J-2-GP
WLAN_WIMAX_LED_R#
SCRL_LED_R#
CAP_LED_R#
NUM_LED_R#
SATA1_ACT_LED
LED_BT_ACT_K_R#

SB-1024

[66] PWR_BTN_LED_R#
[37] CAPA_INT#

+3.3V_RUN
Biometric_USBPN
Biometric_USBPP
BIO_DET#

SB-33
[37,39] THERM_SDA
[37,39] THERM_SCL

KBC_PWRBTN#_L
WLAN_WIMAX_LED_R#
SCRL_LED_R#
CAP_LED_R#
NUM_LED_R#
SATA1_ACT_LED
LED_BT_ACT_K_R#
PWR_BTN_LED_R#
CAPA_INT#
THERM_SDA
THERM_SCL

+3.3V_RUN

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22

2

6

+5V_ALW

+3.3V_RUN

1

1

2

MEDIA1

21
1

C7805
SCD1U10V2KX-4GP

BIO_DET#

[25] BIO_DET#

SB-14

7
Biometric_USBPN
Biometric_USBPP

2
2

0R0603-PAD-2-GP
R7802

2

C7801
SCD1U10V2KX-4GP

1

[21] USB_PN10
[21] USB_PP10

SB-1025
1. SWAP USB NET

2

R7801
0R0603-PAD-2-GP
1
1

2

A00-0104-1

R7804
0R3J-0-U-GP
1

1

+3.3V_RUN

D

C7804
SCD1U10V2KX-4GP

Finger Printer Connector

C7803
SCD1U10V2KX-4GP

D

C

AFTP7806
AFTP7808
AFTP7809
AFTP7810
AFTP7811
AFTP7812

1
1
1
1
1
1

WLAN_WIMAX_LED_R#
SCRL_LED_R#
CAP_LED_R#
NUM_LED_R#
SATA1_ACT_LED
LED_BT_ACT_K_R#

AFTP7814

1

CAPA_INT#

AFTP7816
AFTP7817
AFTP7818
AFTP7819
AFTP7820
AFTP7821
AFTP7822

1
1
1
1
1
1
1

THERM_SDA
THERM_SCL
+3.3V_RUN
+5V_RUN
+5V_ALW
PWR_BTN_LED_R#
KBC_PWRBTN#_L

SB-1024

PTWO-CON20-2-GP-U

1ST: 20.K0392.020
2ND: 20.K0481.020

B

B

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Finger Printer/Felica/Capacity

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

78

of

88

5

4

3

2

1

HOLE:

1

H10
HT85BE85R29-U-5-GP

1

H8
HT85BE85R29-U-5-GP

1

1

H7
HT85BE85R29-U-5-GP

EC7911
SCD1U25V2ZY-1GP
2
1

+3.3V_RUN_CARD

D

SC-1204-4
SB-12
change H2 to ZZ.00PAD.D11

SC-1207-1
add H16 for ME

SB-13
H3
HOLE256R115-GP

H14
HOLE256R115-GP

SSID = Mechanical

+PBATT

EC7915
SCD1U50V3KX-GP
2
1

SC-1130-1
add H15 for ME
H5
HT85BE85R29-U-5-GP

FOR CPU HOLE
H11
HOLE197R166-GP

H12
HOLE197R166-GP

H13
HOLE197R166-GP

C

1

H15
HT85BE85R29-U-5-GP

DY

1

DY

1

DY

1

1

EC7914
SCD1U50V3KX-GP
2
1

EC7913
SCD1U50V3KX-GP
2
1

EC7912
SCD1U50V3KX-GP
2
1

C

1

EC7910
SCD1U50V3KX-GP
2
1

CHAGER_SRC

H6
HT925X85BE95R29-L-5-S-GP

H2
HOLE256R115-GP

1

+5V_USB1

EC7909
SCD1U50V3KX-GP
2
1

EC7908
SCD1U50V3KX-GP
2
1

+1.5V_RUN_GPU

EC7907
SCD1U50V3KX-GP
2
1

+5V_CRT_RUN

EC7906
SCD1U50V3KX-GP
2
1

EC7905
SCD1U50V3KX-GP
2
1

DY

+VCC_CORE +1.5V_SUS

EC7904
SCD1U50V3KX-GP
2
1

EC7903
SCD1U50V3KX-GP
2
1

EC7901
SCD1U25V2ZY-1GP
2
1

+PWR_SRC

EC7902
SCD1U25V2ZY-1GP
2
1

+PWR_SRC

D

1

SC-1204-1
add EMI caps

EMI Request

H1
HT85B85X925R29-S-GP

1

H16
HT85B85X925R29-S-GP

1

SSID = EMI

SSID = RF
FORH4 FAN BOSS
STF296R138H83-GP

SB-29
RF Request

1

SC-1130-1
add RC7931 for RF

DY

+1.5V_RUN_GPU

SB-23

RC7931
SC56P50V2JN-2GP
2
1

DY

RC7929
SC1U6D3V2KX-GP
2
1

DY

RC7928
SC1U6D3V2KX-GP
2
1

DY

RC7910
SC1U6D3V2KX-GP
2
1

DY

RC7909
SC1U6D3V2KX-GP
2
1

DY

RC7908
SC1U6D3V2KX-GP
2
1

DY

RC7907
SC1U6D3V2KX-GP
2
1

DY

RC7906
SC1U6D3V2KX-GP
2
1

B

A00-0105-1
change SPR5 from 34.4F822.002 to 34.42T14.002 by ME

SPR1

SPR3

SPR4

SPR5

SPR6

DY

SPRING-31-GP

SPRING-57-GP

1

SPRING-24-GP-U

1

1

SPRING-24-GP-U

1

1

RC7930
SC1U6D3V2KX-GP
2
1

+PWR_SRC

DY

SPRING-24-GP-U

SPRING-24-GP-U

DY

+PWR_SRC

DY

RC7927
SC56P50V2JN-2GP
2
1

+1.05V_VTT

RC7918
SC56P50V2JN-2GP
2
1

RC7917
SC1U6D3V2KX-GP
2
1

RC7916
SC4D7P50V2CN-1GP
2
1

RC7915
SC1U6D3V2KX-GP
2
1

DY

RC7926
SC1U6D3V2KX-GP
2
1

+VCC_GFX_COREP

DY

RC7925
SC1U6D3V2KX-GP
2
1

DY

RC7914
SC56P50V2JN-2GP
2
1

RC7913
SC1U6D3V2KX-GP
2
1

+1.05V_VTT

SPR2

SC-1130-1
add SPR6 for ME

+3.3V_ALW

RC7924
SC1U6D3V2KX-GP
2
1

RC7920
SC56P50V2JN-2GP
2
1

RC7919
SC1U6D3V2KX-GP
2
1

DY

RC7922
SC56P50V2JN-2GP
2
1

DY

+1.5V_SUS

DY

+5V_ALW

RC7921
SC1U6D3V2KX-GP
2
1

DY

A

+15V_ALW

RC7912
SC1U6D3V2KX-GP
2
1

RC7911
SC1U6D3V2KX-GP
2
1

+PWR_SRC_3D3V

1

DY

RC7905
SC1U6D3V2KX-GP
2
1

DY

RC7904
SC1U6D3V2KX-GP
2
1

DY

RC7903
SC1U6D3V2KX-GP
2
1

+1.05V_VTT_P

RC7902
SC1U6D3V2KX-GP
2
1

B

RC7901
SC56P50V2JN-2GP
2
1

+PWR_SRC

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

+3.3V_ALW

5

+3.3V_ALW

Miscellaneous Components

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
Document Number
Custom

Rev

A00

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

79

of

88

5

4

3

2

1

PCIE_MTX_GRX_P[0..15]

SSID = VIDEO

PCIE_MTX_GRX_P[0..15] [8]

PCIE_MTX_GRX_N[0..15]

PEX_CLKREQ#
PEX_RST#

PEX_SVDD_3V3

1
R8004
10KR2J-3-GP

AG9
2 R8001 2K49R2F-GP

1

PLLVDD

AF9

+PEX_PLLVDD

K5

+GPU_PLLVDD

2009/05/28

Change power rail
2009/05/26
+3.3V_RUN

74LVC1G08GW -1-GP
R8016
100KR2J-1-GP

1
2

PEX_RST#

C8046
SC4D7U6D3V3KX-GP

4

GND

1

Y

1

2

VCC
A

NV suggestion.

07/10 NO STUFF
1. R8002 made NO STUFF

Place under GPU
(Pre pin)

SB-30

Place near GPU

+GPU_PLLVDD

+1.05V_GFX_PCIE
L8005

1
IND-D1UH-20-GP

100NH 0603

DCR= 0.13 ohm

Place near GPU

2009/05/28

Revised decoupling C

07/10 Change
1. Change U8028 from Operating voltage Range 5 to 3 V .
Add
2.Added Pull-down resistors on GPU Reset [PEX_REST#] Pin

A

B

Place under GPU

2

Revised decoupling C

DW

+1.05V_GFX_PCIE

L8011
SC1U10V2KX-1GP
C8070

DY

3

5

2

1

C8086
SC1U6D3V2KX-GP

R8017
100KR2J-1-GP

1

PLT_RST#_RC 2

2

0R2J-2-GP

2

1 R8039

PLT_RST#

2

[9,21,34,36,37,64,70,76]

B

PEX_PLLVDD = 120mA

1

1

[25] DGPU_HOLD_RST#

+PEX_PLLVDD

C8087
SCD1U16V2KX-3GP
2
1

U8028

DW

Remove 0.01u capacity C8039
2009/05/28

C8071
SCD1U16V2KX-3GP
2
1

GT218-ES-S-A1-GP

B

2

PEX_PLLVDD

Change R8004
resistor value
2009/06/05

+3.3V_RUN_GPU
PEX_TERMP

AG10

1

PEX_TERMP

DY

1

PEX_CLKREQ#
PEX_RST#

+3.3V_RUN_GPU

1
R8002

C8041
SC10U6D3V5KX-1GP
2
1

AE9
AD9

2009/05/28

2
200R2F-L-GP

C8073
SC10U6D3V5KX-1GP
2
1

PEX_TEST_PLL_CLK_OUT
PEX_TEST_PLL_CLK_OUT#

2009/05/28
C

C8061
SC1U10V3KX-3GP
2
1

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#

AF10
AE10

CLK_PCIE_VGA [23]
CLK_PCIE_VGA# [23]

C8063
SC1U6D3V2KX-GP
2
1

CLK_PCIE_VGA
CLK_PCIE_VGA#

D

+1.05V_GFX_PCIE

Place near GPU

2

Revised decoupling C

Revised decoupling C

PCIE_MRX_GTX_N[0..15] [8]

2

Place under GPU

AB10
AC10

C8059
SCD1U16V2KX-3GP
2
1

1
2

SCD1U16V2KX-3GP
C8065

1
2

SCD1U16V2KX-3GP
C8066

1
2

SC1U6D3V2KX-GP
C8068

1
2

SC1U10V2KX-1GP
C8067

1
2

SC4D7U6D3V3KX-GP
C8064

1
2

SC10U6D3V5KX-1GP
C8074

1
2

SC22U6D3V5MX-2GP
C8069

Place near GPU

PEX_REFCLK
PEX_REFCLK#

PCIE_MRX_GTX_P[0..15] [8]

PCIE_MRX_GTX_N[0..15]

Place under GPU

C

AB13
AB16
AB17
AB7
AB8
AB9
AC13
AC7
AD6
AE6
AF6
AG6

PCIE_MRX_GTX_P[0..15]

PCIE_MRX_GTX_P0
PCIE_MRX_GTX_N0
PCIE_MRX_GTX_P1
PCIE_MRX_GTX_N1
PCIE_MRX_GTX_P2
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_P3
PCIE_MRX_GTX_N3
PCIE_MRX_GTX_P4
PCIE_MRX_GTX_N4
PCIE_MRX_GTX_P5
PCIE_MRX_GTX_N5
PCIE_MRX_GTX_P6
PCIE_MRX_GTX_N6
PCIE_MRX_GTX_P7
PCIE_MRX_GTX_N7
PCIE_MRX_GTX_P8
PCIE_MRX_GTX_N8
PCIE_MRX_GTX_P9
PCIE_MRX_GTX_N9
PCIE_MRX_GTX_P10
PCIE_MRX_GTX_N10
PCIE_MRX_GTX_P11
PCIE_MRX_GTX_N11
PCIE_MRX_GTX_P12
PCIE_MRX_GTX_N12
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_N13
PCIE_MRX_GTX_P14
PCIE_MRX_GTX_N14
PCIE_MRX_GTX_P15
PCIE_MRX_GTX_N15

SC4D7U6D3V3KX-GP
C8075

AC9
AD7
AD8
AE7
AF7
AG7

1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP
1SCD1U10V2KX-5GP

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

C8062
SC1U6D3V2KX-GP
2
1

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

C8033
C8034
C8035
C8036
C8037
C8038
C8039
C8040
C8042
C8043
C8044
C8045
C8047
C8048
C8050
C8051
C8052
C8053
C8054
C8055
C8056
C8057
C8058
C8077
C8078
C8079
C8080
C8081
C8082
C8083
C8084
C8085

1

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

PCIE_MRX_GTX_C_P0
PCIE_MRX_GTX_C_N0
PCIE_MRX_GTX_C_P1
PCIE_MRX_GTX_C_N1
PCIE_MRX_GTX_C_P2
PCIE_MRX_GTX_C_N2
PCIE_MRX_GTX_C_P3
PCIE_MRX_GTX_C_N3
PCIE_MRX_GTX_C_P4
PCIE_MRX_GTX_C_N4
PCIE_MRX_GTX_C_P5
PCIE_MRX_GTX_C_N5
PCIE_MRX_GTX_C_P6
PCIE_MRX_GTX_C_N6
PCIE_MRX_GTX_C_P7
PCIE_MRX_GTX_C_N7
PCIE_MRX_GTX_C_P8
PCIE_MRX_GTX_C_N8
PCIE_MRX_GTX_C_P9
PCIE_MRX_GTX_C_N9
PCIE_MRX_GTX_C_P10
PCIE_MRX_GTX_C_N10
PCIE_MRX_GTX_C_P11
PCIE_MRX_GTX_C_N11
PCIE_MRX_GTX_C_P12
PCIE_MRX_GTX_C_N12
PCIE_MRX_GTX_C_P13
PCIE_MRX_GTX_C_N13
PCIE_MRX_GTX_C_P14
PCIE_MRX_GTX_C_N14
PCIE_MRX_GTX_C_P15
PCIE_MRX_GTX_C_N15

2

AD10
AD11
AD12
AC12
AB11
AB12
AD13
AD14
AD15
AC15
AB14
AB15
AC16
AD16
AD17
AD18
AC18
AB18
AB19
AB20
AD19
AD20
AD21
AC21
AB21
AB22
AC22
AD22
AD23
AD24
AE25
AE26

SC1U10V2KX-1GP
C8076

PEX_TX0
PEX_TX0#
PEX_TX1
PEX_TX1#
PEX_TX2
PEX_TX2#
PEX_TX3
PEX_TX3#
PEX_TX4
PEX_TX4#
PEX_TX5
PEX_TX5#
PEX_TX6
PEX_TX6#
PEX_TX7
PEX_TX7#
PEX_TX8
PEX_TX8#
PEX_TX9
PEX_TX9#
PEX_TX10
PEX_TX10#
PEX_TX11
PEX_TX11#
PEX_TX12
PEX_TX12#
PEX_TX13
PEX_TX13#
PEX_TX14
PEX_TX14#
PEX_TX15
PEX_TX15#

C8049
SCD1U10V2KX-4GP

+1.05V_GFX_PCIE

PEX_RX0
PEX_RX0#
PEX_RX1
PEX_RX1#
PEX_RX2
PEX_RX2#
PEX_RX3
PEX_RX3#
PEX_RX4
PEX_RX4#
PEX_RX5
PEX_RX5#
PEX_RX6
PEX_RX6#
PEX_RX7
PEX_RX7#
PEX_RX8
PEX_RX8#
PEX_RX9
PEX_RX9#
PEX_RX10
PEX_RX10#
PEX_RX11
PEX_RX11#
PEX_RX12
PEX_RX12#
PEX_RX13
PEX_RX13#
PEX_RX14
PEX_RX14#
PEX_RX15
PEX_RX15#

C8060
SCD1U16V2KX-3GP
2
1

D

AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22
AF22
AE22
AE24
AF24
AG24
AF25
AG25
AG26
AF27
AE27

C8072
SCD1U16V2KX-3GP
2
1

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15

PCIE_MTX_GRX_N[0..15] [8]

2 OF 7

U8001B

2
BLM18SG121TN1D-GP

I SP_PLLVDD=45mA

2009/05/28

1st Samsung

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

VGA-PCIE/LVDS(1/4)

Document Number

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

80

of

88

5

4

3

2

1

DW
+3.3V_RUN_GPU

SC-1204-1
add EC8101,EC8102,EC8103 for EMI

C8103
SCD1U10V2KX-5GP

1

Place under GPU

R8106
124R2F-U-GP
2
1

2

DACA_RSET
+DACA_VDD
DACA_VREF

AE1
AG2
AF1
R4
T4
T5
U4
U6
V6
W5
R6

DACB_VDD

+DACA_VDD

DACA_RSET
DACA_VDD
DACA_VREF

XTAL_IN
XTAL_OUT
XTAL_OUTBUFF
XTAL_SSIN

DACB_BLUE
DACB_GREEN MULTI_STRAP_REF0_GND
DACB_RED
MULTI_STRAP_REF1_GND

STRAP0
STRAP1
STRAP2

C7
B9
A9

AF4
AG3
AF3

TP_JTAG_TMS_GPU
TP8101
1
JTAG_RST#_GPU
2
1
TP_JTAG_TCK_GPU 1KR2J-1-GP
TP8103 R8120
1

C10
A10

ROM_SO_GPU
ROM_SI_GPU

C9
B10

ROM_SCLK_GPU

D10
E10

XTAL_IN
GPU_XTALOUT_1

3
4

TP8102
TP8104

1
1

DACB_VSYNC
DACB_HSYNC

THERMDN
THERMDP

DACB_RSET
DACB_VDD
DACB_VREF

TESTMODE
CEC
SP_PLLVDD
SPDIF

STRAP0
STRAP1
STRAP2

BUFRST#

XTAL_IN

R8123 1

XTAL_SSIN

R8131 1

R8132
10KR2J-3-GP

ROM_SCLK_GPU

STRAP_CAL_PU_GND0
STRAP_CAL_PU_GND1

F11
F10

R8133
1
1
R8126

D8
D9

DY

AD25
N2
L6
F9
N5

R8123

R8131

R8125

R8132

DY

POP

DY

POP

NON-SS

POP

DY

POP

DY

2 40K2R2F-GP
40K2R2F-GP

SB-30

DW30 not support HDMI
NV DG: pull-down 10K
IFPC_IOVDD
1
2
IFPC_PLLVDD
R8135 1 10KR2J-3-GP
2
R8134
10KR2J-3-GP

G4
G5

IFPE_PLLVDD
IFPE_RSET

IFPB_IOVDD
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA#
IFPC_L0
IFPC_L0#
IFPC_L1
IFPC_L1#
IFPC_L2
IFPC_L2#
IFPC_L3
IFPC_L3#

1
2

SC4D7U6D3V3KX-GP
C8120

1
J6
P6
R5

IFPDE_IOVDD

2

1

Place near GPU

D6
C6
A6
A7
B6
B7
E6
E7

1

1

B

R8130
D7
F8

IFPE_PLLVDD

2

Place under GPU
near IFPA_IOVDD

+IFPAB_IOVDD

2009/05/28

1

Revised decoupling C

2

R8129
H6

2009/05/28

+IFPAB_IOVDD
C8150
SCD1U10V2KX-4GP

D3
D4

2

M6

2
C8149
SC1U6D3V2KX-GP

1

BLM18PG181SN1D-GP

10KR2J-3-GP

2

IFPE_L0
IFPE_L0#
IFPE_L1
IFPE_L1#
IFPE_L2
IFPE_L2#
IFPE_L3
IFPE_L3#

IFPB_TXD4
IFPB_TXD4#
IFPB_TXD5
IFPB_TXD5#
IFPB_TXD6
IFPB_TXD6#
IFPB_TXD7
IFPB_TXD7#

2
BLM18SG121TN1D-GP

I SP_PLLVDD=45mA

IFPAB_IOVDD = 300mA

L8107
1

10KR2J-3-GP
IFPB_TXC
IFPB_TXC#

SC1U6D3V2KX-GP
C8127

2
P4
N4
M5
M4
L4
K4
H4
J4

IFPDE_IOVDD

2

1

10KR2J-3-GP

C8151
SCD1U10V2KX-4GP

V2

IFPAB_RSET

C

+1.05V_GFX_PCIE
L8110

+1.8V_RUN_GPU

IFPD_PLLVDD

Place under GPU
near IFPB_IOVDD

F7
G6

Unused IFP
Interfaces setting
2009/06/03
+IFPAB_PLLVDD
Revised decoupling C

IFPC_IOVDD
IFPC_PLLVDD

2009/05/28

IFPC_RSET
IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA#

Change power rail
2009/05/28

IFPAB_PLLVDD = 220mA

L8108
1

+IFPAB_PLLVDD

2

BLM18PG181SN1D-GP

2

GT218-ES-S-A1-GP

+1.05V_GFX_PCIE

Place near GPU

1

+IFPAB_IOVDD

IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA#

IFPAB_PLLVDD

1st: HARMONY 82.30034.651
2nd: ITTI 82.30034.801
3rd: TXC 82.30034.681

1 10KR2J-3-GP
+3.3V_RUN_GPU

Place near GPU

2

DW30 LVDS only 1 chanel
Vendor confirm tie to +1.8V powe rail

W1
V1
W3
W2
AA2
AA3
AB1
AA1

IFPD_RSET

C8138
SC15P50V2JN-2-GP

C8152
SC1U6D3V2KX-GP

AB2

IFPA_IOVDD

N6

4

+IFPAB_IOVDD

R8128
IFPD_PLLVDD

2009/06/15

[39]

2009/06/03

C8128
SC4D7U6D3V3KX-GP

AD5

DY 2 IFPAB_RSET AB6
2009/05/28AB3

1
R8121
1KR2F-3-GP

IFPA_TXD0
IFPA_TXD0#
IFPA_TXD1
IFPA_TXD1#
IFPA_TXD2
IFPA_TXD2#
IFPA_TXD3
IFPA_TXD3#

1

SB-19

Revised decoupling C
F5
F4
E4
D5
C3
C4
B3
B4

3

VGA_THERMDA [39]

R8107 2
1 10KR2J-3-GP

1

V3

IFPD_L0
IFPD_L0#
IFPD_L1
IFPD_L1#
IFPD_L2
IFPD_L2#
IFPD_L3
IFPD_L3#

1

V5
V4
AA5
AA4
W4
Y4
AB4
AB5

B

C8135
SC15P50V2JN-2-GP

+SP_PLLVDD

2

[74]
[74]
[74]
[74]
[74]
[74]

IFPA_TXC
IFPA_TXC#

2

XTAL-27MHZ-84-GP

R8115
1MR2J-1-GP

Added CLK GEN 27M select circuit
Added R8132 (DY) 2009/06/17

2009/06/03
2

3 OF 7

U8001C
AC4
AD4

+IFPAB_PLLVDD

Remove R8112,
R8114 2009/06/09

1

[74] VGA_LVDSA_CLK
[74] VGA_LVDSA_CLK#

+IFPAB_IOVDD

GPU_XTAL_IN

SS

2009/05/28

VGA_LVDSA_DAT0
VGA_LVDSA_DAT0#
VGA_LVDSA_DAT1
VGA_LVDSA_DAT1#
VGA_LVDSA_DAT2
VGA_LVDSA_DAT2#

2 0R2J-2-GP

VGA 27M

VGA_THERMDC

2009/05/28

Main 82.30034.651
Second ?

CLK_VGA_27M [7]

GPU_XTALOUT

C8102
SC2200P50V2KX-2GP

HDCP_TESTMODE
CEC
R8127 2
+SP_PLLVDD

X8101

2 0R2J-2-GP

[83]

0R0402-PAD-2-GP
GPU_XTAL_IN
R8114 1
2
GPU_XTALOUT
1
2
R8113
0R0402-PAD-2-GP
1 10KR2J-3-GP
A00-0104-1

XTALBUFF
R8124 2
E9
D11 XTAL_SSIN

DY
DY

R8125
10KR2J-3-GP

DY

ROM_SO_GPU [83]
ROM_SI_GPU [83]

2

1

C8107
SC470P50V2KX-3GP

2

1
2

[83] STRAP0
[83] STRAP1
[83] STRAP2

TP_JTAG_TDI_GPU
TP_JTAG_TDO_GPU

C8126
SC4D7U6D3V3KX-GP

Revised decoupling C

R8111
10KR2F-2-GP
C8108
SC4700P50V2KX-1GP

2

1

+DACA_VDD
C8118
SCD1U10V2KX-4GP

1
2

1
2

1
2

C8154
SC1U6D3V2KX-GP

1
2

Spec 300 ohm,
ESR<0.25 ohm

C8143
SCD1U10V2KX-4GP

16mil
C8153
SC4D7U6D3V3KX-GP

C

ROM_SCLK
ROM_CS#

DACA_VSYNC
DACA_HSYNC

1

L8106

1
2
BLM18SG331TN1D-GP

C8144
SCD1U10V2KX-4GP

+3.3V_RUN_GPU

DACA_BLUE
DACA_GREEN
DACA_RED

D

CLK GEN 27M select:
AG4
AE4

1

R8119
150R2F-1-GP

R8118
150R2F-1-GP
2
1

1
2

R8116
150R2F-1-GP
2
1

1
2

EC8103
SC15P50V2JN-2-GP

1
2

EC8102
SC15P50V2JN-2-GP

1
2

EC8101
SC15P50V2JN-2-GP

+DACA_VDD = 120mA
Place near GPU

AD1
AD2

[74] VGA_VSYNC
[74] VGA_HSYNC

ROM_SO
ROM_SI

Default X'tal

T1
T2

2

AD3
AE3
AE2

[74] VGA_BLUE
[74] VGA_GREEN
[74] VGA_RED

A3
A4

1

JTAG_TMS
JTAG_TRST#
JTAG_TCK

LDDC_CLK [54]
LDDC_DATA [54]

2

JTAG_TDI
JTAG_TDO

I2CB_SCL
I2CB_SDA

LDDC_CLK
LDDC_DATA

1

I2CS_SCL
I2CS_SDA

I2CB_SCL
I2CB_SDA

R2
R3
A2
B1

1

I2CH_SCL
I2CH_SDA

[55]
[55]

2

DEEPIDLE_WAKE_INT_R#

[25] DEEPIDLE_WAKE_INT_R#

I2CC_SCL
I2CC_SDA

CRT_CLK_DDC
CRT_DAT_DDC

2

THERMTRIP_VGA#

[37] THERMTRIP_VGA#
D

I2CB_SCL
I2CB_SDA

CRT_CLK_DDC
CRT_DAT_DDC

R1
T3

1

PWRCNTL_0
PWRCNTL_1

I2CA_SCL
I2CA_SDA

1

LBKLT_CTL_GPU
LCDVDD_EN_GPU
PANEL_BKEN_GPU
PWRCNTL_0
PWRCNTL_1

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19

2

[54]
[54]
[37]
[86]
[86]

RN8112
SRN2K2J-1-GP

4 OF 7

U8001D
N1
G1
C1
M2
M3
K3
K2
J2
C2
M1
D2
D1
J3
J1
K1
F3
G3
G2
F1
F2

2

SSID = VIDEO

2
1

07/05
1. LCD brightness control are separated by GPU,PCH,EC
2. LCD Power Enable control are separated by GPU,PCH,EC
3. LCD Backlight On/Off Status are separated by GPU,PCH,EC
07/10 Not Reserve
1. Shorted LBKLT_CTL_GPU,LCDVDD_EN_GPU,PANEL_BKEN_GPU Not Reserve R8134,R8135,R8136.

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A2
Date:

VGA-LVDS/CRT/DP PORT

Document Number

Rev

A00

Winery13 MB DIS
Wednesday, January 13, 2010
1

Sheet

81

of

88

5

4

3

2

1

SSID = VIDEO

Revised decoupling C

2009/05/28
U8001G

D

TPAD14-GP
TPAD14-GP

TP8203
TP8205

TP_VDD_SENSE_E15
E15
TP_VDD_SENSE_W 15 W15

1
1

NC#J5
NC#D15
NC#C15

J5
D15
C15

RFU_1
RFU_2
RFU_3
RFU_4
RFU_5

T6
W6
Y6
AA6
N3

Place under GPU

Place near GPU

VDD_SENSE
VDD_SENSE

VID_PLLVDD

K6

1
2

C8231
SC4D7U6D3V3KX-GP

1

Revised decoupling C

C8211
SC1U6D3V2KX-GP

2

1

1

C8232
SCD1U10V2KX-5GP

2

A12
B12
C12
D12
E12
F12

2

VDD33
VDD33
VDD33
VDD33
VDD33
VDD33

C8230
SCD1U10V2KX-5GP

+3.3V_RUN_GPU

1

C8240
SC4D7U6D3V3KX-GP

2

1

Place near GPU

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

2

2

1

C8247
SCD01U16V2KX-3GP

1

C8246
SCD01U16V2KX-3GP

2

1

C8244
SCD01U16V2KX-3GP

2

J9
J10
J12
J13
L9
M9
M11
M17
N9
N11
N12
N13
N14
N15
N16
N17
N19
P11
P12
P13
P14
P15
P16
P17
R9
R11
R12
R13
R14
R15
R16
R17
T9
T11
T17
U9
U19
W9
W10
W12
W13
W18
W19

C8234
SCD1U10V2KX-4GP

SCD047U10V2KX-2GP
2
1

1
2

C8243
SCD01U16V2KX-3GP
C8250

SCD047U10V2KX-2GP
2
1

1
2

C8242
SCD01U16V2KX-3GP
C8249

SCD047U10V2KX-2GP
2
1

1
2
1

C8248

2

C8241
SCD01U16V2KX-3GP

+VCC_GFX_CORE

C

6 OF 7

U8001F

C8229
SCD1U10V2KX-5GP

Place under GPU

2009/05/28

+GPU_PLLVDD

B2
B5
B8
B11
B14
B17
B20
B23
B26
E2
E5
E8
E11
E17
E20
E23
E26
F6
H2
H5
J11
J14
J17
K19
K9
L2
L11
L12
L13
L14
L15
L16
L17
L5
M12
M13
M14
M15
M16
P2
P5
P9
P19
P23
P26
T12
T13
T14
T15
T16

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

7 OF 7

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND_SENSE
GND_SENSE

D

AF8
AF5
AF26
AF23
AF20
AF2
AF17
AF14
AF11
AC26
AC23
AC20
AC17
AC14
AC11
AC8
AC6
AC5
AC2
Y26
Y23
Y5
Y2
W17
W14
W11
V9
V19
U26
U23
U17
U16
U15
U14
U13
U12
U11
U5
U2

C

E14
W16

2009/05/28
GT218-ES-S-A1-GP
GT218-ES-S-A1-GP

"Remote Voltage Sensing" not used,reserve Test-Point.

B

Change FBVDDQ power rail
2009/05/28

B

FBVDD/Q = 2.24A

+1.5V_RUN_GPU
U8001E

1
2

C8253
SCD1U10V2KX-4GP

1

C8252
SCD1U10V2KX-4GP

2

1

C8251
SCD1U10V2KX-4GP

2

1
2

1

C8222
SCD1U10V2KX-4GP

2

C8235
SCD1U10V2KX-4GP

+1.5V_RUN_GPU

1

Place near GPU

2
A

+1.5V_RUN_GPU

Place under GPU
A13
B13
C13
D13
D14
E13
F13
F14
F15
F16
F17
F19
F22
H23
H26
J15
J16
J18
J19

1

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

2

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

C8209
SCD1U10V2KX-4GP

5 OF 7

L19
L23
L26
M19
N22
U22
Y22

C8219
SC1U10V3KX-3GP
1st Samsung

GT218-ES-S-A1-GP

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Revised decoupling C

5

2009/05/28

Title

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

VGA-POWER/GND(3/4)

Document Number

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

82

of

88

5

4

3

2

SSID = VIDEO

1

+3.3V_RUN_GPU

Strap pin resistor need use 1% resistor (NV Design Guide)

Strap pin define

C

B

AC19
R19

16mil
1

+FB_PLLVDD

2

Place near GPU

2

1

+1.05V_GFX_PCIE

FB_CAL_PU_GND
A15
FB_CAL_PD_VDDQ
B15
FB_CAL_TERM_GND B16

T19

FB_CAL_PU_GND
FB_CAL_PD_VDDQ
FB_CAL_TERM_GND
FB_PLLAVDD
FB_PLLAVDD
FB_DLLAVDD

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

C26
B19
D19
D23
T24
AA23
AB27
T26

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

D25
A18
E18
B24
R22
Y24
AA27
R27

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

C25
A19
E19
A24
T22
AA24
AA26
T27

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

F24
F23

CLKA0
CLKA0#

FBA_CLK1
FBA_CLK1#

N24
N23

CLKA1
CLKA1#

FBA_DEBUG

M22

FB_VREF

A16

R8311
4K99R2F-L-GP
2
1

R8312
4K99R2F-L-GP

R8308
20KR2F-L-GP
2
1

R8313
10KR2F-2-GP

R8309
15KR2F-GP
1

DY
2

R8305
4K99R2F-L-GP
2
1
R8316
30KR2F-GP
1

DY

D

DY

STRAP0

[81] STRAP0

STRAP1

[81] STRAP1

STRAP2

[81] STRAP2

ROM_SCLK_GPU

[81] ROM_SCLK_GPU

ROM_SI_GPU

[81] ROM_SI_GPU

DY

DY

DY
2

Logical Strap Bit Mapping
Resistor Pull-Up Pull-Down
5Kohms
1000
0000
10Kohms 1001
0001
15Kohms 1010
0010
20Kohms 1011
0011
25Kohms 1100
0100
30Kohms 1101
0101
35Kohms 1110
0110
45Kohms 1111
0111

R8304
15KR2F-GP
2
1

ROM_SO_GPU

[81] ROM_SO_GPU

C

2009/06/05
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

[84]
[84]
[84]
[84]
[85]
[85]
[85]
[85]

Strap0
USER_BIT0
USER_BIT1
USER_BIT2
USER_BIT3

Strap1
1
1
1
1

EDID is used

FBA_CLK0
FBA_CLK0#

R8302
34K8R2F-1-GP
2
1

FBA_CMD_0 [84]
RAS# [84,85]
FBA_CMD_2 [84]
BA1 [84,85]
FBA_CMD_4 [85]
FBA_CMD_5 [85]
FBA_CMD_6 [85]
FBA_CMD_7 [85]
FBA_CMD_8 [85]
MAA11 [84,85]
CAS# [84,85]
W E# [84,85]
BA0 [84,85]
FBA_CMD_13 [85]
MAA12 [84,85]
MEM_RST [84,85]
MAA7 [84,85]
MAA10 [84,85]
FBA_CMD_18 [84]
MAA0 [84,85]
MAA9 [84,85]
MAA6 [84,85]
FBA_CMD_22 [84]
MAA8 [84,85]
FBA_CMD_24 [84]
MAA1 [84,85]
MAA13 [84,85]
BA2 [84,85]
FBA_CMD_28 [85]
FBA_CMD_29 [84]
FBA_CMD_30 [84]

R8301
10KR2F-2-GP
2
1

1

FBA_CMD_0
RAS#
FBA_CMD_2
BA1
FBA_CMD_4
FBA_CMD_5
FBA_CMD_6
FBA_CMD_7
FBA_CMD_8
MAA11
CAS#
W E#
BA0
FBA_CMD_13
MAA12
MEM_RST
MAA7
MAA10
FBA_CMD_18
MAA0
MAA9
MAA6
FBA_CMD_22
MAA8
FBA_CMD_24
MAA1
MAA13
BA2
FBA_CMD_28
FBA_CMD_29
FBA_CMD_30

2

F26
J24
F25
M23
N27
M27
K26
J25
J27
G23
G26
J23
M25
K27
G25
L24
K23
K24
G22
K25
H22
M26
H24
F27
J26
G24
G27
M24
K22
J22
L22

R8306
45K3R2F-L-GP
2
1

1 OF 7

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

[84]
[84]
[84]
[84]
[85]
[85]
[85]
[85]
[84]
[84]
[84]
[84]
[85]
[85]
[85]
[85]

CLKA0 [84]
CLKA0# [84]
CLKA1 [85]
CLKA1# [85]

nVIDIA recommend

Strap2

3GIO_PADCFG_LUT_ADR0
3GIO_PADCFG_LUT_ADR1
3GIO_PADCFG_LUT_ADR2
3GIO_PADCFG_LUT_ADR3

0
1
1
1

Reserved

PCI_DEVID_0
PCI_DEVID_1
PCI_DEVID_2
PCI_DEVID_3

1
0
1
0

N11M-GE1 GPU Device ID=0x0A75

ROM_SI_GPU

ROM_SO_GPU

RAM_CFG0
RAM_CFG1
RAM_CFG2
RAM_CFG3

VGA_DEVICE
SMB_ALT_ADDR
FB_0_BAR_SIZE
XCLK_417

ROM_SCLK_GPU
1
0
0
0

PEX_PLL_EN_TERM
SLOT_CLK_CONFIG
SUB_VENDOR
PCI_DEVID_4

0
1
0
1

Default setting: SAMSUNG sDDR3 64Mx16BIT-->20K pull down (0x0011)
If use Hynix sDDR3 64Mx16BIT(0x0010), R8308 change to 15K.
RAM_CFG[3:0] Config
0000
0001
64MX16
0010
64MX16
0011
0100
0101
0110
0111

SUB_VENDOR
0
No VBIOS ROM
1
BIOS ROM present

FB_BUS Width Definitions

€

€
€

DDR3 64Bit
DDR3 64Bit

B

Hynix
Samsung

€

€
€
€
€

Default

PEX_PLL_EN_TERM
0 Disable (POR)
1 Enable

XCLK_417
0
277MHz(POR)
1
Reserved

GT218-ES-S-A1-GP

SC1U6D3V2KX-GP
C8301

L8301

1
2
BLM18SG331TN1D-GP

1R8303
1R8314
2R8315

2
2
1

SC4D7U6D3V3KX-GP
C8302

+1.5V_RUN_GPU

40D2R2F-GP
40D2R2F-GP
60D4R2F-GP

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

1

D

D22
E24
E22
D24
D26
D27
C27
B27
A21
B21
C21
C19
C18
D18
B18
C16
E21
F21
D20
F20
D17
F18
D16
E16
A22
C24
D21
B22
C22
A25
B25
A26
U24
V24
V23
R24
T23
R23
P24
P22
AC24
AB23
AB24
W24
AA22
W23
W22
V22
AA25
W27
W26
W25
AB25
AB26
AD26
AD27
V25
R25
V26
V27
R26
T25
N25
N26

R8307
4K99R2F-L-GP
2
1

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

2

U8001A

[84,85] MDA[0..63]

3GIO_PADCFG
0000
Desktop
1110
Notebook (POR)

USER[3:0]
1111 Use EDID to detect panel settings

SLOT_CLOCK_CFG
0
GPU and MCH do not share a common reference clock
1
GPU and MCH share a common reference clock (POR)

FB_PLLAVDD+FB_DLLAVDD=100mA
1st Samsung

A

A

DW
07/10 Updated
1.+FB_PLLVDD power rail

Wistron Corporation

corrected to +1.05V_GFX_PCIE

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

VGA-MEMORY/STRAPS(4/4)

Document Number

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

83

of

88

5

4

3

2

1

SSID = VIDEO
+1.5V_RUN_GPU

+1.5V_RUN_GPU
MDA[0..63]

U8401

[83] CLKA0
[83] CLKA0#

CLKA0
CLKA0#

[83] DQMA#1
[83] DQMA#2
[83,85]
[83,85]
[83,85]

WE#
CAS#
RAS#

CK
CK#

K9

DQMA#1
DQMA#2

D3
E7

WE#
CAS#
RAS#

L3
K3
J3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA0
BA1
BA2

J7
K7

UMA
swap for layout

NC#T7
NC#L9
NC#L1
NC#J9
NC#J1

CKE
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DMU
DML
WE#
CAS#
RAS#

1

1

FBA_CMD_29
MEM_RST [83,85]

[83]

R8409
10KR2J-3-GP

R8410
10KR2J-3-GP

[83]

R8402
1KR2F-3-GP

2

FBA_CMD_30

FBA_CMD_29
MEM_RST

T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1

VREFA2

QSA2 [83]
QSA#2 [83]

2

L2
T2

QSA1 [83]
QSA#1 [83]

EC8401
SC6D8P50V2CN-GP

C8421
SCD01U16V2KX-3GP

FBA_CMD_30

1

K1

R8403
1KR2F-3-GP
2

QSA2
QSA#2

UMA
swap for layout

Added MEN_RST
10K pull down R
2009/05/28

1
R8407

CLKA0

[83,85]
[83,85]
[83,85]

BA0
BA1
BA2

[83] CLKA0
[83] CLKA0#

CLKA0#

G1
F9
E8
E2
D8
D1
B9
B1
G9

UMA
[83]
swap for layout

[83,85]
[83,85]
[83,85]

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
M2
N8
M3

CLKA0
CLKA0#

J7
K7
K9

DQMA#3
DQMA#0

WE#
CAS#
RAS#

H1
M8
L8

BA0
BA1
BA2

FBA_CMD_18

FBA_CMD_18

[83] DQMA#3
[83] DQMA#0

Revised FBCLK Termination
resistor value
2009/06/05
Close to VRAM side

2 ZQ_VRAM12
243R2F-2-GP
MAA0
MAA1
FBA_CMD_22
FBA_CMD_24
FBA_CMD_0
FBA_CMD_2
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

[83,85] MAA0
[83,85] MAA1
[83] FBA_CMD_22
[83] FBA_CMD_24
[83] FBA_CMD_0
[83] FBA_CMD_2
[83,85] MAA6
[83,85] MAA7
[83,85] MAA8
[83,85] MAA9
[83,85] MAA10
[83,85] MAA11
[83,85] MAA12
[83,85] MAA13

R8418
243R2F-2-GP

DUMMY-K4W1G1646E-HC12-GP

D3
E7

WE#
CAS#
RAS#

L3
K3
J3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSU
DQSU#

VREFDQ
VREFCA
ZQ

DQSL
DQSL#
ODT

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7

CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA0
BA1
BA2
CK
CK#
CKE

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DMU
DML
WE#
CAS#
RAS#

E3
F7
F2
F8
H3
H8
G2
H7

MDA7
MDA6
MDA3
MDA0
MDA1
MDA2
MDA5
MDA4

D7
C3
C8
C2
A7
A2
B8
A3

MDA29
MDA24
MDA30
MDA28
MDA25
MDA26
MDA31
MDA27

MDA[0..63]

[83,85]

MDA[0..63]

[83,85]
D

UMA
swap for layout

C7
B7

QSA3
QSA#3

F3
G3

QSA0
QSA#0

K1

FBA_CMD_30

L2
T2

FBA_CMD_29
MEM_RST

QSA3 [83]
QSA#3 [83]
QSA0 [83]
QSA#0 [83]
FBA_CMD_30
FBA_CMD_29
MEM_RST [83,85]

[83]

[83]

T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1

C

G1
F9
E8
E2
D8
D1
B9
B1
G9

DUMMY-K4W1G1646E-HC12-GP

64X16 SAMSUNG K4W1G1646E-HC12 P/N:72.41164.H0U
64X16 HYNIX H5TQ1G63BFR-12C
P/N:72.51G63.C0U
SC-1203-2
change U8401, U8402 to ZZ.00PAD.R01 for layout

1
2

C8429
SC1U10V3KX-3GP

1
2

C8428
SC1U10V3KX-3GP

1
2

C8427

B

Revised decoupling C

Revised decoupling C

C8413
SCD1U16V2KX-3GP

C8415
SCD1U10V2KX-4GP
2
1

C8414
SCD1U16V2KX-3GP
2
1

C8409
SCD1U16V2KX-3GP
2
1

1
2

2009/05/28

C8405
SCD1U16V2KX-3GP
2
1

C8412
SCD1U16V2KX-3GP

C8411
SCD1U16V2KX-3GP
2
1

C8410
SCD1U10V2KX-4GP
2
1

+1.5V_RUN_GPU

C8408
SCD1U16V2KX-3GP
2
1

1
2

C8404
SCD1U10V2KX-4GP
2
1

+1.5V_RUN_GPU

C8426

Place under / near VRAM

SC1U10V3KX-3GP

1

C8425

2

C8424

SC1U10V3KX-3GP

1

C8423

2

1
2

+1.5V_RUN_GPU

Place under / near VRAM

SC1U10V3KX-3GP

2
B

C8422
SC1U10V3KX-3GP

1

+1.5V_RUN_GPU

1

1

M2
N8
M3

CS#
RESET#

2

Added CKE
10K pull down R
2009/06/05

FBA_CMD_18

EC8402
2
SC6D8P50V2CN-GP

10KR2J-3-GP
R8411
2

[83] FBA_CMD_18

1

C

BA0
BA1
BA2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7

F3
G3

A8
A1
C1
C9
D2
E9
F1
H9
H2

+1.5V_RUN_GPU

1

BA0
BA1
BA2

ODT

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

QSA1
QSA#1

[83,85]

2

[83,85]
[83,85]
[83,85]

DQSL
DQSL#

C7
B7

MDA[0..63]

1

MAA0
MAA1
FBA_CMD_22
FBA_CMD_24
FBA_CMD_0
FBA_CMD_2
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

[83,85] MAA0
[83,85] MAA1
[83] FBA_CMD_22
[83] FBA_CMD_24
[83] FBA_CMD_0
[83] FBA_CMD_2
[83,85] MAA6
[83,85] MAA7
[83,85] MAA8
[83,85] MAA9
[83,85] MAA10
[83,85] MAA11
[83,85] MAA12
[83,85] MAA13

VREFDQ
VREFCA
ZQ

MDA13
MDA14
MDA9
MDA8
MDA12
MDA11
MDA15
MDA10

SC1U10V3KX-3GP

1
2
2

R8406

2 ZQ_VRAM11
243R2F-2-GP

DQSU
DQSU#

SC1U10V3KX-3GP

C8420
SCD01U16V2KX-3GP

1
R8401
1KR2F-3-GP

1

H1
M8
L8

D7
C3
C8
C2
A7
A2
B8
A3

U8402
K8
K2
N1
R9
B2
D9
G7
R1
N9

1

VREFA1

MDA17
MDA18
MDA19
MDA22
MDA20
MDA21
MDA16
MDA23

2

1
2

R8404
1KR2F-3-GP

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

E3
F7
F2
F8
H3
H8
G2
H7

2

A8
A1
C1
C9
D2
E9
F1
H9
H2

+1.5V_RUN_GPU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

1

D

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

2

K8
K2
N1
R9
B2
D9
G7
R1
N9

[83,85]

2009/05/28

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

VRAM(1/2)
5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A2
Date:

Document Number

Rev

A00

Winery13 MB DIS
Wednesday, January 13, 2010
1

Sheet

84

of

88

5

4

3

2

1

SSID = VIDEO
+1.5V_RUN_GPU
MDA[0..63]

U8501

+1.5V_RUN_GPU

[83,84]

U8502

[83,84]
[83,84]
[83,84]

BA0
BA1
BA2

[83] CLKA1
[83] CLKA1#

C

J7
K7

FBA_CMD_7

K9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA0
BA1
BA2
CK
CK#
CKE

1

[83] DQMA#6
[83] DQMA#5

DQMA#6
DQMA#5

D3
E7

DMU
DML

SC6D8P50V2CN-GP
[83,84]
[83,84]
[83,84]

WE#
CAS#
RAS#

WE#
CAS#
RAS#

L3
K3
J3

WE#
CAS#
RAS#

1
2

VREFA4
1

QSA5 [83]
QSA#5 [83]
FBA_CMD_28

FBA_CMD_8
MEM_RST

L2
T2

FBA_CMD_8 [83]
MEM_RST [83,84]
R8506
10KR2J-3-GP

T7
L9
L1
J9
J1

Added CKE
10K pull down R
2009/06/05

[83]
R8504
1KR2F-3-GP

EC8502

J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1

1
R8503
[83,84] MAA0
[83,84] MAA1
[83] FBA_CMD_4
[83] FBA_CMD_6
[83] FBA_CMD_5
[83] FBA_CMD_13
[83,84] MAA6
[83,84] MAA7
[83,84] MAA8
[83,84] MAA9
[83,84] MAA10
[83,84] MAA11
[83,84] MAA12
[83,84] MAA13

SC6D8P50V2CN-GP

2 ZQ_VRAM22
243R2F-2-GP

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

BA0
BA1
BA2

M2
N8
M3

CLKA1
CLKA1#

J7
K7

FBA_CMD_7

K9

DQMA#4
DQMA#7

D3
E7

WE#
CAS#
RAS#

L3
K3
J3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

H1
M8
L8

MAA0
MAA1
FBA_CMD_4
FBA_CMD_6
FBA_CMD_5
FBA_CMD_13
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQSU
DQSU#

VREFDQ
VREFCA
ZQ

DQSL
DQSL#
ODT

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7

CS#
RESET#

[83,84]
[83,84]
[83,84]

R8517
243R2F-2-GP

CLKA1#
G1
F9
E8
E2
D8
D1
B9
B1
G9

BA0
BA1
BA2

[83] CLKA1
[83] CLKA1#
[83] FBA_CMD_7
[83] DQMA#4
[83] DQMA#7

Revised FBCLK Termination
resistor value
2009/06/05

[83,84]
[83,84]
[83,84]

Close to VRAM side

WE#
CAS#
RAS#

CK
CK#
CKE

WE#
CAS#
RAS#

D7
C3
C8
C2
A7
A2
B8
A3

MDA36
MDA38
MDA33
MDA39
MDA34
MDA37
MDA32
MDA35

C7
B7

QSA4
QSA#4

F3
G3

QSA7
QSA#7

K1

FBA_CMD_28

L2
T2

FBA_CMD_8
MEM_RST

MDA[0..63]

[83,84]

MDA[0..63]

[83,84]

D

QSA4 [83]
QSA#4 [83]
QSA7 [83]
QSA#7 [83]
FBA_CMD_28

[83]

FBA_CMD_8 [83]
MEM_RST [83,84]

C

G1
F9
E8
E2
D8
D1
B9
B1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DMU
DML

MDA63
MDA59
MDA60
MDA61
MDA57
MDA58
MDA62
MDA56

J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA0
BA1
BA2

E3
F7
F2
F8
H3
H8
G2
H7

T7
L9
L1
J9
J1

NC#T7
NC#L9
NC#L1
NC#J9
NC#J1

CLKA1

DUMMY-K4W1G1646E-HC12-GP

DUMMY-K4W1G1646E-HC12-GP

SC-1203-2
change U8501, U8502 to ZZ.00PAD.R01 for layout

+1.5V_RUN_GPU

1
2

2

C8538
SC1U10V3KX-3GP

1

C8537
SC1U10V3KX-3GP

1

C8536

2

C8535

Place under / near VRAM

SC1U10V3KX-3GP

1

C8534

2

C8533

+1.5V_RUN_GPU

SC1U10V3KX-3GP

1

C8532

2

1
2

Place under / near VRAM

SC1U10V3KX-3GP

2
B

C8531
SC1U10V3KX-3GP

1

+1.5V_RUN_GPU

1

2

2

EC8501

R8501
1KR2F-3-GP

QSA6 [83]
QSA#6 [83]

FBA_CMD_28

K1

2

R8508
10KR2J-3-GP

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

QSA5
QSA#5

C8506
SCD01U16V2KX-3GP

CLKA1
CLKA1#

NC#T7
NC#L9
NC#L1
NC#J9
NC#J1

QSA6
QSA#6

1

M2
N8
M3

CS#
RESET#

C7
B7
F3
G3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A8
A1
C1
C9
D2
E9
F1
H9
H2

+1.5V_RUN_GPU

2

BA0
BA1
BA2

ODT
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7

[83,84]

2

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

1

[83] FBA_CMD_7

MAA0
MAA1
FBA_CMD_4
FBA_CMD_6
FBA_CMD_5
FBA_CMD_13
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

MDA[0..63]

1

[83,84] MAA0
[83,84] MAA1
[83] FBA_CMD_4
[83] FBA_CMD_6
[83] FBA_CMD_5
[83] FBA_CMD_13
[83,84] MAA6
[83,84] MAA7
[83,84] MAA8
[83,84] MAA9
[83,84] MAA10
[83,84] MAA11
[83,84] MAA12
[83,84] MAA13

DQSL
DQSL#

MDA51
MDA52
MDA54
MDA49
MDA48
MDA50
MDA55
MDA53

SC1U10V3KX-3GP

1
2
2

R8509

2 ZQ_VRAM21
243R2F-2-GP

DQSU
DQSU#

VREFDQ
VREFCA
ZQ

SC1U10V3KX-3GP

C8503
SCD01U16V2KX-3GP

1
R8507
1KR2F-3-GP

1

H1
M8
L8

D7
C3
C8
C2
A7
A2
B8
A3

K8
K2
N1
R9
B2
D9
G7
R1
N9

2

VREFA3

MDA46
MDA42
MDA43
MDA40
MDA45
MDA41
MDA47
MDA44

1

1
2

R8510
1KR2F-3-GP

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

E3
F7
F2
F8
H3
H8
G2
H7

1

A8
A1
C1
C9
D2
E9
F1
H9
H2

+1.5V_RUN_GPU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2

D

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

2

K8
K2
N1
R9
B2
D9
G7
R1
N9

B

+1.5V_RUN_GPU

Revised decoupling C

Revised decoupling C

C8521
SCD1U16V2KX-3GP

C8522
SCD1U16V2KX-3GP
2
1

C8523
SCD1U16V2KX-3GP
2
1

C8524
SCD1U16V2KX-3GP
2
1

1
2

2009/05/28

C8525
SCD1U16V2KX-3GP
2
1

1
2

EC8503
SCD1U16V2KX-3GP

C8516
SCD1U10V2KX-4GP

C8517
SCD1U16V2KX-3GP
2
1

C8518
SCD1U16V2KX-3GP
2
1

C8519
SCD1U10V2KX-4GP
2
1

1
2

C8520
SCD1U16V2KX-3GP
2
1

+1.5V_RUN_GPU

2009/05/28

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

VRAM
5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A2
Date:

Document Number

Rev

A00

Winery13 MB DIS
Wednesday, January 13, 2010
1

Sheet

85

of

88

5

4

3

2

1

SSID = PWR.Plane.Regulator_GFX
Vout=0.704V*(R1+R2)/R2
+PWR_SRC

+PWR_SRC_GFX_CORE_

D

D

PG8617
2

1
2

DY

PC8603
SC2200P50V2KX-2GP

1
2

PC8604
SCD1U50V3KX-GP

1
2

2

SC10U25V6KX-1GP
PC8609

PU8601
SI7686DP-T1-GP

DIS
Thermal Design Current
Max Current = 16.77A
18.45A350KHz

GAP-CLOSE-PWR
PG8602
1
2

2009/08/05

PC8608
2
1

2
[81] PWRCNTL_1

PQ8602
2N7002A-7-GP

S

2009/08/05

DY

DY

DY

SCD1U16V2KX-3GP

0.85V

DY

PR8602
100KR2J-1-GP

L

PC8610
2
1

H

PR8620
10KR2F-2-GP

G
SCD1U16V2KX-3GP
1
2

1.03V

2009/08/26

D
2

+VCC_GFX_CORE

H

10KR2F-2-GP

2

PWRCNTL_1

H

1

+3.3V_RUN_GPU

PR8618
1 PWRCNTL_0_R

DY

B

GAP-CLOSE-PWR
PG8608
1
2

PWRCNTL_1#

2

[81] PWRCNTL_0

PWRCNTL_0

2

2

PD8601_A 1

A

DY

PWRCNTL_0#

K

B0530WS-7-F-GP

PR8619
10KR2F-2-GP

PR8607
20KR2F-L-GP

2

PR8611
24K3R2F-1-GP

+3.3V_RUN_GPU

GAP-CLOSE-PWR
PG8606
1
2

1

1

1

DYPR8613
75KR2F-GP
PD8601

C

GAP-CLOSE-PWR
PG8618
2
1

+GFX_CORE_FB

B

GAP-CLOSE-PWR
PG8619
2
1

2

Frequency setting
470K -->290KHz
200K -->340KHz
100K -->380KHz
39K -->430KHz

PC8602
SCD1U10V2KX-4GP

1

PR8606
2D2R5F-2-GP

2

PU8604

DY

A

PG8604
GAP-CLOSE-PWR-3-GP

1+GFX_CORE_LL_R
2

DY

5
6
7
8

TPS51218DSCR-GP-U1

PC8617
SC1U10V2KX-1GP

+VCC_GFX_CORE
PG8601
2
1

1
2
IND-1D5UH-34-GP

1

+5V_ALW
+GFX_CORE_DRVL

D
D
D
D

2

+VCC_GFX_COREP

1

SIR460DP-T1-GE3-GP

100KR2J-1-GP

PR8604
470KR2F-GP

2 +GFX_CORE_VBST12

4
3
2
1

2

DY

1

PR8638 1

1

PM_SLP_S3#

+GFX_CORE_VBST 1
+GFX_CORE_DRVH
+GFX_CORE_SW

PC8616
SCD1U25V3KX-GP

SE330U2VDM-L-GP

[22,34,37,42,50,51]

2

11
10
9
8
7
6

SE330U2VDM-L-GP

C

PR8631 1
1KR2F-3-GP

PR8633
2D2R3J-2-GP
GND
VBST
DRVH
SW
V5IN
DRVL

SC1KP50V2KX-1GP
PC8634
2

[37] GFX_CORE_EN

PGOOD
TRIP
EN
VFB
CCM

1

+GFX_CORE_TRIP
+GFX_CORE_EN
+GFX_CORE_FB
+GFX_CORE_CCM

1
2
73K2R2F-GP

1
2
3
4
5

1 GPU_VDD_SENS_GAP

PU8603

PR8632

2

SB-1103

GAP-CLOSE-PWR

= 12.9A

4
3
2
1

[25] GFX_CORE_PGOOD

GAP-CLOSE-PWR
PG8616
1
2
1st Samsung
GAP-CLOSE-PWR

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

SC-1204-5
add PR8621 pull low 10K R

Title

TPS51218 +VCC_GFX_CORE

Size
Document Number
Custom

Rev

Winery13 MB DIS

Date: Wednesday, January 13, 2010
5

4

3

2

http://laptop-motherboard-schematic.blogspot.com/

Sheet
1

A00
86

of

88

5

4

3

2

1

D

D

+3.3V_RTC_LDO

+3.3V_RUN_GPU

+15V_ALW
2

SSID = VIDEO

1

2

R8714
100KR2J-1-GP

+3.3V_RUN_GPU

Peak current:360mA
Design current: 252mA

R8711
100KR2J-1-GP

RUN_ON_3D3GFX_R

3

2

1

K
2

1ST: 84.03434.031
2ND:

1

D

G

AO3434L-GP MAX 4.2A
Rds(on) = 52 mOhm (Max)

3.3V_GPU_EN_R

+3.3V_RTC_LDO

C

+15V_ALW
2

+1.05V_GFX_PCIE:

S

2

C8708
SCD01U50V2KX-1GP

1
C

R8713
10KR2J-3-GP
RUN_ON_3D3GFX
1

2

C8786
SC1U6D3V2KX-GP

+3.3V_ALW

Q8710
AO3434L-GP

BAS16XV2T1G-GP-U
R8778
2KR2F-3-GP
2
1

[37] 3.3V_RUN_GPU_EN

2

4

C8704
SC10U6D3V5KX-1GP

Q8707
DMN66D0LDW-7-GP

D8706
A

5

6

1

1

3D3V_VGA_ON#

2

+1.05V_GFX_PCIE
R8708
100KR2J-1-GP

1D05V_VGA_ON#

Peak current: 3550mA
Design current:3550mA

Q8704
DMN66D0LDW-7-GP

1
2
3
4

C8705
SCD01U50V2KX-1GP

D
D
D
D

8
7
6
5

FDS8880-NL-GP

1

Added discharge circuit
2009/06/17

U8703
S
S
S
G

10.7A
Rds=12m ohm

1ST: 84.08880.037
2ND: 84.04406.B37

2

3

2

1

R8716
RUN_ON_1D05V
2 10KR2J-3-GP
1

RUN_ON_1D05V_R

assign GPIO
2009/05/28

+1.5V_RUN_GPU

1.05V_GFX_ON

2

[37] 1.05V_GFX_ON

+1.05V_VTT

2

C8701
SC10U6D3V5KX-1GP

4

5

6

1

1

1

R8712
100KR2J-1-GP

R8709

+3.3V_RTC_LDO

1

rail and Q8701 Drain

Q87_D

G

DY

4

5

6

S

1

1D5V_VGA_ON#

Q8705
DMN66D0LDW-7-GP

Q8701
2N7002-7F-GP

Peak current:4230mA
Design current:2961mA

1

R8710
100KR2J-1-GP

1D5V_VGA_ON#

B

+1.5V_RUN_GPU

C8702
SC10U6D3V5KX-1GP

+1.5V_SUS

2

2

R8715
100KR2J-1-GP

D

B

1

Place near device side(VGA chip),

DY 100R2J-2-GPuse 10 mil trace between power
+15V_ALW

2

+1.5V_RUN_GPU:

RUN_ON_1D5V

C8707
SCD01U50V2KX-1GP

U8705
S
S
S
G

D
D
D
D

8
7
6
5

FDS8880-NL-GP

10.7A
Rds=12m ohm

1ST: 84.08880.037
2ND: 84.04406.B37

2

1

3

2

1

R8717
2 10KR2J-3-GP
1

RUN_ON_1D5V_R

1
2
3
4

1D5V_VGA_ON

[37] 1D5V_VGA_ON

A

A

1st Samsung

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

http://laptop-motherboard-schematic.blogspot.com/
5

4

3

2

LDO 1.8V

Size
Document Number
Custom

Rev

Winery13 MB DIS

Date:

Wednesday, January 13, 2010

Sheet
1

A00
87

of

88

5

Item

D

C

Page#

4

Date

Request By

3

Issue description

01
02
03
04

66
60
66
49

2009/10/08
2009/10/08
2009/10/08
2009/10/08

EE
EE
EE
EE

HDD LED light in S5.
External MIC NG.
Correct battery LED color.
Improve VTT_PWRGD ramp up signal.

05

51

2009/10/08

EE

Fine tune +1.8V_RUN power on sequence behind +3.3V_RUN.

2009/10/08

EE

30
64

2009/10/08
2009/10/08

37
79
79
78
27
27
27
24
81
26
26
37
79

06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23

54,78

2

1

Solution Description

Rev.
SB
SB
SB
SB

For KBC ESD protect.

Change HDD LED power rail from +5V_ALW to +5V_RUN.
Add caps C6014 C6015.
Swap LED6601 pin2 & pin3.
Dummy C4912.
Change PR5102 from 2.2K to 3K and
PC5105 from 4700pF to 1uF.
Add 100 ohm resistances R5413, R7803.

EE
EE

By ME request

Change CODEC to 92HD79.
Change WLAN1 to 62.10043.841.

SB
SB

2009/10/09
2009/10/12
2009/10/12
2009/10/12
2009/10/12
2009/10/12
2009/10/12
2009/10/12
2009/10/12
2009/10/13
2009/10/13
2009/10/13
2009/10/13

EE
ME
ME
ME
EE
EE
EE
EE
EE
EE
EE
EE
ME

Change board ID.
By ME request
By ME request
By ME request
Follow Intel spec
Follow Intel spec
Cost down
XTAL Load Capacitance as Vendor suggestion
XTAL Load Capacitance as Vendor suggestion
Follow Intel spec
Follow Intel spec
Modify 10mW schematic
By ME request

Dummy R3708 and pop R3701.
Change H6 to ZZ.00PAD.F91
Change H10 to ZZ.00PAD.D41
Change FP1 to 20.K0315.005
Remove L2701, C2701, C2702; Add TP2701
Remove L2704, C2721, C2722; Add TP2702
Change L2702, L2703 to 68.10050.10Y
Change C2402, C2403 to 12pF
Change C8135, C8138 to 15pF
Remove L2602, C2616; Add TP2601
Remove L2601, C2606; Add TP2602

SB
SB
SB
SB
SB
SB
SB
SB
SB
SB
SB
SB
SB

24

49

2009/10/13

EE

By PSE request

25
26
27
28
29
30
31

73
34
79
64
79
80,81
22

2009/10/13
2009/10/14
2009/10/14
2009/10/14
2009/10/16
2009/10/16
2009/10/16

EE
ME
ME
EE
EE
EE
EE

Two AFTP for +3.3V_RUN
By ME request
By ME request
By AFTE request
By RF request
Voltage Drop over 3%
RTC data loss

32
33
34

25
78
37

2009/10/16
2009/10/16
2009/10/16

EE
EE
EE

B

By SW request

SB

D

SB

Remove H9 (BT BOSS)
Change pg4910~pg4918 and pg4921
close gap to mask type
Remove AFTP6030
change NEW1 connector to 20.K0370.026
change SPR5 to 34.4F822.002
Add AFTP6402, AFTP6403
Add Cross Moat Caps
change bead value to 120 ohm DCR 0.55 ohm
Added 3v/5v S5 power good to control resume reset
sequence prevent RTC data loss
Swapped Q2515 C,E Pin
remove CAPA_RST# from capacity board
Added Switch Baord Detection circuit

C

SB
SB
SB
SB
SB
SB
SB
SB
B

SB
SB
SB

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

Document Number

Change List(1/3)

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

88

of

88

5

Item

D

C

Page#

4

Date

Request By

3

2

1

Issue description

Solution Description

EE
EE
EMI

Correct R3745 power rail to KBC_PWR
TPM connector needn't AFTE test point
No support HDMI and eDP so needn't pop 25MHz Xtal of PCH.
Toggle VGA mode will flicker white screen in hybrid mode.
Toggle VGA mode will flicker white screen in hybrid mode.
For solve WiMAX noise
For solve WiMAX noise
For solve WiMAX noise
For combine material item
For one hand hold issue, ODD have noise
For solve WWAN noise
For solve WiMAX noise
By EMI requirement
By EMI requirement
By EMI requirement
For cosmatic issue when insert 8 cell battery
For cosmatic issue when insert 8 cell battery
Base on Application Note: IDT 92H81/79 AUX Mode as input
of Diagnostic sound.
Set PWRCNTL_1 for default low.
By EMI requirement

EMI
EMI
EMI
EMI
ME
EE
EE
EE
EE
EE
EMI

By EMI requirement
By EMI requirement
By EMI requirement
By EMI requirement
For cosmatic issue when insert 8 cell battery
Base on EA teset result, change to 0 ohm.
Base on ARD_Sightings_Report_18 #3622146
Audio AP LO THD+N fail
Base on EA teset result, change to 0 ohm.
Change PCB Footprint
By EMI requirement

Change R3745 power rail to KBC_PWR
Remove TPM1 AFTP
C2313 pop 0 ohm if no use 25MHz XTAL
Add U3703 mux for panel backlight enable signal select
Add mux U5446 to select LCDVDD enable signal
Change C701 to 4.7pF for RF
Pop PC4303 for RF
Change PC4601 pull up to +5V_ALW for layout.
Change PC4762 to 0603 size
Add H15 for ME
Add RC7931 for RF
Add SPR6 for RF
Change L5501,L5502,L5503 for EMI
Add EMI caps
Add EC8101,EC8102,EC8103 for EMI
Remove TC4701 for layout
Change H2 to ZZ.00PAD.D11
Connect U3001 pin17, pin18 to pin12 net and change
R3016 to 120K for vendor request
Add PR8621 pull low 10K ohm
Pop C1243 and change size to 0603 for EMI
Pop C3301, EC3302, EC3303, EC3305, EC3306, EC3307,
EC3308 and change from 100p to 6.8p for EMI
Pop EC5403 for EMI
Pop EC6001 and EC6002 for EMI
Pop R6307 for EMI
Add H16 for ME
Change R2413,R2414,R2415 from 15ohm to 0 ohm
Change PR5311 from 4.7K to 470 ohm
Change EC6004,EC6005 from 0.1U to 0.01U
Change R6206 from 15ohm to 0 ohm
Change Q6808 to 84.06402.B3D
Pop L7301 for EMI

01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17

37
36
23
37
54
7
43
46
47
79
79
79
55
79
81
47
79

2009/11/18
2009/11/25
2009/11/25
2009/11/25
2009/11/25
2009/11/30
2009/11/30
2009/11/30
2009/11/30
2009/11/30
2009/11/30
2009/11/30
2009/12/04
2009/12/04
2009/12/04
2009/12/04
2009/12/04

EE
EE
EE
EE
EE
RF
RF
RF
EE
ME
RF
RF
EMI
EMI
EMI
ME
ME

18
19
20

30
86
12

2009/12/04
2009/12/04
2009/12/07

21
22
23
24
25
26
27
28
29
30
31

33
54
60
63
79
24
53
60
62
68
73

2009/12/07
2009/12/07
2009/12/07
2009/12/07
2009/12/07
2009/12/08
2009/12/08
2009/12/08
2009/12/08
2009/12/08
2009/12/08

Rev.
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC

D

C

SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC

B

B

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

Change List(2/3)

Document Number

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

88

of

88

5

Item

D

01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18

Page#

4

Date
2010/01/07
2010/01/05
2009/12/18
2009/12/18
2010/01/07
2009/12/23
2009/12/18
2009/12/18
2009/12/18
2009/12/18
2010/01/04
2010/01/04
2010/01/06
2010/01/07
2010/01/07
2009/12/23
2009/12/23
2010/01/05

34
37
46
46
51
52
53
55
55
55
55
62
63
64
73
78
78
79

Request By
EE
EE
EE
EE
EE
EE
EE
EMI
EMI
EMI
ME
ME
EE
EE
EE
EE
EE
ME

3

2

Issue description
For no co-lay after XB
Prevent SPI ROM data lost
By POWER requirement
TO improve +15V_Pump Power on issue
To prevent PM_SLP_S3# signal rebound
PREVNET MOS DEMAGE
By POWER requirement
By EMI requirement
By EMI requirement
By EMI requirement
By ME requirement
By ME requirement
For no co-lay after XB
For no co-lay after XB
For no co-lay after XB
TO PREVENT power pin short to GND when plug in cable
add damping resister R7804
By ME requirement

1

Solution Description

Rev.
A00
A00
A00
A00
A00
A00
A00
A00
A00
A00
A00
A00
A00
A00
A00
A00
A00
A00

remove R3402, R3403
Add reset IC U3704
changePL4602 from 2.2U to 3.3U
pop PR4619; dummy PR4618
change R5102 to short pad, PC5105 to 10K
Change C701 to 4.7pF for RF
change PR5314 from 5.9K to 6.2K
change L5501, L5502, L5503 to 0R
change R5504, R5505, R5506 from 0R to 33R
change C5520 from 22p to 10p
change CRT1 from 20.20431.015 to 20.20401.015
change RCT1 from 20.D0210.102 to 20.D0075.102
remove R6302, R6308,TR6301,TR6302, TR6303
remove L6401
remove R7302, R7303
dummy FP1 pin6, pin7
add R7804
change SPR5 from 34.4F822.002 to 34.42T14.002

D

C

C

B

B

1st Samsung

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

5

http://laptop-motherboard-schematic.blogspot.com/
4

3

2

Size
A3
Date:

Change List(3/3)

Document Number

Rev

A00

Winery13 MB DIS
W ednesday, January 13, 2010

Sheet
1

88

of

88



---

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Create Date                     : 2012:08:02 08:44:02-06:00

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