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User Manual: Motherboard Wistron 2012 S-Series Richie - Schematics. Free.

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Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
Cover Page
A4
1 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
Cover Page
A4
1 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
Cover Page
A4
1 103Wednesday, March 14, 2012
<Core Design>
DY:No stuff
DIS_PX:Only DIS install
2012 S-Series Richie 13.3"
REV:-1
2012-03-15
Intel Chief River Platform
Panther Point PCH
Ivy Bridge (rPGA989)
UMA/DIS Muxless Schematic
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Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
Block Diagram
A3
2 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
Block Diagram
A3
2 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
Block Diagram
A3
2 103Wednesday, March 14, 2012
<Core Design>
PCB LAYER
L1:Top
L2:GND
L3:Signal
L4:Signal
VCC_GFXCORE
ISL95832HRTZ
TPS51461RGER
INPUTS
+VCCSA
OUTPUTS
SYSTEM DC/DC
DCBATOUT
48
L5:Vcc
L6:Signal
L7:GND
L8:Bottom
42~44
45
41
46
25
92
40
FDMC7696
INPUTS OUTPUTS
1D5V_S3 1V_VGA_S0
INPUTS
VGA
DCBATOUT
OUTPUTS
26
UP1527QQDD
VGA_CORE
0D75V_S0
3D3V_AUX_S5
ISL95832HRTZ
1D5V_S3
INPUTS
VCC_CORE
OUTPUTS
SYSTEM DC/DC
TPS51216RUKR
DDR_VREF_S3
OUTPUTS
CPU DC/DC
DCBATOUT
1D5V_S3
INPUTS
TPS51123RGER
DCBATOUT 5V_S5
OUTPUTS
3D3V_S5
TPS51211DSCR
OUTPUTS
SYSTEM DC/DC
INPUTS
DCBATOUT
INPUTS
SYSTEM DC/DC
DCBATOUT
1D5V_S0
OUTPUTS
OUTPUTS
GFX DC/DC
INPUTS
BQ24736RGRR
INPUTS
CHARGER
DCBATOUT
AD+
5V_AUX_S5
SYSTEM DC/DC
Switches
INPUTS OUTPUTS
47
93
INPUTS
SYSTEM DC/DC
5V_S0
OUTPUTS
26
5V_S5
RT8068AZQWID
3D3V_S5
3D3V_S03D3V_S5
1D8V_S0
DCBATOUT
S-Series Richie Block Diagram
42~44
BT+
(Muxless)
Accelerometer
CRT
HDMI 1.4
RGB CRT
LVDS
HDMI
PCIE ports (8)
L2:
L3:
L4:
L5:
L6:
L7:
L8:
Signal
Signal
GND
SMSC KBC1126
DMI2.0*4
5GT/s
PCH
Panther Point-M
Speaker
RJ45 CONN
SD/MMC/MS
PCIE
KBC
Intel CPU
Int.
KB
Ivy Bridge-M
Dual Core SV
35W
LAN
Realtek 8151FH
JMB709
JMicron
LPC Bus
SATA II 6Gb/s
HD Audio
Serial Peripheral I/F(dual output)
SPI Flash
8MB
PCIe
802.11abg/n
Mini-Card
USB2.0
ODD
HDD
Touch
Pad
SMBus
INT MIC
Headphone
WLAN
AUDIO CODEC
Slot 0DDR III
1600/1333
Slot 1
DDRIII 1600/1333 Channel A
DDRIII 1600/1333 Channel B
DDR III
1600/1333
IDT92HD87
GMT G781
Thermal Sensor
(10/100/1000Mb)
USB 3.0/2.0/1.1 ports (14)
ETHERNET
High Definition Audio
SATA ports (6)
ACPI 1.1
LPC I/F
INTEL
SATA II 6Gb/s
10/100/1000
Battery
PCB 8 LAYER
VCC
Signal
Top
GND
L1:
Bottom
SMBus
PCIE
FDI*2
2.7GT/s
HP3DC2
Pre-AMP
TLV2462
EXT MIC
SPI/PECI
18W
Thames Pro
PCIe x 16
VRAM
4
128MBx16 128MBx16
GDDR5
VRAM
4
GDDR5
LCD
Blue Tooth
4,5,6,7,8,9,10
17,18,19,20,21,22,23,24,25 27
56
56
83,84,85,86,87
88 89
14
15
50
51
49
3233
3435
29
65
69
6939
60
53
28
30
31
31
31
31
1D05V_S0
64
61
49
62 USB3.0
USB3.0 x 3
USB2.0 x 1
FingerPrinter
CAMERA
USB 2.0
RGB CRT
54
54
SIM Card WWAN
Mini-Card
S3 Package
SPI
Project code:91.4RS01.001
PCB P/N:11241
X1701
X1801
32.768KHz
25MHz
X3401
25MHz
26
XDP
X8501
27MHz
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Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
Table of Content
Custom
3 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
Table of Content
Custom
3 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
Table of Content
Custom
3 103Wednesday, March 14, 2012
<Core Design>
PCIe Routing
LANE2
LANE3 Card Reader
LANE4
Processor Strapping
Chief River Schematic Checklist Rev0.72
PCH Strapping
Voltage Rails
VOLTAGE DESCRIPTION
ACTIVE IN
POWER PLANE
CPU Core Rail
Graphics Core Rail
AC Brick Mode only
Powered by Li Coin Cell in G3
and 3D3V_S5 in Sx
3.3V
DSW, Sx ON for supporting Deep Sleep states
S0
S3
All S states
G3, Sx
5V_S0
3D3V_S0
1D8V_S0
1D5V_S0
1D05V_S0
VCCSA
0D75V_S0
VCC_CORE
VCC_GFXCORE
VGA_CORE
1D8V_VGA_S0
3D3V_VGA_S0
1D5V_VGA_S0
1V_VGA_S0
5V
3.3V
1.8V
1.5V
1.05V
1.0V
0.9 - 0.675V
0.75V
0.35V to 1.5V
0.4 to 1.25V
1.8V
3.3V
1V
5V
1.5V
1D5V_S3
DDR_VREF_S3
BT+
DCBATOUT
5V_S5
5V_AUX_S5
3D3V_S5
3D3V_AUX_S5
9V-14.1V
9V-19.5V
5V
5V
3.3V
3.3V
3D3V_AUX_S5
PCH_SML1CLK/PCH_SML1DATA
Device
I C / SMBus Addresses
2
SMBus ADDRESSES
Chief River CRV
Address Hex Bus
Ref Des
LANE1
LANE5
LANE6
LANE7
LANE8
LAN
X
X
Mini Card1(WLAN)
SATA Table
Pair
SATA
Device
0
5
4
3
2
1
HDD
N/A
ODD
N/A
X
Chief River Schematic Checklist Rev0.72
3D3V_AUX_KBC 3.3V
G-Sensor
USB 2.0 Table
13
12
10
0
11
Pair
4
5
2
3
1
Device
6
7
8
9
N/A
N/A
FREE
BT WLAN combo
FREE
WWAN
Camera
Fingerprint
FREE
FREE
FREE
FREE
USB 2.0 I/O CONN. 1
X
X
Pair Device
1
2
3
4
USB
USB3.0 Table
I/O CONN. 1
I/O CONN. 2
FREE
I/O CONN. 3
USB 3.0 I/O CONN. 2
USB 3.0 I/O CONN. 1
USB 3.0 I/O CONN. 3
DIMM1
DIMM2
PCH_SMB_CLK/PCH_SMB_DATA
PCH_SMB_CLK/PCH_SMB_DATA
KBC
G781_Thermal IC
GPU_Thames PRO
PCH_SML1CLK/PCH_SML1DATA
PCH_SML1CLK/PCH_SML1DATA
PCH_SMB_CLK/PCH_SMB_DATATouch-Pad
PCH_SML0_CLK/PCH_SML0_DATAN/A
0X52 PCH_SML1CLK/PCH_SML1DATA
DSWVRMEN Deep S4/S5 Well On-Die Voltage Regulator Enable
If strap is sampled high, the Integrated Deep S4/S5 Well (DSW) On-Die VR mode is enabled.
SDVO_CTRLDATA Port B Detected
When '1'- Port B is detected; When '0'- Port B is not detected. This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after PLTRST# deasserts.
This signal is a strap for selecting DMI and FDI termination voltage.
For Ivy Bridge processor only implementation:
DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms ±5% resistor.
For future processor compatibility:
It needs to be connected to PROC_SELECT through a
1.0 kOhms ±5% series resistor. The PROC_SELECT signal would need a 2.2 kOhms ±5% pull-up resistor to PCH VccDFTERM.
GPIO28 The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is
disabled. If not used, 8.2-k to 10-k pull-up to +V3.3A power-rail.
Note: This signal has a weak internal pull-up. The internal pull-up is disabled after RSMRST# deasserts.
DDPC_CTRLDATA Port C Detected.
When '1'- Port C is detected; When '0'- Port C is not detected This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after PLTRST# deasserts
SPKR
Name Schematics Notes
SATA3GP/
GPIO37
HDA_DOCK_EN#
/GPIO33
HDA_SDO
INIT3_3V# This signal has a weak internal pull-up.
Note: The internal pull-up is disabled after PLTRST# deasserts.
NOTE: This signal should not be pulled low. Leave as "No Connect".
GNT3#/GPIO55
GNT2#/GPIO53
GNT1#/GPIO51
High Definition Audio Dock Enable: This signal controls the external Intel HD Audio docking isolation logic. This is an
active-low-signal. When deasserted the external docking switch is in isolate mode. When asserted the external docking switch
electrically connects the Intel? HD Audio dock signals to the corresponding Cougar Point signals. This signal can instead be
used as GPIO33.
DF_TVS
The signal has a weak internal pull-down.
Note: the internal pull-down is disabled after PLTRST# deasserts. If the signal is sampled high, this indicates that the system is
strapped to the "No Reboot" mode (Cougar Point will disable the TCO Timer system reboot feature).
SATA2GP/
GPIO36
Reserved.
This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after PLTRST# deasserts.
NOTE: This signal should not be pulled high when strap is sampled.
Reserved
This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after PLTRST# deasserts.
NOTE: This signal should not be pulled high when strap is sampled.
L_DDC_DATA LVDS Detected.
When '1'- LVDS is detected; When '0'- LVDS is not detected. This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after PLTRST# deasserts.
SATA1GP/
GPIO19
This Signal has a weak internal pull-up.
Note: the internal pull-up is disabled after PLTRST# deasserts. This field determines the destination of accesses to the BIOS
memory range. Also controllable via Boot BIOS Destination bit (Chipset Config Registers: Offset 3410h:Bit 10). This strap is used
in conjunction with Boot BIOS Destination Selection 1 strap.
Bit11 Bit 10 Boot BIOS Destination
0 1 Reserved
1 0 PCI
1 1 SPI
0 0 LPC
NOTE: If option 00 LPC is selected BIOS may still be placed on LPC, but all platforms with Cougar Point require SPI flash
connected directly to the Cougar Point's SPI bus with a valid descriptor in order to boot.
NOTE: Booting to PCI is intended for debut/testing only. Boot BIOS Destination Select to LPC/PCI by functional strap or via Boot
BIOS Destination Bit will not affect SPI accesses initiated by Management Engine or Integrated GbE LAN.
NOTE: PCI Boot BIOS destination is not supported on mobile.
GNT[3:0]# functionality is not available on Mobile. Used as GPIO only. Pull-up resistors are not required on these signals. If
pull-ups are used, they should be tied to the Vcc3_3 power rail.
DDPD_CTRLDATA Port D Detected.
When '1'- Port D is detected; When '0'- Port D is not detected This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after PLTRST# deasserts.
HDA_SYNC This signal has a weak internal pull-down.
On Die PLL VR is supplied by 1.5 V from VCCVRM when sampled high, 1.8 V from VCCVRM when sampled low.
Needs to be pulled High for Chief River platform.
GPIO15
TLS Confidentiality
Low (0) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality
High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality
This signal has a weak internal pull-down.
NOTE: The weak internal pull-down is disabled after RSMRST# deasserts.
NOTE: A strong pull-up may be needed for GPIO functionality
INTVRMEN
Integrated 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when high
NOTE: This signal should always be pulled high
External 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when Low.
NOTE: This signal should be pulled down to GND through 330 kOhms resistor
GPIO29/
SLP_LAN#
GPIO29 is multiplexed with SLP_LAN#. If Intel LAN is implemented on the platform, SLP_LAN# must be used to control the power
to the PHY LAN (no other implementation is supported). If integrated Intel LAN is not supported on the platform, GPIO29 can be
used as a normal GPIO. A soft strap determines the functionality of GPIO29, either as SLP_LAN# or GPIO. By default, the soft
strap enables SLP_LAN# functionality on the pin. If the soft trap is changed to enable GPIO functionality,
then SLP_LAN# functionality is no longer available, and the signal can be used as a normal GPIO (default to GPI).
Signal has a weak internal pull-down. If strap is sampled low, the security measures defined in the Flash Descriptor will be in
effect (default). If sampled high, the Flash Descriptor Security will be overridden. This strap should only be asserted high via
external pull-up in manufacturing/debug environments ONLY.
Note: The weak internal pull-down is disabled after PLTRST# deasserts. Asserting the HDA_SDO high on the rising edge of
RSMRST# will also halt Intel Management Engine after chipset bring up and disable runtime Intel Management Engine features.
This is a debug mode and must not be asserted after manufacturing/ debug.
CFG[6:5]
CFG[17:7]
CFG[2]
CFG2 is for
the 16x
1:Disabled - No Physical Display Port attached to Embedded DisplayPort
0:Enabled - An external Display Port device is connected to the Embedded
Display Port Pull down to GND through a 1K ± 5% resistor to enable port
CFG[4]
Pin Name Strap Description Configuration (Default value for each bit is
1 unless specified otherwise)
PCIe Static x16
Lane Numbering
Reversal.
1: Normal Operation; Lane # definition matches socket pin map definition
0:Lane Reversed
Default
Value
Display Port
Presence strap
00 = 1 x 8, 2 x 4 PCI Express
01 = reserved
10 = 2 x 8 PCI Express
11 = 1 x 16 PCI Express
Reserved configuration
lands. A test point may
be placed on the board
for these lands.
1
1
11
PCIE Port Bifurcation
Straps
CFG[0] Connect a series 1K ohm resistor on the critical CFG[0] trace in a manner
which does not introduce any stubs to CFG[0] trace. Route as needed
from the opposite side of this series isolation resistor to the debug port.
ITP will drive the net to GND.
1001100
0X41
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DP_COMP
FDI_TX_N0
FDI_TX_N1
FDI_TX_N2
FDI_TX_N3
FDI_TX_N4
FDI_TX_N5
FDI_TX_N6
FDI_TX_N7
FDI_TX_P0
FDI_TX_P1
FDI_TX_P2
FDI_TX_P3
FDI_TX_P4
FDI_TX_P6
FDI_TX_P7
FDI_TX_P5
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
PEG_COMP
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0
PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP0
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_C_TXP0 PEG_TXP0
PEG_TXP1PEG_C_TXP1 PEG_TXP2PEG_C_TXP2 PEG_TXP3PEG_C_TXP3 PEG_TXP4PEG_C_TXP4
PEG_C_TXP6 PEG_TXP6
PEG_TXP7PEG_C_TXP7
PEG_TXP5
PEG_C_TXP8 PEG_TXP8
PEG_C_TXP5
PEG_C_TXP10 PEG_TXP10
PEG_TXP11PEG_C_TXP11
PEG_TXP9
PEG_C_TXP12 PEG_TXP12
PEG_C_TXP9
PEG_C_TXP14 PEG_TXP14
PEG_TXP15PEG_C_TXP15
PEG_TXP13PEG_C_TXP13
PEG_C_TXN0 PEG_TXN0
PEG_C_TXN1 PEG_TXN1
PEG_C_TXN2 PEG_TXN2
PEG_C_TXN3 PEG_TXN3
PEG_C_TXN4 PEG_TXN4
PEG_C_TXN5 PEG_TXN5
PEG_C_TXN6 PEG_TXN6
PEG_C_TXN7
PEG_C_TXN11
PEG_C_TXN12 PEG_TXN11
PEG_TXN12
PEG_TXN7
PEG_C_TXN8 PEG_TXN8
PEG_C_TXN9
PEG_C_TXN10 PEG_TXN9
PEG_TXN10
PEG_C_TXN14
PEG_C_TXN15
PEG_C_TXN13 PEG_TXN14
PEG_TXN15
PEG_TXN13
1D05V_S0
1D05V_S0
FDI_FSYNC119
FDI_LSYNC119 FDI_LSYNC019
FDI_INT19
FDI_TX_N[7:0]19
FDI_TX_P[7:0]19
DMI_RXN[3:0]19
DMI_RXP[3:0]19
DMI_TXN[3:0]19
DMI_TXP[3:0]19
FDI_FSYNC019
PEG_RXN[0..15] 83
PEG_RXP[0..15] 83
PEG_TXN[0..15] 83
PEG_TXP[0..15] 83
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(1/7): DMI/PEG/FDI
A3
4 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(1/7): DMI/PEG/FDI
A3
4 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(1/7): DMI/PEG/FDI
A3
4 103Wednesday, March 14, 2012
<Core Design>
IVY BRIDGE PROCESSOR (DMI,DP,PEG,FDI)
DP Compensation, within 500mil
PEG Compensation
12mil
CPU(1/7)
Note:
Intel DMI supports both Lane
Reversal and polarity inversion
but only at PCH side. This is
enabled via a soft strap.
4mil
Note:
Intel FDI supports both Lane
Reversal and polarity inversion
but only at PCH side. This is
enabled via a soft strap.
Note:
Lane reversal does not apply to
FDI sideband signals.
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
NOTE: EDP_HPD
Select a Fast FET similar to 2N7002E whose rise/
fall time is less than 6 ns.
If HPD on eDP interface is
disabled, connect it to CPU VCCIO via a 10-k pull-Up
resistor on the motherboard.
This signal can be left as no connect if entire eDP interface is disabled.
Signal Routing Guideline:
EDP_ICOMPO keep W/S=12/15 mils and routing
length less than 500 mils.
EDP_COMPIO keep W/S=4/15 mils and routing
length less than 500 mils.
NOTE.
Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort. BOM Note:1st/2nd/3rd Add in BOM
1 2
R402 24D9R2F-L-GPR402 24D9R2F-L-GP
1 2
C402 SCD22U16V2KX-GP
DIX_PX
C402 SCD22U16V2KX-GP
DIX_PX
1 2
C405 SCD22U16V2KX-GP
DIX_PX
C405 SCD22U16V2KX-GP
DIX_PX
1 2
C408 SCD22U16V2KX-GP
DIX_PX
C408 SCD22U16V2KX-GP
DIX_PX
1 2
C411 SCD22U16V2KX-GP
DIX_PX
C411 SCD22U16V2KX-GP
DIX_PX
1 2
C414 SCD22U16V2KX-GP
DIX_PX
C414 SCD22U16V2KX-GP
DIX_PX
1 2
C426 SCD22U16V2KX-GP
DIX_PX
C426 SCD22U16V2KX-GP
DIX_PX
1 2
C429 SCD22U16V2KX-GP
DIX_PX
C429 SCD22U16V2KX-GP
DIX_PX
1 2
C432 SCD22U16V2KX-GP
DIX_PX
C432 SCD22U16V2KX-GP
DIX_PX
1 2
C401 SCD22U16V2KX-GP
DIX_PX
C401 SCD22U16V2KX-GP
DIX_PX
1 2
C418 SCD22U16V2KX-GP
DIX_PX
C418 SCD22U16V2KX-GP
DIX_PX
1 2
C421 SCD22U16V2KX-GP
DIX_PX
C421 SCD22U16V2KX-GP
DIX_PX
1 2
C424 SCD22U16V2KX-GP
DIX_PX
C424 SCD22U16V2KX-GP
DIX_PX
1 2
C403 SCD22U16V2KX-GP
DIX_PX
C403 SCD22U16V2KX-GP
DIX_PX
1 2
C406 SCD22U16V2KX-GP
DIX_PX
C406 SCD22U16V2KX-GP
DIX_PX
1 2
C409 SCD22U16V2KX-GP
DIX_PX
C409 SCD22U16V2KX-GP
DIX_PX
1 2
C412 SCD22U16V2KX-GP
DIX_PX
C412 SCD22U16V2KX-GP
DIX_PX
1 2
C415 SCD22U16V2KX-GP
DIX_PX
C415 SCD22U16V2KX-GP
DIX_PX
1 2
C427 SCD22U16V2KX-GP
DIX_PX
C427 SCD22U16V2KX-GP
DIX_PX
1 2
C430 SCD22U16V2KX-GP
DIX_PX
C430 SCD22U16V2KX-GP
DIX_PX
1 2
C419 SCD22U16V2KX-GP
DIX_PX
C419 SCD22U16V2KX-GP
DIX_PX
1 2
C422 SCD22U16V2KX-GP
DIX_PX
C422 SCD22U16V2KX-GP
DIX_PX
1 2
C425 SCD22U16V2KX-GP
DIX_PX
C425 SCD22U16V2KX-GP
DIX_PX
1 2
C404 SCD22U16V2KX-GP
DIX_PX
C404 SCD22U16V2KX-GP
DIX_PX
1 2
C407 SCD22U16V2KX-GP
DIX_PX
C407 SCD22U16V2KX-GP
DIX_PX
1 2
C410 SCD22U16V2KX-GP
DIX_PX
C410 SCD22U16V2KX-GP
DIX_PX
1 2
C413 SCD22U16V2KX-GP
DIX_PX
C413 SCD22U16V2KX-GP
DIX_PX
1 2
C416 SCD22U16V2KX-GP
DIX_PX
C416 SCD22U16V2KX-GP
DIX_PX
1 2
C428 SCD22U16V2KX-GP
DIX_PX
C428 SCD22U16V2KX-GP
DIX_PX
1 2
C431 SCD22U16V2KX-GP
DIX_PX
C431 SCD22U16V2KX-GP
DIX_PX
DMI_RX#0
B27
DMI_RX#1
B25
DMI_RX#2
A25
DMI_RX#3
B24
DMI_RX0
B28
DMI_RX1
B26
DMI_RX2
A24
DMI_RX3
B23
DMI_TX#0
G21
DMI_TX#1
E22
DMI_TX#2
F21
DMI_TX#3
D21
DMI_TX0
G22
DMI_TX1
D22
DMI_TX3
C21 DMI_TX2
F20
FDI0_TX#0
A21
FDI0_TX#1
H19
FDI0_TX#2
E19
FDI0_TX#3
F18
FDI1_TX#0
B21
FDI1_TX#1
C20
FDI1_TX#2
D18
FDI1_TX#3
E17
FDI0_TX0
A22
FDI0_TX1
G19
FDI0_TX2
E20
FDI0_TX3
G18
FDI1_TX0
B20
FDI1_TX1
C19
FDI1_TX2
D19
FDI1_TX3
F17
FDI0_FSYNC
J18
FDI1_FSYNC
J17
FDI_INT
H20
FDI0_LSYNC
J19
FDI1_LSYNC
H17
PEG_ICOMPI J22
PEG_ICOMPO J21
PEG_RCOMPO H22
PEG_RX#0 K33
PEG_RX#1 M35
PEG_RX#2 L34
PEG_RX#3 J35
PEG_RX#4 J32
PEG_RX#5 H34
PEG_RX#6 H31
PEG_RX#7 G33
PEG_RX#8 G30
PEG_RX#9 F35
PEG_RX#10 E34
PEG_RX#11 E32
PEG_RX#12 D33
PEG_RX#13 D31
PEG_RX#14 B33
PEG_RX#15 C32
PEG_RX0 J33
PEG_RX1 L35
PEG_RX2 K34
PEG_RX3 H35
PEG_RX4 H32
PEG_RX5 G34
PEG_RX6 G31
PEG_RX7 F33
PEG_RX8 F30
PEG_RX9 E35
PEG_RX10 E33
PEG_RX11 F32
PEG_RX12 D34
PEG_RX13 E31
PEG_RX14 C33
PEG_RX15 B32
PEG_TX#0 M29
PEG_TX#1 M32
PEG_TX#2 M31
PEG_TX#3 L32
PEG_TX#4 L29
PEG_TX#5 K31
PEG_TX#6 K28
PEG_TX#7 J30
PEG_TX#8 J28
PEG_TX#9 H29
PEG_TX#10 G27
PEG_TX#11 E29
PEG_TX#12 F27
PEG_TX#13 D28
PEG_TX#14 F26
PEG_TX#15 E25
PEG_TX0 M28
PEG_TX1 M33
PEG_TX2 M30
PEG_TX3 L31
PEG_TX4 L28
PEG_TX5 K30
PEG_TX6 K27
PEG_TX7 J29
PEG_TX8 J27
PEG_TX9 H28
PEG_TX10 G28
PEG_TX11 E28
PEG_TX12 F28
PEG_TX13 D27
PEG_TX14 E26
PEG_TX15 D25
EDP_AUX
C15
EDP_AUX#
D15
EDP_TX0
C17
EDP_TX1
F16
EDP_TX2
C16
EDP_TX3
G15
EDP_TX#0
C18
EDP_TX#1
E16
EDP_TX#2
D16
EDP_TX#3
F15
EDP_COMPIO
A18
EDP_HPD
B16 EDP_ICOMPO
A17
PCI EXPRESS* - GRAPHICS
DMI
Intel(R) FDI
eDP
1 OF 9
IVY-BRIDGE
CPU1A
62.10040.821
2nd = 62.10055.321
3rd = 62.10055.731
1ST = 62.10055.551
PCI EXPRESS* - GRAPHICS
DMI
Intel(R) FDI
eDP
1 OF 9
IVY-BRIDGE
CPU1A
62.10040.821
2nd = 62.10055.321
3rd = 62.10055.731
1ST = 62.10055.551
1 2
C417 SCD22U16V2KX-GP
DIX_PX
C417 SCD22U16V2KX-GP
DIX_PX
1 2
R401 24D9R2F-L-GPR401 24D9R2F-L-GP
1 2
C420 SCD22U16V2KX-GP
DIX_PX
C420 SCD22U16V2KX-GP
DIX_PX
1 2
C423 SCD22U16V2KX-GP
DIX_PX
C423 SCD22U16V2KX-GP
DIX_PX
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
XDP_TRST#
H_PM_SYNC_R
H_PROCHOT#
XDP_TMS
XDP_TDI
XDP_PREQ#
XDP_TCK
H_PROCHOT#_D
TP_SKTOCC#_R
PM_DRAM_PWRGD_R
CLK_DP_N_R
CLK_DP_P_R
BUF_CPU_RST#_R
CPU_BCLK_P
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
CPUDRAMRST#
CPUDRAMRST#_R
H_CPUPWRGD_R
H_CPUPWRGD_R
CPU_BCLK_N
CPUDRAMRST#
H_CATERR#
PM_DRAM_PWRGD_M
BUF_CPU_RST#
XDP_BPM1_R
XDP_BPM0_R
XDP_BPM3_R
XDP_BPM2_R
XDP_BPM4_R
XDP_BPM5_R
XDP_BPM6_R
XDP_BPM7_R
XDP_PRDY#
XDP_PREQ#
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_TCK
XDP_TDO
XDP_DBRESET#
1D05V_S0
1D05V_S0
1D5V_S3
1D05V_S0 3D3V_S0
3D3V_S0
1D05V_S0
1D5V_S03D3V_S5
3D3V_S0 1D05V_S0
3D3V_S5
H_PROCHOT# 42
PM_DRAM_PWRGD19
H_SNB_IVB#22
H_THRMTRIP#22,85
H_PECI22,27
H_PM_SYNC19
CLKOUT_DMI_P 18
CLKOUT_DMI_N 18
PCH_DDR_EN# 8
H_CPUPWRGD22
DDR3_DRAMRST# 14,15,97
KBC_PROCHOT27
PLT_RST#17,21,32,34,53,54,56,71,83,96,97
XDP_DBRESET# 19
PWR_GOOD27,37,42,50,96
PCH_DDR_RST#18 PCH_DDR_EN# 8
KBC_DDR_RST#27,46
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(2/7) : CLK/MISC/JTAG
Custom
5 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(2/7) : CLK/MISC/JTAG
Custom
5 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(2/7) : CLK/MISC/JTAG
Custom
5 103Wednesday, March 14, 2012
<Core Design>
CPU(2/7)
Buffered reset to CPU
S3 Power Reduction Circuit
SM_DRAMRST#
PM_DRAM_PWRGD Traces impedance= 50 ohm
DDR3 Compensation Signals
IVY BRIDGE PROCESSOR (CLK,MISC,JTAG)
PU/PD for JTAG signals
AND GATE
PUT CLOSE CPU
DEEP S3
20120112 PV-R
20120116PV-R
20120116PV-R
12
R515
4K99R2F-L-GP
R515
4K99R2F-L-GP
1 2
R530
0R0402-PAD
R530
0R0402-PAD
12
R501
62R2F-GP
R501
62R2F-GP
G
S
D
Q501
2N7002K-2-GP
2nd = 84.07002.I31
84.2N702.J31
3rd = 84.2N702.W31
Q501
2N7002K-2-GP
2nd = 84.07002.I31
84.2N702.J31
3rd = 84.2N702.W31
G
DS
Q503
DMN5L06K-7-GP
84.05067.031
2ND = 84.07002.I31
3rd = 84.2N702.W31
DY_DS3
Q503
DMN5L06K-7-GP
84.05067.031
2ND = 84.07002.I31
3rd = 84.2N702.W31
DY_DS3
1TP510 TPAD14-OP-GPTP510 TPAD14-OP-GP
12
R510
200R2F-L-GP
R510
200R2F-L-GP
12
R524
200R2F-L-GP
R524
200R2F-L-GP
1TP511 TPAD14-OP-GPTP511 TPAD14-OP-GP
1
TP502
TPAD14-OP-GP
TP502
TPAD14-OP-GP
IN B
1
IN A
2
GND
3OUT Y 4
VCC 5
U501
74VHC1G09DFT2G-GP
73.01G09.AAH
2nd = 73.01G09.0AB
3rd = 73.01G09.BAH
U501
74VHC1G09DFT2G-GP
73.01G09.AAH
2nd = 73.01G09.0AB
3rd = 73.01G09.BAH
G
DS
Q502
DMN5L06K-7-GP
2ND = 84.00138.F31
84.05067.031
Q502
DMN5L06K-7-GP
2ND = 84.00138.F31
84.05067.031
1TP515 TPAD14-OP-GPTP515 TPAD14-OP-GP
1 2
R502
0R2J-2-GP
DY
R502
0R2J-2-GP
DY
12
R503
140R2F-GP
R503
140R2F-GP
1TP512 TPAD14-OP-GPTP512 TPAD14-OP-GP
12
C503
SCD1U10V2KX-5GP
C503
SCD1U10V2KX-5GP
12
C504
SCD1U10V2KX-5GP
C504
SCD1U10V2KX-5GP
1 2
R527
1K5R2F-2-GP
DY
R527
1K5R2F-2-GP
DY
12
R513
1KR2F-3-GP
R513
1KR2F-3-GP
1TP503 TPAD14-OP-GPTP503 TPAD14-OP-GP
1TP516 TPAD14-OP-GPTP516 TPAD14-OP-GP
1 2
R528
20KR2J-L2-GP
DY_DS3
R528
20KR2J-L2-GP
DY_DS3
1 2
R511 51R2J-2-GPR511 51R2J-2-GP
12
R526
75R2J-1-GP
R526
75R2J-1-GP
12
R529
20KR2J-L2-GP
DY
R529
20KR2J-L2-GP
DY
12
C501
SCD047U25V2KX-GP
C501
SCD047U25V2KX-GP
1 2
R1110
1KR2J-1-GP
R1110
1KR2J-1-GP
1
TP501TPAD14-OP-GPTP501TPAD14-OP-GP
1 2
R507 51R2J-2-GPR507 51R2J-2-GP
12
C502
SC1U6D3V2KX-GP
C502
SC1U6D3V2KX-GP
12
R521
750R2F-GP
DY
R521
750R2F-GP
DY
1TP513 TPAD14-OP-GPTP513 TPAD14-OP-GP
1 2
R1111
51R2J-2-GP
R1111
51R2J-2-GP
12
R504
25D5R2F-GP
R504
25D5R2F-GP
1 2
R517
43R2J-GP
R517
43R2J-GP
1 2
R514
1KR2J-1-GP
R514
1KR2J-1-GP
1 2
R520 0R0402-PAD-1-GPR520 0R0402-PAD-1-GP
1TP517 TPAD14-OP-GPTP517 TPAD14-OP-GP
1 2
R522
0R2J-2-GP
DY
R522
0R2J-2-GP
DY
1 2
R505 51R2J-2-GP
DY
R505 51R2J-2-GP
DY
1TP514 TPAD14-OP-GPTP514 TPAD14-OP-GP
1
2 3
4
RN
0R4P2R-PADRN501
RN
0R4P2R-PADRN501
1 2
R506 51R2J-2-GPR506 51R2J-2-GP
1 2
R512 130R2F-1-GPR512 130R2F-1-GP
12
R525
100KR2J-1-GP
R525
100KR2J-1-GP
12
R523
200R2F-L-GP
R523
200R2F-L-GP
1
2 3
4RN504
SRN1KJ-7-GP
RN504
SRN1KJ-7-GP
1 2
R518 10KR2J-3-GPR518 10KR2J-3-GP
1 2
R508 56R2F-1-GPR508 56R2F-1-GP
1 2
R519 0R0402-PAD-1-GPR519 0R0402-PAD-1-GP
SM_RCOMP1 A5
SM_RCOMP2 A4
SM_DRAMRST# R8
SM_RCOMP0 AK1
BCLK# A27
BCLK A28
DPLL_REF_CLK# A15
DPLL_REF_CLK A16
CATERR#
AL33
PECI
AN33
PROCHOT#
AL32
THERMTRIP#
AN32
SM_DRAMPWROK
V8
RESET#
AR33
PRDY# AP29
PREQ# AP27
TCK AR26
TMS AR27
TRST# AP30
TDI AR28
TDO AP26
DBR# AL35
BPM#0 AT28
BPM#1 AR29
BPM#2 AR30
BPM#3 AT30
BPM#4 AP32
BPM#5 AR31
BPM#6 AT31
BPM#7 AR32
PM_SYNC
AM34
SKTOCC#
AN34
PROC_SELECT#
C26
UNCOREPWRGOOD
AP33
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
2 OF 9
IVY-BRIDGE
CPU1B
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
2 OF 9
IVY-BRIDGE
CPU1B
1 2
R509 51R2J-2-GPR509 51R2J-2-GP
NC#1
1
A
2
GND
3Y4
VCC 5
U502
74LVC1G07GW-GP
3rd = 73.17S07.0AG
1st = 73.01G07.AHG
2nd = 73.01G07.AHG
U502
74LVC1G07GW-GP
3rd = 73.17S07.0AG
1st = 73.01G07.AHG
2nd = 73.01G07.AHG
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M_A_DQS4
M_A_DQS3
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS2
M_A_DQS1
M_A_DQS0
M_B_DQ39
M_B_DQ54
M_B_DQ24
M_A_DQ13
M_B_DQ21
M_B_DQ8
M_A_DQ55
M_B_DQ40
M_B_DQ55
M_B_DQ25
M_B_DQ22
M_B_DQ9
M_A_DQ56
M_B_DQ41
M_B_DQ56
M_B_DQ26
M_A_DQ0
M_B_DQ10
M_A_DQ57
M_B_DQ42
M_A_DQ14
M_B_DQ27
M_B_DQ57
M_A_DQ1
M_B_DQ11
M_A_DQ58
M_B_DQ43
M_A_DQ15
M_B_DQ28
M_B_DQ58
M_B_DQ23
M_A_DQ2
M_B_DQ12
M_A_DQ59
M_B_DQ44
M_A_DQ16
M_B_DQ29
M_B_DQ59
M_A_DQ3
M_B_DQ13
M_A_DQ60
M_B_DQ45
M_A_DQ17
M_B_DQ30
M_B_DQ60
M_A_DQ4
M_B_DQ14
M_B_DQ46
M_A_DQ18
M_A_DQ61
M_B_DQ31
M_A_DQ5
M_B_DQ15
M_A_DQ19
M_B_DQ47
M_A_DQ62
M_B_DQ32
M_B_DQ0
M_A_DQ6
M_B_DQ16
M_A_DQ20
M_B_DQ48
M_B_DQ33
M_A_DQ63
M_B_DQ1
M_B_DQ62
M_A_DQ7
M_B_DQ17
M_A_DQ21
M_B_DQ34
M_B_DQ49
M_B_DQ2
M_A_DQ8
M_A_DQ22
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ32
M_A_DQ31
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ37
M_B_DQS0
M_A_DQ36
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ43
M_A_DQ42
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_B_DQ35
M_B_DQ3
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQ50
M_A_DQ9
M_A_DQ51
M_A_DQ23
M_B_DQ4
M_B_DQ36
M_B_DQ51
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_A_DQ10
M_B_DQ18
M_A_DQ52
M_A_DQ24
M_B_DQ5
M_B_DQ37
M_B_DQ52
M_A_DQ11
M_B_DQ61
M_B_DQ19
M_A_DQ53
M_A_DQ25
M_B_DQ6
M_B_DQ38
M_B_DQ53
M_A_DQ12
M_B_DQ63
M_B_DQ20
M_A_DQ54
M_B_DQ7
M_A_A7
M_A_A12
M_A_A14
M_A_A13
M_A_A9
M_A_A15
M_A_A10
M_A_A0
M_A_A6
M_A_A8
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A11
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS#3
M_A_DQS#2
M_A_DQS#1
M_A_DQS#0
M_B_DQS#3
M_B_DQS#2
M_B_DQS#1
M_B_DQS#0
M_B_DQS#7
M_B_DQS#6
M_B_DQS#5
M_B_DQS#4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A4
M_B_A3
M_B_A2
M_B_A1
M_B_A0
M_A_BS014 M_A_BS114 M_A_BS214
M_A_CAS#14 M_A_RAS#14 M_A_WE#14
M_A_A[15:0] 14
M_A_DQS[7:0] 14
M_B_BS015 M_B_BS115 M_B_BS215
M_B_CAS#15 M_B_RAS#15 M_B_WE#15
M_A_DQS#[7:0] 14
M_A_DIM0_CKE0 14
M_A_DIM0_CKE1 14
M_A_DIM0_CS#0 14
M_A_DIM0_CS#1 14
M_A_DIM0_ODT0 14
M_A_DIM0_ODT1 14
M_A_DIM0_CLK_DDR0 14
M_A_DIM0_CLK_DDR#0 14
M_A_DIM0_CLK_DDR1 14
M_A_DIM0_CLK_DDR#1 14
M_B_DIM0_CKE0 15
M_B_DIM0_CKE1 15
M_B_DIM0_CS#0 15
M_B_DIM0_CS#1 15
M_B_DIM0_ODT0 15
M_B_DIM0_ODT1 15
M_B_DIM0_CLK_DDR0 15
M_B_DIM0_CLK_DDR#0 15
M_B_DIM0_CLK_DDR1 15
M_B_DIM0_CLK_DDR#1 15
M_B_A[15:0] 15
M_B_DQS[7:0] 15
M_B_DQS#[7:0] 15
M_A_DQ[63:0]14 M_B_DQ[63:0]15
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(3/7) : DDR3
Custom
6 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(3/7) : DDR3
Custom
6 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(3/7) : DDR3
Custom
6 103Wednesday, March 14, 2012
<Core Design>
IVY BRIDGE PROCESSOR (DDR3)
CPU(3/7)
SB_BS0
AA9
SB_BS1
AA7
SB_BS2
R6
SB_CAS#
AA10
SB_RAS#
AB8
SB_WE#
AB9
SB_CK0 AE2
SB_CK1 AE1
SB_CLK#0 AD2
SB_CLK#1 AD1
SB_CKE0 R9
SB_CKE1 R10
SB_ODT0 AE4
SB_ODT1 AD4
SB_DQS4 AN6
SB_DQS#4 AN5
SB_DQS5 AP8
SB_DQS#5 AP9
SB_DQS6 AK11
SB_DQS#6 AK12
SB_DQS7 AP14
SB_DQS#7 AP15
SB_DQS0 C7
SB_DQS#0 D7
SB_DQS1 G3
SB_DQS#1 F3
SB_DQS2 J6
SB_DQS#2 K6
SB_DQS3 M3
SB_DQS#3 N3
SB_MA0 AA8
SB_MA1 T7
SB_MA2 R7
SB_MA3 T6
SB_MA4 T2
SB_MA5 T4
SB_MA6 T3
SB_MA7 R2
SB_MA8 T5
SB_MA9 R3
SB_MA10 AB7
SB_MA11 R1
SB_MA12 T1
SB_MA13 AB10
SB_MA14 R5
SB_MA15 R4
SB_DQ0
C9
SB_DQ1
A7
SB_DQ2
D10
SB_DQ3
C8
SB_DQ4
A9
SB_DQ5
A8
SB_DQ6
D9
SB_DQ7
D8
SB_DQ8
G4
SB_DQ9
F4
SB_DQ10
F1
SB_DQ11
G1
SB_DQ12
G5
SB_DQ13
F5
SB_DQ14
F2
SB_DQ15
G2
SB_DQ16
J7
SB_DQ17
J8
SB_DQ18
K10
SB_DQ19
K9
SB_DQ20
J9
SB_DQ21
J10
SB_DQ22
K8
SB_DQ23
K7
SB_DQ24
M5
SB_DQ25
N4
SB_DQ26
N2
SB_DQ27
N1
SB_DQ28
M4
SB_DQ29
N5
SB_DQ30
M2
SB_DQ31
M1
SB_DQ32
AM5
SB_DQ33
AM6
SB_DQ34
AR3
SB_DQ35
AP3
SB_DQ36
AN3
SB_DQ37
AN2
SB_DQ38
AN1
SB_DQ39
AP2
SB_DQ40
AP5
SB_DQ41
AN9
SB_DQ42
AT5
SB_DQ43
AT6
SB_DQ44
AP6
SB_DQ45
AN8
SB_DQ46
AR6
SB_DQ47
AR5
SB_DQ48
AR9
SB_DQ49
AJ11
SB_DQ50
AT8
SB_DQ51
AT9
SB_DQ52
AH11
SB_DQ53
AR8
SB_DQ54
AJ12
SB_DQ55
AH12
SB_DQ56
AT11
SB_DQ57
AN14
SB_DQ58
AR14
SB_DQ59
AT14
SB_DQ60
AT12
SB_DQ61
AN15
SB_DQ62
AR15
SB_DQ63
AT15
SB_CK2 AB2
SB_CLK#2 AA2
SB_CKE2 T9
SB_CK3 AA1
SB_CLK#3 AB1
SB_CKE3 T10
SB_CS#0 AD3
SB_CS#1 AE3
SB_CS#2 AD6
SB_CS#3 AE6
SB_ODT2 AD5
SB_ODT3 AE5
DDR SYSTEM MEMORY B
4 OF 9
IVY-BRIDGE
CPU1D
DDR SYSTEM MEMORY B
4 OF 9
IVY-BRIDGE
CPU1D
SA_BS0
AE10
SA_BS1
AF10
SA_BS2
V6
SA_CAS#
AE8
SA_RAS#
AD9
SA_WE#
AF9
SA_CK0 AB6
SA_CK1 AA5
SA_CLK#0 AA6
SA_CLK#1 AB5
SA_CKE0 V9
SA_CKE1 V10
SA_CS#0 AK3
SA_CS#1 AL3
SA_ODT0 AH3
SA_ODT1 AG3
SA_DQS0 D4
SA_DQS#0 C4
SA_DQS1 F6
SA_DQS#1 G6
SA_DQS2 K3
SA_DQS#2 J3
SA_DQS3 N6
SA_DQS#3 M6
SA_DQS4 AL5
SA_DQS#4 AL6
SA_DQS5 AM9
SA_DQS#5 AM8
SA_DQS6 AR11
SA_DQS#6 AR12
SA_DQS7 AM14
SA_DQS#7 AM15
SA_MA0 AD10
SA_MA1 W1
SA_MA2 W2
SA_MA3 W7
SA_MA4 V3
SA_MA5 V2
SA_MA6 W3
SA_MA7 W6
SA_MA8 V1
SA_MA9 W5
SA_MA10 AD8
SA_MA11 V4
SA_MA12 W4
SA_MA13 AF8
SA_MA14 V5
SA_MA15 V7
SA_DQ0
C5
SA_DQ1
D5
SA_DQ2
D3
SA_DQ3
D2
SA_DQ4
D6
SA_DQ5
C6
SA_DQ6
C2
SA_DQ7
C3
SA_DQ8
F10
SA_DQ9
F8
SA_DQ10
G10
SA_DQ11
G9
SA_DQ12
F9
SA_DQ13
F7
SA_DQ14
G8
SA_DQ15
G7
SA_DQ16
K4
SA_DQ17
K5
SA_DQ18
K1
SA_DQ19
J1
SA_DQ20
J5
SA_DQ21
J4
SA_DQ22
J2
SA_DQ23
K2
SA_DQ24
M8
SA_DQ25
N10
SA_DQ26
N8
SA_DQ27
N7
SA_DQ28
M10
SA_DQ29
M9
SA_DQ30
N9
SA_DQ31
M7
SA_DQ32
AG6
SA_DQ33
AG5
SA_DQ34
AK6
SA_DQ35
AK5
SA_DQ36
AH5
SA_DQ37
AH6
SA_DQ38
AJ5
SA_DQ39
AJ6
SA_DQ40
AJ8
SA_DQ41
AK8
SA_DQ42
AJ9
SA_DQ43
AK9
SA_DQ44
AH8
SA_DQ45
AH9
SA_DQ46
AL9
SA_DQ47
AL8
SA_DQ48
AP11
SA_DQ49
AN11
SA_DQ50
AL12
SA_DQ51
AM12
SA_DQ52
AM11
SA_DQ53
AL11
SA_DQ54
AP12
SA_DQ55
AN12
SA_DQ56
AJ14
SA_DQ57
AH14
SA_DQ58
AL15
SA_DQ59
AK15
SA_DQ60
AL14
SA_DQ61
AK14
SA_DQ62
AJ15
SA_DQ63
AH15
SA_CK2 AB4
SA_CLK#2 AA4
SA_CK3 AB3
SA_CLK#3 AA3
SA_CKE2 W9
SA_CKE3 W10
SA_CS#2 AG1
SA_CS#3 AH1
SA_ODT2 AG2
SA_ODT3 AH2
DDR SYSTEM MEMORY A
3 OF 9
IVY-BRIDGE
CPU1C
DDR SYSTEM MEMORY A
3 OF 9
IVY-BRIDGE
CPU1C
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
VSSSENSE
VCCSENSE
1D05V_S0
1D05V_S0
VCC_CORE
VCC_CORE
1D05V_S0
VCCSENSE 42
VSSSENSE 42
VTT_SENSE 45
VR_SVID_ALERT# 42
H_CPU_SVIDDAT 42
H_CPU_SVIDCLK 42
VSSP_SENSE 45
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(4/7) : PWR
Custom
7 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(4/7) : PWR
Custom
7 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(4/7) : PWR
Custom
7 103Wednesday, March 14, 2012
<Core Design>
Differential Sense feedback
IVY BRIDGE PROCESSOR (POWER)
PROCESSOR UNCORE POWER
8.5A
CPU(4/7)
53A
Route these three net together
PUT CLOSE CPU
PUT CLOSE CPU
PROCESSOR CORE
POWER
Place Bottom
Place Top
reserve PAD for ESD
12
C709
SC10U6D3V3MX-GP
C709
SC10U6D3V3MX-GP
12
R707
10R2F-L-GP
R707
10R2F-L-GP
12
C716
SC22U6D3V5MX-2GP
C716
SC22U6D3V5MX-2GP
1 2
D702
0R2J-2-GP
DY
D702
0R2J-2-GP
DY
12
C742
SC22U6D3V5MX-2GP
C742
SC22U6D3V5MX-2GP
12
C735
SC22U6D3V5MX-2GP
C735
SC22U6D3V5MX-2GP
12
C717
SC22U6D3V5MX-2GP
C717
SC22U6D3V5MX-2GP
12
C741
SC10U6D3V5KX-1GP
C741
SC10U6D3V5KX-1GP
12
C712
SC22U6D3V5MX-2GP
C712
SC22U6D3V5MX-2GP
12
R706
100R2F-L1-GP-U
R706
100R2F-L1-GP-U
1 2
R703 130R2F-1-GPR703 130R2F-1-GP
1 2
D701
0R2J-2-GP
DY
D701
0R2J-2-GP
DY
12
C702
SC10U6D3V5KX-1GP
C702
SC10U6D3V5KX-1GP
12
C701
SC10U6D3V5KX-1GP
C701
SC10U6D3V5KX-1GP
12
C738
SC10U6D3V5KX-1GP
C738
SC10U6D3V5KX-1GP
12
C715
SC10U6D3V3MX-GP
C715
SC10U6D3V3MX-GP
12
C703
SC22U6D3V5MX-2GP
C703
SC22U6D3V5MX-2GP
12
C710
SC22U6D3V5MX-2GP
C710
SC22U6D3V5MX-2GP
12
C727
SC10U6D3V3MX-GP
C727
SC10U6D3V3MX-GP
12
C714
SC22U6D3V5MX-2GP
C714
SC22U6D3V5MX-2GP
12
C734
SC10U6D3V3MX-GP
C734
SC10U6D3V3MX-GP
12
C733
SC10U6D3V3MX-GP
C733
SC10U6D3V3MX-GP
12
R704
100R2F-L1-GP-U
R704
100R2F-L1-GP-U
12
C722
SC22U6D3V5MX-2GP
C722
SC22U6D3V5MX-2GP
12
C729
SC10U6D3V3MX-GP
C729
SC10U6D3V3MX-GP
VCC_SENSE AJ35
VSS_SENSE AJ34
VIDALERT# AJ29
VIDSCLK AJ30
VIDSOUT AJ28
VSS_SENSE_VCCIO A10
VCC1
AG35
VCC2
AG34
VCC3
AG33
VCC4
AG32
VCC5
AG31
VCC6
AG30
VCC7
AG29
VCC8
AG28
VCC9
AG27
VCC10
AG26
VCC11
AF35
VCC12
AF34
VCC13
AF33
VCC14
AF32
VCC15
AF31
VCC16
AF30
VCC17
AF29
VCC18
AF28
VCC19
AF27
VCC20
AF26
VCC21
AD35
VCC22
AD34
VCC23
AD33
VCC24
AD32
VCC25
AD31
VCC26
AD30
VCC27
AD29
VCC28
AD28
VCC29
AD27
VCC30
AD26
VCC31
AC35
VCC32
AC34
VCC33
AC33
VCC34
AC32
VCC35
AC31
VCC36
AC30
VCC37
AC29
VCC38
AC28
VCC39
AC27
VCC40
AC26
VCC41
AA35
VCC42
AA34
VCC43
AA33
VCC44
AA32
VCC45
AA31
VCC46
AA30
VCC47
AA29
VCC48
AA28
VCC49
AA27
VCC50
AA26
VCC51
Y35
VCC52
Y34
VCC53
Y33
VCC54
Y32
VCC55
Y31
VCC56
Y30
VCC57
Y29
VCC58
Y28
VCC59
Y27
VCC60
Y26
VCC61
V35
VCC62
V34
VCC63
V33
VCC64
V32
VCC65
V31
VCC66
V30
VCC67
V29
VCC68
V28
VCC69
V27
VCC70
V26
VCC71
U35
VCC72
U34
VCC73
U33
VCC74
U32
VCC75
U31
VCC76
U30
VCC77
U29
VCC78
U28
VCC79
U27
VCC80
U26
VCC81
R35
VCC82
R34
VCC83
R33
VCC84
R32
VCC85
R31
VCC86
R30
VCC87
R29
VCC88
R28
VCC89
R27
VCC90
R26
VCC91
P35
VCC92
P34
VCC93
P33
VCC94
P32
VCC95
P31
VCC96
P30
VCC97
P29
VCC98
P28
VCC99
P27
VCC100
P26
VCCIO1 AH13
VCCIO12 J11
VCCIO18 G12
VCCIO19 F14
VCCIO20 F13
VCCIO21 F12
VCCIO22 F11
VCCIO23 E14
VCCIO24 E12
VCCIO2 AH10
VCCIO3 AG10
VCCIO4 AC10
VCCIO5 Y10
VCCIO6 U10
VCCIO7 P10
VCCIO8 L10
VCCIO9 J14
VCCIO10 J13
VCCIO11 J12
VCCIO13 H14
VCCIO14 H12
VCCIO15 H11
VCCIO16 G14
VCCIO17 G13
VCCIO25 E11
VCCIO32 C12
VCCIO33 C11
VCCIO34 B14
VCCIO35 B12
VCCIO36 A14
VCCIO37 A13
VCCIO38 A12
VCCIO39 A11
VCCIO26 D14
VCCIO27 D13
VCCIO28 D12
VCCIO29 D11
VCCIO30 C14
VCCIO31 C13
VCCIO_SENSE B10
VCCIO40 J23
CORE SUPPLY
PEG AND DDR
SENSE LINES SVID
6 OF 9
POWER
IVY-BRIDGE
CPU1F
CORE SUPPLY
PEG AND DDR
SENSE LINES SVID
6 OF 9
POWER
IVY-BRIDGE
CPU1F
12
C720
SC22U6D3V5MX-2GP
C720
SC22U6D3V5MX-2GP
12
C732
SC10U6D3V3MX-GP
C732
SC10U6D3V3MX-GP
12
C718
SC10U6D3V3MX-GP
C718
SC10U6D3V3MX-GP
12
C706
SC10U6D3V5KX-1GP
C706
SC10U6D3V5KX-1GP
12
C736
SC22U6D3V5MX-2GP
C736
SC22U6D3V5MX-2GP
12
C728
SC22U6D3V5MX-2GP
C728
SC22U6D3V5MX-2GP
12
C739
SC22U6D3V5MX-2GP
C739
SC22U6D3V5MX-2GP
12
C719
SC10U6D3V3MX-GP
C719
SC10U6D3V3MX-GP
12
C740
SC22U6D3V5MX-2GP
C740
SC22U6D3V5MX-2GP
12
C711
SC22U6D3V5MX-2GP
C711
SC22U6D3V5MX-2GP
12
R708
10R2F-L-GP
R708
10R2F-L-GP
12
C726
SC10U6D3V3MX-GP
C726
SC10U6D3V3MX-GP
12
C730
SC10U6D3V3MX-GP
C730
SC10U6D3V3MX-GP
12
C721
SC22U6D3V5MX-2GP
C721
SC22U6D3V5MX-2GP
12
C731
SC22U6D3V5MX-2GP
C731
SC22U6D3V5MX-2GP
12
C723
SC22U6D3V5MX-2GP
C723
SC22U6D3V5MX-2GP
12
C708
SC10U6D3V5KX-1GP
C708
SC10U6D3V5KX-1GP
12
C713
SC22U6D3V5MX-2GP
C713
SC22U6D3V5MX-2GP
12
C707
SC10U6D3V5KX-1GP
C707
SC10U6D3V5KX-1GP
12
C704
SC22U6D3V5MX-2GP
C704
SC22U6D3V5MX-2GP
1 2
R705 43R2J-GPR705 43R2J-GP
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_VREF_S3_B4
H_FC_C22
DDR_VREF_S3_D1
H_VCCP_SEL
VCCUSA_SENSE
+V_SM_VREF_CNT
VCCSA_SEL
+V_SM_VREF_CNT
DDR_VREF_S3_D1
PCH_DDR_EN#
DDR_VREF_S3_B4
+V_SM_VREF
+V_SM_VREF_G
VSSGT_SENSE
VCCGT_SENSE
DDR_VREF_S3
VCCSA
1D5V_S0
1D8V_S0
VCCSA
VCC_GFXCORE
1D5V_S3
VCC_GFXCORE
VCC_GFXCORE
H_SNB_IVB#_PWRCTRL 45
VCCGT_SENSE 42
VSSGT_SENSE 42
VCCUSA_SENSE 48
PCH_DDR_EN#5
VCCSA_SEL 48
H_FC_C22 48
M_VREF_DQ_DIMM014
PCH_DDR_EN#5
M_VREF_DQ_DIMM115
PM_SLP_S3#19,27,29,34,35,36,37,45,46,47,48,92,93
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(5/7) : GFX/PWR
Custom
8 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(5/7) : GFX/PWR
Custom
8 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(5/7) : GFX/PWR
Custom
8 103Wednesday, March 14, 2012
<Core Design>
33A
B4:VREF_DQ CHA
D1:VREF_DQ CHB
6A
SNB: No Connect
IVB: VSS
1.0V
1.05V
H_VCCP_SEL Voltage
0
1
S3 Power Reduction Circuit Processor VREF_DQ Implementation
12~16A
IVY BRIDGE PROCESSOR (GRAPHICS POWER)
33OU*1 10U*6
CPU(5/7)
R0801 need be close to pin H23.
CAD Note: +V_SM_VREF should
have 10 mil trace width
1.5A
M3 - Processor Generated SO-DIMM VREF_DQ
Under Socket and Closed to CPU
Closed to CPU Socket
reserve PAD for ESD 20120112 PV-R
20120112 PV-R
20120112 PV-R
20120131PVR
1 2
R814
0R2J-2-GP
DY
R814
0R2J-2-GP
DY
1 2
R802
0R2J-2-GP
DY
R802
0R2J-2-GP
DY
12
R806
1KR2J-1-GP
R806
1KR2J-1-GP
12
C821
SC22U6D3V5MX-2GP
C821
SC22U6D3V5MX-2GP
12
D801
0R2J-2-GP
DY
D801
0R2J-2-GP
DY
SM_VREF AL1
VSSAXG_SENSE AK34
VAXG_SENSE AK35
VAXG1
AT24
VAXG2
AT23
VAXG3
AT21
VAXG4
AT20
VAXG5
AT18
VAXG6
AT17
VAXG7
AR24
VAXG8
AR23
VAXG9
AR21
VAXG10
AR20
VAXG11
AR18
VAXG12
AR17
VAXG13
AP24
VAXG14
AP23
VAXG15
AP21
VAXG16
AP20
VAXG17
AP18
VAXG18
AP17
VAXG19
AN24
VAXG20
AN23
VAXG21
AN21
VAXG22
AN20
VAXG23
AN18
VAXG24
AN17
VAXG25
AM24
VAXG26
AM23
VAXG27
AM21
VAXG28
AM20
VAXG29
AM18
VAXG30
AM17
VAXG31
AL24
VAXG32
AL23
VAXG33
AL21
VAXG34
AL20
VAXG35
AL18
VAXG36
AL17
VAXG37
AK24
VAXG38
AK23
VAXG39
AK21
VAXG40
AK20
VAXG41
AK18
VAXG42
AK17
VAXG43
AJ24
VAXG44
AJ23
VAXG45
AJ21
VAXG46
AJ20
VAXG47
AJ18
VAXG48
AJ17
VAXG49
AH24
VAXG50
AH23
VAXG51
AH21
VAXG52
AH20
VAXG53
AH18
VAXG54
AH17
VDDQ11 U4
VDDQ12 U1
VDDQ13 P7
VDDQ14 P4
VDDQ15 P1
VDDQ1 AF7
VDDQ2 AF4
VDDQ3 AF1
VDDQ4 AC7
VDDQ5 AC4
VDDQ6 AC1
VDDQ7 Y7
VDDQ8 Y4
VDDQ9 Y1
VDDQ10 U7
VCCPLL1
B6
VCCPLL2
A6
VCCSA1 M27
VCCSA2 M26
VCCSA3 L26
VCCSA4 J26
VCCSA5 J25
VCCSA6 J24
VCCSA7 H26
VCCSA8 H25
VCCSA_SENSE H23
VCCSA_VID1 C24
VCCPLL3
A2 VCCSA_VID0 C22
SA_DIMM_VREFDQ B4
SB_DIMM_VREFDQ D1
VCCIO_SEL A19
GRAPHICS
DDR3 -1.5V RAILS SENSE
LINES
1.8V RAIL
SA RAIL
VREFMISC
7 OF 9
POWER
IVY-BRIDGE
CPU1G
GRAPHICS
DDR3 -1.5V RAILS SENSE
LINES
1.8V RAIL
SA RAIL
VREFMISC
7 OF 9
POWER
IVY-BRIDGE
CPU1G
12
C817
SC1U10V2KX-1GP
C817
SC1U10V2KX-1GP
1 2
R810
0R2J-2-GP
DY
R810
0R2J-2-GP
DY
12
C808
SC10U6D3V5KX-1GP
C808
SC10U6D3V5KX-1GP
12
C805
SC10U6D3V5KX-1GP
C805
SC10U6D3V5KX-1GP
12
R804
1KR2J-1-GP
R804
1KR2J-1-GP
12
C819
SC10U6D3V5KX-1GP
DY
C819
SC10U6D3V5KX-1GP
DY
12
C814
SC10U6D3V5KX-1GP
C814
SC10U6D3V5KX-1GP
1 2
R818
0R2J-2-GP
DY
R818
0R2J-2-GP
DY
1 2
R807
0R0402-PAD
R807
0R0402-PAD
1 2
R819
100R2F-L1-GP-U
R819
100R2F-L1-GP-U
12
C820
SC22U6D3V5MX-2GP
C820
SC22U6D3V5MX-2GP
12
C803
SC10U6D3V3MX-GP
C803
SC10U6D3V3MX-GP
G
D S
Q802
AP2302GN-HF-GP
2nd = 84.00138.F31
3rd = 84.05067.031
1st = 84.05067.031
Q802
AP2302GN-HF-GP
2nd = 84.00138.F31
3rd = 84.05067.031
1st = 84.05067.031
12
TC802
SE330U2D5VDM-1GP
2ND = 79.33719.L01
DY
1st = 77.23371.13L
TC802
SE330U2D5VDM-1GP
2ND = 79.33719.L01
DY
1st = 77.23371.13L
12
R822
1KR2F-3-GP
DY
R822
1KR2F-3-GP
DY
12
C816
SC10U6D3V5KX-1GP
C816
SC10U6D3V5KX-1GP
1 2
R823 0R0402-PADR823 0R0402-PAD
G
D S
Q801
DMN5L06K-7-GP
84.05067.031
2ND = 84.07002.I31
3rd = 84.2N702.W31
1st = 84.2N702.J31
Q801
DMN5L06K-7-GP
84.05067.031
2ND = 84.07002.I31
3rd = 84.2N702.W31
1st = 84.2N702.J31
G
DS
Q803
AP2302GN-HF-GP
2nd = 84.00138.F31
3rd = 84.05067.031
1st = 84.05067.031
Q803
AP2302GN-HF-GP
2nd = 84.00138.F31
3rd = 84.05067.031
1st = 84.05067.031
12
C827
SC22U6D3V5MX-2GP
C827
SC22U6D3V5MX-2GP
1 2
C832
SC470P50V2KX-3GP
DY
C832
SC470P50V2KX-3GP
DY
1 2
R811
0R2J-2-GP
DY
R811
0R2J-2-GP
DY
12
C802
SC2D2U10V3ZY-1GP
DY
C802
SC2D2U10V3ZY-1GP
DY
12
C828
SC22U6D3V5MX-2GP
C828
SC22U6D3V5MX-2GP
12
R801
100R2J-2-GP
DY
R801
100R2J-2-GP
DY
12
C815
SC10U6D3V5KX-1GP
C815
SC10U6D3V5KX-1GP
12
C823
SC10U6D3V5KX-1GP
C823
SC10U6D3V5KX-1GP
12
C801
SCD1U16V2ZY-2GP
DY
C801
SCD1U16V2ZY-2GP
DY
12
C830
SC22U6D3V5MX-2GP
C830
SC22U6D3V5MX-2GP
12
R821
1KR2F-3-GP
DY
R821
1KR2F-3-GP
DY
12
C807
SC10U6D3V5KX-1GP
C807
SC10U6D3V5KX-1GP
12
C818
SC1U10V2KX-1GP
C818
SC1U10V2KX-1GP
12
C831
SC22U6D3V5MX-2GP
C831
SC22U6D3V5MX-2GP
12
C822
SC22U6D3V5MX-2GP
C822
SC22U6D3V5MX-2GP
12
C829
SC22U6D3V5MX-2GP
C829
SC22U6D3V5MX-2GP
1 2 R820
100R2F-L1-GP-U
R820
100R2F-L1-GP-U
12
R803
100KR2J-1-GP
R803
100KR2J-1-GP
12
R817
0R2J-2-GP
DY
R817
0R2J-2-GP
DY
12
R815
1KR2F-3-GP
DY
R815
1KR2F-3-GP
DY
12
C825
SC22U6D3V5MX-2GP
C825
SC22U6D3V5MX-2GP
12
TC803
ST330U2D5VBM-1-GP
80.3371V.A2L
2nd = 77.22771.00L
TC803
ST330U2D5VBM-1-GP
80.3371V.A2L
2nd = 77.22771.00L
12
C826
SC10U6D3V5KX-1GP
C826
SC10U6D3V5KX-1GP
12
C813
SC10U6D3V5KX-1GP
C813
SC10U6D3V5KX-1GP
12
C806
SC10U6D3V5KX-1GP
C806
SC10U6D3V5KX-1GP
12
R816
1KR2F-3-GP
DY
R816
1KR2F-3-GP
DY
12
C804
SC10U6D3V3MX-GP
C804
SC10U6D3V3MX-GP
12
D802
0R2J-2-GP
DY
D802
0R2J-2-GP
DY
12
C824
SC22U6D3V5MX-2GP
C824
SC22U6D3V5MX-2GP
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(6/7) : GND
A3
9 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(6/7) : GND
A3
9 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(6/7) : GND
A3
9 103Wednesday, March 14, 2012
<Core Design>
IVY BRIDGE PROCESSOR (GND)
CPU(6/7)
VSS161
T35
VSS162
T34
VSS163
T33
VSS164
T32
VSS165
T31
VSS166
T30
VSS167
T29
VSS168
T28
VSS169
T27
VSS170
T26
VSS171
P9
VSS172
P8
VSS173
P6
VSS174
P5
VSS175
P3
VSS176
P2
VSS177
N35
VSS178
N34
VSS179
N33
VSS180
N32
VSS181
N31
VSS182
N30
VSS183
N29
VSS184
N28
VSS185
N27
VSS186
N26
VSS187
M34
VSS188
L33
VSS189
L30
VSS190
L27
VSS191
L9
VSS192
L8
VSS193
L6
VSS194
L5
VSS195
L4
VSS196
L3
VSS197
L2
VSS198
L1
VSS199
K35
VSS200
K32
VSS201
K29
VSS202
K26
VSS203
J34
VSS204
J31
VSS205
H33
VSS206
H30
VSS207
H27
VSS208
H24
VSS209
H21
VSS210
H18
VSS211
H15
VSS212
H13
VSS213
H10
VSS214
H9
VSS215
H8
VSS216
H7
VSS217
H6
VSS218
H5
VSS219
H4
VSS220
H3
VSS221
H2
VSS222
H1
VSS223
G35
VSS224
G32
VSS225
G29
VSS226
G26
VSS227
G23
VSS228
G20
VSS229
G17
VSS230
G11
VSS231
F34
VSS232
F31
VSS233
F29
VSS234 F22
VSS235 F19
VSS236 E30
VSS237 E27
VSS238 E24
VSS239 E21
VSS240 E18
VSS241 E15
VSS242 E13
VSS243 E10
VSS244 E9
VSS245 E8
VSS246 E7
VSS247 E6
VSS248 E5
VSS249 E4
VSS250 E3
VSS251 E2
VSS252 E1
VSS253 D35
VSS254 D32
VSS255 D29
VSS256 D26
VSS257 D20
VSS258 D17
VSS259 C34
VSS260 C31
VSS261 C28
VSS262 C27
VSS263 C25
VSS264 C23
VSS265 C10
VSS266 C1
VSS267 B22
VSS268 B19
VSS269 B17
VSS270 B15
VSS271 B13
VSS272 B11
VSS273 B9
VSS274 B8
VSS275 B7
VSS276 B5
VSS277 B3
VSS278 B2
VSS279 A35
VSS280 A32
VSS281 A29
VSS282 A26
VSS283 A23
VSS284 A20
VSS285 A3
VSS
9 OF 9
IVY-BRIDGE
CPU1I
VSS
9 OF 9
IVY-BRIDGE
CPU1I
VSS1
AT35
VSS2
AT32
VSS3
AT29
VSS4
AT27
VSS5
AT25
VSS6
AT22
VSS7
AT19
VSS8
AT16
VSS9
AT13
VSS10
AT10
VSS11
AT7
VSS12
AT4
VSS13
AT3
VSS14
AR25
VSS15
AR22
VSS16
AR19
VSS17
AR16
VSS18
AR13
VSS19
AR10
VSS20
AR7
VSS21
AR4
VSS22
AR2
VSS23
AP34
VSS24
AP31
VSS25
AP28
VSS26
AP25
VSS27
AP22
VSS28
AP19
VSS29
AP16
VSS30
AP13
VSS31
AP10
VSS32
AP7
VSS33
AP4
VSS34
AP1
VSS35
AN30
VSS36
AN27
VSS37
AN25
VSS38
AN22
VSS39
AN19
VSS40
AN16
VSS41
AN13
VSS42
AN10
VSS43
AN7
VSS44
AN4
VSS45
AM29
VSS46
AM25
VSS47
AM22
VSS48
AM19
VSS49
AM16
VSS50
AM13
VSS51
AM10
VSS52
AM7
VSS53
AM4
VSS54
AM3
VSS55
AM2
VSS56
AM1
VSS57
AL34
VSS58
AL31
VSS59
AL28
VSS60
AL25
VSS61
AL22
VSS62
AL19
VSS63
AL16
VSS64
AL13
VSS65
AL10
VSS66
AL7
VSS67
AL4
VSS68
AL2
VSS69
AK33
VSS70
AK30
VSS71
AK27
VSS72
AK25
VSS73
AK22
VSS74
AK19
VSS75
AK16
VSS76
AK13
VSS77
AK10
VSS78
AK7
VSS79
AK4
VSS80
AJ25
VSS81 AJ22
VSS82 AJ19
VSS83 AJ16
VSS84 AJ13
VSS85 AJ10
VSS86 AJ7
VSS87 AJ4
VSS88 AJ3
VSS89 AJ2
VSS90 AJ1
VSS91 AH35
VSS92 AH34
VSS93 AH32
VSS94 AH30
VSS95 AH29
VSS96 AH28
VSS98 AH25
VSS99 AH22
VSS100 AH19
VSS101 AH16
VSS102 AH7
VSS103 AH4
VSS104 AG9
VSS105 AG8
VSS106 AG4
VSS107 AF6
VSS108 AF5
VSS109 AF3
VSS110 AF2
VSS111 AE35
VSS112 AE34
VSS113 AE33
VSS114 AE32
VSS115 AE31
VSS116 AE30
VSS117 AE29
VSS118 AE28
VSS119 AE27
VSS120 AE26
VSS121 AE9
VSS122 AD7
VSS123 AC9
VSS124 AC8
VSS125 AC6
VSS126 AC5
VSS127 AC3
VSS128 AC2
VSS129 AB35
VSS130 AB34
VSS131 AB33
VSS132 AB32
VSS133 AB31
VSS134 AB30
VSS135 AB29
VSS136 AB28
VSS137 AB27
VSS138 AB26
VSS139 Y9
VSS140 Y8
VSS141 Y6
VSS142 Y5
VSS143 Y3
VSS144 Y2
VSS145 W35
VSS146 W34
VSS147 W33
VSS148 W32
VSS149 W31
VSS150 W30
VSS151 W29
VSS152 W28
VSS153 W27
VSS154 W26
VSS155 U9
VSS156 U8
VSS157 U6
VSS158 U5
VSS159 U3
VSS160 U2
VSS
8 OF 9
IVY-BRIDGE
CPU1H
VSS
8 OF 9
IVY-BRIDGE
CPU1H
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC_VAL_SENSE
VCC_DIE_SENSE
VSS_VAL_SENSE
CFG6
CFG4
CFG5
CFG2
CFG7
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
CFG2
CFG4
CFG5
CFG6
CFG7
CLK_XDP_ITP_P
CLK_XDP_ITP_N
VCC_CORE
VCC_GFXCORE
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(7/7): CFG/RSVD/DDR3_VREF
A3
10 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(7/7): CFG/RSVD/DDR3_VREF
A3
10 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU(7/7): CFG/RSVD/DDR3_VREF
A3
10 103Wednesday, March 14, 2012
<Core Design>
0:Enable eDP
PEG Static Lane Reversal
1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed
CFG2
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
IVY BRIDGE PROCESSOR (RESERVED)
Display Port Presence Strap
1:(Default) Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG4
CFG[6:5] 11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PCIE Port Bifurcation Straps
CFG7
PEG DEFER TRAINING
CPU(7/7)
12
R1009
1KR2J-1-GP
DY
R1009
1KR2J-1-GP
DY
1
TP1004 TPAD14-OP-GPTP1004 TPAD14-OP-GP
12
R1005
1KR2J-1-GP
R1005
1KR2J-1-GP
12
R1007
1KR2J-1-GP
DY
R1007
1KR2J-1-GP
DY
1
TP1024 TPAD14-OP-GPTP1024 TPAD14-OP-GP
1
TP1025 TPAD14-OP-GPTP1025 TPAD14-OP-GP
12
R1008
1KR2J-1-GP
DY
R1008
1KR2J-1-GP
DY
1 2
R100249D9R2F-GP
DY
R100249D9R2F-GP
DY
1 2
R100349D9R2F-GP
DY
R100349D9R2F-GP
DY
1 2
R100449D9R2F-GP
DY
R100449D9R2F-GP
DY
CFG0
AK28
CFG1
AK29
CFG2
AL26
CFG3
AL27
CFG4
AK26
CFG5
AL29
CFG6
AL30
CFG7
AM31
CFG8
AM32
CFG9
AM30
CFG10
AM28
CFG11
AM26
CFG12
AN28
CFG13
AN31
CFG14
AN26
CFG15
AM27
CFG16
AK31
CFG17
AN29
RSVD#AM33 AM33
RSVD#AJ27 AJ27
RSVD#J16 J16
RSVD_NCTF#AT34 AT34
RSVD#H16 H16
RSVD#G16 G16
RSVD_NCTF#AR35 AR35
RSVD_NCTF#AT33 AT33
RSVD_NCTF#AR34 AR34
RSVD_NCTF#AT2 AT2
RSVD_NCTF#AT1 AT1
RSVD_NCTF#AR1 AR1
RSVD_NCTF#B34 B34
RSVD_NCTF#A33 A33
RSVD_NCTF#A34 A34
RSVD_NCTF#B35 B35
RSVD_NCTF#C35 C35
RSVD#AJ32 AJ32
RSVD#AK32 AK32
RSVD#J15
J15
RSVD#C30
C30 RSVD#D23
D23
RSVD#A31
A31
RSVD#B30
B30
RSVD#D30
D30 RSVD#B29
B29
RSVD#A30
A30 RSVD#B31
B31
RSVD#C29
C29
RSVD#T8 T8
RSVD#F25
F25
RSVD#F24
F24
RSVD#D24
D24
RSVD#G25
G25
RSVD#G24
G24
RSVD#E23
E23
RSVD#W8 W8
RSVD#AT26 AT26
RSVD_NCTF#AP35 AP35
RSVD#F23
F23
RSVD#AJ26
AJ26
VAXG_VAL_SENSE
AJ31
VSSAXG_VAL_SENSE
AH31
VCC_VAL_SENSE
AJ33
VSS_VAL_SENSE
AH33
VCC_DIE_SENSE AH27
BCLK_ITP AN35
BCLK_ITP# AM35
VSS_DIE_SENSE AH26
RSVD#AK2 AK2
RSVD#AE7 AE7
RSVD#AG7 AG7
RSVD#L7 L7
RSVD#J20
J20
RSVD#B18
B18
RESERVED
CFG
5 OF 9
IVY-BRIDGE
CPU1E
RESERVED
CFG
5 OF 9
IVY-BRIDGE
CPU1E
1 2
R100149D9R2F-GP
DY
R100149D9R2F-GP
DY
12
R1006
1KR2J-1-GP
DY
R1006
1KR2J-1-GP
DY
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU_XDP
A3
11 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU_XDP
A3
11 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
CPU_XDP
A3
11 103Wednesday, March 14, 2012
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
RESERVED
A3
12 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
RESERVED
A3
12 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
RESERVED
A3
12 103Wednesday, March 14, 2012
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
RESERVED
A3
13 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
RESERVED
A3
13 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
RESERVED
A3
13 103Wednesday, March 14, 2012
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M_VREF_DQ_DIMM0
M_VREF_CA_DIMM0
TS#_DIMM0_1
SA0_DIM0
SA1_DIM0
M_A_A1
M_A_DQS#0
M_A_DQ43
M_A_DQ42
M_A_DQ41
M_A_DQ40
M_A_DQ13
M_A_DQ12
M_A_DQ14
M_A_DQ15
M_A_DQS3
M_A_DQ0
M_A_A2
M_A_DQS#5
M_A_DQ44
SA0_DIM0
M_A_DQ47
M_A_DQ46
M_A_DQ45
M_A_DQ19
M_A_DQ18
M_A_DQ17
M_A_DQ16
SODIMM1_1_SMB_CLK_R
M_A_DQS4
M_A_A3
M_A_DQS#6
M_A_DQ50
M_A_DQ49
M_A_DQ48
M_A_DQ51
M_A_DQ23
M_A_DQ22
M_A_DQ21
M_A_DQ20
SA1_DIM0
M_A_A4
M_A_DQ1
M_A_DQS5
M_A_DQ53
M_A_DQ52
M_A_DQS#7
M_A_DQ24
M_A_DQ55
M_A_DQ54
M_A_DQ27
M_A_DQ26
M_A_DQ25
M_A_DQS#1
M_A_DQ2
M_A_A5
M_A_DQS6
M_A_DQ59
M_A_DQ58
M_A_DQ57
M_A_DQ56
M_A_DQ30
M_A_DQ29
M_A_DQ28
M_A_DQS0
M_A_DQ31
M_A_A9
M_A_A8
M_A_A7
M_A_A6
M_A_A11
M_A_A10
M_A_DQ3
M_A_DQS#2
M_A_DQS7
M_A_DQ62
M_A_DQ61
M_A_DQ60
M_A_DQ32
M_A_DQ63
M_A_DQ35
M_A_DQ34
M_A_DQ33
M_A_A13
M_A_DQS1
M_A_A12
M_A_A15
M_A_A14
M_A_DQ7
M_A_DQ6
M_A_DQ5
M_A_DQ4
M_A_DQS#3
M_VREF_CA_DIMM0
M_A_A0
M_A_DQ38
M_A_DQ37
M_A_DQ36
M_A_DQ39
SODIMM1_1_SMB_DATA_R
M_A_DQ8
M_A_DQ11
M_A_DQ10
M_A_DQ9
M_A_DQS2
M_A_DQS#4
1D5V_S3
1D5V_S3
3D3V_S0
0D75V_S0
3D3V_S0
0D75V_S0
1D5V_S3
1D5V_S3
DDR_VREF_S3
DDR_VREF_S3
M_A_WE# 6
DDR3_DRAMRST#5,15,97
M_A_CAS# 6
M_A_DIM0_CS#0 6
M_A_DIM0_CKE0 6
M_A_DIM0_ODT16 M_A_DIM0_ODT06
M_A_DIM0_CLK_DDR#0 6
M_A_DIM0_CLK_DDR0 6
M_A_DIM0_CS#1 6
M_A_DIM0_CKE1 6
PCH_SMBDATA 15,18,31,65
M_A_DIM0_CLK_DDR#1 6
M_A_DIM0_CLK_DDR1 6
M_A_BS16 M_A_BS06
M_A_BS26
M_A_DQS#[7:0] 6
PCH_SMBCLK 15,18,31,65
M_A_RAS# 6
TS#_DIMM0_1 15
M_A_A[15:0] 6
M_A_DQS[7:0] 6
M_A_DQ[63:0]6
M_VREF_DQ_DIMM08
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
DDR3 SO-DIMM1
Custom
14 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
DDR3 SO-DIMM1
Custom
14 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
DDR3 SO-DIMM1
Custom
14 103Wednesday, March 14, 2012
<Core Design>
H=9.2mm
DIMM1
Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30
If SA0 DIM0 = 1, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA2
SO-DIMMA TS Address is 0x32
SODIMM A DECOUPLING
Layout Note:
Place these Caps near
SO-DIMMA.
Place these caps
close to VTT1 and
VTT2.
Thermal EVENT
Bom Not: 1st/2nd/3rd Add in BOM
12
C1419
SC1U10V2KX-1GP
C1419
SC1U10V2KX-1GP
12
C1409
SC10U6D3V5KX-1GP
C1409
SC10U6D3V5KX-1GP
12
R1406
1KR2F-3-GP
R1406
1KR2F-3-GP
12
C1416
SCD1U10V2KX-5GP
C1416
SCD1U10V2KX-5GP
A0
98
A1
97
A2
96
A3
95
A4
92
A5
91
A6
90
A7
86
A8
89
A9
85
A10/AP
107
A11
84
A12
83
A13
119
A14
80
A15
78
A16/BA2
79
BA0
109
BA1
108
DQ0
5
DQ1
7
DQ2
15
DQ3
17
DQ4
4
DQ5
6
DQ6
16
DQ7
18
DQ8
21
DQ9
23
DQ10
33
DQ11
35
DQ12
22
DQ13
24
DQ14
34
DQ15
36
DQ16
39
DQ17
41
DQ18
51
DQ19
53
DQ20
40
DQ21
42
DQ22
50
DQ23
52
DQ24
57
DQ25
59
DQ26
67
DQ27
69
DQ28
56
DQ29
58
DQ30
68
DQ31
70
DQ32
129
DQ33
131
DQ34
141
DQ35
143
DQ36
130
DQ37
132
DQ38
140
DQ39
142
DQ40
147
DQ41
149
DQ42
157
DQ43
159
DQ44
146
DQ45
148
DQ46
158
DQ47
160
DQ48
163
DQ49
165
DQ50
175
DQ51
177
DQ52
164
DQ53
166
DQ54
174
DQ55
176
DQ56
181
DQ57
183
DQ58
191
DQ59
193
DQ60
180
DQ61
182
DQ62
192
DQ63
194
DQS0#
10
DQS1#
27
DQS2#
45
DQS3#
62
DQS4#
135
DQS5#
152
DQS6#
169
DQS7#
186
DQS0
12
DQS1
29
DQS2
47
DQS3
64
DQS4
137
DQS5
154
DQS6
171
DQS7
188
ODT0
116
ODT1
120
VREF_DQ
1
VSS 2
NP1 NP1
NP2 NP2
RAS# 110
WE# 113
CAS# 115
CS0# 114
CS1# 121
CKE0 73
CKE1 74
CK0 101
CK0# 103
CK1 102
CK1# 104
DM0 11
DM1 28
DM2 46
DM3 63
DM4 136
DM5 153
DM6 170
DM7 187
SDA 200
SCL 202
VDDSPD 199
SA0 197
SA1 201
VREF_CA
126
VDD 124
NC#77 77
NC#122 122
NC#125/TEST 125
VDD 81
VDD 82
VDD 87
VDD 88
VDD 93
VDD 94
VDD 99
VDD 100
VDD 111
VDD 112
VDD 117
VDD 118
VSS 3
VSS 8
VSS 9
VSS 13
VSS 14
VSS 19
VSS 20
VSS 25
VSS 26
VSS 31
VSS 32
VSS 37
VSS 38
VSS 43
VSS 44
VSS 48
VSS 49
VSS 54
VSS 55
VSS 60
VSS 61
VDD 75
VSS 65
VSS 66
VSS 71
VSS 72
VDD 76
VDD 105
VDD 106
VDD 123
VSS 127
VSS 128
VSS 134
VSS 133
VSS 138
VSS 139
VSS 144
VSS 145
VSS 151
VSS 150
VSS 155
VSS 156
VSS 161
VSS 162
VSS 167
VSS 168
VSS 173
VSS 172
VSS 179
VSS 178
VSS 185
VSS 184
VSS 189
VSS 190
VSS 195
VSS 196
RESET#
30
EVENT# 198
VSS 205
VSS 206
VTT1
203
VTT2
204
DIMM1
DDR3-204P-168-GP
2nd = 62.10017.U01
3rd = 62.10024.H81
1st = 62.10024.I91
DIMM1
DDR3-204P-168-GP
2nd = 62.10017.U01
3rd = 62.10024.H81
1st = 62.10024.I91
12
C1411
SC10U6D3V5KX-1GP
C1411
SC10U6D3V5KX-1GP
1
23
4
RN1402
SRN10KJ-5-GP
RN1402
SRN10KJ-5-GP
12
C1413
SCD1U10V2KX-5GP
C1413
SCD1U10V2KX-5GP
12
R1405
1KR2F-3-GP
R1405
1KR2F-3-GP
12
C1403
SCD1U10V2KX-4GP
C1403
SCD1U10V2KX-4GP
12
C1405
SCD1U10V2KX-4GP
C1405
SCD1U10V2KX-4GP
12
R1401
0R2J-2-GP
DY
R1401
0R2J-2-GP
DY
12
C1410
SC10U6D3V5KX-1GP
C1410
SC10U6D3V5KX-1GP
12
C1421
SC1U6D3V2KX-GP
C1421
SC1U6D3V2KX-GP
12
C1408
SC10U6D3V5KX-1GP
C1408
SC10U6D3V5KX-1GP
12
R1407
1KR2F-3-GP
R1407
1KR2F-3-GP
12
C1406
SC2D2U10V3ZY-1GP
DY
C1406
SC2D2U10V3ZY-1GP
DY
12
C1420
SC1U6D3V2KX-GP
C1420
SC1U6D3V2KX-GP
1
2 3
4
RN
0R4P2R-PADRN1401
RN
0R4P2R-PADRN1401
12
C1407
SC10U6D3V5KX-1GP
C1407
SC10U6D3V5KX-1GP
12
R1402
10KR2J-3-GP
R1402
10KR2J-3-GP
12
C1402
SC2D2U6D3V3KX-GP
C1402
SC2D2U6D3V3KX-GP
12
C1415
SCD1U10V2KX-5GP
C1415
SCD1U10V2KX-5GP
12
C1417
SC1U10V2KX-1GP
C1417
SC1U10V2KX-1GP
12
C1422
SC1U6D3V2KX-GP
DY
C1422
SC1U6D3V2KX-GP
DY
12
C1423
SC1U6D3V2KX-GP
DY
C1423
SC1U6D3V2KX-GP
DY
12
C1414
SCD1U10V2KX-5GP
C1414
SCD1U10V2KX-5GP
12
C1412
SC10U6D3V5KX-1GP
C1412
SC10U6D3V5KX-1GP
12
C1401
SCD1U16V2ZY-2GP
C1401
SCD1U16V2ZY-2GP
12
R1403
1KR2F-3-GP
R1403
1KR2F-3-GP
12
C1404
SC2D2U6D3V3KX-GP
DY
C1404
SC2D2U6D3V3KX-GP
DY
12
C1418
SC1U10V2KX-1GP
C1418
SC1U10V2KX-1GP
12
R809
0R2J-2-GP
DY
R809
0R2J-2-GP
DY
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M_VREF_DQ_DIMM1
M_VREF_CA_DIMM1
M_B_A1
M_B_DQ42
M_B_DQ41
M_B_DQ40
M_B_DQS#0
M_B_DQ43
M_B_DQ14
M_B_DQ13
M_B_DQ12
M_B_DQ15
M_B_DQS3
M_B_DQ0
M_B_A2
M_B_DQS#5
SB0_DIM0
M_B_DQ46
M_B_DQ45
M_B_DQ44
M_B_DQ47
M_B_DQ19
M_B_DQ18
M_B_DQ17
M_B_DQ16
M_B_DQS4
M_B_A3
M_B_DQS#6
M_B_DQ51
M_B_DQ50
M_B_DQ49
M_B_DQ48
M_B_DQ23
M_B_DQ22
M_B_DQ21
M_B_DQ20
SB1_DIM0
M_B_DQ1
M_B_A4
M_B_DQS5
M_B_DQS#7
M_B_DQ53
M_B_DQ52
M_B_DQ24
M_B_DQ55
M_B_DQ54
M_B_DQ27
M_B_DQ26
M_B_DQ25
M_B_DQS#1
M_B_DQ2
M_B_A5
M_B_DQS6
M_B_DQ57
M_B_DQ56
M_B_DQS0
M_B_DQ59
M_B_DQ58
M_B_DQ31
M_B_DQ30
M_B_DQ29
M_B_DQ28
M_B_A7
M_B_A6
M_B_A11
M_B_A10
M_B_A9
M_B_A8
M_B_DQ3
M_B_DQS#2
M_B_DQS7
M_B_DQ63
M_B_DQ62
M_B_DQ61
M_B_DQ60
M_B_DQ33
M_B_DQ32
M_B_DQ35
M_B_DQ34
M_B_DQS1
M_B_A12
M_B_A15
M_B_A14
M_B_A13
M_B_DQ5
M_B_DQ4
M_B_DQ7
M_B_DQ6
M_B_DQS#3
M_VREF_CA_DIMM1
M_B_A0
M_B_DQ39
M_B_DQ38
M_B_DQ37
M_B_DQ36
M_B_DQ8
M_B_DQ11
M_B_DQ10
M_B_DQ9
M_B_DQS2
SODIMM0_1_SMB_CLK_R
SODIMM0_1_SMB_DATA_R
M_B_DQS#4
SB1_DIM0
SB0_DIM0
1D5V_S3
1D5V_S3
0D75V_S0
1D5V_S3
3D3V_S0
1D5V_S3
3D3V_S0
DDR_VREF_S3
DDR_VREF_S3
M_B_WE# 6
M_B_DIM0_CS#0 6
DDR3_DRAMRST#5,14,97
M_B_CAS# 6
M_B_DIM0_ODT06 M_B_DIM0_ODT16
M_B_DIM0_CKE0 6
M_B_DIM0_CKE1 6
M_B_DIM0_CS#1 6
M_B_DIM0_CLK_DDR0 6
M_B_DIM0_CLK_DDR#0 6
M_B_DIM0_CLK_DDR1 6
M_B_DIM0_CLK_DDR#1 6
M_B_BS06
M_B_BS26
M_B_BS16
M_B_RAS# 6
M_B_DQS[7:0]6
M_B_A[15:0]6
M_B_DQS#[7:0]6
TS#_DIMM0_1 14
PCH_SMBDATA 14,18,31,65
PCH_SMBCLK 14,18,31,65
M_B_DQ[63:0]6
M_VREF_DQ_DIMM18
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
DDR3 SO-DIMM2
Custom
15 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
DDR3 SO-DIMM2
Custom
15 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
DDR3 SO-DIMM2
Custom
15 103Wednesday, March 14, 2012
<Core Design>
SODIMM B DECOUPLING
Layout Note:
Place these Caps near
SO-DIMMB.
H=5.2mm
Note:
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34
DIMM2
Place these caps
close to VTT1 and
VTT2.
12
C1501
SC1U6D3V2KX-GP
C1501
SC1U6D3V2KX-GP
1
2 3
4
RN
0R4P2R-PADRN1501
RN
0R4P2R-PADRN1501
12
C1517
SCD1U10V2KX-5GP
C1517
SCD1U10V2KX-5GP
12
R1506
1KR2F-3-GP
R1506
1KR2F-3-GP
12
R1508
1KR2F-3-GP
R1508
1KR2F-3-GP
12
C1519
SCD1U10V2KX-5GP
C1519
SCD1U10V2KX-5GP
12
C1522
SC1U10V2KX-1GP
C1522
SC1U10V2KX-1GP
12
C1504
SCD1U16V2ZY-2GP
C1504
SCD1U16V2ZY-2GP
12
C1508
SC10U6D3V5KX-1GP
C1508
SC10U6D3V5KX-1GP
12
TC1401
SE330U2D5VDM-1GP
2ND = 79.33719.L01
1st = 77.23371.13L
3rd = 77.23371.13L
TC1401
SE330U2D5VDM-1GP
2ND = 79.33719.L01
1st = 77.23371.13L
3rd = 77.23371.13L
12
C1509
SC10U6D3V5KX-1GP
C1509
SC10U6D3V5KX-1GP
12
C1523
SC1U6D3V2KX-GP
C1523
SC1U6D3V2KX-GP
12
C1502
SC1U6D3V2KX-GP
DY
C1502
SC1U6D3V2KX-GP
DY
1
2 3
4
RN1502
SRN10KJ-5-GP
RN1502
SRN10KJ-5-GP
12
C1518
SCD1U10V2KX-5GP
C1518
SCD1U10V2KX-5GP
12
R1507
1KR2F-3-GP
R1507
1KR2F-3-GP
12
C1505
SC2D2U10V3ZY-1GP
DY
C1505
SC2D2U10V3ZY-1GP
DY
12
C1510
SC10U6D3V5KX-1GP
C1510
SC10U6D3V5KX-1GP
12
C1506
SCD1U10V2KX-4GP
C1506
SCD1U10V2KX-4GP
A0
98
A1
97
A2
96
A3
95
A4
92
A5
91
A6
90
A7
86
A8
89
A9
85
A10/AP
107
A11
84
A12
83
A13
119
A14
80
A15
78
A16/BA2
79
BA0
109
BA1
108
DQ0
5
DQ1
7
DQ2
15
DQ3
17
DQ4
4
DQ5
6
DQ6
16
DQ7
18
DQ8
21
DQ9
23
DQ10
33
DQ11
35
DQ12
22
DQ13
24
DQ14
34
DQ15
36
DQ16
39
DQ17
41
DQ18
51
DQ19
53
DQ20
40
DQ21
42
DQ22
50
DQ23
52
DQ24
57
DQ25
59
DQ26
67
DQ27
69
DQ28
56
DQ29
58
DQ30
68
DQ31
70
DQ32
129
DQ33
131
DQ34
141
DQ35
143
DQ36
130
DQ37
132
DQ38
140
DQ39
142
DQ40
147
DQ41
149
DQ42
157
DQ43
159
DQ44
146
DQ45
148
DQ46
158
DQ47
160
DQ48
163
DQ49
165
DQ50
175
DQ51
177
DQ52
164
DQ53
166
DQ54
174
DQ55
176
DQ56
181
DQ57
183
DQ58
191
DQ59
193
DQ60
180
DQ61
182
DQ62
192
DQ63
194
DQS0#
10
DQS1#
27
DQS2#
45
DQS3#
62
DQS4#
135
DQS5#
152
DQS6#
169
DQS7#
186
DQS0
12
DQS1
29
DQS2
47
DQS3
64
DQS4
137
DQS5
154
DQS6
171
DQS7
188
ODT0
116
ODT1
120
VREF_DQ
1
VSS 2
NP1 NP1
NP2 NP2
RAS# 110
WE# 113
CAS# 115
CS0# 114
CS1# 121
CKE0 73
CKE1 74
CK0 101
CK0# 103
CK1 102
CK1# 104
DM0 11
DM1 28
DM2 46
DM3 63
DM4 136
DM5 153
DM6 170
DM7 187
SDA 200
SCL 202
VDDSPD 199
SA0 197
SA1 201
VREF_CA
126
VDD18 124
NC#1 77
NC#2 122
NC#/TEST 125
VDD3 81
VDD4 82
VDD5 87
VDD6 88
VDD7 93
VDD8 94
VDD9 99
VDD10 100
VDD13 111
VDD14 112
VDD15 117
VDD16 118
VSS 3
VSS 8
VSS 9
VSS 13
VSS 14
VSS 19
VSS 20
VSS 25
VSS 26
VSS 31
VSS 32
VSS 37
VSS 38
VSS 43
VSS 44
VSS 48
VSS 49
VSS 54
VSS 55
VSS 60
VSS 61
VDD1 75
VSS 65
VSS 66
VSS 71
VSS 72
VDD2 76
VDD11 105
VDD12 106
VDD17 123
VSS 127
VSS 128
VSS 134
VSS 133
VSS 138
VSS 139
VSS 144
VSS 145
VSS 151
VSS 150
VSS 155
VSS 156
VSS 161
VSS 162
VSS 167
VSS 168
VSS 173
VSS 172
VSS 179
VSS 178
VSS 185
VSS 184
VSS 189
VSS 190
VSS 195
VSS 196
RESET#
30
EVENT# 198
VSS 205
VSS 206
VTT1
203
VTT2
204
DIMM2
DDR3-204P-85-GP-U
62.10017.U21
3rd = 62.10024.I61
2nd = 62.10017.T91
DIMM2
DDR3-204P-85-GP-U
62.10017.U21
3rd = 62.10024.I61
2nd = 62.10017.T91
12
C1521
SC1U10V2KX-1GP
C1521
SC1U10V2KX-1GP
12
C1514
SCD1U10V2KX-4GP
C1514
SCD1U10V2KX-4GP
12
C1516
SCD1U10V2KX-5GP
C1516
SCD1U10V2KX-5GP
12
C1515
SC2D2U10V3ZY-1GP
DY
C1515
SC2D2U10V3ZY-1GP
DY
12
C1511
SC10U6D3V5KX-1GP
C1511
SC10U6D3V5KX-1GP
12
R1509
1KR2F-3-GP
R1509
1KR2F-3-GP
12
R1501
0R2J-2-GP
DY
R1501
0R2J-2-GP
DY
12
C1507
SC2D2U6D3V3KX-GP
DY
C1507
SC2D2U6D3V3KX-GP
DY
12
C1512
SC10U6D3V5KX-1GP
C1512
SC10U6D3V5KX-1GP
12
C1503
SC1U6D3V2KX-GP
DY
C1503
SC1U6D3V2KX-GP
DY
12
C1520
SC1U10V2KX-1GP
C1520
SC1U10V2KX-1GP
12
C1513
SC10U6D3V5KX-1GP
C1513
SC10U6D3V5KX-1GP
12
R808
0R2J-2-GP
DY
R808
0R2J-2-GP
DY
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
RESERVED
A3
16 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
RESERVED
A3
16 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
RESERVED
A3
16 103Wednesday, March 14, 2012
<Core Design>
(Blanking)
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
HDA_SPKR
SRTC_RST#
RTC_PWR+RTC_VCC
RTC_X2
SATA_COMP
RBIAS_SATA3
HDA_BIT_CLK
RTC_X1
BAT_GRNLED#_S
PCH_JTAG_TMS
PCH_JTAG_TDO
PCH_JTAG_TDI
PLT_RST#_G
PCH_JTAG_TCK_BUF
PCH_INTVRMEN
HDA_SDO
PCH_HDA_SPKR
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
HDD_HALTLED_R
HDD_HALTLED_R
PCH_HDA_RST#
PCH_JTAG_TCK_BUF
PCH_JTAG_TDI
SIRQ
PCH_INTVRMEN PCH_GPIO23
BAT_GRNLED#_G
RTC_RST#
HDA_SYNC
HDA_SDO
HDA_SDO_R
BAT_GRNLED#_D
SATA3_COMP
SATA_LED#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#_R
HDA_SYNC
ISO_PREP#
ISO_PREP#
HDA_SYNC_C
HDA_SDO_G
HDA_SDO_G
HDA_SYNCHDA_SYNC_C
HDA_SDO HDA_SDO_R
PCH_JTAG_TMS
PCH_JTAG_TDO
RTC_X2
RTC_X1
+RTC_VCC
3D3V_S0
1D05V_S0
3D3V_AUX_S5 RTC_AUX_S5
RTC_AUX_S5
RTC_AUX_S5
RTC_AUX_S5
3D3V_S0
3D3V_S5
3D3V_S5
3D3V_S5
1D05V_S0
5V_S0
INTRUDER#54,97
PLT_RST#
5,21,32,34,53,54,56,71,83,96,97
BAT_GRNLED#27,82
SATA_TXN0 56
SATA_RXP0 56
SATA_RXN0 56
SATA_TXP0 56
LPC_AD[3:0] 27,71
HDA_SYNC_CODEC29
HDA_RST#_CODEC29,97
HDA_SDIN0_CODEC29
HDA_SDOUT_CODEC29,97
HDA_BITCLK_CODEC29,97
SIRQ 27,71
SATA_TXN1 56
SATA_RXP1 56
SATA_RXN1 56
SATA_TXP1 56
LPC_FRAME# 27,71
SATA_LED# 68
SATA0GP_GPIO21 22
PCH_SPI_MOSI60
PCH_SPI_CLK60
PCH_SPI_CS#060
PCH_SPI_MISO60 SATA_ODD_DET# 56
SPI_CS1#27,71
HDA_SPKR29
HDD_HALTLED68
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(1/9) : HDA/JTAG/SATA
A3
17 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(1/9) : HDA/JTAG/SATA
A3
17 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(1/9) : HDA/JTAG/SATA
A3
17 103Wednesday, March 14, 2012
<Core Design>
RTC Battery
NEED TO PLACE CLOSE TO PCH
HDD
NO REBOOT STRAP
PCH(1/9)
For Flash Descriptor Security Override HW strap
INTVRMEN- Integrated
SUS 1.05V VRM Enable
High - Enable internal VRs
ODD
No Reboot Strap R710
HDA_SPKR Low = Default
High = No Reboot
LAYOUT NOTE:
JTAG_TMS TERMINATIONS NEED TO BE PLACED NEAR PCH
JTAG_TDI TERMINATIONS NEED TO BE PLACED NEAR PCH
JTAG_TDO TERMINATIONS NEED TO BE PLACED NEAR XDP
JTAG_TCK TERMINATIONS NEED TO BE PLACED NEAR PCH
7pF20PPM
20120112 PV-R
20120210PV-R
20120312MV
20120314 MV
20120315 MV
1 2
R1727 1KR2J-1-GP
DY
R1727 1KR2J-1-GP
DY
12
C1703
SC6P50V2CN-1GP
C1703
SC6P50V2CN-1GP
1 2
R1713 37D4R2F-GPR1713 37D4R2F-GP
1 2
R1709 1MR2J-1-GPR1709 1MR2J-1-GP
1 2
R1726 22R2J-2-GPR1726 22R2J-2-GP
1 2
R1706
10MR2J-L-GP
R1706
10MR2J-L-GP
1 2
R1715 750R2F-GPR1715 750R2F-GP
1
2
3
4 5
6
7
8
RN1703
SRN100J-4-GP
PCHXDP
RN1703
SRN100J-4-GP
PCHXDP
1 2
R1717 210R2F-L-GP
PCHXDP
R1717 210R2F-L-GP
PCHXDP
PWR 1
GND 2
NP1 NP1
NP2 NP2
RTC1
BAT-060003HA002M213ZL-GP-U
62.70014.001
2nd = 62.70001.061
RTC1
BAT-060003HA002M213ZL-GP-U
62.70014.001
2nd = 62.70001.061
1 2
R1708
20KR2J-L2-GP
R1708
20KR2J-L2-GP
1 2
R1710 330KR2J-L1-GPR1710 330KR2J-L1-GP
12
C1702
SC6P50V2CN-1GP
C1702
SC6P50V2CN-1GP
1 2
R1714 49D9R2F-GPR1714 49D9R2F-GP
1 2
R1719 210R2F-L-GP
PCHXDP
R1719 210R2F-L-GP
PCHXDP
RTCX1
A20
RTCX2
C20
INTVRMEN
C17
INTRUDER#
K22
HDA_BCLK
N34
HDA_SYNC
L34
HDA_RST#
K34
HDA_SDIN0
E34
HDA_SDIN1
G34
HDA_SDIN2
C34
HDA_SDO
A36
SATALED# P3
FWH0/LAD0 C38
FWH1/LAD1 A38
FWH2/LAD2 B37
FWH3/LAD3 C37
LDRQ1#/GPIO23 K36
FWH4/LFRAME# D36
LDRQ0# E36
RTCRST#
D20
HDA_SDIN3
A34
HDA_DOCK_EN#/GPIO33
C36
HDA_DOCK_RST#/GPIO13
N32
SRTCRST#
G22
SATA0RXN AM3
SATA0RXP AM1
SATA0TXN AP7
SATA0TXP AP5
SATA1RXN AM10
SATA1RXP AM8
SATA1TXN AP11
SATA1TXP AP10
SATA2RXN AD7
SATA2RXP AD5
SATA2TXN AH5
SATA2TXP AH4
SATA3RXN AB8
SATA3RXP AB10
SATA3TXN AF3
SATA3TXP AF1
SATA4RXN Y7
SATA4RXP Y5
SATA4TXN AD3
SATA4TXP AD1
SATA5RXN Y3
SATA5RXP Y1
SATA5TXN AB3
SATA5TXP AB1
SATAICOMPI Y10
SPI_CLK
T3
SPI_CS0#
Y14
SPI_CS1#
T1
SPI_MOSI
V4
SPI_MISO
U3
SATA0GP/GPIO21 V14
SATA1GP/GPIO19 P1
JTAG_TCK
J3
JTAG_TMS
H7
JTAG_TDI
K5
JTAG_TDO
H1
SERIRQ V5
SPKR
T10
SATAICOMPO Y11
SATA3COMPI AB13
SATA3RCOMPO AB12
SATA3RBIAS AH1
RTCIHDA
SATA
LPC
SPI JTAG
SATA 6G
1 OF 10
PCH1A
PANTHER-GP-NF
RTCIHDA
SATA
LPC
SPI JTAG
SATA 6G
1 OF 10
PCH1A
PANTHER-GP-NF
1 2
R1705
20KR2J-L2-GP
R1705
20KR2J-L2-GP
1 2
R1720 1KR2J-1-GPR1720 1KR2J-1-GP
1 2
R1729 10KR2J-3-GPR1729 10KR2J-3-GP
1
2
3
4 5
6
7
8
RN1701
SRN33J-7-GP
RN1701
SRN33J-7-GP
1
2
3 4
5
6
U1704
2N7002KDW-GP
2nd = 84.2N702.E3F
84.2N702.A3F
3rd = 84.2N702.F3F
U1704
2N7002KDW-GP
2nd = 84.2N702.E3F
84.2N702.A3F
3rd = 84.2N702.F3F
12
C1704
SC1U10V2KX-1GP
C1704
SC1U10V2KX-1GP
G
D S
Q1701
BSS84-7-F-GP
2nd = 84.BSS84.B31
84.00084.F31
Q1701
BSS84-7-F-GP
2nd = 84.BSS84.B31
84.00084.F31
21
G1701
GAP-OPEN
G1701
GAP-OPEN
1 2
R1724 1KR2J-1-GPR1724 1KR2J-1-GP
12
C1705
SC1U10V3ZY-6GP
C1705
SC1U10V3ZY-6GP
1 2
R1701
10KR2J-3-GP
R1701
10KR2J-3-GP
1
2 3
4
RN1702
SRN10KJ-5-GP
RN1702
SRN10KJ-5-GP
1
TP1701 TPAD14-OP-GPTP1701 TPAD14-OP-GP
12
C1701
SC1U10V2KX-1GP
C1701
SC1U10V2KX-1GP
1 2
R1711
0R0402-PAD
R1711
0R0402-PAD
1
2 3
4
X1701
X-32D768KHZ-34GPU
82.30001.661
2ND = 82.30001.B21
X1701
X-32D768KHZ-34GPU
82.30001.661
2ND = 82.30001.B21
G
D S
Q1702
BSS84-7-F-GP
2nd = 84.BSS84.B31
84.00084.F31
Q1702
BSS84-7-F-GP
2nd = 84.BSS84.B31
84.00084.F31
1 2
R1718 210R2F-L-GP
PCHXDP
R1718 210R2F-L-GP
PCHXDP
1 2
R1721 51R2J-2-GP
PCHXDP
R1721 51R2J-2-GP
PCHXDP
1 2
R1712
1KR2J-1-GP
R1712
1KR2J-1-GP
1 2
R1702
10KR2J-3-GP
R1702
10KR2J-3-GP
12
R1725
1KR2J-1-GP
R1725
1KR2J-1-GP
1
2
3
U1701
CH715FGP-GP-U
83.R0304.D81
2ND = 83.00040.E81
U1701
CH715FGP-GP-U
83.R0304.D81
2ND = 83.00040.E81
1 2
R1707 330KR2J-L1-GP
DY
R1707 330KR2J-L1-GP
DY
1 2
R1723 10KR2J-3-GPR1723 10KR2J-3-GP
1 2
R1722 10KR2J-3-GP
DY
R1722 10KR2J-3-GP
DY
12
R1716
10KR2J-3-GP
R1716
10KR2J-3-GP
1 2
R1728 20KR2J-L2-GPR1728 20KR2J-L2-GP
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
CLKREQ_LAN#
XTAL25_OUT
CLK_14M_KBC_P
GPIO44
GPIO73
PCIE_TXN6_C
PCIE_TXP6_C
GPIO20
GPIO18
CLK_BUF_EXP_N
CLK_BUF_EXP_P
CLK_BUF_DOT96_N
CLK_BUF_DOT96_P
CLK_BUF_CKSSCD_N
CLK_BUF_CKSSCD_P
PCIE_TXP3_C
PCIE_TXN3_C
CLK_BUF_CPYCLK_N
CLK_BUF_CPYCLK_P
CLK_48_USB30
PCH_SML1CLK
PCH_SML1DATA
GPIO56
GPIO73
CLK_BUF_REF14
GPIO44
PCIE_TXN4_C
PCIE_TXP4_C
CLK_27_NSSC
CLKREQ_MEDIA#
GPIO18
XTAL25_IN
XCLK_RCOMP
XTAL25_OUT
CLKRQ_WWAN# GPIO56
PCH_SML1DATA
PCH_GPIO74
PCH_SML0_CLK
PCH_SML0_DATA
PCH_SML1CLK
PCH_SML1DATA
PCH_GPIO74
PCH_SMB_CLK
PCH_SMB_DATA
CLK_48_KBC_PCH_SIO
CLKRQ_WLAN#
GPIO20
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
PCH_SMB_CLK
PCH_SMB_DATA
PCH_SML0_CLK
PCH_SMB_DATA
CLKRQ_WWAN#
CLKREQ_PEG_A#
PCIE_CLK_XDP_N
PCIE_CLK_XDP_P
PCH_SML1CLK
PCH_SML0_DATA
PCH_SMB_CLK
XTAL25_IN
3D3V_S5
3D3V_S5
3D3V_S5
1D05V_S0
3D3V_S5
3D3V_S0
3D3V_S5
3D3V_S5
3D3V_S0
3D3V_S0
3D3V_S5
3D3V_S5
3D3V_AUX_S5
PCH_DDR_RST# 5
CLKREQ_MEDIA#32
CLK_PCI_FB 21
CLKOUT_DMI_P 5
CLKOUT_DMI_N 5
CLKREQ_LAN#34
CLKRQ_WLAN#53
FPR_OFF 64,97
CLK_PCIE_WLAN#53 CLK_PCIE_WLAN53
PCIE_TXN3_MEDIA32 PCIE_TXP3_MEDIA32
PCIE_RXP3_MEDIA32 PCIE_RXN3_MEDIA32
CLK_PCIE_MEDIA#32 CLK_PCIE_MEDIA32
PCIE_TXN4_WLAN53 PCIE_TXP4_WLAN53
PCIE_RXP4_WLAN53 PCIE_RXN4_WLAN53
PCIE_TXN6_LAN34 PCIE_TXP6_LAN34
PCIE_RXP6_LAN34 PCIE_RXN6_LAN34
CLK_PCIE_LAN34 CLK_PCIE_LAN#34
PCH_KBC_DATA 27,28,85
PCH_KBC_CLK27,28,85
CLK_PCIE_VGA 83
CLK_PCIE_VGA# 83
PCH_SMBDATA14,15,31,65
PCH_SMBCLK 14,15,31,65
WWAN_DET#54
PE_PWRGD 22,86,92,93,96,97
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH : PCI/USB/NVRAM/RSVD
A3
18 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH : PCI/USB/NVRAM/RSVD
A3
18 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH : PCI/USB/NVRAM/RSVD
A3
18 103Wednesday, March 14, 2012
<Core Design>
LAN
Media
Media
CLOCK TERMINATION FOR FCIM
WLAN
All resistors need very close to PCH
PCH(2/9)
WLAN
LAN
20120112 PV-R
20120116PV-R
20120212 MV
1
2
3
45
6
7
8
RN1802
SRN2K2J-4-GP
RN1802
SRN2K2J-4-GP
1 2
C1809 SCD1U10V2KX-5GPC1809 SCD1U10V2KX-5GP
1
TP1802 TPAD14-OP-GPTP1802 TPAD14-OP-GP
G
S
D
Q1801
2N7002K-2-GP
2nd = 84.07002.I31
84.2N702.J31
DIS_PX
3rd = 84.2N702.W31
Q1801
2N7002K-2-GP
2nd = 84.07002.I31
84.2N702.J31
DIS_PX
3rd = 84.2N702.W31
1 2
R1803 90D9R2F-1-GPR1803 90D9R2F-1-GP
PERN1
BG34
PERP1
BJ34
PERN2
BE34
PERP2
BF34
PERN3
BG36
PERP3
BJ36
PERN4
BF36
PERP4
BE36
PERN5
BG37
PERP5
BH37
PERN6
BJ38
PERP6
BG38
PERN7
BG40
PERP7
BJ40
PERN8
BE38
PERP8
BC38
PETN1
AV32
PETP1
AU32
PETN2
BB32
PETP2
AY32
PETN3
AV34
PETP3
AU34
PETN4
AY34
PETP4
BB34
PETN5
AY36
PETP5
BB36
PETN6
AU36
PETP6
AV36
PETN7
AY40
PETP7
BB40
PETN8
AW38
PETP8
AY38
CLKOUT_PCIE0N
Y40
CLKOUT_PCIE0P
Y39
CLKOUT_PCIE1N
AB49
CLKOUT_PCIE1P
AB47
CLKOUT_PCIE2N
AA48
CLKOUT_PCIE2P
AA47
CLKOUT_PCIE3N
Y37
CLKOUT_PCIE3P
Y36
CLKOUT_PCIE4N
Y43
CLKOUT_PCIE4P
Y45
CLKOUT_PCIE5N
V45
CLKOUT_PCIE5P
V46
CLKIN_GND1_N BJ30
CLKIN_GND1_P BG30
CLKIN_DMI_N BF18
CLKIN_DMI_P BE18
CLKIN_DOT_96N G24
CLKIN_DOT_96P E24
CLKIN_SATA_N AK7
CLKIN_SATA_P AK5
XTAL25_IN V47
XTAL25_OUT V49
REFCLK14IN K45
CLKIN_PCILOOPBACK H45
CLKOUT_PEG_A_N AB37
CLKOUT_PEG_A_P AB38
PEG_A_CLKRQ#/GPIO47 M10
PCIECLKRQ0#/GPIO73
J2
PCIECLKRQ1#/GPIO18
M1
PCIECLKRQ2#/GPIO20
V10
PCIECLKRQ3#/GPIO25
A8
PCIECLKRQ4#/GPIO26
L12
PCIECLKRQ5#/GPIO44
L14
CLKOUTFLEX0/GPIO64 K43
CLKOUTFLEX1/GPIO65 F47
CLKOUTFLEX2/GPIO66 H47
CLKOUTFLEX3/GPIO67 K49
CLKOUT_DMI_N AV22
CLKOUT_DMI_P AU22
PEG_B_CLKRQ#/GPIO56
E6
CLKOUT_PEG_B_P
AB40 CLKOUT_PEG_B_N
AB42
XCLK_RCOMP Y47
CLKOUT_DP_P AM13
CLKOUT_DP_N AM12
CLKOUT_PCIE6N
V40
CLKOUT_PCIE6P
V42
PCIECLKRQ7#/GPIO46
K12
CLKOUT_PCIE7N
V38
CLKOUT_PCIE7P
V37
CLKOUT_ITPXDP_N
AK14
CLKOUT_ITPXDP_P
AK13
SMBALERT#/GPIO11 E12
SMBCLK H14
SMBDATA C9
SML0ALERT#/GPIO60 A12
SML0CLK C8
SML0DATA G12
SML1ALERT#/PCHHOT#/GPIO74 C13
SML1CLK/GPIO58 E14
SML1DATA/GPIO75 M16
CL_CLK1 M7
CL_DATA1 T11
CL_RST1# P10
PCIECLKRQ6#/GPIO45
T13
PCI-E*
CLOCKS
FLEX CLOCKS
SMBUSController
Link
2 OF 10
PCH1B
PANTHER-GP-NF
PCI-E*
CLOCKS
FLEX CLOCKS
SMBUSController
Link
2 OF 10
PCH1B
PANTHER-GP-NF
12
R1801
10KR2J-3-GP
R1801
10KR2J-3-GP
12
R1808
10KR2J-3-GP
DY
R1808
10KR2J-3-GP
DY
1
2
3 4
5
6
U1801
2N7002KDW-GP
2nd = 84.2N702.E3F
84.2N702.A3F
3rd = 84.2N702.F3F
U1801
2N7002KDW-GP
2nd = 84.2N702.E3F
84.2N702.A3F
3rd = 84.2N702.F3F
1
TP1801 TPAD14-OP-GPTP1801 TPAD14-OP-GP
1 2
C1806 SCD1U10V2KX-5GPC1806 SCD1U10V2KX-5GP
1
2 3
4
RN1807
SRN10KJ-5-GP
RN1807
SRN10KJ-5-GP
1
2
3
4
5 6
7
8
9
10
RN1804
SRN10KJ-L3-GP
RN1804
SRN10KJ-L3-GP
1
2 3
4
RN1808
SRN10KJ-5-GP
RN1808
SRN10KJ-5-GP
1 2
C1801
SC15P50V2JN-2-GP
C1801
SC15P50V2JN-2-GP
1 2
C1807 SCD1U10V2KX-5GPC1807 SCD1U10V2KX-5GP
1
TP1803TPAD14-OP-GPTP1803TPAD14-OP-GP
1 2
C1802
SC18P50V2JN-1-GP
C1802
SC18P50V2JN-1-GP
1 2
C1811 SCD1U10V2KX-5GPC1811 SCD1U10V2KX-5GP
1
2 3
4
RN1809
SRN10KJ-5-GP
RN1809
SRN10KJ-5-GP
1 2
R1804
0R2J-2-GP
R1804
0R2J-2-GP
1
2 3
4
RN1803
SRN2K2J-1-GP
RN1803
SRN2K2J-1-GP
1
TP1806TPAD14-OP-GPTP1806TPAD14-OP-GP
1
2
3
45
6
7
8
RN1801
SRN2K2J-4-GP
RN1801
SRN2K2J-4-GP
1
2 3
4
RN1806
SRN10KJ-5-GP
RN1806
SRN10KJ-5-GP
1
2 3
4
RN
0R4P2R-PAD
RN1810
RN
0R4P2R-PAD
RN1810
1 2
R1807 1KR2J-1-GP
R1807 1KR2J-1-GP
1 2
R1802 10KR2J-3-GPR1802 10KR2J-3-GP
1 2
C1810 SCD1U10V2KX-5GPC1810 SCD1U10V2KX-5GP
41
2 3
X1801
XTAL-25MHZ-155-GP
82.30020.D41
3rd = 82.30020.G61
2nd = 82.30020.G71
X1801
XTAL-25MHZ-155-GP
82.30020.D41
3rd = 82.30020.G61
2nd = 82.30020.G71
1
TP1805TPAD14-OP-GPTP1805TPAD14-OP-GP
1 2
C1805 SCD1U10V2KX-5GPC1805 SCD1U10V2KX-5GP
1
TP1804TPAD14-OP-GPTP1804TPAD14-OP-GP
12
R1805
1MR2J-1-GP
R1805
1MR2J-1-GP
12
R1806 10KR2J-3-GP
R1806 10KR2J-3-GP
1
2
3 4
5
6
U1802
2N7002KDW-GP
2nd = 84.2N702.E3F
84.2N702.A3F
3rd = 84.2N702.F3F
U1802
2N7002KDW-GP
2nd = 84.2N702.E3F
84.2N702.A3F
3rd = 84.2N702.F3F
1
2 3
4
RN1805
SRN10KJ-5-GP
RN1805
SRN10KJ-5-GP
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
PM_SLP_S5#
PM_RI#
SLP_S4#_R
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
PM_PCH_PWROK PCH_GPIO61
RBIAS_CPY
PM_SYSRST#_R
DSWODVREN
DSWODVREN
RSMRST#
PCH_DPWROK
PM_CLKRUN#
APWROK
DMI_COMP_R
SYS_PWROK_R
PM_SLP_A#_R
PWR_BTN_OUT#
ADP_PRES_OUT
FDI_TX_N0
FDI_TX_N1
FDI_TX_N2
FDI_TX_N3
FDI_TX_N4
FDI_TX_N5
FDI_TX_N6
FDI_TX_N7
FDI_TX_P0
FDI_TX_P1
FDI_TX_P2
FDI_TX_P3
FDI_TX_P4
FDI_TX_P5
FDI_TX_P6
FDI_TX_P7
SUSACK#_R
PCH_GPIO72
SLP_LAN#
SLP_SUS#
PCIE_WAKE#
PM_RI#
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_A#
ON_OFF#
SLP_LAN#
SLP_S3#_R
PCH_GPIO72
SUS_PWR_ACK
RTC_AUX_S5
3D3V_S0
3D3V_S0
1D05V_S0
3D3V_S5
3D3V_S5
3D3V_S5
PM_DRAM_PWRGD5
XDP_DBRESET#5
RSMRST#27,41,97
SUS_PWR_ACK27
PWR_BTN_OUT#27
PM_CLKRUN# 27
PCIE_WAKE# 34,53
SUSCLK32_KBC 27
PM_SLP_S4# 46,62,97
PM_SLP_S3# 8,27,29,34,35,36,37,45,46,47,48,92,93
H_PM_SYNC 5
DMI_RXN[3:0]4
DMI_RXP[3:0]4
DMI_TXN[3:0]4
DMI_TXP[3:0]4
ADP_PRES_OUT27,85
PM_PWROK27,97
PM_SLP_A# 27
VGATE42
FDI_TX_N[7:0] 4
FDI_TX_P[7:0] 4
FDI_INT 4
FDI_FSYNC0 4
FDI_FSYNC1 4
FDI_LSYNC0 4
FDI_LSYNC1 4
ON_OFF#82,97
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(3/9) : DMI/FDI/PM
A3
19 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(3/9) : DMI/FDI/PM
A3
19 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(3/9) : DMI/FDI/PM
A3
19 103Wednesday, March 14, 2012
<Core Design>
DSWODVREN - On Die DSW VR Enable
HIGH Enabled (DEFAULT)
(R1917 STUFFED,
R1901 UNSTUFFED
LOW Disabled
(R1901 STUFFED,
R1917 UNSTUFFED
PCH(3/9)
Signal Name Platform With M3 Support
(e.g., Intel AMT) Platform Without M3 Support
SUSPWRDNACK(GPIO30) Required Required
Required RequiredACPRESENT(GPIO31)
SLP_A# Required
(Tie to SLP_S3#)
Note: If SLP_S3# is not
routed from PCH to EC, then
SLP_A# becomes required
from Intel ME-EC
prespecrive.
Intel ME-EC Interaction Signal List with and without M3 support
AMT/ME COMPLIANCY TEST CONN.
PUT CLOSE PCH
20120112 PV-R
20120112 PV-R
1 2
R1915 8K2R2J-3-GPR1915 8K2R2J-3-GP
1
2 3
4
RN1902
SRN10KJ-5-GP
RN1902
SRN10KJ-5-GP
1 2
R1910 0R2J-2-GP
DY
R1910 0R2J-2-GP
DY
1 2
R1904 0R0402-PADR1904 0R0402-PAD
1
2
3
4 5
6
7
8
RN1901
SRN10KJ-6-GP
RN1901
SRN10KJ-6-GP
1
TP1903TPAD14-OP-GPTP1903TPAD14-OP-GP
DMI0RXN
BC24
DMI1RXN
BE20
DMI2RXN
BG18
DMI3RXN
BG20
DMI0RXP
BE24
DMI1RXP
BC20
DMI2RXP
BJ18
DMI3RXP
BJ20
DMI0TXN
AW24
DMI1TXN
AW20
DMI2TXN
BB18
DMI3TXN
AV18
DMI0TXP
AY24
DMI1TXP
AY20
DMI2TXP
AY18
DMI3TXP
AU18
DMI_ZCOMP
BJ24
DMI_IRCOMP
BG25
FDI_RXN0 BJ14
FDI_RXN1 AY14
FDI_RXN2 BE14
FDI_RXN3 BH13
FDI_RXN4 BC12
FDI_RXN5 BJ12
FDI_RXN6 BG10
FDI_RXN7 BG9
FDI_RXP0 BG14
FDI_RXP1 BB14
FDI_RXP2 BF14
FDI_RXP3 BG13
FDI_RXP4 BE12
FDI_RXP5 BG12
FDI_RXP6 BJ10
FDI_RXP7 BH9
FDI_FSYNC0 AV12
FDI_FSYNC1 BC10
FDI_LSYNC0 AV14
FDI_LSYNC1 BB10
FDI_INT AW16
PMSYNCH AP14
SLP_SUS# G16
SLP_S3# F4
SLP_S4# H4
SLP_S5#/GPIO63 D10
SYS_RESET#
K3
SYS_PWROK
P12
PWRBTN#
E20
RI#
A10
WAKE# B9
SUS_STAT#/GPIO61 G8
SUSCLK/GPIO62 N14
ACPRESENT/GPIO31
H20
BATLOW#/GPIO72
E10
PWROK
L22
CLKRUN#/GPIO32 N3
SUSWARN#/SUSPWRDNACK/GPIO30
K16
RSMRST#
C21
DRAMPWROK
B13
SLP_LAN#/GPIO29 K14
APWROK
L10
DPWROK E22
DMI2RBIAS
BH21
SLP_A# G10
DSWVRMEN A18
SUSACK#
C12
DMI
FDI
System Power Management
3 OF 10
PCH1C
PANTHER-GP-NF
DMI
FDI
System Power Management
3 OF 10
PCH1C
PANTHER-GP-NF
1
TP1905 TPAD14-OP-GPTP1905 TPAD14-OP-GP
1 2
R1911 0R0402-PADR1911 0R0402-PAD
1 2
R1905 10KR2J-3-GP
DY
R1905 10KR2J-3-GP
DY
1 2
R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP
1
TP1901 TPAD14-OP-GPTP1901 TPAD14-OP-GP
1 2
R1913 0R0402-PADR1913 0R0402-PAD
12
R1907 0R0402-PADR1907 0R0402-PAD
1 2
R1901 330KR2J-L1-GP
DY
R1901 330KR2J-L1-GP
DY
12
R1908 0R0402-PADR1908 0R0402-PAD
12
R1906 0R0402-PADR1906 0R0402-PAD
1 2
R1903 750R2F-GPR1903 750R2F-GP
1 2
R1912 0R0402-PADR1912 0R0402-PAD
12
R1909 0R0402-PADR1909 0R0402-PAD
1 2
R1902 49D9R2F-GPR1902 49D9R2F-GP
1
2
3
4
5
6
7
8
9
10
APS1
ACES-CON8-13-GP-U1
20.F1295.008
DY
APS1
ACES-CON8-13-GP-U1
20.F1295.008
DY
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
LVD_IBG
L_CTRL_CLK
L_CTRL_DATA
DAC_IREF
DPD_AUXN
DPD_AUXP
3D3V_S0
3D3V_S0
TXOUTA_L0-49 TXOUTA_L1-49 TXOUTA_L2-49
TXOUTA_L0+49 TXOUTA_L1+49 TXOUTA_L2+49
CRT_DDC_CLK50 CRT_DDC_DATA50
PCH_RED50 PCH_GREEN50 PCH_BLUE50
BKLT_CTL49
TXCLKA_L+49 TXCLKA_L-49
LCD_BL_EN49,97 LCDVDD_EN49,97
LCD_SMBCLK49 LCD_SMBDATA49
CRT_HSYNC50 CRT_VSYNC50
PCH_HDMI_CLK 51
PCH_HDMI_DATA 51
HDMI_PCH_DET 51,97
HDMI_DATA0_R 51
HDMI_DATA0_R# 51
HDMI_CLK_R 51
HDMI_DATA1_R 51
HDMI_CLK_R# 51
HDMI_DATA1_R# 51
HDMI_DATA2_R 51
HDMI_DATA2_R# 51
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(4/9) : LVDS/CRT/DDI
A3
20 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(4/9) : LVDS/CRT/DDI
A3
20 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(4/9) : LVDS/CRT/DDI
A3
20 103Wednesday, March 14, 2012
<Core Design>
PCH(4/9)
1
2 3
4
RN2001
SRN2K2J-1-GP
RN2001
SRN2K2J-1-GP
1 2
R2005 2K37R2F-GPR2005 2K37R2F-GP
12
R2003
1KR2D-1-GP
R2003
1KR2D-1-GP
1
23
4
RN2002
SRN2K2J-1-GP
RN2002
SRN2K2J-1-GP
L_BKLTCTL
P45
L_BKLTEN
J47
L_CTRL_CLK
T45
L_CTRL_DATA
P39
L_DDC_CLK
T40
L_DDC_DATA
K47
L_VDD_EN
M45
LVDSA_CLK#
AK39
LVDSA_CLK
AK40
LVDSA_DATA#0
AN48
LVDSA_DATA#1
AM47
LVDSA_DATA#2
AK47
LVDSA_DATA#3
AJ48
LVDSA_DATA0
AN47
LVDSA_DATA1
AM49
LVDSA_DATA2
AK49
LVDSA_DATA3
AJ47
LVDSB_CLK#
AF40
LVDSB_CLK
AF39
LVDSB_DATA#0
AH45
LVDSB_DATA#1
AH47
LVDSB_DATA#2
AF49
LVDSB_DATA#3
AF45
LVDSB_DATA0
AH43
DDPB_0N AV42
DDPB_1N AV45
LVD_VREFH
AE48
LVD_VREFL
AE47
DDPD_2N BF42
DDPD_3N BJ42
DDPB_2N AU48
DDPB_3N AV47
DDPC_0N AY47
DDPC_1N AY43
DDPC_2N BA47
DDPC_3N BB47
DDPD_0N BB43
DDPD_1N BF44
DDPB_0P AV40
DDPB_1P AV46
DDPD_2P BE42
DDPD_3P BG42
DDPB_2P AU47
DDPB_3P AV49
LVDSB_DATA1
AH49
LVDSB_DATA2
AF47
LVDSB_DATA3
AF43
LVD_IBG
AF37
LVD_VBG
AF36
DDPC_1P AY45
DDPC_0P AY49
DDPC_2P BA48
DDPC_3P BB49
DDPD_0P BB45
DDPD_1P BE44
CRT_BLUE
N48
CRT_DDC_CLK
T39
CRT_DDC_DATA
M40
CRT_GREEN
P49
CRT_HSYNC
M47
CRT_IRTN
T42
CRT_RED
T49
CRT_VSYNC
M49
DAC_IREF
T43
SDVO_CTRLCLK P38
SDVO_CTRLDATA M39
DDPC_CTRLCLK P46
DDPC_CTRLDATA P42
DDPD_CTRLCLK M43
DDPD_CTRLDATA M36
DDPB_AUXN AT49
DDPC_AUXN AP47
DDPD_AUXN AT45
DDPB_AUXP AT47
DDPC_AUXP AP49
DDPD_AUXP AT43
DDPB_HPD AT40
DDPC_HPD AT38
DDPD_HPD BH41
SDVO_TVCLKINP AP45
SDVO_TVCLKINN AP43
SDVO_STALLP AM40
SDVO_STALLN AM42
SDVO_INTP AP40
SDVO_INTN AP39
LVDS
Digital Display Interface
CRT
4 OF 10
PCH1D
PANTHER-GP-NF
LVDS
Digital Display Interface
CRT
4 OF 10
PCH1D
PANTHER-GP-NF
1
TP2002TPAD14-OP-GPTP2002TPAD14-OP-GP
1
TP2001TPAD14-OP-GPTP2001TPAD14-OP-GP
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
LANLINK_STATUS
OC1#_GPIO40
OC5#_GPIO9
PCI_PLTRST#
CLK_PCI_SIO_R OC2#_GPIO41
NMI_SMI_DBG#
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
PCH_GPIO50
PLT_DET_R
PE_GPIO1
PCH_GPIO2
ACCEL_INT
OC3#_GPIO42
PME#
USB_BIAS
CAMERA_ON
OC0#_GPIO59
CLK_OUT_PCI3
CLK_PCI_FB_R
PCH_GPIO51
OC4#_GPIO43
CLK_OUT_PCI2
OC7#_GPIO14
PE_GPIO0
PCH_GPIO51
PCH_GPIO51
INT_PIRQA#
PCH_GPIO50
INT_PIRQC# PCH_GPIO2
PE_GPIO1
INT_PIRQB# PLT_DET_R
INT_PIRQD#
CLK_PCI_KBC_R
PCI_PLTRST# OC1#_GPIO40
OC4#_GPIO43
OC2#_GPIO41
OC3#_GPIO42
OC7#_GPIO14
OC5#_GPIO9
OC0#_GPIO59
PLT_RST#
3D3V_S5
3D3V_S5
3D3V_S0
3D3V_S5
3D3V_S0
3D3V_S0
3D3V_S0
3D3V_S0
CLK_PCI_KBC27,97
USB3_RXN462
USB3_RXP462
USB3_TXN462
USB3_TXP462
CLK_PCI_DEBUG71,97
CLK_PCI_FB18
SATA_ODD_DA#56,96
PLT_RST# 5,17,32,34,53,54,56,71,83,96,97
USB_PP8 64
USB_PN8 64
NMI_SMI_DBG#27,71
CAMERA_ON49
ACCEL_INT65
USB3_RXN362
USB3_RXP362
USB3_TXN362
USB3_TXP362
LANLINK_STATUS 35
USB_PP10 49
USB_PN10 49
USB_PP12 54
USB_PN12 54
USB_PP5 53
USB_PN5 53
USB_PP3 62
USB_PN3 62
USB_PP1 62
USB_PN1 62
USB_PP2 62
USB_PN2 62
USB_PP9 61
USB_PN9 61
PE_GPIO083
PE_GPIO192,93
USB3_RXN262
USB3_RXP262
USB3_TXN262
USB3_TXP262
PLT_DET27,69
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(5/9) : PCI/USB/NVM
A3
21 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(5/9) : PCI/USB/NVM
A3
21 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(5/9) : PCI/USB/NVM
A3
21 103Wednesday, March 14, 2012
<Core Design>
Pair Device
1
2
3
4
FREE
USB
USB3.0 Table
PCH(5/9)
I/O CONN. 2
WWAN
I/O CONN. 3
12
13
Camera
Pair Device
0
1
2
3
4
5
6
7
8
9
10
11
FREE
FREE
USB 3.0 I/O CONN. 2
BT WLAN combo
USB
USB2.0 Table
Fingerprint
AND GATE
I/O CONN. 1
FREE
FREE
USB 2.0 I/O CONN. 1
FREE
FREE
USB 3.0 Conn. 1
Fingerprint
Camera
WWAN
BT WLAN combo
USB 3.0 I/O CONN. 1
USB 3.0 I/O CONN. 3
USB 3.0 Conn. 2
USB 3.0 Conn. 3
USB 2.0 Conn. 1
S 2012 Chief River PCH GPIO 52
Richie U&D (13 inches)
Rocky U&D (14 inches)
Rocky U&D (15/17 inches)
1
1
0
GPIO Table
GNT1#/GPIO51
0
Boot BIOS Strap
SATA1GP#/GPIO19 Boot BIOS Location
0
0
01
1
1 1
LPC
Reserved
SPI(Default)
PCI
20120112 PV-R
1
2 3
4
RN2101
SRN8K2J-3-GP
RN2101
SRN8K2J-3-GP
1 2
R2107 22R2J-2-GPR2107 22R2J-2-GP
1 2
R2103 22R2J-2-GPR2103 22R2J-2-GP
1
2
3
45
6
7
8
RN2104
SRN10KJ-6-GP
RN2104
SRN10KJ-6-GP
1
2
3
4
5 6
7
8
9
10
RN2102
SRN8K2J-2-GP-U
RN2102
SRN8K2J-2-GP-U
1 2
R2101 22D6R2F-L1-GPR2101 22D6R2F-L1-GP
1 2
R2110
10KR2J-3-GP
DY
R2110
10KR2J-3-GP
DY
1 2
R2109 10KR2J-3-GP
DY
R2109 10KR2J-3-GP
DY
1 2
R2113 10KR2J-3-GP
R2113 10KR2J-3-GP
1 2
R2112
10KR2J-3-GP
DY
R2112
10KR2J-3-GP
DY
1 2
R2105 22R2J-2-GPR2105 22R2J-2-GP
1 2
R2102 10KR2J-3-GP
DY
R2102 10KR2J-3-GP
DY
1
2
3
45
6
7
8
RN2103
SRN10KJ-6-GP
RN2103
SRN10KJ-6-GP
1 2
R2106 0R0402-PADR2106 0R0402-PAD
A
1
B
2
GND
3Y4
VCC 5
U2101
U74LVC1G08G-AL5-R-GP-U
3rd = 73.01G08.L04
2nd = 73.7SZ08.EAH
73.01G08.EHG
U2101
U74LVC1G08G-AL5-R-GP-U
3rd = 73.01G08.L04
2nd = 73.7SZ08.EAH
73.01G08.EHG
12
R2108
100KR2J-1-GP
DY
R2108
100KR2J-1-GP
DY
RSVD23 AV5
RSVD1 AY7
RSVD2 AV7
RSVD3 AU3
RSVD4 BG4
RSVD5 AT10
RSVD6 BC8
RSVD7 AU2
RSVD8 AT4
RSVD17 BB5
RSVD18 BB3
RSVD19 BB7
RSVD20 BE8
RSVD21 BD4
RSVD22 BF6
RSVD9 AT3
RSVD10 AT1
RSVD11 AY3
RSVD12 AT5
RSVD13 AV3
RSVD14 AV1
RSVD15 BB1
RSVD16 BA3
RSVD25 AT8
RSVD24 AV10
RSVD26 AY5
RSVD27 BA2
RSVD28 AT12
RSVD29 BF3
PIRQA#
K40
PIRQB#
K38
PIRQC#
H38
PIRQD#
G38
REQ1#/GPIO50
C46
REQ2#/GPIO52
C44
REQ3#/GPIO54
E40
GNT1#/GPIO51
D47
GNT2#/GPIO53
E42
GNT3#/GPIO55
F46
PIRQE#/GPIO2
G42
PIRQF#/GPIO3
G40
PIRQG#/GPIO4
C42
PIRQH#/GPIO5
D44
USBP0N C24
USBP0P A24
USBP1N C25
USBP1P B25
USBP2N C26
USBP2P A26
USBP3N K28
USBP3P H28
USBP4N E28
USBP4P D28
USBP5N C28
USBP5P A28
USBP6N C29
USBP6P B29
USBP7N N28
USBP7P M28
USBP8N L30
USBP8P K30
USBP9N G30
USBP9P E30
USBP10N C30
USBP10P A30
USBP11N L32
USBP11P K32
USBP12N G32
USBP12P E32
USBP13N C32
USBP13P A32
PME#
K10
CLKOUT_PCI0
H49
CLKOUT_PCI1
H43
CLKOUT_PCI2
J48
USBRBIAS# C33
USBRBIAS B33
OC0#/GPIO59 A14
OC1#/GPIO40 K20
OC2#/GPIO41 B17
OC3#/GPIO42 C16
OC4#/GPIO43 L16
OC5#/GPIO9 A16
OC6#/GPIO10 D14
OC7#/GPIO14 C14
CLKOUT_PCI4
H40 CLKOUT_PCI3
K42
PLTRST#
C6
TP1
BG26
TP2
BJ26
TP3
BH25
TP6
AH38
TP7
AH37
TP8
AK43
TP9
AK45
TP16
Y13
TP17
K24
TP18
L24
TP19
AB46
TP20
AB45
TP21
B21
TP22
M20
TP23
AY16
USB3RN1
BE28
USB3RN2
BC30
USB3RN3
BE32
USB3RN4
BJ32
USB3RP1
BC28
USB3RP2
BE30
USB3RP3
BF32
USB3RP4
BG32
USB3TN1
AV26
USB3TN2
BB26
USB3TN3
AU28
USB3TN4
AY30
USB3TP1
AU26
USB3TP2
AY26
USB3TP3
AV28
USB3TP4
AW30
TP4
BJ16
TP5
BG16
TP15
AM5 TP14
AM4 TP13
AH12 TP12
H3 TP11
N30 TP10
C18
TP24
BG46
RSVD
PCI
USB
5 OF 10
PCH1E
PANTHER-GP-NF
RSVD
PCI
USB
5 OF 10
PCH1E
PANTHER-GP-NF
1
TP2106TPAD14-OP-GP TP2106TPAD14-OP-GP
1
TP2108TPAD14-OP-GP TP2108TPAD14-OP-GP
1 2
R2104
0R2J-2-GP
DY
R2104
0R2J-2-GP
DY
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
D3E_WAKE#
SATA5GP_GPIO49
FPR_LOCK#
SATA3GP_GPIO37
KBRST#
RUNSCI_EC#
PE_PWRGD
SATA2GP_GPIO36
SATA4GP_GPIO16
WWAN_TRANSMIT_OFF#
PCH_GPIO24
GPIO34
PE_PWRGD
TLS_ENcrytion
PCH_GPIO39
PCH_GPIO38
SATA5GP_GPIO49
INIT3_3V#
CRD_REQ#_R_R
GATEA20
PCH_GPIO28
SATA4GP_GPIO16
GPIO34
OCP_OC#
PCH_GPIO12
GPS_XMIT_OFF#
WLAN_TRANSMIT_OFF#
PCH_GPIO24
GPI_INV_LIDWAKE
DF_TVS
SATA3GP_GPIO37
H_PECI_R
PCH_THRMTRIP#_R
LPC_RESET#
PCH_GPIO27
PCH_GPIO27
CRD_REQ#_R_R
SATA2GP_GPIO36
SATA_ODD_PWR_EN
NCTF_VSS#A4
NCTF_VSS#BG48
NCTF_VSS#BF49
NCTF_VSS#BF1
NCTF_VSS#BH3
NCTF_VSS#B47
NCTF_VSS#B3
NCTF_VSS#BG2
NCTF_VSS#C48
NCTF_VSS#C2
NCTF_VSS#D49
NCTF_VSS#BH47
BT_OFF#
GPI_INV_LIDWAKE
PCH_GPIO39 PCH_GPIO38
BT_OFF#
PCH_GPIO12
3D3V_S0
1D8V_S0
3D3V_S0
3D3V_S03D3V_S0
1D05V_S0
3D3V_S0
3D3V_S0
3D3V_S0
3D3V_S0
3D3V_S5
3D3V_S5
3D3V_S0 3D3V_S0
3D3V_S5
H_SNB_IVB# 5
D3E_WAKE# 32,97
GPS_XMIT_OFF# 54,97
LPC_RESET# 27
FPR_LOCK#64,97
OCP_OC#38
KBRST# 27,97
H_THRMTRIP# 5,85
GATEA20 27
H_CPUPWRGD 5
H_PECI 5,27
RUNSCI_EC#27
SATA_ODD_PWR_EN 56,97
THERM_SCI#28
WWAN_TRANSMIT_OFF#54,68
WLAN_TRANSMIT_OFF#53
SATA0GP_GPIO21 17
CRD_REQ#_R_R32
PE_PWRGD18,86,92,93,96,97
BT_OFF#53,97
SATA4GP_GPIO16 96
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(6/9) : GPIO/NTCF/RSVD
A3
22 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(6/9) : GPIO/NTCF/RSVD
A3
22 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(6/9) : GPIO/NTCF/RSVD
A3
22 103Wednesday, March 14, 2012
<Core Design>
DF_TVS SNB: "1"
IVB: "0"
DMI & FDI Termination Voltage
PROC_SELECT
GPIO36
DMI TERMINATION VOLTAGE OVERRIDE
LOW - Tx, Rx terminated to same voltage
(DC Coupling Model DEFAULT)
PCH(6/9)
GPIO37
(FDI_OVRVLTG)
FDI TERMINATION VOLTAGE OVERRIDE
LOW - Tx, Rx terminated to same voltage
(DC Coupling Model DEFAULT)
VRAM ID TABLE
PCH_GPIO38PCH_GPIO39
0 1
1 0
1 1
0 0
VENDER
UMA
Elpida
Hynix
Samsung
0 (13") GDDR5
PCH GPIO 12
GDDR5/DDR3 TABLE
20110822SI
1(14",15",17")DDR3
1(14",15",17")DDR3
2012 Chief River
Richie U&D (13 inches)
Rocky U&D (14 inches)
Rocky U&D (15/17 inches)
1 2
R2223
10KR2J-3-GP
UMA_Samsung
R2223
10KR2J-3-GP
UMA_Samsung
12
R2222
56R2J-4-GP
DY
R2222
56R2J-4-GP
DY
1
2 3
4
RN2202
SRN10KJ-5-GP
RN2202
SRN10KJ-5-GP
1
TP2203TPAD14-OP-GPTP2203TPAD14-OP-GP
GPIO27
E16
GPIO28
P8
GPIO24
E8
GPIO57
D6
LAN_PHY_PWR_CTRL/GPIO12
C4
VSS_NCTF_1#A4
A4
VSS_NCTF_2#A44
A44
VSS_NCTF_3#A45
A45
VSS_NCTF_4#A46
A46
VSS_NCTF_5#A5
A5
VSS_NCTF_6#A6
A6
VSS_NCTF_7#B3
B3
VSS_NCTF_8#B47
B47
VSS_NCTF_9#BD1
BD1
VSS_NCTF_10#BD49
BD49
VSS_NCTF_11#BE1
BE1
VSS_NCTF_12#BE49
BE49
TACH2/GPIO6
H36
TACH0/GPIO17
D40
TACH3/GPIO7
E38
SATA3GP/GPIO37
M5
SATA5GP/GPIO49/TEMP_ALERT#
V3
SCLOCK/GPIO22
T5
SLOAD/GPIO38
N2
SDATAOUT0/GPIO39
M3
SDATAOUT1/GPIO48
V13
PROCPWRGD AY11
RCIN# P5
PECI AU16
THRMTRIP# AY10
GPIO8
C10
BMBUSY#/GPIO0
T7
GPIO15
G2
TACH1/GPIO1
A42
SATA2GP/GPIO36
V8
INIT3_3V# T14
STP_PCI#/GPIO34
K1
GPIO35
K4
SATA4GP/GPIO16
U2
VSS_NCTF_32#F49 F49
A20GATE P4
TACH4/GPIO68 C40
TACH6/GPIO70 C41
TACH7/GPIO71 A40
TACH5/GPIO69 B41
VSS_NCTF_17#BH3 BH3
VSS_NCTF_18#BH47 BH47
VSS_NCTF_19#BJ4 BJ4
VSS_NCTF_20#BJ44 BJ44
VSS_NCTF_21#BJ45 BJ45
VSS_NCTF_22#BJ46 BJ46
VSS_NCTF_23#BJ5 BJ5
VSS_NCTF_24#BJ6 BJ6
VSS_NCTF_25#C2 C2
VSS_NCTF_26#C48 C48
VSS_NCTF_27#D1 D1
VSS_NCTF_28#D49 D49
VSS_NCTF_29#E1 E1
VSS_NCTF_30#E49 E49
VSS_NCTF_31#F1 F1
TS_VSS4 AK10
TS_VSS3 AH10
TS_VSS2 AK11
TS_VSS1 AH8
NC_1 P37
VSS_NCTF_13#BF1
BF1
VSS_NCTF_14#BF49
BF49
VSS_NCTF_15#BG2 BG2
VSS_NCTF_16#BG48 BG48
DF_TVS AY1
CPU/MISC
NCTF
GPIO
6 OF 10
NCTF TEST PIN:
A4,A44,A45,A46,A5,A6,B3,B47,
BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
D49,E1,E49,F1,F49
PCH1F
PANTHER-GP-NF
CPU/MISC
NCTF
GPIO
6 OF 10
NCTF TEST PIN:
A4,A44,A45,A46,A5,A6,B3,B47,
BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
D49,E1,E49,F1,F49
PCH1F
PANTHER-GP-NF
1
TP2207 TPAD14-OP-GPTP2207 TPAD14-OP-GP
12
R2206
10KR2J-3-GP
DY
R2206
10KR2J-3-GP
DY
1 2
R2216 10KR2J-3-GP
DY
R2216 10KR2J-3-GP
DY
1 2
R2204 10KR2J-3-GP
DY
R2204 10KR2J-3-GP
DY
1
TP2211TPAD14-OP-GPTP2211TPAD14-OP-GP
1 2
R2217 200KR2J-L1-GP
DY
R2217 200KR2J-L1-GP
DY
1 2
R2202 1KR2J-1-GPR2202 1KR2J-1-GP
1
TP2214TPAD14-OP-GPTP2214TPAD14-OP-GP
1
TP2213TPAD14-OP-GPTP2213TPAD14-OP-GP
1
2
3
4
5 6
7
8
9
10
RP2201
SRN10KJ-L3-GP
RP2201
SRN10KJ-L3-GP
1
TP2212TPAD14-OP-GPTP2212TPAD14-OP-GP
1
TP2208 TPAD14-OP-GPTP2208 TPAD14-OP-GP
1
TP2210 TPAD14-OP-GPTP2210 TPAD14-OP-GP
1 2
R2213 200KR2J-L1-GP
DY
R2213 200KR2J-L1-GP
DY
1 2
R2209 0R2J-2-GP
DY
R2209 0R2J-2-GP
DY
1 2
R2214 1KR2J-1-GP
R2214 1KR2J-1-GP
1
TP2217TPAD14-OP-GPTP2217TPAD14-OP-GP
1 2
R2218
10KR2J-3-GP
R2218
10KR2J-3-GP
1 2
R2207 10KR2J-3-GPR2207 10KR2J-3-GP
1 2
R2212 10KR2J-3-GP
DY
R2212 10KR2J-3-GP
DY
1 2
R2210 390R2F-2GPR2210 390R2F-2GP
1
TP2218TPAD14-OP-GPTP2218TPAD14-OP-GP
1 2
R2225
10KR2J-3-GP
Hynix_Elpida
R2225
10KR2J-3-GP
Hynix_Elpida
12
R2201
2K2R2J-2-GP
R2201
2K2R2J-2-GP
1
TP2209 TPAD14-OP-GPTP2209 TPAD14-OP-GP
1 2
R2211 10KR2J-3-GPR2211 10KR2J-3-GP
1 2
R2220
10KR2J-3-GP
Samsung_Elipda
R2220
10KR2J-3-GP
Samsung_Elipda
1
2
3
45
6
7
8
RN2205
SRN10KJ-6-GP
RN2205
SRN10KJ-6-GP
1
TP2206TPAD14-OP-GPTP2206TPAD14-OP-GP
1
TP2216TPAD14-OP-GPTP2216TPAD14-OP-GP
1
2 3
4
RN2203
SRN10KJ-5-GP
RN2203
SRN10KJ-5-GP
1 2
R2224
10KR2J-3-GP
UMA_Hynix
R2224
10KR2J-3-GP
UMA_Hynix
1 2
R2205 10KR2J-3-GPR2205 10KR2J-3-GP
1
TP2215TPAD14-OP-GPTP2215TPAD14-OP-GP
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+V1.05S_VCCAPLL_FDI
VCCCLKDMI
+V1.05S_VCCAPLL_EXP
+VCCAFDI_VRM
+VCCAFDI_VRM
+V1.05S_VCCDPLL_FDI
5V_S0
3D3V_S5
3D3V_S0
3D3V_S0_LDO
1D5V_S0
+V1.05S_VCC_DMI
+V1.05S_VCC_DMI 1D05V_S0
3D3V_S0
1D8V_S0
3D3V_S0
+VCCAFDI_VRM
1D8V_S0
1D05V_S0
1D05V_S0
1D05V_S0
1D05V_S0
1D05V_S0
1D05V_S0
1D8V_S0
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(7/9) : PWR1
A3
23 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(7/9) : PWR1
A3
23 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(7/9) : PWR1
A3
23 103Wednesday, March 14, 2012
<Core Design>
PCH(7/9)
20mA
190mA
42mA
160mA
266mA
1mA
VCC_PCH: 6A
1mA
60mA
20mA
2.925A
1.3A
20120112 PV-R
20120116PV-R
12
C2310
SC10U6D3V3MX-GP
C2310
SC10U6D3V3MX-GP
1 2
R2304 0R0603-PAD-1-GPR2304 0R0603-PAD-1-GP
12
C2318
SCD1U10V2KX-4GP
C2318
SCD1U10V2KX-4GP
12
C2301
SC1U10V2KX-1GP
C2301
SC1U10V2KX-1GP
12
C2309
SC22U6D3V5MX-2GP
C2309
SC22U6D3V5MX-2GP
1 2
R2306
0R0402-PAD
R2306
0R0402-PAD
12
C2325
SC2D2U6D3V3KX-GP
C2325
SC2D2U6D3V3KX-GP
12
C2314
SC1U10V2KX-1GP
C2314
SC1U10V2KX-1GP
12
C2316
SC1U10V2KX-1GP
DY
C2316
SC1U10V2KX-1GP
DY
12
R2303
0R0402-PAD
R2303
0R0402-PAD
12
C2320
SC1U10V2KX-1GP
C2320
SC1U10V2KX-1GP
12
C2308
SC1U10V2KX-1GP
C2308
SC1U10V2KX-1GP
12
C2319
SC1U10V2KX-1GP
C2319
SC1U10V2KX-1GP
NC#4
4
OUT
5IN 1
GND 2
EN 3
U2301
TLV70233DBVR-GP
3rd = 74.09090.D3F
2nd = 74.08818.B3F
74.70233.03F
U2301
TLV70233DBVR-GP
3rd = 74.09090.D3F
2nd = 74.08818.B3F
74.70233.03F
12
C2311
SC1U10V2KX-1GP
C2311
SC1U10V2KX-1GP
12
C2306
SCD01U16V2KX-3GP
C2306
SCD01U16V2KX-3GP
12
R2301
0R0402-PAD
R2301
0R0402-PAD
12
C2322
SCD01U16V2KX-3GP
C2322
SCD01U16V2KX-3GP
1 2
R2305 0R3J-0-U-GP
DY
R2305 0R3J-0-U-GP
DY
12
C2315
SC1U10V2KX-1GP
C2315
SC1U10V2KX-1GP
12
C2307
SCD01U16V2KX-3GP
C2307
SCD01U16V2KX-3GP
12
C2305
SC1U10V2KX-1GP
C2305
SC1U10V2KX-1GP
1 2
R2302 0R3J-0-U-GP
DY
R2302 0R3J-0-U-GP
DY
12
C2317
SC10U6D3V3MX-GP
DY
C2317
SC10U6D3V3MX-GP
DY
12
C2323
SCD1U10V2KX-4GP
C2323
SCD1U10V2KX-4GP
12
C2321
SC1U10V2KX-1GP
C2321
SC1U10V2KX-1GP
VCCCORE1
AA23
VCCCORE2
AC23
VCCCORE3
AD21
VCCCORE4
AD23
VCCCORE5
AF21
VCCCORE6
AF23
VCCCORE7
AG21
VCCCORE8
AG23
VCCCORE9
AG24
VCCCORE10
AG26
VCCCORE11
AG27
VCCCORE12
AG29
VCCCORE13
AJ23
VCCCORE14
AJ26
VCCCORE15
AJ27
VCCDFTERM4 AJ17
VCCDFTERM3 AJ16
VCCIO17
AN21
VCCIO18
AN26
VCCIO19
AN27
VCCIO20
AP21
VCCIO23
AP26
VCCIO24
AT24
VCCIO15
AN16
VCCIO16
AN17
VCCIO21
AP23
VCCIO22
AP24
VCCADAC U48
VCCTX_LVDS1 AM37
VCCTX_LVDS2 AM38
VCCALVDS AK36
VCCVRM3 AT16
VCCVRM2
AP16
VCCAPLLEXP
BJ22
VCCAFDIPLL
BG6
VCCIO28
AN19 VCCTX_LVDS4 AP37
VCCTX_LVDS3 AP36
VSSADAC U47
VSSALVDS AK37
VCCIO27
AP17
VCC3_3_6 V33
VCC3_3_7 V34
VCC3_3_3
BH29 VCCDFTERM2 AG17
VCCDFTERM1 AG16
VCCDMI1 AT20
VCCIO25
AN33
VCCIO26
AN34
VCCCORE16
AJ29
VCCCORE17
AJ31
VCCSPI V1
VCCCLKDMI AB36
VCCDMI2
AU20
POWER
VCC CORE
DMI
VCCIO
CRTLVDS
FDI
DFT / SPI HVCMOS
7 OF 10
PCH1G
PANTHER-GP-NF
POWER
VCC CORE
DMI
VCCIO
CRTLVDS
FDI
DFT / SPI HVCMOS
7 OF 10
PCH1G
PANTHER-GP-NF
12
C2313
SC10U6D3V3MX-GP
C2313
SC10U6D3V3MX-GP
1 2
L2301
IND-1UH-100-GP
DY
L2301
IND-1UH-100-GP
DY
12
C2304
SCD1U10V2KX-4GP
C2304
SCD1U10V2KX-4GP
12
C2303
SCD1U10V2KX-4GP
C2303
SCD1U10V2KX-4GP
12
C2302
SC1U10V2KX-1GP
C2302
SC1U10V2KX-1GP
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
+VCCACLK
+V1.05S_VCCA_A_DPL
+V5A_PCH_VCC5REFSUS
+V1.05S_VCCA_B_DPL
+VCCA_USBSUS
PCH_VCCDSW
+V5S_PCH_VCC5REF
+VCCRTCEXT
+VCCAFDI_VRM
+V1.05S_VCCAPLL_SATA3
+V3.3S_VCC_CLKF33
+V3.3S_VCC_CLKF33
+V1.05S_VCCA_B_DPL
+V1.05S_VCCA_A_DPL
+VCCPDSW
+VCCAPLL_CPY_PCH
+VCCSUS1
PCH_DCPSST
+V1.05M_VCCSUS
1D05V_S0
RTC_AUX_S5
3D3V_S0
3D3V_S5
3D3V_S5
3D3V_S5 5V_S5
1D05V_S0
3D3V_S5
1D05V_S0
+VCCAFDI_VRM
1D05V_S0
3D3V_S0 5V_S0
3D3V_S0
3D3V_S0
3D3V_S5
3D3V_S5
1D05V_S0
1D05V_S0
1D05V_S0
1D05V_S0 1D05V_S0
1D05V_S0
1D05V_S0
1D05V_S0
1D05V_S0
1D05V_S0
1D05V_S0
1D05V_S0
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(8/9) : PWR2
A3
24 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(8/9) : PWR2
A3
24 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(8/9) : PWR2
A3
24 103Wednesday, March 14, 2012
<Core Design>
AF33, AF34 and AG34 should be VCCDIFFCLKN[3:1]
55mA
95mA
80mA
80mA
160mA
PCH(8/9)
2mA
2.925A
97mA
1mA
1mA
10mA
6uA
1mA
266mA
1.01A
20120116PV-R
20120201PV-R
20120201PV-R
12
TC2402
SC22U6D3V5MX-2GP
DY
TC2402
SC22U6D3V5MX-2GP
DY
12
C2412
SC1U10V2KX-1GP
C2412
SC1U10V2KX-1GP
12
C2435
SCD1U10V2KX-4GP
C2435
SCD1U10V2KX-4GP
12
C2418
SCD1U10V2KX-4GP
C2418
SCD1U10V2KX-4GP
12
C2402
SC1U10V2KX-1GP
C2402
SC1U10V2KX-1GP
12
C2405
SC1U10V2KX-1GP
C2405
SC1U10V2KX-1GP
12
L2405
IND-10UH-193-GP
DY
L2405
IND-10UH-193-GP
DY
12
C2433
SCD1U10V2KX-4GP
C2433
SCD1U10V2KX-4GP
12
C2414
SC1U10V2KX-1GP
DY
C2414
SC1U10V2KX-1GP
DY
12
C2424
SCD1U10V2KX-4GP
C2424
SCD1U10V2KX-4GP
12
C2406
SCD1U10V2KX-4GP
C2406
SCD1U10V2KX-4GP
1 2
R2401
0R0603-PAD-1-GP
R2401
0R0603-PAD-1-GP
1 2
C2430
SCD1U10V2KX-4GP
C2430
SCD1U10V2KX-4GP
12
C2429
SC1U10V2KX-1GP
C2429
SC1U10V2KX-1GP
12
C2432
SC4D7U6D3V3KX-GP
C2432
SC4D7U6D3V3KX-GP
12
C2436
SCD1U10V2KX-4GP
DY
C2436
SCD1U10V2KX-4GP
DY
12
C2426
SC1U10V2KX-1GP
C2426
SC1U10V2KX-1GP
12
C2409
SCD1U10V2KX-4GP
C2409
SCD1U10V2KX-4GP
12
C2411
SC10U6D3V3MX-GP
C2411
SC10U6D3V3MX-GP
12
C2408
SC1U10V2KX-1GP
DY
C2408
SC1U10V2KX-1GP
DY
1 2
L2401
IND-10UH-238-GP
2nd = 68.1001D.10E
1st = 68.1001A.10B
3rd = 68.1001A.10B
L2401
IND-10UH-238-GP
2nd = 68.1001D.10E
1st = 68.1001A.10B
3rd = 68.1001A.10B
1 2
R2405 0R3J-0-U-GP
DY
R2405 0R3J-0-U-GP
DY
12
C2407
SCD1U10V2KX-4GP
C2407
SCD1U10V2KX-4GP
12
C2422
SCD1U10V2KX-4GP
C2422
SCD1U10V2KX-4GP
12
C2410
SC10U6D3V3MX-GP
C2410
SC10U6D3V3MX-GP
12
C2415
SC1U10V2KX-1GP
DY
C2415
SC1U10V2KX-1GP
DY
AK
D2401
CH751H-40-1-GP
83.R0304.D8F
2ND = 83.R2004.C8F
3RD = 83.1PS76.01F
D2401
CH751H-40-1-GP
83.R0304.D8F
2ND = 83.R2004.C8F
3RD = 83.1PS76.01F
12
C2419
SCD1U10V2KX-4GP
C2419
SCD1U10V2KX-4GP
12
TC2401
SC22U6D3V5MX-2GP
DY
TC2401
SC22U6D3V5MX-2GP
DY
1 2
L2402 IND-10UH-238-GP
1st = 68.1001A.10B
2nd = 68.1001D.10E
3rd = 68.1001A.10B
L2402 IND-10UH-238-GP
1st = 68.1001A.10B
2nd = 68.1001D.10E
3rd = 68.1001A.10B
12
C2434
SCD1U10V2KX-4GP
C2434
SCD1U10V2KX-4GP
12
C2431
SC1U10V2KX-1GP
DY
C2431
SC1U10V2KX-1GP
DY
1 2
R2404 0R3J-0-U-GP
DY
R2404 0R3J-0-U-GP
DY
12
C2438
SCD1U10V2KX-4GP
C2438
SCD1U10V2KX-4GP
AK
D2402
CH751H-40-1-GP
2ND = 83.R2004.C8F
83.R0304.D8F
3RD = 83.1PS76.01F
D2402
CH751H-40-1-GP
2ND = 83.R2004.C8F
83.R0304.D8F
3RD = 83.1PS76.01F
12
R2402
10R2J-2-GP
R2402
10R2J-2-GP
12
C2420
SC1U10V2KX-1GP
C2420
SC1U10V2KX-1GP
12
C2427
SC1U10V2KX-1GP
C2427
SC1U10V2KX-1GP
1 2
L2403
IND-10UH-238-GP
2nd = 68.1001D.10E
1st = 68.1001A.10B
3rd = 68.1001A.10B
L2403
IND-10UH-238-GP
2nd = 68.1001D.10E
1st = 68.1001A.10B
3rd = 68.1001A.10B
12
C2403
SCD1U10V2KX-4GP
C2403
SCD1U10V2KX-4GP
12
C2417
SC1U10V2KX-1GP
C2417
SC1U10V2KX-1GP
12
C2423
SC1U10V2KX-1GP
C2423
SC1U10V2KX-1GP
12
R2403
10R2J-2-GP
R2403
10R2J-2-GP
DCPSUSBYP
V12
VCCASW1
AA19
VCCASW2
AA21
VCCASW3
AA24
VCCASW5
AA27
VCCASW6
AA29
VCCSUSHDA P32
VCCSUS3_3_6 P24
VCCIO34 T26
VCCIO4 AD17
VCCASW7
AA31
VCCASW8
AC26
VCCASW9
AC27
VCCASW10
AC29
VCCASW11
AC31
VCCASW12
AD29
V5REF P34
VCC3_3_4 T34
VCCRTC
A22
VCCSUS3_3_10 V24
VCCSUS3_3_9 V23
VCCSUS3_3_8 T24
VCCSUS3_3_7 T23
VCCIO2 AC16
VCCADPLLB
BF47
VCCDIFFCLKN1
AF33
V5REF_SUS M26
VCCIO3 AC17
DCPSUS1
T17
VCCSSC
AG33
VCCADPLLA
BD47
VCCVRM4
Y49
VCCACLK
AD49
DCPRTC
N16
VCCASW4
AA26
VCCDIFFCLKN2
AF34
VCCIO7
AF17
DCPSST
V16
VCCIO5 AF13
VCCASW22 T21
VCCASW23 V21
VCCASW21 T19
VCC3_3_1 AA16
VCC3_3_8 W16
VCCSUS3_3_2 N20
VCCSUS3_3_3 N22
VCCSUS3_3_4 P20
VCCSUS3_3_5 P22
VCCIO29 N26
VCCIO30 P26
VCCIO31 P28
VCCIO32 T27
V_PROC_IO
BJ8
VCCIO33 T29
VCCDIFFCLKN3
AG34
VCCASW13
AD31
VCCASW14
W21
VCCASW15
W23
VCCASW16
W24
VCCASW17
W26
VCCASW18
W29
VCCASW19
W31
VCCASW20
W33
VCCIO6 AF14
VCCVRM1 AF11
VCCIO12 AH13
VCCIO13 AH14
VCC3_3_2 AJ2
VCCAPLLSATA AK1
DCPSUS3
AL24
VCCIO14
AL29
DCPSUS4 AN23
VCCSUS3_3_1 AN24
VCCAPLLDMI2
BH23
DCPSUS2
V19
VCCDSW3_3
T16
VCC3_3_5
T38
POWER
SATA USB
Clock and Miscellaneous
HDA
CPURTC
PCI/GPIO/LPCMISC
10 OF 10
PCH1J
PANTHER-GP-NF
POWER
SATA USB
Clock and Miscellaneous
HDA
CPURTC
PCI/GPIO/LPCMISC
10 OF 10
PCH1J
PANTHER-GP-NF
12
C2425
SC10U6D3V3MX-GP
DY
C2425
SC10U6D3V3MX-GP
DY
12
C2416
SC1U10V2KX-1GP
C2416
SC1U10V2KX-1GP
12
C2439
SC10U6D3V3MX-GP
DY
C2439
SC10U6D3V3MX-GP
DY
12
C2413
SC1U10V2KX-1GP
C2413
SC1U10V2KX-1GP
12
C2421
SC1U10V2KX-1GP
C2421
SC1U10V2KX-1GP
12
C2401
SCD1U10V2KX-4GP
DY
C2401
SCD1U10V2KX-4GP
DY
12
C2404
SC10U6D3V3MX-GP
C2404
SC10U6D3V3MX-GP
12
C2437
SC1U10V2KX-1GP
DY
C2437
SC1U10V2KX-1GP
DY
1 2
L2404
IND-10UH-193-GP
DY
L2404
IND-10UH-193-GP
DY
12
C2428
SC1U10V2KX-1GP
C2428
SC1U10V2KX-1GP
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(9/9) : GND
A3
25 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(9/9) : GND
A3
25 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH(9/9) : GND
A3
25 103Wednesday, March 14, 2012
<Core Design>
PCH(9/9)
VSS159
AY4
VSS160
AY42
VSS161
AY46
VSS162
AY8
VSS163
B11
VSS164
B15
VSS165
B19
VSS166
B23
VSS167
B27
VSS168
B31
VSS169
B35
VSS170
B39
VSS171
B7
VSS173
BB12
VSS174
BB16
VSS175
BB20
VSS176
BB22
VSS177
BB24
VSS178
BB28
VSS179
BB30
VSS180
BB38
VSS181
BB4
VSS182
BB46
VSS183
BC14
VSS184
BC18
VSS185
BC2
VSS186
BC22
VSS187
BC26
VSS188
BC32
VSS189
BC34
VSS190
BC36
VSS191
BC40
VSS192
BC42
VSS193
BC48
VSS194
BD46
VSS195
BD5
VSS196
BE22
VSS197
BE26
VSS198
BE40
VSS199
BF10
VSS200
BF12
VSS201
BF16
VSS202
BF20
VSS203
BF22
VSS204
BF24
VSS205
BF26
VSS206
BF28
VSS207
BD3
VSS208
BF30
VSS209
BF38
VSS210
BF40
VSS211
BF8
VSS212
BG17
VSS213
BG21
VSS214
BG33
VSS215
BG44
VSS216
BG8
VSS217
BH11
VSS218
BH15
VSS219
BH17
VSS220
BH19
VSS222
BH27
VSS223
BH31
VSS224
BH33
VSS225
BH35
VSS226
BH39
VSS227
BH43
VSS228
BH7
VSS229
D3
VSS230
D12
VSS231
D16
VSS232
D18
VSS233
D22
VSS234
D24
VSS235
D26
VSS236
D30
VSS237
D32
VSS264 K7
VSS265 L18
VSS266 L2
VSS267 L20
VSS268 L26
VSS269 L28
VSS270 L36
VSS271 L48
VSS272 M12
VSS273 P16
VSS274 M18
VSS275 M22
VSS276 M24
VSS277 M30
VSS278 M32
VSS279 M34
VSS280 M38
VSS281 M4
VSS282 M42
VSS283 M46
VSS284 M8
VSS285 N18
VSS286 P30
VSS288 P11
VSS289 P18
VSS290 T33
VSS291 P40
VSS292 P43
VSS293 P47
VSS294 P7
VSS295 R2
VSS296 R48
VSS297 T12
VSS298 T31
VSS299 T37
VSS300 T4
VSS301 W34
VSS302 T46
VSS303 T47
VSS304 T8
VSS305 V11
VSS306 V17
VSS307 V26
VSS308 V27
VSS309 V29
VSS310 V31
VSS311 V36
VSS312 V39
VSS313 V43
VSS314 V7
VSS315 W17
VSS316 W19
VSS238
D34
VSS239
D38
VSS240
D42
VSS241
D8
VSS242
E18
VSS243
E26
VSS244
G18
VSS245
G20
VSS246
G26
VSS247
G28
VSS248
G36
VSS249
G48
VSS250
H12
VSS251
H18
VSS317 W2
VSS318 W27
VSS319 W48
VSS320 Y12
VSS321 Y38
VSS322 Y4
VSS323 Y42
VSS324 Y46
VSS325 Y8
VSS328 BG29
VSS329 N24
VSS330 AJ3
VSS287 N47
VSS252
H22
VSS253
H24
VSS254
H26
VSS255
H30
VSS256
H32
VSS257
H34
VSS258
F3
VSS262 K39
VSS263 K46
VSS259 H46
VSS260 K18
VSS261 K26
VSS331 AD47
VSS333 B43
VSS334 BE10
VSS335 BG41
VSS337 G14
VSS338 H16
VSS340 T36
VSS342 BG22
VSS343 BG24
VSS344 C22
VSS345 AP13
VSS172
F45
VSS221
H10
VSS346 M14
VSS347 AP3
VSS348 AP1
VSS349 BE16
VSS350 BC16
VSS351 BG28
VSS352 BJ28
9 OF 10
PCH1I
PANTHER-GP-NF
9 OF 10
PCH1I
PANTHER-GP-NF
VSS1
AA17
VSS2
AA2
VSS3
AA3
VSS5
AA34
VSS6
AB11
VSS7
AB14
VSS8
AB39
VSS9
AB4
VSS10
AB43
VSS11
AB5
VSS12
AB7
VSS13
AC19
VSS14
AC2
VSS15
AC21
VSS16
AC24
VSS17
AC33
VSS18
AC34
VSS19
AC48
VSS20
AD10
VSS21
AD11
VSS22
AD12
VSS23
AD13
VSS24
AD19
VSS25
AD24
VSS26
AD26
VSS27
AD27
VSS28
AD33
VSS29
AD34
VSS30
AD36
VSS31
AD37
VSS33
AD39
VSS34
AD4
VSS35
AD40
VSS36
AD42
VSS37
AD43
VSS38
AD45
VSS39
AD46
VSS43
AF10
VSS44
AF12
VSS46
AD16
VSS47
AF16
VSS48
AF19
VSS49
AF24
VSS50
AF26
VSS51
AF27
VSS52
AF29
VSS53
AF31
VSS54
AF38
VSS55
AF4
VSS56
AF42
VSS57
AF46
VSS59
AF7
VSS60
AF8
VSS61
AG19
VSS62
AG2
VSS63
AG31
VSS64
AG48
VSS65
AH11
VSS66
AH3
VSS67
AH36
VSS68
AH39
VSS69
AH40
VSS70
AH42
VSS71
AH46
VSS72
AH7
VSS73
AJ19
VSS76
AJ33
VSS77
AJ34
VSS78
AK12
VSS79
AK3
VSS80 AK38
VSS81 AK4
VSS82 AK42
VSS83 AK46
VSS84 AK8
VSS85 AL16
VSS86 AL17
VSS87 AL19
VSS88 AL2
VSS89 AL21
VSS90 AL23
VSS91 AL26
VSS92 AL27
VSS93 AL31
VSS96 AL48
VSS97 AM11
VSS98 AM14
VSS99 AM36
VSS100 AM39
VSS102 AM45
VSS103 AM46
VSS104 AM7
VSS105 AN2
VSS106 AN29
VSS107 AN3
VSS108 AN31
VSS109 AP12
VSS110 AP19
VSS111 AP28
VSS112 AP30
VSS113 AP32
VSS114 AP38
VSS116 AP42
VSS117 AP46
VSS118 AP8
VSS119 AR2
VSS120 AR48
VSS121 AT11
VSS122 AT13
VSS123 AT18
VSS124 AT22
VSS125 AT26
VSS126 AT28
VSS127 AT30
VSS128 AT32
VSS131 AT42
VSS132 AT46
VSS133 AT7
VSS134 AU24
VSS135 AU30
VSS136 AV16
VSS137 AV20
VSS138 AV24
VSS139 AV30
VSS140 AV38
VSS141 AV4
VSS142 AV43
VSS143 AV8
VSS144 AW14
VSS145 AW18
VSS146 AW2
VSS147 AW22
VSS148 AW26
VSS149 AW28
VSS150 AW32
VSS151 AW34
VSS152 AW36
VSS153 AW40
VSS154 AW48
VSS155 AV11
VSS156 AY12
VSS157 AY22
VSS158 AY28
VSS40
AD8
VSS42
AE3
VSS45
AD14
VSS115 AP4
VSS0
H5
VSS58
AF5
VSS32
AD38
VSS4
AA33
VSS74
AJ21
VSS75
AJ24
VSS41
AE2
VSS129 AT34
VSS130 AT39
VSS101 AM43
VSS95 AL34
VSS94 AL33
8 OF 10
PCH1H
PANTHER-GP-NF
8 OF 10
PCH1H
PANTHER-GP-NF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH_XDP
A3
26 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH_XDP
A3
26 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
PCH_XDP
A3
26 103Wednesday, March 14, 2012
<Core Design>
(Blanking)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TACH_FAN_IN_R
ADC_VREF_L
KBC_DDR_RST#
GPIO17
GPIO8/RXD
KSO17
VOLTAGE_ADC_R
KBC_CAP
PWR_GOOD
VOLTAGE_ADC_R
OCP_IN_ADC_L
ADP_EN_L
ADC_VREF_L
CURRENT_ADC_L
FET_A
RSMRST#_R
PGD_IN
CHG_RST
KBC_DDR_RST#
8051_RECOVER#
PWM_LED#
VCC1_POR#
AMBER_BATLED#
PLT_DET
SPI_CS1#_R
KSI7
KSI0
KSI6
KSI2
KBRST#_L
KBC_GPIO37
PWR_BTN_OUT#_KBC PLT_DET
ADP_ID_ADC_L
OCP_IN_ADC_L
GPIO8/RXD
CURRENT_ADC_L
KCB_GPIO33
KBC_GPIO15
TACH_FAN_IN_R
PGD_IN
VREF_PECI
1070_TEST
PM_SLP_S4#_KBC
1070_VCC2
VCC1_POR#
KBRST#_L
ADP_DET_R
KSI0
KSI3
KSI2
KSI1
KSI4
KSI7
KSI6
KSI5
LPC_AD2
LPC_AD1
LPC_AD0
LPC_AD3
ADP_ID_ADC_L
SPI_CS1#_R
CPPWR_EN
EC_PECI
RSMRST#_R
KBC_GPIO36
KBC_PWR_ON
SUSCLK32_KBC_IN
ADP_EN_L
8051RX/CAPS_LED
8051TX/S3_LED#
FET_A
FET_B
FET_B
KSO14
KSO15
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO5
KSO15
PWR_BD_LED#
KB_CAPS_LED8051RX/CAPS_LED
8051TX/S3_LED#
TP_LED#
KSI4
KSI5
KSI3
KSI1
VOLTAGE_ADC
KBC_GPIO15
KBC_DDR_RST#
KBC_AGND
3D3V_S0
3D3V_S0
+VCC0 RTC_AUX_S5
3D3V_AUX_S5
3D3V_AUX_S5
3D3V_AUX_S5
KBC_AGND
3D3V_AUX_S5
+VCC0
3D3V_AUX_KBC
3D3V_AUX_S5
3D3V_AUX_KBC
KBC_AGND
1D05V_S0
3D3V_AUX_KBC
3D3V_AUX_S5
3D3V_AUX_KBC
3D3V_S5
PM_SLP_S3#8,19,29,34,35,36,37,45,46,47,48,92,93
TACH_FAN_IN28
SPI_CS1#17,71
IMDAT31
KBC_PWR_ON 41
PM_CLKRUN#19
SPI_SI_FLASH60
LID_SW#49,82,97
A_SD# 29
FAN_PWM 28
CHARGER_CLK 40
CURRENT_ADC38
ADC_VREF38
IMCLK31
WLAN_OFF53
SPI_CS0#_FLASH60
CHARGER_DAT 40
NMI_SMI_DBG# 21,71
KBRST# 22,97
GATEA20 22
RSMRST# 19,41,97
8051RX/CAPS_LED 71
ADP_PRES_OUT 19,85
8051TX/S3_LED# 71
AB1A_CLK 39,97
AMBER_BATLED# 82
AB1A_DATA 39,97
PM_PWROK 19,97
PWR_GOOD 5,37,42,50,96
BAT_GRNLED# 17,82
SPI_CLK_FLH60
LPC_FRAME#17,71 LPC_RESET#22
KSI[0..7]69,82,97
RUNSCI_EC#22
LPC_AD[3:0]17,71
WWAN_OFF54
CLK_PCI_KBC21,97
SPI_SO_FLASH60
PCH_KBC_DATA 18,28,85
OCP_A_IN38
PCH_KBC_CLK 18,28,85
KBC_PROCHOT 5
ADP_PRES 34,38
PWR_BTN_OUT#19
OCP_PWM_OUT38
ADP_A_ID38
SUSCLK32_KBC19
ON/OFFBTN_KBC# 82
VCC1_POR# 71
PM_SLP_A# 19
SUS_PWR_ACK 19
PM_SLP_S3# 8,19,29,34,35,36,37,45,46,47,48,92,93
8051_RECOVER# 71
KSO1782,97
H_PECI 5,22
MAIN_BAT_DET#39,97
QUICKX_LED#82,97
CHG_RST40
VOLTAGE_ADC 38
ADP_EN40
ADP_DET40
KSO[0..15]69,97
PLT_DET 21,69
SIRQ17,71
PWR_BD_LED# 82
KB_CAPS_LED 69,97
PM_SLP_S4#_KBC46
KBC_DDR_RST# 5,46
KBC_GPIO5141
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
KBC_SMSC_KBC1126
A3
27 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
KBC_SMSC_KBC1126
A3
27 103Wednesday, March 14, 2012
<Core Design>
Title
Size Document Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2012 S-Series Richie 13.3
-1
KBC_SMSC_KBC1126
A3
27 103Wednesday, March 14, 2012
<Core Design>
127
KBC PIN
122
113
60
100
85
123
77
78
75
63
86
Keyboard Matrix:
high for 13"&14"
and low for 15"&17"
114
83
115
61
116
PM_PWROK DELAY 99ms 92
20111117PV
20111122PV
20120112 PV-R
20120112 PV-R
20120112 PV-R
20120112 PV-R
20120112 PV-R
20120112 PV-R
20120112 PV-R
20120116PV-R
20120131PVR
20120201PV-R
20120201PV-R
20120210PV-R
20120210PV-R
1 2
R2721 0R2J-2-GP
DY
R2721 0R2J-2-GP
DY
1 2
R2713 22KR2J-GP
DY_DS3
R2713 22KR2J-GP
DY_DS3
12
C2712SC100P50V2JN-3GP C2712SC100P50V2JN-3GP
1 2
R2709 100KR2J-1-GPR2709 100KR2J-1-GP
1 2
C2714
SCD1U16V2ZY-2GP
C2714
SCD1U16V2ZY-2GP
1 2
R2744 0R0402-PADR2744 0R0402-PAD
1
2 3
4
RN2703
SRN100KJ-6-GP
RN2703
SRN100KJ-6-GP
1<