Emerson Kat4000 Users Manual

2015-01-05

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KAT4000: AMC Carrier for ATCA®
User’s Manual
from Emerson Network Power
Embedded Computing
April 2007
The information in this manual has been checked and is believed to be accurate and reli-
able. HOWEVER, NO RESPONSIBILITY IS ASSUMED BY ARTESYN COMMUNICATION PROD-
UCTS FOR ITS USE OR FOR ANY INACCURACIES. Specifications are subject to change
without notice. ARTESYN COMMUNICATION PRODUCTS DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF USE OR OTHER APPLICATION OF ANY PRODUCT, CIRCUIT, OR PROGRAM
DESCRIBED HEREIN. This document does not convey any license under Artesyn Communi-
cation Products patents or the rights of others.
Artesyn and the Artesyn logo are registered trademarks of Artesyn Technologies and are
used by Artesyn Communication Products under license from Artesyn Technologies. All
other trademarks are property of their respective owners.
Copyright © 2007 Artesyn Communication Products. All rights reserved.
Emerson. Consider It Solved is a trademark, and Business-Critical Continuity,
Emerson Network Power, and the Emerson Network Power logo are trademarks
and service marks of Emerson Electric Co. © 2007 Emerson Electric Co.
Revision Level: Principal Changes: Date:
10007175-00 Original release January 2007
10007175-01 Added “Appendix A” February 2007
10007175-02 Added PCIe functionality; Released 10 GbE-1 GbE
fat pipe switch
April 2007
10007175-02 KAT4000 User’s Manual i
Regulatory Agency Warnings & Notices
The Emerson KAT4000 meets the requirements set forth by the Federal Communications
Commission (FCC) in Title 47 of the Code of Federal Regulations. The following information
is provided as required by this agency.
This device complies with part 15 of the FCC Rules. Operation is subject to the following
two conditions: (1) This device may not cause harmful interference, and (2) this device
must accept any interference received, including interference that may cause undesired
operation.
FCC RULES AND REGULATIONS — PART 15
This equipment has been tested and found to comply with the limits for a Class B digital
device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reason-
able protection against harmful interference in a residential installation. This equipment
generates, uses and can radiate radio frequency energy and, if not installed and used in
accordance with the instructions, may cause harmful interference to radio communica-
tions. However, there is no guarantee that interference will not occur in a particular installa-
tion. If this equipment does cause harmful interference to radio or television reception,
which can be determined by turning the equipment off and on, the user is encouraged to
try to correct the interference by one or more of the following measures:
Reorient or relocate the receiving antenna
Increase the separation between the equipment and receiver
Connect the equipment into an outlet on a circuit different from that to which the
receiver is connected
Consult the dealer or an experienced radio/TV technician for help
Caution: Making changes or modifications to the KAT4000 hardware without the explicit consent of
Emerson Network Power could invalidate the user’s authority to operate this equipment.
EMC COMPLIANCE
The electromagnetic compatibility (EMC) tests used a KAT4000 model that includes a front
panel assembly from Emerson Network Power.
Caution: For applications where the KAT4000 is provided without a front panel, or where the front
panel has been removed, your system chassis/enclosure must provide the required
electromagnetic interference (EMI) shielding to maintain CE compliance.
!
!
Regulatory Agency Warnings & Notices (continued)
KAT4000 User’s Manual 10007175-02
ii
EC Declaration of Conformity
According to EN 45014:1998
Manufacturer’s Name: Emerson Network Power
Embedded Computing
Manufacturer’s Address: 8310 Excelsior Drive
Madison, Wisconsin 53717
Declares that the following product, in accordance with the requirements of 89/336/EEC, EMC
Directive and 99/5/EC, RTTE Directive and their amending directives,
Product: ATCA Carrier
Model Name/Number: KAT4000/10007505-xx
has been designed and manufactured to the following specifications:
EN55022:1998 Information Technology Equipment, Radio disturbance characteristics, Limits and
methods of measurement
EN55024:1998 Information Technology Equipment, Immunity characteristics, Limits and methods
of measurement
EN300386 V.1.3.1 Electromagnetic compatibility and radio spectrum matters (ERM);
Telecommunication network equipment; EMC requirements
As manufacturer we hereby declare that the product named above has been designed to comply
with the relevant sections of the above referenced specifications. This product complies with the
essential health and safety requirements of the EMC Directive and RTTE Directive. We have an
internal production control system that ensures compliance between the manufactured products
and the technical documentation.
Issue date: April 3, 2007
Bill Fleury
Compliance Engineer
10007175-02 KAT4000 User’s Manual iii
Contents
1Overview
Components and Features . . . . . . . . . . . 1-1
KAT4000 Options. . . . . . . . . . . . . . . . 1-3
Functional Overview . . . . . . . . . . . . . . . . 1-5
Physical Memory Map . . . . . . . . . . . . . . . 1-6
AMC Mapping . . . . . . . . . . . . . . . . . . . . . . 1-9
Additional Information . . . . . . . . . . . . . 1-10
Product Certification . . . . . . . . . . . .1-10
UL Certification . . . . . . . . . . . . . . . . .1-11
RoHS Compliance. . . . . . . . . . . . . . .1-11
Terminology and Notation . . . . . . .1-12
Technical References. . . . . . . . . . . .1-12
2Setup
Electrostatic Discharge . . . . . . . . . . . . . . 2-1
KAT4000 Circuit Board . . . . . . . . . . . . . . 2-1
Front Panel . . . . . . . . . . . . . . . . . . . . . 2-4
Connectors . . . . . . . . . . . . . . . . . . . . . 2-4
Header JP4 . . . . . . . . . . . . . . . . . . . . . . 2-5
Jumpers . . . . . . . . . . . . . . . . . . . . . . . . 2-5
JTAG Interfaces . . . . . . . . . . . . . . . . . . 2-9
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
Reset. . . . . . . . . . . . . . . . . . . . . . . . . .2-13
KAT4000 Setup . . . . . . . . . . . . . . . . . . . . 2-15
Identification Numbers . . . . . . . . . .2-15
Power Requirements . . . . . . . . . . . .2-16
Environmental Considerations . . .2-16
Troubleshooting . . . . . . . . . . . . . . . . . . . 2-17
Technical Support . . . . . . . . . . . . . .2-17
Product Repair . . . . . . . . . . . . . . . . .2-18
3 Central Processing Unit
MPC8548 Functions . . . . . . . . . . . . . . . . . 3-3
Microprocessor Core (e500). . . . . . . . . . 3-3
L1 Cache. . . . . . . . . . . . . . . . . . . . . . . . 3-3
L2 Cache. . . . . . . . . . . . . . . . . . . . . . . . 3-3
Timer/Counter . . . . . . . . . . . . . . . . . . 3-4
PCI Device and Vendor ID Assignment.
3-4
L2 Control Register (L2CR) . . . . . . . . 3-4
Hardware Implementation Dependent
0 Register. . . . . . . . . . . . . . . . . . . . . . . 3-6
Hardware Implementation Dependent
1 Register. . . . . . . . . . . . . . . . . . . . . . . 3-7
Interrupts and Exception Processing. . . 3-8
Machine State Register. . . . . . . . . . . 3-9
Peripheral Interface . . . . . . . . . . . . . . . . 3-10
MPC8548 Peripheral Modules . . . . . . . 3-11
Three-Speed Ethernet Controllers
(TSEC) . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Local Bus Controller (LBC) . . . . . . . 3-12
Chip Select Generation. . . . . . . . . . 3-12
Processor Reset and Clocking Signals. 3-12
MPC8548 Exception Handling . . . . . . . 3-13
JTAG/COP Interface . . . . . . . . . . . . . . . . 3-14
No Processor Configuration . . . . . . . . . 3-15
4 Common Switch Region
Ethernet Core Switch (optional) . . . . . . .4-2
Switch Configuration . . . . . . . . . . . . 4-3
High-Speed Serial Data Path
Configuration . . . . . . . . . . . . . . . . . . . 4-3
On-Board Path Device Settings 4-4
Off-Board Path Device Settings4-4
Ethernet Transceivers . . . . . . . . . . . . 4-5
Ethernet Address for the KAT4000 . . . . .4-5
Ethernet Address for the GbE Fat Pipe Switch
Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6
PCI Express Switch (optional). . . . . . . . . .4-7
PCI Express Interface. . . . . . . . . . . . . 4-8
EEPROM Interface . . . . . . . . . . . . . . . 4-9
JTAG Controller Interface . . . . . . . . . 4-9
5 Fat Pipe Switch Module
GbE Fat Pipe Switch Module. . . . . . . . . . .5-2
GbE Fat Pipe Switch Module Circuit
Board . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Components and Features. . . . . . . . 5-5
GbE Fat Pipe Switch Module PLD . . 5-6
Product ID/Version Register . . 5-6
Scratch Register . . . . . . . . . . . . . 5-7
I2C Register. . . . . . . . . . . . . . . . . 5-7
Signal Detect Register . . . . . . . 5-8
Switch Reset Register . . . . . . . . 5-8
Module Status Register . . . . . . 5-8
Switch GPIO Register . . . . . . . . 5-9
GPIN/LED Register . . . . . . . . . . . 5-9
10 GbE-1 GbE Fat Pipe Switch Module 5-11
10 GbE-1 GbE Fat Pipe Switch Module
Circuit Board. . . . . . . . . . . . . . . . . . . 5-13
Components and Features. . . . . . . 5-14
Contents (continued)
KAT4000 User’s Manual 10007175-02
iv
10 GbE-1 GbE Fat Pipe Switch Module
PLD . . . . . . . . . . . . . . . . . . . . . . . . . . .5-16
Product ID/Version Register. .5-16
Scratch Register . . . . . . . . . . . .5-17
I2C Register . . . . . . . . . . . . . . . .5-17
Reserved Register 1 . . . . . . . . .5-18
Switch Reset Register . . . . . . .5-18
Module Status Register . . . . . .5-19
Switch GPIO Register. . . . . . . .5-19
GPIN/LED Register . . . . . . . . . .5-20
10 GbE-10 GbE Fat Pipe Switch Module5-21
sRIO Fat Pipe Switch Module . . . . . . . . 5-22
6 Memory Configuration
Boot Memory Configuration . . . . . . . . . .6-1
User Flash. . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
On-Card SDRAM . . . . . . . . . . . . . . . . . . . . .6-2
NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . .6-2
NVRAM Allocation . . . . . . . . . . . . . . . . . . .6-3
7CPLD
PLD Register Summary . . . . . . . . . . . . . . .7-1
Version and ID Registers . . . . . . . . . . . . . .7-2
Product ID Register (PIDR) . . . . . . . . 7-2
Hardware Version Register (HVR) . . 7-3
PLD Version Register (PVR) . . . . . . . 7-3
Configuration Registers . . . . . . . . . . . . . .7-4
Hardware Configuration Register 0
(HCR0) . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
PLL Configuration Register (PLLC). . 7-4
Miscellaneous Registers . . . . . . . . . . . . . .7-5
LED Control Register (LEDR). . . . . . . 7-5
Jumper Settings Register (JSR). . . . . 7-6
RTM GPIO State Register (RGSR). . . 7-6
RTM GPIO Control Register (RGCR) 7-7
MISC Control Register (MISC) . . . . . 7-7
Scratch Register 1 (SCR1) . . . . . . . . . 7-8
Boot and Reset Registers . . . . . . . . . . . . .7-8
Reset Event Register (RER) . . . . . . . . 7-8
Reset Command Register 1 (RCR1) 7-9
Reset Command Register 2 (RCR2)7-10
Boot Device Redirection Register
(BDRR) . . . . . . . . . . . . . . . . . . . . . . . .7-11
Clock Synchronizer Registers . . . . . . . . 7-13
Clock Synchronizer Control Registers 1-
3 (CSC1—CSC3) . . . . . . . . . . . . . . . . .7-13
Clock Synchronizer Primary Source
Registers 1-3 (CPS1—CPS3) . . . . . . 7-14
Clock Synchronizer Secondary Source
Registers 1-3 (CSS1—CSS3) . . . . . . 7-15
Clock Control Registers (CCR1—CCR14)
7-17
Clock Synchronizer Interrupt Registers
(CSI1-CSI3) . . . . . . . . . . . . . . . . . . . . 7-18
JTAG Interface . . . . . . . . . . . . . . . . . . . . . 7-19
8AMC Sites
AMC Connectors . . . . . . . . . . . . . . . . . . . .8-2
AMC Signals. . . . . . . . . . . . . . . . . . . . . . . . .8-2
Pin Assignments . . . . . . . . . . . . . . . . . . . . .8-4
SATA Lines . . . . . . . . . . . . . . . . . . . . . . . . . .8-6
9 System Management
IPMC Overview . . . . . . . . . . . . . . . . . . . . . .9-1
IPMI Messaging. . . . . . . . . . . . . . . . . . . . . .9-3
IPMI Completion Codes . . . . . . . . . . 9-4
IPMB Protocol . . . . . . . . . . . . . . . . . . . . . . .9-5
SIPL Protocol . . . . . . . . . . . . . . . . . . . . . . . .9-6
Message Bridging. . . . . . . . . . . . . . . . . . . .9-7
Standard Commands. . . . . . . . . . . . . . . . .9-9
Vendor Commands . . . . . . . . . . . . . . . . 9-12
Get Status Command . . . . . . . . . . . 9-12
Get Serial Interface Properties
Command. . . . . . . . . . . . . . . . . . . . . 9-14
Set Serial Interface Properties
Command. . . . . . . . . . . . . . . . . . . . . 9-15
Get Debug Level Command . . . . . 9-16
Set Debug Level Command . . . . . . 9-17
Get Hardware Address Command 9-17
Set Hardware Address Command 9-18
Get Handle Switch Command. . . . 9-18
Set Handle Switch Command . . . . 9-19
Get Payload Communication Time-Out
Command. . . . . . . . . . . . . . . . . . . . . 9-19
Set Payload Communication Time-Out
Command. . . . . . . . . . . . . . . . . . . . . 9-20
Enable Payload Control Command9-20
Disable Payload Control Command . . .
9-20
Reset IPMC Command . . . . . . . . . . 9-21
Hang IPMC Command . . . . . . . . . . 9-21
Bused Resource Control Command . . .
9-22
Contents (continued)
10007175-02 KAT4000 User’s Manual v
Bused Resource Status Command 9-22
Graceful Reset Command. . . . . . . .9-23
Diagnostic Interrupt Results . . . . .9-24
Get Payload Shutdown Time-Out
Command . . . . . . . . . . . . . . . . . . . . .9-24
Set Payload Shutdown Time-Out
Command . . . . . . . . . . . . . . . . . . . . .9-25
Get Module State Command . . . . .9-25
Enable AMC Site Command . . . . . .9-26
Disable AMC Site Command . . . . .9-26
IPMC Watchdog Timer Commands. . . 9-27
Watchdog Timer Actions . . . . . . . .9-27
Watchdog Timer Use Field and
Expiration Flags . . . . . . . . . . . . . . . .9-27
Using the Timer Use Field and
Expiration Flags. . . . . . . . . . . . .9-28
Watchdog Timer Event Logging . .9-28
Monitor Support for Watchdog
Timer . . . . . . . . . . . . . . . . . . . . .9-29
Reset Watchdog Timer Command9-29
Set Watchdog Timer Command . . 9-29
Get Watchdog Timer Command. . 9-31
FRU LEDs . . . . . . . . . . . . . . . . . . . . . . . . . 9-33
Get FRU LED Properties Command9-34
Get LED Color Capabilities Command .
9-34
Set FRU LED State Command. . . . .9-36
Get FRU LED State Command . . . . 9-38
Entities and Entity Associations . . . . . . 9-39
Sensors and Sensor Data Records . . . . 9-40
FRU Inventory . . . . . . . . . . . . . . . . . . . . . 9-44
E-Keying . . . . . . . . . . . . . . . . . . . . . . . . . . 9-45
Base Point-to-Point Connectivity .9-45
Carrier Point-to-Point Connectivity9-46
Firmware Upgrade . . . . . . . . . . . . . . . . . 9-47
Firmware Upgrade Status Command . .
9-47
Firmware Upgrade Start Command . . .
9-48
Firmware Upgrade Prepare Command
9-49
Firmware Upgrade Write Command . .
9-49
Firmware Upgrade Complete
Command . . . . . . . . . . . . . . . . . . . . .9-50
Firmware Upgrade Restore Backup
Command . . . . . . . . . . . . . . . . . . . . .9-50
Firmware Upgrade Backup Revision
Command . . . . . . . . . . . . . . . . . . . . .9-51
Firmware Upgrade Termination . . 9-51
Firmware Upgrade Sequence . . . . 9-51
10Synchronization Clocks
MT9045 and MT9046 Clock Synchronizers .
10-2
11 Real-Time Clock
Block Diagram. . . . . . . . . . . . . . . . . . . . . 11-1
Operation . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Clock Operation . . . . . . . . . . . . . . . . . . . 11-2
12Connectors
Zone 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Zone 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Zone 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
13Rear Transition Module
Components and Features . . . . . . . . . . 13-1
Functional Overview . . . . . . . . . . . . . . . 13-2
Circuit Board . . . . . . . . . . . . . . . . . . . . . . 13-3
Face Plate. . . . . . . . . . . . . . . . . . . . . . . . . 13-5
Connectors . . . . . . . . . . . . . . . . . . . . . . . 13-5
Console Serial Ports. . . . . . . . . . . . . 13-5
Ethernet Port . . . . . . . . . . . . . . . . . . 13-6
Zone 3 . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Identification Numbers . . . . . . . . . 13-7
Installation. . . . . . . . . . . . . . . . . . . . . . . . 13-7
14 Monitor
Command-Line Features. . . . . . . . . . . . 14-1
Basic Operation . . . . . . . . . . . . . . . . . . . 14-4
Power-up/Reset Sequence . . . . . . 14-4
POST Diagnostic Results . . . . . . . . 14-6
Monitor SDRAM Usage . . . . . . . . . . 14-6
Monitor Recovery and Updates . . . . . . 14-6
Recovering the Monitor . . . . . . . . . 14-7
Resetting Environment Variables . 14-7
Updating the Monitor via TFTP . . . 14-7
Monitor Command Reference . . . . . . . 14-8
Command Syntax . . . . . . . . . . . . . . 14-8
Command Help . . . . . . . . . . . . . . . . 14-9
Contents (continued)
KAT4000 User’s Manual 10007175-02
vi
Typographic Conventions . . . . . . .14-9
Boot Commands. . . . . . . . . . . . . . . . . . . 14-9
bootd . . . . . . . . . . . . . . . . . . . . . . . . .14-9
bootelf . . . . . . . . . . . . . . . . . . . . . . . .14-9
bootm . . . . . . . . . . . . . . . . . . . . . . . .14-9
bootp . . . . . . . . . . . . . . . . . . . . . . . . .14-9
bootv . . . . . . . . . . . . . . . . . . . . . . . .14-10
bootvx . . . . . . . . . . . . . . . . . . . . . . .14-10
dhcp . . . . . . . . . . . . . . . . . . . . . . . . .14-10
rarpboot. . . . . . . . . . . . . . . . . . . . . .14-11
tftpboot . . . . . . . . . . . . . . . . . . . . . .14-11
File Load Commands . . . . . . . . . . . . . . 14-12
loadb . . . . . . . . . . . . . . . . . . . . . . . .14-12
loads . . . . . . . . . . . . . . . . . . . . . . . . .14-12
Memory Commands . . . . . . . . . . . . . . 14-12
cmp. . . . . . . . . . . . . . . . . . . . . . . . . .14-13
cp . . . . . . . . . . . . . . . . . . . . . . . . . . .14-13
find . . . . . . . . . . . . . . . . . . . . . . . . . .14-13
md. . . . . . . . . . . . . . . . . . . . . . . . . . .14-13
mm . . . . . . . . . . . . . . . . . . . . . . . . . .14-14
nm. . . . . . . . . . . . . . . . . . . . . . . . . . .14-14
mw . . . . . . . . . . . . . . . . . . . . . . . . . .14-14
Flash Commands . . . . . . . . . . . . . . . . . 14-15
cp . . . . . . . . . . . . . . . . . . . . . . . . . . .14-15
erase . . . . . . . . . . . . . . . . . . . . . . . . .14-15
flinfo . . . . . . . . . . . . . . . . . . . . . . . . .14-15
protect . . . . . . . . . . . . . . . . . . . . . . .14-16
EEPROM/I2C Commands . . . . . . . . . . 14-16
eeprom . . . . . . . . . . . . . . . . . . . . . .14-16
icrc32 . . . . . . . . . . . . . . . . . . . . . . . .14-17
iloop . . . . . . . . . . . . . . . . . . . . . . . . .14-17
imd . . . . . . . . . . . . . . . . . . . . . . . . . .14-17
imd2 . . . . . . . . . . . . . . . . . . . . . . . . .14-17
imm . . . . . . . . . . . . . . . . . . . . . . . . .14-17
imm2 . . . . . . . . . . . . . . . . . . . . . . . .14-17
imw. . . . . . . . . . . . . . . . . . . . . . . . . .14-18
inm . . . . . . . . . . . . . . . . . . . . . . . . . .14-18
iprobe . . . . . . . . . . . . . . . . . . . . . . . .14-18
iprobe2. . . . . . . . . . . . . . . . . . . . . . .14-18
switchsrom . . . . . . . . . . . . . . . . . . .14-18
IPMC Commands . . . . . . . . . . . . . . . . . 14-18
fru . . . . . . . . . . . . . . . . . . . . . . . . . . .14-18
fruinit . . . . . . . . . . . . . . . . . . . . . . . .14-19
fruled . . . . . . . . . . . . . . . . . . . . . . . .14-19
ipmcfw . . . . . . . . . . . . . . . . . . . . . . .14-19
sensor. . . . . . . . . . . . . . . . . . . . . . . .14-19
Environment Parameter Commands 14-20
printenv. . . . . . . . . . . . . . . . . . . . . . 14-21
saveenv . . . . . . . . . . . . . . . . . . . . . . 14-21
setenv . . . . . . . . . . . . . . . . . . . . . . . 14-21
Test Commands . . . . . . . . . . . . . . . . . . 14-21
diags. . . . . . . . . . . . . . . . . . . . . . . . . 14-21
mtest . . . . . . . . . . . . . . . . . . . . . . . . 14-21
um . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
Other Commands. . . . . . . . . . . . . . . . . 14-22
autoscr. . . . . . . . . . . . . . . . . . . . . . . 14-22
base . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
bdinfo . . . . . . . . . . . . . . . . . . . . . . . 14-22
coninfo . . . . . . . . . . . . . . . . . . . . . . 14-22
crc32 . . . . . . . . . . . . . . . . . . . . . . . . 14-22
date . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
echo . . . . . . . . . . . . . . . . . . . . . . . . . 14-23
enumpci . . . . . . . . . . . . . . . . . . . . . 14-23
go . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23
help . . . . . . . . . . . . . . . . . . . . . . . . . 14-23
iminfo . . . . . . . . . . . . . . . . . . . . . . . 14-23
isdram . . . . . . . . . . . . . . . . . . . . . . . 14-23
loop . . . . . . . . . . . . . . . . . . . . . . . . . 14-24
memmap . . . . . . . . . . . . . . . . . . . . 14-24
moninit . . . . . . . . . . . . . . . . . . . . . . 14-24
pci. . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24
phy . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
ping . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
reset . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
run . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
script . . . . . . . . . . . . . . . . . . . . . . . . 14-26
showmac. . . . . . . . . . . . . . . . . . . . . 14-26
showpci . . . . . . . . . . . . . . . . . . . . . . 14-26
sleep. . . . . . . . . . . . . . . . . . . . . . . . . 14-26
switch_reg . . . . . . . . . . . . . . . . . . . 14-27
version . . . . . . . . . . . . . . . . . . . . . . . 14-27
vlan. . . . . . . . . . . . . . . . . . . . . . . . . . 14-27
Environment Variables . . . . . . . . . . . . 14-28
Troubleshooting. . . . . . . . . . . . . . . . . . 14-31
Download Formats. . . . . . . . . . . . . . . . 14-32
Binary. . . . . . . . . . . . . . . . . . . . . . . . 14-32
Motorola S-Record . . . . . . . . . . . . 14-32
15 Acronym List
16 Appendix A
No-CPU KAT4000 . . . . . . . . . . . . . . . . . . . .A-1
Contents (continued)
10007175-02 KAT4000 User’s Manual vii
Ethernet Switch Configuration . . . . . . . A-2
Default Switch Configuration . . . . .A-2
Serial Command Line Interface (CLI). . . A-3
Log In/Log Out Procedures. . . . . . . .A-3
Help Utility. . . . . . . . . . . . . . . . . . . . . .A-3
Command Hierarchy . . . . . . . . . . . . .A-4
Command Usage Instructions . . . . . A-5
Commands . . . . . . . . . . . . . . . . . . . . . A-5
Command Overview . . . . . . . . .A-6
System Commands . . . . . . . . . . A-8
Console Commands . . . . . . . . . A-8
Port Commands . . . . . . . . . . . . .A-9
MAC Commands . . . . . . . . . . .A-10
VLAN Commands . . . . . . . . . . A-12
Aggregation/Trunking Commands
A-13
User Group Commands . . . . . A-14
QoS Commands. . . . . . . . . . . . A-14
Mirror Commands . . . . . . . . . . A-16
IP Commands . . . . . . . . . . . . . . A-16
Debug Commands . . . . . . . . . A-17
Web Interface . . . . . . . . . . . . . . . . . . . . . A-18
17 Appendix B
Sensor Data Records . . . . . . . . . . . . . . . . .B-1
KAT4000 User’s Manual 10007175-02
viii
(blank page)
10007175-02 KAT4000 User’s Manual ix
Figures
Figure 1-1: General System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Figure 1-2: KAT4000 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Figure 1-3: AMC Port Mapping Regions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Figure 2-1: Component Map, Top (Rev. 02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 2-2: Component Map, Bottom (Rev. 02). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Figure 2-3: KAT4000 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Figure 2-4: Jumper, Fuse and Switch Locations, Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Figure 2-5: Jumper, Fuse and Switch Locations, Bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Figure 2-6: JTAG Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Figure 2-7: LEDs, Top. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Figure 2-8: LEDs, Bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Figure 2-9: KAT4000 Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Figure 3-1: MPC8548 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Figure 3-2: Processor JTAG/COP Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Figure 3-3: Processor JTAG/COP Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Figure 4-1: Board Area Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Figure 4-2: VSC7376 GbE Switch Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Figure 4-3: PEX 8524 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Figure 4-4: PEX 8524 SPI EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Figure 5-1: AMC Port Map Fat Pipes Region–GbE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Figure 5-2: Signal Routing of the GbE Fat Pipe Switch Module on the KAT4000 . . . . . . . . . . . . . . 5-2
Figure 5-3: GbE Fat Pipe Switch Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Figure 5-4: GbE Fat Pipe Switch Module Component Map, Top (Rev. 00). . . . . . . . . . . . . . . . . . . . 5-4
Figure 5-5: GbE Fat Pipe Switch Module Component Map, Bottom (Rev. 00) . . . . . . . . . . . . . . . . 5-4
Figure 5-6: GbE Fat Pipe Switch JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Figure 5-7: GbE Fat Pipe Switch Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Figure 5-8: AMC Port Map Fat Pipes Region–10 GbE-1 GbE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Figure 5-9: Signal Routing of the 10 GbE-1 GbE Fat Pipe Switch Module on the KAT4000 . . . . 5-11
Figure 5-10: 10 GbE-1 GbE Fat Pipe Switch Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Figure 5-11: 10 GbE-1 GbE Fat Pipe Switch Module Component Map, Top (Rev. 01) . . . . . . . . . . 5-13
Figure 5-12: 10 GbE-1 GbE Fat Pipe Switch Module Component Map, Bottom (Rev. 01) . . . . . . 5-13
Figure 5-13: 10 GbE-1 GbE Fat Pipe Switch JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Figure 5-14: 10 GbE-1 GbE Fat Pipe Switch Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Figure 5-15: AMC Port Map Fat Pipes Region–10 GbE-10 GbE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
Figure 5-16: Signal Routing of the 10 GbE-10 GbE Fat Pipe Switch Module on the KAT4000 . . . 5-21
Figure 5-17: AMC Port Map Fat Pipes Region–sRIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
Figure 5-18: Signal Routing of the sRIO Fat Pipe Switch Module on the KAT4000. . . . . . . . . . . . . 5-22
Figure 7-1: Boot Device Redirection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Figure 7-2: PLD JTAG Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
Figure 8-1: AMC B+ Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Figures (continued)
KAT4000 User’s Manual 10007175-02
x
Figure 8-2: Diagram of SATA line connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Figure 9-1: IPMC Connections Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Figure 9-2: Extension Command Request Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Figure 9-3: Extension Command Response Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Figure 9-4: IPMB Entity Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40
Figure 10-1: Synchronization Clock Circuit Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Figure 11-1: M41T00 Real-Time Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Figure 12-1: Zone 1 Connector, P10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Figure 12-2: Zone 2 Connectors, J20 and J23, and Zone 3 Connectors, J30-J32. . . . . . . . . . . . . . . 12-3
Figure 12-3: Zone 3 Connector, J33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
Figure 13-1: RTM General System Block Diagram with Face Plate . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Figure 13-2: RTM Component Map, Top (Rev. 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Figure 13-3: Micro-D Console Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
Figure 13-4: Standard Console Cable Wiring, #10007665-xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Figure 13-5: Installing a KAT-Z3DB RTM on the KAT4000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Figure 14-1: Example Monitor Start-up Display for KAT4000 with GbE Fat Pipe Switch Module 14-2
Figure 14-2: Example Monitor Start-up Display for KAT4000 with 10 GbE-1 GbE Fat Pipe Switch Mod-
ule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
Figure 14-3: Power-up/Reset Sequence Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
Figure A-1: No-CPU KAT4000 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Figure A-2: Web Interface for the Ethernet Core Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
10007175-02 KAT4000 User’s Manual xi
Tables
Table 1-1: KAT4000 Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Table 1-2: Regulatory Agency Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Table 1-3: Technical References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Table 2-1: Circuit Board Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Table 2-2: JP4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Table 2-3: Jumpers–JP2 and JP7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Table 2-4: J35 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Table 2-5: Typical Power Requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Table 2-6: Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Table 2-7: Air Flow Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Table 3-1: MPC8548 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Table 3-2: PCI Device and Vendor ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Table 3-3: MPC8548 Peripheral Request Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Table 3-4: MPC8548 Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Table 3-5: MPC8548 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Table 3-6: Processor JTAG/COP Pin Assignments (P1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Table 4-1: KAT4000 PHYs and Address Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Table 4-2: Ethernet Core Switch Off-Board Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Table 4-3: GbE Fat Pipe Module Ethernet Switch Off-Board Ports. . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Table 4-4: Ethernet Port Address Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Table 4-5: PEX 8524 JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Table 5-1: GbE Fat Pipe PLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Table 5-2: BCM56580 Switch Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Table 5-3: 10 GbE-1 GbE Fat Pipe PLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Table 6-1: Memory Configuration Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Table 6-2: NVRAM Memory Map, User EEPROM 1 (write protected)1. . . . . . . . . . . . . . . . . . . . . . 6-3
Table 6-3: NVRAM Memory Map, User EEPROM 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Table 7-1: PLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Table 7-2: JP3 PLD JTAG Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
Table 7-3: JP1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
Table 8-1: B1-B4 AMC Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Table 9-1: Network Function Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Table 9-2: Completion Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Table 9-3: Format for IPMI Request Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Table 9-4: Format for IPMI Response Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Table 9-5: IPMC IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
Table 9-6: Vendor Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
Table 9-7: Get Status Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
Table 9-8: Get Serial Interface Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
Table 9-9: Set Serial Interface Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
Tables (continued)
KAT4000 User’s Manual 10007175-02
xii
Table 9-10: Get Debug Level Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
Table 9-11: Set Debug Level Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
Table 9-12: Get Hardware Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
Table 9-13: Set Hardware Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
Table 9-14: Get Handle Switch Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
Table 9-15: Set Handle Switch Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
Table 9-16: Get Payload Communication Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
Table 9-17: Set Payload Communication Time-Out Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
Table 9-18: Disable Payload Control Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
Table 9-19: Reset IPMC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
Table 9-20: Hang IPMC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
Table 9-21: Bused Resource Control Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22
Table 9-22: Bused Resource Status Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
Table 9-23: Graceful Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
Table 9-24: Diagnostic Interrupt Results Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
Table 9-25: Get Payload Shutdown Time-Out Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
Table 9-26: Set Payload Shutdown Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
Table 9-27: Get Module State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
Table 9-28: Enable AMC Site Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
Table 9-29: Disable AMC Site Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
Table 9-30: IPMC Watchdog Timer Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
Table 9-31: Reset Watchdog Timer Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
Table 9-32: Set Watchdog Timer Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
Table 9-33: Get Watchdog Timer Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
Table 9-34: FRU LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33
Table 9-35: Get FRU LED Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34
Table 9-36: Get LED Color Capabilities Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34
Table 9-37: Set FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36
Table 9-38: Get FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-38
Table 9-39: IPMI Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40
Table 9-40: Event Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43
Table 9-41: FRU Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-44
Table 9-42: Link Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-45
Table 9-43: Firmware Upgrade Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-47
Table 9-44: Firmware Upgrade Status Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-47
Table 9-45: Firmware Upgrade Start Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-48
Table 9-46: Firmware Upgrade Prepare Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-49
Table 9-47: Firmware Upgrade Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-50
Table 9-48: Firmware Upgrade Complete Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-50
Table 9-49: Firmware Upgrade Restore Backup Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-51
Table 9-50: Firmware Upgrade Backup Revision Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-51
Tables (continued)
10007175-02 KAT4000 User’s Manual xiii
Table 11-1: RTC Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Table 12-1: Zone 1 Connector, P10 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Table 12-2: Zone 2 Connector, J20 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
Table 12-3: Zone 2 Connector, J23 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Table 12-4: Zone 3 Connector, J30 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
Table 12-5: Zone 3 Connector, J31 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
Table 12-6: Zone 3 Connector, J32 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
Table 12-7: Zone 3 Connector, J33 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
Table 13-1: RTM Circuit Board Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Table 13-2: Console Serial Port Pin Assignments, P1, P2 and P4-P7 . . . . . . . . . . . . . . . . . . . . . . . . 13-5
Table 13-3: Ethernet Port Pin Assignments, P3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Table 14-1: Debug LED Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Table 14-2: POST Diagnostic Results–Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Table 14-3: Monitor Address per Flash Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
Table 14-4: Static IP Ethernet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Table 14-5: DHCP Ethernet Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
Table 14-6: Standard Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28
Table 14-7: Optional Environment Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30
Table A-1: General Command Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
Table B-1: IPMI Sensor Data Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Table B-2: KAT4000 IPMC SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
Table B-3: Hot Swap SDR Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
Table B-4: IPMB Physical SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
Table B-5: BMC Watchdog SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
Table B-6: +3.3 Volt SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
Table B-7: +2.5 Volt SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9
Table B-8: +1.8 Volt SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11
Table B-9: +1.2 Volt SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13
Table B-10: +1.0 Volt SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15
Table B-11: CPU Volt SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17
Table B-12: Inflow Temp SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-19
Table B-13: Outflow Temp SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-21
Table B-14: Version Change SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-24
Table B-15: B1 Hot Swap SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-25
Table B-16: B2 Hot Swap SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-27
Table B-17: B3 Hot Swap SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-28
Table B-18: B4 Hot Swap SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-30
Table B-19: B1 +12V Current SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-31
Table B-20: B1 +12V Volt SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-33
Table B-21: B2 +12V Current SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-35
Table B-22: B2 +12V Volt SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-36
Tables (continued)
KAT4000 User’s Manual 10007175-02
xiv
Table B-23: B3 +12V Current SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
Table B-24: B3 +12V Volt SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-40
Table B-25: B4 +12V Current SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-41
Table B-26: B4 +12V Volt SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-43
Table B-27: -48V Volt SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-45
Table B-28: -48V Current SDR Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-47
Table B-29: -48V Source A Volt SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-48
Table B-30: -48V Source B Volt SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-50
Table B-31: +3.3V Management SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-52
Table B-32: +12V Volt SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-54
Table B-33: -12V Current SDR Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-56
Table B-34: F/W (Firmware) Progress SDR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-58
10007175-02 KAT4000 User’s Manual i
Registers
Register 3-1: L2 Control Register (L2CR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Register 3-2: MPC8548 Hardware Implementation Dependent Register 0 (HID0) . . . . . . . . . . . . . 3-6
Register 3-3: MPC8548 Hardware Implementation Dependent Register 1 (HID1) . . . . . . . . . . . . . 3-8
Register 3-4: CPU Machine State Register (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Register 5-1: Product ID/Version Register (PIDV) at 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Register 5-2: Scratch Register (SCR) at 0x01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Register 5-3: I2C Register (I2C) at 0x02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Register 5-4: Signal Detect Register (SDET) at 0x03. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Register 5-5: Switch Reset Register (SRST) at 0x04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Register 5-6: Module Status Register (STAT) at 0x05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Register 5-7: Switch GPIO Register (GPIO) at 0x06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Register 5-8: GPIN/LED Register (GPLED) at 0x07 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Register 5-9: Product ID/Version Register (PIDV) at 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Register 5-10: Scratch Register (SCR) at 0x01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Register 5-11: I2C Register (I2C) at 0x02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Register 5-12: Reserved Register 1 at 0x03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
Register 5-13: Switch Reset Register (SRST) at 0x04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
Register 5-14: Module Status Register (STAT) at 0x05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Register 5-15: Switch GPIO Register (GPIO) at 0x06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Register 5-16: GPIN/LED Register (GPLED) at 0x07 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
Register 7-1: Product ID Register (PIDR) at 0xfc40,0000. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Register 7-2: Hardware Version Register (HVR) at 0xfc40,0004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Register 7-3: PLD Version Register (PVR) at 0xfc40,0008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Register 7-4: Hardware Configuration Register 0 (HCR0) at 0xfc40,0010 . . . . . . . . . . . . . . . . . . . . . 7-4
Register 7-5: PLL Configuration Register (PLLC) at 0xfc40,000c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Register 7-6: LED Control Register (LEDR) at 0xfc40,001c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Register 7-7: Jumper Settings Register (JSR) at 0xfc40,0018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Register 7-8: RTM GPIO State Register (RGSR) at 0xfc40,0038 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Register 7-9: RTM GPIO Control Register (RGCR) at 0xfc40,003c . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Register 7-10: MISC Control Register (MISC) at 0xfc40,0034 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Register 7-11: Scratch Register 1 (SCR1) at 0xfc40,002c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Register 7-12: Reset Event Register (RER) at 0xfc40,0020. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Register 7-13: Reset Command Register 1 (RCR1) at 0xfc40,0024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Register 7-14: Reset Command Register 2 (RCR2) at 0xfc40,0028 . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Register 7-15: Boot Device Redirection Register (BDRR) at 0xfc40,0030 . . . . . . . . . . . . . . . . . . . . . . 7-12
Register 7-16: Clock Synchronizer Control Registers 1-3 (CSC1-CSC3) at 0xfc40,0040, 0xfc40,0044,
0xfc40,0048, respectively . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
Register 7-17: Clock Synchronizer Primary Source Registers 1-3 (CPS1-CPS3) at 0xfc40,0050,
0xfc40,0054, 0xfc40,0058, respectively . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
Register 7-18: Clock Synchronizer Secondary Source Registers 1-3 (CSS1-CSS3) at 0xfc40,0060,
0xfc40,0064, 0xfc40,0068, respectively . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
Registers (continued)
KAT4000 User’s Manual 10007175-02
ii
Register 7-19: Clock Control Registers 1-14 (CCR1-CCR14) at 0xfc40,0070, 0xfc40,0074,
0xfc40,0078, 0xfc40,007c, 0xfc40,0080, 0xfc40,0084, 0xfc40,0088, 0xfc40,008c, 0xfc40,0090,
0xfc40,0094, 0xfc40,0098, 0xfc40,009c, 0xfc40,00a0, 0xfc40,00a4, respectively . . . . . . . . . . . . . . 7-17
Register 7-20: Clock Synchronizer Interrupt Registers 1-3 (CSI1-CSI3) at 0xfc40,00a8, 0xfc40,00ac,
0xfc40,00b0, respectively . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
Register 9-1: Enable Payload Control Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
10007175-02 KAT4000 User’s Manual 1-1
Section 1
Overview
The KAT4000 is a single-slot Advanced Telecom Computing Architecture (AdvancedTCA®,
ATCA™) carrier with up to four Advanced Mezzanine Cards (AMC) expansion modules. This
expansion capability enables a wide variety of control and packet processing applications
such as WAN access, traffic processing, signaling gateways, media gateways, and many
others. ATCA is an open architecture telecom platform as defined by the PICMG® 3.0 Revi-
sion 2.0 AdvancedTCA™ Base Specification.
The KAT4000 features on-board Ethernet and PCI Express switches for the AdvancedMC
Common Options Region, where the majority of control plane data flows, and a flexible
modular Fat Pipe Switch (FPS) to address data plane traffic in the AdvancedMC Fat Pipes
Region. The FPS is implemented using a plug-over module, enabling simple maintenance
and a rapid upgrade path when a newer switch fabric is required. An optional on-board pro-
cessor gives users additional processing power and can be used to off-load system manage-
ment or OA&M functionality.
The KAT4000 is an intelligent Field Replaceable Unit (FRU) and implements a redundant
System Management Bus (SMB). It also fully supports the Intelligent Platform Management
Interface (IPMI) with AdvancedTCA extensions to support standards-based shelf manage-
ment, allowing it to be monitored by a local shelf management controller or by a remote
OA&M system over Ethernet.
COMPONENTS AND FEATURES
The following is a brief summary of the KAT4000 hardware components and features:
Processor: The Central Processing Unit (CPU) is a Freescale® Semiconductor MPC8548 PowerQUICC
III™ processor, operating at a rate of up to 1.3 GHz with a 533 MHz DDR2 bus. The
MPC8548 contains 32-kB separate level-one (L1) data and instruction caches, and 512-kB
L2 cache. The processor has a local bus that connects to the socketed, NOR, and NAND
flash; Ethernet core switch; fat pipe switch module; and PLD. The processor also has a
COP/JTAG for debugging purposes. Chapter 3 provides more information.
SDRAM: The KAT4000 includes a 64M x 72-bit Double Data Rate Two (DDR2) Synchronous Dynamic
Random Access Memory (SDRAM) Small-Outline Dual In-line Memory Module (SO-DIMM).
Options include 512 megabytes and 1 gigabyte. The interface implements eight additional
bits to permit the use of Error-Correcting Code (ECC). SDRAM is only implemented on the
processor KAT4000 board configuration. “On-Card SDRAM” on page 6-2 provides more
information.
Flash: The KAT4000 includes three independent Flash regions—socketed, NOR, and NAND. The
blade is capable of booting from either an 8-bit, 32-pin PLCC ROM socket up to 512 kilo-
bytes in size, or from a 16-bit NOR Flash region that consists of one or two Flash devices.
Overview: Components and Features
KAT4000 User’s Manual 10007175-02
1-2
The NOR Flash consists of two 16 megabyte banks. The supported NAND flash is 512 mega-
bytes or 1 gigabyte. Flash is only implemented on the processor KAT4000 board configura-
tion. Chapter 6 provides more information.
CPLD: The KAT4000 uses a Complex Programmable Logic Device (CPLD) to control board reset
logic, the Board Configuration, Board Revision and User LED registers, and miscellaneous
board logic. Register access to the PLD is only available on the processor KAT4000 board
configuration. Chapter 7 provides more information.
Ethernet: Depending on the configuration, the KAT4000 Ethernet interface consists of: Reduced
Gigabit (RGMII)/Serial Gigabit (SGMII)/1000Base-BX Serializer-Deserializer (SerDes) Ether-
net core or fat pipe switch module (Vitesse VSC7376), and 1000Base-BX (SerDes) devices
to the AMC sites.
One 10/100 eTSEC port from the MPC8548 is available through Zone 3 for Rear Transition
Module (RTM) access. This port is for development purposes only.
Serial I/O: An EIA-232 console serial port from the MPC8548 (serial 1) is available through an on-board
header and is optionally routable to Zone 3 for Rear Transition Module (RTM) access. The
default serial port settings are: 9,600 baud, 8 data, no parity, and 1 stop bit. This port is for
development purposes only.
A second serial port (serial 2) allows the MPC8548 to communicate with the Intelligent Plat-
form Management Controller (IPMC). The default serial port settings are: 115,200 baud, 8
data, no parity, and 1 stop bit.
I2C Bus: The private IPMC I2C bus consists of the following devices: temp sensors, the -48V con-
verter, AMC A-to-D converters, and an optional connection to Zone 3 for Rear Transition
Module (RTM) access.
One processor I2C bus links to the following: two user SEEPROMs, the CPU init SEEPROM,
the Real-Time Clock (RTC), the SO-DIMM, and the fat pipe switch module, if used. Another
processor I2C bus provides an optional connection to Zone 3 for Rear Transition Module
(RTM) access.
JTAG Hubs: The IPMC controls the two Joint Test Action Group (JTAG) interfaces (hubs). One JTAG hub
is connected to seven ports: the KSL PLD, the IPMC PLD, the fat pipe switch module, and the
four AMC sites. The other hub is connected to five ports: the VSC7376 switch, the PEX8524
switch, the clock synchronizers, the IPMC GPIO, and GbE PHYs. See “JTAG Interfaces” on
page 2-9 for more information.
AMC Sites: The KAT4000 has four single-width, mid-size Advanced Mezzanine Card (AMC) sites which
allow for use of up to four compatible AMC modules. Double-width and compact modules
can also be accommodated. B+ style AMC connectors are used. The KAT4000 complies
Overview: Components and Features
10007175-02 KAT4000 User’s Manual 1-3
with the PICMG® AMC.0 Revision 2.0 Advanced Mezzanine Card Base Specification with the
exception of a couple non-conformances. See the KAT4000 Errata for details. Each AMC site
is individually configurable. Chapter 8 provides more information.
System Management: The KAT4000 supports an Intelligent Platform Management Interface (IPMI) based on a
Renesas microcontroller with a UART interface for processor to IPMC communication (fixed
rate at 115,200 baud) and dual redundant IPMB-A/B interfaces. The IPMC allows for fea-
tures such as remote shutdown, remote reset, payload voltage monitoring, temperature
monitoring, and access to Field Replaceable Unit (FRU) data. Chapter 9 provides more
information.
Synchronization Clock: The synchronization clock interface consists of MT9045 or MT9046 T1/E1 system synchro-
nizers. Chapter 10 provides more information.
RTC: The Real-Time Clock (RTC) is an ST®Microelectronics M41T00 Serial Access Timekeeper®.
Chapter 11 provides more information.
Caution: There are no serviceable parts in this product. Return all damaged boards to Emerson for
repair (see page 2-18).
KAT4000 Options
No-CPU Configuration: A no-CPU KAT4000 board configuration is available. This configuration includes 256 Kb of
SRAM memory used by the internal 8051 microcontroller on the VSC7376 Ethernet core
switch for run time code storage. This configuration omits SDRAM and NOR and NAND
flash. Appendix A provides more information.
Ethernet Core Switch: The Ethernet core switch provides the interconnect between the fat pipe switch module,
the Ethernet ports on the AMC sites, two channels on the ATCA backplane Base fabric, the
processor, and the Update Channel (optional). A Vitesse VSC7376 GbE switch implements
this function. “Ethernet Core Switch (optional)” on page 4-2 provides more information.
PCI Express Switch: The PCIe switch provides the interconnect between the AMC sites, the processor, and the
fat pipe switch module. A PLX Technology PEX 8524 PCIe switch implements this function.
“PCI Express Switch (optional)” on page 4-7 provides more information.
Note: Of the Ethernet core switch and the PCI Express switch, at least one of the two switches must be used on the
board. The board can also use both switches.
!
Overview: Components and Features
KAT4000 User’s Manual 10007175-02
1-4
Fat Pipe Switch Module:
A high-speed fat pipe switch is provided as a plug-over module. It supports GbE, Serial
Rapid IO (sRIO), PCI Express (PCIe) or 10 Gigabit Ethernet (10 GbE). This switch provides an
interconnect between the AMC sites, the ATCA high-speed fabric ports, the processor, the
PCIe switch and the Ethernet core switch. See “Fat Pipe Switch Module”, Chapter 5, for
information on your module’s configuration.
Rear Transition Module (RTM):
The optional transition modules provide access to 16 or 32 ports when AMCs are installed
on the KAT4000. AMC site ports 12-20 are routed to Zone 3 for Rear Transition Module
(RTM) I/O. 64 AMC signals route to 264 pins in Zone 3 (see “Zone 3” on page 12-4). There
are nine T1/E1 ports per AMC site routed as differential pairs (64 signals). There are sepa-
rate I2C connections to the IPMC and the processor, and two ports each from the fat pipe
switch module and the Ethernet Core switch. A serial port and GbE port are provided for
development purposes only.
Overview: Functional Overview
10007175-02 KAT4000 User’s Manual 1-5
FUNCTIONAL OVERVIEW
The following block diagram provides a functional overview for the KAT4000:
Figure 1-1: General System Block Diagram
MPC8548
Processor
IPMB Base High Speed
Fabric A
Clock RTM I/O
(Optional)
High Speed
Fabric B
Clock
sRIO (x4)
IPMC
To Zone 3
(Optional)
Zone 3
Connections
(Opt.)
To Eth
Core
Switch
(Opt.)
GbE
RGMII
PLD
NOR
Flash
Socketed
Flash
To Update Channel
on J20 (Optional)
Xfmr
Xfmr (2)
GbE
PHYs (2)
Local bus
10/100
PHY Xfmr
DDR2-667
2GB
SROM
Fat Pipe Switch Module
Fabric Options:
GbE, sRIO,
10-1 GbE or 10-10 GbE
GbE
PHY
EIA-232
Transceiver
Sensors
-48V
Cnvrtr
AMC
A-to-D
EIA-232
Xcvr
Serial
Header
GbE
PHYs (2)

 
AMC (x4) Single-Width,
Half-/Full-/Extended-Height
Serial
Header
NAND
Flash
To Zone 3
PCIe or GbE
on port 1
I
2
C
RTC
Fat Pipe
SO-DIMM
User 1
SEEPROM
CPU Init
SEEPROM User 2
SEEPROM
PCIe
(x1 or x4)
To Eth
Core
Switch
PEX8524
PCI Express Switch
(Optional)
VSC7376
Ethernet Core Switch
Layer 2 (Optional)
SERDES
SERDES
4 SERDES
2 SGMII
SERDES
Private I
2
C
GbESERDES
Main PLD
I
2
C
To Zone 3
To Zone 3
2 SERDES
To local bus
2 SERDES
To processor
Optional
Serial 1
10/100 Debug Eth (MII)
PCIe
GMII/RGMII
4 SERDES
Serial 2
242
4 SERDES
4 SERDES
2 9
To
local
bus
4 SERDES
(no conn.
for
GbE)
3
IPMB-L I
2
C
P10 J20 Zone 3J23
Overview: Physical Memory Map
KAT4000 User’s Manual 10007175-02
1-6
PHYSICAL MEMORY MAP
Fig. 1-2 illustrates the KAT4000 memory map:
Figure 1-2: KAT4000 Memory Map
8000,0000
FC12,0000
FC00,0000
FC80,0000
FC88,0000
FFFF,FFFF
Hex Address
0000,0000
CPLD Registers (512 KB)
NAND Flash (32 KB)
FFF0,0000
Socketed Flash (if installed) (512 KB)
Boot Area (1 MB)
Reserved
Reserved
CCSRBAR (MPC8548 Registers, 1 MB)
FF70,0000
FF80,0000
A000,0000 PCI Express Switch
(if installed) (512 MB)
NOR Flash (32 MB)
E000,0000
Reserved
FC48,0000
Reserved
E200,0000
Reserved
Hex Address
FC40,0028
Scratch Register 1
Boot Device Redirection Register
Clock Sync. Control Register 2
Clock Control, AMC4 CLK1 Register
Clock Control, AMC4 CLK2 Register
Clock Control, AMC1 CLK1 Register
Clock Sync. Primary Source 1
Clock Sync. Primary Source 2
Clock Control, AMC3 CLK3 Register
Clock Control, AMC3 CLK2 Register
FC40,0040
FC40,0044
FC40,004C
FC40,0050
FC40,0054
FC40,0058
FC40,005C
FC40,0060
FC40,0064
FC40,0068
FC40,006C
FC40,0070
FC40,0074
FC40,0048
MISC Control Register
Clock Sync. Control Register 1
Clock Sync. Control Register 3
Clock Control, AMC1 CLK2 Register
Clock Control, AMC1 CLK3 Register
Clock Control, AMC2 CLK1 Register
Clock Control, AMC2 CLK2 Register
Clock Control, AMC2 CLK3 Register
Clock Control, AMC4 CLK3 Register
FC40,002C
FC40,0030
FC40,0034
FC40,0038
FC40,003C
FC40,0078
FC40,007C
FC40,0080
FC40,0084
FC40,0088
Clock Control, aTCA CLK3 A Register
FC40,008C
FC40,0000
FC40,0004
FC40,0024
FC40,0020
FC40,001C
FC40,0018
FC40,0014
FC40,0010
FC40,000C
FC40,0008
FC40,0090
Product ID Register
Hardware Version Register
PLD Version Register
PLL Configuration Register
Hardware Config. Register 0
Jumper Settings Register
LED Control Register
Reset Event Register
Reset Command Register 1
Reset Command Register 2
Reserved
Clock Sync. Primary Source 3
Reserved
Clock Control, AMC3 CLK1 Register
Reserved
RTM GPIO State Register
RTM GPIO Control Register
Clock Sync. Secondary Source 1
Clock Sync. Secondary Source 2
Clock Sync. Secondary Source 3
Reserved
Clock Control, aTCA CLK3 B Register
Clock Sync. Interrupt Register 1
Clock Sync. Interrupt Register 2
Clock Sync. Interrupt Register 3
FC40,0094
FC40,0098
FC40,009C
FC40,00A0
FC40,00A4
FC40,00A8
FC40,00AC
FC40,00B0
1FFF,FFFF
3FFF,FFFF
Reserved
SDRAM
DDR2
(512 MB)
SDRAM
DDR2
(1 GB)
PCIe Switch or sRIO Fat Pipe Module
(if installed) (1 GB)
FC14,0000
FC18,0000
FC40,0000 Reserved
Ethernet Core Switch Registers (128 KB)
FC10,0000 Reserved
FC00,8000
Reserved
Fat Pipe Switch Registers
(if installed) (256 KB)
Overview: Physical Memory Map
10007175-02 KAT4000 User’s Manual 1-7
Table 1-1 summarizes the physical addresses for the KAT4000 and provides references to
more detailed information:
Table 1-1: KAT4000 Address Summary
Physical
Address (hex):
Access
Mode: Description: See Page:
FFF0,0000 R/W Boot Area (1 MB)
FF80,0000 Reserved
FF70,0000 W CCSRBAR (MPC8548 Registers, 1 MB)
FC88,0000 Reserved1
FC80,0000 R/W Socketed Flash (if installed) (512 KB) 6-1
FC48,0000 Reserved
FC40,00B0 R/W Clock Synchronizer Interrupt Register 3 (CSI3) 7-18
FC40,00AC R/W Clock Synchronizer Interrupt Register 2 (CSI2) 7-18
FC40,00A8 R/W Clock Synchronizer Interrupt Register 1 (CSI1) 7-18
FC40,00A4 R/W Clock Control, aTCA CLK3 B Register (CCR14) 7-17
FC40,00A0 R/W Clock Control, aTCA CLK3 A Register (CCR13) 7-17
FC40,009C R/W Clock Control, AMC4 CLK3 Register (CCR12) 7-17
FC40,0098 R/W Clock Control, AMC4 CLK2 Register (CCR11) 7-17
FC40,0094 R/W Clock Control, AMC4 CLK1 Register (CCR10) 7-17
FC40,0090 R/W Clock Control, AMC3 CLK3 Register (CCR9) 7-17
FC40,008C R/W Clock Control, AMC3 CLK2 Register (CCR8) 7-17
FC40,0088 R/W Clock Control, AMC3 CLK1 Register (CCR7) 7-17
FC40,0084 R/W Clock Control, AMC2 CLK3 Register (CCR6) 7-17
FC40,0080 R/W Clock Control, AMC2 CLK2 Register (CCR5) 7-17
FC40,007C R/W Clock Control, AMC2 CLK1 Register (CCR4) 7-17
FC40,0078 R/W Clock Control, AMC1 CLK3 Register (CCR3) 7-17
FC40,0074 R/W Clock Control, AMC1 CLK2 Register (CCR2) 7-17
FC40,0070 R/W Clock Control, AMC1 CLK1 Register (CCR1) 7-17
FC40,006C Reserved
FC40,0068 R/W Clock Synchronizer Secondary Source Register 3 (CSS3) 7-15
FC40,0064 R/W Clock Synchronizer Secondary Source Register 2 (CSS2) 7-15
FC40,0060 R/W Clock Synchronizer Secondary Source Register 1 (CSS1) 7-15
FC40,005C Reserved
FC40,0058 R/W Clock Synchronizer Primary Source Register 3 (CPS3) 7-14
FC40,0054 R/W Clock Synchronizer Primary Source Register 2 (CPS2) 7-14
FC40,0050 R/W Clock Synchronizer Primary Source Register 1 (CPS1) 7-14
FC40,004C Reserved
FC40,0048 R/W Clock Synchronizer Control Register 3 (CSC3) 7-13
FC40,0044 R/W Clock Synchronizer Control Register 2 (CSC2) 7-13
FC40,0040 R/W Clock Synchronizer Control Register 1 (CSC1) 7-13
Overview: Physical Memory Map
KAT4000 User’s Manual 10007175-02
1-8
1. Depends on Flash/memory size.
2. Both the PCI Express Switch and sRIO Fat Pipe Switch Module are optional. If both devices are discovered onboard, then the PCIe
switch will be allocated 512 MB and the sRIO fat pipe switch module will be allocated 1 GB of addressable space. If neither device
is found onboard, the entire 1.5 GB area is reserved.
FC40,003C R/W RTM GPIO Control Register (RGCR) 7-7
FC40,0038 R RTM GPIO State Register (RGSR) 7-6
FC40,0034 R/W MISC Control (PCIe, SIO, I2C, Test Clock) Register (MISC) 7-7
FC40,0030 R Boot Device Redirection Register (BDRR) 7-12
FC40,002C R/W Scratch Register 1 (SCR1) 7-8
FC40,0028 W Reset Command Register 2 (RCR2) 7-10
FC40,0024 W Reset Command Register 1 (RCR1) 7-9
FC40,0020 R Reset Event Register (RER) 7-9
FC40,001C R/W LED Control Register (LEDR) 7-5
FC40,0018 R Jumper Settings Register (JSR) 7-6
FC00,0014 Reserved
FC40,0010 R Hardware Configuration Register 0 (HCR0) 7-4
FC40,000C R/W PLL Configuration Register (PLLC) 7-4
FC40,0008 R PLD Version Register (PVR) 7-3
FC40,0004 R Hardware Version Register (HVR) 7-3
FC40,0000 R Product ID Register (PIDR) 7-2
FC18,0000 Reserved
FC14,0000 R/W Fat Pipe Ethernet Switch Registers (if installed) (256 KB) 5-2
FC12,0000 Reserved
FC10,0000 R/W Ethernet Core Switch Registers (128 KB) 4-2
FC00,8000 Reserved
FC00,0000 R/W NAND Flash (32 KB) 6-2
E200,0000 Reserved1
E000,0000 R/W NOR Flash (32 MB) 6-1
A000,0000 R/W PCI Express Switch or sRIO Fat Pipe Switch Module (if installed)
(1 GB)24-7 or 5-22
8000,0000 R/W PCI Express Switch (if installed) (512 MB)24-7
4000,0000 Reserved1
0000,0000 R/W SDRAM DDR2 (512 MB/1 GB) 6-2
Physical
Address (hex):
Access
Mode: Description:
See Page:
(continued)
Overview: AMC Mapping
10007175-02 KAT4000 User’s Manual 1-9
AMC MAPPING
The figure below shows how the KAT4000 maps to the ports defined by the AMC.0 specifi-
cation:
Figure 1-3: AMC Port Mapping Regions
Port MappingPort #
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&'
Basic Connector Extended Connector
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+,
&-()*
./+,
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."
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&' 3
Port #
+,
+,
+,
+,
+,
(4#56"
."
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
&.%
Port #
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(4#56"
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+,

Port #
7+,
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(4#56"
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B4

B3

B2

B1
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B4
! 
B2
! 
B3
! 
B1
! 
(,"41/
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(
,"41/
#1'6/
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(,"4
1//
/6'
&'
Port #
+,
+,
+,
+,
7+,
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(4#56"
."
Overview: Additional Information
KAT4000 User’s Manual 10007175-02
1-10
Clocks: This region supports a subset of the clock architecture, as defined in the AMC.0 specifica-
tion.
Common Options: This region supports essential interfaces that are common across multiple Fat Pipe imple-
mentations.
Fat Pipes: This region supports data path connections including GbE, sRIO, PCIe, and 10 GbE. It can
carry large amounts of data without significantly degrading the speed of transmission.
Extended Options: This region supports Rear Transition Modules. Also, it may be used to extend the Common
Options and Fat Pipes Regions, when required.
x1, x2, x4: This refers to the link width of the port (the number of lanes that can be used to intercon-
nect between two link partners).
ADDITIONAL INFORMATION
This section lists the KAT4000 hardware regulatory certifications and briefly discusses the
terminology and notation conventions used in this manual. It also lists general technical
references.
Mean time between failures (MTBF) has been calculated at greater than 315,816 hours for
the KAT4000 and greater than 264,795 hours for the KAT4000 with a GbE fat pipe switch
module. MTBFs were calculated using Method I Case 3, Telcordia Issue 1 model at 30° C.
Product Certification
The KAT4000 hardware has been tested to comply with various safety, immunity, and
emissions requirements as specified by the Federal Communications Commission (FCC),
Industry Canada (IC), Underwriters Laboratories Inc.® (UL), and the European Union Direc-
tives (CE mark). The following table summarizes this compliance:
Table 1-2: Regulatory Agency Compliance
Type: Specification:
Safety IEC60950/EN60950 – Safety of Information Technology Equipment
(Western Europe)
UL60950, CSA C22.2 No. 60950, Third Edition – Safety of Information
Technology Equipment, including Electrical Business Equipment (BI-
National)
AS/NZS 60950:2000 – Safety Standard for Australia and New Zealand
Global IEC – CB Scheme Report IEC 60950, all country deviations
Overview: Additional Information
10007175-02 KAT4000 User’s Manual 1-11
Emerson maintains test reports that provide specific information regarding the methods
and equipment used in compliance testing. Unshielded external I/O cables, loose screws, or
a poorly grounded chassis may adversely affect the KAT4000’s ability to comply with any of
the stated specifications.
UL Certification
The UL web site at ul.com has a list of Emerson’s UL certifications.
1To find the list, go to the web site and search in the online certifications directory using
Emerson’s UL file number, E190079. There is a list for products distributed in the United
States, as well as a list for products shipped to Canada.
2Products are listed by board type followed by the model name and/or number. The
KAT4000 is an AdvancedTCA (ATCA) blade. The model number is KAT4000’s Printed Circuit
Board (PCB) artwork number, which is 10007505-xx.
RoHS Compliance
The KAT4000, all fat pipe modules listed in Chapter 5, and the RTM described in Chapter 13
are compliant with the European Union’s RoHS (Restriction of Use of Hazardous Sub-
stances) directive created to limit harm to the environment and human health by restrict-
ing the use of harmful substances in electrical and electronic equipment. Effective July 1,
2006, RoHS restricts the use of six substances: cadmium (Cd), mercury (Hg), hexavalent
chromium (Cr (VI)), polybrominated biphenyls (PBBs), polybrominated diphenyl ethers
Environmental NEBS™: Telcordia™ GR-63 (applies to an entire system) –
Section 4.3 Equipment Handling Criteria;
Section 4.4.1 Earthquake Environment and Criteria (Zone 4);
Section 4.4.3 Office Vibration Environment and Criteria;
Section 4.4.4 Transportation Vibration Criteria
EMC FCC Part 15, Class B – Title 47, Code of Federal Regulations, Radio
Frequency Devices
ICES 003, Class A – Industry Canada Interference-causing Equipment
Standard for Digital Apparatus
NEBS: Telcordia GR-1089 level 3 – Emissions and Immunity (circuit pack
level testing only)
EN300386 – Electromagnetic Compatibility and Radio Spectrum Matters
(ERM), Telecommunication Network Equipment, Electromagnetic
Compatibility (EMC) Requirements
AS/NZS 3548 003 – Standard for radiated and conducted emissions for
Australia and New Zealand, Class A
Type: Specification: (continued)
Overview: Additional Information
KAT4000 User’s Manual 10007175-02
1-12
(PBDEs) and lead (Pb). Configurations that are RoHS compliant are built with lead-free sol-
der. Configurations that are 5-of-6 are built with tin-lead solder per the lead-in-solder RoHS
exemption.
To obtain a certificate of conformity (CoC) for the KAT4000 or other modules, send an e-
mail to sales@artesyncp.com or call 1-800-356-9602. Have the part number(s) (e.g.,
C000####-##) for your configuration(s) available when contacting Emerson.
Terminology and Notation
Active low signals: An active low signal is indicated with an asterisk * after the signal name.
Byte, word: Throughout this manual byte refers to 8 bits, word refers to 16 bits, and long word refers to
32 bits, double long word refers to 64 bits.
PLD: This manual uses the acronym, PLD, as a generic term for programmable logic device (also
known as FPGA, CPLD, EPLD, etc.).
Radix 2 and 16: Hexadecimal numbers end with a subscript 16 or begin with 0x. Binary numbers are shown
with a subscript 2.
Technical References
Further information on basic operation and programming of the KAT4000 components can
be found in the following documents:
Table 1-3: Technical References
Device / Interface: Document: 3
AMC/ATCA Advanced Mezzanine Card Base Specification
(PICMG® AMC.0 Rev. 2.0: November 15, 2006)
PCI Express and Advanced Switching on AdvancedMC
(PICMG® AMC.1 Rev. 1.0: January 20, 2005)
AdvancedTCA® Base Specification
(PICMG® 3.0 Rev. 2.0: March 18, 2005)
Engineering Change Notice 3.0-2.0-001
(PICMG® 3.0 Rev. 2.0: ECN 3.0-2.0-001; June 15, 2005)
AdvancedTCA® Ethernet/Fibre Channel for AdvancedTCA® Systems
(PICMG® 3.1 Rev. 1.0: January 22, 2003)
http://www.picmg.org
CPLD MAX®II Device Handbook
(Altera® MII5V1-1.3, Preliminary; December 2004)
http://www.altera.com
Overview: Additional Information
10007175-02 KAT4000 User’s Manual 1-13
CPU MPC8548E PowerQUICC III™ Integrated Host Processor Family Preliminary
Reference Manual
(Freescale® Semiconductor MPC8548ERM Rev. 1: July 2005)
http://www.freescale.com
EEPROM ATMEL® 2-Wire Serial EEPROM 64K AT24C64B Data Sheet
(ATMEL® Corp., Rev. 3350D-SEEPR: May 2005)
http://www.atmel.com/literature
Ethernet HawX-G26 – 26-Port 10/100/1000 Managed Layer 2 Ethernet Switch,
VSC7376 Data Sheet
(Vitesse Semiconductor Corp., VMDS-10133 Rev. 2.1: August 2005)
HawX-G26 Reference Board Manual/Software Manual
(Vitesse Semiconductor Corp., RBM0007 Rev. 09: November 24, 2005)
http://www.vitesse.com
88E1111 Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Datasheet
(Marvell® Doc. No. MV-S100649-00, Rev. G: February 10, 2006)
http://www.marvell.com
BCM5241 10/100Base-TX/FX Mini- ™ Transceiver Preliminary Data Sheet
(Broadcom® Corporation Document 5241-DS03-R 6/21/05)
http://www.broadcom.com
Flash Intel® StrataFlash® Embedded Memory (P30) Data Sheet
(Intel, Order Number: 306666 Rev. 002: August 2005)
http://www.intel.com
AMD® AM29LV040B 4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only, Uniform
Sector 32-Pin Flash Memory Data Sheet
(Advanced Micro Devices, Inc. Publication #21354 Rev: E; June 11, 2004)
http://www.amd.com
mDOC H3 Embedded Flash Drive (EFD) featuring Embedded TrueFFS® Flash
Management Software Preliminary Data Sheet
(M-Systems Flash Disk Pioneers Ltd., 92-DS-1205-10 Rev: 0.2; June 2006)
http://www.m-systems.com/mobile
Hot Swap™ LTC®4211 Hot Swap Controller with Multifunction Current Control
(Linear Technology Corporation LT/TP 0702 2K 4211f)
LTC®4300A-1/LTC 4300A-2 Hot Swappable 2-Wire Bus Buffers
(Linear Technology Corporation LT/TP 0203 2K sn4300a)
http://www.linear.com
Hot Swap Specification
(PICMG® 2.1 Rev. 2.0: January 17, 2001)
http://www.picmg.org
Device / Interface: Document: 3
Φ
Overview: Additional Information
KAT4000 User’s Manual 10007175-02
1-14
IPMI/IPMB IPMI — Intelligent Platform Management Interface Specification v2.0
(Intel Corp., Hewlett-Packard Co., NEC Corp., Dell Computer Corp., Rev.
1.0; Feb. 12, 2004)
IPMB — Intelligent Platform Management Bus Communications Protocol
Specification v1.0
(Intel Corp., Hewlett-Packard Co., NEC Corp., Dell Computer Corp., Rev.
1.0; Nov. 15, 1999)
IPMI Platform Management FRU Information Storage Definition v1.0
(Intel, Document Revision 1.1; Sept. 27, 1999)
http://www.intel.com/design/servers/ipmi/spec.htm
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual, H8S/2168
Group
(Renesas Technology Corp., Rev. 3.00; March 12, 2004)
http://www.renesas.com
JTAG SCANSTA112 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer Data Sheet
(National Semiconductor Corp., DS200512, May 2004)
http://www.national.com
PCI Express PCI Express™ Base Specification Revision 1.0
(PCI Special Interest Group (PCI-SIG), July 22, 2002)
http://www.pcisig.com
PEX 8524 Versatile PCI Express Switch Preliminary Data Book
(PLX Technology, Inc. Version 0.99: June 2005)
http://www.plxtech.com
Real-Time Clock Serial Access Timekeeper® M41T00
(ST®Microelectronics, June 2004)
http://www.st.com
SDRAM (SO-DIMM)
Module
512MB 64Mx72 DDR2 SDRAM Unbuffered SO-DIMM ECC Product
Specification
(Virtium Technology, Inc. Part Number VL491T6553B-D5/CC Rev. 1.3:
August 2005)
http://www.virtium.com
Serial
Interface
TIA/EIA-232-F: Interface Between Data Terminal Equipment and Data Circuit-
Terminating Equipment Employing Serial Binary Data Interchange
(Electronic Industries Association, October 1997)
http://www.eia.com
Synchronization
Clock Interface
MT9045 T1/E1/OC3 System Synchronizer Data Sheet
(Zarlink™ Semiconductor Inc., February 2005)
MT9046 T1/E1 System Synchronizer with Holdover Data Sheet
(Zarlink™ Semiconductor Inc., February 2005)
http://www.zarlink.com
Device / Interface: Document: 3
Overview: Additional Information
10007175-02 KAT4000 User’s Manual 1-15
3. Frequently, the most current information regarding addenda/errata for specific documents may be found
on the corresponding web site.
KAT4000 User’s Manual 10007175-02
1-16
(blank page)
10007175-02 KAT4000 User’s Manual 2-1
Section 2
Setup
This chapter describes the physical layout of the board and the setup process, including
power requirements and environmental considerations. This chapter also includes trouble-
shooting, service, and warranty information.
ELECTROSTATIC DISCHARGE
Before you begin the setup process, please remember that electrostatic discharge (ESD)
can easily damage the components on the KAT4000 hardware. Electronic devices, espe-
cially those with programmable parts, are susceptible to ESD, which can result in opera-
tional failure. Unless you ground yourself properly, static charges can accumulate in your
body and cause ESD damage when you touch the board.
Caution: Use proper static protection and handle KAT4000 boards only when absolutely necessary.
Always wear a wriststrap to ground your body before touching a board. Keep your body
grounded while handling the board. Hold the board by its edges–do not touch any
components or circuits. When the board is not in an enclosure, store it in a static-shielding
bag.
To ground yourself, wear a grounding wriststrap. Simply placing the board on top of a
static-shielding bag does not provide any protection–place it on a grounded dissipative
mat. Do not place the board on metal or other conductive surfaces.
KAT4000 CIRCUIT BOARD
The KAT4000 is a 16-layer, 8U form factor circuit board that conforms to the PICMG 3.0
Rev. 2 and AMC.0 Rev. 2 mechanical specifications with the exception of a couple non-con-
formances. See the KAT4000 Errata for details. It has the following physical dimensions:
Table 2-1: Circuit Board Dimensions
The following figures show the component maps for the KAT4000 circuit board. Figures are
also provided for the front panel, LEDs, fuse, jumper and JTAG locations.
Width: Depth: Thickness:
Component
Height (top side):
Component Height
(bottom side):
12.687 in.
(322.25 mm)
11.024 in.
(280.0 mm)
0.075 in.
(1.9 mm)
< 0.84 in.
(21.33 mm)
< 0.144 in.
(3.65 mm)
!
Setup: KAT4000 Circuit Board
KAT4000 User’s Manual 10007175-02
2-2
Figure 2-1: Component Map, Top (Rev. 02)
XXXX-
YYYYYY
C422
C374
C457
U81
100Base-T
L13
L8
L9
L7
L12
L11
U80
Flash
Y2
U34
U33
U32
C323
U82
1000Base-T
U79
1000Base-T
C417
C418
C453
C428 C448
C452
C420
C445
C380
C458
C381
C437
C433
C436
C434
C415
C435
C414
L10
U72
U6 U7
U15U14
U24 U27
U56
C337
C383
C394
C291
C395
C335
C94
C411
C400
C425
U36
Clock
U28
Clock
E1
R364
C468
C467
C408
C405
C459
C396
U63
C416
C407
U19
Clock
C404 C442
Y3
C39
C386
R186
C300
C463
C462
C464
C391
C379
C377
C392C378
C393
C375 C397
C410 C419
C65
C64 L6
U59
C403
U37
C382
U61
U60
U18
PLD
U76
SRAM
U69
U62
48->12 volt Power Supply
C216
C217
U21
U8
U16
SW2
SW1
R269
R270
U5
U65
PHY
U70
PHY
RN36
RN12
RN21
RN18
RN25
RN62
RN61
RN19 RN20
RN11
RN44
RN39
RN42
RN37
RN38
RN54
RN52
RN50
RN51RN49
RN48
RN47
RN46
RN40
RN43
RN45
RN41
RN58
RN15RN14
RN65
RN57
RN55
RN53 RN56
RN60RN59
RN28RN26 RN29
RN23 RN24
RN30 RN33RN31 RN34
RN32
RN27
RN35
RN64
RN63
M7
M8
F5
F6
F3
F4
U78
NAND Flash
R290
R199
R297
R296
R295
R200
R321
R320
R303
R304
R305
R306
R323
R291
R289
R322
R288
R298
R318
R287
R293
R286
R238
R351
R349
R292
R245
R354
R319
R2062
R2063
R314
R357
R325
R324
R352
R156
R353
R317
R302
R301 R312
R313
C409
C451
C449
C450
C454
C443
C444
C447
C446
C389
C426
C421
C440
C465
C466
C423
C429
C430
C438
C431
C424
C432
C439
C29
C45
C345
C343
C398
C387
C390
C470
C469
C460
C427
C441
C401
C402
C370
C371
C372
C373
R337
R336
R339
R338
R235
R365
R355 R356
R174
R160
R175
R157
R259
R358
R359
R350
R348
R250
R332
R343
C31
C388
C399
R347
R345
R344
R346
R307 R299
R308
C66
C86
C322
C334
C455
C456
C385
C406
C352
C384
C376
C412 C413
C55
C56
R311
R310
R309
R333
R340
R341
R271
R300
R334
R273
R272
R362
R363
R360
R361
R294
R329
R330
R54
R331
R50
R38
R335
R36
R37
R342
R326
R327
R328
R2004 R2005 R2006
R2007 R2008 R2009
R2012
R2048
R2049
U53
U2000
C2037
C2038
C2036
R2088
R2089
C2034
C2035
R2026
R2027
R2028
R2029
R2030
R2031
R2032
R2033
R2034
R2035
R2036
R2037
C2039
C2040
F1
F2
R1204
C461
R258
R2119
R2120
R2123
R2124
C13
C23
C367
C365
C358
R201
R130
Y5
Y4
U12
U11
U31
C326
C325
C165
C230
C301
C97
C70
C59
C63
C27
C24
C62
C26
C28
C25
C61
C60
C71
C73
C72
C90
C22
C21
C20
R257
R266
R253
R251
U13
C53
C54
L3
L2
U23 U26
U55
U57
U54
C119
C118
C117
C196
C331
C231
C93
C198
C106
C105
C329
C333
C341
C120
C107
U29 U35
U9
PLD
L5
C302
C85
C149
C259
C229
R219
R218
R131
R171
R179
C84
U38
U46
U44
U42
U4
U3
U41
C83
C74
C19
R222
R78
R153
Y1
U1
U22
C324
C48
C183
C35
C36 C80
C34
C81
C38 C82
C79
C78
C37
C67C16
C18 C69
C68C17
C57
C58
C51
C52
L4
L1
U10
U2
Y6
U43
U45
U25
U20
R240
R236
R263
R264
R260
R261
U17
RN6
RN1 RN2 RN3 RN4 RN5
RN22
RN17
RN16
RN13
RN7 RN8 RN9 RN10
U40
U39
U30
M1
M2
M3
M4
M5
M6
R191
R225
R215
R232
R230
R231
R229
R220
R227
R207
R228
R224
R226
R121
R94
R204
R203
R202
R143
R185
R206
R197
R205
R198
R180
R132
R127
R145
R149
R140
R135
R146
R141
R136
R137
R152
R147
R148
R187
R188
R189
R217
R194
R234
R193
R190
R233
R216
R221
R195
R196
R181
R178
R177
R138
R142
R183
R11
R10
R176
R169
R170
R268
R237
R159
R280
R239
R158
R151
R155
R210
R82
R209
R208
R150
R96
R154
R113
R83
R81
R192
R108
R91
R162
R161
R163
R164
R165
R166
R167
R168
R144
R244
R211
R212
R213
R262
R248
R92
R46
R87
R133
R139
R117
R116
R86
R134
R67
R85
R84
R126
R5
R6
R7
R8
R9
R1158
R12
C96
C76
C95
C75
C203
C263
C173
C147 C239
C266
C265
C142
C199C192C177C167 C212C159C144
C179C178
C102 C103
C130
C122
C133
C104
C315
C319
C318
C320
C321
C314
C316
C317
C137
C140
C134
C257
C260
C261
C109 C124
C123
C190
C208
C242
C150
C161
C209
C218
C170
C185
C184
C197
C228
C253
C254
C138
C255
C135
C256
C298
C297
C98 C101
C100C99
C47
C46
C303
C10
C30
C6
C8
C33
C4
C113
C110 C125
C111 C126
C112
C293
C252
C152
C151
C154
C153
C156
C155
C158
C157
C114
C115
C116
C129
C235
C234
C233
C232
C220 C223
C146
C175 C176
C204
C213
C281
C336
C145
C143
C132
C264
C269
C270
C108
C292
C294
C295
C296
C299
C290
C271 C272
C267
C268
C243
C128
C127
C174
C191
C180
C193
C221
C237
C238
C222
C139
C258
C244
C202
C136
C162
C15
C77
C87
C182
C344
C340
C346
C338
C342
C347
C2
C32
C7
C369
C339
C360
C353
C131
C121
C200
C168
C188
C163
C141
C249
C181
C205
C275
C276
C277
C278
C247
C273
C274
C248
C306
C308
C309
C307
C246
C245
C310
C311
C362
C364
C363
C361
C9
C5
C12
C3
C225
C224
C305
C304
C160
C148
C164
C169
C282
C283
C280
C279
C219
C236
C210
C211
C172
C187
C166
C171
C194
C201
C214
C206
C189
C195
C286
C287
C284
C285
C251
C241
C312
C313
C240
C250
C288
C289
C215
C207
C226
C227
C348
C351
C350
C349
C355
C356
C357
C354
R1
R214
R223
R128 R129
R95
R61
R62
R43
R47
R41
R115
R114
R120
R119
R125
R122
R123 R124
R184 R182
R64
R256
R265
R242
R79
R90
R89
R80
R34
R31
R105
R104
R100
R101
R99
R88 R102
R103
R60
R63
R24
R20
R247R246
R32
R29
R40 R42
R21
R22
R23
R18
R19
R17
C14
C1
C11
R2
R109
R98
R97
R45
R26
R3
R4
R28
R51
R16
R249
C40
C327
C332
C330
C328
C366
C359
C368
C91
C92
C262
C186
C88
C89
C43
C44
C50
C49
C42
C41
R39
R44
R35
R25
R14
R15
R13
R173
R172
R112
R118
R110
R285
R243
R267
R278 R279
R274 R275
R33
R27
R30
R49
R283
R284
R281
R282
R276
R277
R65
R53
R66
R107
R52
R93
R48
R241
R1159
R2016
R2018
C2000C2001
C2002
C2003
R2001
R2002
R2013
R2014R2015
R2045
R2050
R2051
R2052
R2053
U58
U52
U51
U50
U49
U48
U47
C2030
C2031
R2085
C2044
L20
R252
R254
R255
U77
K2
Polar Key
ATCA Guide
J33
24-pin
ATCA
Connector
J32
80-pin ATCA
Zone 3
Connector
J31
80-pin ATCA
Zone 3
Connector
J30
80-pin ATCA
Zone 3
Connector
JP4
JP3
CR40
CR41
K1
Polar Key
ATCA Guide
J20
80-pin ATCA
Zone 2
Connector
J34
J23
80-pin ATCA
Zone 2
Connector
JP2
JP7JP1
P10
34-pin ATCA
Zone 1
Connector
00000000-00 D
CR38 CR39CR36CR35 CR37
U66
PHY
U71
PHY
U67
PHY
U73
U74
U75
U68
MPC8548
Processor
U64
DDR2
SO-DIMM
J10
J4
J3
J2
J1
P1
CR34
CR33
CR32
CR29
CR30
CR31
CR28
CR27
CR14
CR12
CR9
CR10
CR19
CR16
CR18
CR21
CR1
CR3
CR5
CR7
CR25
CR24
CR20
CR23
CR22
CR17
CR15
CR13
CR11
CR26
CR8
CR6
CR2
CR4
COPYRIGHT 2006
Setup: KAT4000 Circuit Board
10007175-02 KAT4000 User’s Manual 2-3
Figure 2-2: Component Map, Bottom (Rev. 02)
R68
R2137
R2125
R2112
R2111
R2110
R2109
R2131
R1023
R1016
C592
C590
C588
C585
R2133
U2002
C827
C833
C668
R1202
R1201
R2126
R2122R2121 R2118R2117
R2116
R2115
R2114
R2113
R1200
C2043
R2132
C2041
R2134
R2130
R2129
R2128
R2127
C2042
R2136
R2107
R2106
R2105
R2104
R2103
R2102
R2101
R2100
R2097
R2096
R2099
R2098
R2094
R2092
R2095
R2093
R1203
R1208
R1207
R1206
R1205
R2108
R2091
R2090
U98
U99
R2086
R2087
CR2004
C2033
C2032
C2028
C2027
C2023
C2022
C2018
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R2084
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R2079 R2078
C2029 C2024
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R2073
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C863
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C591 C586
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R2011 R2010
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R710
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R809
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R1104
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R1111
R1114
R1123
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R1113 R1125
R367
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R372
R374
R570
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R954
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C688
C867
C593
C752
C619
R716
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R865
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R834 R870
R744
R563
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R578
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R386
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R877
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R1012
R838
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R599
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R1065
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R873
R1005
R1032
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R1038
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R566
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R540 R541
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R428
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R391
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R734 R739 R749
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R955R945R876 R879
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R1096
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R750 R752 R754 R756
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R1122
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R545
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R721 R727
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R725 R715
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R719
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R455
R520
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R682
R506
R949
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R704
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R548
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R743
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R748R746
R883
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R501
R568
R944
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R664
R960
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R574
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R514
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C596
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C612
C613
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C615
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C608
C607
C894
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C886
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C900
C901
C905
C603
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C587 C589
C601
C584
C851
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C858
C857
C852
C899 C902
C523
C530
C516
C524
C882
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C889 C890
C507
C493
C475
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C478
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C872
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C885
C699
C707
C737
C480
C481
C663
C660
C634
C629 C658
C632
C574
C580
C555 C564
C572 C567
C573
C582
C579
C566
C512
C471
C477
C472
C486
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C577 C578
C560 C565
C544
C568
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C625C622
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C620 C624
C754
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C801 C826 C835
C809 C828
C800
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C792
C738
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C627
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C895 C904
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C502 C503
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C556 C558
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C765
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C741
C838
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C788C770
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C888
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C628
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C633 C662
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C536 C538
C535 C537
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C728
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C798C771
C744
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C685 C777
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C730 C721 C722
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C691C692
C684
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R2061 R2059
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C2010
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C819
C818
C817
C816
M9
M10
CR2003CR2001 CR2002CR2000
R55
R56
R57
R58
SW3
J2000
RN71 RN72
RN70RN69
RN66
RN73 RN74 RN75
RN76 RN77 RN78
RN68
RN67
U84
PEX8524 Switch
U85
U97
L17
L18
L19
C639
C723
U83
VSC7376 GbE Switch
C710
C711
C712
C715
C714
C713
U88
C778
C780
C779
C781
C487
C636
C648
J35
R419R418
R406
C877
C876
U92
Flash
U91
Flash
U93
C506
L14
C534
R941
R407
U90
C859
C753
C725
U101U100
U94
U95
U96
U86
U87 U89
R1087
R1088
C860
C796
C832
C551
C892
C782
C783
C786
C784
C785
R939
R940
R630
R629
L16
L15
Q5
R1050
R1037
R943
R942
R59
F10
F7
F9F8
CR43 CR44
CR42
C880
C896
COPYRIGHT 2006
Setup: KAT4000 Circuit Board
KAT4000 User’s Manual 10007175-02
2-4
Front Panel
The front panel, shown in Fig. 2-3, consists of four single-width, mid-size Advanced Mezza-
nine Card (AMC) sites (double-width and compact modules can be accommodated), a hot
swap LED, an out of service LED, two user LEDs (see “LEDs” on page 2-10 for more informa-
tion), and a reset switch.
Note: When using a compact AMC module, the module must have a front panel that fully covers the front opening
of the KAT4000 to maintain EMC compliance.
Figure 2-3: KAT4000 Front Panel
Note: The electromagnetic compatibility (EMC) tests used a KAT4000 model that includes a front panel assembly
from Emerson.
Caution: For applications where the KAT4000 is provided without a front panel, or where the front
panel has been removed, your system chassis/enclosure must provide the required
electromagnetic interference (EMI) shielding to maintain CE compliance.
Connectors
The KAT4000 circuit board has various connectors (see Fig. 2-1), summarized as follows:
EIA-232: A serial port is accessible off of the CPU through an on-board header for development pur-
poses and routes to Zone 3.
Ethernet: A 10/100 Ethernet port is accessible off of the CPU through Zone 3.
AMC Expansion Sites J1-J4:
Each site is capable of supporting an AMC module, depending on the configuration, using
B+ style AMC connectors. J1-J4 map to sites B1-B4 (see Table 8-1 for pin assignments).
Backplane Connectors: Whether individual backplane connectors are populated on the KAT4000 depends on the
specific product configuration. PICMG 3.0 specification defines three connector zones on
the backplane:
Zone 1 is the power connection (dual redundant -48V DC) and system management
connections—P10
Zone 2 is the data transport interface covering: Base, Fabric, and Synchronization clock
interfaces—J20 through J24
Front Panel
KAT4000
OOS
2
3
H/S
B1
B2
B3
B4
Out of service
and user LEDs
Hot
Swap
LED
AMC1 AMC2 AMC3 AMC4
RST
Reset
Switch
!
Setup: KAT4000 Circuit Board
10007175-02 KAT4000 User’s Manual 2-5
Zone 3 (ATCA) is for the optional Rear Transition Module (RTM) I/O interconnect—J30
through J33
P10: This connector provides the power and IPMB to the KAT4000. The P10 connector has four
levels of sequential mating to provide the proper functionality during live insertion or
extraction of the KAT4000. See Table 12-1 for the pin assignments.
J20, J23: The 80-pin Zone 2 (ZD) connectors provide three levels of sequential mating. See Table 12-2
and Table 12-3 for pin assignments.
J30-J32: The 80-pin Zone 3 (ZD) connectors provide an interconnect to an optional RTM. Connec-
tions include AMC ports 12-20, serial ports, a debug Ethernet port, and various other inter-
faces. See Table 12-4, Table 12-5 and Table 12-6 for pin assignments.
J33: The 24-pin Zone 3 connector provides the 3.3 volt, 12 volt, and transmit/receive signals to
the AMCs. See Table 12-7 for the pin assignments.
J2000: This hot swap switch header is a connector only–a switch assembly (P/N 10005468-xx)
connects to this socket.
Header JP4
JP4 is the 16-pin serial port header for the IPMC debug console, fat pipe debug console, and
host debug console. See Table 2-2 for signal descriptions. See Fig. 2-4 for the header’s loca-
tion.
Table 2-2: JP4 Signal Descriptions
Jumpers
The following KAT4000 jumpers select the boot device, SROM initialization, logic probe,
and whether the IPMC will communicate with the shelf manager system. See Table 2-3 for
jumper descriptions. Fig. 2-4 and Fig. 2-5 show jumper, switch and fuse locations.
Jumper: Pin: Signal Description: Pin: Signal Description:
JP4
1 IPMC_RS232_TX 2 GND
3 IPMC_RS232_RX 4 GND
5no connect 6 GND
7FP_CONN_RX 8GND
9 FP_CONN_TX 10 GND
11 no connect 12 GND
13 HOST_CONN_RX 14 GND
15 HOST_CONN_TX 16 GND
Setup: KAT4000 Circuit Board
KAT4000 User’s Manual 10007175-02
2-6
Table 2-3: Jumpers–JP2 and JP7
Note: Jumper settings for JP7 pins 1:2, 3:4 and 5:6 are not applicable to the no-CPU KAT4000 board configuration.
Jumper: Shunt Description:
Register
Map:
JP2
1:2 IPMC Mode bit MD2
out-factory use only–used for initial programming of the IPMC
controller (default) N/A
3:4 IPMC Mode bit MD1
out-factory use only–used for initial programming of the IPMC
controller (default)
JP7
1:2 Boot from socket
in-boot from ROM socket (default)
out-boot from soldered flash
7-7
3:4 Ignore SROM
in-CPU ignores SROM (default)
out-CPU loads from SROM
5:6 Boot redirect (see Register Map 7-4 and Register Map 7-15)
in-disabled The board only attempts to boot from the device
specified by JP7 1:2.
out- enabled (default) The board cycles through the boot
devices until a valid boot image is executed.
7:8 Logic probe–Reserved
out-(default)
9:10 Standalone (SA) mode
in-in ATCA standalone mode, the IPMC disconnects IPMB-0, then
activates/deactivates the board itself
out-in ATCA normal mode, the IPMC communicates with the
shelf manager to activate/deactivate the board (default)
Setup: KAT4000 Circuit Board
10007175-02 KAT4000 User’s Manual 2-7
Figure 2-4: Jumper, Fuse and Switch Locations, Top
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
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
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
70
  

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
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
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
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
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
JP3 - PLD Prog. JTAG
JP4 - Serial Port:
1-4 IPMC
7-10 Fat Pipe Module
13-16 Host CPU


SW2 - Main Reset
JP7 - Boot
1:2 Boot from socket (defaultinstalled)
3:4 Ignore SROM
5:6 Enable boot redirection
7:8 Logic probe
9:10 Standalone (SA) mode
JP2 - IPMC
1:2 IPMC Mode bit MD2
3:4 IPMC Mode bit MD1
SW1 - IPMC Reset
JP1 - PLD Config. Header




F3 - Fuse

F5 - Fuse

F6 - Fuse

F4 - Fuse

F2 - Fuse

F1 - Fuse

P1 - CPU JTAG/COP
%)&.+92
Setup: KAT4000 Circuit Board
KAT4000 User’s Manual 10007175-02
2-8
Figure 2-5: Jumper, Fuse and Switch Locations, Bottom

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


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














 

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















 


 


 








































































































 


































 










  
  




















































 



























 



J2000 - Hot Swap Switch Header
F7 - Fuse

J35 - IPMC JTAG/Emulation Header
F8 - Fuse (
 F9 - Fuse

F10 - Fuse

SW3 - Front Panel Reset
%)&.+92
Setup: KAT4000 Circuit Board
10007175-02 KAT4000 User’s Manual 2-9
JTAG Interfaces
The KAT4000 provides the capability for JTAG type boundary scan testing. The IPMC con-
trols the two JTAG interfaces (hubs), see Fig. 2-6. One JTAG hub is connected to the fat pipe
switch module, two PLDs, and the four AMC sites. The other hub is connected to the Ether-
net core switch, the PCI Express switch, the processor, the GbE PHYs, and the synchroniza-
tion clock circuitry. See Fig. 2-4 and Fig. 2-5 for the location of individual headers.
Figure 2-6: JTAG Hubs
P1: The 16-pin JTAG/COP P1 header is provided for debug purposes for the processor. This inter-
face provides for boundary-scan testing and COP debugger support of the CPU (see Fig. 3-2)
and is compliant with the IEEE 1149.1 standard. The header pin assignments are defined in
Table 3-6.
Caution: Install a shunt on JP1 pins 1:2 before using the JTAG/COP interface (P1) to enable CPU
JTAG/COP access. Attempting to use the JTAG/COP interface without this shunt in place may
cause damage to the board. Refer to Table 7-3 for JP1 pin details.
JP3: The 10-pin JTAG JP3 header is provided for programming In-System Programmable (ISP)
PLDs (see Fig. 7-2). The header pin assignments are defined in Table 7-2.
AMC 1
AMC 2
AMC 4
AMC 3
VSC7376
Ethernet Core Switch
Layer 2
PEX8524
PCI Express Switch
MPC8548
Processor
COP/JTAG
P1
SCANSTA112
JTAG Multiplexer
SCANSCA112
JTAG
Multiplexer
Master
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 0
SCANSTA112
JTAG Multiplexer
SCANSCA112
JTAG
Multiplexer
Master
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 0
GbE PHY
(5)
Clock
Synch. (3)
KSL PLD
IPMC PLD
Prog.
Header JP3
IPMC GPIO
JTAG/Debug
Header J35
Fat Pipe
Switch Module
Config.
Header JP1
!
Setup: KAT4000 Circuit Board
KAT4000 User’s Manual 10007175-02
2-10
JP1: The 10-pin JP1 configuration header is provided for PLD programming. Installing a shunt on
JP1, pins 1:2, enables the JP3 PLD programming header. The header pin assignments are
defined in Table 7-3.
J35: J35 is the 14-pin IPMC JTAG/emulation header. See Table 2-4 for signal descriptions.
Table 2-4: J35 Signal Descriptions
LEDs
See Fig. 2-7 for the on-board Light-Emitting Diodes (LEDs). The KAT4000 has four front
panel LEDs. See Fig. 2-8 for their location. The debug LED codes are defined in Table 14-1. The
front panel LEDs include:
2 and 3: The yellow (CR2000) and green (CR2002) LEDs are user defined.
OOS: The Out Of Service (CR2003) programmable LED controlled by the IPMI controller is either
red (North America) or yellow (Europe). When lit, this LED indicates the KAT4000 is in a
failed state.
HS: The blue Hot Swap LED (CR2001) displays four states:
On-the board can be safely extracted
Off-the board is operating and not safe for extraction
Long blink-insertion in progress
Short blink-requesting permission for extraction
Caution: Do not remove the KAT4000 while the blue LED is blinking.
Reference the PICMG® 3.0 Revision 2.0 AdvancedTCA™ Base Specification for more detailed
LED information.
Jumper: Pin: Signal Description: Pin: Signal Description:
J35
1IPMC_TCK 2GND
3IPMC_TRST* 4GND
5IPMC_TDO 6GND
7 IPMC_EMUL_RESI* 8 3_3 volts
9IPMC_TMS 10GND
11 IPMC_TDI 12 GND
13 IPMC_RES* 14 GND
!
Setup: KAT4000 Circuit Board
10007175-02 KAT4000 User’s Manual 2-11
Figure 2-7: LEDs, Top
&
&
&
&
&
&!
&
&
&
&
&
&
&!
&
&!
&
&
&
&
&
&
&
&& & & &!
&
&
&
&
&
&
&
&
&
&
&
&
&
&
Internal 8051 Debug
:0;<+:0
:0;<+:0
:0;<+:0
:0;<+:0
0;<+:0=
0;<+:0=
0;<+:0=
0;<+:0=
Debug
Boot Device
CPU Status
:0=
:0=
(2:0=
<:+&*0=
<:&00=
<:(2:%<2=
PCIe Lane Good
:*:+0
:*:+0
:*:+0
:*:+0
:*:+0
:*:+0
:*:+0
:*:+0
:*:+0
:*:+0
:*:+0
:*:+0
IPMC PLD Status
>"/
?"'1"6/
@1"6/
@1"6/
 @1"6/
@1"6/
@1"6/
<#/?"'1"6/
2(:2.@.2):0
2(:.*:0
Status:
10/100
Debug
Ethernet
Activity:
Fat Pipe, Core Switch,
Base PHYs
(:2:0
(A:2:0
(A:2:0
;:.*:2:0
;:.*:2:0
Setup: KAT4000 Circuit Board
KAT4000 User’s Manual 10007175-02
2-12
Figure 2-8: LEDs, Bottom
CR2001   CR2003
Hot Swap
;<:0:%**
User
0:%**
User
0:%**
Out of Service
0:%**-0&:%**
B&-,/C
Setup: KAT4000 Circuit Board
10007175-02 KAT4000 User’s Manual 2-13
Reset
The reset signals are routed to the PLD. See Chapter 7 for the reset registers. The following
sources can reset the KAT4000:
Front Panel: The front panel reset switch can reset the board.
Remote IPMI: The KAT4000 is capable of being reset remotely via the IPMI controller.
Software: Software is capable of asserting reset to the individual modules (see “reset” on
page 14-25).
Processor: The processor is also capable of resetting the board.
RTM: If a rear transition module is used that utilizes the Zone 3 reset signal, the board can be
reset from the RTM.
Setup: KAT4000 Circuit Board
KAT4000 User’s Manual 10007175-02
2-14
Figure 2-9: KAT4000 Reset Diagram
Soldered Flash
16/32/64MB
MPC8548
Processor
KSL
CPLD
%:9&(2:*
DEBUG_HRESET*
%:(&(2:*
Voltage
Monitor
250ms
Delay
Voltage
Monitor
250mS
Delay
<:9&(2:*
<:(&(2:*
DEBUG_SRESET*
CPU
COP/
JTAG CPU_SRESET*
CPU_HRESET*
PCIE_RST*
OSC_EN
FLASH_RST*
(9:&(2:*
%(:*
.:&(2:*
PAYLD_RST*
POR_RST*
3_3V
PWR_OK
PWRGD_OR
3_3V
3_3V
Front Panel
RESET
1_5V 1_5V
)0:&(2:*
PCI Express
Switch
Clock Tree
A&:%
3_3V
IPMC
PLD
%&:&(2:*
CORESW_RST*
%&(A:&(2:*
Core Switch
Port 3 PHY
Core Switch
Port 2 PHY
Ethernet
Core Switch
BC_RST*
;:&(2:*
Base Channel 2
Base Channel 1
GbE PHY
NAND_RST*
**0:&(2:* NAND Flash
256/512MB
EDEBUG_RST*
0;<+:&(2:* Debug 10/100
Ethernet PHY
FP_RST*
:&(2:* Fat Pipe
GbE PHY
Fat Pipe
Module Site
CLK_SYNC2_RST*
:()*BDC:&(2:*
MT9046 Clock
Synchronizers
(3)
<:2&(2:* CPU_TRST*
L_PAYLD_EN
FP_PWR_GOOD
3_3V_PWRGD
2_5V_PWRGD
1_8V_PWRGD
1_2V_PWRGD
1_0V_PWRGD
CPU_CORE_PWRGD
DEBUG_TRST*
3_3V
HRESET_REQ*
3_3V
CLK_SYNC1_RST*
CLK_SYNC3_RST*
NAND_WARM_RST*
**0:A&:&(2:*
DDR2_RST* DDR2
SODIMM
00&:&(2:*
125 MHz
20 MHz
25 MHz
33 MHz
IPMC
9&(2:&E:*
%:2&(2:*
3_3V
2_5V
3_3V
1_8V
1_2V
1_0V
1_1V_CPU_CORE
SCANSCA112_RST* PLD JTAG
MUX
3_3V_MP
33 MHz OSC33_IPMC
3_3V_MP
3_3V_MP
IPMC
RESET
IPMC_PO_RST*
I2C
I/O Port
PRIV_I2C_SCL
PRIV_I2C_SDA
IPMC
BMR-H8S
16-Bit uP
3_3V_MP
Hotswap
Switch
E_HANDLE
OSC_EN
48A_OK*
48B_OK*
IPMC_RST_PB*
3_3V
Voltage
Monitor
250mS
Delay
3_3V_MP
-48V
to 12V
Brick
IPMC_RES*
AMCs
PB_RST*
IPMC
NVRAM
AMCs
4
/
Bn_EN*
Setup: KAT4000 Setup
10007175-02 KAT4000 User’s Manual 2-15
KAT4000 SETUP
For step-by-step setup instructions, see the KAT4000 Quick Start Guide, #10008585-xx, or
the KAT4000 Quick Start Guide for the No-CPU Carrier Board, #10008506-xx.
You need the following items to set up and check the operation of the Emerson KAT4000:
KAT4000 carrier
ATCA chassis and power supply
Compatible AMC modules
Console serial cable(s)
Optional rear transition module and cable
CRT terminal
Save the antistatic bag and box for future shipping or storage.
Note: This guide assumes that the host is running Red Hat Linux 9.0. If you use a different Linux distribution, you’ll
have to adapt these instructions to your implementation.
Identification Numbers
Before you install the KAT4000 circuit board in a system, you should record the following
information:
The board serial number: 711_______________________________________ .
The board serial number appears on a bar code sticker located on the back of the board.
The board product identification: _____________________________________ .
This sticker is located near the board serial number.
The monitor version: _______________________________________________ .
The version number of the monitor is on the monitor start-up display.
The operating system version and part number:__________________________ .
This information is labeled on the master media supplied by Emerson or another vendor.
Any custom or user ROM installed, including version and serial number:
________________________________________________________________ .
It is useful to have these numbers available when you contact the Technical Support
department at Emerson.
Setup: KAT4000 Setup
KAT4000 User’s Manual 10007175-02
2-16
Power Requirements
The KAT4000 draws all payload power from the dual redundant -48 volt inputs on the ATCA
connector P10 (Zone 1). Under normal operating conditions, the power requirement is
shared between the two -48 volt supplies. Power is limited to 200 watts maximum (includ-
ing AMC and optional RTM sites), with 80W maximum per site and a combined max of
120W to all four sites and the RTM, if used. Optional RTMs receive their power from the
KAT4000. Table 2-5 lists the board’s typical power requirements.
Table 2-5: Typical Power Requirement
Note: When the KAT4000 is powered off, so is the RTM.
The exact power requirements for the KAT4000 circuit board depend upon the specific
configuration of the board, including the CPU frequency and amount of memory installed
on the board. Please contact Emerson Technical Support at 1-800-327-1251 if you have
specific questions regarding the board’s power requirements.
Environmental Considerations
As with any printed circuit board, be sure that air flow to the board is adequate. Chassis
constraints and other factors greatly affect the air flow rate. The environmental require-
ments are shown in Table 2-6 and Table 2- 7.
Table 2-6: Environmental Requirements
Table 2-7: Air Flow Requirements
1. The physical placement of AMC modules greatly affects air flow requirements. Air flow is required at the
processor to maintain junction temperature less than 105° C at specified ambient temperature.
Configuration: Watts:
1.3 GHz 8548 processor, 1 GB DDR2 SDRAM,
No AMC modules
40 W
Environment: Range: Relative Humidity:
Operating
Temperature
0° to +55° Centigrade, ambient
(at board)
Not to exceed 85%
(non-condensing)
Storage Temperature —40° to 70° Centigrade Not to exceed 95%
(non-condensing)
Altitude 0 to 4,000 meters above sea level n/a
Configuration: Power/Temperature: Air Flow:
1.3 GHz processor with
1 GB DDR2 SDRAM14 AMC
modules
182 W @ 55° C
(35.5 W per AMC)
21 CFM
Setup: Troubleshooting
10007175-02 KAT4000 User’s Manual 2-17
Cooling requirements are a function of operating software, AMC power consumption and
AMC airflow resistance. The KAT4000 thermal performance must be verified in the end
user’s operating environment. Contact Emerson Technical Support at 1-800-327-1251 for
more information.
TROUBLESHOOTING
For instructions on how to properly install and configure the KAT4000 in a system, see the
KAT4000 Quick Start Guide, #10008585-xx, or the KAT4000 Quick Start Guide for the No-CPU
Carrier Board, #10008506-xx. If difficulty persists after referencing the Quick Start Guide,
use this checklist:
Be sure all modules are seated firmly: the AMC modules on the KAT4000, the RTM on
the KAT4000 (if used), and the KAT4000 in the card cage.
Verify the jumper settings (see Table 2-3).
Be sure the system is not overheating.
Check the cables and connectors to be certain they are secure.
Check your power supply for proper DC voltages.
Check that your terminal is connected to a console port.
Technical Support
If you need help resolving a problem with your KAT4000, visit
http://www.artesyncp.com/support/index.html#postsales on the Internet or send e-mail
to support@artesyncp.com. Please have the following information available:
KAT4000 serial number
monitor revision level
product identification from the sticker on the KAT4000 board
version and part number of the operating system (if applicable)
whether your board has been customized for options such as a higher processor speed
or additional memory
license agreements (if applicable)
If you do not have Internet access, please call Emerson for further assistance:
(800) 327-1251 or (608) 826-8006 (US)
44-131-475-7070 (UK)
Setup: Troubleshooting
KAT4000 User’s Manual 10007175-02
2-18
Product Repair
If you plan to return the board to Emerson Network Power for service, visit
http://www.artesyncp.com/support on the internet or send e-mail to
serviceinfo@artesyncp.com to obtain a Return Merchandise Authorization (RMA) number.
We will ask you to list which items you are returning and the board serial number, plus your
purchase order number and billing information if your KAT4000 hardware is out of war-
ranty. Contact our Test Services Department for any warranty questions. If you return the
board, be sure to enclose it in an antistatic bag, such as the one in which it was originally
shipped. Send it prepaid to:
Emerson Network Power, Embedded Computing
Test Ser vices Department
8310 Excelsior Drive
Madison, WI 53717
RMA #____________
Please put the RMA number on the outside of the package so we can handle your problem
efficiently. Our service department cannot accept material received without an RMA num-
ber.
10007175-02 KAT4000 User’s Manual 3-1
Section 3
Central Processing Unit
This chapter is an overview of the processor logic (optional) on the KAT4000. It includes
information on the CPU, exception handling, and the I/O parallel port pin assignments. The
KAT4000 uses a Freescale MPC8548 PowerQUICC III™ microprocessor. For more detailed
information, refer to the MPC8548E PowerQUICC III™ Integrated Host Processor Family Refer-
ence Manual. Refer to Fig. 3-1 for a block diagram of the MPC8548. The MPC8548 is divided
into two main system blocks as outlined in the following table:
Table 3-1: MPC8548 Features
Category: MPC8548 Key Features:
Microprocessor Core
Embedded e500 Core Full 32-bit Book E architecture, integer data types of 8, 16, and 32 bits,
32-bit floating-point data type, capable of issuing and completing two
instructions per clock cycle, 7 pipeline stages, Auxiliary Processing
Units (APUs), page address translation, core registers, memory
management unit
L1 Cache 32-kilobyte data and 32-kilobyte instruction cache, 32-byte line,
eight-way set associative, parity protection
L2 Cache 512 kilobytes, eight-way set associative
CPU Core Speed 1 GHz or 1.3 GHz, with a 400 MHz or 533 MHz DDR2 bus, respectively
Peripheral Modules
Ethernet Four 10/100/1000 enhanced three-speed controllers (eTSEC), full-
/half-duplex support, for high-speed interconnect, a set of multiplexed
pins support two high-speed interface standards: 1x/4x serial RapidIO
(with message unit) and up to x4 PCI Express
Local Bus Controller (LBC) DDR2 SDRAM memory controller, General Purpose Chip Select
Machine (GPCM), and three User-Programmable Machines (UPM)
High-Speed Serial
Interfaces
PCIe, sRIO
Central Processing Unit:
KAT4000 User’s Manual 10007175-02
3-2
Figure 3-1: MPC8548 Block Diagram
The MPC8548 PowerQUICC III version follows the PowerQUICC II communications proces-
sor. Some new MPC8548 features used on the KAT4000 include:
e500 core 32-bit implementation of the Book E architecture
Serial Management Channel (SMC) UART functionality implemented in SCC
Four integrated 10/100/1000 Ethernet controllers
Double Data Rate Two (DDR2) SDRAM memory controller
4-port On-Chip Network (OCeaN) full crossbar switch fabric
Enhanced debug features
For more detailed information, reference the Freescale application note Migrating from
PowerQUICC II to PowerQUICC III.
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Central Processing Unit: MPC8548 Functions
10007175-02 KAT4000 User’s Manual 3-3
MPC8548 FUNCTIONS
The MPC8548 provides the following functions on the KAT4000 module.
•Dual UART devices
•Two I
2C controllers
Programmable interrupt controller
•DDR2 SDRAM memory controller
General-purpose I/O (GPIO)
Chip select generation for the local bus devices
DMA capability
•PCI-X bus interface
•sRIO or PCIe controller
Four three-speed Ethernet controllers
MICROPROCESSOR CORE (E500)
L1 Cache
The MPC8548 processor implements two separate 32-kilobyte, level-one (L1) instruction
and data caches that are eight-way, set-associative. The L1 supports a four-state modi-
fied/exclusive/shared/invalid (MESI) cache coherency protocol. The caches also employ
pseudo-least recently used (PLRU) replacement algorithms within each way.
L2 Cache
The internal 512 kilobyte L2 cache is an eight-way set associative instruction and data
cache. The L2 cache is fully pipelined to provide 32 bytes per clock to the L1 caches. The L2
Control (L2CTL) register configures and operates the L2 SRAM array. The L2CTL is
read/write and contents are cleared during power-on reset.
The L2 cache is cleared following a power-on or hard reset. Before enabling the L2 cache,
configuration parameters must be set in the L2CR and the L2 tags must be globally invali-
dated. Initialize the L2 cache during system start-up per the following sequence:
1Power-on reset is automatically performed by the assertion of HRESET* signal.
2Verify that L2CR[L2E] = 0.
3Perform an L2 global invalidate by setting L2CR[L21].
Central Processing Unit: Microprocessor Core (e500)
KAT4000 User’s Manual 10007175-02
3-4
4Poll L2CR[L2I] until it is cleared.
5Enable the L2 cache for normal operation and then set the L2CR[L2E].
Timer/Counter
Each of the four 32-bit wide timer/counters can be selected to operate as a timer or a
counter. Each timer/counter increments with every TCLK rising edge. In counter mode, the
counter counts down to terminal count, stops, and issues an interrupt. In timer mode, the
timer counts down, issues an interrupt on terminal count, reloads itself to the programmed
value, and continues to count. Reads from the counter or timer are completed directly from
the counter, and writes are to the timer/counter register.
PCI Device and Vendor ID Assignment
The KAT4000 has been assigned the following PCI identification number:
Table 3-2: PCI Device and Vendor ID
The KAT4000 sets the PCI revision ID to the hardware version number located in the CPLD’s
Hardware Version register (Register Map 7-2).
L2 Control Register (L2CR)
Register 3-1: L2 Control Register (L2CR)
L2E: L2 Enable—enables L2 cache or memory-mapped SRAM (L2 array).
0 L2 array disabled
1 L2 array enabled
L2I: L2 Flash Invalidate
0 L2 status and LRU bits are not being cleared
1 Clears all L2 status bits and LRU
Vendor ID: Device ID: Description:
0x1223 0x001B Reported by the PCI bridge
0123456 8910111213 15
L2E L2I L2SIZ reserved L2
DO
L2I0 RL2IN
TDIS
L2SRAM
16 17 18 19 20 21 22 23 24 27 28 29 30 31
reserved L2
LO
L2
SLC
RL2LF
R
L2LFRID reserved
L2STA
SHDIS
RL2STASH
Central Processing Unit: Microprocessor Core (e500)
10007175-02 KAT4000 User’s Manual 3-5
L2SIZ: L2 SRAM Size—indicates the total available L2 SRAM size (read-only).
00 Reserved
01 256 kilobyte
10 512 kilobyte
11 1024 kilobyte
L2DO: L2 Data-Only mode (reserved in full memory-mapped SRAM mode)
0 L2 cache allocates entries for instruction fetches that miss in the L2
1 L2 cache allocates entries for processor data loads that miss in the L2
L2IO: L2 Instruction Only—causes L2 cache to allocate lines for instruction cache transactions only
(reserved in full memory-mapped SRAM mode).
0 L2 cache entries allocated for data loads that miss in the L2 and for processor L1
castouts
1 L2 cache allocates entries for instruction fetch misses
L2INTDIS: L2 read Intervention Disable (reserved for full memory-mapped SRAM mode)
0 Cache intervention enabled
1 Cache intervention disabled
L2SRAM: L2 cache/memory-mapped SRAM block assignment
L2SIZ = L2BLKSIZ (1 block):
000 Block 0 = cache
001 Block 0 = SRAM0
010-111 Reserved
L2SIZ = L2BLKSIZx2 (2 blocks):
Block 0 Block 1
000 Not used Cache
001 SRAM0 Not used
010 SRAM0 Cache
011 SRAM0 SRAM1
100-111 Reserved
L2LO: L2 cache Lock Overflow—sticky bit sets when an overlook condition is detected in L2 cache
(reserved in full memory-mapped SRAM mode).
0 Lock overflow not detected (clear L2LO in software)
1 Lock overflow condition detected
L2SLC: L2 Snoop Lock Clear—sticky bit sets when a snoop invalidated a locked data cache line
(reserved in full memory-mapped SRAM mode).
0 Snoop did not invalidate (clear L2LO in software)
1 Snoop invalidated a locked line
Central Processing Unit: Microprocessor Core (e500)
KAT4000 User’s Manual 10007175-02
3-6
L2LFR: L2 cache Lock bits Flash Reset—L2 cache must be enabled for reset to occur (reserved in full
memory-mapped SRAM mode).
0 L2 cache lock bits are not cleared or the clear operation completed
1 Reset operation clears each L2 cache line’s lock bits
L2LFRID: L2 cache Lock bits Flash Reset select Instruction or Data—indicates whether data, instruc-
tion, or both bits are reset.
00 Not used
01 Reset data locks if L2LFR=1
10 Reset instruction locks if L2LFR=1
11 Reset both data and instruction locks if L2LFR=1
L2STASHDIS: L2 Stash allocate Disable—disables allocation of lines for stashing.
00 L2 allocates lines
01 L2 does not allocate lines
L2STASH: L2 Stash configuration—reserves regions of cache for stash-only operation.
00 No stash-only region
01 One-half of the array is stash-only
10 One-quarter of the array is stash-only
11 One-eighth of the array is stash-only
Hardware Implementation Dependent 0 Register
The Hardware Implementation Dependent 0 (HID0) register contains bits for
CPU-specific features. Most of these bits are cleared on initial power-up of the KAT4000.
Please refer to the MPC8548 PowerQuicc III Integrated Communications Processor Reference
Manual for more detailed descriptions of the HIDx registers. The following register map
summarizes HID0 for the MPC8548 processor:
Register 3-2: MPC8548 Hardware Implementation Dependent Register 0 (HID0)
EMCP: Enable Machine Check Pin—masks further machine check exceptions caused by assertion of
MCP*.
0 MCP* is disabled
1 MCP* is enabled
32 33 39 40 41 42 43 47
EM
CP
reserved DOZ
E
NAP SLP reserved
48 49 50 51 55 56 57 58 62 63
RTB
EN
STB
CLK
reserved
EN_
MAS7
DCF
A
reserved NOP
TI
Central Processing Unit: Microprocessor Core (e500)
10007175-02 KAT4000 User’s Manual 3-7
R: Reserved should be cleared.
DOZE: Doze power management mode
0 Doze mode disabled
1 Doze mode enabled
NAP: Nap power management mode
0 Nap mode disabled
1 Nap mode enabled
SLP: Sleep power management mode enable
0 Sleep mode disabled
1 Sleep mode enabled
TBEN: Time Base Enable
0 Time base disabled (no counting)
1 Time base enabled
STBCLK: Select Time Base Clock—functions if the time base is enabled.
0 Time base is based on the processor clock
1 Time base is based on the TBCLK (RTC) input
EN_MAS7: Enable MAS7 update—enables updating MAS7 by tibre and tibsx.
0 MAS7 is not updated
1 MAS7 is updated
DCFA: Data Cache Flush Assist—forces data cache to ignore invalid sets on miss replacement selec-
tion.
0 DCFA is disabled
1 DCFA is enabled
NOPTI: No-op the data and instruction cache touch instructions
0dcbt, dcbst, and icbt are enabled
1dcbt, dcbst, and icbt are treated as no-ops
Hardware Implementation Dependent 1 Register
One of the functions of the Hardware Implementation Dependent 1 (HID1) register is to
display the state of the PLL_CFG[0:4] signals. The following register map summarizes HID1
for the MPC8548 CPU:
Central Processing Unit: Interrupts and Exception Processing
KAT4000 User’s Manual 10007175-02
3-8
Register 3-3: MPC8548 Hardware Implementation Dependent Register 1 (HID1)
PLL_MODE: Read-on