IP Mobilenet ECSDT800TX Mobile Data Transmitter User Manual 40714

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Document ID	40714
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Document Type	User Manual
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Date Submitted	1999-06-07 00:00:00
Date Available	1999-03-30 00:00:00
Creation Date	2001-06-21 08:56:51
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Document Lastmod	2001-06-21 08:56:59
Document Title	40714.pdf
Document Author:	jsoscia

Instrument Specialties Company, Inc. —— World Compliance Center
Hmdwauuqrzriu ( ww'ru' ,, , ,
EXHIBIT C:
DT800 MX919B FSK Modem Manual
mm-urmnwu. Mixed Signal ics
DATA BULLETIN
k MX91 QB 4-Level FSK Modem Data Pump
PRELIMINARY INFORMATION
Features Applications
. 4-Level Root Raised Cosine FSK Modulation . Wireless Data Terminals
- Half Duplex, 4800 to 19.2kbps . Two Way Paging Systems
. Increase Channel Blt Rate/Hz - Digital Radio Systems
. Full Data Packet Framing . Wide Area Wireless Data Broadcasts
- impulse and NRZ Signal Modes . Point to Point Wireless Data Links
. Enhanced Performance in Noisy Conditions
. Error Detection and Error Correction
0 Low Power 3.3V15.0V Operation
MX9198 HOST ”c
RADIO
ANALOGTX
m...
ANALOG Fix
The MX91QB is a low voltage CMOS device wniaining all of the baseband signal processing and Medium Access Control
(MAC) protocol functions required tor a high performance 4-Ievel FSK Wireless Packet Data Modem. It interfaces with the
modem host pic and the radio modulation/demodulation circuits to deliver reliable two-way transfer of the application data
over a wireless link
The MX9195 assembles application data received from the host uG. adds fonrvard error correction (FEC) and error
detection (CRC) inionnation, and interieaves the result for burst-error protection. After automatically adding symbol and
trams sync codewords, the data packet is convened into filtered Mevel analog signals for modulating the radio
transmitter.
ln receive mode, the MX9195 performs the reverse function using the analog signals irom the receiver discriminator.
After error correction and removal oi the packet overhead, the recovered application data is smplied to the host uCt CRC
detected residual uncorrected data errors will be flagged A readout of the SNFI value during receipt of a packet is also
provided
The MX91BB uses data block sizes and PEG/ORG suitable for applications where high speed transfer of data over
narrow-band wireless llnls is required. The device 5 programmable to operate at standard bit rates from a wide range of
Xtai/ciock frequencies.
The MX9195 may be used with a 3.0V to 5.0V power supply and is available in the lollowing package styles:
Eat-pin ssop (mxsr 9303), 24-pin sorc (MX91QBDW), 24~pin FLCC (MXSIQBLH), and 24-pin PDlP (MX91QBP).
SYSTEM
APPLICATION
PROCESSING
CONTENTS
”Section ~ Page
_______—____—___-————————————
1 Block Diagram . ..... .......... .............. ..... 6
2 Signal List . ..... ......... .......... . ................. ...... .. 7
3 Enamel Components ........ .......... . ........ . 8
4 General Description . 9
4.1 Description of Blocks 9
4.1.1 Data Bus Buffers
4.1.2 Address and RIW Decode
4.1.3 Status and Data Quality Register
4.1.4 Command, Mode, and Control Registers
4.1.5 DataBufier...
4.1.6 CRC Generator/Checks
4.1.7 FEC Generator/Checker
4.1 .8 interleavdDe—Interieave Buffer
4.1.9 Frame Sync Detect...
4.1.10 Rx Input Arrp .....
4.1.11 RRC Low Pass Filter.
4.1.12 Tx Output Buffer...
4.1.13 Rx Level/Clock Extraction
4.1.14 Clock Oscillator and Dividers
42 Modem - uC interaction .....
4.3 Binary to Symbol Translation
4.4 Frame Structure ................
4.5 The Programmer‘s View.
4 5 1 Data Block Bufler..
4. 5. 2 Command Register"
4.5.2.1 Command Register 87 AQSC- Acquire Symbol Clock
4.5.2.2 Commam Register BS: AOLEV Acquire Receive Signal Level
4.5.2.3 Command Register 55: CBC
4.5.2.4 Command Register B4:1XIMP-Tx LeveVimpuIse Shape
4.5.2.5 Command Register Bs- Reserved ..
4.5.2.6 Command Register 52 B1 80: TASK
4.5.2.7 NULL: No effect" ....
4.5.2.8 SFSH: Search lor Frame Sync plus Header Block
4.5.2.9 HHB: Head Header Block"
4.5.2.10 FllLB: Read 'imermediate’ or 'Last' Block
4.5.2.11 SFS: Search for Frame Sync
,A. 4.5.2.12 R43: Read 4 Symbols
4.5.2.13 T24S: Transmit 24 Symbo
4.5.2.14 THB: Transmit Header Block
________—_—.___.__———————————
4.5.2.15 TIB: Transmit Intermediaszck 19
452.16 TLB: Transmlt Last Bloch. .....
4.5.2.17 T4S: Transmit 4 Symbols--.
4.5.2.18 RESET: Stop any current-mien
4.5.2.19 Task Timlng
4. 5. 2. 20 HRC Filter Delay
4. 5. 3 Control Register ..
4.5.3.1 Control Register B7, B amiw- Clock Division Ratio
4.5.3.2 Control Register BS, B4: PST 0L - Frame Sync Tolerance to lnexact Matches
4.5.3.3 Control Register as, 32: LEVRES - Level Measurement Modes.......,..........
4.5.3.4 Control Reglster B1, 50: FlLBW » Phase-Locked Loop Bandwidth Modes .
4.5.4 Mode Register .............. ..
4.5.4.1 Mode Register B IROEN- RGOutput Enable.
4.5.4.2 Mode Reg'ster Be: INVSYH - Invert Symbols...........
4.5.4.3 Mode Register 85: TX/Fi—X - TxIRx Mode...
4.5.4.4 Mode Register B4: RXEYE- Show Rx Eye
4.5.4.5 Mode Register 83: PSAVE- Powersave
4.5.4.6 Mode Register 52, E1, Bl] ...............
4.5.5 Status Register ...........
4.5.5.1 Stems Register B . IRQ -Itemlpt Reques
4.5.5.2 Status Register B6: BFREE - Data Block Buffer Free...
4.5.5.3 Status Register B5: IBEM’W - lnterleave Buffer Empty.
4.5.5.4 Status Register E4: DlBOUF - De—Interleave Builer Overflow
4.5.5.5 Stems Register B3: CRCERR - CRC Checksum Error
4.5.5.6 Status Register BZ, B1. en ......
4.5.6 Data Quality Register..
4.6 CRC, PEG, and Intel-leaving
4.6.1 Cyclic Redundancy Code
4.6.1.1 CRC1
4.6.1.2 CRCZ
4.5.1.3 Fomard Error Correction
4.6.1.4 Interleaving
4.7 Transmined Symbol Shape............... .
Application
5.1 Transmit Frame Example.
5.2 Receive Frame Example“
5.3 Clock Extraction and Level Measuremmt Systems.
5 3.1 Supported Types of Systems... .
5 3.2 Ciodt and Level AcquSitlon Profiles with RF Carrier Detect“
5.3.3 Clock and Level Acquisition Prooutle without RF Carrier Detect
5.3.4 Automatic Acquisition Functions.—._.....,...
5.4 AC Coupling ........
5.5 Radio Performance
5.6 Received Slgnal Quality Monitor ............................................................................................................ 39
6 Performance Speclflcatlon ......................................................................................................... 40
" 6.1 Electrical Performance ........... 40
6.1.1 Absolute Maximum Ratings .40
6.1.2 Operating Umiis.......... 440
6.1.3 Operating Chamcterisfius A1
6.1.4 Operating (mannerisms News .42
6.1.5 Timing .42
6.1.6 Typical Bi1 Error Flat .44
6.2 Packaging 45
MX-COM, Inc. Reserves the rigm no change specifications at any time and without notice
Figure
Figures
’_—___—.___—_-—————-———-—
igure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 3:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
A Figure 20:
Figure 21:
Figure 22:
Figure 23;
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
Figure 33:
Block Diagram
Recommended Extemal Components
Typical Modern uc connections" ...
Translation of Binary Data to Filtered 4- Level Symbols In Tx Mode
RRC Filler Frequency Response vs. Bit Rate (including the external RC filter R4/C5) .....
RRC Filter Frequency Response vs. Symbol Rate (indwlng the external RC filter R4ICS).
Over-Air Signal Fon'nat .....
Alternative Frame Structures
Transmit Task Overlapping...
Receive Task Overlapping .....
Transmit Task Timing Diagra
Receive Task Timing Diagram
RRC Low Pass Filter Delay
Ideal 'RXEYE' Signal ......
Typical Data Quality Rea
Input Signal to RRC Filter in Tx Mode for TXIMP
Tx Signal Eye TXIMP = 0
Tx Signal Eye TXIMP = 1
Transmit Frame Example Flowchart, Main Program.
Tx Interrupt Service Routine ...............................
Receive Frame Example Flowchart, Main Program
Rx Interrupt Service routine ................................
Acquisition Sequence Tlrnlng... ..
Effect of AC Cowling on BER (without FEC).
Decayi Tme- AC Coupling .......
Typical Connections between Radio and MX9195
Received Signal Quality Monitor Flowchart....
uC Parallel Interface Timings...
Typical Bit Error Rate With and Without "FEC.
24-pin SOIC Mechanical Outline: Orderas patina. MX91960W.
24-pin SSOP Mechanical Outline: Olderaspen‘na. Ari/(91.9505.
24-pin PLCC Mechanical Outline : Orderasparr no. MXQIQELH.
24-pin PDlP Mechanical Outline: Ode/aspanna. MX9195P.
1 Block Diagram
DATA
QUALITY
REGISTER
STATUS
REGISTER
D0
D1
m REGISTER
COMMAND MODE
REGISTER REGISTER
DATA
BUFFER
pC-ONTHOLIEH
INTERFACE
8 E
D7 cnc
emsmron/
FEC CHECKER
ENCODER/
DECODER
INTEFILEAVE/
DE-INTERIEAVE CT
FRAME
SYNC DETE
0001
Rx LEVEL/CLOCK
I m
Figure 1: Block Diagram
2 Signal List
mm_
output A Wire—OHable' output for connection to the host pC's Interrupt
Request input. When active, this output has a low impedance
pull down to Vss It has a high impedance when inactive.
Pins 2-9 (D7-DO) are B-bit, bi-directional, 3—state
pC interface data lines
mama-1mm
CCCCCC
mmmmmm
(I)
Read. An active low logic level irput used to control the reading
of date from the modern into the host uC.
Write. An active low logic level lnput used to control the writing
of data into the modem from the host uC.
Negative supply (ground).
input Chip Select An active low logic level input to the modern used
to enable a data read or write operation.
m Logic level modem r -ister select input
ML - - ic level modern register select input
Output of the on—chip oscillator
17 XTAL/CLLOCK input input to the on-chip oscillator. for an external Xtal circuit or
clock.
DOC 2 output Connection to the Rx level measurement circuitry. Should be
capacitive coupled to Vss-
Connection to the Rx level measurement circuitry. Should be
capacitive coupled to Vss
EST-mm Tx signal output from the modem.
VBIAS A bias line for the internal circuitry held at Von 12. This pin must
be bypassed to Vss by a capacitor mounted close to the device
pins.
-M input to the Fix int-m amplifier»
“ RXAMPOUT [Mom of the Rx input amplifier
24 Positive supply Levels and voltages are dependent upon this
supply This pin should be bypassed to Vss by a capao'tor
mounted close to the device pins.
3 External Components
vDu
v C1 ’:
rm 1 ”0 FromleFM
RXAMPOUT “2 R‘ Discrininator
D’ 2 lint—n
Lu De 3
g 135 4 V-lAS ToTxFrequency
if D4 5 [mg—Wm"
E De 6 MX919B Doc,
E D2 7 0002
m D1 8 XTAL/CLOCK
_, _
é DO 9 XTA" c7 ca cs 02
,__ H0 10 is)
6 W“ ‘1 XTALJCLOCK
g 3
A0
E“
Recommended External Component Names:
1.
2.
PH“
See Section 4.1 .10.
For best resdts, a crystal owuator design should drive the clock inverter input with signal levels of at least 40% of
VDD. peak to peak. Tuning kirk crystab generally cannot meet this requirement To obtain crystal oscillator design
assistance, corsult your crystal manufacturer.
The values used lor ca and C4 should be suitable for the frequency of the crystal X1. As a guide. values (including
stray capacitance) of 33pF at 1MHz falling to mm: at 10MHz will generally prove suitable. Crystal frequency
tolerances are discussed in Section 45,3.4t
Values CS and 08 should be equal to 750.000 I symbol rate, e.gv
Values CS and C7 should be equal to 50.000/ symbol rate, e.g.
9600 symbols/second m
4 General Description
4.1 Description of Blocks
‘ 1.1.1 Data Bus Buffers
Eight bi-directional 3-state logic level butters between the modem‘s intemel registers and the host uC‘s data bus lines.
4.1.2 Address and Fllllv Decode
This block controls the transfer of data bytes biween the pic and the mode_m's intemal registers according to the state of
the Write and Read Enable inputs (WIT and RD ), the Chip Select input (CS ), and the Register Address inputs
A0 and A1.
The Data Bus Butlers, Address, and RM Decode blocls provide a byte-wide parallel in: interface, which can be
memory-mapped, as shown in Figure 3.
, - Figure 3: Typical Modem “(2 connections
4.1.3 Status and Data Quality Registers
Two, B-bit registers which the us can read, to determine the status of the modern and received data quality.
4.1.4 Command, Mode, and Control Registers
The values written by the rm to these B-bit registers control the operation ol the modern.
4.1.5 Dm Butler
A 12-byte buffer used to hold receive or transmit data to or from the 110.
4.1.6 CHC Generator/Checker
A circuit which generates (in transmit mode) or checls (in receive mode) the Cyclic Redundancy Checksum bits, which
may be included in the transmitted data blocks so the receive modem can detect transmission errors.
4.1.7 FEC Germain/Checker
In transmit mode, this circuit adds Forward Error Correction hits to the transmitted data, resulting in the conversion of
binary data to 4-Ievel symbols In receive mode, this circuit translates received Havel symbols to binary data, using the
FEC information to correct a large proportion of transmission errors.
4.1.8 lmerleaveIDe-Interleave Butter
This circuit Interleaves data symbols within a block before transmission and de-interleaves the received data so that the
FEC system is best able to handle short noise bursts or lades.
4.1.9 Frame Sync Detect
This circuit, which is only active in receive mode, is used to look for the 24-symbol Frame Synchronization pattern that is
trammitted to mark the start of every frame.
4.1.10 Rx Input Amp
This amplifier allows the received signal input to the modem to be set to the optimum level by suitable selection of the
external components R1 and H2. The value at H1 should be calculated to give 0.2 x VDD volts” at the RXAMPOUT pin
' iorareceived'...+3 +3 43 -3 ...‘ sequence.
A capacitor may be placed in series with H1 it ac coupling of the received signal is desired (see Section 5.4). otherwise
the DC level oi the received signal should be adjustd so that the signal at the modem's RXAMPOUT pin is centered
around VBMS (Vpo’2l-
4.1.11 BBC Low Pass Fitter
This filter, which is used in both transmit and receive modes, is a linear-phase ldwpass filter with a 'Ftoot Fiaised Ccsine'
frequency response defined by:
2T
H(t)=1lor 05 f<
lor1‘b f 1+b
2T 5 5 2T
1+b
H(f)=0 for 1 > _2T
Where b—02 T——1—
‘ ' ' “symbolrate
A This frequency response is illustrated in Figure 5 art! Figure 6.
in transmit mode, the 4-ie'vel symbols are passed trough this filter to eliminate the high frequemy components which
would otherwise cause interference into adiacent radio channels. The input applied to the REC Tx fitter may be impulses
or lull-width symbols depending on the setfing of the Command Register TXIMF' bit. See Section 4.7
Figure 4: Translation at Bit-y Dell to Filtered 4—Levei Symbols in Tx Mode
In receive mode, the filter is used to reject HF no'ee and to equalize the received signal to a form suitable for extracting
the 4-tevei symbols The equalization characteristis are determined by the setting of the Command Register TXIMP bit.
dB -15
0 0.1 02 0.3 04 0.5
Frequency / Bit Fiate
Figure 5: BBC Filler Frequency Response vs. Bit Rate (including the external RC litter R4ICS)
o 0.2 0.4 0.6 0.8 1 .0
Frequency / Symbol Rate
Figure 6: RHC Filter Frequency Response vs. Symbol Rate (including the external RC filter RAICS)
4.1.12 Tx Output Buffer
This is a unity gain amplifier used in the transmit mode to buffer the output of the Tx low pass filter. in receive mode, the
input of this butter is connected to Vgus. unless the RXEYE bit of the Control Register is '1', in which case it is connected
to the received signal. When changing from Rx to Tx mode, the input to this buffer will be connected to VBIAS ior B symbol
times whie the RRC filter settles.
Note: The RC low pass filter formed by the extemel components R4 and CS between the TXOUT pin and the input to the
radio‘s frequency modulator forms an imponant pan of the transmit signal littering, These components may form
pen of any DC level-shitting and gain adjustment circuitry. The vaiue used for CS should take into account stray
circuit capacitance, and its ground connection should be positioned to give maximum attenuafion of high frequency
noise imo the modulator.
The signal at the TXOUT pin is centered around VBiAS- it is approximately 0.2 x VDD volts”: for a
continuous ’+3 +3 -3 -3...‘ pattern with TXIMP = 0. For typical Tx Eye Diagrams refer to Section 4.7, Figure 17 and
zigure 18. For typical Fix Eye Diagrams reier to Section 4.5.4.4, Figure 14.
A capacitor may be placed in series with the input to the frequency modulator ii AC coupling is desired. See Section 5.4.
4.1.13 Fix Level/Clock Extraction
These circuits, which operate only in receive mode. derive a symbol rate clock from the received signal and measure the
received signal amplitude and DC offset This information Is then used to extract the received 4-level symbols and also to
rovlde an Input to the recelved Data Quality measuring circuit. The external capacitors 06 and C7 form part of the
.eceived signal level measuring circuit.
The capacitors CB and C7 are driven from a very high impedance source so any measurement of the voltages on the
DOC pins must be made via high Input Impedance (MOS input) voltage followers to avoid disturbance of the level
measurement circuits.
Further details at the level and clock extraction functions are given In Section 5.3.
4.1.14 Clock Oscillator and Dividers
These circuits derive the transmit symbol rate (and the nominal receive symbol rate) by frequency division of a reference
frequency which may be generated by the oft-chip Xtal oscillator or applied from an external source.
Note: It the on-ch'p Xtal oscillator Is to be used. then the extemal components X1, 03, C4, and R3 are required. If an
external clock source is to be used, then it should be connected to the XTAIJCLOCK input pin, the XTAL pin
should be ten unconnected. and X1, 03, Cd, and R3 should not be installed.
4.2 Modem - uC Interaction
In general, data is transmitted over-air in the form of messages. or 'Frames‘, consisting of a 'mee Prearnble‘ followed by
one or more formatted data blocks. The Frame Preamble includes a Frame Synchronization pattern designed to allow the
receian modem to identify the start of a lrame. The following data blocks are constmc‘ted from the ‘raw‘ data using a
combination of CRC (Cyclic Redundancy Checksum) generation, Forward Error Correction coding, and Interteavlng.
Details of the meaage formats handled by the modem are provided in Section 44, Figure 7, and Figure 8.
To reduce the processing load on the associated pc. the Mx919t3 modem has been designed to perform as much of the
computationally lntersive work involved in Frame formatting and de-fonnatting and (when in receive mode) searching for
and synchronizing onto the Frame Preamble. In normal operation. the modem will only require servicing by the uC once
per received or transmitted block.
" 1'heretorc, to transmit a block, the controlling uc needs only to load the unlormotted 'raw‘ binary data into the modem's
Data Block Butler, than instruct the modem to format and transmit that data. The modem will then calculate and add the
CBC hits as required. encode the result as 4-Ievel symbols (with Fomard Error Correction coding), and interleave the
symbols before transmission.
In receive mode, the modern can be instructed to assemble a block's worth of received symbols, de-intedeave the
symbols, translate them to binary, perform Forward Error Correction, and check the resulting CFiC before placing the
received binarydata into the Data Block Bufferforthe pc: to read.
The modem can also handle the transmission and reception of untonnatted data using the T45, T248. and FMS tasks as
described in Sections 4.3 and 45.2. These tasks are nonnalfy used for the transmission of Symbol and Frame
Synchronization sequences. These tasks may also be used for the transmission and reception of special test patterns or
special data formats. In such a case, care should be taken to ensure that the transmitted TXOUT signal contairs enough
level and timing information for the receian modem‘s level and clock extraction circuits to function conectly.
See Section 5.3.
4.3 Binary to Symbol Translation
Although the over~air signal. and therefore the signas at the modern TXOUT and FlXIN pins, consists of 4-Ievel symbols,
the raw data passing between the modem and the uC is in binary form. Translation between binary data and the 4-Ievel
symbols is done in one of two ways, depending on the task being performed.
1. Direct way: (simplest form) - comers between 2 binary bits and a single symbol.
Abourdingly, 1 byte = 4 symbols = 8 bits, and one byte translates to tour symbols for the T48 and R48 tasks and six bytes
translates to twenty-four symbols for the T243 task described in Section 4.5.2.
h MSB LSB
Bus: “III-“fl.-
SYmbols: nan-
sent first sent last
2. FEC way (more complicated) - essentially translates groups of 3 binary bits to pairs of 4-level symbols using 3
Forward Error Correcting coding scheme to! the block oriented tasks THB, TIB, TLB, RHB, and RILB described in Section
4.5.2
4.4 Frame Structure
Figure 7 shows how an over-air message frame may be constructed from a sequence of: a Symbol Sync pattern
_(preamble), e Frame Sync pattern, and one or more ‘Header, 'lnterrnediate' or ‘Lasf' blocks.
I ______ _'_""_"_-'___"'_""_I
I HeaderBlodt Immnmiats Blodt
Byte . l
l 0 I
l g l
quinarydmnerod 3 I
inMXSlsBdamwak 4
memoryoonfimndu 5 I
header. imarmnfibar 5
mmwmm 7 '
tadtbehgemrhd s I
9 I
10
rr l
FEC Trellis Codng / Decoding
(Error Correction)
Irrterleaving I De-interteaving
Symbol Sync: atleastzAsyrrboIaol'...“ a e £...'sequenoe
Figure 7: Over-Alr Signal Format
The Header block is self-contained and includes its own checksurn (CFtC1). it would normally carry information such as
the address of the calling and called parties, the number of following blocks in the frame (it any), and miscellaneous
control information. The number of following blocks (if any) is required to allow the Rx device software to expect the Last
Block and interpret it as a Last Block rather than an lnten'nediete Block. There is no other indirztor to differentiate a Last
Block and an Intermediate Block.
The "Intermediate' block(s) contain onty data, the checksum for all of the data In the '|nterrnediate' and 'Last‘ blocks
(CHCZ) being contained at the end of the 'Last' block.
This arrangement. while efficient in terms of data capacity. may not be optimum lor poor signal-to-noise conditions, since
a reception error in any one oi the ‘Imermediate' or 'Last‘ blocks would invalidate the whole frame. in such conditions,
increased throughput may be obtained by using the 'Header‘ block format for all blocks of the frame, so blocks that are
______—__—_.__..___—————
received correctly can be identified as such, and do not need to be retransmitted. These, and some other possible frame
structures, are shown in Figure 8.
SYMBOL FRAME . _ _
- - SYNC sync HEADER“ BLOCKS
5 SYMBOL FRAME , ‘LAST‘
- - svuc SYNC INTERMEDIATE BLOCKS BLOCK - -
0 SYMBOL FRAME . .
-- SYNC sync lNTEHMEDlATE BLOCKS --
Figure 8: Alternative Frame Structures
The MX91QB performs the entire block formatting and tie-formatting required to convert data between uC binary form and
Over-Air as shown In Figure 7.
4.5 The Programmer‘s View
To the programmer. the modem appears as 4 write only B-bit registers, shadowed by 3 read only registers. The individual
registers are selected by the A0 and A1 chip inputs:
Read from Modern
0 commem
_—
Note: There is a minimum time allowance between acceses of the modem's registers, see Section 6.1.5.
4.5.1 Data Block Butler
This is a 12-byte read/write butler used to transfer data (as opposed to command, status, mode, data quality or control
Intonation) between the modem and the host us.
To the pc, the Data Block Buffer appears as a single B»bit register. The modem ensures that sequential uC reads or
writes to the butler are routed to the correct locations within the buffer.
The uc should only access this buffer when the Status Register BFREE (Buffer Free) bit is ‘1‘.
The butler should only be written to white in Tx mode and read from white in Rx mode. Note that in receive mode, the
modern will function correcfiy even ii the received data is not read from the Data Butler by the ac.
4.5.2 command Reglsler
ertlng to this register tells the modem to perform a specific task as indicated by the TASK bits and modified by the
A030, AQLEV, CBC, and TXlMP bits.
Write to Modern
Data Butler
1 Command Register
Command Register
AQSC AOLEV CRC TlePReserved
Sotin'fl'
When there is no action to perform, the modem will be in an ‘idle' state. If the modem is in transmit mode, the input to the
Tar Rfic filter will be connected to vgms. ln receive mode. the modem will continue to measure the received data quality
and extract symbols from the received signal, supplying them to the de—interleave buffer, otherwise these received
symbols are ignored.
’fi4.5.2.1 Command Register B7: MISC - Acquire Symbol Clock
' 'his bit has no effect in transmit mode.
in receive mode, when a byte with the AQSC bit set to ’i' is written to the Command Register, and TASK is not set to
RESET, it initiates an automatic sequence designed to achieve symbol timing synchronization with the received signal as
quickly as possible. This involves setting the Phase Locked Loop of the received bit timing extraction circuits to its widest
bandwidth. then gradually reducirg the bandwidth as timing synchronization is achieved, until it reaches the 'normal‘ value
set by the FLLBW bits of the Control Register.
Setting this bit to 'D' (or changing it from '1' to '0') has no effect, howev
time a byte written to the Command Register has the A050 bit set to '1'.
The use of the symbol clock acquisition sequence is described in Section 5.3.
4.5.22 Command Register Be: AQLEV - Acquire Receive Signal Levels
This bit has no effect in transmit mode.
In receive mode, when a byte with the AQLEV bit set to '1' is written to the Command Register and TASK is not set to
RESET, it initiates an automatic sequence designed to measure the amplitude and DC offset of the received signal as
rapidiy as possible. This sequence involves setting the measurement circuits to respond quickly at first, then gradually
increasing their response time, thereiore improving the measurement accuracy, until the 'normal‘ value set by the
LEVRES bits of the Control Register is reached.
Setting this bit to '0' (or changing it from ‘1' to '0') has no effect, however; the acquisition sequence will be re—started every
time a byte written to the Command Register has the AOLEV bit set to '1'.
The use of the level measurement acquisition sequence (AQLEV) is described in Section 5.3.
4.5.2.3 Command Ragnar BS: one
This bit allows the user to select between two different initial states of the CRC1 and CRC2 checksum generators. When
this bit is set to ‘0', the CRC generators are initialized to ‘ell ones' as for CCITi' X25 CRC calculations When this bit is set
etc ‘1', the CRC generators are initialized to 'all zeros'. Setting this bit to ‘0’ provides compatibility with the MX919, a prior
nember of the MX919 device family. Other systems may set this bit as required. Note: This bit must be set correctly
every time the Command Register is written to. ‘
4.5.2.4 Command Raider B4: TXIMP - Tx LeveVlmpulse Shape
This bit allow the user to choose between two transmit symbol waveform shapes as described in Section 4.7. Note: This
bit must be set conectiy every time the Command Register is written to.
1.5.25 Command Register BS - Reserved
This blt should always be set to '0'.
4.5.2.6 Command Redmr 52, B1, BO: TASK
Operations such as transmitting or receiving a data block are treated by the modem as 'tasks' and are initiated when the
uC writes a byte to the Command Register with the TASK bits set to anything other than the 'NULL' code.
The uC should not write a task (other than NULL or RESET) to the Command Register or write to or read from the Data
Buffer when the BFREE (Butter Free) bit of the Smtus Register is '0'.
Different tasks apply it receive and haremit modes.
When the modem is in lrarsmit mode, all fasls other than NULL or RESET instruct the modem to transmit data from the
Data Buffer. formatting it as required. The uC should therefore wait unlil the BFREE (Butler Free) bit of the Status
Register is ‘1‘. before writing the data to the Data Block Buffer, then it should write the desired task to the Command
Register. If more than 1 byte needs to be written to the Data Block Buffer. byte number 0 of the block should be written
first
Once the byte containing the desired task has been written to the Command Register, the modem will:
Set the BFREE (Buffer Free) bit of the Status Register to 'O'.
Take the data from the Data Block Butler as quickly as it can - transferring it to the lnterteave Butler for eventual
,. transmission. This operation will start immediatery if the modem is 'idle' (i.e. not transmitting data from a previous
task), otherwise it will be delayed until there is sufficient room in the lnteneave Buffer.
the acquisition sequence will be restarted every
Once all or the data has been transferred fromme Data Block Butter, the modern will set the BFHEE and IRO bite at
the Status Register to 't'. (causing the chip E output to go low if the lRQEN bit of the Mode Register has been set
to '1‘) to tell the pC that it may write new data and the next task to the modern.
F This lets the NC write the next task and its associem data to the modern while the modem is still transmitting the data
from its previous task.
Datairom uCto Block Butter - Task 1 data
Task lrom tic in Command |
Register lv
BFREE Bit 01 Status Register
iRQ Blt of Status Register
m Output (IROEN = '1‘)
TXOUT Signal
Figure 9: Transmit Task Overlapping
When the modem “5 in receive mode, the pC shout wait until the BFREE bit of the Status Register is ‘t‘, then write the
desired task to the Command Register.
Once the byte containing the desired task has beenwritten to the Command Register. the modem will:
Set the BFREE bit of the Status Register to ‘0',
Wait until enough received symbols are in them-interleave Butter.
Decode them as needed and transfer the restfitg binary data to the Data Block Buffer
Then the modem will set the BFFlEE and lFtOhits oi the Status Register to '1‘, (causing the m output to 90 low if
the IRQEN bit of the Mode Register has beenset to '1') to tell the 11C that it may read from the Date Block Buffer and
write the next task to the modem. If more than byte is contained in the bitter. byte number 0 of the data will be
read out first.
in this way. the us can read data and write a newuk to the modem while the received symbols needed for this new task
are being received and stored in the De-interteave Butler.
RXlN Signal
W Output amen = ‘t‘)
IRQ Bit at Status Register I i
BFREE Bit of Slat]; Register I
Tesktrumuc t.
toC dFl . r : Tnkt : Taekz
Datatrom Block Bufierto uC _Task 1 data
Figure 1th Receive Task Overlapping
Detailed timings tor the various tasks are provide ‘nFigure 11 and Figure 12.
MXMQB Modem Tasks:
Receive Mode Transmit Mode
0 n“ NULL
0 n_
n_
“I... RiLB Read intermediate orLast Block
[Inla—
n“.- was Read 4 symbols T4S Transmit 4 symbols
“n“ NULL NULL
IIII_
4.5.2.7 NULL: No eflect
This 'task' is provided so an AQSC or AQLEV command can be initiated without loading a new task.
4.5.2.5 SFSH: Search tor Frame Sync plus Header Block
NULL
T24S
THE
Transmit 24 symbols
Transmit Header Block
Transmit intermediate Block
Tl
TL Transmit Last Block
RESET Cancei any current action
This task causes the modem to search the received signal for a valid Eat-symbol Frame Sync sequence followed by
Header Block which has a correct CRct checksum.
The task continues until a valid Frame Sync plus Header Block has been found.
The search consists of two stages:
First the modem will attempt to match the incoming symbols against the 24-symbol Frame Synchronization pattern to
within the tolerance defined by the FSTOL bits of the Control Register.
Once a match has been found, the modern will read in the next 66 symbols as if they were a 'Header‘ block, decoding
the symbols and checking the CRCt checksum. If this is incorrect, the modern will resume the search, looking for a
fresh Frame Sync pattern.
~— It the received CROt is correct, the 10 decoded data bytes will be placed into the Dam Block Butter. the BFREE and
lRQ bits of the Status Register will be set to '1' and the CRCERR bit cleared to ‘0'.
Once detecting that the BFREE bit oi the Status Register has gone to '1', the uc shoUId read the 10 bytes from the Data
Block Buffer and then write the next task to the modem’s Command Register.
4.5.2.9 HHE: Head Header Block
This task causes the modem to read the next 66 symbols as a 'Headet‘ Block, decoding them, placing the resulting 10
date bytes and the 2 received CRC1 bytes into the Data Block Buffer, and setting the BFREE and lRQ bits of the Status
Register to '1'. When the task is complete, It indicates that the no may read the data item the Data Block Butter and write
the next task to the modem's Command Register.
The CRCERR bit of the Status Register will be set to '1' or ‘0' depending on the validity of the received CRC1 checksum
bytes.
4.52.10 RILB: Reed 'lmermedllie’ or 'Lest‘ Block
This task causes the modem to read the next 66 symbols as an 'Interrnediate‘ or ‘Last‘ block (the uC should be able to tell
from the 'Header‘ block how many blocks are in the frame and when to expect the 'Last' block).
In each case, it will decode the 66 symbols and place the resulting 12 bytes into the Data Block Buffer, setting the BFREE
and IRQ bits of the Status Register to '1' when the task is complete.
If an 'lntennediate' block is received, then the 110 should read out all 12 bytes from the Data Block Buffer and ignore the
CRCERR bit of the Status Register, for a ‘Last‘ block the uC need only read the first 8 bytes truth the Data Block Butter,
and the CRCERR bit in the Status Register will reflect the validity oi the received CR02 checksum.
4.5.2.11 SPS: Search tor Frame Sync
This task causes the modem to search the received signal for a 24-symbol sequence which matches the Frame
Synchronization pattern to within the tolerance defined by the FSTOL bits oi the Mode Register.
, When a match is found the modem will set the BFREE and lRQ hits of the Status Register to '1' to indicate to the no that it
:hould write the next task to the Command Register.
4.5.2.12 HAS: Read a Symbols
This task causes the modem to read the next 4 symbols and translate them directly (without de—interleaving or FEC) to an
8-bit byte which placed into the Data Block Butler. The BFREE and IRO bits of the Status Register are then set to ‘1 ' to
' T’hdicate that the pit? may read the data byte from the Data Block Butler and write the next task to the Command Register.
This task is intended for special tests and channel monitoring - perhaps preceded by a SFS task.
Note: It is possible to construct message ton-nets, which do not rely on the block formatting of the THB, TIE, and TLB
tasks. This can be accomplished by using T4S or T24S tasks to transmit and R48 to receive the user’s data. One should
be aware, that the receive level and timing measurement circuits need to see a reasonably 'random' distribution at all four
possible symbols in the received signal to operate correctly Accordingly, binary data may benefit from scrambling beiore
transmission If it a not reasonably 'random' to start with.
45213 T245: Transmit 24 Symbols
This task, which is intended to facilitate the transmission at Symbol and Frame Sync patterns as well as special test
sequences, takes 5 bytes of data from the Data Block Buffer and transmits them as 24 4-level symbols without any CR0
or FEC.
Byte O of the Data Block Butler is sent first, byte 5 last.
Once the modem has read the data bytes from the Data Block Buffer, the BFREE and ”RC bits of the Status Register will
be set to '1', indicating to the at: that it may write the data and command byte tor the next task to the modem.
The tabies below show what data needs to be written to the Data Block Buffer to transmit the MXQ‘lSB Symbol and Frame
Sync sequences:
Symbol Sync' Values written to Data Block Butter
11110101
11110101
11110101
" 7 11110101
11110101
11110101
m Hex
: nonom
01001001
4.52.14 THE: Transmit Header Block
This task films 10 bytes of data (Address and Control) from the Data Block Buffer, calculates and appends the 2-byte
CRC1 checksum, translates the result to 4—ievei symbols (with FEC), interieaves the symbols, and transmits the result as
a lonnatted Header“ Block
Once the modem has read the data bytes from the Data Block Butler. the BFREE and iRQ bits 01 the Status Register will
be set to '1't
4.52.15 TIE: Transmit Intermediate Block
This task takes 12 bytes of data lrom the Data Block Butter. Lpdates the 4-byte CRCZ checksum tor inclusion in the “Last‘
,, block, translates the 12 data bytes to 4—ievel symbols (with PEG), interleaves the symbols, and transmits the result as a
formatted intermediate‘ Block
Once the modem has read the data bytes from the Data Block Buffer, the BFREE and lRQ bits of the Status Register will
be set to '1'.
4.52.16 TLB: Transmit Last Block
This task takes 6 bytes oi dam from the Data Block Buffer, updates and appends the 4~t7yte oncz checksum, translates
the resulting 12 bytes to 4-Ievel symbols (with PEG), interleaves the symbols, and transmits the result as a formatted 'Last'
’ “took.
Once the modem has read the data bytes from the Data Block Buffer, the BFREE and lRO bits of the Status Register will
be set to '1'.
4.5.2." HS: Transmit A Symbols
This command is similar to 7245 but takes onty one byte from the Data Block Butter, transmitting it as four 4-level
symbols.
4.52.18 RESET: Stop only current action
This ‘ask‘ takes effect immediately. and terminates any current action (task, AQSC or AQLEV) the modem may be
performing and sets the BFREE bit of the Status Register to '1', without sean the [no hit. it should be used when VDD is
applied, to set the modem into a known state.
Note: Due to delays in the transmit fitter, it will take several syn'bol times for any change to appear at the TXOUT pin.
4.52.19 Task Timing
The following table and figures describe the duration of tasks and timing sequences for Tx and Fix operation.
1,——
Task Time
r (symbol times)
t1 Modem in idle state. Time from writing first task to application of first Any 1 to 2
flsmit bit to Tx FtFlC filter -
ta Time from application of first synbol oi the task to the T): RRC T243 5
liner until BFREE goes to a logic ‘1' THB/TlB/TLB 15
T48 ' 0
lg Time to transmit all symbols of the task T243 24
" THB/l'IB/T LB 66
T48 4 l
t4 Max time allowed from BFREE going to a logic '1' (high) for next T248 15
task (and data) to be written to modern THB/TlB/TLB 49
be 3
is. “me to receive all symbols of task SFS 24 (minimum)
SFSH 90 (minimum)
RHB/RILB 56
MS 4
is Maximum time between first symbol of task entering the delntefleave SFS 21
circuit and the task being written to modem SFSH 21
RHB/FlILB 49
R45 3
£7 Maximum time from the last bit at the task entering the de interleave Any 1
cirwii to BFREE Qing to a logic '1' (high)
Data to Data Block Buffer
Task lo Command Register
IBEMF’TY Bil
BFREE Bit
Symbols w RRC Fitter I _-Mm
Modem ow W
Figure 11: Transmit Task Timing Diagram
Modemnxmpm M
Syn'bols io Deimerleave for Task 1 for Task 2
Cirnufl
Data from Data Block Bufler
Task to Command Register
BFREE Ell
Figure 12: Receive Task Timing Diagram
4.52.20 RHC Filler Daily
The previous task timing figures are based on the signal at the input to the HRC filler (in transmit mode) or the input to the
de—interleave buffer (in receive mode). There is an additional delay of about 8 symbol times through to the RRC filter in
both transmit and receive modes as illustrated below:
_l'i____—__
Delayfmme mpg Tx Symbol m RRC Filter
synod to'i'xOUT
response.
TxSymbolatTXOUTpin/Rxsymbolirmn FMmcrim’nator
Dollyrrom Fix mm
(1mm FMdlfl'Imlrflmr)
romwemmln
m M'- nx symbol to De-Imerleave Buller | |
h—f—fi—i—i—i—i—l—i—i—i—i—i—P—r—i—i—f—i—i
Sfllifl-llmes
Figure 13: BBC Low Puss Film Delay
4.5.3 Control Register
This a-bit write-onty register controls the modern's symbol rate. the response times of the receive clock extraction. signal
level measurement circuits. and the Frame Sync pattern recognition tolerance to inexact matches.
Control Register
FSTOL LEVRES PLLBW
4.5.3.1 control Reglswr 57, BS: CKDIV - Clock Division Ratio
These bits control a frequency divider driven from the clock signal present at the XTAL pin, thereiore determining the
nominal symbol rate. Because each symbol represents two bits, bit rates are 2x the symbol rates. The table below shows
how symbol rates of 24001480019600 symbols/sec (4800/9600/19200bps) may be obtained from common Xtal
frequencies:
Xtal Frequency (MHz)
2.4575 4.9152
flfl Division Ratio: Symbol Rate (symbols/sec) I Bit Rate (bps)
xraiF rs mbolFlate
mum—_—
fl--_—__
-fl____
--E__— 2400/4800
Note: Device operation is not guaranteed below 2400 symbols/sec (4800bps) or above 9500 symbols/sec
(1 92011395).
4.5.3.2 Control Register 85, B4: FSTOL - Frame Sync Tolerance to Inexacf Matches
These two bits have no effect in transmit mode. In receive mode, they define the maximum number of mismatches
allowed during a search for the Frame Sync pattern:
IEE_
“II-—
um—
--—
-_
Note: A single ‘rnisrnatch' is defined as the difference between two adjacent synboi levels, thus it the symbol '+1' were
expected, then received symbol values of "+3' and ‘-1‘ would count as 1 mismatch. a received symbol value of '-3'
would count 5 2 mismatches. A setting of ‘4 mismatches' is recommended for normal use.
4.5.3.3 Comml Register 83, 52: LEVRES - Level Measurement Modes
These two bits have no effect in transmit mode. In receive mode they set the 'normal' or 'steady state‘ operating mode of
the Rx signal amplitude and DC oflset measuring and tracking circuits. These circuits analyze the Fix signal envelope and
charge the D001 and 0002 capacitors to 'store‘ signal maximum and minimum references that are used in the data
meption process. This setting is temporarily overridden during the automatic sequencing triggered by an AQLEV
command when level is initially being acquired as described in Section 5.3.
“n Lossy Peak Detect
I... Slow Peak Detect
f‘ i normal use the LEVFtES bits should be set to '0 1' (Level Track). The other modes are Intended ior special purposes,
tor device testing, or are invoked automatically during an AQLEV sequence.
In 'Slow Peak Detect“ modes, the positive and negative excursiors oi the received signal (alter filtering) are measured by
peak rectifiers driving the D001 and D002 capacitors to establish the amplitude of the signal and any DC oflset with
regards to Vms. This mode provides good overall performance, particulariy when acquiring level intern-ration at the start
of a received message, but does not work as well with certain long sequences oi repeated data byte values. It is also
susceptible to tame amplitude noise spikes, which can be caused by deep fades.
The ‘Lossy Peak Detect mode is similar to ‘Slow Peak Detect‘ but the capacitor discharge time constant is much shorter
so this mode is not suitable tor normal data reception and is only used within part of the automatic AQLEV acquisition
sequence.
In lLevel Track' mode the DOC capacitor voltages are slowly adjusted by the MX91QB in such a way as to minimize the
average errors seen in the received signal. This mode provides the best overall performance, being much more accurate
than ‘Slow Peak Detect‘ when receiving large amplitude noise spikes on long sequences of repeated data byte values. it
does, however, depend on the measured levels and timing being approximately correct. if either of these is significantly
wrong then the correction algorithm used by the ‘Level Track“ mode can actually drive the voltages on the DOC capacitors
away from their optimum levels. For this reason. the automatic AQLEV acquisition sequence (see Section 5.3) forces the
level measuring circuits into 'Slow Peak Detect mode until a Frame Sync pattern has been lound.
4.5.3.4 control Register B1, BO: PLLBW - PmLoclwd Loop Bandwidth Modes
These two bits have no ettect tn transmit mode. In receive mode, they set the 'normal' or ‘steady state' bandwidth of the
Rx clock extraction Phase Locked Loop circuit. The PLL circuit synchronizes itsell with the fix Signal to develop a local
clock signal used in the data clock recovery process. This setting will be temporarily overridden during the automatic
sequencing of an AQSC command when Rx clock extraction circuits are initially being trained as described in Section 5.3.
mm—
I’ll!—
un—
II_
II_
The normal setting tor the PLLBW bits should be ‘Medium Bandwidth' when the received symbol rate and the frequency of
the receiving modem‘s crystal are both within tiOOppm of nominal, except at the start of a symbol clock acquisition
sequence (AQSC) when Wde Bandwidth‘ should be selected as described in Section 5.3
lithe received symbol rate and the crystal frequency are both within 120mm of nominal then selection of the lNarrow
Bandwidth' setting will provide better performance especially through fades or noise bursts which may otherwise pull the
PLL away from its optimum timing. In this case however: it is recommended that the PLLBW bits only be set to ‘Narrow
Bomidth' alter the modem has been running in Medium Bandwidth' mode for about 200 symbol times to ensure
acwrate lock has first been achieved.
The 'Hold' setting disables the ieedtack loop of the PLL which continues to run at a rate determined only by the acmal
crystal frequency and the setting of the Control Register CKDIV bits, not the PLL's operating frequency immediately prior
to the 'Hold' settling.
4.5.4 Mode ”Her
The contents of this obit write only register control the basic operating modes oi the modem:
4.5.4.1 Mode Register 87: IRQEN - moment Enable
When this bit is set to '1', the WG- chip output pin is pulled low (Vss) given the IRQ bit or the Status Register is a '1'.
4.5.4.2 Mode Register as: INVSYM - Invert Symbols
This bit controls the polarity of the transmitted and received symbol voltages.
BS Symbol Signal at TXOUT Signal at RXAMPOUT
o -.3-
'-3' Below vans Above vans
“——
Note: Be must be normally set to the same value in Tx and Fix devices for suoeesslul operation.
4.5.4.3 Mode Register 35: WW -TWRX Mode
Setting this bit to '1' places the modem into the Transmit mode, clearing it to ‘0‘ puts the modem into the Receive mode.
hNote: Changing between receive and transmit modes will cancel any current task.
4.5.4.4 Mode Register 94: nxrsvs - Show Rx Eye _
This bit should normally be set to '0'. Setting it to '1' when the modem is in receive mode configures the modem for a
special test mode. in which the input of the Tx output butter is connected to the Fix Symbol/Clock extraction circuit at a
point which carries the equalized reoeive signal. This may be monitored with an oscilloscope (at the TXOUT pin itself), to
assess the quaflty oi the complete radio channel including the Tx and Rx modem filters, the Tx modulator and the Rx IF
filters, and FM demodulator.
This mode is provided because observation of the direct discriminator output at a root raised cosine Tx filtered signal
(before Rx equalization) is not very recognizable so it is generally not useful.
The resulting eye diagram (for reasonably random data) should ideally be as shown In the following Figure 14, with 4
distinct and equally spaced level crossing points.
Figure 14: ideal 'RXEYE' Signal
4.5.4.5 Mode Register 83: PSAVE - Powersave
When this bit is a ‘1‘. the modem will be in a ‘powersave' mode in which the internal filters, the Rx Symbol and Clock
extraction circuits, and the Tx output buffer will be disabled. The TXOUT pin will be connected to VBlAs through a high
value Internal resistance. The Xtel clock oscillator. Rx input amplifier and the ac hterfece iogic will continue to operate.
Setting the PSAVE bit to ‘0’ restores power to all of the chip circuitry
Note: The internal filters. and therefore the TXOUT pin in transmit mode, will take approximamly 20 symbol-times to settle
after the PSAVE bit has gone from '1' to ‘O’.
,. 4.5.4.6 Mode Register 52, B1. BO
These bits should be set to '000‘.
4.5.5 Statue Register
This register may be read by the pic to determine the current state of the modem.
Status Register
4.55.1 Status Register B7: mo - Interrupt Request
This bit is setto '1' by:
The Status Register BFREE bit going from '0' to '1', unless this is caused by a RESET task or by a change to the
Mode Register TXIR_X orPSAVE his
or The Status Register IBEMPTY bit going from 'D‘ to '1', unles this is caused by a RESET task or by changing the
Mode Register mfi‘x or PSAVE bits.
or The Status Register DIBOVF bit going from '0' to '1'.
A The IRQ bit is cleared to ‘0‘ immediately after a read of the Status Register.
If the IRQEN bit or the Mode Register is -1', then the chip Fifi output will be pulled low (vss) when the lRQ bit is set to '1'.
and will go high impedance when the Status Register Is read.
4.5.5.2 Status Register 86: BFREE - Data Block Butter Free
This bit reflects the availability of the Data Block Butler and is cleared to 'U when a task other than NULL or RESET is
written to the Command Register.
f n transmit mode. the BFREE bit will be set to '1' (also setting the Status Register lRQ bit to '1') by the modem when the
modem is ready for the uC to write new data to the Data Block Buffer and the next task to the Command Register.
in receive mode, the BFREE bit is set to '1' (also setting the Status Register IRQ bit to ‘1') by the modem when it has
completed a task and any data associated with that task has been placed into the Data Block Butter. The uC may then
read that data and write the next task to the Command Register.
The BFREE bit is also set to '1' - but without setting the lRQ bit - by a RESET task or when the Mode Register TXIF-l—x or
PSAVE bits are changed.
4.5.5.3 SM!!! Register 35: IBEMPTY - Interieeve Butler Empty
ln transmit mode, this hit will be set to '1‘ - also setting the me hit - when less than two symbols remain in the interleave
Butler. Any transmit task written to the modern after this bit goes to '1‘ will be too late to avoid a gap in the transmit output
signal.
The bit is also set to '1‘ by a RESET task or by a change of the Mode Register TX/W or PSAVE bits. but in these cases
the IRO bit will not be set.
The bit is cleared to '0' within one symbol time after a task other than NULL or RESET is written to the Command
Register.
Note: When the modem is in transmit mode and the Interleave Butler is empty, a mid-level (halfway between '+t' and '-1')
signal will be sent to the RRC filter.
in receive mode this bit will be '0’.
4.5.5.4 Status Register B4: DIBDVF - De-lnterleave Buffer Overflow
In receive mode this bit will be set to '1' - also setting the IRQ bit - when a RHB, RILB or R43 task is written to the
Command Register too late to allow continuous reception.
F The bit is cleared to '0‘ ignediately alter reading the Status Register, by writing a RESET task to the Command Register
>r by changing the ”(X/RX or PSAVE bits of the Mode Register.
in transmit mode this bit will be ’O‘.
4.5.5.5 Status Register 53: CRCERR - CRC Checkeum Error
In receive mode. this bit will be Lpdated at the end oi a SFSH, RHB or RlLB task to reflect the result of the receive CRC
creek. '0' indicates that the CRC was received correctly, '1' indicates an error.
Note: This bit should be ignored when an intermediate“ block (which does not have an integral ORG) is received.
The bit is cleared to '0‘ by a RESET task or by changing the TX/R7 , or PSAVE bis oi the Mode Register. in transmit
mode this bit is 'D'.
4.5.5.6 Status Register 52, B1 , BO
These bits are reserved tor future use.
4.5.6 Data Quality Register
in receive mode. the MX91QB continually measures the 'quality‘ of the received signal, by comparing the actual received
wavei‘orm over the previous 64 symbol times against an internally generated 'ideal' 4-ievel FSK baseband signal.
The result is placed into bits 3-7 of the Data Quality Register for the pic to read at any time, bits 0-2 being always set to ‘0’.
Figure 15 shows how the value (0-255) read irorn the Data Quality Register varies with received signal-to—noise ratio:
SIN dB (noise In 2 x symbol-file bandwidth)
Figure 15: Typical Data Quality Heading vs SIN
The Data Quality readings are only valid when the modern has successfully acquired signal level and timing lock for at
least 64 symbol times. it is invalid when an AQSC or AQLEV sequence is being perlorrned or when the LEVRES setting
is 'I.ossy Peak Detect. A low reading will be obtained it the PLLBW bits are set to Wide“ or it the received signal
waveform is distorted in any significant way.
Section 5.6 describes how monitoring the Data Quality reading can help improve the overall system performance in some
applications.
4.6 CRC, PEG and lnterleaving
”4.6.1 Cyclic Redundancy Codes
4.6.1.1 CRC1
This is a sixteen-bit one check code contained in bytes 10 and 11 of the Header Block, which provides error detection
coverage for the Header Block of a message. it is calculated by the modem trot-n the first 80 bits of the Header Block
(Bytes 0 to 9 inclusive) using the generator polynomial:
xw+x12+x5+1
4.6.1.2 CHC2
This b a thirty-two—bit CFlC check code contained in bytes 5 to 11 oi the ‘Last’ Block, which provides error detection
coverage torthe combined Intermediate Blocks and Last Block of a message. It is calculated by the modem from all oi
the data and pad bytes in the Intermediate Elects and in the first 8 bytes ot the Last Block using the generator polynomial:
x32+fie+f3+x22+xw+xm+fl1+x1°+x8+x7+x5+fl+xz+>0+1
Note: In receive mode the CRCZ ehedtsum circuits are initialized on completion of any task other than NULL or FiILB. In
transt mode the CRCZ checksum circuits are initialized on completion of any task other than NULL, 118, or TLB.
Command Fiegister bit as (CEO) allows the user to select between two different terms of the CRC1 and CHCZ
checksums. When this bit is set to ‘O‘, the CRC generators are initialized to 'all ones' for calculations such as
CCITT X25 CBC. When this blt h set to '1', the CRC generators are initialized to 'all zeros'.
4.6.1.3 Forward Error Correction
In transmit mode. the stt SE uses a Trell‘s Encoder to translate the 96 bits (12 bytes) of a Header, ‘intermediate' or
'Last‘ Block into a ss-symbol (132 bits) sequence which includes FEC Information.
in receive mode. the MXQtQB decodes the received 66 symbols of a block into 96 bits of binary data using a “Soft
Decision' Viterbi algorithm to perform decoding and error correction.
fl 4.3.1.4 imaging
The 66 symbols of a Header, ‘Intennediate' or 'Last' block are interleaved by the modern betore transmission to provide
promotion against the eltects of noise bursts and short fades.
in receive mode. the MX9195 de-interieaves the received symbols prior to decoding.
4.7 Transmitted Symbol Shape
Bit 4 of the Command Register (T XIMP) selects the transmit beseband signal and the receive signal equalization as
VAfoIIaws:
the “IXIMP bit ls '0', then the transmit baseband signal is generated by feeding full-symbol—time—width 4-Ieval symbols
into the RRC Iowpass filter. The receive signal equalization is optimized tennis type of signal. With this setting, the
MX91 QB is compatible with the MX919A devices, another member of the MX919 device family.
If the TXIMP bit Is set to ‘1 ,' impulses. rather than tuli-symboI-fime—widtl'i symbols are fed into the REC filter when In TX
mode, and the receive signal equalization is suitably adjusted In RX mode.
TXIMP = 0 TXIMP = 1
+3 +3
+1 +1
.1 -1
<3 -3
1 symbol 1 symbol
time time
Flgure 16: Input Signal to RRC Filter In Tx Mode for TXIMP = 0 and 1
Figure 17: “hr Signal Eye TXIMP = o
Flgure 18: Tx Signal Eye TXlMP = 1
None: Setting TXlMP to '1‘ affects the Tx outpul signal level as shown in Section 6.1 .3 and the table below.
TXIMP
Nominal Voltage difference belween continuous '+3' and 0.157VDD 0157qu
ccnfinuougflymbol outputs.
! Nomlnal Vp.p for continuous 33 +3 -3 -3...' symbol panem. 0,20VDD 0.22VDD
5 Application
YH5.1 Transmit Frame Example
the operations needed to transmit a single Frame consisting of Symbol and Frame Sync sequences, and one each
Header, lnten-nediate and Last blocks are provided below:
1.
2.
10.
11.
12.
Ensure that the Control Register has been loaded with a suitable CKDIV value, that the lRQEN and TXIFTX bits of the
Mode Register are '1', the RXEYE and PSAVE bits are '0". and the lNVSYM bit is set appropriately.
Read the Status Register to ensure that the BFREE bit is ‘1‘, then write 6 Symbol Sync bytes (a preamble) to the
Data Block Butler and a T24S task to the Command Register.
Wait for an interrupt from the modem, read the Status Register; the lRQ and BFREE bits should be '1' and the
IBEMPTY bit should be '0‘.
Write 6 byte Frame Sync to the Data Block Butler and a T24S task to the Command Register.
Wait tor an interrupt from the modem, read the Status Register, the lRQ and BFREE bits should be '1' and the
IBEMPTY bit should be '0'.
Write to Header Block bytes to the Data Block Butter and a THB task to the Command Register.
Wait for an interrupt from the modem, read the Status Register, the IRQ and BFREE bits should be '1' and the
IBEMPTY hit should be 'O'.
Write 12 intermediate Block bytes to the Data Block Buffer and e TIB task to the Command Register.
Wait for an interrupt from the modem, read the Status Register; the mo and BFREE bits should be '1‘ and the
IBEMPTY bit should be '0'.
Write 8 Last Block bytes to the Data Block Butter and a TLB task to the Command Register.
Wait for an interrupt from the modem, read the Status Register; the mo and BFREE bits should be '1‘ and the
IBEMPTY bit should be '0'.
Wait for another interrupt from the modem, read the Status Register; the IRQ, BFREE and IBEMPTY bis should be
'1',
Note: The final symbol oi the frame will start to appear approximately 2 symbol times after the Status Register iBEMPTY
bit goes to '1'; a further 16 symbol times should be allowed for the symbol to pass oorrpletely through the REC
filter.
Figure 19 and Figure 20 illustrate the host at: routines needed to send a single Frame consisting oi Symbol and Frame
Sync patterns, a Header block, and any number of Intermediate blocks and one Last Block. it is assumed that the T:
Intempt Service Routine Figure 20 is called when the MX9195 fid output line goes low.
Ensure that the Control Register
Set [10 variable 'IBLOCKS'
has been loaded with
a suitable CKDlV value to the number oi lntennerfiale blocks
to be transmitted
Ensure that the Mode Reg‘mar
mmwewxsww-
the TX/RX bit is ‘1'.
and the INVSYM bit is set appropriately
Set the Mode Register IFiQEN bitlo ‘1'
Wriw e RESET task to the Command Reg'ster
Enable uC's MXBiQB Tx interrupt Service Routine
Read the Status Regiflsr
Write 6 bytes 01 Symbol Sync
pattern tothe Data Butter
BFREE bit = 1 7 5°
Write a TEAS task to the Command Register
No
Nola: during this timathe uC may
peflorm Other functions as the
pC variable 'STATE' il updated
by the interrupt service routine
Figure 19: Transmit Frame Example Flowchart, Main Program
Nuts
1. The RESET command in Figure 19 and the practice of disabling the MXQtQB’s m output when not needed are not
essential but can eliminate problems during debugging and it errors occur in operation
2. The CRC and TXIMP bits should be set appropriately every time a byte ‘5 written to the Command Register.
vamaflcwmummmmmm
mmmmuwmmm
m wsmmmw mm
mmsympmm rusux
1; Fianwsyncmunbdnglmmod
mmmmwtmm
2 Hum “mama“
anTnm-mmmmama flux
a: mmmmm
wan-mum.
4: ' bra-dam.
flrimmilmtuvdlhlBEWTYbil-d.
RETURN
(mwmsam)
WmaSanm-Sym
mama-um
Mun-726mm
WWW“
Sawm-It'STATE‘wQ
Mas mlmunlmDmm
mmamugkm
Figure 20: Tx InIL-rrupt Service Routine
5.2 Reoeive Frame Example
The operations needed to receive a single Frame consistlng of Symbol and Frame Sync sequences and one each
Header, Intermediate and Last blocks are shown below;
A4
Snitffll“
>‘.°’
Si
10.
11.
124
Ensure that the Control Register has been loaded with Enable CKDIV, FSTOL, LEVRES and Pu.BW values, and
that the IRQEN bit of the Mode Register is '1‘, the TX/RX PSAVE, and RXEYE bits are '0‘, and the lNVSYM bit is set
appropriately.
Wait until the received carrier has been present for at least 8 symbol times (see Section 5.3).
Read the Status Register to ensure that the BFREE bit is '1'.
Write a byte containing a SFSH task and with the A030 and AQLEV bits set to '1' to the Command Register.
Wait for an interrupt from the modem, read the Status Register: the IRQ and BFREE bits should be '1' and the
CRCERR and DIBOVF blts should he ‘0‘.
Check that the CRCEFIR bit of the Status Register is '0' and read 10 Header Block bytes from the Data Block Buffer,
Write a RILE task to the Command Register.
Wait for an intempt from the modern, read the Status Register; the IRQ and BFREE bite should be '1' and the
DIBOVF bit ‘0'.
Read 12 Intermediate Block bytes from the Data Block Buffer
Write a RlLB task to the Command Register.
Wait for an Interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the
DIBOVF bit '0'.
Check that the CRCERR bit of the Status Register is ‘0’ and read the 8 Last Block bytes from Data Butler.
Figure 21 and Figure 22 illustrate the host uC routines needed to receive a single Frame consisting of Symbol and Frame
Sync patterns, a Header Block, any number of Intermediate blocks and one Last block. It is assumed that the Rx Interrupt
Service Routine Figure 22 is called when the MX91QB's m output goes low.
Ensurn manhs Control thbm
has baa-i waded wilh suihbh
(IKDiVv FSTOL. LEVRES anfl PLLEW villi“
Wufihmfivedmnifirhmbunpnnnl
hrulhunnmbonius
Sdevur'nbb‘STATE‘wO
S‘H’EMedeRegimrIRQENbiHo'f
Enlbia pC‘s mxms Rx
Ensure Mme Made R ‘ XHQEN,
FSAVE, RXEYE and bin are ‘0‘.
911de INVSVMbitixutwpn-ipriabiy
WriteuFlESETMhiwaomnw-d Rag'sfier
5.51me Mr I
BFHEE bit-1 7
WmelSFSHMbhcolmnfll-iw
mmmscmmwmmb'r
Newmringmisfimomepcnflj
mrm,umfl
pCvariabh'STATE'iswdaM
whim-"um service lamina
Figure 21: Receive Frame Example Flawcilart, Main Program
Notes
1. The RESET command in Figure 21 and the practice of disabiing me MX91QB‘s fifi outpm when not needed are not
menfial but can eliminate problems during debugging and if errors owur in operation.
2. The CEO and TXIMP bits should be set appropriately every time a byte is written to the Command Register.
anixcvanafle'sflTE‘menirym mm mm-
mmwmxsisa'sm:
DzFrlmISymilshunnmwfizsd
lndHlnhrbioderewsd.
MSIMR-m ludmddamdbadeLBluk
lzlrimmdusbiodhasbemuuivad.
MafimmanflloadRiLBusk.
21WMMMMM
N" "ENE" madman-mama
(mumsmam
CRCEHH M I 0 7
m G
f m
Human-"manna MioMrmm
mammogram mmmmrm Na
mum-mum mieanLBhskmlh!
019qu Commlmww
555mm
WWW sqpcm'iswcxs
Iii-m mmmmmmae
maximum
in m
N“ mousse? e
S-qu-hfi'S'TKT'E‘hZ Setquar'nbie'STATElnfl
RETURN
(Em!)
Figure 2: Fix Interrupt Service routine
_. Nona: This routine assumes that the number of Intermediate blocks in the Frame is contained within me Header Block
Data.
5.3 Clock Extraction and Level Measurement Systems
5.3.1 Supported Types of Systems
_ The MXBtBB is intended for use in systems where:
i. The Symbol Sync pattem is tmnsmitted immediame on start-up of the transmitter, before the first Frame Sync pattern
(see Figure 23).
2. A terminal may remain powered up indefinitely. transmitting concatenated Frames with or without intervening Symbol
Sync patterns (each Frame having a Frame Sync pattern and symbol timing being maintained from one Frame to the
next).
3. A receiving modern may be switched onto a channel before the distant transmitter has started up. or may be switched
onto a channel where the transmitting station is already sending concatenated Frames
5.3.2 Clock and Level Acquisition Procedures with RF Carrier Detect
When the receiving modem is enabled or switched onto a channel, it needs to establish the received symbol levels, clock
timing, and look for a Frame Sync pattern in the incoming signal. This is best done by the following procedure:
1, Ensure that the Control Registers PLLBW bits are set to 'lMde' and the LEVRES bits to 'Track’.
2. Wait until a received carrier has been present for 8 symbol times. This B~symbol delay gives time lor the received
signal to propagate through the modem's HRC filter. An 'FtF received 8 symbol times' qualifying function can be
included in a radio's carrier detect circuitry to take this into account.
3. Write a SFS or SFSH task to the Command Register with the A050 and the AQLEV bits set to '1'.
4. When the modern interrupts to signal that it has recognized a Frame Sync pattern (or completed the SFSH task) then
change the PLLBW bits to 'Medium'.
Once the receiving modem has achieved level and symbol timing synchronization with a particular channel - as evidenced
by recognition of a Frame Sync pattern - then subsequent concatenated Frames can be read by simply issuing SFS or
SFSH tasks at appropriate times, keeping the ASQSC and AQLEV bits at zero, and the PLLBW and LEVRES bits at their
current 'Medium' and 'Track' settings, respectively.
Rest of Frame
B-symbol delay dotemined by external
, circuit such as HF carrier detect
Set A050 and AQLEV bits
to man Acquisition sequences
Level Measurement and Ctock
Extraction CIrwiB
Increasing accuracy and lengthening response times
Figure 23: Acquisition Sequence Timing
5.3.3 Clock and Level Acquisition Procedure wimut RF Carrier Detect
It '5 also possible to use the modem in a system where there is an indeterminate delay between the RF transmitter turn on
tine and the transmission moment of the Symbol Sync pattern, or where a receive carrier detect signal is not available to
the controlling pc, or where the transmitting terminal can send separate unsynchronized Frames. in these cases, each
Frame should be preceded by, a Symbol Sync pattern which should be extended to about 100 symbols and the procedure
provided in Section 5.3.2. used.
5.3.4 Automatic Acquisition Functions
Setting the A080 and AQLEV bits to 't' triggers the modem's automatic Symbol Clock Extraction and Level Measurement
acquisition sequences, which are designed to measure the received symbol timing, amplitude. am Dc citset as quickly as
"" wsslble before switching to accurate - but slower- measurement modes. These acquisition sequences act very quickly if
triggered at the start of a received Symbol Sync pattern (as shown in Figure 23), but will still function correctly, although
more slowly, it started any time during a normal Frame as when the receiver is switched onto a channel where the
transmitter is operating continuously.
The automatic AQLEV Level Measurement acquisition sequence starts with the level measurement circuits being put into
‘Clamp' Mode tor one symbol time to quickly set the voltages on the DOC pins to approximately correct levels. The level
measurement circuits are then automatically set to ‘Lossy Peak Detect' mode for 15 symbol times, then 'Siow Peak
Detect‘ until a received Frame Sync pattern is recognized, otter which the automatic sequence ends and the level
measurement circuit mode reverts to the mode set by the LEVFIES bis oi the Control Register (normally ‘Level Track').
The peak detectors used in both "Slow' and ‘Lossy Peak Detect‘ modes include additional low pass filtering oi the received
signal which greatly reduces the effect of pattem noise on the reference voltages held on the external DOC capacitors, but
means that pairs oi '+3' (and ‘-3') symbols need to be received to establish the correct levels, Two pairs oi '+3‘ and two
pairs ol '-3' symbols received after the start of an AQLEV sequence are suiiicient to correctly set the levels on the DOC
capacitors.
The automatic AQSC Symbol Clock acquisition sequence sets the PLL to "Extra Wide Bandwidth’ mode for 16 symbol
times (this mode is not one of those which can be selected by the Control Register PLLEW bits) then changes to 'Wide‘
bandwidth. After 45 symbol times, the PLL mode will revert to that set by the Control Register PLLBW bits.
5.4 AC Coupling
For a practical circuit, ac coupling between the modem's transmit output to the lrequancy modulator and between the
receiver‘s trequemy discriminator and the receive ir'put of the modern may be desired. There are. however, two issues
which deserve consideration:
1. Ac coupling of the signal degrades the Bit Error Rate performance of the modem. The following graph illustrates the
typical bit error rates at 4800 symbols/sec (9600bps) without FEC for reasonme random data with differing degrees of AC
_, coupling:
rem
Lem
use
rem
_rumocm
—n—Tx5k mac
—o—Tx§tz. use
---- use. rum;
1,504
r s a r a l to Ir r: r: u
ma(m-mmmmum
Figure 24: Effect 01 Ac Coupling on BER (without FEC)
2. Arty ac coupling at the receive input will transform any step in the voltage at the discriminator output to a slowly
decaying pulse which can confuse the modem‘s level measuring circuits. As illustrated in Figure 25 below, the time for
this step to decay to 37% of its original value is 'FlC' where:
RC = 2n(3dB cut - off frequency of the RC network)
which is 32ms, or 153 symbol times at 4800 symbols/sec (9600bps) tor a 5Hz network,
Figure 25: Decay 11me - Ac Coupling
In general, it Is best to DC couple the receiver discriminator to the modern and ensure that any AC coupling to the
transmitters frequency modulator has a -3dB cut-off frequency of no higher than 5Hz for 4800 symbols/sec (swoops).
55 Radio Performance
The maximum data rate that can be transmitted over a radio channel using these modems depends on:
RF channel sparing.
Allowable adiacent channel interference.
Symbol rate.
Peak carrier deviation (modulation Index).
Tx and th reference oscillator accuracy.
Modulator and demodulator linearity.
Receiver IF filter frequency and phase characteristics.
Use of error correction techniques.
Acceptable error rate.
As a guide, 4800 symbols/sec (swoops) an be achieved (subject to local regulatory requirements) over a system with
125kHz channel spacing if the transmitter frequency deviation is set to z2.5kl-lz peak for a repetitive ' +3 +3 -3 -3 '
pattern and the maximum difference between transmitter and receiver ‘canier‘ frequencies is less than 2400Hz.
The modulation scheme employed by these modems is designed to achieve high data throughout by exploiting as much
as possible of the RF channel bandwidth. However: this does place constraints on the performance of the radio.
Particular attention must be paid to:
Linearity, frequency, and phase response of the Tx Frequency Modulator. For a 4800 symbols/sec (SGOObps) system,
the lrequency response should be within 12dB over the range SHz to 5kHz. relative to 2400Hz.
The bandwidth and phase response of the receiver‘s IF filters.
Accuracy of the Tx and For reference oscillators, as any difference will shift the received signal towards the skins of
the IF filter response and cause a DC offset at the discriminator output
Viewing the equalized received signal eye diagram. using the Mode Register FtXEYE function, provides a good indication
of the overall RF transmitter/receiver perton'nance.
Rx FREQUENC‘V
DISCRIMINATDR
SIGNAL LEVEL
ADJLSTMENT
SIGNAL AND
DO LEVEL
ADJUSTMENT
Figure 26: Typical Connections between Radio and MIX!" 95
5.6 Received Signal Quality Monitor
In applications where the modem has to monitor a long transmission containing a number of concatenated Frames, it is
Frecornmended that the controlling software include a function which regularly checks that the modem is still receiving a
toad data signal and triggers a re~acquisition and possibly changes to another channel ii a problem is encountered. This
strategy has been shown to improve the system's overall performance in situation where fading, large noise bursts, severe
co-channel interference, or loss of the received signal for long periods are likely to occur.
Such a function can be simply implemented by regularly reacfing the Data Quality Register, which gives a measure of the
overall quality of the received signal. as well as the current effectiveness of the modem's clock extraction and level
measurement systems. Experience has shown that if two consecutive D0 readings are both less than 50 then it is worth
instructing the MX91 QB to re-acquire the received signal levels and timing once it has been established that the received
carrier level is setislactory. Re—ecquisifion should follow the procedure given In Section 543.
The intervals between Data Quality readings is not critical. but should be a minimum of 64 symbol times except for the first
reading made eftertriggering the A030 and AOLEV automatic acquisition sequences, which should be delayed for about
250 symbol times
A suitable algorithm is shown in Figure 27.
Note: Times are symbol times.
BS
'LAST_DQ < 50 7
Ves
Figure 27: Received Signal Quality Monitor Flowchart
6 Performance Specification
’6.1 Electrical Performance
‘i.1.1 Absolute Maximum Ratings
Exceeding these maximum ratings can result in damage to the device,
General
An other - n
DW, LH, P Package
Total Allowable Power Dissipation at Tm; = 25°C
Deming above 250
Storage Temperature -55
0- - ting Temperature 40
Min.
Total Allowable Power Dissipation at TAMB 25“C
Derating above 25“C
Storage Tem reture
Operating Ten-i erature
mW
9 mW/‘C above “C
1 25 °C
-40 85 1 “C
6.1.2 Operating Limits
Correct operation of the device outside these limils is not “implied,
Symbol Rate
Xtal Frequency
6.1.3 Operating Characterlstlcs
For the following conditions unless othenm'se specified:
”Xlal Frequency = 4,9152MHz, Symbol Rate = 4800 symbols/sec,
' loise Bandwidth = D to QSOOHZ, VDD = 5.0V Q TAMB = 25°C
Unlts
_|
DC Parameters
hm
hm (VDD = 33V)
[DD (Powersave Mode)
IDD (Powersave Mode, VDD = 3.3V)
mA
mA
mA
mA
AC Parameters
Tx Output
TXOUT Impedance
Signal Level
TXIMP = 0
TXIMP = 1
_.
0.83
5000) N AAAIIE
r A o
7‘
IS
“o
output Dc Offset with respect to vm, 12 m v
Rx Input —
RXIN Impedance (at 100Hz) m M9
RXIN Amp Voltage Gain (input = 1mVRM5 at 100Hz) 300 VN
Input Signal Level 5 07 t 0 Vp_p
" DC Offset with respect to V5.) [2 5 -05 ‘J
XTALICLOCK INPUT
'High‘ Pulse Width 6 40 ns
‘Low‘ Pulse Width 6 40 ns
Input Impedance (at tOOHz) 10.0 - M9
Inverter Gain (input = 1 mVHMs at 100Hz) 20 dB
at: interlude
Input Logic '1' Level 7, a 70% VDD
Input Logic "0' Level 7, a 31W. vDD
Input Leakage Current (vm = o to van) 7. a ~5.o -m pA
Input Capacitance 7, B 1040 pF
Output Logic "1' Level (lot. = 120pA) 8 9236 VDD
Output Logic '0' Level um = SGOuA) a, 9 VDD
or State Leakage Current (vow = v0.3) 9 -m uA
6.1.4 Operating Characteristics Notes:
1. Not including any current drawn from the modem pins by external circuitry other than the Xtal oscillator.
2. Small signal impedance.
/ 1. Measured after the external RC filter (FM/05) for a '+3 +3 —3 <1..." symbol sequence, (T x output level is proportional
to VDD).
Measured at the TXOUT pin with the modem in the Tx idle mode.
For optimum performance, measured at FtXAMPOUT pin, for a "...+3 +3 —3 -...a" symbol sequence, TXIMP = 0 or 1,
The optimum level and Dc offset values are proportional to VDD.
Timing for an enemal input to the XTAL/CLOCK pin.
W, m fi,A0andA1plns.
DO - D7 plns.
9. W pin.
6.1.5 Timing
9‘?‘
we!»
‘ “0 Parallel Interface Timings (ref. Figure Units
28)
hcsi Address valid to a low time "5
Address hold time
6§ hold time
——n-- memes
§§ toV—Vfiorfi Iowtime
m Head data hold lime
m Write data held time
—m
mm m high in 5 low time (write) -“ “
CL Read access time from fi low 2 -
RL Read access time from E low 2 -
W low tlme
m high to 00437 3-state time
Whigh to filow time (read)
W—Fi'lolw time
Iiiiilfi
Tlmlng News:
1. XtallClock cycles at the XTAlJCLOCK pin.
2. With SOpF max to Vss on DO - D7 pins.
VMIT'E (Nd-E (WAT!) moan)
kn M—N
I I
ADDRESS I
A“,
I I I
Ina K—P’I lcsu K—N , I
I I
a | l | Icsm
, lq——-J
I I ML | I I
I | 14———>I I
u I |
WR ' | I I I
l I m“ I I I I
hm- n—u N—-—H I I
I l I
_ I I
RD I (w | I
I H N—N w
| I I |
| I
DATA
DOInD7 (1 ma)
. l
mmumlnmouuoom)
1m N—n
I I
ADDRESS I
“7,“ ADDRESSVAIJD I
I I I
m H—H “H H I '
I I I
g . I , l |
I I n ' IcsI-al "
Muss. fi—‘PI | I I
I I | l
WI: ‘ 7 ' m,“
I I | I
| fl—P: I
I I I In. :
H———>‘ v
I I
as M
' ' ham ' I '
' K———N m K—H'
I | | I
DATA
~———-—-h
Figure 28: “C Parallel Interlaee fimings
6.1.6 Typical Bit Error Rate
15-1
— BER with FEC
15-2 - - -EERwlthout FEC
1 5-3
BE R
1E—4
1 5-5
1E-G
B 9 10 11 12 13 14 15 16
SIN dB (Noise in 2 x Symbol RateBandelh)
Figure 29: Typical Bit Error Rate With and Without FEc
Measured under nominal working conditions, LEVRES bits set to ‘Level Track“ or 'Slow Peak Detect“ and PLLBW bits set
.- to 'Medium‘ or ‘Narrouf Bandwidth, Command Register TXIMP bit set to '0’ or '1' (same for Tx and Rx devices), with
weirdo-random data.
Signal Voltage
N t : S/Ncalc isles 20I
°e " as og‘°(VoilageNoise
Where: Signal Voltage is the measured Vans of a random 4—level signaL
Noise Voltage is the Vans of a flat Gaussian noise signal having a bandwidth from a few Hz to twice the
symbol rate e.g. to 9600Hz when measuring a 4800 symboVsec (9600bps) system.
Both signals are measured at the same point in the test circuit.
8.2 Packaging
Package Tolerances
DIM. MIN. TYP. MAX.
A 0.597 (15.15) 0.513 (15m
B 0205 (7.20) 0.299 (7.59)
C 0.000 (2.35) 0.105 (2.87)
E 0500 (0.00) 0.010 (10.01)
H 0.000 (0.00) 0.020 (0.51)
J 0.013 (030) 0,020 (0.51)
K 00050191) 0.00 (1.17)
L 0.016 (0.41) 0.050 (1.21)
P 0.050 (127)
T 0.000 (020) 0.0125 (0.32)
w 45°
X 0° 10‘=
Y 5° 7"
Z 5-
NOTE: Ald'meflsiofs'n hams(m)
Manninm
Figure 30: 2bpln SOIC Mechanical Ouulne: Orderas par-ma. MXQIBBDW
Package Tolerances
DIM. MIN. TYF‘. MAX.
A 0.310 (007) 0.320 (0.33)
B 0205 (520) 0213 (5.30)
C 0.000 (1.07) 0.079 (2.00)
E 0.301 (7.05) 0312 (7.90)
H 0.002 (0.05) 0000 (0.21)
J 0.010 (025) 0.015 (0.30)
L 0.022 (0.55) 0.037 (0.95)
P 0020055)
T 0.005 (0.13) 0.000 (022)
X 0' a“
Y 7“ 9°
Z 4- 10°
NOTE: (“him-mics i1 5711135an
Mm‘ndeg‘ees
Flgure 31: 24-pin SSOP Mechanlcal Outline: Wasp-rim 50519508
PackageTolerances
01m. MIN. TYE MAX.
A 0.000 (0.01) 0.409 (10.40)
B 0000 (9.01) 0.409 (10.40)
c 0.120 (3.25) 0.146 (0.70)
D 0.417 (10.00) 0.435 (11.05)
E 0417 (10.60) 0.435 (11.05)
F 0250 (0.35)
G 0250 (0.35)
H 002.1 (0.50)
J 0.010 (0.45) 0.002 (0.55)
K 0.047 (1.19) 0.040 (122)
P 0.040 (1.24) 0.051 (1.30)
T 0.000 (0 152) 0.009 (022)
w so- 45“
Y 6"
NOTE: Andimamions il Mann.)
mushdegsa
Figure 32: 24-pin PLCC Mechanical Outllne : Orderaspafl no. MSIQBLH
l‘.___A_—__.
Package Tolerances
DIM. M|N. TYP. MAX.
A 1200 (30.40) 1270 (0220)
B 0.500 (12.70) 0.555 (14.04)
C 0.151 (3.04) 0m (5.59)
E 0.500 (15.24) 0.570 (17.02)
E1 0500 (14.09) 0.625 (15.00)
H 0.015 (0.30) 0.06 (1.14)
J 0.015 (038) 0.023 (0.50)
J1 0.040 (1.02) 0.065 (1.05)
K 0.066 (1.57) 0.074 (1 as)
L 0.121 (3.07) 0.150 (4.05)
P 0.100 (154)
T 0.000 (020) 0.015 (0.30)
Y 7“
NOTE: 011mm “11 110100501110)
Angus m in deg-u
Flgwe 33: 24-pin PDIP Mechanical Oufline: Orderasparnm. MXQIQBP

---

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