IP Mobilenet M64780D25 High Speed Mobile Radio User Manual MX919BDB r3

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MX919B
COMMUNICATION SEMICONDUCTORS
DATA BULLETIN
4-Level FSK Modem Data Pump
PRELIMINARY INFORMATION
Features
Applications
•
4-Level Root Raised Cosine FSK Modulation
•
Wireless Data Terminals
•
Half Duplex, 4800 to 19.2kbps
•
Two Way Paging Systems
•
Increase Channel Bit Rate/Hz
•
Digital Radio Systems
•
Full Data Packet Framing
•
Wide Area Wireless Data Broadcasts
•
Impulse and NRZ Signal Modes
•
Point to Point Wireless Data Links
•
Enhanced Performance in Noisy Conditions
•
Error Detection and Error Correction
•
Low Power 3.3V/5.0V Operation
MX919B
RADIO
MODULATOR
ANALOG TX
RF
DISCRIMINATOR
ANALOG RX
MODEM
DATA
PUMP
HOST µC
DATA AND
CONTROL BUS
SYSTEM
APPLICATION
PROCESSING
The MX919B is a low voltage CMOS device containing all of the baseband signal processing and Medium
Access Control (MAC) protocol functions required for a high performance 4-level FSK Wireless Packet Data
Modem. It interfaces with the modem host µC and the radio modulation/demodulation circuits to deliver
reliable two-way transfer of the application data over a wireless link.
The MX919B assembles application data received from the host µC, adds forward error correction (FEC) and
error detection (CRC) information, and interleaves the result for burst-error protection. After automatically
adding symbol and frame sync codewords, the data packet is converted into filtered 4-level analog signals for
modulating the radio transmitter.
In receive mode, the MX919B performs the reverse function using the analog signals from the receiver
discriminator. After error correction and removal of the packet overhead, the recovered application data is
supplied to the host µC. CRC detected residual uncorrected data errors will be flagged. A readout of the
SNR value during receipt of a packet is also provided.
The MX919B uses data block sizes and FEC/CRC suitable for applications where high-speed transfer of data
over narrow-band wireless links is required. The device is programmable to operate at standard bit rates from
a wide range of Xtal/clock frequencies.
The MX919B may be used with a 3.0V to 5.5V power supply and is available in the following package styles:
24-pin SSOP (MX919BDS), 24-pin SOIC (MX919BDW), 24-pin PLCC (MX919BLH), and 24-pin PDIP
(MX919BP).
©2001 MX•COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 2 of 47
MX919B PRELIMINARY INFORMATION
CONTENTS
Section
Page
1. Block Diagram ............................................................................................................... 6
2. Signal List ...................................................................................................................... 7
3. External Components ................................................................................................... 8
4. General Description ...................................................................................................... 9
4.1
Description of Blocks ......................................................................................................... 9
4.1.1
Data Bus Buffers..................................................................................................................... 9
4.1.2
Address and R/W Decode ...................................................................................................... 9
4.1.3
Status and Data Quality Registers.......................................................................................... 9
4.1.4
Command, Mode, and Control Registers ............................................................................... 9
4.1.5
Data Buffer.............................................................................................................................. 9
4.1.6
CRC Generator/Checker ........................................................................................................ 9
4.1.7
FEC Generator/Checker ......................................................................................................... 9
4.1.8
Interleave/De-Interleave Buffer............................................................................................... 9
4.1.9
Frame Sync Detect ................................................................................................................. 9
4.1.10 Rx Input Amp ........................................................................................................................ 10
4.1.11 RRC Low Pass Filter ............................................................................................................ 10
4.1.12 Tx Output Buffer.................................................................................................................... 11
4.1.13 Rx Level/Clock Extraction..................................................................................................... 12
4.1.14 Clock Oscillator and Dividers................................................................................................ 12
4.2
4.3
4.4
4.5
Modem - µC Interaction ................................................................................................... 12
Binary to Symbol Translation ........................................................................................... 13
Frame Structure............................................................................................................... 14
The Programmer’s View................................................................................................... 15
4.5.1
Data Block Buffer .................................................................................................................. 15
4.5.2
Command Register ............................................................................................................... 15
4.5.2.1
Command Register B7: AQSC - Acquire Symbol Clock ................................................ 16
4.5.2.2
Command Register B6: AQLEV - Acquire Receive Signal Levels ................................. 16
4.5.2.3
Command Register B5: CRC ........................................................................................ 16
4.5.2.4
Command Register B4: TXIMP - Tx Level/Impulse Shape ............................................ 16
4.5.2.5
Command Register B3 - Reserved ................................................................................ 16
4.5.2.6
Command Register B2, B1, B0: TASK........................................................................... 16
4.5.2.7
NULL: No effect .............................................................................................................. 18
4.5.2.8
SFSH: Search for Frame Sync plus Header Block ........................................................ 18
4.5.2.9
RHB: Read Header Block............................................................................................... 18
4.5.2.10 RILB: Read 'Intermediate' or 'Last' Block ....................................................................... 18
4.5.2.11 SFS: Search for Frame Sync ......................................................................................... 18
4.5.2.12 R4S: Read 4 Symbols .................................................................................................... 19
4.5.2.13 T24S: Transmit 24 Symbols ........................................................................................... 19
4.5.2.14 THB: Transmit Header Block.......................................................................................... 19
4.5.2.15 TIB: Transmit Intermediate Block ................................................................................... 20
4.5.2.16 TLB: Transmit Last Block ............................................................................................... 20
©2001 MX•COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 3 of 47
MX919B PRELIMINARY INFORMATION
4.5.2.17 T4S: Transmit 4 Symbols ............................................................................................... 20
4.5.2.18 RESET: Stop any current action .................................................................................... 20
4.5.2.19 Task Timing .................................................................................................................... 20
4.5.2.20 RRC Filter Delay............................................................................................................. 21
4.5.3
4.5.3.1
Control Register B7, B6: CKDIV - Clock Division Ratio ................................................. 22
4.5.3.2
Control Register B5, B4: FSTOL - Frame Sync Tolerance to Inexact Matches............. 22
4.5.3.3
Control Register B3, B2: LEVRES - Level Measurement Modes .................................. 23
4.5.3.4
Control Register B1, B0: PLLBW - Phase-Locked Loop Bandwidth Modes .................. 23
4.5.4
Mode Register B7: IRQEN - IRQ Output Enable ......................................................... 24
4.5.4.2
Mode Register B6: INVSYM - Invert Symbols................................................................ 24
4.5.4.3
Mode Register B5: TX/RX - Tx/Rx Mode ...................................................................... 24
4.5.4.4
Mode Register B4: RXEYE - Show Rx Eye.................................................................... 25
4.5.4.5
Mode Register B3: PSAVE - Powersave........................................................................ 25
4.5.4.6
Mode Register B2, B1, B0 .............................................................................................. 25
Status Register ..................................................................................................................... 26
4.5.5.1
Status Register B7: IRQ - Interrupt Request .................................................................. 26
4.5.5.2
Status Register B6: BFREE - Data Block Buffer Free.................................................... 26
4.5.5.3
Status Register B5: IBEMPTY - Interleave Buffer Empty............................................... 26
4.5.5.4
Status Register B4: DIBOVF - De-Interleave Buffer Overflow ....................................... 26
4.5.5.5
Status Register B3: CRCERR - CRC Checksum Error.................................................. 27
4.5.5.6
Status Register B2, B1, B0............................................................................................. 27
4.5.6
Data Quality Register............................................................................................................ 27
CRC, FEC, and Interleaving............................................................................................. 27
4.6.1
4.7
Mode Register....................................................................................................................... 24
4.5.4.1
4.5.5
4.6
Control Register .................................................................................................................... 22
Cyclic Redundancy Codes.................................................................................................... 27
4.6.1.1
CRC1 .............................................................................................................................. 27
4.6.1.2
CRC2 .............................................................................................................................. 28
4.6.1.3
Forward Error Correction................................................................................................ 28
4.6.1.4
Interleaving ..................................................................................................................... 28
Transmitted Symbol Shape.............................................................................................. 28
5. Application................................................................................................................... 30
5.1
5.2
5.3
5.4
5.5
5.6
Transmit Frame Example................................................................................................. 30
Receive Frame Example.................................................................................................. 33
Clock Extraction and Level Measurement Systems.......................................................... 36
5.3.1
Supported Types of Systems................................................................................................ 36
5.3.2
Clock and Level Acquisition Procedures with RF Carrier Detect ......................................... 36
5.3.3
Clock and Level Acquisition Procedure without RF Carrier Detect ...................................... 36
5.3.4
Automatic Acquisition Functions........................................................................................... 37
AC Coupling..................................................................................................................... 37
Radio Performance .......................................................................................................... 39
Received Signal Quality Monitor ...................................................................................... 40
©2001 MX•COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 4 of 47
MX919B PRELIMINARY INFORMATION
6. Performance Specification ......................................................................................... 41
6.1
Electrical Performance..................................................................................................... 41
6.1.1
Absolute Maximum Ratings .................................................................................................. 41
6.1.2
Operating Limits.................................................................................................................... 41
6.1.3
Operating Characteristics ..................................................................................................... 42
6.1.3.1
6.2
Operating Characteristics Notes: ................................................................................... 42
6.1.4
Timing ................................................................................................................................... 43
6.1.5
Typical Bit Error Rate............................................................................................................ 45
Packaging........................................................................................................................ 46
MX-COM, Inc. Reserves the right to change specifications at any time and without notice
©2001 MX•COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 5 of 47
MX919B PRELIMINARY INFORMATION
Figures
Figure
Page
Figure 1: Block Diagram ..................................................................................................................................... 6
Figure 2: Recommended External Components ................................................................................................ 8
Figure 3: Typical Modem µC connections .......................................................................................................... 9
Figure 4: Translation of Binary Data to Filtered 4-Level Symbols in Tx Mode................................................. 10
Figure 5: RRC Filter Frequency Response vs. Bit Rate (including the external RC filter R4/C5).................... 11
Figure 6: RRC Filter Frequency Response vs. Symbol Rate (including the external RC filter R4/C5)............ 11
Figure 7: Over-Air Signal Format ..................................................................................................................... 14
Figure 8: Alternative Frame Structures ............................................................................................................ 15
Figure 9: Transmit Task Overlapping ............................................................................................................... 17
Figure 10: Receive Task Overlapping .............................................................................................................. 17
Figure 11: Transmit Task Timing Diagram ....................................................................................................... 21
Figure 12: Receive Task Timing Diagram ........................................................................................................ 21
Figure 13: RRC Low Pass Filter Delay............................................................................................................. 21
Figure 14: Ideal 'RXEYE' Signal....................................................................................................................... 25
Figure 15: Typical Data Quality Reading vs S/N .............................................................................................. 27
Figure 16: Input Signal to RRC Filter in Tx Mode for TXIMP = 0 and 1 ........................................................... 28
Figure 17: Tx Signal Eye TXIMP = 0 ................................................................................................................ 29
Figure 18: Tx Signal Eye TXIMP = 1 ................................................................................................................ 29
Figure 19: Transmit Frame Example Flowchart, Main Program ...................................................................... 31
Figure 20: Tx Interrupt Service Routine ........................................................................................................... 32
Figure 21: Receive Frame Example Flowchart, Main Program ........................................................................ 34
Figure 22: Rx Interrupt Service routine ............................................................................................................ 35
Figure 23: Acquisition Sequence Timing.......................................................................................................... 36
Figure 24: Effect of AC Coupling on BER (without FEC) ................................................................................. 37
Figure 25: Decay Time - AC Coupling.............................................................................................................. 38
Figure 26: Typical Connections between Radio and MX919B......................................................................... 39
Figure 27: Received Signal Quality Monitor Flowchart .................................................................................... 40
Figure 28: µC Parallel Interface Timings.......................................................................................................... 44
Figure 29: Typical Bit Error Rate With and Without FEC ................................................................................. 45
Figure 30: 24-pin SOIC Mechanical Outline: Order as part no. MX919BDW ................................................. 46
Figure 31: 24-pin SSOP Mechanical Outline: Order as part no. MX919BDS ................................................. 46
Figure 32: 24-pin PLCC Mechanical Outline : Order as part no. MX919BLH ................................................. 47
Figure 33: 24-pin PDIP Mechanical Outline: Order as part no. MX919BP ..................................................... 47
©2001 MX•COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 6 of 47
MX919B PRELIMINARY INFORMATION
1. Block Diagram
STATUS
REGISTER
IRQ
DATA
QUALITY
REGISTER
µCONTROLLER
INTERFACE
D0
D1
D2
D3
D4
D5
D6
D7
COMMAND
REGISTER
DATA
BUS
BUFFERS
CONTROL
REGISTER
DATA
BUFFER
WR
RD
CRC
GENERATOR/
CHECKER
FEC
ENCODER/
DECODER
ADDRESS
AND
R/W
DECODE
CS
A0
A1
FRAME
SYNC DETECT
INTERLEAVE/
DE-INTERLEAVE
VDD
VDD
MODE
REGISTER
VBIAS
Tx Symbols
Rx Symbols
VSS
RXAMPOUT
Rx Input Amp
VBIAS
RXIN
DOC1
Tx
Rx
RRC
LOW PASS
FILTER
XTAL
VBIAS
CLOCK
OSCILLATOR
AND
DIVIDERS
Rx
Tx
Rx LEVEL/CLOCK
EXTRACTION
DOC2
RxEye
Rx
TXOUT
Tx
Tx Output Buffer
XTAL /
CLOCK
Figure 1: Block Diagram
©2001 MX•COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 7 of 47
MX919B PRELIMINARY INFORMATION
2. Signal List
Pin No.
Signal
Type
output
10
D7
D6
D5
D4
D3
D2
D1
D0
RD
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
input
11
WR
Input
12
13
VSS
power
input
14
15
16
A0
A1
IRQ
CS
input
input
output
17
18
XTAL
XTAL/CLOCK
DOC2
19
DOC1
output
20
21
TXOUT
VBIAS
output
output
22
23
24
RXIN
RXAMPOUT
VDD
input
output
power
input
output
Description
A 'wire-ORable' output for connection to the host µC's Interrupt
Request input. When active, this output has a low impedance pull
down to VSS. It has high impedance when inactive.
Pins 2-9 (D7-D0) are 8-bit, bi-directional,
3-state µC interface data lines
Read. An active low logic level input used to control the reading of data
from the modem into the host µC.
Write. An active low logic level input used to control the writing of data
into the modem from the host µC.
Negative supply (ground).
Chip Select. An active low logic level input to the modem used to
enable a data read or write operation.
Logic level modem register select input
Logic level modem register select input
Output of the on-chip oscillator.
Input to the on-chip oscillator, for an external Xtal circuit or clock.
Connection to the Rx level measurement circuitry. Should be
capacitive coupled to VSS .
Connection to the Rx level measurement circuitry. Should be
capacitive coupled to VSS
Tx signal output from the modem.
A bias line for the internal circuitry held at VDD/2. This pin must be
bypassed to VSS by a capacitor mounted close to the device pins.
Input to the Rx input amplifier.
Output of the Rx input amplifier.
Positive supply. Levels and voltages are dependent upon this supply.
This pin should be bypassed to VSS by a capacitor mounted close to
the device pins.
Table 1: Signal List
©2001 MX•COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 8 of 47
MX919B PRELIMINARY INFORMATION
3. External Components
µCONTROLLER INTERFACE
VDD
IRQ
D7
D6
D5
D4
D3
D2
D1
D0
RD
WR
VSS
CS
A0
A1
MX919B
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
C1
RXAMPOUT
RXIN
VBIAS
TXOUT
C8
To Tx Frequency
Modulator
R4
DOC1
DOC2
XTAL/CLOCK
XTAL
A1
A0
CS
From Rx FM
Discriminator
R1
R2
C7
C5
C6
C2
XTAL/CLOCK
17
X1
R3
16
C3
C4
XTAL
Figure 2: Recommended External Components
Component
Notes
R1
Value
Tolerance
Component
Notes
±20%
C4
Value
Tolerance
±20%
R2
100kΩ
±5%
C5
±5%
R3
1MΩ
±20%
C6
±20%
R4
100kΩ
±5%
C7
±20%
C1
0.1µF
±20%
C8
±5%
C2
0.1µF
±20%
X1
2,3
C3
±20%
Table 2: Recommended External Components
Recommended External Component Notes:
1. See Section 4.1.10.
2. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at
least 40% of VDD, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain
crystal oscillator design assistance, consult your crystal manufacturer.
3. The values used for C3 and C4 should be suitable for the frequency of the crystal X1. As a guide, values
(including stray capacitance) of 33pF at 1MHz falling to 18pF at 10MHz will generally prove suitable.
Crystal frequency tolerances are discussed in Section 4.5.3.4.
4. Values C5 and C8 should be equal to 750,000 / symbol rate, e.g.
5. Values C6 and C7 should be equal to 50,000 / symbol rate, e.g.
Symbol Rate
C5 and C8
Symbol Rate
C6 and C7
2400 symbols/second
330pF
2400 symbols/second
0.022µF
4800 symbols/second
150pF
4800 symbols/second
0.01µF
9600 symbols/second
82pF
9600 symbols/second
4700pF
©2001 MX•COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 9 of 47
MX919B PRELIMINARY INFORMATION
4. General Description
4.1
4.1.1
Description of Blocks
Data Bus Buffers
Eight bi-directional 3-state logic level buffers between the modem's internal registers and the host µC's data
bus lines.
4.1.2
Address and R/W Decode
This block controls the transfer of data bytes between the µC and the modem's internal registers according to
the state of the Write and Read Enable inputs ( WR and RD ), the Chip Select input ( C S ), and the Register
Address inputs A0 and A1.
The Data Bus Buffers, Address, and R/W Decode blocks provide a byte-wide parallel µC interface, which can
be memory-mapped, as shown in Figure 3.
D0:7
D0:7
Data Bus
A0:1
A0:1
Address Bus
A2:7
µC
Address Decode
Circuit
MODEM
VDD
IRQ pull up
resistor
IRQ
CS
IRQ
WR
RD
WR
RD
Figure 3: Typical Modem µC connections
4.1.3
Status and Data Quality Registers
Two, 8-bit registers which the µC can read, to determine the status of the modem and received data quality.
4.1.4
Command, Mode, and Control Registers
The values written by the µC to these 8-bit registers control the operation of the modem.
4.1.5
Data Buffer
A 12-byte buffer used to hold receive or transmit data to or from the µC.
4.1.6
CRC Generator/Checker
A circuit which generates (in transmit mode) or checks (in receive mode) the Cyclic Redundancy Checksum
bits, which may be included in the transmitted data blocks so the receive modem can detect transmission
errors.
4.1.7
FEC Generator/Checker
In transmit mode, this circuit adds Forward Error Correction bits to the transmitted data, resulting in the
conversion of binary data to 4-level symbols. In receive mode, this circuit translates received 4-level symbols
to binary data, using the FEC information to correct a large proportion of transmission errors.
4.1.8
Interleave/De-Interleave Buffer
This circuit interleaves data symbols within a block before transmission and de-interleaves the received data
so that the FEC system is best able to handle short noise bursts or fades.
4.1.9
Frame Sync Detect
This circuit, which is only active in receive mode, is used to look for the 24-symbol Frame Synchronization
pattern that is transmitted to mark the start of every frame.
©2001 MX•COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 10 of 47
MX919B PRELIMINARY INFORMATION
4.1.10 Rx Input Amp
This amplifier allows the received signal input to the modem to be set to the optimum level by suitable
selection of the external components R1 and R2. The value of R1 should be calculated to give 0.2 x VDD
voltsP-P at the RXAMPOUT pin for a received '...+3 +3 -3 -3 ...' sequence.
A capacitor may be placed in series with R1 if ac coupling of the received signal is desired (see Section 5.4),
otherwise the DC level of the received signal should be adjusted so that the signal at the modem's
RXAMPOUT pin is centered around VBIAS (VDD/2).
4.1.11 RRC Low Pass Filter
This filter, which is used in both transmit and receive modes, is a linear-phase lowpass filter with a 'Root
Raised Cosine' frequency response defined by:
H( f ) = 1 for 0 < f <
1- b
2T
π
( πTf - )
1 sin
1- b
for
2T
H( f ) =
H( f ) = 0 for f >
Where
 250 ?
Read DQ register into
µC variable 'THIS_DQ'
'THIS_DQ' < 50 ?
No
Yes
'LAST_DQ' < 50 ?
No
Copy 'THIS_DQ' to 'LAST DQ'.
Reset Timer.
Yes
Re Acquire
No
Timer > 64 ?
Yes
Figure 27: Received Signal Quality Monitor Flowchart
©2001 MX•COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 41 of 47
MX919B PRELIMINARY INFORMATION
6. Performance Specification
6.1
6.1.1
Electrical Performance
Absolute Maximum Ratings
Exceeding these maximum ratings can result in damage to the device.
General
Supply (VDD – VSS)
Voltage on any pin to VSS
Current
VDD
VSS
Any other pin
DW, LH, P Package
Total Allowable Power Dissipation at TAMB = 25°C
Derating above 25°C
Storage Temperature
Operating Temperature
DS Package
Total Allowable Power Dissipation at TAMB = 25°C
Derating above 25°C
Storage Temperature
Operating Temperature
6.1.2
Min.
-0.3
-0.3
Max.
7.0
VDD + 0.3
Units
-30
-30
-20
30
30
20
mA
mA
mA
-55
-40
800
13
125
85
mW
mW/°C above 25°C
°C
°C
-55
-40
550
125
85
mW
mW/°C above 25°C
°C
°C
Operating Limits
Correct operation of the device outside these limits is not implied.
Notes
Supply (VDD – VSS)
Symbol Rate
Temperature
Xtal Frequency
©2001 MX•COM, INC.
www.mxcom.com
Min.
3.0
2400
-40
1.0
Max.
5.5
9600
85
10.0
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Units
Symbols/sec
°C
MHz
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
6.1.3
Page 42 of 47
MX919B PRELIMINARY INFORMATION
Operating Characteristics
For the following conditions unless otherwise specified:
Xtal Frequency = 4.9152MHz, Symbol Rate = 4800 symbols/sec,
Noise Bandwidth = 0 to 9600Hz, VDD = 5.0V @ TAMB = 25°C
Notes
DC Parameters
IDD
IDD (VDD = 3.3V)
IDD (Powersave Mode)
IDD (Powersave Mode, VDD = 3.3V)
AC Parameters
TX Output
TXOUT Impedance
Signal Level
TXIMP = 0
TXIMP = 1
Output DC Offset with respect to VDD/2
RX Input
RXIN Impedance (at 100Hz)
Typ.
Max.
Units
4.0
2.5
1.5
0.6
10.0
6.3
mA
mA
mA
mA
1.0
2.5
kΩ
1.0
1.1
1.2
1.32
0.25
VP-P
VP-P
1.3
0.5
MΩ
V/V
VP-P
Min.
0.8
0.88
-0.25
10.0
RXIN Amp Voltage Gain (input = 1mVRMS at 100Hz)
Input Signal Level
DC Offset with respect to VDD/2
XTAL/CLOCK INPUT
‘High’ Pulse Width
‘Low’ Pulse Width
Input Impedance (at 100Hz)
Inverter Gain (input = 1mVRMS at 100Hz)
µC Interface
Input Logic ‘1’ Level
Input Logic ‘0’ Level
Input Leakage Current (VIN = 0 to VDD)
Input Capacitance
Output Logic ‘1’ Level (IOH = 120µA)
Output Logic ‘0’ Level (IOL = 360µA)
‘Off’ State Leakage Current (VOUT = VDD)
0.7
-0.5
40
40
10.0
300
1.0
ns
ns
MΩ
dB
20
7,8
7,8
7,8
7,8
8,9
70%
30%
5.0
-5.0
10.0
92%
8%
10
VDD
VDD
µA
pF
VDD
VDD
µA
6.1.3.1 Operating Characteristics Notes:
1. Not including any current drawn from the modem pins by external circuitry other than the Xtal oscillator.
2. Small signal impedance.
3. Measured after the external RC filter (R4/C5) for a "+3 +3 -3 -3...." symbol sequence, (Tx output level is
proportional to VDD).
4. Measured at the TXOUT pin with the modem in the Tx idle mode.
5. For optimum performance, measured at RXAMPOUT pin, for a "...+3 +3 -3 -3..." symbol sequence,
TXIMP = 0 or 1, The optimum level and DC offset values are proportional to VDD.
6. Timing for an external input to the XTAL/CLOCK pin.
7. WR , RD , CS , A0 and A1 pins.
8. D0 - D7 pins.
9.
IRQ pin.
©2001 MX•COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
6.1.4
Page 43 of 47
MX919B PRELIMINARY INFORMATION
Timing
µC Parallel Interface Timings (see Figure 28 )
tACSL
Address valid to CS low time
tAH
tCSH
Address hold time
tCSHI
CS high time
tCSRWL
Notes
Min.
Typ.
Max.
Units
ns
ns
ns
clock cycles
CS to WR or RD low time
ns
tDHR
tDHW
tDSW
tRHCSL
Read data hold time
Write data hold time
Write data setup time
90
ns
ns
ns
ns
tRACL
Read access time from CS low
175
ns
tRARL
Read access time from RD low
145
ns
tRL
RD low time
tRX
RD high to D0-D7 3 state time
tWHCSL
WR high to CS low time (read)
tWL
WR low time
CS hold time
RD high to CS low time (write)
200
ns
50
ns
ns
200
ns
Timing Notes:
1. Xtal/Clock cycles at the XTAL/CLOCK pin.
2. With 30pF max to VSS on D0 - D7 pins.
©2001 MX•COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 44 of 47
MX919B PRELIMINARY INFORMATION
WRITE CYCLE (DATA TO MODEM)
tAH
ADDRESS
A0, A1
ADDRESS VALID
tACSL
tCSH
tCSHI
CS
tWL
WR
tRHCSL
tCSRWL
RD
tDSW
tDHW
DATA
D0 to D7 (1 byte)
DATA
VALID
READ CYCLE (DATA FROM MODEM)
tAH
ADDRESS
A0, A1
ADDRESS VALID
tACSL
tCSH
CS
tCSHI
tWHCSL
WR
tCSRWL
tRL
RD
tRX
tRARL
DATA
D0 to D7 (1 byte)
tDHR
DATA VALID
tRACL
Figure 28: µC Parallel Interface Timings
©2001 MX•COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
6.1.5
Page 45 of 47
MX919B PRELIMINARY INFORMATION
Typical Bit Error Rate
1E-1
BER with FEC
1E-2
BER without FEC
1E-3
BER
1E-4
1E-5
1E-6
10
11
12
13
14
15
16
S/N dB (Noise in 2 x Symbol RateBandwidth)
Figure 29: Typical Bit Error Rate With and Without FEC
Measured under nominal working conditions, LEVRES bits set to 'Level Track' or 'Slow Peak Detect' and
PLLBW bits set to 'Medium' or 'Narrow' Bandwidth, Command Register TXIMP bit set to '0' or '1' (same for Tx
and Rx devices), with pseudo-random data.
Note: S / N calculates as 20log10 (
Where:
Signal Voltage
Voltage Noise
Signal Voltage is the measured VRMS of a random 4-level signal.
Noise Voltage is the VRMS of a flat Gaussian noise signal having a bandwidth from a few Hz to
twice the symbol rate e.g. to 9600Hz when measuring a 4800 symbol/sec (9600bps) system.
Both signals are measured at the same point in the test circuit.
©2001 MX•COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
6.2
Page 46 of 47
MX919B PRELIMINARY INFORMATION
Packaging
Package Tolerances
ALTERNATIVE
PIN
LOCATION
MARKING
PIN 1
C K
DIM.
MIN.
TYP.
MAX.
0.613 (15.57)
0.299 (7.59)
0.105 (2.67)
0.419 (10.64)
0.020 (0.51)
0.020 (0.51)
0.046 (1.17)
0.597 (15.16)
0.286 (7.26)
0.093 (2.36)
0.390 (9.90)
0.003 (0.08)
0.013 (0.33)
0.036 (0.91)
0.050 (1.27)
0.016 (0.41)
0.050 (1.27)
0.0125 (0.32)
0.009 (0.23)
45°
10°
0°
7°
5°
5°
NOTE : All dimensions in inches (mm.)
Angles are in degrees
Figure 30: 24-pin SOIC Mechanical Outline: Order as part no. MX919BDW
Package Tolerances
PIN 1
PIN 1
DIM.
MIN.
TYP.
MAX.
0.318 (8.07)
0.328 (8.33)
0.205 (5.20)
0.213 (5.39)
0.066 (1.67)
0.079 (2.00)
0.312 (7.90)
0.301 (7.65)
0.002 (0.05)
0.008 (0.21)
0.010 (0.25)
0.015 (0.38)
0.022 (0.55)
0.037 (0.95)
0.026 (0.65)
0.005 (0.13)
0.009 (0.22)
0°
8°
7°
9°
4°
10°
NOTE : All dimensions in inches (mm.)
Angles are in degrees
Figure 31: 24-pin SSOP Mechanical Outline: Order as part no. MX919BDS
©2001 MX•COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 47 of 47
Package Tolerances
DIM.
DA
PIN 1
MX919B PRELIMINARY INFORMATION
MIN.
TYP.
MAX.
0.409 (10.40)
0.380 (9.61)
0.409 (10.40)
0.380 (9.61)
0.146 (3.70)
0.128 (3.25)
0.417 (10.60)
0.435 (11.05)
0.417 (10.60)
0.435 (11.05)
0.250 (6.35)
0.250 (6.35)
0.023 (0.58)
0.018 (0.45)
0.022 (0.55)
0.047 (1.19)
0.048 (1.22)
0.049 (1.24)
0.051 (1.30)
0.006 (0.152)
0.009 (0.22)
30°
45°
6°
NOTE : All dimensions in inches (mm.)
Angles are in degrees
Figure 32: 24-pin PLCC Mechanical Outline : Order as part no. MX919BLH
Package Tolerances
E1
PIN1
J1
DIM.
E1
J1
MIN.
TYP.
MAX.
1.270 (32.26)
1.200 (30.48)
0.555 (14.04)
0.500 (12.70)
0.151 (3.84)
0.220 (5.59)
0.600 (15.24)
0.670 (17.02)
0.590 (14.99)
0.625 (15.88)
0.015 (0.38)
0.045 (1.14)
0.015 (0.38)
0.023 (0.58)
0.040 (1.02)
0.065 (1.65)
0.066 (1.67)
0.074 (1.88)
0.121 (3.07)
0.160 (4.05)
0.100 (2.54)
0.008 (0.20)
0.015 (0.38)
7°
NOTE : All dimensions in inches (mm.)
Angles are in degrees
Figure 33: 24-pin PDIP Mechanical Outline: Order as part no. MX919BP
©2001 MX•COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480170.003
All trademarks and service marks are held by their respective companies.

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Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
Create Date                     : 2001:08:28 11:03:17
Producer                        : Acrobat Distiller 4.0 for Windows
Creator                         : AdobePS5.dll Version 5.1
Title                           : Microsoft Word - MX919BDB_r3.doc
Modify Date                     : 2001:08:28 11:03:17-05:00
Page Count                      : 47

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