Intel 82557 Intel® 8255x 10/100 Mbps Ethernet User Manual To The 74761afe D960 432d 8832 A0a4bf9b78a2
User Manual: Intel 82557 to the manual
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- Contents
- Revision History
- Intel 8255x 10/100 Mbps Ethernet Controller Family
- Introduction 1
- Adapter and Controller Overview 2
- Power Management Interface 3
- PCI Interface 4
- 4.1 PCI Configuration Space
- Table 1. PCI Configuration Space
- 4.1.1 Vendor ID (Offset 0)
- 4.1.2 Device ID (Offset 2)
- 4.1.3 Command Register (Offset 4)
- 4.1.4 Status Register (Offset 6)
- 4.1.5 Revision (Offset 8)
- 4.1.6 Class Code (Offset 9)
- 4.1.7 Cache Line Size (Offset C)
- 4.1.8 Latency Timer (Offset D)
- 4.1.9 Header Type (Offset E)
- 4.1.10 Built in Self Test (Offset F)
- 4.1.11 Subsystem ID (Offset 2C)
- 4.1.12 Subsystem Vendor ID (Offset 2E)
- 4.1.13 Expansion ROM Base Address Register (Offset 30)
- 4.1.14 The Capabilities Pointer (Offset 34)
- 4.1.15 Interrupt Line (Offset 3C)
- 4.1.16 Interrupt Pin (Offset 3D)
- 4.1.17 Max_Lat / Min_Gnt (Offset 3E)
- 4.1.18 Power Management PCI Configuration Registers
- 4.2 PCI Command Usage
- 4.1 PCI Configuration Space
- EEPROM Interface 5
- Host Software Interface 6
- 6.1 The Shared Memory Architecture
- 6.2 Initializing the LAN Controller
- 6.3 Controlling the Device
- 6.3.1 Control / Status Registers (CSR)
- 6.3.2 System Control Block (SCB)
- 6.3.3 PORT Interface
- 6.3.4 EEPROM Control Register
- 6.3.5 Management Data Interface Control Register
- 6.3.6 Receive Byte Count Register
- 6.3.7 Early Receive Interrupt
- 6.3.8 Flow Control Register
- 6.3.9 Power Management Driver Register
- 6.3.10 General Control Register
- 6.3.11 General Status Register
- 6.4 Shared Memory Structures
- 6.4.1 Action Commands and Operating Modes
- 6.4.2 Specific Action Commands
- 6.4.2.1 NOP (000b)
- 6.4.2.2 Individual Address Setup (001b)
- 6.4.2.3 Configure (010b)
- Figure 17. Configure Command Format
- Table 38. 82557 Configuration Byte Map
- Table 39. 82558 Configuration Byte Map
- Table 40. 82559 Configuration Byte Map
- 6.4.2.3.1 Configuration Parameters
- Table 41. 82557 Dual-Port FIFO Settings - Transmit
- Table 42. 82557 Dual-Port FIFO Settings - Receive
- Table 43. 82558 and 82559 Dual-Port FIFO Settings - Transmit
- Table 44. 82558 and 82559 Dual-Port FIFO Settings - Receive
- Table 45. Extended Statistics Functionality
- Table 46. Pre-amble Length
- Table 47. 82558 B-step Configuration Block ARP Frame IP Address
- Table 48. 82558 B-step ARP Frame IP Address Mapping
- Table 49. Full Duplex Functionality
- 6.4.2.4 Multicast Setup (011b)
- 6.4.2.5 Transmit (100b)
- 6.4.2.6 Load Microcode (101b)
- 6.4.2.7 Dump (110b)
- 6.4.2.8 Diagnose (111b)
- 6.4.3 Receive Operation
- 6.5 Command Unit and Receive Unit Operation
- 6.6 Flow Control
- 6.7 Collision Backoff Modification in Switched Environments
- Physical Layer Interface 7
- 7.1 Management Data Interface (MDI)
- 7.2 MDI Register Set
- Table 59. MDI Register Set
- Table 60. 82555 MDI Register Set
- 7.2.1 Control Register: Register 0
- 7.2.2 Status Register: Register 1
- 7.2.3 Identification Registers: Registers 2 and 3
- 7.2.4 Auto-Negotiation Advertisement Register: Register 4
- 7.2.5 Auto-Negotiation Link Partner Ability Register: Register 5
- 7.2.6 Auto-Negotiation Expansion Register: Register 6
- 7.3 Intel 82555 Specific Registers
- 7.3.1 Status and Control Register: Register 16
- 7.3.2 Special Control Register: Register 17
- 7.3.3 Clock Synthesis Test and Control Register: Register 18
- 7.3.4 100BASE-TX Receive False Carrier Counter: Register 19
- 7.3.5 100Base-TX Receive Disconnect Counter: Register 20
- 7.3.6 100BASE-TX Receive Error Frame Counter: Register 21
- 7.3.7 Receive Symbol Error Counter: Register 22
- 7.3.8 100BASE-TX Receive EOF Error Counter: Register 23
- 7.3.9 10BASE-T Receive EOF Error Counter: Register 24
- 7.3.10 10BASE-T Transmit Jabber Detect Counter: Register 25
- 7.3.11 Equalizer Control and Status Register: Register 26
- 7.3.12 Special Control Register: Register 27
- 7.4 Auto-Negotiation Functionality
- 7.5 Vendor-Specific PHY Programming
- Programming Recommendations 8
- Wake-up Functionality A
- A.1 Wake-up Capability
- A.2 Low Power Modes
- A.3 Power Management Context After Reset
- A.4 Fixed Packet Filtering
- A.5 Link Status Event
- A.6 Flexible Packet Filtering
- A.7 82559 and Later Generation Device Implementation
- 82550 and 82551QM Specific Information B