Intel Laptop 8080 Users Manual
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2015-02-02
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In December 1973 Intel shipped the first 8-bit, N-channel microprocessor, the 8080. Since then it has become the most widely used microprocessor in the industry. Applications of the 8080 span from large, intelligent systems terminals to decompression computers for deep sea divers. This 8080 Microcomputer Systems User's Manual presents all of the 8080 system components. Over twenty-five devices are described in detail. These new devices further enhance the 8080 system: 8080A - 8-Bit Central Processor Unit Functionally and Electrically Compatible with the 8080. TTL Drive Capability. Enhanced Timing. 8224 - Clock Generator for 8080A. Single 16 Pin (DIP) Package. Auxiliary Timing Functions. Power-On Reset. 8228 - System Controller for 8080A. Single 28 Pin (DIP) Package. Single Interrupt Vector (RST 7) . . Multi-Byte Interrupt Instruction Capability (e.g. CALL). Direct Data and Control Bus Connect to all 8080 System. I/O and Memory Components. 8251 - Programmable Communication Interface. ASYNC or SYNC (including IBM bi·SYNC). Single 28 Pin Package. Single +5 Volt Power Supply. 8255 - Programmable Peripheral Interface. Three 8-Bit Ports. Bit Set/Reset Capability. Interrupt Generation. Single 40 Pin Package. Single +5 Volt Power Supply. In addition, new memory components include: 8708, 8K Erasable PROM; 8316A, High Density Mask ROM; and 5101, Low Power CMOS RAM. intel® Microcomputers. First from the beginning. CONTENTS INTRODUCTION General . Advantages of Designing with Microcomputers . . Microcomputer Design Aids Application Example . . . . . . . . . . . . . . . . . . . Application Table .. . . . . . . . . . . . . . . . . . . . ii iii iii iv CHAPTER 1THE FUNCTIONS OF A COMPUTER A Typical Computer System The Architecture of a CPU Computer Operations. . . . . . . . . . . . . . . . . . . 1-1 1-1 1-3 CHAPTER 2THE 8080 CENTRAL PROCESSING UNIT General . . . . . . . . . . . . . . . . . . . . . . Architectu.re of the 8080 CPU . . . . . . . The Processor Cycle . . . . . . . . . . . . . . Interrupt Sequences. . . . . . . . . . . . . . Hold Sequences. . . . . . . . . . . . . . . . . Halt Sequences . . . . . . . . . . . . . . . . . Start-u p of the 8080 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. 2-1 2-2 2-3 2-11 2-12 2-13 2-13 CHAPTER 3INTERFACING THE 8080 General . . . . . . . . . . . . . . . . . . . . . . . . . . .. Basic System Operation CPU Module Design . . . . . . . . . . . . . . . . . . .. Interfacing the 8080 to Memory and I/O Devices 3-1 3-1 3-2 CHAPTER 4INSTRUCTION SET General . . . . . . . . . . . . . . . . . . . . . Data Transfer Group Arithmetic Group . . . . . . . . . . . . . . Branch Group. . . . . . . . . . . . . . . . . Stack, I/O and Machine Control Group Summary Table. . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . .. .. .. .. CHAPTER 58080 MICROCOMPUTER SYSTEM COMPONENTS CPU Group 8224 Clock Generator Functional Description and System Applications Data Sheet . . . . . . . . . . . . . . . . . . . . . . .. 8228 System Controller Functional Description and System Applications. . . . . . . . . . . . . . . . .. Data Sheet. . . . . . . . . . . . . . . . . . . . . . .. S080A Central Processor Data Sheet . . . . . . . . . . . . . . . . . . . . . . .. 8080A-1 Central Processor (1.3,us) Data Sheet. . . . . . . . . . . . . . . . . . . . . . .. 8080A-2 Central Processor (1.5,us) Data Sheet. . . . . . . . . . . . . . . . . . . . . . .. M80SOA Central Processor (-55° to +125°C) Data Sheet . . . . . . . . . . . . . . . . . . . . . . .. 4-1 4-4 4-6 4-11 4-13 4-15 5-1 5-4 5-7 5-11 5-13 5-20 5-24 5-29 3-6 Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. ROMs 8702A Erasable PROM (256 x 8) Data Sheet . . . . . . . . . . . . . . . . . . 8708/8704 Erasable PROM (1 K x 8) Data Sheet . . . . . . . . . . . . . . . . . . 8302 Mask ROM (256 x 8) Data Sheet . . . . . . . . . . . . . . . . . . 8308 Mask ROM (1 K x 8) Data Sheet . . . . . . . . . . . . . . . . . . 8316A Mask ROM (2K x 8) Data Sheet . . . . . . . . . . . . . . . . . . RAMs 8101-2 Static RAM (256 x 4) Data Sheet. . . . . . . . . . . . . . . . . . 8111-2 Static RAM (256 x 4) Data Sheet . . . . . . . . . . . . . . . .. . 8102-2 Static RAM (1K x 1) Data Sheet 8102A-4 Static RAM (1 K x 1) Data Sheet . . . . . . . . . . . . . . . . . . 81078-4 Dynamic RAM (4K x 1) Data Sheet. . . . . . . . . . . . . . . . . . 5101 Static CMOS RAM (256 x 4) Data Sheet . . . . . . . . . . . . . . . . . . 8210 Dynamic RAM Driver Data Sheet . . . . . . . . . . . . . . . . . . 8222 Dynamic RAM Refresh Controller New Product Announcement . . . . . . . . . . .. 5-37 . . . . .. 5-45 . . . . .. 5-51 . . . . .. 5-59 . . . . .. 5-61 . . . . .. 5-67 . . . . .. 5-71 0 5-75 . . . . .. 5-79 . . . . .. 5-83 . . . . .. 5-91 . . . . .. 5-95 . . . . .. 5-99 I/O 8212 8-Bit I/O Port 5-101 Functional Description System Applications of the 8212 5-103 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . 5-109 8255 Programmable Peripheral Interface Basic Functional Description . . . . . . . . . . ~ . Detailed Operationa-I Description . . System Appl ications of the 8255 Data Sheet . . . . . . . . . . . . . . . . . . . . . . 8251 Programmable Communication Interface Basic Functional Description . . . . . . . . . . Detailed Operational Description System Applications of the 8251 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-113 5-116 5-127 5-1 30 . . 5-135 5-139 5-143 . . 5-144 Peri pherals 8205 One of 8 Decoder Functional Description System Applications of the 8205 Data Sheet 8214 Priority Interrupt Control Unit Interrupts jn Microcomputer Systems Functional Description . . . . . . . . . . . . . . . . System Appl ications of the 8214 .. . . . . . . . Data Sheet 8216/8226 4-Bit Bi-Directional Bus Driver Functional Description System Applications of the 8216/8226 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . 5-147 5-149 5-151 5-153 5-155 5-1 57 5-160 5-163 5-165 5-166 Coming Soon 8253 Programmable Interval Timer . . . . . . . . . . 5-169 5-171 8257 Programmable DMA Controller 8259 Programmable Interrupt Controller 5-173 CHAPTER 6PACKAGING INFORMATION. . . . • . . . . . . . . . . 6-1 Since their inception, digital computers have continuously become more efficient, expanding into new applications with each major technological improvement. The advent of minicomputers enabled the inclusion of digital computers as a permanent part of various process control systems. Unfortunately, the size and cost of minicomputers in "dedicated" applications has limited their use. Another approach has been the use of custom built systems made up of "random logic" (i .e., logic gates, flip-flops, counters, etc.). However, the huge expense and development time involved in the design and debugging of these systems has restricted their use to large volume applications where the development costs could be spread over a large number of machines. Today, Intel offers the systems designer a new alternative ... the microcomputer. Utilizing the technologies and experience gained in becoming the world's largest supplier of LSI memory components, Intel has made the power of the digital computer available at the integrated circuit level. Using the n-channel silicon gate MOS process, Intel engineers have implemented the fast (2/ls. cycle) and powerful (72 basic instructions) 8080 microprocessor on a single LSI chip. When this processor is combined with memory and I/O circuits, the computer is complete. Intel offers a variety of random-access memory (RAM), read-only memory (ROM) and shift register circu~ts, that combine with the 8080 processor to form the MCS-80 microcomputer system, a system that can directly address and retrieve as many as 65,536 bytes stored in the memory devices. The 8080 processor is packaged in a 40-pin dual in-line package (DIP) that allows for remarkably easy interfacing. The 8080 has a 16-bit address bus, a 8-bit bidirectional data bus and fully decoded, TTL-compatible control outputs. In addition to supporting up to 64K bytes of mixed RAM and ROM memory, the 8080 can address up to 256 input ports and 256 output ports; thus allowing for virtually unlimited system expansion. The 8080 instruction set includes conditional branching, decimal as well as binary arithmetic, logical, register-to-register, stack control and memory reference instructions. In fact, the 8080 instruction set is powerful enough to rival the performance of many of the much higher priced minicomputers, yet the 8080 is upward software compatible with Intel's earlier 8008 microprocessor (Le., programs written for the 8008 can be assembled and executed on the 8080). In addition to an extensive instruction set oriented to problem solving, the 8080 has another significant featureSPEED. In contrast to random logic designs which tend to work in parallel, the microcomputer works by sequentially executing its program. As a result of this sequential execution, the number of tasks a microcomputer can undertake in a given period of time is directly proportional to the execution speed of the microcomputer. The speed of execution is the limiting factor of the realm of applications of the microcomputer. The 8080, with instruction times as short as 2 /lsec., is an order of magnitude faster than earlier generations of microcomputers, and therefore has an expanded field of potential applications. The architecture of the 8080 also shows a significant improvement over earlier microcomputer designs. The 8080 contains a 16-bit stack pointer that controls the addressing of an external stack located in memory. The pointer can be initialized via the proper instructions such that any portion of external memory can be used as a last in/first out stack; thus enabling almost unlimited subroutine nesting. The stack pointer allows the contents of the program counter, the accumulator, the condition flags or any of the data registers to be stored in or retrieved from the external stack. In addition, multi-level interrupt processing is possible using the 8080's stack control instructions. The status of the processor can be "pushed" onto the stack when an interrupt is accepted, then "popped" off the stack after the interrupt has been serviced. This ability to save the contents of the processor's registers is possible even if an interrupt service routine, itself, is interrupted. CONVENTIONAL SYSTEM Product definition System and logic design Debug Done with logic diagrams Done with conventional Lab Instrumentation PC card layout Documentation Cooling and packaging Power distribution Engineering changes PROGRAMMED LOGIC Simpl ified because of ease of incorporating features Can be programmed with design aids (compilers, assemblers, editors) Software and hardware aids reduce time Fewe r cards to layout Less hardware to document Reduced system size and power consumption eases job Less power to distribute Change program Done with yellow wire Table 0-1. The Advantages of Using Microprocessors of the logical control functions formerly performed by numerous hardware components can now be implemented in a few ROM circuits which are non-volatile; that is, the contents of ROM will never be lost, even in the event of a power failure. Table 0-1 summarizes many of the advantages of using microcomputers. ADVANTAGES OF DESIGNING WITH MICROCOMPUTERS Microcomputers simplify almost every phase of product development. The first step, as in any product development program, is to identify the various functions that the end system is expected to perform. Instead of realizing these functions with networks of gates and flip-flops, the functions are implemented by encoding suitable sequences of instructions (programs) in the memory elements. Data and certain types of programs are stored in RAM, while the basic program can be stored in ROM. The microprocessor performs all of the system's functions by fetching the instructions in memory, executing them and communicating the results via the microcomputer's I/O ports. An 8080 microprocessor, executing the programmed logic stored in a single 2048-byte ROM element, can perform the same logical functions that might have previously required up to 1000 logic gates. MICROCOMPUTER DESIGN AIDS If you're used to logic design and the idea of designing with programmed logic seems like too radical a change, regardless of advantages, there's no need to worry because Intel has already done most of the groundwork for you. The INTELLEC® 8 Development Systems provide flexible, inexpensive and simplified methods for OEM product development. The INT~LLEC@ 8 provides RAM program storage making program loading and modification easier, a display and control console for system monitoring and debugging, a standard TTY interface, a PROM programming capability and a standard software package (System Monitor, Assembler and Test Editor). In addition to the standard software package available with the INTELLEC® 8, Intel offers a PL/MTcompiler, a cross-assembler and a simulator written in FORTRAN IV and designed to run on any large scale computer. These programs may be procured directly from Intel or from a number of nationwide computer time-sharing services. Intel's Microcomputer Systems Group is always available to provide assistance in every phase of your product development. The benefits of designing a microcomputer into your system go far beyond the advantages of merely simplifying product development. You will also appreciate the profitmaking advantages of using a microcomputer in place of custom-designed random logic. The most apparent advantage is the significant savings in hardware costs. A microcomputer chip set replaces dozens of random logic elements, thus reducing the cost as well as the size of your system. In addition, production costs drop as the number of individual components to be handled decreases, and the number of complex printed circuit boards (which are difficult to layout, test and correct) is greatly reduced. Probably the most profitable advantage of a microcomputer is its flexibility for change. To modify your system, you merely re-program the memory elements; you don't have to redesign the entire system. You can imagine the savings in time and money when you want to upgrade your product. Reliability is another reason to choose the microcomputer over random logic. As the number of components decreases, the probability of a malfunctioning element likewise decreases. All Intel also provides complete documentation on all their hardware and software products. In addition to this User's Manual, there are the: • • • • • ii PL/M'~Language Reference Manual 8080 Assembly Language Programming Manual INTELLEC®8/MOD 80 Operator's Manual INTELLEC®8/MOD 80 Hardware Reference Manual 8080 User's Program Library APPLICATIONS EXAMPLE the control unit (as shown in Figure 0-1), the only "custom" logic will be that of the interface circuits. These circuits are usually quite simple, providing electrical buffering for the input and output signals. The 8080 can be used as the basis for a wide variety of calculation and control systems. The system configurations for particular applications will differ in the nature of the peripheral devices used and in the amount and the type of memory required. The applications and solutions described in this section are presented primarily to show how microcomputers can be used to solve design problems. The 8080 should not be considered limited either in scope or performance to those applications listed here. Instead of drawing state diagrams leading to logic, the system designer now prepares a flow chart, indicating which input signals must be read, what processing and computations are needed, and what output signa Is must be produced. A program is written from the flow chart. The program is then assembled into bit patterns which are loaded into the program memory. Thus, this system is customized primarily by the contents of program memory. Consider an 8080 microcomputer used within an automatic computing scale for a supermarket. The basic machine has two input devices: the weighing unit and a keyboard, used for function selection and to enter the price per unit of weight. The only output device is a display showing the total price, although a ticket printer might be added as an optional output device. For this automatic scale, the program would probably reside in read-only memory (ROM), since the microcomputer would always execute the same program, the one which implements the scale functions. The processor would constantly monitor the keyboard and weighing unit, and update the display whenever necessary. The unit would require very little data memory; it would only be needed for rate storage, intermediate results, and for storing a copy of the display. The control unit must accept weight information from the weighing unit, function and data inputs from the keyboard, and generate the display. The only arithmetic function to be performed is a simple multiplication of weight times rate. When the control portion of a product is implemented with a microcomputer chip set, functions can be changed and features added merely by altering the program in memory. With a TTL based system, however, alterations may require extensive rewiring, alteration of PC boards, etc. The control unit could probably be realized with standard TTL logic. State diagrams for the various portions could be drawn and a multiplier unit designed. The whole design could then be tied together, and eventually reduced to a selection of packages and a printed circuit board layout. In effect, when designing with a logic family such as TTL, the designs are "customized" by the choice of packages and the wiring of the logic. The number of applications for microcomputers is limited only by the depth of the designer's imagination. We have listed a few potential applications in Table 0-2, along with the types of peripheral devices usually associated with each product. If, however, an 8080 microcomputer is used to realize / / - KEYBOARD 000 000 000 000 WEIGHING UNIT PRINTER 00 00 00 00 00 INPUT INTERFACE #1 --- .. 1':II':II':~I':ff':'1 I II II II II I 1 1 CIJ DISPLAY T INPUT INTERFACE #2 OUTPUT INTERFACE #1 + I r - - -I- - I I , OPTIONAL OUTPUT INTERFACE #2 I I I I ' - - - T T - - -J 8080 CPU CONTROL UNIT I+I ItI 1+ BUS It[ ItI DATA MEMORY (RAM) PROGRAM MEMORY (PROM) Figure 0-1. Microcomputer Application - Automatic Scale iii t I I I I I L..-- APPLICATION PERIPHERAL DEVICES ENCOUNTERED Intelligent Terminals Cathode Ray Tube Display Printing Units Synchronous and Asynchronous data lines Cassette Tape Unit Keyboards Gaming Machines Keyboards, push buttons and switches Various display devices Coin acceptors Coin dispensers Cash Registers Keyboard or Input Switch Array Change Dispenser Digital Display Ticket Printer Magnetic Card reader Communication interface Accounting and Billing Machines Keyboard Printer Unit Cassette or other magnetic tape unit "Floppy" disks Telephone Switching Control Telephone Line Scanner Analog Switching Network Dial Registers Class of Service Parcel Numerically Controlled Machines Magnetic or Paper Tape Reader Stepper Motors Optical Shaft Encoders Process Control Ana log-to-D igita I Converters Digital-to-Analog Converters Control Switches Displays Table 0-2. Microprocessor Applications iv This chapter introduces certain basic computer concepts. It provides background information and definitions which will be useful in later chapters of this manual. Those already familiar with computers may skip this material, at their option. peripheral storage device, such as a floppy disk unit, or the output may constitute process control signals that direct the operations of another system, such as an automated assembly line. Like input ports, output ports are addressable. The input and output ports together permit the processor to communicate with the outside world. A TYPICAL COMPUTER SYSTEM The CPU unifies the system. It controls the functions performed by the other components. The CPU must be able to fetch instructions from memory, decode their binary contents and execute them. It must also be able to reference memory and I/O ports as necessary in the execution of instructions. In addition, the CPU should be able to recognize and respond to certain external control signals, such as INTERRUPT and WAIT requests. The functional units with in a CPU that enable it to perform these functions are described below. A typical digital computer consists of: a) A central processor unit (CPU) b) A memory c) Input/output (I/O) ports The memory serves as a place to store Instructions, the coded pieces of information that direct the activities of the CPU, and Data, the coded pieces of information that are processed by the CPU. A group of logically related instructions stored in memory is referred to as a Program. The CPU "reads" each instruction from memory in a logically determined sequence, and uses it to initiate processing actions. If the program sequence is coherent and logical, processing the program will produce intelligible and useful results. THE ARCHITECTURE OF A CPU A typical central processor unit (CPU) consists of the following interconnected functional units: • Registers • Arithmetic/Logic Unit (ALU) • Control Circuitry The memory is also used to store the data to be manipulated, as well as the instructions that direct that manipulation. The program must be organized such that the CPU does not read a non-instruction word when it expects to see an instruction. The CPU can rapidly access any data stored in memory; but often the memory is not large enough to store the entire data bank required for a particular application. The problem can be resolved by providing the computer with one or more Input Ports. The CPU can address these ports and input the data contained there. The addition of input ports enables the computer to receive information from external equipment (such as a paper tape reader or floppy disk) at high rates of speed and in large volumes. \ Registers are temporary storage units within the CPU. Some registers, such as the program counter and instruction register, have dedicated uses. Other registers, such as the accumulator, are for more general purpose use. Accumulator: The accumulator usually stores one of the operands to be manipulated by the ALU. A typical instruction might direct the ALU to add the contents of some other register to the contents of the accumulator and store the result in the accumulator itself. In general, the accumulator is both a source (operand) and a destination (result) register. A computer also requires one or more Output Ports that permit the CPU to communicate the result of its processing to the outside world. The output may go to a display, for use by a human operator, to a peripheral device that produces "hard-copy," such as a line-pri nter, to a Often a CPU will include a number of additional general purpose registers that can be used to store operands or intermediate data. The availability of general purpose 1-1 cessor loads the address specified in the Call into its Program Counter. The next instruction fetched will therefore be the first step of the subroutine. registers eliminates the need to "shuffle" intermediate results back and forth between memory and the accumulator, thus improving processing speed and efficiency. The last instruction in any subroutine is a Return. Such an instruction need specify no address. When the processor fetches a Return instruction, it simply replaces the current contents of the Program Counter with the address on the top of the stack. This causes the processor to resume execution of the calling program at the point immediately foUowing the original Call Instruction. Program Counter (Jumps, Subroutines and the Stack): The instructions that make up a program are stored in the system's memory. The central processor references the contents of memory, in order to determine what action is appropriate. This means that the processor must know which location contains the next instruction. Subroutines are often Nested; that is, one subroutine will sometimes call a second subroutine. The second may call a third, and so on. This is perfectly acceptable, as long as the processor has enough capacity to store the necessary return addresses, and the logical provision for doing so. In other words, the maximum depth of nesting is determined by the depth of the stack itself. If the stack has space for storing three return addresses, then three levels of subroutines may be accommodated. Each of the locations in memory is numbered, to distinguish it from all other locations in memory. The number which identifies a memory location is called its Address. The processor maintains a counter which contains the address of the next program instruction. This register is called the Program Counter. The processor updates the program counter by adding "1" to the counter each time it fetches an instruction, so that the program counter is always current (pointing to the next instruction). Processors have different ways of maintaining stacks. Some have facilities for the storage of return addresses built into the processor itself. Other processors use a reserved area of external memory as the stack and simply maintain a Pointer register which contains the address of the most recent stack entry. The external stack allows virtually unlimited subroutine nesting. In addition, if the processor provides instructions that cause the contents of the accumulator and other general purpose registers to be "pushed" onto the stack or "popped" off the stack via the address stored in the stack pointer, multi-level interrupt processing (described later in this chapter) is possible. The status of the processor (i.e., the contents of all the registers) can be saved in the stack when an interrupt is accepted and then restored after the interrupt has been serviced. This ability to save the processor's status at any given time is possible even if an interrupt service routine, itself, is interrupted. The programmer therefore stores his instructions in numerically adjacent addresses, so that the lower addresses contain the first instructions to be executed and the higher addresses contain later instructions. The only time the programmer may violate this sequential rule is when an instruction in one section of memory is a Jump instruction to another section of memory. A jump instruction contains the address of the instruction which is to follow it. The next instruction may be stored in any memory location, as long as the programmed jump specifies the correct address. During the execution of a jump instruction, the processor replaces the contents of its program counter with the address embodied in the Jump. Thus, the logical continuity of the program is ma.intained. A special kind of program jump occurs when the stored program "Calls" a subroutine. In this kind of jump, the processor is required to "remember" the contents of the program counter at the time that the jump occurs. This enables the processor to resume execution of the main program when it is finished with the last instruction of the subroutine. Instruction Register and Decoder: Every computer has a Word Length that is characteristic of that machine. A computer's word length is usually determined by the size of its internal storage elements and interconnecting paths (referred to as Busses); for example, a computer whose registers and busses can store and transfer a bits of information has a characteristic word length of 8-bits and is referred to as an a-bit parallel processor. An eight-bit parallel processor generally finds it most efficient to deal with eight-bit binary fields, and the memory associated with such a processor is therefore organized to store eight bits in each addressable memory location. Data and instructions are stored in memory as eight-bit binary numbers, or as numbers that are integral multiples of eight bits: 16 bits, 24 bits, and so on. This characteristic eight-bit field is often referred to as a Byte. A Subroutine is a program within a program. Usually it is a general-purpose set of instructions that must be executed repeatedly in the course of a main program. Routines which calculate the square, the sine, or the logarithm of a program variable are good examples of functions often written as subroutines. Other examples might be programs designed for inputting or outputting data to a particular peripheral device. The processor has a special way of handling subroutines, in order to insure an orderly return to the main program. When the processor receives a Call instruction, it increments the Program Counter and stores the counter's contents in a reserved memory area known as the Stack. The Stack thus saves the address of the instruction to be executed after the subroutine is completed. Then the pro- Each operation that the processor can perform is identified by a unique byte of data known as an Instruction 1-2 performs the arithmetic and logical operations on the binary data. Code or Operation Code. An eight-bit word used as an instruction code can distinguish between 256 alternative actions, more than adequate for most processors. The ALU must contain an Adder which is capable of combining the contents of two registers in accordance with the logic of binary arithmetic. This provision permits the processor to perform arithmetic manipulations on the data it obtains from memory and from its other inputs. The processor fetches an instruction in two distinct operations. First, the processor transmits the address in its Program Counter to the memory. Then the memory returns the addressed byte to the processor. The CPU stores this instruction byte in a register known as the Instruction Register, and uses it to direct activities during the remainder of the instruction execution. Using only the basic adder a capable programmer can write routines which will subtract, multiply and divide, giving the machine complete arithmetic capabilities. In practice, however, most ALUs provide other built-in functions, including hardware subtraction, boolean logic operations, and sh ift capabi Iities. The mechanism by which the processor translates an instruction code into specific processing actions requires more elaboration tha~ we can here afford. The concept, however, should be intuitively clear to any logic designer. The eight bits stored in the instruction register can be decoded and used to selectively activate one of a number of output lines, in this case up to 256 lines. Each line represents a set of activities associated with execution of a particular instruction code. The enabled line can be combined w\th selected timing pulses, to develop electrical signals that can then be used to initiate specific actions. This translation of code into action is performed by the Instruction Decoder and by the associated control circu itry. The ALU contains Flag Bits which specify certain conditions that arise in the course of arithmetic and logical manipulations. 'Flags typically include Carry, Zero, Sign, and Parity. It is possible to program jumps which are conditionally dependent on the status of one or more flags. Thus, for example, the program may be designed to jump to a special routine if the carry bit is set following an addition instruction. Control Circuitry: An eight-bit instruction code is often sufficient to specify a particular processing action. There are times, however, when execution of the instruction requires more information than eight bits can convey. The control circuitry is the primary functional unit within a CPU. Using clock inputs, the control circuitry maintains the proper sequence of events required for any processing task. After an instruction is fetched and decoded, the control circuitry issues the appropriate signals (to units both internal and external to the CPU) for initiating the proper processing action. Often the control circuitry will be capable of responding to external signals, such as an interrupt or wait request. An Interrupt request will cause the control circuitry to temporarily interrupt main program execution, jump to a special routine to service the interrupting device, then automatically return to the main program. A Wait request is often issued by a memory or I/O element that operates slower than the CPU. The control circuitry will idle the CPU until the memory or I/O port is ready with the data. One example of this is when the instruction references a memory location. The basic instruction code identifies the operation to be performed, but cannot specify the object address as well. In a case like this, a two- or threebyte instruction must be used. Successive instruction bytes are stored in sequentially adjacent memory locations, and the processor performs two or three fetches in succession to obtain the full instruction. The first byte retrieved from memory is placed in the processor's instruction register, and subsequent bytes are placed in temporary storage; the processor then proceeds with the execution phase. Such an instruction is referred to as Variable Length. Address Register(s): COMPUTER OPERATIONS A CPU may use a register or register-pair to hold the address of a memory location that is to be accessed for data. If the address register is Programmable, (Le., if there are instructions that allow the programmer to alter the contents of the register) the program can "build" an address in the address register prior to executing a Memory Reference instruction (Le., an instruction that reads data from memory, writes data to memory or operates on data stored in memory). There are certain operations that are basic to almost any computer. A sound understanding of these basic operations is a necessary prerequisite to examining the specific operations of a particular computer. Timing: The activities of the central processor are cyclical. The processor fetches an instruction, performs the operations required, fetches the next instruction, and so on. This orderly sequence of events requires precise timing, and the CPU therefore requires a free running oscillator clock which furnishes the reference for all processor actions. The combined fetch and execution of a single instruction is referred to as an Instruction Cycle. The portion of a cycle identified Arithmetic/Logic Unit (ALU): All processors contain an arithmetic/logic unit, which is often referred to simply as the ALU. The ALU, as its name implies, is that portion of the CPU hardware which 1-3 with a clearly defined activity is called a State. And the interval between pulses of the timing oscillator is referred to as a Clock Period. As a general rule, one or more clock periods are necessary for the completion of a state, and there are several states in a cycle. had time to respond, it frees the processor's READY line, and the instruction cycle proceeds. Input/Output: Input and Output operations are similar to memory read and write operations with the exception that a peripherall/O device is addressed instead of a memory location. The CPU issues the appropriate input or output control signal, sends the proper device address and either receives the data being input or sends the data to be output. Instruction Fetch: The first state(s) of any instruction cycle will be dedicated to fetching the next instruction. The CPU issues a read signal and the contents of the program counter are sent to memory, which responds by returning the next instruction word. The first byte of the instruction is placed in the instruction register. If the instruction consists of more than one byte, additional states are required to fetch each byte of the instruction. When the entire instruction is present in the CPU, the program counter is incremented (in preparation for the next instruction fetch) and the instruction is decoded. The operation specified in the instruction will be executed in the remaining states of the instruction cycle. The instruction may call for a memory read or write, an input or output and/or an internal CPU operation, such as a register-to-register transfer or an add-registers operation. Data can be input/output in either parallel or serial form. All data within a digital computer is represented in binary coded form. A binary data word consists of a group of bits; each bit is either a one or a zero. Parallel I/O consists of transferring all bits in the word at the same time, one bit per line. Serial I/O consists of transferring one bit at a time on a single line. Naturally serial I/O is much s.lower, but it requires considerably less hardware than does parallel I/O. Interrupts: Interrupt. provIsions are included on many central processors, as a means of improving the processor's efficiency. Consider the case of a computer that is processing a large volume of data, portions of which are to be output to a printer. The CPU can output a byte of data within a single machine cycle but it may take the printer the equivalent of many machine cycles to actually print the character specified by the data byte. The CPU could then remain idle waiting until the printer can accept the next data byte. If an interrupt capability is implemented on the computer, the CPU can output a data byte then return to data processing. When the printer is ready to accept the next data byte, it can request an interrupt. When the CPU acknowledges the interrupt, it suspends main program execution and automatically branches to a routine that will output the next data byte. After the byte is output, the CPU continues with main program execution. Note that this is, in principle, quite similar to a subroutine call, except that the jump is initiated externally rather than by the program. Memory Read: An instruction fetch is merely a special memory read operation that brings the instruction to the CPU's instruction register. The instruction fetched may then call for data to be read from memory into the CPU. The CPU again issues a read signal and sends the proper memory address; memory responds by returning the requested word. The data received is placed in the accumulator or one of the other general purpose registers (not the instruction register). Memory Write: A memory write operation is similar to a read except -for the direction of data flow. The CPU issues a write signal, sends the proper memory address, then sends the data word to be written into the addressed memory location. Wait (memory synchronization): More complex interrupt structures are possible, in which several interrupting devices share the same processor but have different priority levels. Interruptive processing is an important feature that enables maximum untilization of a processor's capacity for high system throughput. As previously stated, the activities of the processor are timed by a master clock oscillator. The clock period determines the timing of all processing activity. The speed of the processing cycle, however, is limited by the memory's Access Time. Once the processor has sent a read address to memory, it cannot proceed until the memory has had time to respond. Most memories are capable of responding much faster than the processing cycle requires. A few, however, cannot supply the addressed byte within the minimum time established by the processor's clock. Hold: Another important feature that improves the throughput of a processor is the Hold. The hold provision enables Direct Memory Access (DMA) operations. In ordinary input and output operations, the processor itself supervises the entire data transfer. Information to be placed in memory is transferred from the input device to the processor, and then from the processor to the designated memory location. In similar fashion, information that goes Therefore a processor should contain a synchronization provision, which permits the memory to request a Wait state. When the memory rec.eives a read or write enable signal, it places a request signal on the processor's READY line, causing the CPU to idle temporarily. After the memory has 1-4 _... from memory to output devices goes by way of the processor. having the device accomplish the transfer directly. The processor must temporarily suspend its operation during such a transfer, to prevent conflicts that would arise if processor and peripheral device attempted to access memory simultaneously. It is for this reason that a hold provision is included on some processors. Some peripheral devices, however, are capable of transferring information to and from memory much faster than the processor itself can accomplish the transfer. If any appreciable quantity of data must be transferred to or from such a device, then system throughput will be increased by 1-5 The 8080 is a complete 8-bit parallel, central processor unit (CPU) for use in general purpose digital computer systems. It is fabricated on a single LSI chip (see Figure 2-1). using Intel's n-channel silicon gate MaS process. The 8080 transfers data and internal state information via an 8-bit, bidirectional 3- state Data Bus (00-07). Memory and peripheral device addresses are transmitted over a separate 16- bit 3-state Address Bus (AO-A 15). Six timing and control outputs (SYNC, DBIN, WAIT,WR, HLDA and INTE) emanate from the 8080, while four control inputs (READY, HOLD, INT and RESET), four power inputs (+12v, +!5v, -5v, and GND) and two clock inputs (<1>1 and <1>2) are accepted by the 8080. A,O 1 40 A" GNO 2 39 A14 A'3 A'2 04 3 38 Os 4 37 0 6 0.-.5 36 35 34 07 03 6 7 O2 8 0,0 9 10 DO 0 Figure 2-1.8080 Photomicrograph With Pin Designations 2-1 INTE~ 8080 33 32 o A,s o Ag As o A7 A6 As 31 o A4 -5V RESET 11 12 30 29 A3 HOLD 13 28 +12V INT 14 27 A2 ¢2 15 26 A, INTE 0 25 Ao DBIN 0 16 17 24 WAIT WR 18 23 READY SYNC 19 22 tp, +5V 20 21 HLOA ARCHITECTURE OF THE 8080 CPU matically during every instruction fetch. The stack pointer maintains the address of the next available stack location in memory. The stack pointer can be initialized to use any portion of read-write memory as a stack. The stack pointer is decremented when data is "pushed" onto the stack and incremented when data is "popped" off the stack (Le., the stack grows "downward"). The 8080 CPU consists of the following functional units: • Register array and address logic • Arithmetic and logic unit (ALU) • Instruction register and control section • Bi-directional, 3-state data bus buffer Figure 2-2 illustrates the functional blocks within the 8080 CPU. The six general purpose registers can be used either as single registers (8-bit) or as register pairs (16-bit). The temporary register pair, W,Z, is not program addressable and is only used for the internal execution of instructions. Registers: Eight-bit data bytes can be transferred between the internal bus and the register array via the register-select multiplexer. Sixteen-bit transfers can proceed between the register array and the address latch or the incrementer/ decrementer circu it. The address latch receives data from any of the three register pairs and drives the 16 address output buffers (AO-A 15), as well as the incrementer/ decrementer circuit. The incrementer/decrementer circuit receives data from the address latch and sends it to the register array. The 16-bit data can be incremented or decremented or simply transferred between registers. The register section consists of a static RAM array organized into six 16-bit registers: • Program counter (PC) • Stack pointer (SP) • Six 8-bit general purpose registers arranged in pairs, referred to as S,C; D,E; and H,L • A temporary register pair called W,Z The program counter maintains the memory address of the current program instruction and is incremented auto- 81-01 RECTIONAL DATA BUS ... 0 INSTRUCTION DECODER AND MACHINE CYCLE ENCODING (8) W TEMP REG. B REG. (8) C REG. (8) 0 (8) E REG. (8) (8) L REG. (8) w ..J w en REG. ...enw H REG. a: a w a: (8) Z TEMP REG. STACK POINTER (16) (16) PROGRAM COUNTER POWER SUPPLI ES .. 1-" +12V ---. +5V ---. -5V ---. GND DATA BUS INTERRUPT HOLD WAIT WRITE CONTROL CONTROL CONTROL CONTROL SYNC CLOCKS RESET ACK Figure 2-2. 8080 CPU Functional Block Diagram 2-2 A 15 -Ao ADDRESS BUS REGISTER ARRAY THE PROCESSOR CYCLE Arithmetic and Logic Unit (ALU): An instruction cycle is defined as the time required to fetch and execute an instruction. During the fetch, a selected instruction (one, two or three bytes) is extracted from memory and deposited in the CPU's instruction register. During the execution phase, the instruction is decoded and translated into specific processing activities. The ALU contains the following registers: • An 8-bit accumulator • An 8-bit temporary accumulator (ACT) • A 5-bit flag register: zero, carry, sign, parity and auxiliary carry Every instruction cycle consists of one, two, three, four or five machine cycles. A machine cycle is required each time the CPU accesses memory or an I/O port. The fetch portion of an instruction cycle requires one machine cycle for each byte to be fetched. The duration of the execution portion of the instruction cycle depends on the kind of instruction that has been fetched. Some instructions do not require any machine cycles other than those necessary to fetch the instruction; other instructions, however, require additional machine cycles to write or read data to/ from memory or I/O devices. The DAD instruction is an exception in that it requires two additional machine cycles to complete an internal register-pair add (see Chapter 4). • An 8-bit temporary register (TMP) Arithmetic, logical and rotate operations are performed in the ALU. The ALU is fed by the temporary register (TMP) and the temporary accumulator (ACT) and carry flip-flop. The result of the operation can be transferred to the internal bus or to the accumulator; the ALU also feeds the flag register. The temporary register (TMP) receives information from the internal bus and can send all or portions of it to the ALU, the flag register and the internal bus. Each machine cycle consists of three, four or five states. A state is the smallest unit of processing activity and is defined as the interval between two successive positive~ going transitions of the ¢1 driven clock pulse. The 8080 is driven by a two-phase clock oscillator. All processing activities are referred to the period of th is clock. The two nonoverlapping clock pulses, labeled ¢1 and cP2, are furnished by external circuitry. It is the cPl clock pulse which divides each machine cycle into states. Timing logic within the 8080 uses the clock inputs to produce a SYNC pulse, which identifies the beginning of every machine cycle. The SYNC pulse is triggered by the low-to-high transition of cP2, as shown in Figure 2-3. The accumulator (ACC) can be loaded from the ALU and the internal bus and can transfer data ~o the temporary accumulator (ACT) and the internal bus. The contents of the accumulator (ACC) and the auxiliary carry flip-flop can be tested for decimal correction during the execution of the DAA instruction (see Chapter 4). Instruction Register and Control: During an instruction fetch, the first byte of an instruction (containing the OP code) is transferred from the internal bus to the 8-bit instruction register. The contents of the instruction register are, in turn, available to the instruction decoder. The output of the decoder, combined with various timing signals, provides the control signals for the register array, ALU and data buffer blocks. In addition, the outputs from the instruction decoder and external control signals feed the timing and state control section which generates the state and cycle timing signals. FIRST STATE OF *EVERY MACHINE CYCLE 4>1 SYNC Data Bus Buffer: *SYNC DOES NOT OCCUR IN THE SECOND AND THIRD MACHINE CYCLES OF A DAD INSTRUCTION SINCE THESE MACHINE CYCLES ARE USED FOR AN INTERNAL REGISTER-PAIR ADD. This 8-bit bidirectional 3-state buffer is used to isolate the CPU's internal bus from the external data bus. (DO through 07). In the output mode, the internal bus content is loaded into an 8-bit latch that, in turn, drives the data bus output buffers. The output buffers are switched off during input or non-transfer operations. Figure 2-3.1>1,2. HALT. INTERRUPT The machine cycles that actually do occur in a particular instruction cycle depend upon the kind of instruction, with the overriding stipulation that the first machine cycle in any instruction cycle is always a FETCH. The processor identifies the machine cycle in progress by transmitting an eight-bit status word during the first state of every machine cycle. Updated status information is presented on the 8080's data lines (00-07), during the SYNC interval. This data should be saved in latches, and used to develop control signals for external circuitry. Table 2-1 shows how the positive-true status information is distributed on the processor's data bus. The rising edge of ¢2 during T 1 also loads the processor's address lines (AO-A 15). These lines become stable within a brief delay (tDA) of the cP2 clocking pulse, and they remain stable until the first ¢2 pulse after state T3. Th is gives the processor ample time to read the data returned from memory. Once the processor has sent an address to memory, there is an opportunity for the memory to request a WAIT. This it does by pulling the processor's READY line low, prior to the "Ready set-up" interval (tRS) which occurs during the (/)2 pulse within state T2 or TW. As long as the REAOY line remains low, the processor will idle, giving the memory time to respond to the addressed data request. Refer to Figure 2-5. Status signals are provided principally for the control of external circuitry. Simplicity of interface, rather than machine cycle identification, dictates the logical definition of individual status bits. You will therefore observe that certain processor machine cycles are uniquely identified by a single status bit, but that others are not. The M1 status bit (06), for example, unambiguously identifies a FETCH machine cycle. A STACK REAO, on the other hand, is indicated by the coincidence of STACK and MEMR signals. Machine cycle identification data is also valuable in the test and de-bugging phases of system development. Table 2-1 lists the status bit outputs for each type of machine cycle. The processor responds to a wait request by entering an alternative state (TW) at the end of T2, rather than proceed ing directly to the T 3 state. Entry into the TW state is indicated by a WAIT signal from the processor, acknowledging the memory's request. A low-to-high transition on the WAIT line is triggered by the rising edge of the (/)1 clock and occurs within a brief delay (tOC) of the actual entry into the TW state. State Transition Sequence: Every machine cycle within an instruction cycle consists of three to five active states (referred to as T 1, T 2, T 3, T4, T5 or TW). The actual number of states depends upon the instruction being executed, and on the particular machine cycle within the greater instruction cycle. The state transition diagram in Figure 2-4 shows how the 8080 proceeds from state to state in the course of a machine cycle. The diagram also shows how the READY, HOLD, and INTERRUPT lines are sampled during the machine cycle, and how the conditions on these lines may modify the A wait period may be of indefinite duration. The processor remains in the waiting condition until its READY line again goes high. A READY indication must precede the failing edge of the (/)2 clock by a specified interval (tRS), in order to guarantee an exit from the TW state. The cycle may then proceed, beginning with the rising edge of the next (/)1 clock. A WAIT interval will therefore consist of an integral number of TW states and will always be a multiple of the clock period. 2-5 Instructions for the 8080 require from one to five machine cycles for complete execution. The 8080 sends out 8 bit of status informatton on the data bus at the beginning of each machine cycle (during SYNC time). The following table defines the status information. 8080 STATUS LATCH o o 0, o STATUS INFORMATION DEFINITION Data Bus Symbols Bit Definition INTA* 00 Acknowledge signal for INTERRUPT request. Signal should be used to gate a restart instruction onto the data bus when OBIN is active. 0, Indicates that the operation in the current machine cycle will be a WR ITE memory or OUTPUT function (WO = O).Otherwise, a REAO memory or INPUT operation will be executed. STACK Indicates that the address bus holds the pushdown stack address from the Stack Pointer. HLTA Acknowledge signal for HALT instruction. OUT I ndicates that the address bus contains the address of an output device and the data bus will contain the output data when WR is active. M, Provides a signal to indicate that the CPU is in the fetch cycle for the first byte of an instruction. INP* Indicates that the address bus contains the address of an input device and the input data shou Id be placed on the data bus when OB I N is active. MEMR* Designates that the data bus will be used 07 for memory read data. 10 9 8 2 7 03 3 04 4 05 5 8080 ~6 6 SYNC - 7 OBIN 01 19 ~ 02 22 STATUS LATCH 15 --2. 5 01 °2 CLOCK GEN. & DRIVER °3 °4 -- (olTTl) ~ r;; CLR OS2 MO T2 01 °6 SYNC STATUS *These three status bits can be used to control the flow of data onto the 8080 data bus. TYPE OF MACHINE CYCLE I INTA 02 STACK 03 04 OUT HLTA 06 INP 07 MEMR Table 2-1. 8080 Status Bit Definitions 2-6 ''---t--t-- ......-.----+001'----1 STATUS WORD CHART 17 OUT M1 ~ MEMR JL INP 13 12 1------ .lL. 8212 I ~ OAT A ~ INTA ~ W6 ~ STACK ~ HlTA 9 16 18 20 22 °5 DO DO ~ OS, Y1 I DBIN Till G)_RESET READY + HLTA (2) YES READY. HLTA NO ~~ READY -------------~ READY I... INT. INTE YES SET INTERNAL HOLD F/F SET INTERNAL HOLD F/F (3) I I I I (31 HOLD I HOLD I MODE I 7 I I ?~~---- I __ .J RESET INTERNAL HOLD F/F YES NO RESET HLTA NO HOLD NO RESET INTERNAL HOLD F/F SET INTERNAL INT F/F (1),NTE F/F IS RESET IF INTERNAL INT F/F IS SET. (2),NTERNAL INT F/F IS RESET IF INTE F/F IS RESET. (3)SEE PAGE 2-13. Figure 2-4. CPU State Transition Diagram 2-7 The events that take place during the T3 state are determined by the kind of machine cycle in progress. In a FETCH machine cycle, the processor interprets the data on its data bus as an instruction. During a MEMORY READ or a STACK READ, data on this bus is interpreted as a data word. The processor outputs data on this bus during a MEMORY WRITE machine cycle. During I/O operations, the processor may either transmit or receive data, depending on whether an OUTPUT or an INPUT operation is involved. data must remain stable during the "data hold" interval (tDH) that occurs following the rising edge of the1 n T2 , L.-J Figure 2-7 shows the timing of a machine cycle in wh ich the processor outputs data. Output data may be destined either for memory or for peripherals. The rising edge of 2 clock's leading edge. Data on the bus remains stable throughout the remainder of the machine cycle, until replaced by updated status information in the subsequent T 1 state. Observe that a READY signal is necessary for completion of an OUTPUT machine cycle. Unless such an indication is present, the processor enters the TW state, following the T2 state. Data on the output lines remains stable in the interim, and the processing cycle will not proceed until the READY line again goes high. sarily extend WR, in much the same way that DBrN is affected during data input operations. All processor mach ine cycles consist of at least three states: T 1, T2, and T3 as just described. If the processor has to wait for a response from the peripheral or memory with which it is communicating, then the machine cycle may also contain one or more TW states. During the three basic states, data is transferred to or from the processor. After the T3 state, however, it becomes difficult to generalize. T4 and TS states are available, if the execution of a particular instruction requires them. But not ·all machine cycles make use of these states. It depends upon the kind of instruction being executed, and on the particular machine cycle within the instruction cycle. The processor will terminate any mach ine cycle as soon as its processing activities are completed, rather than proceeding through the T4 and TS states every time. Thus the 8080 may exit a machine cycle following the T3, the T41 or the TS state and proceed directly to the T 1 state of the next mach ine cycle. The 8080 CPU generates a WR output for the synchronization of external transfers, during those machine cycles in which the processor outputs data. These include MEMORY WRITE, STACK WRITE, and OUTPUT. The negative-going leading edge of WR is referenced to the rising edge of the first 1 clock pulse following T2, and occurs within a brief delay (tDC) of that event. WR remains low until re-triggered by the leading edge of 1 during the state following T3. Note that any TW states intervening between T2 and T3 of the output machine cycle will neces- ASSOCIATED ACTIVITIES STATE A memory address or I/O device number is placed on the Address Bus (A 15-0); status information is placed on Data Bus (D7-0). The CPU samples the READY and HOLD inputs and checks for halt instruction. TW (optional) T3 An instruction byte (FETCH machine cycle), data byte (MEMORY READ, STACK READ) or interrupt instruction (INTERRUPT machine cycle) is input to the CPU from the Data Bus; or a data byte (MEMORY WRITE, STACK WR ITE or OUTPUT machine cycle) is output onto the data bus. T4 States T 4 and TS are available if the execution of a particular instruction requires them; if not, the CPU may skip one or both of them. T4 and TS are only used for internal processor operations. TS (optional) Table Processor enters wait state if READY is low or if HALT instruction has been executed. 2~2. State Definitions 2-10 INTERRUPT SEQUENCES In this way, the pre-interrupt status of the program counter is preserved, so that data in the counter may be restored by the interrupted program after the interrupt request has been processed. The 8080 has the built-in capacity to handle external interrupt requests. A peripheral device can initiate an interrupt simply by driving the processor's interrupt (INT) line high. The interrupt (INT) input is asynchronous, and a request may therefore originate at any time during any instruction cycle. Internal logic re-clocks the external request, so that a proper correspondence with the driving clock is established. As Figure 2-8 shows, an interrupt request (I NT) arriving during the time that the interrupt enable line (I NTE) is high, acts in coincidence with the ~2 clock to set the internal interrupt latch. This event takes place during the last state of the instruction cycle in wh ich the request occurs, thus ensuring that any instruction in progress is completed before the interrupt can be processed. The interrupt cycle is otherwise indistinguishable from an ordinary FETCH machine cycle. The processor itself takes no further special action. It is the responsibility of the peripheral logic to see that an eight-bit interrupt instruction is "jammed" onto the processor's data bus during state T3. In a typical system, this means that the data-in bus from memory must be temporarily disconnected from the processor's main data bus, so that the interrupting device can command the main bus without interference. The 8080's instruction set provides a special one-byte call which facilitates the processing of interrupts (the ordinary program Call takes three bytes). This is the RESTART instruction (RST). A variable three-bit field embedded in the eight-bit field of .the RST enables the interrupting device to direct a Call to one of eight fixed memory locations. The decimal addresses of these dedicated locations are: 0, 8, 16, 24, 32, 40, 48, and 56. Any of these addresses may be used to store the first instruction (s) of a routine designed to service the requirements of an interrupting device. Since the (RST) is a call, completion of the instruction also stores the old program counter contents on the STACK. The INTERRUPT machine cycle which follows the arrival of an enabled interrupt request resembles an ordinary FETCH machine cycle in most respects. The M1 status bit is transmitted as usual during the SYNC interval. It is accompanied, however, by an INTA status bit (DO) which acknowledges the external request. The contents of the program counter are latched onto the CPU's address lines during T 1, but the counter itself is not incremented during the INTERRUPT machine cycle, as it otherwise would be. T1 _n T2 n pc·, A1S-0 T1 \ \ --- -RST --- ~- I ~-- 1 - - (INTA) I T3 T2 T1 X sP·' X PCH SP·2 X X \ L- '---' -~ ,- \ INTE INT PCl rM I \ DBIN RETURN M1 (INTERNAL) T3 r--L LJl.LIl.J\. J\ U\Wl. Lr\.Jl..Jl. Do SYNC T2 rLrL-rL"-rL rL-rL- rLrL pc I Ts T4 T3 r~ _---r~U~~U M3 M2 M1 T3 I ~ INT F/F (INTERNAL) I \ INHIBIT STORE OF PC+1 (INTERNAL) I \ 0--- STATUS INFORMATION NOTE: ® X\@ Refer to Status Word Chart on Page 2-6. Figure 2-8. Interrupt Timing 2-11 A\@ Mn l--OR~ ¢l_n ¢2 n ~n i I : 1 I : I ! ! I I ~ \ ' i \ .- HOLD U ~ REQUEST OJ·O I I ~ n -+--sLJJlL-..rrL~LJLLJTLJJ\.lJL ! A'5·0 n ~ Mn +1 1 (1) I I I -:- - - - - - - - - -:- - - - - - - - FLOATING I .1 -I----------I----------......--~ -..II I I 1 : i HOLD ..... 1 1 I ' i i READY HOLD F/F INTERNAL -+- +--_J --+- HLDA I (1) *T4 AND T5 OPERATION CAN BE DONE INTERNALLY. SEE ATTACHED ELECTRICAL CHARACTERISTICS. I I Figure 2-9. HOLD Operation (Read Mode) Mn T3 n _V\ A'5·0 T, T4 n T2 M n+1 M n+2 T3 T, n n n n L.-ILL.-IL -L.-ILL.-IL--F\...--F\... L.....JLL.-IL I - ----- - - j X I ,--- ----- --yX I FLOATING I ~----- I -~--~ I HOLD REQUEST n \ -U I HOLD \ READY ! HOLD F/F INTERNAL I HLDA WRITE DATA Figure 2-10. HOLD Operation (Write Mode) 2-12 I HOLD SEQUENCES The SOSOA CPU contains provisions for Direct Memory Access (DMA) operations. By applying a HO LD to the appropriate control pin on the processor, an external device can cause the CPU to suspend its normal operations and relinquish control of the address and data busses. The processor responds to a request of this kind by floating its address to other devices sharing the busses. At the same time, the processor acknowledges the HO LD by placing a high on its HLDA outpin pin. During an acknowledged HOLD, the address and data busses are under control of the peripheral which originated the request, enabling it to conduct memory transfers without processor intervention. returns to a low level following the leading edge of the next ¢1 clock pulse. Normal processing resumes with the machine cycle following the last cycle that was executed. HALT SEQUENCES When a halt instruction (H LT) is executed, the CPU enters the ha It state (TWH) after state T 2 of the next machine cycle, as shown in Figure 2-11. There are only three ways in which the 8080 can exit the halt state: • A high on the RESET line will always reset the 8080 to state T 1; RESET also clears the program counter. • A HOLD input will cause the 8080 to enter the hold state, as previously described. When the HOLD line goes low, the 8080 re-enters the halt state on the rising edge of the next ¢1 clock pulse. • An interrupt (Le., INT goes high while INTE is enabled) will cause the 8080 to exit the Halt state and enter state T 1 on the rising edge of the next ¢1 clock pulse. NOTE: The interrupt enable (INTE) flag must be set when the halt state is entered; otherwise, the 8080 will only be able to exit via a RESET signal. Like the interrupt, the HO LD input is synchronized internally. A HOLD signal must be stable prior to the "Hold set-up" interval (tHS), that precedes the rising edge of 1 DO eJ>2 01 02 WAIT 03 READY 04 RESET SYNC Clock Generator and High Level Driver 05 06 07 STATUS STROBE 25 AO 26 Al 27 A2 29 A3 30 A4 31 AS 32 A6 33 A7 34 A8 35 1 Al0 40 All 37 A12 38 ~13 39 A14 36 A15 18 17 21 10 9 8 7 3 4 BI-DIRECTIONAL BUS DRIVER 5 6 SYSTEM CONTROL Figure 3-2. 8080 CPU Interface 3-2 ADDRESS BUS A9 DATA BUS OSCILLATOR ~ 20MHz 330 330 ~""""--01 >-......- - - - - - - - - - - -.......- - - - - - - -.... OSC 74S04 CLOCK GENERATOR 7486 DB OB 74163 DC OC . . . . . . . - - . . . - - - - - - - ' 7486 GND--+-~ 1 0 - - + - - - - - - - - -. . 4>2 (TTL) AUXILIARY FUNCTIONS r-----IIIIII---- SYNC 74HOO '----........--410 74S74 WAVEFORMS ----u 4>1 ---f 1~~~ 4>2 --' 50ns~ 4>1A SYNC t+- ---I u ~50ns \ --.f 250ns r- , ClK ------41---1 50ns , READY ClK I , ---1' a 0 tf>1A (TTL) 74574 '~_ _ , 250ns WA IT REO -Ir- 0.......-..-.-----.. a DMAREO--~----IID \ HOLD 74S74 ClK ,\,.-_---1' Figure 3-3. 8080 Clock Generator positive transition when biased from the 8080 Voo supply (12V) but to achieve the low voltage specification (V ILC ) .8 volts Max. the driver is biased to the 8080 Vss supply (-5V). This allows the driver to swing from GND to Vo o with the aid of a simple resistor divider. 20 MHZ oscillator, a four bit counter, and gating circuits. The oscillator provides a 20 MHZ signal to the input of a four (4) bit, presettable, synchronous, binary counter. By presetting the counter as shown in figure 3-3 and clocking it with the 20 MHZ signal, a simple decoding of the counters outputs using standard TTL gates, provides proper timing for the two (2) 8080 clock inputs. A low resistance series network is added between the driver and the 8080 to eliminate any overshoot of the pulsed waveforms. Now a circuit is apparent that can easily comply with the 8080 specifications. I n fact rise and falltimes of this design are typically less than 10 ns. Note that the timing must actually be measured at the output of the High Level Driver to take into account the added delays and waveform distortions within such a device. +12V High Level Driver Design The voltage level of the clocks for the 8080 is not TTL compatible like the other signals that input to the 8080. The voltage swing is from .6 volts (VILC ) to 11 volts (VIHC ) with risetimes and falltimes under 50 ns. The Capacitive Drive is 20 pf (max.). Thus, a High Level Driver is required to interface the outputs of the Clock Generator (TTL) to the 8080. 6 6S0pF cf>1 (TTL) ---1 47n 2 MH0026 OR 680 pF ¢2 (TTL)-) cf>1 (SOSO PIN 22) 4 EQUIV. 5 47n ¢2 (8080 PIN 15) 3 15K .68 J.LF The two (2) outputs of the Clock Generator are capacitivity coupled to a dual- High Level clock driver. The driver must be capable of complying with the 8080 clock input specifications, page 5-15. A driver of this type usually has little problem supplying the 100n -5V Figure 3-4. High Level Driver 3-3 15K 3. Auxiliary Timing Signals and Functions Bi-Directional Bus Driver and System Control Logic The Clock Generator can also be used to provide other signals that the designer can use to simplify large system timing or the interface to dynamic memories. The system Memory and I/O devices communicate with the CPU over the bi-directional Data Bus. The system Control Bus is used to gate data on and off the Data Bus within the proper timing sequences as dictated by the operation of the 8080 CPU. The data lines of the 8080 CPU, Memory and I/O devices are 3-state in nature, that is, their output drivers have the ability to be forced into a high-impedance mode and are, effectively, removed from the circuit. This '3state bus technique allows the designer to construct a system around a single, eight (8) bit parallel, bi-directional Data Bus and simply gate the information on or off this bus by selecting or deselecting (3-stating) Memory and I/O devices with signals from the Control Bus. Functions such as power-on reset, synchronization of external requests (HOLD, READY, etc.) and single step, could easily be added to the Clock Generator to further enhance its capabilities. For instance, the 20 MHZ signal from the oscillator can be buffered so that it could provide the basis for communication baud rate generation. The Clock Generator diagram also shows how to generate an advanced timing signal (l/>1A) that is handy to use in clocking "0" type flipflops to synchronize external requests. It can also be used to generate a strobe (STSTB) that is the latching signal for the status information which is available on the Data Bus at the beginning of each machine cycle. A simple gating of the SYNC signal from the 8080 and the advanced (l/>1A) will do the job. See Figure 3-3. Bi-Directional Data Bus Driver Design The 8080 Data Bus (07-00) has two (2) major areas of concern for the designer: 1. Input Voltage level (V1H ) 3.3 volts minimum. 2. Output Drive Capability (tOL) 1.7 rnA maximum. BUSEN - 2,4 DO 5,7 01 rr- 3 6 8216 9,11r- 02 10 12,14r- 03 13 OlEN CS 15? 04 05 3 r- 6 8216 9,11r- 06 10 12,14r- 07 ~I OBIN 3 - 5 7 9 16 -68 ?1 STACK - 17 M1 191NP 21 MEMR 20 22 12 [13 Q.»-- WO -10 HLTA -15 OUT 8212 18 ------!1 STSTB CS 4 INTA I....-- 808 0 13 OlEN 15)' ..., ~ Q.»-- c=[y-- Vee - WR -I ...... 1 ...... - --(>0.-=0-- Figure 3-5. 8080 System Control 3-4 OB2 OB3 «1 2,4] 5,7 OBO OB1 OB4 DB5 DB6 DB7 The input level specification impl ies that any semiconductor memory or I/O device connected to the 8080 Data Bus must be able to provide a minimum of 3.3 volts in its high state. Most semiconductor memories and standard TTL I/O devices have an output capability of between 2.0 and 2.8 volts, obviously a direct connection onto the 8080 Data Bus would require pullup resistors, whose value should not affect the bus speed or stress the drive capability of the memory or I/O components. Status information. The signal that loads the data into the Status Latch comes from the Clock Generator, it is Status Strobe (STSTB) and occurs at the start of each Machine Cycle. Note that the Status Latch is connected onto the SOSO Data Bus (07-00) before the Bus Buffer. This is to maintain the integrity of the Data Bus and simplify Control Bus timing in DMA dependent environments.. As shown in the diagram, a simple gating of the outputs of the Status Latch with the DB INand WR signals from the S080 generate the (4) four Control signals that make up the basic Control Bus. The 80S0A output drive capability (lOl) 1.9mA max. is sufficient for small systems where Memory size and I/O requirements are minimal and the entire system is contained on a single printed circuit board. Most systems however, take advantage of the high-performance computing power of the 8080 CPU and thus a more typical system would require some form of buffering on the 80S0 Data Bus to support a larger array of Memory and I/O devices which are likely to be on separate boards. These four signals: 1. Memory Read (MEM R) 2. Memory Write (MEM W) 3. I/O Read (I/O R) 4. I/O Write (I/O W) A device specifically designed to do this buffering function is the INTEL® 8216, a (4) four bit bi-directional bus driver whose input voltage level is compatible with standard TTL devices and semiconductor memory components, and has output drive capability of 50 mAo At the 8080 side, the 8216 has a "high" output of 3.65 volts that not only meets the S080 input spec but provides the designer with a worse case 350 mV noise margin. TM connect directly to the MCS-80 component "family" of ROMs, RAMs and I/O devices. A fifth signal, Interrupt Acknowledge (lNTA) is added to the Control Bus by gating data off the Status Latch with the DBIN signal from the S080 CPU. This signal is used to enable the Interrupt Instruction Port wh ich holds the RST instruction onto the Data Bus. A pair of S216's are connected directly to the 8080 Data Bus (07-00) as shown in figure 3-5. Note that the OBI N signal from the 8080 is connected to the direction control input (01 EN) so the correct flow of data on the bus is maintained. The chip select (CS) of Other signals that are part of the Control Bus such as WO, Stack and M1 are present to aid in the testing of the System and also to simplify interfacing the CPU to dynamic memories or very large systems that require several levels of bus buffering. the S216 is connected to BUS ENABLE (BUSEN) to allow for DMA activities by deselecting the Data Bus Buffer and forcing the outputs of the S216's into their high impedance (3-state) mode. This allows other devices to gain access to the data bus (DMA). Address Buffer Design System Control Logic Design The Address Bus (A 15-AO) of the 8080, like the Data Bus, is sufficient to support a small system that has a moderate size Memory and I/O structure, confined to a single card. To expand the size of the system that the Address Bus can support a simple buffer can be added, as shown in figure 3-6. The INTEL®S212 or 8216 is an excellent device for this function. They provide low input loading (.25 mA), high output drive and insert a minimal delay in the System Timing. The Control Bus maintains discipline of the bi-directional Data Bus, that is, it determines what type of device will have access to the bus (Memory or I/O) and generates signals to assure that these devices transfer Data with the SOSO CPU within the proper timing "windows" as dictated by the CPU operational characteristics. As described previously, the 8080 issues Status information at the beginning of each Machine Cycle on its Data Bus to indicate what operation will take place during that cycle. A simple (8) bit latch, like an INTEL® 8212, connected directly to the 80S0 Data Bus (07-00) as shown in figure 3-5 will store the Note that BUS ENABLE (BUSEN) is connected to the buffers so that they are forced into their highimpedance (3-state) mode during DMA activities so that other devices can gain access to the Address Bus. 3-5 INTERFACING THE 8080 CPU TO MEMORY AND I/O DEVICES This feature eliminates the need for extra equipment like tape readers and disks to load programs initially, an important aspect in small system design. The 8080 interfaces with standard semiconductor Memory components and I/O devices. In the previous text the proper control signals and buffering were developed which will produce a simple bus system similar to the basic system example shown at the beginning of this chapter. In Figure 3-6 a simple, but exact 8080' typical system is shown that can be used as a guide for any 8080 system, regardless of size or complexity. It is a "three bus" architecture, using the signals developed in the CPU module. Interfacing standard ROMs, such as the devices shown in the diagram is simple and direct. The output Data lines are connected to the bi-directional Data Bus, the Address inputs tie to the Address bus with possible decoding of the most significant bits as chip selects" a~d the MEMR signal from the Control Bus connected to a "chip select" or data buffer. Basically, the CPU issues an address during the first portion of an instruction or data fetch (Tl & T2). This value on the Address Bus selects a specific location within the ROM, then depending on the ROM's delay (access time) the data stored at the addressed location is present at the Data output lines. At this time (T3) the CPU Data Bus is in the "input Mode" and the control logic issues a Memory Read command (MEMR) that gates the addressed data on to the Data Bus. II Note that Memory and I/O devices interface in the same manner and that their isolation is only a function of the definition of the Read-Write signals on the Control Bus. This allows the 8080 system to be configured so that Memory and I/O are treated as a single array (memory mapped I/O) for small systems that require high thruput and have less than 32K memory size. This approach will be brought out later in the chapter. RAM INTERFACE A RAM is a device that stores data. This data can be program, active "look-up tables," temporary values or external stacks. The difference between RAM and ROM is that data can be written into such devices and are in essence, Read/Write storage elements. RAMs do not hold their data when power is removed so in the case where Program or "look-up tables" data is stored a method to load ROM INTERFACE A ROM is a device that stores data in the form of Program or other information such as "look-up tables" and is only read from, thus the term Read Only Memory. This type of memory is generallY' non-volatile, meaning that when the power is removed the information is retained. HOLD REO WR DO-D7DBIN HLDA AO-A15 !r-:- -- -----"1 I 8212 II I 8205 lL.83..1~ ADDRESS BUFFERSI DECODER I I (OP~I£.N~~..J 8702A 8704 ROMs 8708 8302 8101-2 8308 8111·2 RAMs 8316A 8102-2 5101 DATA BUS (8) u {} D"---_~rl {[- DL...-.--_n '0 _ _ _LCJJ~)7 8251 I/O COMMUNICATION INTERFACE CONTROL BUS (6) I ADDRESS BUS (16) 8212 8255 Figure 3-6. Microcomputer System 3-6 I/O PERIPHERAL INTERFACE 8214 8212 PRIORITY INTERRUPT 8102A·4 8107B·4 8210 8222 o::=c The memories chosen for this example have an access time of 850 nS (max) to illustrate that slower, economical devices can be easily interfaced to the 8080 with little effect on performance. When the 8080 is operated from a clock generator with a tCY of 500 nS the required memory access time is Approx. 450-550 nS. See detailed timing specification Pg. 5-16. Using memory devices of this speed such as Intel@8308, 8102A, 8107A, etc. the READY input to the· 8080 CPU can remain "high" because no "wait" states are required. Note that the bus interface to memory shown in Figure 3-7 remains the same. However, if slower memories are to be used, such as the devices illustrated (8316A, 8111) that have access times slower than the minimum requirement a simple logic control of the READY input to the 8080 CPU will insert an extra "wait state" that is equal to one or more clock periods as an access time "adjustment" deiay to compensate. The effect of the extra "wait" state is naturally a slower execution time for the instruction. A single "wait" changes the basic instruction cycle to 2.5 microSeconds. RAM memory must be provided, such as: Floppy Disk, Paper Tape, etc. The CPU treats RAM in exactly the same manner as ROM for addressing data to be read. Writing data is very similar; the RAM is issued an address during the first portion of the Memory Write cycle (T1 & T2) in T3 when the data that is to be written is output by the CPU and is stable on the bus an MEMW command is generated. The MEMW signal is connected to the R/W input of the RAM and strobes the data into the addressed location. In Figure 3-7 a typical Memory system is illustrated to show how standard semiconductor components interface to the 8080 bus. The memory array shown has 8K bytes • ® (8 bits/byte) of ROM storage, uSing four Intel 8216As and 512 bytes of RAM storage, using Intel 8111 static RAMs. The basic interface to the bus structure detailed here is common to almost any size memory. The only addition that might have to be made for larger systems is more buffers (8216/8212) and decoders (8205) for generating "chip selects." 8K + 512 o 8K ROM RAM MEMORY MAP ROM -----------, RAM ----------.... #4.:.#3;;. ........... ..-. #2 #1 8111 8111 FiJW 00 1/0 1-4 R/W 00 AO-A7 1/01-4 AO-A7 AO-A7 8316A CS3 CS2 01-08 AO-Al0 AllA12 _01.--_0 _-.-ill DATA BUS IsiJL.-..--_IJL--.------L----_DL---- CONTROL BUS (6) ADDRESS BUS (16) Figure 3-7. Typical Memory Interface 3-7 n 11_ I/O INTERFACE General Theory MEMR } __ As in any computer based system, the 8080 CPU must be able to communicate with devices or structures that exist outside its normal memory array. Devices like keyboards, paper tape, floppy disks, printers, displays and other control structures are used to 'input information into the 8080 CPU and display or store the results of the computational activity. TO MEMORY DEVICES ~----MEMW SYSTEM CONTROL (8228) I/OR } TO I/O DEVICES ~----I/OW Probably the most important and strongest feature of the 8080 Microcomputer System is the flexibility and power of its I/O structure and the components that support it. There are many ways to structure the I/O array so that it will "fit" the total system environment to maximize efficiency and minimize component count. Figure 3-9. Isolated I/O. Memory Mapped I/O By assigning an area of memory address space as I/O a powerful architecture can be developed that can manipulate I/O using the same instructions that are used to manipulate memory locations. Thus, a "new" instruction set is created that is devoted to I/O handling. The basic operation of the I/O structure can best be viewed as an array of single byte memory locations that can be Read from or Written into. The 8080 CPU has special instructions devoted to managing such transfers (IN, OUT). These instructions generally isolate memory and I/O arrays so that memory address space is not effected by the I/O structure and the general concept is that of a simple transfer to or from the Accumulator with an addressed "PORT". Another method of I/O architecture is to treat the I/O structure as part of the Memory array. This is generally referred to as "Memory Mapped I/O" and provides the designer with a powerful new "instruction set" devoted to I/O manipulation. As shown in Figure 3-10, new control signals are generated by gating the MEMR and MEMW signals with A15, the most significant address bit. The new I/O control signals connect in exactly the same manner as Isolated I/O, thus the system bus characteristics are unchanged. By assigning A15 as the I/O "flag", a simple method of I/O discipline is maintained: If A 15 is a "zero" then Memory is active. If A 15 is a "one" then I/O is active. ISOLATED I/O ~--------------------I 1 T! ME;;RY ~6 o Other address bits can also be used for this function. A 15 was chosen because it is the most significant address bit so it is easier to control with software and because it still allows memory addressing of 32K. : c:=J I/O devices are still considered addressed II ports" but instead of the Accumulator as the only transfer medium any of the internal registers can be used. All instructions that could be used to operate on memory locations can be used in I/O. iI r--------------------- j ! I I ~ MEMORY T MEMORY MAPPED I/O I/O T! Examples: MOVr, M MOV M, r MVI M LOA STA JI Figure 3-8. Memory/I/O Mapping. LHLO SHLO Isolated I/O ADD M ANAM In Figure 3-9 the system control signals, previously detailed in this chapter, are shown. Thi~ type of I/O architecture separates the memory address space from the I/O address space and uses a conceptually simple transfer to or from Accumulator technique. Such an architecture is easy to understand because I/O communicates only with the Accumulator using the IN or OUT instructions. Also because of the isolation of memory and I/O, the full address space (65K) is uneffected by I/O addressing. (I nput Port to any Register) (Output any Register to Port) (Output immediate data to Port) (I nput to ACC) (Output from ACC to Port) (1 ~ Bit Input) (16 Bit Output) (Add Port to ACC) ("AND" Port with ACC) It is easy to see that from the list of possible "new" instructions that this type of I/O architecture could have a drastic effect on increased system throughput. It is conceptually more difficult to understand than Isolated I/O and it does limit memory address space, but Memory Mapped I/O can mean a significant increase in overall speed and at the same time reducing re~uired program memory area. 3-8 10--------...--r>-----.---+---- MEMR MEMW } TO MEMORY DEVICES SYSTEM CONTROL (8228) I/OR} NOT USED _ IIOW I/O R (MMJTO I/O DEVICES I/OW (MM) The second example uses Memory Mapped I/O and linear select to show how thirteen devices (8255) can be addressed without the use of extra decoders. The format shown could be the second and third bytes of the LDA or STA instructions or any other instructions used to manipulate I/O using the Memory Mapped technique. It is easy to see that such a flexible I/O structure, that can be "tailored" to the overall system environment, provides the designer with a powerful tool to optimize efficiency and minimize component count. EXAMPLE #2 Figure 3-10. Memory Mapped I/O. I/O Addressing With both systems of I/O structure the addressing of each device can be configured to optimize efficiency and reduce component count. One method, the most common, is to decode the address bus into exclusive "chip selects" that enable the addressed I/O device, similar to generating chipselects in memory arrays. } PORT SELECTS } DEVICE SELECTS '-- Another method is called "Iinear select". In this method, instead of decoding the Address Bus, a singular bit from the bus is assigned as the exclusive enable for a specific I/0 device. This method, of course, limits the number of I/O devices that can be addressed but eliminates the need for extra decoders, an important consideration in small system design. DEVICE SELECTS A simple example illustrates the power of such a flexible I/O structure. The first example illustrates the format of the second byte of the IN or 0 UT instruction usi ng the Isolated I/O technique. The devices used are Intel®8255 Programmable Peripheral Interface units and are linear selected. Each device has three ports and from the format it can be seen that six devices can be addressed without additional decoders. " ' - - - - - - - - - - - - 1/0 FLAG I = I/O 0= MEMORY ADDRESSES -13 - 82555 (39 PORTS - 312 BITS) Figure 3-12. Memory Mapped I/O - (Linear Select (8255) EXAMPLE #1 I/O Interface Example '-- } PORT SELECTS } DEVICE SELECTS In Figure 3-16 a typical I/O system is shown that uses a variety of devices (8212, 8251 and 8255). It could be used to interface the peripherals around an intelligent CRT terminals; keyboards, display, and communication interface. Another application could be in a process controller to interface sensors, relays, and motor controls. The limitation of the application area for such a circuit is solely that of the designers imagination. The I/O structure shown interfaces to the 8080 CPU using the bus architecture developed previously in this chapter. Either Isolated or Memory Mapped techniques can be used, depending on the system I/O environment. ADDRESSES - 6 - 82555 (18 PORTS -144 BITS) The 8251 provides a serial data communication interface so that the system can transm it and receive data over communication links such as telephone lines. Figure 3-11. Isolated I/O - (Linear Select) (8255) 3-9 The three 8212s can be used to drive long lines or LED indicators due to their high drive capability. (15mA) O-DATA 1-COMMAND C/DCONTROL _____________________ 8251SELECT (ACTIVE LOW) ________________________ 8212 #1 SE LECT (ACTIVE HIGH) _ _ _ _ _ _ _ _ _ _ _ 8212 #2 SELECT (ACTIVE HIGH) _ _ _ _ _ _ _ _ _ _ _ _ _ 8212 #3 SELECT (ACTIVE HIGH) Figure 3-13. 8251 Format. The two (2) 8255s provide twenty four bits each of programmable I/O da~a and control so that keyboards, sensors, paper tape, etc., can be interfaced to the system. Figure 3-15. 8212 Format. OO-PORTA 01-PORTB 10 -PORTC 11-COMMAND } '--- "------- Addressing the structure is described in the formats illustrated in Figures 3-13, 3-14, 3-15. Linear Select is used so that no decoders are requ ired thus, each device has an exclusive "enable bit". PORT SELECT 8255 #1 SELECT (ACTIVE LOW) The example shows how a powerful yet flexible I/O structure can be created using a minimum component count with devices that are all members of the 8080 Microcomputer System. 8(~g::~~i~E~;r Figure 3..14. 8255 Format. SERIAL DATA COMMUNICATION #2 8255 8251 D~.Do #1 8255 cs Ao A, DATA BUS CONTROL BUS 8212 #2 8212 #3 8212 #1 MD MD Figure 3-16. Typical I/O Interface. 3-10 MD A computer, no matter how sophisticated, can only do what it is "told" to do. One "tells" the computer what to do via a series of coded instructions referred to as a Program. The realm of the programmer is referred to as Software, in contrast to the Hardware that comprises the actual computer equipment. A computer's software refers to all of the programs that have been written for that computer. are programs available which convert the programming language instructions into machine code that can be interpreted by the processor. One type of programming language is Assembly language. A unique assembly language mnemonic is assigned to each of the computer's instructions. The programmer can write a program (called the Source Program) using these mnemonics and certain operands; the source program is then converted into machine instructions (called the Object Code). Each assembly language instruction is converted into one machine code instruction (1 or more bytes) by an Assembler program. Assembly languages are usually machine dependent (Le., they are usually able to run on only one type of computer). When a computer is designed, the engineers provide the Central Processing Unit (CPU) with the ability to perform a particular set of operations. The CPU is designed such that a specific operation is performed when the CPU control logic decodes a particular instruction. Consequently, the operations that can be performed by a CPU define the computer's Instruction Set. Each computer instruction allows the programmer to initiate the performance of a specific operation. All computers implement certain arithmetic operations in their instruction set, such as an instruction to add the contents of two registers. Often logical operations (e.g., 0 R the contents of two registers) and register operate instructions (e.g., increment a register) are included in the instruction set. A computer's instruction set will also have instructions that move data between registers, between a register and memory, and between a register and an I/O device. Most instruction sets also provide Conditional Instructions. A conditional ·instruction specifies an operation to be performed only if certain conditions have been met; for example, jump to a particular instruction if the result of the last operation was zero. Conditional instructions provide a program with a decision-making capability. THE 8080 INSTRUCTION SET The 8080 instruction set includes five different types of instructions: • Data Transfer Group-move data between registers or between memory and registers • Arithmetic Group - add, subtract, increment or decrement data in registers or in memory • logical Group - AND, OR, EXCLUSIVE-OR, compare, rotate or complement data in registers or in memory • Branch Group - conditional and unconditional jump instructions, subroutine call instructions and return instructions By logically organizing a sequence of instructions into a coherent program, the programmer can "tell" the computer to perform a very specific and useful function. • Stack, I/O and Machine Control Group - includes I/O instructions, as well as instructions for maintaining the stack and internal control flags. The computer, however, can only execute programs whose instructions are in a binary coded form (Le.,· a series of 1's and D's), that is called Machine Code. Because it would be extremely cumbersome to program in machine code, programming languages have been developed. There Instruction and Data Formats: Memory for the 8080 is organized into 8-bit quantities, called Bytes. Each byte has a unique 16-bit binary address corresponding to its sequential position in memory. 4-1 The 8080 can directly address up to 65,536 bytes of memory, which may consist of both read-only memory (ROM) elements and random-access memory (RAM) elements (read/ write memory). address where the data is located (the high-order bits of the address are in the first register of the pair, the low-order bits in the second). • Oata in the 8080 is stored in the form of 8-bit binary integers: OATA WORO I 07 I 06 1 05 1 04 I 03 1 02 I MSB D1 I 00 I Unless directed by an interrupt or branch instruction, the execution of instructions proceeds through consecutively increasing memory locations. A branch instruction can specify the address of the next instruction to be executed in one of two ways: LSB When a register or data word contains a binary number, it is necessary to establish the order in which the bits of the number are written. In the Intel 8080, BIT 0 is referred to as the Least Significant Bit (LSB), and BIT 7 (of an 8 bit number) is referred to as the Most Significant Bit (MSB). The 8080 program instructions may be one, two or three bytes in length. Multiple byte instructions must be stored in successive memory locations; the address of the first byte is always used as the address of the instructions. The exact instruction format will depend on the particular operation to be executed. Si ngle Byte Instructions 1_0_7_' Byte Two I ' I o Op Code I_ 0_.......J I D7 I I Do Oata or -,- - - - - - - - - - - - - , Address I I) I I_D_7_1 1_0 0 Op Code Byte Two I 1 I Do I I Do D7 I Byte Three D7 Direct - The branch instruction contains the address of the next instruction to be executed. (Except for the 'RST' instruction, byte 2 contains the low-order address and byte 3 the high-order address.) • Register indirect - The branch instruction indicates a register-pair which contains the address of the next instruction to be executed. (The high-order bits of the address are in the first register of the pair, the low-order bits in the second.) Condition Flags: There are five condition flags associated with the execution of instructions on the 8080. They are Zero, Sign, Parity, Carry, and Aux iIiary Carry, and are each represented by a l-bit register in the CPU. A flag is "set" by forcing the bit to 1; "reset" by forcing the bit to O. Three-Byte Instructions Byte One • The RST instruction is a special one-byte call instruction (usually used during interrupt sequences). RST includes a three-bit field; program control is transferred to the instruction whose address is eight times the contents of this three-bit field. Two-Byte Instructions Byte One Immediate - The instruction contains the data itself. This is either an 8-bit quantity or a 16-bit quantity (least significant byte first, most significant byte second). Oata or Unless indicated otherwise, when an instruction affects a flag, it affects it in the following manner: Address Zero: If the result of an instruction has the value 0, this flag is set; otherwise it is reset. Sign: If the most significant bit of the result of the operation has the value 1, this flag is set; otherwise it is reset. Parity: If the modulo 2 sum of the bits of the result of the operation is 0, (Le., if the result has even parity), this flag is set; otherwise it is reset (Le., if the result has odd parity). Carry: If the instruction resulted in a carry (from addition), or a borrow (from subtraction or a comparison) out of the highorder bit, th is flag is set; otherwise it is reset. Addressing Modes: Often the data that is to be operated on is stored in memory. When multi-byte numeric data is used, the data, like instructions, is stored in successive memory locations, with the least significant byte first, followed by increasingly significant bytes. The 8080 has four different modes for addressing data stored in memory or in registers: • Oirect - Bytes 2 and 3 of the instruction contain the exact memory address of the data item (the low-order bits of the address are in byte 2, the high-order bits in byte 3). • Register - The instruction specifies the register or register-pair in wh ich the data is located. • Register Indirect - The instruction specifies a register-pair which contains the memory 4-2 Auxiliary Carry: If the instruction caused a carry out of bit 3 and into bit 4 of the resulting value, the auxiliary carry is set; otherwise it is reset. This flag is affected by single precision additions, subtractions, increments, decrements, comparisons, and logical operations, but is principally used with additions and increments preceding a DAA (Decimal Adjust Accumulator) instruction. Symbols and Abbreviations: The following symbols and abbreviations are used in the subsequent description of the 8080 instructions: SYMBOLS MEANING accumulator Register A addr 16-bit address quantity data 8-bit data quantity data 16 16-bit data quantity byte 2 The second byte of the instruction byte 3 The third byte of the instruction port 8-bit address of an I/O device r,rl,r2 DDD,SSS rl The second (low-order) register of a designated register pair. PC 16-bit program counter register (PCH and PCl are used to refer to the high-order and low-order 8 bits respectively). SP 16-bit stack pointer register (SPH and SPL are used to refer to the high-order and loworder 8 bits respectively). rm Bit m of the register r (bits are number 7 through a from left to right). Z,S,P,CY,AC The condition flags: Zero, Sign, Parity, Carry, and Auxiliary Carry, respectively. ( ) The contents of the memory location or registers enclosed in the parentheses. "1 s transferred to" Logical AND One of the registers A,B,C,D,E,H,L V Inclusive OR The bit pattern designating one of the registers A,B,C,D,E,H,L (DDD=destination, SSS= source): + Addition 111 000 001 010 A all E H Exclusive 0 R Two's complement subtraction * REGISTER NAME Multiplication "Is exchanged with" The one's complement (e.g., (A)) B C D 100 101 a through 7 n The restart number NNN The binary representation 000 through 111 for restart number 0 through 7 respectively. L One of the register pairs: Description Format: B represents the B,C pair with B as the highorder register and C as the low-order register; The following pages provide a detailed description of the instruction set of the 8080. Each instruction is described in the following manner: D represents the D,E pair with D as the highorder register and E as the low-order register; 1. The MAC 80 assembler format, consisting of the instruction mnemonic and operand fields, is printed in BOLDFACE on the left side of the first line. H represents the H,L pair with H as the highorder register and L as the low-order register; SP represents register. RP The first (high-order) register of a designated register pair. /\ V DOD or SSS rp rh the 16-bit stack pointer 2. The name of the instruction is enclosed in parenthesis on the right side of the fi rst line. The bit pattern designating one of the register pairs B,D,H,SP: RP 00 01 10 11 3. The next line(s) contain a symbolic description of the operation of the instruction. REGISTER PAIR 4. This is followed by a narative description of the B-C D-E H-L SP operation of the instruction. 5. The following line(s) contain the binary fields and patterns that comprise the machine instruction. 4-3 6. The last four lines contain incidental information about the execution of the instruction. The number of machine cycles and states required to execute the instruction are listed first. If the instruction has two possible execution times, as in a Conditional Jump·, both times will be listed, separated by a slash. Next, any significant data addressing modes' (see Page 4-2) are listed. The last line lists any of the five Flags that are affected by the execution of the instruction. MVI r, data (Move Immediate) (r) ~ (byte 2) The content of byte 2 of the instruction is moved to register r. Data Transfer Group: This group of instructions transfers data to and from registers and memory. Condition flags are not affected by any instruction in this group. MOV r1, r2 (Move Register) MVI M, data (Move to memory immediate) ((H) (L)) ~ (byte 2) The content of byte 2 of the instruction is moved to the memory location whose address is in registers H and L. (r1)"'- (r2) The content of register r2 is moved to register r1. 0 I D I '.1 D I (r) S S f' Cyc·'es: States: Addressing: Flags: MOV r, M D . 1 5 register none I S \ o I 0 o 1 I 0 data Cycles: States: Addressing: Flags: (Move from memory) ~ 1 ' ((H) (L)) 3 10 immed.lreg. indirect none The content of the memory location, whose address is in registers Hand L, is moved to register r. 1 Cycles: States: Addressi ng: Flags: MOV M, r I I 0 2 7 LXI rp, data 16 (Load register pair immediate) (rh) ~ (byte 3), (rl) ~ (byte 2) Byte 3 of the instruction is moved into the high-order register (rh) of the register pair rp. Byte 2 of the instruction is moved into the low-order register (rl) of the register pair rp. reg. indirect none (Move to memory) ((H)(L))~ (r) o The content of register r is moved to the memory location whose address is in registers Hand L. o ' 1 I o I R 1 p I o I o I low-order data high-order data I Cycles: States: Addressing: Flags: Cycles: States: Addressing: Flags: 2 7 reg. indirect none 4-4 3 10 immediate none o I 1 SHLD addr (Store Hand L direct) ((byte 3) (byte 2)) ~ (L) ((byte 3)(byte 2) + 1) ~ (H) The content of register L is moved to the memory Jocation whose address is specified in byte 2 and byte 3. The content of register H is moved to the succeeding memory location. LOA addr (Load Accumulator direct) (A) ~ ((byte 3) (byte 2)) The content of the memory location, whose address is specified in byte 2 and byte 3 of the instruction, is moved to register A. o I 0 I 1 1 1 1 0 low-order addr I 1 I 1 I 0 0 I 0 I 1 I 0 I 0 T 0 T 1 I 0 high-order addr low-order addr Cycles: States: Addressing: Flags: 4 high-order addr 13 direct none Cycles: States: Addressing: Flags: 5 16 direct none LOAX rp (Load accumulator indirect) ((rp)) The content of the memory location, whose address is in the register pair rp, is moved to register A. Note: only register pairs rp=B (registers B and C·) or rp=D (registers D and E) may be specified. (A)~ STA addr (Store Accumulator direct) ((byte 3)(byte 2)) ~ (A) The content of the accumulator is moved to the memory location whose address is specified in byte 2 and byte 3 of the instruction. 0 I 0 I 1 I 1 I 0 I 0 I 1 r o I 0 I Cycles: States: Addressing: Flags: low-order addr high-order addr Cycles: States: Addressing: Flags: 4 13 dire<;t none LHLD addr (Load Hand L direct) (L) ~ ((byte 3)(byte 2)) (H) ~ ((byte 3) (byte 2) + 1) The content of the memory location, whose address is specified in byte 2 and byte 3 of the instruction, is moved to register L. The content of the memory location at the succeeding address is moved to register H. 1 0 I 1 I 0 XCHG I R 2 7 reg. indirect none (Exchange Hand L with D and E) (H)~(D) (L)~(E) I 1 T 0 The contents of registers Hand L are exchanged with the contents of registers D and E. low-order add r I high-order addr Cycles: States: Addressing: Flags: 0 Cycles: States: Addressing: Flags: f I 2 7 reg. indirect none STAX rp (Store accumulator indirect) ((rp)) ~ (A) The content of register A is moved to the memory location whose address is in the register pair rp. Note: only register pairs rp=B (registers B and C) or rp=D (registers D and E) may be specified. o I 0 I 0 I p R 0 5 1 I 0 Cycles: States: Addressing: Flags: 16 direct none 4-5 1 4 register none Arithmetic Group: ADC r (Add Register with carry) (A) ~ (A) + (r) + (CY) The content of register r and the content of the carry bit are added to the content of the accumulator. The result is placed in the accumulator. This group of instructions performs arithmetic operations on data in registers and memory. Unless indicated otherwise, all instructions in this group affect the Zero, Sign, Parity, Carry, and Auxiliary Carry flags accord ing to the standard rules. 1 I I 0 All ~ubtraction operations are performed via two's complement arithmetic and set the carry flag to one to indicate a borrow and clear it to indicate no borrow. ADD r ADC M + (r) I o I o o I Cycles: States: Addressing: Flags: I 0 I 0 register Z,S,P,CY,AC (Add memory with carry) The content of the memory location whose address is contained in the Hand L registers and the content of the CY flag are added to the accumulator. The result is placed in the accumulator. 0 1 o 4 register Z,S,P,CY ,AC Cycles: States: Addressing: Flags: ADD M (Add memory) (A)...- (A) + ((H) (L)) The content of the memory location whose address is contained in the Hand L registers is added to the content of the accumulator. The result is placed in the accumulator. 1 1 4 (A) ~ (A) + ((H) (L)) + (CY) The content of register r is added to the content of the accumulator. The result is placed in the accumulator. 1 o Cycles: States: Addressing: Flags: (Add Register) (A) ~ (A) 0 0 0 Cycles: States: Addressing: Flags: reg. indirect Z,S,P,CY,AC ACI data (Add immediate with carry) (A) ~ (A) + (byte 2) + (CY) The content of the second byte of the instruction and the content of the CY flag are added to the contents of the accumulator. The result is placed in the accumulator. 0 I 1 I 0 2 o o data 7 reg. indirect Z,S,P,CY ,AC Cycles: States: Addressing: Flags: ADI data (Add immediate) (A) ~ (A) + (byte 2) The content of the second byte of the instruction is added to the content of the accumulator. The result is placed in the accumulator. 1 I 1 I SUB r 2 7 immediate Z,S,P ,CY ,AC (Subtract Register) (A) ~ (A) - (r) The content of register r is subtracted from the content of the accumulator. The result is placed in the accumulator. 0 1 data Cycles: States: Addressing: Flags: 2 7 I 0 I 0 Cycles: States: Addressing: Flags: 2 7 immediate Z,S,P,CY,AC 4-6 0 i S I 1 4 register Z,S,P,CY,AC S I S SUB M (Subtract memory) SBI data (Subtract immediate with borrow) (A) ~ (A) - (byte 2) - (CY) The contents of the second byte of the instruction and the contents of the CY flag are both subtracted from the accumulator. The result is placed in the accumulator. (A) ~ (A) - ((H) (L)) The content of the memory location whose address is contained in the Hand L registers is subtracted from the content of the accumulator. The result is placed in the accumulator. o Cycles: States: Addressi ng: Flags: o 1 I I 0 o data 2 7 Cycles: States: Addressing: Flags: reg. indirect Z,S,P,CY,AC 2 7 immediate Z,S,P,CY,AC SUI data (Subtract immediate) (A) ~ (A) - (byte 2) The content of the second byte of the instruction is subtracted from the content of the accumulator. The result is placed in the accumulator. INR r (Increment Register) (r) ~ (r) + 1 The content of register r is incremented by one. Note: All condition flags except CY are affected. o SBB Cycles: States: Addressi ng: Flags: 2 Cycles: States: Addressing: Flags: 7 immediate Z,S,P,CY,AC r (Subtract Register with borrow) (A) - (r) - (CY) The content of register r and the content of the CY flag are both subtracted from the accumulator. The result is placed in the accumulator. (A) 1 I INR M ~ 0 I 0 S Cycles: States: Addressing: Flags: 1 D data I S I S 0 r I 0 1 5 register Z,S,P,AC (Increment memory) ((H) (L)) ~ ((H) (L)) + 1 The content of the memory location whose address is contained in the Hand L registers is incremented by one. Note: All condition flags except CY are affected. I o I 0 o o o 1 4 Cycles: States: Addressing: Flags: register Z,S,P,CY ,AC 3 10 reg. indirect Z,S,P,AC SBa M (Subtract memory with borrow) (A) ~ (A) - ((H) (L)) - (CY) The content of the memory location whose address is contained in the Hand L registers and the content of the CY flag are both subtracted from the accumulator. The result is placed in the accumulator. 1 I 0 , 0 1 I Cycles: States: Addressing: Flags: 1 I 1 I 0 OCR r (Decrement Register) (r) ~ (r)-1 The content of register r is decremented by one. Note: All condition flag~ except CY are affected. I 0 2 I 0 I D I D Cycles: States: Addressing: Flags: 7 reg. indirect Z,S,P,CY,AC 4-7 D I 1 1 5 register Z,S,P,AC I 0 I 1 .f' OCR M (Decrement memory) OAA ((H) (L)) . . - ((H) (L)) - 1 The content of the memory location whose address is contained in the Hand L registers is decremented by one. Note: All condition flags except CY are affected. Cycles: States: Addressing: Flags: (Decimal Adjust Accumulator) The eight-bit number in the accumulator is adjusted to form two four-bit Binary-Coded-Decimal digits by the following process: 3 1. If the value of the least significant 4 bits of the accumulator is greater than 9 or if the AC flag is set, 6 is added to the accumulator. 2. If the value of the most significant 4 bits of the accumulator is now greater than 9, or if the CY flag is set, 6 is added to the most significant 4 bits of the accumulator. 10 reg. indirect Z,S,P,AC NOTE: All flags are affected. o INX rp (Increment register pair) (rh) (rl) ..- (rh) (rl) + 1 The content of the register pair rp is incremented by one. Note: No condition flags are affected. Cycles: States: Addressing: Flags: Cycles: States: Flags: 1 4 Z,S,P,CY,AC Logical Group: 1 5 This group of instructions performs logical (Boolean) operations on data in registers and memory and on condition flags. register none Unless indicated otherwise, all instructions in this group affect the Zero, Sign, Parity, Auxiliary Carry, and Carry flags according to the standard rules. OCX rp (Decrement register pair) (rh) (rl) . . - (rh) (rl) - 1 The content of the register pair rp is decremented by one. Note: No condition flags are affected. I Cycles: States: Addressing: Flags: 0 I I ANA r (AND Register) (A) ~ (A) /\ (r) The content of register r is logically anded with the content of the accumulator. The result is placed in the accumulator. The CY flag is cleared. 1 a 1 5 register none Cycles: States: Addressing: Flags: DAD rp (Add register pair to Hand L) (H) (L) . . - (H) (L) + (rh) (rl) The content of the register pair rp is added to the content of the register pair Hand L. The result is placed in the register pair Hand L. Note: Only the CY flag is affected. It is set if there is a carry out of the double precision add; otherwise it is reset. . ANA M I s S 1 4 register Z,S,P,CY,AC (AND memory) (A) ~ (A) /\ ((H) (L)) The contents of the memory location whose address is contained in the Hand L registers is logically anded with the content of the accumulator. The result is placed in the accumulator. The CY flag is cleared. I Cycles: States: Addressing: Flags: Is 0 I 1 a Cycles: States: Addressing: Flags: 3 10 register CY 4-8 a I 1 , 1 2 7 reg. indirect Z,S,P,CY,AC I a ORA r (OR Register) (A) ~ (A) V (r) The content of register r is inclusive-OR'd with the content of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared. ANI data (AND immediate) (A) ~ (A) /\ (byte 2) The content of the second byte of the instruction is logicaJly anded with the contents of the accumu lator . The result is placed in the accumulator. The CY and AC flags are cleared. I 1 o I 0 I 1 I 1 I I 0 2 7 immediate Z,S,P,CY ,AC ORA M (A) V ((H) (L)) The content of the memory location whose address is contained in the Hand L registers is inclusive-OR'd with the content of the accumu lator. The result is placed in the accumulator. The CY and AC flags are cleared. register Z,S,P,CY,AC I o Cycles: States: Addressing: Flags: 0 . CMP r 1 I 0 7 reg. indirect Z,S,P ,CY ,AC 2 7 immediate Z,S,P,CY,AC (Compare Register) (A) (r) The content of register r is subtracted from the accumulator. The accumulator remains unchanged. The condition flags are set as a result of the subtraction. The Z flag is set to 1 if (A) = (r). The CY flag is set to 1 if (A) (r) . < 1 _1__0_ I data Cycles: States: Addressing: Flags: I 2 Cycles: States: Addressing: Flags: reg. indirect Z,S,P,CY,AC 1 1 data 7 _1_ o I 1 1 1 2 0_ _ 1--..1_ _ ' I ORI data (OR Immediate) (A) ~ (A) V (byte 2) The content of the second byte of the instruction is inclusive-OR'd with the content of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared. XRI data (Exclusive OR immediate) (A) ~ (A) V (byte 2) The content of the second byte of the instruction is exclusive-O R'd with the content of the accumu lator. The result is placed in the accumulator. The CY and AC flags are cleared. . 1~_1_1~ 1 Cycles: States: Addressing: Flags: 1 4 XRA M (Exclusive OR Memory) (A) ~ (A) V ((H) (L)) The content of the memory location whose address is contained in the Hand L registers is exclusive-O R'd with the content of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared. 0 register Z,S,P,CY,AC (OR memory) I a I I 1 4 ~ (A) XRA r (Exclusive OR Register) (A) ~ (A) V (r) The content of register r is exclusive-or'd with the content of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared. Cycles: States: Addressing: Flags: 1 Cycles: States: Addressing: Flags: data Cycles: States: Addressing: Flags: I I 0 2 0 I 1 Cycles: States: Addressing: Flags: 7 immediate Z,S,P ,CY ,AC 4-9 1 4 register Z,S,P,CY,AC CMP M (A) (Compare memory) RRC ((H) (L)) The content of the memory location whose address is contained in the Hand L registers is subtracted from the accumulator. The accumulator remains unchanged. The condition flags are set as a result of the subtraction. The Z flag is set to 1 if (A) = ((H) (L)). The CY flag is set to 1 if (A) < ((H) (L)). (Rotate right) (An) ~ (A n -,); (A7) ~ (AO) (CY) ~ (AO) The content of the accumu lator is rotated right one position. The high order bit and the CY flag are both set to the value shifted out of the low order bit position. Only the CY flag is affected. 0 o o Cycles: States: Addressing: Flags: 0 I 0 I 2 7 reg. indirect Z,S,P,CY,AC RAL RAR data 2 7 immediate Z,S,P,CY,AC 0 I 0 (Rotate left) (A n+l) ~ (An) ; (AO) ~ (A7) (CY) ~ (A7) The content of the accumulator is rotated left one position. The low order bit and the CY flag are both set to the value shifted out of the high order bit position. Only the CY flag is affected. I , o Cycles: States: Flags: 1 4 CY I 1 I , I , (Rotate right through carry) (An) ~ (A n+l); (CY)..- (AO) (A7) ~ (CY) The content of the accumulator is rotated right one position through the CY flag. The high order bit is set to the CY flag and the CY flag is set to the value shifted out of the low order bit. Only the CY flag is affected. CMA 1 4 CY (Complement accumulator) (A)~(A) The contents of the accumulator are complemented(zero bits become 1, one bits become 0). No flags are affected. o I Cycles: States: Flags: 1 1 4 CY I , Cycles: States: Flags: RLC I (Rotate left through carry) (A n+,) . . - (An) ; (CY) . . - (A7) (AO)"- (CY) The content of the accumu lator is rotated left one position through the CY flag. The low order bit is set equal to the CY flag and the CY flag is set to the value shifted out of the high order bit. Only the CY flag is affected. o I , I , I , I I 0 Cycles: States: Flags: CPI data (Compare immediate) (byte 2) (A) The content of the second byte of the instruction is subtracted from the accumulator. The condition flags are set by the result of the subtraction. The Z flag is set to 1 if (A) = (byte 2). The CY flag is set to 1 if (A) < (byte 2). Cycles: States: Addressing: Flags: I 0 I 1 I 0 Cycles: States: Flags: 1 4 CY 4-10 I , 4 none 1 I , I , CMC (Complement carry) (CY)~ (CY) The CY flag is complemented. No other flags are affected. a , 0 dress is specified in byte 3 and byte 2 of the current instruction. 1 I 1 I 0 I I 0 0 I 0 I 1 I 1 low-order addr , high-order addr Cycles: States: Flags: STC 1 CY (Set carry) (CY) ~ 1 The CY flag is set to 1. No other flags are affected. 0 I 0 I 0 Cycles: States: Flags: 3 Cycles: States: Addressing: Flags: 4 I 1 I 10 immediate none Jcondition addr (Conditional jump) If (CCC), (PC) ~ (byte 3) (byte 2) If the specified condition is true, control is transferred to the instruction whose address is specified in byte 3 and byte 2 of the current instruction; otherwise, control continues sequentially. 1 1 4 CY " 1 I 1 I C I C I C I 0 I 1 I 0 low-order addr high-order addr Cycles: States: Addressing: Flags: Branch Group: 3 10 immediate none This group of instructions alter normal sequential program flow. CALL addr (Call) ((SP) - 1) ~ (PCH) ((SP) - 2) ~ (PCl) (SP) ~ (SP) - 2 (PC) ~ (byte 3) (byte 2) The high-order eight bits of the next instruction address are moved to the memory location whose address is one less than the content of register SP. The low-order eight bits of the next instruction address are moved to the memory location whose address is two less than the content of register SP. The content of register SP is decremented by 2. Control is transferred to the instruction whose address is specified in byte 3 and byte 2 of the current instruction. Condition flags are not affected by any instruction in this group. The two types of branch instructions are unconditional and conditional. Unconditional transfers simply perform the specified operation on register PC (the program counter). Conditional transfers examine the status of one of the four processor flags to determi ne if the specified branch is to be executed. The conditions that may be specified are as follows: CONDITION CCC NZ 2 NC C PO PE P 000 M - not zero (Z = 0) - zero (2 = 1) - no carry (CY = 0) - carry (CY = 1) - parity odd (P = 0) - parity even (P = 1) - plus (S = 0) -minus(S=1) 001 010 011 100 101 110 111 ~ 1 I 1 I 0 I 0 I 1 T 1 I 0 I 1 low-order addr high-ord~r addr Cycles: States: Addressing: Flags: JMP addr (Jump) (PC) ~ (byte 3) (byte 2) Control is transferred to the instruction whose ad- 4-11 5 17 immediate/reg. indirect none RST n (Restart) ((SP) - 1) ~ (PCH) ((SP) - 2) ~ (PCl) (SP) ~ (SP) - 2 (PC) ~ 8* (NNN) The high-order eight bits of the next instruction address are moved to the memory location whose address is one less than the content of register SP. The low-order eight bits of the next instruction address are moved to the memory location whose address is two less than the content of register SP. The content of register SP is decremented by two. Control is transferred to the instruction whose address is eight times the content of NNN. Ccondition addr (Condition call) If (CCC), ((SP) -1) ~ (PCH) ((SP) - 2) ~ (PCl) (SP) ~ (SP) - 2 (PC) ~ (byte 3) (byte 2) If the specified condition is true, the actions specified in the CAll instruction (see above) are performed; otherwise, control continues sequentially. 1 ' 1 I C I C I c I 1 I o I 0 low-order addr high-order addr Cycles: States: Addressing: Flags: RET 3/5 11/17 1 I N immediate/reg. indirect none N I N Cycles: States: Addressing: Flags: I 1 I 3 11 reg. indirect none (Return) (PCl) ~ ((SP)); (PCH) ~ ((SP) + 1); (SP) ~ (SP) + 2; Program Counter After Restart The content of the memory location whose address is specified in register SP is moved to the low-order eight bits of register PC. The content of the memory location whose address is one more than the content of register SP is moved to the high-order eight bits of register PC. The content of register SP is incremented by 2. 1 I I 0 I 0 PCHL Cycles: States: Addressing: Flags: 3 10 reg. indirect none (Jump Hand l indirect - move Hand L to PC) (PCH) ~ (H) (PCl) ~ (l) The content of register H is moved to the high-order eight bits of register PC. The content of register l is moved to the low-order eight bits of register PC. 1 Rcondition (Conditional return) If (CCC), (PCl) ~ ((SP)) (PCH) ~ ((SP) + 1) (SP) ~ (SP) + 2 If the specified condition is true, the actions specified in the RET instruction (see above) are performed; otherwise, control continues sequentially. 1 I I c c I c Cycles: States: Addressing: Flags: I 0 I 0 I I 1 I Cycles: States: Addressing: Flags: 0 1/3 5/11 reg. indirect none 4-12 o ,. o ' 1 5 register none 0 I 1 FLAG WORD Stack, I/O, and Machine Control Group: This group of instructions performs I/O, manipulates the Stack, and alters internal control flags. D1 Do Unless otherwise specified, condition flags are not affected by any instructions in this group. PUSH rp (Push) ((SP) - 1) ~ (rh) ((SP) - 2) ~ (rl) (SP) ~ (SP) - 2 The content of the high-order register of register pair rp is moved to the memory location whose address is one less than the content of register SP. The content of the low-order register of register pair rp is moved to the memory location whose address is two less than the content of register SP. The cont~nt of register SP is decremented by 2. Note: Register pair rp = SP may not be specified.. 1 I 1 I R P I Cycles: States: Addressing: Flags: 0 POP rp (Pop) (rl) ~((SP)) (rh) ~ ((SP) + 1) (SP) ~ (SP) + 2 The content of the memory location, whose address is specified by the content of register SP, is moved to the low-order register of register pair rp. The content of the memory location, whose address is one more than the content of register SP, is moved to the highorder register of register pair rp. The content of register SP is incremented by 2. Note: Register pair rp = SP may not be specified. I 0 Cycles: States: Addressi ng: Flags: I 1 o o 1 3 10 reg. indirect none ((SP) - 2)3 ~ 0 I 1 I 1 o I Cycles: States: Addressing: Flags: o I POP PSW (Pop processor status word) (CY) ~ ((SP))O (P) . . - ((SP))2 (AC) ~ ((SP))4 (Z) ~ ((SP))6 (S) ~ ((SP))7 (A) ...- ((SP) + 1) (SP) ...- (SP) + 2 The content of the memory location whose address is specified by the content of register SP is used to restore the condition flags. The content of the memory location whose address is one more than the content of register SP is moved to register A. The content of register SP is incremented by 2. ((SP) - 2)4 ~ (AC) , ((SP) - 2)5 ~ 0 ((SP) - 2)6 . . - (Z), ((SP) - 2)7 ~ (S) (SP) ~ (SP) - 2 The content of register A is moved to the memory location whose address is one less than register SP. The contents of the condition flags are assembled into a processor status word and the word is moved to the memory location whose address is two less than the content of register SP. The content of register SP is decremented by two. 1 P 3 11 reg. indirect none PUSH PSW (Push processor status word) ((SP) -1) ~ (A) ((SP) - 2)0 . . - (CY) , ((SP) - 2) 1 ~ 1 ((SP) - 2)2 ~ (P), 1 Cycles: States: Addressing: Flags: 3 11 reg. indirect none 4-13 3 10 reg. indirect Z,S,P,CY ,Ae XTHL (Exchange stack top with Hand L) (L) (H) EI ~((SP)) ~ ((SP) + 1) The content of the L register is exchanged with the content of the memory location whose address is specified by the content of register SP. The content of the H register is exchanged with the content of the memory location whose address is one more than the content of register SP. 1 I 0 I SPHL 1 I I Cycles: States: Flags: 01 5 I 1 18 reg. indirect none I IN port o o Cycles: States: Addressing: Flags: HLT 1 5 register none 0 I 1 I 0 I I 1 I 0 I 1 I NOP 1 3 10 direct none o port Cycles: States: Addressing: Flags: 1 Cycles: States: Flags: 4 3 10 direct none 4-14 1 0 ' 1 1 1 1 none 0 I 1 I 1 I 0 1 7 none (No op) No operation is performed. The registers and flags are unaffected. 0 OUT port (Output) (data) ~ (A) The content of register A is placed on the eight bit bi-directional data bus for transmission to the specified port. o I none 0 Cycles: States: Flags: port Cycles: States: Addressing: Flags: 1 1 4 1 1 I (I nput) I I (Halt) The processor is stopped. The registers and flags are unaffected. (A) ~ (data) The data placed on the eight bit bi-directional data bus by the specified port is moved to register A. 1 0 (Disable interrupts) The interrupt system is disabled immediately following the execution of the 01 instruction. (Move HL to SP) (SP) ~ (H) (L) The contents of registers Hand L (16 bits) are moved to register SP. 1 , 1 o o Cycles: States: Addressing: Flags: (Enable interrupts) The interrupt system is enabled following the execution of the next instruction. I 0 I 0 0 0 Cycles: States: Flags: 1 4 none 0 0 0 INSTRUCTION SET Summary of Processor Instructions Mnemonic Description try 06 MOV r1 ,r2 MOVM,r MOVr,M HlT MVI r MVIM INR r OCR r INR M OCR M ADOr AOCr SUB r SBB r Move register to register Move register to memory Move memory to register Halt Move immediate register Move immediate memory Increment register Decrement register Increment memory Decrement memory Add register to A Add register to A with carry Subtract register from A Subtract register from A with borrow And register with A Exclusive Or register with A Or register with A Compare register with A Add memory to A Add memory to A with carry Subtract memory from A Subtract memory from A with borrow And memory with A Exclusive Or memory with A Or memory with A Compare memory with A Add immediate to A Add immediate to A with carry Subtract immediate from A Subtract immediate from A with borrow And immediate with A Exclusive Or immediate with A Or immediate with A Compare immediate with A Rotate A left Rotate A right Rotate A left through carry Rotate A right through carry Jump unconditional Jump on carry Jump on no carry Jump on zero Jump on no zero Jump on positive Jump on minus Jump on parity even Jump on parity odd Call unconditional Call on carry Call on no carry Call on zero Call 0 n no zero Call on positive Call on minus Call on parity even Call on parity odd Return Return on carry Return on no carry 0 0 0 ANA r XRA r OIiAr CMPr ADD M AOC M SUB M SBB M ANA M XRA M ORA M CMPM AOI ACI SUI SBI ANI XRI ORI CPI RLC RRC RAl RAR JMP JC JNC JZ JNZ JP JM JPE JPO CALL CC CNC CZ CNZ CP CM CPE CPO RET RC RNC NOTES: 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Instruction Code [11 Os 04 03 02 0, DO 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 Clock 121 Cycles S S 1 1 1 1 1 1 1 1 S S S S S S 1 1 1 1 0 0 0 0 S S S S S S 0 0 0 0 0 1 0 1 S S S S 5 7 7 7 7 10 S S S S 1 1 1 1 S S S S 1 1 1 1 S S S S 0 0 0 0 4 4 4 4 7 7 7 7 5 5 10 10 4 4 4 4 Mnemonic Description 07 06 Instruction Code [11 Os 04 03 02 0, DO RZ RNZ RP RM RPE RPO RST IN OUT lXI B Return on zero Return on no zero Return on positive Return on minus Return on parity even Return on parity odd Restart Input Output load Immediate register Pair B & C Load immediate register Pair 0 & E Load immediate register Pair H & L load immediate stack pointer Push register Pair B & C on stack Push register Pair 0 & E on stack Push register Pair H & l on stack Push A and Flags on stack Pop register pair B & C off stack Pop register pair 0 & E off stack Pop register pair H & L off stack Pop A and Flags off stack Store A direct Load A direct Exchange 0 & E, H & L Registers Exchange top of stack, H & l H & L to stack pointer H & L to program counter Add B & C to H & L Add 0 & E to H & L Add H & L to H & L Add stack pointer to H & L Store A indirect Store A indirect load A indirect Load A indirect Increment B & C registers Increment 0 & E registers Increment H & L registers Increment stack pointer Decrement B & C Decrement 0 & E Decrement H & L Decrement stack pointer Complement A Set carry Complement carry Decimal adjust A Store H & l direct load H & L direct Enable Interrupts Disable interrupt No-operation 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 A 0 0 0 LXI 0 LXI H lXI SP PUSH B PUSH 0 PUSH H PUSH PSW 0 1 0 1 0 1 POP B POP 0 POP H POP PSW STA lOA XCHG 1 1 0 XTHl SPHL PCHL DAD B DAD 0 DAD H DAD SP STAX B STAX 0 LOAX B lOAX 0 INX B INX 0 INX H INX SP DCX B DCX 0 DCX H DCX SP CMA STC CMC OAA SHlD LHLO EI 01 NOP 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 1 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 10 10 10 10 10 10 10 10 10 17 11/17 11/17 11/17 11/17 11/17 11/17 11/17 11/17 10 5/11 5/11 1. DDD or SSS - 000 B - 001 C - 010 D - 011 E - 100 H - 101 L - 110 Memory - 111 A. 2. Two possible cycle times, (5/11) indicate instruction cycles dependent on condition flags. 4-15 0 0 1 1 0 0 A 1 1 0 '1 0 0 1 1 0 A 1 0 0 0 0 0 0 0 0 1 0 0 0 0 C 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 Clock [21 Cycles 5/11 5/11 5/11 5/11 5/11 5/11 11 10 10 10 10 10 10 11 11 11 11 10 10 10 10 13 13 4 1 1 1 0 l:' 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 18 5 5 10 10 10 10 7 7 7 7 5 5 5 5 5 5 5 5 4 4 4 4 16 16 4 4 4 CPU Group 8224 Clock Generator 8228 System Controller . . . . . . . . . . . . . . . . . . . . . . . 8080A Central Processor 8080A-1 Central Processor (1.3#ls) ••..•.••.••.••.• 8080A-2 Central Processor (1.5#ls) •...•..•..•.••.. MBOBOA Central Processor (_55° to +125°C) 5-1 5-7 5-13 5- 20 5-24 5-29 ROMs 8702A Erasable PROM (256 x 8) 8708/8704 Erasable PROM (1 K x 8302 Mask ROM (256 x 8) 8308 Mask ROM (1 K x 8) . . . . . 8316A Mask ROM (2K x 8) . . . . 5-37 5-45 5-51 5-59 5-61 .. . ... .. . . . . . . . . . 8) . . . . . . . . . . . . . . . . . . .. .. . . . .. . . . . . . . . . .. .. . . .. . . . . . RAMs 8101-2 Static RAM (256 x 4) 8111-2 Static RAM (256 x 4) 8102-2 Static RAM (1 K x 1) . . . . . . . . 8102A-4 Static RAM (1K x 1) . . . . . . . 81078-4 Dynamic RAM (4K x 1) . . . . . 5101 Static CMOS RAM (256 x 4) . . . . 8210 Dynamic RAM Driver. . . . . . . . . 8222 Dynamic RAM Refresh Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67 5-71 5-75 5-79 5-83 5-91 5-95 5-99 I/O 8212 8-Bit I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . 8255 Programmable Peripheral Interface . . . 8251 Programmable Communication Interface. . . . . . . . 5-101 5-113 5-135 Peripherals 8205 One of Eight Decoder . . . . . . . . . . . . . . . . . . . . . 8214 Priority Interrupt Control Unit 8216/8226 4-8 it Bi-D irectional Bus Driver . . . . . . . . . . . 5-147 5-153 5-163 Coming Soon 8253 Programmable Interval Timer. . . . . . . . . . . . . . . . 8257 Programmable DMA Controller 8259 Programmable Interrupt Controller . . . . . . . . . . . . 5-169 5-171 5-173 CPU Group 8224 8228 8080A 8080A-1 8080A-2 M8080-A Schottky Bipolar 8224 CLOCK GENERATOR AND DRIVER FOR 8080A CPU • Oscillator Output for External System Timing • C.rystal Controlled for Stable System Operation • Reduces System Package Count • Single Chip Clock Generator/Driver for 8080A CPU • Power-Up Reset for CPU • Ready Synchronizing Flip-Flop • Advanced Status Strobe The 8224 is a single chip clock generator/driver for the 8080A CPU. It is controlled by a crystal, selected by the designer, to meet a variety of system speed requirements. Also included are circuits to provide power-up reset, advance status strobe and synchronization of ready. The 8224 provides the designer with a significant reduction of packages used to generate clocks and timing for 8080A. PIN NAMES I RESIN RESET RESET INPUT RESET OUTPUT XTAl1 XTAl2 RDYIN READY READY INPUT READY OUTPUT TANK USED WITH OVERTONE XTAL OSC SYNC SYNC INPUT rP2 (TTL) OSCILLATOR OUTPUT rP2 elK (TTL lEVEL) STSTB STATUSSTB (ACTIVE lOW) Vee Voo GND +5V +12V OV rPl rP2 !8080 CLOCKS 5-1 CONNECTIONS FOR CRYSTAL SCHOTTKY BIPOLAR 8224 FUNCTIONAL DESCRIPTION The waveforms generated by the decode gating follow a simple 2-5-2 digital pattern. See Figure 2. The clocks generated; phase 1 and phase 2, can best be thought of as consisting of "units" based on the oscillator frequency. Assume that one "unit" equals the period of the oscillator frequency. By multiplying the number of "units" that are contained in a pulse width or delay, times the period of the oscillator frequency, the approximate time in nanoseconds can be derived. General The 8224 is a single chip Clock Generator/Driver for the S080A CPU. It contains a crystal-controlled oscillator, a "divide by nine" counter, two high-level drivers and several auxiliary logic functions. The outputs of the clock generator are connected to two high level drivers for direct interface to the 80S0A CPU. A TTL level phase 2 is also brought out ct>2 (TTL) for external timing purposes. It is' especially useful in DMA dependant activities. This signal is used to gate the requesting device onto the bus once the 8080A CPU issues the Hold Acknowledgement (H LOA). Oscillator The oscillator circuit derives its basic operating frequency from an external, series resonant, fundamental mode crystal. Two inputs are provided for the crystal connections (XTAL 1, XTAL2). The selection of the external crystal frequency depends mainly on the speed at which the 8080A is to be run at. Basically, the oscillator operates at 9 times the desired processor speed. Several other signals are also generated internally so that optimum timing of the auxiliary flip-flops and status strobe (STSTB) is achieved. A simple formula to guide the crystal selection is: Crystal Frequency = -'tCY Example' : Example 2: times 9 (500ns tCY) 2mHz times 9 = 18mHz* (800ns tCY) '.25mHz times 9 = '1.25mHz Another input to the oscillator is TANK. This input allows the use overtone mode crystals. Th is type of crystal generally has much lower IIgain" than the fundamental type so an external LC network is necessary to provide the additional "gain" for proper oscillator operation. The external LC network is connected to the TANK input and is AC coupled to ground. See Figure 4. The formula for the LC network is: F= __ l __ 21TVLC The output of the oscillator is buffered and brought out on ElSC (pin 12) so that other system timing signals can be derived from this stable, crystal-controlled source. 1 UNIT = o~c. FREQ. 4>, *When using crystals above 10mHz a small amount of frequency "trimming" may be necessary to produce the exact desired frequency. The addition of a small selected capacitance (3pF - 10pF) in series with the crystal will accomplish this function. EXAMPLE: (8080 t CY = 500ns) OSC = 18mHz/55ns 4>1 = 110ns (2 x 55ns) cP2 = 275ns (5 x 55ns) 4>2-4>, = 110ns (2 x 55ns) Clock Generator The Clock Generator consists of a synchronous IIdivide by nine" counter and the associated decode gating to create the waveforms of the two 8080A clocks and auxiliary timing signals. 5-2 SCHOTTKY BIPOLAR 8224 STSTB (Status Strobe) The READY input to the 8080A CPU has certain timing specifications such as "set-up and hold" thus, an external synchronizing flip-flop is required. The 8224 has this feature built-in. The ROYI N input presents the asynchronous "wait request" to the "0" type flip-flop. By clocking the flip-flop with <1>20, a synchronized READY signal at the correct input level, can be connected directly to the a080A. At the beginning of each machine cycle the aOaOA CPU issues status information on its data bus. Th is information tells what type of action will take place during that machine cycle. By bringing in the SYNC signal from the CPU, and gating it with an internal timing signal (<1>1A), an active low strobe can be derived that occu rs at the start of each machine cycle at the earliest possible moment that status data is stable on the bus. The STSTB signal connects directly to the 8228 System Controller. The reason for requ iring an external flip-flop to synchronize the "wait request" rather than internally in the 8080 CPU is that due to the relatively long delays of MOS logic such an implementation would "rob" the designer of about 200ns during the time his logic is determining if a "wait" is necessary. An external bipolar circuit built into the clock generator eliminates most of this delay and has no effect on component count. The power-on R-eset also generates STSTB, but of course, for a longer period of time. This feature allows the 8228 to be automatically reset without additional pins devoted for th is fu nction. Power-On Reset and Ready Flip-Flops A common function in a080A Microcomputer systems is the generation of an automatic system reset and start-up upon initial power-on. The 8224 has a built in feature to accomplish this feature. ,------...., 1 An external RC network is connected to the R ESI N input. The slow transition of the power supply rise is sensed by an internal Schmitt Trigger. Thiscircuit converts the slow transition into a clean, fast edge when its input level reaches a predetermined value. The output of the Schmitt Trigger is connected to a "0" type flip-flop that is clocked with <1>20 (an internal tim ing signal). The flip-flop is synchronously reset and an active high level that complies with the aOaOA input spec is generated. For manual switch type system Reset circuits, an active low switch closing can be connected to the RESIN input in addition to the power-on RC netnetwork. I I I 1 :1 1-= I Ln7-I F=-'21rJLC USEDONLV FOR OVERTONE CRYSTALS °1 r - - , 3.10pF L_ _.J ABOVE 10 MHz) I 13 OSC 1 , if>2 READY, RESET All Other Outputs .45 V .45 V 9.4 3.6 2.4 IOH = -100J.lA IOH = -1 o0J.l A IOH = -lmA -60 rnA Vo =OV Vee =5.0V Output Short Circuit Current (All Low Voltage Outputs Only) Icc Power Supply Current 115 rnA 100 Power Supply Current 12 rnA Note: 1. Caution, cP1 and cP2 output drivers do not have short circuit protection CRYSTAL REQUIREMENTS Tolerance: .005% at O°C -70°C Resonance: Series (Fundamental) * Load Capacitance: 20-35pF Equivalent Resistance: 75-20 ohms Power Dissipation (Min): 4mW *With tan k circu it use 3rd overtone mode. 5-4 (if>1,if>2), Ready, Reset, STSTB IOl =2.5mA All Other Outputs IOl = 15mA V V V Ise[1] -10 Vee = 5.0V SCHOTTKY BIPOLAR 8224 A.C. Characteristics vcc = +5.0V ± 5%; Voo = +12.0V ± 5%; TA = O°C to 70°C Symbol Limits Typ. Min. Parameter tq,1 cP1 Pulse Width 2tcy - - 20ns t2 cP2 Pulse Width 5tcy _ 35ns t01 cP1 to cP2 Delay 0 t02 cP2 to cP1 Delay 2tcy --14ns t03 cP1 to cP2 Delay tR cP1 and cP2 Rise Time cP1 and cP2 Fall Time cP2 to cP2 (TTL) Delay tF to2 Max. Units Test Conditions 9 9 ns CL = 20pF to 50pF 9 2tcy 2tcy + 20ns 9 9 20 20 +15 -5 ns cP2TTl,Cl=30 R1=300Q R2=600Q toss cP2 to STSTB Delay 6tcy _ 30ns tpw STSTB Pulse Width tcy _ 15ns tORS RDYIN Setup Time to Status Strobe 50ns _ 4tcy tORH RDYIN Hold Time After STSTB tOR RDYIN or RESIN to cP2 Delay tCLK ClK Period f max Maximum Oscillating Frequency Cin Input Capacitance 6tcy 9 9 STSTB,Cl=15pF R1 = 2K R2 = 4K 9 9 4tcy 9 Ready & Reset Cl=10pF R1=2K R2=4K 4tcy _ 25ns 9 tcy 9 27 MHz 8 pF INPUT VcC=+5.0V Voo=+12V VBIAS=2.5V f=1 MHz >---......----.... GND 5-5 SCHOTTKY BIPOLAR 8224 WAVEFORMS ~-------------tey---------------.I 1'4------t2fTTL) SYNC (FROM 8080A) ~--------toss-------.....----- t..-----tORH------.t RDYIN OR RESIN READY OUT RESET OUT VOLTAGE MEASUREMENT POINTS: cP1, cP2 Logic "0" = 1.0V, Logic "1" = 8.0V. All other signals measured at 1.5V. EXAMPLE: A.C. Characteristics (For tCY = 488.28 ns) TA = O°C to 70°C; Voo = +qV Symbol ±5%; Voo = +12V Parameter ±5%. Limits Typ. Min. Max. Units ~1 Q>1 Pu Ise Width 89 ns t4>2 Q>2 Pulse Width 236 ns t01 Delay 4>1 to 4>2 0 ns t02 Delay 4>2 to 4>1 95 ns t03 Delay 4>, to 4>2 Leading Edges 109 tr 129 ns Output Rise Time 20 ns tf Output Fall Time 20 ns toss Q>2 to STSTB Delay 296 326 ns tO cP 2' tpw 4>2 to -5 +15 ns Status Strobe Pu Ise Width tORS RDYIN SetupTimeto STSTB tORH 4>2 (TTL) Delay 40 ns -167 ns RDYIN Hold Time after STSTB 217 ns tOR READY or RESET to Q>2 Delay 192 ns fMAX Oscillator Frequency 18.432 . 5-6 MHz Test Conditions - tcy=488.28ns _ Q>1 & Q>2 Loaded to CL = 20 to 50pF - Ready & Reset Loaded to 2mA/10pF All measurements referenced to 1.5V unless specified otherwise. Schottky Bipolar 8228 SYSTEM CONTROLLER AND BUS DRIVER FOR 8080A CPU • User Selected Single Leve,1 Interrupt Vector (RST 7) • 28 Pin Dual In-Line Package • Reduces System Package Count • Sing.le Chip System Control for MCS:SO Systems • Built-in Bi-Directional Bus Driver for Data Bus Isolation • Allows the use of Multiple Byte Instructions (e.g. CAL:L) for Interrupt Acknowledge The 8228 is a single chip system controller and bus driver for MCS-80. It generates all signals required to directly interface MCS-80 family RAM, ROM, and I/O components. A bi-directional bus driver is included to provide high system TTL fan-out. It also provides isolation of the 8080 data bus from memory and I/O. This allows for the optimization of control signals, enabling the systems deisgner to use slower memory and I/O. The isolation of the bus driver also provides for enhanced system noise immunity. A user selected single level interrupt vector (RST 7) is provided to simplify real time, interrupt driven, small system requirements. The 8228 also generates the correct control signals to allow the use of multiple byte instructions (e.g., CALL) in response to an INTERRUPT ACKNOWLEDGE by the 8080A. This feature permits large, interrupt driven systems to have an unlimited number of interrupt levels. The 8228 is designed to support a wide variety of system bus structures and also reduce system package count for cost effective, reliable, design of the MCS-80 systems. PIN CONFIGURATION 8228 BLOCK DIAGRAM STSTB Vee HLDA I/OW WR OBIN OB4 04 OB7 07 OB3 03 DB2 02 MEMW CPU DATA BUS BI·DIRECTIONAL BUS DRIVER SYSTEM OATA BUS IIOR MEMR DRIVER CONTROL INTA BUSEN 06 OB6 05 DBS STSTB ~---------- 01 DBIN DB~ OB1 GND 0' -.0--------------1 -.0-------------011 WR HLDA ~ - - - - - - - - - - - - - I PIN NAMES 07·00 DATA BUS (8080 SIDE) INTA INTERRUPT ACKNOWLEDGE OB7·DBO DATA BUS (SYSTEM SIDE) HLOA HLDA (FROM 8080) IIOR 1/0 READ WR WR (FROM 8080) I!OW 1/0 WRITE BUSEN MEMR MEMORY READ STSTB BUS ENABLE INPUT STATUS STROBE (FROM 8224) MEMW MEMORY WR ITE DBIN DBIN (FROM 8080) Vee GND a VOLTS 5-7 +5V SCHOTTKY BIPOLAR 8228 FUNCTIONAL DESCRIPTION Gating Array General The Gating Array generates control signals (MEM R, MEM W, I/O R, I/O Wand INTA) by gating the outputs of the Status Latch with signals from the 8080 CPU (DBIN, WR, and HLDA). The 8228 is a single chip System Controller and Data Bus driver for the 8080 Microcomputer System. It generates all control signals required to directly interface MCS-80™ family RAM, ROM, and I/O components. The "read" control signals (MEM R, I/O Rand INTA) are derived from the logical combination of the appropriate Status Bit (or bits) and the DBIN input from the 8080 CPU. Schottky Bipolar technology is used to maintain low delay times and provide high output drive capability to support small to medium systems. The "write" control signals (MEM W, I/O W) are derived from the logical combination of the appropriate Status Bit (or bits) and the WR input from the 8080 CPU. Bi-Directional Bus Driver All Control Signals are "active low" and directly interface to MCS-80 family RAM, ROM and I/O components. An eight bit, bi-directional bus driver is provided to buffer the 8080 data bus from Memory and I/O devices. The 8080A data bus has an input requirement of 3.3 volts (min) and can drive (sink) a maximum current of 1.9mA. The 8228 data bus driver assures that these input requ irements will be not only met but exceeded for enhanced noise immunity. Also, on the system side of the driver adequate drive current is available (10mA Typ.) so that a large number of Memory and I/O devices can be directly connected to the bus. The INTA control signal is normally used to gate the "interrupt instruction port" onto the bus. It also provides a special feature in the 8228. If only one basic vector is needed in the interrupt structure, such as in small systems, the 8228 can automatically insert a RST 7 instruction onto the bus at the proper time. To use this option, simply connect the INTA output of the 8228 (pi n 23) to the + 12 volt supply through a series resistor (1 K ohms). The voltage is sensed internally by the 8228 and logic is "set-up" so that when the DBIN input is active a RST 7 instruction is gated on to the bus when an interrupt is acknowledged. This feature provides a single interrupt vector with no additional components, such as an interrupt instruction port. The Bi-Directional Bus Driver is controlled by signal~ from the Gating Array so that proper bus flow is maintained and its outputs can be forced into their high impedance state (3-state) for DMA activities. When using CALL as an Interrupt instruction the 8228 will generate an INTA pulse for each of the three bytes. Status Latch At the beginning of each machine cycle the 8080 CPU issues "status" information on its data bus that indicates the type of activity that will occur during the cycle. The 8228 stores this information in the Status Latch when the STSTB input goes "low". The output of the Status Latch is connected to the Gating Array and is part of the Control Signal generation. The BUSEN (Bus Enable) input to the Gating Array is an asynchronous input that forces the data bus output buffers and control signal buffers into their high-impedance state if it is a "one". If BUSEN is a "zero" normal operation of the data buffer and control signals take place. 8228 BLOCK DIAGRAM CPU DATA BUS BI-OI RECTIONAL BUS DRIVER SYSTEM DATA BUS DRIVER CONTROL GATING ARRAY STSTB ----. --J ----.-------------41 WR --.-------------011 DBIN HLDA ----.--------------1 5-8 SCHOTTKY BIPOLAR 8228 _ 18 WRn-------....., DBINt-=-1.:....7----..-----, HDLA ~2;.;.1~_--. 8080A CPU 3 °O~10~~-I 011-9--l~-I °2~8--l~~ ..... 0 3 1-7--l~-I DATA BUS 0 4 1-3--l~-I °51-4--l~-I 0 6 .-5--l~~-I _----- 0 7 .-6--l~~-I .... INTA MEMR MEM W CONTROL (FROM 8224) STATUSSTROBE--...c1II CONTROL BUS I/O R BUSEN _ _.... 22a I/OW STATUS WORD CHART TYPE OF MACHINE CYCLE I STATUS WORD DO INTA o WO 1 STACK HLTA o o OUT o INP o MEMR 1 1 05 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 --L..-- INTA (NONE) INTA W ~ - - - - - - I/O ' - - - - - - - - - - - - I/O R L...-- L....- ' - - - - - - - - - - - - - - MEM W MEM R ' - - - - - - - - - - - - - - - - - - MEM W MEM R ' - - - - - - - - - - - - - - - - - - - - MEM R 5-9 _ CONTROL SIGNALS SCHOTTKY BIPOLAR 8228 WAVEFORMS STATUS STROBE 8080 DATA BUS -----...".I'~~+--,.,.I"-------------------- DBIN HLDA --------+----+-----'1 INTA, lOR, MEMR DURING HLDA SYSTEM BUS DURING READ 8080 BUS DURING READ· - - - - - - - - - lOW OR MEMW 8080 BUS DURING WRITE SYSTEM BUS DURING WRITE - - - - - - - - <~ - we1= SYSTEM BUS E N A B L E . SYSTEM BUS OUTPUTS - - - - - - - - - - - - - .-j - 1 - tE~r < >- - - - - - - - - - - - - - t-- VOLTAGE MEASUREMENT POINTS: 00-07 (when outputs) Logic "0" = 0.8V, Logic "1" = 3.0V. All other signals measured at 1.5V. A.C. Characteristics TA = O°c to 70°C; Vee = 5V ±5%. Limits Symbol Parameter tpw Width of Status Strobe tss Min. Units Max. 22 ns Setup Time, Status Inputs D o -D7 8 ns tSH Hold Time, Status Inputs Do-D7 5 ns toe Delay from STSTB to any Control Signal tRR ns = 100pF CL = 100pF CL = 25pF CL = 25pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF 60 ns Delay from DB IN to Control Outputs 30 ns tRE Delay from DBIN to Enable/Disable 8080 Bus 45 ns tAD Delay from System Bus· to 8080 Bus during Read 30 ns tWA Delay from WR to Control Outputs 45 ns tWE Delay to Enable System Bus DBo-DB7 after STSTB 30 ns two Delay from 8080 Bus Do -D7 to System Bus DBo-DB7 during Write 20 5 5 CL 40 tE Delay from System Bus Enable to System Bus DBo-DB7 30 ns tHO HLDA to Read Status Outputs 25 ns tos Setup Time, System Bus Inputs to HLDA 10 tOH Hold Time, System Bus Inputs to HLDA 20 5-10 Condition ns \ ns SCHOTTKY BIPOLAR 8228 D.C. Characteristics TA = O°c to 70°C; Vee = 5V ±5%. Symbol Limits Min. Typ.[1] Max. Parameter Ve Input Clamp Voltage, All Inputs IF Input Load Current, STSTB .75 02&06 Test Conditions -1.0 V Vee=4.75V; le=-5mA 500 IlA Vee=5.25V 750 IlA VF=O.45V IlA Do, 01, 04, Os, & 07 250 All Other Inputs 250 Il A 100 IlA Vee=5.25V OBo-OB7 20 IlA VR =5.25V All Other Inputs 100 p.A 2.0 V VCC=5V 190 mA VCC=5.25V Input Leakage Current STSTB IR Unit VTH Input Threshold Voltage, AU Inputs Icc Power Supply Current VOL Output Low Voltage, 00- 0 7 .45 V VCC=4.75V; IOl=2mA All Other Outputs .45 V IOl = 10mA V VcC=4.75V; IOH=-10p.A V IOH = -1mA VOH 140 Output High Voltage, 00- 0 7 3.6 All Other Outputs 2.4 los Short Circuit Current, All Outputs 10 (off) Off State Output Current, All Control Outputs 3.8 15 I NTA Current liNT Note 1: 0.8 90 mA Vec =5V 100 IlA Vce=5.25V; VO=5.25 -100 p.A VO=·45V mA (See Figure below) 5 Typical values are for TA = 2So e and nominal supply voltages. Capacitance This parameter is periodically sampled and not 100%. test,ed. Limits Symbol Parameter Min. Typ.£1] Max. Unit elN Input Capacitance 8 12 pF GoUT Output Capacitance Control Signals 7 15 pF I/O I/O Capacitance (0 or OB) 8 15 pF TEST CONDITIONS: VBIAS = 2.5V, Vcc=S.OV, TA = 2Soe, f = 1 MHz. Note 2: For 00-07: R1 = 4Kn, R2 = oon, cL = 25pF. For all other outputs: R1 = 500n, R2= 1Kn, CL = 100pF. 8228 23 INTA INTA Test Circuit (for RST 7) 5-11 SCHOTTKY BIPOLAR 8228 · · 2 GND. Ao 20 +5V A1 11 -5V A2 28 +12V A3 A4 25 Ao 26 A1 27 A2 29 -- A 3 30 A4 31 As AS 8080A CPU · A7 HOLD INT. ENABLE ......- A 10 14 • INT 16 A 12 A 13 INTE A 14 A 1S WR r,; 1 D 14 13 TANK ----. OSC ~ cfJ2 (TTL) ~ RDYIN ~ RESIN -..0 +12V ----. DBIN TAl HDLA 22 10 15 24 ~ 8224 CLOCK GENERATOR DRIVER 4 23 1 12 cP1 cfJ 2 WAIT O2 REArJY 03 04 RESET 9 Os 16 06 +5V ----. GND ---. 5 8 r -- 19 SYNC 07 A 10 40 A 11 37 A 12 38 A 13 39 A 14 36 A 1S 18 P - 17 21 413(') 10 15 13 . 9 17 16 ,. 8 12 11 7 10 DB 8228 9 BI-DIRECTIONAL BUS DRIVER 5 3 6 4 19 18 5 21 20 6 8 7 28 +5V~ 14 GND---'" 1 STATUS STROBE ADDRESS BUS Ag 1 DO 01 I- AS 21 11 6 2 A7 34 15 12 3 A6 33 35 Ag A 11 SYSTEM INT. REO. 32 AS 13 SYSTEM DMA REO. A6 - .n """ 22 ·-c BUSEN 8080A CPU Standard Interface 5-12 ------- n23 ~4 ..... ...., SYSTEM CONTROL h . ,. . . . ,. DBO DB1 DB2 DB 3 DB4 DATA BUS DBs DB6 D~ -- INTA MEM R 26 ~5 MEMW !"oF I/OW ~7 I/O R CONTROL BUS intel® Silicon Gate MOS 8080 A SINGLE CHIP a-BIT N-CHANNEL MICROPROCESSOR The 8080A is functionally and electrically compatible with the Intel® 8080. • 2 J.Ls Instruction Cycle • Sixteen Bit Stack Pointer and Stack Manipulation Instructions for Rapid Switching of the Program Environment • Powerful Problem Solving Instruction Set • Decimal,Binary and Double Precision Arithmetic • Six General Purpose Registers and an Accumulator • Ability to Provide Priority Vectored Interrupts • Sixteen Bit Program Counter for Directly Addressing up to 64K Bytes of Memory • 512 Directly Addressed I/O Ports • TTL Drive Capability The Intel® 8080A is a complete 8-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip using Intel's n-channel silicon gate MOS process. This offers the user a high performance solution to control and processing applications. The 8080A contains six 8-bit general purpose working registers and an accumulator. The six general purpose registers may be addressed individually or in pairs providing both single and double precision operators. Arithmetic and logical instructions set or reset four testable flags. A fifth flag provides decimal arithmetic operation. The 8080A has an external stack feature wherein any portion of memory may be used as a last in/first out stack to store/ retrieve the contents of the accumulator, flags, program counter and all of the six general purpose registers. The sixteen bit stack pointer controls the addressing of this external stack. This stack gives the 8080A the ability to easily handle multiple level priority interrupts by rapidly storing and restoring processor status. It also provides almost unlimited subroutine nesting. This microprocessor has been designed to simplify systems design. Separate 16-line address and 8-line bi-directional data busses are used to facilitate easy interface to memory and I/O. Signals to control the interface to memory and I/O are provided directly by the 8080A. Ultimate control of the address and data busses resides with the HOLD signal. It provides the ability to suspend processor operation and force the address and data busses into a high impedance state. This permits ORtying these busses with other controlling devices for (DMA) direct memory access or mUlti-processor operation. : .•.. ,'. '/:;):"., :;:", ,.'H:.: ':~, '.:.: •.' ." ': ~',:, '.o;?oo .'H.; '.;:':' :.,. ; >::.... c·... '<1:,: ; , : :', . .~:? ". :. : .. , .. ...• .... 't .;. ;)it~:' :'..':. >:.~ .; ;;:"'.,.':':J ..r·: ACCUMULATOR '';','': :.... .,. ::;." .. :/ (8) :.... ./:, .-,; (8) (8) Z TEMP REG. (8) C REG. (8) D REG. (8) E REG. (8) H REG. (8) L REG. (8) W <~'>:'.~ TEMP REG. ACCUMULATOR LATCH (8) B REG. STACK POINTER :·i.' ,<'., <: :::. ·:i··. (16) TIMING ...,: .: . . :, . :'>; .~ 5-13 '\' (16) PROGRAM COUNTER . '.' ",'," ·SILICON GATE MOS 8080'A . 8080A FUNCTIONAL PIN DEFINITION The following describes the function of all of the 8080A I/O pins. Several of the descriptions refer to internal timing periods. _. . A 15. A O (oU1put three-state) ADDRESS BUS;.the address bus provides the address to memory (up to 64K 8-bit words) or denotes the I/O device number for up to 256 input and 256 output devices. Ao is the least significant address. bit. 04 3 40 __~'-JI A 11 39 A 14 38 A 13 05 4 37 °6~5 36 35 A 12 0 A 15 0 Ag 34 33 0 A7 32 A6 A 10 1 GNO 2 07 03 O~ 0 1.0 OJ-D.o (input/output three-state) DATA BUS; the data bus provides bi-directional. communication .between the CPU, memory, and I/O. devices for instructions and data transfers. Also, during the first clock cycle of each machine cycle, the 8080A outputs a status word on the data bus that de. _scribes the current machine cycle. Do is the least significant bit. DO 0 -5V RESET HOLD SYNC (output) SYNCHRONlZING SIGNAL; the SYNC pin provides a signal to indicate the beginning-of each machine cycle. DATA BUS IN; the DBIN signal indicates to external circuits that the data bus is in the input mode. This signal should be used to enable the gating of data onto the 8080A data bus from memory or I/O. 8 9 10 11 12 13 INTE~ 8080A As 31 As 30 29 28 0 A4 A3 +12V INT 14 27 A2 4>2 15 26 A1 INTE 0 OBIN 0 16 25 17 24 Ao WAIT 18 23 22 4>1 21 HLOA WR SYNC +5V DBIN (output) 6 7 19 20 READY -. Pin Configuration REAPV (input) will go to the high impedance state. The HLOA signal begins at: • T3 for READ memory or input. • The Clock Period following T3 for WR ITE memory or OUTPUT operation. READY; the READY signal indicates to the 8080A that valid memory or input data is available on the 8080A data bus. This signal is used to synchronize t.he CPU with slower memory or I/O devices. If after sending an address out the 8080A does not receive a READY input, the 8080A will enter a WAIT state for as long as the READY line is low. READY can also be used to single step the CPU. In either case, the HLOA signal appears after the rising edge of 4>1 and high impedance occurs after the rising edge of 4>2. INTE (output) INTER RUPT ENABLE; indicates the content of the internal interYlJAIT (output) rupt enable flip/flop. This flip/flop may be set or reset by the EnWAIT; the WAIT signal acknowledges that th~ CPU is in a WAIT able. and Disable Interrupt instructions and inhibits interrupts s~ate. from being accepted by the CPU when it is reset. It is auto, matically reset (dfsab'ling further interrupts) -at time T1 of the inWR (output) struction fetch cycle (M 1) when an interrupt is accepted and is WRITE; the WR signal is used for memory WRITE or I/O output also reset by the RESET signal. control. The data on the data bus is stable while the WR signal is active low (WR = 0). INT (input) INTERR.UPT REQUEST; the CPU recognizes an interrupt re. HOLD (input) quest on this line at the end of the current instruction or while HOLD; the HOLD signal requests' the CPU to 'enter the HOLD halted. If the CPU is in the HOLD state or if the Interrupt Enable state. The HOLD state allows an external device to gain control flip/flop is reset it will not honor the request. of the 8080A address and data bus as soon as the 8080A has com- pleted its use of these buses for the current machine cycle. It is recognized under the following conditions: • the CPU is in the HALT state. • the CPU is in the T2 or TW state and the READY signal is active. As a result of entering the HOLD stf'te the CPU ADDRESS BUS. (A15-AO) and DATA BUS (0 7 -00) will be in their high impedance state. The CPU acknowledges its state with the HOLD ACKNOWLEDGE (HLDA) pin. HLOA (output) HOLD ACKNOWLEDGE; the HLDA signal appears in response to the HOLD' signal and !ndicates that the data and address bus RESET (input) [1] RESET; while the RESET signal is activated, the content of the program counter is cleared. After RESET, the program will start at location 0 in memory. the INTE and HLDA flip/flops are also reset. Note that the flags, accumulator, stack pointer, and registers are not cleared. Vss Ground Reference. VDD +12 ± 5% Volts. Vee +5 ± 5% Volts. Vss -5 ±5% Volts (substrate bias). ,l/>1,'l/>2 2 externally supplied clock phases. (non TTL compatible) 5-14 SILICON GATE MOS 8080 A ABSOLUTE MAXIMUM RATINGS· *COMMENT: Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Temperature Under Bias ' O°C to +70° C Storage T emperatu re . . . . . . . . . . . . . . . _65° C to + 150° C All Input or Output Voltages With Respect to VSS -0~3V to +20V Vcc, Voo and VSS With Respect to Vss -0.3V to +20V . Power Dissipation 1.5W D.C. CHARACTERISTICS = O°C TA to 70°C, VOO Symbol = +12V ± 5%, Vcc = +5V ± 5%, Vss = -5V ± 5%, Vss Typ. Max. Unit Min. Parameter = OV, Unless Otherwise Noted. VILC Clock Input Low Voltage Vss-1 Vss+0.8 V VIHC Clock Input High Voltage 9.0 Voo+1 V VIL Input Low Vss-1 VsstO.8 V 3.3 Vcc+1 V 0.45- V Vol~age Test Condition VIH Input High Voltage VOL Output Low Vqltage VOH Output High Voltage 100 (AV) Avg. Power Supply Current (Voo) 40 70 mA ICC (AV) Avg. Power Supply Current (Vc c ) 60 80 mA ISB(AV) Avg. Power Supply Current (V ss ) .01 1 mA IlL Input Leakage ±10 J.1A VSS ~ VIN ~ V cc ICl Clock Leakage ±10 J.1A Vss ~ VCLOCK ~ VDD IDL[2] Data Bus Leakage in Input Mode -100 -2.0 ~A VSS ~VIN ~Vss +0.8V mA Vss+0.8V~VIN~Vcc IFL 3.7 } IOl = 1.9mA on all outputs, IOH =-150~A. V Address and Data Bus Leakage Dl:Iring HOLD +10 -100 } Operation TCy = .48 J.1sec VADoR/oATA = VCC ~A VADOR/DATA CAPACITANCE TA = 25°C Symbol VCC TYPICAL SUPPLY CURRENT VS. TEMPERATURE, NORMALIZED.[3] = Voo = Vss = OV, Vss =-5V Parameter 1.5,..-----r-----,-----_ Typ. Max. Unit Test Condition = 1 MHz Cq> Clock Capacitance 17 25 pf fc CIN Input Capacitance 6 10 pf Unmeasured Pins CO UT Output Capacitance 10 20 = Vss + 0.45V pf Returned to Vss NOTES: 1. The RESET signal must be active for a minimum of 3 clock cycles. 2. When DSIN is high and VIN > VIH an internal active pull up will be switched onto the Data Sus. 3. ~I supply / ~ TA = -O.45%t C. ...z w a: a: ::» (,) > ..J 1.0 t----~~=------+__--~ a. a. ::» U) 0.5 0~---+2&.-5- - - - + 5 " ' - 0 - - - '......1+ 75 AMBIENT TEMPERATURE (Oe) DATA BUS CHARACTERISTIC DURING DB"IN MAX °O~------------~ Vee 5-15 SILICON GATE MOS 8080A A.C. CHARACTERISTICS = O°C to 70°C, VOO = +12V ± 5%, VCC = +5V ± 5%, Vas = -5V ± 5%, Vss = OV, Unless Otherwise Noted TA Symbol Parameter Min. Max. Unit 0.48 2.0 J1sec 50 nsec Test Condition tCy[3] Clock Period t r , tf ·Clock Rise and Fall Time 0 ~1 f/J1 Pulse Width 60 nsec tq,2 cf>2 Pu.lse Width 220 nsec t01 Delayep1 to ep2 0 nsec . t02 Delay lP2 to l/>, 70 nsec t03 Delayep, to ep2 Leading Edges 80 nsec tOA [2] Address Output Delay From ~2 200 nsec to.D [2] Data Output Delay From f/J2 220 nsec toC[2] Signal 'Output Delay From ep1 , or ep2 (SYNC, WR,WArT, HLDA) 120 nsec tOF [2] DBIN Delay From lP2 140 nsec tOI[1] Delay for Input Bus to Enter Input Mode tOF nsec tOS1 .Data Set~p Time During ~1 and DB IN TIMING WAVEFORMS --. (/>, I 25 [14] } Cl }Cl = 100pf =50pf nsec 30 (Note: Timing measurements are made at the following reference voltages: CLOCK "1" = 8.0V "0" = 1.0V; INPUTS "1" = 3.3V, 110" = 0.8V; OUTPUTS "1" = 2.0V, "0" = 0.8V.) -I t CY ~~1 -. to, .- r~ f\ JF\ iF\ .-t 2~1 }~ j~ jJ- ~ ~ ....h ... ~to3 . .1 !O2 ~ .. ___ I r. ~tOA-.I ~too--' --..;.. ~ --- -- ---- t OI I......... -"rr· ,,"".J-,------- -- 4=..... ~ ---i t DATA IN ~-- --. tos, ...- -t- T SYNC· ~ tocl~ DBIN ---.. t oc ~-- --- ---- -f 1--- -- - ---r---. ...-tOO - ' toHI"'- ~ .J DATA OUT ~I--tow -I ~tOS2-' 1..- -r 1- ~tOF~ ~tOF ~t ----------READY H tAW ~ ~~ F- ~~ ~ t oc .........1 . ItHl~ -I=@ t ------------ -~:'J> tH-. WAIT - .-t oc ---" HOLD -;f!1~ t RS X- 1.- t oc ..........1 l- --J@ 1.-- tH -. I ~I~;~~ HLDA --X@ INT 1=-= tiS t H --. INTE . 5-16 ,. ~~ ~ SILICON GATE MOS 8080A A.C. CHARACTERISTICS (Continued) TA = O°C to 70°C, Voo = +12V ± 5%, Vee = +5V ± 5%, Vss = -5V'± 5%, V55 = OV, Unless Otherwise Noted Symbol Min. Parameter Max. Unit t052 Data Setup Time to ~2 During DBIN 150 nsec tOH (1) Data Hold Time From ~2 During DBIN [1 ] nsec tiE [2) INTE Output Delay From ~2 tRS READY Setup Time During ~2 120 nsec tH5 HOLD Setup Time to ~2 140 nsec tiS INT Setup Time During ~2 (During cP1 in Halt Mode) 120 nsec tH Hold Time From 0 nsec tFO Delay to Float During Hold (Address and Data ~us) tAW [2) Address Stable Prior to WR [5] nsec tow [2) Output Data Stable Prior to WR [6] nsec tWD[2] Output Data Stable From WR [7] nsec [7] nsec tWf\[2] ~2 200 (READY, INT, HOLD) .- nsec 120 , Address Stable From WR Test Condition CL'= 50pf nsec - ~ - tHF[2] HLDA to Float Delay [8] nsec tWF[2] WR to Float Delay [9] nsec tAH[2] Address Hold Time After DBIN During HLDA -20 nsec CL= 100pf: Address, Data C L =50pf: WR, HLDA, DBIN -- NOTES: 1. Data input should be enabled with 'OBIN status. No bus co~f1ict can then occur and data hold time is assured. tOH = 50 ns or tOF, whichever is less. 2. Load Circuit. +5V 2.1K 8080A OUTPUT 3. tCY = t03 + tr~2 + t4>2 + tf~2 + t02 + t rit>1 ;> 480ns. TYPICAL 0 7 .00 +20 ~ ~ OUTPUT DELAY VS. A CAPACITANCE r-----~-----r----~---__. lit ..s > SYNC « ..J +10 w C ~ OBIN 0 :;) Q. ~ :;) 0 -10 <1 WR -20 -100 t oc READY o -50 .:1. +50 +100 CAPACITANCE (pf) (CACTUAL - C SPEC ) WAIT HOLD st oc HLDA ~ INT INTE I -t:1- ...- 4. The following are relevant when interfacing the 8080A to devices having VIH = 3.3V: a) Maximum output rise time from .8V to 3.3V = 100ns @ CL = SPEC. b) Output delay when measured to 3.0V == SPEC +60ns @ CL == SPEC. c) If CL "* SPEC, add .6ns/pF if CL> CSPEC, subtract .3ns/pF (from modified delay) if CL < CSPEC. 5. tAW = 2 tCY -t03 -t r2 -140nsec. 6. • tow = tCY -t03 -tr2 -l70nsec. 7. If not HLOA, two =tWA = t03 + t r2 +10ns. If HLOA, two = twA = twF. 8. tHF == t03 + t rc/>2 -50ns. 9. twF = t03 + t r c/>2 -10ns 10. Data in must be stable for this period during OBIN ·T3. Both tOS1 and tOS2 must be satisfied.' 11. Ready signal must be stable for this period during T 2 or TW. (Must be externally synchronized.) 12. Hold signal must be stable for this period during T2 or TW when entering hold mode, and during T3, T4, TS and TWH when in hold mode. (External synchronization is not required.) 13. Interrupt signal must be stable during this period of the last clock cycle of any instruction in order to be recognized on the following instruction. (External synchronization is not required.) 14. This timing diagram, shows timing relationships only; it does not represent any specific machine cycle. 5-17 SILICON GATE MOS 8080 A INSTRUCTION SET The accumulator group instructions include arithmetic and logical operators with direct, indirect, and immediate addressing modes. increment and decrement memory, the six general registers and the accumulator is provided as well as extended increment and decrement instructions to operate on the register pairs and stack pointer. Further capability is provided by the abil ity to rotate the accu mu lator I~ft or right through or arou nd the carry bit. Move, load, and· store instruction groups provide the ability to move either a or 16 bits of data between memory,' the six working registers and the accumulator using direct, indirect, and 'immediate addressing modes. Input and output may be accomplished using memory addresses as I/O ports or the directly addressed I/O provided for in the 8080A instruction set. The ability to branch to different portions of the program is provided with jump, jump conditional, and computed jumps. Also the ability to call to and return from subroutines is provided both conditionally and unconditionally. The RESTART (or single byte call instruction) is useful for interrupt vector operation. The following special instruction group completes the 8080A instruction set: the NOP instruction, HALT to stop processor execution and the OAA instructions provide decimal arithmetic capabil ity. STC allows the carry flag to be directly set, and the CMC instruction allows it to be complemented. CMA complements the contents of the accumulator and XCHG exchanges the contents of two 16-bit register pairs directly. OOl:Jble precision operators such as stack manipulation and double add instructions extend both the arithmetic and interrupt handl ing capability of the a080A. The ability to Data and Instruction Formats Data in the a080A is stored in the form of a-bit binary integers. All data transfers to the system data bus will be in the same format. 1 0 7 06 Os 04 03 02 01 001 OATA WORO The program instructions may be one, two, or three bytes in length. Multiple byte instructions must be stored in successive words in program memory. The instruction formats then depend on the particular operation executed. TYPICAL INSTRUCTIONS One Byte Instructions Register to register, memory reference, arithmetic or logical, rotate, return, push, pop, enable or disable Interrupt instructions Two Byte Instructions 1 0. 7 06 Os D4 °3 °2 °1 DO 1 0 7 °6 Os D4 °3 °2 °1 DO I OP CODE I OPERANO Immediate mode or I/O instructions Three Byte Instructions 10 7 °6 Os 04 °3 °2 °1 DO 0 1 0 7 °6 Os 04 °3 °2 1 DO I OP COOE I LOW ADDRESS OR OPERAND 1 I Jump, call or direct load and store instructions HIGH ADDRESS OR OPERANO 2 0 1 7 06 Os 04 03 °2 °1 DO For the 8080A a logic "1" is defined as a high level and a logic 110" is defined as a low level. 6-18 SILICON GATE MOS 8080.A INSTRUCTION SET Summary of Processor Instructions Mnemonic Description D7 D6 MOV r1 .r2 MOVM,r MOVr,M .HLT MVI r MVIM lNR r OCRr INR M OCR M ADD r ADCr SUB r SaB r Move register to register Move register to memory Move memory to register Halt Movi immediate register Move immediate memory Increment register Decrement register Increment memory Decrement memory Add register to A Add register to Awith carry Subtract register from A Subtract register from A with borrow And register with A Exclusive Or register with A .0 r register with A Compare register with A Add memory to A Add memory to Awith carry Subtract memory from A Subtract memory from A with borrow And memory with A Exclusive 0 r memory with A Or memory with A Compare memory with A Add immediate to A Add immediate to A with carry Subtract immediate from A Subtract immediate from A with borrow And immediate with A Exclusive Or immediate with A Or immediate with A Compare immediate with A Rotate A left Rotate A right Rotate A left through carry Rotate A right through carry Jump unconditional Jump on carrY Jump on no carry Jump on zero Jump on no zero Jump on positive Jump on minus Jump on parity even Jump on parity odd Call unconditional Call on carry Call on no carry Call on zero Call on no zero Call on positive Call on minus Call on parity even Call on parity odd Return Return on carry Return on no carry 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0' 0 0 0 ANAr XRAr ORAr CMPr ADOM ADCM SUB M SBB M ANAM XRAM ORAM CMPM ADI ACI SUI SBI ANI XRI ORI CPI RLC RRC RAL RAR JMP JC JNC JZ JNZ JP JM JPE JPO CALL CC CNC CZ CNZ CP CM CPE CPO RET RC RNC Instruction Code [1 J Os D4 D3 02 0, Do 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 S S 1 1 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 1 1 1 1 S S S S S S S S' 1 1 1 1 5 7 7 7 7 10 5 5 10 10 4 4 S S S S 0 ,4 4 4 4 '1 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 O. 1 1 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 7 7 4 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 10 10 10 10 10 10 10 10 .10 17 11/17 11/17 11/17 11/17 11/17 11/17 11/17 11/17 10 5/11 5/11 0 0 0 1 1 0, 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 1 0 0 1 1 1 1 1 1 ,1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 0 0 l' 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0, 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Mnemonic Description RZ RNZ RP RM RPE RPO RST IN OUT LXIB Return on zero Return on no zero Return on positive Return on minus Return on parity even Return on parity odd Restart Input Output Load immediate register Pair B & C LXIO Load immediate register Pair D & E LXIH Load immediate register Pair H & L Load immediate stack pointer LXISP PUSH a Push register Pair B & Con stack PUSH 0 Push register Pair 0 & E on stack PUSH H Push register Pair H & Lon stack PUSH PSW Push Aand Flags on stack POP B Pop register pair B & C off stack POPD Pop register pair 0 & E off stack POP H Po.p register pair H & Loff stack POP PSW Pop Aand Flags off stack STA Store Adtrect LOA Load Adirect XCHG Exchange 0 & E, H& L Registers XTHL Exchang~ top of stack, H& L SPHL H & L to stack pointer PCHL H & Lto program counter DAD B Add B & Cto H & L DAD 0 Add 0 & E to H & L DAD H Add H & L to H & L DAD SP Add stack pointer to H & L STAXB Store A indirect STAX 0 Store A indirect LOAXB Load A indirect Load A indirect LoAXO INX B Increment B & Cregisters INX D Increment 0 & E registers INX H Increment H & L registers INXSP Increment stack pointer OCX B Decrement B & C ,OCX 0 Decrement 0 & E OCX H Decrement H & L OCXSP Decrement stack pointer CMA Complement A STC Set carry CMC Complement carry DAA Decimal adjust A SHLD Store H & Ldirect LHLD Load H & Ldirect EI Enable Interrupts 01 Disable interrupt N.OP No-operation 44 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 S S S S 1 1 1 1 S S 0 0 0 0 0 1 0 1 S S S S 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 S S 1 1 1 1 0 0 0 0 S S S S Clock [2] Cycles 7 7 7 7 7 7 7 7 7 7 4 4 4 NOTES:. 1. DDDorSSS-OOOB-001 C-010D-011'E-100H-101 L-110Memory....:.111 A. 2. Two possible cycle times, (5/11) indicate instruction cycles dependent on condition flags. 5-19 D7 06 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Instruction Code (1) Os 04 Da ~ 0, 0 0 1 1 1 1 1 1 0 0 1 A 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 0 1 0 0 A A 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O. 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 5/11 5/11 5/11 5/11 5/11 5/11 11 10 10 10 0 1 0 0 0 1 1 1 0 0 0 0 10 0 0 0 0 10 1 0 0 0 0 1 0 0 10 11 0 0 11 0 0 11 0 0 11 0 0 0 10 0 0 O' 10 0 0 0 10 0 0 0 10 1 1 0 0 0 0 0 0 0 1 13 13 4 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ,1 1 0 1 0 1 1 1 1 0 0 18 5 5 10 10 10 10 7 7 7 7 5 5 5 '5 5 5 5 5 4 4 4 4 16 16 4 4 4 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 C 0 0 0 0 1 0 0 0 0 Clock[2J Cycles 0 0 0 0 0 , Do 1 1 0 (} 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 " 1 1 0 0 0 0 0 infel® Silicon Gate MOS 8080A-1 SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSOR • TTL Drive Capability • 1.3 J.Ls Instruction Cycle • Sixteen Bit Stack Pointer and Stack Manipulation Instructions for Rapid Switching of the Program Environment • Powerful Problem Solving Instruction Set • Decimal,Binary and Double Precision Arithmetic • Six General Purpose Registers and an Accumulator • Ability to Provide Priority Vectored Interrupts • Sixteen Bit Program Counter for Directly Addressing up to 64K Bytes of Memory • 512 Directly Addressed 1/0 Ports The Intel® aOaOA is a complete a-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip using Intel's n-channel silicon gate MOS process. This offers the user a high performance solution to control and processing applications. The aOaOA contains six 8-bit general purpose working registers and an accumulator. The six general purpose registers may be addressed individually or in pairs providing both single and double precision operators. Arithmetic and logical instructions set or reset four testable flags. A fifth flag provides decimal arithmetic operation. The aOaOA has an external stack feature wherein any portion of memory may be used as a last in/first out stack to store/ retrieve the contents of the accumulator, flags, program counter and all of the six general purpose registers. The sixteen bit stack pointer controls the addressing of this external stack. This stack gives the 80aOA the ability to easily handle multiple level priority interrupts by rapidly storing and restoring processor status. It also provides almost unlimited subroutine nesting. This microprocessor has been designed to simplify systems design. Separate 16-line address and a-line bi-directional data busses are used to facilitate easy interface to memory and I/O. Signals to control the interface to memory and I/O are provided directly by the aOaOA. Ultimate control of the address and data busses resides with the HOLD signal. It provides the ability to suspend processor operation and force the address and data busses into a high impedance state. This permits ORtying these busses with other controlling devices for (DMA) direct memory access or mUlti-processor operation. 5-20 SILICON GATE MOS 8080A-1 ABSOLUTE MAXIMUM RATINGS· *COMMENT: Stresses above those listed under 'Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is'not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Temperature Under Bias O°C to +70° C Storage Temperature -65°C to +150°C All Input or Output Voltages With Respect to Vaa -0.3V to +20V Vee, VOO and Vss With Respect to Vaa -0.3V to +20V Power Dissipation . . . . . . . . . . . .. 1.5W D.C. CHARACTERISTICS = O°C TA to 70°C, Voo Symbol = +12V ± 5%, Vce = +5V ± 5%, Vss = -5V Typ. Min. Parameter ± 5%, Vss = OV, Unless Otherwise Noted. Max. Unit VILe Clock Input Low Voltage Vss-1 Vss+0.8 V VIHC Clock Input High Voltage 9.0 Voo+1 V VIL Input Low Voltage Vss-1 Vss+0.8 V VIH Input High Voltage 3.3 Vec+1 V VOL Output Low Voltage 0.45 V VO H Output High Voltage 3.7 Test Condition }'0 L = 1.9mA on all outputs, 'OH = 150J,.lA. V Avg. Power Supply Current (Voo) 40 70 mA ICC (AV) Avg. Power Supply Current (Vce) 60 80 mA 'ss (AV) Avg. Power Supply Current (V ss ) .01 1 mA IlL Input Leakage ±10 pA Vss ~ VIN ~ Vee ICl Clock Leakage ±10 pA Vss ~ VeLOeK ~ Voo IOL[2] Data Bus Leakage in Input Mode -100 -2.0 JlA mA VSS~VIN ~Vss+0.8V +10 -100 pA 100 (AV) IFL Address and Data Bus Leakage During HOLD } Operation T Cy = .32Jlsec Vss+0.8V~VIN~Vec VAOOR/OATA = Vec VAOOR/OATA = VSS + 0.45V CAPACITANCE TA = 25°C Symbol TYPICAL SUPPLY CURRENT VS. TEMPERATURE, NORMALIZED.[3] Vee = VOO = Vss = OV, Vas =-5V Parameter Typ. Max. Unit Test Condition Cf/> Clock Capacitance 17 25 pf fc CIN Input Capacitance 6 10 pf Unmeasured Pins CO UT Output Capacitance 10 20 pf = 1 MHz Returned to VSS NOTES: 1. The RESET signal must be active for a minimum of 3 clock cycles. 2. When OSIN is high and VIN > VIH an internal active pull up will be switched onto the Data Sus. 3. aI supply I b. T A = -0.45%/ c. 1.5 r------r-----~---_ 1.0 1"-----=-~:------+-------4 ~ z w a: a: ::> (J > -' Q. Q. ::> en 0.5 ----"'-----....L..- o +25 ....J +50 +75 AMBIENT TEMPERATURE (OC) DATA BUS CHARACTERISTIC DURING DBIN MAX °o'-------------~ Vee 5-21 SILICON GATE MOS 8080A-1 A. c. CHARACTERISTICS TA CA UTlON: When operating the 8080A·l at or near full speed, care must be taken to assure precise timing compatibility between 8080A·', 8224 and 8228. = O°C to 70°C, Voo = +12V ± 5%, VCC = +5V ± 5%, VSS = -5V ± 5%, VSS = OV, Unless Otherwise Noted Symbol Parameter Min. Max. Unit .32 2.0 J.1sec 25 nsec tCy[3] Clock Period t r , tf Clock Rise and Fall Time 0 t4»1 ¢1 Pulse Width 50 nsec t4»2 ~ 145 nsec t01 Delay cfJ1 to cfJ2 0 nsec t02 Delay ¢2 to cfJ1 60 nsec t03 Delay ¢, to ¢2 Leading Edges 60 nsec tOA [2] Address Output Delay From ¢2 150 nsec too [2] Data Output Delay From ¢2 180 nsec toc[2] Signal Output Delay From ¢" or cfJ2 (SYNC, WR.WAIT, HLOA) 110 nsec tOF [2] DBIN Delay From ¢2 130 nsec tOI[1] Delay for Input Bus to Enter Input Mode tOF nsec tOS1 Data Setup Time During cfJ1 and DBIN Pulse Width TIMING WAVEFORMS ---. I 25 [14] Test Condition } Cl }Cl = 50pf =50pf nsec 10 (Note: Timing measurements are made at the following reference voltages: CLOCK 111" = 8.0V 110" = 1.0V; INPUTS 111" = 3.3V, 1'0" = 0.8V; OUTPUTS "1" = 2.0V, "0" = O.8V.) . ---. ~I t CY Fft~l r~ f\ ~11- }F\ Jf\ ~t~2~1 -~ }~ -J ...t 03 "'! -.\ --~ i4-- t OA-'\ i4---too~1 r ~ t 02 ~ .. - ---. toc DBIN 1.-. -... ,- t OI -- 1'- +:..... - ~-t-... t ...- OS1 ..... t oS2 ..... -i.-. --t H" .,._ .JrPATA IN tAW ~ ~tOO-" toHI'- ~ .J 1--- -- - 10---- DATA OUT I-f--tow -I ~ tocl.- -r t ... t OF ~l ----------- t oc -r@ I t H -ij L-, --_ .... 1 "1 --- --- ---- --f 1 - - - ~--- ~tOF:.I READY ~ I -=1 --- .....,J- ..Jjl- -~ ~k- I T SYNC ~ 1~~ _------~- t -tRSItH -. WAIT .t oc ---' HOLD T I~ r-- .-.-.\ ~~ 'RS toe -'-{ II _ I t H -.1 1.- !@ IX ~r~:~ HLDA - INT L !@ ~~ 1== ~ tiS t H -... INTE 5-22 ... SILICON GATE MOS 8080A-1 A.C. CHARACTERISTICS (Continued) TA = O°C to 70°C, Vo o = +12V ± 5%, Vee = +5V ± 5%, Vss Symbol = -5V ± 5%, V ss = OV, Unless Otherwise Noted Min. Parameter Max. Unit 120 nsec [1] nsec tOS2 Data Setup Time to ¢2 During DBIN tOH [1] Data Hold Time From ¢2 During DBIN tiE [2] INTE Output Delay From ¢2 tRS READY Setup Time During ¢2 90 nsec tHS HOLD Setup Time to ¢2 120 nsec tiS INT Setup Time During ¢2 (During 1 in Halt Mode) 100 nsec tH Hold Time From ¢2 (REAOY, INT, HOLD) 0 nsec tFO Delay to Float During Hold (Address and Oata Sus) tAW [2] Address Stable Prior to WR [5] nsec tOW[2] Output Data Stable Prior to WR [6] nsec two [2] Output Data Stable From WR [7] nsec tWA [2] Address Stable From WR [7] nsec tHF[2] H LDA to Float Delay [8] nsec tWF[2] WR to Float Delay [9] nsec tAH [2] Address Hold Time After DBIN During HLDA -20 nsec 200 Test Condition nsec 120 CL = 50pf nsec ........, ~ CL = 50pf: Address, Data CL =50pf: WR, HLDA, DBIN - NOTES: 1. Data input should be enabled with OBIN status. No bus conflict can then occur and data hold time is assured. tOH :::: 50 ns or tOF, whichever is less. 2. Load Circuit. +5V 9 2.1K 8080A OUTPUT A 1S -AO ~ 3. tCY:::: t03 + t nt>2 + t4>2 + tf4>2 + t02 + t r 4>1 ;> 320ns. twA 0 7 -0 0 I- ~ CAPACITANCE +20 r - - - - - - - . - - - - - - - - - - - r - - - -----, TYPICAL!:J. OUTPUT DELAY VS. - two .5- SYNC > oBIN ::::> ~ ...J W 0 ~ +10 0 Q. ~ ::::> 0 -1 -10 WR o -50 t oc READY ~ +50 +100 CAPACITANCE (pf) (CACTUAL - CSPEC ) WAIT HOLD I---. t oc .-- HLoA INT INTE 4. The following are relevant when interfacing the 8080A to devices having VIH :::: 3.3V: a) Maximum output rise time from .8V to 3.3V = 1OOns @ CL = SPEC. b) Output delay when measured to 3.0V = SPEC +60ns @ CL = SPEC. c) If CL :f. SPEC, add .6ns/pF if CL> CSPEC, subtract .3ns/pF (from modified delay) if CL < CSPEC. 5. tAW:::: 2 tCY -t03 -t nt>2 -110nsec. 6. tOW:::: tCY -t03 -t r2 -150nsec. 7. If not HLDA, tWO:::: tWA:::: t03 + t r 2 -10ns 10. Data in must be stable for this period during DB IN ·T3. Both tOS1 and tOS2 must be satisfied. 11. Ready signal must be stable for this period during T2 or TW. (Must be externally synchronized.) 12. Hold signal must be stable for this period during T2 or TW when entering hold mode, and during T3, T4, TS and TWH when in hold mode. (External synchronization is not required.) 13. Interrupt signal must be stable during this period of the last clock cycle of any instruction in order to be recognized on the following instruction. (External synchronization is not requiredJ 14. This timing diagram shows timing relationships only; it does not represent any s~ific machine cycle. 5-23 infel® Silicon Gate MOS 8080 A-2 SINGLE CHIP a-BIT N-CHANNEL MICROPROCESSOR • 1.5 J.Ls Instruction Cycle • Sixteen Bit Stack Pointer and Stack Manipulation Instructions for Rapid Switching of ~he Program Environment • Powerful Problem Solving Instruction Set • Decimal,Binary and Double Precision Arithmetic • Six General Purpose Registers and an Accumulator • Ability to Provide Priority Vectored Interrupts • Sixteen Bit Program Counter for Directly Addressing up to 64K Bytes of Memory • 512 Directly Addressed 1/0 Ports • TTL Drive Capability The Intel® aOaOA is a complete a-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip using Intel's n-channel silicon gate MOS process. This offers the user a high performance solution to control and processing appli"cations. The aOaOA contains six a-bit general purpose working registers and an accumulator. The six general purpose registers may be addressed individually or in pairs providing both single and double precision operators. Arithmetic and logical instructions set or reset four testable flags. A fifth flag provides decimal arithmetic operation. The aOaOA has an external stack feature wherein any portion of memory may be used as a last in/first out stack to store/ retrieve the contents of the accumulator, flags, program counter and all of the six general purpose registers. The sixteen bit stack pointer controls the addressing of this external stack. This stack gives the aOaOA the ability to easily handle multiple level priority interrupts by rapidly storing and restoring processor status. It also provides almost unlimited subroutine nesting. This microprocessor has been designed to simplify systems design. Separate 16-line address and a-line bi-directional data busses are used to facilitate easy interface to memory and I/O. Signals to control the interface to memory and I/O are provided directly by the aOaOA. Ultimate control of the address and data busses resides with the HOLD signal. It provides the ability to suspend processor operation and force the address and data busses into a high impedance state. This permits ORtying these busses with other controlling devices for (DMA) direct memory access or mUlti-processor operation. 5-24 SILICON GATE MOS 8080A-2 ABSOLUTE MAXIMUM RATINGS· *COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Temperature Under Bias O°C to +70° C Storage T emperatu re .. . . . . . . . . . . . .. _65° C to + 150° C All Input or Output Voltages With Respect to Vas -0.3V to +20V Vee, Voo and Vs s With Respect to V ss -0.3V to +20V Power Dissipation . . . . .. 1.5W D.C. CHARACTERISTICS = O°C TA to 70°C, VOO = +12V ± 5%, V CC = +5V ± 5%, = -5V ± 5%, Vss = OV, Unless Otherwise Noted. Typ. Min. Parameter Symbol Vas Max. Unit VILC Clock Input Low Voltage Vss-l Vss+0.8 V V,HC Clock Input High Voltage 9.0 Voo+l V V,L Input Low Voltage Vss - l Vss+0.8 V 3.3 Vee+ 1 V 0.45 V Test Condition V,H Input High Voltage VOL Output Low Voltage VO H Output High Voltage 100 (AV) Avg. Power Supply Current (V oo ) 40 70 mA lee (AV) Avg. Power Supply Current (Vc c ) 60 80 mA 'ss (AV) Avg. Power Supply Current (V ss ) .01 1 mA IlL Input Leakage ±10 J1A Vss ~ VIN ~ Vec I Cl Clock Leakage ±10 J1A Vss ~ VeLocK ~ Voo lol[2] Data Bus Leakage in Input Mode -100 -2.0 J1A mA VSS~VIN ~VsS+O.8V IFl 3.7 } IOL = 1.9mA on all outputs, IOH = 150tlA. V Address and Data Bus Leakage During HOLD +10 -100 Symbol Cq, C,N COUT Vec = Voo = VSS = OV, Parameter Clock Capacitance Input Capacitance Output Capacitance Max. Unit 17 25 pf 10 pf 20 = Vec = VSS + O.45V TYPICAL SUPPLY CURRENT VS. TEMPERATURE, NORMALIZED.[3] 1.5,.....-----r-----or----_ Typ. 10 VAOOR/OATA VAOOR/OATA VBS = -5V 6 Vss+O.8V~VIN~Vee J1A CAPACITANCE T A = 25°C } Operation TCy = .38J,Lsec Test Condition fc = 1 MHz Unmeasured Pins to- Z w a:: a:: :> (J 1.0 > ..J r------""""=-~---+__--~ Q" Q" pf Returned to Vss NOTES: 1. The RESET signal must be active for a minimum of 3 clock cycles. 2. When oBIN is high and V,N > VIH an internal active pull up will be switched onto the Data Bus. 3. AI supply / ATA = -O.45%f C. :> (I) 0.5 - - - - - +.1-.----+5"'-0---......J+ 0 25 75 AMBIENT TEMPERATURE (OC) DATA BUS CHARACTERISTIC DURING DBIN MAX °o~--""""'-----_----3llo-- Vee 5-25 SILICON GATE MOS 8080A-2 A.C. CHARACTERISTICS TA = O°C to 70°C, Vee = +12V ± 5%, VCC Symbol = +5V ± 5%, Vss = -5V ± 5%, Vss Parameter = OV, Unless Otherwise Noted Min. Max. Unit .38 2.0 /lsec 50 nsec tCy[31 Clock Period t r , tf Clock Rise and Fall Time 0 t¢1 (j>1 Pulse Width 60 nsec !¢2 l/>2 Pulse Width 175 nsec t01 Delay (j>1 to (j>2 0 nsec t02 Delay 2 Leading Edges 70 nsec tOA [2] Address Output Delay From (j>2 175 nsec too [2] Data Output Delay From (j>2 200 nsec toc [2] Signal Output Delay From ¢1, or (/>2 (SYNC, WR,WAIT, HLOA) 120 nsec tOF [2] DSIN Delay From 140 nsec tOI[1] Delay for Input Bus to Enter Input Mode tOF nsec tOS1 Data Setup Time During TIMING WAVEFORMS 25 lP2 [14] ~1 }CL=50pf nsec 20 and DBIN } CL = 100pf (Note: Timing measurements are made at the following reference voltages: CLOCK "1" = 8.0V "0" = 1.0V; INPUTS "1" = 3.3V, "0" = 0.8V; OUTPUTS "1" = 2.0V, "0" = 0.8V.) ift., 'II --. lP1 Test Condition -I t CY -. to, r~ f\ J ~ 71\ }\ - 4 - t 2----'1 4~ <1>2 ... A 1S -A }~ to3~1 --.1 t 02 .- .. --"i o - - - - - - - - -........- - lr-----.x= ~ 0 7 .0 0 to! \.- ---l 1-........ 1.- @I ~,...OATA IN ~ ~A!.A_O~T ) , ..... iIIf-- t ow _, ,---. ~tOS2-' ~ t oc I-+-- -t-1P--------+~\1 ------------------+----11 ... / I - \ - ~tDF-.1 - --+o-----++---+--+--++----t+"--t -X@ t READY -;:r... lIl tH_--. _ _~_;__... WAIT t oc --. HOLD "" ~H i f4--t OO - ' toHI"'- -~ IJ.....-......---H--.~...- ~ t os1 - . t oc OBIN ~ ~ - - - - - - - - -......."""1 ~ J tAW--++---~·1 ---------oo+---....."rl-....------ --,..... . . .J~-t-1.- SYNC - ~I- ~J- ~r- -=t --- -- ---- ------ ---- ~tOA~ ..-too-'I -ll ~ .... 1..- t H -.1 1.- .-X@ IX - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -......tr . ~; .... I~..,..I~- .......... HLOA -------------------------------------------,t"-f INT ~-----------------_-:-'Xr ~ ~t _~LI~-"""""Ij,.. t,s!=-= tH~ INTE 5-26 ... SILICON GATE MOS 8080A-2 A.C. CHARACTERISTICS (Continued) TA = O°C to 70°C, VOD = +12V ± 5%, Vee = +5V ± 5%, V BB = -5V ± 5%, Vss = OV, Unless Otherwise Noted Symbol Min. Parameter Max. Unit tOS2 Data Setup Time to 2 During DBIN tiE [2] INTE Output Delay From 1 in Halt Mode) 100 nsec tH Hold Time From ep2 (READY, INT, HOLD) 0 nsec tFD Delay to Float During Hold (Address and Data Bus) tAW [2] Address Stable Prior to WR [5] nsec tow [2] Output Data Stable Prior to WR [6] nsec tWD[2] Output Data Stable From WR [7] nsec tWA [2] Address Stable From WR [7] nsec tHF[2] HLDA to Float Delay [8] nsec tWF[2] WR to Float Delay [9] nsec tAH[2] Address Hold Time After DBIN During HLDA -20 nsec Test Condition nsec 130 nsec [1] 200 nsec 120 CL = 50pf nsec - CL = 100pf: Address, Data CL =50pf: WR, HLDA, DBIN -- - - NOTES: 1. Data input should be enabled with DBIN status. No bus conflict can then occur and data hold time is assured. tOH = 50 ns or tOF. whichever is less. 2. Load Circuit. t/), +5V 2.1K 8080A OUTPUT A'S-AO to3. tCY tWA 0 7 -00 ,. - = t03 + t r4>2 + t4>2 + tf4>2 + t02 + t r4>1 TYPICAL ~ ~ 380ns. OUTPUT DELAY VS. ~ CAPACITANCE +20,....----.....-------,------y------. two .=. > SYNC «-J +10 w 0 t- DBIN O :::> Q.. t- :::> 0 -10 <1 WR o -50 t oc READY ~ +50 +100 CAPACITANCE (pf) (CACTUAL - C SPEC ) WAIT HOLD I-... t oc HLDA INT INTE I .- 4. The following are relevant when interfacing the 8080A to devices having V,H = 3.3V: a) Maximum output rise time from .8V to 3.3V = 100ns @ CL = SPEC. b) Output delay when measured to 3.0V = SPEC +60ns @ CL = SPEC. c) If CL #: SPEC, add .6ns/pF if CL> CSPEC, subtract .3ns/pF (from modified delay) if CL < CSPEC. 5. tAW = 2 tCY -t03 -t r2 -130nsec. . 6. tow = tCY -t03 -tr4>2 -170n5ec. 7. If not HLOA, two =twA = tD3 + t r2 +10n5. If HLDA, two = twA = tWF. 8. t HF = t03 + t r 4>2 -SOns. 9. twF = t03 + t rcf)2 -10ns 10. Data in must be stable for this period during DBIN °T3. Both tOS1 and tOS2 must be satisfied. 11. Ready signal must be stable for this period during T2 or TW. (Must be externally synchronized.) 12. Hold signal must be stable for this period during T2 or TW when entering hold mode, and during T3, T4, T5 and TWH when in hold mode. (External synchronization is not required.) 13. Interrupt signal must be uable during this period of the last clock cycle of any instruction in order to be recognized on the followi,1g instruction. (External synchronization is not required.) 14. This timing diagram shows timing relationships only; it does not represent any s~ific machine cycle. 5-27 intel®. Silicon Gate MOS M8080A SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSOR • Sixteen Bit Stack Pointer and Stack Manipulation Instructions for Rapid Switching of the Program Environment • Full Military Temperature Range -55°C to +125°C • ±10% Power Supply Tolerance • 2 J-Ls Instruction Cycle • Powerful Problem Solving Instruction Set • Decimal,Binary and Double Precision Arithmetic • Ability to Provide Priority Vectored Interrupts • Six General Purpose Registers and an Accumulator • 512 Directly Addressed I/O Ports • Sixteen Bit Program Counter for Directly Addressing up to 64K Bytes of Memory • TTL Drive Capability The Intel® MaOaOA is a complete a-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip using Intel's n-channel silicon gate MaS process. This offers the user a high performance solution to control and processing applications. The MaOaOA contains six a-bit general purpose working registers and an accumulator. The six general purpose registers may be addressed individually or in pairs providing both single and double precision operators. Arithmetic and logical instructions set or reset four testable flags. A fifth flag provides decimal arithmetic operation. The MaOaOA has an external stack feature wherein any portion of memory may be used as a last in/first out stack to store/ retrieve the contents of the accumulator, flags, program counter and all of the six general purpose registers. The sixteen bit stack pointer controls the addressing of this external stack. This stack gives the MaOaOA the ability to easily handle multiple level priority interrupts by rapidly storing and restoring processor status. It also provides almost unlimited subroutine nesting. This microprocessor has been designed to simplify systems design. Separate l6-line address and a-line bi-directional data busses are used to facilitate easy interface to memory and I/O. Signals to control the interface to memory and I/O are provided directly by the MaOaOA. Ultimate control of the address and data busses resides with the HOLD signal. It provides the ability to suspend processor operation and force the address and data busses into a high impedance state. This permits ORtying these busses with other controlling devices for (DMA) direct memory access or mUlti-processor operation. 5-29 SILICON GATE MOS M8080A INSTRUCTION SET The accumulator group instructions include arithmetic and logical operators with direct, indirect, and immediate addressing modes. increment and decrement memory, the six general registers and the accumulator is provided as well as extended increment and decrement instructions to operate on the register pairs and stack pointer. Further capability is provided by the ability to rotate the accumulator left or right through or arou nd the carry bit. Move, load, and store instruction groups provide the ability to move either 8 or 16 bits of data between memory, the six working registers and the accumulator using direct, indirect, and immediate addressing modes. The abil ity to branch to different portions of the program is provided with jump, jump conditional, and computed jumps. Also the ability to call to and return from subroutines is provided both conditionally and unconditionally. The RESTART (or single byte call instruction) is useful for interrupt vector operation. Double precision operators such as stack manipulation and double add instructions extend both the arithmetic and interrupt handling capability of the MaOaOA. The ability to Input and output may be accomplished using memory ad- . dresses as I/O ports or the directly addressed I/O provided for in the MaOaOA instruction set. The following special instruction group completes the Ma080A instruction set: the NOP instruction, HALT to stop processor execution and the DAA instructions provide decimal arithmetic capability. STC allows the carry flag to be directly set, and the CMC instruction allows it to be complemented. CMA complements the contents of the accumulator and XCHG exchanges the contents of two 16-bit register pairs directly. Data and Instruction Formats Data in the M80aOA is stored in the form of 8-bit binary integers. All data transfers to the system data bus will be in the same format. ID 7 D6 Ds D4 D3 D2 D1 Dol DATA WORD The program instructions may be one, two, or three bytes in length. Multiple byte instructions must be stored in successive words in program memory. The instruction formats then depend on the particu lar operation executed. TYPICAL INSTRUCTIONS One Byte Instructions I0 7 Register to regist~r, memory reference, arithmetic or logical, rotate, return, push, pop, enable or disable Interrupt instructions 06 05 0 4 03 02 OLDOJ OPCOOE Two Byte Instru·ctions I OP CODE D1 DO I OPERAND 1 0 7 D6 D5 D4 D3 D2 D, DO D D 1 0 7 D6 D5 D4 3 2 Immediate mode or I/O instructions Three Byte Instructions I OP CODE D1 DO I LOW ADDRESS OR OPERAND 1 0 1 DO I HIGH ADDRESSOR OPERAND 2 1 0 7 D6 Os 04 03 D2 0 1 DO 0 3 O2 1 0 7 D6 Os 04 1 0 7 D6 Ds 04 D3 D2 Jump, call or direct load and store instructions For the M80aOA a logic "1" is defined as a high level and a logic "0" is defined as a low level. 5-30 SILICON GATE MOS M8080A INSTRUCTION SET Summary of Processor Instructions Mnemonic Description 07 06 MOV r1 ,r2 MOV M,r MOVr,M HlT MVIr MVIM INR r OCR r INR M OCR M ADO r ADC r SUB r SBB r Move register to register Move register to memory Move memory to register Halt Move immediate register Move immediate memory Increment register Decrement register Increment memory Decrement memory Add register to A Add register to A with carry Subtract register from A Subtract register from A with borrow And register with A Exclusive Or register with A Or register with A Compare register with A Add memory to A Add memory to A with carry Subtract memory from A Subtract memory from A with borrow And memory with A Exclusive ar memory with A Or memory with A Compare memory with A Add immediate to A Add immediate to A with carry Subtract immediate from A Subtract immediate from A with borrow And immediate with A Exclusive Or immediate with A Or immediate with A Compare immediate with A Rotate A left Rotate A right Rotate A left through carry Rotate A right through carry Jump unconditional Jump on carry Jump on no carry Jump on zero Jump on no zero Jump on positive Jump on minus Jump on parity even Jump on parity odd Call unconditional Call on carry Call on no carry Call on zero Call on no zero Call on positive Call on minus Call on parity even Call on parity odd Return Return on carry Return on no carry 0 0 0 0 0 0 0 0 0 0 1 1 1 1 ANA r XRA r ORA r CMPr ADD M AOC M SUB M SBB M ANAM XRA M ORA M CMPM ADI ACI SUI SBI ANI XRI ORI CPI RLC RRC RAL RAR JMP JC JNC JZ JNZ JP JM JPE JPO CALL CC CNC CZ CNZ CP CM CPE CPO RET RC RNC NOTES: Instruction Code (1) Os 04 03 02 0, Do 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 S S 1 1 1 1 1 1 1 1 S S S S S S 1 1 1 1 0 0 0 0 S S S S S S 0 0 0 0 0 1 0 1 S S S S 5 7 7 7 7 10 5 5 10 10 4 4 4 4 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 S S S S 1 1 1 1 S S S S 1 1 1 1 S S S S 0 0 0 0 4 4 4 4 7 7 7 7 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 Clock (21 Cycles 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 7 7 4 4 4 4 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 10 10 10 10 10 10 10 10 10 17 11/17 11/17 11/17 11/17 11/17 11/17 llf17 l1f17 10 5/11 5/11 Mnemonic Description RZ RNZ RP RM RPE RPO RST IN OUT LXI B Return on zero Return on no zero Return on positive Return on minus Return on parity even Return on parity odd Restart Input Output Load Immediate register Pair B & C LXI 0 Load immediate register Pair 0 & E LXI H Load immediate register Pair H & L LXISP Load immediate stack pointer PUSH B Push register Pair B & C on stack PUSH 0 Push register Pair 0 & E on stack PUSH H Push register Pair H & L on stack PUSH PSW Push A and Flags on stack POP B Pop register pair B & C off stack POP 0 Pop register pair 0 & E off stack POP H Pop register pair H & L off stack POP PSW Pop A and Flags off stack STA Store A direct LOA Load A direct XCHG Exchange 0 & E, H & L Registers XTHL Exchange top of stack, H& L SPHL H & L to stack pointer PCHL H & L to program counter DAD B Add B & C to H & L DAD 0 Add 0 & E to H & L DAD H Add H & L to H & L DAD SP Add stack pointer to H & l STAX B Store A indirect STAX 0 Store A indirect LOAX B Load A indirect Load A indirect LOAX 0 INX B Increment B & C registers INX 0 Increment 0 & E registers INX H Increment H & L registers INX SP Increment stack pointer OCX B Decrement B & C OCX 0 Decrement 0 & E OCX H Decrement H & L OCX SP Decrement stack pointer CMA Complement A STC Set carry CMC Complement carry OAA Decimal adjust A SHLD Store H & l direct LHlO Load H & L direct EI Enable Interrupts 01 Disable interrupt NOP No-operation 1. DOD or SSS - 000 B - 001 C - 010 0 - 011 E - 100 H - 101 L - 110 Memory - 111 A. 2. Two possible cycle times, (5/11) indicate instruction cycles dependent on condition flags. 07 06 Instruction Code [n Os 04 03 02 0 1 00 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 A 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 A 1 1 0 1 0 0 0 0 0 1 0 1 0 0 0 A 1 1 0 0 0 0 0 0 C 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 Clock (2) Cycles 5/11 5/11 5/11 5/11 5/11 5/11 11 10 10 10 10 0 10 0 0 0 0 10 11 11 11 0 0 11 0 10 10 10 10 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 13 13 4 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 18 5 5 10 10 10 10 7 7 7 7 5 5 5 5 5 5 5 5 4 4 4 4 16 16 4 4 4 SILICON GATE MOS M8080A M8080A FUNCTIONAL PIN DEFINITION The following describes the function of all of the M8080A I/O pi ns. Several of the descriptions refer to internal tim ing periods. 1 2 3 4 A15-AO (output' three~state) ADDRESS BUS; the address bus provides the address to memory (up to 64K 8-bit words) or denotes the I/O device number for up to 256 input and 256 output devices. Ao is the least significant address bit. 5 07 -Do (input/output three-state) DATA BUS; the data bus provides bi-directional communication between the CPU, memory, and I/O devices for instructions and data transfers. Also, during the first clock cycle of each machine cycle, the M8080A outputs a status word on the data bus that describes the current machine cycle. Do is the least significant bit. SYNC (output) SYNCHRONIZING SIGNAL; the SYNC pin provides a signal to indicate the beginning of each machine cycle. WR DBIN (output) DATA BUS IN; the DBIN signal indicates to external circuits that the data bus is in the input mode. This signal should be used to enable the gating of data onto the M8080A data bus from memory or I/O. READY (input) READY; the READY signal indicates to the M8080A that valid memory or input data is available on the M8080A data bus. This signal is used to synchronize the CPU with slower memory or I/O devices. If after sending an address out the M8080A does not receive a READY input, the M8080A will enter a WAIT state for as long as the READY line is low. READY can also be used to single step the CPU. WAIT (output) WAIT; the WAIT signal acknowledges that the CPU is in a WAIT state. WR (output) WRITE; the WR signal is used for memory WRITE or I/O output control. The data on the data bus is stable while the WR signal is active low (WR = 0). HOLD (input) HO LD; the HO LD signal requests the CPU to enter the HO LD state. The HO LD state allows an external device to gain control of the M8080A address and data bus as soon as the M8080A has completed its use of these buses for the current machine cycle. It is recognized under the following conditions: • the CPU is in the HALT state. • the CPU is in the T2 or TW state and the READY signal is active. As a result of entering the HOLD state the CPU ADDRESS BUS (A 15 -A o ) and DATA BUS (0 7 -0 0 ) will be in their high impedance state. The CPU acknowledges its state with the HOLD ACKNOWLEDGE (HLDA) pin. HLDA (output) HOLD ACKNOWLEDGE; the HLDA signal appears in response to the HOLD signal and indicates that the data and address bus SYNC +5V 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 INTE~ M8080A 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 All A14 A13 A12 o A1S o Ag As o A7 A6 As o A4 A3 +12V A2 Al Ao WAIT READY ¢l HLDA Pin Configuration will go to the high impedance state. The H LOA signal begins at: • T3 for READ memory or input. • The Clock Period following T3 for WR ITE memory or OUTPUT operation. In either case, the H LOA signal appears after the rising edge of (/)1 and high impedance occurs after the rising edge of (/)2. INTE (output) INTE R RUPT ENAB LE; indicates the content of the internal interrupt enable flip/flop. This flip/flop may be set or reset by the Enable and Disable Interrupt instructions and inhibits interrupts from being accepted by the CPU when it is reset. It is automatically reset (disabling further interrupts) at time T 1 of the instruction fetch cycle (M 1) when an interrupt is accepted and is also reset by the RESET signal. INT (input) INTERRUPT REQUEST; the CPU recognizes an interrupt request on this line at the end of the current instruction or while halted. If the CPU is in the HOLD state or if the Interrupt Enable flip/flop is reset it will not honor the request. RESET (input) [1] RESET; while the RESET signal is activated, the content of the program counter is cleared. After RESET, the program will start at location 0 in memory. The INTE and HLDA flip/flops are also reset. Note that the flags, accumulator, stack pointer, and registers are not cleared. Vss Ground Reference Vee +12 Volts ±10%. Vee +5 Volts ±10%. Vs s -5 Volts ±10%. ¢1, ¢2 2 externally supplied clock phases. (non TTL compatible) 5-32 SILICON GATE MOS M8080A ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias -55°C to +125°C Storage T emperatu re .. . . . . . . . . . . . . . _65° C to + 150° C All Input or Output Voltages With Respect to VBB -0.3V to +20V Vcc, Voo and Vss With Respect to VBB -0.3V to +20V Power Dissipation . . . . . . . . . . . .. 1.7W *COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. D.C. CHARACTERISTICS TA = -55°C to +125°C, VOD = +12V ±10%, Vee = +5V ±10%, VBB = -5V ±10%, Vss = OV, Unless Otherwise Noted. Symbol Min. Parameter Typ. Max. Unit Test Condition VILC Clock Input Low Voltage Vss-l Vss+0.8 V VIHC Clock Input High Voltage 8.5 Voo+1 V V IL Input Low Voltage Vss-l Vss +0.8 V V IH Input High Voltage 3.0 Vcc+1 V VOL Output Low Voltage 0.45 V VO H Output High Voltage IOD(AV) Avg. Power Supply Current (V oo ) 50 80 rnA ICC (AV) Avg. Power Supply Current (Vec) 60 100 mA IBB(AV) Avg. Power Supply Current (V BB ) .01 1 mA IlL Input Leakage ±10 J1A Vss ~ VIN ~ V cc I CL I DL [2] Clock Leakage ±10 J1A Vss ~ VCLOCK ~ VDD Data Bus Leakage in I nput Mode -100 -2.0 J1A rnA VSS ~VIN ~VSS +O.~V +10 -100 J1A IFL } IOL Address and Data Bus Leakage During HOLD } Operation T Cy = 25°C Vec Symbol C¢ = V OD VADDR/DATA VADDR/DATA Clock Capacitance CIN I nput Capacitance CO UT Output Capacitance = VCC = Vss + O.45V TYPICAL SUPPLY CURRENT VS. TEMPERATURE, NORMALIZEO.l3] = Vss = OV, VBB =-5V Parameter = .48 J.1.sec VSS +0.8V ~VIN ~VCC CAPACITANCE TA = 1.9mA on all outputs, IOH = 150J-lA. V 3.7 1.5,.....------r-----------, Typ. Max. Unit 17 25 pf Test Condition I- 2 ~ fc = 1 MHz a: 1.0 J---------:::::l~I------______I 0.5 t------J-------______I :::> u 6 10 pf Unmeasured Pins > ...J 10 20 pf Returned to Vss en 8: :::> NOTES: 1. The RESET signal must be active for a minimum of 3 clock cycles. 2. When DBIN is high and VIN > VIH an internal active pull up will -55 +50 AMBIENT TEMPERATURE be switched onto the Oata Bus. = -0.45%/ C. +125 rc) 3. ~ I supply / ~ TA DATA BUS CHARACTERISTIC DURING DBIN MAX °0"----------------------30-Vee SILICON GATE MOS M8080A A.C. CHARACTERISTICS (Continued) TA = -55°C to +125°C, VOO = +12V ±10%, Vee = +5V ±10%, VBB = -5V ±10%, Vss = OV, Unless Otherwise Noted. Symbol Min. Parameter Max. Unit 130 nsee 50 nsee tOS2 Data Setup Time to ¢2 During DBIN tOH [1] Data Hold Time From ¢2 During DBIN tiE (2) INTE Output Delay From ¢2 tRS READY Setup Time During ¢2 120 nsee tHS HOLD Setup Time to ¢2 140 nsee tiS INT Setup Time During ¢2 (During 4>1 in Halt Mode) 120 nsee tH Hold Time From ¢2 (READY, INT, HOLD) 0 nsee tFD Delay to Float During Hold (Address and Data Bus) tAW [2] Address Stable Prior to WR [5] nsee tDW[2] Output Data Stable Prior to WR [6] nsee tWD[2] Output Data Stable From WR [7] nsee tWA [2] Address Stable From WR [7] nsee tHF[2] H LOA to Float Delay [8] nsee tWF[2] WR to Float Delay [9] nsee tAH [2] Address Hold Time After DBIN During HLDA -20 nsee 200 130 Test Condition CL = 50pf nsee nsee - ~ C L =50pf - NOTES: 1. Data input should be enabled with OBIN status. No bus conflict can then occur and data hold time is assured. tOH = 50 ns or tOF, whichever is less. 2. Load Circuit. +5V 8080A OUTPUT 3. tey = t03 + t r q,2 + tq,2 + tfq,2 + tD2 + t r q,l ~ 480ns. .......... TYPICAL -----..... --- ~--- ....... +20 oS > SYNC « ~ OUTPUT DELAY VS. ~ CAPACITANCE r-----~---~---_---_ +10 ..J w 0 DBIN .... :::J Q. .... 0 0 -10 :::J -1 -20 -100 o -50 ~ READY +50 +100 CAPAC IT ANCE (pf) (CACTUAL - CSPEC ) WAIT HOLD 4. The following are relevant when interfacing the M8080A to devices having VI H fa- * ~ t HLDA INT INTE oe ' - = 3.3V: a) Maximum output r'ise time from .8V to 3.3V = lOOns @ CL = SPEC. b) Output delay when measured to 3.0V = SPEC +60n5 @ CL = SPEC. d If CL SPEC, add .6ns/pF if CL> CSPEC, subtract .3n5/pF (from modified delay) if CL 5. tAW = 2 tey -t03 -t rct>2 -140nsec. 6. tow = tCY -t03 -t rep2 -170nsec. 7. If not HLOA, two = tWA = t03 + t r¢2 +10ns. If HLOA, two = tWA = tWF· < CSPEC. t H F = t03 + t r q,2 -50ns. tWF = tD3 + t r 2 -10ns Data in must be stable for this period during DBIN ·T3. Both tOS1 and tOS2 must be satisfied. Ready signal must be stable for this perio~ during T2 or TW. (Must be externally synchronized.) Hold signal must be stable for this period during T 2 or TW when entering hold mode, and during T3, T 4, T 5 and TWH when in hold mode. (External synchronization is not required.~ 13. Interrupt signal must be stable during this period of the last clock cycle of any instruction in order to be recognized on the following instruction. (External synchronization is not required.) 14. This timing diagram shows timing relationships only; it does not represent any specific machine cycle. 8. 9. 10. 11. 12. 5-34 SILICON GATE MOS M8080A A.C. CHARACTERISTICS TA = -55°C to +125°C, Voo = +12V ±10%, Vee = +5V ±10%, VBB = -5V ±10%, Vss = OV, Unless Otherwise Noted. Symbol Parameter Min. Max. Unit 0.48 2.0 Jisec 50 nsec tCy[3] Clock Period t r , tf Clock Rise and Fall Time 0 t(/>l epl Pulse Width 60 nsec tep2 cI>2 Pulse Width 220 nsec t01 Delay epl to 4>2 0 nsec t02 Delay ~2 to ~1 80 nsec t03 Delay ~1 to ~2 Leading Edges 80 nsec tOA [2) Address Output Delay From too [2] Data Output Delay From ~2 toc [2] Signal Output Delay From tOF [2] DBIN Delay From tOI[l) Delay for Input Bus to Enter Input Mode tOSl Data Setup Time During TIMING WAVEFORMS I ~1, or ~2 200 nsec 220 nsec 140 nsec 150 nsec tOF nsec (SYNC, WR,WAIT,HLDA) ep2 25 [14] --. ~2 ~1 - - CL = 50pf - nsec 30 and DBIN Test Condition (Note: Timing measurements are made at the following reference voltages: CLOCK "1" = 7.0V, "0" = 1.0V; INPUTS "1" = 3.0V, "0" = 0.8V; OUTPUTS "1" = 2.0V, "0" = 0.8V.) .. 01 F\I ·t ey r~ f\ ...-to2 - " 1- 7~ -J .... t o3 .....! --.1 --x ...-t OA -'! .--too--'I ... r T - . t oc 14- t\ t 02 ~ ~~ Jf\ .., r- ~ I~ ~ ..... ~ .-- .. - -=1 --- -- -. to! 1'- --t t oH I4-- --- ----~~ ~--- ~-- -\- --. i f.--t OO - ' ------ __+:=: J~~A I~ ~ - 'osl1=-1 _I ) I DATA -- - ----- ~-- .. ~tow ~ OUT ..- t OS2 - ' i I tocl..- t .... I toF~1 ! -~~-------L --tRsl~ ~@ ------------ t H --. WAIT t oc ,tHil'- r.-t oc -"'" HOLD -f ! i I ~t READY r I - - ~tAW ~ ~toF-.1 DBIN 01 1 1 ....,~ SYNC --. -\ ~I &~~I IRS""':' loe -I I I 1- I li _ t H -.; I@ 1·- I~ --.r~;I~ HLDA -I~ ~~ [I- INT tH~ INTE 5-35 .... ROMs 8702A 8704 8708 8302 8308 8316A Silicon Gate MOS 8702A 2048 BIT ERASABLE AND ELECTRICALLY REPROGRAMMABLE READ ONLY MEMORY • Access Time -1.3 ~sec Max. • Fast Programming - 2 Minutes for All 2048 Bits • Fully Decoded, 256 x 8 Organization • Static MOS - No Clocks Required • Inputs and Outputs TTL Compatible • Three-State Output Capability OR-Tie • Simple Memory Expansion Chip Select Input Lead The 8702A is a 256 word by 8 bit electrically programmable ROM ideally suited for microcomputer system development where fast turn-around and pattern experimentation are important. The 8702A undergoes complete programming and functional testing on each bit position prior to shipment, thus insuring 100% programmability. The 8702A is packaged in a 24 pin dual-in line package with a transparent quartz lid. The transparent quartz lid allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written into the device. This procedure can be repeated as many times as required. The circuitry of the 8702A is entirely static; no clocks are required. A pin-for-pin metal mask programmed ROM, the Intel 8302, is ideal for large volume production runs systems initially using the 8702A. ~f The 8702A is fabricated with silicon gate technology. This low threshold technology allows the design and production of higher performance MOS circuits and provides a higher functional density on a monolithic chip than conventional MOS technologies. BLOCK DIAGRAM PIN CONFIGURATION A2 Voo A, Vee Ao Vee *DATA OUT 1 A3 *DATA OUT 2 A4 *DATA OUT 3 As *DATA OUT 4 A6 *DATA OUT 5 A7 DATA OUT 1 OUTPUT BUFFERS PROGRAM ........ 2048 BIT PROM MATRIX (256 X 8) *DATA OUT 6 9 16 VGG *DATA OUT 7 10 15 Vee *DATA OUT 8 11 (MSB) 14 CS 12 13 PROGRAM Vee DATA OUT 8 *THIS PIN IS THE DATA INPUT LEAD DURING PROGRAMMING. PIN NAMES ADDRESS INPUTS Ao-A7 CS CHIP SELECT INPUT 001- 002 DATA OUTPUTS 5-37 SILICON GATE MOS 8702A PIN CONNECTIONS The external lead connections to the 8702A differ, depending on whether the device is being programmed (1) or used in read. mode. (See following table.) 12 15 14 13 16 22 23 (Vee) (Vee) (Vee) (Program) (CS)· (VBB ) (VGG Read Vee Vee Vee VGG Vee Vee Programming GND Program Pulse GND GND Vee Pulsed VGG (V, L4P ) GND GND MODE . ) ABSOLUTE MAXIMUM RATINGS· 0 *COMMENT Ambient Temperature Under Bias OOC to + 70 C Storage Temperature -65°C to +125 0 C Soldering Temperature of Leads (10 sec) . . . . . . .. +300 oC Power Dissipation 2 Watts Read Operation: Input Voltages and Supply Stresses above those listed under"Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device rei iabil ity. Voltages with respect to Vee +0.5V to -20V Program Operation: Input Voltages and Supply Voltages with respect to Vee -48V READ OPERATION D.C. AND OPERATING CHARACTERISTICS . (2) . TA = aoc to 70oC, Vee = +5V±5%, Voo = -9V±5%, VGG = -9V±5%, unless otherwise noted. TypJ3) MAX. SYMBOL TEST III Address and Ch ip Select Input Load Current 10 fJA V IN = O.OV I lO Output Leakage Current 10 JJA V OUT = O.OV, CS = Vee -2 1000 Power Supply Current 5 10 mA VGG=Vee,CS=Vee-2 10l = O.OmA, T A = 2Soc 1001 Power Supply Current 35 SO mA CS=Vcc -2 10l =O.OmA, T A = 2SoC 1002 Power Supply Current 32 46 mA CS=O.O MIN. UNIT CONDITIONS ""'" 10l =O.OmA, T A = 2SoC Note 1: Note 2: Note 3: 1003 Power Supply Current 38.5 60 mA CS=Vec -2 10l =O.OmA , T A = OOC leF1 Output Clamp Current 8 14 mA V OUT = -l.QV, T A = OOC V = -1.0V, TA = 2SoC OUT leF2 Output Clamp Current 13 mA IGG Gate Supply Current 10 fJA V,l1 Input Low Voltage for n 0.65 -1.0 > Continuous Operation ~ V L Interface V1L2 Input Low Voltage for MOS Interface V 1H Address and Chip Select Input High Voltage IOl Output Sink Current VOL Output Low Voltage V OH Output High Voltage Voo Vec- 6 V V cc -2 Vee +0.3 V 1.6 mA 4 -.7 0.45 3.5 V OUT = 0.45V V IOl V IOH = 1.6mA = -2001lA In the programming mode, the data inputs 1-8 are pins 4-11 respectively. es = GN O. VGG may be clocked to reduce power dissipation. In this mode average 100 increases in proportion to VGG duty cycle. (See p. 5) 0 Typical values are at nominal voltages and T A = 25 C. 5-38 SILICON GATE MOS 8702A A.C. CHARACTERISTICS TA = 00 C to +70°C, Vcc = +5V ±5%, Voo = -9V ±5%, VGG MINIMUM TEST SYMBOL = -9V ±5% unless otherwise noted TYPICAL MAXIMUM UNIT 1 Freq. Repetition Rate tOH Previous read data val id 100 ns tAcc t ovGG Address to output delay 1.3 p.s 400 JlS ns Clocked VGG set up Chip select delay t es [2] MHz 1.0 teo Output delay from CS 900 ns too Output deselect 400 ns tOHC Data out hold in clocked VGG mode (Note 1) 5 JlS Note 1. The output will remain valid for tOHe as long as clocked VGG is at Vee. An address change may occur as soon as the output is sensed (clocked VGG may still be at Vee). Data becomes invalid for the old address when clocked VGG is returned to VGG. 2. For this option please specify 8702AL CAPACITANCE* SYMBOL ~ TEST MINIMUM C 1N Input Capacitance COUT C VGG Output Capacitance TYPICAL MAXIMUM UNIT 8 15 pF 10 15 pF 30 pF VGG Capacitance (Clocked VGG Mode) CONDITIONS '1N= Vee } CS = Vce VOUT = Vee VGG = Vce All unused pins are at A.C. ground This parameter is periodically sampled and is not 100% tested. B) Clocked V GG Operation SWITCHING CHARACTERISTICS xl ~ CYCLE: TIME - 1 FREO '- VIHXI,0"lo ADDRESS ~ I V I------------..J Conditions of Test: Input pulse amplitudes: 0 to 4V; t R ' t F ::; 50 ns . Output load is 1 TTL gate; measurements made at output of TTL gate (t pD ~ 15 ns) ._ 90% 1L • \1 • I~--- I ' Cs VIH 1 1 1 : I---~Ons_____' \1--------11---------Vcc\~ : J I:r---- ----i : I V1L -I I.- A) Constant VGG Operation --XI CYCLE TIME I 1H V ){~10% I ADDRESS V1l _ 1H V cs I/F REO CLOCKED GG V Vee; 90% ----I t cs ill I..... I V1l ~ I I ' : t-- : /: GG toH--1 V I ,H I ADDRESS , I v: V V1L .A ,,,r---;;... . VGG 10% V OH DATA OUT VOL DATA ---fe' I I -l I tOD~ GG :: I I / I" t l - - - - - - J I I I I ~50ns ~~~: \ : . - tACC - - - \• V O l ~ too - V teo L·'·'; DV - ---: I cs - ~~Ons -, I VCC, \ ' : CLOCKED VGG ---7 I NOTE 2 '\ ~~t I I I I I 1L CS V1l I I V 1----------------I I ---f ~. 'OHC I I I DESELECTIDN OF DATA OUTPUT IN DR·TlE OPERATION ,H V 1H \-- (SEE NOTE 11 -I DATA OUT I VOH 7DATA l OUT : DV tACC ------------J, . . . .- --- ~ "I t {' ..J NOTE 1: The output will remain valid tor tOHe as long as clocked VGG is at Vee. An address change may occur as soon as the output is sensed (clocked VGG may still be at Vee!. Data becomes invalid for the old address when clocked VGG is returned to VGG' f- ~OTE 2: It CS makes a transition from VI L to VIH while clocked VGG IS at VGG. then deselection of output occurs at too as shown in static operation with constant VGG. 5-39 SILICON GATE MOS 8702A TYPICAL CHARACTERISTICS OUTPUT CURRENT VS. VDO SUPPLY VOLTAGE '00 CURRENT VS. TEMPERATURE 39 38 37 36 1 35 33 ~ 32 o _0 v oo = -9V r\ \ '\ f'\ I" ~ 31 29 I '" ~ z I Vaa:l -9V II ~ -- .P ~ ~ -~ ! _. I - -5 ~ .~ -6 -3 ~ 80 100 120 AMBIENT TEMPERATURE (OCI VOH '" O.OV => TA -3.5 t--+-~ '" 25°C 10 0 ! I I- ffi a: -I-~~iii'it---I-----j V GG '" -9V ~ ~ ~ -8 = +SV V CC a 60 -7 V oo SUPPLY VOLTAGE (V) I I I- --~ -+-_~M--+----i I 20 30 50 60 70 80 AjBIENT TEMPERATURE (oCI do a: Vee' +5V w V oo => u. u a: => -3 I--- I- 0 en I- =-9V I V aa = -9V V OH = O.OV i:... ~ I--- => 0 % 2-4L-_"""'--_.........._ ............_ I--- ~ ~ --~ rr % .........._----'_ _L.-----' _0 -4 OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE AVERAGE CURRENT VS. DUTY CYCLE FOR CLOCKED VGG 45 ~ ! ... V CC 12.0 ~ :ll: - I- ~=> I ~ I 0 ..F O.OV 30 6.0 ffi > c( +1 [ T4 '" 25°C 20 f- 15 o -1 -i.- '" V 1H +3 +2 I .--V I ---- '000 5 -2 I 25 10 -3 '" -9V cs w C) c( 0 -4 V oo 1001 35 '" 25°C f-CS '" I '" -9V 8.0 en ., -9V V GG ! I I I -L i CLOCKED VGG TA I I ! ! 40 V DD '" -9V a: a: 10.0 => u Z '" +5V +4 o V ~ 10 - V ~ ............ I ~ I ~ : ! 20 30 ............ -' ~ ~1.--"" i I i I ! i r II , I i 40 50 60 70 80 90 DUTY CYCLE 1%) OUTPUT VOLTAGE (VOL TS) ACCESS TIME VS. LOAD CAPACITANCE ACCESS TIME VS. TEMPERATURE 1400 ----.,..-.,.----.,..-~--r--r---r--r-__r____, 1400 ---.--..----.--..----r--r--,--r---r----, 1300 ~-I--~_l_-~_+_-f--_+___If----+-___i 1300 ~--+--+-__+_-t-__+_-t--t--+---+----t 1200 ~--+--f--__+_-f--_+_-f----+-__If----+---i 1200 ~-4--.j-~-.j_~-t---+--+----t-----1 1100 '----+--.j--+-+--~-+---t--+---+-----i 1100 ~-4--.j-~-+---+--t---+--+----t-----1 _.....-~~.....-~ c: c: 1000 L---L-L-~~~~~r::+=r--+----1 ~ 1 000 ~-;.-~=f--+---+--+---+---t---t----1 :E :E ~ w ~ ~ w U U c( 900 I---I--~_l_-~_l_-~__+_-f--_t____i CI.l 800 ~-+~I---+-____4--+- 1 TTL LOAD 700 ~-4---11---+----+--+-- V Vee oo ~ u -f- U = -9V - 0 10 20 30 40 50 60 70 80 ~~-+---4--+--~-+---+--+---t-----t 1 TTL LOAD::. 20 pf = +5V 600 ...--t--+---t--t- Vee = -9V VGG = -9V 500 ~-+--+--+--~__+_-f---t--t---+----t I---I--~-l--~_+_-t--__+_-f---t-___i 0 800 700 I---t--+--+--t- Vee f- 6001---4----+--+---+--t- VGG = -9V - TA = 25°C 500 900 ~-+----f---t--+---t--+--_t_-t---t----t « = +5V 10 90 100 20 30 40 50 60 AMBIENT TEMPERATURE LOAD CAPACITANCE (pF) 5·40 ~ I ~ ".,.- 70 rc) 80 90 I I l- ~ => o l- ..- cs=o.~t'-..... ............. :;) I- VOL" +.45V- "~ 0 I 40 Voo:l -9V ~~ ...i: NS=Vee 27 Vee" +5V l- I I ~ => u en CS = 0.0V' 28 20 ffi a: a: OUTPUTS ARE OPEN I" I" 'l 30 ---b,......:::=I===:t_ _F=l~--1 TA - INPUTS" Vee I- VOL - V aa = -9V \ V GG '" -9V - ! '" +5V V CC Vee = +5V I\. 34 ~ => u r\ II, ~ I '\ OUTPUT CURRENT VS. TEMPERATURE 90 100 SILICON GATE MOS 8702A PROGRAMMING OPERATION D.C. AND OPERATING CHARACTERISTICS FOR PROGRAMMING OPERATION TA = 25°C, Vee = OV, Vss = +12V SYMBOL ± 10%, CS TEST Address and Data Input Load Current Program and VG G Load Current Vss Supply Load Current Peak 100 Supply Load Current Input High Voltage Pulsed Data Input Low Voltage Address Input Low Voltage Pulsed Input Low Voo and Program Voltage Pulsed Input Low VGG Voltage ILl1 P 'LI2P 'ss IOOp(l) VIHP V IL1P V1L2P VIL3P VIL4P = OV unless otherwise noted MIN. TYP. MAX. UNIT 10 rnA VIN = -48V 10 rnA VIN = -48V .05 200 rnA mA CONDITIONS pro,7 -48V Voo = V VGG = -35 -46 0.3 -48 V V -40 -48 V -46 -48 V -35 -40 V Note 1: lOOp flows only during VOO, VGG on time. lOOp should not be allowed to exceed 300mA for greater than supply current lOOp is typically 40 mA at 20% duty cycle. 100~sec. Average power A.C. CHARACTERISTICS FOR PROGRAMMING OPERATION TAMSIENT = 25°C, Vee = OV, Vss = + 12V TEST SYMBOL ± 10%, MIN. CS = OV unless otherwise noted TYP. Duty Cycle (Voo , VGG ) MAX. UNIT 20 % 3 ms t~pw Program Pulse Width tow Data Set Up Time 25 IlS tOH Data Hold Time 10 IlS tvw Voo , VGG Set Up 100 IlS tvo Voo , VGG Hold 10 (2) Address Complement Set Up 25 IlS tACH (2) 25 J.1S tATW Address Complement Hold Address True Set Up 10 J.1S tATH Address True Hold 10 J.1S tACW Note 2. All 8 address 255) must be 100 CONDITIONS VG G = -35V, V oo Vprog = -48V = J.1S bits must be in the complement state when pulsed Vee and VGG move to their negative levels. The addresses (0 through programmed as shown in the timing diagram for a minimum of 32 times. 5-41 SILICON GATE MOS 8702A SWITCHING CHARACTERISTICS FOR PROGRAMMING OPERATION PROGRAM OPERATION Conditions of Test: Input pulse rise and fall times :s 1J1sec CS = OV PROGRAM WAVEFORMS ---.l tACH r-I I I tACW----.l', I I o BINARY COMPLEMENT OF ADDRESS OF WORD TO BE PROGRAMMED ADDRESS BINARY ADDRESS OF WORD TO BE PROGRAMMED -40 to -48 I I I o------------~ I ~tvoi I I ~ f--tATW PULSED V oo POWER SUPPLY -46 to-48 0------------""'" PULSED VGG POWER SUPPLY -35 to-40 o--------------~ I I I PROGRAMMING PULSE I 1 - tATH-----"1 -46 to-48 I I I I I I I I --'ltOHr- I o DATA INPUT (DEVICE OUTPUT LINES) --46 to -48 DATA STABLE TIME PROGRAMMING OPERATION OF THE 8702A ADDRESS When the Data I nput for the Progra m Mode is: V,L,P = ""-48V pulsed VIHP;: "" OV Then the Data Output during the Read Mode is: Logic 1 = VOH Logic 0 WORD = 'P' on tape = VOL ='N' on tape Address Logic Level During Read Mode: Logic 0 = VIL ("" .3V) Logic 0 A6 AS A4 A3 A2 A1 AO 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 I I I I I I I I I I I I I I I I I I 1 1 1 1 1 1 255 Address Logic Level During Program Mode: = V I L2P A7 Logic 1 = V,H ( "" 3V) ( "" -40V) 5-42 Logic 1 = V, HP (-- OV) SILICON GATE MOS 8702A PROGRAMMING INSTRUCTIONS FOR THE 8702A I. Operation of the 8702A in Program Mode II. Programming of the 8702A Using Intel ® Microcomputers Initially, all 2048 bits of the ROM are in the "0" state (output low). Information is introduced by se\ectively programming "1 "s (output high) in the proper bit locations. Intel provides low cost program development systems which may be used to program its electrically programmable ROMs. Note that the programming specifications that apply to the 8702A are identical to those for Intel's 1702A. Word address selection is done by the same decoding circuitry used in the READ mode (see table on page 6 for logic levels). All 8 address bits must be in the binary complement state when pulsed VDD and VGG move to their negative levels. The addresses must be held in their binary complement state for a minimum of 25 p'sec after VDD and VGG have moved to their negative levels. The addresses must then make the transition to their true state a minimum of 10 p'sec before the program pulse is applied. The addresses should be programmed in the sequenc~ 0 through 255 for a minimum of 32 times. The eight output terminals are used as data inputs to determine the information pattern in the eight bits of each word. A low data input level (- 48V) will program a "1" and a high data input level (ground) will leave a "0" (see table on page 6). All eight bits of one word are programmed simultaneously by setting the desired bit information patterns on the data input terminals. During the programming, VGG , VDD and the Program Pulse are pulsed signals. A. Intellec® The Intellec series of program development systems, the Intellec 8/Mod 8 and Intellec 8/Mod 80, are used as program development tools for the 8008 and 8080 microprocessors respectively. As such, they are equipped with a PROM programmer card and may be used to program Intel's electrically programmable and ultraviolet erasable ROMs. An ASR-33 teletype terminal is used as the input device. Through use of the InteHec software system monitor, programs to be loaded into PROM may be typed in directly or loaded through the paper tape reader. The system monitor allows the program to be reviewed or altered at will prior to actually programming the PROM. For more complete information on these program development systems, refer to the Intel Microcomputer Catalog or the Intellec Specifications. B. Users of the SIM8 microcomputer programming systems may also program the 8702A using the MP7-03 programmer card and the appropriate control ROMs: SIM8 system-Control ROMs A0860, A0861 and A0863. 5-43 III. 8702A Erasing Procedure The 8702A may be erased by exposure to high intensity short-wave ultraviolet light at a wavelength of 2537A. The recommended integrated dose (Le., UV intensity x exposure time) is 6W-sec/cm 2• Examples of ultraviolet sources which can erase the 8702A in 10 to 20 minutes are the Model UVS-54 and Model S-52 short-wave ultraviolet lamps manufactured by Ultra-Violet Products, Inc. (5114 Walnut Grove Avenue, San Gabriel, California). The lamps should be used without short-wave filters, and the 8702A to be erased should be placed about one inch away from the lamp tubes. · :, Silicon Gate MOS 8708/8704 8192/4096 BIT ERASABLE AND ELECTRICALLY REPROGRAM MABLE READ ONLY MEMORY • 8708 1024x8 Organization • 8704 512x8 Organization • Fast Programming Typ. 100 sec. For All 8K Bits • Low Power During Programming • Access Time - 450 ns • Standard Power Supplies+12V, ±5V • Static - No Clocks Required • Inputs and Outputs TTL Compatible During Both Read and Program Modes • Three-State Output- OR-Tie Capability The Intel@8708/8704 are high speed 8192/4096 bit erasable and electrically reprogrammable ROM's (EPROM) ideally suited where fast turn around and pattern experimentation are important requirements. The 8708/8704 are packaged in a 24 pin dual-in-line package with transparent lid. The transparent lid allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written into the devices. @ A pin for pin mask programmed ROM, the Intel 8308, is available for large volume production runs of systems initially using the 8708. The 8708/8704 is fabricated with the time proven N-channel silicon gate technology. PIN CONFIGURATIONS A7 24 Vee As BLOCK DIAGRAM DATA OUTPUT 0, Os I A6 2 23 As 3 22 A4 4 21 Vea A3 5 20 CSIWE 19 Voo 18 PROGRAM 87081 8704 CS/WE- A2 6 A1 7 Ao 8 17 Os 01 9 16 07 02 10 15 06 AO·A g 03 11 14 Os ADDRESS INPUTS Vss 12 13 04 *8704 8708 = Vss =Ag PIN NAMES Ao·Ag ADDRESS INPUTS O,·Os DATA OUTPUTS CSIWE CHIP SElECTIWRITE ENABLE INPUT 5-45 CHIP SELECT LOGIC OUTPUT BUFFERS Y DECODER Y GATING X DECODER 64 X 128 ROM ARRAY SILICON GATE MOS 8708/8704 Absolute Maximum Ratings~· Temperature Under Bias Storage Temperature ,. -25°C to +85°C -~5°C to +125°C All Input or Ou'tput Voltages with Respect to VBB (except Program) . . . . . . . . . . . . . . . . . . . . . Program Input to VBB . . . . . . . . . . . . . . . . . . . . Supply Voltages Vcc and Vss with Respect to VBB. Vo o with Respect to VBB . . . . . . . . . . . . . . . . . Power Dissipation ... . .... .. . . . . . . . . . . . . . . . . . . . . .. .. .. .. ... +15V to +35V to +15V to +20V to . . . . .. -0.3V -O.3V -O.3V -O.3V 1.5W *COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability·. READ OPERATION D.C. and Operating Characteristics TA = o°c to 70°C, Vee = +5V ±5%, Voo = +12V ±5%, VeB = -5V ±5%, VSS = ov, Unless Otherwise Noted. .Symbol Parameter Min. Typ.l1] Max. Unit Conditions III Address and Chip Select Input Load Current 10 JlA Ilo Output Leakage Current 10 JlA = 5.25V VOUT = 5.25V, CS/WE = 5V 100 Voo Supply Current 50 65 mA Worst Case Supply Currents: lee Vee Supply Current 6 10 mA All Inputs High IBB VBe Supply Current 30 45 mA CS/WE Vil Input Low Voltage Vss 0.65 V VIH Input High Voltage 3.0 Vee+ 1 V VOL Output Low Voltage V IOl = 1.6mA VOH1 Output High Voltage 3.7 V IOH VOH2 Output High Voltage 2.4 V IOH = -1mA Po Power Dissipation 0.45 800 NOTES: 1. Typical values are for TA = 2Soe and nominal supply voltages. 2. The program input (Pin 18) may be tied to VSS or Vee during the read mode. 5-46 mW VIN = 5V; TA = -100JlA TA = 70°C = O°C SILICON GATE MOS 8708/8704 A.C. Characteristics TA =O°C to 70°C, Vee = +SV ±S%, Vo o = +12V ±S%, Vee = -SV ±S%, Vss = OV, Unless Otherwise Noted. Symbol Min. Parameter tAce Address to Output Delay teo Chip Select to Output Delay tOF Chip De-Select to Output Float 0 tOH Address to Output Hold 0 Capacitance£1] Symbol Typ. Max. Unit 280 4S0 ns 120 ns 120 ns ns TA = 2SoC, f = 1MHz Parameter Typ. Max. Unit Conditions CIN Input Capacitance 4 6 pF VIN=OV COUT Output Capacitance 8 12 pF VOUT=QV Note 1. This parameter is periodically sampled and not 100% tested. A.C. Test Conditions: Output Load: 1 TTL gate and CL = 100pF Input Rise and Fall Times: ~20ns Timing Measurement Reference Levels: 0.8V and 2.8V for inputs; 0.8V and 2.4V for outputs Input Pulse Levels: O.6SV to 3.0V Waveforms ADDRESS ----X--------------......J'IX,.,-------I 1 I~ tOH-----'1 I C.S./WE i I ~'--------------......."A I.--- teo ---'1 14-11- - - - t ACC _I 5-47 I i1 ~tDF---.1 1 SILICON GATE MOS 8708/8704 PROGRAMMING OPERATION Description Initially, and after each erasure, all bits of the 8708/8704 are in the "1" state (Output High). Information is introduced by selectively programming "0" into the desired bit locations. The circuit is set up for programming operation by raising the CS/WE input (Pin 20) to +12V. The word address is selected in the same manner as in the read mode. Data to be programmed are presented, 8-bits in parallel, to the data output lines (01-08). Logic levels for address and data lines and the supply voltages are the same as for the read mode. After address and data set up one program pulse (Vp) per address is applied to the program input (Pin 18). One pass through all addresses to be programmed is defined as a program loop. The number of loops (N) required is a function of the program pulse width (tpw) according to N x tpw ~ 100 ms. For program verification, program loops and read loops may be alternated as shown in waveform B. Program Characteristics TA = 25°C, Vcc = +5V ±5%, Voo = +12V ±5%, Vss = -5V ±5%, Vss = OV, CS/WE = +12V, Unless Otherwise Noted. Min. Max. Symbol Parameter tAS Address Setup Time 10 llS tcss CS/WE Setup Time 10 llS tos Data Setup Time 10 llS tAH Address Hold Time 1 llS tCH CS/WE Hold Time .5 lls tOH Data Hold Time 1 lls tOF Chip Deselect to Output Float Delay 0 tOPR Program To Read Delay tpw Program Pulse Width tpR tpF Typ. Units 120 ns 10 llS .1 1.0 ms Program Pulse Rise Time .5 2.0 llS Program Pulse Fall Time .5 2.0 llS 20 rnA 27 V Ip Programming Current Vp Program Pulse Amplitude 10 25 NOTE: Intels standard product warranty applies only to devices programmed to specifications described herein. Erasing Procedure The 8708/8704 may be erased by exposu re to high intensity short-wave ultraviolet Iight at a wavelength of 2537 A. The recommended integrated dose. (Le., UV intensity x exposure time) is 10W-sec/cm2 . Examples of ultraviolet sources which can erase the 8708/8704 in 20 to 30 minutes are the Model UVS-54 and Model S-52 short-wave ultraviolet lamps manufactured by Ultra-Violet Products, Inc. (5114 Walnut Grove Avenue, San Gabriel, California). The lamps should be used without short-wave filters, and the 8708/8704 to be erased should be placed about one inch away from the lamp tubes. 5-48 SILICON GATE MOS 8708/8704 Waveforms (Logic levels and timing reference levels same as in the Read Mode unless noted otherwise.) A) Program Mode CS/WE = +12V . . . - - - - - - - - - - - - - - - O N E PROGRAM LOOP ---------------.! I ~ ADDRESS 0 ADDRESS __ AD_D_R_ESS_1_....c ~_--·-·-·----.lX'---A-D-D-RE-SS-1-0-23--~ 26V PROGRAM PULSE OV-------II DATA °1·0S B) Read/Program/Read Transitions ~ PR~g~:M --'1 ADDRESS o tess 26V PROGRAM PULSE 0--+-------"""1 DATA °1·0 S DATA OUT VALID DATA FLOAT DATA IN VALID DATA IN VALID 5-49 DATA OUT VALID SILICON GATE MOS 8708/8704 Typical Characteristics (Nominal supply voltages unless otherwise noted): RANGE OF SUPPLY CURRENTS VS. TEMPERATURE OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE 10 80 r-----...----or----...----..,---,~ .----..----,....---~--~--, ALL POSSIBLE OPERATING CONDITIONS: Vee = 5.25V Voo = 12.6V Vee = 4.75V 81----+----t----t--~1t--~---::l~ 6 Vaa 60 =O°C TA =25°C TA =70°C ~~---#----+_'_~-+-----i TA = -5.25V =i .§ ...2 Cf.) w a:: a:: 40 ;:) 0 > ..J 41----t----#-i~,r;--t----+__-__i ~ ~ ;:) Cf.) 20 ---SPEC pEEE]f!1EJEZPlEzz$m:=:2!:;·m··;:: }Icc o'---_ _ 20 o ...l........-_------' . . I -_ _""'--- .4 .2 .6 1.0 .8 MAXIMUM JUNCTION TEMPERATURE VS. AMBIENT TEMPERATURE 150 60 100 80 ACCESS TIME VS. TEMPERATURE r------_----..,..----,....------.. 500 I 8JA = 80°CIW I 1 TTL LOAD + 100pF Vee = 5.25V Voo = 12.6V Vaa = -5.25V 100 1 - - - - - 40 400 4~=----+------+----i 300 ~~ E. u tJ ... Continuous Operation 4 VOUT = 0.45V VOUT = O.OV V 'Ol = 1.6mA V 'OH = -100 fJA VGG may be clocked to reduce power dissipation. In this mode average 100 increases in proportion to VGG duty cycle. Typical values are at nominal voltages and T A = 25°C. 5-52 SILICON GATE MOS 8302 A.C. Characteristics TA = (1J C to +70°C, Vee = +5V ±5%, Voo SYMBOL MINIMUM TYPICAL MAXIMUM UNIT 1 Repetition Rate tOH Previous read data val id tACC t ovGG t cs Address to output delay Clocked VGG set up Ch ip select delay tco Output delay from CS too t OHC Output deselect .700 MHz 100 ns 1 JJ.s 1 JJ.s ns 200 500 300 ns ns 5 Data out hold in clocked VGG mode (Note 1) JJ.s The output will remain valid for tOHC as long as clocked VGG is at Vce. An address change may occur as soon as the output is sensed (clocked VGG may still be at Vee). Data becomes invalid for the old address when clocked VGG is returned to VGG. Capacitance* SYMBOL C -9V ±5%, VGG = -9V ±5% unless otherwise noted TEST Freq. Note 1. = TA = 25°C MINIMUM TEST ,N TYPICAL Input Capacitance COUT Output Capacitance C VGG VGG Capacitance (Clocked VGGMode) MAXIMUM UNIT 5 10 pF 5 10 pF 30 pF CONDITIONS "1N= vee} All unused pins are at A.C. ground CS = VCC VOUT = VCC VGG = VCC *This parameter is periodically sampled and is not 100% tested. B) Clocked VGG Operation ~ CYCLE Switching Characteristics ADDRE~~H~ Conditions of Test: Input pulse. amplitudes: 0 to 4V; t R , t F ~ 50 ns Output load is 1 TTL gate; measurements made at. output of TTL gate (tpD ::5 15 ns) V1L :: I I I IH V CS I ,,: I I _I - - C Y C L E TIME' I / F R E O - V1L A n' I 1 ~tDV 1H _ V I V1L oH : .... 1·----tAcc-----·~1 VOL r;I ADDRESS --I I I I cs ,H V '-"L .fi. CLOCKED V GG NOTE 2 . _ ~ ~ V III I 1-+1-----....", I DATA OUT VOL I I I ---l - too ~ O~HT i-'ACC ~ VOL U I I I I I I I I I {I: . ----------1 ...... NOTE 1: The output will remain valid for tOHe as long as clocked VGG is at Vee. An address change may occur as soon as the output is sensed (clocked VGG may still be at Vee). Data becomes invalid for the old address when clocked VGG is returned to VGG' I t co ~ ...--~50ns---1 I V DATA L': : I too --, I GG I V 1L ~ ~ Ons .·. . . .i--,I I I: ~ ,',r---~----l " - to v cc, , : : 10% I DATA OUT INVALID ---------r--ISr----------v. : t---+-- DATA OUT INVALID CS "o~---f() ~ t OHC I 1L V GG 1 1 ~--- (SEE NOTE 1) I I V 1----------------- X"---- V 1H - - - f . - . - 'ACC ~ ; : DESELECTlDN OF DATA OUTPUT IN OR·TlE OPERATION ,H DESELECTION OF DATA OUTPUT IN OR·TlE OPERATION AD:~:Y:: VIL'~ / I': DATA OUT INVALID V : I /:..--------..\ '\ I DATA OUT t g~~~H --4!~--~N-~-TA-AL-~-DU-T--~\ VOL ~---- t-- --l I : I :. GG VOH-----~ I --I 'cs ~ cs CLOCKED GG V VGG V ,10 ---------_ % I ~~ons---{ '\ Vee,; : ADDRESSfi 90% >C I FREO---....l I A) Constant VGG Operation V ~ I V1L VIH TIME .- NOTE 2: If CS makes a transition from VI L to VIH while clocked VGG is at VGG, then deselection of output occurs at too as shown in static operation with constant VGG' 5-53 SILICON GATE MOS 8302 Typical Characteristics ACCESS TIME VS. LOAD CAPACITANCE 100 CURRENT VS. TEMPERATURE 39 38 37 36 35 i 34 zau 33 ~ II: II: 32 u 31 0 _0 30 \ 900 I \ vee = +5V ~ \ "I" '\ j 29 l' '- 700 - v GG = -9V \ 800 - v oo = -9V ~ INPUTS:: Vee ! I ~ I 4( t----+---+-1 TTL LOAD t-- CJ 300 V cc = +5V = -9V I---- en 200 VGG :: -9V 250C TA ::I 100 o I 40 20 t----+---+-- ~ e I-- o 20 10 30 40 50 60 80 70 .: 60 80 100 r---- t----+---+-- 0 90 100 120 -4 -3 -2 I I Vcc :: +5V ;{ ~ ~ zau ""'"" """ VGG = -9V VOL :: +.45V/ _ TA =.250C ~ ::) u ~ z 400 u u 300 4( ~ a: a: en 500 ~ w 200 100 - 1 TTL LOAD~20 p f - Vcc II +5V V DO .. -9V VGG - 80 I ~ ::) ~ :J 90 z w -3 i-- II: II: -9 ! w II: a: VOH ::I O.OV au :J TA '" 25°C a: ::) CJ -3 - V oo • -9V -VGG - -9V V OH " O.OV S ,,~ ~ :J ::) ~ ~ :J :J I- - --- ~ o 0 x % _0 .9-4 -4 AVERAGE CURRENT VS. DUTY CYCLE FOR CLOCKED VGG 45 I I I I I 40 CLOCKED VGG V 1001 35 DD :: -9V .. -9V CS :: V 1H T .. 25°C A au CJ 4( 20 a: w > 4( 15 10 --- 1000 5 o o ~ ~ 10 --~ 20 ~~ 30 ~ ~ 40 ~ .---~ 50 DUTY CYCLE (%) 5-54 ~ 60 --- ~ ~- 70 80 2030 5060 70 80 AiBIENT TEMPERATURE t"CI Vee" +5V ::) U w I- 10 r--...... k I 0 ~ z VGG :: -9V VOL· +.45V- I - - ~~ 0 Ci -10 ::I :;) 0-3.5 en 26 v GG • -9V I 0 , I -7 -8 -6 V DO SUPPL Y VOLTAGE (V) I I +5V VCC U II: 0 _0 v oo • -9V cs .. o.~ ~ ~ r--_ -5 U 30 ~~ _0 n( ;{ ! ~ C .! +4 vee· +5V j I 10 20 30 40 50 60 70 AMBI ENT TEMPERATURE (OC) Specified Operating Range _ I - = -9V I +3 III .! w ~ +2 OUTPUT CURRENT VS. TEMPERATURE OUTPUT CURRENT VS. VOOSUPPLY VOLTAGE 800 - +1 -1 OUTPUT VOLTAGE (VOLTSI 900 600 6.0~--+-~T---+-----t LOAD CAPACITANCE (pF) ACCESS TIME VS. TEMPERATURE I-- 8.0 :;) AMBIENT TEMPERATURE (OC) 700 10.0 ~ I I I I o ~ 400 V OO CS= 0.0V' 27 z au ::) ~ au u u NSIIVee 12.0 ~ 500 ~ I ." "l'" 28 Ci I---+---+--.! 600 w OUTPUTS ARE OPEN I ~ OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE ~ ~ 90 ---- 100 ~I-- ~ ~ ~rr 90 Silicon Gate MOS 8308 8192 BIT STATIC MOS READ ONLY MEMORY Organization --1024 Words x 8 Bits • Fast Access - 450 ns • Directly Compatible with 8080 CPU at Maximl)m Processor Speed • Three State Output - OR-Ti~ Capability • Two Chip Select Inputs for Easy Memory Expansion • Standard Power Supplies +12V DC, ±5V DC • ·Fully Decoded • Directly TTL Compatible - All Inputs and Outputs The Intel® 8308 is an 8,192 bit static MOS mask prog~ammable Read Only Memory organized as 1024 words by ~-bi~s. This ROM is designed for 8080 microcomputer system applications where high performance, large bit storage, and simple interfacing are important design objectives. The inputs and outputs are fully TTL compatible. A pin for pin compatible electrically programmed erasable ROM, the Intel® 8708, is available for system development and small quantity production use. Two Chip Selects are provided - CS 1 which is negative true, and CS2/CS2 which may be programmed either negative or positive true at the mask level. The 8308 read only memory is fabricated with N-channel silicon gate technology. This technology provides the designer with high performance, easy-to-use MOS circuits. BLOCK DIAGRAM PIN CONFIGURATION DATA OUT 1 A7 Vee A6 As CS1--' A5 Ag CS 2 /CS 2 . -... A4 Va8 A3 CSl A2 \bo A, CS2 /CS 2 Ao Os 0, 07 02 06 03 05 Vss 04 DATA OUT 8 OUTPUT BUFFERS 811)2 BIT ROM MATRIX (1024 X 8) Ao A, PIN NAMES AO-Ag ADDR ESS INPUTS o,-Os DATA OUTPUTS CS,. CS2 CHIP SELECT INPUTS 5-55 Ag SILICON GATE MOS 8308 Absolute Maximum Ratings* Ambient Temperature Under Bias Storage Temperature Voltage On Any Pin With Respect To Vaa . . . . . . . . . . . . . . . . . Power Dissipation *COMMENT -25°C to +85°C -65°·C to-i-150°C Stresses above those listed under"Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in' the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliabil ity. -0..3V to 20V 1.0 Watt D.C. and Operating Characteristics TA = O°C to +70°C, VCC = 5V ±5%; Vo o = 12V ±5%, Vas = -5V ±5%, Vss = OV Unless Otherwise Specified. Limits Symbol Parameter Min. TypJ1] Unit Max. Test Conditions = 0 to 5.25V ILl Input Load Current (All Input Pins Except CS, ) 10 J.l.A VIN ILCL Input Load Current on CS, 1.6 rnA ILPC Input Peak Load Current on CS, 4 rnA ILKC Input Leakage Current on CS, 10 J.l.A = 0.45V VIN = 0.8V to 3.3V VIN = 3.3V to 5.25V ILO Output Leakage Current 10 J.l.A Chip Deselected VIL Input "Low" Voltage Vss-1 0.8V V VIH Input "H igh" Voltage 3.3 Vcc+1.0 V VOL Output "Low" Voltage 0.45 V VOH' Output "High" Voltage 2.4 V VOH2 Output "High" Voltage 3.7 V Icc Power ~upplV Current Vcc .8 2 rnA 100 Power Supply Current Voo 32 60 rnA Iss Power Supply Current Vss 10~A 1 rnA Po Power Dissipation 775 rnW VIN = 2rnA IOH = -4rnA IOH = -1rnA IOL NOTE 1: Typical values for TA = 25° C and nominal supply voltage D.C. OUTPUT CHARACTERISTICS 9 ~A ::: 6to 76°C ~ 8 ~ 7 D.C. OUTPUT CHARACTERISTICS , -10 -9 / ,~I 6 5 .1J 4 '(' / ~J 2 I ~ V o~ o .1 ~ ~ .2 V .3 ~ ......... ~ V ~ ~ ~ -4 -3 VOL .5 .6 .7 .8 .9 1.0 5-56 I I ", 'lIlI /~ ~ ~ ~Ill.. -........ (( 2.4 2.6 2.8 3.0 VOH VOLTS I I TYPICAL " -2 -1 = Oto 70°C 'I', SPEf '" I I II A ~-5 SPEC .4 t 1', 1-6 / 3 ~, -7 TYPICAL J 1 'lil , -8 3.2 ~ ,....." 3.4 3.6 VOLTS 3.8 4 0 4 .2 SILICON GATE - MOS 8308 - A.C. Characteristics TA = oo.c to'+70~C, VCC = +5V ±5%; VO_D = +12V ±5%, VBB = -5V _±5%, VSS_= OV, Unless Otherwise Specif.i~d. Limits[2] Symbol Parameter Min. Typ. Max. Unit tACC Address to Output Delay Time 200- 450 ns tC01 Chip Select 1 to Output Dela.y~ime 85 160 ns teo 2 Chip Select 2 to O~tput Delay Time 125 220 Chip Deselect to Output Data float Ti~_e_ tOF conditions~of Test for A.C. Characteristics. VOH = 3.7V @ IOH = -1mA, CL = 100pF. NOTE 2: Refer to ~dd 125 220 ns .- ns 50 nanoseconds (worst case) to specified values at CAP~CI_!ANCE TA_=__ ~5°C, f= 1 MHz! VBB =-5V, VOO,. Vcc and all ot~er pins ti~~ ~o Vss. CONDITIONS OF TEST FOR A.C. CHARACTERISTICS Output Load 1 TTL Gate, and CLOAO = 100pF Input Pulse Levels . . . . . . . . . . . . . . . .. .65V to 3.3V 20 nsec Input Pulse Rise and Fall Times Timing Measurement Reference Level ........ · .... · .. · .. 2.4V VIH, VOH; 0.8V VIL, VOL Symbol Test CIN Input Capacitance CoUT Output C~pacitance Limits Typ. Max. 6pF 12pF 4-------- t ACC --------~I ADDRESS .Ao-Ag ----------~ --------------------- -------------1 . . - - - - tCo1 - - - - · 1 ---------------, ~---------------- 1 . . . . - - - - - - - t e 0 2 - - - - - -...1 5-57 SILICON GATE MOS 8308 Typical Characteristics (Nominal supply voltages unless .otherwise noted.) A OUTPUT CAPACITANCE VS. A OUTPUT DELAY 100 VS. TE""PERATURE (NORMALIZED) 1.4 1.2 +40 r-----~--_r__--~---, _ +20 t----+-----+----~<------f u W 1.1 1.0 (I) ..5- ~ .9 ~ ~ .J ~ ~ .8 0 t---:---+-------:::._--""'"'"f-- t- "- ~ .7 ::J ~ t- ::J ~ o <1 -20 ~--+_--_+__----+---__t ~ .6 ::::;~ -40 10 20 30 40 50 60 70 80 90 L . . -_ _...I..-_ _...Io....-_ _.......I.-_ _- - ' -100 o -50 ~ AMBIENT TEMPERATURE TA (OC) CS1 INPUT CHARACTERISTICS +100 +50 CAPACITANCE (pF) TACC VS. TEMPERATURE .(NORIVIALIZ~O) 1.4 2.5 1.3 2.5 1.2 1.1 2.0 ~ 1.0 .§ 1.5 )/1 -~ 1.0 .5 o / o ~/ .5 .9 .8 \ 1.5 ~ ~ ~ ~ ~ .7 \\... 1.0 --- ~ .6 2.0 2.5 o.-:::i:::::= o 10 3.0 V 1N (VOLTS) 20 30 40 50 60 70 AMBIENT TEMPERATURE TA (OC) 5-58 80 90 MCS™ CUSTOM ROM ORDER FORM 8308 ROM CUSTOMER P.O. NUMBER _ . _ OATE _ For Intel use only S# _ STO PPpp--------_ zz, _ 00 APp _ _ OATE . _ All custom 8308 ROM orders must be submitted on this form. Programming information should be sent in the form of computer punched cards or punched paper tape per the formats designated on this order form. Additional forms are available from Intel. MARKING INTEL PATTERN NUMBER ® The marking as shown at the right must contain the Intel logo, the product type (P8308), the 4-digit Intel pattern number (PPPP), a date code (XXXX), and the 2-digit chip number (DO). An optional customer identification number may be substituted for the ch ip number (ZZ). Optional Customer Number (maximum 9 characters or spaces). CUSTOMER NUMBER _ • I 8308 PPPP xxxx zz DATE CODE CHIP NUMBER OR CUSTOMER NUMBER MASK OPTION SPECIFICATIONS A. CHIP NUMBER (CHIP SELECT OPTION) Must be specified 0 or 1. The chip number will be coded in terms of positive logic where a logic "1" is high level input. Programming information should be sent in the form of computer punched cards or punched paper tape. Ineither case, a printout of the truth table should be accompanied with the order. The following general format is applicable to the programming information sent to Intel: Chip Select Truth Table Chip Number CS1 CS2 Selected 0 1 0 0 0 1 0 1 0 1 1 1 Yes Yes No No Chip Number B. ROM Truth Table Format • Data fields should be ordered beginning with the least significant address (0000) and ending with the most sig. nificant address (1023). • A data field should start with the most significant bit and end with the least significant bit. 5-59 • The data field should consist of P's and N's. A P is to indicate a high level output (most positive) and an N a low level output (most negative). In terms of positive logic, a P is defined as a logic "1" and an N is defined as a iogic "0". If the programming information is sent on a punched paper tape, then a start character, B, and an end character, F, must be used in the data field. See paragraph 2. 1. Punched Card Format An SO-column Hollerith card (preferably interpreted) punched by an IBM 026 or 029 keypunch should be submitted. The first' card will be a title card; the format is as follows: MCS™ CUSTOM ROM ORPER _FOR.M_ 8308 a. Title Card '1 NO. OF OUTPUTS 4 or 8 TITLE CARD DESIGNATION CUSTOMER'S DIVISION OR CUSTOMER'S COMPANY NAME I ' ~"/~ G.:"-'·i-i·iNl('·~ I II II I III LOCATION INTEL CUSTOMER:S ~ i ,-:~AI?~ ::.,.o#1'i:: CORP I I III ~ PIN h?14:' \.!iLI~ P/Nl I I I I II II I I I I 1 DECIMAL NUMBER INDICATING THE TRUTH TABLE NUMBER 6~30 (h', 31-34 35-54 55-57 58-66 67 68-75 I I ~ ~ ~ ~ ~!~, ~ ~ ~ ~~~ ~ ~ ~ ~ I~!~ ~~~~~~~~ ~~ ~ ~~~~ ~!~~~ ~~!~~~~~~~ ~~~~~~~~~~~~I~~~~'~~!~ ~ ~I~ ~~~, ~,,! 1I1111111 i 11111111111111 Column 1 2-5 1 1111111111111111111111111111111111111111111111111111111 2222211221121122212122222'21222122 il21112 222222222222222222212221222222 2121l2121? I) II J3) ) ) 31 )11) ) lll) )I) ) ) )) )) ) ) ) 3l ) ) ) I) )Illl ) )1) I J3 )) )) ) ) )) ) I) )] ] )) II) ] ) ) ) ) ) ) 1)) 4U44uuU4u44u44U44u4u4UUUU4U4444UU444UU4UUIU444u41U444~~44 ~ ! ~ SS5SSSI ~ I S ~ 5SIS SS5SSSSS5S ~ SSS S55 5ISS 5 5SS ~ SSSS5SSSSSSSSS s' SSSIS 5SS5S5SIS IS) SSSS 76-78 666666 &6 6 6 &66661666666166666666666666666666666 &6661666666666 6 ~ &&6 666666666666666 II" II I T I I I I I ,," 88 8 8 8818 8 8 88 88 88 88 8 8 88 8 8 88888888888 8888 8 8 8 8 8 8888888888888 8 ~ 99 H H 919 ' ...... II I •• g.~ ea68 GH& U 9 9 ql9 9199 9 9 919 9 99999999999999999199 J 9 919 9 9 gq 9 9999 ),. 79-80 I 111 I 1 III I 1111 I I I I I I 11 I 111 I 1 I I 11 T 111111111 I 1 I 11111' I' 11111111 j 1 I 'I 'l '. J • ,.,.:.:: .LO' :\:.:' ••••, 1Q)1 .'.l ~"'l J: 'J'. J\" J~ J:I)1 ,,, •• ,:.,.: l .••• ' " , • • . ' \: ~'J' .1", ,•• ' ,f •• • 8881118 8 adB P r, q 913 9 9 q 9 n 9 q ~ . .. ~. fl'!' .. •• • '. qq q • b. fQr_a 1024 wQrd X 8-bit organization only, cards 2 and the following cards should be punched as shown. MSB (OUTPUT 8l DECIMAL WORD ADDRESS BEGINNING LSB (OUTPUT 1) ~ DECIMAL NUMBER INDICATING THE 8 DATA F.IELDS EACH CARD Column Data' 1-5 Punch the 5-digit decimal equivalent of the binary coded location which begins each card. The address is right justified, Le., 00000, 00008, 00016, etc. Blank Data Field Blank Data Field Blank Data Field Blank Data Field Blank Data Field Blank Data Field Blank Data Field Blank Punch same 2-digit decimal number as in title card. 6 7-14 15 16-23 TRUTH TABLE NUMBER r - - - - - - + - - t - - - . L . - - - - - - _ rJ, ;33 34-41 11111111 1I11II1I 1111I1I1 11111111 11111111 11111111 11111111 11111111 42 1111100000000000000000000000000 U0 000000000000000000000000000000000000000000 u 0011 • 11' I I " ",' " '·\'I·:III'~:·:.:.: •. I:\:::tI~10111lIJ.. nlll:III"'U'/fI""''':lIh':III:II~III6I'I.lt"'II;lhHIIU·I'I'·; ,·.·j·.·I·.·· ",n 22222 1111111 2121222212212 , 11 2111 22 22222222 222222 ? Z212222211 2'12 22 ~ 222 222; 222 i ? ~ ; 2 43-50 51 3] J J ] )) J ) ) 1 ) ) ) ) J JJ ) ) ) ) ] ] ] JJ 52-59 1I1111I1I1I1111111111111111I111111111111I111111111111111111I1111111111111111111I U 4 C.: u. U U:4 4 .. H 4. 4 c:: ~~ S ~ ~ S~ I S11111 ~ S sSSIII ~ J j ) ) ] J) ~. t J ))) ) ] ) ] ) J J J lJ J lJ ) ] 13 J J )) )) J ) ] J J JJ t.:.· 14 C.:: 4 44 ~ J] 13J 1) 1) J J J 4 H 4 4 4: 4 H 4 4: 4 U H: 4 H: ~ 4 ~: ~:::: 60 61-68 69 4 ~:: s) S1111. ) ;. i j II i ) Iss sill; i ; ) 1111I i iSS II) sIII ~ i ) II ~ ; II) ) ) ) H b E~ bt 0 6 Ii 6& 6 0 t 666 t ~ b0 ~ ~ 0 ~ 6 60 6 ~ 0 ii£ i: DO 0 0 ~ ~ c ~ ~ : ~ 0 t bEt 0 ~ 0 ~ ; I; II: ~ 1: II; 111111111111//11111111 i 11111111: i 11/1; ...... ; I: I H H H H H 66 6 6b 6 66 6 & 6 Et ( i 1111111: 11: : : : : 1111;': 70-77 78 79-80 868S8868Pfltg86G8888a888aci8888886~888888688666886&e8~~~Eae~li:~:i~o:~i,'~~:ii~i=: •q Q q H 9h ~"O;" I :.,. ~ ~ ~ " 9 qg • 9 q 0; ~ ~ It" ;. • go C q q H 99 9 q 9 9 n 9 Q 5 ~ .; ; '...• , • ; • , , .' . . , .••• I ~ : I ~ : f 2. Paper Tape Format 1" wide paper tape using 7- or 8-bit ASCII code, such as a model 33 ASR teletype produces, or the 11/16" wide paper tape using a 5-bit Baudot code, such as a Telex produces. The format requi rements are as follows: a. All word fields are to be punched in consecutive order, starting with word field 0 (all addresses low). There mu~t be exactly 1024 word fields for the 1024 X 8 ROM organization. b. Each word field must begin with the start character B and end with the stop character F. There must be exactly 8 data characters between the B and F. Start Character ~ , Leader: Rubout Key for TWX and Letter Key for Telex (at least 25 frames). c,.. . NO OTHER CHARACTERS, SUCH AS RUBOUTS, ARE ALLOWED ANYWHERE IN A WORD FIELD. If in preparing a tape an error i~ made, the entire word field, including the Band F, must be rubbed out. Within the word field, a P results in a high level output and an N results in a low level output. c. Preceding the first word field and following the last word field, there must be a leader/trailer length of at least 25 characters. This should consist of rubout or null punches (letter key for Telex tapes). d. Between word fields, comments not containing B's or F's may be inserted. Carriage return and line feed characters should be inserted as a "comment") Stop Character I , I Data Punch·a T Blank Customer Company Name Blank Customer's Company Division or location Blank Customer Part Number Blank Punch the Intel 4-digit basic part number and in ( ) the number of output bits, e.g., ·8308(8). Blank' . Punch a 2-digit decimal number to identify the truth table number (mask programmed ch ip select number). Data Field just before each word field (or at least between every four word fields). When these carriage returns, etc., are inserted, the tape may be easily listed on the teletype for purposes of error checking. The customer may also find it helpful to insert the word number (as a comment) at least every four word fields. e. Incl uded in the tape before the leader should be the customer's complete Telex or TWX number and, if more than one pattern is being transmitted, the ROM pattern number. f. MSB and LSB are the most and least significant bit of the device outputs. Refer to the data sheet for the pi n numbers. MSB I LSB , + BPPPNNNNN FBNNNNNNPP F BNPNPPPNNF ' I I i ' I Word'Field 0 I WordiField 1 5-60 Word Field 1023 Trailer: Ruboul Key for TWX and Leuer Key for Telex (al leasl 25 frames), intel® Silicon Gate MOS ROM 8316A 16,384 BIT STATIC MOS READ ONLY MEMORY Organization-2048 Words x 8 Bits Access Time-SSO ns max -- • Single + 5 Volts Power Supply Voltage • Directly TTL Compatible - All Inputs and Outputs • Low Power Dissipation of 31.4 /LW/Bit Maximum • Three Programmable Chip Select Inputs for Easy Memory Expansion . • Three-State Output Capability • Fully Decoded Decode OR-Tie On Chip Address • Inputs Protected - All Inputs Have Protection Against Static Charge ® The Intel 8316A is a 16,384-bit static MOS read only memory organized as 2048 words by 8 bits. This ROM is designed for microcomputer memory applications where high performance, large bit storage, and simple interfacing are important design objectives. The inputs and outputs are fully TTL compatible. This device operates with a single +5V power supply. The three chip select inputs are programmable. Any combination of active high or low level chip select inputs can be defined and the desired chip select code is fixed during the masking process. These three programmable chip select inputs, as well as OR-tie compatibility on the outputs, facilitate easy memory expansion. The 8316A read only memory is fabricated with N-channel silicon gate technology. This technology provides the designer with high performance, easy-to-use MOS circuits. Only a single +5V power supply is needed and all devices are directly TTL compatible. PIN CONFIGURATION BLOCK DIAGRAM 0, 02 03 04 as 06 07 Os A,o Ag As (/) A7 A6 a: CHIP SELECT PROG. w I.L I.L :J CD ~ :J As 0... A4 (/) (/) ~ w a: A3 0 0 « A2 A1 A CHIP SELECT "'--CS 2 INPUT BUFFERS "-cs3 o PIN NAMES AO· A,o 01. 0 8 CS1· CS3 """-CS, 16,384 BIT CELL MATRIX ADDRESS INPUTS OATA OUTPUTS PROGRAMMABLE CHIP SELECT INPUTS 5-61 SI~ICON GATE MOS ROM 8316A ABSOLUTE MAXIMUM RATINGS· Ambient Temperature Under Bias O°C to 70°C -65°C to +150°C Storage Temperature Voltage On Any Pin With Respect To Ground. . . . . . . . . . . . . . . . . . . . .. -0.5V to +7V Power Dissipation ~ . . 1.0 Watt *COMMENT: Stresses above those Iisted under"Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. D.C. AND OPERATING CHARACTERISTICS. T A = O°C to +70°C, Vee = 5V ±5% unless otherwise specified LIMITS SYMBOL PARAMETER MIN. TYP.(1) TEST CONDITIONS UNIT MAX. = 0 to 5.25V ILl Input Load Current (All Input Pins) 10 IlA VIN ILOH Output Leakage Current 10 IlA ILOL Output Leakage Current -20 IlA = 2.2V, CS = 2.2V, ICC Power Supply Current 98 mA All inputs 5.25V Data Out Open VIL Input" Low" Voltage -0.5 '0.8 V VIH Input "High" Voltage 2.0 VCC+ 1.OV V VOL Output" Low" Voltage 0.45 V VOH Output "H igh" Voltage 40 CS = 2.0 mA I 0 H = -1 00 ,uA IOl V 2.2 = 4.0V VOUT = 0.45V VOUT (1) Typical values for T A = 25°e and nominal supply voltage. A.C. CHARACTERISTICS TA = O°C to +70°C, Vee = +5V ±5% unless otherwise specified LIMITS PARAMETER SYMBOL MIN. Address to Output Delay Time teo Chip Select to Output Enable Delay Time tOF Chip Deselect to Output Data Float Delay Time Output Load ... 1 TTL Gate, and CLOAD = 100 pF Input Pulse Levels . . . . . . . . . . . . . . . 0.8 to 2.0V Input Pulse Rise and Fall Times. (10% to 90%) 20 nS Timing Measurement Reference Level Input 1.5V Output 0.45V to 2.2V 0 CAPACITANCE(2) TA = 25°C, f = UNIT MAX. 400 tA CONDITIONS OF TEST FOR A.C. CHARACTERISTICS Typ.(1) 850 nS 300 nS 300 nS 1 MHz LIMITS SYMBOL TEST TYP. MAX. CIN 'All Pins Except Pin Under Test Tied to AC Ground 4 pF 10 pF COUT All Pins Except Pin Under Test Tied to AC Ground 8 pF 15 pF (2) This parameter is periodically sampled and is not 1000A» tested. 5-62 SILICON GATE MOS ROM 831.6A WAVEFORMS ADDRESS tOF PROGRAMMABLE CHIP SELECTS OU~TVALID 5-63 1111. S.ILICO.N GATE MOS ROM 8316A TYPICAL D.C. CHARACTERISTICS ACCESS TIME VS. AMBIENT TEMPERATURE V,N LIMITS VS. TEMPERATURE 900 . - - - - - - , . . - - - , - - - - - - . - - - - - - - . 800 1.8 r----,r----r--.,r---r---.,r---r--_ r----;----t----:::::;~--t---__I TYPICAL 1.6 t - - - - 1 t - - - - - t - - - - 1 t - - - t - - - I - - - - f - - - - - - f 600 ....-~--+----t-----+---~ en t-l ~ 1.4 t - - - t - - - - - - t - - t - - - t - - - t - - - t - - - - f z -> 400 r-----:=--...-==----t------t------I 1.2 200 t - - - - - t - - - . : . . - + - - - - - + - - - - - - t t---t---l--t---t--------"t---t-------4 VCC:;;: 5.0V 1.0 20 60 1ooo.---'1-----1_---'I--_"--_"--_.&...._--1 o 80 OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE 60 70 -30 -25 25 ./ 20 / 15 -l 9 / 10 v V ~ I-- -20 TYPICAL <' E V -15 ~ 9 -10 jV TA = 25°C VCCMIN I \ \ ~ \ TYPICAL ~\ TA = 25°C I\..VCC MIN -5 / o 1000 50 OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE 30 <' E 20 10 ~ ~ 3 VOL (VOLTS) VOH (VOLTS) ACCESS T"ME VS. LOAD CAPACITANCE STATIC 'CC VS. AMBIENT TEMPERATURE WORST CASE ---....--~--...,.--~~-......, 100 - - - - - - -.........~---------. WORST CASE 800 I - - - - - + - - - - + - - - - t - - - - t - - - - - t 80 I-----+---~!-----+------I 600 I - - - - - - + - - - - - + - - - - + - - - - + - - - - - t TYPICAL 4OO1-----fl-=:;;.----+----t----t-----t 6Oi------+----t-----t-------t 200 I - - - - - + - - - - I - - - - - - t - - - - t - - - - - t o 100 200 300 400 O~-------I--------20 60 80 500 CLOAO (pfd) 5-64 MCS™ CUSTOM ROM ORDER FORM 8316A ROM CUSTOMER,-----------------P.O. NUMBER ----.;. _ OATE _ For Intel use only S# ----:. STO _ pppp-------- zz, _ 00 APp _ _ OATE _ All custom 8316A ROM orders must be submitted on this form. Programming information should be sent in the form of computer punched cards or punched paper tape per the formats designated on this order form. Additional forms are available from Intel. MARKING INTEL PATTERN NUMBER The marking as shown at the right must contain the Intel@logo, the product type (P8316A), the 4-digit I ntel pattern number (PPPP), a date code (XXXX), and the 2-digit chip number (DD). An optional customer identification number may be substituted for the chip number (ZZ). Optional Customer Number (maximum 9 characters or spaces). CUSTOMER"NUMBER • I _ 8316A xxxx DATE. CODE zz .CHI"P"NUMBER OR CUSTOMER NUMBER MASK OPTION SPECI FICATIONS A. CHIP NUMBER (Must be specified-any number from 0 through 7-00). The chip number will be coded in terms of positive logic where a logic 1" is a high level input. II Chip Number o 1 2 3 4 5 CS3 CS2 CS1 0 0 0 0 1 a a a 1 0 1 1 100 101 1 a 6 1. 7 111 B. ROM Truth Table Format Programming information should be sent in the form of computer punched cards or punched paper tape. Ineither case, a printout of the truth table should be accompanied with the order. The following general format is applicable to the programming information sent to Intel: • Data fields·should be ordered beginning with the least significant address (0000) and ending with the most significant address (2047). • A data field should start with the most significant bit and end with the least significant bit. 5-65 • The data field should consist of P's and N's. A P is to indicate a high level output (most positive) and an N a low level output (most negative). I n terms of positive logic, a"P is defined .as a logic 111" and an N is defined as a logic 110". If the programming information is sent on a punched paper tape, the~ a start character, B, and an end character, F, must be used in the data field. 1. Punched Card Format An SO-column Hollerith card (preferably interpreted) punched by an J8M 026 or 029 keypunch should be submitted. The first card will be a title card; the format is as follows: a. Title Card 4 or 8 DESIGNATION 1 1I NO. OF OUTPUTS TITLE CARD CUSTOMER'S INTEL PIN DIVISION OR LOCATION CUSTOMER'S PIN ,----....1..-------,,1 r--L-, ~ CUSTOMER'S I COM~ANY NAME I ' DECIMAL NUMBER INDICATING THE TRUTH TABLE NUMBER r--;,~·'I·~l.~I:.~·LL[!":':_~.~·r"!:-,""·~.;~'~l~r.·)~·~CO~~R~P--:.--!;:'~,"~:i':!":,ri~~~l;L""':'t4":":"ll.~. "':'C~:\L""':!I~.~....:-~l2~J~4:;.\-.l-...:.:.(h~~·.~~{J~O I II II III I I I III • I I I I II II I I I I I Column Data 1 2-5 6-30 31-34 35-54 Punch aT Blank Customer Company Name Blank Customer's Company Division or location Blank Customer Part Number Blank Punch the Intel 4-digit basic part number and in ( ) the number of output bits, e.g., 8316A(8). Blank Punch a 2-digit decimal number to identify the truth table number (mask programmed ch ip select number). 55-57 58-66 ~ ~ ~ ~ ~!~! ~,~ I~ I~ ,~! ,~ ~ ~ ~ ~!~ ~~~~~~~~~~ ~ ~~!~~I~~~ ~~,~~~~~~~~ e~~~~e~~~~~~I~I~~~~~,!~ ~,~,~~\~~'~~! Itlllllll!II!!!!!!II!IIIIIII!!llllllllllllllllllllllll11111111111111111111111\!1 2222222222222222222122222'222222222122222222222222222 22222221222222222'22222222227 67 1111)) 11 311111111111 3111 311111 313313313311333313133333333333 I 333333 II 33331333333 68-75 4 U 444 U4 4 4 4 44 4 4 4 4 4 4 4 4 44 4'" 44 4 4 4 4 ~ U U 4 4 4 4 44 4 4 4 4 4 4 4 4 4 4 ~ 4 44 44 4414 4444 4 4414 4 444 444 4 SS SS SS S SS~ SI SS SSI SSSS SS SS ~ SSS SSS55 SSI S5 5 SS SS SS5 S5555 S5 SS5 S5 S551 S5 SSS 5 5S151 SS5555 76-78 79-80 .66666666666666616666661666666666666& 6 6& 6 &&6& 6 6& &6&16 66&6 6& 666L666666 6666666 666 66 ," , 11111'11'" 111 1 r 11 11111'" 1 III 11111 11111 11111 11111 11111,," 11 U 111" 111" 1" 8883881888888888888888888888888888888888888888888888888 8 88 8 e8888 8 8 8 8 8881118 8888 @ 999 9 ~ 99199 ~ 999199199 99 91 99 999999999999999991993991 9 99 99 9 9 999 ~ ~ ~ 9 99 99 9 99 9 ~ 9 9 q 999 q ': II" '" .0"': . '''''I''·I'':t:'I:''/lr.l.;'"alOlll1I1!11\.1I1111101l1:'IUhIP·'''~·,,1\;'/10':." .. ··, ... ··,:·:·:· '''I~'1 ,,,,.,.0':":;'.', " ··t·· .• b. For a 2048 word X 8-bit organization only, cards 2' and the following cards should be punched as shown. DECIMAL WORD ~~~:~~R~EGINNING MSB (OUTPUT 8) I ,L, I LSB DECIMAL NUMBER I08U::~: ~IELDS I· . 7-14 15 rl, I 16-23 33 34-41 42 43-50 I,Ili'" I1I11I11 11111111 11111111 11111111 11111111 11111111 IlIlIill 11111111 1111100000000000000000000000000000000000000000000000 0000000000000 0000 0000000 0 011 I ~ :; i;;;i'i 'i'[ 'I"; 'I' 'I '; '; 'I'~:I~: ',;1:,17:; ~~ ~ I I iii ~ i l; ~ ~~;II"tl;l·tlr-r';';'~l ¥;l~'t~I[~'II~'i;at"j'II~i:lt",'~::,~: ~'~. ~l j"11 :\' :Il~ 51 222 212 21211 n 2212222222222222122 ZZ222 222 222 222222222222222 22 222 222222 2222 Z 22222 Z 52-59 60 61-68 333JJ33333131333333J3333331JJJJlJ3J33333333333333333'33333333333333JJ333JJJ333JJJ ~ ~ ~,u l •• ss 5 ~ 55I ~ 11111 ~ ~ 5551115 5 i S1111 C, ( I ••• ~ ~ 444444444 4 ~ 444444444444.4 44 ~ 4: 4 H 4444 ~ ~. j II S) 15 5S1115 :. :. :. 11111 :. ,i 5SII s SIII 5 ~ 5115 511 5) S5 )):.) 69 70-77 78 79-80 ,H 6 &t ~ 66' £& 666 66 66 6 66 Et t b i: b ~ lib ~ 11 61i 6ii 6 ii £6 &6 6 £ L0 ~ ~ ii ii 6 6 ii 6 C6 ii Eii ii ii ii 0 ~ 0 ii t ii 50 0 i: &E E0 L6 ii , " 111III 1; : : ? i I111 i :; I; III : 1111/111111111 II 1111111 / 111/111111111 / /111 ; ill; 11; : 1 868888888 PEt 8888888888888 Ii 88 8 8 8 8 &a8 8 8 8 8 8 8 8 8 &8 8 8 8 &&e8 8 ~ aEaa~ 8 58 &38 8 ~ 6 Eet 5 6 0 tee i 1. ! "" ~ 9 ~ ~ ~ ~ s ~ q ~ ~ .q. ~ ~ ~ ~ ) ~ .~ 9 ~ ~. ~.~ .~ ~ ~ 9 Q 0 ~ ~ ~ ~ ~ ~ 9, ~ ~ ~ ~, ~. ~ ~ ~ ~. ~ ~.i ~ , 1 ~ 2. Paper Tape Format 1" wide paper tape using 7- or 8-bit ASCII code, such· as a model 33 ASR teletype produces, or the 11/16" wide paper tape usi ng a 5-bit Baudot code, such as a Telex prod uces. The format requirements are 'as follows: a. All word fields are to be punched in consecutive order, starting with word field 0 (all addresses low). There must be exactly 2048 word fields for the 2048 X 8 ROM organization. b. Each word field must begin with the start character B and end with the stop character F. There must be exactly 8 data characters between the B and F. Start Character ~_ , Leader: Rubout Key for TWX and Letter Key for Telex (at least 25 frames). t t : .; .: •• ; 1 '1 '~ .1 .: ~ ~ . , .~ ••• Punch the 5-digit decimal equivalent of the binary coded location which begins each card. The address is right justified, Le., 00000, 00008, 00016, etc. Blank Data Field Blank Data Field Blank Data Field Blank Data Field Blank Data Field Blank Data Field Blank Data Field Blank Punch same 2-digit decimal number as in title card. 6 ~~~;~~I:;L~~EUMBER .':.":;.'!.' F'f1J-'rthr1rdt F'f'F'F'WthF' F'F'ftrtrtftH' f'f'F'rtttf'F'f1 F'Htf·ttff·f-'f-' t1Ufcttl'tF'F'f-' f1f1F'f-'t1tHif' f-'ttr'1f-'f'Wtf-' U 44 U U U 4 U 4 U U 44 4 44 Data Column 1-5 c.- '~ ~ ".~ ~ NO OTHER CHARACTERS, SUCH AS RUBOUTS, ARE ALLOWED ANYWHERE IN A WORD FIELD. If in prepari ng a tape an error is made, the entire word field, including the Band F, must be rubbed out. Within the word field, a P results in a high level output and an N results in a low level output. c. Preceding the first word field and following the last word field, there must be a leader/trai ler length of at just before each word field (or at least between every four word fields). When these carriage returns, etc., are inserted, the tape may be easily listed on the teletype for purposes of error checking. The customer may also find it helpful to insert the word number (as a comment) at least every four word fields. least 25 characters. This should consist of rubout or null punches -(Jetter key for Telex tapes). e. Included in the tape before the leader should be the customer's complete Telex or TWX number and, if more than one pattern is being transmitted, the ROM pattern number. d. Between word fields, comments not containing B's or F's may be inserted. Carriage return and line feed characters should be inserted as a "comment") f. MSB and LSB are the most and least significant bit of the device outputs. Refer to the data sheet for the pin numbers. Stap Character --1 , I Data Field I BPPPN NNNN FBNNNNNNPP F I 1 Ward'Field 0 L..' ---r- WardlField 1 5-66 ----J MSB LSB t t BNPNPPPNNF I Word F i~'d 2048 Trailer: Rubaut Key far TWX and Let~~r Key for Telex {at least .25 framesL RAMs 8101-2 8111-2 8102-2 8102A-4 81078-4 5101 8210 8222 Silicon Gate MOS 8101-2 1024 BIT (256 x 4) STATIC MOS RAM WITH SEPARATE 1/0 • 256 x 4 Organization to Meet Needs for Small System Memories • Access Time - 850 nsec Max. • Single + 5V Supply Voltage • Directly TTL Compatible - All Inputs and Output • Static MOS - No Clocks or Refreshing Required • Simple Memory Expansion - Chip Enable Input • Inputs Protected - All Inputs Have Protection Against Static Charge • Low Cost Packaging - 22 Pin Plastic Dual-In-Line Configuration • Low Power - Typically 150 mW • Three-State Output Capability OR-Tie • Output Disable Provided for Ease of Use in Common Data Bus Systems ® The Intel 8101-2 is a 256 word by 4 bit static random access memory element using normally off N-channel MOS devices integrated on a monolithic array. It uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to operate. The data is read out nondestructively and has the same polarity as the input data. The 8101-2 is designed for memory applications where high performance, low cost, large bit storage, and simple interfacing are important design objectives. It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. Two chip-enables allow easy selection of an individual package when outputs are OR-tied. An output disable is provided so that data inputs and outputs can be tied for common I/O systems. Output disable is then used to eliminate any bidirectional logic. ® The Intel 8101-2 is fabricated with N-channel silicon gate technology. This technology allows the design and_ production of high performance, easy-to-use MOS circuits and provides a higher functional density on a monolithic chip than either conventional MOS technology or P-channel silicon gate technology. Intel's silicon gate technology also provides excellent protection against contamination. This permits the use of low cost silicone packaging. LOGIC SYMBOL PIN CONFIGURATION A3 22 Vee Ao 01, A2 21 A4 A, DO, A, 20 RIW A2 01 2 CEl A3 A4 00 2 Ao 4 As 5 A6 6 19 18 00 17 CE2 16 0°4 8 15 01 4 01, 9 14 0°3 DO, 10 13 01 3 01 2 11 12 0°2 A7 @ AO ---0 ROW SELECT 01 3 As 003 A 8101-2 01 4 6 A7 0°4 8101-2 GNo BLOCK DIAGRAM CELL ARRAY 32 ROWS 32 COLUMNS Vee ~GND R/W 00 RIW CE2 CEl m~-.~ PIN NAMES CE2~---I DIN DATA INPUT 00 OUTPUT DISABLE Ao-A., ADDRESS INPUTS DOUT DATA OUTPUT RIW READIWRITE INPUT Vee POWER (+5V) m,CE2 CHIP ENABLE- 00 5-67 ::>--4 > o - ~ o= PIN NUMBERS SILICON GATE MOS 8101-2 Absolute Maximum Ratings* *COMMENT: Stresses above those listed under ''Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Ambient Temperature Under Bias. . . . .. O°C to 70° C 0 0 Storage T emperatu re .. . . . . . . . . . -65 C to + 150 C Voltage On Any Pin With Respect to Ground. . . . . . . .. Power Dissipation -0.5V to +7V . . . . . . . . . . . .. 1 Watt D.C. and Operating TA = o°c to 70°C, Vee = 5V Charact~ristics ±5% unless otherwise specified. Typ.[1] Max. Unit 10 pA V,N 110 Leakage Current[2] 15 pA CE = 2.2V, VO UT = 4.0V ILO L 1/0 Leakage Current[2] -50 J1A CE lecl Power Supply Current 60 rnA V,N = 5.25V, 10 = OmA TA = 25°C 70 mA VIN = 5.25V. 10 = OmA Min. Parameter Symbol Input Current ILl I LOH - 30 ~I~~;--l-p~~-;s~;~~c~;~;~~ --1~~:~;-_: I VOL = 0 to 5.25V = 2.2V, VOUT TA = O°C _ +0.45 VIOL - V____ 10H = 2.0mA = -150 p.A 1. Typical values are for T A = 25() e and nominal supply voltage. 2. Input and Output tied together. OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE : ~ ~ -10 .. _.- AMBIENT TEMPERATURE ~O"l: l- ---l-----.-i-.-t-.-.-- : -f I ! ! I I t' : r.'I I ~l~t-+-- ---T~-I! I .-+----+----. I ! 25 C , _0 I ~. --,- - I -_.V u 4.75V OUTPUT "HI(iH" TYPICAL t.---"-'-~---+------""!I--t--o +---;- L-.-----'-_.....L.-----lo....-~_"O"- I = 0.45V ~_!~~~-~~~-==--------~ Output "Low" Voltage ~E~~:=~utP~-t-·7~igh-~;\/oltage-~------ ---- --i2-+---=~== ~= NOTE: Test Conditions _ 1 VOL (VOLTS) VOH IVOL lS) 5-68 SILICON GATE MOS 8101-2 A.C. Characteristics READ CYCLE TA = o°c to 70°C, Vee ±5~/~, unless otherwise specified. = 5V =I~ tRey Read Cycle tA Access Time ----- Chip Enable To Output too Output Disable To Output tOF [1] Data Output to High Z State - - _ . _ - _ .. _---._-----. -'----- -- Max. Test Conditions Unit ~--_._--- ns .- --.-- r _ _ _ _ ._.__u. ___________ teo I Previous Data Read Valid tOH Typ. Min. Parameter Symbol after change of Address ---_._----0 850 ns ~ - - -~ . _ - - - - ~ . _ - - - 6~._~~ 550 ns 200~--~~-1 ~- -- 0 (See below) i ns WRITE CYCLE Parameter Symbol I Min. i, 850 ns 150 ns tweY Write Cycle tAW Write Delay tew Chip Enable To Write tDW Data Setup tOH Data Hold twp Write Pulse ! 630 tWR Write Recovery : 50 Typ. Max. -T 750 -1 Test Conditions Unit ns 500 ns 100 ns (See below) ---_..._ - - - - - - j - - - - - - - - t - - - - - - - , . . . - - ' , i ns Capacitance A. C. CONDITIONS OF TEST ns I _---L- T A = 25°C, f = 1 MHz - Input Pulse Levels: +0.65 Volt to 2.2 Volt Symbol Input Pulse Rise and Fall Times: ! Typ. 20nsec Timing Measurement Reference Level: 1 TTL Gate and CL Output Load: Limits (pF) Test 1.5 Volt ~.: 100pF Max. CIN Input Capacitance (All Input Pins) V IN = OV 4 8 CoUT Output Capacitance V OUT = OV 8 12 ~- Waveforms WRITE CYCLE l2] READ CYCLE ADDRESS CE2 - 00 (COMMON lID) 131 I -....Il- CE2 ...... t co - - . ' \ '00 ~. I '-- tA -1--- - - - - -y OUT _ _ j ..A DATA - ==:>c / -----" ODJ /'OH -..J • t OF 11; .' • IJATAOUT V_A_L_ID DATA IN _ .-. RW =x tDf' j. - .--., t OH / . - · - - ~_~_~:_L_I~ tow -J . --- tAW ; . . . . . - - '\ ~p . NOTES: 1. tDF is with respect to the trailing edge of CE1, CE2, or OD, whichever occurs first. 2. During the write cycle, 00 is a logical 1 for common 1/0 and "don't care" for sepJ~ate I/O operation. 3. 00 should be tied low for separate I/O operation. 5-69 t -_.__...:, tw ~ R ! I Silicon Gate MOS 8111-2 1024 BIT (256 x 4) STATIC MOS RAM WITH COMMON I/O AND OUTPUT DISABLE • • • • • Organization 256 Words by 4 Bits Access Time - 850 nsec Max. Common Data Input and Output Single + 5V Supply Voltage Directly TTL Compatible - All Inputs and Output • Static MOS - No Clocks or Refreshing Required • Simple Memory Expansion - Chip Enable Input • Fully Decoded Decode On Chip Address • Inputs Protected - All Inputs Have Protection Against Static Charge • Low Cost Packaging -18 Pin Plastic Dual-In-Line Configuration • Low Power - Typically 150 mW • Three-State Output Capability OR-Tie The Intel®8111-2 is a 256 word by 4 bit static random access memory element using normally off N-channel MOS devices integrated on a monolithic array. It uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to operate. The data is read out nondestructively and has the same polarity as the input data. Common input/output pins are provided. The 8111-2 is designed for memory applications in small systems where high performance, low cost, large bit storage, and simple interfacing are important design objectives. It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. Separate chip enable (CEl leads allow easy selection of an individual package when outputs are OR-tied. The Intel®8111-2 is fabricated with N-channel silicon gate technology. This technology allows the design and production of high performance, easy-to-use MOS circuits and provides a higher functional density on a monolithic chip than either conventional MOS technology or P-channel silicon gate technology. Intel's silicon gate technology also provides excellent protection against contamination. This permits the use of low cost silicone packaging. PIN CONFIGURATION LOGIC SYMBOL A3 18 Vee AO A2 17 A4 A, I/O, Az I/O z 16 A, R/W @ 15 tEl A3 1/0 3 14 1/04 A4 1/04 13 1/03 As A7 12 1/02 GNO 11 I/O, 10 CE2 Ao 4 As 5 A6 6 00 8111-2 9 BLOCK DIAGRAM -------0 ROW SELECT MEMORY ARRAY 32 ROWS 32 COLUMNS 8111-2 PIN NAMES AO-A7 00 ADDRESS INPUTS OUTPUT DISABLE RIW READIWR ITE INPUT CE, CHIP ENABLE 1 CE2 CHIP ENABLE 2 1/0,- 1/04 DATA INPUT/OUTPUT o' 5-71 Vee ~GNO PIN NUMBERS SILICON GATE MOS 8111-2 Absolute Maximum Ratings* *COMMENT: Stresses above those listed under ''Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Ambient Temperature Under Bias. . . . .. O°C to 70°C -65°C to +150°C Storage Temperature Voltage On Any Pin With Respect to Ground . . . . . . . .. -0.5V to +7V Power Dissipation 1 Watt D.C. and Operating Characteristics TA = O°C to 70°C, VCC = 5V ±5% Symbol , unless otherwise specified. Parameter Min. Typ.r 1 ] Max. Unit 10 J.1A J.1A Input Load Current III I/O Leakage Current 15 -50 J1A 60 mA 70 mA IlOl ICC1 Power Supply Current ICC2 Power Supply Current VIL Input Low Voltage -0.5 +0.65 V VIH Input High Voltage 2.2 V Val Output Low Voltage Vcc 0.45 VOH Output High Voltage NOTES: 30 2.2 = 0 to 5.25V CE = 2.2V, VI/O = 4.0V CE = 2.2V, VI/a = 0.45V VIN = 5.25V 11/0 = OmA, TA = 25°C VIN = 5.25V 11/0 = OmA, TA = O°C VIN IlO H I/O Leakage Current Test Conditions V 10l V 10H = 2.0mA = -150 J.1A 1. Typical values are for T A = 25° C and nominal supply voltage. OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE AMBIENT TEMPERATURE -15 ~~-==--~O°C -t----+---I----+--; 25°C 70°C i 15 ..--+---+--+-~~--+-------t i -10 ~----4-..-+---+--t----t--+----1 ! 10 ~--4---+--'~-~-+--+------4 ! ~ ..J o .2 .-.----+--~- -5 o L----L-_..L-.-..L.---.;;;~__.._. _ _. - . 0.5 1 1.0 VOL (VOLTS) V OH (VOLTS) 5-72 1.5 SILICON GATE MOS 8111-2 A.C. Characteristics READ CYCLE TA = o°c to 70°C, Vee = 5V ±5%, unless otherwise specified. Symbol Parameter tRCY tA tco too tOF [1] Read Cycle Access Time Chip Enable To Output Output Disable To Output Data Output to High Z State tOH Previous Data Read Valid after change of Add ress Typ. Min. Max. Unit Test Conditions ns ns ns ns ns (See below) 850 850 650 550 200 0 ns 0 WRITE CYCLE Symbol Parameter twCY tAW tcw tow tOH twP tWR Timing Measurement Reference Level: Output Load: Unit 500 100 630 50 Capacitance 20nsec 1.5 Volt 1 TTL Gate and CL = 100pF Test Conditions ns ns ns ns ns ns ns 150 750 +0.65 Volt to 2.2 Volt Input Pulse Rise and Fall Times: Max. 850 A. C. CONDITIONS OF TEST Input Pulse Levels: Typ. Min. Write Cycle Write Delay Chip Enable To Write Data Setup Data Hold Write Pulse Write Recovery TA = 25°C, f Symbol CIN GoUT (See below) = 1 MHz Limits (pF) Test Typ. Max. 4 8 10 15 Input Capacitance (All Input Pins) VIN = OV Output Capacitance VOUT = OV Waveforms READ CYCLE WRITE CYCLE 1..-------tReY-----~ ----twey-----.. I ADDRESS CHIP ENABLES ADDRESS _ ........._""I..- - - t e w - - -..I .........- " " 1 " - - teo tCE1, CE2) CHIP ENABLES OUTPUT DISABLE OUTPUT DISABLE ~ ~ t OF I DATA I/O DATA OUT VALID DATA IN STABLE DATA I/O _---+ READ/ WRITE "'" f4---lwp ------..............- tWR~ 1~-tAW--.I""-----"I NOTE: 1. tOF is with respect to the trailing edge of eEl, CE2, or 00, whichever occurs first. 5-73 tOH ----.I....- - tow - - - . Silicon Gate MOS 8102-2 1024 BIT FULLY DECODED STATIC MOS RANDOM ACCESS MEMORY • Simple Memory Expansion Enable Input • Access Time - 850ns Max. • Single + 5 Volts Supply Voltage • Directly TTL Compatible - All Inputs and Output • Static MOS - No Clocks or Refreshing Required • Low Power - Typically 150 mW • Three-State Output - OR-Tie Capability • Fully Decoded Decode Chip On Chip Address • Inputs Protected - All Inputs Have Protection Against Static Charge • Low Cost Packaging -16 Pin Plastic Dual-In-Line Configuration The Intel@8102-2 is a 1024 word by one bit static random access memory element using normally off N-channel MOS devices integrated on a monolithic array. It uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to operate. The data is read out nondestructively and has the same polarity as the input data. The 8102-2 is designed for microcomputer memory applications where high performance, low cost, large bit storage, and simple interfacing are important design objectives. It is directly TTL compatible in all respects: inputs, output, and a single +5 volt supply. A separate chip enable (CE) lead allows easy selection of an individual package when outputs are OR-tied. The Intel®8102-2 is fabricated with N-channel silicon gate technology. This technology allows the design and production of high performance, easy-to-use MOS circuits and provides a higher functional density on a monolithic chip than either conventional MOS technology or P-channel silicon gate technology. Intel's silicon gate technology also provides excellent protection against contamrnation. This permits the use of low cost silicone packaging. LOGIC SYMBOL PIN CONFIGURATION A6 16 A7 BLOCK DIAGRAM Ao As 2 15 As RIW 3 14 Ag A, 4 13 CE A2 5 12 DATA OUT AJ 6 11 DATA IN A7 A4 7 10 Vee As Ag Ao 8 9 A, A2 AJ A4 As 8102-2 GND DIN CELL ARRAY 32 ROWS 32 COLUMNS 8102-2 A6 R/W DOUT CE R/W COLUMN I/O CIRCUITS DATA IN PIN NAMES DIN Ao- Ag RIW DATA INPUT CE ADDRESS INPUTS DOUT OATA OUTPUT POWER (+5V) Vee READIWRITE INPUT CHIP ENABLE 0= PIN NUMBERS 5-75 DATA OUT SILICON GATE MOS 8102-2 ABSOLUTE MAXIMUM RATINGS· *COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any oth~r condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Ambient Temperature Under Bias Storage Temperature Voltage On Any Pin With Respect To Ground -O.5V to +7V Power Dissipation . 1 Watt D.C. AND OPERATING CHARACTERISTICS = OOC TA to +70°C, Vee = 5V ±5% unless otherwise specified SYMBOL LIMITS PARAMETER -- TYP.(1) MIN. MAX. 10 , III INPUT LOAD CURRENT (ALL INPUT PINS) I LOH OUTPUT LEAKAGE CURRENT I lOL OUTPUT LEAKAGE CURRENT POWER SUPPLY CURRENT CC1 -- ~-- 30 I CC2 TEST CONDITIONS p.A VIN = 0 to 5.25V 10 IJA CE = 2.2V, VOUT = 4.0V -100 IJA CE = 2.2V, VOUT = O.45V ALL INPUTS = 5.25V DATA OUT OPEN TA = 25°C 60 ' i UNIT I, mA i I 70 POWER SUPPLY CURREN:=] mA ALL INPUTS = 5.25V DATA OUT OPEN TA = OOC I I i I V Vee i V +0.45 ! V 'Ol= 1.9mA I V 'OH= -100IJA Vil INPUT "LOW" VOLTAGE -0.5 +0.65 V1H INPUT "HIGH" VOLTAGE 2.2 OUTPUT "LOW" VOL-rAGE VOL VOH 2.2 OUTPUT "HIGH" VOLTAGE I ! I I Typical values are for T A = 25°C and nominal supply voltage. (1) TYPICAL D.C. CHARACTERISTICS POWER SUPPLY CURRENT VS. SUPPLY VOLTAGE POWER SUPPL V CURRENT VS. AMBIENT TEMPERATURE 80 I ~ 0 50 I ~4~! 60 ! w I I . V --+--T~'-- cc 70 , I I -'~--i---± Y: SPEC. '-"-- POINTS I = 525V _ I: 50 n I._ ,..- .. ~ _ t? 1- ~ . ·l - -,-+----+---1 +_.- I - -+-- --.~! I \ -_+____f I 30 <{ - - +- - AMBI~NT TEMPERAl URE ~ 25°C E i i i <{ w 40 4 - - 40 ___ o~. a: w > --.-i 20 - _ .. t « u 40 ..s ..s w « a: w > « 40 u ~ _u 30 20 10 V / o(-.(v~ ~ '............ "" 0 20 10 ' - -_ _ o 10 ~ _ _ 20 _ _ " _ " " 30 " ' O - ' _ 40 . . I o o . _ - 50 - I __ . . 60 3 70 4 5 Vee (VOLTS) AMBIENT TEMPERATURE (OC) 5-80 6 SILICON GATE MOS 8102A-4 A. C. Characteristics TA = O°C to 70°C, Vee = 5V ±5% unless otherwise specified Limits Parameter Symbol TypJ1 ] Min. Max. Unit READ CYCLE 450 ns tRC Read Cycle tA Access Time 450 ns tco Chip Enable to Output Time 230 ns tOHl Previous Read Data Valid with Respect to Address tOH2 WRITE CYCLE Previous Read Data Valid with Respect to Chip Enable 40 ns 0 ns ns ns twc Write Cycle tAW Address to Write Setup Time 450 20 twP Write Pulse Width 300 ns tWA Write Recovery Time 0 ns tow Data Setup Time 300 ns tOH Data Hold Time 0 ns tcw Chip Enable to Write Setup Time 300 ns NOTE: 1. Typical values are for TA = 25° C and nominal supply voltage. Capacitance l21 TA A. C. CONDITIONS OF TEST Input Pulse Levels: Output Load: LIMITS (pF) Typ.,[1] MAX. TEST SYMBOL 0.8 Volt to 2.0 Volt Input Rise and Fall Times: Timing Measurement Reference Levels = 25°C, f = 1 MHz INPUT CAPACITANCE (ALL INPUT PINS) V1N C 1N 10nsec Inputs: Output: 1.5 Volts 0.8 and 2.0 Volts C OUT 1 TTL Gate! and CL = 100 pF =: OUTPUT CAPACITANCE VOUT = OV NOTE: 2. This parameter is periodically sampled and is not 100% tested. Waveforms READ CYCLE WRITE CYCLE twe tRC ADDRESS CD teo CHIP ENABLE CHIP ENABLE tA DATA OUT 'ew twP READI WRITE CD ® fj) 1.5 VOLTS 2.0 VOLTS 0.8 VOLTS OV tow DATA IN 5-81 DATA CAN CHANGE DATA STABLE 3 5 7 10 SILICON GATE MOS 8102A-4 Typical D. C. and A. C. Characteristics POWER SUPPLY CURRENT VS. SUPPLY VOLTAGE POWER SUPPLY CURRENT VS. AMBIENT TEMPERATURE 45 35 I I 40 30 VeeMAX.- ct ............ 30 25 r---___ -.............. TYPICAL ~ ! - ........ /r / 10 o 10 20 30 40 50 60 5 70 I 1 T (OC) A Vee (VOLTS) OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE 30 -30 -25 -20 ct ! ~PICAL / 20 15 20 15 V ./ 25 35 i~ I TA "'25°C- f-- -15 " \ .. \ % ~ -10 25 20 TYPICAL TA ~ ;: 25°C Vee MIN. 10 '~ -5 V / j' 15 J ~ / TYPICAL = 25'C TA Vee MIN. I '""'" VOH (VOLTS) VOL (VOLTS) ACCESS TIME VS. Vee NORMALIZED TO Vee = 5.0V VIN LIMITS VS. TEMPERATURE 1.05 1.8 TA 1.6...----+--_+_- ~ .... ~ ,......,.....1- 1.00 1.4...----+--_+_-+--+----+--t----t Z >1.2 ...----+--_+_-+---+----+--t----t 0.95 "" .. .l 700C CYCLE TIME = 350ns ~ Vee" 5.0V 1.0 0 10 20 30 40 50 60 70 4.0 4.5 5.5 5.0 TA (OC) 6.0 Vee (VOLTS) ACCESS TIME VS. LOAD·CAPACITANCE ACCESS TIME VS. AMBIENT TEMPERATURE 350 ,...----,----,----r---r----'T"""'-....., TA " 25°C Vee MIN. 1 TTL LOAD Vee MIN. 1 TTL LOAD "100pF c;. 250 t - - - - - t - - - - - - i 250 t-----+--TY....... P-ICA-L-+----+----I:=........,~--1 -=T---+---+--~ TYPICAL c ..-:. 150 t - - - - - - I - - - - t - - + - - - t - - - - t - - - i 150 t-----+--+----+--+-----+--t----t OUTPUT REFERENCE LEVEL" , .5V OUTPUT REFERENCE LEVELS: VOH '" 2.0V VOL aO.8V 5O~---I._---I._---.l.---'-----""'" 5OL.-----J...._..L-----L._.....L----L_.........- - - ' o 10 20 30 40 50 60 o 70 100 200 300 C L (pF) TA (OC) 5-82 400 500 600 Silicon Gate MOS 81078·4 FULLY DECODED RANDOM ACCESS 4096 BIT DYNAMIC MEMORY * Access Time·· 270 ns max. * Read, Write Cycle Times--470 ns max. * Refresh Period -- 2 ms • Low Cost Per Bit • Low Standby Power • Easy System Interface • Only One High Voltage Input Signal- Chip Enable • TTL Compatible -- All Address, Data, Write Enable, Chip Select Inputs • Read-Modify-Write Cycle Time _. 590 ns • Address Registers Incorporated on the Chip • Simple Memory ExpansionChip Select Input Lead • Fully Decoded - On Chip Address Decode • Output is Three State and TTL Compatible • Industry Standard 22-Pin Configuration The Intel 81078 is a 4096 word by 1 bit dynamic n-channel MOS RAM. It was designed for memory applications where very low cost and large bit storage are important design objectives. The 81078 uses dynamic circuitry which reduces the standby power dissipation. Reading information from the memory is non-destructive. Refreshing is most easily accomplished by performing one read cycle on each of the 64 row addresses. Each row address must be refreshed every two milliseconds. The memory is refreshed whether Chip Select is a logic one or a logic zero. The 81078 is fabricated with n-channel silicon gate technology. This technology allows the design and production of high performance, easy to use MOS circuits and provides a higher functional density on a monolithic chip than other MOS technologies. The 81078 uses a single transistor cell to achieve high speed and low cost. It is a replacement for the 81078. PIN CONFIGURATION LOGIC SYMBOL 81078 Vee Vss Ag As A, A,o A] A2 A" ~ Vee CS A O 0----. Ao A, As A6 A] CE DouT NC Ao As A, A.1 A,o A2 A3 A" WE CS 0----. A2 DIN AJ AJ A4 o.N Vee BLOCK DIAGRAM 81078 0----. ROW DECODE and BUFFER REGISTER A4 ~ 64 MEMORY ARRAY 64 x 64 0----. f64 DOUT As Ag CE 0----. TIMING CONTROL GENERATOR COLUMN AMPLIFIERS CE WE 64 PIN NAMES DIN 0----. Ao-A" CE ADDRESS INPUTS* VBB POWER (-5V) WE 0----. CHIP ENABLE Vee POWER (+5V) CS CS CHIP SELECT DATA INPUT VOO Vss POWER (+12V) DIN DOUT DATA OUTPUT WE WRITE ENABLE NC NOT CONNECTED GROUND * Refresh Address A o -As' 5-83 0----. I/O .......0 "be ~ ~ Vee Vss .......0 "BB SILICON GATE MOS 81078·4 Absolute Maximum Ratings* ooc to 70°C Temperature Under Bias Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°C to +150 0 C All I nput or Output Voltages with Respect to the most Negative Supply Voltage, Vee . . . . . . . . . . . . . . . . .. +25V to -O.3V Supply Voltages Vee, Vcc, and Vss with Respect to Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. +20V to -O.3V Power Dissipation 1.25W *COMMENT: Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. D.C. and Operating Characteristics T A = 0° C to 70° C, Voo = + 12V ± 5%, Vcc = +5V ± 5%, Vss [1] = -5V ± 5%, Vss = OV, unless otherwise noted. Symbol Parameter Min. Limits Typ.[2] Max. Unit Conditions III Input Load Current (all inputs except CE) .01 10 JJA VIN = VIL MIN to V,H MAX Ilc Input Load Current .01 10 JJA V,N = V,L MIN Illol Output Leakage Current for high impedance state .01 10 JJA CE = VILC or CS = V,H Vo =OV to 5.25V to V,H MAX 1001 Voo Supply Current during CE off[3] 110 200 JJA CE = -1V to +.6V '002 Voo Supply Current during CE on 80 100 mA CE = V,HC, T A = 25°C 100 AV1 Average Vo o Current 55 80 mA IOOAV2 Average Voo Current 27 40 rnA Cycletime=470ns, } tCE = 300ns Cycle time =1000ns, tCE = 300ns ICC1 [4] Vec Supply Current during CE off .01 10 JJA Iss VeB Supply Cu rrent 5 100 JJA Vil Input Low Voltage -1.0 0.6 V VIH Input High Voltage 2.4 VCC+l V VllC CE Input Low Voltage -1.0 +1.0 V VIHC CE Input High Voltage Voo-l Voo+1 V Val Output Low Voltage 0.0 0.45 V Vec V VO H Output High Voltage 2.4 TA - CE = V'LC or CS = V,H tT= 20ns - See Figure 4 = 2.0mA 'OH = -2.0mA IOl NOTES: 1. The only requirement for the sequence 'of applying voltage to the device is that VOO, VCC, and VSS should never be .3V more negative than VSS. 2. Typical values are for TA = 25° C and nominal power supply voltages. 3. The I DO and ICC currents flow to VSS' The I Be current is the sum of all leakage currents. 4. During CE on VCC supply current is dependent on output loading, VCC is connected to output buffer only. 5-84 = 250C SILICON GATE MOS 81078·4 Read and Refresh Cycle [1) (Numbers in parentheses are for minimum cycle timing in ns) ~-------------- t Cy (470) ----------------------~ ADDRESS AND~ ADDRESS CAN CHANGE 0 \'IL 1 4 - - - - - - - - - - - tce (300) tAC(O)-.......-~ V,HC ----------~ ----+-----+-I..-oI!""!!-----------------------.. . CE \'JH - -...--~-+------------------------_t-;-.....,r_----.,...-- t cO (2S0) OoUT ..... VoL - - IMP~6~NCE V_A_L_ID_-_-_-:.::=~~~:~~~:~ 1-_....iI... -II.~----------------- t ACc (270) Write Cycle tCF(O) .1 - - - - - - t Cy (470) --- - - - - - - \'JH ® ® ADDRESS ANDCS \'JL t:(~ ~ - - - - - - - - - . 1.._----..-- ADDR ESS STAB LE ADDRESS CAN CHANGE : ------. -----..1 CD . . - - - - t AH (SO)-----. - t ce (300) _ . _ - - V1HC - - - - - - - - i - ._----_._--~ ~~~---------------------..... ® CE . . - - - - - tw ' 1 S 0 ) - - - - o V'LC - - - -.....-..11 1 4 - - - - - - - - t cw (1S0) V1H -----4-----~ ------~-----------~ WE CAN CHANGE V1L ------t--------------I--...----.... -----~~------_t_--- \'JH ------+----------~ DtN CAN CHANGE DIN \'JL ------t-----------~ 'bH------D OUT '-IMP~~~~CE-.~_....... VOL - - - - - --I11111111'.--- U_N_D_E_FI_N_E_D_ _...... -----~ _IM_P~_ri~~_CE_ _ ' --,.teF(O) NOTES: 1. 2. 3. 4. 5. 6. 7. For Refresh cycle row and column addresses must be stable before tAC and remain stable for entire tAH period. VIL MAX is the reference level for measuring timing of the addresses, CS, WE, and DIN. VIH MIN is the reference level for measuring timing of the addresses, CS, WE, and DIN. VSS +2.0V is the reference level for measuring timing of CEo VOO -2V is the reference level for measuring timing of CEo VSS +2.0V is the reference level for measuring the timing of 00UT. During CE high typically O.5mA will be drawn from any address pin which is switched from low to high. 5-85 SILICON GATE MOS 81078·4 A. C. Characteristics TA = oOc to 0 70 C, Voo = 12V ± 5%, VCC = 5V ± 10%, Va a READ, WRITE, AND READ MODIFY/WRITE CYCLE vss Symbol Parameter Min. Max. Unit 2 ms tREF Time Between Refresh tAC Address to CE Set Up Time 0 ns tAH Address Hold Time 100 ns tcc CE Off Time 130 tT CE Transition Time 10 tCF CE Off to Output High Impedance-State 0 = = -5V ± 5%, OV, unless otherwise noted. Conditions tAC is measured from end of address transition ns 40 ns ns READ CYCLE Symbol Parameter Min. Max. Unit Conditions Cycle Time 470 tCE CE On Time 300 tco CE Output Delay 250 ns C10ad tACC Address to Output Access 270 ns Ref = tWL CE to WE 0 ns twc WE to CE on 0 ns tCY ns 4000 tT = 20ns ns = 50pF, Load = One TTL Gate, 2.0V. tACC = tAC + tco + 1tT WRITE CYCLE Symbol Parameter Min. Max. Unit tCY Cycle Time 470 tCE CE On Time 300 tw WE to CE Off 150 ns tcw CE to WE 150 ns tow [2] DIN to WE Set Up 0 ns tOH DIN Hold Time 0 ns, twP WE Pulse Width 50 ns ns 4000 Conditions tT = 20ns ns Read Modify Write Cycle Symbol Parameter Min. Max. ns t RwC Read Modify Write( RMW) Cycle Time 590 t CRW CE Width During RMW 420 !wc WE to CE on 0 ns tw WE to CE off 150 ns twp WE Pulse Width 50 ns tow DIN to WE Set Up 0 ns t OH DIN Hold Time 0 ns tco CE to Output Delay 250 ns tACC Access Time 270 ns 4000 Conditions Unit tT = 20ns ns 5-86 C 10ad = 50pF, Load = One TTL Gate, Ref = 2.0V tACC = tAC + tco + ltT SILICON GATE MOS 81078·4 Typical Characteristics Fig. 1. 100 AV VS. TEMPERATURE Fig. 2. TYPICAL 100 AVERAGE VS. CYCLE TIME 2.0 . - - - - - - - . - - - - - - - . . . - - - - - - , 1.751--------4------+-----; 39 1-----4---+-.....-....::IIlr-+-----I1-- > ~ 1.51----------+----- -+-----_1 TA ! 0 w > 1.25 ~~":;;~~~b_,~~J;~RAIYl~1ike the 81078. The 8222 is designed ,'<:i"~:/:, for large, asynchronously driven, dynamic memory systems. 0 ~ '~ , ~~';;~~;~'~"!J;F~j») eft BLOCK DIAGRAM PIN CONFIGURATION START CYCLE REFRESH REQUEST LOGIC CYC. REQ. a BUSY ACK REF. ON REFREQ CYREQ STARTCY ADDRESS INPUT A 2 CENTER ADDRESS INPUT A 1 ADDRESS INPUT A o A 4 ADDRESS INPUT ADDRESS OUTPUT 00 As ADDRESS INPUT OUTPUT ADDRESSES Ao-A s MUX INPUT ADDRESSES ADDRESS OUTPUT 0 1 Vee ADDRESS OUTPUT 02 04 ADDRESS OUTPUT GROUND 03 ADDRESS OUTPUT cX/Rxl--I -=- 5-99 REF. REa. osc. D I/O 8212 8255 8251 Schottky Bipolar 8212 EIGHT-BIT INPUT/OUTPUT PORT • 3.65V Output High Voltage for Direct Interface to 8080 CPU or 8008 CPU • Asynchronous Register Clear • Replaces Buffers, Latches and Multiplexers in Microcomputer Systems • Reduces System Package Count • Fully Parallel 8-Bit Data Register and Buffer • Service Request Flip-Flop for Interrupt Generation • Low Input Load Current .25 mA Max. • Three State Outputs • Outputs Sink 1.5 mA The 8212 input/output port consists of an 8-bit latch with 3-state output buffers along with control and device selection logic. Also included is a service request flip-flop for the generation and control of interrupts to the microprocessor. The device is multimode in nature. It can be used to implement latches, gated buffers or multiplexers. Thus, all of the principal peripheral and input/output functions of a microcomputer system can be implemented with this device. PIN CONFIGURATI"ON LOGIC DIAGRAM SERVICE REQUEST FF \ vee OS1 MO INT 01, Dl a DO, OOa 01 2 01 7 0°2 0°7 01 3 01 6 00 3 0°6 01 4 015 0°4 0°5 STB CLR GND DS 2 DEVICE SELECTION -~ [DOS1 I!D OS2 ~ MO - - - - + -........L-~ [i> STB - - - - . . . - - - - 11> 01 3 - - - - - - -.................... [[> 01 4 ---------+--+-4 PIN NAMES 01,.01& DATA IN oo,-DOa DSi-DS2 MD DATA OUT STB INT CLR [9DI5-------~ ....... DEVICE SELECT MODE STROBE INTERRUPT (ACTIVE LOW) CLEAR (ACTIVE LOW) [g> 01 8 - - - - - - - - - 1 -....... (ACTIVE LOW) 5-101 OUTPUT BUFFER SCHOTTKY BIPOLAR 8212 Functional Description Data Latch The 8 flip-flops that make up the data latch are of a "0" type design. The output (Q) of the flip-flop will follow th~ data input (0) while the clock input (C) is high. Latching will occur when the clock (C) returns low. The data latch is cleared by an asynchronous reset input (CLR). (Note: Clock (C) Overides Reset (CLR).) Output Buffer The outputs of the data latch (Q) are connected to 3-state, non-inverting output buffers. These buffers have a common control line (EN); this control line either enables the buffer to transmit the data from the outputs of the data latch (Q) or disables the buffer; forcing the output into a high impedance state. (3 -state) This high-impedance state allows the designer to connect the 8212 directly onto the microprocessor bi-directional data bus. Service Request Flip-Flop The (SR) flip-flop is used to generate and control interrupts in microcomputer systems. It is asynchronously set by the CLR input (active low). When the (SR) flip-flop is.set it is in the non-interrupting state. The output of the (SR) flip-flop (Q) is connected to an inverting input of a "NOR" gate. The other input to the "NOR" gate is non-inverting and is connected to the device selection logic (081 • 082). The output of the "NOR" gate (INT) is active low (interrupting state) for connection to active low input priority generating circuits. SERVICE REQUEST FF \ DEVICE SELECTION -~ [I> OS1 [g> OS2 ~ MO - - - - t o 4 '_ _~ [ j j > S T B - -............ OUTPUT BUFFER Control Logic The 8212 has control inputs 051, 052, MO and STB. These inputs are used to control device selection, data latching, output buffer state and service request flip-flop. DATA LATCH [ [ > 0 1 2 - - - - - - - - + -..... DS1, DS2 (Device Select) These 2 inputs are used for device selection. When OS1 is low and OS2 is high (OS1 • OS2) the device is selected. In the selected state the output buffer is enabled and the service request flip-flop (SR) is asynchronously set. MD (Mode) This input is used to control the state of the output buffer and to determine the source of the clock input (C) to the data latch. When MO is high (output mode) the output buffers are enabled and the source of clock (C) to the data latch is from the device selection logic (051 • OS2). When MD is low (input mode) the output buffer state is det~rmined by the device selection logic (OS1 • OS2) and the source of clock (C) to the data latch is the.STB (Strobe) input. ff§> D IS - - - - - - -.............. ~ 01 7 ~D18-------~..... IE> C L R - - - - - 0 0 1 ~ ~ _.......--' (ACTIVE LOW) STB ~ MD 0 0 , , ,, 0 0 STB (Strobe) This input is used as the clock (C) to the data latch for the input mode MO = 0) and to synchronously reset the service request flip-flop (SR). -------+-1-1 0 5-102 ,, , ,, , -,- ~ Note that the SR flip-flop is negative edge triggered. 0 0 (DS,-DS2) 0 0 0 0 0 C'i:R - 1--- DATA OUT EaUALS 3-STATE 3=STAte-----DATA LATCH DATA LATCH DATA LATCH DATA IN DATA IN DATA IN RESETS DATA LATCH SETS SR FLlP·FLOP (NO EFFECT ON OUTPUT BUFFER) CLR 0 ,,, 0 1 (OS1-0S2) 0 STB 1 1 0 '- , , 0 0 0 0 ~I ,, , , , -SR 0 1 1 -INTERNAL SR FLIP-FLOP tNT 0 0 0 0 SCHOTTKY BIPOLAR 8212 Applications Of The 8212 -- For Microcomputer Systems I II III IV V VI Basic Schematic Symbol Gated Buffer Bi-Directional Bus Driver Interrupting Input Port Interrupt Instruction Port Output Port VII VIII IX 8080 Status Latch 8008 System 8080 System: 8 Input Ports 8 Output Ports 8 Level Priority Interrupt I. Basic Schematic Symbols Two examples of ways to draw the 8212 on system schematics-(1) the top being the detailed view showing pin numbers, and (2) the bottom being the symbolic view showing the system input or output as a system bus (bus containing 8 parallel lines). The output to the data bus is symbolic in referencing 8 parallel lines. BASIC SCHEMATIC SYMBOLS OUTPUT DEVICE INPUT DEVICE 11~-~ 3 5 3 01 5 7 9 16 7 9 16 18 8212 (DETAILED) 4 6 01 STB DO 8 10 8212 15 18 20 20 - 17 19 -- 22 INT CLR 21 23 / MD '" 14 I~ DS 2 13 INPUT STROBE SYSTEM INPUT 2 1 Vee _ - - - . . . . - OUTPUT FLAG (SYMBOLIC) 8212 CLR INT INT GND DATA BUS SYSTEM OUTPUT 8212 CLR DATA BUS GATED BUFFER II. Gated Buffer ( 3· STATE) 3-STATE The simplest use of the 8212 is that of a gated buffer. By tying the mode signal low and the strobe input high, the data latch is acting as a straight through gate. The output buffers are then enabled from the device selection logic 051 and 052. When the device selection logic is false, the outputs Vee - - - - - - - . . - - - 8TB INPUT DATA (250 ~A) are 3-state. When the device selection logic is true, the input data from the system is directly transferred to the output. The input data load is 250 micro amps. The output data can sink 15 milli amps. The minimum high output is 3.65 volts. """'------C)I 8212 CLR GATING { CONTROL (081-082) 5-103 ---......--------' OUTPUT DATA (15mA) (3.65V MIN) SCHOTTKY BIPOLAR 8212 III. Bi-Directional Bus Driver BI-DIRECTIONAL BUS DRIVER A pair of 8212's wired (back-to-back) can be used as a symmetrical drive, bi-directional bus driver. The devices are controlled by the data bus input control which is connected to D81 on the first 8212 and to D82 on the second. One device is active, and acting as a straight through buffer the other is in 3-state mode. This is a very useful circuit in small system design. STB DATA---~ BUS DATA BUS CONTROL (o= L - R) (I = R - 1----'---......... OATA 8212 BUS GND L) STB 8212 GND INTERRUPTING INPUT PORT IV. Interrupting Input Port This use of an 8212 is that of a system input port that accepts a strobe from the system input source, which in turn clears the service request flip-flop and interrupts the processor. The processor then goes through a service routine, identifies the port, and causes the device selection logic to go true enabling the system input data onto the data bus. DATA BUS INPUT STROBE STB SYSTEM INPUT SYSTEM RESET PORT { SELECTION (DS1.DS2) --------' TO PRIORITY CKT _ - . . . - (ACTIVE LOW) OR . TO CPU INTERRUPT INPUT INTERRUPT INSTRUCTION PORT V. Interrupt Instruction Port The 8212 can be used to gate the interrupt instruction, normally RESTART instructions, onto the data bus. The device is enabled from the interrupt acknowledge signal from the microprocessor and from a port selection signal. This signal is normally tied to ground. (081 could be used to multiplex a variety of interrupt instruction ports onto a common bus). DATA BUS STB RESTART INSTRUCTION (RST 0 - RST 7) (DSI) PORT SELECTION - ........~ INTERRUPT ACKNOWLEDGE - . . . - - _.......... 5-104 SCHOTTKY BIPOLAR 8212 VI. Output Port (With Hand-Shaking) OUTPUT PORT (WITH HAND-SHAKING) The 8212 can be used to transmit data from the data bus to a system output. The output strobe could be a hand-shaking signal such as "reception of data" from the device that the system is outputting to. It in turn, can interrupt the system signifying the reception of data. The selection of the port comes from the device selection logic. (OS1· OS2) DATA BUS r----~- OUTPUT STROBE STB 8212 INT SYSTEM INTERRUPT SYSTEM OUTPUT CLR 11.>----...-- SYSTEM RESET L..-- ..._- } PORT SELECTION (LATCH CONTROL) (OS1.0S2) VII. 8080 Status Latch Note: The mode signal is tied high so that the output on the latch is active and enabled all the time. It is shown that the two areas of concern are the bidirectional data bus of the microprocessor and the control bus. Here the 8212 is used as the status latch for an 8080 microcomputer system. The input to the 8212 latch is directly from the 8080 data bus. Timing shows that when the SYNC signal is true, which is connected to the OS2 input and the phase 1 signal is true, which is a TTL level coming from the clock generator; then, the status data will be latched into the 8212. 8080 STATUS LATCH DO 0, SYNC OBIN 19 -17 STATUS LATCH 15 3 f\ ovJ OATA BUS 2 22 12V 9 8 °2 7 °3 3 °4 4 Os 5 °6 6 °7 8080 1 10 "'"'--- 5 7 \.. -4 ~) CLOCK GEN. & DRIVER 9 -- (1TTL) I""-- 16 18 20 22 0, 4 °0 I6- - - INTA I - - - WO STACK ~ HLTA OUT 8212 17 ~ M1 19 ~ INP 21 I - - - MEMR T1 L- 1 J..L CLR 14 OS2 MO OS, BASIC 2 CONTROL BUS SYNC r<: ·13 12 I I 5-105 OATA 11 I OBIN STATUS T2 SCHOTTKY BIPOLAR 8212 VIII. 8008 System This shows the 8212 used in an 8008 microcomputer system. They are used to multiplex the data from three different sources onto the 8008 input data bus. The three sources of data are: memory data, input data, and the interrupt instruction. The 8212 is also used as the uni-directional bus driver to provide a proper drive to the address latches (both low order and high order are also 8212's) and to provide adequate drive to the output data bus. The control of these six 8212's in the 8008 system is provided by the control logic and clock generator circuits. These circuits consist of flip-flops, decoders, and gates to generate the control functions necessary for 8008 microcomputer systems. Also note that the input data port has a strobe input. This allows the proces- sor to be interrupted from the input port directly. The control of the input bus consists of the data bus input signal, control logic, and the appropriate status signal for bus discipline whether memory read, input, or interrupt acknowledge. The combination of these four signals determines which one of these three devices will have access to the input data bus. The bus driver, which is implemented in an 8212, is also controlled by the control logic and clock generator so it can be 3-stated when necessary and also as a control transmission device to the address latches. Note: The address latches can be 3-stated for DMA purposes and they provide 15 miHi amps drive, sufficient for large bus systems. 8008 SYSTEM INPUT DATA BUS BUS DRIVER ADDRESS LATCHES LOW ORDER (8 BITS) MEMORY DATA ------vee INPUT STROBE 00-07 INPUT DATA HIGH ORDER (6 BITS) SYNC ¢1 INT READY ~ ¢2 I t l BUS I • • • • • • DATA OUT L-..----......----0111 MEM READ """--'----------4----rJIII INPUT - - - - - - - - - 4 - - - - - o I I I I N T ACK INTERRUPT INSTRUCTION 8212 - - - - - . . . . . . - - - - - t l D A T A BUS IN ' - f - - I - - - - - - - - - - - - . q , N T REO. WAIT REQ.------l.MI '- (04,5,6,7) I b - - - - - - - - - ... WR I .. OUT I J CONTROL LOGIC & CLOCK GEN. 5-106 SCHOTTKY BIPOLAR 8212 . IX. 8080 System This drawing shows the 8212 used in the I/O section of an 8080 microcomputer system. The system consists of 8 input ports, 8 output ports, 8 level priority systems, and a bidirectional bus driver. (The data bus within the system is darkened for emphasis). Basically, the operation would be as follows: The 8 ports, for example, could be connected to 8 keyboards, each keyboard having its own priority level. The keyboard could provide a strobe input of its own which would clear the service request flip-flop. The INT signals are connected to an 8 level priority encoding circuit. This circuit provides a positive true level to the central processor (lNT) along with a three-bit code to the interrupt instruction port for the generation of RESTART instructions. Once the processor has been interrupted and it acknowledges the reception of the interrupt, the Interrupt Acknowledge signal is generated. This signal transfers data in the form of a RESTART instruction onto the buffered data bus. When the DBIN signal is true this RESTART instruction is gated into the microcomputer, in this case, the 8080 CPU. The 8080 then performs a software controlled interrupt service routine, saving the status of its current operation in the push-down stack and performing an INPUT instruction. The INPUT instruction thus sets the INP status bit, which is common to all input ports. Also present is the address of the device on the 8080 address bus which in this system is connected to an 8205, one out of eight decoder with active low outputs. These active low outputs will enable one of the input ports, the one that interrupted the processor, to put its data onto the buffered data bus to be transmitted to the CPU when the data bus input signal is true. The processor can also output data from the 8080 data bus to the buffered data bus when the data bus input signal is false. Using the same address selection technique from the 8205 decoder and the output status bit, we can select with this system one of eight output ports to transmit the data to the system's output device structure. Note: This basic I/O configuration for the 8080 can be expanded to 256 input devices and 256 output devices all using 8212 and, of course, the appropriate decoding. 5-107 Note that the 8080 is a 3.3-volt minimum high input requirement and that the 8212 has a 3.65-volt minimum high output providing the designer with a 350 milli volt noise margin worst case for 8080 systems when using the 8212. SCHOTTKY BIPOLAR 8212 (See Note 1) AO - ' A 1 --+8080 ADDRESS .:... BUS A 2 --+- 8205 ST;~;T:¢ ST:212 t :7: :~ l l ltn ~ ::=:- ~ ~ E1 ~ --0 E2 ::Vee- ..E_3_ _.. ~ ;:N~~- I/O DEVICE SELECTOR :IIII[ INP - -......----t-t-t-t-t-+--+-t------------+-6 8212 _~L~ee? => ~:~~T STROBE 2 ---. STB INPUT ~ PORT 2 L-Y STATUS BITS - 8212 8212 ~ OUTPUT PORT 2 W ~ CLR _ INT OUT ----t------r-t-t-t-t----ir+-t-----------+--+----1~:::::f_4 r- D:J:~!I. DalN-t?!NrJ ~ ~ 8212 I 8212 ~ I I 0 '1IO-++++----4~ 1 IO-++++-.-.....~ 2 1O-++++---oIt--..... H I ~ --I ................ I v~e ~ I: I L __ II_ 8212 u +--.s> GND -----..----t: INTERRUPT INSTRUCTION PORT (RST) ~ L-~ :111 8212 y ~ OUTPUT W PORT 4 _~L:ee y ST;~;;~¢ ST:212 ~m:~~j!II!:w::7::~3 8212 t> ~~~~~T ~ ~~~~_. I! ! -~~e I I I ..I I PRIORITY ENCODER & INTERRUPT GENERATING LOGIC CIRCUITS (USER DESIGNED) CLR ~f ::::: i I GND y 1G~D I ttm::zb ill\:,z:Zht~ 8212 1O-++++---oIt---------<:::JIINT 5 1O-++++---oIt--_ =: I INPUT ~ PORT 4 L.-,I 3 IO-++++-.....-~ 4 Ill:: STROBE 4 --. STB I I I - - I I PORT 3 0-<1 -, I ~ 8080 --...J.. ~ OUTPUT I I I Vee I I BUFFERED DATA BUS INT ACK ST;;;;T::: ST:212 m::ili::~Jtmm:~ 8212 W _----L.-,I-<~J11INT CLR -Y[[~\! . : CLR . 1G~D L-_ :::[:[ ,_-.J Vee Y --------004----------1 ST;;;;T:¢ ST:2~ : : : : : : : :~ .......------<=.11 INT CLR ~~ II::::::::::::::::::::? :~:~: 8212 ~ OUTPUT hi" PORT 6 ~ CLR 1G~D L-_ \l~\l -~ Vee I BI-DI RECTIONAL BUS DRIVER STROBE 7 ---+- STB 8212 8212 ~OUTPUT PORT 7 W SYSTEM--.....RESET Note 1. This basic I/O configuration for the 8080 can be expanded to 256 input devices and 256 output devices all using 8212 and the appropriate decoding. 5-108 SCHOTTKY BIPOLAR 8212 Absolute Maximum Ratings· Temperature Under Bias Plastic .. -65°C to + 75°C Storage Temperature -65°C to +160°C All Output or Supply Voltages - 0.5 to + 7 Volts ,All Input Voltages -1.0 to 5.5 Volts Output Currents *COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. 125 mA D.C. Characteristics = O°C to + 75°C 'Vee = +5V ±5°k TA Symbol Parameter Limits Min. Typ. Unit Test Conditions Max. IF Input Load Current ACK, 05 2 , CR, Oll-Ols Inputs -.25 mA VF = .45V IF Input Load Current MO Input -.75 mA VF = .45V IF Input Load Current OSI Input -1.0 mA VF = .45V IR Input Leakage Current ACK, OS, CR, Oil-Dis Inputs 10 }lA VR = 5.25V IR Input Leakage Current MO Input 30 JvtA VR = 5.25V IR Input Leakage Current OSI Input 40 {tA VR = 5.25V Vc Input Forward Voltage Clamp -1 V Ie = -5 mA V1L V1H Input "Low" Voltage .85 V VOL Output "Low" Voltage VOH Ise Output "High" Voltage 3.65 Short Circuit Output Current -15 Input "High" Voltage 11 01 Output Leakage Current High Impedance State lee Power Supply Current 2.0 V .45 4.0 90 5-109 V V -75 20 mA 130 mA {tA = 15 mA 10H = -1 mA Va = OV Va = .45V/ 5.25V lal SCHOTTKY BIPOLAR 8212 Typical Characteristics INPUT CURRENT YS. INPUT YOLTAGE o r Vee Vee (;" ....z TA =o°c""'" '/ w -150 « E = 25°C V : / TA =75°C V / TA I- zw I- I:::J ~ 60 a: a: :::J u u a. =+5.0V 801-----1----1----+--------4 I « -100 ..=: ~ 100 ....----.,...----.,...----~--____. ~~~ =+5.0V -50 :::J OUTPUT CURRENT VS. OUTPUT "LOW" YOLTAGE :;) ....a. :;) -200 40 0 20 -250 -300 -3 -2 o -1 +1 +2 O'---~~'-----'-----.L..------' o +3 .2 INPUT VOLTAGE (vt DATA TO OUTPUT DELAY YS. LOAD CAPACITANCE O---.......---------------.--~-5 .8 .6 OUTPUT "LOW" VOLTAGE (V) OUTPUT CURRENT YS. OUTPUT "HIGH" YOLTAGE Vee .4 50 =+5.0V I Vee =- +5.0V TA = 25°C I-----+----+----+------#~----I 40 « E. -10 TA ! =75"C > et ~ w I- z w a: a: TA = 25"C :::J u I- :::> 0 I:::J CL I:::J -15 1----+------.,~~-4---= TA = -20 O"'C 0 0 CL ......- ~ et et -' I- -25 .,.,-""- 0 .,.,-""- ~~ ~.,.,- .,.,--- - \ ++ .,.,-"".- .,.,20 I- I:::J 0 30 ~ .,.,- .,.,-0iI' ~ 10 -30 -35 O. 22 1.0 3.0 2.0 4.0 5.0 100 50 150 200 250 OUTPUT "HIGH" VOLTAGE (V) LOAD CAPACITANCE (pF) DATA TO OUTPUT DELAY YS. TEMPERATURE WRITE ENABLE TO OUTPUT DELAY YS. TEMPERATURE 40 T Vee = +5.0V 300 1 vee =+5.0V I 20 E. et « 18 CL \.';,'c" 16 0 0 I- et et w 1..0'/ ~ I:::J ~ // ~ w 0 I:::J I > III .: > 35 ,," " ~" 14 30 o oI- 25 I:::J CL I:::J " - c t-- \.'c~ " 5TB< 05 2 W ~ ~ co ~ I- 20 w w 0 --~ ---- ... -------~---- "filii' ,,-""- ____ f'" -\' -\.'-, .,.,- ~ --t +_ t-_ ............ 05,<:: ~ ~ I- ~ ~ 12 10 -25 o 25 50 75 10 -25 100 TEMPERATURE (OC) -- 15 o 25 50 TEMPERATURE rc) 5-110 75 100 SCHOTTKY BIPOLAR 8212 Timing Diagram 1.5Vy----------y.5V DATA _____ -J. I;==t pw 1.5vl STB or oSl • oS2 ~twE=J ~I_ tH :.j'---- ' -1._5V _ -/'10-:------- OUTPUT 1.5Vj oSl. OS2 ________l_tE_~ r ~E~~~W_) _ X OUTPUT \1.5V __ ~-t-D-~---- ~----,~t- I~tpw~I 1.5V\. eLR .5fV 11.5V ~~~~~~~~~~~~1r----- ><"-:._5V DO _____ J r1.5V . _ _ _ _ _ _ _--+-_--_--_-_tS _E_T_--__'-_" STB or _ 1.SV X- - - ----------- -- 'i1.5V DATA OS, • DS2 ~ 'OUTPUT -j tPD-j J{SV- - - - - - - - - -- _ _ _ _ _ _ _ .J -----,I STB _ _'I~ tH !--tpw \~1.5V _ 1.5V ~tPw-~ts I NOTE: ALTERNATIVE TEST LOAD Vcc 10K OUT 0---....----. CL ·lK 5-111 Y VOH VOL SCHOTTKY BIPOLAR 8212 A.C. Characteristics TA = O°C to + 75°C Symbol Vee = +5V ± 5% Limits Parameter Typ. Min. Unit t pw Pulse Width t pd Data To Output Delay 30 ns t we Write Enable To Output Delay 40 ns t set Data Setu·p Time 15 ns th Data Hold Time 20 ns tr Reset To Output Delay 40 ns ts Set To Output Delay 30 ns te Output Enable/Disable Time 45 ns tc Clear To Output Delay 55 ns CAPACITANCE * Symbol F 30 = 1 MHz VsrAs = 2.5V Vee Test Conditions Max. ns = Test +5V TA = 25°C LIMITS Typ. Max. CIN DS I MD Input Capacitance 9 pF 12 pF CIN DS 2 , CK, ACK, Oil-Dis Input Capacitance 5 pF 9 pF COUT DOl-DOs Output Capacitance 8 pF 12 pF *This parameter is sampled and not 100% tested. Switching Characteristics TEST LOAD CONDITIONS OF TEST Input Pulse Amplitude = 2.5 V Input Rise and Fall Times 5 ns Between 1V and 2V Measurements made at 1.5V with 15 rnA & 30 pF Test Load 15mA & 30pF 300 TO D.U.T. 600 * INCLUDING JIG & 5-112 PROBE CAPACITANCE Silicon Gate MOS 8255 PROGRAMMABLE PERIPHERAL INTERFACE • Direct Bit Set/Reset Capability Easing Control Application Interface • 40 Pin Dual In-Line Package • Reduces System Package Count • 24 Programmable I/O Pins • Completely TTL Compatible • Fully Comp.atible with MCS™-8 and MCSTM'_80 Microprocessor Families The 8255 is a general purpose programmable I/O device designed for use with both the 8008 and 8080 microprocessors. It has 24 I/O pins which may be individually programmed in two groups of twelve and used in three major modes of operation. In the first mode (Mode 0), each group of twelve I/O pins may be programmed in sets of 4 to be input or output. In Mode 1, the second mode, each group may be programmed to have 8 lines of input or output. Of the remaining four pins three are used for handshaking and interrupt control signals. The third mode of operation (Mode 2) is a Bidirectional Bus mode which uses 8 lines for a bidirectional bus, and five lines, borrowing one from the other group, for handshaking. Other features of the 8255 include bit set and reset capability and the ability to source 1mA of current at 1.5 volts. This allows darlington transistors to be directly driven for applications such as printers and high voltage displays. PIN CONFIGURATION PA3 1 PA2 2 39 PA5 PAl 3 38 PA6 PAO 4 37 PA7 AD 5 36 WR cs G 35 RESET GNO 7 34 DO Al 8 33 01 AO 9 32 O2 PC7 10 31 03 PCG 11 30 04 PC5 12 29 Os PC4 13 28 06 PCO 14 27 ~ 8255 8255 BLOCK DIAGRAM S~~~lEI~S 1-- +SV --GND 1'\.....-----./ PCl 15 26 V CC PC2 16 25 PB7 PC3 17 24 PB6 PBO 18 23 PB5 PB1 19 22 PB4 PB2 20 21 PB3 I/~-~ 1'\......--.-.... / iffi A, PIN NAMES DATA BUS (BI-DIRECTIONAL) RESET INPUT CS CHIP SELECT READ INPUT WR WRITE INPUT AO,A1 PORT ADDRESS PA7·PAO. PORT A (BIT) PB7·PBO PORT B (BIT) PC7·PCO PORT C (BIT) VCC +5 VOLTS GND gVOLTS 1'0 PC3·PCO 0 - - - 0 :~~~~ I C~~~~~L ./'--""_ , 1'\......--.- Ao---I RESET---I 0 7 -00 RESET 1'0 PCrPC4 BI·DIRECTIONAl DATA BUS WR RD 1'0 1'\.,....---./ PA7·PAO cs------' 5-113 / 1/0 PBrPBo SILICON GATE MOS 8255 8255 BASIC FUNCTIONAL DESCRIPTION (RD) General Read: A II10w" on this input pin enables the 8255 to send the Data or Status information to the 8080 CPU on the Data Bus. In essence, it allows the 8080 CPU to II read from" the 8255. The 8255 is a Programmable Peripheral Interface (PPI) device designed for use in 8080 Microcomputer Systems. Its function is that of a general purpose I/O component to interface peripheral equipment to the 8080 system bus. The functional configuration of the 8255 is programmed by the system software so that normally no external logic is necessary to interface peripheral devices or structures. (WR) Write: A "low" on this input pin enables the 8080 CPU to write Data or Control words into the 8255. (AO and A1) Data Bus Buffer Port Select 0 and Port Select 1: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the Control Word Register. They are normally connected to the least significant bits of the Address Bus (A o and A 1 ). This 3-state, bi-directional, eight bit buffer is used to interface the 8255 to the 8080 system data bus. Data is transmitted or received by the buffer upon execution of INput or OUTput instructions by the 8080 cPU. Control Words and Status information are also transferred through the Data Bus buffer. 8255 BASIC OPERATION AO 0 1 0 RD WR CS 0 0 0 1 1 1 0 0 0 PORT A ~ DATA BUS PORT B => DATA BUS PORT C=> DATA BUS OUTPUT OPERATION (WRITE) 0 0 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 DATA BUS => PORT A DATA BUS => PORT B DATA BUS~ PORT C DATA BUS => CONTROL X X X 1 1 1 X 0 1 0 A1 Read/Write and Control Logic 0 0 The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the 8080 CPU Address and Control busses and in turn, issues commands to both of the Control Groups. 1 1 1 INPUT OPERATION (READ) DISABLE FUNCTION Chip Select: A "low" on this input pin enables the communication between the 8255 and the 8080 CPU. 8255 Block Diagram 5-114 DATA BUS=> 3-STATE ILLEGAL CONDITION SILICON GATE MOS 8255 (RESET) Ports A, B, and C Reset: A "high" on this input clears all internal registers including the Control Register and all ports (A, B, C) are set to the input mode. The 8255 contains three 8-bit ports (A, S, and C). All can be configured in a wide variety of functional characteristics by the system software but each has its own speci al featu res or "personality" to further enhance the power and flexibil ity of the 8255. Group A and Group B Controls The functional configuration of each port is programmed by the systems software. In essence, the 8080 CPU "outputs" a control word to the 8255. The control word contains information such as "mode", "bit set", "bit reset" etc. that initializes the functional configuration of the 8255. Port A: One 8-bit data output latch/buffer and one 8-bit data input latch. Port B: One 8-bit data input/output latch/buffer and one 8-bit data input buffer. Each of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write. Control Logic, receives "control words" from the internal data bus and issues the proper commands to its associated ports. Port C: One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4bit port contains a 4-bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with Ports A and B. Control Group A - Port A and Port C upper (C7-C4) Control Group B - Port B and Port Clower (C3-CO) The Control Word Register can Only be written into. No Read operation of the Control Word Register is allowed. 8255 BLOCK DIAGRAM PIN CONFIGURATION PA3 1 PA2 2 39 PA5 PAl 3 38 PA6 PAO 4 37 PA7 AD 5 36 WR cs 6 35 RESET GNO 7 34 DO A1 8 33 0, AO 9 32 O2 PC7 10 31 03 PC6 11 30 04 PC5 12 Os PC4 13 06 PCO 14 PC1 15 PA4 8255 0, 26 V CC P86 PC2 16 PC3 17 24 P80 18 23 P85 P81 19 22 P84 P82 20 21 P83 P87 PIN NAMES 0 7 -00 5-115 DATA BUS (BI-DIRECTIONAL) RESET RESET INPUT CS CHIP SELECT RD READ INPUT WR WRITE INPUT AO,A1 PORT ADDRESS PA7·PAO PORT A (BIT) PB7·PBO PORT B (BIT) PC7·PCO PORT C (SfT) VCC GND +5VOL1S "VOLTS j 1 SILICON GATE MOS 8255 8255 DETAILED OPERATIONAL DESCRIPTION CONTROL WORD Mode Selection There are three basic modes of operation that can be selected by the system software: Mode 0 - Basic Input/Output Mode 1 - Strobed Input/Output Mode 2 - Bi-Directional Bus ~ When the RESET input goes "high" all ports will be set to the Input mode (Le., all 24 lines will be in the high impedance state). After the RESET is removed the 8255 can remain in the Input mode with no additional initialization required. During the execution of the system program any of the other modes may be selected using a single OUTput instruction. This allows a single 8255 to service a variety of peripheral devices with a simple software maintenance routine. GROUPB '" PORT C (LOWER) 1 = INPUT 0= OUTPUT ~ PORTB 1 = INPUT 0= OUTPUT MODE SELECTION 0= MODE 0 1 = MODE 1 The modes for Port A and Port B can be separately defined, while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status fl ip-flops, will be reset whenever the mode is changed. Modes may be combined so that their functional definition can be "tailored" to almost any I/O structure. For instance; Group B can be programmed in Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt-driven basis. ;I' GROUP A '" PORT C (UPPER) 1 = INPUT 0= OUTPUT PORTA 1 = INPUT 0= OUTPUT MODE SELECTION 00= MODE 0 01 = MODE 1 1X =MODE 2 MODE SET FLAG 1 = ACTIVE Mode Definition Format C MODE 1 --....rL.~~8~B-1/-o..J;itllfTm=;;;;:;;:::;:t:=::::;:::;:;:::;;J.i-~~:~I.J/O Pa,.PBo MODE 2 CONTROL OR I/O CONTROL OR I/O ~"'----rrrnmi I/O I CONtROL PA7 ·pAo A r The Mode definitions and possible Mode combinations may seem confusing at first but after a cursory review of the complete device operation a simple, logical I/O approach will surface. The design of the 8255 has taken into account things such as efficient PC board layout, control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of the available pins. ~I.DIRECTIONAL Single Bit Set/Reset Feature I Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction. This feature reduces software requirements in Control-based applications. Basic Mode Definitions and Bus Interface 5-116 SILICON GATE MOS 8255 When Port C is being used as status/control for Port A or B, these bits can be set or reset by using the Bit Set/Reset operation just as if they were data output ports. CONTROL WORD r 07 t 06 I 1 05 04 I 0 3 1 O2 I 0, I DO I L I I x,I ,x X I Interrupt Control Functions BIT SET/RESET 1 =SET 0:: RESET DON'T CARE BIT SELECT o1 2 3 4 o1 o1 o o0 1 1 o o0 o0 1 5 6 7 1 o1 0 1 1 B,-l 1 1 1 B21 801 When' the-' 8255 is programmed to operate in Mode 1 or Mode 2, control signals are provided that can be used as interrupt request inputs to the CPU. The interrupt request signals, generated from Port C, can be inhibited or enabled by setting or resetting the associated INTE flip-flop, using the' Bit set/reset function of Port C. This function allows the Programmer to disallow or allow a .specific I/O device to interrupt the CPU without effecting any other device in the interrupt structure. INTE flip-flop definition: BIT SET/RESET FLAG Om ACTIVE (BIT-SET) - INTE is SET - Interrupt enable (BIT-RESET) - INTE is RESET - Interrupt disable Note: All Mask flip-flops are automatically reset during mode selection and device Reset. Bit Set/Reset Format Operating Modes Mode 0 Basic Functional Definitions: Mode 0 (Basic Input/Output) • Two 8-bit ports and two 4-bit ports. • Any port can be input or output. • Outputs are latched. • Inputs are not latched. • 16 different Input/Output configurations are possible in this Mode. This functional configuratioD provides simple .1 nput and Output operations for each ,of the three ports. No "handshaking" is required, data is simply written to or read from a specified port. BASIC INPUT TIMING (07-00 FOLLOWS INPUT, NO LATCHING) INPUT --------- tDELAYTIME FROM RD t DELAY TIME FROM INPUT DATA -------X ------- X----------- ~ SET·UP VIOLATION BASIC OUTPUT TIMING (OUTPUTS LATCHED) OUTPUT tDATA - . SET·UP Mode 0 Timing 5-117 SILICON GATE MOS 8255 MODE 0 PORT DEFINITION CHART A B GROUPA GROUPB PORTC PORTC 04 03 01 DO PORTA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 OUTPUT OUTPUT OUTPUT OUTPUT 1 1 0 0 1 OUTPUT INPUT 7 INPUT INPUT 0 INPUT OUTPUT 8 OUTPUT OUTPUT 1 INPUT OUTPUT 9 OUTPUT INPUT 1 0 INPUT OUTPUT 10 INPUT OUTPUT 1 0 0 1 1 INPUT OUTPUT 11 INPUT INPUT 1 1 0 INPUT INPUT 12 OUTPUT OUTPUT 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 # PORT B OUTPUT OUTPUT 0 1 OUTPUT INPUT OUTPUT 2 INPUT OUTPUT 3 4 INPUT INPUT OUTPUT OUTPUT (UPPER) 1 OUTPUT OUTPUT 0 OUTPUT INPUT 1 OUTPUT INPUT 0 OUTPUT INPUT 5 6 (LOWER) OUTPUT OUTPUT INPUT INPUT OUTPUT 1 INPUT INPUT INPUT INPUT INPUT 13 14 OUTPUT 0 INPUT OUTPUT 1 INPUT INPUT 15 INPUT INPUT MODE 0 CONFIGURATIONS CONTROL WORD #2 CONTROL WORD #0 ~ 06 05 04 03 O2 0, D7 DO .1 A 06 05 04 03 02 8 . c{ ,4 c{ I ,,4 ,.1 8 B 05 04 03 02 0, 07 DO 8 A 06 05 04 D3 O2 0, PA7·pAo ,/4 --.1 8 I DO A ,.1 8 - ,4 - 8255 8255 ° 7-°0 ,4 CONTROL WORD #3 CONTROL WORO #1 06 ,,8 8255 B 07 00 A 8255 . 0, 4 c{ °7·°0 ; B PC,-PC4 ,4 8 . ., c{ PC3·PCO ,4 I B Ps.,.PBo 5-118 I ' 8 Ps.,.PBO SILICON GATE MOS 8255 CONTROL WORD #8 CONTROL WORD #4 07 A 06 Os 04 03 ,02 A B , ,4 . . ,4 18 I c{ 07 ,8 A -, c{ -, • 06 05 04 03 O2 04 ,4 ,,4 ,8 I c{ pc'-PC4 0 7 -00 PC3 -PCO B P~-PBO 07 B 06 06 04 O2 0, ,8 PA7 ·pAo ,4 -, ,4 -, ,8 I PC7 ·PC4 PC3 -PCO P~.PBO DO A 14 c{ ,,4 -,' 8 B ,,8 14 ,1 4 ,8 -, CONTROL WORD #11 03 07 A 8 06 05 PA7 ·pAo A 8255 0 7-00 03 -, CONTROL WORD #7 04 ,8 I 8255 c{ 05 . CONTROL WORD #10 8255 06 DO A 03 A 07 0, PA7 -PAo CONTROL WORD #6 05 18 -, 8255 B 06 ,4 CONTROL WORD #9 8255 07 ,8 -, B P~.PBO 05 . I ,,4 -, CONTROL WORD #5 0, . 8255 c{ • DO ,18 8255 . 0, 8 PA7 ·pAo 8255 c{ B 4 PC7 ·PC4 0 7 .00 4 8 PC3 ·PCO P~.PBo c{ B 5-119 4 4 8 PC7 ·PC4 PC3 -PCO PS,-PBo SILICON GATE MOS 8255 CONTROL WORD #12 07 06 05 04 CONTROL WORD #14 03 O2 07 01 A 06 05 04 03 O2 ,8 . 8255 c{ · B ,4 . / ,,4 06 05 04 c{ • ,8 B ~ I CONTROL WORD #13 07 DO A F 8255 • 0, . . ,8 I ,4 I ,4 . ,8 I CONTROL WORD #15 03 O2 0, 07 DO A 06 05 04 03 O2 0, ,8 DO ,8 A 7 8255 8255 c{ , 4 c{ I ,4 7 B ,4 1 ,4 7 ,8 B I ,,8 P~.PBO Mode 1 Basic Functional Definitions: Operating Modes • Two Groups (Group A and Group B) • Each group contains one 8-bit·data-port and one 4-bit control/data port. • The 8-bit data port can be either input or output. Both inputs and outputs are latched. • The 4-bit port is used for control and status of the 8-bit data port. Mode 1 (Strobed Input/Output) This functional configuration provides a means for .transferring I/O data to or from a specified port in conjunction with strobes or "handshaking'~ signals. In Mode 1, Port A and Port B use the Iines on Port C to generate or accept these "handshaking~' signals. 5-120 SILICON GATE MOS 8255 Input Control Signal Definition MODE 1 (PORT A) STB (Strobe (nput) A "low" on this input loads data into the input latch. CONTROL WORD IBF (Input Buffer Full F/F) STB A A "high" on this output indicates that the data has been loaded into the input latch; in essence, an acknowledgement ISF is set by the falling edge of the STB input and is reset by the rising edge of the RD input. IBF A INTRA RD INTR (Interrupt Request) I/O A "high" on this output can be used to interrupt the CPU when an input device is requesting service. INTR is set by the rising edge of STB if IBF is a "one" and INTE is a "one". It is reset by the falling edge of RD. This procedure allows an input device to request service from the CPU by simply strobing its data into the port. MODE 1 (PORT B) INTE A Controlled by bit set/reset of PC 4. INTE B Controlled by bit set/reset of PC2. Mode 1 Input MODE 1 (STROBED INPUT) BASIC TIMING IBF (INPUT BUFFER FULL) """""""'..........,~ NO PROTECTION FOR THIS OPERATION DATA INPUT INTERNAL INPUT LATCH \ INTR Basic Timing Input 5-121 \-_-------- SILICON GATE MOS 8255 Output Control Signal Definition OBF (Output Buffer Full F/F) MODE 1 (PORT A) The OBF output will go ~'Iow" to indicate that the CPU has written data out to the specified port. The OBF F/F will be set by the rising edge of the WR input and reset by the failing edge of the ACK input signal. CONTROL WORD r- - -, I INTE I I __ A .JI ACK (Acknowledge Input) A "Iow" on this input informs the 8255 that the data from Port A or Port B has been accepted. In essence, a response from the peripheral device ind icating that it has received the data output by the CPU. INTR (Interrupt Request) MODE 1 (PORT B) A "high" on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU. INTR is set by the rising edge of ACK if OBF is a "one" and INTE is a "one". It is reset by the falling edge ofWR. P~.PBo 0 7 0 6 Os 0 4 0 3 O2 0, Do PC, INTEA Controlled by bit set/reset of PC 6. INTE B Controlled by bit set/reset of PC 2. Mode 1 Output (OUTPUT BUFFER FULL) / NO PROTECTION FOR THIS OPERATION DATA BUS OUTPUT 8 CONTROL WORD \ ~- Basic Timing Output 5-122 -- - ----- - - ------ OBFB SILICON GATE MOS 8255 Combinations of Mode 1 Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications. PA7 -PAo PA 7 -PAO 8 PC4 STBA PCs IBFA 8 PC 7 OBFA PC6 - + - - ACKA CONTROL WORD PC3 PC 3 INTRA 2 PC6 • 7 ..-.;-.-.. I/O P~-PBO INTRA 2 PC4 • 5 I/O PB7 -PBo 8 PC, INTR B PC 2 STBB PC, IBFB PCo INTR B PORT A - (STROBED OUTPUT) PORT B - (STROBED INPUT) PORT A - (STROBED INPUT) PORT B - (STROBED OUTPUT) Operating Modes Output Operations Mode 2 (Strobed Bi-Directional Bus I/O) OBF (Output Buffer Full) This functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bi-directional bus I/O). "Handshaking" signals are provided to maintain proper bus flow discipline in a similar manner to Mode 1. Interrupt generation and enable/disable fu nctions are also available. The OBF output will go "low" to indicate that the CPU has written data out to Port A. Mode 2 Basic Functional Definitions: • Used in Group A only. • One 8-bit, bi-directional bus Port (Port A) and a 5-bit control Port (Port C). • Both inputs and outputs are latched. • The 5-bit control port (Port C) is used for control and status for the 8-bit, bi-directional bus port (Port A). Bi-Directional Bus I/O Control Signal Definition INTR (Interrupt Request) A high on this output can be used to interrupt the CPU for both input or output operations. ACK (Acknowledge) A "Iow" on this input enables the tri-state output buffer of Port A to send out the data. Otherwise, the output buffer will be in the high-impedance state. INTE 1 (The INTE Flip-Flop associated with OBF) Controlled by bit set/reset of PCs. Input Operations STB (Strobe Input) A "low" on this input loads data into the input latch. IBF (Input Buffer Full F/F) A "h igh" on th is output indicates that data has been loaded into the input latch. INTE 2 (The INTE Flip-Flop associated with IBF) Controlled by bit set/reset of PC4. 5-123 SILICON GATE MOS 8255 CONTROL WORD OBF A pC 200 ACKA 1 = INPUT 0= OUTPUT r--l PORTB 1 = INPUT 0= OUTPUT IN;E L __ I J PC4 . STBA PCs GROUP B MODE 0= MODE 0 1 = MODE 1 AD Mode 2 Control Word PC200 Mode 2 \'----" INTR 1 IBF DATA BUS (BETWEEN I/O CHIP AND I/O DEVICE) - - - - - - IBFA WR - DATA I/O DEVICE -+- Mode 2 (Bi-directional) Timing 5-124 I/O CHIP DATA I/O CHIP -+ I/O DEVICE . 3 I / • I/O SILICON GATE MOS 8255 MODE 2 AND MODE 0 (OUTPUT) MODE 2 AND MODE 0 (INPUT) PC3 INTRA PC3 PA7 -PAO ~ PC 6 CONTROL WORD PA7 -PAo OBFA . P~ ACKA CONTROL WORD PC4 STBA PC5 IBFA . ACKA PC4 . STBA I/O PC2.() AD IBFA PC5 PC2.() 1 = INPUT 0= OUTPUT 3 PC2.() OBFA PC6 0 7 0 6 0 5 0 4 0 3 O2 0, DO 0 7 0 6 05 04 03 O2 0, DO PC 2.() 1 = INPUT O=OUTPUT INTRA . 3 I I I/O " RO 8 PB 7 -PBO P~-PBO WR WR MODE 2 AND MODE 1 (OUTPUT) MODE 2 AND MODE 1 (INPUT) PC3 PC3 A ~ A. PA77 PAo ( PA7 -PAo ~ 8 ~ ° 2 PC 7 CONTROLWOR PC6 0, DO 0 ° 2 PC6 0, DO 1 PC4 PC4 PCs PC s t-... PB7 -PBO 8 A ) PB7 -PBO PC2 RO PC, WR PCO y 'f PC7 CONTROLWOR -". 8 PC2 ACK B RO WR Mode 2 Combinations 5-125 .. PC, PCO K ....., . 8 I SILICON GATE MOS 8255 MODE DEFINITION SUMMARY TABLE PAO PA1 PA2 PA3 PA4 PAS PAe PA7 IN IN IN IN IN IN IN IN MODE 0 OUT OUT OUT OUT OUT OUT OUT OUT OUT PBO P81 PB2 PB3 PB4 PB5 PBe PB7 IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT PCO PC, PC2 PC3 PC4 PCS PC6 PC7 IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT INTRB IBFB STBB INTRA STBA IBFA I/O I/O INTRB OBFB ACKB INTRA I/O I/O ACKA OBFA IN IN IN IN IN IN IN IN IN MODE 1 OUT OUT OUT OUT OUT OUT OUT OUT OUT IN Special Mode Combination Considerations There are several combinations of modes when not all of the bits in Port C are used for control or status. The remaining bits can be used as follows: If Programmed as Inputs All input lines can be accessed during a normal Port C read. MODE 2 GROUP A ONLY •... ... ~ ... •... • ~ • ~ ... ~ ----- MODE 0 ----- OR MODE ONLY allows the programmer to test or verify the "status" of each peripheral device and change the program flow accordingly.. There is no special instruction to read the status information from Port C. A normal read operation of Port C is executed to perform this function. INPUT CONFIGURATION Os Bits in Clower (PC3-PCO) can be accessed using the bit set/reset function or accessed as a threesome by writing into Port C. 03 Do I i GROUP A GROUPS OUTPUT CONFIGURATION 07 Source Current Capability on Port B and Port C 06 Os 04 i GROUP A 03 O2 01 Do i GROUPB Mode 1 Status Word Format Reading Port C Status In Mode 0, Port C transfers data to or from the peripheral device. When the 8255 is programmed to function in Modes 1 or 2, Port C generates or accepts "hand-shaking" signals with the peripheral device. Reading the contents of Port C 1 I/O I/O I/O INTRA STBA 'IBFA ACKA OBFA If Programmed as Outputs Bits in C upper (PC7-PC4) must be individually accessed using the bit set/reset function. Any set of eight output buffers, selected randomly from Ports Band C can source lmA at 1.5 volts. This feature allows the 8255 to directly drive Darlington type drivers and high-voltage 'displays that require such source current. • • ~ i GROUP A i GROUP B (DEFINED BY MODE 0 OR MODE 1 SELECTION) Mode 2 Status Word Format 5·126 SILICON GATE MOS 8255 INTERRUPT REQUE STi APPLICATIONS OF THE 8255 PC 3 The 8255 is a very powerful tool for interfacing peripheral equipment to the 8080 microcomputer system. It represents the optimum use of available pins and is flexible enough to interface almost any I/O device without the need for additional external logic. - MODE 1 _ (INPUT) Each peripheral device in a Microcomputer system usually has a "service routine" associated with it. The routine manages the software interface between the device and the CPU. The functional definition of the 8255 is programmed by the I/O service routine and becomes an extension of the systems software. By examining the I/O devices interface characteristics for both data transfer and tim ing, and matching this information to the examples and tables in the Detailed Operational Description, a control word can easily be developed to initialize the 8255 to exactly "fit" the application. Here are a few examples of typical applications of the 8255. PA, Ro R, PAo 8255 PA 2 R2 PA 3 R3 PA4 R4 PAs PA6 Rs SHIFT PA7 CONTROL PC4 STROBE PCs ACK FULLY DECODED KEYBOARD ~ - MODE 1 _ (OUTPUT) INTERRUPT REQUEST PB o PB, Bo B, PB 2 B2 PB 3 B3 PB4 B4 PBs BURROUGHS SELF·SCAN DISPLAY PB 6 Bs BACKSPACE PB7 CLEAR PC, DATA READY PC 2 ACK PC 6 BLANKING CANCEL WORD PC o L.fC 7 UPT~ INTERR REQUEST HIGH-SPEED PRINTER Keyboard and Display Interface MODEl (OUTPUT) STi INTERRUPT REQUE HAMMER RELAYS DATA READY PC 3 ACK PAPER FEED FORWARD/REV 8255 MODE 1 (INPUT) - PAo Ro PA, R, PA2 R2 PA3 R3 PA4 R4 FULLY DECODED KEYBOARD PAs Rs PA6 SHIFT PA7 CONTROL RIBBON PC 4 STROBE CARRIAGE SEN. PC s ACKNOWLEDGE PC 6 BUSY LT PC 7 TEST LT DATA READY 8255 ACK MODEl (OUTPUT) PAPER FEED I FORWARD/REV PC, DATA READY PC 2 ACK f-------_-INTERRUPT REQUEST CONTROL LOGIC AND DRIVERS PB o .... PB, .... PB 2 MODE 0 (INPUT) - Printer Interface PB3 .... PB 4 -- ----- '0 TERMINAL ADDRESS ~ 't> "0 .... --"", PBs PB 6 .... PB 7 .... -- -~ Keyboard and Terminal Address Interface 5-127 SILICON GATE MOS 8255 INTERRUPT REQUE STi IP~ PAl I LSB r-- PC3 PA2 JPA PA3 PBO Do PB, 0, PB 2 O2 03 PB3 4 MODE 0 (OUTPUT) PAS ; PA PB4 PBs f-----------.. 12-BIT D-A CONVERTER (DAC) 6 PA7 PC4 PCS ---. ANALOG OUTPUT ,PC O BIT 06 PC4 PCS ACK (IN) PC7 _Pe 6 PC2 SAMPLE EN PC 3 STB PBO LSB DATA STB DATA READY ACK (OUT) 8255 OUTPUT EN PC2 TRACK "0" SENSOR PCo SYNC READY PC, INDEX PAO ENGAGE HEAD I SET/RESETl DS 07 STB DATA PC, ,...- r- 8-BIT A-D CONVERTER (ADC) PB, PB2 ..-- ANALOG INPUT PAl FORWARD/REV. P~ READ ENABLE PB4 MODE 0 _ P~ PA4 (OUTPUT) PBS PAs ENABLE CRC PB6 PAG TEST PB 3 MODE 0 (INPUT) P~ MSB _PA 7 Digital to Analog, Analog to Digital i WRITE ENABLE DISC SELECT BUSY LT Basic Floppy Disc Interface INTERRUPT INTERRUPT REQUEST REQUEST ...-------------.--. I PC3 ""-PAo ~------t~. Ro PAl R, CRT CONTROLLER PAo ....- - - - - 1 RO PAl R, PA 2 R2 R3 • CHARACTER GEN. PA 2 R2 • REFRESH BUFFER PA 3 R3 PA4 R4 • CURSOR CONTROL PA4 R4 PAs RS SHIFT CONTROL PAs PAG PA7 Rs RG PA 3 MODE 1 (OUTPUT) - PA6 PA 7 PC 7 8255 I-------t~. MODE 1 (INPUT) - DATA READY PC 6 ACK PCS BLANKED PC BLACK/WHITE 4 PC3 L.- PCG COLUMN STB CURSOR HN STB PB O I--------t~. l PB, PB2 PB3 PB4 PBs PB6 .....----_.. ,-P~ STOP/GO .... ... MACHINE TOOL PCo MODE 0 (INPUT) 2 PCO R7 8255 L.- PC, 8 LEVEL PAPER TAPE READER PC4 ....- - - -.... STB PCs ACK - PC I--------li~. ROW STB MODE 0 _ (OUTPUT) FLOPPY DISK CONTROLLER AND DRIVE 04 PB7 MSB '- PC7 . MODE 2- PB6 PC6 8255 . START/STOP PC .....- - - - - 1 LIMIT SENSOR (H/V) 1 { PC2 ....-----IOUTOF FLUID I PB CHANGE TOOL PB2 UP/DOWN PB 3 HOR. STEP STROBE I PB: 1--------t~.LEFT/RIGHT ! i CURSOR/ROW/COLUMN :-- ADDRESS ! H& V 1 1 MODE 0 J (OUTPUT) lPB4 I J .._------------~ ... VERT. STEP STROBE PBs SLEW/STEP PBG FLUID ENABLE . . . .__.. PB7 1._-----------_.. EMERGENCY STOP Machine Tool Controller Interface Basic CRT Controller Interface 5-128 SILICON GATE MOS 8255 I SYSTEM BUS (0, A, AND C) r--- ~---- I- - - - - , ,-- ~v ~V "",,-/7 "v'7 8080 CPU MEMORY ROM AND RAM 8255 8255 MODE 2 ..t. A t- - - - - , 1-- --.--- I I I 8255 MODE 2 ~~ ~ MASTER CPU MASTER I/O L 8080 CPU 8080 CPU MEMORY MEMORY I/O I/O J Distributed I ntell igence Multi-Processor Interface 5-129 I I I I SILICON GATE MOS 8255 D.C. CHARACTERISTICS TA = o°c to 70°C; Vee = +5V ±5%; vss = OV Typ. Symbol Parameter Vil Input Low Voltage V IH Input High Voltage Val Output Low Voltage VOH Output High Voltage IOH[1] Darlington Drive Current 2.0 rnA Ice Power Supply Current 40 rnA Min. Max. Unit .8 V Test Conditions V 2.0 .4 2.4 V IOl = 1.6mA V IOH = -50JlA (-1 OOJlA for D.B. Port) VOH=1.5V, REXT=390n NOTE: 1. Available on 8 pins only. A.C. CHARACTERISTICS TA = o°c to 70°C; Vee = +5V ±6%; Vss = OV Min. Typ. Max. Unit Symbol Parameter twP Pulse Width of WR tow Time D.B. Stable Before WR 10 ns two Time D.B. Stable After WR 65 ns tAW Time Address Stable Before WR 20 ns tWA Time Address Stable After WR 35 ns tew Time CS Stable Before WR 20 ns twe Time CS Stable After WR 35 ns tWB Delay From WR To Output tRP Pulse Width of RD tlR 430 500 ns ns 430 ns RD Set-Up Time 50 ns tHR Input Hold Time 50 ns tRO Delay From RD = 0 To System Bus 350 ns too Delay From RD = 1 To System Bus 150 ns tAR Time Address Stable Before RD 50 ns teR Time CS Stable Before RD 50 ns tAK Width Of ACK Pulse 500 ns tST Width Of STB Pulse 350 ns tps Set-Up Time For Peripheral 150 ns tpH Hold Time For Peripheral 150 ns tRA Hold Time for A1, Ao After RD = 1 379 ns 'IRe Hold Time For CS After RD = 1 - ns 5 tAD Time From ACK = 0 To Output(Mode 2) 500 tKO Time From ACK = 1 To Output Floating 300 ns two Time From WR = 1 To OBF = 0 300 ns tAO Time From ACK = 0 To OBF = 1 500 ns tSI Time From STB = 0 To IBF 600 ns tRI Time From RD = 1 To IBF = 0 300 ns - 5-130 ns Test Condition SILICON GATE MOS 8255 .. ~ t RP ~ ~ 7 I[ ~tHR-----" .--t'R---' K >: INPUT ~tRA--" tAR :~ ~~ A1,AO t RC ~tCR----' \~ JV :0- ~ ----- -- -- ---- .. t RD .. too Mode 0 (Basic Input) ~ .. twp { ,-- f-- 7 \ ~twD--' ~tDW~ )( tAW A1,AO twA )( .. cs K .. t cw JK .. twc \\ OUTPUT .. ~ J )( . twB Mode 0 (Basic Output) 5-131 -------. r-- SILICON GATE MOS 8255 IBF ~tRI INTR INPUT FROM PERIPHERAL _ I . . . - - - - - tps - - - - - . · Mode 1 (Strobed Input) INTR OUTPUT Mode 1 (Strobed Output) 5-132 SILICON GATE MOS 8255 . WR tAO OBF INTR ACK STB IBF PERIPHERAL _ BUS DATA FROM PERIPHERAL TO 8255 DATA FROM 8255 TO 8080 Mode 2 (Bi-directional) 5-133 Silicon Gate MOS 8251 PROGRAMMABLE COMMUNICATION INTERFACE .. Synchronous and Asynchronous Operation • Synchronous: 5-8 Bit Characters Internal or External Character Synchronization Automatic Sy.nc Insertion • Asynchronous: 5-8 Bit Characters Clock Rate -1,16 or 64 Times Baud Rate Break Character Generation 1, 1 1h, or 2 Stop Bits False Start Bit Detection • Baud Rate - DC to 56 k Baud ( Sync Mode) DC t09.6k Baud (Async Mode) • Full Duplex, Double Buffered, Transmitter and Receiver • Error Detection - Parity, Overrun, and Framing • Fully Compatible with 8080 CPU • 28-Pin DIP Package • All Inputs and Outputs Are TTL Compatible • Single 5 Volt Supply • Single TTL Clock The 8251 is a Universal Synchronous/Asynchronous Receiver / Transmitter (USA RT) Chip designed for data communications in microcomputer systems. The USART is used as a peripheral device and is programmed by the CPU to operate using virtually any serial data transmission technique presently in use (including IBM Bi-Sync). The USART accepts data characters from the CPU in parallel format and then converts them into a continuous serial data stream for transmission. Simultaneously it can receive serial data streams and convert them into. parallel data characters for the CPU. The USART will signal the CPU whenever it can accept a new character for transmission or whenever it has received a character for the CPU. The CPU can read the complete status of the USART at any time. These include data transmission errors and control signals such as SYNDET, TxEMPT. The chip is constructed using N-channel silicon gate technology. PIN CONFIGURATION O2 03 01 Do RxD Vee GND RxC 04 DTR 05 RTS 06 DSR 07 RESET fXC CLK WR TxD CS C/O RD RxRDY BLOCK DIAGRAM TxRDY TxEMPTY TxE CTS SYNDET TxRDY Pin Function Pin Name Pin Function 07-0 0 C/O Data Bus (8 bits) Control or Data is to be Written or Read Read Data Command Write Data or Control Command Chip Enable Clock Pulse (TTL) Reset Transmitter Clock Transmitter Data Receiver Clock Receiver Data Receiver Ready (has character for 8080) Transmitter Ready (ready for char. from 8080) DSR DTR SYNDET RTS CTS TxE Data Set Ready Data Terminal Ready Sync Detect Request to Send Data Clear to Send Data Transmitter Empty +5 Volt Supply Ground CLK RESET TxC TxD RxC RxD RxRDY TxRDY TxD (p.... S) TRANSMIT CONTROL Pin Name AD WR Cs TRANSMIT BUFFER 0 7 -0 0 Vee GND RxD / INTERNAL DATA BUS 5-135 RxRDY RxC ..... SYNDET SILICON GATE MOS 8251 8251 BASIC FUNCTIONAL DESCRIPTION General C/D (Control/Data) The 8251 is a Universal Synchronous!Asynchronous Receiver/Transmitter designed specifically for the 8080 Microcomputer System. like other I!O devices in the 8080 Microcomputer System its functional configuration is programmed by the systems software for maximum flexibility. The 8251 can support virtually any serial data technique currently in use (including IBM "bi-sync"). This input, in conjunction with the WR and RD inputs informs the 8251 that the word on the Data Bus is either a data character, control word or status information. 1 = CONTROL 0 = DATA In a communication environment an interface device must convert parallel format system data into serial format for transmission and convert incoming serial format data into parallel system data for reception. The interface device must also delete or insert bits or characters that are functionally unique to the communication technique. In essence, the interface should appear "transparent" to the CPU, a simple input or output of byte-oriented system data. CS (Chip Select) A "low" on this input enables the 8251. No read ing or writing will occur unless the device is selected. Data Bus Buffer This 3-state, bi-directional,8-bit buffer is used to interface the 8251 to the 8080 system Data Bus. Data is transmitted or received by the buffer upon execution of INput or OUTput instructions of the 8080 CPU. Control words, Command words and Status information are also transferred through the Data Bus Buffer. ReadlWrite Control logic This functional block accepts inputs from the 8080 Control bus and generates control signals for overall device operation. It contains the Control Word Register and Command Word Register that store the various control formats for device functional definition. RESET (Reset) A "high" on this input forces the 8251 into an "Idie" mode. The device will remain at "Idle" until a new set of control words is written into the 8251 to program its functional definition. ClK (Clock) The ClK input is used to generate internal device timing and is normally connected to the Phase 2 (TTL) output of the 8224 Clock Generator. No external inputs or outputs are referenced to ClK but the frequency of ClK must be greater than 30 times the Receiver or Transmitter clock inputs for synchronous mode (4.5 times for asynchronous mode). c/o RD WR CS o o 0 1 0 1 X 1 0 1 0 X 0 0 0 0 1 1 1 X WR (Write) A "Iow" on this input informs the 8251 that the CPU is outputting data or control words, in essence, the CPU is writi ng out to the 8251. RD (Read) A "Iow" on this input informs the 8251 that the CPU is inputting data or status information, in essence, the CPU is reading from the 8251. 5-136 8251 => DATA BUS DATA BUS => 8251 STATUS=> DATA BUS DATA BUS=> CONTROL DATA BUS=> 3-STATE SILICON GATE MOS 8251 Modem Control TxE (Transmitter Empty) The 8251 has a set of control inputs and outputs that can be used to simplify the interface to almost any Modem. The modem control signals are general purpose in nature and can be used for functions other than Modem control, if necessary. When the 8251 has no characters to transm it, the T x E output will go "high". It resets automatically upon receiving a character from the CPU. TxE can be used to indicate the end of a transmission mode, so that the CPU "knows" when to "turn the line around" in the half-duplexed operational mode. DSR (Data Set Ready) In SYNChronous mode, a "high" on this output indicates that a character has not been loaded and the SYNC character or characters are about to be transmitted automatically as "fillers". The DSR input signal is general purpose in nature. Its condition can be tested by the CPU using a Status Read operation. The DSR input is normally used to test Modem conditions such as Data Set Ready. DTR (Data Termin·al Ready) The DTR output signal is general purpose in nature. It can be set "low" by programming the appropriate bit in the Command Instruction word. The DTR output signal is normally used for Modem control such as Data Terminal Ready or Rate Select. RTS (Request to Send) The RTS output signal is general purpose in nature. It can be set "low" by programr:ning the appropriate bit in the Command Instruction word. The RTS output signal is normally used for Modem control such as Request to Send. CTS (Clear to Send) A "low" on this input enables the 8251 to transmit data (serial) if the Tx EN bit in the Command byte is set to a "one." Transmitter Buffer The Transmitter Buffer accepts parallel data from the Data Bus Buffer, converts it to a serial bit stream, inserts the appropriate characters or bits (based on the 'communication technique) and outputs a composite serial stream of data on the TxD output pin. Transmitter Control The Transmitter Control manages all activities associated with the transmission of serial data. It accepts and issues signals both externally and internally to accomplish this function. TxC (Transmitter Clock) The Transmitter Clock controls the rate at which the character is to be transmitted. In the Synchronous transmission mode, the frequency of TxC is equal to the actual Baud Rate (1 X). In Asynchronous transmission mode, the frequency of TxC is a multiple of the actual Baud Rate. A portion of the mode instruction selects the value of the multiplier; it can be 1x, 16x or 64x the Baud Rate. For Example: If Baud Rate equals 110 Baud, TxC equals 110 Hz (1x) TxC equals 1.76 kHz (16x) TxC equals 7.04 kHz (64x). If Baud Rate equals 9600 Baud, TxC equals 614.4 kHz (64x). TxRDY (Transmitter Ready) This output signals the CPU that the transmitter is ready to accept a data character~ It can be used as an interrupt to the system or for the Polled operation the CPU can check TxRDY using a status read operation. TxRDY is automatically reset when a character is loaded from the CPU. The falling edge of TxC shifts the serial data out of the 8251. 5-137 SILICON GATE MOS 8251 Receiver Buffer The Receiver accepts serial data, converts this serial input to parallel format, checks for bits or characters that are unique to the communication technique and sends an "assembled" character to the CPU. Serial data is input to the RxD pin. When used as an input, (external SYNC detect mode), a positive going signal will cause the 8251 to start assembling data characters on the falling edge of the next RxC. Once in SYNC, the "high" input signal can be removed. The duration of the high signal should be at least equal to the period of RxC. Receiver Control This functional block manages all receiver-related activities. RxRDY (Receiver Ready) This output indicates that the 8251 contains a character that is ready to be input to the CPU. RxRDY can be connected to the interrupt structure of the CPU or for Polled operation the CPU can check the condition of RxRDY using a status read operation. RxRDY is automatically reset when the character is read by the CPU. RxC (Receiver Clock) The Receiver Clock controls the rate at which the character is to be received. In Synchronous Mode, the frequency of RxCisequal to the actual Baud Rate (1x). In Asynchronous Mode, the frequency of RxC is a multiple of the actual Baud Rate. A portion of the mode instruction selects the value of the multipl ier; it can be 1x, 16x or 64x the Baud Rate. For Example: If Baud Rate equals 300 Baud, RxC equals 300 Hz (1 x) RxC equals 4800 Hz (16x) RxC equals 19.2 kHz (64x). If Baud Rate equals 2400 Baud, RxC equals 2400 Hz (1 x) RxC equals 38.4 kHz (16x) RxC equals 153.6 kHz (64x). Data is sampled into the 8251 on the rising edge of RxC. NOTE: In most communications systems, the 8251 will be handling both the transmission and reception operations of a single link. Consequently, the Receive and Transmit Baud Rates will be the same. Both TxC and RxC will require identical frequencies for this operation and can be tied together and connected to a single frequency source (Baud Rate Generator) to simpl ify the interface. \ \ \ CONTROL BUS I/O R \ n I/OW RESET ( C/O \ cs ~7 0 7 -00 t'\ RD ( WR RESET 8251 8251 Interface to 8080 Standard System Bus 5-138 t/>2 (TTL) DATA BUS SYNDET (SYNC Detect) This pin is used in SYNChronous Mode only. It is used as either input or output, programmable through the Control Word. It is reset to "low" upon RESET. When used as an output (internal Sync mode), the SYNDET pin will go "high" to indicate that the 8251 has located the SYNC character in the Receive mode. If the 8251 is programmed to use double Sync characters (bi-sync), then SYNDET will go "high" in the middle of the last bit of the second Sync character. SYNDET is automatically reset upon a Status Read operation. \ ADDRESS BUS Ao ClK SILICON GATE MOS 8251 DETAILED OPERATION DESCRIPTION General The complete functional definition of the 8251 is programmed by the systems software. A set of control words must be sent out by the CPU to initialize the 8251 to support the desired communications format. These control words will program the: BAUD RATE, CHARACTER LENGTH, NUMBER OF STOP BITS, SYNCHRONOUS or ASYNCHRONOUS OPERATION, EVEN/ODD PARITY etc. In the Synchronous Mode, options are also provided to select either internal or external character synchronization. All control words written into the 8251 after the Mode Instruction will load the Command Instruction. Command Instructions can be written into the 8251 at any time in the data block during the operation of the 8251. To return to the Mode Instruction format a bit in the Command Instruction word can be set to initiate an internal Reset operation which automatically places the 8251 back into the Mode Instruction format. Command Instructions must follow the Mode Instructions or Sync characters. Once programmed~ the 8251 is ready to perform its communication functions. The TxRDY output is raised "high" to signal the CPU that the 8251 is ready to receive a character. This output (TxRDY) is reset automatically when the CPU wdtes a character into the 8251. On the other hand, the 8251 receives serial data from the MODEM or I/O device, upon receiving an entire character the RxRDY output is raised "high" to signal the CPU that the 8251 has a complete character ready for the CPU to fetch. Rx RDY is reset automatically upon the CPU read operation. MODE INSTRUCTION C/O:: 1 SYNC CHARACTER 1 C/o = 1 SYNC CHARACTER 2 C/D:: 1 COMMAND INSTRUCTION C/D:: 0 DATA C/o:: 1 COMMAND INSTRUCTION C/o:;;: 0 DATA C/O:::: 1 COMMAND INSTRUCTION } The 8251 cannot begin transmission until the TxEN (Transmitter Enable) bit is set in the Command Instruction and it has received a Clear To Send (CTS) input. The TxD output will be held in the marking state upon Reset. Programming the 8251 Prior to starting data transmission or reception, the 8251 must be loaded with a set of control words generated by the CPU. These control signals define the complete functional definition of the 8251 and must immediately follow a Reset operation (internal or external). C/O:: 1 SYNC MODE ONLY· ·The second SYNC character is skipped if MODE instruction has programmed the 8251 to single character Internal SYNC Mode. Both SYNC characters are skipped if MODE instruction has programmed the 8251 to ASYNC mode. Typical Data Block The control words are split into two formats: 1. Mode Instruction 2. Command Instruction Mode Instruction This format defines the general operational characteristics of the 8251. It must follow a Reset operation (internal or external). Once the Mode instruction has been written into the 8251 by the CPU, SYNC characters or Command instructions may be inserted. Command Instruction This format defines a status word that is used to control the actual operation of the 8251. Both the Mode and Command instructions must conform to a specified sequence for proper device operation. The Mode Instruction must be inserted immediately following a Reset operation, prior to using the 8251 for data communication. 5-139 SILICON GATE MOS 8251 Mode Instruction Definition The 8251 can be used for either Asynchronous or Synchronous data communication. To understand how the Mode Instruction defines the functional operation of the 8251 the designer can best view the device as two separate components sharing the same package. One Asynchronous the other Synchronous. The format definition can be changed lion the fly" but for explanation purposes the two formats will be isolated. I~ I I I I~ 81 EP PEN 1 L 1 1 B21 B1 I L BAUD RATE FACTOR 0 1 0 1 0 0 1 1 SYNC MODE (1X) (16X) (64X) CHARACTER LENGTH 0 Asynchronous Mode (Transmission) Whenever a data character is sent by the CPU the 8251 automatically adds a Start bit (low level) and the programmed number of Stop bits to each character. Also, an even or odd Parity bit is inserted prior to the Stop bit(s), as defined by the Mode Instruction. The character is then transmitted as a serial data stream on the TxD output. The serial data is shifted out on the falling edge of TxC at a rate equal to 1, 1/16, or 1/64 that of the TxC, as defined by the Mode Instruction. 8 REAK characters can be continuously sent to the TxD if commanded to do so. When no data characters have loaded into the 8251 the TxD output remains "high" (marking) unless a Break (continuously low) has been programmed. 1 0 1 0 0 1 5 6 BITS BITS BITS 1 7 8 BITS PARITY ENABLE 1 = ENABLE 0= DISABLE EVEN PARITY GENERATION/CHE CK 0=000 1 = EVEN NUMBER OF STOP BITS 0 1 0 0 0 1 1 1 INVALID 1 BIT 1% BITS 2 BITS Mode Instruction Format, Asynchronous Mode Asynchronous Mode (Receive) The RxD line is normally high. A falling edge on this line triggers the beginning of a START bit. The validity of this START bit is checked by again strobing this bit at its nominal center. If a low is detected again, it is a valid START bit, and the bit counter will start counting. The bit counter locates the center of the data bits, the parity bit (if it exists) and the stop bits. If parity error occurs, the parity error flag is set. Data and parity bits are sampled on the RxD pin with the rising edge of RxC. If a low level is detected as the STOP bit, the Framing Error flag will be set. The STOP bit signals the end of a character. This character is then loaded into the parallel I/O buffer of the 8251. The RxRDY pin is raised to signal the CPU that a character is ready to be fetched. If a previous character has not been fetched by the CPU, the present character replaces it in the I/O buffer, and the OVERRUN flag is raised (thus the previous character is lost). All of the error flags can be reset by a command instruction. The occurrence of any of these errors will not stop the operation of the 8251. TRANSMITTER OUTPUT TxD ST~ MARKING BITS L RECEIVER INPUT START BIT RxD ST6;"l BrTS DATA: B\-IT_S_....-._ _... TRANSMISSION FORMAT CPU BYTE (5·8 BITS/CHAR) DATA C~~RACTER ASSEMBLED SERIAL DATA OUTPUT (TxD) DATA CHARACTER STO[] BITS ......- - - . . a - - - . . . & - - - - f RECEIVE FORMAT SERIAL DATA INPUT (RxD) DATA CHARACTER STOtJ BITS f----.&.---.Iooo----t CPU BYTE (5·8 BITS/CHAR)* DATA CH:;ACTER *NOTE: IF CHARACTER LENGTH IS DEFINED AS 5,6 OR 7 BITS THE UNUSED BITS ARE SET TO "ZERO". Asynchronous Mode 5-140 L SILICON GATE MOS 8251 Synchronous Mode (Transmission) The TxD output is continuously high until the CPU sends its first character to the 8251 which usually is a SYNC character. When the CTS line goes low, the first character is serially transmitted out. All characters are shifted out on the falling edge of TxC. Data is shifted out at the same rate as the TxC. CHARACTER LENGTH Once transmission has started, the data stream at TxD output must continue at the TxC rate. If the CPU does not provide the 8251 with a character before the 8251 becomes empty, the SYNC characters (or character if in single SYNC word mode) will be automatically inserted in the TxD data stream. In this case, the TxEMPTY pin is raised high to signal that the 8251 is empty and SYNC characters are being sent out. The TxEMPTY pin is internally reset by the next character bei ng written into the 8251. L.....- -.. L.....- .. o 1 0 o 0 1 1 5 BITS 6 BITS 7 BITS 8 BITS PARITY ENABLE (1 = ENABLE) (0 = DISABLE) EVEN PARITY GENERATION/CHECK 1 c EVEN 0=000 ' " - - - - - - - - - - - . . EXTERNAL SYNC DETECT 1 = SYNDET IS AN INPUT = SYNDET IS AN OUTPUT o Synchronous Mode (Receive) " - - - - - - - - - - - - -.... SINGLE CHARACTER SYNC 1 = SINGLE SYNC CHARACTER 0= DOUBLE SYNC CHARACTER In this mode, character synchronization can be internally or externally achieved. If the internal SYNC mode has been programmed, the receiver starts in a HUNT mode. Data on the Rx.D pin is then sampled in on the rising edge of RxC. The content of the Rx buffer is continuously compared with the first SYNC character until a match occurs. If the 8251 has been programmed for two SYNC characters, the subsequent received character is also compared; when both SYNC characters have been detected, the USART ends the HUNT mode and is in character synchronization. The SYNDET pin is then set high, and is reset automatically by a STATUS READ. Mode Instruction Format, Synchronous Mode CPU BYTES (5-8 BITS/CHAR) DATA In the external SYNC mode, synchronization is achieved by applying a high level on the SYNDET pin. The high level can be removed after one RxC cycle. C~~RACTERS ASSEMBLED SERIAL DATA OUTPUT (TxD) DATACHA~~AC_T_E_RS Parity error and overrun error are both checked in the same way as in the Asynchronous Rx mode. ~ RECEIVE FORMAT The CPU can command the receiver to enter the HUNT mode if synchronization is lost. SERIAL DATA INPUT (RxD) DATACHAR~~C_TE_R_S CPU BYTES (5-8 BITS/CHAR) ~f DATA CH:~ACTERS Synchronous Mode, Transmission Format 5-141 ___ SILICON GATE MOS 8251 COMMAND INSTRUCTION DEFINITION STATUS READ DEFINITION Once the functional definition of the 8251 has been programmed by the Mode Instruction and the Sync Characters are loaded (if in· Sync Mode) then the device is ready to be used for data communication. The Command Instruction controls the actual operation of the selected format. Functions such as: Enable Transmit/Receive, Error Reset and Modem Controls are provided by the Command Instruction. In data communication systems it is often necessary to examine the "status" of the active device to ascertain if errors have occu rred or other cond itions that requ ire the processor's attention. The 8251 has facilities that allow the programmer to "read" the status of the device at any time du ring the fu nctional operation. Once the Mode Instruction has been written into the 8251 and Sync characters inserted, if necessary, then all further "control writes" (C/O = 1) will load the Command Instruction. A Reset operation (internal or external) will return the 8251 to the Mode Instruction Format. A normal "read" command is issued by the CPU with the C/O input at one to accomplish this function. Some of the bits in the Status Read Format have identical meanings to external output pins so that the 8251 can be used in a completely Polled environment or in an interrupt driven environment. TRANSMIT ENABLE 1 = enable 0= disable ~ '------~ SAME DEFINITIONS AS I/O PINS PARITY ERROR The PE flag is set when a parity error is detected. It is reset by the ER bit of the Command Instruction. PE does not inhibit operation of the 8251. DATA TERMINAL READY "high" will force DTR output to zero RECEIVE ENABLE 1 = enable 0= disable OVERRUN ERROR The OE flag is set when the CPU does not read a character before the next one becomes available. It is reset by the ER bit of the Command Instruction. OE does not inhibit operation of the 8251 ; however, the previously overrun character is lost. SEND BREAK CHARACTER 1 = forces TxD "Iow" o = normal operation ERROR RESET - - - - - - - - - - - . . 1 = reset all error flags PE, OE, FE L.-- --.. FRAMING ERROR (Async only) The FE flag is set when a valid Stop bit is not detected at the end of every character. It is reset by the ER bit of the Command Instruction. FE does not inhibit the operation of the 8251. REQUEST TO SEND "high" will force RTS output to zero L.-- ....... INTERNAL RESET "high" returns 8251 to Mode Instruction Format Status Read Format L.-- --.. ENTER HUNT MODE 1 = enable search for Sync Characters Command Instruction Format 5-142 SILICON GATE MOS 8251 APPLICATIONS OF THE 8251 ADDRESS BUS ADDRESS BUS CONTROL BUS CONTROL BUS DATA BUS DATA BUS r----' I EIA TO TTL :. CONVERT I IL ____ (OPT) J 8251 BAUD RATE GENERATOR TxC QJ) :: ASYNC MODEM CRT TERMINAL PHONE LINE INTER· FACE 8251 Asynchronous Serial Interface to CRT Terminal, DC-9600 Baud TELEPHONE LINE Asynchronous Interface to Telephone Lines L.- ADDRESS BUS ..... SYNCHRONOUS TERMINAL OR PERIPHERAL DEVICE SYNC MODEM SYNDET 1 - - - - - + 1 Synchronous Interface to Terminal or Peripheral Device PHONE LINE INTER· FACE TELEPHONE LINE Synchronous Interface to Telephone Lines 5-143 SILICON GATE MOS 8251 D.C. Characteristics: Symbol Parameter Min. Typ. Max. Unit V,L Input Low Voltage Vss-·5 0.8 V VIH Input High Voltage 2.0 Vee V VOL Output Low Voltage 0.45 V VOH Output High Voltage IOL Data Bus Leakage 50 IJ.A ILl Input Load Current 10 IlA Icc Power Supply Current 2.2 V 45 80 Typ. Max. Unit Test Conditions = 1.6mA IOH = -1001lA ( DB o-7) IOH = -1001lA (Others) IOl VOUT = 4.5V @5.5V Capacitance TA = 25°C; Vee = vss = OV Symbol Parameter Min. Test Conditions CtN Input Capacitance 10 pF fc = 1MHz CliO I/O Capacitance 20 pF Unmeasured pins returned to Vss. 5-144 SILICON GATE MOS 8251 A.C. Characteristics: TA = o°c to 70°C; VCC = 5.0V ±5%; Vss = OV Parameter Symbol Min. Typ. Max. Unit tCY Clock Period .420 1.35 JlS t ~~MORIES Ao All - - - - . - . . - t - - I A, °4 A3 _ A2 CS 17 CS'8 CS'9 8205 CS20 e; e; E3 23 I/O Port Decoder 24K Memory Interface 5-149 CS 2, CS22 CS23 CHIP SELECTS SCHOTTKY BIPOLAR 8205 Logic Element Example Probably the most overlooked application of the 8205 is that of a general purpose logic element. Using the lion-chip" enabl ing gate, the 8205 can be configu red to gate its decoded outputs with system timing signals and generate strobes that can be directly connected to latches, flip-flops and one-shots that are used throughout the system. and T2 decoded strobes can connect directly to devices like 8212s for latching the address information. The other decoded strobes can be used to generate signals to control the system data bus, memory timing functions and interrupt structure. RESET is connected to the enable gate so that strobes are not generated during system reset, eliminating accidental loading. An excellent example of such an appl ication is the "state decoder" in an 8008 CPU based system. The 8008 CPU issues three bits of information (SO, S1, S2) that indicate the nature of the data on the Data Bus during each machine state. Decoding of these signals is vital to generate strobes that can load the address latches, control bus discipline and general machine functions. The power of such a circuit becomes evident when a single decoded strobe is logically broken down. Consider T1 output, the boolean equation for it would be: Tl = (SO·S1·S2)"(SYNC·Phase 2·Reset) A six input NAND gate plus a few inverters would be needed to implement this function. The seven remaining outputs would need a similar circuit to duplicate their function, obviously a substantial savings in components can be achieved when using such a technique. In the figure below a circuit is shown using the 8205 as the "state decoder" for an 8008 CPU that not only decodes the SO, 51, 52 outputs but gates these signals with the clock (phase 2) and the SYNC output of the 8008 CPU. The T1 S o , 13 S 12 S 11 8008 CPU 2 2 I 3 I-----i+----+-I I '----++-------tM---~1 T3 820~ I I 6 \lJ I I 2~ I I STOP I I I I I I I I I I 1 I 1 i I I I I 4" ----.....,~r----+I---+I--t-I -""'"""I""'"--It- OUTPUTS FROM 8205 o------~\lJ I ro----++-----:I--+---..-I I I I l------------,.wr----+\--:....1---+-1 3" ---------------,JJ,.--+-I----.....1 7----------------,1 5 SYSTEM RESET State Control Coding So S, S2 STATE 0 0 0 1 1 0 0 0 0 0 0 T1 T11 T2 WAIT a 1 1 1 1 a 1 1 0 1 1 1 1 T3 STOP T4 T5 5-150 w--r'ill I SCHOTTKY BIPOLAR 8205 ABSOLUTE MAXIMUM RATINGS· Temperatu re Under Bias: *COMMENT -65°C to +125° C -65°C to +75°C Ceram ic Plastic Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. -65°C to +1600 C Storage Temperature -0.5 to +7 Volts All Output or Supply Voltages -1.0 to +5.5 Volts All Input Voltages 125 rnA Output Cu rrents D.C. CHARACTERISTICS TA = OOC to +75°C, Vee = 5.0V ±5% 8205 SYMBOL LIMIT PARAMETER INPUT LOAD CURRENT IF UNIT MAX. MIN. TEST CONDITIONS -0.25 rnA Vee INPUT LEAKAGE CURRENT 10 ~A Vee ' V e INPUT FORWARD CLAMP VOLTAGE -1.0 V Vee VOL VOH OUTPUT "LOW" VOLTAGE V Vee V Vee V 1l INPUT "LOW" VOLTAGE V'H INPUT "HIGH" VOLTAGE se ' OUTPUT HIGH SHORT CIRCUIT CURRENT Vox OUTPUT "LOW" VOLTAGE @ HIGH CURRENT 'ee POWER SUPPLY CURRENT R 0.45 OUTPUT HIGH VOLTAGE 2.4 0.85 2.0 -40 -120 0.8 70 = 5.25V, V F = 0.45V = 5.25V, V R = 5.25V = 4.75V, Ie = -5.0 rnA = 4.75V, IOl = 10.0 rnA V Vee V Vee rnA Vee = 4.75V, IOH = -1.5 rnA = 5.0V = 5.0V = 5.0V, VOUT = OV V Vee = 5.0V, rnA Vee = 5.25V lox = 40 rnA TYPICAL CHARACTERISTICS OUTPUT CURRENT VS. OUTPUT IILOW" VOLTAGE OUTPUT CURRENT VS. OUTPUT "HIGH" VOLTAGE o 100 --.....,....----~.....--....------- I I I ~ I( --- vee = s.ov « .§. ...z U.l 80 t---t-----t---+---+---f~oII--_+__-f---+-~ ~ -20 ::> ... 40 ::> t----+--f---+--+-""""*"if---+---+---+----+-----4 ...::> ~ -30 ~ ... ~ 4- ~ 20 t---t---+---JT-~----lf---+---+-----+----+-----t 0I000o-...............--1000..........----'-''''''---..1--'''''----1..----1 .2 .4 .6 .8 1.0 o OUTPUT "LOW" VOLTAGE (V) a , -40 I A -50 o 1.0 I I I ......... TA ::;: 25°C " TA ::;: 75°C - ~ I w ~ ... ::{ 3.0 ..... TA - OOC \~ ...J a > ... ...::::> ~ TA = 2SoC- 2.0 TA ::;: 75OC_ 4- a f\< ,\\ rl- -..\~ ~\ \ \ 1.0 \. o 3.0 4.0 OUTPUT "HIGH" VOLTAGE (V) 5-151 5.0 - 4.0 1\ 2.0 - Vee::;: 5.0V I I ~ (.) nrt ~ ~, w a: a: a: a: o TA ::;: O°C- < .§. 60 IfIt I -10 t---+--+---+---+-----Ir----+---+---:.~--#-----t DATA TRANSFER FUNCTION 5.0 o .2 .4 .6 .8 1.0 1\ , "-~ 1.2 1.4 1.6 1.8 2.0 INPUT VOLTAGE (V) SCHOTTKY BIPOLAR 8205 8205 SWITCHING CHARACTERISTICS CONDITIONS OF TEST: Input pulse amplitudes: TEST LOAD: 390n 2.5V Input rise and fall times: 5 nsec between 1V and 2V Measurements are made at 1.5V 2K All Transistors 2N2369 or Equivalent. TEST WAVEFORMS ADDRESS OR ENABLE INPUT PULSE ---..1'~1 _ _ _ _ ___t+_-_'.... t++ 1'---___ =b~:.:~-I.-,..-------- I-: I eL = 30 pF , , , , OUTPUT = aoc to +75°C, Vee = 5.0V ±5% unless otherwise specified. A.C. CHARACTERISTICS TA PARAMETER SYMBOL MAX. LIMIT UNIT 18 ns 18 ns 18 ns 18 ns t++ ADDRESS OR ENABLE TO OUTPUT DELAY t_+ t+_ t -- C,N (1; INPUT CAPACITANCE P8205 C8205 4(typ.) 5(typ.) pF pF TEST CONDITIONS f =1 MHz, VSIAS Vee = = 2.0V, T A OV :: 250 e 1. This parameter is penodically sampled and is not 100% tested. TYPICAL CHARACTERISTICS ADDRESS OR ENABLE TO OUTPUT DELAY VS. AMBIENT TEMPERATURE ADDRESS OR ENABLE TO OUTPUT DELAY VS. LOAD CAPACITANCE 20 ,....-..-------~--........------ 20 , . . . . - . . - - - . . . , . . . . - - - - - , - - - - - - Vee = 5.0V TA = 25"C ~ _ Vee = 5.0V Cl = 30 pf o 15 ~----+ ~ C m- ~..:. ~~ ~ g o I~~ ~50 0 « 15 t - - - - - - + W -III 1 - ~ ----~I--------I t~_..:.~:.. ~~ t_+ 1 _ I w..J ~~ 10 t - - - - - - + - - - + - - - - + : : : - . . . - = : ; ; - - - 4 \ ... ", ~5 « 0° 5 1------1----+-----+-----1 o l - . -_ _..L..-_ _..1--_ _ .......I...-_ _ o 50 100 10 ~5 w CL 150 51------+------+------1 OL..-----....L.....------'------- ~ o 200 25 SO AMBIENT TEMPERATURE (OC) LOAD CAPACITANCE (pf) 5-152 75 Schottky Bipolar 8214 PRIORITY INTERRUPT CONTROL UNIT • Eight Priority Levels • Current Status Register • Priority Comparator • Fully Expandable • High Performance (50ns) • 24-Pin Dual In-Line Package The 8214 is an eight level priority interrupt control unit designed to simplify interrupt driven microcomputer systems. The PICU can accept eight requesting levels; determine the highest priority, compare this priority to a software controlled current status register and issue an interrupt to the system along with vector information to identify the service routine. The 8214 is fully expandable by the use of open collector interrupt output and vector information. Control signals are also provided to simplify this function. The PICU is designed to support a wide variety of vectored interrupt structures and reduce package count in interrupt driven microcomputer systems. LOGIC DIAGRAM PIN CONFIGURATION [TI> Bo ElR 24 Vee [}DETlG-- l!P REQUEST ACTIVITY B, 2 23 ECS B2 3 22 R7 SGS 4 21 R6 INT 5 20 Rs elK 6 19 R4 18 R3 17 R2 8214 INTE Ao 8 A, 9 16 R, A2 10 15 Ro ElR 11 14 ENLG GND 12 13 ETLG ~ R, ~ [1D ~ ~ ~ R; IT> ED 60 (OPEN COllECTOR) ~ [D ITI> R; ~ ~ ~ ~ ~ A2 }A A>B S; ED SGS ~ ECS []> }B ~ [I> IT> PIN NAMES Ro PRIORITY COMPARATOR INTE ------------~ ClK-------------~ INPUTS Ro·R7 REQUEST LEVELS (R7 HIGHEST PRIORITY) Bo·B2 ECS INTE CURRENT STATUS STATUS GROUP SELECT ENABLE CURRENT STA"fUS INTERRUPT ENABLE CLK CLOCK (tNT F·F) ELR ENABLE LEVEL READ E1'\.G ENABLE THIS LEVEL GROUP SGS OUTPUTS: J- Ao·A2 INT REQUEST LEVELS INTERRUPT (ACT. LOW) OPEN COLLECTOR ENLG ENABLE NEXT LEVEL GROUP 5-153 CD SCHOTTKY BIPOLAR 8214 INTERRUPTS IN MICROCOMPUTER SYSTEMS Microcomputer system design requires that I/O devices such as keyboards, displays, sensors and other components receive servicing in an efficient method so that large amounts of the total systems tasks can be assumed by the microcomputer with little or no effect on throughput. CPU·DRIVEN MULTIPLEXOR CPU The most common method of servicing such devices is the Polled approach. This is where the processor must test each device in sequence and in effect "ask" each one if it needs servicing. It is easy to see that a large portion of the main program is looping through this continuence polling cycle and that such a method would have a serious, detrimental effect on system throughput thus limiting the tasks that could be assumed by the microcomputer and reducing the cost effectiven.ess of using such devices. --"""'" RAM ROM A more desireable method would be one that would allow the microprocessor to be executing its main program and only stop to service peripheral devices when it is told to do so by the device itself. In effect, the method would provide an external asynchronous input that would inform the processor that it should compiete whatever instruction that is currently being executed and fetch a new routine that will service the requesting device. Once this servicing is complete however the processor would resume exactly where it left off. Polled Method This method is called Interrupt. It is easy to see that system throughput would drastically increase, and thus more tasks could be assumed by the microcomputer to further enhance its cost effectiveness. CPU The Priority Interrupt Control Unit (PICU) functions as an overall manager in an Interrupt-Driven system environment. It accepts requests from the peripheral equipment, determines which of the incoming requests is of the highest importance (priority), ascertains whether the incoming request has a higher priority value than the level currently being serviced and issues an Interrupt to the CPU based on this determination. RAM Each peripheral devi~e or structure usually has a special program or "routine" that is associated with its specific functional or operational requ irements; this is referred to as a "service routine". The PICU, after issuing an Interrupt to the CPU, must somehow input information into the CPU that can "point" the Program Counter to the service routine associated with the requesting device. The PICU encodes the requesting level into such information for use as a "vector" to the correct Interrupt Service Routine. ROM Interrupt Method 5-154 INT " SCHOTTKY BIPOLAR 8214 FUNCTIONAL DESCRIPTION General 'he 8214 is a device specifically designed for use in real time, interrupt driven, microcomputer systems. Basically it is an eight (8) level priority control unit that can accept eight different interrupt requests, determine which has the highest priority, compare that level to a software maintained current status register and issue an interrupt to the system based on this comparison along with vector information to ind icate the location of the service routine. Note that the fourth bit in the register is SGS. This input is part of the value written out by the programmer and performs a special function. The Priority Comparator will only issue an output that indicates the request level is greater than the Current Status Register. If both comparator inputs are equal to zero no output will be present. The SGS input allows the programmer to, in effect, disable this comparison and allow the 8214 to issue an interrupt to the system that is based only on the logic of the priority encoder. Priority Encoder The eight requests inputs, which are active low, come into the Priority Encoder. This circuit determines which request input is the most important (highest priority) as preassigned by the designer. (R7) is the highest priority input to the 8214 and (RO) is the lowest. The logic of the Priority Encoder is such that if two or more input levels arrive at the same time then the input having the highest priority will take presidence and a three bit output, corresponding to the active level (modulo 8) will be sent out. The Priority Encoder also contains a latch to store the request input. This latch is controlled by the Interrupt Disable Flip-flop so that once an interrupt has been issued by the 8214 the request latch is no longer open. (Note that the latch does not store inactive requests. In order for a request to be monitored by the 8214 it must remain present until it has been serviced.) Current Status Register In an interrupt driven microcomputer system it is important to not only prioritize incom ing requests but to ascertain whether such a request is a higher priority than the interrupt currently being serviced. The Current Status Register is a simple 4-bit latch that is treated as an addressable outport port by the microcomputer system. It is loaded when the ECS input goes low. Maintenance of the Current Status Register is performed as a portion of the service routine. Basically, when an interrupt is issued to the system the programmer outputs a binary code (modulo 8) that is the compliment of the interrupt level. This value is stored in the Current Status Register and is compared to all further prioritized incoming requests by the Priority Comparator. In essence, a copy of the cu rrent interrupt level is written into the 8214 to be used as a reference for comparison. There is no restriction to this maintenance, other level values can be written into this register as references so that groups of interrupt requests may be disallowed under complete control of the programmer. 5-155 SCHOTTKY BIPOLAR 8214 Control Signals INT The 8214 also has several inputs that enable the designer to synchronize the interrupt issued to the microprocessor and to allow or disallow such an issuance. Also, signals are provided that perm it simple expansion to other 8214s so that more than eight levels can be controlled. The INT output of the 8214 is the signal that is issued to the microprocessor to initiate the interrupt sequence. As soon a INT is active the INT DIS FF is set, inhibiting further requests from entering the Request Latch. Only the writing out of the current status information by strobing the ECS input will clear the INT DIS FF and allow requests to enter the latch. INTE, elK The INTE (Interrupt Enable) input allows the designer to "shutoff" the interrupt system under control of external logic or possibly under software maintenance. A "zero" on this line will not allow interrupts to be issued to the microcomputer system. Note that INT is also open collector so that when cascaded to other 8214s an interrupt in any of the active devices will set alllNT DIS FFs in the entire array. The ClK (Clock) input is actually the trigger that strobes the Interrupt Flip-Flop. It can be connected to one of the clocks of the microprocessor so that the interrupt issued meets the CPU set-up time specification. Note that due to the gating of the input to the Interrupt Flip-Flop the INT output will only be active for the time of a single clock period, so external latching may be required to hold this signal. ElR, ETlG, ENGl These three signals allow 8214s to be cascaded so that more than eight levels of interrupt requests can be controlled. Basically, the ENLG output of one 8214 is connected to the ETLG input of the next and so on, with the first 8214 having its ETLG input pulled "high" and assigned the highest priority. When the ENlG output is "high" it indicates that there is no interrupt pending on that device and that interrupts can be monitored on the next lower priority 8214. This "cascading" can be expanded almost indefinitely to accomodate even the largest of interrupt driven system arch itectu res. AO, A1, A2 In order to identify which device has interrupted the processor so that the service routine associated with it can be addressed, a pointer or "vector" must accompany the interrupt issued to the microcomputer system. The AD, A1 and A2 outputs represent the complement of the active interrupt level (modulo 8). By using these signals to encode the special instruction, RST, the program counter of the microprocessor, can point to the location of the service routine. Note that these three outputs are gated by the ELR input and are open collector so that expansion is simplified. 5-156 SCHOTTKY BIPOLAR 8214 APPLICATIONS OF THE 8214 8 Level Controller (8080) Basic Operation The most common of applications of the 8214 is that of an eight level priority structure for 8080 or 8008 microcomputer systems. When the initial interrupt request is presented to the 8214 it will issue an interrupt to the 8080 if the structure is enabled. The 8214 will encode the request into 3 bits (modulo 8) and output them to the 8212. After the acknowledgement of the interrupt has been issued by the 8080 the encoded RST instruction is gated onto the Data Bus by the 8212. The processor executes the instruction and points the program counter to the desired serviced routine. In this routine the programmer will probably save the status of the register array and flags within a series of PUSH instructions (4). Then a copy of the current interrupt level (modulo 8) can be "built" in the Accumulator and output to the Current Status Register of the 8214 for use as a comparison reference for all further incoming requests to the system. Shown in the figure below is a detailed logic schematic of a simple circuit that will accept eight input requests, maintain current status, issue the interrupt signal to the 8080 and encode the proper RST instruction to gate onto the data bus. The eight requests are connected to the 8214 by the designer in whatever order of priority is to be preassigned. For example, eight keyboards could be monitored and each assigned a degree of importance (level of priority) so that faster processor attention or access can be assigned to the critical or time dependent tasks. The inputs to the Current Status Register are connected to the Data Bus so that data can be written out into this "port". This Vectored Eight Level Priority Interrupt Structure for 8080 microcomputer systems is a powerful yet flexible circuit that is high performance and has a minimal component count. An 8212 is used to encode the RST instruction and also to act as a 3-state gate to place the proper RST instruction when the 8080 Data Bus is in the input mode. Note that the INT signal from the 8214 is latched in the SR flip-flop of the 8212 so that proper timing is maintained. The 8212 is selected (enabled) when the INTA signal from the 8080 status latch and the DB IN from the 8080 are active, this assures that the RST instruction will be placed on the Data Bus at the proper time. Note that the INT output from the 8212 is inverted and pulled up before it is connected to the 8080. This is to generate an INT signal to the 8080 that has the correct polarity and meets the input voltage requ irement (3.3V). I PRIORITY REQUEST LOWEST 0 1 2 3 4 5 HIGHEST 6 7 RST 1 1 A2 Al Ao 1 1 1 7 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 4 3 2 1 -0 -RST 0 WILL VECTOR PROGRAM COUNTER TO LOCATION o (ZERO) AND INVOKE THE SAME ROUTINE AS "RESET" INPUT TO 8080. THIS COULD RE·INITlALIZE THE SYSTEM BASED ON THE ROUTINE INVOKED. (A CAUTION TO SYSTEM PROGRAMMERS.) 8080 BI-DIRECTIONAL BUS Vee rj>2 (TTL) A6 1K ClK INTE 7 INTE INT b > : 1K 5 > 10K 11 STB INT .... 23 'J 8212 15 _ ~ Do '6~ ~ Fr.; REQUESTS 17 ~ 18 ::: 19 ~ 20~ 21 .... 22 ;:: R2 AQ Ai Ai Ai R5 R6 R7 8214 R; ETlG ~ O2 ",8 .... 9 9 03 16 04 18 ~10 05 ~ 06 ~ 07 11- 13 .... ~ S; ~ 3 .... 4~ 23 .... .... 1~1 MD OSl 113 1 2 01 GND ECS ElR ClR DS2 B2 .... SGS ENABl E CURRE NT STATUS (FROM I/O PORT DECODER) 000 0°1 00 2 00 3 0°4 0°5 0°6 0°7 ~ 01 INTA GND 8 Level Controller 5-157 ...!....6 8 10 15 17 19 21 INT (8080 PIN 14) SCHOTTKY BIPOLAR 8214 DO 8080 BI-ol RECTIONAL BUS ~ ~ ~ ~ 0 ~5 T I T ~ ~2 (TIL) INTE I • IIII • I ,6 I I I • I cl ClK ETLG 1K~ ~ ~: INT I:> 5 III~ b 11 GND PFlg mJ - 2 8214 RESET PR 4 PA5 PR6 PR 7 14 CLR 8212 os, ~ PRIORITY ARRAY EN (FROM I/O PORT DECODER) INT p5 ,~~~ 17~R, 1B~R2 ~~ Ri "'::lI 7n::3R'4 21 ~ R6 ?~~ A J! 8214 9 10 2 ~ ~ ~ 4 22 5 06 07 I/O R GND INTE 3 2 ffl1 7 ClK ETlG 13 PR 3 INT p23 oS2 Mo GND 1~ 0, 0 20 ~ECS ~ Do 7 16 ~3 4 18 0 ~ ~ 4if;s 2 3 : 9 Ai 9 AO~ A 10 PAll PR 12 PR 13 PR 14 PA 15 ENABLE CURRENT STATUS 1 (FROM I/O PORT DECODER) I STB 7 I INTE f5R l0 PRO Pfi l fiR 2 ~ I IT PRs REQUESTS ~ ~ ~ ~ 04 ~ B2 ~ ENABLE CURRENT 2~ ..... STATUS 2 ------~l- ECS (FROM I/O PORT ErR DECODER) 1 ENLG ~ GND 16 Level Controller 5-158 I 07 I T mmn ~10K I I I I I I I I c4> '(808~Np1N 14) ~ SCHOTTKY BIPOLAR 8214 APPLICATIONS OF THE 8214 RST7 Cascading the 8214 SAVE PROCESSOR STATUS When greater than eight levels of interrupts must be prioritized and serviced, the 8214 can be cascaded with other 8214s to support such an .architecture. On the previous page a simple circuit is shown that can control 16 levels of interrupt and is easily expandable to support up to 40 levels of interrupt by just cascading more 8214s. INPUT PRIORITY ARRAY VALUE As described previously, there are signals provided in the 8214 for cascading (ELR, ETLG, ENLG) and in effect the ENLG output of the first 8214 "ripples" down to the next and so on. The entire array of 8214s regardless of size, can be thought of as a single priority control unit, with the first having the highest priority and the next 8214 having a lower priority and so on. LOAD BASE VALUE INTO H REGISTER TRANSFER H & L REGISTER TO PROGRAM COUNTER In this application, the manner in which software handles the servicing of the interrupt will change. Since more than eight vectors must be generated a method other than the common RST instruction must be implemented. Basically, the priority control array must somehow modify the contents of the 8080 Program Counter so that it can point ("vector") to one of 16 (or how many levels are to be serviced) and fetch the proper service routine. A simple approach is to treat the priority control array as a single input port that can input a value into the Accumulator and use this value as an offset to modify the Program Counter (Indirect Jump). I An initial CALL is needed to invoke this Indirect Jump routine so the circuitry is configured to insert an RST 7 (FFh) for all interrupts, thus the Indirect Jump Routine starts at location (56d). 8 9 10 11 12 13 14 HIGHEST 15 SERVICE ROUTINE REQUEST (PR) PRIORITIES LOWEST 0 1 2 3 4 5 6 7 D-7 8-15 A2 EN EN 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 - A, 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 - Ao 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 The Assembly Code for the flow chart is as follows: PUSH PUSH PUSH PUSH IN MOV MVI PCHL :SW} o Shown in the figure above is a chart of the 16 different array values that are used to offset the Program Counter and vector to the proper service routine. These values are the ones that are loaded into the ilL" register; the value loaded into the "H" register with an "immediate instruction" is used to identify the major area of memory where the service routines are stored, similar to a "course setting" and the value in the ilL" register is used to identify a specific location, similar to a "fine setting". (save processor status) (22 microseconds) H (n) L,A H,(n) (input Priority Array Value) (transfer Accumulator to L register) (load Base Address into H register) (transfer H&L to Program Counter) (The execution time for the total routine is 35.5 microseconds based on an 8080 clock period of 500ns.) Following is a basic flowchart of the priority array Indirect Jump routine. Note that the last step in the routine will vector the processor to fetch the proper service routine as dictated by the interrupting level. 5-159 Note that DO, 01, and D2 are always set to "zero", this provides the programmer eight (8) memory locations between the start of each service routine so that maintenance of the associated Current Status Register and a JUMP or CALL instruction can be implemented. This method of interrupt control can be almost indefinitely expanded and provides the system designer with a powerful tool to enhance total system throughput. SCHOTTKY BIPOLAR 8214 D.C. AND OPERATING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias O°C to 70°C -65°C to +150°C Storage Temperature All Output and Supply Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5V to +7V All Input Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -1.0V to +5.5V Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 rnA *COMMENT: Stresses above those listed under"Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specifications is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Symbol Parameter Vc Input Clamp Voltage (all inputs) IF Input Forward Current: ETLG input all other inputs IR Input Reverse Current: Vil Min. Limits Typ.£1] Max. Unit Conditions -1.0 V Ic=-5mA -0.5 -0.25 rnA rnA VF=0.45V ETLG input all other inputs 80 40 IlA IlA VR=5.25V Input LOW Voltage: all inputs 0.8 V Vcc=5.0V VIH Input HIGH Voltage: all inputs V Vcc=5.0V Icc Power Supply Current Val Output LOW Voltage: -.15 -.08 2.0 all outputs VOH Output HIGH Voltage: ENLG output los Short Circuit Output Current: EN LG output ICEX Output Leakage Current: INT and Ao-A2 90 130 rnA See Note 2. .3 .45 V IOl =15mA V IOH=-1mA 2.4 3.0 -20 -35 NOTES: 1. Typical values are for T A = 25° C, V CC = 5.0V. 2. 80-82, SGS, elK, RO-R4 grounded, all other inputs and all outputs open. 5-160 -55 rnA VOs=OV, Vcc=5.0V 100 IlA VCEx=5.25V SCHOTTKY BIPOLAR 8214 A.C. CHARACTERISTICS AND WAVEFORMS TA = o°c to +70°C, vcc = +5V ±5% Parameter Symbol Min. Limits Typ.[1] Max. Unit tCY ClK Cycle Time 80 50 ns tpw ClK, ECS, INT Pulse Width 25 15 ns tlSS INTE Setup Time to ClK 16 12 ns t,SH INTE Hold Time after ClK 20 10 ns tETCS[2] ETlG Setup Time to ClK 25 12 ns tETCH[2] ETlG Hold Time After ClK 20 10 ns tECCS[2] ECS Setup Time to ClK 80 50 ns tECCH[3] ECS Hold Time After ClK 0 tECRS[3] ECS Setup Time to ClK tECRH [3] ECS Hold Time After ClK 0 tECSS[2] ECS Setup Time to ClK 75 tECSH[2] ECS Hold Time After ClK tOCS[2] SGS and 80-82 Setup Time to ClK 70 tOCH[2] SGS and 80-82 Hold Time After ClK 0 tRCS[31 Ro-R 7 Setup Time to ClK 90 tRCH[3] Ro-R 7 Hold Time After ClK 0 tiCS INT Setup Time to ClK 55 tCI ClK to INT Propagation Delay tRIS[41 Ro -R 7 Setup Time to INT 10 0 ns tRIH[4] Ro-R7 Hold Time After INT 35 20 ns tRA Ro-R 7 to Ao·A2 Propagation Delay 80 100 ns tELA ElR to Ao -A2 Propagation Delay 40 55 ns tECA ECS to Ao-A2 Propagation Delay 100 120 ns tETA ETlG to Ao-A2 Propagation Delay 35 70 ns tOECS[41 SGS and 80-82 Setup Time to ECS 15 10 ns tOECH[4] SGS and 8 0 -82 Hold Time After ECS 15 10 ns tREN Ro -R 7 to EN lG Propagation Delay 45 70 ns tETEN ETlG to EN lG Propagation Delay 20 25 ns tECRN ECS to EN lG Propagation Delay 85 90 ns tECSN ECS to EN lG Propagation Delay 35 55 ns 110 ns 70 ns 70 ns ns 0 ns 50 ns ns 55 ns ns 35 15 25 ns CAPACITANCE [5] Symbol Min. Parameter Limits TypJ1] Max Unit C,N Input Capacitance 5 10 pF COUT Output Capacitance 7 12 pF TEST CONDITIONS: VBIAS = 2.5V, Vce = 5V, TA = 25°C, f = 1 MHz NOTE 5. This parameter is periodically sampled and not 100% tested. 5·161 SCHOTTKY BIPOLAR 8214 WAVEFORMS ENLG -----------------"'j( -------- -J.\ _ NOTES: (1) Typical values are for T A = 25°C ,Vee = 5.0V. (2) Required for proper operation if ISE is enabled during next clock pulse. (3) These times are not required for proper operation but for desired change in interrupt flip-flop. (4) Required for new request or status to be properly loaded. TEST CONDITIONS: TEST LOAD CI RCUIT Vee ) Input pulse amplitude: 2.5 volts. Input rise and fall times: 5 ns between 1 and 2 volts. 300n Output loading of 15 rnA and 30 pf. aUTO....----.----------. Speed measurements taken at the 1.5V levels. == 30pf 5-162 600n Schottky Bipolar 8216/8226 4 BIT PARALLEL BIDIRECTIONAL BUS DRIVER • 3.65V Output High Voltage for Direct Interface to 8080 CPU • Data Bus Buffer Driver for 8080 CPU • Low Input Load Current - .25 mA Maximum • High Output Drive Capability for Driving System Data Bus • Three State Outputs • Reduces System Package Count The 8216/8226 is a 4-bit bi-directional bus driver/receiver. All inputs are low power TTL compatible. For driving MOS, the DO outputs provide a high 3.65V VOH, and for high capacitance terminated bus structures, the DB outputs provide a high 50mA IOl capability. A non-inverting (8216) and an inverting (8226) are available to meet a wide variety of applications for buffering in microcomputer systems. cs 2 0°0 OBo 3 16 Vee 15 OlEN 14 LOGIC DIAGRAM 8226 LOGIC DIAGRAM 8216 PIN CONFIGURATION 010 010 OBo 0°3 0°0 010 4 8216/ 13 OB3 DO, 5 8226 12 013 6 11 DB, 01, 01, , 7 10 GND 8 9 _----0 DB, 0°2 DO, 01, _ - - - - o O BO 0°0 DB, DO, OB2 O~ 012 01 2 OB 2 0°2 PIN NAMES 0°2 013 01 3 OB 3 OBO·OB3 DATA BUS BI-OIRECTIONAL 0'o.0~ DATA INPUT 00 0.0°3 DATA OUTPUT OlEN DATA IN ENABLE DIRECTION CONTROL cs CHIP SELECT 0°3 ------+-......- - - - n cs OlEN o - - - _ e _ - - - - - - J ------+.......- - - - 0 cs OlEN 0 - - -.......- - - - - - 1 5-163 SCHOTTKY BIPOLAR 8216/8226 FUNCTIONAL DESCRIPTION Microprocessors like the 8080 are MOS devices and are generally capable of driving a single TTL load. The same is true for MOS memory devices. While this type of drive is sufficient in small systems with few components, quite often it is necessary to buffer the microprocessor and memories when adding components or expanding to a multi-board system. 01 0 0 - - - - -.... "---1---.. ------oOBO OOoo------t-----c: 1-------1-_ 01, 0-------+---1 __' "--4--.. DB, DO, o------t--~ I--~---' The 8216/8226 is a four bit bi-directional bus driver specifically designed to buffer microcomputer system components. Bi-Directional Driver Each buffered Iine of the four bit driver consists of two separate buffers that are tri-state in nature to achieve direct bus interface and bi-directional capabil ity. On one side of the driver the output of one buffer and the input of another are tied together (DB), this side is used to interface to the system side components such as memories, I/O, etc., because its interface is direct TTL compatible and it has high drive (50mA). On the other side of the driver the inputs and outputs are separated to provide maximum flexibility. Of ·course, they can be tied together so that the driver can be used to buffer a true bi-directional bus such as the 8080 Data Bus. The DO outputs on this side of the driver have a special high voltage output drive capability (3.65V) so that direct interface to the 8080 and 8008 CPUs is achieved with an adequate amount of noise immunity (350mV worst case). 01 3 0-------+----1 >--+--.. 003o------t-----c: 1-----+-...... '--------1- ----0 cs OlEN (a) 8216 01 0 - - - - O O BO 0°0 01, Control Gating OlEN, CS DB, DO, The CS input is actually a device select. When it is "high" the output drivers are all forced to their high-impedance state. When it is at "zero" the device is selected (enabled) and the direction of the data flow is determined by the DIEN input. 01 2 0°2 The DIEN input controls the direction of data flow (see Figure 1) for complete truth table. This direction control is accomplished by forcing one of the pair of buffers into its high impedance state and allowing the other to transmit its data. A simple two gate circuit is used for this function. 01 3 0°3 The 8216/8226 is a device that will reduce component count in mjcrocomputer systems and at the same time enhance noise immunity to assure reliable, high performance operation. OlEN ~--------...... (b) 8226 OlEN 0 1 cs 0 0 0 1 1 1 Ol~ OB~ DB DO }HIGH IMPEDANCE Figure 1. 8216/8226 Logic Diagrams 5-164 SCHOTTKY BIPOLAR 8216/8226 APPLICATIONS OF 8216/8226 . 8080 Data Bus Buffer The 8080 CPU Data Bus is capable of driving a single TTL load and is more than adequate for small, single board systems. When expand ing such a system to more than one board to increase I/O or Memory size, it is necessary to provide a buffer. The 8216/8226 is a device that is exactly fitted to this application. The 8216/8226 can be used in a wide variety of other buffering functions in microcomputer systems such as Address Bus Drivers, Drivers to peripheral devices such as printers, and as Drivers for long length cables to other peripherals or systems. Shown in Figure 2 are a pair of 8216/8226 connected directly to the 8080 Data Bus and associated control signals. The buffer is bi-directional in nature and serves to isolate the CPU data bus. 15 4 01 OlEN On the system side, the DB lines interface with standard semiconductor I/O and Memory components and are completely TTL compatible. The DB lines also provide a high drive capability (50mA) so that an extremely large system can be dirven along with possible bus termination networks. 00 DB 2 DO 7 01 8216 8226 9 03 OB1 10 11 12 On the 8080 side the 01 and DO lines are tied together and are directly connected to the 8080 Data Bus for bi-directional operation. The DO outputs of the 8216/8226 have a high voltage output capability of 3.65 volts which allows direct connection to the 8080 whose minimum input voltage is 3.3 volts. It also gives a very adequate noise margin of 350mV (worst case). OBo 6 5 D2 3 OB2 13 14 DB 3 cs SYSTEM OATA BUS 8080 15 01 OlEN D4 OB DO OB4 6 Os 8216 8226 The DIEN inputs to 8216/8226 is connected directly to the 8080. OlEN is tied to DBIN so that proper bus flow is maintained, and CS is tied to BUSEN so that the system side Data Bus will be 3-stated when a Hold request has been acknowledged during a DMA activity. 3 06 DBs 10 OB 6 13 07 DB7 CS Memory and 1/0 Interface to a Bi-directional Bus In large microcomputer systems it is often necessary to provide Memory and I/O with their own buffers and at the same time maintain a direct, common interface to a bi-directional Data Bus. The 8216/8226 has separated data in and data out lines on one side and a common bi-directional set on the other to accomodate such a function. Figure 2. 8080 Data Bus Buffer. Shown in Figure 3 is an example of how the 8216/8226 is used in this type of application. MEMORY The interface to Memory is simple and direct. The memories used are typically Intel® 8102, 81 02A, 8101 or 8107B-4 and have separate data inputs and outputs. The DI and DO lines of the 8216/8226 tie to them directly and under control of the MEMR signal, which is connected to the DIEN input, an interface to the bi-directional Data Bus is maintained. 01 I/O DO OlEN (2) CS 8216 8226 (2) 01 DO OlEN (2) CS 8216 8226 (2) BUSEN ........----~ The interface to I/O is similar to Memory. The I/O devices used are typically Intel® 8255s, and can be used for both input and output ports. The I/O R signal is connected directly to the DI EN input so that proper data flow from the I/O device to the Data Bus is maintained. Figure 3. Memory and I/O Interface to a Bi-Directional Bus. 5-165 SCHOTTKY BIPOLAR 8216/8226 D.C. AND OPERATING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ' O°C to 70°C Storage Temperature -6SoC to +150°C All Output and Supply Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -O.5V to +7V All Input Voltages -1.0V to +5.5V Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 125 rnA *COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Symbol Parameter Min. Limits Typ. Max. Unit Conditions IF1 Input Load Current OlEN, CS -0.15 -.5 mA VF =0.45 IF2 Input Load Current All Other Inputs -0.08 -.25 mA VF =0.45 IR1 Input Leakage Current OlEN, CS 20 p.A VR =5.25V IR2 Input Leakage Current 01 Inputs 10 p.A VR =5.25V Vc Input Forward Voltage Clamp -1 V le= -5mA Vil Input "Low" Voltage .95 V VIH Input "H igh" Voltage 1101 Output Leakage Current (3-State) IcC Power Supply Current VOl1 Output" Low" Voltage VOl2 Output "Low" Voltage VOH1 Output "High" Voltage 3.65 VOH2 Output "High" Voltage 'OS Output Short Circuit Current V 2.0 DO DB 20 100 p.A Vo = 0.45V/5.25V 8216 95 130 rnA 8226 85 120 rnA 0.3 .45 V DO Outputs IOl=15rnA DB Outputs IOl=25rnA 8216 0.5 .6 V DB Outputs IOl=55mA 8226 0.5 .6 V DB Outputs IOL=50mA 4.0 V DO Outputs IOH = -1 mA 2.4 3.0 V DB Outputs 10H = -1 OmA -15 -30 -35 -75 NOTE: Typical values are for TA = 25°C, Vee = 5.0V. 5-166 -65 -120 mA rnA DO Outputs Vo==OV, DB Outputs Vee=5.0V SCHOTTKY BIPOLAR 8216/8226 WAVEFORMS -'X'-:,_5V INPUTS _ l--t FD OUTPUT ENABLE .5V ---+---V OH f VOL .5V A.C. CHARACTERISTICS TA = O°C to +70°C, Vcc = +5V ±5% Parameter Symbol Limits Typ,£1] Min. Max. Unit Conditions TpD1 Input to Output Delay DO Outputs 15 25 ns CL=30pF,R 1 =300n R2=600n TpD2 Input to Output Delay DB Outputs 8216 20 30 ns C L=300pF,R 1 =90n 8226 16 25 ns R 2 = 180n 8216 45 65 ns (Note 2) 8226 35 54 ns (Note 3) 20 35 ns (Note 4) Output Enable Time TE Output Disable Time To TEST CONDITIONS: TEST LOAD CI RCUIT Input pulse amplitude of 2.5V. Input rise and fall times of 5 ns between 1 and 2 volts. Output loading is 5 rnA and 10 pF. Speed measurements are made at 1.5 volt levels. OUT 0---.......------...... Capacitance [5] Symbol Parameter Min. Limits Typ'£1] Max. Unit 4 8 pF CIN Input Capacitance COUT1 Output Capacitance 6 10 pF CO UT2 Output Capacitance 13 18 pF TEST CONDITIONS: NOTES: VB1AS = 2.5V, Vcc = 5.0V, TA = 25°C, f = 1 MHz. 1. Tvpical values are for TA = 25°C, VCC = 5.0V. 2. DO Outputs, CL = 30pF, R1 = 300/10 Kil, R2 = 180/1 Kil; DB Outputs, CL = 300pF, Rl = 90/10 Kil, R2 = 180/1 Kil. 3. DO Outputs, CL = 30pF, Rl = 300/10 Kil, R2 = 600/1 K; DB Outputs, CL = 300pF, Rl = 90/10 Kfl, R2 = 180/1 Kil. 4. DO Outputs, CL = 5pF, Rl = 300/10 Kil, R2 = 600/1 Kil; DB Outputs, CL = 5pF, R1 = 90/10 Kil, R2 = 180/1 Kil. 5. This parameter is periodically sampled and not 100% tested. 5-167 Coming Soon 8253 8257 8259 Silicon Gate MOS 8253 PROGRAMMABLE INTERVAL TIMER • 3 Independent 16-Bit Counters • Count Binary or BCD • Single +5V SUPR • 24 Pin Dual-in-li • DC to 3 MHz • Programmable Counter Modes The 8253 is a programmable counter/timer chip designed for use as an 8080 (or with a single +5V supply and is packaged in a 24-pin plastic DIP. It uses nMOS technology It is organized as three independent 16-bit counters, each with a count rat software programmable by the 8080. z. ~Jmodes'of v operation are "'."~O S" ,9 PIN CONFIGURATION ClKO GATE 0 ...------..OUT 0 ClK 1 COUNTER #1 GATE 1 .....---. OUT 1 CONTROL WORD REGISTER AND MODE SELECTION INTERNAL BUS / 5-169 ClK2 COU':;TER 14'-_ GATE 2 ~----"OUT2 SILICON GATE MOS 8253 8253 PRELIMINARY FUNCTIONAL DESCRIPTION In Microcomputer-based systems the most common interface is to a mechanical device such as a printer head or stepper motor. All such devices have inherent delays that must be accounted for if accurate and reliable performance is to be achieved. The systems software allows for such delays by programmed timing loops. This type of programming requires significant ov~rhead and maintenance of multiple loops gets extremely complicated. CLKO DATA BUS BUFFER AD • Programmable Baud Rate Generator • Event Counter • Binary Rate Multiplier • Real Time Clock --___.a WR -----+C11 The 8253 Programmable Interval Timer is a single chip solution to system timing problems. In essence, it is a group of three 16-bit counters that are independent in nature but driven commonly as I/O peripheral ports. Instead of setting up timing loops in the system software, the programmer configures the 8253 to match his requirements. The programmer initializes one of the three counters of the 8253 with the quantity and mode desired then, upon command, the 8253 will count out the delay and interrupt the microcomputer when it has finished its task. It is easy to see that the software overhead is minimal and that multiple delays can be easily maintained by assigned interrupt levels to different counters. Other functions that are non-delay in nature and require counters can also be implemented with the 8253. GATE 0 ClK 1 READ/ WRITE lOGIC GATE 1 OUT 1 cs-------' CLK2 COUNTER #2 GATE 2 OUT2 INTERNAL BUS 8253 Block Diagram. System Interface The 8253 is a component of the MC5-80 system and interfaces in the same manner as all other peripherals of the family. It is treated by the systems software as an array of I/O ports; three are counters and the fourth is a control register for programming. The OUT lines of each counter would normally be tied to the interrupt request inputs of the 8259. ADDRESS BUS (16) The 8253 represents a significant improvement for solving one of the most common problems in system design and reducing software overhead. A1 An 0 0 .0 7 8253 COUNTER COUNTER COUNTER 0 1 2 I I I lOUT GATE ClK I lOUT GATE ClK I lOUT GATE ClK I 8253 System Interface. 5..170 Silicon Gate MOS 8257 PROGRAMMABLE DMA CONTROLLER • Four Channel DMA Controller • Priority DMA Request Logic • Channel Inhibit Logic • Terminal and Modulo 256/128 Outputs • Auto Load Mode • Single TTL Clock «(/)21 TTL) • Single +5V SUR~~ • Expandable • 40 Pin Du ~~:W~l~\:~~ '.'., cl}mputer systems. Its priThe 8257 is a Direct Memory Access (DMA) Chip which has four channels for use i allow the peripheral to acmary function is to generate, upon a peripheral request, a sequential memory a ress ; the system bus. It also keeps cess or deposit data directly from or to memory. It uses the Hold feature of th "grar11mable terminal count has count of the number of DMA cycles for each channel and notifies the periphe ~<, amon9,$fl'e four channels, programbeen reached. Other features that it has are two mode priority logic to res/ mabie channel inhibit logic, an early write pulse option, a modulo 256/1 for s~~tbred data transfers, an auto/'dur!~:~i)DMA cycles. There are three matic load mode, a terminal count status register, and control signaL;:-· . types of DMA cycles: Read DMA Cycle, Write DMA Cycle and Verify,/,t The 8257 is a 40-pin, N-channel MOS chip which uses a single ~; designed to work in conjunction with a single 8212 8-bit, thr~ the number of channels with the aid of the 8214 Priority Inter' e ¢2,.JJTL) clock of the 8080 system. It is '"Mulff;J3I'e DMA chips can be used to expand . ~ , .::-,/ c~::~"t OACK 0 + - - ORO 1 OACK 1 ORO 2 oACK 2 cs----A4 ----1 As ----1 A6 ----1 A7 ----1 ORO 3 OACK 3 REAoY----.tI HOLD ..........- - - 1 CONTROL LOGIC HLDA----.. MEMR ---ClIII MEMW ----<...JI AEN ----1 AoSTB ----1 PRIORITY RESOLVER INTERNAL BUS TC ..........- - - - ' " 128/256 . . - - - - - - - - - - ' 5-171 SILICON GATE MOS 8257 8257 PRELIMINARY FUNCTIONAL DESCRIPTION The transfer of data between a mass storage device such as a floppy disk or mag cassette and system RAM memory is often limited by the speed of the microprocessor. Removing the processor during such a transfer and letting an auxiliary device manage the transfer in a more efficient manner would greatly improve the speed and make mass storage devices more attractive, even to the small system designer. operation, a request is made from a peri phera I device for access to the system bus. After its pr iority is accepted a HOLD command is ussued to the CPU, the CPU issues a HLDA and that DMA channel has complete control of the system bus. Transfers can be made in blocks, suspending the processors operation during the entire transfer or, the transfer can be made a few bytes at a time, hidden in the execution states of each instruction cycle, (cycle-stealing). The transfer technique is called DMA (Direct Memory Access); in essence the CPU is idled so that it no longer has control of the system bus and a DMA controller takes over to manage the transfer. The modes and priority resolving are maintained by the system software as well as initializing each channel as to the starting address and length of transfer. The 8257 Programmable DMA Controller is a single chip, four channel device that can efficiently manage DMA activities. Each channel is assigned a priority level so that if multi-DMA activities are required each mass storage device can be serviced, based on its importance in the system. In The system interface is si mi lar to the other peri phera Is of the MCS-80 but an additional 8212 is necessary to control the entire address bus. A special control signal BUSEN is connected directly to the 8228 so that the data bus and control bus will be released at the proper time. \ ADDRESS BUS (16) ~ CONTROL BUS \ ilOR flOW ~ \ HOLD RESET \ DATA BUS (8) 4:/'\~ A s -A,5 1/ / A o-A 3 / READY 8 V A 4 -A7 l/L-- '--- 8212 BUSEN 8228 CS A o·A 3 MEMW MEMR A 4 -A7 ['r- HLDA t t I AOSTB 8 1 "',/7 AEN 0 7 -00 MEM I/O R W HOLD HLOA 92(TTL) CLK ROYIN RESET ORO 1 DACK ORO 0 0 l f W if 8257 128/256 MOD TC ~ ! DACK ORO 3 3 DACK 2 ORO 2 ~ t l t DACK 1 I l 1 OMA CHANNEL REOUESTS AND ACKNOWLEDGES System Interface 8257. ADDRESS BUS ORO 0 ......-----11 DACK 0 1------.. DISK 1 ORO 1 1 . . - - - - - 1 8257 AND 8212 DACK 1 I _ _ _ - - - - - . t ORO 2 ......- - - - 1 1 DACK 2 1------... ORO 3 1 + - - - - - - 1 DISK 2 DACK 31--------.. OMA CONTROLLER DUAL FLOPPY DISK CONTROLLER System Application of 8257. 5-172 SYSTEM RAM MEMORY Silicon Gate MOS 8259 PROGRAMMABLE INTERRUPT CONTROLLER • Individual Request Mask Capability • Single + 5V Sup (No Clocks) • 28 Pin Dua ckage • Eight Level Priority Controller • Expandable to 64 Levels • Programmable Interrupt Modes (Algorithms) The 8259 handles up to eight vectored priority interrupts for the 8080A CPU. I interrupts, without additional circuitry. It will be, packaged in a 28-pin plasf single +5V supply. Circuitry is static, requiring no clock input. r up to 64 vectored priority technology and requires a The 8259 is designed to minimize the software and real time overhead in modes, permitting optimization for a variety of system requirements. PIN CONFIGURATION READ! WRITE LOGIC REQUEST LATCH MASK REGISTER IR 0 4---IR 1 IR 2 4--- IR 3 . - - IR 4 4 - - - IR 5 "'-IR6 "'-IR7 o CS-------It CASO~--.nI CAS1 ....--....n CAS 2 " " " - - - . n I I SP ~--.nII INT......----I INTA---.nI 5-173 CONTROL LOGIC ~INTERNALBUS INTERRUPT REQUESTS SILICON GATE MOS 8259 8259 PRELIMINARY FUNCTIONAL DESCRIPTION In microcomputer systems, the rate at which a peripheral device or devices can be serviced determines the total amount of system tasks that can be assigned to the control of the microprocessor. The higher the throughput the more jobs the microcomputer can do and the more cost effective it becomes. Interrupts have long been accepted as a key to improving system throughput by servicing a peripheral device only when the device has requested it to do so. Efficient managing of the interrupt requests to the CPU will have a significant effect on the overall cost effectiveness of the microcomputer system. ADDRESS BUS (16) The 8259 Programmable Interrupt Controller is a single-chip device that can manage eight levels of requests and has builtin features for expandability to other 8259s (up to 64 levels). It is programmed by the systems software as an I/O peripheral. A selection of priority algorithms is available to the programmer so that the manner in which the requests are processed by the 8259 can be configured to match his system requirements. The priority assignments and algorithms can be changed or reconfigured dynamically at any time during the main program. This means that the oomplete interrupt structure can be defined as required, based on the total system environment. 8259 IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ 765 4 ~ 2 1 0 SLAVE PROG. I INTERRUPT REQUESTS 8259 System Interface. The system interface is the same as other peripheral devices in the MC5-80. A special input is provided (SP) to program the 8259 as a slave or master device when expanding to more than eight levels. Basically the master accepts INT inputs from the slaves and issues a composite request to the 8080A; when it receives the INTA from the 8228 it puts the first byte on the CALL on the bus. On subsequent INTAs the interrupting slave puts out the address of the vector. ~ ADDR ESS BUS (16) \ CONTROL BUS ~ \ INT REQ \ \ DATA BUS (8) .",,t. to/'.. :lo --- --- - - - - - -- ---- - ---I-~ ~ 1-- - I---~ --I- I---- I-- - I- - ~V7 ~v'7 ( r-p.- 8259 SLAVE 2 ,t./'.. ~,7 ""' 8259 SLAVE 1 I-- ""' SP G!O 1 fIll 21 20 19 18 f 11 17 16 15 14 G!O f 13 f f fIlII 12 11 10 9 8 I INTERRUPT REQUESTS Cascading the 8259 22 Level Controller (Expandable to 64 levels). 5-174 7 6 "'v'7 '" 8259 MASTER '" p...tSf ~v'7 "''...1''1 '" SP lJJ J 1111 , 5 4 3 2 1 0 Intel Product Number CPU GROUP ROMs RAMs I/O PERIPHERAL - - - - - Standard Package Type 8224 C 0 P 16 8228 C 0 P 28 8080A C 40 8702A C 24 8708/4 C 24 8302 C P 24 8308 C P 24 8316A C P 24 8101-2 C P 22 8111-2 C P 18 8102-2 C P 16 8102A-4 C P 16 81078-4 C P 22 5101 C P 22 P 18 8210 0 8222 D 8212 0 8255 C 8251 C 8205 C 8214 C 8216/26 COMING SOON - Number Of Pins 22 P Comments Including 8080A-1, 8080A-2 and M8080A New Product 24 40 P 28 0 P 16 0 P 24 0 P 16 8253 24 Coming Soon 8257 40 Coming Soon 8259 28 Coming Soon C = Ceramic 0 = Cerdip P = Plastic 6·1 PACKAGING INFORMATION Dimensions in inches and (millimeters). 16-LEAD CERAMIC DUAL IN-LINE PACKAGE (C) 16-LEAD CerDIP DUAL IN-LINE PACKAGE (D) ~:[O:::JJ .735~ I I .830 121,0821 ~~ .070 (1,778) ~!2.ill1_ .023 10,5841 :Q!Q~- I---l-~ ~ .06511.651 .11012,7941 TYP. 16-LEAD PLASTIC DUAL IN-LINE PACKAGE (P) 1a-LEAD CERAMIC DUAL IN-LINE PACKAGE (C) -- -- .855121,7171 ~ lli!.ml If----_ ALTERNATE PIN ;:1 IDENT. (IF NO NOTCH AT END OF PKG.I .-r--t==:I..lI::t.~....:::::::Io.I:=--e::s...c:~::::IiIloI~., I ~~ .29517,493) ~:~':~:1 'r- .0751t.9051 REF l .025 10,6351 I R rr .050 11,271 MAX. REF. I ,~t 1-.290~-l ?ml17'~741~ .OO8~ :Di2 10,3051 I ~~ I I--- -II-, .410 110.41414 1a-LEAD PLASTIC DUAL IN-LINE PACKAGE (P) 1a-LEAD CerDIP DUAL IN-LINE PACKAGE (D) I ,B50~ I .930 123,62) C:=§' :'L .240~ 1 I - 1 1-.045 /1,141 I :07011,7BI I ,905~ .925 (23,495) 20015,~ f .07011,7B} : ;: : ;i: : i=: :;: : : j;: : :=c: : ;=;: : ;: : =;=;:=r~ 1 i'i=i::::i"=i:=i=1=i::: I -+ ~ .- _.._-- :i1ii112..l91 ! --r- ll~~') .2~l~~' MAX t ~ JIO,511 .050 11,27} I • ! I ,057~~i4611 .100 (2,541 JL .11012,794} .065/1,6511 T ].075/1,905) REF. -l ~ ~ ~ .032(0,8131' 1·15013,Bl} REF.:21§~ .024 IO,610} 22-LEAD CERAMIC DUAL IN-LINE PACKAGE (C) 114·-------~:~~e------- ~lMW .4~ .·.1 PIN#lID ,. . . ., . .,- ,-. . ,. . . ,. . ,. . ,.- ,. . ., ............ 25R.REF ~~ (NOTCH OPTIONAl) ,054 ~ .040 /1,016) (r t* :oso 0321 ~ 200 Is,oa;f L...i. MAX, L Jl :~: ~. ~, . 1 ~~ II -.j f4- ~ - - - - - 10 Ea. SPACES@.10012,540) 6-2 =, L .140~ - -- -- - - _. - LL ~~ ~~ • :;so 13,81) r[Lr-__.. ,-,...,- ,. ~-1 I- ~~TYP. •012 (0,3051 /I f .39Ol!.!!!!L Ji50 /1,271 -.f f.- .010 (()~:10,414) .10012,54} REF, It-j PACKAGING INFORMATION Dimensions in inches and (millimeters). 22-LEAD PLASTIC DUAL IN-LINE PACKAGE (P) PIN 1 ~ I ·34o~ I .360 19.144) .126 13.175) 1;r==i="-.=:::::p;;;;;r==:p;;;;r=;~==p:;r=::::p;:;;;;r=:::;;:::;;r==Fr===r;;;;;:;==;:;:or="'~ . I 1.090 ~) 1.110128.194) .02010,508) MIN. - - - - - -L --r- \.--.J..'~~~l = j ~ -j h j ~ Il .03~~p~'3) .025 10,635) RjF. ---l- ::r~ :t .160 14,0641 -.L --==l .~ I I -i~.•,~~::~, •.'.1 .15013,81) ~ -L O' ... .06~~p~24) 24-LEAD CERAMIC DUAL IN-LINE PACKAGE (C) 24-LEAD CerDIP DUAL IN-LINE PACKAGE (D) ~:: I I :::::------h NOTE 1. 0.126 (3.176) MAX. NOTE 2. 0.050 11,279) MAX. .550 113.97) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .,..,.l1'u, __ I 120 I -+ I .0076 (0.19) .0116 (0.29) - Ir I I t 112.701 _ _1 .020 (0.511 .05011.27) .~ 12,54) U 1.300 I ~~~~~T t 11~~l\ n .012 (0.30) I .050 llJ1ID REF ~ _~3.D481 133.0'01 -r-::..I h 1_~115,24)-1 .730 118,64) 1.175 ~ ·D4~~F·'i _ _ .~(0.20) t . NOTE 1 '~ .800 115,241 -liIS.59) MAX." .._ _........._ _.. .015 (0,38) :023 (0,581 TYP 1 1 . 0 6 0 (1,624) .07011.78) .110,12.79) ...- -.....- - - - - - - - - - - . . . . -----.J L:Qg~ PIN 1 I :~g ~ TYP. .150 (3,81) 0" - / .032(O,813)--1h TYP. I '1 I #:."'" 15° ~ ~ TYP. / r-------. ~= ~.090(2.29) ~~ .012 (0,305) r-r:iiO(2.79) 24-LEAD PLASTIC DUAL IN-LINE PACKAGE (P) 28-LEAD CERAMIC DUAL IN-LINE PACKAGE (C) ~:=~-----.I I.... (REF) 1.40 13.556) I' •190 14,826) -. REF. MAX. '1 D ----l. .150(3.81) REF. .250(6,35) t ,ill1.!.M§§J .588 (14.735) ~ REF• •200 ' & , 0 8 1 . MAX. If Y ~ I 'I I JL . -1 f- .06011,524) REF. ~~ BEND LINE "I-±- .07011.n8) REF. ---- .145~ -,--~"30(&'''') ~ I~ ~ I :1Q:Q~ m -:roo *~(4,'9') j ~ ---. .020 (0,508) .032 (0,813) REF. II r-l ~ ~~ -..j " MAX. .020 (0,508) MIN. MIN. .015~_ 10.584) .100 (2,64) TYP. .090~ .150(3.8101 12.6401 TYP. •023 (0,684) 40-LEAD CERAMIC DUAL IN-LINE PACKAGE (C) 2·,c:l~,34}- 1 PIN 1 .,. , . ,. , . ,. ,l"T"'l "T"'lrT"'l "T"'l,.,. ,r-r;p:i i i ~;:; : ;~ "I" 'I' 'I' ' 'I' 'I' ' 'W' 'I' ' 'W' I ..i- . o,.r:: MIN. _ IL &!§~ ~~ ........... ~ ••361 ~230MAX. 1&.6421 .02310.5841 -r _ IL j ~~TYP .11012.7941' 6-3 t --t.. :16013.81) .1oo~1 SALES AND MARKETING OFFICES U.S. SALES AND MARKETING OFFICES U.S. MARKETING HEADQUARTERS 3065 Bowers Avenue Santa Clara, California 95051' Tel (408) 246-7501 TWX: 910-338-0026 TELEX: 34-6372 NATIONAL SALES MANAGER Hank O'Hara 3065 Bowers Avenue Sanla Clara. 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Germany Tel: 6127/2314 SWEDEN Nordisk Electronik AS Fack S-103 Stockholm 7 Tel: (08)-24-83-40 TELEX: 10547 SWITZERLAND Industrade AG Gemsenstrasse 2 Postcheck 80 - 21190 8021 Zurich Tel: (01) 602230 TELEX: 56788 UNITED KINGDOM Rapid Recall. Ltd. 11-14 Betterton Street Drury Lane London WC2H 9BS Tel: (01) 379-6741 TELEX: 28752 u.s. DISTRIBUTORS u.s. DISTRIBUTORS WEST MID-AMERICA NORTHEAST SOUTHEAST ARIZONA Cramer/Arizona 2643 East University Drive Phoenix 85034 Tel: (602) 263·1112 Hamilton/Avnet Electronics 2615 South 21st Street Phoenix 85034 Tel: (602) 275·7851 INDIANA Sheridan Associates. Inc. 4002 Medows Dr. Indianapolis 46205 Tel: (317) 547-7777 CONNECTICUT Cramer/Connecticut 35 Dodge Avenue North Haven 06473 Tel: (203) 239-5641 Hamilton/Avnet Electronics 643 Danbury Road Georgetown 06829 Tel: (203) 762-0361 ALABAMA Cramer/EW Huntsville. Inc. 2310 Bob Wallace Avenue. S.W. Huntsville 35805 Tel: (205) 539-5722 Hamilton/Avnet Electronics 805 Oster Drive NW Huntsville 35805 Tel: (205) 533-1170 MARYLAND Cramer/EW Baltimore 7255 Standard Drive Hanover 21076 Tel: (301) 796-5790 Cramer/EW Washington 16021 Industrial Drive Gaithersburg 20760 Tel: (301) 948-0110 Hamilton/Avnet Eleclronics 7255 Standard Drive Hanover 21076 Tel: (301) 796-5000 FLORIDA Cramer/E.W. Hollywood 4035 No. 29th Avenue Hollywood 33020 Tel: (305) 923·8181 Hamilton/Avnet Electronics 4020 No. 29th Ave. Hollywood 33021 Tel: (305) 925-5401 Cramer/E.W. Orlando 345 No. Graham Ave. Orlando 32814 Tel: (305) 894-1511 MASSACHUSETTS Cramer Electronics Inc. 85 Wells Avenue Newton 02159 Tel: (617) 969-7700 Hamilton/Avnet Electronics 185 Cambridge Street Burlington 01803 Tel: (617) 273-2120 GEORGIA Cramer/EW Atlanta 3923 Oakcliff Industrial Center Atlanta 30340 Tel: (404) 448-9050 Hamilton/Avnet Electronics 6700 I 85. Access Road, Suite 2B Norcross 30071 Tel: (404) 448-0800 NEW JERSEY Cramer/Pennsylvania, Inc. 12 Springdale Road Cherry Hill Industrial Center Cherry Hill 08003 Tel: (609) 424-5993 TW X: 710-896-0908 Hamilton/Avnet Electronics 218 Little Falls Road Cedar Grove 07009 Tel: (201) 239-0800 TWX: 710-994-5787 Cramer/New Jersey No.1 Barrett Avenue Moonachie 07074 Tel: (201) 935-5600 Hamilton/Avnet Electronics 113 Gaither Drive East Gate Industrial Park Mt. Laurel 08057 Tel: (609) 234-2133 TWX: 710-897-1405 NORTH CAROLINA Cramer Electronics 938 Burke Street Winston-Salem 27102 Tel: (919) 725-8711 CALIFORNIA Hamilton/Avnet Electronics 575 E. Middlefield Road Mounlain View 94040 Tel: (415) 961·7000 Hamillon/Avnet Electronics 8917 Complex Drive San Diego 92123 Tel: (714) 279·2421 Hamilton Electro Sales 10912 W. Washington Boulevard Culver City 90230 Tel: (213) 558-2121 Cramer/San Francisco 720 Palomar Avenue Sunnyvale 94086 Tel: (408) 739-3011 Cramer/los Angeles 17201 Daimler Street Irvine 92705 Tel: (714) 979-3000 Cramer/San Diego 8975 Complex Drive San Diego 92123 Tel: (714) 565·1881 COLORADO Cramer/Denver 5465 E. Evans PI. at Hudson Denver 80222 Tel: (303) 758-2100 Hamilton/Avnet Electronics 5921 No. Broadway Denver 80216 Tel: (303) 534-1212 NEW MEXICO Hamilton/Avnet Electronics 2450 Baylor Drive. S.E. Albuquerque 87119 Tel: (505) 765·1500 Cramer/New Mexico 137 Vermont, N.E. Albuquerque 87108 Tel: (505) 265-5767 OREGON Almac/Stroum Electronics 4475 S.W. Scholls Ferry Rd. Portland 97225 Tel: (503) 292-3534 UTAH Cramer/Utah 391 W. 2500 South Salt Lake City 84115 Tel: (801) 487-4131 Hamilton/Avnet Electronics 647 W. Billinis Road Salt Lake City 84119 Tel: (801) 262-8451 WASHINGTON Hamilton/Avnet Electronics 13407 Northrup Way Bellevue 98005 Tel: (206) 746·8750 Almac/Stroum Electronics 5811 Sixth Ave. South Seattle 98108 Tel: (206) 763-2300 Cramer/Seattle 5602 Sixth Ave. South Seattle 98108 Tel: (206) 762·5755 ILLINOIS Cramer/Chicago 1911 So. Busse Rd. Mt. Prospect 60056 Tel: (312) 593-8230 Hamilton/Avnet Electronics 3901 No. 25th Ave. Schiller Park 60176 Tel: (312) 678-6310 KANSAS Hamilton/Avnet Electronics 37 lenexa Industrial Center 9900 PlIumm Road Lenexa 66215 Tel: (913) 888-8900 Sheridan Associates. Inc. 10100 Santa Fe Dr. Mark 1 Bldg.• Suite 101 Overland Park 66212 Tel: (913) 383·1636 MICHIGAN Sheridan Sales Co. 24543 Indoplex Drive Farmington Hills 48024 Tel: (313) 477-3800 Cramer/Detroit 13193 Wayne Road Livonia 48150 Tel: (313) 425·7000 TWX: 810-242-2985 Hamilton/Avnet Electronics 12870 Farmington Road Livonia 48150 Tel: (313) 522-4700 TWX: 810-242-8775 MINNESOTA Industrial Components. Inc. 5280 West 74th Street Minneapolis 55435 Tel: (612) 831-2666 Cramer/Bonn 7275 Bush Lake Road Edina 55435 Tel: (612) 835-7811 Hamilton/Avnet Electronics 7683 Washington Avenue So. Edina 55435 Tel: (612) 941-3801 MISSOURI Hamilton/Avnet Electronics 364 Brookes Lane Hazelwood 63042 Tel (314) 731-1144 Sheridan Sales Co. 110 South Highway 140, Suite 10 Florissant 63033 Tel: (314) 837·5200 OHIO Hamilton/Avnet Electronics 118 Westpark Road Dayton 45459 Tel: (513) 433-0610 TWX: 810-450-2531 Sheridan Sales Co. 10 Knollcrest Drive Cincinnati 45222 Tel: (513) 761-5432 TWX: 810-461-2670 Cramer/Cleveland 5835 Harper Road Cleveland 44139 Tel: (216) 248·8400 TWX: 810-427-9407 Hamilton/Avnet Electronics 761 Beta Drive Cleveland 44143 Tel: (216) 461-1400 Cramer/Tri States. Inc. 666 Redna Terrace Cincinnati 45215 Tel. (513) 771-6441 TWX: 810-461-2882 Sheridan Sales Co. 23224 Commerce Park Road Beachwood 44122 Tel: (216) 831-0130 Sheridan Sales Co. Shiloh Building, Suite 250 5045 North Main Street Dayton 45405 Tel: (513) 277-8911 TEXAS Cramer Electronics 2970 Blystone Dallas 75220 Tel: (214) 350-1355 Hamilton/Avnet Electronics 4445 Sigma Road Dallas 75240 Tel: (214) 661-8661 Hamilton/Avnet Electronics 1216 W. Clay Houston 77019 Tel: (713) 526-4661 Component Specialties, Inc. 10907 Shady Trail, Suite 101 Dallas 75220 Tel: (214) 357-4576 Component Specialties, Inc. 7313 Ashcroft Street Houston 77036 Tel: (713) 771-7237 WISCONSIN Cramer/Wisconsin 430 West Rawson Avenue Oak Creek 53154 Tel: (414) 764-1700 NEW YORK Cramer/Binghamton 3220 Watson Boulevard Endwell 13760 Tel. (607) 754-6661 Cramer/Rochester 3000 Winton Road South Rochester 14623 Tel: (716) 275-0300 Hamilton/Avnet Electronics 167 Clay Road Rochester 14623 Tel: (716) 442-7820 Cramer/Syracuse 6716 Joy Road East Syracuse 13057 Tel: (315) 437-6671 Hamilton/Avnet Electronics 6500 Joy Road E. Syracuse 13057 Tel: (315) 437-2642 Cramer/Long Island 29 Oser Avenue Hauppauge, L.J. 11787 Tel: (516) 231-5600 TWX: 510-227-9863 Hamilton/Avnet Electronics 70 State Street Westbury, L.I. 11590 Tel: (516) 333-5800 TWX: 510-222-8237 PENNSYLVANIA Sheridan Sales Co. 1717 Penn Avenue, Suite 5009 Pittsburgh 15221 Tel: (412) 244-1640 Cramer Electronics 616 Beatty Drive Monroeville 15146 Tel: (412) 242-7410 CANADA ALBERTA L. A. Varah Ltd. 4742 14th Street N.E. Calgary T2E 6LT Tel: (403) 276-8818 Telex: 138258977 BRITISH COLUMBIA L. A. Varah Ltd. 2077 Alberta Street Vancouver 10 Tel: (604) 873·3211 ONTARIO Cramer/Canada 920 Alness Avenue, Unit No.9 Downsview Toronto 392 Tel: (416) 661-9222 TWX: 610-492-6210 Hamilton/Avnet Electronics 6291-16 Dorman Road Mississauga l4V 1H2 Tel: (416) 677-7432 TWX: 610-492·8867 Hamilton!Avnet Electronics 1735 CourtwOOd Cresco Ottawa K2C 3J2 Tel: (613) 226-1700 TWX: 610 562-1906 QUEBEC Hamilton/Avnet Electronics 2670 Paulus SI. Laurent H45 1G2 Tel: (514) 331-6443 TWX: 610-421-3731 NOTES: _ NOTES: _ NOTES: _ INSTRUCTION SET Summary of Processor Instructions Mnemonic Description 07 06 Instruction Code 11 J Os 04 03 02 0, Do Clock(2) Cycles MOV r1 • r2 MOVM.r MOVr.M HLT MVI r MVIM tNR r OCR r INR M OCR M AOOr AOCr SUB r SBB r Move register to register Move register to memory Move memory to register Halt Move immediate register Move immediate memory Increment register Decrement register Increment memory Decrement memory Add register to A Add register to A with carry Subtract register from A Subtract register from A with borrow And register with A Exclusive Or register with A Or register with A Compare register with A Add memory to A Add memory to A with carry Subtract memory from A Subtract memory from A with borrow And memory with A Exclusive Or memory with A Or memory with A Compare memory with A Add immediate to A Add immediate to A with carry Subtract immediate from A Subtract immediate from A with borrow And immediate with A Exclusive Or immediate with A Or immediate with A Compare immediate with A Rotate A left Rotate A right Rotate A left through carry Rotate A right through carry Jump unconditional Jump on carry Jump on no carry Jump on zero Jump on no zero Jump on positive Jump on minus Jump on parity even Jump on parity odd Call unconditional Call on carry "Call on no carry Call on zero Call on no zero Call on positive Call on minus Call on parity even Call on parity odd Return Return on carry Return on no carry 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 1 0 0 0 0 5 7 7 7 7 10 5 5 10 10 4 4 4 4 ANAr XRA r ORA r CMPr ADO M AOC M SUB M SBB M ANA M XRA M ORA M CMPM AOI ACI SUI SBI ANI XRI ORI CPt RLC RRC RAL RAR JMP JC JNC JZ JNZ JP JM JPE JPO CALL CC CNC CZ CNZ CP CM CPE CPO RET RC RNC NOTES: 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 1 S S S S S S 1 1 1 1 0 0 0 0 S S S S S S S S 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 S S 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 S S 0 0 0 0 0 1 0 1 S S S S S S S S 0 0 0 0 7 7 4 4 4 4 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 10 10 10 10 10 10 10 10 10 17 11/17 11/17 11/17 11/17 11/17 11/17 11/17 11/17 10 5/11 5/11 Mnemonic Description 07 06 RZ RNZ RP RM RPE RPO RST IN OUT LXI B Return on zero Return on no zero Return on positive Return on minus Return on parity even Return on parity odd Restart Input Output Load Immediate register Pair B & C LXIO Load immediate register Pair 0 & E LXI H Load immediate register Pair H & L LXI SP Load immediate stack pointer PUSH B Push register Pair B& C on stack PUSH 0 Push register Pair 0 & E on stack PUSH H Push register Pair H& L on stack PUSH PSW Push A and Flags on stack POP B Pop register pair B & C off stack POP 0 Pop register pair 0 & E off stack POP H Pop register pair H& L off stack POP PSW Pop A and Flags off stack Store A direct STA LOA Load A direct XCHG Exchange 0 &E. H& L Registers XTHL Excnange top of stack, H& L SPHL H& L to stack pointer PCHL H& L to program counter DAD B Add B & C to H& L DAD 0 Add D & E to H& L DAD H Add H& L to H& L DAD SP Add stack pointer to H& L STAX B Store A indirect STAX 0 Store A indirect Load A indirect LOAX B Load A indirect LOAX 0 INX B Increment B& C registers INX 0 Increment 0 & E registers INX H Increment H& L registers INX SP Increment stack pointer OCX B Decrement B & C OCX 0 Decrement 0 & E OCX H Decrement H& L OCX SP Decrement stack pointer Complement A CMA STC Set carry CMC Complement carry OAA Decimal adjust A SHLO Store H& L direct LHLO Load H& L direct EI Enable Interrupts 01 Disable interrupt NOP No-operation 1. DOD or SSS - 000 B - 001 C - 010 0 - 011 E - 100 H - 101 L - 110 Memory - 111 A. 2. Two possible cycle times, (5/11) indicate instruction cycles dependent on condition flags. Instruction Code 11 J Os 04 03 02 0, Do 0 0 1 1 1 1 A 0 0 0 0 0 1 1 0 0 A 1 1 0 '1 0 0 1 1 0 A 1 0 0 0 0 0 0 0 0 1 0 0 0 0 C 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 Clock (2) Cycles 5/11 5/11 5/11 5/11 5/11 5/11 11 10 10 10 10 10 10 11 11 11 11 10 10 10 10 0 0 0 1 1 1 0 (l 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 . 0 1 1 0 1 1 1 0 1 0 0 1 0 1 0 0 0 0 0 13 13 4 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 18 5 5 10 10 10 10 7 7 7 7 5 5 5 5 5 5 5 5 4 4 4 4 16 16 4 4 4 ~ INSTRUCTION SET Summary of Processor Instructions By Alphabetical Order Mnemonic Desaiptioll ACI Add immediate to A with tarry Add memory to A with tarry Add register to A with carry Add memory to A Add register to A Add immediate to A And memory with A And register with A And immediate with A Call ullCondi1ional Call on carry Call on minus Compliment A Compliment carry Compare memory with A Compare register with A Call on no carry Call on no lero Call on positive Call on parity even Compare immediate with A Call on parity odd Call OnltrO Decimal adjust A Add a & Cto H & L Add 0 & E to H & L Add H & Lto H & L Add stack pointer to H & L Decrement memory Decrement register Decrement B & C Decrement 0 & E Decrement H & L Decrement stack po inter Disable Interrupt Enable Interrupts Halt Input Increment memory Increment register Increment a & Cregisters Increment 0 & Eregisters Increment H & Lregisters Increment stack pointer Jump on carry Jump on minus Jump unconditional Jump on no carry Jump on no lero Jump on positive Jump on parity even Jump on parity odd Jump onlero Load A direct Load A indirect Load A indirect Load H & Ldinct Load immediate register Pair a & C Load immediate register Pair 0 & E Load immediate register Pair H & L Load immed iate steck pointer AOC M ADCr ADD M AOOr AOI ANAM ANAr ANI CALL CC CM Cl1A CMC CMPM CMPr CNC CNZ CP CPE CPI CPO CZ DAA DAD a DAD 0 DAD H DAD SP OCR M OCR r DCX 8 DCX D OCX H OCXSP 01 EI HLT IN INR M INR r INX8 INX 0 INX H INXSP JC JM JMP JNC JNZ JP JPE JPO JZ LOA LOAXa LOAX 0 LHLD LXI8 LXIO LXI H LXI SP 07 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 I 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 06 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 I 1 1 1 1 1 1 1 0 0 0 0 0 Instrumon Cod.lll 0 5 04 03 02 0 0 0 0 0 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 1 1 0 1 0 0 1 0 0 D 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 1 0 1 0 0 0 0 1 0 1 1 D 0 1 0 1 1 1 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 I 1 0 0 0 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 D 0 0 0 0 1 1 0 0 0 0 1 0 1 1 1 1 1 0 01 DO 1 S 1 S 1 1 S 1 1 1 I 1 1 1 S 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 Clock121 Cychs 7 4 7 4 7 7 4 7 17 11/17 11/17 4 4 7 4 11/17 11/17 11/17 11/17 7 11/17 11/17 4 10 10 10 10 10 5 5 5 5 5 4 4 7 10 10 5 5 5 5 5 10 10 10 10 10 10 10 10 10 13 7 7 16 10 10 Mn.mollie Description MVI M MVlr MOVM.r MOVr,M MOV rt ,r2 NOP DRAM ORAr ORI OUT PCHL POP 8 Move immediate memory Move immediate register Move register to memory Move memory to register Move register to register No-operation Or memory with A Or register with A Or immediate with A Output H & L to program counter Pop regi$ter pair a & Coff stick Pop register pair 0 & E off stack Pop register pair H & L off stack Pop Aand Flags all stack Push register Pa ir 8 & Con stack Push register Pair 0 & Eon stack Push register Pair H & L on stack Push Aand Flags on stack Rotlle A left through carry Rolate A right through carry Return on carry Return Rotate A left Return on minus Return on no carry Return on no lero Relurn on positive Return on parity even Return on parity odd Rotate A right Restart Return on lero Subtract memory Irom A with borrow Subtract register from A with borrow Subtract immediate from A with borrow Slore H & Ldirect H & Lto stack pointer Store A direct Slore A indirect Store A indirect Sel ClIrry Subtract memory from A Subtract register Ira m A Subtrlct immediate from A Exchange 0 & E. H & L Registers Exclusive Or memory with A Exclusive Or register with A Exclusive Or immediate with A Exchange to p 01 stack, H & L pop 0 POP H POP PSW PUSH 8 PUSH 0 PUSH H PUSH PSW RAL RAR RC RET RLC RM RNC RNZ RP RPE RPO RRC RST RZ SaB M SBa r S81 SHLO SPHL STA STAX 8 STAX 0 STC SUB M SU8 r SUI XCHG XRAM XRA r XRI 10 XTHL 10 NOT ES: 1. 0 DO or SSS - 000 B - 001 C - 010 0 - 011 E - 1OOH - 101 L - 110 Memory - 111 A. 2. Two possible cycle times, (5/11) indicate instruction cycles dependent on condition flags. 07 06 Illstrudion Cod.(1) 05 04 03 02 1 D 1 0 0 0 1 1 1 0 1 0 1 D 1 D D 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 S 1 S 0 1 S 1 0 0 0 01 Do C1cckl2J Cychs 1 1 S 1 S 0 1 S 1 1 0 0 0 0 S 0 S 0 0 S 0 1 1 1 10 7 7 7 5 4 7 4 7 10 5 10 10 10 10 11 11 11 11 0 0 0 1 0 0 1 1 1 0 A 0 0 1 1 0 0 1 1 0 1 0 0 0 A 0 1 I 0 0 0 1 0 0 0 1 0 1 A 1 1 0 0 0 0 0 0 1 1 0 1 5'11 10 4 5'11 5'11 5'11 5111 5'11 5'11 4 11 5'11 7 1 0 0 0 0 0 1 1 S 1 0 0 1 0 0 0 1 0 S 0 1 16 5 13 7 7 4 7 4 7 4 18 Dear Customer, Please fill out the card below completely to make sure your name is entered accurately on the MCS-BO Registered Users List. This assures you of getting the latest information on all new MCS-BO Product Developments and Application Literature. Any comments or suggestions regarding MCS-BO would be appreciated. Sincerely, Ken McKenzie MCS-BO Product Manager 8080 MICROCOMPUTER SYSTEM USERS REGISTRATION CARD (Please Print) Name .,..-_ _ Title _ Company ~_ _- - - - - - - - - _ Address -"'- --==__ City _ Mail Stop _ State ZipCode _ _ Application Peripherals D Floppy Disk D Line Printer D Stepper D Mag Cassette D Keyboard D Servo D Paper Tape Other: ROM k Bytes Inports RAM Outports DMA Chan~els # Interrupts # Communication Interface D ASYNC D Baud Rate SYNC D Baud Rate SDLC D Baud Rate OTHER D Baud Rate k Bytes ··1 BJ lt~ .- e E c PLACE STAMP HERE c @ .S=! ~ :s .. c LC INTEL CORPORATION Microcomputer Systems 3065 Bowers Avenue Santa Clara, CA 95051 inter INTEL CORPORATION 3065 Bowers Avenue, Santa Clara. California 95051 (408) 246-7501 Primed in U.5.A.fMC5-662-Q975/40K
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