Intel Video Game Controller Gigabit Ethernet Controllers Users Manual 8254x Family Of Software Developer’s
Intel Gigabit Ethernet Controllers to the manual 52760d54-ea50-44bc-960c-7c6b40914c50
2015-02-02
: Intel Intel-Intel-Video-Game-Controller-Intel-Gigabit-Ethernet-Controllers-Users-Manual-432899 intel-intel-video-game-controller-intel-gigabit-ethernet-controllers-users-manual-432899 intel pdf
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- Introduction 1
- Architectural Overview 2
- Receive and Transmit Description 3
- 3.1 Introduction
- 3.2 Packet Reception
- 3.3 Packet Transmission
- 3.4 Transmit Descriptor Ring Structure
- 3.5 TCP Segmentation
- 3.5.1 Assumptions
- 3.5.2 Transmission Process
- 3.5.3 TCP Segmentation Performance
- 3.5.4 Packet Format
- 3.5.5 TCP Segmentation Indication
- 3.5.6 TCP Segmentation Use of Multiple Data Descriptors
- 3.5.7 IP and TCP/UDP Headers
- 3.5.8 Transmit Checksum Offloading with TCP Segmentation
- 3.5.9 IP/TCP/UDP Header Updating
- 3.6 IP/TCP/UDP Transmit Checksum Offloading
- PCI Local Bus Interface 4
- EEPROM Interface 5
- 5.1 General Overview
- 5.2 Component Identification Via Programming Interface
- 5.3 EEPROM Device and Interface
- 5.4 Signature and CRC Fields
- 5.5 EEUPDATE Utility
- 5.6 EEPROM Address Map
- 5.6.1 Ethernet Address (Words 00h-02h)
- 5.6.2 Software Compatibility Word (Word 03h)
- 5.6.3 SerDes Configuration (Word 04h)
- 5.6.4 EEPROM Image Version (Word 05h)
- 5.6.5 Compatibility Fields (Word 05h - 07h)
- 5.6.6 PBA Number (Word 08h, 09h)
- 5.6.7 Initialization Control Word 1 (Word 0Ah)
- 5.6.8 Subsystem ID (Word 0Bh)
- 5.6.9 Subsystem Vendor ID (Word 0Ch)
- 5.6.10 Device ID (Word 0Dh, 11h)
- 5.6.11 Vendor ID (Word 0Eh)
- 5.6.12 Initialization Control Word 2 (Word 0Fh)
- 5.6.13 PHY Register Address Data (Words 10h, 11h, and 13h - 1Eh)
- 5.6.14 OEM Reserved Words (Words 10h, 11h, 13h - 1Fh)
- 5.6.15 EEPROM Size (Word 12h)
- 5.6.16 Common Power (Word 12h)
- 5.6.17 Software Defined Pins Control (Word 10h, 20h)
- 5.6.18 CSA Port Configuration 2 (Word 21h)
- 5.6.19 Circuit Control (Word 21h)
- 5.6.20 D0 Power (Word 22h high byte)
- 5.6.21 D3 Power (Word 22h low byte)
- 5.6.22 Reserved Words (23h - 2Eh)
- 5.6.23 Reserved Words (23h - 2Fh)
- 5.6.24 Management Control (Word 13h, 23h)
- 5.6.25 SMBus Slave Address (Word 14h low byte, 24h low byte)
- 5.6.26 Initialization Control 3 (Word 14h high byte, 24h high byte)
- 5.6.27 IPv4 Address (Words 15h - 16h and 25h - 26h)
- 5.6.28 IPv6 Address (words 17h - 1Eh1 and 27h - 2Eh)
- 5.6.29 LED Configuration Defaults (Word 2Fh)
- 5.6.30 Boot Agent Main Setup Options (Word 30h)
- 5.6.31 Boot Agent Configuration Customization Options (Word 31h)
- 5.6.32 Boot Agent Configuration Customization Options (Word 32h)
- 5.6.33 IBA Capabilities (Word 33h)
- 5.6.34 IBA Secondary Port Configuration (Words 34h-35h)
- 5.6.35 Checksum Word Calculation (Word 3Fh)
- 5.6.36 82546GB/EB Dual-Channel Fiber Wake on LAN (WOL) Mode and Functionality (Word 0Ah, 20h)
- 5.6.37 EEPROM Images
- 5.7 Parallel FLASH Memory
- FLASH Memory Interface 7
- Power Management 6
- 6.1 Introduction to Power Management
- 6.2 Assumptions
- 6.3 D3cold support
- 6.3.1 Power States
- 6.3.2 Timing
- 6.3.3 PCI Power Management Registers
- 6.3.3.1 Capability ID 1 Byte Offset = 0 (RO)
- 6.3.3.2 Next Item Pointer 1 Byte Offset = 1 (RO)
- 6.3.3.3 Power Management Capabilities - (PMC) 2 Bytes Offset = 2 (RO)
- 6.3.3.4 Power Management Control / Status Register - (PMCSR) 2 Bytes Offset = 4 (RO)
- 6.3.3.5 PMCSR_BSE Bridge Support Extensions 1 Byte Offset = 6 (RO)
- 6.3.3.6 Data Register 1 Byte Offset = 7 (RO)
- 6.4 Wakeup
- Ethernet Interface 8
- 8.1 Introduction
- 8.2 Link Interfaces Overview
- 8.3 Internal Interface
- 8.4 Duplex Operation
- 8.5 Auto-Negotiation and Link Setup
- 8.6 Auto-Negotiation and Link Setup
- 8.7 10/100 Mb/s Specific Performance Enhancements
- 802.1q VLAN Support 9
- Configurable LED Outputs 10
- PHY Functionality and Features 11
- 11.1 Auto-Negotiation
- 11.2 MDI/MDI-X Crossover (copper only)
- 11.3 Cable Length Detection (copper only)
- 11.4 PHY Power Management (copper only)
- 11.5 Initialization
- 11.6 Determining Link State
- 11.7 Link Criteria
- 11.8 Link Enhancements
- 11.9 Management Data Interface
- 11.10 Low Power Operation
- 11.11 1000 Mbps Operation
- 11.12 100 Mbps Operation
- 11.13 10 Mbps Operation
- 11.14 PHY Line Length Indication
- Dual Port Characteristics 12
- Register Descriptions 13
- 13.1 Introduction
- 13.2 Register Conventions
- 13.3 PCI-X Register Access Split
- 13.4 Main Register Descriptions
- 13.4.1 Device Control Register
- 13.4.2 Device Status Register
- 13.4.3 EEPROM/Flash Control & Data Register
- 13.4.4 EEPROM Read Register
- 13.4.5 Flash Access
- 13.4.6 Extended Device Control Register
- 13.4.7 MDI Control Register
- 13.4.8 Flow Control Address Low
- 13.4.9 Flow Control Address High
- 13.4.10 Flow Control Type
- 13.4.11 VLAN Ether Type
- 13.4.12 Flow Control Transmit Timer Value
- 13.4.13 Transmit Configuration Word Register
- 13.4.14 Receive Configuration Word Register
- 13.4.15 LED Control
- 13.4.16 Packet Buffer Allocation
- 13.4.17 Interrupt Cause Read Register
- 13.4.18 Interrupt Throttling Register
- 13.4.19 Interrupt Cause Set Register
- 13.4.20 Interrupt Mask Set/Read Register
- 13.4.21 Interrupt Mask Clear Register
- 13.4.22 Receive Control Register
- 13.4.23 Flow Control Receive Threshold Low
- 13.4.24 Flow Control Receive Threshold High
- 13.4.25 Receive Descriptor Base Address Low
- 13.4.26 Receive Descriptor Base Address High
- 13.4.27 Receive Descriptor Length
- 13.4.28 Receive Descriptor Head
- 13.4.29 Receive Descriptor Tail
- 13.4.30 Receive Delay Timer Register
- 13.4.31 Receive Interrupt Absolute Delay Timer
- 13.4.32 Receive Small Packet Detect Interrupt
- 13.4.33 Transmit Control Register
- 13.4.34 Transmit IPG Register
- 13.4.35 Adaptive IFS Throttle - AIT
- 13.4.36 Transmit Descriptor Base Address Low
- 13.4.37 Transmit Descriptor Base Address High
- 13.4.38 Transmit Descriptor Length
- 13.4.39 Transmit Descriptor Head
- 13.4.40 Transmit Descriptor Tail
- 13.4.41 Transmit Interrupt Delay Value
- 13.4.42 TX DMA Control (82544GC/EI only)
- 13.4.43 Transmit Descriptor Control
- 13.4.44 Transmit Absolute Interrupt Delay Value
- 13.4.45 TCP Segmentation Pad And Minimum Threshold
- 13.4.46 Receive Descriptor Control
- 13.4.47 Receive Checksum Control
- 13.5 Filter Registers
- 13.6 Wakeup Registers
- 13.6.1 Wakeup Control Register
- 13.6.2 Wakeup Filter Control Register
- 13.6.3 Wakeup Status Register
- 13.6.4 IP Address Valid
- 13.6.5 IPv4 Address Table
- 13.6.6 IPv6 Address Table
- 13.6.7 Wakeup Packet Length
- 13.6.8 Wakeup Packet Memory (128 Bytes)
- 13.6.9 Flexible Filter Length Table
- 13.6.10 Flexible Filter Mask Table
- 13.6.11 Flexible Filter Value Table
- 13.7 Statistics Registers
- 13.7.1 CRC Error Count
- 13.7.2 Alignment Error Count
- 13.7.3 Symbol Error Count
- 13.7.4 RX Error Count
- 13.7.5 Missed Packets Count
- 13.7.6 Single Collision Count
- 13.7.7 Excessive Collisions Count
- 13.7.8 Multiple Collision Count
- 13.7.9 Late Collisions Count
- 13.7.10 Collision Count
- 13.7.11 Defer Count
- 13.7.12 Transmit with No CRS
- 13.7.13 Sequence Error Count
- 13.7.14 Carrier Extension Error Count
- 13.7.15 Receive Length Error Count
- 13.7.16 XON Received Count
- 13.7.17 XON Transmitted Count
- 13.7.18 XOFF Received Count
- 13.7.19 XOFF Transmitted Count
- 13.7.20 FC Received Unsupported Count
- 13.7.21 Packets Received (64 Bytes) Count
- 13.7.22 Packets Received (65-127 Bytes) Count
- 13.7.23 Packets Received (128-255 Bytes) Count
- 13.7.24 Packets Received (256-511 Bytes) Count
- 13.7.25 Packets Received (512-1023 Bytes) Count
- 13.7.26 Packets Received (1024 to Max Bytes) Count
- 13.7.27 Good Packets Received Count
- 13.7.28 Broadcast Packets Received Count
- 13.7.29 Multicast Packets Received Count
- 13.7.30 Good Packets Transmitted Count
- 13.7.31 Good Octets Received Count
- 13.7.32 Good Octets Transmitted Count
- 13.7.33 Receive No Buffers Count
- 13.7.34 Receive Undersize Count
- 13.7.35 Receive Fragment Count
- 13.7.36 Receive Oversize Count
- 13.7.37 Receive Jabber Count
- 13.7.38 Management Packets Received Count
- 13.7.39 Management Packets Dropped Count1
- 13.7.40 Management Pkts Transmitted Count
- 13.7.41 Total Octets Received
- 13.7.42 Total Octets Transmitted
- 13.7.43 Total Packets Received
- 13.7.44 Total Packets Transmitted
- 13.7.45 Packets Transmitted (64 Bytes) Count
- 13.7.46 Packets Transmitted (65-127 Bytes) Count
- 13.7.47 Packets Transmitted (128-255 Bytes) Count
- 13.7.48 Packets Transmitted (256-511 Bytes) Count
- 13.7.49 Packets Transmitted (512-1023 Bytes) Count
- 13.7.50 Packets Transmitted (1024 Bytes or Greater) Count
- 13.7.51 Multicast Packets Transmitted Count
- 13.7.52 Broadcast Packets Transmitted Count
- 13.7.53 TCP Segmentation Context Transmitted Count
- 13.7.54 TCP Segmentation Context Transmit Fail Count
- 13.8 Diagnostics Registers
- 13.8.1 Receive Data FIFO Head Register
- 13.8.2 Receive Data FIFO Tail Register
- 13.8.3 Receive Data FIFO Head Saved Register
- 13.8.4 Receive Data FIFO Tail Saved Register
- 13.8.5 Receive Data FIFO Packet Count
- 13.8.6 Transmit Data FIFO Head Register
- 13.8.7 Transmit Data FIFO Tail Register
- 13.8.8 Transmit Data FIFO Head Saved Register
- 13.8.9 Transmit Data FIFO Tail Saved Register
- 13.8.10 Transmit Data FIFO Packet Count
- 13.8.11 Packet Buffer Memory
- General Initialization and Reset Operation 14
- Diagnostics and Testability 15
- Appendix (Changes From 82544EI/82544GC) A
- Appendix (82540EP/EM and 82545GM/EM Differences) B