Intel Video Game Controller Gigabit Ethernet Controllers Users Manual 8254x Family Of Software Developer’s

2015-02-02

• Introduction 1
  • 1.1 Scope
  • 1.2 Overview
  • 1.3 Ethernet Controller Features
    • 1.3.1 PCI Features
    • 1.3.2 CSA Features (82547GI/EI Only)
    • 1.3.3 Network Side Features
    • 1.3.4 Host Offloading Features
    • 1.3.5 Additional Performance Features
    • 1.3.6 Manageability Features (Not Applicable to the 82544GC/EI or 82541ER)
    • 1.3.7 Additional Ethernet Controller Features
    • 1.3.8 Technology Features
  • 1.4 Conventions
    • 1.4.1 Register and Bit References
    • 1.4.2 Byte and Bit Designations
  • 1.5 Related Documents
  • 1.6 Memory Alignment Terminology
• Architectural Overview 2
  • 2.1 Introduction
  • 2.2 External Architecture
  • 2.3 Microarchitecture
    • 2.3.1 PCI/PCI-X Core Interface
    • 2.3.2 82547GI/EI CSA Interface
    • 2.3.3 DMA Engine and Data FIFO
    • 2.3.4 10/100/1000 Mb/s Receive and Transmit MAC Blocks
    • 2.3.5 MII/GMII/TBI/Internal SerDes Interface Block
    • 2.3.6 10/100/1000 Ethernet Transceiver (PHY)
    • 2.3.7 EEPROM Interface
    • 2.3.8 FLASH Memory Interface
  • 2.4 DMA Addressing
  • 2.5 Ethernet Addressing
  • 2.6 Interrupts
  • 2.7 Hardware Acceleration Capability
    • 2.7.1 Checksum Offloading
    • 2.7.2 TCP Segmentation
  • 2.8 Buffer and Descriptor Structure
• Receive and Transmit Description 3
  • 3.1 Introduction
  • 3.2 Packet Reception
    • 3.2.1 Packet Address Filtering
    • 3.2.2 Receive Data Storage
    • 3.2.3 Receive Descriptor Format
      • 3.2.3.1 Receive Descriptor Status Field
      • 3.2.3.2 Receive Descriptor Errors Field
      • 3.2.3.3 Receive Descriptor Special Field
    • 3.2.4 Receive Descriptor Fetching
    • 3.2.5 Receive Descriptor Write-Back
      • 3.2.5.1 Receive Descriptor Packing
      • 3.2.5.2 Null Descriptor Padding
    • 3.2.6 Receive Descriptor Queue Structure
    • 3.2.7 Receive Interrupts
      • 3.2.7.1 Receive Timer Interrupt
      • 3.2.7.2 Small Receive Packet Detect
      • 3.2.7.3 Receive Descriptor Minimum Threshold (ICR.RXDMT)
      • 3.2.7.4 Receiver FIFO Overrun
    • 3.2.8 82544GC/EI Receive Interrupts
    • 3.2.9 Receive Packet Checksum Offloading
      • 3.2.9.1 MAC Address Filter
      • 3.2.9.2 SNAP/VLAN Filter
      • 3.2.9.3 IPv4 Filter
      • 3.2.9.4 IPv6 Filter
      • 3.2.9.5 UDP/TCP Filter
  • 3.3 Packet Transmission
    • 3.3.1 Transmit Data Storage
    • 3.3.2 Transmit Descriptors
    • 3.3.3 Legacy Transmit Descriptor Format
      • 3.3.3.1 Transmit Descriptor Command Field Format
      • 3.3.3.2 Transmit Descriptor Status Field Format
    • 3.3.4 Transmit Descriptor Special Field Format
    • 3.3.5 TCP/IP Context Transmit Descriptor Format
    • 3.3.6 TCP/IP Context Descriptor Layout
      • 3.3.6.1 TCP/UDP Offload Transmit Descriptor Command Field
      • 3.3.6.2 TCP/UDP Offload Transmit Descriptor Status Field
    • 3.3.7 TCP/IP Data Descriptor Format
      • 3.3.7.1 TCP/IP Data Descriptor Command Field
      • 3.3.7.2 TCP/IP Data Descriptor Status Field
      • 3.3.7.3 TCP/IP Data Descriptor Option Field
      • 3.3.7.4 TCP/IP Data Descriptor Special Field
  • 3.4 Transmit Descriptor Ring Structure
    • 3.4.1 Transmit Descriptor Fetching
    • 3.4.2 Transmit Descriptor Write-back
    • 3.4.3 Transmit Interrupts
      • 3.4.3.1 Delayed Transmit Interrupts
  • 3.5 TCP Segmentation
    • 3.5.1 Assumptions
    • 3.5.2 Transmission Process
      • 3.5.2.1 TCP Segmentation Data Fetch Control
    • 3.5.3 TCP Segmentation Performance
    • 3.5.4 Packet Format
    • 3.5.5 TCP Segmentation Indication
    • 3.5.6 TCP Segmentation Use of Multiple Data Descriptors
    • 3.5.7 IP and TCP/UDP Headers
    • 3.5.8 Transmit Checksum Offloading with TCP Segmentation
    • 3.5.9 IP/TCP/UDP Header Updating
      • 3.5.9.1 TCP/IP/UDP Header for the First Frame
      • 3.5.9.2 TCP/IP/UDP Header for the Subsequent Frames
      • 3.5.9.3 TCP/IP/UDP Header for the Last Frame
  • 3.6 IP/TCP/UDP Transmit Checksum Offloading
• PCI Local Bus Interface 4
  • 4.1 PCI Configuration
    • 4.1.1 PCI-X Configuration Registers
      • 4.1.1.1 PCI-X Capability ID
      • 4.1.1.2 Next Capability
      • 4.1.1.3 PCI-X Command
      • 4.1.1.4 PCI-X Status
    • 4.1.2 Reserved and Undefined Addresses
    • 4.1.3 Message Signaled Interrupts
      • 4.1.3.1 Message Signaled Interrupt Configuration Registers
  • 4.2 Commands
  • 4.3 PCI/PCI-X Command Usage
    • 4.3.1 Memory Write Operations
      • 4.3.1.1 MWI Bursts
      • 4.3.1.2 MW Bursts
    • 4.3.2 Memory Read Operations
      • 4.3.2.1 PCI-X Command Usage
  • 4.4 Cache Line Information
    • 4.4.1 Target Transaction Termination
  • 4.5 Interrupt Assignment (82547GI/EI Only)
  • 4.6 LAN Disable
  • 4.7 CardBus Application (82541PI/GI/EI Only)
• EEPROM Interface 5
  • 5.1 General Overview
  • 5.2 Component Identification Via Programming Interface
  • 5.3 EEPROM Device and Interface
    • 5.3.1 Software Access
  • 5.4 Signature and CRC Fields
  • 5.5 EEUPDATE Utility
    • 5.5.1 Command Line Parameters
  • 5.6 EEPROM Address Map
    • 5.6.1 Ethernet Address (Words 00h-02h)
    • 5.6.2 Software Compatibility Word (Word 03h)
    • 5.6.3 SerDes Configuration (Word 04h)
    • 5.6.4 EEPROM Image Version (Word 05h)
    • 5.6.5 Compatibility Fields (Word 05h - 07h)
    • 5.6.6 PBA Number (Word 08h, 09h)
    • 5.6.7 Initialization Control Word 1 (Word 0Ah)
    • 5.6.8 Subsystem ID (Word 0Bh)
    • 5.6.9 Subsystem Vendor ID (Word 0Ch)
    • 5.6.10 Device ID (Word 0Dh, 11h)
    • 5.6.11 Vendor ID (Word 0Eh)
    • 5.6.12 Initialization Control Word 2 (Word 0Fh)
    • 5.6.13 PHY Register Address Data (Words 10h, 11h, and 13h - 1Eh)
    • 5.6.14 OEM Reserved Words (Words 10h, 11h, 13h - 1Fh)
    • 5.6.15 EEPROM Size (Word 12h)
    • 5.6.16 Common Power (Word 12h)
    • 5.6.17 Software Defined Pins Control (Word 10h, 20h)
    • 5.6.18 CSA Port Configuration 2 (Word 21h)
    • 5.6.19 Circuit Control (Word 21h)
    • 5.6.20 D0 Power (Word 22h high byte)
    • 5.6.21 D3 Power (Word 22h low byte)
    • 5.6.22 Reserved Words (23h - 2Eh)
    • 5.6.23 Reserved Words (23h - 2Fh)
    • 5.6.24 Management Control (Word 13h, 23h)
    • 5.6.25 SMBus Slave Address (Word 14h low byte, 24h low byte)
    • 5.6.26 Initialization Control 3 (Word 14h high byte, 24h high byte)
    • 5.6.27 IPv4 Address (Words 15h - 16h and 25h - 26h)
    • 5.6.28 IPv6 Address (words 17h - 1Eh1 and 27h - 2Eh)
    • 5.6.29 LED Configuration Defaults (Word 2Fh)
    • 5.6.30 Boot Agent Main Setup Options (Word 30h)
    • 5.6.31 Boot Agent Configuration Customization Options (Word 31h)
    • 5.6.32 Boot Agent Configuration Customization Options (Word 32h)
    • 5.6.33 IBA Capabilities (Word 33h)
    • 5.6.34 IBA Secondary Port Configuration (Words 34h-35h)
    • 5.6.35 Checksum Word Calculation (Word 3Fh)
    • 5.6.36 82546GB/EB Dual-Channel Fiber Wake on LAN (WOL) Mode and Functionality (Word 0Ah, 20h)
    • 5.6.37 EEPROM Images
  • 5.7 Parallel FLASH Memory
• FLASH Memory Interface 7
  • 7.1 FLASH Interface Operation
  • 7.2 FLASH Control and Accesses
    • 7.2.1 Read Accesses
    • 7.2.2 Write Accesses
• Power Management 6
  • 6.1 Introduction to Power Management
  • 6.2 Assumptions
  • 6.3 D3cold support
    • 6.3.1 Power States
      • 6.3.1.1 Dr State
      • 6.3.1.2 D0u State
      • 6.3.1.3 D0a (D0 active)
      • 6.3.1.4 D3
    • 6.3.2 Timing
      • 6.3.2.1 Power Up (Off to Dr to D0u to D0a)
      • 6.3.2.2 Transition From D0a to D3 and Back Without PCI Reset
      • 6.3.2.3 Transition From D0a to D3 and Back with PCI Reset
      • 6.3.2.4 PCI Reset Without Transition to D3
    • 6.3.3 PCI Power Management Registers
      • 6.3.3.1 Capability ID 1 Byte Offset = 0 (RO)
      • 6.3.3.2 Next Item Pointer 1 Byte Offset = 1 (RO)
      • 6.3.3.3 Power Management Capabilities - (PMC) 2 Bytes Offset = 2 (RO)
      • 6.3.3.4 Power Management Control / Status Register - (PMCSR) 2 Bytes Offset = 4 (RO)
      • 6.3.3.5 PMCSR_BSE Bridge Support Extensions 1 Byte Offset = 6 (RO)
      • 6.3.3.6 Data Register 1 Byte Offset = 7 (RO)
  • 6.4 Wakeup
    • 6.4.1 Advanced Power Management Wakeup
    • 6.4.2 ACPI Power Management Wakeup
    • 6.4.3 Wakeup Packets
      • 6.4.3.1 Pre-Defined Filters
      • 6.4.3.2 Directed IPv6 Packet
      • 6.4.3.3 Flexible Filter
      • 6.4.3.4 IPv6 Neighbor Discovery Filter
      • 6.4.3.5 Wakeup Packet Storage
• Ethernet Interface 8
  • 8.1 Introduction
  • 8.2 Link Interfaces Overview
    • 8.2.1 Internal SerDes Interface/TBI Mode- 1Gb/s
      • 8.2.1.1 Gigabit Physical Coding Sub-Layer (PCS) for the Internal SerDes
      • 8.2.1.2 8B10B Encoding/Decoding
      • 8.2.1.3 Code Groups and Ordered Sets
    • 8.2.2 GMII - 1 Gb/s
    • 8.2.3 MII - 10/100 Mb/s
  • 8.3 Internal Interface
  • 8.4 Duplex Operation
    • 8.4.1 Full Duplex
    • 8.4.2 Half Duplex
      • 8.4.2.1 Carrier Extension (1000 Mb/s Only)
      • 8.4.2.2 Packet Bursting
  • 8.5 Auto-Negotiation and Link Setup
  • 8.6 Auto-Negotiation and Link Setup
    • 8.6.1 Link Configuration in Internal Serdes/TBI Mode
      • 8.6.1.1 Link Speed
      • 8.6.1.2 Auto-Negotiation
      • 8.6.1.3 Hardware Auto-Negotiation
      • 8.6.1.4 Software Auto-Negotiation
      • 8.6.1.5 Forcing Link
    • 8.6.2 Internal GMII/MII Mode
      • 8.6.2.1 Auto-Negotiation
      • 8.6.2.2 Link Speed
      • 8.6.2.3 Duplex
      • 8.6.2.4 MII Management Registers
      • 8.6.2.5 Comments Regarding Forcing Link
    • 8.6.3 Internal SerDes Mode Control Bit Resolution
    • 8.6.4 Internal PHY Mode Control Bit Resolution
    • 8.6.5 Loss of Signal/Link Status Indication
      • 8.6.5.1 Internal Serdes Mode
      • 8.6.5.2 Internal PHY Mode
  • 8.7 10/100 Mb/s Specific Performance Enhancements
    • 8.7.1 Adaptive IFS
    • 8.7.2 Flow Control
    • 8.7.3 MAC Control Frames & Reception of Flow Control Packets
    • 8.7.4 Discard PAUSE Frames and Pass MAC Control Frames
    • 8.7.5 Transmission of PAUSE Frames
    • 8.7.6 Software Initiated PAUSE Frame Transmission
    • 8.7.7 External Control of Flow Control Operation
• 802.1q VLAN Support 9
  • 9.1 802.1q VLAN Packet Format
    • 9.1.1 802.1q Tagged Frames
  • 9.2 Transmitting and Receiving 802.1q Packets
    • 9.2.1 Adding 802.1q Tags on Transmits
    • 9.2.2 Stripping 802.1q Tags on Receives
  • 9.3 802.1q VLAN Packet Filtering
• Configurable LED Outputs 10
  • 10.1 Configurable LED Outputs
    • 10.1.1 Selecting an LED Output Source
    • 10.1.2 Polarity Inversion
    • 10.1.3 Blink Control
• PHY Functionality and Features 11
  • 11.1 Auto-Negotiation
    • 11.1.1 Overview
    • 11.1.2 Next Page Exchanges
    • 11.1.3 Register Update
    • 11.1.4 Status
  • 11.2 MDI/MDI-X Crossover (copper only)
    • 11.2.1 Polarity Correction (copper only)
    • 11.2.2 10/100 Downshift (82540EP/EM Only)
  • 11.3 Cable Length Detection (copper only)
  • 11.4 PHY Power Management (copper only)
    • 11.4.1 Link Down - Energy Detect (copper only)
    • 11.4.2 D3 State, No Link Required (copper only)
    • 11.4.3 D3 Link-Up, Speed-Management Enabled (copper only)
    • 11.4.4 D3 Link-Up, Speed-Management Disabled (copper only)
  • 11.5 Initialization
    • 11.5.1 MDIO Control Mode
  • 11.6 Determining Link State
    • 11.6.1 False Link
    • 11.6.2 Forced Operation
    • 11.6.3 Auto Negotiation
    • 11.6.4 Parallel Detection
  • 11.7 Link Criteria
    • 11.7.1 1000BASE-T
    • 11.7.2 100BASE-TX
    • 11.7.3 10BASE-T
  • 11.8 Link Enhancements
    • 11.8.1 SmartSpeed
      • 11.8.1.1 Using SmartSpeed
    • 11.8.2 Flow Control
  • 11.9 Management Data Interface
  • 11.10 Low Power Operation
    • 11.10.1 Powerdown via the PHY Register
    • 11.10.2 Smart Power-Down
  • 11.11 1000 Mbps Operation
    • 11.11.1 Introduction
    • 11.11.2 Transmit Functions
      • 11.11.2.1 Scrambler
    • 11.11.3 Transmit FIFO
      • 11.11.3.1 Transmit Phase-Locked Loop PLL
      • 11.11.3.2 Trellis Encoder
      • 11.11.3.3 4DPAM5 Encoder
      • 11.11.3.4 Spectral Shaper
      • 11.11.3.5 Low-Pass Filter
      • 11.11.3.6 Line Driver
      • 11.11.3.7 Transmit/Receive Flow
    • 11.11.4 Receive Functions
      • 11.11.4.1 Hybrid
      • 11.11.4.2 Automatic Gain Control
      • 11.11.4.3 Timing Recovery
      • 11.11.4.4 Analog-to-Digital Converter
      • 11.11.4.5 Digital Signal Processor
      • 11.11.4.6 Descrambler
      • 11.11.4.7 Viterbi Decoder/Decision Feedback Equalizer (DFE)
      • 11.11.4.8 4DPAM5 Decoder
  • 11.12 100 Mbps Operation
  • 11.13 10 Mbps Operation
    • 11.13.1 Link Test
    • 11.13.2 10Base-T Link Failure Criteria and Override
    • 11.13.3 Jabber
    • 11.13.4 Polarity Correction
    • 11.13.5 Dribble Bits
  • 11.14 PHY Line Length Indication
• Dual Port Characteristics 12
  • 12.1 Introduction
  • 12.2 Features of Each MAC
    • 12.2.1 PCI/PCI-X interface
    • 12.2.2 MAC Configuration Register Space
    • 12.2.3 SDP, LED, INT# output
  • 12.3 Shared EEPROM
    • 12.3.1 EEPROM Map
    • 12.3.2 EEPROM Arbitration
  • 12.4 Shared FLASH
    • 12.4.1 FLASH Access Contention
  • 12.5 LAN Disable
    • 12.5.1 Overview
    • 12.5.2 Values Sampled on Reset
    • 12.5.3 Multi-Function Advertisement
    • 12.5.4 Interrupt Use
    • 12.5.5 Power Reporting
    • 12.5.6 Summary
• Register Descriptions 13
  • 13.1 Introduction
  • 13.2 Register Conventions
    • 13.2.1 Memory and I/O Address Decoding
      • 13.2.1.1 Memory-Mapped Access to Internal Registers and Memories
      • 13.2.1.2 Memory-Mapped Access to FLASH
      • 13.2.1.3 Memory-Mapped Access to Expansion ROM
    • 13.2.2 I/O-Mapped Internal Register, Internal Memory, and Flash
      • 13.2.2.1 IOADDR
      • 13.2.2.2 IODATA
  • 13.3 PCI-X Register Access Split
  • 13.4 Main Register Descriptions
    • 13.4.1 Device Control Register
    • 13.4.2 Device Status Register
    • 13.4.3 EEPROM/Flash Control & Data Register
    • 13.4.4 EEPROM Read Register
    • 13.4.5 Flash Access
    • 13.4.6 Extended Device Control Register
    • 13.4.7 MDI Control Register
      • 13.4.7.1 PHY Registers
    • 13.4.8 Flow Control Address Low
    • 13.4.9 Flow Control Address High
    • 13.4.10 Flow Control Type
    • 13.4.11 VLAN Ether Type
    • 13.4.12 Flow Control Transmit Timer Value
    • 13.4.13 Transmit Configuration Word Register
    • 13.4.14 Receive Configuration Word Register
    • 13.4.15 LED Control
      • 13.4.15.1 MODE Encodings for LED Outputs1
    • 13.4.16 Packet Buffer Allocation
    • 13.4.17 Interrupt Cause Read Register
    • 13.4.18 Interrupt Throttling Register
    • 13.4.19 Interrupt Cause Set Register
    • 13.4.20 Interrupt Mask Set/Read Register
    • 13.4.21 Interrupt Mask Clear Register
    • 13.4.22 Receive Control Register
    • 13.4.23 Flow Control Receive Threshold Low
    • 13.4.24 Flow Control Receive Threshold High
    • 13.4.25 Receive Descriptor Base Address Low
    • 13.4.26 Receive Descriptor Base Address High
    • 13.4.27 Receive Descriptor Length
    • 13.4.28 Receive Descriptor Head
    • 13.4.29 Receive Descriptor Tail
    • 13.4.30 Receive Delay Timer Register
    • 13.4.31 Receive Interrupt Absolute Delay Timer
    • 13.4.32 Receive Small Packet Detect Interrupt
    • 13.4.33 Transmit Control Register
    • 13.4.34 Transmit IPG Register
    • 13.4.35 Adaptive IFS Throttle - AIT
    • 13.4.36 Transmit Descriptor Base Address Low
    • 13.4.37 Transmit Descriptor Base Address High
    • 13.4.38 Transmit Descriptor Length
    • 13.4.39 Transmit Descriptor Head
    • 13.4.40 Transmit Descriptor Tail
    • 13.4.41 Transmit Interrupt Delay Value
    • 13.4.42 TX DMA Control (82544GC/EI only)
    • 13.4.43 Transmit Descriptor Control
    • 13.4.44 Transmit Absolute Interrupt Delay Value
    • 13.4.45 TCP Segmentation Pad And Minimum Threshold
    • 13.4.46 Receive Descriptor Control
    • 13.4.47 Receive Checksum Control
  • 13.5 Filter Registers
    • 13.5.1 Multicast Table Array
    • 13.5.2 Receive Address Low
    • 13.5.3 Receive Address High
    • 13.5.4 VLAN Filter Table Array
  • 13.6 Wakeup Registers
    • 13.6.1 Wakeup Control Register
    • 13.6.2 Wakeup Filter Control Register
    • 13.6.3 Wakeup Status Register
    • 13.6.4 IP Address Valid
    • 13.6.5 IPv4 Address Table
    • 13.6.6 IPv6 Address Table
    • 13.6.7 Wakeup Packet Length
    • 13.6.8 Wakeup Packet Memory (128 Bytes)
    • 13.6.9 Flexible Filter Length Table
    • 13.6.10 Flexible Filter Mask Table
    • 13.6.11 Flexible Filter Value Table
  • 13.7 Statistics Registers
    • 13.7.1 CRC Error Count
    • 13.7.2 Alignment Error Count
    • 13.7.3 Symbol Error Count
    • 13.7.4 RX Error Count
    • 13.7.5 Missed Packets Count
    • 13.7.6 Single Collision Count
    • 13.7.7 Excessive Collisions Count
    • 13.7.8 Multiple Collision Count
    • 13.7.9 Late Collisions Count
    • 13.7.10 Collision Count
    • 13.7.11 Defer Count
    • 13.7.12 Transmit with No CRS
    • 13.7.13 Sequence Error Count
    • 13.7.14 Carrier Extension Error Count
    • 13.7.15 Receive Length Error Count
    • 13.7.16 XON Received Count
    • 13.7.17 XON Transmitted Count
    • 13.7.18 XOFF Received Count
    • 13.7.19 XOFF Transmitted Count
    • 13.7.20 FC Received Unsupported Count
    • 13.7.21 Packets Received (64 Bytes) Count
    • 13.7.22 Packets Received (65-127 Bytes) Count
    • 13.7.23 Packets Received (128-255 Bytes) Count
    • 13.7.24 Packets Received (256-511 Bytes) Count
    • 13.7.25 Packets Received (512-1023 Bytes) Count
    • 13.7.26 Packets Received (1024 to Max Bytes) Count
    • 13.7.27 Good Packets Received Count
    • 13.7.28 Broadcast Packets Received Count
    • 13.7.29 Multicast Packets Received Count
    • 13.7.30 Good Packets Transmitted Count
    • 13.7.31 Good Octets Received Count
    • 13.7.32 Good Octets Transmitted Count
    • 13.7.33 Receive No Buffers Count
    • 13.7.34 Receive Undersize Count
    • 13.7.35 Receive Fragment Count
    • 13.7.36 Receive Oversize Count
    • 13.7.37 Receive Jabber Count
    • 13.7.38 Management Packets Received Count
    • 13.7.39 Management Packets Dropped Count1
    • 13.7.40 Management Pkts Transmitted Count
    • 13.7.41 Total Octets Received
    • 13.7.42 Total Octets Transmitted
    • 13.7.43 Total Packets Received
    • 13.7.44 Total Packets Transmitted
    • 13.7.45 Packets Transmitted (64 Bytes) Count
    • 13.7.46 Packets Transmitted (65-127 Bytes) Count
    • 13.7.47 Packets Transmitted (128-255 Bytes) Count
    • 13.7.48 Packets Transmitted (256-511 Bytes) Count
    • 13.7.49 Packets Transmitted (512-1023 Bytes) Count
    • 13.7.50 Packets Transmitted (1024 Bytes or Greater) Count
    • 13.7.51 Multicast Packets Transmitted Count
    • 13.7.52 Broadcast Packets Transmitted Count
    • 13.7.53 TCP Segmentation Context Transmitted Count
    • 13.7.54 TCP Segmentation Context Transmit Fail Count
  • 13.8 Diagnostics Registers
    • 13.8.1 Receive Data FIFO Head Register
    • 13.8.2 Receive Data FIFO Tail Register
    • 13.8.3 Receive Data FIFO Head Saved Register
    • 13.8.4 Receive Data FIFO Tail Saved Register
    • 13.8.5 Receive Data FIFO Packet Count
    • 13.8.6 Transmit Data FIFO Head Register
    • 13.8.7 Transmit Data FIFO Tail Register
    • 13.8.8 Transmit Data FIFO Head Saved Register
    • 13.8.9 Transmit Data FIFO Tail Saved Register
    • 13.8.10 Transmit Data FIFO Packet Count
    • 13.8.11 Packet Buffer Memory
• General Initialization and Reset Operation 14
  • 14.1 Introduction
  • 14.2 Power Up State
  • 14.3 General Configuration
  • 14.4 Receive Initialization
  • 14.5 Transmit Initialization
    • 14.5.1 Signal Interface
    • 14.5.2 GMII/MII Features not Supported
    • 14.5.3 Avoiding GMII Test Mode(s)
    • 14.5.4 MAC Configuration
    • 14.5.5 Link Setup
  • 14.6 PHY Initialization (10/100/1000 Mb/s Copper Media)
  • 14.7 Reset Operation
  • 14.8 Initialization of Statistics
• Diagnostics and Testability 15
  • 15.1 Diagnostics
    • 15.1.1 FIFO State
    • 15.1.2 FIFO Data
    • 15.1.3 Loopback
      • 15.1.3.1 Internal Loopback
  • 15.2 Testability
    • 15.2.1 EXTEST Instruction
    • 15.2.2 SAMPLE/PRELOAD Instruction
    • 15.2.3 IDCODE Instruction
    • 15.2.4 BYPASS Instruction
• Appendix (Changes From 82544EI/82544GC) A
• Appendix (82540EP/EM and 82545GM/EM Differences) B