Intel Multiprocessor Users Manual Specification

2015-02-02

• MultiProcessor Specification
• Disclaimer
• Revision Histoy
• Table of Contents
• 1 Introduction
  • 1.1 Goals
  • 1.2 Features of the Specification
  • 1.3 Scope
  • 1.4 Target Audience
  • 1.5 Organization of This Document
  • 1.6 Conventions Used in This Document
  • 1.7 For More Information
• 2 System Overview
  • 2.1 Hardware Overview
    • 2.1.1 System Processors
    • 2.1.2 Advanced Programmable Interrupt Controller
    • 2.1.3 System Memory
    • 2.1.4 I/O Expansion Bus
  • 2.2 BIOS Overview
  • 2.3 Operating System Overview
• 3 Hardware Specification
  • 3.1 System Memory Configuration
  • 3.2 System Memory Cacheability and Shareability
  • 3.3 External Cache Subsystem
  • 3.4 Locking
  • 3.5 Posted Memory Write
  • 3.6 Multiprocessor Interrupt Control
    • 3.6.1 APIC Architecture
    • 3.6.2 Interrupt Modes
      • 3.6.2.1 PIC Mode
      • 3.6.2.2 Virtual Wire Mode
      • 3.6.2.3 Symmetric I/O Mode
    • 3.6.3 Assignment of System Interrupts to the APIC Local Unit
    • 3.6.4 Floating Point Exception Interrupt
    • 3.6.5 APIC Memory Mapping
    • 3.6.6 APIC Identification
    • 3.6.7 APIC Interval Timers
    • 3.6.8 Multiple I/O APIC Configurations
  • 3.7 RESET Support
    • 3.7.1 System-wide RESET
    • 3.7.2 System-wide INIT
    • 3.7.3 Processor-specific INIT
  • 3.8 System Initial State
  • 3.9 Support for Fault-resilient Booting
• 4 MP Configuration Table
  • 4.1 MP Floating Pointer Structure
  • 4.2 MP Configuration Table Header
  • 4.3 Base MP Configuration Table Entries
    • 4.3.1 Processor Entries
    • 4.3.2 Bus Entries
    • 4.3.3 I/O APIC Entries
    • 4.3.4 I/O Interrupt Assignment Entries
    • 4.3.5 Local Interrupt Assignment Entries
  • 4.4 Extended MP Configuration Table Entries
    • 4.4.1 System Address Space Mapping Entries
    • 4.4.2 Bus Hierarchy Descriptor Entry
    • 4.4.3 Compatibility Bus Address Space Modifier Entry
• 5 Default Configurations
  • 5.1 Discrete APIC Configurations
  • 5.2 Integrated APIC Configurations
  • 5.3 Assignment of I/O Interrupts to the APIC I/O Unit
    • 5.3.1 EISA and IRQ13
    • 5.3.2 Level-triggered Interrupt Support
  • 5.4 Assignment of System Interrupts to the APIC Local Unit
• A System BIOS Programming Guidelines
  • A.1 BIOS Post Initialization
  • A.2 Controlling the Application Processors
  • A.3 Programming the APIC for Virtual Wire Mode
  • A.4 Constructing the MP Configuration Table
• B Operating System Programming Guidelines
  • B.1 Operating System Boot-up
  • B.2 Operating System Booting and Self-configuration
  • B.3 Interrupt Mode Initialization and Handling
  • B.4 Application Processor Startup
    • B.4.1 USING INIT IPI
    • B.4.2 USING STARTUP IPI
  • B.5 AP Shutdown Handling
  • B.6 Other IPI Applications
    • B.6.1 Handling Cache Flush
    • B.6.2 Handling TLB Invalidation
    • B.6.3 Handling PTE Invalidation
  • B.7 Spurious APIC Interrupts
  • B.8 Supporting Unequal Processors
• C System Compliance Checklist
• D Multiple I/O APIC Multiple PCI Bus Systems
  • D.1 Interrupt Routing with Multiple APICs
    • D.1.1 Variable Interrupt Routing
    • D.1.2 Fixed Interrupt Routing
  • D.2 Bus Entries in Systems with More Than One PCI Bus
  • D.3 I/O Interrupt Assignment Entries for PCI Devices
• E Errata
• Glossary