M2Communication MD903A1 Wireless ED Module_9 series User Manual MA903A1 FCC 20151028

M2Communication Inc. Wireless ED Module_9 series MA903A1 FCC 20151028

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User Manual OEM

MA903A1 Wireless AP Module_9 series Copyright © by M2Communcation, Inc. All rights reserved. This document is the sole and exclusive property of M2Communication, Inc. Not to be distributed or divulged without prior written agreement. Feature Highlights Low supply operation: 2.4V –3.6VCompact size: 35.5mm x 37.5mm, ideal for embedded systemintegration such as access pointLow-power consumptionUsing M2C patented Platanus™platform for smart-networkingapplicationARM Cortex-M0 up to 32MHzclock rate, with embedded 128KB flash memory and 1MBSRAMFrequency range: 903~927MHzData bandwidth: up to 500kbpsHigh receiver sensitivity: -96dBmat 500kbpsIntegrated power amplifier up to11dBmPre-matched RF front-end,reducing design hasslesSupport UART and GPIOs asinterface with other LAN modulesin the embedded systemSupports 128-node “star” and16000-node “tree” networkinfrastructure.Applications Comply with FCC Part 15CInnovative turn-key solutionfor ultra-low power wirelesslinkRemote control systemsWireless sub-metering (plug)Home automationWireless sensor networkTelemedicine serviceWireless lighting controlSmart rack for logisticssystemDescriptions Overview MA903A1 is an easy-to-integrate Access Point embedded module for hosting ultra-low-power wireless-link application. With state-of-the-art PlatanusTM protocol and networking kit, large network (up to 16000 nodes) can be easily formed. Equipped with ISM-band RF operated at 868MHz/915MHz bands and popular ARM 32-bit MCU along with embedded flash memory and SRAM, MA903A1 is an ideal embedded solution for system integrator to develop wireless applications with no worry about design hassles, both wireless and networking. Easy to Integrate and Use Designed as the embedded module, MA903A1 has only the board area of 35.5mm x 37.5mm, compact enough for most embedded system design. A pre-matched 50 ohm port is ready to be used with on-board or external antenna. The RF matched network is calibrated to optimize the RF performance when the module is shipped, saving the design hassles for application designers. There are total 50 stamp pads on MA903A1 with multiple digital interfaces: UART, GPIOs, and JTAGS. This brings the design flexibility to end applications that MA903A1 is easy to interface with other LAN modules. Through the robust wireless link, controlled/collected information from End Device (ME10WM010) can be easily sent to the upper application layers and devices.
Datasheet v1.0 MA903A1 2014/01 Copyright © by M2Communication Inc. Page 2 of 22 Ready-to-go Sub-GHz Radio Link with Excellent Reliability The wireless link utilizes the sub-GHz radio band, requiring no special licenses (free-ISM) and certification. MA903A1 comply with the ETSI EN 300 220 and FCC part 15 regulations. Compared to the crowded 2.4GHz band, sub-GHz radio link, given the similar power level, allows better distance and penetration especially in the hostile indoor environment. In particular, with WiFi and Bluetooth crowding the 2.4GHz band these days, MA903A1 is immune from all 2.4GHz interference and delivers the reliable wireless link. With the data rate of 500kbps in 2FSK, the bandwidth use efficiency is 16x better than 2.4GHz Zigbee (2MHz). MA903A1 can deliver the link budget up to 107dB (TX maximum power: 11dBm, RX Sensitivity level: -96dBm) without adding external components. The Line-of-Sight (LOS) link distance is over 300 meters*. * tested with 63-byte payload with PER of 1%. This may be variable depending on test environmentRobust Two-way Networking MA903A1 uses a built-in protocol PlatanusTM to support “two-way” networking, saving the SI’s design headache of linking large amounts of wireless nodes. Used with ME10WM010 (End Device), MA903A1 can support two types of network hierarchies: STAR and TREE (as shown below). When MA903A1 is configured in STAR networking, up to 128 nodes can be supported. When MA903A1 is configured in TREE network, up to 16000 nodes can be supported. Asymmetrical downlink and uplink are supported to balance between network reliability and response time, and the programmable network parameters can be used to optimize for each use scenario. Figure 1. STAR configuration Figure2. TREE configuration Upper Layer Connectivity MA903A1 is shipped with the UART interface and the managing software library. Thus the upper-layer devices, such as TCP/IP gateway, can easily access MA903A1 in the network, as the Access Point to the private network, to exchange data “interactively” via the Ethernet or WiFi. This makes the cloud-based application developer easy to hook up with the privately-own network when building with MA903A1. Figure 3. Network Structure
Datasheet v1.0 MA903A1 2014/01 Copyright © by M2Communication Inc. Page 3 of 22 Ideal Platform for Low-power Application Development MA903A1 is powered by ARM Cortex MCU with clock up to 32MHz with embedded 128K-Byte flash and 1M-Byte SRAM, to support built-in PlatanusTM networking library from M2C and for peripherals. For details, please refer to the associated documentation. Using PlatanusTM protocol with M2C MA903A1 (Access Point) and/or MR1001 (Router), the formed network can achieve ultra-low power consumption for battery-friendly applications. The network acts in the cellular-like behavior, with sleep time configurable from 5 seconds up to 90 seconds. Details of power consumption can be referred to the datasheet of ME10WM010. Pin Diagram & Components Placement Figure4. Pin diagram
Datasheet v1.0 MA903A1 2014/01 Copyright © by M2Communication Inc. Page 4 of 22 Figure5. Pin diagram
Datasheet v1.0 MA903A1 2014/01 Copyright © by M2Communication Inc. Page 5 of 22 Table of Contents 1 Electrical Characteristics ................................................................................... 62 Pin Out ................................................................................................................. 93 Memory .............................................................................................................. 104 Serial Interfaces ................................................................................................ 104.1 General-purpose I/O (GPIO) .................................................................................................... 104.2 UART ........................................................................................................................................ 105 How to Use MA903A1 to Design & Compliance with FCC requirements ..... 115.1 50ohm RF Trace Calculation .................................................................................................... 115.2 PCB Design .............................................................................................................................. 125.3 PCB Layout Recommend ......................................................................................................... 145.4 PCB Layout Guide .................................................................................................................... 146 Available Antenna List ..................................................................................... 157 Regulation Approval......................................................................................... 198 Recommended PCB Footprint ......................................................................... 199 Contact Information.......................................................................................... 2010 Ordering Information ..................................................................................... 20
Datasheet v1.0 MA903A1 2014/01 Copyright © by M2Communication Inc. Page 6 of 22 1 Electrical Characteristics Table 1. Absolute Maximum Rating Parameter Symbol Condition Min Typ Max UnitSupply Voltage Vdd VCC to GND -0.3 3.6 Volt Voltage on I/O Pin VIO -0.3 Vcc + 0.3 Volt Temperature Range for Storage Tsto -10 +85 oC Operation Temperature Topt -10 +45 oC Table 2. DC Characteristics Parameter Symbol Condition Min Typ Max UnitPower Supply Vdd see note 1 2.4 3.6 V Low-power Current Consumption Inormal (see below) N/A Istandby Standby mode 4 mA RX Mode Current Consumption TX Mode Current Consumption IRX,MB 923MHz band Data rate = 500kbps 2FSK 30 mA TX Mode Current Consumption Read/Write Memory ITX1, 11dBm Output power = 11.28dBm 50 mA IBB Read/Write Memory 60 mA Linking and Data Transmitting Itotal System Linking, Transmit and Receive Data TBD <100 mA Note 1: all performance parameters are guaranteed at Vdd = 3.3V
Datasheet v1.0 MA903A1 2014/01 Copyright © by M2Communication Inc. Page 7 of 22 Table 3. AC Characteristics Parameter Symbol Condition Min Typ Max Unit RF Frequency Range F915M 903 927 MHz RX Sensitivity PRx_500K BER < 0.1% 2FSK, BT=0.5 500Kbps -96 dBm Saturation Power Level Psat 10 dBm RSSI Range RESRSSI -82 -58 dBm Output TX Power Pout 7 dBm RF Data Rate DT 500 Kbps Link Distance Rlink Line-of-Sight 20-byte packet length PER<1% Pout = 10dBm 250 Meters Link Distance Rlink Line-of-Sight 20-byte packet length PER<1% Pout = 0dBm 110 Meters
Datasheet v1.0 MA903A1 2014/01 Copyright © by M2Communication Inc. Page 8 of 22 Table 4. Digital IO Specification Parameter Symbol Condition Min Typ Max Unit Rise Time Tr 10% to 90% of VCC CL=10pF, DR<1:0>=11 10 ns Fall Time Tf 10% to 90% of VCC CL=10pF, DR<1:0>=11 10 ns Logic “H” Input Level VIH VDD-0.6 V Logic “L” Input Level VIL 0.6 V Input Capacitance Cpin 1 pF Input Impedance Zpin,hiZ DC, Configured as hi-Z 10M Ω Zpin,pl DC, Configured as pull-low 100K Ω Zpin,ph DC, Configured as pull-high 100K Ω Maximal Output Current Idrive programmable 1 4 8 mA Logic “H” Output Level VOH VDD-0.5 V Logic “L” Output Level VOL 0.5 V Digital IO Specification Annotation 0.9VDD0.1VDDTrTfVIHVILVOHVOL Figure6. I/O level diagram
Datasheet v1.0 MA903A1 2014/01 Copyright © by M2Communication Inc. Page 9 of 22 2 Pin Out All VDDs are rated from 2.4V to 3.6V. Pin # Pin Name Description Type[1] I/O/PWR 1 RFIO RF Signal 50 ohm IO RF 2~20, 22~26, 32, 40, 47, 49 GND Board ground G 0 21 VDD1 Module Power Input. 2.4V~3.6V VDD1+VDD2+VDD3+VDD_RF 150mA Requirement P PWR 27 VDD2 Module Power Input. 2.4V~3.6V VDD1+VDD2+VDD3+VDD_RF 150mA Requirement P PWR 28 UART_RXD UART_RXD, Baud Rate = 460.8kbps D/A IO 29 UART_TXD UART_TXD, Baud Rate = 460.8kbps D/A IO 30 IO2 GPIO D IO 31 IO1 GPIO D IO 33 JTAG_CLK ICE CLK (debugger) D I 34 JTAG_DAT ICE DATA IN (debugger) D IO 35 SYS_RESET External reset input, No need RC Delay [2] SYS SYS 36, 44~46 NC No Connection 37 DEBUG_IO2 Debug UART_TXD, No connection D O 38 DEBUG_IO1 Debug UART_RXD, No connection D I 39 RF_TEST_IO1 RF Test Pin Data_Out, No connection D O 41 RF_TEST_IO2 RF Test Pin CLK_Out, No connection D O 42 LED2 LED Index, Driver current 3mA D IO 43 LED1 LED Index, Driver current 3mA D IO 48 VDD3 Module Power Input. 2.4V~3.6V VDD1+VDD2+VDD3+VDD_RF 150mA Requirement P PWR 50 VDD_RF Module Power Input. 2.4V~3.6V VDD1+VDD2+VDD3+VDD_RF 150mA Requirement P PWR [1] D=digital, A=analog, P=power, G=ground [2] Set this pin low reset chip to initial state, with internal pull-up [3] External interrupt input
Datasheet v1.0 MA903A1 2014/01 Copyright © by M2Communication Inc. Page 10 of 22 3 Memory MA903A1 is equipped with embedded 128KB flash memory and 1MB SRAM. The specification is listed as below. Currently MA903A1 does not support the external memory due to performance compromises, 4 Serial Interfaces MA903A1 support the common serial data interfaces, including GPIO, and UART. Their timing and specifications are addressed at the following sections. 4.1 General-purpose I/O (GPIO) The functions of GPIOs are summarized as below:  Push-Pull output  Open-Drain output  Input only with high impendence (100K ~ 300Kohms)  All inputs with Schmitt trigger  I/O pin configured as interrupt source with edge/level setting  Supports input 5V tolerance 4.2 UART Figure7. UART Data Format The features of UART interfaces are summarized as below:  Two sets of UART controllers  The UART0 and UART1 are built-in with a 16-byte TX_FIFO and a 16-byte RX_FIFO to reduce the number of interrupts presented to the CPU  Baud rate is up to 460800 bps

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