Panasonic Gd55 Schematics
User Manual: Manual Panasonic - Schematics & Service Manuals PDF
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3. CIRCUIT DIAGRAMS 3.1. Circuit Diagram-1 VCORE VMEM VCORE C101 0.1U C102 0.1U C103 0.1U C104 0.1U C105 0.1U C106 0.1U C107 0.1U C108 0.1U C109 0.1U C110 0.1U VMEM VCORE C111 0.1U VRTC R101 33K C112 0.1U + BAT101 ML414R-F9A TP105 TP_GPIO9 TP107 TP_GPIO11 TP109 TP_GPIO18 [7] VIBRATOR_ON [6] AUDIO_ON [5] [5] [5] [5] YMU_SCLK YMU_AVCC_ON YMU_SYNC YMU_SDIN TP111 TP_GPIO19 TP113 TP_GPIO20 TP115 TP_GPIO21 T117 TP_GPO23 TP119 TP_GPCS1 TP121 TP_GPCS0 [7] BACKLIGHT [7] [7] [7] LCDCTL LCDCS NRESET_LCD C5 A7 M5 P5 F12 L13 M12 L14 GPIO_32(WAIT) AD6522 A2 VDDRTC TRSW3 RXEN1 PA_EN TRSW2 TRSW1 [9] [8] [9] [9] [9] TX_GSM (GPO_16) ADD23(TX_DCS)GPO_17 (OTH_EN)GPO_18 (OTH_VLO_EN)GPO_19 (OTH_DATA)GPO_20 (OTH_CLK)GPO_21 (RXON)GPO_0 (TXON)GPO_1 GPO_3 E13 G11 E12 D14 D13 F11 B1 C2 G12 GSMEN DCSEN S XE N LE DATA CLK RXEN TXEN RFEN [8,9] [8] [8] [8] [8] [8] [2] [2,8,9] [9] T123 TP_GPIO32 – 3-1 – CLKOUT CLKOUT_GATE (VBCRESET)GPO_24 (ARSM)GPO_5 (ATSM)GPO_6 ASDI ASDO ASFS D1 D2 E1 A1 C1 E2 F1 F2 CLK_OUT CLKOUT_GATE VBC_RESET ARSM AT SM ASDI ASDO ASFS [2,5] [2] [2] [2] [2] [2] [2] [2] BSDO BSOFS BSDI BSIFS VSDI VSDO VSFS F3 G4 G2 G1 G3 H3 H2 BSDO BSOFS BSDI BSIFS VSDI VSDO VSFS [2] USC0 USC1 USC2 USC3 USC4 USC5 USC6 C14 D12 A14 A13 E11 C12 B13 USC0 USC1 USC2 USC3 USC4 USC5 USC6 SIMDATAOP SIMCLK SIMRESET (GPIO_23) SIMSUPPLY (GPIO_24) SIMVPROG (GPIO_22) J13 K12 L10 K13 J14 JTAGEN [2] [2] [2] [2] [2] TP124 RXEN TP101 TP_CLKOUT VMEM R103 TBD 8 7 6 5 E3 VPEG1 VEXT1 VEXT2 VEXT3 VEXT4 L2 N5 N9 N1 3 VMEM1 VMEM2 VMEM3 VMEM4 L9 BACKLIGHT1 (GPO_23) BACKLIGHT0 (GPO_22) LCDCTL (nDISPLAYCS) nDISPLAYCS (ADD22) SM_SW_SYNC (GPO_10) GPCS1 GPCS0 G13 H12 F14 F13 H11 [4] [4] [4] [4,7] [4] [4] R104 TBD VMEM TP106 TP_USC0 R105 100K 1 2 3 4 YMU_IRQ HPOUT_ON GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_20 GPIO_21 (GPO_2) (GPO_4) (GPO_7) (GPO_8) (GPO_9) TXPA PA_NEGBIAS TXPHASE DCS_SW_SYNC DCS_SW_DRV RD HWR LWR WE ROMCS RAMCS TP108 TP_USC1 TP110 TP_USC2 TP112 TP_USC3 TP114 TP_USC4 SIM_IO SIM_CLK SIM_RESET SIM_ON 1 TP120 TP_GPIO22 1 TP122 TP_JTAGEN K11 [4] [4] [4] [3] R107 TBD 8 7 6 5 [5] [6] RESET D11 D10 B12 C11 D9 B11 A11 C10 D8 A10 C9 C7 B9 A9 B8 A8 D6 B7 H14 H13 J12 J11 M11 N12 P13 P14 M13 M14 R108 TBD R106 100K TP116 TP_USC5 TP118 TP_USC6 1 2 3 4 [3] CHARGER_DET PT T [6] HANDFREE_IN TP103 TP_GPIO7 N14 RD HWR LWR WE ROMCS RAMCS 2 4 [3] END_OF_CHARGE [3] CHARGER_GATEIN [3] CHARGER_EN TP102 TP_GPIO3 TP104 TP_GPIO9 NRESET D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 N6 P6 M6 N7 M7 L7 P8 N8 M8 P9 M9 P10 N10 M10 P11 N11 1 3 [3,4,5] CLKIN CLKON OSCOUT OSCIN PWRON GSM_SW_DRV (GPO_11) [4,7] DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 2 4 [3] POWER_ON [3] SYS_POWERON L12 G14 B3 A3 B2 E14 D[0..15] 1 3 R102 10M KEYPADROW0 KEYPADROW1 KEYPADROW2 KEYPADROW3 KEYPADROW4 KEYPADCOL0 KEYPADCOL1 KEYPADCOL2 KEYPADCOL3 KEYPADCOL4 VSSRTC X101 MC-146 BBCLK CLKON A6 F4 D4 B5 A5 C4 E4 B4 A4 C3 D3 [3] [3] ADD0 ADD1 ADD2 ADD3 ADD4 ADD5 ADD6 ADD7 ADD8 ADD9 ADD10 ADD11 ADD12 ADD13 ADD14 ADD15 ADD16 ADD17 ADD18 ADD19 ADD20 ADD21 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND1 0 GND1 1 [7] [7] [7] [7] [7] KEYROW_0 KEYROW_1 KEYROW_2 KEYROW_3 KEYROW_4 KEYCOL_0 KEYCOL_1 KEYCOL_2 KEYCOL_3 KEYCOL_4 H4 J3 J2 J4 K3 K2 K4 L4 L1 L3 L5 M1 M2 N1 P1 N2 P2 N3 M3 P4 N4 M4 J1 K1 P3 L6 L8 P12 L11 C1 3 A12 D7 B6 [7] [7] [7] [7] [3] VCC1 VCC2 VCC3 VCC4 U101 ADD0 ADD1 ADD2 ADD3 ADD4 ADD5 ADD6 ADD7 ADD8 ADD9 ADD10 ADD11 ADD12 ADD13 ADD14 ADD15 ADD16 ADD17 ADD18 ADD19 ADD20 ADD21 VSIM H1 P7 K14 C8 ADD[0..21] ADD[0..21] B14 B10 C6 D5 D[0..15] [4,7] 3.2. Circuit Diagram-2 VANA VCORE D201 VMEM VANA VCORE TBD R213 100K C202 0.1U C203 0.1U C204 0.1U C205 0.1U C206 0.1U C207 0.1U RXIP RXIN RXQP RXQN [8] [8] [8] [8] 2 4 C201 2.2U VSFS VSDO VSDI [1] [1] [1] BSIFS BSDI BSOFS BSDO E2 F1 F2 G2 BSOFS BSDO BSIFS BSDI [1] [1] ATSM ARSM K3 J3 ATSM ARSM [1] [1,5] CLKOUT_GATE CLK_OUT K2 J2 MCLKEN MCLK [1,8,9] [1] TXEN RXEN K4 J4 TXON RXON [1] VBC_RESET K1 RESET B2 B1 C2 C1 TDI TDO TMS TCK B4 A3 IDACOUT IDACREF TP201 TP_VBCRST R207 100K G1 A1 J8 A9 F10 K5 DVDD3 D2 D1 E1 DVDD2 VSFS VSDI VSDO DVDD1 [1] [1] [1] AVDD3 ASDI ASFS ASDO AVDD2 H1 H2 J1 ITXP ITXN QTXN QTXP F9 E9 C9 D9 IRXP IRXN QRXP QRXN E10 D10 C10 B10 AFCDAC RAMPDAC A10 H9 TXIP TXIN TXQN TXQP AFC RAMP [8] [8] [8] [8] [3] [9] R206 100K REFOUT REFCAP A7 A8 VREFOUT C218 2.2U C212 0.1U C213 0.1U VINNORP VINNORN J10 K10 VINNORP VINNORN [6] [6] VINAUXP VINAUXN H10 G10 VINAUXP VINAUXN [6] [6] VOUTNORP VOUTNORN K8 K7 VOUTNORP VOUTNORN [5] [5] VOUTAUXP VOUTAUXN K9 K6 VOUTAUXP VOUTAUXN [5] [5] BUZZER J6 TP202 TP_BUZZER BUZZER [6,7] A6 BAT_VIOLTAGE AUXADC1 VANA C214 0.1U R208 200K/1% A5 C215 0.1U VBAT R210 100K/1% VANA AUXADC4 B7 A4 2 C216 0.1U VBAT 3 BAT_TEMP GND BAT_CON VANA TP204 ADC6 R211 TBD B6 TP203 ADC5 1 TP301 TP_VBAT TP302 TP_GND PCB_ID AD6521 – 3-2 – R212 TBD DGND1 DGND3 A2 J5 AGND4 AGND3 AGND2 AGND1 AUXADC6 B3 J7 B8 G9 NC(MICCAP) NC(REFCAP20) AUXADC5 BAT_TEMP C217 TBD B5 AUXADC3 CON301 R211 TBD NTC AUXADC2 J9 B9 TP206 BSDO ASDO ASFS ASDI 2 4 TP208 BSOFS [1] [1] [1] 1 3 TP207 BSIFS TP205 BSDI U201 AVDD1 1 3 R201 100K R209 100K [3] 3.3. Circuit Diagram-3 VBAT C301 4.7U C302 0.1U VRTC VBAT TP303 POWERON_KEY R301 100K/0402R R302 100K POWERON_IN [1] SYS_POWERON 1 [7] [1] NC NC NC VRTCIN VRTC 3 VRTC PWRONIN VANA 23 VANA PWRONKEY VCORE 21 VCORE 31 ROWX VMEM 20 VMEM [1] SIM_ON 1 SIMEN VSIM 18 SIMVCC [1] CLKON 28 TCXOEN VTCXO 25 VTCXO [1] CHARGER_EN 14 CHGEN EOC 13 END_OF_CHARGE [1] 8 GATEIN CHRDET 6 CHARGER_DET [1] 7 CHRIN NRESET [1,4,5] 12 ISENSE GATEDIR F301 TBD C309 10N 2 C310 2.2U/25V U306 BLM55C9V1 - B U308 C319 1 6 4 0.01U - B 22K 2 1 P_JACK 3 T301 2 1 2 RESET 16 RESCAP 15 REFOUT 26 C311 0.1U 5 U309 SI3443DV 1 2 5 6 U310 1 2 VBAT RB491D 22K 3 3 4 R310 10K - B EMD2 - B C312 10N C321 0.1U R309 10K - B C323 0.1U C322 0.1U VTCXO R304 0 R305 27K [2] [1] CLKON U304 AFC C313 10N 1 AFC VCC 6 2 GND GND 5 3 GND OUT 4 TG-2820CB C314 10P C316 1U C317 10N 1 2 D A 3 GND VCC 5 Y 4 R308 0R R306 100R BBCLK U305 NC7SZU00P5X C318 TBD R307 1M [8] 13 M H z TO RF BLOCK – 3-3 – [1] C304 4.7U SIMVCC C306 4.7U R303 0.3 U307 FDC640P - B 4 1 2 5 6 F302 FULSE 1 2 1 TBD 27 ADP3408 R311 TBD VMEM 30 CHARGER_GATEIN VCORE C305 4.7U [2] KEYROW_4 9 CON302 BAT_VOLTAGGE [1] POWER_KEY R313 TBD R312 5 29 DGND 3 C303 0.1U MVBAT 11 2 BATSNS 2 DGND POWER_ON VBAT2 4 AGND [1] DAN222 19 10 U302 VBAT 24 32 17 U301 22 VANA C307 2.2U VTCXO C308 1U 3.4. Circuit Diagram-4 VMEM [1,7] D[0..15] D[0..15] C401 0.1U C5 K6 H9 D6 WP/ACC CIOs CIOf CE2s [1] [1] [1] [1,7] [1] [1] [1,3,5] RD HWR LWR WE ROMCS RAMCS NRESET H3 D4 C4 C6 H2 J2 OE UB LB WE CEf CE1s D5 RESET E5 RY/BY G8 SA VSS VSS WP-ACC CIOs CIOf CE2s MC-222243AF9-B85XBT3(FBGA) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 G2 F2 E2 D2 F3 E3 D3 C3 C7 E7 F7 C8 D8 E8 F8 D9 G9 F4 E4 D7 E6 NC0 NC1 E9 F9 MB16 MB15 MB14 MB13 MB12 MB11 MB10 MB9 MB8 MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0 M10 L10 G10 F10 B10 A10 L6 B6 L5 B5 M1 L1 G1 F1 C1 B1 A1 ADD[0..21] [1,7] ADD1 ADD2 ADD3 ADD4 ADD5 ADD6 ADD7 ADD8 ADD9 ADD10 ADD11 ADD12 ADD13 ADD14 ADD15 ADD16 ADD17 ADD18 ADD19 ADD20 ADD21 SIMVCC TP401 TP_SIMVCC R405 100K TP403 TP_SIMCLK R403 10K TP402 TP_SIMRST J401 R404 150R/1% [1] [1] SIM_RESET SIM_CLK C402 TBD 5 VCC GND 6 3 RST VPP 4 1 CLK I/O 2 C403 0.1U SIM SOCKET SIM_IO C404 33pF TP404 TP_SIMIO G3 J9 8 7 6 5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 1 2 3 4 R401 100K J3 G4 K4 H5 H6 K7 G7 J8 K3 H4 J4 K5 J7 H7 K8 H8 VCCf VCCs D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VMEM J5 J6 ADD[0..21] U401 – 3-4 – [1] 3.5. Circuit Diagram-5 TP502 TP_SPK-N TP501 TP_SPK-P R503 0R [2] VOUTNORP LS502 C522 TBD R504 0R RECEIVER - B C524 33P C523 33P T504 - B 1 2 VOUTNORN T503 - B 1 2 [2] R520 0R [2] VOUTAUXN [2] VOUTA U XP VOICEOUT [6] VBAT R521 100K YMU_AVCC U505 VM EM YMU_AVCC R510 TBD 5 4 C513 0.1U C517 22N R508 22K R514 20K C521 0.1U [1] YMU_IRQ 15 IRQ [1,3,4] NRESET 17 RST EQ1 6 16 /TESTI R509 82K EQ3 LS501 11 SPOUT2 12 HPOUT 5 C511 TBD SPEAKER C515 33P C516 33P 1 YMU757B TESTO VREF SPVSS CLK_I 4 8 18 C519 0.1U 19 10 CLK_OUT DVSS [1,2] SPOUT1 C518 120P HPOUT – 3-5 – [6] 2 SYNC SCLK SDIN 7 1 1 2 20 ER2 2 YMU_SYNC YMU_SCLK YMU_SDIN [2,6] T502 [1] [1] [1] DVDD U504 14 BUZZER T501 C512 0.1U C526 4.7U 13 C525 2.2U 9 SC1563ISK-3.0 AVDD C527 TBD N O I C G AVSS 1 2 3 YMU_AVCC_ON 3 R522 0R [1] C520 TBD 3.6. Circuit Diagram-6 MIC_PWR VBAT U601 AUDIO_ON N O I C G R626 2.4K 5 MIC_PWR TP601 TP_MIC 4 C621 0.1U LP2985AIMX5-2.5 C629 2.2U C601 10N C602 10U C626 10U R602 4.7K C603 0.1U C627 0.1U R621 0R MIC601 VINNORP C623 100P MICROPHONE VANA C620 0.1U R630 0R R606 4.7K VMEM C622 0.1U R620 0R [2] R632 100K VINAUXP C624 100P R603 0 MIC_PWR R631 TBD [2] R628 TBD C608 33P T603 2 C607 33P 1 VINNORN T602 2 [2] C606 TBD R624 0R 1 2 C605 TBD 1 [2] R623 0R [1] HANDFREE_IN VINAUXN C610 33P R629 TBD C611 33P R634 0R C612 TBD J601 1 4 6 5 3 2 EXT_SPK R609 1M R615 47K C614 0.1uF [5] R611 0R R610 1M C630 2.2uF C616 10uF HPOUT R625 0R C628 10uF [5] VOICEOUT C615 33P – 3-6 – R608 TBD T606 -B 1 2 YMU_AVCC T605 - B 1 2 EXT_MIC T604 -B 1 2 [1] 1 2 3 MIC_PWR R633 0R PHONEJACK-B 3.7. Circuit Diagram-7 VM EM KEYCOL_0 KEYCOL_1 KEYCOL_2 KEYCOL_3 KEYCOL_4 SW70 1 SW7 02 2 1 KEY [*] SW70 3 2 1 KEY [7] SW7 04 2 1 KEY [4] 1 KEY [1] SW70 6 SW7 07 2 1 SW70 8 2 1 1 KEY [5] KEY [2] SW71 1 SW7 12 SW71 3 SW7 14 2 1 KEY [#] 2 KEY [9] 1 2 KEY [6] 1 1 2 [1] 1 2 C734 0.1U [1,4] SOFTKEY_LEFT [1] ADD[0..21] 2 D15 D14 D13 D12 D11 D10 D9 D8 ADD[0..21] 1 VM EM 2 KEY [SEND] KEYROW_3 [1] R708 100K [1] [1,4] R707 10K SW71 8 2 LCDCTL WE ADD0 [1] NRESET_LCD [4] POWERKEY & END POWER_KEY LCDCS VBAT C732 C731 TBD 0.1UF TBD C730 C729 C728 C727 C726 C725 C724 C723 C722 C721 TBD TBD TBD 33pF 33pF 33pF 33pF TBD TBD VBAT D701 D702 D703 D704 D705 D706 D709 LED - B LED - B LED - B LED - B LED - B LED - B HT-110NB5CT - B D710 HT-110NB5CT - B M 701 + Samsung(AY010300035) D713 1SS355 A 2 4 8 7 6 5 2 - R702 150 1 2 3 4 R703 33R R704 0R U702 R705 1K [1] C86 VSS V5 V4 V3 V2 V1 CAP2+ CAP2CAP1CAP1+ CAP3VOUT VSS VDD D7 D6 D5 D4 D3 D2 D1 D0 RD/E WR/R/W A0 RES CS1 [3] 1 3 1 D[0..15] D[0..15] SW7 17 SOFTKEY_RIGHT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SW7 15 [1,4] 1 C708 0.47U C709 1U KEYROW_2 SW71 6 C707 1U C705 0.47U [1] KEY_[DOWN] 2 KEY [3] 1U/0805 -B U701 C706 1U KEYROW_1 1 C710 SW7 10 2 KEY [8] C701 4.7U C704 0.47U C733 0.1U 2 KEY_[UP] SW7 09 2 KEY [0] R701 1M C703 0.47U SW7 05 2 KEYROW_0 1 C702 0.47U 1 1 [1] [1] [1] [1] [1] BACKLIGHT 6 C1 C2 3 2 B1 B2 5 1 E1 E2 4 FFB2222A – 3-7 – R706 100R VIBRATOR_ON [1] C720 TBD LCD interface Connect to LCM 3.8. Circuit Diagram-8 TP4 [9] VRF [9] VTX TP2 TP1 RXIP RXIN RXQP RXQN VRF L1202 27n C1285 100n C1288 33p C1286 22p C1203 33p [9] TP3 C1283 33p C1284 10p L1262 12n 12n R1277 JP GSMTX C1269 R1281 JP R1275 JP L1261 100n C1210 2.7p R1276 JP B1261 BEAD VSYN C1215 18p DCSTX TP5 [1] [1,2,9] [1,9] [1] TP8 C1208 2.2n C1209 39p C1207 39p R1203 220/1% R1202 510/1% L1201 180n/0603 RXEN1 TXEN GSMEN DCSEN R1269 10 [9] VRF C1281 100p R1279 51 C1211 15p U1231 GSMRX 1 2 IN G G OUT 4 3 U1232 [9] DCSRX G OUT IN G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 L1237 2n2 220p R1265 CX74017 C1266 680p 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 C1237 C1238 470p 470p C1204 22p 18p C1212 0p5 U1233 [9] PCSRX G OUT IN G R1231 JP SRF1960NMC31K C1202 100p C1213 0p5 – 3-8 – C1201 100p TP7 TP10 LE CLK DATA [1] [1] [1] SXEN [1] 13MHz [3] C1290 5p VTCXO C1276 100n R1291 NM C1278 100n R1267 10 C1280 100n R1268 10 8 7 6 5 4 3 TP6 C1279 22p C1277 22p C1235 C1267 8n2 R1290 10k SRF1842NHC31K 1 2 C1274 100n R1266 10 C1262 10P L1266 82n R1232 39k/1% 4 3 5k6 [9] B1262 BEAD TP9 BYP VDD LE CLK DATA LD_MUX SXEN VCCFN_CP LOCP GNDCP GNDFN FREF VCCF VCCD GNDD NC NC Tx/D TXTUNE RXEN TXEN PCO1 PCO2 VTXCP VCC1 TXCP TXFB LNA/G GNDLNA/G LNA/D FEEN LNA/P NC NC L1235 3n3 L1234 8n2 EPCOS B7707 1 2 C1234 15p U1234 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 [9] C1268 C1271 22p C1273 0.1U R1264 2K 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 R1205 390 10u TX/G NC NC NC VCCTXVCO VCC4 RXIP RXIN RXQP RXQN LON LOP VCC3 VCCLO LOTUNE R1204 510/1% C1272 FILTN FILTP TXIP TXIN TXQP TXQN TXIFP TXIFN VCC2 CAPIP CAPIN CAPQP CAPQN LPFADJ T/H [9] [2] [2] [2] [2] R1201 JP R1-2 R2-2 R3-2 R4-2 R1-1 R2-1 R3-1 R4-1 1 2 3 4 B1263 BEAD VRF R1271 JP TXQN TXQP TXIN TXIP [2] [2] [2] [2] [9] 3.9. Circuit Diagram-9 VBAT AN1131 C1109 33p C1145 6.8p C1146 0 L1132 8n2 11 2 8 GND GND 3 P_RX VC3 4 D_RX GND 5 [8] DCSRX 10 SHS-L090TL L1143 DNI 8 VCC2 4 5 VBATT 4 PA ENABLE 3 PA_EN [1] BAND SELECT 2 GSMEN [1,8] DCS IN 1 DCSTX [8 ] C1140 [8] R1111 110K [2] R1112 49.9K TP13 1nF 2 C1178 DNI 1 GND C1106 DNI C1105 2.7p 1 R1113 180 U1132 6 2 TRSW3 [1] TRSW1 [1] TXEN [1,2,8] TRSW2 [1] VRF [8] 4.7K 1 5 3 C1144 33p 6 GSMRX U1103 4 EM B 3 2 1 C1137 10p OUT BYP C1112 1u VCC GND CTL 1 2 3 LDO/MAX8878EUK-2.9 5 C1138 10p 4.7K 3 5 4 4.7K L1133 DNI R1115 100K C1136 33p 4.7K [8] 3 VREG GSMTX RAMP 3 ANT PCSRX 18p 13 12 11 D/P_TX [8] C1120 G_TX GND VC1 7 G_TX GND VC2 GND 9 6 R1102 6 C1142 12p VRAMP GSM OUT 16 15 14 L1135 DNI 7 DCS OUT L1101 JP R1101 1 2 GSM IN RF3110 C1147 1n8 9 U1133 R1114 180 C1107 DNI L1136 DNI C1141 33p VCC2 C1132 39p 12 U1101 L1140 DNI 10 GND GND 1 4 6 C1179 1pF 5 L1131 6.8nH IN 3 OUT GND 2 4 L1139 JP GND L1144 1.8nH C1111 220U M M 8430-2600 VCC OUT J1131 C1110 100n C1177 4.7U C1113 10n 4 EM B 3 U1131 U1173 1 [8] VTX [8] VSYN [1] RFEN 2 3 4 C1175 1U C1174 1U OUTA OUTB OUTC VCC ENBC GND ENA VREF M AS9122 8 7 6 5 C1172 10n C1173 10U C1176 0.1U – 3-9 – 4. LAYOUT DIAGRAMS U304 E13.000 U1173 9122 MC-222243AF9 -B85X-BT3 U1234 AD6521ACA CX74017 ACBM U601 LAUA 5 U504 Y757B RF3110 U309 43FCX U301 ADP3408 U1101 AD6522N U505 6330 – 4-1 –
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