Mitsubishi Electronics Digital Smoker Qseries Users Manual QCPU Programming (Common Instruction)

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SAFETY PRECAUTIONS
(Always read these cautions before using the product)
Before using this product, please read this manual and the related manuals introduced in this manual, and pay
full attention to safety to handle the product correctly.
Please store this manual in a safe place and make it accessible when required. Always forward a copy of the
manual to the end user.

A-1

REVISIONS
*The manual number is given on the bottom left of the back cover.
Print Date

*Manual Number

Revision

Dec., 2008

SH (NA)-080809ENG-A First edition

Mar., 2009

SH (NA)-080809ENG-B Partial corrections
Section 3.3, 3.8, 5.1.3, 6.1.7, 6.2.14, 7.3.3, 7.11.18, 7.11.19, 7.12.1.5,12.7, 7.12.11, 7.12.25,
7.12.26, 7.13.4, 7.13.5, 7.15.7, 7.15.8

Jul., 2009

SH (NA)-080809ENG-C Revision because of function support by the Universal model QCPU having a
serial number "11043" or later
Partial corrections
Section 2.1, 2.5.6, 2.5.18, 2.5.20, 7.6.9, 7.12.7, 7.12.11, 12.1.3, 12.1.4, APPENDIX 1.2, 1.3, 1.4.2,
3, 5.1
Additions
Section 2.5.16, 7.16, 7.18.10
Modification
Section 2.5.21
Section 9.14
Section 9.15.3

2.5.22, Section 2.5.22
7.6.1, Section 9.15
7.16.3, Section 9.1

2.5.21, Section 9.13

7.16, Section 9.15.1

7.16.2,

7.18.9, Section 9.2

7.18.11, Section 9.3

7.18.12,

7.18.15, Section 9.7

7.18.16,

Section 9.4

7.18.13, Section 9.5

7.18.14, Section 9.6

Section 9.8

7.18.17, Section 9.9

7.18.18, Section 9.10

Section 9.11.1
Chapter 10

9.1.1, Section 9.11.2
11, Chapter 11

7.6.10,

7.16.1, Section 9.15.2

9.1.2, Section 9.12

7.18.19, Section 9.11

9.1,

9.2, Section 9.12.1

9.2.1,

10

Japanese Manual Version SH-080804-B

This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses.
Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may
occur as a result of using the contents noted in this manual.
© 2008 MITSUBISHI ELECTRIC CORPORATION

A-2

INTRODUCTION
This manual explains the common instructions required for programming of the QCPU.
• The common instructions refer to all instructions except those dedicated to special function
modules (such as AJ71QC24 and AJ71PT32-S3) and to AD57 models, as well as PID control instructions, SFC
instructions and ST instructions.
Before using this product, please read this manual and the relevant manuals carefully and develop familiarity with
the functions and performance of the Q series programmable controller to handle the product correctly.
■ Relevant CPU module
CPU module

Basic model QCPU
High Perfomance model QCPU
Process CPU
Redundant CPU

Model

Q00JCPU, Q00CPU, Q01CPU
Q02CPU, Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU
Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU
Q12PRHCPU, Q25PRHCPU
Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU,
Q04UDHCPU, Q06UDHCPU, Q10UDHCPU, Q13UDHCPU,

Universal model QCPU

Q20UDHCPU, Q26UDHCPU, Q03UDECPU, Q04UDEHCPU,
Q06UDEHCPU, Q10UDEHCPU, Q13UDEHCPU,
Q20UDEHCPU

A-3

CONTENTS
SAFETY PRECAUTIONS ..................................................................................................................A - 1
REVISIONS .......................................................................................................................................A - 2
INTRODUCTION ...............................................................................................................................A - 3
CONTENTS .......................................................................................................................................A - 4
MANUALS........................................................................................................................................A - 14

Common Instructions 1/2
1. GENERAL DESCRIPTION
1.1

Related Programming Manuals

1-2

1.2

Abbreviations and Generic Names

1-5

2. INSTRUCTION TABLES

2 - 1 to 2 - 62

2.1

Types of Instructions

2-2

2.2

How to Read Instruction Tables

2-4

2.3

Sequence Instructions

2-6

2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.4

2.5

Contact instructions ...................................................................................................... 2 - 6
Association instructions ................................................................................................ 2 - 7
Output instructions........................................................................................................ 2 - 8
Shift instructions ........................................................................................................... 2 - 8
Master control instructions............................................................................................ 2 - 9
Termination instructions ............................................................................................... 2 - 9
Other instructions ......................................................................................................... 2 - 9

Basic instructions

2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.4.8

2 - 10

Comparison operation instructions ............................................................................. 2 - 10
Arithmetic operation instructions ................................................................................ 2 - 16
Data conversion instructions ...................................................................................... 2 - 22
Data transfer instructions............................................................................................ 2 - 24
Program branch instructions....................................................................................... 2 - 27
Program execution control instructions ...................................................................... 2 - 27
I/O refresh instructions ............................................................................................... 2 - 27
Other convenient instructions ..................................................................................... 2 - 28

Application Instructions

2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.5.8
2.5.9
2.5.10

A-4

1 - 1 to 1 - 8

2 - 29

Logical operation instructions ..................................................................................... 2 - 29
Rotation instructions ................................................................................................... 2 - 32
Shift instructions ......................................................................................................... 2 - 33
Bit processing instructions.......................................................................................... 2 - 34
Data processing instructions ...................................................................................... 2 - 35
Structure creation instructions .................................................................................... 2 - 38
Data table operation instructions ................................................................................ 2 - 40
Buffer memory access instructions............................................................................. 2 - 41
Display instructions..................................................................................................... 2 - 41
Debugging and failure diagnosis instructions ............................................................. 2 - 42

2.5.11
2.5.12
2.5.13
2.5.14
2.5.15
2.5.16
2.5.17
2.5.18
2.5.19
2.5.20
2.5.21
2.5.22

Character string processing instructions .................................................................... 2 - 43
Special function instructions ....................................................................................... 2 - 46
Data control instructions ............................................................................................. 2 - 49
Switching instructions ................................................................................................. 2 - 51
Clock instructions ....................................................................................................... 2 - 52
Expansion clock instruction ........................................................................................ 2 - 55
Program control instructions....................................................................................... 2 - 56
Other instructions ....................................................................................................... 2 - 57
Instructions for Data Link............................................................................................ 2 - 59
Multiple CPU dedicated instruction............................................................................. 2 - 60
Multiple CPU high-speed transmission dedicated instruction..................................... 2 - 60
Redundant system instructions (For Redundant CPU) .............................................. 2 - 61

3. CONFIGURATION OF INSTRUCTIONS

3 - 1 to 3 - 48

3.1

Configuration of Instructions

3-2

3.2

Designating Data

3-3

3.2.1
3.2.2
3.2.3
3.2.4
3.2.5

Using bit data................................................................................................................ 3 - 3
Using word (16 bits) data.............................................................................................. 3 - 4
Using double word data (32 bits).................................................................................. 3 - 6
Using real number data ................................................................................................ 3 - 8
Using character string data......................................................................................... 3 - 11

3.3

Indexing

3 - 12

3.4

Indirect Specification

3 - 23

3.5

Reducing Instruction Processing Time

3 - 25

3.5.1
3.5.2

Subset Processing...................................................................................................... 3 - 25
Operation processing with standard device registers (Z)
(only Universal model QCPU) ............................................................................ 3 - 26

3.6

Cautions on Programming (Operation Errors)

3 - 27

3.7

Conditions for Execution of Instructions

3 - 33

3.8

Counting Step Number

3 - 34

3.9

Operation when the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device

3 - 39

3.10 Precautions for Use of File Registers

4. HOW TO READ INSTRUCTIONS
5. SEQUENCE INSTRUCTIONS
5.1

Contact Instructions

5.1.1
5.1.2
5.1.3
5.2

4 - 1 to 4 - 4
5 - 1 to 5 - 60
5-2

Operation start, series connection, parallel connection (LD,LDI,AND,ANI,OR,ORI).... 5 - 2
Pulse operation start, pulse series connection, pulse parallel connection
(LDP,LDF,ANDP,ANDF,ORP,ORF) ..................................................................... 5 - 5
Pulse NOT operation start, pulse NOT series connection, pulse NOT parallel connection
(LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI) ............................................................... 5 - 7

Association Instructions

5.2.1
5.2.2

3 - 44

5 - 10

Ladder block series connection and parallel connection (ANB,ORB) ........................ 5 - 10
Operation results push,read,pop (MPS,MRD,MPP) ................................................... 5 - 12

A-5

5.2.3
5.2.4
5.2.5
5.3

Output Instructions

5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
5.4

5.6

5.7

Comparison Operation Instructions

6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.2

A-6

6 - 1 to 6 - 168
6-2

BIN 16-bit data comparisons (=,<>,>,<=,<,>=) ............................................................. 6 - 2
BIN 32-bit data comparisons (D=,D<>,D>,D<=,D<,D>=) ............................................. 6 - 4
Floating decimal point data comparisons (Single precision)
(E=,E<>,E>,E<=,E<,E>=)..................................................................................... 6 - 6
Floating decimal point data comparisons (Double precision)
(ED=,ED<>,ED>,ED<=,ED<,ED>=) ..................................................................... 6 - 8
Character string data comparisons ($=,$<>,$>,$<=,$<,$>=) ..................................... 6 - 11
BIN block data comparisons (BKCMP … ,BKCMP … P) ............................................ 6 - 15
BIN 32-bit block data comparisons (DBKCMP … ,DBKCMP … P) ............................ 6 - 18

Arithmetic Operation Instructions

6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9

5 - 55

Sequence program stop (STOP) ................................................................................ 5 - 55
No operations (NOP,NOPLF,PAGE n) ....................................................................... 5 - 57

6. BASIC INSTRUCTIONS
6.1

5 - 51

End main routine program (FEND)............................................................................. 5 - 51
End sequence program (END) ................................................................................... 5 - 53

Other instructions

5.7.1
5.7.2

5 - 47

Setting and resetting the master control (MC,MCR)................................................... 5 - 47

Termination Instructions

5.6.1
5.6.2

5 - 44

Bit device shifts (SFT(P))............................................................................................ 5 - 44

Master Control Instructions

5.5.1

5 - 20

Out instruction (excluding timers, counters, and annunciators) (OUT)....................... 5 - 20
Timers (OUT T,OUTH T) ............................................................................................ 5 - 22
Counter (OUT C) ........................................................................................................ 5 - 26
Annunciator output (OUT F) ....................................................................................... 5 - 28
Setting devices (except for annunciators) (SET) ........................................................ 5 - 30
Resetting devices (except for annunciators) (RST).................................................... 5 - 32
Setting and resetting the annunciators (SET F,RST F) .............................................. 5 - 35
Leading edge and trailing edge outputs (PLS,PLF).................................................... 5 - 37
Bit device output reverse (FF) .................................................................................... 5 - 40
Pulse conversions of direct outputs (DELTA(P)) ........................................................ 5 - 42

Shift Instructions

5.4.1
5.5

Operation results inversion (INV) ............................................................................... 5 - 15
Operation result conversions (MEP,MEF) .................................................................. 5 - 17
Pulse conversions of edge relay operation results (EGP,EGF).................................. 5 - 18

6 - 22

BIN 16-bit addition and subtraction operations (+(P),-(P)) ......................................... 6 - 22
BIN 32-bit addition and subtraction operations (D+(P),D-(P)) .................................... 6 - 26
BIN 16-bit multiplication and division operations (*(P),/(P))........................................ 6 - 30
BIN 32-bit multiplication and division operations (D*(P),D/(P)) .................................. 6 - 32
BCD 4-digit addition and subtraction operations (B+(P),B-(P)) .................................. 6 - 34
BCD 8-digit addition and subtraction operations (DB+(P),DB-(P)) ............................. 6 - 38
BCD 4-digit multiplication and division operations (B*(P),B/(P)) ................................ 6 - 42
BCD 8-digit multiplication and division operations (DB*(P),DB/(P)) ........................... 6 - 44
Addition and subtraction of floating decimal point data (Single precision)
(E+(P),E-(P)) ...................................................................................................... 6 - 46

6.2.10 Addition and subtraction of floating decimal point data (Double precision)
(ED+(P),ED-(P)) ................................................................................................. 6 - 50
6.2.11 Multiplication and division of floating decimal point data (Single precision)
(E*(P),E/(P)) ....................................................................................................... 6 - 54
6.2.12 Multiplication and division of floating decimal point data (Double precision)
(ED*(P),ED/(P)) .................................................................................................. 6 - 56
6.2.13 Block addition and subtraction (BK+(P),BK-(P))......................................................... 6 - 59
6.2.14 BIN 32-bit data block addition and subtraction operations (DBK+(P),DBK-(P)) ........ 6 - 62
6.2.15 Linking character strings ($+(P)) ................................................................................ 6 - 65
6.2.16 Incrementing and decrementing 16-bit BIN data (INC(P),DEC(P)) ............................ 6 - 69
6.2.17 Incrementing and decrementing 32-bit BIN data (DINC(P),DDEC(P)) ....................... 6 - 71
6.3

Data conversion instructions

6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
6.3.13
6.3.14
6.3.15
6.3.16
6.3.17
6.4

6.5

Conversion from BIN data to 4-digit and 8-digit BCD (BCD(P),DBCD(P)) ................. 6 - 73
Conversion from BCD 4-digit and 8-digit data to BIN data (BIN(P),DBIN(P)) ............ 6 - 75
Conversion from BIN 16 and 32-bit data to floating decimal point (Single precision)
(FLT(P),DFLT(P)) ............................................................................................... 6 - 78
Conversion from BIN 16 and 32-bit data to floating decimal point (Double precision)
(FLTD(P),DFLTD(P)).......................................................................................... 6 - 81
Conversion from floating decimal point data to BIN16- and
32-bit data (Single precision) (INT(P),DINT(P)) ................................................. 6 - 83
Conversion from floating decimal point data to BIN16- and
32-bit data (Double precision) (INTD(P),DINTD(P)) ........................................... 6 - 86
Conversion from BIN 16-bit to BIN 32-bit data (DBL(P)) ............................................ 6 - 88
Conversion from BIN 32-bit to BIN 16-bit data (WORD(P))........................................ 6 - 89
Conversion from BIN 16 and 32-bit data to Gray code (GRY(P),DGRY(P)) .............. 6 - 90
Conversion of Gray code to BIN 16 and 32-bit data (GBIN(P),DGBIN(P))................. 6 - 92
Complement of 2 of BIN 16- and 32-bit data (sign reversal) (NEG(P),DNEG(P)) ...... 6 - 94
Floating-point sign invertion (Single precision) (ENEG(P)) ........................................ 6 - 96
Floating-point sign invertion (Double precision) (EDNEG(P)) .................................... 6 - 97
Conversion from block BIN 16-bit data to BCD 4-digit data (BKBCD(P))................... 6 - 98
Conversion from block BCD 4-digit data to block BIN 16-bit data (BKBIN(P)) ......... 6 - 100
Single precision to Double precision conversion (ECON(P)) ................................... 6 - 102
Double precision to Single precision conversion (EDCON(P))................................. 6 - 104

Data Transfer Instructions

6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
6.4.9
6.4.10
6.4.11

6 - 106

16-bit and 32-bit data transfers (MOV(P),DMOV(P))................................................ 6 - 106
Floating-point data transfer (Single precision) (EMOV(P)) ....................................... 6 - 108
Floating-point data transfer (Double precision) (EDMOV(P)) ................................... 6 - 110
Character string transfers ($MOV(P))....................................................................... 6 - 112
16-bit and 32-bit negation transfers (CML(P),DCML(P)) .......................................... 6 - 114
Block 16-bit data transfers (BMOV(P)) ..................................................................... 6 - 117
Identical 16-bit data block transfers (FMOV(P)) ....................................................... 6 - 120
Identical 32-bit data block transfers (DFMOV(P))..................................................... 6 - 122
16-bit and 32-bit data exchanges (XCH(P),DXCH(P)) ............................................. 6 - 124
Block 16-bit data exchanges (BXCH(P)) .................................................................. 6 - 126
Upper and lower byte exchanges (SWAP(P)) .......................................................... 6 - 128

Program Branch Instructions

6.5.1
6.5.2

6 - 73

6 - 129

Pointer branch instructions (CJ,SCJ,JMP) ............................................................... 6 - 129
Jump to END (GOEND)............................................................................................ 6 - 132

A-7

6.6

Program Execution Control Instructions

6.6.1
6.6.2
6.7
6.8

Interrupt disable/enable instructions, interrupt program mask (DI,EI,IMASK) .......... 6 - 133
Recovery from interrupt programs (IRET) ................................................................ 6 - 139

I/O Refresh Instructions

6.7.1

Logical operation instructions

7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.2

7.3

7.4

7.5

A-8

7 - 46

7 - 59

Bit set and reset for word devices (BSET(P),BRST(P)) ............................................. 7 - 59
Bit tests (TEST(P),DTEST(P)).................................................................................... 7 - 61
Batch reset of bit devices (BKRST(P)) ....................................................................... 7 - 64

Data processing instructions

7.5.1
7.5.2
7.5.3
7.5.4

7 - 35

n-bit shift to right or left of 16-bit data (SFR(P),SFL(P)) ............................................. 7 - 46
1-bit shift to right or left of n-bit data (BSFR(P),BSFL(P)) .......................................... 7 - 49
n-bit shift to right or left of n-bit data (SFTBR(P),SFTBL(P)) ...................................... 7 - 51
1-word shift to right or left of n-word data (DSFR(P),DSFL(P)) .................................. 7 - 54
n-bit shift to right or left of n-word data (SFTWR(P),SFTWL(P)) ................................ 7 - 56

Bit processing instructions

7.4.1
7.4.2
7.4.3

7-2

Right rotation of 16-bit data (ROR(P),RCR(P)) .......................................................... 7 - 35
Left rotation of 16-bit data (ROL(P),RCL(P)) .............................................................. 7 - 38
Right rotation of 32-bit data (DROR(P),DRCR(P)) ..................................................... 7 - 41
Left rotation of 32-bit data (DROL(P),DRCL(P))......................................................... 7 - 44

Shift instruction

7.3.1
7.3.2
7.3.3
7.3.4
7.3.5

7 - 1 to 7 - 452

Logical products with 16-bit and 32-bit data (WAND(P),DAND(P)).............................. 7 - 3
Block logical products (BKAND(P)) .............................................................................. 7 - 9
Logical sums of 16-bit and 32-bit data (WOR(P),DOR(P))......................................... 7 - 11
Block logical sum operations (BKOR(P)).................................................................... 7 - 17
16-bit and 32-bit exclusive OR operations (WXOR(P),DXOR(P)) .............................. 7 - 19
Block exclusive OR operations (BKXOR(P)) .............................................................. 7 - 25
16-bit and 32-bit data exclusive NOR operations (WXNR(P),DXNR(P)).................... 7 - 27
Block exclusive NOR operations (BKXNR(P))............................................................ 7 - 33

Rotation instruction

7.2.1
7.2.2
7.2.3
7.2.4

6 - 143

Counter 1-phase input up or down (UDCNT1) ......................................................... 6 - 143
Counter 2-phase input up or down (UDCNT2) ......................................................... 6 - 146
Teaching timer (TTMR) ............................................................................................ 6 - 149
Special function timer (STMR).................................................................................. 6 - 151
Rotary table shortest direction control (ROTC) ........................................................ 6 - 154
Ramp signal (RAMP)................................................................................................ 6 - 157
Pulse density measurement (SPD) .......................................................................... 6 - 160
Fixed cycle pulse output (PLSY) .............................................................................. 6 - 162
Pulse width modulation (PWM) ................................................................................ 6 - 164
Matrix input (MTR).................................................................................................... 6 - 166

7. APPLICATION INSTRUCTIONS
7.1

6 - 141

I/O refresh (RFS(P)) ................................................................................................. 6 - 141

Other Convenient Instructions

6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
6.8.7
6.8.8
6.8.9
6.8.10

6 - 133

7 - 66

16-bit and 32-bit data searches (SER(P),DSER(P))................................................... 7 - 66
16-bit and 32-bit data checks (SUM(P),DSUM(P))..................................................... 7 - 69
Decoding from 8 to 256 bits (DECO(P)) ..................................................................... 7 - 71
Encoding from 256 to 8 bits (ENCO(P)) ..................................................................... 7 - 73

7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10
7.5.11
7.5.12
7.5.13
7.5.14
7.5.15
7.6

Structure creation instructions

7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.6.7
7.6.8
7.6.9
7.6.10
7.6.11
7.6.12
7.6.13
7.7

7.8.2
7.9

7 - 160

Reading 1-/2-word data from the intelligent function module
(FROM(P),DFRO(P))........................................................................................ 7 - 160
Writing 1-/2-word data to intelligent function module (TO(P),DTO(P)) ..................... 7 - 163

Display instructions

7.9.1
7.9.2
7.9.3

7 - 151

Writing data to the data table (FIFW(P))................................................................... 7 - 151
Reading oldest data from tables (FIFR(P))............................................................... 7 - 153
Reading newest data from data tables (FPOP(P)) ................................................... 7 - 155
Deleting and inserting data from and in data tables (FDEL(P),FINS(P)).................. 7 - 157

Buffer memory access instruction

7.8.1

7 - 105

FOR to NEXT instruction loop (FOR,NEXT)............................................................. 7 - 105
Forced end of FOR to NEXT instruction loop (BREAK(P))....................................... 7 - 108
Subroutine program calls (CALL(P)) ........................................................................ 7 - 110
Return from subroutine programs (RET) .................................................................. 7 - 115
Subroutine program output OFF calls (FCALL(P)) ................................................... 7 - 116
Subroutine calls between program files (ECALL(P)) ................................................ 7 - 120
Subroutine output OFF calls between program files (EFCALL(P))........................... 7 - 125
Subroutine program call (XCALL)............................................................................. 7 - 129
Refresh instruction (COM)........................................................................................ 7 - 134
Select Refresh Instruction (COM)............................................................................. 7 - 137
Select Refresh Instruction (CCOM) .......................................................................... 7 - 141
Index modification of entire ladder (IX,IXEND)......................................................... 7 - 144
Designation of modification values in index modification of entire ladders
(IXDEV,IXSET)................................................................................................. 7 - 148

Data Table Operation Instructions

7.7.1
7.7.2
7.7.3
7.7.4
7.8

7-segment decode (SEG(P)) ...................................................................................... 7 - 75
4-bit dissociation of 16-bit data (DIS(P))..................................................................... 7 - 77
4-bit linking of 16-bit data (UNI(P)) ............................................................................. 7 - 79
Dissociation or linking of random data (NDIS(P),NUNI(P)) ........................................ 7 - 81
Data dissociation and linking in byte units (WTOB(P),BTOW(P)) .............................. 7 - 85
Maximum value search for 16- and 32-bit data (MAX(P),DMAX(P)) .......................... 7 - 89
Minimum value search for 16- and 32-bit data (MIN(P),DMIN(P)) ............................. 7 - 92
BIN 16 and 32 bits data sort operations (SORT,DSORT) .......................................... 7 - 95
Calculation of totals for 16-bit data (WSUM(P)) ......................................................... 7 - 99
Calculation of totals for 32-bit data (DWSUM(P))..................................................... 7 - 101
Calculation of averages for 16-bit or 32-bit data (MEAN(P),DMEAN(P)) ................. 7 - 103

7 - 166

Print ASCII code instruction (PR) ............................................................................. 7 - 166
Print comment instruction (PRC) .............................................................................. 7 - 169
Error display and annunciator reset instruction (LEDR) ........................................... 7 - 172

7.10 Debugging and failure diagnosis instructions

7 - 175

7.10.1 Special format failure checks (CHKST,CHK) ........................................................... 7 - 175
7.10.2 Changing check format of CHK instruction (CHKCIR,CHKEND) ............................. 7 - 179
7.11 Character string processing instructions

7 - 183

7.11.1 Conversion from BIN 16-bit or 32-bit to decimal ASCII (BINDA(P),DBINDA(P))...... 7 - 183
7.11.2 Conversion from BIN 16-bit or 32-bit data to hexadecimal ASCII
(BINHA(P),DBINHA(P)).................................................................................... 7 - 186

A-9

7.11.3 Conversion from BCD 4-digit and 8-digit to decimal ASCII data
(BCDDA(P),DBCDDA(P))................................................................................. 7 - 189
7.11.4 Conversion from decimal ASCII to BIN 16-bit and 32-bit data
(DABIN(P),DDABIN(P)).................................................................................... 7 - 192
7.11.5 Conversion from hexadecimal ASCII to BIN 16-bit and 32-bit data
(HABIN(P),DHABIN(P)).................................................................................... 7 - 195
7.11.6 Conversion from decimal ASCII to BCD 4-digit or 8-digit data
(DABCD(P),DDABCD(P))................................................................................. 7 - 198
7.11.7 Reading device comment data (COMRD(P)) ........................................................... 7 - 201
7.11.8 Character string length detection (LEN(P)) .............................................................. 7 - 204
7.11.9 Conversion from BIN 16-bit or 32-bit to character string (STR(P),DSTR(P)) ........... 7 - 206
7.11.10 Conversion from character string to BIN 16-bit or 32-bit data (VAL(P),DVAL(P)) .... 7 - 212
7.11.11 Conversion from floating decimal point to character string data (ESTR(P))............. 7 - 217
7.11.12 Conversion from character string to floating decimal point data (EVAL(P)) ............. 7 - 224
7.11.13 Conversion from hexadecimal BIN to ASCII (ASC(P)) ............................................. 7 - 228
7.11.14 Conversion from ASCII to hexadecimal BIN (HEX(P)) ............................................. 7 - 230
7.11.15 Extracting character string data from the right or left (RIGHT(P),LEFT(P)).............. 7 - 232
7.11.16 Random selection from and replacement in character strings (MIDR(P),MIDW(P))
........................................................................................................................ 7 - 235
7.11.17 Character string search (INSTR(P)) ......................................................................... 7 - 239
7.11.18 Insertion of character string (STRINS(P))................................................................. 7 - 241
7.11.19 Deletion of character string (STRDEL(P)) ................................................................ 7 - 243
7.11.20 Floating decimal point to BCD (EMOD(P)) ............................................................... 7 - 245
7.11.21 From BCD format data to floating decimal point (EREXP(P)) .................................. 7 - 248
7.12 Special function instructions
7.12.1
7.12.2
7.12.3
7.12.4
7.12.5
7.12.6
7.12.7
7.12.8
7.12.9
7.12.10
7.12.11
7.12.12
7.12.13
7.12.14
7.12.15
7.12.16
7.12.17
7.12.18
7.12.19
7.12.20
7.12.21
7.12.22
7.12.23
7.12.24

A-10

7 - 250

SIN operation on floating-point data (Single precision) (SIN(P)) .............................. 7 - 250
SIN operation on floating-point data (Double precision) (SIND(P)) .......................... 7 - 252
COS operation on floating-point data (Single precision) (COS(P)) .......................... 7 - 254
COS operation on floating-point data (Double precision) (COSD(P)) ...................... 7 - 256
TAN operation on floating-point data (Single precision) (TAN(P))............................ 7 - 258
TAN operation on floating-point data (Double precision) (TAND(P))........................ 7 - 260
SIN-1 operation on floating point data (Single precision) (ASIN(P)) ......................... 7 - 262
SIN-1 operation on floating-point data (Double precision) (ASIND(P)) ..................... 7 - 265
COS -1 operation on floating-point data (Single precision) (ACOS(P)) .................... 7 - 267
COS -1 operation on floating-point data (Double precision) (ACOSD(P)) ................ 7 - 269
TAN -1 operation on floating-point data (Single precision) (ATAN(P))...................... 7 - 271
TAN -1 operation on floating-point data (Double precision) (ATAND(P)).................. 7 - 273
Conversion from floating-point angle to radian (Single precision) (RAD(P)) ............ 7 - 275
Conversion from floating-point angle to radian (Double precision) (RADD(P)) ........ 7 - 277
Conversion from floating-point radian to angle (Single precision) (DEG(P)) ............ 7 - 279
Conversion from floating-point radian to angle (Double precision) (DEGD(P)) ........ 7 - 281
Exponentiation operation on floating-point data (Single precision) (POW(P)).......... 7 - 283
Exponentiation operation on floating-point data (Single precision) (POWD(P)) ....... 7 - 285
Square root operation for floating-point data (Single precision) (SQR(P)) ............... 7 - 287
Square root operation for floating-point data (Double precision) (SQRD(P)) ........... 7 - 289
Exponent operation on floating-point data (Single precision) (EXP(P)).................... 7 - 291
Exponent operation on floating-point data (Double precision) (EXPD(P))................ 7 - 294
Natural logarithm operation on floating-point data (Single precision) (LOG(P)) ....... 7 - 296
Natural logarithm operation on floating-point data (Double precision) (LOGD(P)) ... 7 - 298

7.12.25 Common logarithm operation on floating-point data (Single precision)
(LOG10(P))....................................................................................................... 7 - 300
7.12.26 Common logarithm operation on floating-point data (Double precision)
(LOG10D(P)) .................................................................................................... 7 - 302
7.12.27 Random number generation and series updates (RND(P),SRND(P)) ..................... 7 - 304
7.12.28 BCD 4-digit and 8-digit square roots (BSQR(P),BDSQR(P)) ................................... 7 - 306
7.12.29 BCD type SIN operation (BSIN(P))........................................................................... 7 - 309
7.12.30 BCD type COS operations (BCOS(P)) ..................................................................... 7 - 311
7.12.31 BCD type TAN operation (BTAN(P)) ........................................................................ 7 - 313
7.12.32 BCD type SIN -1 operations (BASIN(P)) ................................................................... 7 - 315
7.12.33 BCD type COS -1 operation (BACOS(P)) ................................................................. 7 - 317
7.12.34 BCD type TAN -1 operations (BATAN(P)) ................................................................ 7 - 319
7.13 Data Control Instructions

7 - 321

7.13.1 Upper and lower limit controls for BIN 16-bit and BIN 32-bit data
(LIMIT(P),DLIMIT(P)) ....................................................................................... 7 - 321
7.13.2 BIN 16-bit and 32-bit dead band controls (BAND(P),DBAND(P)) ............................ 7 - 324
7.13.3 Zone control for BIN 16-bit and BIN 32-bit data (ZONE(P),DZONE(P))................... 7 - 327
7.13.4 Scaling (Point-by-point coordinate data) (SCL(P),DSCL(P)).................................... 7 - 330
7.13.5 Scaling (Point-by-point coordinate data) (SCL2(P),DSCL2(P))................................ 7 - 334
7.14 File register switching instructions

7 - 337

7.14.1 Switching file register numbers (RSET(P))............................................................... 7 - 337
7.14.2 Setting files for file register use (QDRSET(P)) ......................................................... 7 - 339
7.14.3 File setting for comments (QCDSET(P)) .................................................................. 7 - 342
7.15 Clock instructions
7.15.1
7.15.2
7.15.3
7.15.4
7.15.5
7.15.6
7.15.7
7.15.8

7 - 344

Reading clock data (DATERD(P)) ............................................................................ 7 - 344
Writing clock data (DATEWR(P)) ............................................................................. 7 - 346
Clock data addition operation (DATE+(P)) ............................................................... 7 - 348
Clock data subtraction operation (DATE-(P)) ........................................................... 7 - 350
Time data conversion (from Hour/Minute/Second to Second) (SECOND(P)) .......... 7 - 352
Time data conversion (from Second to Hour/Minute/Second ) (HOUR(P)).............. 7 - 354
Date comparison (DT=,DT<>,DT>,DT<=,DT<,DT>=) .............................................. 7 - 356
Clock comparison (TM=,TM<>,TM>,TM<=,TM<,TM>=).......................................... 7 - 361

7.16 Expansion Clock Instructions

7 - 366

7.16.1 Reading expansion clock data (S(P).DATERD) ....................................................... 7 - 366
7.16.2 Expansion clock data addition operation (S(P).DATE+)........................................... 7 - 369
7.16.3 Expansion clock data subtraction operation (S(P).DATE-)....................................... 7 - 372
7.17 Program control instructions
7.17.1
7.17.2
7.17.3
7.17.4
7.17.5

Program standby instruction (PSTOP(P)) ................................................................ 7 - 377
Program output OFF standby instruction (POFF(P))................................................ 7 - 378
Program scan execution registration instruction (PSCAN(P)) .................................. 7 - 380
Program low speed execution registration instruction (PLOW(P)) ........................... 7 - 382
Program execution status check instruction (PCHK)................................................ 7 - 384

7.18 Other instructions
7.18.1
7.18.2
7.18.3
7.18.4

7 - 375

7 - 386

Resetting watchdog timer (WDT(P))......................................................................... 7 - 386
Timing pulse generation (DUTY) .............................................................................. 7 - 388
Time check instruction (TIMCHK)............................................................................. 7 - 390
Direct 1-byte read from file register (ZRRDB(P))...................................................... 7 - 391

A-11

7.18.5
7.18.6
7.18.7
7.18.8
7.18.9
7.18.10
7.18.11
7.18.12
7.18.13
7.18.14
7.18.15
7.18.16
7.18.17
7.18.18
7.18.19

File register direct 1-byte write (ZRWRB(P)) ............................................................ 7 - 393
Indirect address read operations (ADRSET(P)) ....................................................... 7 - 395
Numerical key input from keyboard (KEY) ............................................................... 7 - 396
Batch save or recovery of index register (ZPUSH(P),ZPOP(P)) .............................. 7 - 400
Reading Module Information (UNIRD(P))................................................................. 7 - 402
Reading module model name(TYPERD(P))............................................................. 7 - 406
Trace Set/Reset (TRACE,TRACER) ........................................................................ 7 - 411
Writing Data to Designated File (SP.FWRITE)......................................................... 7 - 413
Reading Data from Designated File (SP.FREAD) .................................................... 7 - 424
Writing Data to Standard ROM (SP.DEVST)............................................................ 7 - 436
Read Data from Standard ROM (S(P).DEVLD)........................................................ 7 - 438
Load Program from Memory Card (PLOADP).......................................................... 7 - 440
Unload Program from Program Memory (PUNLOADP) ........................................... 7 - 443
Load + Unload (PSWAPP) ....................................................................................... 7 - 445
High-speed Block Transfer of File Register (RBMOV(P)) ........................................ 7 - 448

Common Instructions 2/2
8. INSTRUCTIONS FOR DATA LINK
8.1

Network refresh instructions

8.1.1
8.2

Writing to the CPU Shared Memory of Host CPU

9.1.1
9.1.2
9.2

9 - 1 to 9 - 18
9-2

Write to Host CPU Shared Memory (S(P).TO) ............................................................. 9 - 4
Writing to host station CPU shared memory (TO(P), DTO(P))..................................... 9 - 7

Reading from the CPU Shared Memory of another CPU

9.2.1

8-6

Reading routing information (S(P)/Z(P).RTREAD) ....................................................... 8 - 6
Registering routing information (S(P)/Z(P).RTWRITE)................................................. 8 - 8

9. Multiple CPU dedicated instruction
9.1

8-2

Refresh instruction for the designated module (S(P)/J(P)/G(P).ZCOM)....................... 8 - 2

Reading/Writing Routing Information

8.2.1
8.2.2

8 - 1 to 8 - 10

9 - 11

Reading from Other CPU Shared Memory (FROM(P), DFRO(P)) ............................. 9 - 12

10. QCPU INSTRUCTIONS
10.1 Overview

10 - 1 to 10 - 20
10 - 2

10.2 Writing Devices to Another CPU (D(P).DDWR)

10 - 13

10.3 Reading Devices from Another CPU (D(P).DDRD)

10 - 17

11. QCPU INSTRUCTIONS
11.1 System Switching Instruction (SP.CONTSW)

12. ERROR CODES
12.1 Error Code List

11 - 1 to 11 - 4
11 - 2

12 - 1 to 12 - 84
12 - 2

12.1.1 Error codes ................................................................................................................. 12 - 3
12.1.2 Reading an error code................................................................................................ 12 - 3
12.1.3 Error code list (1000 to 1999) ..................................................................................... 12 - 4

A-12

12.1.4
12.1.5
12.1.6
12.1.7
12.1.8
12.1.9

Error code list (2000 to 2999) ................................................................................... 12 - 16
Error code list (3000 to 3999) ................................................................................... 12 - 34
Error code list (4000 to 4999) ................................................................................... 12 - 51
Error code list (5000 to 5999) ................................................................................... 12 - 66
Error code list (6000 to 6999) ................................................................................... 12 - 68
Error code list (7000 to 10000) ................................................................................. 12 - 78

12.2 Canceling of Errors

12 - 83

APPENDICES

App - 1 to App - 198

Appendix 1 OPERATION PROCESSING TIME

App - 2

Appendix 1.1
Appendix 1.2
Appendix 1.3

Definition .....................................................................................................App - 2
Operation Processing Time of Basic Model QCPU.....................................App - 3
Operation Processing Time of High Performance Model QCPU/Process CPU/
Redundant CPU ........................................................................................App - 21
Appendix 1.4
Operation Processing Time of Universal Model QCPU.............................App - 50
Appendix 1.4.1 Subset instruction processing time............................................................App - 50
Appendix 1.4.2 Processing time of instructions other than subset instruction ...................App - 66

Appendix 2 CPU PERFORMANCE COMPARISON

App - 114

Appendix 2.1
Appendix 2.1.1
Appendix 2.1.2
Appendix 2.1.3
Appendix 2.1.4
Appendix 2.1.5
Appendix 2.1.6
Appendix 2.1.7

Comparison of Q with AnNCPU, AnACPU, and AnUCPU ......................App - 114
Usable devices ........................................................................................App - 114
I/O control mode......................................................................................App - 115
Data that can be used by instructions .....................................................App - 115
Timer comparison....................................................................................App - 116
Comparison of counters ..........................................................................App - 117
Comparison of display instructions..........................................................App - 117
Instructions whose designation format has been changed
(Except dedicated instructions for AnACPU and AnUCPU) ....................App - 118
Appendix 2.1.8 AnACPU and AnUCPU dedicated instructions........................................App - 119
Appendix 3 SPECIAL RELAY LIST

App - 120

Appendix 4 SPECIAL REGISTER LIST

App - 146

Appendix 5 APPLICATION PROGRAM EXAMPLES
Appendix 5.1

INDEX

App - 198
n

Concept of Programs which Perform Operations of X , X ....................App - 198
n

Index - 1 to Index - 12

A-13

MANUALS
To understand the main specifications, functions, and usage of the CPU module, refer to the basic manuals.
Read other manuals as well when using a different type of CPU module and its functions.
Order each manual as needed, referring to the following list.
The numbers in the "CPU module" and the respective modules are as follows.
Nunber

CPU module

1)

Basic model QCPU

2)

High Perfomance model QCPU

3)

Process CPU

4)

Redundant CPU

5)

Universal model QCPU
:Basic manual,

Manual name

:Other CPU module manuals

Description

< Manual number (model code) >
■User’s manual

Specifications of the hardware (CPU modules,

QCPU User's Manual
(Hardware design, Maintenance and Inspection)
< SH-080483ENG (13JR73) >

power supply modules, base units, extension cables, and
memory cards), system maintenance and inspection,
troubleshooting, and error codes

QnUCPU User’s Manual
Functions, methods, and devices for programming
(Function Explanation, Program Fundamentals)
< SH-080807ENG (13JZ27) >

Qn(H)/QnPH/QnPRHCPU User's Manual
(Function Explanation, Program Fundamentals)

Functions, methods, and devices for programming

< SH-080808ENG (13JZ28) >
QnUCPU User's Manual
(Communication via Built-in Ethernet Port)
< SH-080811ENG (13JZ29) >

Functions for the communication via built-in Ethernet
port of the CPU module

■Programming Manual
QCPU Programming Manual (Common Instructions) How to use sequence instructions, basic instructions,
< SH-080809ENG (13JW10) > and application instructions
QCPU (Q Mode)/QnACPU Programming Manual
(SFC)

System configuration, performance specifications,

functions, programming, debugging, and error codes
< SH-080041 (13JF60) > for SFC (MELSAP3) programs

QCPU (Q Mode) Programming Manual (MELSAP-L) Programming methods, specifications, and functions
< SH-080072 (13JC03) > for SFC (MELSAP-L) programs
QCPU (Q Mode) Programming Manual
(Structured Text)

Programming methods using structured languages
< SH-080366E (13JF68) >

QCPU (Q Mode) / QnACPU Programming Manual
(PID Control Instructions)

Dedicated instructions for PID control
< SH-080040 (13JF59) >

QnPH/QnPRHCPU Programming Manual
(Process Control Instructions)
< SH-080316E (13JF59) >

A-14

Describes the dedicated instructions for performing process control.

CPU module
1)

2)

3)

4)

5)

Related Manuals

Manual name

Description

< Manual number (model code) >
CC-Link IE Controller Network Reference Manual

Specifications, procedures and settings before system operation, parameter

< SH-080668ENG (13JV16) > setting, programming, and troubleshooting of the CC-Link IE controller network module
Q Corresponding MELSECNET/H Network System Reference Explains the specifications for a MELSECNET/H network system for PLC to PLC
Manual (PLC to PLC network)

network. It explains the procedures and settings up to operation, setting the parame-

< SH-080049 (13JF92) > ters, programming and troubleshooting.
Q Corresponding MELSECNET/H Network System Refer- Explains the specifications for a MELSECNET/H network system for remote I/O
ence Manual (Remote I/O network)

network. It explains the procedures and settings up to operation, setting the

< SH-080124 (13JF96) > parameters, programming and troubleshooting.
Type MELSECNET, MELSECNET/B Data Link System
Reference Manual

< IB-66530 (13JF70) >
Q Corresponding Ethernet Interface Module
User's Manual (Application)
< SH-080010 (13JF70) >

Describes the general concept, specifications, and part names and settings for
MELSECNET (II) and MELSECNET/B.
Describes various functions of the Ethernet module: e-mail function, PLC CPU
status monitoring, communication via MELSECNET/H or MELSECNET/10 network system, communication using data link instructions, file transfer (using FTP)
and other functions.

A-15

MEMO

A-16

1

1

GENERAL
DESCRIPTION

1-1

This manual explains the common instructions required for programming of the QCPU.
The common instructions refer to all instructions except those dedicated to special function
modules (such as AJ71QC24 and AJ71PT32-S3) and to AD57 models, as well as PID control
instructions, SFC instructions and ST instructions.

1.1 Related Programming Manuals
Before reading this manual, check the functions, programming methods, devices and others that
are necessary to create programs with the CPU in the manuals below:
• QnUCPU User's Manual (Function Explanation, Program Fundamentals)
• Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals)
(1) High Performance model QCPU

Qn(H)/QnPH/
QnPRHCPU
User's Manual
(Function Explanation,
Program
Fundamentals)

Explains the functions,
programming methods,
devices and others that
are necessary to create
programs with the CPU.

This manual

QCPU
Programming
Manual (Common
Instructions)

Describes the instructions
other than those described
in the manuals on the right.

1-2

QCPU(Q Mode)/
QnACPU
Programming
Manual
(PID Control
Instructions)
Describes the instructions
to perform PID control.

QCPU(Q Mode)/
QnACPU
Programming
Manual (SFC)

QCPU(Q Mode)
Programming
Manual
(MELSAP-L)

Describes SFC.

Describes MELSAP-L.

QCPU(Q Mode)
Programming
Manual
(Structured Text)

Describes the ST language.

(2) Basic model QCPU

1
Qn(H)/QnPH/
QnPRHCPU
User's Manual
(Function Explanation,
Program
Fundamentals)

2

Explains the functions,
programming methods,
devices and others that
are necessary to create
programs with the CPU.

3
4

This manual

QCPU
Programming
Manual (Common
Instructions)

QCPU(Q Mode)/
QnACPU
Programming
Manual (PID
Control
Instructions)

Describes the instructions Describes the instructions
other than those described to perform PID control.
in the manuals on the right.

QCPU(Q Mode)/
QnACPU
Programming
Manual (SFC)

QCPU(Q Mode)
Programming
Manual
(MELSAP-L)

QCPU(Q Mode)
Programming
Manual
(Structured Text)

4
6

Describes SFC.

Describes MELSAP-L.

Describes the ST language.

7

(3) Process CPU and Redundant CPU

Explains the functions,
programming methods,
devices and others that
are necessary to create
programs with the CPU.

1.1 Related Programming Manuals

Qn(H)/QnPH/
QnPRHCPU
User's Manual
(Function Explanation,
Program
Fundamentals)

8

This manual

QCPU
Programming
Manual (Common
Instructions)

Describes the instructions
other than those described
in the manuals on the right.

QnPHCPU/
QnPRHCPU
Programming
Manual
(Process Control
Instructions)
Describes the instructions
to perform process control.

QCPU(Q Mode)/
QnACPU
Programming
Manual (SFC)

QCPU(Q Mode)
Programming
Manual
(MELSAP-L)

QCPU(Q Mode)
Programming
Manual
(Structured Text)

Describes SFC.

Describes MELSAP-L.

Describes the ST language.

1-3

(4) Universal model QCPU

QnUCPU
User's Manual
(Function Explanation,
Program
Fundamentals)

Explains the functions,
programming methods,
devices and others that
are necessary to create
programs with the CPU.

This manual

QCPU
Programming
Manual (Common
Instructions)

QCPU(Q Mode)/
QnACPU
Programming
Manual (PID
Control
Instructions)

Describes the instructions Describes the instructions
other than those described to perform PID control.
in the manuals on the right.

1-4

QCPU(Q Mode)/
QnACPU
Programming
Manual (SFC)

Describes SFC.

QCPU(Q Mode)
Programming
Manual
(MELSAP-L)

Describes MELSAP-L.

QCPU(Q Mode)
Programming
Manual
(Structured Text)

Describes the ST language.

1.2 Abbreviations and Generic Names
1
This manual uses the generic names and abbreviations shown below to refer to Q series CPU
modules, unless otherwise specified.
*

indicates a part of the model or version.

Generic term/Abbreviation

Description of Generic Name/Abbreviation

3

■ Series
Q series

2

Abbreviation for Mitsubishi MELSEC-Q series programmable controller

4

■ CPU module type
CPU module

Generic term for Basic model QCPU, High Performance model QCPU, Process CPU,
Redundant CPU and Universal model QCPU

Basic model QCPU

Generic term for Q00JCPU, Q00CPU and Q01CPU

High Performance model
QCPU

Generic term for Q02CPU, Q02HCPU, Q06HCPU, Q12HCPU and Q25HCPU

Process CPU

Generic term for Q02PHCPU, Q06PHCPU, Q12PHCPU and Q25PHCPU

Redundant CPU

Generic term for Q12PRHCPU and Q25PRHCPU

4
6
7

Generic term for Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU,
Universal model QCPU

Q04UDHCPU, Q06UDHCPU, Q10UDHCPU, Q13UDHCPU, Q20UDHCPU, Q26UDHCPU,
Q03UDECPU, Q04UDEHCPU, Q06UDEHCPU, Q10UDEHCPU, Q13UDEHCPU,

8

Q20UDEHCPU and Q26UDEHCPU

■ CPU module model
Generic term for Q00JCPU, Q00CPU, Q01CPU and Q02CPU

QnHCPU

Generic term for Q02HCPU, Q06HCPU, Q12HCPU and Q25HCPU

QnPHCPU

Generic term for Q02PHCPU, Q06PHCPU, Q12PHCPU and Q25PHCPU

QnPRHCPU

Generic term for Q12PRHCPU and Q25PRHCPU
Generic temr for Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU,

QnUCPU

Q04UDHCPU, Q06UDHCPU, Q10UDHCPU, Q13UDHCPU, Q20UDHCPU, Q26UDHCPU,
Q03UDECPU, Q04UDEHCPU, Q06UDEHCPU, Q10UDEHCPU, Q13UDEHCPU,
Q20UDEHCPU and Q26UDEHCPU

QnU(D)(H)CPU

QnUD(H)CPU

QnUDE(H)CPU

Generic temr for Q02UCPU, Q03UDCPU, Q04UDHCPU, Q06UDHCPU, Q10UDHCPU,
Q13UDHCPU, Q20UDHCPU and Q26UDHCPU
Generic name for Q03UDCPU, Q04UDHCPU, Q06UDHCPU, Q10UDHCPU,
Q13UDHCPU, Q20UDHCPU and Q26UDHCPU
Generic name for Q03UDECPU, Q04UDEHCPU, Q06UDEHCPU, Q10UDEHCPU,
Q13UDEHCPU,Q20UDEHCPU and Q26UDEHCPU

1-5

1.2 Abbreviations and Generic Names

QnCPU

(Continued)
Generic Name/Abbreviation

Description of Generic Name/Abbreviation

■ Base unit model

Q3

B

Generic term for Q33B, Q35B, Q38B and Q312B main base units on which CPU module
(except Q00JCPU), Q series power supply module, Q series I/O module, and intelligent
function module can be mounted.

Q3

SB

Generic term for Q32SB, Q33SB and Q35SB slim type main base units on which Basic
model QCPU (except Q00JCPU), High Performance model QCPU, slim type power supply
module, Q series I/O module, and intelligent function module can be mounted.

Q3

RB

Other name for Q38RB redundant power supply main base unit on which CPU module
(except Q00JCPU), redundant power supply module, Q series I/O module, and intelligent
function module can be mounted.

Q3

DB

Generic term for the Q38DB and Q312DB type Multiple CPU high speed main base unit on
which CPU module (except the Q00JCPU), Q series power supply module, Q series I/O
module, and intelligent function module can be mounted.

Q5

B

Generic term for Q52B and Q55B extension base unit on which the Q Series I/O and
intelligent function module can be mounted.

Q6

B

Generic term for Q63B, Q65B, Q68B and Q612B extension base unit on which Q Series
power supply module, I/O module, intelligent function module can be mounted.

Q6

RB

Other name for Q68RB redundant power supply extension base unit on whichredundant
power supply module, Q series I/O module, and intelligent function module can be mounted.

Q6

WRB

Other name for Q65WRB extension base unit for redundant system on which redundant
power supply module, Q series I/O module, and intelligent function module can be mounted.

QA1S6

QA6

Generic term for QA1S65B and QA1S68B extension base units on which AnS Series power
supply module, I/O module, special function module can be mounted.

B

Generic term for QA65B and QA68B extension base units on which the A series power
supply module, A series I/O modules and special function modules can be mounted.

B

A5

B

Generic term for A52B, A55B, and A58B extension base units on which A series I/O module
and special function module can be mounted without power supply.

A6

B

Generic term for A62B, A65B, and A68B extension base units on which A series I/O module
and special function module can be mounted.

QA6ADP
QA6ADP+A5

Abbreviation for QA6ADP QA conversion adapter module.
B/A6

B

Abbreviation for A large type extension base unit on which QA6ADP is mounted.

■ Network

1-6

MELSECNET/H

Abbreviation for MELSECNET/H network system

MELSECNET/10

Abbreviation for MELSECNET/10 network system

MELSECNET(II/,B)

Abbreviation for MELSECNET and MELSECNET/B data link system

Ethernet

Abbreviation for Ethernet network system

CC-Link

Abbreviation for Control & Communication Link

(Continued)
Generic Name/Abbreviation

1

Description of Generic Name/Abbreviation

■ Others
Product name of Q series Corresponding SW

D5C-GPPW-type GPP function software

2

package
GX Developer

: Version of the software

3

Check the GX Developer versions that can be used for each CPU module in "System
Configuration," QCPU User's Manual (Hardware Design, Maintenance and Inspection).
Intelligent function module
Intelligent function module
device

Generic name for intelligent function modules and special function modules

4

Generic name for intelligent function module devices and special function module devices

4
6
7
8

1.2 Abbreviations and Generic Names

1-7

MEMO

1-8

2

INSTRUCTION
TABLES

2

2-1

2.1 Types of Instructions
The major types of CPU module instructions consist of sequence instructions, basic instructions,
application instructions, data link instructions, QCPU instructions and redundant system
instructions. These types of instructions are listed in Table 2.1 below.
Table 2.1 Types of Instructions
Types of Instruction

Sequence
instruction

Basic
instruction

Application
instruction

2-2

Meaning

Contact instruction

Operation start, series connection, parallel connection

Association instruction

Ladder block connection, store/read operation results, creation of pulses from
operation results

Output instruction

Bit device output, pulse output, output reversal

Shift instruction

Bit device shift

Master control instruction

Master control

Termination instruction

Program termination

Other instruction

Program stop, instructions such as no operation which do not fit in the above
categories

Comparison operation
instruction

Comparisons such as

Arithmetic operation instruction

Addition, subtraction, multiplication or division of BIN or BCD

BCD
BIN conversion
instruction

Conversion from BCD to BIN and from BIN to BCD

Reference
Chapter

5

,

Data transfer instruction

Transmits designated data

Program branch instruction

Program jumps

,

Program run control instruction

Enables or inhibits interrupt programs

I/O refresh

Executes partial refresh

Other convenient instruction

Instructions for: Counter increment/decrement, teaching timer, special function timer,
rotary table shortest direction control, etc.

Logical operation instruction

Logical operations such as logical sum, logical product, etc.

Rotation instruction

Rotation of designated data

Shift instruction

Shift of designated data

Bit processing instruction

Bit set and reset, bit test, batch reset of bit devices

Data processing instruction

16-bit data searches, data processing such as decoding and encoding

Structure creation instruction

Repeated operation, subroutine program calls, indexing in ladder units

Table operation instruction

Data table read/write

Buffer memory access
instruction

Data read/write from/to an intelligent function module

Display instruction

Print ASCII code, LED character display, etc.

Debugging and failure
diagnosis instruction

Check, status latch, sampling trace, program trace

Character string processing
instruction

Conversion between BIN/BCD and ASCII;conversion between BIN and character
string; conversion between floating decimal point data and character strings,
character string processing, etc.

Special function instruction

Trigonometric functions, conversion between angles and radians, exponential
operations, automatic logarithms, square roots

Data control instruction

Upper and lower limit controls, dead band controls, zone controls

Switching instruction

File register block No. switches, designation of file registers and comment files

Clock instruction

Reading/writing of the values of year, month, day, hour, minute, second, and day of
the week; addition/subtraction of the values of hour, minute, and second; conversion
of the values of hour, minute, and second into second; comparison between the
values of year, month, and day; and comparison between the values of hour, minute,
and second

Expansion clock instruction

Reading of the values of year, month, day, hour, minute, second, millisecond, and
day of the week; addition/subtraction of the values of hour, minute, second, and
millisecond

Peripheral device instruction

I/O to peripheral devices

Program control instruction

Instructions to switch program execution conditions

Other instruction

Instructions that do not fit in the above categories, such as watchdog timer reset
instructions and timing clock instructions

6

7

Table 2.1 Types of Instructions (Continued)
Types of Instruction
Instruction
for Data Link

Link refresh instruction
Routing information read/write
instruction

Meaning

Reference
Chapter

Designated network refresh

8

2

Writing to host CPU shared memory, Reading from other CPU shared memory

9

3

Writes/reads devices to/from another CPU.

10

System switching

11

Reads, writes, and registers routing information

Multiple
CPU

Multiple CPU dedicated

dedicated

instruction

instruction
Multiple CPU
high-speed
transmission
dedicated

Multiple CPU device write/read
instruction

4

instruction

4

Redundant
system

Instruction for Redundant CPU

instruction

6
7
8

2.1 Types of Instructions

2-3

2.2 How to Read Instruction Tables
The instruction tables found from Section 2.3 to 2.5 have been made according to the following
format:

BIN
16-bit
addition
and
subtraction
operations

1)

Processing Details

+

+

S D

+P

+P

S D

(D)+(S)

+

+

S1 S2 D

+P

+P

S1 S2 D

(S1)+(S2)

2)

3)

Execution
Condition

(D)

(D)

4)

5)

See for Description

Symbol

Subset

Category

Number of Basic Steps

Instruction Symbols

Table 2.2 How to Read Instruction Tables

3

6-16

4

6-20

6) 7)

8)

Description
1) ..........Classifies instructions according to their application.
2) ..........Indicates the instruction symbol added to the instruction in a program.
Instruction code is built around the 16-bit instruction. The following notations are used to
mark 32-bit instructions, instructions executed only at the leading edge of OFF to ON,
real number instructions, and character string instructions:
• 32-bit instruction ..... The letter "D" is added to the first line of the instruction.
D+

Example +

16-bit instruction 32-bit instruction

• Instructions executed only at the leading edge of OFF to ON
............................... The letter "P" is added to the end of the instruction.
+P

Example +
Instruction executed
when ON

Instruction executed
only at the leading
edge of OFF to ON

• Real number instructions
............................... The letter "E" is added to the first line of the instruction.
Example +

E+
Real number instructions

• Character string instructions
............................... A dollar sign $ is added to the first line of the instruction.
Example +

$+
Character string instructions

2-4

3) ..........Shows symbol diagram on the ladder.
+

S D

S1 S2 D

+

Indicates destination.
Indicates source.

Indicates destination.

Indicates instruction symbol.

Indicates instruction symbol.

2

Indicates source.

Fig. 2.1 Symbol Diagram on the Ladder

3

Destination............ Indicates where data will be sent after operation.
Source .................. Stores data prior to operation.

4

4) ..........Indicates the type of processing that is performed by individual instructions.
(D)+(S)

(D)

(D+1, D) +(S+1, S)
16 bits

4

(D +1,D)

16 bits

Indicates 16 bits.

6

Indicates 32 bits.
D+1
D
Upper 16 bits Lower 16 bits

7

Fig. 2.2 Type of Processing Performed by Individual Instructions
5) ..........The details of conditions for the execution of individual instructions are as follows:
Symbol
No symbol
recorded

8

Execution Condition
Instruction executed under normal circumstances, with no regard to the ON/OFF status of conditions prior to
the instruction.
If the precondition is OFF, the instruction will conduct OFF processing.
Executed during ON; instruction is executed only while the precondition is ON. If the preconditions is OFF,

2.2 How to Read Instruction Tables

the instruction is not executed, and no processing is conducted.
Executed once at ON; instruction executed only at leading edge when precondition goes from OFF to ON.
Following execution, instruction will not be executed and no processing conducted even if condition remains
ON.
Executed during OFF; instruction is executed only while the precondition is OFF. If the precondition is ON,
the instruction is not executed, and no processing is conducted.
Executed once at OFF; instruction executed only at trailing edge when precondition goes from ON to OFF.
Following execution, instruction will not be executed and no processing conducted even if condition remains
OFF.

6) ..........Indicates the basic number of steps for individual instructions.
See Section 3.8 for a description of the number of steps.

7) ..........The

mark indicates instructions for which subset processing is possible.

See Section 3.5 for details on subset processing.
8) ..........Indicates the page numbers where the individual instructions are explained.

2-5

2.3 Sequence Instructions
2.3.1

Contact instructions

Execution
Condition

• Starts logic operation

LD

(Starts a contact logic operation)
• Starts logical NOT operation

LDI

(Starts b contact logic operation)
• Logical product (a contact series connection)

AND

• Logical product NOT (b contact series

ANI

*1

5-2

*2

5-5

connection)
• Logical sum (a contact parallel connection)

OR

• Logical sum NOT (b contact parallel

ORI

Contact

Processing Details

See for Description

Symbol

Subset

Category

Number of Basic Steps

Instruction Symbol

Table 2.3 Contact Instructions

connection)

LDP

• Starts leading edge pulse operation

LDF

• Starts trailing edge pulse operation

ANDP

• Leading edge pulse series connection

ANDF

• Trailing edge pulse series connection

ORP

• Leading edge pulse parallel connection

ORF

• Trailing edge pulse parallel connection

LDPI

• Starts leading edge pulse NOT operation

3

LDFI

• Starts trailing edge pulse NOT operation

3

ANDPI

• Leading edge pulse NOT series connection

4

ANDFI

• Trailing edge pulse NOT series connection

4

ORPI

• Leading edge pulse NOT parallel connection

4

ORFI

• Trailing edge pulse NOT parallel connection

4

5-7

*1: The number of steps may vary depending on the device being used.
Device

2-6

Number of Steps

Internal device, file register (R0 to R32767)

1

Direct access input (DX)

2

Devices other than above

3

*2: The number of steps may vary depending on the device and type of CPU module being used.
Number of Steps

Device

2.3.2

QCPU

Internal device, file register (R0 to R32767)

1

Direct access input (DX)

2

Devices other than above

3

2
3

Association instructions

4

ANB

ORB

MPS
MRD

7

1

-

5-12

1

-

5-15

MEP
MEF

• Conversion of operation result to trailing edge
pulse

1

-

5-17

-

5-18

Vn

• Conversion of operation result to leading edge
pulse
(Stored at Vn)

1

Vn

• Conversion of operation result to trailing edge
pulse
(Stored at Vn)

*1

*1: The number of steps may vary depending on the device and type of CPU module being used.
Component

Number of Basic Steps

High Performance model QCPU
Process CPU
Redundant CPU

1

Universal model QCPU
Basic model QCPU

2

2-7

2.3 Sequence Instructions
2.3.2 Association instructions

• Inversion of operation result
• Conversion of operation result to leading edge
pulse

EGF

5-10

6

• Read and reset of operation results stored with
MPS instruction

MPP

INV

EGP

-

4

8

• Read of operation results stored with MPS
instruction

MPS

Connection

1
• OR between logical blocks
(Series connection between logical blocks)
• Memory storage of operation results

MRD

MPP

Condition

• AND between logical blocks
(Series connection between logical blocks)

ANB

ORB

Execution

Processing Details

See for Description

Symbol

Subset

Category

Number of Basic Steps

Instruction Symbol

Table 2.4 Association Instructions

2.3.3

Output instructions

Processing Details

Execution
Condition

See for Description

Symbol

Subset

Category

Number of Basic Steps

Instruction Symbol

Table 2.5 Output Instructions

5-20
OUT

• Device output

*1

-

5-22
5-26
5-28

SET

SET

D

• Sets device

*2

RST

RST

D

• Resets device

*2

PLS

PLS

D

• Generates 1 cycle program pulse at leading
edge of input signal.

Output

5-30

*1

-

*1

-

2

-

5-37

5-35
5-32
5-35

PLF

PLF

D

• Generates 1 cycle program pulse at trailing
edge of input signal.

FF

FF

D

• Reversal of device output

2

-

5-40

DELTA

DELTA

D
• Pulse conversion of direct output

2

-

5-42

DELTAP

DELTAP

D

*1: The number of steps may vary depending on the device being used. See description pages of individual
instructions for number of steps.
*2: The

2.3.4

execution condition applies only when an annunciator (F) is in use.

Shift instructions

SFT

SFT

D

SFTP

SFTP

D

Shift

2-8

• 1-bit shift of device

Execution
Condition

See for Description

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.6 Shift Instructions

2

-

5-44

2.3.5

Master control instructions

control

Processing Details

MC

MCR

2.3.6

n D

MCR

n

Execution
Condition

• Starts master control

2

• Resets master control

1

See for Description

MC

Master

Symbol

Subset

Category

Number of Basic Steps

Instruction Symbol

Table 2.7 Master Control Instructions

-

5-47

Execution
Condition

5-53

• Termination of sequence program

END

Other instructions

PAGE

• Terminates sequence operation after
input condition has been met.
• Sequence program is executed by
placing the RUN/STOP key switch
back in the RUN position.

STOP

Execution
Condition

See for Description

NOPLF

Processing Details

Subset

STOP

NOP
Ignored

Symbol

Number of Basic Steps

Stop

Instruction Symbol

Table 2.9 Other Instructions

Category

1

-

5-55

1

-

5-57

• Ignored (For program deletion or
space)

––––––

• Ignored (To change pages during
printouts)

NOPLF
PAGE

n

8

• Ignored (Subsequent programs will be
controlled from step 0 of page n)

2-9

2.3 Sequence Instructions
2.3.5 Master control instructions

2.3.7

-

7

5-51

Termination
END

1

• Termination of main program

FEND

See for Description

Processing Details

Subset

FEND

4

6
Number of Basic Steps

Instruction Symbol

Symbol

3

4

Termination instructions
Table 2.8 Termination Instructions

Category

2

2.4 Basic instructions
2.4.1

Comparison operation instructions

LD=

S1 S2

AND=

S1 S2

OR=

• Conductive status when (S1)
• Non-conductive status when
(S1)

S1 S2

AND<>

S1 S2

(S1)

(S2)

3

(S2)

S1 S2

AND>

S1 S2

• Conductive status when (S1)
• Non-conductive status when

(S2)

3

(S2)

S1 S2

6-2

data
comparisons LD<=
AND<=
OR<=

S1 S2
S1 S2

• Conductive status when (S1)
• Non-conductive status when
(S1)

LD<

S1 S2

AND<

S1 S2

OR<

3

(S2)

• Conductive status when (S1)
• Non-conductive status when

(S2)

3

(S2)

S1 S2

LD>=

S1 S2

AND>=

S1 S2

OR>=

(S2)

S1 S2

(S1)

2-10

See for Description

3

S1 S2

LD>

OR>

(S2)

(S2)

• Conductive status when (S1)
• Non-conductive status when

(S1)
BIN 16-bit

Condition

S1 S2

LD<>

OR<>

Execution

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.10 Comparison Operation Instructions

• Conductive status when (S1)
• Non-conductive status when
(S1)

S1 S2

(S2)

(S2)

3

LDD=

D

S1 S2

ANDD=

D

S1 S2

D

S1 S2

LDD<>

D

S1 S2

ANDD<>

D

S1 S2

D

S1 S2

LDD>

D

S1 S2

ANDD>

D

S1 S2

(S1+1, S1)
(S2+1, S2)
• Non-Conductive status when

D

See for Description

*1

4
4
*1

(S2+1, S2)

6

• Conductive status when
(S1+1, S1)
(S2+1, S2)
• Non-Conductive status when

7

*1

(S2+1, S2)

S1 S2

6-4

data
comparisons LDD<=

S1 S2

D

S1 S2

D

S1 S2

LDD<

D

S1 S2

ANDD<

D

S1 S2

D

S1 S2

LDD>=

D

S1 S2

ANDD>=

D

S1 S2

D

S1 S2

ANDD<=

(S1+1, S1)
(S2+1, S2)
• Non-Conductive status when
(S1+1, S1)

ORD<=

(S2+1, S2)

(S1+1, S1)
(S2+1, S2)
• Non-Conductive status when

*1

(S2+1, S2)

• Conductive status when
(S1+1, S1)
(S2+1, S2)
• Non-Conductive status when
(S1+1, S1)

ORD>=

*1

• Conductive status when

(S1+1, S1)

ORD<

*1

(S2+1, S2)

*1: The number of steps may vary depending on the device and type of CPU module being used.
Component

High Performance model QCPU
Process CPU
Redundant CPU
Basic model QCPU
Universal model QCPU

8

• Conductive status when

2.4 Basic instructions
2.4.1 Comparison operation instructions

D

2
3

(S2+1, S2)

(S1+1, S1)
(S2+1, S2)
• Non-Conductive status when

(S1+1, S1)

ORD>

Condition

• Conductive status when

(S1+1, S1)

ORD<>

Execution

• Conductive status when

(S1+1, S1)

ORD=

BIN 32-bit

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.10 Comparison Operation Instructions (Continued)

Device
• Word device:
• Bit device:
• Constant:

Internal device (except for file register ZR)
Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no Indexing.
No limitations

Number of
Steps

5 Note 1)

Devices other than above

3 Note 2)

All devices that can be used

3 Note 2)

Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU,
the number of steps increases but the processing speed becomes faster.
Note 2) The number of steps may increase due to the conditions described in Section 3.8.

2-11

LDE=

E

S1 S2

ANDE=

E

S1 S2

E

S1 S2

LDE<>

E

S1 S2

ANDE<>

E

S1 S2

E

S1 S2

LDE>

E

S1 S2

ANDE>

E

S1 S2

decimal

E

S1 S2

LDE<=

E

S1 S2

ANDE<=

E

S1 S2

E

S1 S2

LDE<

E

S1 S2

ANDE<

E

S1 S2

E

S1 S2

LDE>=

E

S1 S2

ANDE>=

E

S1 S2

E

S1 S2

ORE>

point data
comparisons
(Single
precision)

3

-

3

-

3

-

See for Description

Condition

(S2+1, S2)

• Conductive status when
(S1+1, S1)
(S2+1, S2)
• Non-Conductive status when
(S2+1, S2)

• Conductive status when
(S1+1, S1)
(S2+1, S2)
• Non-Conductive status when
(S1+1, S1)

(S2+1, S2)

6-6
• Conductive status when

ORE<=

ORE<

ORE>=

2-12

(S1+1, S1)
(S2+1, S2)
• Non-Conductive status when

(S1+1, S1)

Floating

Execution

• Conductive status when

(S1+1, S1)

ORE=

ORE<>

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.10 Comparison Operation Instructions (Continued)

(S1+1, S1)
(S2+1, S2)
• Non-Conductive status when
(S1+1, S1)

3

-

3

-

3

-

(S2+1, S2)

• Conductive status when
(S1+1, S1)
(S2+1, S2)
• Non-Conductive status when
(S1+1, S1)

(S2+1, S2)

• Conductive status when
(S1+1, S1)
(S2+1, S2)
• Non-Conductive status when
(S1+1, S1)

(S2+1, S2)

LDED=
ANDED=

ED
ED

S1 S2

• Conductive status when

S1 S2

(S1+3, S1+2, S1+1, S1)
(S2+3, S2+2, S2+1, S2)
• Non-Conductive status when

ED

S1 S2

(S1+3, S1+2, S1+1, S1)
(S2+3, S2+2, S2+1, S2)

LDED<>

ED

S1 S2

• Conductive status when

ANDED<>

ED

S1 S2

(S1+3, S1+2, S1+1, S1)
(S2+3, S2+2, S2+1, S2)

ORED=

• Non-Conductive status when

ED

S1 S2

(S1+3, S1+2, S1+1, S1)
(S2+3, S2+2, S2+1, S2)

LDED>

ED

S1 S2

• Conductive status when

ANDED>

ED

S1 S2

(S1+3, S1+2, S1+1, S1)
(S2+3, S2+2, S2+1, S2)

ORED<>

• Non-Conductive status when

Floating
decimal

ORED>

point data
comparisons
(Double
precision)

ED

S1 S2

(S1+3, S1+2, S1+1, S1)
(S2+3, S2+2, S2+1, S2)

LDED<=

ED

S1 S2

• Conductive status when

ANDED<=

ED

S1 S2

(S1+3, S1+2, S1+1, S1)
(S2+3, S2+2, S2+1, S2)
• Non-Conductive status when

S1 S2

(S1+3, S1+2, S1+1, S1)
(S2+3, S2+2, S2+1, S2)

LDED<

ED

S1 S2

• Conductive status when

ANDED<

ED

S1 S2

(S1+3, S1+2, S1+1, S1)
(S2+3, S2+2, S2+1, S2)
• Non-Conductive status when

ED

S1 S2

(S1+3, S1+2, S1+1, S1)
(S2+3, S2+2, S2+1, S2)

LDED>=

ED

S1 S2

• Conductive status when

ANDED>=

ED

S1 S2

(S1+3, S1+2, S1+1, S1)
(S2+3, S2+2, S2+1, S2)

ORED<

• Non-Conductive status when
ORED>=

ED

S1 S2

Condition

2
3

3

-

4
4

3

-

6
3

7

-

6-8

3

-

3

-

3

-

8

2.4 Basic instructions
2.4.1 Comparison operation instructions

ED

ORED<=

Execution

See for Description

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.10 Comparison Operation Instructions (Continued)

(S1+3, S1+2, S1+1, S1)
(S2+3, S2+2, S2+1, S2)

2-13

LD$=

$

S1 S2

AND$=

$

S1 S2

$

S1 S2

LD$<>

$

S1 S2

AND$<>

$

S1 S2

$

S1 S2

LD$>

$

S1 S2

AND$>

$

S1 S2

OR$>
Character

$

S1 S2

$

S1 S2

$

S1 S2

string data
comparisons LD$<=
AND$<=

OR$<=

$

S1 S2

LD$<

$

S1 S2

AND$<

$

S1 S2

OR$<

• Compares character string S1 and
character string S2 one character at a
time. *2
• Conductive status when (character
string S1)
(character string S2)
• Non-Conductive status when

OR$=

OR$<>

$

S1 S2

LD$>=

$

S1 S2

AND$>=

$

S1 S2

(character string S1)
string S2)

Condition

3

-

3

-

3

-

(character

• Compares character string S1 and
character string S2 one character at a
time. *2
• Conductive status when (character
string S1)
(character string S2)
• Non-Conductive status when
(character string S1)
(character
string S2)
• Compares character string S1 and
character string S2 one character at a
time. *2
• Conductive status when (character
string S1)
(character string S2)
• Non-Conductive status when
(character string S1)
(character
string S2)
• Compares character string S1 and
character string S2 one character at a
time. *2
• Conductive status when (character
string S1)
(character string S2)
• Non-Conductive status when
(character string S1)
(character
string S2)
• Compares character string S1 and
character string S2 one character at a
time. *2
• Conductive status when (character
string S1)
(character string S2)

6-8

3

-

3

-

3

-

• Non-Conductive status when
(character string S1)
(character
string S2)
• Compares character string S1 and
character string S2 one character at a
time. *2
• Conductive status when (character
string S1)

OR$>=

Execution

See for Description

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.10 Comparison Operation Instructions (Continued)

(character string S2)

• Non-Conductive status when

$

S1 S2

(character string S1)
string S2)

(character

*2: The conditions under which character string comparisons can be made are as shown below:
• Match:
All characters in the strings must match
• Larger string: If character strings are different, determines the string with the largest number of
character codes. If the lengths of the character strings are different, determines the
longest character string.
• Smaller string: If the character strings are different, determines the string with the smallest number of
character codes.
If the lengths of the character strings are different, determines the shortest character
string.

2-14

BIN 16-bit
Block
data
comparisons

32-bit block
data
comparisons

BKCMP=

BKCMP

S1 S2 D n

BKCMP<>

BKCMP

S1 S2 D n

BKCMP>

BKCMP

S1 S2 D n

BKCMP<=

BKCMP

S1 S2 D n

BKCMP<

BKCMP

S1 S2 D n

BKCMP>=

BKCMP

S1 S2 D n

BKCMP=P

BKCMP P S1 S2 D n

BKCMP<>P

BKCMP

BKCMP>P

BKCMP P S1 S2 D n

BKCMP<=P

BKCMP

BKCMP
=P

BKCMP

P S1 S2 D n

DBKCMP=

DBKCMP

S1 S2 D n

DBKCMP<>

DBKCMP

S1 S2 D n

DBKCMP>

DBKCMP

S1 S2 D n

DBKCMP<=

DBKCMP

S1 S2 D n

DBKCMP<

DBKCMP

S1 S2 D n

DBKCMP>=

DBKCMP

S1 S2 D n

DBKCMP=P

DBKCMP P S1 S2 D n

DBKCMP<>P

DBKCMP

DBKCMP>P

DBKCMP P S1 S2 D n

DBKCMP<=P

DBKCMP

DBKCMP
=P

DBKCMP

P S1 S2 D n

Condition

See for Description

Execution

Subset

Processing Details

2
3
4

• This instruction compares BIN 16-bit
data stored in n-point devices starting
from the device specified by S1 with
BIN 16-bit data stored in n-point
devices starting from the device
specified by S2, and then stores the
result into the nth device specified by
(D) and up.

4
5

-

6-15

6
7

P S1 S2 D n

8

• This instruction compares BIN 32-bit
data stored in n-point devices starting
from the device specified by S1 with

P S1 S2 D

P S1 S2 D

P S1 S2 D

n

BIN 32-bit data stored in n-point
devices starting from the device

5

-

6-18

specified by a constant and S2, and
then stores the result into the nth
device specified by (D) and up.

n

n

2-15

2.4 Basic instructions
2.4.1 Comparison operation instructions

BIN

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.10 Comparison Operation Instructions (Continued)

2.4.2

Arithmetic operation instructions

Processing Details

+

+

S D

+P

+P

S D

• (D)+(S)

BIN 16-bit
addition and
subtraction
operations

+

+

S1 S2 D

+P

+P

S1 S2 D

(D)

• (S1)+(S2)

-

(D)

• (D)

P

-

(S)

(D)

BIN 16-bit
multiplication
and division
operations

BIN 32-bit
multiplication
and division
operations

2-16

4

6-24

3

6-22

(S2)

(D)

4

6-24

*1

6-26

*2

6-28

*1

6-26

*2

6-28

S1 S2 D

P

D+

D+

S D

D+P

D+P

S D

• (D+1, D)+(S+1, S)

operations

6-22

S D

• (S1)

subtraction

3

S1 S2 D

-P

addition and

Condition

S D

-P

BIN 32-bit

Execution

See for Description

Symbol

Subset

Category

Number of Basic Steps

Instruction Symbol

Table 2.11 Arithmetic Operation Instructions

D+

D+

S1 S2 D

D+P

D+P

S1 S2 D

D-

D

S D

D-P

D P

S D

(D+1, D)

• (S1+1, S1)+(S2+1, S2)

• (D+1, D)

D-

D

D-P

D

*

*

*P

(S+1, S)

(D+1, D)

(D+1, D)

S1 S2 D
P

• (S1+1, S1)

(S2+1, S2)

• (S1)

(D+1,D)

(D+1, D)

S1 S2 D
S1 S2 D
(S2)

*3

S1 S2 D

6-30
/

/

S1 S2 D

/P

/P

S1 S2 D

D*

S1 S2 D

D*P

S1 S2 D

• (S1) / (S2)
Quotient(D), Remainder (D+1)

• (S1+1,S1)

(S2+1,S2)

(D+3,D+2,D+1,D)

*4

*4

6-32
D/

D/

S1 S2 D

D/P

D/P

S1 S2 D

• (S1+1, S1) / (S2+1, S2)
Quotient (D+1, D), Remainder (D+3,
D+2)

*4

*1: The number of steps may vary depending on the device and type of CPU module being used.
Component

Number of

Device
• Word device:
• Bit device:

High Performance model QCPU
Process CPU

• Constant:

Redundant CPU
Basic model QCPU
Universal model QCPU

Steps

Internal device (except for file register ZR)
Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no indexing.
No limitations

5 Note 1)

Devices other than above

3

All devices that can be used

3 Note 2)

Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU,
the number of steps increases but the processing speed becomes faster.
Note 2) The number of steps may increase due to the conditions described in Section 3.8.

*2: The number of steps may vary depending on the device and type of CPU module being used.
Component

Number of

Device
• Word device:
• Bit device:

High Performance model QCPU
Process CPU

• Constant:

Redundant CPU

Internal device (except for file register ZR)
Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no indexing.
No limitations

6 Note 1)
4 Note 2)
4 Note 2)

All devices that can be used

Universal model QCPU

3 Note 2)

Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU,
the number of steps increases but the processing speed becomes faster.
Note 2) The number of steps may increase due to the conditions described in Section 3.8.

Device
• Word device:
• Bit device:

QCPU

• Constant:

Internal device (except for file register ZR)
Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no indexing.
No limitations

Devices other than above

4
4

Number of Steps

3

4 Note 1)

Note 1) The number of steps may increase due to the conditions described in Section 3.8.
*4: The number of basic steps is three for the Universal model QCPU only.

2-17

6
7
8

2.4 Basic instructions
2.4.2 Arithmetic operation instructions

*3: The number of steps may vary depending on the device and type of CPU module being used.
Component

3

Steps

Devices other than above
Basic model QCPU

2

Note 2)

Processing Details

B+

B+

S D

B+P

B+P

S D

• (D)+(S)

BCD 4-digit
addition

B+

B+

S1 S2 D

B+P

B+P

S1 S2 D

B-

B

S D

B-P

B P

S D

Condition

3

(D)

• (S1)+(S2)

Execution

4

(D)

See for Description

Symbol

Subset

Category

Number of Basic Steps

Instruction Symbol

Table 2.11 Arithmetic Operation Instructions (Continued)

6-34

-

6-36

and
subtraction
operations

• (D)

B-

B

S1 S2 D

B-P

B P

S1 S2 D

• (S1)

DB+

DB+

S D

DB+P

DB+P

S D

(S)

(S2)

(D)

• (D+1, D)+(S+1, S)

BCD 8-digit
addition

DB+

DB+

S1 S2 D

DB+P

DB+P

S1 S2 D

DB-

DB

S D

DB-P

DB

3

(D)

(D+1, D)

• (S1+1, S1)+(S2+1, S2)

(D+1, D)

6-34

4

-

6-36

3

-

6-38

4

-

6-40

3

-

6-38

4

-

6-40

and
subtraction
operations

BCD 4-digit

• (D+1, D)

BCD 8-digit
multiplication

(S+1, S)

(D+1, D)

S D

DB-

DB

S1 S2 D

DB-P

DB P

S1 S2 D

B*

B

S1 S2 D

B P

S1 S2 D

B/

S1 S2 D

B/P

B/P

S1 S2 D

DB*

DB

S1 S2 D

multiplication B*P
and
B/
division
operations

P

• (S1+1, S1)

(S2+1, S2)

• (S1)

(D+1,D)

(S2)

(D+1, D)

4
6-42

• (S1) / (S2)
Quotient(D), Remainder (D+1)

• (S1+1,S1)

(S2+1,S2)

(D+3,D+2,D+1,D)

DB*P

DB P

S1 S2 D

DB/

DB/

S1 S2 D

• (S1+1, S1) / (S2+1, S2)

DB/P

DB/P

S1 S2 D

Quotient (D+1, D),
Remainder (D+3, D+2)

4

4

6-44

and
division
operations

2-18

-

4

E+

E+

Processing Details

decimal
point data
addition

E+P
E+

E+P

3

S D

E+

S1 S2 D

E+P

S1 S2 D

E

S D

(D+1, D)

*6

4
*5

*6

6-46

6-48

and
subtraction
operations
(Single
precision)

E-

• (D+1, D)
E-P
E-

E

P

E

Floating
decimal
point data
addition

ED+

(S2+1, S2)

(D+1, D)

S1 S2 D

ED+

ED+P

(D+1, D)

S1 S2 D

E P

ED+

(S+1, S)

S D

ED+P
ED+

S D
S1 S2 D

• (D+3, D+2, D+1, D)+(S+3, S+2, S+1, S)
(D+3, D+2, D+1, D)

6-46

ED+P

S1 S2 D

(D+3, D+2, D+1, D)

ED-

ED

S D

• (D+3, D+2, D+1, D)

ED-P

ED

4
4

*6

4
*5

*6

6-48

3

6-50

4

6-52

3

6-50

4

6-52

• (S1+3, S1+2, S1+1, S1)+
(S2+3, S2+2, S2+1, S2)

ED+P

3

S D

• (S1+1, S1)
E-P

2
3

(D+1, D)

• (S1+1, S1)+(S2+1, S2)
E+P

Condition

S D
• (D+1, D)+(S+1, S)

Floating

Execution

See for Description

Symbol

Subset

Category

Number of Basic Steps

Instruction Symbol

Table 2.11 Arithmetic Operation Instructions (Continued)

6
7
8

and
subtraction
(Double
precision)

Floating
decimal
point data

P

S D

ED-

ED

S1 S2 D

ED-P

ED P

S1 S2 D

(S+3, S+2, S+1, S)

(D+3, D+2, D+1, D)
• (S1+3, S1+2, S1+1, S1)
(S2+3, S2+2, S2+1, S2)

E*

S1 S2 D

E*P

S1 S2 D

(D+3, D+2, D+1, D)

• (S1+1,S1)

(S2+1,S2)

(D+1,D)

3

*6

multiplication
and division

E/

E/

S1 S2 D

E/P

E/P

S1 S2 D

ED*

ED

S1 S2 D

ED*P

ED P

S1 S2 D

ED/

ED/

S1 S2 D

ED/P

ED/P

S1 S2 D

operations
(Single

6-54
• (S1+1, S1) / (S2+1, S2)
Quotient (D+1, D)

4

*6

precision)
Floating
decimal
point data

(S2+3,S2+2,S2+1,S2)

multiplication
and division
operations
(Double
precision)

• (S1+3,S1+2,S1+1,S1)

4

(D+3,D+2,D+1,D)

*6

6-56

• (S1+3, S1+2, S1+1, S1) /
(S2+3, S2+2, S2+1, S2)
Quotient (D+3, D+2, D+1, D)

4

*6

*5: The number of basic steps is three for the Universal model QCPU only.
*6: The subset is effective only with Universal model QCPU.

2-19

2.4 Basic instructions
2.4.2 Arithmetic operation instructions

operations

subtraction
operations

BK+

BK+

S1 S2 D n

BK+P

BK+P

S1 S2 D n

-

BK-

BK

S1 S2 D n

• This instruction substracts BIN 16-bit data
stored in the n-point devices starting from
the devices specified by (S2) from BIN 16bit data stored in n-point devices starting
from the device specified by (S1) in batch.

BK-P

BK

P

S1 S2 D n

5

-

5

-

Execution
Condition

See for Description

5

Processing Details

addition
and

• This instruction adds BIN 16-bit data
stored in n-point devices starting from the
device specified by (S1) to the n-point data
stored in the devices starting from the
device specified by (S2) in batch.

Symbol

BIN 16-bit
data block

Subset

Category

Number of Basic Steps

Instruction Symbol

Table 2.11 Arithmetic Operation Instructions (Continued)

6-59

• Adds BIN 32-bit data stored in the nDBK+

DBK+

S1 S2 D n

point devices starting from the device
specified by (S1) and a constant to BIN
32-bit data stored in the n-point devices

BIN 32-bit
data block

DBK+P

DBK+P

S1 S2 D n

(S2) and stores the result into the nth
device specified by (D) and up.

addition
and
subtraction

starting from the device specified by

6-62

• Subtracts BIN 32-bit data stored in the
DBK-

DBK

S1 S2 D n

operations

n-point devices starting from the device
specified by (S2) or a constant from BIN
32-bit data stored in n-point devices

DBK-P

DBK

P

S1 S2 D n

5

-

• Links character string designated with (S)
to character string designated with (D),
and stores the result from (D) onward.

3

-

6-65

• Links character string designated with (S2)
to character string designated with (S1),
and stores the result from (D) onward.

4

-

6-67

• (D)+1

2

6-69

*7

6-71

2

6-69

*7

6-71

starting from the device specified by
(S1) and stores the operation result into
the nth device specified by (D) and up.

Character

$+

$+

S D

$+P

$+P

S D

string data
Connection $+
$+P

$+

S1 S2 D

$+P

S1 S2 D

INC

INC

D

INCP

INCP

D

DINC

DINC

D

DINCP

DINCP

D

DEC

DEC

D

DECP

DECP

D

DDEC

DDEC

D

DDECP

DDECP

D

(D)

• (D+1, D)+1
BIN data
increment

• (D)

1

• (D+1, D)

2-20

(D+1, D)

(D)

1

(D+1, D)

*7: The number of steps may vary depending on the device and type of CPU module being used.
Component

High Performance model QCPU
Process CPU
Redundant CPU
Basic model QCPU
Universal model QCPU

Device
• Word device:
• Bit device:
• Constant:

Internal device (except for file register ZR)
Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no indexing.
No limitations

Number of
Steps
3 Note 1)

2

Note 2)

Devices other than above

2

All devices that can be used

2 Note 2)

Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU,
the number of steps increases but the processing speed becomes faster.
Note 2) The number of steps may increase due to the conditions described in Section 3.8.

3
4
4
6
7
8

2.4 Basic instructions
2.4.2 Arithmetic operation instructions

2-21

2.4.3

Data conversion instructions

BCD

BCD

Processing Details

S D

(S)
BCD
conversions

BCDP

BCDP

S D

DBCD

DBCD

S D

conversions

BIN

DBCDP

DBCDP

S D

BIN

BIN

S D

BINP

BINP

S D

DBIN

DBIN

S D

point
conversions
(Single
precision)
BIN

point
conversions
(Double
precision)
Floating

DBINP

DBINP

S D

FLT

FLT

S D

FLTP

FLTP

S D

DFLT

DFLT

S D

conversions
(Single
precision)
Floating

DFLTP

DFLTP

S D

FLTD

FLTD

S D

FLTDP

FLTDP

S D

DFLTD

DFLTD

S D

DFLTDP

DFLTDP

S D

INT

INT

S D

conversions

INTP

INTP

S D

DINT

DINT

S D

DINTP

DINTP

S D

INTD

INTD

S D

INTDP

INTDP

S D

DINTD

DINTD

S D

Conversion to real number
(S+1, S)
(D+1, D)
BIN( 2147483648 to
2147483647)
Conversion to real number
( D+3, D+2, D+1, D)
BIN( 32768 to 32767)

3
*1

3
*1

*2

DINTDP

DINTDP

S D

3
*1

*2

4
*2

6-81

Conversion to real number
(S+1, S)
(D+3, D+2, D+1, D)
BIN( 2147483648 to
2147483647)
Conversion to BIN
(D)
Real number
 
(-32768 to 32767)

Conversion to BIN
(S+1, S)
(D+1, D)
Real number (-2147483648 to
2147483647)
Conversion to BIN
(S+3, S+2, S+1, S)
(D)
Real number ( 32768 to
32767)
Conversion to BIN
(S+3, S+2, S+1, S)
(D+1, D)
Real number ( 2147483648 to
2147483647)

*1: The number of basic steps is two for the Universal model QCPU only.
*2: The subset is effective only with Universal model QCPU.

2-22

3
*1

4
*2

3
*1

*2

6-83
3
*1

3

*2

*2

6-86

(Double
precision)

Conversion to real number
(D+1, D)
BIN( 32768 to 32767)

(S+1, S)

point

BIN

3
*1

6-78

point

BIN

3
*1

6-75

(S)
Floating

BIN conversions
(D)
BCD (0 to 9999)

BIN conversions
(S+1, S)
(D+1, D)
BCD (0 to 99999999)

(S)
Floating

Condition

6-73
BCD conversions
(S+1, S)
(D+1, D)
BIN (0 to 99999999)

(S)
BIN

BCD conversions
(D)
BIN (0 to 9999)

Execution

See for Description

Symbol

Subset

Category

Number of Basic Steps

Instruction Symbol

Table 2.12 Data Conversion Instructions

3

*2

DBL

S D

(S)

16-bit

DBLP

DBLP

S D

32-bit

WORD

WORD

S D

conversion

BIN

Gray code

BIN

(D+1, D)
BIN (-32768 to 32767)
Conversion

(S+1, S)
WORDP

WORDP

S D

GRY

GRY

S D

GRYP

GRYP

S D

DGRY

DGRY

S D

conversions

Gray code

Conversion

DGRYP

DGRYP

S D

GBIN

GBIN

S D

GBINP

S D

DGBIN

DGBIN

S D

DGBINP

DGBINP

S D

NEG

D

conversions

NEG
NEGP

NEGP

D

DNEG

DNEG

D

Conversion to gray code
(S)
(D)
BIN (-32768 to 32767)

Condition

3

-

6-88

3

-

6-89

3

-

3

-

Conversion to BIN data
(S)
(D)
Gray code (-32768 to 32767)

3

-

Conversion to BIN data
(S+1, S)
(D+1, D)
Gray code (-2147483648 to
2147483647)
(D)

(D)
BIN data

Complement
to 2

Block
conversion

DNEGP

DNEGP

D

ENEG

ENEG

D

ENEGP

ENEGP

D

EDNEG

EDNEG

D

EDNEGP

EDNEGP D

BKBCD

BKBCD

S D n

BKBCDP

BKBCDP

S D n

BKBIN

BKBIN

S D n

BKBINP

BKBINP

S D n

Floating-point ECON
Single precision
ECONP
Double precision
Floating-point EDCON
Double precision
EDCONP
Single precision

ECON

S D

ECONP

S D

EDCON

S D

EDCONP S D

(D+1, D)

6-92
3

-

2

-

2

-

(D+1, D)
Real number data

2

-

6-96

(D+3, D+2, D+1, D)
(D+3, D+2, D+1, D)
Real number data

3

-

6-97

• Batch converts BIN data n points from (S)
to BCD data and stores the result from (D)
onward.

4

-

6-98

• Batch converts BCD data n points from (S)
to BIN data and stores the result from (D)
onward.

4

-

6-100

Conversion to double precision
(S+1, S)
(D+3, D+2, D+1, D)
32-bit floating-point real number

3

-

6-102

Conversion to single precision
(S+3, S+2, S+1, S)
(D+1, D)
64-bit floating-point real number

3

-

6-104

BIN data

(D+1, D)

4

6
7

6-94

(D+1, D)

3

4
6-90

Conversion to gray code
(S+1, S)
(D+1, D)
BIN (-2147483648 to
2147483647)

2

2-23

8

2.4 Basic instructions
2.4.3 Data conversion instructions

GBINP

(D)
BIN (-32768 to 32767)

Execution

See for Description

DBL

Processing Details

Subset

BIN

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.12 Data Conversion Instructions (Continued)

2.4.4

Data transfer instructions

16-bit data
transfer

MOV

MOV

Condition

*4

S D
( D)

(S)
MOVP

MOVP

S D

DMOV

DMOV

S D

DMOVP

DMOVP

S D

EMOV

EMOV

S D

See for Description

Execution

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.13 Data Transfer Instructions

*1

6-106
32-bit data
transfer
Floating
decimal
point data
transfer
(Single

(S+1, S)
EMOVP

EMOVP

S D

EDMOV

EDMOV

S D

*2

(D+1,D)

(S+1,S)

(D+1, D)

*2
*3

Real number data

6-108

precision)
Floating
decimal
point data

(S+3, S+2, S+1, S)

transfer
EDMOVP

EDMOVP S D

$MOV

$MOV

S D

transfer

$MOVP

$MOVP

S D

16-bit data

CML

CML

S D

transfer

CMLP

CMLP

S D

32-bit data

DCML

DCML

S D

DCMLP

DCMLP

S D

(Double

(D+3, D+2, D+1, D)

2

Real number data

*3

6-110

precision)
Character
string data

negation

• Transfers character string designated by
(S) to device designated by (D) onward.

3

(S)

*1

(D)

-

6-112

6-114
negation
transfer
Block
transfer
Identical 16-

(S+1,S)

BMOV

BMOV

S D n

BMOVP

BMOVP

S D n

FMOV

FMOV

S D n

(S)

(D)
n

(D)

bit data block

(S)

transfers

FMOVP

FMOVP

S D n

Identical 32-

DFMOV

DFMOV

S D n

DFMOVP

DFMOVP S D n

*2

(D+1,D)

n

4

6-117

4
6-120

(S+1,S)

bit data block
transfers
16-bit data
exchange

(D+1,D)

XCH

XCH

D1 D2

XCHP

XCHP

D1 D2

DXCH

DXCH

D1 D2

DXCHP

DXCHP

D1 D2

(D1)

n

4

3

(D2)

6-122
32-bit data
exchange

2-24

(D1+1,D1)

(D2+1,D2)

3

Exchange

BXCH

BXCHP

S D n

BXCHP

SWAP

4

-

6-126

n

(S)

D

b15 to b8 b7 to b0
8 bits
(D) 8 bits

3

and lower
bytes

4

b15 to b8 b7 to b0
8 bits
8 bits

D

SWAPP

SWAPP

-

6-128

4

*1: The number of steps may vary depending on the device and type of CPU module being used.
Component

Device
• Word device:
• Bit device:

QCPU

• Constant:

2
3

(D)

S D n

SWAP

of upper

(S)

Condition

See for Description

exchange

BXCH

Execution

Processing Details

Subset

Block data

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.13 Data Transfer Instructions (Continued)

Internal device (except for file register ZR)
Devices whose device Nos. are multiples of 16, whose digit
designation is K4, and which use no indexing.
No limitations

Number of
Steps

7

2

3 Note 1)

Devices other than above

6

Note 1) The number of steps may increase due to the conditions described in Section 3.8.

8

*2: The number of steps may vary depending on the device and type of CPU module being used.
Device

Number of
Steps

• Word device: Internal device (except for file register ZR)
High Performance model QCPU

• Bit device:

Process CPU
Redundant CPU

Devices whose device Nos. are multiples of 16, whose
digit designation is K8, and which use no indexing.

• Constant:

3

No limitations

Devices other than above

3 Note 1)

• Word device: Internal device (except for file register ZR)
• Bit device:

Basic model QCPU

Universal model QCPU

Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no indexing.
• Constant:
No limitations
(The number of steps is 3 when the above device + constant are used.)

2

Devices other than above

3 Note 1)

All devices that can be used

2 Note 1)

Note 1) The number of steps may increase due to the conditions described in Section 3.8.

2-25

2.4 Basic instructions
2.4.4 Data transfer instructions

Component

*3: The subset is effective only with QCPU.
*4: The number of steps may vary depending on the device and type of CPU module being used.
Component

Device
• Word device:
• Bit device:

QCPU

• Constant:

Internal device (except for file register ZR)
Devices whose device Nos. are multiples of 16, whose digit
designation is K4, and which use no indexing.
No limitations

Devices other than above

Number of
Steps

2

3 Note 1)

Note 1) The number of steps may increase due to the conditions described in Section 3.8.

2-26

2.4.5

Program branch instructions

Processing Details

CJ

CJ

Pn

SCJ

SCJ

Pn

JMP

JMP

Pn

Jump

GOEND

2.4.6

Execution
Condition

• Jumps to Pn when input conditions are

2

met.
• Jumps to Pn from the scan after the

6-129

2

meeting of input condition.
• Jumps unconditionally to Pn.

2

• Jumps to END instruction when input

GOEND

See for Description

Symbol

Subset

Category

Number of Basic Steps

Instruction Symbol

Table 2.14 Program Branch Instructions

1

condition is met.

-

6

interrupts

EI

EI

• Prohibits the running of an interrupt
program.
• Resets interrupt program execution
prohibition.

1

-

1

6-133

IMASK

S

• Inhibits or permits interrupts for each
interrupt program.

2

-

1

-

See for Description

IMASK

Subset

enable

Number of Basic Steps

Interrupt
disable/

See for Description

Instruction Symbol

DI

Subset

Enable

DI

Condition

Number of Basic Steps

interrupts

Execution

7

3

-

6-141

setting
Return

IRET

2.4.7

• Returns to sequence program from an

IRET

interrupt program.

6-139

I/O refresh instructions

Category

I/O
Refresh

Instruction Symbol

Table 2.16 I/O Refresh Instructions

Symbol

Processing Details

RFS

RFS

S n

RFSP

RFSP

S n

• Refreshes the relevant I/O area during
scan.

Execution
Condition

2-27

8

2.4 Basic instructions
2.4.5 Program branch instructions

Disable

Processing Details

4

6-132

Program execution control instructions

Symbol

3

4

Table 2.15 Program Execution Control Instructions

Category

2

2.4.8

Other convenient instructions

Condition

See for Description

Execution

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.17 Other convenient instructions

4

-

6-143

4

-

6-146

3

-

6-149

3

-

6-151

5

-

6-154

6

-

6-157

4

-

6-160

4

-

6-162

4

-

6-164

5

-

6-166

(S)+0

UDCNT1

UDCNT1

S D n

UDCNT2

UDCNT2

S D n

Down
Up
Up
(S)+1
Present Cn value 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 -1 -2 -3 -2 -1 0
Cn contact

Up/Down
counter

(S)+0
(S)+1
Present Cn value 0 1

2

3

4

5

4

3

2

1

0

-1

Cn contact

Teaching
timer

(D)

(Time that TTMR is ON) n
TTMR

TTMR

D n

n=0:1, n=1:10n, n=2:100
• The 4 points from the bit device
designated by (D) operate as shown
below, depending on the ON/OFF
status of the input conditions for the

Special
timer

STMR instruction:
STMR

STMR

S n D

(D)+0: Off delay timer output
(D)+1: One shot after off timer output
(D)+2: One shot after on timer output
(D)+3: On delay and off delay timer
output
• Rotates a rotary table with n1 divisions

Shortest
direction

ROTC

ROTC

S n1 n2 D

control
Ramp
signal

from the stop position to the position
designated by (S+1) in the shortest
direction.

RAMP

RAMP

n1 n2 D1 n3 D2

• Changes device data designated by D1
from n1 to n2 in n3 scans.
• Counts the pulse input from the device

Pulse
density

SPD

SPD

S n

D

designated by (S) for the duration of
time designated by n, and stores the
count in the device designated by (D).

Pulse
output

PLSY

PLSY

n1 n2 D

(n1)Hz
(D)
Output n2 times
n1

Pulse
width

PWM

PWM

n2

n1 n2 D

modulation

(D)
• Reads data of 16 points
Matrix
input

MTR

MTR

S D1 D2 n

specified by (S), and stores them to the
devices starting from the one specified
by (D2).

2-28

n rows from

the devices starting from the one

2.5 Application Instructions
2.5.1

1
Logical operation instructions

2

WAND

S D

WANDP

WANDP

S D

(D)

WAND

WAND

Logical
product

WANDP

(S2)

DAND

DAND

S D

DANDP

DANDP

S D

(S+1,S)

(D+1,D)

DAND

DAND

S1 S2 D

DANDP

DANDP

S1 S2 D

BKAND

BKAND

BKANDP

BKANDP S1 S2 D n

(S1)

S1 S2 D n

WOR

S D

WORP

WORP

S D

WOR

WOR

Logical
sum

WORP

(S2)

DOR

S D

DORP

DORP

S D

(D+1,D)

DOR

DOR

S1 S2 D

DORP

DORP

S1 S2 D

(S+1,S)

BKOR

BKOR

S1 S2 D n

BKORP

BKORP

S1 S2 D n

WXOR

WXOR

S D

WXORP

WXORP

S D

(S1)

Exclusive
OR

WXOR

WXOR
WXORP

(S2)

(D+1,D)

(S2)

DXOR

S D

DXORP

DXORP

S D

(D+1,D)

(S+1,S)

5

-

7-9

7-11

7-14

*2

7-11

*3

7-14

5

4

(D)

*1

S1 S2 D

DXOR

8

3

(D)

(S)

7-6

(D)

S1 S2 D
(S1)

WXORP

(D+1,D)

n

(D)

*3

*1

(S2+1,S2)

(S1+1,S1)

7

4

(D)

S1 S2 D

DOR

7-3

3

(D)

(S)

*2

(D)

S1 S2 D
(S1)

WORP

(S2)

(D+1,D)

n

(D)

6

(D+1,D)

*2

-

7-17

7-19

7-22

7-19

2-29

2.5 Application Instructions
2.5.1 Logical operation instructions

WOR

(D+1,D)

(S2+1,S2)

(S1+1,S1)

7-6

*1

S1 S2 D

4
2

4

(D)

4

7-3

3

(D)

(S)

S1 S2 D
(S1)

WANDP

Condition

See for Description

WAND

Processing Details

Subset

Symbol

Execution

Number of Basic Steps

Category

Instruction Symbol

Table 2.18 Logical Operation Instructions

DXOR

DXOR

S1 S2 D

DXORP

DXORP

S1 S2 D

(S2+1,S2)

(S1+1,S1)
Exclusive
OR

BKXOR

BKXOR

BKXORP

BKXORP S1 S2 D n

(S1)

S1 S2 D n

WXNR

WXNR

S D

WXNRP

WXNRP

S D

WXNR

NON
exclusive
logical
sum

WXNRP

(S2)

DXNR

S D

DXNRP

DXNRP

S D

(D+1,D)

DXNR

DXNR

S1 S2 D

DXNRP

DXNRP

S1 S2 D

BKXNR

BKXNR

S1 S2 D n

BKXNRP

BKXNRP

S1 S2 D n

(S1)

(D+1,D)

(D+1,D)

See for Description
7-25

7-27

7-30

*1

(S2+1,S2)

(S2)

-

4

(D)

(S+1,S)

5

3

S1 S2 D

DXNR

7-22

*3

(D)

(D)

(S)

(S1+1,S1)

2-30

(D+1,D)

S1 S2 D
(S1)

WXNRP

(S2)

Condition

n

(D)

WXNR

Execution

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.18 Logical Operation Instructions (Continued)

*2

7-27

*3

7-30

(D)
n

5

-

7-33

*1: The number of basic steps is three for the Universal model QCPU only.
*2: The number of steps may vary depending on the device and type of CPU module being used.
Component

Device

Number of

1

Steps

• Word device: Internal device (except for file register ZR)
High Performance model QCPU

• Bit device:

Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no indexing.

Process CPU

• Constant:

Redundant CPU

Basic model QCPU
Universal model QCPU

5 Note 1)

No limitations

Devices other than above

3 Note 2)

All devices that can be used

3 Note 2)

Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU,
the number of steps increases but the processing speed becomes faster.
Note 2) The number of steps may increase due to the conditions described in Section 3.8.

Component

Device

• Bit device:

Redundant CPU

Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no indexing.

• Constant:

Steps

Basic model QCPU
Universal model QCPU

All devices that can be used

6

6 Note 1)

7

No limitations

Devices other than above

4

Number of

• Word device: Internal device (except for file register ZR)
Process CPU

4

2

*3: The number of steps may vary depending on the device and type of CPU module being used.

High Performance model QCPU

2

4

Note 2)

4 Note 2)
3 Note 2)

8

Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU,
the number of steps increases but the processing speed becomes faster.
Note 2) The number of steps may increase due to the conditions described in Section 3.8.
2.5 Application Instructions
2.5.1 Logical operation instructions

2-31

2.5.2

Rotation instructions

Condition

ROR

ROR

D n

RORP

RORP

D n

Right rotation by n bits Carry flag

D n

b15

b15

(D)

See for Description

Execution

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.19 Rotation Instructions

SM700

b0

3
Right
rotation

7-35
RCR

RCR

(D)

SM700

b0

3
RCRP

RCRP

D n

ROL

ROL

D n

Right rotation by n bits Carry flag
SM700 b15

(D)

b0
3

Left
rotation

ROLP

ROLP

D n

Carry flag

Left rotation by n bits
7-38

RCL

RCL

D n

RCLP

RCLP

D n

DROR

DROR

D n

SM700 b15

(D)

b0
3

Carry flag

Left rotation by n bits

(D+1)
(D)
b31 to b16 b15 to b0

SM700
3

Right
rotation

DRORP

DRORP

D n

DRCR

DRCR

D n

DRCRP

DRCRP

D n

DROL

DROL

D n

Right rotation by n bits Carry flag
(D+1)
(D)
b31 to b16 b15 to b0

7-41

SM700
3

Right rotation by n bits Carry flag
SM700

(D+1)
(D)
b31 to b16 b15 to b0
3

DROLP

DROLP

D n

DRCL

DRCL

D n

DRCLP

DRCLP

D n

Left
rotation

Carry flag
SM700

Left rotation by n bits

7-44

(D+1)
(D)
b31 to b16 b15 to b0
3

2-32

Carry flag

Left rotation by n bits

2.5.3

Shift instructions

1

n-bit shift

SFR

SFR

D n

b15

SFRP

SFRP

D n

b15
0 to 0

SFL

SFL

D n

of 16-bit
data

1-bit shift

SFLP

SFLP

D n

BSFR

BSFR

D n

BSFRP

BSFRP

D n

of n-bit
data

BSFL

BSFLP

SFTBR

BSFL

SFTBR

bn

D n

See for Description

Condition

b0
Carry flag
b0 SM700

b15

bn

2

b0
3

Carry flag
SM700 b15

b0
0 to 0

6

n
(D)
Carry flag
SM700

3

-

7

0

7-49

n
(D)
Carry flag
SM700

3

-

4

-

8

0
n1

D n1 n2

SFTRP

D n1 n2

SM700

0 0

of n-bit
data

Carry flag

SFTBL

SFTBL

7-51
n1

D n1 n2
n2

(D)

Carry flag

SFTBLP

SFTBLP

D n1 n2

4

-

SM700
0 0

DSFR

1-word

DSFRP

DSFR

DSFRP

D n

DSFL

D n

shift of
n-words
data

DSFL

DSFLP

SFTWR

DSFLP

n

D n

(D)

0

7-54

n
(D)

D n

SFTWRP

shift of
n-words
data

3

0
n1

SFTWR

D n1 n2

n2

(D)

n-words

3

4

-

SFTWRP D n1 n2
0 0

SFTWL

SFTWLP

7-56

n1

SFTWL

D n1 n2

SFTWLP D n1 n2

n2

(D)

4

-

0 0

2-33

2.5 Application Instructions
2.5.3 Shift instructions

(D)

n-bit shift

4
4

3

n2

SFTBRP

2

7-46

D n

BSFLP

Execution

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.20 Shift Instructions

2.5.4

Bit processing instructions

BSET

Bit
set/reset

BSET

D n

BSETP

BSETP

D n

BRST

BRST

D n

BRSTP

D n

BRSTP
TEST

TEST

S1 S2 D

TESTP

TESTP

S1 S2 D

DTEST

DTEST

S1 S2 D

(D)
b15

bn

Condition

b0

3

1
(D)
b15

bn

7-59

b0

3

0
(S1)
b15

to

b0

(D)
4

-

Bit designated by (S2)
7-61

Bit tests

DTESTP

Batch

BKRST

(S1)
b31

DTESTP S1 S2 D

BKRST

D n

to

2-34

BKRSTP

BKRSTP

D n

b0

(D)
4

-

3

-

Bit designated by (S2)
(D)

ON
OFF

reset of bit
devices

See for Description

Execution

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.21 Bit Processing Instructions

ON
ON

(D)
Reset

OFF
OFF
n
OFF
OFF

7-64

2.5.5

Data processing instructions

1

SERP

SER

S1 S2 D n

SERP

Condition

5

-

(S2)

(S1)

(D): Match No.
(D + 1): Number of matches

S1 S2 D n

7-66
DSER

DSERP

DSER

S1 S2 D n

DSERP

SUM

S D

SUMP

SUMP

S D

DSUM

DSUM

S D

DSUMP

DSUMP

S D

DECO

DECO

S D n

Decode

S D n

ENCO

ENCO

S D n

ENCOP

ENCOP

S D n

SEG

S D

SEG

ment
decode

5

SEGP

S D

-

6

(D): Match No.
(D + 1): Number of matches

(S)
b0

b15

7

3

(D): Number of 1s
(S + 1) (S)

7-69

8

3

(D): Number of 1s
Decode from 8 to 256
(D)
Decode

4

-

7-71

4

-

7-73

2n bits

n
Decode from 256 to 8
(S)
Encode
n
2 bits

to 0
(S)

SEGP

2

(D)

(D)
n

3

7-75

7SEG

2-35

2.5 Application Instructions
2.5.5 Data processing instructions

DECOP

Encode

7-seg-

n

(S)
DECOP

4

(S2)

S1 S2 D n

SUM

Bit checks

32 bits
(S1)

2

4

n

Data
searches

See for Description

Execution

Processing Details

Subset

SER

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.22 Data Processing Instructions

S D n

DISP

DISP

S D n

UNI

UNI

S D n

UNIP

UNIP

S D n

NDIS

NDIS

S1 D S2

NDISP

NDISP

S1 D S2

Separating
and linking

NUNI

NUNI

S1 D S2

NUNIP

NUNIP

S1 D S2

WTOB

WTOB

S D n

WTOBP

WTOBP

S D n

BTOW

BTOW

S D n

BTOWP

BTOWP

S D n

MAX

MAX

S D n

MAXP

MAXP

S D n

Condition

• Separates 16-bit data designated by (S)
into 4-bit units, and stores at the lower 4
bits of n points from (D). (n

4

-

7-77

4

-

7-79

4

-

7-81

4

-

7-85

4)

• Links the lower 4 bits of n points from the
device designated by (S) and stores at the
device designated by (D). (n

See for Description

DIS

Execution

Processing Details

Subset

DIS

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.22 Data Processing Instructions (Continued)

4)

• Separates the data in the devices starting
from the one specified by (S1) into bits
specified by the devices from (S2), and
stores them to the devices starting from the
one specified by (D).
• Links the data in the devices starting from
the one specified by (S1) with bits specified
by the devices from (S2), and stores them
to the devices starting from the one
specified by (D).
• Breaks n points of 16-bit data from the
device designated by (S) into 8-bit units,
and stores in sequence at the device
designated by (D).
• Links the lower 8 bits of 16-bit data of n
points from the device designated by (S)
into 16-bit units, and stores in sequence at
the device designated by (D).
• Searches the data of n points from the
device designated by (S) in 16-bit units,
and stores the maximum value at the
device designated by (D).

7-89
4

MIN

MIN

S D n

MINP

MINP

S D n

DMAX

DMAX

S D n

-

• Searches the data of n points from the
device designated by (S) in 16-bit units,
and stores the minimum value at the
device designated by (D).

7-92

• Searches the data of 2n points from the
device designated by (S) in 32-bit units,
and stores the maximum value at the
device designated by (D).

7-89

Search

DMAXP

DMAXP

S D n

4
DMIN
DMINP

2-36

DMIN
DMINP

S D n
S D n

• Searches the data of 2n points from the
device designated by (S) in 32-bit units,
and stores the minimum value at the
device designated by (D).

7-92

SORT

SORT
S1 n S2 D1 D2
· S2: Number of comparisons to be
made during a single run
· D1: Device to be turned ON at the
completion of sort
· D2: For system use

Execution
Condition

WSUM

WSUM

S D n

(n x (n-1)/2 scans required)
-

calculations

WSUMP

WSUMP

S D n

DWSUM

DWSUM

S D n

(n x (n-1)/2 scans required)

6

• Adds 16 bit BIN data of n points from the
7-99

the device specified by (D).

of averages

MEAN

S D n

MEANP

MEANP

S D n

7-101

the device specified by (D).

8

• Calculates the mean of n-point devices
(in 16-bit units) starting from the device
specified by (S), and then stores the
result into the device specified by (D).
4

DMEAN

DMEAN

DMEANP

DMEANP S D n

S D n

• Calculates the mean of n-point devices

-

7-103

(in 32-bit units) starting from the device
specified by (S), and then stores the
result into the device specified by (D).

2-37

2.5 Application Instructions
2.5.5 Data processing instructions

Calculation

MEAN

7

-

• Adds 32 bit BIN data of n points from the
device specified by (S), and stores it in

DWSUMP S D n

4
2

designated by (S1) in 32-bit units.

4

DWSUMP

7-95

• Sorts data of 2n points from device

device specified by (S), and stores it in
Total value

2

designated by (S1) in 16-bit units.

6

DSORT

1

4

• Sorts data of n points from device

Sort
DSORT S1 n S2 D1 D2
· S2: Number of comparisons to be
made during a single run
· D1: Device to be turned ON at the
completion of sort
· D2: For system use

See for Description

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.22 Data Processing Instructions (Continued)

2.5.6

Structure creation instructions

FOR

Number of
repeats

FOR

NEXT

n

and NEXT .

NEXT

BREAK

BREAK

BREAKP

D Pn

BREAKP

D Pn

CALL

Pn

CALL

CALL

Pn S1 Sn
CALLP

Pn

CALLP

CALLP
RET

RET
FCALL
FCALL

Pn

Pn S1 Sn

program
calls

FCALLP

Pn

FCALLP

ECALL
ECALL

1

-

3

-

7-105

7-108

• Executes subroutine program Pn when

*1

input condition is met. (S1 to Sn are

2

arguments sent to subroutine program.

+

n

n

5)

*3

7-110

• Returns from subroutine program

1

• Performs non-execution processing of

*1

subroutine program Pn if input

2

conditions have not been met. (S1 to

+

Sn are arguments sent to subroutine

n

-

7-115

-

7-116

-

7-120

5)

Pn
Pn S1 Sn

ECALLP
ECALLP

-

Pn Sn S1

: File name

ECALLP

2

to NEXT cycle and jumps pointer Pn.

program. n
FCALLP

ECALL

• Forcibly ends the execution of the FOR

Condition

Pn S1 Sn

FCALL
Subroutine

• Executes n times between the FOR

Execution

See for Description

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.23 Structure Creation Instructions

Pn S1 Sn

• Executes subroutine program Pn from

*2

within designated program name when

3

input condition is met. (S1 to Sn are

+

arguments sent to subroutine program.

n

n

5)

: File name

*1: n indicates number of arguments for subroutine program.
*2: n indicates the total of the number of arguments used in the subroutine program and the number of program
name steps. The number of program name steps is calculated as "number of characters in the program/2"
(decimal fraction is rounded up).
*3: The subset is effective only with the Universal model QCPU.

2-38

Processing Details

EFCALL
EFCALL

EFCALL

Pn S1toSn

EFCALLP
EFCALLP

program

Condition

Pn

EFCALLP

Pn S1toSn

• Performs non-execution processing of

3

conditions have not been met. (S1 to

+

Sn are arguments sent to subroutine

n

program. N

-

7-125

5)

input condition is met.
XCALL

XCALL

Pn S1 Sn

subroutine program Pn if input
conditions have not been met. (S1 to
Sn are arguments sent to subroutine
program. N

2
6

*1

2
+

-

7-129

7

n

5)

• Performs auto refresh of intelligent
COM

function modules, link refresh, auto

COM

refresh of CPU shared memory, and

1

-

7-134

1

-

7-141

1

-

7-137

2

-

1

-

• Performs auto refresh of intelligent

CCOM

CCOM

function modules, auto refresh of CPU

1

-

3

-

COM

IX

CCOMP

IX

S

Device indexing ladder
IXEND
IXDEV

with peripherals after the input
conditions are met.
• Perform indexing for individual devices
used in device indexing ladder.

IXEND
IXDEV
IXSET

S D

IXSET

7-144

• Stores indexing value used for indexing
7-148

performed between the IX and IXEND
to the device designated by D or later.

Designates indexing value.

*1: n indicates number of arguments for subroutine program.
*2: n indicates the total of the number of arguments used in the subroutine program and the number of program
name steps. The number of program name steps is calculated as "number of characters in the program/2"
(decimal fraction is rounded up).

2-39

2.5 Application Instructions
2.5.6 Structure creation instructions

shared memory, and communications

indexing

8

communications with peripherals.

Select

Fixed

4

• Executes subroutine program Pn when
• Performs non-execution processing of

refresh

2

*2

subroutine program Pn if input

:File name

calls

1

4

Pn

:File name

Subroutine

Execution

See for Description

Symbol

Subset

Category

Number of Basic Steps

Instruction Symbol

Table 2.23 Structure Creation Instructions (Continued)

2.5.7

Data table operation instructions

S D

FIFWP

FIFWP

S D

FIFR

FIFR

S D

FIFRP

FIFRP

S D

FPOP

FPOP

S D

(S)

(D) Pointer

Condition

FPOPP

FPOPP
FDEL

S D n

FDELP

FDELP

S D n

-

7-151

3

-

7-153

3

-

7-155

4

-

Device at
pointer + 1
(S) Pointer

(S) Pointer

(D)

Pointer - 1

Pointer - 1

S D

FDEL

3

Pointer + 1

(D)

Data table
processing

See for Description

FIFW

Execution

Processing Details

Subset

FIFW

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.24 Data table Operation Instructions

Device at pointer + 1
(S) Pointer

Pointer - 1 (D)

Designated by n
FINS

FINS

S D n

(S)

(D) Pointer

7-157

Pointer + 1
4

FINSP

2-40

FINSP

S D n

Designated by n

-

2.5.8

Buffer memory access instructions

1

FROM

FROM

Processing Details

n1 n2 D n3

FROMP

FROMP

n1 n2 D n3

DFRO

DFRO

n1 n2 D n3

Execution
Condition

• Reads data in 16-bit units from an
intelligent function module.

5

-

See for Description

Symbol

Subset

Category

Number of Basic Steps

Instruction Symbol

Table 2.25 Buffer Memory Access Instructions

2
4
4

7-160

Data read

DFROP

DFROP

n1 n2 D n3

TO

TO

n1 n2 S n3

TOP

TOP

n1 n2 S n3

DTO

DTO

n1 n2 S n3

• Reads data in 32-bit units from an
intelligent function module.

• Writes data in 16-bit units to an
intelligent function module.

5

-

2

5

-

6
7-163

Data write

DTOP

2.5.9

DTOP

n1 n2 S n3

• Writes data in 32-bit units to an

5

intelligent function module.

-

7
8

Display instructions

PR

ASCII
print

PR

When SM701 is OFF
PR
S D

When SM701 is ON
PR
S D

Execution
Condition

See for Description

Processing Details

Subset

Symbol

Number of Basic Steps

Category

• Outputs ASCII code of 8 points (16
characters) from device designated by
(S) to output module.

7-166

• Outputs ASCII code from device
designated by (S) to 00H to output

3

-

module.
• Converts comments from device

PRC

PRC

S D

designated by (S) to ASCII code and

7-169

outputs to output module.
Reset

LEDR

LEDR

• Resets annunciator and LED indicator
display.

1

-

7-172

2-41

2.5 Application Instructions
2.5.8 Buffer memory access instructions

Instruction Symbol

Table 2.26 Display Instructions

2.5.10

Debugging and failure diagnosis instructions

Condition

See for Description

Execution

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.27 Debugging and Failure Diagnosis Instructions

1

-

7-175

1

-

7-179

• The CHK instruction is executed when
CHKST is executable.
CHKST

CHKST

• Jumps to the step following the CHK
instruction when CHKST is in a
non-executable status.
• During normal conditions

Checks

CHK

CHK

SD80 : 0
• During abnormal conditions

Check condition

SM80 : OFF,
SM80 : ON,

SD80 : Failure No.

2-42

CHKCIR

CHKCIR

CHKEND

CHKEND

• Starts update in ladder pattern being
checked by the CHK instruction.
• Ends update in ladder pattern being
checked by the CHK instruction.

2.5.11

Character string processing instructions

1

BIN

Decimal

BINDAP
DBINDA

BINDA
BINDAP
DBINDA

S D
S D
S D

ASCII

DBINDAP S D

Condition

3

-

• Converts 1-word BIN value designated
by (S) to a 5-digit, decimal ASCII value,
and stores it at the word device

BINHA

S D

7-183

by (S) to a 10-digit, decimal ASCII value,
3

BINHAP

BINHAP

S D

6

• Converts 1-word BIN value designated
by (S) to a 4-digit, hexadecimal ASCII
3

ASCII

DBINHA

DBINHA

S D

DBINHAP S D

7-186

• Converts 2-word BIN value designated
by (S) to an 8-digit, hexadecimal ASCII
value, and stores it at word devices

DBINHAP

7

-

following the word device number
designated by (D).

Hexadecimal

2

-

the word device number designated by

value, and stores it at a word device
BIN

4
4

(D).
BINHA

2

designated by (D).
• Converts 2-word BIN value designated
and stores it at word devices following

DBINDAP

Execution

See for Description

Processing Details

Subset

BINDA

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.28 Character String Processing Instructions

3

-

3

-

8

following the word device number
designated by (D).

BCDDA

S D

BCDDAP

BCDDAP

S D

• Converts 1-word BCD value designated
by (S) to a 4-digit, decimal ASCII value,
and stores it at a word device following

BCD

the word device number designated by
(D).

Decimal
ASCII

DBCDDA

DBCDDA

DBCDDAP

DBCDDAP S D

S D

7-189

• Converts 2-word BCD value designated
by (S) to an 8-digit, decimal ASCII value,
and stores it at word devices following

3

-

3

-

the word device number designated by
(D).

Decimal
ASCII

BIN

Hexadecimal
ASCII

BIN

DABIN

DABIN

S D

DABINP

DABINP

S D

DDABIN

DDABIN

S D

• Converts a 5-digit, decimal ASCII value
designated by (S) to a 1-word BIN value,
and stores it at a word device number
designated by (D).
7-192
• Converts a 10-digit, decimal ASCII value
designated by (S) to a 2-word BIN value,
and stores it at a word device number

DDABINP

DDABINP S D

HABIN

HABIN

S D

HABINP

HABINP

S D

DHABIN

DHABIN

S D

3

-

3

-

designated by (D).
• Converts a 4-digit, hexadecimal ASCII
value designated by (S) to a 1-word BIN
value, and stores it at a word device
number designated by (D).
7-195

DHABINP

• Converts an 8-digit, hexadecimal ASCII
designated by (S) value to a 2-word BIN
value, and stores it at a word device

DHABINP S D

3

-

number designated by (D).

2-43

2.5 Application Instructions
2.5.11 Character string processing instructions

BCDDA

ASCII

BCD

DABCD

S D

DABCDP

DABCDP

S D

DDABCD

DDABCD

S D

DDABCDP
Device
comment
read
operation
Character

COMRD

DDABCDP S D
COMRD

S D

COMRDP

COMRDP S D

LEN

LEN

S D

LENP

LENP

S D

string length
detection

BIN

STR

STR

S1 S2 D

STRP

STRP

S1 S2 D

DSTR

DSTR

S1 S2 D

Decimal
character
string
DSTRP

DSTRP

VAL

VAL

S1 S2 D

S D1 D2

Decimal
character

VALP

VALP

S D1 D2

DVAL

DVAL

S D1 D2

DVALP

DVALP

S D1 D2

ESTR

ESTR

string

BIN

Floating
decimal point

Character
string

Character
string

Floating
decimal point

2-44

ESTRP

EVAL

EVALP

ESTRP

EVAL

EVALP

• Converts a 4-digit, decimal ASCII value
designated by (S) to a 1-word BCD
value, and stores it at a word device
number designated by (D).

3

-

• Converts a 8-digit decimal ASCII value
designated by (S) to a 2-word BCD
value, and stores it at the word device
number designated by (D).

3

-

• Stores comment from device designated
by (S) at a device designated by (D).

3

-

7-201

• Stores data length (number of
characters) in character string
designated by (S) at a device designated
by (D).

3

-

7-204

• Converts a 1-word BIN value designated
by (S2) to a decimal character string with
the total number of digits and the
number of decimal fraction digits
designated by (S1) and stores them at a
device designated by (D).

4

-

• Converts a 2-word BIN value designated
by (S2) to a decimal character string with
the total number of digits and the
number of decimal fraction digits
designated by (S1) and stores them at a
device designated by (D).

4

-

• Converts a character string including
decimal point designated by (S) to a
1-word BIN value and the number of
decimal fraction digits, and stores them
into devices designated by (D1) and (D2).

4

-

• Converts a character string including
decimal point designated by (S) to a
2-word BIN value and the number of
decimal fraction digits, and stores them
into devices designated by (D1) and (D2).

4

-

• Converts the 32-bit floating decimal point
data designated by (S) to a character
string, and stores it in devices
designated by (D).

4

-

7-217

• Converts the character string designated
by (S) to a 32-bit floating decimal point
data, and stores it in devices designated
by (D).

3

-

7-224

Processing Details

S1 S2 D

S1 S2 D

S D

S D

Execution
Condition

See for Description

DABCD

Subset

Decimal

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.28 Character String Processing Instructions (Continued)

7-198

7-206

7-212

Hexadecimal
BIN

ASCII
ASCII

Hexadecimal
BIN

ASC

ASC

S D n

ASCP

ASCP

S D n

HEX

HEX

S D n

HEXP

HEXP

S D n

RIGHT

RIGHT

S D n

RIGHTP

RIGHTP

S D n

LEFT

LEFT

S D n

Execution
Condition

See for Description

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.28 Character String Processing Instructions (Continued)

4

• Converts n hexadecimal ASCII
characters of the device numbers
designated by (S) and after to BIN
values, and stores them at the device
numbers designated by (D).

4

-

7-228

4
-

7-230

• Stores n characters from the end of a

6
-

7-232

7

• Stores n characters from the beginning
of a character string designated by (S) at

S D n

MIDR

MIDR

S1 D S2

MIDRP

MIDRP

S1 D S2

2

device designated by (D).
4

LEFTP

2
4

• Converts the 1-word BIN value at the
device numbers designated by (S) to
hexadecimal ASCII, and stores n
characters of them at the device numbers
designated by (D) and after.

character string designated by (S) at the

LEFTP

1

the device designated by (D).

8

• Stores the designated number of
characters in the character string
designated by (S1) from the position
designated by (S2) at the device
designated by (D).

MIDW

MIDW

S1 D S2

string

5

-

7-239

4

-

7-241

4

-

7-243

4

-

7-245

4

-

7-248

• Stores the character string of (S1) in the

MIDWP

S1 D S2

INSTR

INSTR

S1 S2 D n

INSTRP

INSTRP

S1 S2 D n

of (D) at the position specified by (S2).
• Searches character string (S1) from the
nth character of character string (S2),

STRINS

STRINS

STRINSP

STRINSP S D n

STRDEL

STRDEL

STRDELP

STRDELP D n1 n2

S D n

D n1 n2

and stores matched positions at (D).
• Inserts the character string data
specified by (S) to the (n)th character
(insert position) from the initial character
string data specified by (D).
• Deletes the (n2) characters data
specified by (D) starting from the

EMOD

decimal point

device(insert position) specified by n1.
• Converts 32-bit floating decimal point

EMOD

S1 S2 D

data (S1) to BCD data with number of
decimal fraction digits designated by

BCD

EMODP

EMODP

S1 S2 D

BCD

EREXP

EREXP

S1 S2 D

(S2) , and stores at device designated
by (D).
• Converts BCD data (S1) to 32-bit
floating decimal point data with the
number of decimal fraction digits

Floating
decimal point

7-235

specified number to the character string
MIDWP

Floating

-

EREXPP

EREXPP S1 S2 D

designated by (S2), and stores at device
designated by (D).

2-45

2.5 Application Instructions
2.5.11 Character string processing instructions

Character

4

2.5.12

Special function instructions

See for Description

functions

Subset

Trigonometric

Number of Basic Steps

Category

Instruction Symbol

Table 2.29 Special Function Instructions

Sin (S+1,S)

(D+1,D)

3

-

7-250

Cos(S+1,S)

(D+1,D)

3

-

7-254

Tan(S+1,S)

(D+1,D)

3

-

7-258

Symbol

Processing Details

SIN

SIN

S D

SINP

SINP

S D

COS

COS

S D

COSP

COSP

S D

TAN

TAN

S D

TANP

TANP

S D

ASIN

ASIN

S D

Execution
Condition

(Floatingpoint singleprecision)

Trigonometric
functions

ASINP

ASINP

S D

ACOS

ACOS

S D

ACOSP

ACOSP

S D

ATAN

ATAN

S D

ATANP

ATANP

S D

SIND

SIND

S D

SINDP

SINDP

S D

COSD

COSD

S D

COSDP

COSDP

S D

TAND

TAND

S D

TANDP

TANDP

S D

ASIND

ASIND

S D

ASINDP

ASINDP

S D

ACOSD

ACOSD

S D

ACOSDP

ACOSDP

S D

ATAND

ATAND

S D

ATANDP

S D

Sin -1 (S+1,S)

(D+1,D)

3

-

7-262

Cos-1(S+1,S)

(D+1,D)

3

-

7-267

Tan-1(S+1,S)

(D+1,D)

3

-

7-271

Sin(S+3, S+2, S+1, S)
(D+3, D+2, D+1, D)

3

-

7-252

Cos(S+3, S+2, S+1, S)
(D+3, D+2, D+1, D)

3

-

7-256

Tan(S+3, S+2, S+1, S)
(D+3, D+2, D+1, D)

3

-

7-260

3

-

7-265

3

-

7-269

3

-

7-273

(Floatingpoint doubleprecision)

ATANDP

2-46

-1

Sin (S+3, S+2, S+1, S)
(D+3, D+2, D+1, D)

-1

Cos (S+3, S+2, S+1, S)
(D+3, D+2, D+1, D)

-1

Tan (S+3, S+2, S+1, S)
(D+3, D+2, D+1, D)

See for Description

3

-

7-275

(D+3, D+2, D+1, D)
(S+3, S+2, S+1, S)
Conversion from angle to radian

3

-

7-277

(D+1, D)
(S+1, S)
Conversion from radians to angles

3

-

7-279

(S+3, S+2, S+1, S) (D+3, D+2, D+1, D)
Conversion from radian to angle

3

-

7-281

3

-

7-287

3

-

7-289

(D+1,D)

3

-

7-291

(D+3, D+2, D+1, D)

3

-

7-294

(D+1,D)

3

-

7-296

(D+3, D+2, D+1, D)

3

-

7-298

4

-

7-300

4

-

7-302

3

-

7-300

3

-

7-302

Processing Details

RAD

S D

RADP

RADP

S D

RADD

RADD

S D

RADDP

RADDP

S D

DEG

DEG

S D

DEGP

DEGP

S D

DEGD

DEGD

S D

conversion

(D+1, D)
(S+1, S)
Conversion from angles to radians

Symbol

Angles

Radians

Subset

RAD

Number of Basic Steps

Category

Instruction Symbol

Table 2.29 Special Function Instructions (Continued)

DEGDP

DEGDP

S D

SQR

SQR

S D
(D+1,D)

(S+1,S)
SQRP

SQRP

S D

SQRD

SQRD

S D

Execution
Condition

SQRDP

SQRDP

S D

EXP

EXP

S D
e(S+1,S)

operations

EXPP

S D

EXPD

EXPD

S D

e(S+3, S+2, S+1, S)
EXPDP

EXPDP

S D

LOG

LOG

S D

LOGP

LOGP

S D

LOGD

LOGD

S D

LOGDP

LOGDP

S D

Loge (S+1,S)
Natural
logarithms

Loge(S+3, S+2, S+1, S)

POW

POW

S1 S2 D

• (S1+1,S1)
Expone
ntiation

POWP

POWP

S1 S2 D

POWD

POWD

S1 S2 D

POWDP

Common
logarithm

POWDP

S1 S2 D

LOG10

LOG10P
LOG10

S D

LOG10P

LOG10P

S D

LOG10D

LOG10D

S D

LOG10DP

LOG10DP S D

(S2+1,S2)

(D+1,D)

(S2+3,S2+2,S2+1,S2)

• (S1+3,S1+2,S1+1,S1)

• log10(S+1,S)

(D+3,D+2,D+1,D)

(D+1,D)

• log10(S+3,S+2S+1,S)

(D+3,D+2,D+1,D)

2-47

4
2
6
7
8

2.5 Application Instructions
2.5.12 Special function instructions

Exponent

EXPP

(D+3, D+2, D+1, D)

2
4

Square root

(S+3, S+2, S+1, S)

1

RND

D

generation

RNDP

RNDP

D

Random

SRND

SRND

D

• Updates random number series

SRNDP

SRNDP

D

in the device designated by (S).

number
series update

BSQR

BSQR

S D

BSQRP

BSQRP

S D

BDSQR

BDSQR

S D

BDSQRP

BDSQRP S D

BSIN

BSIN

S D

BSINP

BSINP

S D

BCOS

BCOS

S D

BCOSP

BCOSP

S D

BTAN

BTAN

S D

BTANP

BTANP

S D

BASIN

BASIN

S D

BASINP

BASINP

S D

BACOS

BACOS

S D

BACOSP

BACOSP

S D

BATAN

BATAN

S D

BATANP

BATANP

S D

Square root

Trigonometric
functions

2-48

Condition

2

-

7-304

3

-

• Generates a random number (from 0 to

RND

number

Execution

See for Description

Processing Details

Subset

Random

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.29 Special Function Instructions (Continued)

less than 32767) and stores it at the
device designated by (D).

according to the 16-bit BIN data stored

(S)

(D)+0 Integer part
+1 Decimal fraction part

7-306
(D)+0 Integer part
+1 Decimal fraction part

3

-

Sin(S)

(D)+0 Sign
+1 Integer part
+2 Decimal fraction part

3

-

7-309

Cos(S)

(D)+0 Sign
+1 Integer part
+2 Decimal fraction part

3

-

7-311

Tan(S)

(D)+0 Sign
+1 Integer part
+2 Decimal fraction part

3

-

7-313

Sin -1 (S)

(D)+0 Sign
+1 Integer part
+2 Decimal fraction part

3

-

7-315

Cos -1 (S)

(D) +0 Sign
+1 Integer part
+2 Decimal fraction part

3

-

7-317

3

-

7-319

(S+1, S)

Tan -1 (S)

(D) +0 Sign
+1 Integer part
+2 Decimal fraction part

2.5.13

Data control instructions

1

LIMIT

LIMIT

S1 S2 S3 D

Condition

Upper and

LIMITP

S1 S2 S3 D

5

controls

2

• When (S2)
(S3)
......... Stores value of (S2) at (D)

7-321
DLIMIT

DLIMIT

S1 S2 S3 D

• When ((S3)+1, (S3))
((S1)+1, S1)
.. Stores value of ((S1)+1, (S1)) at ((D)+1, (D))
• When ((S1)+1, (S1))
((S3)+1, (S3))
(S2+1, S2)
.. Stores value of ((S3)+1, (S3)) at ((D)+1, (D))

DLIMITP

S1 S2 S3 D

• When ((S2), (S2)+1)
((S3), (S3)+1)
.. Stores value of ((S2)+1, (S2)) at ((D)+1, (D))

BAND

BAND

S1 S2 S3 D

• When (S1)

(S3)

• When (S3)

(S1)......... (S3)

(S1)

(D)

BANDP

BANDP

S1 S2 S3 D

• When (S2)

(S3)......... (S3)

(S2)

(D)

band

DBAND

DBAND

S1 S2 S3 D

controls

• When ((S1)+1, (S1))

((S3)+1, (S3))

DBANDP S1 S2 S3 D

ZONE

ZONE

ZONEP

ZONEP

S1 S2 S3 D
S1 S2 S3 D

((S3)+1, (S3))

DZONE

controls

DZONE

S1 S2 S3 D

((D)+1, (D))

• When (S3)

0 ................................ 0

• When (S3)

0 .................. (S3)+(S2)

(D)

• When (S3)

0 .............. (S3)

(D)

7-324
5

-

(S1)

5

-

(D)

0

.................................... 0

• When ((S3)+1, (S3))

-

((D)+1, (D))

((D)+1, (D))

((D)+1, (D))

DZONEP S1 S2 S3 D

5

((D)+1, (D))

• When ((S3)+1, (S3))
0
......... ((S3)+1, (S3))+((S2)+1, (S2))

DZONEP

8

((S3)+1, (S3)) .......

((S2)+1, (S2))

• When ((S3)+1, (S3))
Zone

7

(D)

((S1)+1, (S1)) ........

((S1)+1, (S1))

• When ((S2)+1, (S2))

-

((S3)+1, (S3))

((S2)+1, (S2)) ................... 0
• When ((S3)+1, (S3))

DBANDP

(S2)..............0

5

6

7-327
5

-

0

........ ((S3)+1, (S3)) + ((S1)+1, (S1))
((D)+1, (D))

2-49

2.5 Application Instructions
2.5.13 Data control instructions

DLIMITP

Dead

4

-

lower
limit

2

4

• When (S3)
(S1)
......... Stores value of (S1) at (D)
• When (S1)
(S3)
(S2)
......... Stores value of (S3) at (D)

LIMITP

See for Description

Execution

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.30 Data Control Instructions

Execution
Condition

4

-

See for Description

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.30 Special Function Instructions (Continued)

• Executes scaling for the scaling
SCL

SCL

S1 S2 D

conversion data (16-bit data units)
specified by (S2) with the input value
specified by (S1), and then stores the
result into the device specified by (D).
The scaling conversion is executed

SCLP

SCLP

S1 S2 D

based on the scaling conversion data

Point-by-

stored in the device specified by (S2) an

point

up.

coordinate
data

7-330

• Executes scaling for the scaling
DSCL

DSCL

S1 S2 D

conversion data (32-bit data units)
specified by (S2) with the input value
specified by (S1), and then stores the
result into the device specified by (D).

4

-

4

-

The scaling conversion is executed
DSCLP

DSCLP

S1 S2 D

based on the scaling conversion data
stored in the device specified by (S2) an
up.
• Executes scaling for the scaling

SCL2

SCL2

S1 S2 D

conversion data (16-bit data units)
specified by (S2) with the input value
specified by (S1), and then stores the
result into the device specified by (D).
The scaling conversion is executed

SCL2P

SCL2P

S1 S2 D

based on the scaling conversion data
stored in the device specified by (S2)

X or Y

and up.

coordinate

7-334

• Executes scaling for the scaling

data
DSCL2

DSCL2

S1 S2 D

conversion data (32-bit data units)
specified by (S2) with the input value
specified by (S1), and then stores the
result into the device specified by (D).
The scaling conversion is executed

DSCL2P

DSCL2P

S1 S2 D

based on the scaling conversion data
stored in the device specified by (S2)
and up.

2-50

4

-

2.5.14

Switching instructions

1

RSET

S

number
switching

RSETP

RSETP

S

QDRSET

QDRSET

QDRSETP

QDRSETP File name

QCDSET

QCDSET

• Converts extension file register block
number to number designated by (S).

2

-

7-337

2
+

-

• Sets file names used as comment files.

2
+

4
4

7-339

6

*1

File name

2

2

n

File set

QCDSETP File name

Condition

*1

File name

• Sets file names used as file registers.

QCDSETP

Execution

See for Description

RSET

Processing Details

Subset

Block

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.31 Switching Instructions

-

7-342

7

n

*1: n ([number of file name characters] / 2) indicates a step. (Decimal fractions are rounded up.)

8

2.5 Application Instructions
2.5.14 Switching instructions

2-51

2.5.15

Clock instructions

DATERD

D

DATERDP

DATERDP D

DATEWR

DATEWR S

Read/

(Clock elements)

(D) +0
Year
+1
Month
+2
Day
+3
Hour
+4
Minute
+5
Sec.
+6 Day of the week

Execution
Condition

See for Description

DATERD

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.32 Clock Instructions

2

-

7-344

2

-

7-346

write clock
data

DATEWRP

DATE+
Clock data DATE+P

DATEWRP S

DATE+

S1 S2 D

DATE+P

S1 S2 D

DATE-

S1 S2 D

(D) +0
Year
+1
Month
+2
Day
+3
Hour
+4
Minute
+5
Sec.
+6 Day of the week

(Clock elements)

(S1)
Hour
Mitnute
Sec.

(S2)
Hour
+ Mitnute
Sec.

(D)
Hour
Mitnute
Sec.

4

-

7-348

(S1)
Hour
Mitnute
Sec.

(S2)
Hour
Mitnute
Sec.

(D)
Hour
Mitnute
Sec.

4

-

7-350

3

-

7-352

3

-

7-354

addition/
subtraction DATEDATE-P

Clock data
translation

S1 S2 D

SECOND

SECOND S D

SECONDP

SECONDP S D

HOUR
HOURP

2-52

DATE-P

HOUR
HOURP

S D
S D

(S)
Hour
Minute
Sec.

(D)
Sec. (Lower 16 bits)
Sec. (Upper 16 bits)

(S)
Sec. (Lower 16 bits)
Sec. (Upper 16 bits)

(D)
Hour
Mitnute
Sec.

LDDT=
ANDDT=

ORDT=

LDDT<>
ANDDT<>

ORDT<>

LDDT<
ANDDT<

ORDT<
Date
comparison

DT

S1 S2 n

DT

S1 S2 n

DT

S1 S2 n

DT

S1 S2 n

DT
DT

DT

Condition

See for Description

Execution

1
2
4

S1

Year

S2

Year

S1 +1 Month

S2 +1 Month

S1 +2 Day

S2 +2 Day

Companson
operation resuit

4

-

4

S1 S2 n

DT

DT

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.32 Character String Processing Instructions (Continued)

2
S1

Year

S2

Year

S1 +1 Month

S2 +1 Month

S1 +2 Day

S2 +2 Day

S1

S2

Companson
operation resuit

4

-

6

S1 S2 n

7

S1 S2 n
S1 S2 n

Year

Year

S1 +1 Month

S2 +1 Month

S1 +2 Day

S2 +2 Day

Companson
operation resuit

4

-

8

S1 S2 n

7-356
LDDT<=

ORDT<=

S1 S2 n

DT

S1 S2 n

DT
DT

S1 S2 n

ANDDT>

DT

S1 S2 n

LDDT>=
ANDDT>=

ORDT>=

DT

S2

Year

S2 +1 Month

S1 +2 Day

S2 +2 Day

S1

S2

Companson
operation resuit

4

-

Year

Companson
operation resuit

4

-

Companson
operation resuit

4

-

Year

S1 +1 Month

S2 +1 Month

S1 +2 Day

S2 +2 Day

S1

S2

S1 S2 n

DT

S1 S2 n

DT

S1 S2 n

DT

Year

S1 +1 Month

S1 S2 n

LDDT>

ORDT>

S1

2.5 Application Instructions
2.5.15 Clock instructions

ANDDT<=

DT

Year

Year

S1 +1 Month

S2 +1 Month

S1 +2 Day

S2 +2 Day

S1 S2 n

2-53

ANDTM=

ORTM=

LDTM<>
ANDTM<>

ORTM<>

LDTM<
ANDTM<

ORTM<
Clock
comparison

TM

TM

S1 S2 n

S1 S2 n

TM

S1 S2 n

S1

Hour

S2

4

-

Companson
operation resuit

4

-

See for Description

Companson
operation resuit

Hour

S1 +1 Minute

S2 +1 Minute

S1 +2 Second

S2 +2 Second

S1

S2

Companson
operation resuit

Hour

Hour

S1 +1 Minute

S2 +1 Minute

S1 +2 Second

S2 +2 Second

S1

S2

S1 S2 n

TM

S1 S2 n

TM

S1 S2 n

TM

-

Condition

S1 S2 n

TM

TM

4

Execution

Processing Details

S1 S2 n

Hour

Hour

S1 +1 Minute

S2 +1 Minute

S1 +2 Second

S2 +2 Second

S1 S2 n

7-361
LDTM<=

TM

S1 S2 n

ANDTM<=

TM

S1 S2 n

ORTM<=

LDTM>
ANDTM>

ORTM>

LDTM>=
ANDTM>=

ORTM>=

2-54

TM

Subset

LDTM=

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.32 Character String Processing Instructions (Continued)

TM

S1 S2 n

TM

S1 S2 n

S2

Hour

S2 +1 Minute

S1 +2 Second

S2 +2 Second

S1

S2

Companson
operation resuit

4

-

Hour

Companson
operation resuit

4

-

Companson
operation resuit

4

-

Hour

S1 +1 Minute

S2 +1 Minute

S1 +2 Second

S2 +2 Second

S1

S2

S1 S2 n

TM

S1 S2 n

TM

S1 S2 n

TM

Hour

S1 +1 Minute

S1 S2 n

TM

TM

S1

S1 S2 n

Hour

Hour

S1 +1 Minute

S2 +1 Minute

S1 +2 Second

S2 +2 Second

2.5.16

Expansion clock instruction

1

S.DATReading

ERD

(Clock elements)
S.DATERD D

data of the
expansion clock

SP.DATERD

S.DATE+

SP.DATERD D

S.DATE+ S1 S2 D

Adding or
subtracting

SP.DATE+

data val-

SP.DATE+ S1 S2 D

ues of the
expansion

S.DATE-

S.DATE

S1 S2 D

clock
SP.DATE-

SP.DATE

S1 S2 D

(S1)
Hour
Minute
Sec.

1/1000 sec.

Condition

(D) +0
Year
+1
Month
+2
Day
+3
Hour
+4
Minute
+5
Sec.
+6 Day of the week
+7 1/1000 sec.

(S2)
Hour
Minute
+
Sec.

1/1000 sec.

See for Description

Execution

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.33 Expansion clock instruction

6

-

2
6
8

-

1/1000 sec.

(S1)
Hour
Minute
Sec.

(S2)
Hour
Minute
Sec.

(D)

1/1000 sec.

1/1000 sec.

1/1000 sec.

Hour
Minute
Sec.

4
4

(D)

Hour
Minute
Sec.

2

7
8

-

8

2.5 Application Instructions
2.5.16 Expansion clock instruction

2-55

2.5.17

Program control instructions

File name

PSTOPP

PSTOPP

File name

POFF

POFF

File name

Program
control
instructions

POFFP

File name

PSCAN

PSCAN

File name

PSCANP

PSCANP

File name

PLOW

PLOW

File name

PLOWP

PLOWP

LDPCHK

PCHK

File name

status.

• Turns OUT instruction coil of designated
standby status.

ORPCHK

PCHK

PCHK

2
+
n

7-377

-

7-378

-

7-380

-

7-382

-

7-384

*1

2
+
n

execution type.

2
+
n
*1

• Registers designated program as
low-speed execution type.

2
+
n

File name
File name

file name is being executed.

*1

2

• In non-conduction when program of

+

specified file name is not executed.

n

File name

*1: n ([number of file name characters] / 2) indicates a step. (Decimal fractions are rounded up.)

2-56

-

*1

• Registers designated program as scan

• In conduction when program of specified
ANDPCHK

Condition

*1

• Places designated program in standby

program OFF, and places program in
POFFP

Execution

See for Description

PSTOP

Processing Details

Subset

PSTOP

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.34 Program Control Instructions

2.5.18

Other instructions

1

reset

WDT

WDTP

Timing

DUTY

clock

• Resets watchdog timer during sequence
program.

WDTP

Condition

1

-

7-386

n1 scans

n1 n2 D

n2 scans

4

-

7-388

4

-

7-390

SM420 to SM424, SM430 to SM434
TIMCHK

TIMCHK

S1 S2 D

4
4

6

• Turns ON device specified by (D) if
Time check

2

2

(D)
DUTY

Execution

See for Description

WDT

WDT

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.35 Other Instructions

measured ON time of input condition is
longer than preset time continuously.

Direct read/
write

ZRRDB

ZRRDB

n D

ZRRDBP

ZRRDBP

n D

ZRWRB

ZRWRB

n S

0
1
2
3
n

Lower 8 bits ZR0
Upper 8 bits
Lower 8 bits ZR1
Upper 8 bits

operations in
1-byte units

ZRWRBP

ZRWRBP n

ADRSET

ADRSET

ADRSETP

S

ADRSETP S D

KEY

KEY

S n D1 D2

from keyboard

ZPUSH

D

register

ZPUSHP

ZPUSHP

D

Batch

ZPOP

ZPOP

D

ZPOPP

D

3

-

7-393

3

-

7-395

5

-

7-396

2

-

7-400

5

-

7-400

4

-

8 bits

(D)
Indirect address of
designated device

Device name
unit designated by (S), converts to
hexadecimal value following device

• Saves the contents of index registers to a

index register ZPOPP
Batch write
operation to
file

register

designated by (D).
• Reads the data stored in the location
starting from the device designated by

recovery of

E

Lower 8 bits
ZR0
Upper 8 bits
Lower 8 bits
ZR1
Upper 8 bits

location starting from the device

of index

2PROM

8

number designated by (D1), and stores.
ZPUSH

Batch save

7-391

• Takes in ASCII data for 8 points of input

Numerical
key input

(S)

S D

-

EROMWR

EROMWR

EROMWRP

EROMWRP S D1 n D2

S D1 n D2

(D) to index registers.

• Writes a batch of data to E2PROM file
register.

• Reads the module information stored in
Reading

UNIRD

UNIRD n1 D n2

the area starting from the I/O No.

module infor-

designated by n by the points designated

mation

by n2, and stores it in the area starting
UNIRDP

UNIRDP n1 D n2

from the device designated by (D).

2-57

2.5 Application Instructions
2.5.18 Other instructions

0
1
2
3
n

3

(D)

8 bits

(S)

7

TYPERD

n

D

TYPERDP

TYPERDP n

D

-

1

-

1

-

• Writes data to the designated file.

11

-

• Reads data from the designated file.

11

-

• Writes data to the device data storage file in
the standard ROM.

9

-

• Reads data from the device data storage file
in the standard ROM.

8

-

3

-

3

-

4

-

4

-

• This instruction reads the module
information stored in the area starting from
the I/O number specified by "n", and stores
it in the area starting from the device
specified by (D).

Execution
Condition

• Stores the trace data set with peripheral
Trace set

TRACE

TRACE

device by the number of times set when
SM800, SM801 and SM802 turn on, to
the sampling trace file.

Trace rset
Writing data to the
designated file

TRACER

TRACER

SP.FWRITE

SP.FWRITE U0 S0 D0 S1 S2 D1

SP.FREAD

SP.FREAD U0 S0 D0 S1 S2 D1

• Resets the data set the TRACE
instruction.

Reading data
from designated
file
Writing data to
standard ROM
Reading data from
standard ROM

S.DEVST

SP.DEVST n1 S n2 D

S.DEVLD

S.DEVLD n1 D n2

SP.DEVLD

SP.DEVLD n1 D n2

• Transfers the program stored in a
Loading program
from memory

PLOADP

PLOADP

S D

memory card or standard memory (other
than drive 0) to drive 0 and places the
program in standby status.

Unloading
program from

PUNLOADP

PUNLOADP S D

program memory

• Deletes the standby program stored in
standard memory (drive 0).
• Deletes standby program stored in
standard memory (drive 0) designated by

Load
+

PSWAPP

PSWAPP S1 S2 D

Unload

(S1). Then, transfers the program stored
in a memory card or standard memory
(other than drive 0) designated by (S2) to
drive 0 and places it in standby status.

High-speed

RBMOV

RBMOV S D n

block transfer of

device designated by (S) to the devices
of n points starting from the one

file register
RBMOVP

2-58

• Transfers n points of 16-bit data from the

RBMOVP S D n

designated by (D).

See for Description

Subset

3

Processing Details

TYPERD
Module model
name read

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.35 Other Instructions (Continued)

2.5.19

Instructions for Data Link

1

Q link
instruction:
Network
refresh

Reading
routing
information

Registering
routing
information

S.ZCOM

S.ZCOM

SP.ZCOM

SP.ZCOM Jn

S.ZCOM

S.ZCOM

SP.ZCOM

SP.ZCOM Un

Execution
Condition

See for Description

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.36 Instructions for Data Link

Refreshes the designated network.

5

-

8-2

2

Un

S.RTREAD

n D

SP.RTREAD

SP.RTREAD

n D

Z.RTREAD

Z.RTREAD

n D

ZP.RTREAD

ZP.RTREAD

n D

S.RTWRITE

S.RTWRITE

n S

SP.RTWRITE

SP.RTWRITE

n S

Z.RTWRITE

Z.RTWRITE

n S

ZP.RTWRITE

ZP.RTWRITE

n S

4
4

Jn

S.RTREAD

2

6
Reads data set at routing parameters.

7

-

8-6

7

Writes routing data to the area designated by
routing parameters.

8
8

-

8-8

2.5 Application Instructions
2.5.19 Instructions for Data Link

2-59

2.5.20

Multiple CPU dedicated instruction

S. TO

S.TO

n1 n2 n3 n4 D

SP. TO

SP.TO

n1 n2 n3 n4 D

TO

TO

n1 n2 S n3

TOP

TOP

n1 n2 S n3

DTO

DTO

n1 n2 S n3

DTOP

DTOP

n1 n2 S n3

CPU shared
memory

Read from other

FROM

FROM

n1 n2 D n3

FROMP

FROMP

n1 n2 D n3

DFRO

DFRO

n1 n2 D n3

DFROP

DFROP

n1 n2 D n3

CPU shared
memory

2.5.21

Processing Details

Execution
Condition

• Writes device data of the host station to
the host CPU shared memory.

• Writes device data of the host station to
the host CPU shared memory.

See for Description

Write to host

Symbol

Subset

Category

Number of Basic Steps

Instruction Symbol

Table 2.37 Multipe CPU dedicated instruction

5

-

9-4

5

9-7

• Writes device data of the host station to
the host CPU shared memory in 32-bit

5

-

5

-

units.
• Reads device data from the other CPU
shared memories, and stores the data in
the host station.

9-12

• Reads device data from the other CPU
shared memories in 32-bit units, and

5

-

stores the data in the host station.

Multiple CPU high-speed transmission dedicated instruction

D.DDWR

n S1 S2 D1 D2

In multiple CPU system, data stored in a

Execution
Condition

10

-

10

-

10

-

10

-

See for Description

Processing Details

Subset

D.DDWR

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.40 Multiple CPU high-speed transmission dedicated instruction

device specified by host CPU ( S2 ) or later is
Writing Devices
to Another CPU

stored by the number of write points specified
DP.DDWR

DP.DDWR n S1 S2 D1 D2

by ( D2 +1) into a device specified by another

10-13

CPU (n) ( D1 ) or later
D.DDRD

D.DDRD

n S1 S2 D1 D2

In multiple CPU system, data stored in a

Reading Devices

device specified by another CPU (n) ( D1 ) or

from Another

lrater is stored by the number of read points

CPU

DP.DDRD

DP.DDRD n S1 S2 D1 D2

specified by ( S1 +1) into a device specified by
host CPU ( S2 ) or late

2-60

10-17

2.5.22

Redundant system instructions (For Redundant CPU)

1

Execution
Condition

See for Description

Processing Details

Subset

Symbol

Number of Basic Steps

Category

Instruction Symbol

Table 2.39 Redundant System Instructions (For Redundant CPU)

8

-

11-2

Switches between the control system and
System
switching

SP.CONTSW

SP.CONTSW S D

standby system at the END processing of the
scan executed with the SP.CONTSW

2
4
4

instruction.

2
6
7
8

2.5 Application Instructions
2.5.22 Redundant system instructions (For Redundant CPU)

2-61

MEMO

2-62

3

CONFIGURATION
OF INSTRUCTIONS
3

3-1

3.1 Configuration of Instructions
Most CPU module instructions consist of an instruction part and a device part.
Each part is used for the following purpose:
• Instruction part ...... indicates the function of the instruction.
• Device part ............ indicates the data that is to be used with the instruction.
The device part is classified into source data, destination data, and number of devices.
(1) Source (S)
(a) Source is the data used for operations.
(b) The following source types are available, depending on the designated device:
• Constant ............................................... Designates a numeric value to be used in the
operation.
This is set when the program is created, and
cannot be changed during the execution of
the program.
Constants should be indexed when used as
variable data.
• Bit devices and word devices ............... Designates the device that stores the data to
be used in the operation.
Data must be stored in the designated
device until the operation is executed.
By changing the data stored in a designated
device during program execution, the data to
be used in the instruction can be changed.
(2) Destination (D)
(a) The destination stores the data after the operation has been conducted. However,
some instructions require storing the data to be used in an operation at the destination
prior to the operation execution.
Example An addition instruction involving BIN 16-bit data
+

S

D

+

Stores the data needed for operation
before the actual operation.

S1

S2

D

Stores only the
operation results.

(b) A device for the data storage must always be set to the destination.
(3) Number of devices and number of transfers (n)
(a) The number of devices and number of transfers designate the numbers of devices and
transfers used by instructions involving multiple devices.
Example Block transfer instruction
BMOV

S

D

n

Designates the number of transfers
used by a BMOV instruction

(b) The number of devices or number of transfers can be set between 0 and 32767.
However, if the number is 0, the instruction will be a no-operation instruction.

3-2

3.2 Designating Data
The following six types of data can be used with CPU module instructions.
Bit data ...................... Section 3.2.1

Data that can be handled by
CPU module

Numeric data

Integer data

Word data

Real number
(floating point) data

Character string data .... Section 3.2.5

3.2.1

.......................Section 3.2.2

Double-word data

...........Section 3.2.3

Single-precision
floating point data

.... Section 3.2.4 (1)

Double-precision
floating point data

.... Section 3.2.4 (2)

3
4
4

Using bit data

6

Bit data is data used in one-bit units, such as for contacts or coils.
"Bit devices" and "Bit designated word devices" can be used as bit data.

7

(1) When using bit devices
Bit devices are designated in one-point units.

8

Designation of 1 point
of bit device M0
M0
Y10

SET

3.2 Designating Data
3.2.1 Using bit data

Designation of 1 point
of bit device Y10

(2) Using word devices
(a) Word devices enable the use of a designated bit number 1/0 as bit data by the
designation of that bit number.
b15
Word device

to

b0

1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
Each bit of a word device can be
used (1=ON, 0=OFF)

(b) Word device bit designation is done by designating " Word device . Bit No. ".
(Designation of bit numbers is done in hexadecimal.)
For example, bit 5 (b5) of D0 is designated as D0.5, and bit 10 (b10) of D0 is designated
as D0.A. However, there can be no bit designation for timers (T), retentive timers (ST),
counters (C) or index register (Z). (Example Z0.0 is not available).
X0

D0.5

SET

D0.5

Bit designated for word device
(Bit 5 (b5) of D0 is turned ON if X0 is ON.)

Bit designated for word device
(Turns ON Y10 if bit 5 (b5) of D0 is ON (1).)
SET

Y10

3-3

3.2.2

Using word (16 bits) data

Word data is 16-bit numeric data used by basic instructions and application instructions.
The following two types of word data can be used with CPU module:
• Decimal constants................. K-32768 to K32767
• Hexadecimal constants ......... H0000 to HFFFF
Word devices and bit devices designated by digit can be used as word data.
For direct access input (DX) and direct access output (DY), word data cannot be designated by
digit. (For details of direct access input and direct access output, refer to the QnUCPU User's
Manual (Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's
Manual (Function Explanation, Program Fundamentals).
(1) When Using Bit Devices
(a) Bit devices can deal with word data when digits are designated.
Digit designation of bit devices is done by designating
" Number of digits Head number of bit device ". Digit designation of bit devices can
be done in
4-point (4-bit) units, and designation can be made for K1 to K4. (For link direct devices,
designation is done by "J Network No. \

Number of digits

Head number of bit device ".
When X100 to X10F are designated for Network No.2, it is done by J2\K4X100).For
example, if X0 is designated for digit designation, the following points would be
designated:
• K1X0 ......... The 4 points X0 to X3 are designated.
• K2X0 ......... The 8 points X0 to X7 are designated.
• K3X0 ......... The 12 points X0 to XB are designated.
• K4X0 ......... The 16 points X0 to XF are designated.

XF

to

XC XB

to

X8 X7

X4 X3

to

to

X0

K1 designation
range
(4 points)
K2 designation range
(8 points)
K3 designation range
(12 points)
K4 designation range
(16 points)

Fig 3.1 Digit Designation Setting Range for 16-Bit Instruction
(b) In cases where digit designation has been made at the source (S), the numeric values
shown in Table 3.1 are those which can be dealt with as source data.
Table 3.1 List of Numeric Values that Can Be Dealt with as Digit Designation
Number of Digits Designated

3-4

With 16-Bit Instruction

K1 (4 points)

0 to 15

K2 (8 points)

0 to 255

K3 (12 points)

0 to 4095

K4 (16 points)

-32768 to 32767

(c) When destination (D) data is a word device
The word device for the destination becomes 0 following the bit designated by digit
designation at the source.
Ladder Example

Processing

With 16-Bit Instruction

K1X0 X3 X2 X1 X0

X010
MOV K1X0

Filled with 0s

D0

3

b15
b4 b3 b2 b1 b0
D0 0 0 0 0 0 0 0 0 0 0 0 0 X3 X2 X1 X0

Source (S) data

Fig 3.2 Ladder Example and Processing Conducted
(d) In cases where digit designation is made at the destination (D), the number of points
designated are used as the destination.
Bit devices below the number of points designated as digits do not change.
Ladder Example

4
4

Processing

When source (S) data is a numerical value

1

3

2

4

6

H1234 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
X010
MOV H1234

K2M0
M15

Destination (D)

Not changed
When source (S) data is a word device

7

M8 M7
M0
0 0 1 1 0 1 0 0

K2M0

3

4

8

b15
b8 b7
b0
D0 1 1 1 0 1 0 1 0 1 0 0 1 1 1 0 1

X10
MOV D0

K2M100

M115

M108 M107
M100
1 0 0 1 1 1 0 1

3.2 Designating Data
3.2.2 Using word (16 bits) data

Destination (D)

K2M100

Not changed

Fig 3.3 Ladder Example and Processing Conducted
(2) Using word devices
Word devices are designated in 1-point (16 bits) units.
M0
MOV K100

D0

Designation of 1 point of word
device D0 (16 bits)

1. When digit designation processing is conducted, a random value can be used
for the bit device initial device number.
2. Digit designation cannot be made for the direct access I/O (DX, DY).

3-5

3.2.3

Using double word data (32 bits)

Double word data is 32-bit numerical data used by basic instructions and application instructions.
The two types of double word data that can be dealt with by CPU module are as follows:
• Decimal constants................. K-2147483648 to K2147483647
• Hexadecimal constants ......... H00000000 to HFFFFFFFF
Word devices and bit devices designated by digit designation can be used as double word data.
For direct access input (DX) and direct access output (DY), designation of double word data is
not possible by digit designation.
(1) When Using Bit Devices
(a) Digit designation can be used to enable a bit device to deal with double word data.
Digit designation of bit devices is done by designating
" Number of digits Head number of bit device ". For link direct devices, designation
is done by
Network No.
Head number of bit device ". When X100
"J
\ Number of digits
to X11F are designated for Network No.2, it is done by J2\K8X100. Digit designation of
bit devices can be done in 4-point (4-bit) units, and designation can be made for K1 to
K8. For example, if X0 is designated for digit designation, the following points would be
designated:
• K1X0 ...... The 4 points X0 to X3 are
• K5X0...... The 20 points X0 to X13 are
designated.
designated.
• K2X0 ...... The 8 points X0 to X7 are
• K6X0...... The 24 points X0 to X17 are
designated.
designated.
• K3X0 ...... The 12 points X0 to XB are
• K7X0...... The 28 points X0 to X1B are
designated.
designated.
• K4X0 ...... The 16 points X0 to XF are
• K8X0...... The 32 points X0 to X1F are
designated.
designated.
X1F

X1C X1B

X18 X17

X14 X13

X10 XF

XC XB

X8 X7

X4 X3

X0

K1
designation
range
(4 points)
K2 designation
range
(8 points)
K3 designation range
(12 points)
K4 designation range
(16 points)
K5 designation range
(20 points)
K6 designation range
(24 points)
K7 designation range
(28 points)
K8 designation range
(32 points)

Fig 3.4 Digit Designation Setting Range for 32-Bit Instructions
(b) In cases where digit designation has been made at the source (S) , the numeric values
shown in Table 3.2 are those which can be dealt with as source data.
Table 3.2 List of Numeric Values that Can Be Dealt with as Digit Designation
Number of Digits
Designated

3-6

With 32 Bit Instructions

Number of Digits
Designated

With 32 Bit Instructions

K1 (4 points)

0 to 15

K5 (20 points)

0 to 1048575

K2 (8 points)

0 to 255

K6 (24 points)

0 to 16777215

K3 (12 points)

0 to 4095

K7 (28 points)

K4 (16 points)

0 to 65535

K8 (32 points)

0 to 268435455
2147483648 to 2147483647

(c) When destination (D) data is a word device
The word device for the destination becomes 0 following the bit designated by digit
designation at the source.
Ladder Example

Processing

With 32 bit Instructions

K1X0 X3 X2 X1 X0
Filled with 0s

X10
DMOV K1X0

D0

Source (S) data

3

b15
b4 b3 b2 b1 b0
D0 0 0 0 0 0 0 0 0 0 0 0 0 X3 X2 X1 X0
D1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
b31
b16

4

Filled with 0s

Fig 3.5 Ladder Example and Processing Conducted
(d) In cases where digit designation is made at the destination (D), the number of points
designated are used as the destination. Bit devices below the number of points
designated as digits do not change.
Ladder Example

Processing

When source (S) data is a numerical value

H78123456
0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0
3

4

5

4
6
7

6

0 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0
X10
DMOV H78123456 K5M0
Destination (D)

8

7
8
1
2
K5M0
M15
M8 M7
M0
0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0
M31

M20 M19
M16
0 0 1 0
3.2 Designating Data
3.2.3 Using double word data (32 bits)

Not changed
When source (S) data is a word device

b15
b8 b7
b0
D0 1 1 1 0 0 1 0 0 0 1 0 1 1 1 0 1
b15
b8 b7
b0
D1 0 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1

X10

DMOV D0

K5M10

Destination (D)

M25
M18 M17
M10
1 1 1 0 0 1 0 0 0 1 0 1 1 1 0 1
M41

M30M29
M26
0 1 1 1
Not changed

Fig 3.6 Ladder Example and Processing Conducted

1. When digit designation processing is conducted, a random value can be used
for the bit device initial device number.
2. Digit designation cannot be made for the direct access I/O (DX, DY).

3-7

(2) Using word devices
A word device designates devices used by the lower 16 bits of data. A 32-bit instruction
uses (designation device number) and (designation device number + 1).
M0
DMOV K100

D0

Designation of 2 points of
word devices D0 and D1 (32 bits)
32-bit data transfer instruction

3.2.4

Using real number data

Real number data is floating decimal point data used with basic instructions and application
instructions.
Only word devices are capable of storing real number data.
(1) Single-precision floating-point data
Instructions which deal with single-precision floating-point data designate devices which are
used for the lower 16 bits of data.
Single-precision floating-point data are stored in the 32 bits which make up (designated
device number) and (designated device number + 1).
M0
EMOV R100

D0

Designation of 2 points of word devices D0 and D1
(32 bits)
Designation of 2 points of R100 and R101 (32 bits)
Single-precision floating-point data transfer instruction

Remark
In sequence programs, floating decimal point data are designated by E

.

Single-precision floating-point data uses two word devices and is expressed in
the following manner:
[Sign] 1. [Mantissa part] 2 [Exponent part]
The bit configuration and meaning of the internal representation of singleprecision floating-point data is as follows:

b31

b30

b31
Sign

to

b23

b22

to

b16

b15

b23 to b30
Exponent part

b0

to
b0 to b22
Mantissa part

• Sign The sign is represented at b31.
0: Positive
1: Negative
• Exponent part The n of 2n is represented from b23 to b30.
Depending on the BIN value of b23 to b30, the value of n is as follows:
b23 to b30
n

3-8

FFH

FEH

FDH

81

80

7FH

7EH

Not used 127

126

2

1

0

-1

02

01

00

-125 -126 Not used

• Variable part
The 23 bits from b0 to b22, represents the XXXXXX... at
binary 1.XXXXXX....
(2) Double-precision floating-point data
Instructions which deal with double-precision floating-point datadesignate devices which are
used for the lower 16 bits of data.
Double-precision floating-point data are stored in the 64 bits which make up (designated
device number) to (designated device number + 3).

3

M0
EDMOV R100

D0

Designation of 4 points of word devices D0, D1, D2
and D3 (64 bits)
Designation of 4 points of R100, R101, R102 and
R103 (64 bits)

4

Double-precision floating-point data transfer
instruction

4

Remark
In sequence programs, floating decimal point data are designated by E

6

.

Double-precision floating-point data uses four word devices and is expressed
in the following manner:
[Sign] 1. [Mantissa part] 2 [Exponent part]
The bit configuration and meaning of the internal representation of doubleprecision floating-point data is as follows:

b63
Sign

b62

to

b52

b51

b16

to

b15

b0

to

b52 to b62
Exponent part

8

b0 to 51
Mantissa part

• Sign The sign is represented at b63.
0: Positive
1: Negative
• Exponent part The n of 2n is represented from b52 to b62.
Depending on the BIN value of b52 to b62, the value of n is as follows:
b52 to b62
n

7FFH 7FEH 7FDH
Not used 1023 1022

400H 3FFH 3FEH 3FDH 3FCH
2

1

0

1

2

02H

01H

00H

1021

1022 Not used

• Variable part
The 52 bits from b0 to b51, represents the XXXXXX... at
binary 1.XXXXXX....

3-9

3.2 Designating Data
3.2.4 Using real number data

b63

7

1. The CPU module floating decimal point data can be monitored using the
monitoring function of a peripheral device.
2. When floating-point data is used to express 0, all data in the following range are
turned to 0.
(a) Single-precision floating-point data: b0 to b31
(b) Double-precision floating-point data: b0 to b63
3. The setting range of floating decimal point data is as follows. *1
(a) Single-precision floating-point data
2-126, 0, 2-126
2128 < Device data
(b) Double-precision floating-point data
21024 < Device data

2-1022,0,2-1022

Device data < 2128
Device data < 21024

4. Do not specify 0 in floating-point data (when only the most significant bit of
the floating-point real number is 1). (An operation error will occur if
floating-point operation is performed with 0.) The CPU module that performs
the internal operation of floating-point operation with double precision does not
result in operation error since it performs floating-point operation after
converting 0 into 0 in the CPU module when 0 is specified. The CPU
module that performs the internal operation of floating-point operation with
single precision results in operation error since it gives priority to the processing
speed and uses
specified.

0 in floating-point operation without conversion when

0 is

(a) The following CPU modules will not result in operation error when 0 is
specified.
• High Performance model QCPU where internal operation is set to
double precision *2
(The internal operation of floating-point operation defaults to double
precision.)
(b) The following CPU modules will result in operation error when -0 is
specified.
• Basic model QCPU *3
• High Performance model QCPU where internal operation is set to single
precision *2
• Process CPU
• Redundant CPU
• Universal model QCPU
*1: For operations when a real number is out of range and operations when an invalid value is input, refer to the
QnUCPU User's Manual (Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU
User's Manual (Function Explanation, Program Fundamentals).
*2: Switch between single precision and double precision of the internal operation of floating-point operation in
the PLC system of the PLC parameter dialog box. For the single precision and double precision of floatingpoint operation, refer to the QnUCPU User's Manual (Function Explanation, Program Fundamentals) or
Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals).
*3: The Basic model QCPU can perform floating-point operation if its first five digits of serial No. are "04122 or
later".

3-10

3.2.5

Using character string data

Character string data is character data used by basic instructions and application instructions.
The target ranges from the designated character to the NULL code (00H) that indicates the end
of the character string.
(1) When designated character is the NULL code

3

One word is used to store the NULL code.
M0
$MOV " "

4

D0

D0 NULL

4

Designation of NULL code (00H)
Character string data transfer instruction

6

(2) When character string is even
Uses (number of characters/2 + 1) words, and stores character string and NULL code.
For example, if "ABCD" is transferred to D0, the character string ABCD is stored at D0 and
D1, and the NULL code is stored at D2. (The NULL code is stored as the last one word.)

7

M0
$MOV "ABCD"

D0

8
D0

42H

41H

D1

44H

43H

NULL

Designation of a character string
composed of even numbers
Character string data transfer instruction

(3) When number of characters is odd
Uses (number of characters/2) words (rounds up decimal fractions) and stores the character
string and NULL code.
For example, if "ABCDE" is transferred to devices starting from D0, the character string
(ABCDE) and the NULL code are stored from D0 to D2. (The NULL code is stored into the
upper 8 bits of the last one word.)
M0
$MOV "ABCDE" D0

D0 42H

41H

D1 44H

43H

D2 NULL

45H

Designation of a character string
composed of odd numbers
Character string data transfer instruction

3-11

3.2 Designating Data
3.2.5 Using character string data

D2

3.3 Indexing
(1) Overview of indexing
(a) Indexing is an indirect setting made by using an index register.
When an Indexing is used in a sequence program, the device to be used will become
the device number specified directly plus the contents of the index register.
For example, if D2Z2 has been specified, the specified device is calculated as
follows: D(2+3) = D5 and the content of Z2 is 3 become the specified device.
(b) Indexing with 16-bit index registers and indexing with 32-bit index registers are possible
only for Universal model QCPU.
(2) Indexing with 16-bit index registers
(a) Example of indexing
Each index register can be set between 32768 and 32767.
Indexing is performed in the way shown below:
X0
MOV

K 1

Z0

Stores -1 at Z0.

MOV

D10Z0

D0

Stores the data of D10Z0=
D{10+(-1)} = D9 at D0.

X0

Indexing

(b) Devices to which indexing can be used
With the exception of the restrictions noted below, Indexing can be used with devices
used with contacts, coils, basic instructions, and application instructions.
1) Devices to which indexing can not be used
Device

Meaning

K, H

32-bit constant

E

Floating decimal point data

$

Character string data
.

FX, FY, FD

Bit designated for word device
Function devices

P

Pointers used as labels

I

Interrupt pointers used as labels

Z

Index register

S

Step relay

TR

SFC transfer devices*1

BL

SFC block devices*1

*1: SFC transfer devices and SFC block devices are devices for SFC use.
Refer to the manual below for how to use these devices.
• QCPU (Q mode)/QnACPU Programming Manual (SFC)

3-12

2) Devices with limits for use with index registers
Device

Meaning

Application Example

T

• Only Z0 and Z1 can be used for
timer contacts and coils.

C

• Only Z0 and Z1 can be used for
counter contacts and coils.

T0Z0

K100
T1Z1

C0Z1

K100
C1Z0

1
2
3

Remark
For timer and counter present values, there are no limits on index register
numbers used.

4

Value set for timer
X0

K100
T0

2
Present value of timer

SM400
BCD T0Z4

6

K4Y30
Value set for counter
K10
C100

X1

7

Present value of counter
SM400
BCD C100Z6

K2Y40

8

(c) A case where Indexing has been performed, and the actual process device, would be
as follows:
20 and Z1

5)

Ladder Example

3.3 Indexing

(When Z0

Actual Process Device

X0
MOV K20

Z0

MOV K 5

Z1

X1
MOV K2X64

K1M33

Description
K2X50Z0

Converts K20 into a hexadecimal number.
K1M38Z1
K1M(38 - 5) = K1M33

X1
MOV K2X50Z0 K1M38Z1
X0
MOV K20

Z0

MOV K 5

Z1

MOV D0Z0

K3Y12FZ1

K2X(50 + 14) = K2X64

X1
MOV D20

K3Y12A

Description

X1

D0Z0
K3Y12FZ1

D (0 + 20) = D20
K3Y(12F - 5) = K3Y12A
Hexadecimal number

Fig. 3.7 Ladder Example and Actual Process Device
(3) Indexing with 32-bit (only Universal model QCPU)
A method of specifing index registers in indexing with 32-bit can be selected from the
following two methods.
• Specifing the index registers’ range used for indexing with 32-bit.

3-13

• Specifing the 32-bit indexing using “ZZ” specification.

The 32-bit indexing with “ZZ” specification is available only for the following CPU
modules that the version of GX Developer is 8.68W or later.
• The first five digits of the serial No. for QnU(D)(H)CPU is “10042” or higher.
• QnUDE(H)CPU
(a) Example of specifing the range of index registers for use of 32-bit indexing.
1) Each index register can be set between -2147483648 and 2147483647.
An example of indexing is shown below.
X0
DMOV K40000

Z0

Stores 40000 at Z0.

ZR10Z0

D0

Stores the data of ZR10Z0=
ZR{10+40000}=ZR40010 at D0.

X0
MOV

Indexing

2) Specification method
For indexing with a 32-bit index register, specify the head number of an index
register to be used on the Device tab of the Q parameter setting screen on GX
Developer.

GX Developer 8.68R or earlier

GX Deveioper 8.68W or later

Fig. 3.8 Setting windows for ZR device indexing setting parameter

When the head number of the index register used is changed on the Device tab of
the Q parameter setting screen, do not change the parameters only or do not write
only the parameters into the programmable controller. Be sure to write the parameter into the programmable controller with the program.
When the parameter is forced to be written into the programmable controller, an
error of CAN'T EXE. PRG. occurs. (Error code: 2500)

3-14

3) Device that indexing can be used
Indexing can be used only for the device shown below.
Device

1

Meaning

ZR

Serial number access format file register

D

Extended data register (D)

W

Extended link register (W)

2

4) Usable range of index registers
The following table shows the usable range of index registers for indexing with
32-bit index registers.
For indexing with 32-bit index registers, the specified index register (Zn) and
the next index register of the specified register (Zn+1) are used. Be sure not to

3
4

overlap index registers to be used.
Setting Value

Index Registers to be Used

Setting Value

Index Registers to be Used

Z0

Z0, Z1

Z10

Z10, Z11

Z1

Z1, Z2

Z11

Z11, Z12

Z2

Z2, Z3

Z12

Z12, Z13

Z3

Z3, Z4

Z13

Z13, Z14

Z4

Z4, Z5

Z14

Z14, Z15

Z5

Z5, Z6

Z15

Z15, Z16

Z6

Z6, Z7

Z16

Z16, Z17

Z7

Z7, Z8

Z17

Z17, Z18

Z8

Z8, Z9

Z18

Z18, Z19

Z9

Z9, Z10

Z19

Cannot be specified

2
6
7
8

5) An example of indexing and the actual process device are as follows.
(When Z0 (32-bit)

100000 and Z2 (16-bit)

Actual Process Device

X0

X1

3.3 Indexing

Ladder Example

20)

DMOV K100000

Z0

MOV

K-20

Z2

MOV

ZR1000Z0 D30Z2

X1

MOV ZR101000 D10

Description
ZR1000Z0
D30Z2

ZR(1000+100000)=ZR101000
D(30-20)=D10

Fig. 3.9 Ladder Example and Actual Process Device

3-15

(b) Example of specifing 32-bit indexing with “ZZ” specification.
1) One index register can specify 32-bit indexing by using “ZZ” specification such
as “ZR0ZZ4”.
The 32-bit indexing with “ZZ” specification is as follows.
M0

M0

DMOVP

K100000

Z4

Stores 100000 at Z4 and Z5.

MOVP

K100

ZR0ZZ4

Indexing ZR device with 32-bit
index registers (Z4 and Z5)
ZR (0+100000) =ZR100000

2) Specification method
To perform 32-bit indexing by using “ZZ” specification, select “Use of ZZ” in
“Indexing Setting for ZR Device” in PC parameter for GX Developer.

Fig. 3.10 Setting window for indexing setting parameter for ZR device
3) Device that indexing can be used
The following device is available for indexing.
Device

Meaning

ZR

Serial number access format file register

D

Extended data register (D)

W

Extended link register (W)

4) Usable range of index registers
The following table shows the usable range of index registers in 32-bit indexing
used “ZZ” specification.
The 32-bit indexing with “ZZ” specification is specified as the format ZRmZZn.
Specifying ZRmZZn enables Zn and Zn+1 of 32-bit values to index the device
number, ZRm,
“ZZ”
specification

*1

Index Registers Used

specification*1

Index Registers Used

ZZ0

Z0, Z1

ZZ10

Z10, Z11

ZZ1

Z1, Z2

ZZ11

Z11, Z12

ZZ2

Z2, Z3

ZZ12

Z12, Z13

ZZ3

Z3, Z4

ZZ13

Z13, Z14

ZZ4

Z4, Z5

ZZ14

Z14, Z15

ZZ5

Z5, Z6

ZZ15

Z15, Z16

ZZ6

Z6, Z7

ZZ16

Z16, Z17

ZZ7

Z7, Z8

ZZ17

Z17, Z18

ZZ8

Z8, Z9

ZZ18

Z18, Z19

ZZ9

Z9, Z10

ZZ19

Not available

*1: refers to device name (ZR) for indexing target.

3-16

“ZZ”

5) The 32-bit indexing used “ZZ” specification and the acutual processing device
are as follows.
(Z0 (32-bit)

100000.Z2 (16-bit)

20)

Ladder Example

Actual Process Device

X1

X0

DMOV K100000 Z0

MOV

2

ZR101000 D10

3

END
MOV
X1

K-20

Z2
Description

MOV

ZR1000ZZ0

D30Z2

ZR1000ZZ0
D30Z2

4

ZR(1000+100000)=ZR101000
D(30-20)=D10

2

Fig.3.10 Ladder Example and Actual Process Device
6) Available functions for “ZZ” specification
The 32-bit indexing specification with “ZZ” specification applies in the following
functions in GX Developer.
No.

Function Name and Description

1

Specifing devices in program instruction

2

Monitoing device registrations

3

Testing devices execution type

4

Testing devices with conditions

5

Setting monitor conditions

1

6
7
8

Tracing sampling

6

(Trace point(specifing devices),

Single ZZn cannot be used as a device like “DMOV K100000 ZZ0”. When setting
values of index registers to specify 32-bit indexing with “ZZ” specification, set the
value of Zn (Z0~Z19).
Single ZZAn cannot be input to each function in GX Develoiper.

3-17

3.3 Indexing

Trace taget device)

(4) Index modification using extended data register (D) and extended link register (W)
(Universal model QCPU(except Q00UJCPU))
Like index modification using data register (D) and link register (W) of internal user device, a
device can be specified by index modification within the range of the extended data register
(D) and extended link register (W).
User Program

Index modification in internal
user device
Z0=0

Image of D device
D100

MOV K1234

Z0=1000
Z1=0

Internal user
device

D1100

D20000

Extended data
register

MOV K1234

Z1=2000

D22000

Index modification in
extended data register

1) Index modification where the device number crosses over the boundary
between the internal user device and the extended data register (D) or
extended link register (W)
The specification of index modification where the device number crosses over
the boundary between the internal user device and the extended data register
(D) or extended link register (W) cannot be made.
If doing so, an error occurs when the device range check is enabled at index
modification (error code: 4101).
User Program

Index modification in internal
user device
Z0=0

Image of D device
D100

MOV K1234

Z0=20000
Index modification where the device number
crosses over the boundary between
theinternal user device and the extended data
register is not possible.

3-18

D20100

Internal user
device

Extended data
register

2) Index modification where the device number crosses over the boundary
among the file register (ZR), extended data register (D), and extended link
register (W)
Index modification where the device number crosses over the boundary
among the file register (ZR), extended data register (D), and extended link
register (W) will not cause an error.
However, an error occurs if the index modification result of file register (ZR),
extended data register (D), and extended link register exceeds the file register
range (error code: 4101).
Index modification where the device
number crosses over the boundary
among the file register (ZR), extended
data register (D) will not cause an error.

Z1=0

ZR100

D14196
D20000

MOV K1234 Z20000Z1

Z1=4000

3

File register files

MOV K1234

Z0=10000

2

4

User Program
Z0=0

1

W2DC0

Index modification where the device number
crosses over the boundary among the
extended data register (D), and extended
link register (W) will not cause an error.

2

File
register
(8k)

6

Extended data
register (D)
(8k)
D12288~

7

Extended link
register (W)
(8k)
W2000~

8

3.3 Indexing

Extended link register exceeds
the file register range.
Z1=10000

3-19

(5) Other index modifications
(a) Bit data
Device numbers can be index modified when performing digit designation. However,
Indexing is not possible by digit designation.
BIN K4X0Z2

D0

BIN K4Z3X0

D0

Setting is possible since this indicates
Indexing for device number.
If Z2=3, then (X0+3)=X3

Setting is not possible since this indicates
Indexing by digit designation.

(b) Both I/O numbers and buffer memory number can be performed indexing with
intelligent function module devices*1.
MOV U10Z1\G0Z2 D0
If Z1=2 and Z2=8,
then U(10+2)\G(0+8)=U12\G8

(c) Both network numbers and device numbers can be performed indexing with link direct
devices*1.
MOV J1Z1\K4X0Z2 D0
If Z1=2 and Z2=8,
then J(1+2)\K4X(0+8)=J3\K4X8
*1: For the intellingent function module device, link direct devices, refer to the QnUCPU User’s Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User’s Manuall
(Function Explanation, Program Fundamentals)

(d) When indexing is used for multiple CPU shared devices*2, indexing for the head I/O
numbers of CPU modules and indexing for the CPU shared memory address are
automatically executed.
MOV U3E0Z1\G0Z2 D0
If Z1=2 and Z2=8,
then U3E(0+2)\G(0+8)=U3E2\G8
*2: For the multiple CPU shared device, refer to the QnUCPU User’s Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User’s Manuall
(Function Explanation, Program Fundamentals)

3-20

(e) Index modification using extended data register (D) and extended link register (W) by
32 bits (Universal model QCPU(except Q00UJCPU))
Like index modification using file register (ZR), index modification using extended data
register (D) and extended link register (W) by 32 bits can be performed by the following
two methods.

1
2

• Specifing the index registers’ range used for indexing with 32-bit.
• Specifing the 32-bit indexing using “ZZ” specification.

3
The 32-bit indexing with “ZZ” specification is available only for the following CPU
modules that the version of GX Developer is 8.68W or later.
• The first five digits of the serial No. for QnU(D)(H)CPU is “10042” or higher.
(except Q00UJCPU)
• QnUDE(H)CPU

4
2

(6) Cautions
(a) Performing indexing between the FOR and NEXT instructions
Pulses can be output between the FOR and NEXT instructions by use of the edge relay
(V). However, pulse output using the PLS/PLF/pulse (

P) instruction is not allowed.

[When edge relay is used]

[When edge relay is not used]

(M0Z1 provides normal pulse output.)

(M0Z1 does not provide normal pulse output.)

SM400

MOV

K0

Z1

FOR

K10

X0Z1 V0Z1
INC

Z1
NEXT

X0Z1
SM400

MOV

K0

Z1

FOR

K10

PLS

M0Z1

INC

Z1

7
8

3.3 Indexing

SM400

M0Z1

SM400

6

NEXT

Remark
The ON/OFF data of X0Z1 is stored by the edge relay V0Z1.
For example, the ON/OFF data of X0 is stored by V0, and that of X1 by V1.

3-21

(b) Performing indexing with the CALL instruction
Pulses can be output with the CALL instruction by use of the edge relay (V). However,
pulse output using the PLS/PLF/pulse (

P) instruction is not allowed.

[When edge relay is used]

[When edge relay is not used]

(M0Z1 provides normal pulse output.)

(M0Z1 does not provide normal pulse output.)

SM400

MOV

SM400

MOV

K0

Z1

CALL

P0

K1

Z1

CALL

P0

SM400

SM400

MOV

MOV

K0

Z1

CALL

P0

K1

Z1

CALL

P0

FEND

FEND

P0

X0Z1 V0Z1

M0Z1

P0

X0Z1

RET

PLS

M0Z1

RET

(c) Device range check during indexing
1) CPUs other than Universal model QCPU
Device range checks are not conducted during indexing.
Therefore, when the data after index modification exceed the user specified
device range, the data is written to another device without causing an
error.(Note, however, that when the data after index modification is written to
the device for system use exceeding the user specified device range, an error
occurs. (Error code: 1103))
Take extra precaution when using indexing in programming.
2) Universal model QCPU
The device range is checked for indexing.
With changing the settings of the PLC parameter on GX Developer, the device
range is not checked.
(d) Changing indexing with 16-bit index register for indexing with 32-bit index register
For changing indexing with 16-bit index register for indexing with 32-bit index register,
check if the program has enough spaces for indexing.
For indexing with 32-bit index registers, the specified index register (Zn) and the next
index register of the specified register (Zn+1) are used. Be sure not to overlap index
registers to be used.

3-22

3.4 Indirect Specification
1
(1) Indirect Specification
(a) Indirect specification is a method that specifies address of the device to be used in a
sequence program using two word devices (two points of word device). Use indirect
specification as index modification when the index register is insufficient.
ADRSET D100

D0

MOV

K50

Z0

DMOV

K50

W0

DMOV

K10000

D150

DMOV

K10000

D150

DMOV

D100Z0

D110

W0

D10

D+ D0

Specification of
D (100 + 50) = D150

MOV

@D10

Stores the address of
D100 to D0.

(Address of D100) + 50 =
(Address of D150)

3
4

D110

Specification of
address of D150
[When index resister is used]

2

2

[When indirect specification is used]

(b) Specify the device to be used for specifying the address as "@ + (word device
number)". For example, when @D100 is specified, the device address will be the
contents of D101 and D100.

6

(c) The address of the device specified indirectly can be confirmed with the ADRSET
instruction.
For the ADRSET instruction, refer to Section 7.18.6.

7

(2) Indirect specification available devices

8

Table 3.3 shows that the CPU module devices can be specified indirectly.
Table 3.3 List of Indirect Specification Available Devices
Availability of
Device Type

Indirect

Example of Indirect Specification
3.4 Indirect Specification

Specification
Bit device *1
Internal user device

Word device *1
Bit device *1

Link direct device

Word device *1

Intelligent function module device

N/A
Available

––––––––––

• @D100
• @D100Z2 *2

N/A

––––––––––

Available*3

• @J1\W10
• @J1Z1\W10Z2 *2

Available*3

• @U10\G0
• @U10Z1\G0Z2 *2

N/A

Index register
File register
Extended data register (D)
Extended link register (W)

––––––––––

Available

• @R0, @ZR20000
• @R0Z1,@ZR20000Z1 *2

Available

• @D1000
• @W1000

Nesting

––––––––––

Pointer

––––––––––

Constants

––––––––––

SFC block device
SFC transition device
Other

Network No. specification
device

N/A
––––––––––

I/O No. specification device

*1: For the device names, refer to the QnUCPU User’s Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User’s Manuall
(Function Explanation, Program Fundamentals)
*2: Indicates when index modification by an index register is performed.
*3: Indirect specification is possible, but the address can not be written with the ADRSET instruction.

3-23

(3) Precautions
(a) The address for indirect specification uses two words.Therefore, to substitute indirect
specification for index modification, the addition/subtraction of 32-bit data is required.
The following is the ladder used for the address addition/subtraction of the device
stored in D1 and D0 for indirect specification.
[To add "1" to the address of the device for indirect specification]
DINCP

D0
Device used for indirect specification
32-bit instruction

[To subtract "1" from the address of the device for indirect specification]
DDECP

D0
Device used for indirect specification
32-bit instruction

(b) Indirect specification of extended data register (D) and extended link register (W)
Indirect specification with indirect address can be performed in the extended data
register (D) and extended link register (W).
Note that when indirect specification is performed to the extended data register (D) and
data register (D) in internal device or to the extended link register (W) and link register
(W) in internal device, the areas of the internal user device and extended data register
(D) or extended link register (W) are not treated as a sequence.
Internal user device

ADRSET D12000 D100

D+

K1000 D100

MOV

D102

Setting an address
"D12000 h to D100 and D101
Setting the address that
is an addition of 1000 to
the address of D12000 to
D102 and D103

D0

Data register

D12000
D12287

K1234 @D102

File register files
File register
D12288
D13000
Since the areas of the data register and
extended data register are not sequence,
D13000 is inaccessible.

3-24

D63487

Extended data
register(D)

Extended link
register (W)

3.5 Reducing Instruction Processing Time
1

3.5.1

Subset Processing

2

Subset processing is used to place limits on bit devices used by basic instructions and
application instructions in order to increase processing speed.

3

However, the instruction symbol does not change.
To shorten scans, run instructions under the conditions indicated below.

4

(1) Conditions which each device must meet for subset processing
(a) When using word data
Device

Condition

2

• Designates a bit device number in a factor of 16.
• Only K4 can be designated for digit designation.
• Does not perform indexing.

Bit device

6

• Internal user device.
• File register (R, ZR *1)

Word device

• Multiple CPU shared device *1, *2
• Index register (Z) / Standard device register (Z) *1

Constants

7

• No limitations

8

(b) When using double word data
Device

Condition
• Designates a bit device number in a factor of 16.
• Only K8 can be designated for digit designation.
• Does not perform indexing.

Bit device

3.5 Reducing Instruction Processing Time
3.5.1 Subset Processing

• Internal user device.
• File register (R, ZR *1)

Word device

• Multiple CPU shared device *1, *2
• Index register (Z) / Standard device register (Z) *1

Constants

• No limitations

(c) When using bit data
Device
Bit device

Condition
• Internal user device (indexing possible)
• Bit specification of internal user device

Word device

• Bit specification of file register (R, ZR *1)
• Bit specification of multiple CPU shared device *1, *2

*1: Only for Universal model QCPU
*2: Valid only for the multiple CPU high speed transmission area (from U3En\G10000)
(Excluding the case that indexing is executed for the head I/O number of the CPU module (U3En\G10000))

3-25

(2) Instructions for which subset processing can be used
Types of Instructions

Instruction Symbols
LD,LDI,AND,ANI,OR,ORI,LDP,LDF,ANDP,ANDF,ORP,ORF,LDPI,ANDPI,ANDFI,

Contact instructions

ORPI,ORFI

Output instructions

OUT,SET,RST

Comparison operation instruction

•
• +,

Arithmetic operation

,

,

,

,

,

,D

,*,/,INC,DEC,D+,D

• B+,B

,B*,B/, E+,E

,D

,D

,D

,D

,D

,D*,D/,DINC,DDEC

,E*,E/

Data conversion instructions

• BCD, BIN, DBCD, DBIN, FLT, DFLT, INT, DINT

Data transfer instruction

• MOV, DMOV, CML, DCML, XCH, DXCH
• FMOV, BMOV, EMOV

Program branch instruction

• CJ, SCJ, JMP

Logic operations

• WAND, DAND, WOR, DOR, WXOR, DXOR, WXNR, DXNR

Rotation instruction

• RCL, DRCL, RCR, DRCR, ROL, DROL, ROR, DROR

Shift instruction

• SFL, DSFL, SFR, DSFR

Data processing instructions

• SUM, SEG

Structure creation instructions

• FOR, CALL

3.5.2

Operation processing with standard device registers (Z) (only
Universal model QCPU)

Operation processing time can be reduced with standard device registers (Z).
The following shows an example program with standard device registers.

+ D0 D10 D20

+ Z0 Z1 Z2

Using data registers takes three steps and
the operation processing time of 28.5 ns.
(With Q4/Q06/Q10/Q13/Q20/Q26UD(E)HCPU)
Using standard device registers instead of
data registers takes one step and the
operation processing time of 9.5 ns.
(With Q4/Q06/Q10/Q13/Q20/Q26UD(E)HCPU)

Operation processing time is reduced with the instructions that the subset processing is possible.
For the number of steps, refer to Section 3.8.
For the operation time for each instruction, refer to Appendix 1.

Because standard device registers are the same devices as index registers, do
not use device numbers of the standard device registers for the index registers.

3-26

3.6 Cautions on Programming (Operation Errors)
1

Operation errors are returned in the following cases when executing basic instructions and
application instructions with CPU module:
• An error listed on the explanatory page for the individual instruction occurred.
• When an intelligent function module device is used, no intelligent function module is installed
at the specified I/O number position.
• When an intelligent function module device is used, the specified buffer memory address does not exist.
• The relevant network does not exist when using a link device.
• When a link device is used, no network module is installed at the specified I/O number position.
• When a multiple CPU shared device is used, a CPU module is not installed at the head I/O
number position of the specified CPU module.
• When a multiple CPU shared device is used, the specified shared memory address does not exist.
• The setting of the device number crosses over the boundary between the internal user device
and the extended data register (D) or extended link register (W).
(Universal model QCPU only)

2
3
4
2
6

When file register is set but a memory card is not installed or when file register is
not set, writing/reading to/from file register is as follows:
(1) For the High Performance model QCPU, Process CPU, and Redundant CPU
An error does not occur even when writing/reading to/from file register is
performed. However, “0H” is stored when reading from file register is
performed.
(2) For the Universal model QCPU
The OPERATION ERROR (error code:4101) occurs when writing/reading to/
from file register is performed.

Device range checks for the devices used by basic instructions and application instructions
in CPU module are as indicated below:
(a) Instructions for specified each device, including MOV and DMOV
1) CPUs other than Universal model QCPU
The device range is not checked. In cases where the corresponding device
range is exceeded, data is written to other devices. *1
For example, in a case where the data register has been allocated 12k points,
there will be no error even if it exceeds D12287.
DMOV

K100 D12287
This designates D12287 and D12288 as the
target devices for executing the DMOV instruction.
However, since D12288 does not exist,
data in another device is corrupted.

Device range checks are not conducted also in cases where indexing is being
performed.
In cases where the corresponding device range is exceeded as the result of
performing indexing, data is written to other devices.*1
*1:

For the assignment order of internal user devices, refer to this Section (c) Character string data.

3-27

8

3.6 Cautions on Programming (Operation Errors)

(1) Device range check

7

2) Universal model QCPU
The device range is checked. When the device number is outside the device
range, an operation error occurs.
For example, when12 k points are assigned to a data register, an error occurs
if the device number of the data register exceeds D12287.
DMOV K100

D12287
When D12287 is specified with the DMOV instruction,
the target devices are D12287 and D12288.
However, an operation error occurs because D12288
does not exist.

The device range is checked even though indexing is executed.
With changing the settings of the PLC parameter on GX Developer, the device
range is not checked.*2
*2:

For changing the settings of the PLC parameter on GX Developer, refer to the following manual.
• QCPU User's Manual (Function Explanation, Program Fundamentals)

(b) Instructions for a block of devices, including BMOV and FMOV
1) CPUs other than Universal model QCPU
The device range is checked.
When the device number is outside the device range, an operation error
occurs.
For example, when 12 k points are assigned to a data register, an error occurs
if the device number of the data register exceeds D12287.
BMOV D0

D12287 K2
This designates D12287 and D12288 as the
target devices for executing the BMOV instruction.
However, since D12288 does not exist,
an operation error occurs.

Device range checks are also conducted when indexing is performed.
However, if indexing has been conducted, there will be no error returned if the initial device
number exceeds the relevant device range.
MOV

BMOV D0

BMOV D0

K2

Z1

D12285Z1 K2

D12287Z1 K2

When D12287 is specified with the BMOV instruction,
the target devices are D12287 and D12288.
However, an operation error occurs because D12288
does not exist.

An operation error occurs since head device number
is D12289 that exceeds the device range.

3-28

2) Universal model QCPU
The device range is checked.
When the device number is outside the device range, an operation error
occurs.
For example, when12 k points are assigned to a data register, an error occurs
if the device number of the data register exceeds D12287.

1
2

BMOV D0 D12287 K2
When D12287 is specified with the BMOV instruction,
the target devices are D12287 and D12288.
However, an operation error occurs because D12288
does not exist.

The device range is checked even though indexing is executed.
An error occurs when the head device number of the devices with indexing
exceeds the device range.
MOV

BMOV D0

BMOV D0

K2

3
4
2

Z1

6

D12285Z1 K2

D12287Z1 K2

When D12287 is specified with the BMOV instruction,
the target devices are D12287 and D12288.
However, an operation error occurs because D12288
does not exist.

An operation error occurs since head device number
is D12289 that exceeds the device range.

7
8

With changing the settings of the PLC parameter on GX Developer, the device
range is not checked.*2
For changing the settings of the PLC parameter on GX Developer, refer to the following manual.
• QCPU User's Manual (Function Explanation, Program Fundamentals)

(c) Character string data
Because all character string data is of variable length, device range checks are
performed.
In cases where the corresponding device range has been exceeded, an operation error
will be returned.
For example, in a case where the data register has been allocated 12k points, there will
be an error if it exceeds D12287.
$MOV

"ABC" D12287
This designates D12287 and D12288 as the
target devices for executing the $MOV instruction.
However, since D12288 does not exist,
an operation error occurs.

However, with CPUs other than Universal model QCPU, when indexing is executed and
the head device number is outside the device range, no error occurs and the other
devices are accessed.

3-29

3.6 Cautions on Programming (Operation Errors)

*2:

When performing the following access in Universal model QCPU, an error (error code:
4101) occurs.
1) Access crossing the boundary of devices caused by indexing
(range of A area)
The allocation order of individual devices is shown below:
SM
SD
X
Y
M
L
B
F
SB
V

Area A

S
Contact and coil of T
Contact and coil of ST
Contact and coil of C
Present value of T
Present value of ST
Present value of C
D
W
SW
Empty area
File register
(32K points)

Boundary B

2) Access crossing the boundary of file registers caused by indexing
3) Access to file registers (R, ZR) without setting file register files
4) Access to file registers (R, ZR) exceeded the range of file register files
Presetting PC parameter not to check indexing device range enables the Universal
model QCPU not to detect an error in the above accesses from 1) to 4).
Detecting an error in the above accesses from 1) to 4) , however, depends on the serial
No. of Universal model QCPU.*2
Setting device range in indexing
Set
Not set
*2:

First 5 digits of serial No. for Universal model QCPU
Serial No.”10021” or lower

Serial No.”10022” or higer

Detected errors in accesses 1) to 4)
Detected errors in accesses 2) to 4)

Not detected

For changing the settings of the PLC parameter on GX Developer, refer to the QnUCPU User's Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's Manual (Function
Explanation, Program Fundamentals).

When indexing is executed only with Universal model QCPU, devices between
internal user devices (SW) and file registers (R) cannot be skipped. (Error code:
4101).

3-30

Remark
For the how to change the internal user device allocation, referto User’s Manual
(Functions Explanation, Program Fundamentals) for the CPU module used.

1
2

(d) Device range checks are conducted when indexing is performed by direct access
output (DY).
(e) Set the following items so that the specification does not cross over theboundary
between the internal user device and the extended data register (D) or extended link
register (W).
• Index modification
• Indirect specification

User Program

6
Image of D device
D100

FMOV K0 D100 K200

Internal user
device

D199
FMOV K0 D12200 K200

FMOV K0 D20000 K200

4
2

• Specification for the instructions which target data block*1
Data biock where the device number
crosses over the boundary between the
internal user device and the extended data
register (D) is not possible.

3

7
8

D12200

D12299
D20100

D20299
*1 Data block indicates the following data.
• Data used in the instructions, such as FMOV, BMOV, BK+, which multiple words are targeted for
operation
• Control data, composed of two or more words, specified in the instructions, such as SP.FWRITE,
SP.FREAD
• Data whose data type is 32-bit or more (BIN 32-bit, real number, indirect address of the device)

3-31

3.6 Cautions on Programming (Operation Errors)

Extended data
register (D)

(2) Device data check
Device data checks for the devices used by basic instructions and application instructions in
CPU module are as indicated below:
(a) When using BIN data
No error is returned even if the operation results in overflow or underflow. The carry flag
does not go on at such times, either.
(b) When using BCD data
1) Each digit is check for BCD value (0 to 9). An operation error is returned if individual
digits are outside the 0 to 9 (A to F) range.
2) No error is returned even if the operation results in overflow or underflow. The carry
flag does not go on at such times, either.
(c) When using floating-point data
1) An operation error occurs when the following operation results are returned with the
single-precision floating-point operation instruction.
When the absolute value of the floating decimal point data is 1.0

2-127 or lower

When absolute value of floating decimal point data is 1.0 2128 or higher
2) An operation error occurs when the following operation results are returned with the
double-precision floating-point operation instruction.
When the absolute value of the floating decimal point data is 1.0
When absolute value of floating decimal point data is 1.0

2-1023 or lower

21024 or higher

(d) Using character string data
No data check is conducted.
(3) Buffer memory access
For accessing buffer memories, using instructions with intelligent function module devices
(from Un\G0) is recommended.
(4) Multiple CPU shared memory access
For accessing multiple CPU shared memories, using instructions with multiple CPU shared
devices (from U3En\G10000) is recommended.

3-32

3.7 Conditions for Execution of Instructions
1
The following four types of execution conditions exist for the execution of CPU module sequence
instructions, basic instructions, and application instructions:
• Non-conditional execution...... Instructions executed without regard to the ON/OFF status of
the device
Example

LD X0, OUT Y10
• Executed at ON...................... Instructions executed while input condition is ON

2
3

Example

MOV instruction, FROM instruction
• Executed at leading edge ...... Instructions executed only at the leading edge of the input
condition (when it goes from OFF to ON) Example
PLS instruction, MOVP instruction.
• Executed at trailing edge ....... Instructions executed only at the trailing edge of the input
condition (when it goes from ON to OFF) Example
PLF instruction.

4
2
6

For coil or equivalent basic instructions or application instructions, where the same instruction
can be designated for either execution at ON or leading edge execution, a "P" is added after the
instruction name to specify the condition for execution.

7

• Instruction to be executed at ON Instruction name

8

• Instruction to be executed at leading edge Instruction name + P

Execution at ON and execution at leading edge for the MOV instruction are designated as
follows:
K4X0

3.7 Conditions for Execution of Instructions

MOV

D0
Execution during ON

MOVP

K4X0

D0
Execution at leading edge

3-33

3.8 Counting Step Number
The number of steps in CPU module sequence instructions, basic instructions, and application
instructions differs depending on whether indirect setting of the device used is possible or not.
(1) Counting the number of basic steps
The basic number of steps for basic instructions and application instructions is calculated by
adding the device number and 1.
For example, the "+ instruction" would be calculated as follows:
+

+

D0

D10

(1)

(2)

D0

D10

D20

(1)

(2)

(3)

Number of devices 2

Number of basic steps: 3

Number of devices 3

Number of basic steps: 4

(2) Conditions for increasing the number of steps
The number of steps is increased over the number of basic steps in cases where a device is
used that is designated indirectly or for which the number of steps is increased.
(a) When device is designated indirectly
In cases where indirect designation is done by @ , the number of steps is increased 1
step over the number of basic steps.
For example, when a 3-step MOV instruction is designated indirectly (example: MOV
K4X0 @D0), one step is added and the instruction becomes 4 steps.
(b) Devices with additional steps (Except Universal model QCPU)
Devices with Additional Steps

Added Steps

Example
MOV U4\G10 D0

Intelligent function module device

MOV U3E1\G0 D0

Multiple CPU shared device

MOV J3\B20 D0

Link direct device

1

Index register

MOV Z0 D0

Serial number access format file register

MOV ZR123 D0

32-bit constant

DMOV K123 D0

Real constant

EMOV E0.1 D0
For even numbers: (number of characters) / 2

Character string constant

For odd numbers:
(number of characters + 1) / 2

3-34

$MOV "123" D0

(c) Devices with additional steps (Universal model QCPU(except Q00UJCPU))
1) Instructions applicable to subset processing

1

The following table shows steps depending on the devices.
Added Steps
Instruction Symbols

Devices with Additional Steps

(Number of

Basic Number of
Steps

2

1(2)

1

3

1(4)

3

1(5)

4

Instruction Steps)
Serial number access format file register,
LD,LDI,AND,ANI,OR,ORI,

Extended data register (D),

LDP,LDF,ANDP,ANDF,ORP,ORF

Extended link register (W)
Multiple CPU shared device
Serial number access format file register,

LDPI,LDFI

Extended data register (D),
Extended link register (W)

4

Multiple CPU shared device
Serial number access format file register,
ANDPI,ANDFI,ORPI,ORFI

2

Extended data register (D),
Extended link register (W)
Multiple CPU shared device

6

Serial number access format file register
SET

Extended data register (D),

1(2)

Extended link register (W)

1

7

Multiple CPU shared device
Timer/Counter

3(4)

Serial number access format file register
OUT

Extended data register (D),

8

1

1(2)

Extended link register (W)
Multiple CPU shared device
Serial number access format file register
Extended data register (D),

1(2)

Extended link register (W)

1

3.8 Counting Step Number

RST (bit device)

Multiple CPU shared device
Timer/Counter

2(4)

(Bit/word device)
RST (word device)

Serial number access format file register
Extended data register (D),

2

1(3)

Extended link register (W)
Multiple CPU shared device
Standard device register *
LD=,LD<>,LD<,LD<=,LD>,LD>=,
AND=,AND<>,AND<,AND<=,AND>,AND>=,
OR=,OR<>,OR<.OR<=,OR>,OR>=

1(3)

2

-1

Serial number access format file register
Extended data register (D),

3

1

Extended link register (W)
Multiple CPU shared device
Standard device register *2

LDD=,LDD<>,LDD<,LDD<=,LDD>,LDD>=,
ANDD=,ANDD<>,ANDD<,ANDD<=,ANDD>,
AND>=,ORD=,ORD<>,ORD<.ORD<=,
ORD>,ORD>=

-1

Serial number access format file register
Extended data register (D),
Extended link register (W)

3

1

Multiple CPU shared device
Decimal constant, hexadecimal
constant, real constant
Standard device register *2

+,-,+P,-P,WAND,WOR,WXOR,WXNR,
WANDP,WORP,WXORP,WXNRP
(2 devices)

D

:-1

Serial number access format file register
Extended data register (D),
Extended link register (W)

S1

: 1,

D

:3

3

Multiple CPU shared device

3-35

Added Steps
Instruction Symbols

Devices with Additional Steps

(Number of
Instruction Steps)

Standard device register *2

D

Basic Number of
Steps

:-1

Serial number access format file register
D+,D-,D+P,D-P,DAND,DOR,DXOR,DXNR,

Extended data register (D),

DANDP,DORP,DXORP,DXNRP

Extended link register (W)

(2 devices)

S1

:1,

D

S1

:1

constant, real constant

WANDP,WORP,WXORP,WXNRP
(3 devices)*1

3

Multiple CPU shared device
Decimal constant, hexadecimal

+,-,+P,-P,WAND,WOR,WXOR,WXNR,

:3

Serial number access format file register
Extended data register (D),
Extended link register (W)

S1

, S2 :1,

D

:2

S1

, S2 :1,

D

:2

3

Multiple CPU shared device
Serial number access format file register

D+,D-,D+P,D-P,DAND,DOR,DXOR,DXNR,
DANDP,DORP,DXORP,DXNRP
(3

devices)*1

Extended data register (D),
Extended link register (W)

3

Multiple CPU shared device
Decimal constant, hexadecimal
S1

constant, real constant

, S2 :1

Serial number access format file register
*, *P, /, /P

Extended data register (D),
Extended link register (W)

S1

, S2 :1,

D

:2

S1

, S2 :1,

D

:2

3

Multiple CPU shared device
Serial number access format file register
Extended data register (D),
D*, D*P, D/, D/P, E*, E*P

Extended link register (W)

3

Multiple CPU shared device
Decimal constant, hexadecimal
constant, real constant

3-36

S1

, S2 :1

Added Steps
Instruction Symbols

Devices with Additional Steps

(Number of

Basic Number of

Instruction Steps)

INC,INCP,DEC,DECP,DINC,DINCP,
DDEC,DDECP

Index register/Standard device register *2
Serial number access format file register

1

2

2

-1

Extended data register (D),

3

Extended link register (W)
Multiple CPU shared device
Serial number access format file register
Extended data register (D),

MOV,MOVP

Steps

1

Extended link register (W)
Multiple CPU shared device
Serial number access format file register

3

2

4

Extended data register (D),
Extended link register (W)
Multiple CPU shared device
Decimal constant, hexadecimal

DMOV,DMOVP,EMOV,EMOVP

1

2

2

constant, real constant
Serial number access format file register
BCD,BCDP,BIN,BINP,FLT,FLTP,CML,CMLP

Extended data register (D),
Extended link register (W)
Multiple CPU shared device
Serial number access format file register
Extended data register (D),

DBCD,DBCDP,DBIN,DBINP,INT,INTP,DINT,
DINTP,DFLT,DFLTP,DCML,DCMLP

Extended link register (W)
Multiple CPU shared device
Decimal constant, hexadecimal

:1, S2 :2

S1

:1, S2 :2

2

6
7

2
S1

constant, real constant
*1:
*2:

S1

:1

8

If the same device is used for S1 and S2 , the number of basic steps increases by one.
The number of steps decreases with a standard device register.

Instruction Symbols

Locations Where Standard Device Register Is Used

LD=,LD<>,LD<,LD<=,LD>,LD>=,
AND=,AND<>,AND<,AND<=,AND>,AND>=,
OR=,OR<>,OR<.OR<=,OR>,OR>=
LDD=,LDD<>,LDD<,LDD<=,LDD>,LDD>=,
ANDD=,ANDD<>,ANDD<,ANDD<=,ANDD>,
AND>=,ORD=,ORD<>,ORD<.ORD<=,
ORD>,ORD>=
+,-,+P,-P,D+,D-,D+P,D-P,
WAND,WOR,WXOR,WXNR,
DAND,DOR,DXOR,DXNR,
WANDP,WORP,WXORP,WXNRP,
DANDP,DORP,DXORP,DXNRP
(2 devices)
S1
S1

+,-,+P,-P,D+,D-,D+P,D-P,
WAND,WOR,WXOR,WXNR,
DAND,DOR,DXOR,DXNR,
WANDP,WORP,WXORP,WXNRP,
DANDP,DORP,DXORP,DXNRP

Instruction Steps)

-2(1)

3

S1

and

D

-2(1)

3

,

S2

, or

, and

S2

and

and

-2(1)

D

-1(2)

D

S2

(only when that device that the
specified for
and

D

D

3

)

file register is specified for
and

±0(3)

S2

(only when a serial number access format

S1

Steps

S2

number of steps does not increase is

If the same device is used for

Basic Number of

and

S1

*1:

(Number of

S1

S1

(3 devices)*1

Added Steps

D

+2(5)

)

, the number of basic steps increases by one.

3-37

3.8 Counting Step Number

When multiple standard device registers are used in an instruction applicable
to subset processing, the number of steps decreases. The following table
shows the number of steps for each instruction.

Added Steps

Locations Where Standard Device Regis-

Instruction Symbols

ter Is Used
S1

*, *P, /, /P
S1

S2

, or

S1
S1

,

,

S1

S2

S2

, or

, and

S2

Instruction Steps)

3
-1(2)

D

-2(1)

D

and

and

-1(2)

D

S2

(only when that device that the
D*, D*P, D/, D/P, E*, E*P

number of steps does not increase is
specified for
S1

and

D

±0(3)

3

)

S2

(only when a serial number access format
file register is specified for
MOV,MOVP,DMOV,DMOVP,EMOV,EMOVP

Steps

-2(1)

D

and

, and

Basic Number of

(Number of

D

+2(5)

)

S1

and

D

-1(1)

2

S1

and

D

-1(1)

2

BCD,BCDP,BIN,BINP,DBCD,DBCDP,
DBIN,DBINP,FLT,FLTP,DFLT,DFLTP,
INT,INTP,DINT,DINTP,CML,CMLP,
DCML,DCMLP

2) Except Instructions applicable to subset processing
The following table shows steps depending on the devices.
Devices with Additional Steps

Added Steps

Example
MOV U4\G10 D0

Intelligent function module device

MOV U3E1\G10000 D0

Multiple CPU shared device

MOV J3\B20 D0

Link direct device

MOV Z0 D0

Index register / standard device register

1

Serial number access format file register

MOV ZR123 D0

Extended data register(D)

MOV D123

Extended link register(W)

MOV W123

32-bit constant

DMOV K123 D0

Real constant

EMOV E0.1 D0
For even number: (number of characters) / 2

Character string constant

For odd numbers: (number of characters + 1) / 2

$MOV "123" D0

(d) In cases where the conditions described in (a) to (c) above overlap, the number of steps
becomes a culmination of the two.
Example MOV If U1\G10 ZR123 has been designated, a total of 2 steps are added.
MOV

U1\
G10

ZR123

Serial number access format file registers

=

Intelligent function module devices

: 1 step
+
: 1 step
Increased by 2 steps

3-38

3.9 Operation when the OUT, SET/RST, or PLS/PLF
Instructions Use the Same Device

1

The following describes the operation for executing multiple instructions of the OUT, SET/RST, or
PLS/PLF that use the same device in one scan.

2
3

(1) OUT instructions using the same device
Do not program more than one OUT instruction using the same device in one scan. If the
OUT instructions using the same device are programmed in one scan, the specified device
will turn ON or OFF every time the OUT instruction is executed, depending on the operation
result of the program up to the relevant OUT instruction. Since turning ON or OFF of the
device is determined when each OUT instruction is executed, the device may turn ON and
OFF repeatedly during one scan. The following diagram shows an example of a ladder that
turns the same internal relay (M0) with inputs X0 and X1 ON and OFF.
[Ladder]

4
2
6

X0
M0

7

X1
M0

8
[Timing Chart]
X0

X0

M0

X1

X1
M0

M0

END

END

END

ON
X0

OFF
ON

X1

OFF
ON

M0

OFF

M0 turns OFF because X1 is OFF.
M0 turns ON because X0 is ON.

M0 turns ON because X1 is ON.

M0 remains OFF because X0 is OFF.

With the refresh type CPU module, when the output (Y) is specified by the OUT instruction,
the ON/OFF status of the last OUT instruction of the scan will be output.

3-39

3.9 Operation when the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device

M0

(2) SET/RST instructions using the same device
(a) The SET instruction turns ON the specified device when the execution command is ON
and performs nothing when the execution command is OFF.
For this reason, when the SET instructions using the same device are executed two or
more times in one scan, the specified device will be ON if any one of the execution
commands is ON.
(b) The RST instruction turns OFF the specified device when the execution command is
ON and performs nothing when the execution command is OFF.
For this reason, when the RST instructions using the same device are executed two or
more times in one scan, the specified device will be OFF if any one of the execution
commands is ON.
(c) When the SET instruction and RST instruction using the same device are programmed
in one scan, the SET instruction turns ON the specified device when the SET execution
command is ON and the RST instruction turns OFF the specified device when the RST
execution command is ON.
When both the SET and RST execution commands are OFF, the ON/OFF status of the
specified device will not be changed.
[Ladder]
X0
SET M0

X1
RST M0

[Timing Chart]
X0

X0
SET M0
X1
RST M0
END

END

SET M0
X1
RST M0
END

ON
X0

OFF

X1

OFF

M0

OFF

ON

ON

RST M0 is not executed
because X0 is OFF.
(M0 remains ON.)
M0 turns ON because X0 is ON.

M0 turns OFF because X1 is ON.
SET M0 is not executed
because X0 is OFF.
(M0 remains ON.)

When using a refresh type CPU module and specifying output (Y) in the SET/RST
instruction, the ON/OFF status of the device at the execution of the last instruction in the
scan is returned as the output (Y).

3-40

(3) PLS instructions using the same device
The PLS instruction turns ON the specified device when the execution command is turned
ON from OFF.
It turns OFF the device at any other time (OFF to OFF, ON to ON, or ON to OFF).
If two or more PLS instructions using the same device are executed in one scan, each
instruction turns ON the device when the corresponding execution command is turned ON
from OFF and turns OFF the device in other cases.
For this reason, if multiple PLS instructions using the same device are executed in a single
scan, a device that has been turned ON by the PLS instruction may not be turned ON during
one scan.

1

[Ladder]

4

X0

2
3

PLS M0

2
X1
PLS M0

6

[Timing Chart]
• The ON/OFF timing of the X0 and X1 is different. (The specified device does not turn ON
throughout the scan.)
X0

X0
PLS M0
X1

PLS M0
END

END

END

8

PLS M0
X1

PLS M0

7

ON
OFF

X1

OFF

M0

OFF

3.9 Operation when the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device

X0

ON

ON

ON

M0 turns ON because X1
M0 turns OFF because X1
goes ON (OFF ON).
status is other than OFF ON.
M0
turns
OFF because X0 status
M0 turns ON because
is other than OFF ON.
X0 goes ON (OFF ON).
(M0 remains OFF.)

3-41

• The X0 and X1 turn ON from OFF at the same time.
X0

X0
PLS M0
X1
PLS M0
END

END

PLS M0
X1
PLS M0
END

ON
X0

OFF

X1

OFF

M0

OFF

ON

ON

M0 turns ON because X1
goes ON (OFF ON).
(M0 remains ON.)
M0 turns ON because
X0 goes ON (OFF ON).

M0 turns OFF because X1 status is
other than OFF ON.
(M0 remains OFF.)
M0 turns OFF because X0 status is other
than OFF ON.

When using a refresh type CPU module and specifying output (Y) in the PLS instructions,
the ON/OFF status of the device at the execution of the last PLS instruction in the scan is
returned as the output (Y).
(4) PLF instructions using the same device
The PLF instruction turns ON the specified device when the execution command is turned
OFF from ON.
It turns OFF the device at any other time (OFF to OFF, OFF to ON, or ON to ON).
If two or more PLF instructions using the same device are executed in one scan, each
instruction turns ON the device when the corresponding execution command is turned OFF
from ON and turns OFF the device in other cases.
For this reason, if multiple PLF instructions using the same device are executed in a single
scan, a device that has been turned ON by the PLF instruction may not be turn ON during
one scan.
[Ladder]
X0
PLF M0

X1
PLF M0

3-42

[Timing Chart]
• The ON/OFF timing of the X0 and X1 is different. (The specified device does not turn ON
throughout the scan.)
X0

X0
PLF M0
PLF M0
END

END

2

PLF M0
X1
PLF M0
END

X1

3

ON
OFF

X0

4

ON
X1

1

OFF
ON

2

M0 OFF
M0 turns OFF because X1 status is
M0 turns OFF because X1
other than ON OFF.
status is other than ON OFF.
(M0 remains OFF.)
M0 turns ON because
X0 goes OFF (ON OFF).
M0 turns OFF because X0 status is
other than ON OFF
(M0 remains OFF.)

6
7

• The X0 and X1 turn OFF from ON at the same time.
X0

X0
PLF M0
X1
PLF M0
END

END

8

PLF M0
X1
PLF M0
END

ON

ON
X1

OFF
ON

M0 OFF
M0 turns ON because
X1 goes OFF (ON OFF).
(M0 remains ON.)
M0 turns ON because
X0 goes OFF (ON OFF).

M0 turns OFF because X1 status is
other than ON OFF.
(M0 remains OFF.)
M0 turns OFF because X1 status is
other than ON OFF.

When using a refresh type CPU module and specifying output (Y) in the PLF instructions,
the ON/OFF status of the device at the execution of the last PLF instruction in the scan is
returned as the output (Y).

3-43

3.9 Operation when the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device

OFF

X0

3.10 Precautions for Use of File Registers
This section explains the precautions for use of the file registers in the QCPU.
(1) CPU modules that cannot use file registers
The Q00JCPU and Q00UJCPU cannot use the file registers. When using the file registers,
use the CPU module of other than the Q00JCPU and Q00UJCPU.
(2) Setting of file registers to be used
When using the file registers, the file registers to be used must be set with the PLC
parameter or QDRSET instruction. (The PLC parameters of the Q00CPU and Q01CPU
need not be set since they are preset to "Use file register".) If the file registers to be used
have not been set, normal operation cannot be performed with the instructions that use the
file registers.

Even when file registers to be used are not set in the PLC parameter, a program
that uses file registers can be created. For the CPU module other than the
Universal model QCPU, an error does not occur when that program is written to
the CPU module.
However, note that the correct data cannot be written/read to/from the file register.
For the Universal model QCPU, an error occurs if the program where file registers
are used is executed.
(3) Securing of file register area
(a) High Performance model QCPU, Process CPU, Redundant CPU, Universal model
QCPU
When using file registers, register the file registers to the standard RAM/memory card to
secure the file register area.
(b) Basic Model QCPU (except Q00JCPU)
The file register area has been secured in the standard RAM beforehand. The user
need not secure the file register area.
The following table indicates the memories that can use the file registers in each CPU
module.
High Performance model QCPU
Memory

Process CPU

Basic Model QCPU

Redundant CPU

(except Q00JCPU)

Universal model QCPU
Standard RAM
Memory card *1 *2

*3
: Can be registered,

: Cannot be registered.

*1: When the flash memory is used, only read from the file registers can be performed. (Write to the flash ROM
cannot be performed.)
*2: When the E2PROM is used, write to the E2PROM can be performed with the PROMWR instruction.
*3: Unusable for the Q00UCPU and Q01UCPU.

3-44

Remark
For the file register setting method and file register area securing method, refer to
User’s Manual (Functions Explanation, Program Fundamentals) for the CPU
module used.

(4) Designation of file register number in excess of the registered number of points
(a) CPUs other than Universal model QCPU
An error will not occur if data are written or read to or from the file registers that have
numbers greater than the registered number of points. However, note that the read/write
of correct data to/from the file registers cannot be performed.
(b) Universal model QCPU
When data are written to or read from the file registers that are not registered, an error
occurs. (Error code: 4101)
(5) File register specifying method
There are the block switching method and serial number access method to specify the file
registers.
(a) Block switching method
In the block switching method, specify the number of used file register points in units of
32k points (one block). For file registers of 32k points or more, specify the file registers
by switching the block No. to be used with the RSET instruction. Specify each block as
R0 to R32767.
RSET K1

D0

Block 0

R32767
RSET K2

MOV

D0

R0

Specifying R0
for block 2

3
4
2
6
7
8

Standard RAM/Memory card
R0
to

R0

2

3.10 Precautions for Use of File Registers

MOV

Specifying R0
for block 1

1

R0
to

Block 1

R32767
R0
to

Block 2

3-45

(b) Serial number access method
In the serial number access method, specify the file registers beyond 32k points with
consecutive device numbers. The file registers of multiple blocks can be used as
consecutive file registers. Use "ZR" as the device name.
MOV

D0

Standard RAM/Memory card

ZR32768
ZR0
to

MOV

D0

ZR65536

(Block 0)

ZR32767
ZR32768
to

(Block 1)

ZR65535
ZR65536
to

(Block 2)

(6) Settings and restrictions when refreshing file registers
(a) Settings
The settings of refresh devices are as follows.
• Refresh settings for CC-Link IE controller network
• Refresh settings for MELSECNET/H
• Refresh settings for CC-Link
• Auto refresh settings for the intelligent function module
• Auto refresh settings for the multiple CPU system
(b) Restrictions
The restrictions when specifying file registers to refresh devices are as follows.
1) Refresh cannot be performed correctly if the use of file register which has the
same name as the program is specified by the PLC parameter.
When the file register which has the same name as the program is used,
refresh is performed to the data of the file register having the same name as
the program that is set at the last number in the [Program] tab page of PLC
parameter. To read/write the refresh data, specify the file register to the refresh
device after switching the file register to the corresponding one with the
QDRSET instruction.
2) Refresh cannot be performed correctly if the file name of file register or the
drive number is changed by the QDRSET instruction.
If the file name of file register or the drive number is changed by the QDRSET
instruction, link refresh is performed to the data of the setting file at the time of
the END instruction execution. To read/write the refresh data, specify the file
register of the setting file at the time of the END instruction execution.
If the drive number is changed by the QDRSET instruction when "ZR" is
specified for the device in the CPU modules other than the Universal model
QCPU, an error (LINK PARA ERROR (3101)) occurs. (Note that an error does
not occur when "R" is specified for the device.)

3-46

3) When a block number is switched by the RSET instruction, refresh is
performed to the data of the file register (R) in the switched block number.
When a block number is switched by the RSET instruction, refresh is
performed to the data of the file register (R) in the block number at the time of
the END instruction execution. To read/write the refresh data, specify the file
register of the block number at the time of the END instruction execution.

1
2

(7) Precautions when file registers in the flash memory are used
This section explains the precautions for use of the flash memory.

3

(a) The following flash memory can be used.
•Flash card

4

(b) File registers in the flash memory can be only read in a sequence program.
(Write to the flash memory cannot be performed in a sequence program.)
Sequence program

2

Flash memory

BMOV D100 R0

K10

BMOV R100 D0

K10

6

Write
File register
Read

7
8

When using the flash memory for the file registers, write data in advance.
Using GX Developer, write data to the flash card.
3.10 Precautions for Use of File Registers

3-47

MEMO

3-48

4

HOW TO READ
INSTRUCTIONS
4

4-1

The description of instructions that are contained in the following chapters are presented in the
following format.
1)
2)

3)

4)

5)

6)

7)

8)

1) Code used to write instruction (instruction symbol).
2) Section number and general category of instructions described.
3) Shows if instructions are enabled or disabled for each CPU module type.
Icon
Universal model
QCPU

Basic model
QCPU

High Performance
model QCPU

Process CPU

Redundant CPU

Universal

Basic

High
performance

Process

Redundant

Meaning
A normal icon means the
corresponding instruction can be
used.
The icon with Ver. means the

Ver.

Ver.

Universal

Basic

Ver.
High
performance

Ver.

Ver.

Process

Redundant

instruction can be used with
some restrictions (e.g., function
version, software version).
The icon with

Universal

4-2

Basic

High
performance

Process

Redundant

(cross) means

the corresponding instruction
cannot be used.

9)

4

4) Indicates ladder mode expressions and execution conditions for instructions.
Execution Condition

Non-conditional
Execution

Code recorded on

No symbol

description page

recorded

Executed while ON

Executed One Time
at ON

Executed while OFF

Executed One
Time at OFF

5) Indicates the data set for each instruction and the data type.
Data Type

Meaning

Bit

Bit data or head number in bit data

BIN 16 bits

BIN 16-bit data or head number in word device

BIN 32 bits

BIN 32-bit data or head number in double word device

BCD 4-digit

4-digit BCD data

BCD 8-digit

8-digit BCD data

Real number

Floating decimal point data

character string

Character string data

Device name

Device name data

4-3

6) Devices which can be used by the instruction in question are indicated with circle. The types
of devices that can be used are as indicated below:

Setting Data

Internal Devices
(System, User)
Bit

Applicable
devices *1

X, Y, M, L,
SM, F,
B, SB,
FX, FY *2

Word
T, ST, C, *3
D, W, SD,
SW, FD,
@

Link direct device *4

File
Register
R, ZR

R, ZR

J

\

Bit

Word

J

\X

J

\Y

J

\W

J

\B

J

\SW

J

\SB

Intelligent
function
module
U

U

Index register
Zn

Constant *5

Others *5

\G

\G

Z

K, H , E, $

P, I, J, U,
DX, DY, N,
BL, TR,
BL \ S,V

*1: For the description for the individual devices, refer to the QnUCPU User’s Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User’s Manuall
(Function Explanation, Program Fundamentals)
*2: FX and FY can be used only for bit data, and FD only for word data.
*3: When T, ST and C are used for other than the instructions below, only word data can be used.
(Bit data cannot be used.)
[Instructions that can be used with bit data]
LD, LDI, AND, ANI, OR, ORI, LDP, LDF, ANDP, ANDF, ORP, ORF,LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI,
OUT, RST
*4: Usable with the CC-Link IE controller network, MELSECNET/H, and MELSECNET/10.
*5: Devices which can be set are recorded in the "Constant" and the "Other" columns.

7) Indicates the function of the instruction.
8) Indicates conditions under which error is returned, and error number. See Section 3.6 for
errors not included here.
9) Indicates both ladder and list for simple program example. Also indicates the types of
individual devices used when the program is executed.

4-4

5

7

SEQUENCE
INSTRUCTIONS

7
7
7
5
7

Category
Contact instruction
Association instruction

Processing Details
Operation start, series connection, parallel connection
Ladder block connection, creation of pulses from operation
results, store/read operation results

Section
Section 5.1

Bit device output, pulse output, output reversal

Section 5.3

Shift instruction

Bit device shift

Section 5.4

Master control instruction

Master control

Section 5.5

Termination instruction

Program termination

Section 5.6

Other instruction

fit in the above categories

7

Section 5.2

Output instruction

Program stop, instructions such as no operation which do not

7

Reference

Section 5.7

5-1

LD,LDI,AND,ANI,OR,ORI

5.1 Contact Instructions
5.1.1

Operation start, series connection, parallel connection
(LD,LDI,AND,ANI,OR,ORI)

LD,LDI,AND,ANI,OR,ORI

Basic

High
performance

Process Redundant Universal

Bit device number / Word device bit designation ( S )
X1/D0.1

LD

X1/D0.1

LDI

X2/D0.2

AND

X2/D0.2

ANI
OR
X3/D0.3

ORI
X3/D0.3

S

Setting
Data
S

: Devices used as contacts (bits)

Internal Devices
Bit

Word

J

R, ZR
Bit

\
Word

U

\G

Zn

Constants

Other
DX, BL

––

Function
LD, LDI
(1) LD is the A contact operation start instruction, and LDI is the B contact operation start
instruction. They read ON/OFF information from the designated device*1, and use that as an
operation result.
*1: When a bit designation is made for a word device, the device turns ON or OFF depending on the 1/0 status of
the designated bit.

5-2

LD,LDI,AND,ANI,OR,ORI

AND, ANI
(1) AND is the A contact series connection instruction, and ANI is the B contact series
connection instruction. They read the ON/OFF data of the designated bit device*2, perform
an AND operation on that data and the operation result to that point, and take this value as
the operation result.
*2: When a bit designation is made for a word device, the device turns ON or OFF depending on the 1/0 status of
the designated bit.

1
2
3

(2) There are no restrictions on the use of AND or ANI, but the following applies with a
peripheral device used in the ladder mode:
(a) Write ......... When AND and ANI are connected in series, a ladder with up to 24 stages
can be displayed.
(b) Read......... When AND and ANI are connected in series, a ladder with up to 24 stages
can be displayed. If the number exceeds 24 stages, up to 24 will be
displayed.

4
5

OR, ORI
(1) OR is the A contact single parallel connection instruction, and ORI is the B contact single
parallel connection instruction. They read ON/OFF information from the designated
device*3, and perform an OR operation with the operation results to that point, and use the
resulting value as the operation result.
*3: When a bit designation is made for a word device, the device turns ON or OFF depending on the 1/0 status of
the designated bit.

6
7
8

(2) There are no limits on the use of OR or ORI, but the following applies with a peripheral
device used in the ladder mode.

5.1 Contact Instructions
5.1.1 Operation start, series connection, parallel connection (LD,LDI,AND,ANI,OR,ORI)

(a) Write ......... OR and ORI can be used to create connections of up to 23 ladders.
(b) Read......... OR and ORI can be used to create connections of up to 23 ladders.
The 24th or subsequent ladders cannot be displayed properly.

Remark
Word device bit designations are made in hexadecimal.
Bit b11 of D0 would be D0.0B.
See 3.2.1 for more information on word device bit designation.

5-3

LD,LDI,AND,ANI,OR,ORI

Operation Error
(1) There are no operation errors with LD, LDI, AND, ANI, OR, or ORI instruction.

Program Example
(1) A program using the LD, AND, OR, and ORI instructions.
[Ladder Mode]

[List Mode]
Step

b15
D0

Device
Bit designated
for word
device

b0

b5
1

Instruction

0

(2) A program linking contacts using the ANB and ORB instructions.
[Ladder Mode]
b15
D6

b4

b1b0

1

1

0

[List Mode]
Step

Instruction

Device

0

Bit designated
for word
device

ORB

ANB

(3) A parallel program with the OUT instruction.
[Ladder Mode]

[List Mode]
Step

5-4

Instruction

Device

LDP,LDF,ANDP,ANDF,ORP,ORF

5.1.2

Pulse operation start, pulse series connection, pulse parallel
connection (LDP,LDF,ANDP,ANDF,ORP,ORF)

1

LDP,LDF,ANDP,ANDF,ORP,ORF

Basic

High
performance

Process Redundant Universal

2
3

Bit device number / Word device bit designation ( S )

4

X1/D0.1

LDP

5

X1/D0.1

LDF

6

X2/D0.2

ANDP
X2/D0.2

7

ANDF
ORP

8
X3/D0.3

X3/D0.3

S

Setting
Data

: Devices used as contacts (bits)

Internal Devices
Bit

Word

J

R, ZR
Bit

\

U

Word

\G

Zn

Constants

Other
DX

––

S

Function
LDP, LDF
(1) LDP is the leading edge pulse operation start instruction, and is ON only at the leading edge
of the designated bit device (when it goes from OFF to ON). If a word device has been
designated, it is ON only when the designated bit changes from 0 to 1.
In cases where there is only an LDP instruction, it acts identically to instructions for the
creation of a pulse that are executed during ON( P).
Ladder using an LDP instruction
X0
MOV
K0
D0
X0

Ladder not using an LDP instruction
X0
MOVP
K0
D0
X0

M0

PLS

M0

5-5

5.1 Contact Instructions
5.1.2 Pulse operation start, pulse series connection, pulse parallel connection (LDP,LDF,ANDP,ANDF,ORP,ORF)

ORF

LDP,LDF,ANDP,ANDF,ORP,ORF

(2) LDF is the trailing edge pulse operation start instruction, and is ON only at the trailing edge
of the designated bit device (when it goes from ON to OFF).
If a word device has been designated, it is ON only when the designated bit changes from 1
to 0.

ANDP, ANDF
(1) ANDP is a leading edge pulse series connection instruction, and ANDF is a trailing edge
pulse series connection instruction. They perform an AND operation with the operation
result to that point, and take the resulting value as the operation result.
The ON/OFF data used by ANDP and ANDF are indicated in the table below:
Device Specified in ANDP or ANDF
Bit Device

Bit Designated for

ANDP State

ANDF State

Word Device

OFF to ON

0 to 1

OFF

0

ON

1

ON to OFF

1 to 0

ON
OFF
OFF
ON

ORP, ORF
(2) ORP is a leading edge pulse parallel connection instruction, and ORF is a trailing edge pulse
serial connection instruction. They perform an OR operation with the operation result to that
point, and take the resulting value as the operation result.
The ON/OFF data used by ORP and ORF are indicated in the table below:
Device Specified in ORP or ORF
Bit Device

Bit Designated for

ORP State

ORF State

Word Device

OFF to ON

0 to 1

OFF

0

ON

1

ON to OFF

1 to 0

ON
OFF
OFF
ON

Operation Error
(1) There are no operation errors with LDP, LDF, ANDP, ANDF, ORP, or ORF instruction.

Program Example
(1) The following program executes the MOV instruction at input X0, or at the leading edge of
b10 (bit 11) of data register D0.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

*1

*1: Word device bit designation is performed in hexadecimal. Bit b10 of D0 will be D0.A.

5-6

LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI

5.1.3

Pulse NOT operation start, pulse NOT series connection,
pulse NOT parallel connection
(LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI)

1
2

LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI

Ver.
Basic

High
performance

Process Redundant Universal

• QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.
• QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

3
4

Bit device number / Word device bit designation ( S )
X1/D0.1

LDPI

5

X1/D0.1

LDFI

6
X2/D0.2

ANDPI

7

X2/D0.2

ANDFI

8

ORPI
X3/D0.3

X3/D0.3

S

Setting
Data
S

: Devices used as contacts (bits)

Internal Devices
Bit

Word

J

R, ZR
Bit

\
Word

U

\G

Zn

Constants

Other
DX

––

Function
LDPI, LDFI
(1) LDPI is the leading edge pulse NOT operation start instruction that is on only at the leading
edge of the specified bit device (when the bit device goes from on to off) or when the bit
device is on or off. If a word device has been specified, LDPI is on only when the specified
bit is 0, 1, or changes from 1 to 0.

5-7

5.1 Contact Instructions
5.1.3 Pulse NOT operation start, pulse NOT series connection, pulse NOT parallel connection (LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI)

ORFI

LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI

(2) LDFI is the trailing edge pulse NOT operation start instruction that is on only at the trailing
edge of the specified bit device (when the bit device goes from off to on) or when the bit
device is on or off. If a word device has been specified, LDFI is on only when the specified
bit is 0, 1, or changes from 0 to 1.
Device Specified in LDPI or LDFI
Bit Device

Bit Designated for

LDPI State

LDFI State

Word Device

OFF to ON

0 to 1

OFF

ON

OFF

0

ON

ON

ON

1

ON

ON

ON to OFF

1 to 0

ON

OFF

ANDPI, ANDFI
(1) ANDPI is a leading edge pulse NOT series connection, and ANDFI is a trailing pulse NOT
series connection. ANDPI and ANDFI execute an AND operation with the previous operation
result, and take the resulting value as the operation result.
The on or off data used by ANDPI and ANDFI are indicated in the table below.
Device Specified in ANDPI or ANDFI
Bit Device

Bit Designated for

LDPI State

LDFI State

Word Device

OFF to ON

0 to 1

OFF

ON

OFF

0

ON

ON

ON

1

ON

ON

ON to OFF

1 to 0

ON

OFF

ORPI, ORFI
(1) ORPI is a leading edge pulse NOT parallel connection, and ORFI is a trailing pulse NOT
parallel connection. ORPI and ORFI execute an OR operation with the previous operation
result, and take the resulting value as the operation result.
The on or off data used by ORPI and ORFI are indicated in the table below.
Device Specified in ORPI or ORFI
Bit Device

Bit Designated for

ORPI State

ORFI State

Word Device

OFF to ON

0 to 1

OFF

ON

OFF

0

ON

ON

ON

1

ON

ON

ON to OFF

1 to 0

ON

OFF

Operation Error
(1) There are no operation errors with LDPI, LDFI, ANDPI, ANDFI, ORPI, or ORFI instruction.

5-8

LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI

Program Example

1

(1) The following program stores 0 into D0 when X0 is on, off, or turns from on to off, or M0 is
on, off, or turns from off to on.
[Ladder Mode]

[List Mode]
Step

Instruction

2

Device

3
4
(2) The following program stores 0 into D0 when X0 is on and b10 (bit 11) of D0 is on, off, or
turns from on to off.
Ladder Mode]

5

[List Mode]
Step

Instruction

6

Device

7
8

5.1 Contact Instructions
5.1.3 Pulse NOT operation start, pulse NOT series connection, pulse NOT parallel connection (LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI)

5-9

ANB,ORB

5.2 Association Instructions
5.2.1

Ladder block series connection and parallel connection
(ANB,ORB)

ANB,ORB

Basic

High
performance

Process Redundant Universal

ANB

ANB

Block A

Block B

Block A

ORB
ORB
Block B

Internal Devices

Setting
Data

Bit

Word

R, ZR

J

For parallel connection of 1 contact,
OR or ORI is used.

\

Bit

U

Word

––

\G

Zn

Constants

Other

––

Function
ANB
(1) Performs an AND operation on block A and block B, and takes the resulting value as the
operation result.
(2) The symbol for ANB is not the contact symbol, but rather is the connection symbol.
(3) When programming in the list mode, up to 15 ANB instructions (16 blocks) can be written
consecutively.

ORB
(1) Conducts an OR operation on Block A and Block B, and takes the resulting value as the
operation result.
(2) ORB is used to perform parallel connections for ladder blocks with two or more contacts.
For ladder blocks with only one contact, use OR or ORI; there is no need for ORB in such
cases.
[Ladder Mode]
X1
X0

[List Mode]
Y10

0
X2

X4

X3

0
1
2
3
4
5
6

LD
AND
LD
AND
ORB
OR
OUT

X0
X1
X2
X3
X4
Y10

(3) The ORB symbol is not the contact symbol, but rather is the connection symbol.
(4) When programming in the list mode, it is possible to use up to 15 ORB instructions
successively (16 blocks).

5-10

ANB,ORB

Operation Error

1

(1) There are no operation errors associated with ANB or ORB instruction.

2

Program Example

3

(1) A program using the ANB and ORB instructions.
[Ladder Mode]

[List Mode]
Step

4
Instruction

Device

5
6
7
8

5.2 Association Instructions
5.2.1 Ladder block series connection and parallel connection (ANB,ORB)

5-11

MPS,MRD,MPP

5.2.2

Operation results push,read,pop (MPS,MRD,MPP)

MPS,MRD,MPP

Basic

High
performance

Process Redundant Universal

In the ladder display, MPS, MRD and MPP are not displayed.
Command

Command
MPS
Command
MRD
Command
MPP

Setting
Data
––

Internal Devices
Bit

Word

R, ZR

J
Bit

\

U

Word

\G

Zn

Constants

Other

––

Function
MPS
(1) Stores the memory of the operation result (ON or OFF) immediately prior to the MPS
instruction.
(2) Up to 16 MPS instructions can be used successively.
If the MPP instruction is used during this process, the number of uses calculated for the
MPS instruction will be decremented by one.

MRD
(1) Reads the operation result stored for the MPS instruction, and uses that result to perform the
operation in the next step.

MPP
(1) Reads the operation result stored for the MPS instruction, and uses that result to perform the
operation in the next step.
(2) Clears the operation results stored by the MPS instruction.
(3) Subtracts 1 from the number of MPS instruction times of use.

5-12

MPS,MRD,MPP

1. The following shows ladders both using and not using the MPS, MRD, and
MPP instructions.
Ladder Using the MPS, MRD and MPP Instruction Ladder not Using MPS, MRD, and MPP Instructions

X0

X1

X2
X3
X5

Y10
X4

Y11
Y12

X0

X1

X2

X0

X1

X3

X0

X1

X5

1
2

Y10
X4

3

Y11
Y12

4

2. The MPS and MPP instructions must be used the same number of times.
Failure to observe this will not correctly display the ladder in the ladder mode of
the peripheral device.

5
6

Operation Error
7

(1) There are no errors associated with the MPS, MRD, or MPP instruction.

8

Program Example
(1) A program using the MPS, MRD, and MPP instructions.

1)

[List Mode]
Step

Instruction

5.2 Association Instructions
5.2.2 Operation results push,read,pop (MPS,MRD,MPP)

[Ladder Mode]

Device

1)

2)
4)

3)

2)
3)

5)

4)

6)

5)
7)
8)

6)
7)

9)

8)

10)

9)
10)

5-13

MPS,MRD,MPP

(2) A program using the MPS and MPP instructions successively.
[Ladder Mode]

[List Mode]
Step

5-14

Instruction

Device

INV

5.2.3

Operation results inversion (INV)

1
INV

Basic

High
performance

Process Redundant Universal

3

Command

INV

2

4
Internal Devices

Setting
Data

Bit

Word

––

R, ZR

J
Bit

\

U

Word

\G

Zn

Constants

Other

––

5
6

Function
Inverts the operation result immediately prior to the INV instruction.

7

Operation Result Immediately Prior to the Operation Result Following the Execution of
INV Instruction

the INV Instruction

OFF

ON

ON

OFF

8

Operation Error
5.2 Association Instructions
5.2.3 Operation results inversion (INV)

(1) There are no operation errors associated with the INV instruction.

Program Example
(1) A program which inverts the X0 ON/OFF data, and outputs from Y10.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Timing Chart]
ON
X0
Y10

OFF
ON
OFF

5-15

INV

1. The INV instruction operates based on the results of calculation made until the
INV instruction is given. Accordingly, use it in the same position as that of the
AND instruction.
The INV instruction cannot be used at the LD and OR positions.
2. When a ladder block is used, the operation result is inverted within the range of
the ladder block. To operate a ladder using the INV instruction in combination
with the ANB instruction, pay attention to the range that will be inverted.
Range inverted
M0

M1

M2

0

Y10
ANB

M10

M20

10

For details of the ANB instruction, refer to Section 5.2.1

5-16

END

MEP,MEF

5.2.4

Operation result conversions (MEP,MEF)

1

MEP,MEF

Basic

High
performance

Process Redundant Universal

2
MEP
MEF

Command

3

Command

4

Internal Devices

Setting
Data

Bit

––

Word

R, ZR

J
Bit

\

U

Word

\G

Zn

Constants

Other

5

––

6

Function

MEP
(1) If operation results up to the MEP instruction are leading edge (from OFF to ON), goes ON
(continuity status).
If operation results up to the MEP instruction are anything other than leading edge, goes
OFF (non-continuity status).
(2) Use of the MEP instruction simplifies pulse conversion processing when multiple contacts are
connected in series.

7
8

MEF

(2) Use of the MEF instruction simplifies pulse conversion processing when multiple contacts are
connected in series.

Operation Error
(1) There are no operation errors associated with the MEP or MEF instruction.

Program Example
(1) A program which performs pulse conversion to the operation results of X0 and X1
[Ladder Mode]
[List Mode]
Step

Instruction

Device

1. The MEP and MEF instructions will occasionally not function properly when
pulse conversion is conducted for a contact that has been indexed by a
subroutine program or by the FOR to NEXT instructions. If pulse conversion is
to be conducted for a contact that has been indexed by a subroutine program
or by the FOR to NEXT instructions, use the EGP/EGF instructions.
2. Because the MEP and MEF instructions operate with the operation results
immediately prior to the MEP and MEF instructions, the AND instruction should
be used at the same position. The MEP and MEF instructions cannot be used
at the LD or OR position.

5-17

5.2 Association Instructions
5.2.4 Operation result conversions (MEP,MEF)

(1) If operation results up to the MEF instruction are trailing edge (from ON to OFF), goes ON
(continuity status).
If operation results up to the MEF instruction are anything other than trailing edge, goes OFF
(non-continuity status).

EGP,EGF

5.2.5

Pulse conversions of edge relay operation results (EGP,EGF)

EGP,EGF

Basic

EGP
EGF
D

Setting
Data
D

Command

D

Command

D

Process Redundant Universal

: Edge relay number where operation results are stored (bits)

Internal Devices
Bit

High
performance

Word

R, ZR

J
Bit

\
Word

U

\G

Zn

Constants

Other
V

––

Function
EGP
(1) Operation results up to the EGP instruction are stored in memory by the edge relay (V).
(2) Goes ON (continuity status) at the leading edge (OFF to ON) of the operation result up to the
EGP instruction.
If the operation result up to the EGP instruction is other than a leading edge (i.e., from ON to
ON, ON to OFF, or OFF to OFF), it goes OFF (non-continuity status).
(3) The EGP instruction is used for subroutine programs, and for conducting pulse operations
for programs designated by indexing between the FOR and NEXT instructions.
(4) The EGP instruction can be used like an AND instruction.

EGF
(1) Operation results up to the EGF instruction are stored in memory by the edge relay (V).
(2) Goes ON at the trailing edge (from ON to OFF) of the operation result up to the EGF
instruction.
If the operation result up to the EGF instruction is other than a trailing edge (i.e., from OFF to
ON, ON to ON, or OFF to OFF), it goes OFF (non-continuity status).
(3) The EGF instruction is used for subroutine programs, and for conducting pulse operations
for programs designated by indexing between the FOR and NEXT instructions.
(4) The EGF instruction can be used like an AND instruction.

Operation Error
(1) There are no operation errors associated with the EGP or EGF instruction.

5-18

EGP,EGF

Program Example

1

(1) A program using the EGP instruction in the subroutine program using the EGD instruction
[Ladder Mode]

[List Mode]
Step

2
Instruction

Device

3
4
5
6
7
[Operation]
END processing (1)

(2)

(1)

(2)

(1)

(2)

(1)

(2)

(1)

8

(2)

ON

ON
OFF

X0 OFF
ON

Turns OFF as X0 remains ON.

ON

ON

V0 OFF
V1 OFF

Turns ON at the leading ON
edge of X0.

Turns OFF as X1 remains ON.

Turns ON at the leading edge of X1.
D0

2

1
1

D1

1. Since the EGP and EGF instructions are executed according to the operation
results performed immediately before the EGP/EGF instructions, these
instructions must be used at the same position as the AND instruction.
(Refer to Section 5.1.1.)
The EGP and EGF instruction cannot be used at the position of the LD or OR
instruction.
2. EGP and EGF instructions cannot be used at the ladder block positions shown
below.
X0

X1

V0
SET M0

X2

5-19

5.2 Association Instructions
5.2.5 Pulse conversions of edge relay operation results (EGP,EGF)

X1 OFF

OUT

5.3 Output Instructions
5.3.1

Out instruction (excluding timers, counters, and annunciators) (OUT)

OUT

Basic

High
performance

Process Redundant Universal

Bit device number ( D )
Command
Y35

OUT

Word device
bit designation ( D )

Command
D0.5

D

Setting
Data

D

: Number of the device to be turned ON and OFF (bits)

Internal Devices
Bit

Word

R, ZR

J
Bit

\
Word

U

\G

Zn

(Other
than T, C,
or F)

Constants

––

Function
(1) Operation results up to the OUT instruction are output to the designated device.
(a) When Using Bit Devices
Operation Results

Coil

OFF

OFF

ON

ON

(b) When Bit Designation has been Made for Word Device
Operation Results

Bit Designated

OFF

0

ON

1

Operation Error
(1) There are no operation errors associated with the OUT instruction.

5-20

Other
DY

OUT

Program Example

1

(1) When using bit devices
[Ladder Mode]

[List Mode]
Step

Instruction

2

Device

3
4
(2) When bit designation has been made for word device
[Ladder Mode]

5

[List Mode]
Step

Instruction

Device

6
7
8

b15

b7 b6 b5

b0

D0

5.3 Output Instructions
5.3.1 Out instruction (excluding timers, counters, and annunciators) (OUT)

Remark
The number of basic steps for the OUT instructions is as follows:
• When using internal device or file register (R)
• When using direct access output (DY)
• When using serial number access format file register
(Only for Universal model QCPU)
(Other than Universal model QCPU)
• Devices other than above

:1
:2
:2
:3
:3

5-21

OUT T,OUTH T

5.3.2

Timers (OUT T,OUTH T)

OUT T,OUTH T

Basic

Command

OUT T

Command

Set value
Setting in the range
from 1 to 32767 is valid.

D10

Set value
Data register value in
the range from 1 to
32767 is valid.

T0

Set value
Setting in the range
from 1 to 32767 is valid.

H K50

Command

T0

OUTH T

(High-speed timer)

Command

H D10

Set value
Data register value in
the range from 1 to
32767 is valid.

T0

K50

Command

Set value
Setting in the range
from 1 to 32767 is valid.

ST0

OUT ST
(Low-speed retentive timer)

Command

D10

Set value
Data register value in
the range from 1 to
32767 is valid.

ST0

H K50

Command

Set value
Setting in the range
from 1 to 32767 is valid.

ST0

OUTH ST

(High-speed retentive timer)

Command

Process Redundant Universal

K50
T0

(Low-speed timer)

High
performance

H D10

Set value
Data register value in
the range from 1 to
32767 is valid.

ST0

D
: Timer number (bit)
Set value : Value set for timer (BIN 16 bits *1)

Setting
Data
D

Set value

Internal Devices
Bit
(Only T)
––

Word
––

R, ZR
––

(Other
than T, C)

J
Bit

\
Word

––

U
––

––

\G

Zn

Constants
K

Other

––

––

––

––

*2

––

*1: The value setting for the timer cannot be designated indirectly.
@D0
T0

Indirect designation is
not permitted.

See Section 3.4 for further information on indirect designation.
*2: Timer values can be set only as a decimal constant (K). Hexadecimal constants (H) and real numbers
cannot be used for timer settings.

Function
(1) When the operation results up to the OUT instruction are ON, the timer coil goes ON and the
timer counts up to the value that has been set; when the time up status (total numeric value
is equal to or greater than the setting value), the contact responds as follows:

5-22

A Contact

Continuity

B Contact

Non-continuity

OUT T,OUTH T
(2) The contact responds as follows when the operation result up to the OUT instruction is a
change from ON to OFF:
Type of Timer

Timer Coil

Low speed timer

Present Value of

After Time Up

1

Timer

A Contact

B Contact

A Contact

B Contact

0

Non-continuity

Continuity

Non-continuity

Continuity

2

Non-continuity

Continuity

Continuity

Non-continuity

3

OFF

High speed timer

Prior to Time Up

Low speed
retentive timer

OFF

High speed

Maintains the
present value

retentive timer

(3) To clear the present value of a retentive timer and turn the contact OFF after time up, use the
RST instruction.
(4) A negative number ( 32768 to 1) cannot be set as the setting value for the timer.*3
If the setting value is 0, the timer will time out when the time the OUT instruction is executed.
*3: When specifying a setting value for the timer using a word device (D, W, R, ZR, J \ or U \ ), whether
the value is in the setting range is not checked. Check the value in the user program so that a negative
number is not set.

(5) The following processing is conducted when the OUT instruction is executed:
• OUT T

coil turned ON or OFF

• OUT T

contact turned ON or OFF

• OUT T present value updated
In cases where a JMP instruction or the like is used to jump to an OUT T instruction while
the OUT T instruction is ON, no present value update or contact ON/OFF operation is
conducted.
Also, if the same OUT T instruction is conducted two or more times during the same scan,
the present value of the number of repetitions executed will be updated.

Remark
1. Timer's time limit
Time limit of the timer is set in the PLC system of the PLC parameter dialog
box.
Type of Timer

QCPU
Setting Range

Low speed timer

1 ms to 1000 ms

Low speed retentive timer

(Default: 100 ms)

High speed timer

0.1 ms to 100.0 ms

High speed retentive timer

(Default: 10.0 ms)

Setting Unit
1 ms
0.1 ms

2. For information on timer counting methods, User's Manual
(Functions Explanation, Program Fundamentals) for the CPU module used.
3. The number of basic steps of the OUT C

instruction is 4.

Operation Error
(1) There are no operation errors associated with the OUT T

instruction.

5-23

5
6
7
8

5.3 Output Instructions
5.3.2 Timers (OUT T,OUTH T)

(6) Indexing for timer coils or contacts can be conducted only by Z0 or Z1.
Timer setting value has no limitation for indexing.

4

OUT T,OUTH T

Caution
(1) When creating a program in which the operation the timer contact triggers the operation of
other timer, create the program for the timer that operates later first.
In the following cases, all timers go ON at the same scan if the program is created in the
order the timers operate.
• If the set value is smaller than a scan time.
• If "1" is set
Example
• For timers T0 to T2, the program is created in the order the timer operates later.
T1

T0

X0

K1
T2
K1
T1
K1
T0

T2 timer starts measurement from the next scan after
turning ON of the contact of T1 timer.
T1 timer starts measurement from the next scan after
turning ON of the contact of T0 timer.
T0 timer starts measurement when X0 is turned ON.

• For timers T0 to T2, the program is created in the order of timer operation.
X0

5-24

K1
T0

T0

K1
T1

T1

K1
T2

T0 timer starts measurement when X0 is turned ON.

Contacts of T1 and T2 timers are turned ON
when the contact of T0 timer is turned ON.

OUT T,OUTH T

Program Example

1

(1) The following program turns Y10 and Y14 ON 10 seconds after X0 has gone ON.
[Ladder Mode]

[List Mode]
*3

Step

2
Instruction

Device

3
4
5

*3: The setting value of the low-speed timer indicates its default time limit (100 ms).

(2) The following program uses the BCD data at X10 to X1F as the timer's set value.

6

[Ladder Mode]
Converts the BCD data at X10 to X1F to BIN
and stores the converted value at D10.
When X2 is turned ON, T2 starts measurement
using the data stored in D10 as the set value.

7

Y15 goes ON at the count-up of T2.

8

[List Mode]
Instruction

Device

5.3 Output Instructions
5.3.2 Timers (OUT T,OUTH T)

Step

(3) The following program turns Y10 ON 250 ms after X0 goes ON.
[Ladder Mode]

[List Mode]
*4

Step

Instruction

Device

*4: The setting value of the high-speed timer indicates its default time limit (10 ms).

5-25

OUT C

5.3.3

Counter (OUT C)

OUT C

Basic

Command

High
performance

K50

Set value
Setting in the range
from 1 to 32767 is valid.

D10

Set value
Data register value in
the range from 1 to
32767 is valid.

C0

OUT C
Command
C1

D

Process Redundant Universal

: Counter number (bits)

Set value : Counter setting value (BIN 16 bits *1)
Internal Devices

Setting
Data

Bit
(Only C)

D

Set value

––

Word
––

R, ZR
––

(Other
than T, C)

J
Bit

\

U

Word

––

\G

––

––

Zn

Constants
K

Other

––

––

––

––

*2

––

*1: Counter value cannot be set by indirect designation.
@D0
C0

Indirect designation is
not permitted.

See Section 3.4 for further information on indirect designation.
*2: Counter value can be set only with a decimal constant (K). A hexadecimal constant (H) or a real number
cannot be used for the counter value setting.

Function
(1) When the operation results up to the OUT instruction change from OFF to ON, 1 is added to
the present value (count value) and the count up status (present value set value), and the
contacts respond as follows:
A Contact

Continuity

B Contact

Non-continuity

(2) No count is conducted with the operation results at ON. (There is no need to perform pulse
conversion on count input.)
(3) After the count up status is reached, there is no change in the count value or the contacts
until the RST instruction is executed.
(4) A negative number ( 32768 to

1) cannot be set as the setting value for the timer.

If the set value is 0, the processing is identical to that which takes place for 1.
(5) Indexing for the counter coil and contact can use only Z0 and Z1.
Counter setting value has no limitation for indexing.
Remark
1. For counter counting methods, refer to the User's Manual
(Functions Explanation, Program Fundamentals) for the CPU module used.
2. The number of basic steps of the OUT C

5-26

instruction is 4.

OUT C

Operation Error

1

(1) There are no operation errors associated with the OUT C

instruction.

2

Program Example
(1) The following program turns Y30 ON after X0 has gone ON 10 times, and resets the counter
when X1 goes ON.
[Ladder Mode]

3

[List Mode]
Step

Instruction

4

Device

5
6
(2) The following program sets the value for C10 at 10 when X0 goes ON, and at 20 when X1
goes ON.

7

[Ladder Mode]

8

Stores 10 at D0 when X0 goes ON.
Stores 20 at D0 when X1 goes ON.

5.3 Output Instructions
5.3.3 Counter (OUT C)

C10 executes counting using the data
stored in D0 as the set value.
Y30 goes ON at the count-up of C10.

[List Mode]
Step

Instruction

Device

5-27

OUT F

5.3.4

Annunciator output (OUT F)

OUT F

Basic

High
performance

Process Redundant Universal

Annunciator number
Command

OUT F

F35

D

Setting
Data
D

: Number of the annunciator to be turned ON (bits)

Internal Devices
Bit

Word

R, ZR

J
Bit

\
Word

U

\G

Zn

Constants

Other

––

(Only F)

Function
(1) Operation results up to the OUT instruction are output to the designated annunciator.
(2) The following responses occur when an annunciator (F) is turned ON.
• The "USER"/"ERR." LED goes ON.
• The annunciator numbers which are ON (F numbers) are stored in special registers
(SD64 to SD79).
• The value of SD63 is incremented by 1.
(3) If the value of SD63 is 16 (which happens when 16 annunciators are already ON), even if a
new annunciator is turned ON, its number will not be stored at SD64 to SD79.
(4) The following responses occur when the annunciator is turned OFF by the OUT instruction.
The coil goes OFF, but there are no changes in the status of the "USER" / "ERR." LED and
the contents of the values stored in SD63 to SD79.
Use the RST F

instruction to make the "USER"/"ERR." LED go OFF as well as to delete

the annunciator which was turned OFF by the OUT F

5-28

instruction from SD63 to SD79.

OUT F

Operation Error

1

(1) There are no operation errors associated with the OUT F

instruction.

2

Remark
1. For details of annunciators, refer to the User's Manual (Functions Explanation,
Program Fundamentals) for the CPU module used.
2. The number of basic steps for the OUT module F instruction is 2.
3. The table below shows which CPU module features either the LED display
device on front of the CPU module or "USER" LED.
Type of LED
"USER" LED
"ERR." LED

3
4

CPU Module Type Name
High Performance model QCPU, Process CPU, Redundant

5

CPU, Universal model QCPU
Basic model QCPU

6

Program Example

7

(1) The following program turns F7 ON when X0 goes ON, and stores the value 7 from SD64 to
SD79.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

5.3 Output Instructions
5.3.4 Annunciator output (OUT F)

[Operation]
X0 ON
SD63
SD64
SD65
SD66
SD67

0
0
0
0
0

SD79

0

Adds 1

SD63
SD64
SD65
SD66
SD67

1
7
0
0
0

SD79

0

8

5-29

SET

5.3.5

Setting devices (except for annunciators) (SET)

SET

Basic

High
performance

Process Redundant Universal

Command

SET

SET

D

Setting
Data

D

: Bit device number to be set (ON)/Word device bit designation (bits)

Internal Devices
Bit

Word

R, ZR

J

\

Bit

U

Word

Zn

\G

Other
BL, DY

––

(Other than T, C)

D

Constants

Function
(1) When the execution command is turned ON, the status of the designated devices becomes
as shown below:
Device

Device Status

Bit device

Coils and contacts turned ON

When Bit Designation has been Made for Word Device

Designation bit set at 1

(2) Devices turned ON by the instruction remain ON when the same command is turned OFF.
Devices turned ON by the SET instruction can be turned OFF by the RST instruction.
ON

Command
X5
SET

Y10

X5 OFF
ON

X7
RST
Command

Y10

X7 OFF
ON
Y10 OFF

(3) When the execution command is OFF, the status of devices does not change.

5-30

SET

Operation Error

1

(1) There are no operation errors associated with the SET instruction.

2

Program Example
(1) The following program sets Y8B (ON) when X8 goes ON, and resets Y8B (OFF) when X9
goes ON.
[Ladder Mode]

[List Mode]
Step

3
4

Instruction

Device

5
6
(2) The following program sets the value of D0 bit 5 (b5) to 1 when X8 goes ON, and set the bit
value to 0 when X9 goes ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

7
8

Sets b5 of D0 at 1.
Sets b5 of D0 at 0.

5.3 Output Instructions
5.3.5 Setting devices (except for annunciators) (SET)

B5

B0

D0

Remark
1. The number of basic steps for the SET instruction is as follows:
• When internal device or file register (R0 to R32767) are in use : 1
• When direct access output (DY) or SFC program device (BL) are in use
:2
• When using serial number access format file register
(Only for Universal model QCPU)
(Other than Universal model QCPU)

:2
:3

• When some other device is in use
:3
2. When using X as a device, use the device numbers that are not used for the
actual input. If the same number is used for the actual input device and input X,
the data of the actual input will be written over the input X specified in the SET
instruction.

5-31

RST

5.3.6

Resetting devices (except for annunciators) (RST)

RST

Basic

High
performance

Process Redundant Universal

Command

RST

RST

: Bit device number to be reset/ Word device bit designation (bits)
Word device number to be reset (BIN 16 bits)

D

Internal Devices

Setting
Data

D

Bit

Word

R, ZR

J
Bit

U

Word

Zn

G

Constants

Other
DY

––

D

Function
(1) When the execution command is turned ON, the status of the designated devices becomes
as shown below:
Device

Device Status

Bit device

Turns coils and contacts OFF

Timers and counters

Sets the present value to 0, and turns coils and contacts OFF

When Bit Designation has been Made for Word Device

Sets value of designated bit to 0

Word devices other than timers and counters

Sets contact to 0

(2) When the execution command is OFF, the status of devices does not change.
(3) The functions of the word devices designated by the RST instruction are identical to the
following ladder:
X10

Command

Command

X10
RST

D50
Device number

5-32

MOV

K0

D50
Device number

RST

Operation Error

1

(1) There are no operation errors associated with the RST instruction.

2

Remark
The basic number of steps of the RST instruction is as follows.
a) For bit processing
• Internal device (bit to be specified by bit device or word device)
• Direct access output
• Timer, counter
• When using serial number access format file register
(Only for Universal model QCPU)
(Other than Universal model QCPU)
• Other than above
b) For word processing
• Internal device
• Index resister
• When using serial number access format file register
(Only for Universal model QCPU)
(Other than Universal model QCPU)
• Other than above

3

:1
:2
:4

4

:2
:3
:3

5

:2
:2

6

:2
:3
:3

7
8

Program Example
5.3 Output Instructions
5.3.6 Resetting devices (except for annunciators) (RST)

(1) The following program sets the value of the data register to 0.
[Ladder Mode]
Stores the contents at X10 to X1F in D8
when X0 is turned ON.
Resets D8 to 0 when X5 is turned ON.

[List Mode]
Steps

Instruction

Device

5-33

RST
(2) The following program resets the 100 ms retentive timer and counter.
[Ladder Mode]
When ST225 is set as retentive timer, it is
turned ON when X4 ON time reaches 30 min.
Counts the number of times ST225 was
turned ON.
Resets the coil, contact and present value of
ST225 when the contact of ST225 is turned ON.
Y55 goes ON at the count-up of C23.
Resets C23 to 0 when X5 is turned ON.

[List Mode]
Step

5-34

Instruction

Device

SET F,RST F

5.3.7

Setting and resetting the annunciators (SET F,RST F)

1

SET F,RST F

Basic

High
performance

Process Redundant Universal

2
3

Command

SET

SET

D

RST

D

Command

RST

Setting
Data

SET

D

: Number of the annunciator to be set (F number) (bits)

RST

D

: Number of the annunciator to be reset (F number) (bits)

Internal Devices
Bit
(Only F)

D

Word

R, ZR

J
Bit

\
Word

U

\G

4
5

Zn

Constants

Other

––

6
7

Function
SET
(1) The annunciator designated by D is turned ON when the execution command is turned ON.
(2) The following responses occur when an annunciator (F) is turned ON.

*1: When using the Basic model QCPU, the "ERR."LED goes ON.

(3) If the value of SD63 is 16 (which happens when 16 annunciators are already ON), even if a
new annunciator is turned ON, its number will not be stored at SD64 to SD79.

RST
(1) The annunciator designated by D is turned OFF when the execution command is turned ON.
(2) The annunciator numbers (F numbers) of annunciators that have gone OFF are deleted
from the special registers (SD64 to SD79), and the value of SD63 is decremented by 1.
Remark
1. For details of annunciators,refer to the User's Manual (Functions Explanatio
Program Fundamentals) for the CPU module used.
2. The number of basic steps for the SET F and RST F instructions is 2.

5-35

5.3 Output Instructions
5.3.7 Setting and resetting the annunciators (SET F,RST F)

• The "USER" LED goes ON.*1
• The annunciator numbers which are ON (F numbers) are stored in special registers
(SD64 to SD79).
• The value of SD63 is incremented by 1.

8

SET F,RST F

(3) When the value of SD63 is "16", the annunciator numbers are deleted from SD64 to SD79
by the use of the RST instruction. If the annunciators whose numbers are not registered in
SD64 to SD79 are ON, these numbers will be registered.
If all annunciator numbers from SD64 to SD79 are turned OFF, the LED display device on
the front of the CPU module, or the "USER" LED, will be turned OFF.*2
*2: When using the Basic model QCPU, the "ERR." LED goes OFF.

[Operations which take place when SD63 is 16]
Turns F30 ON.
SD63
SD64
SD65
SD66

16
233
90
700

SD64
SD65
SD66

SD78 145
SD79 1027

Resets F90.
16
233
90
700

SD64
SD65
SD66

16
233
700
28

F number in
SD67 is stored.

SD77 145
SD78 1027
SD79
30

SD78 145
SD79 1027

F30, which was ON,
is stored in SD79.

Contents of SD63 and
those of SD64 to SD79
are not changed.

Operation Error
(1) There are no operation errors associated with the SET F

or RST F

instruction.

Program Example
(1) The following program turns annunciator F11 ON when X1 goes ON, and stores the value 11
at the special register (SD64 to SD79). Further, the program resets annunciator F11 if X2
goes ON, and deletes the value 11 from the special registers (SD64 to SD79).
[Ladder Mode]

[List Mode]
Step

Instruction

[Operation]
When X1 is ON

5-36

SD63
SD64
SD65
SD66

0
0
0
0

SD78
SD79

0
0

Adds 1

When X2 is ON

SD63
SD64
SD65
SD66
SD67

1
11
0
0
0

SD78
SD79

0
0

Subtracts 1

SD63
SD64
SD65
SD66
SD67

0
0
0
0
0

SD78
SD79

0
0

Device

PLS,PLF

5.3.8

Leading edge and trailing edge outputs (PLS,PLF)

1
PLS,PLF

Basic

High
performance

Process Redundant Universal

3

Command

PLS

PLS

D

PLF

D

4

Command

PLF

D

Setting
Data

Bit

5

: Pulse conversion device (bits)

Internal Devices

R, ZR

Word

2

J
Bit

\
Word

U

\G

Zn

Constants

Other
DY

––

D

6
7

Function
PLS

8

(1) Turns ON the designated device when the execution command is turned OFF ON, and
turns OFF the device in any other case the execution command is turned OFF ON (i.e., at
ON ON, ON OFF or OFF OFF of the execution command).

ON
X5 OFF

X5

ON

M0

PLS

M0 OFF
1 scan

1 scan

(2) If the RUN/STOP key switch is changed from RUN to STOP after the execution of the PLS
instruction, the PLS instruction will not be executed again even if the switch is set back to
RUN.
X0

Operating the
RUN/STOP
key switch of
CPU module
Operating the
"STOP
RUN".
RUN/STOP key
switch of CPU module
LD X0 "RUN
STOP".
LD X0
PLS
PLS M0
M0
END

END 0
ON
X0 OFF

Operating the
RUN/STOP
key switch of
CPU module
"STOP
RUN".

M0

PLS

CPU operation
stop time

Operating the
RUN/STOP
key switch of
CPU module
"RUN
STOP".
END

0

LD X0
PLS M0

CPU operation
stop time

ON

M0 OFF
1 scan of PLS M0

5-37

5.3 Output Instructions
5.3.8 Leading edge and trailing edge outputs (PLS,PLF)

When there is one PLS instruction for the device designated by D during one scan, the
specified device turns ON one scan.
See Section 3.9 for the operation to be performed when the PLS instruction for the same
device is executed more than once during one scan.

PLS,PLF

(3) When designating a latch relay (L) for the execution command and turning the power supply
OFF to ON with the latch relay ON, the execution command turns OFF to ON at the first
scan, executing the PLS instruction and turning ON the designated device.
The device turned ON at the first scan after power-ON turns OFF at the next PLS instruction.

PLF
(1) Turns ON the designated device when the execution command is turned ON OFF, and
turns OFF the device in any other case the execution command is turned ON OFF (i.e., at
OFF OFF, OFF ON or ON ON of the execution command).
When there is one PLF instruction for the device designated by D during one scan, the
specified device turns ON one scan.
See Section 3.9 for the operation to be performed when the PLF instruction for the same device
is executed more than once during one scan.
ON
X5 OFF

X5
PLF

ON

M0
M0 OFF
1 scan

1 scan

(2) If the RUN/STOP key switch is changed from RUN to STOP after the execution of the PLF
instruction, the PLF instruction will not be executed again even if the switch is set back to
RUN.

Note that the device designated by D may remain ON for more than one scan if
the PLS or PLF instruction is jumped by the CJ instruction or if the executed
subroutine program was not called by the CALL instruction.

Operation Error
(1) There are no operation errors associated with the PLS or PLF instruction.

Program Example
(1) The following program executes the PLS instruction when X9 goes ON.
[Ladder Mode]

[List Mode]
Step

[Timing Chart]
ON
X9 OFF
ON
M9 OFF

5-38

1 scan

Instruction

Device

PLS,PLF

(2) The following program executes the PLF instruction when X9 goes OFF.
[Ladder Mode]

1

[List Mode]
Step

Instruction

Device

2
3

[Timing Chart]
ON
X9 OFF

4

ON
M9 OFF
1 scan

5
6
7
8

5.3 Output Instructions
5.3.8 Leading edge and trailing edge outputs (PLS,PLF)

5-39

FF

5.3.9

Bit device output reverse (FF)

FF

Basic

High
performance

Process Redundant Universal

Command

FF

FF

D

Setting
Data

D

: Device number of the device to be reversed (bits)

Internal Devices
Bit

Word

R, ZR

J

\

Bit

U

Word

Zn

\G

Constants

Other
DY

––

D

Function
(1) Reverses the output status of the device designated by
turned OFF ON.

D

when the execution command is

Device Status

Device
Bit device

Bit designated for word device

Prior to FF Execution

After FF Execution

OFF

ON

ON

OFF

0

1

1

0

Operation Error
(1) There are no operation errors associated with the FF instruction.

Program Example
(1) The following program reverses the output of Y10 when X9 goes ON.
[Ladder Mode]

[List Mode]
Step

[Timing Chart]
ON
X9

OFF

Y10

OFF

ON

5-40

Instruction

Device

FF

(2) The following program reverses b10 (bit 10) of D10 when X0 goes ON.
[Ladder Mode]

[List Mode]
Step

1
Instruction

Device

2
3

[Timing Chart]
ON
X0

D10 of b10

OFF

4
0

1

0

5
6
7
8

5.3 Output Instructions
5.3.9 Bit device output reverse (FF)

5-41

DELTA(P)

5.3.10

Pulse conversions of direct outputs (DELTA(P))

DELTA(P)

Basic

High
performance

Process Redundant Universal

Command

DELTA

DELTA

D

DELTAP

D

Command

DELTAP
D

: Bit for which pulse conversion is to be conducted (bits)

Internal Devices

Setting
Data

Bit

Word

J

R, ZR

Bit

\

U

Word

\G

Zn

Constants

Other
DY

––

D

Function
(1) Conducts pulse output of direct access output (DY) designated by

D

.

If DELTA DY0 has been designated, the resulting operation will be identical to the ladder
shown below, which uses the SET/RST instructions.
[Ladder using the DELTA instruction]
X100

[Ladder using the SET/RST instructions]
X100

DELTA DY0

SET

DY0

RST

DY0

[Operation]
END processing

DELTA DY0

DELTA DY0

ON
X100 OFF
ON

ON

DY0 OFF

(2) The DELTA (P) instruction is used by commands for leading edge execution for an intelligent
function module.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• A direct access output number designated by
range.

5-42

D

has exceeded the CPU module output
(Error code: 4101)

DELTA(P)

Program Example

1

(1) The following program presets CH1 of the AD61 mounted at slot 0 of the main base unit,
when X20 goes ON.
[Ladder Mode]
Stores preset value (0) at addresses 1 and 2
of the AD61 buffer memory.

2
3

Outputs the preset command.

4
[List Mode]
Step

5
Instruction

Device

6
7
8

5.3 Output Instructions
5.3.10 Pulse conversions of direct outputs (DELTA(P))

5-43

SFT(P)

5.4 Shift Instructions
5.4.1

Bit device shifts (SFT(P))

SFT(P)

Basic

High
performance

Process Redundant Universal

Command

SFT

SFT

D

SFTP

D

Command

SFTP
D

Setting
Data

: Device number to shift (bits)

Internal Devices
Bit

J

R, ZR

Word

\

Bit

U

Word

Zn

\G

Other
DY

––

(Other than T, C)

D

Constants

Function
(1) When bit device is used
(a) Shifts to a device designated by

D

the ON/OFF status of the device immediately prior

to the one designated by D , and turns the prior device OFF.
For example, if M11 has been designated by the SFT instruction, when the SFT
instruction is executed, it will shift the ON/OFF status of M10 to M11, and turn M10 OFF.
(b) Turn the first device to be shifted ON with the SET instruction.
(c) When the SFT and SFTP are to be used consecutively, the program starts from the
device with the larger number.
Shift range
M0

Shift input
SFTP

M14

M15 M14 M13 M12 M11 M10 M9 M8
0
0
0
0
1
1 0 X02 ON
(1) 0
0

(2) 0
SFTP

SFTP

0

0

0

1

0

M13

M12

0

After the 1st shift input

1

0

After the 2nd shift input

1

0

X02 ON

0

After the 3rd shift input

0

After the 4th shift input

0

After the 5th shift input

1
0

(3) 0

0

0

1

0

0

(4) 0

0

0

1

0

1

0

(5) 0
SFTP

0

1

0

1

0

M11
(6) 0

1

0

1

0

0

X2

1
0

SET

M10

Head device to shift

5-44

1
0

(7) 0

0

1

0

0

0

1

* At M8 to M15, "1" indicates ON and "0" indicates OFF.

SFT(P)

(2) When word device bit designation is used
the 1/0 status of the bit immediately prior to

1

the one designated by D , and turns the prior bit to 0.
For example, if D0.5 (bit 5 [b5] of D0) has been designated by the SFT instruction, when
the SFT instruction is executed, it will shift the 1/0 status of b4 of D0 to b5, and turn b4
to 0.

2

(a) Shifts to a bit in the device designated by

D

b5 b4 to b0
b15
to
Before the
0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1
execution of shift
0
D0
After the
0 1 0 0 1 0 0 0 1 1 1 0 0 0 0 1
execution of shift

3
4
5

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU only.)
(Error code: 4101)

6
7
8

5.4 Shift Instructions
5.4.1 Bit device shifts (SFT(P))

5-45

SFT(P)

Program Example
(1) The following program shifts Y57 to Y5B when X8 goes ON.
[Ladder Mode]

Executes shift for Y57 to Y5B when X8 goes
ON.
Start programming from the device having
a large number.

Turns Y57 ON when X7 goes ON.

[Timing Chart]

[List Mode]

ON
X8

Step

OFF
ON

X7

OFF
ON

Y57

OFF
ON

Y58

OFF
ON

Y59

OFF
ON

Y5A

OFF
ON

Y5B

5-46

OFF

Instruction

Device

MC,MCR

5.5 Master Control Instructions
1

5.5.1

Setting and resetting the master control (MC,MCR)

2
MC,MCR

Basic

High
performance

Process Redundant Universal

4

Command

MC

n

MC

n

D

D

5

Master control ladder

MCR

n

MCR

n

: Nesting (N0 to N14) (Nesting)

D

: Device number to be turned ON (bits)

Internal Devices

Setting
Data

Bit

Word

J

R, ZR

n

\

Bit

U

Word

Zn

\G

––

Constants

6
Other
N

––
––

D

––
––

A ladder using the master control is as follows:
Ladder as it actually operates

Ladder as displayed in GPP ladder mode
X0
MC

n1

MC

M0
n1

M0
X1 X3 M7

n1

Y47
M5

M0

M0
X1 X3 M7
Y47
M5

Y4F
X6 X4

Y4F

Executed
only when
X0 is ON.

X6 X4

MCR

MCR

n1

X0F

n1

XF
Y10

Y40

Remark
Inputting of contacts on the vertical bus is not necessary when programming in the
write mode of a peripheral device.
These will be automatically displayed when the "conversion" operation is
conducted after the creation of the ladder and then "read" mode is set.

5-47

8

5.5 Master Control Instructions
5.5.1 Setting and resetting the master control (MC,MCR)

The master control instruction is used to enable the creation of highly efficient ladder switching
sequence programs, through the opening and closing of a common bus for ladders.

X0

7

DY

Function

n1

3

MC,MCR

MC
(1) If the execution command of the MC instruction is ON when master control is started, the
result of the operation from the MC instruction to the MCR instruction will be exactly as the
instruction (ladder) shows.
If the execution command of the MC instruction is OFF, the result of the operation from the
MC instruction to the MCR instruction will be as shown below:
Device

Device Status

High speed timer

Count value goes to 0, coils and contacts all go OFF.

Low speed timer
High speed retentive timer

Coils go OFF, but counter values and contacts all maintain

Low speed retentive timer

current status.

Counter
Devices in OUT instruction

All turned OFF

SET, RST
SFT

Devices in the following instructions:

Basic,

Maintain current status

Application

(2) Even when the MC instruction is OFF, instructions from the MC instruction to the MCR
instruction will be executed, so scan time will not be shortened.

When a ladder with master control contains instructions that do not require any
contact instruction (such as FOR to NEXT, EI, DI instructions), the CPU module
executes these instructions regardless of the ON/OFF status of the MC instruction
execution command.

(3) By changing the device designated by
number as often as desired.
(4) Coils from devices designated by

D

D

, the MC instruction can use the same nesting (N)

are turned ON when the MC instruction is ON.

Further, using these same devices with the OUT instruction or other instructions will cause
them to become double coils, so devices designated by
instructions.

D

should not be used within other

MCR
(1) This is the instruction for recovery from the master control, and indicates the end of the
master control range of operation.
(2) Do not place contact instructions before the MCR instruction.
(3) Use the MC instruction and MCR instruction of the same nesting number as a set.
However, when the MCR instructions are nested in one place, all master controls can be
terminated with the lowest nesting (N) number.
(Refer to the "Precautions for nesting" in the program example.)

Operation Error
(1) There are no operation errors associated with the MC or MCR instruction.

5-48

MC,MCR

Program Example

1

The master control instruction can be used in nesting. The different master control regions are
distinguished by nesting (N). Nesting can be performed from N0 to N14.
The use of nesting enables the creation of ladders which successively limit the execution
condition of the program.

3

A ladder using nesting would appear as shown below:
[Ladder as displayed in the GPP ladder mode]
A

MC N0 M15

NO M15

B

4

A
MC N0 M15

B

MC N2 M17

C

MCR N2

5

Executed
when A and
B are ON.

6

MC N2 M17

N2 M17

N2 M17

Executed
when A is ON.
MC N1 M16

N1 M16

N1 M16

C

[Ladder as it actually operates]

NO M15

MC N1 M16

2

Executed
when A, B
and C are ON.

7
8

MCR N2
Executed
when A and
B are ON.

MCR N1

MCR N1

MCR N0

MCR N0
Not related
to the status
of A, B or C.

5-49

5.5 Master Control Instructions
5.5.1 Setting and resetting the master control (MC,MCR)

Executed
when A is ON.

MC,MCR

Cautions when Using Nesting Architecture
(1) Nesting can be used up to 15 times (N0 to N14)
When using nesting, nests should be inserted from the lower to higher nesting number (N)
with the MC instruction, and from the higher to the lower order with the MCR instruction.
If this order is reversed, there will be no nesting architecture, and the CPU module will not be
capable of performing correct operations. For example, if nesting is designated in the order
N1 to N0 by the MC instruction, and also designated in the N1 to N0 order by the MCR
instruction, the vertical bus will intersect and a correct master control ladder will not be
produced.
[Ladder as displayed in the GPP ladder mode]
A
N1

[Ladder as it actually operates]
A

MC N1 M15

M15

N1

MC N1 M15

M15

B
MC N0 M16
N0

MC N0 M16
N0

M16

M16

MCR N1

MCR N1

MCR N0

MCR N0

(2) If the nesting architecture results in MCR instructions concentrated in one location, all
master controls can be terminated by use of just the lowest nesting number (N).
X1

X1
MC NO M15
NO

M15

MC NO M15
NO

X2

X2

MC N1 M16
N1

M16

N1

X3
N2

M17

MCR N2
MCR N1
MCR N0

5-50

MC N1 M16

M16

X3

MC N2 M17
N2

M15

MC N2 M17

M17

MCR N0

FEND

5.6 Termination Instructions
1

5.6.1

End main routine program (FEND)

2
FEND

Basic

High
performance

Process Redundant Universal

3
4

FEND

FEND

5
Setting
Data

Internal Devices
Bit

Word

R, ZR

J
Bit

\

U

Word

––

\G

Zn

Constants

Other

––

6
7

Function
(1) The FEND instruction is used in cases where the CJ instruction or other instructions are
used to cause a branch in the sequence program operations, and in cases where the main
routine program is to be split from a subroutine program or an interrupt program.

8

(2) Execution of the FEND instruction will cause the CPU module to terminate the program it
was executing.

(Peripheral devices continue to display ladders until encountering the END instruction.)
0

Operation
performed
when the CJ
instruction is
not executed

Main routine
program
CJ P
Main routine
program
FEND

P

Main routine
program
FEND

CALL P
Jump caused
by the CJ instruction
Operation
performed
when the CJ
instruction is
executed

Main routine
program
FEND

P

Subroutine
program

I
Interrupt program
END

END
(a) When the CJ instruction is used

(b) When there are subroutine and
interrupt programs

5-51

5.6 Termination Instructions
5.6.1 End main routine program (FEND)

(3) Even sequence programs following the FEND instruction can be displayed in ladder display
at a peripheral device.

FEND

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The FEND instruction is executed after the execution of the CALL, FCALL, ECALL, or
EFCALL instruction, and before the execution of the RET instruction.
(Error code: 4211)
• The FEND instruction is executed after the execution of the FOR instruction, and before
the execution of the NEXT instruction.
(Error code: 4200)
• The FEND instruction is executed during an interrupt program, and before the execution
of the IRET instruction.
(Error code: 4221)
• The FEND instruction is executed between the CHKCIR and CHKEND instructions.
(Error code: 4230)
• The FEND instruction is executed between the IX and IXEND instructions.
(Error code: 4231)

Program Example
(1) The following program uses the CJ instruction.
[Ladder Mode]

When XB is ON, the program jumps to
label P23 and the steps that follow P23
are executed.
Executed when XB is OFF.

Indicates the termination of the sequence
program to be executed when XB is OFF.

[List Mode]
Step

5-52

Instruction

Device

END

5.6.2

End sequence program (END)

1
END

Basic

High
performance

Process Redundant Universal

2
3
4
5

END

END

6
Setting
Data

Internal Devices
Bit

Word

J

R, ZR

Bit

––

\

U

Word

\G

Zn

Constants

Other

7

––

Function

8

(1) Indicates termination of programs, including main routine program, subroutine program, and
interrupt programs.

0

Sequence program

END

(2) The END instruction cannot be used during the execution of the main sequence program.
If it is necessary to perform END processing during the execution of a program, use the
FEND instruction.
(3) When programming in the ladder mode of a peripheral device, it is not necessary to input the
END instruction.

5-53

5.6 Termination Instructions
5.6.2 End sequence program (END)

Execution of the END instruction will cause the CPU module to terminate the program that
was being executed.

END

(4) The use of the END and FEND instructions is broken down as follows for main routine
programs, subroutine programs, and interrupt programs:
Main routine program
FEND

(FEND instruction is necessary.)

Subroutine program

Main sequence
program area

Interrupt program
END

(END instruction is necessary.)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The END instruction was executed before the execution of the RET instruction and after
the execution of the CALL, FCALL, ECALL, or EFCALL instruction.
(Error code: 4211)
• The END instruction was executed before the execution of the NEXT instruction and after
the execution of the FOR instruction.
(Error code: 4200)
• The END instruction was executed during an interrupt program prior to the execution of
the IRET instruction.
(Error code: 4221)
• The END instruction was executed within the CHKCIR to CHKEND instruction loop.
(Error code: 4230)
• The END instruction was executed within the IX to IXEND instruction loop.
(Error code: 4231)

5-54

STOP

5.7 Other instructions
5.7.1

1
Sequence program stop (STOP)

2

STOP

Basic

High
performance

Process Redundant Universal

3
4

Command

STOP

STOP

5
Setting
Data

Internal Devices
Bit

Word

R, ZR

J
Bit

\

U

Word

––

Zn

\G

Constants

Other

––

6
7

Function
(1) Resets the output (Y) and stops the CPU module operation when the execution command is
turned ON.

8

(The same result will take place if the RUN/STOP (key) switch is turned to the STOP
setting.)

b15 to b12 b11 to

SD203

b8 b7

to

b4 b3

to

b0

0 0 1 1
Sets value "3".

(3) In order to restart CPU module operations after the execution of the STOP instruction, return
the RUN/STOP key switch, which has been changed from RUN to STOP, back to the RUN
position.

5-55

5.7 Other instructions
5.7.1 Sequence program stop (STOP)

(2) Execution of the STOP instruction will cause the value of b4 to b7 of the special register
SD203 to become "3".

STOP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The STOP instruction was executed before the execution of the RET instruction and after
the execution of the CALL/FCALL/ECALL/EFCALL/XCALL instruction.
(Error code: 4211)
• The STOP instruction was executed before the execution of the NEXT instruction and
after the execution of the FOR instruction.
(Error code: 4200)
• The STOP instruction was executed during an interrupt program prior to the execution of
the IRET instruction.
(Error code: 4221)
• The STOP instruction was executed within the CHKCIR to CHKEND instruction loop.
(Error code: 4230)
• The STOP instruction was executed within the IX to IXEND instruction loop.
(Error code: 4231)
• The STOP instruction was executed during the fixed scan execution type program.
(For the Universal model QCPU only)
(Error code: 4223)

Program Example
(1) The following program stops the CPU module when X8 goes ON.
[Ladder Mode]
Stops the programmable controller when X8 goes ON.

Sequence program

[List Mode]
Step

5-56

Instruction

Device

NOP,NOPLF,PAGE n

5.7.2

No operations (NOP,NOPLF,PAGE n)

1

NOP,NOPLF,PAGE n

Basic

High
performance

Process Redundant Universal

2
3

In the ladder display, NOP is not displayed.
Command

NOP

NOP

4

NOPLF

NOPLF

PAGE n

PAGE n

Setting
Data

Internal Devices
Bit

Word

R, ZR

J
Bit

––

\

U

Word

\G

Zn

Constants

5

Other

––

6
7

Function

8

NOP
(1) This is a no operation instruction that has no impact on any operations up to that point.

(a) To insert space for sequence program debugging.
(b) To delete an instruction without having to change the number of steps. (Replace the
instruction with NOP.)
(c) To temporarily delete an instruction.

NOPLF
(1) This is a no operation instruction that has no impact on any operations up to that point.
(2) The NOPLF instruction is used when printing from a peripheral device to force a page
change at any desired location.
(a) When printing ladders
• A page break will be inserted between ladder blocks with the presence of the NOPLF
instruction.
• The ladder cannot be displayed correctly if an NOPLF instruction is inserted in the
midst of a ladder block.
Do not insert an NOPLF instruction in the midst of a ladder block.
(b) When printing instruction lists
• The page will be changed after the printing of the NOPLF instruction.
(3) Refer to the Operating Manual for the peripheral device in use for details of printouts from
peripheral devices.

5-57

5.7 Other instructions
5.7.2 No operations (NOP,NOPLF,PAGE n)

(2) The NOP instruction is used in the following cases:

NOP,NOPLF,PAGE n

PAGE n
(1) This is a no operation instruction that has no impact on any operations up to that point.
(2) No processing is performed at peripheral devices with this instruction.

Operation Error
(1) There are no errors associated with the NOP, NOPLF, or PAGE instruction.

Program Example
NOP
(1) Contact closed.... Deletes the AND or ANI instruction.
[Ladder Mode]

[List Mode]

Before change
Step

Instruction

Device

Step

Instruction

Device

Changing to NOP

After change

(2) Contact closed.... LD, LDI changed to NOP. (Note carefully that changing the LD and LDI
instructions to NOP completely changes the nature of the ladder.)
[Ladder Mode]

[List Mode]

Before change
Step
Step

Instruction
Instruction

Device
Device

Step

Instruction

Device

Changing to NOP

After change

5-58

NOP,NOPLF,PAGE n
[Ladder Mode]

[List Mode]

1

Before change
Step

Instruction

Device

2
Changing to LD T3
Changing to NOP

3
4

After change

Step

Instruction

Device

5
6
7

NOPLF
[Ladder Mode]

[List Mode]
Step

Instruction

8

Device

5.7 Other instructions
5.7.2 No operations (NOP,NOPLF,PAGE n)

5-59

NOP,NOPLF,PAGE n
• Printing the ladder will result in the following:

0

X0
MOV

K1

D30

MOV

K2

D40

5

NOPLF instruction, inserted as a delimiter
of ladder blocks, causes print out page to
be changed forcibly.

NOPLF

X1
6

Y40

8

END

• Printing an instruction list with the NOPLF instruction will result in the following:
0

LD

X0

1

MOV

K1

D30

3

MOV

K2

D40

5

NOPLF

6

LD

X1

7

OUT

Y40

8

END

Changes print output page
after printing NOPLF.

PAGE n
[Ladder Mode]

[List Mode]
Step

NOP

5-60

Instruction

Device

6

7

BASIC
INSTRUCTIONS

7
7
7
7
6

Category
Comparison operation
instruction
Arithmetic operation instruction

Processing Details
Compares data to data.
Adds, subtracts, multiplies, divides, increments, or
decrements data with other data.

Section

Section 6.2

Converts data types.

Section 6.3

Data transfer instruction

Transmits designated data.

Section 6.4

Program branch instruction

Program jumps.

Section 6.5

Program run control instruction

Enables and disables program interrupts.

Section 6.6

Refreshes bit devices.

Section 6.7

Other convenient instructions

Up/down counters, teaching timers, special function timers,
rotary table shortest direction controls, etc.

7

Section 6.1

Data conversion instructions

I/O refresh instruction

7

Reference

Section 6.8

6-1

=,<>,>,<=,<,>=

6.1 Comparison Operation Instructions
6.1.1

BIN 16-bit data comparisons (=,<>,>,<=,<,>=)

=,<>,>,<=,<,>=

Basic

High
performance

indicates an instruction symbol of

LD

S1

S2

S1

S2

S1

S2

Process Redundant Universal

/

/

/

/

.

/

Command

AND
Command

Command

OR

,

S1

Setting
Data

S2

: Data for comparison or head number of the devices where the data for comparison is stored (BIN 16 bits)

Internal Devices
Bit

Word

R, ZR

J
Bit

\

U

Word

Zn

\G

Constants
K, H

Other

S1

––

S2

––

Function
(1) Treats BIN 16-bit data from device designated by
designated by

S2

S1

and BIN 16-bit data from device

as an a normally-open contact, and performs comparison operation.

(2) The results of the comparison operations for the individual instructions are as follows:
Instruction
Symbol in
=
<>
>
<=
<
>=

Condition
S2

=

>

S1

S1

<>

S2

Continuity
S2

S1

<

S2

S2

Instruction
Symbol in
=

S1
S2

S1

S1

Comparison
Operation Result

>
<=
<
>=

Condition
S2

S1
S2

Comparison
Operation Result

=

S1
S2

S1

Non-continuity
S1

>

S2

S1

S1

S2

<

S2

(3) When S1 and S2 are assigned by a hexadecimal constant and the numerical value (8 to F)
whose most significant bit (b15) is "1" is designated as a constant, the value is considered
as a negative BIN value in comparison operation.

6-2

=,<>,>,<=,<,>=

Operation Error

1

(1) There are no operation errors associated with the

,

,

,

,

, or

instruction.

2

Program Example
(1) The following program compares the data at X0 to XF with the data at D3, and turns Y33 ON
if the data is identical.
[Ladder Mode]

3

[List Mode]
Step

Instruction

4

Device

4
(2) The following program compares BIN value K100 to the data at D3, and establishes
continuity if the data in D3 is something other than 100.
[Ladder Mode]

6

[List Mode]
Step

Instruction

Device

7
8

(3) The following program compares the BIN value 100 with the data at D3, and establishes
continuity if the D3 data is less than 100.
[Ladder Mode]

[List Mode]
Instruction

Device

(4) The following program compares the data in D0 and D3, and if the data in D0 is equal to or
less than the data in D3, establishes continuity.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

6-3

6.1 Comparison Operation Instructions
6.1.1 BIN 16-bit data comparisons (=,<>,>,<=,<,>=)

Step

D=,D<>,D>,D<=,D<,D>=

6.1.2

BIN 32-bit data comparisons (D=,D<>,D>,D<=,D<,D>=)

D=,D<>,D>,D<=,D<,D>=

Basic

High
performance

indicates an instruction symbol of D / D

LD

S1

S2

S1

S2

S1

S2

Process Redundant Universal

/D /D

/D

/ D

.

Command

AND

Command

Command

OR

,

S1

Setting
Data

S2

: Data for comparison or head number of the devices where the data for comparison is stored (BIN 32 bits)

Internal Devices
Bit

Word

R, ZR

J
Bit

\

U

Word

Zn

\G

Constants
K, H

Other

S1

––

S2

––

Function
(1) Treats BIN 32-bit data from device designated by
designated by

S2

S1

and BIN 32-bit data from device

as an a normally-open contact, and performs comparison operation.

(2) The results of the comparison operations for the individual instructions are as follows:
Instruction
Symbol in
D=
D<>
D>
D<=
D<
D>=

Condition
S2

=

>

S1

S1

D<>

S2

Continuity
S2

S1

<

S2

S2

Instruction
Symbol in
D=

S1
S2

S1

S1

Comparison
Operation Result

D>
D<=
D<
D>=

Condition
S2

S1
S2

Comparison
Operation Result

=

S1
S2

S1

Non-continuity
S1

>

S2

S1

S1

S2

<

S2

(3) When S1 and S2 are assigned by a hexadecimal constant and the numerical value (8 to F)
whose most significant bit (b31) is "1" is designated as a constant, the value is considered
as a negative BIN value in comparison operation.
(4) Data used for comparison should be designated by a 32-bit instruction (DMOV instruction,
etc.).
If designation is made with a 16-bit instruction (MOV instruction, etc.), comparisons of large
and small values cannot be performed correctly.

6-4

D=,D<>,D>,D<=,D<,D>=

Operation Error

1

(1) There are no operation errors associated with the D , D
instruction.

,D ,D

,D

or D

2

Program Example

3

(1) The following program compares the data at X0 to X1F with the data at D3 and D4, and
turns Y33 ON, if the data at X0 to X1F and the data at D3 and D4 match.
[Ladder Mode]

4

[List Mode]
Step

Instruction

Device

4
6

(2) The following program compares BIN value K38000 to the data at D3, and D4, and
establishes continuity if the data in D3 and D4 is something other than 38000.
[Ladder Mode]

[List Mode]
Step

Instruction

7

Device

8

[Ladder Mode]

[List Mode]
Instruction

Step

Device

(4) The following program compares the data in D0 and D1 with the data in D3 and D4, and
establishes continuity if the data in D0 and D1 is equal to or less than the data in D3 and D4.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

6-5

6.1 Comparison Operation Instructions
6.1.2 BIN 32-bit data comparisons (D=,D<>,D>,D<=,D<,D>=)

(3) The following program compares BIN value K 80000 to the data at D3 and D4, and
establishes continuity if the data in D3 and D4 is less than 80000.

E=,E<>,E>,E<=,E<,E>=

6.1.3

Floating decimal point data comparisons (Single precision)
(E=,E<>,E>,E<=,E<,E>=)

E=,E<>,E>,E<=,E<,E>=

Ver.
Basic

High
performance

Process Redundant Universal

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

indicates an instruction symbol of E / E

LD

S1

S2

S1

S2

S1

S2

/E /E

/E

.

/ E

Command

AND

Command Command

OR

,

S1

S2

: Data for comparison or head number of the devices where the data for comparison is stored
(real number)

Setting
Data

Internal Devices
Bit

Word

J

R, ZR

\

Bit

Word

U

Zn

\G

Constants
E

Other

S1

––

––

––

––

S2

––

––

––

––

*1:Available only in multiple Universal model QCPU

(1) The 32-bit floating decimal point data from device designated by S1 and 32-bit floating decimal
point data from device designated by S2 as A normally-open contact, and performs comparison
operation.
(2) The results of the comparison operations for the individual instructions are as follows:
Instruction
Symbol in
E=
E<>
E>
E<=
E<
E>=

S2

=

>

<

S1

Symbol in
E=

S1

E<>
E>

S2

Continuity

E<=

S2

S1

S1

Operation Result

S2

S1

S1

Instruction

Comparison

Condition

E<

S2

E>=

S2

Condition
S2

S1
S2

Comparison
Operation Result

=

S1
S2

S1

Non-continuity
S1

>

S2

S1

S1

S2

<

S2

Note that use of the E= instruction can on occasion result in situations where
errors cause the two values to not be equal.
Example

X0
EMOV E1.23 D0

E

D0

D2

E*

D0

E4.56 D2

E/

D2

E4.56 D2
M0

Two values may not be equal.

6-6

E=,E<>,E>,E<=,E<,E>=

Operation Error

1

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is 0. *1
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU)
(Error code: 4100)
*1: There are CPU modules that will not result in an operation error if
Section 3.2.4.

0 is specified. For details, refer to

• The value of the specified device is outside the following range. (For the Universal model
QCPU)
0, 2 -126

| value of specified device | < 2128

3
4

(Error code: 4140)

• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU only)
(Error code: 4140)

Program Example

4
6

(1) The following program compares 32-bit floating decimal point real number data at D0 and
D1 to 32-bit floating decimal point real number data at D3 and D4.
[Ladder Mode]

2

[List Mode]
Step

Instruction

7

Device

8

[Ladder Mode]

[List Mode]
Step

Instruction

Device

(3) The following program compares 32-bit floating decimal point real number data at D0 and
D1 to 32-bit floating decimal point real number data at D3 and D4.
[Ladder Mode]

[List Mode]
Instruction

Step

Device

(4) The following program compares the 32-bit floating decimal point data at D0 and D1 to the
floating decimal point real number 1.23.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

6-7

6.1 Comparison Operation Instructions
6.1.3 Floating decimal point data comparisons (Single precision) (E=,E<>,E>,E<=,E<,E>=)

(2) The following program compares the floating decimal point real number 1.23 to the 32-bit
floating decimal point real number data at D3 and D4.

ED=,ED<>,ED>,ED<=,ED<,ED>=

6.1.4

Floating decimal point data comparisons (Double precision)
(ED=,ED<>,ED>,ED<=,ED<,ED>=)

ED=,ED<>,ED>,ED<=,ED<,ED>=

High
performance

Basic

/ED

indicates an instruction symbol of ED

LD

S1

S2

S1

S2

S1

S2

Process Redundant Universal

/ED

/E

/E

/E

Command

AND
Command

Command

OR

,

S1

S2

: Data for comparison or head number of the devices where the data for comparison is stored
(real number)

Setting
Data

Internal Devices
Bit

Word

R, ZR

J
Bit

\
Word

U

Constants
$

Zn

\G

Other

S1

––

––

––

––

S2

––

––

––

––

Function
(1) The 64-bit floating decimal point real number from device designated by
decimal point real number from device designated by
performs comparison operation.

S2

S1

and 64-bit floating

as A normally-open contact, and

(2) The results of the comparison operations for the individual instructions are as follows:
Instruction
Symbol in
ED=
ED<>
ED>
ED<=
ED<
ED>=

6-8

Condition
S2

=

S1

S1

>

S1

<

Continuity

S2

S2

Symbol in

ED<>

S2

S2

Instruction

ED=

S1

S2

S1

S1

Comparison
Operation Result

ED>
ED<=
ED<
ED>=

Condition
S1

S2

Comparison
Operation Result

S2

=

S1

S1

S2

Non-continuity
S1

>

S1

S1

S2

S2

<

S2

ED=,ED<>,ED>,ED<=,ED<,ED>=

Operation Error

1

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range:
0,2 -1022

| value of specified device | <

• The value of the designated device is

(Error code: 4140)

0.

(Error code: 4140)

Program Example

3
4

(1) The following program compares 64-bit floating decimal point real number data at D0 to D3
with 64-bit floating decimal point real number data at D4 to D7.
[Ladder Mode]

2

21024

[List Mode]
Step

Instruction

Device

4
6
7

(2) The following program compares the floating decimal point real number 1.23 with the 64-bit
floating decimal point real number data at D4 to D7.
[Ladder Mode]

[List Mode]
Instruction

Step

Device

[List Mode]
Instruction

Step

Device

(4) The following program compares the 64-bit floating decimal point data at D0 to D3 with the
floating decimal point real number 1.23.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

6-9

6.1 Comparison Operation Instructions
6.1.4 Floating decimal point data comparisons (Double precision) (ED=,ED<>,ED>,ED<=,ED<,ED>=)

(3) The following program compares 64-bit floating decimal point real number data at D0 to D3
with 64-bit floating decimal point real number data at D4 to D7.
[Ladder Mode]

8

ED=,ED<>,ED>,ED<=,ED<,ED>=

Caution
(1) Since the number of digits of the real number that can be input by GX Developer is up to 15
digits, the comparison with the real number whose number of significant digits is 16 or more
cannot be made by the instruction shown in this section.
When judging match/mismatch with the real number whose significant digits is 16 or more by
the instruction in this section, compare it with the approximate values of the real number to
be compared and judge by the sizes.
Example

When judging the match of E1.234567890123456+10 (Number of significant
digits is 16) and the double-precision floating-point data.

E1.23456789012345+10

E1.234567890123456+10

E1.23456789012346+10

Whether D0 to D3 is within this range is checked.(Values on boundaries are excluded.)

Example

When judging the mismatch of E1.234567890123456+10 (Number of significant
digits is 16) and the double-precision floating-point data.

E1.23456789012345+10

E1.234567890123456+10

E1.23456789012346+10

Whether D0 to D3 is within this range is checked.(Values on boundaries are included.)

6-10

$=,$<>,$>,$<=,$<,$>=

6.1.5

Character string data comparisons ($=,$<>,$>,$<=,$<,$>=)

1
$=,$<>,$>,$<=,$<,$>=

Basic

indicates an instruction symbol of $

LD

S1

S2

S1

S2

High
performance

/$

Process Redundant Universal

/$

/ $

/$

/ $

.

Command

3
4

Command

AND

2

4

Command

OR
S1

S2

6
S1

,

S2

: Data for comparison or head number of the devices where the data for comparison is stored
(character string)

Setting
Data

Internal Devices
Bit

Word

R, ZR

J

\

Bit

U

Word

\G

Constants
$

Zn

7
Other

S1

––

––

––

S2

––

––

––

(1) Compares the character string data designated by
designated by

S2

S1

with the character string data

as a normally-open contact.

(2) A comparison operation involves the character-by-character comparison of the ASCII code
of the first character in the character string.
(3) The character string data of S1 and S2 for comparison refers to the data stored at the range
from the designated device number to the device number where "00H" code is stored.
(a) If all character strings match, the comparison result will be matched.
S1
S1
S1

b15
b8
42H (B)
+1 44H (D)
+2 00H

b7
b0
41H (A)
43H (C)
45H (E)

"ABCDE"

Instruction Symbol in

S2
S2
S2

b15
b8 b7
b0
42H (B) 41H (A)
+1 44H (D) 43H (C)
45H (E)
+2 00H
"ABCDE"

Comparison Operation
Result

Instruction Symbol in

Comparison Operation
Result

$=

Continuity

$<=

Continuity

$<>

Non-continuity

$<

Non-continuity

$>

Non-continuity

$>=

Continuity

6-11

6.1 Comparison Operation Instructions
6.1.5 Character string data comparisons ($=,$<>,$>,$<=,$<,$>=)

Function

8

$=,$<>,$>,$<=,$<,$>=

(b) If the character strings are different, the character string with the larger character code
will be the larger.
b15
b8
42H (B)
S1 +1 44H (D)
S1 +2 00H
S1

b7
b0
41H (A)
43H (C)
46H (F)

b15
b8
42H (B)
S2 +1 44H (D)
S2 +2 00H
S2

"ABCDF"

"ABCDE"

Comparison Operation

Instruction Symbol in

b7
b0
41H (A)
43H (C)
45H (E)

Result

$=

Non-continuity

$<>
$>

Instruction Symbol in

Comparison Operation
Result

$<=

Non-continuity

Continuity

$<

Non-continuity

Continuity

$>=

Continuity

(c) If the character strings are different, the first different sized character code will
determine whether the character string is larger or smaller.
S1
S1
S1

b15
b8
32H (2)
+1 34H (4)
+2 00H

b7
b0
31H (1)
33H (3)
35H (5)

S2
S2
S2

b15
b8
32H (2)
+1 33H (3)
+2 00H

"12345"

"12435"

Comparison Operation

Instruction Symbol in

Result

Instruction Symbol in

Comparison Operation
Result

$=

Non-continuity

$<=

Continuity

$<>

Continuity

$<

Continuity

$>

Non-continuity

$>=

Non-continuity

(4) If the character strings designated by
longer character string will be larger.
b15
b8
32H (2)
S1 +1 34H (4)
S1 +2 36H (6)
S1 +3 00H
S1

b7
31H
33H
35H
37H

S1

b0
(1)
(3)
(5)
(7)

"1234567"
Instruction Symbol in

6-12

b7
b0
31H (1)
34H (4)
35H (5)

and

S2
S2
S2
S2

S2

are of different lengths, the data with the

b15
b8
32H (2)
+1 34H (4)
+2 36H (6)
00H
+3

b7
b0
31H (1)
33H (3)
35H (5)
00H

"123456"

Comparison Operation
Result

Instruction Symbol in

Comparison Operation
Result

$=

Non-continuity

$<=

Non-continuity

$<>

Continuity

$<

Non-continuity

$>

Continuity

$>=

Continuity

$=,$<>,$>,$<=,$<,$>=

Operation Error

1

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The code "00H" does not exist within the range of the relevant device, starting from the
device number designated by

S1

and

S2

.

2

(Error code: 4101)
(Error code: 4101)

3

The character string data comparison instruction checks the device range while
comparing the designated character string data. For this reason, if the "00H" code
does not exist in the relevant device range, the instruction outputs the comparison
result instead of returning an operation error when no match of characters is
detected.

4

• The character string of

Example

S1

and

$

S2

exceeds 16383 characters.

M0

D12287 D10
S1

If

S1

and

S2

6

S2

Data of S2

Data of S1
D12287
W0

4

B
00 H

D10
D11

A
C

Z
00 H

data are as shown above, the second character of

7

A
C
S1

does not

match with that of S2 , and the comparison result is expressed as S1 S2 (the
operation result is "non-conductive"). Though the "00H" code is not included

8

within the S1 device range, no operation error is returned, because the
no-match is detected at D12287, which is within the device range.

(1) The following program compares character strings stored following D0 and characters
following D10.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

(2) The following program compares the character string "ABCDEF" with the character string
stored following D10.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

6-13

6.1 Comparison Operation Instructions
6.1.5 Character string data comparisons ($=,$<>,$>,$<=,$<,$>=)

Program Example

$=,$<>,$>,$<=,$<,$>=

(3) The following program compares the character string stored following D10 with the character
string stored following D100.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

(4) The following program compares the character string stored following D200 with the
character string "12345".
[Ladder Mode]

[List Mode]
Step

6-14

Instruction

Device

BKCMP …,BKCMP … P

6.1.6

BIN block data comparisons (BKCMP … ,BKCMP … P)

1

BKCMP …,BKCMP … P

Basic

High
performance

Process Redundant Universal

2
3

indicates an instruction symbol of

/

/

/

/

.

/

Command

BKCMP

BKCMP

S1

S2

D

n

S1

S2

D

n

4

Command

BKCMP P

BKCMP

P

4
S1

: Data to be compared or head number of the devices where the data to be compared is stored (BIN 16 bits)

S2

: Head number of the devices where the comparison data is stored (BIN 16 bits)

D

: Head number of the devices where the comparison operation result will be stored (bits)

n

: Number of comparison data blocks (BIN 16 bits)

Internal Devices

Setting
Data

Bit

J

R, ZR

Word

Bit

\

U

Word

6
Constants
K, H

Zn

\G

Other

S1

––

––

S2

––

––

––

––

––

––

––

D

––

n

16-bit data the nth point from the device number designated by
from the device designated by

D

onward.
D

will be turned ON.

(b) If the comparison condition has not been met, the device designated by
turned OFF.

1
2

1234 (BIN)
5678 (BIN)
5000 (BIN)

S1
S1

(n 2)
(n 1)

7777 (BIN)
4321 (BIN)

1
2

5321 (BIN)
3399 (BIN)
5678 (BIN)

(n 2)
(n 1)

6543 (BIN)
1200 (BIN)

S2
S2
S2

n

with BIN

, and stores the result

S2

(a) If the comparison condition has been met, the device designated by

S1

S1

S2
S2

n

D

will be

Operation Results
OFF (0)
ON (1)
OFF (0)

D
D
D

1
2

D
D

(n 2)
(n 1)

ON
ON

n

(1)
(1)

(2) The comparison operation is conducted in 16-bit units.
(3) The constant designated by

S1

can be between

32768 and 32767 (BIN 16-bit data).
Operation Results

32000 (BIN)
4321 (BIN)
32000 (BIN)

S2
S2
S1

32000 (BIN)

S2
S2
S2

1
2
(n
(n

2)
1)

1234 (BIN)
5678 (BIN)

n

D
D
D

1
2

D
D

(n
(n

2)
1)

ON
OFF
ON

(1)
(0)
(1)

OFF
OFF

(0)
(0)

n

6-15

6.1 Comparison Operation Instructions
6.1.6 BIN block data comparisons (BKCMP … ,BKCMP … P)

(1) Compares BIN 16-bit data the nth point from the device number designated by

S1

8

––

Function

S1

7

BKCMP …,BKCMP … P

(4) The results of the comparison operations for the individual instructions are as follows:
Instruction

Condition

Symbols
BKCMP=

S2

BKCMP<>

=

S1

BKCMP<=

>

S1

BKCMP>=

Symbols
BKCMP=

S1

BKCMP<>
BKCMP>

S2

ON (1)

BKCMP<=

S2

S1

BKCMP<

Instruction

S2

S1

BKCMP>

Comparison
Operation Result

<

S1

BKCMP<

S2

BKCMP>=

S2

(5) If all comparison results stored n points from
signal) goes ON.

D

Comparison

Condition
S2

S1
S2

Operation Result

=

S1
S2

S1

OFF (0)
S1

>

S2

S1

S1

S2

<

S2

are ON (1), SM704 (block comparison

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The range of the device n points from a device designated by
relevant device.

S1

,

S2

• The device range for n points starting from the device designated by
device range for n points starting from the device designated by

D

or D exceeds the
(Error code: 4101)
S1

overlaps with the

.
(Error code: 4101)

• The device range for n points starting from the device designated by
device range for n points starting from the device designated by

D

S2

overlaps with the

.
(Error code: 4101)

Program Example
(1) The following program compares, when X20 is turned ON, the data stored at D100 to D103
with the data stored at R0 to R3 and stores the operation result into the area starting from
M10.
[Ladder Mode]

[List Mode]
Step

Device

Instruction

[Operation]
D100
D101
D102
D103

b15
1000
2000
3000
4000
D0

6-16

b0
(BIN)
(BIN)
(BIN)
(BIN)
4

R0
R1
R2
R3

b15
1000
2000
5000
4000

b0
(BIN)
(BIN)
(BIN)
(BIN)

M10
M11
M12
M13

ON
ON
OFF
ON

BKCMP …,BKCMP … P

(2) The following program compares, when X1C is turned ON, the constant K1000 with the data
stored at D10 to D13, and stores the operation result at b4 to b7 in D0.
[Ladder Mode]

[List Mode]
Instruction

Step

1

Device

2
3

[Operation]
D10
D11
D12
D13

b15
b0
1000 (BIN)

b15
2000
1000
1000
2222

b0
(BIN)
(BIN)
(BIN)
(BIN)

4
4

D0 before
operation

D0 after
operation

b15
b4
b7
b0
0 10000 1000 100000

6
b7
b15
b4
b0
0 10000 10100 10000

7

(3) The following program compares, when X20 is turned ON, the data at D10 to D12 with the
data at D30 to D32, and stores the operation result into the area starting from M100.
The following program transfers the character string "ALL ON" to D100 onward when all
devices from M100 onward have reached the 1 "ON" state.
[Ladder Mode]

[List Mode]
Instruction

Device

6.1 Comparison Operation Instructions
6.1.6 BIN block data comparisons (BKCMP … ,BKCMP … P)

Step

[Operation]
D10
D11
D12

b15
1234
5678
9876

b0
(BIN)
(BIN)
(BIN)

8

D30
D31
D32

b15
4321
5678
9999

b0
(BIN)
(BIN)
(BIN)

M100
M101
M102

b0
b15
b8 b7
D100 4CH (L) 41H (A)
D101 20H ( ) 4CH (L)
D102 4EH (N) 4FH (O)

ON
ON
ON

SM704
ON

$MOV

6-17

BKCMP …,BKCMP … P

6.1.7

BIN 32-bit block data comparisons
(DBKCMP … ,DBKCMP … P)
Ver.
High
performance

Basic

Process Redundant Universal

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.
QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

indicates an instruction symbol of

/

/

/

/

/

.

Command

DBKCMP

DBKCMP

S1

S2

D

n

S1

S2

D

n

Command

DBKCMP P

DBKCMP

S1

: Data to be compared or head number of the devices where the data to be compared are stored (BIN 32 bits)

S2

: Head number of the devices where the comparison data are stored (BIN 32 bits)

D

: Head number of the devices where the comparison operation result will be stored (bits)
: Number of comparison data blocks (BIN 16 bits)

n

Internal Devices

Setting
Data

P

Bit

Word

R, ZR

J

\

Bit

Word

U

Constants
K, H

Zn

\G

Other

S1

––

––

S2

––

––

––

––

––

––

––

D

––

n

––

Function
(1) This instruction compares BIN 32-bit data stored in n-point devices starting from the device
specified by

S1

with BIN 32-bit data stored in n-point devices starting from the device

specified by a constant and
and up.

S2

and then stores the result into the nth device specified by

(a) If the comparison condition has been met, the corresponding devices specified by
be turned on.

D

(b) If the comparison condition has not been met, the corresponding devices specified by
will be turned off.
b31
S1 ＋1,

S1

S1 ＋3,

S1 ＋2

S1 ＋5,

S1 ＋4

S1 ＋n 1, S1 ＋n 2

6-18

b0
1090 (BIN)
2080 (BIN)
5060 (BIN) n
1106 (BIN)

b31
S2 ＋1,

S2

S2 ＋3,

S2 ＋2

S2 ＋5,

S2 ＋4

S2 ＋n 1, S2 ＋n 2

b0
1000 (BIN)
2000 (BIN)
5060 (BIN)
1106 (BIN)

n

D
D ＋1
D ＋2

D

will

D

Operation result
OFF (0)
OFF (0)
n
ON (1)

D ＋n 1

ON

(1)

BKCMP …,BKCMP … P

(2) The comparison operation is executed in 32-bit units.
(3) The constant in the device specified by
(BIN 32-bit data).

S1

can be between
b31

b31
b0
S1 ＋1, S1 32800 (BIN)

S2 ＋1,

S2

S2 ＋3,

S2 ＋2

S2 ＋5,

S2 ＋4

2147483648 and 2147483647
b0

32700 (BIN)
40000 (BIN)
32800 (BIN)

D
D ＋1
D ＋2

n

S2 ＋n 1, S2 ＋n 2 2147400 (BIN)

(4)

Operation result
ON (1)
OFF (0)
n
ON (1)

D ＋n 1

OFF

(0)

D

specifies out of the device range of n-point devices starting from the device specified by

S1

and

S2

.

(5) The following table shows the results of the comparison operations for each individual
instruction.
Instruction
Symbols
DBKCMP=
DBKCMP<>
DBKCMP>
DBKCMP<=
DBKCMP<
DBKCMP>=

Condition
S2

=

>

S1

Operation Result

Symbols
DBKCMP=

S1

DBKCMP<>

S2

ON (1)
S2

S1

S1

Instruction

S2

S1

S1

Comparison

<

DBKCMP>
DBKCMP<=
DBKCMP<

S2

DBKCMP>=

S2

Condition

S2

=

>

6

S1

7

S2

S2

S1

S1

4

Operation Result

OFF (0)
S1

3

4

S2

S1

2

Comparison

S2

S1

1

<

8

S2

(6) If all comparison results stored into the devices starting from the device specified by D to
nth device are on(1), or one of the results is off(2), the special relays will be on or off in
accordance with the conditions as follows.

No.

Number

Initial execution/Scan

1

SM704

ON

2

SM716

3

SM717

4

SM718

Interrupt (other
than l45)/Fixed

Interrupt(l45)

scan execution

When results of comparison operations have a result of
off(0)
Initial execution/
Scan

Interrupt (other
than l45)/Fixed

Interrupt(l45)

scan execution

ON

ON

OFF

OFF

OFF

ON

––

––

OFF

––

––

––

ON

––

––

OFF

––

––

––

ON

––

––

OFF

In a standby program, a special relay depending on the caller program turns on or off.
(7) If the value specified by n is 0, the instruction will be not processed.

6-19

6.1 Comparison Operation Instructions
6.1.7 BIN 32-bit block data comparisons (DBKCMP … ,DBKCMP … P)

When all results of comparison operations are on(1)

BKCMP …,BKCMP … P

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• A negative value is specified for n.

(Error code: 4100)

• The range of the n-point devices starting from the device specified by S1 , S2 . or D
exceeds the specified device range.
(Error code: 4101)
• The range of the n-point devices starting from the device specified by
range of the n-point devices starting from the device specified by

S1

overlaps with the

.

D

(Error code: 4101)
• The range of the n-point devices starting from the device specified by
range of the n-point devices starting from the device specified by

S2

overlaps with the

.

D

(Error code: 4101)

Program Example
(1) The following program compares the value data stored at R0 to R5 with the value data
stored at D20 to D25, and then stores the operation result into Y0 to Y2, when M0 is turned
on,
[Ladder Mode]

[List Mode]
Device

Instruction

Step

[Operation]
b31
b0
R1,R0 -2147483000
0
R3,R2
R5,R4 2147483000

b31
b0
D21,D20 -2147483000
1
D23,D22
D25,D24 2147482999

Y0
Y1
Y2

OFF
ON
ON

(0)
(1)
(1)

(2) The following program compares the constant with the value data stored at D0 to D9, and
then stores the operation result into D10.5 to D10.9, when M0 is turned on,
[Ladder Mode]

[List Mode]
Instruction

Step

Device

[Operation]

b31

b0
-60000

6-20

b31
D1,D0
D3,D2
D5,D4
D7,D6
D9,D8

b0
-70000
50000
-32768
32767
0

D10.5
D10.6
D10.7
D10.8
D10.9

ON
OFF
OFF
OFF
OFF

(1)
(0)
(0)
(0)
(0)

BKCMP …,BKCMP … P

When certain bits are specified in a word device, bits other than the certain bits
that store the operation result do not change.
D10.F
Before execution 0

0

1

0

1

1

1

1

1

0

0

1

1

0

0

D10.0
0

D10.F
0

0

1

0

1

1

0

0

0

0

1

1

1

0

0

D10.0
0

After execution

2
3

No change

No change

(3) The following program compares the value data stored at D0 to D5 with the value data
stored at D10 to D15, and then stores the operation result into M20 to M22, when M0 is
turned on. Also, the program transfers the character string "ALL ON" to D100 and up when
all devices from M20 to M22 have reached the on status.
[Ladder Mode]

1

4
4

[List Mode]
Step

6

Device

Instruction

7
[Operation]
b31
b0
D1,D0 -2147483000
60000
D3,D2
D5,D4
-900000

8
b31
b0
D11,D10 -2147483000
60001
D13,D12
D15,D14
-899999

ON
ON
ON

(1)
(1)
(1)

SM704

ON

(1)

SM716
SM717
SM718

ON
OFF
OFF

(1)
(0)
(0)

6.1 Comparison Operation Instructions
6.1.7 BIN 32-bit block data comparisons (DBKCMP … ,DBKCMP … P)

When all operation results are on(1),
the special relays corresponding to
each program turn on(1).
(Since this program examples refer
to scan programs, SM704 and SM716
turn on(1), SM7171 and SM718 do not
change in the scan program)

M20
M21
M22

6-21

+(P),-(P)

6.2 Arithmetic Operation Instructions
6.2.1

BIN 16-bit addition and subtraction operations (+(P),-(P))

+(P),-(P)

Basic

When two data are set (

D

+

S

D

,

-

D

D

S

High
performance

Process Redundant Universal

)

indicates an instruction symbol of +/

.

Command

+,

S

D

S

D

Command

+P, P

P

Setting
Data

S

: Data for additing/subtracting or head number of the devices where the data for additing/subtracting is stored
(BIN 16 bits)

S1
D

: Head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits)

Internal Devices
Bit

Word

J

R, ZR

\

Bit

U

Word

Zn

\G

Constants
K, H

Other
––

S

––

D

––

Function
+
(1) Adds 16-bit BIN data designated by

D

to 16-bit BIN data designated by

result of the addition at the device designated by
D
b0
5678 (BIN)

S

and

D

b15

and stores the

.

S

b15

(2) Values for

D

S

D
b0

1234 (BIN)

can be designated between

b15

b0
6912 (BIN)

32768 and 32767 (BIN, 16 bits).

(3) The judgment of whether data is positive or negative is made by the most significant bit
(b15).
• 0: Positive
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag in this case does not go ON.

6-22

K32767 +K2
(0002H)
(7FFFH)

K 32767
(8001H)

Since bit 15 value is "1",
result of operation takes a negative value.

K 32768 +K 2
(8000H) (FFFEH)

K32766
(7FFEH)

Since bit 15 value is "0",
result of operation takes a positive value.

+(P),-(P)

–
(1) Subtracts 16-bit BIN data designated by

D

from 16-bit BIN data designated by

stores the result of the subtraction at the device designated by
D
b15

S
b0

5678 (BIN)

(2) Values for

S

and

D

b15

D

S

1

and

.

2

D
b0

1234 (BIN)

can be designated between

b15

b0
4444 (BIN)

3

32768 and 32767 (BIN, 16 bits).

(3) The judgment of whether data is positive or negative is made by the most significant bit
(b15).
• 0: Positive

4

• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:

4

The carry flag in this case does not go ON.
K 32768
(8000H)

K2
(0002H)

K32766
(7FFEH)

Since bit 15 value is "0",
result of operation takes a positive value.

K32767
(7FFFH)

K 2
(FFFEH)

K 32767
(8001H)

Since bit 15 value is "1",
result of operation takes a negative value.

6
7

Operation Error

8

(1) There are no operation errors associated with the +(P) or -(P) instruction.

6.2 Arithmetic Operation Instructions
6.2.1 BIN 16-bit addition and subtraction operations (+(P),-(P))

6-23

+(P),-(P)

When three data are set ( S1 + S2

D

,

S1

- S2

D

)

indicates an instruction symbol of +/

.

Command

+,

S1

S2

D

S1

S2

D

Command

+P, P

P

: Data to be added to/subtracted from or head number of the devices where the data to be added

S1

to/subtracted from is stored (BIN 16 bits)
: Data for additing/subtracting or head number of the devices where the data for additing/subtracting is stored

S2

(BIN 16 bits)
: Head number of the devices where the addition/subtraction operation result will be stored (BIN 16 bits)

D

Internal Devices

Setting
Data

Bit

J

R, ZR

Word

\

Bit

U

Word

Zn

\G

Constants
K, H

Other

S1

––

S2

––
––

D
S

––

Function
+
(1) Adds 16-bit BIN data designated by

S1

to 16-bit BIN data designated by

result of the addition at the device designated by
S1

b15

b0

S1

,

S2

D

b15

and stores the

.
D

S2

5678 (BIN)

(2) Values for

D

S2

b0

b15

1234 (BIN)

andcan be designated between

b0
6912 (BIN)

D

32768 and 32767 (BIN, 16 bits).

(3) The judgment of whether data is positive or negative is made by the most significant bit
(b15).
• 0: Positive
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag in this case does not go ON.
K32767
(7FFFH)

+K2
(0002H)

K 32768 +K 2
(8000H) (FFFEH)

6-24

K 32767
(8001H)

Since bit 15 value is "1",
result of operation takes a negative value.

K32766
(7FFEH)

Since bit 15 value is "0",
result of operation takes a positive value.

+(P),-(P)

–
(1) Subtracts 16-bit BIN data designated by

S1

from 16-bit BIN data designated by

stores the result of the subtraction at the device designated by
S1
b15
5678 (BIN)

(2) Values for

S1

, S2

D

1

and

.

2

D

S2
b0

D

S2

b15

b0

b15

1234 (BIN)

and can be designated between

b0
4444 (BIN)

D

32768 and 32767 (BIN, 16 bits).

(3) The judgment of whether data is positive or negative is made by the most significant bit
(b15).

3
4

• 0: Positive
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:

4

The carry flag in this case does not go ON.
K 32768 K2
(8000H)
(0002H)

K32766
(7FFEH)

Since bit 15 value is "0",
result of operation takes a positive value.

K 2
K32767
(7FFFH) (FFFEH)

K 32767
(8001H)

Since bit 15 value is "1",
result of operation takes a negative value.

6
7

Operation Error
8

(1) There are no operation errors associated with the +(P) or -(P) instruction.

Program Example

[Ladder Mode]

[List Mode]
Instruction

Step

Device

(2) The following program outputs the difference between the set value for timer T3 and its
present value in BCD to Y40 to Y53.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

6-25

6.2 Arithmetic Operation Instructions
6.2.1 BIN 16-bit addition and subtraction operations (+(P),-(P))

(1) The following program adds, when X5 is turned ON, the data at D3 and D0 and outputs the
operation result at Y38 to Y3F.

D+(P),D-(P)

6.2.2

BIN 32-bit addition and subtraction operations (D+(P),D-(P))

D+(P),D-(P)

Basic

When two data are set ((

D

+1, D )+(

+1,

S

S

) (

D

+1,

D

), (

D

High
performance

+1,

D

)-(

Process Redundant Universal

S

+1,

) (

S

D

+1,

D

))

indicates an instruction symbol of D+/D .
Command

D+, D

S

D

S

D

Command

D+P, D P

P

S

: Data for additing/subtracting or head number of the devices where the data for additing/subtracting is stored

D

: Head number of the devices where the data to be added to/subtracted from is stored (BIN 32 bits)

(BIN 32 bits)

Setting
Data

Internal Devices
Bit

J

R, ZR

Word

\

Bit

U

Word

Zn

\G

Constants
K, H

Other
––

S

––

D

––

Function
D+
(1) Adds 32-bit BIN data designated by

D

to 32-bit BIN data designated by

result of the addition at the device designated by
D +1

D

b31 b16 b15 b0
567890 (BIN)

(2) The values for
(BIN 32 bits).

S

and

D

S +1

S

b31 b16 b15 b0
123456 (BIN)

D

S

, and stores the

.
D +1

D

b31 b16 b15 b0
691346 (BIN)

can be designated at between

2147483648 and 2147483647

(3) Judgment of whether the data is positive or negative is made on the basis of the most
significant bit (b31).
• 0: Positive
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag in this case does not go ON.

6-26

K 2147483647
K2147483647 +K2
(00000002H) (80000001H)
(7FFFFFFFH)

Since bit 31 value is "1",
result of operation takes a negative value.

K 2147483648 +K 2
K2147483646
(80000000H)
(FFFFFFFEH) (7FFFFFFEH)

Since bit 31 value is "0",
result of operation takes a positive value.

D+(P),D-(P)

D(1) Subtracts 32-bit BIN data designated by

D

from 32-bit BIN data designated by

stores the result of the subtraction at the device designated by
D

D +1

b31 b16 b15 b0
567890 (BIN)

(2) The values for
(BIN 32 bits).

S

and

D

S +1

D +1

S

b31 b16 b15 b0
123456 (BIN)

D

S

1

and

.

2

D

b31 b16 b15 b0
444434 (BIN)

can be designated at between

2147483648 and 2147483647

(3) Judgment of whether the data is positive or negative is made on the basis of the most
significant bit (b31).

3
4

• 0: Positive
• 1: Negative

4

(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag in this case does not go ON.
K2147483646
K 2147483648 K2
(80000000H)
(00000002H) (7FFFFFFEH)
K2147483647
(80000000H)

K 2147483647
K 2
(FFFFFFFEH) (80000001H)

6

Since bit 31 value is "0",
result of operation takes a positive value.
Since bit 31 value is "1",
result of operation takes a negative value.

7

Operation Error

8

(1) There are no operation errors associated with the D+(P) or D-(P) instruction.

6.2 Arithmetic Operation Instructions
6.2.2 BIN 32-bit addition and subtraction operations (D+(P),D-(P))

6-27

D+(P),D-(P)

When three data are set (( S1 +1, S1 )+( S2 +1, S2 ) (

D

+1,

D

), ( S1 +1, S1 )-( S2 +1, S2 ) ( D +1,

D

))

indicates an instruction symbol of D+/ D .
Command

D+, D

S1

S2

D

S1

S2

D

Command

D+P, D P

P

S1

: Data to be added to/subtracted from or head number of the devices where the data to be added

S2

: Data for additing/subtracting or head number of the devices where the data for additing/subtracting is stored

to/subtracted from is stored (BIN 32 bits)
(BIN 32 bits)
D

Setting
Data

: Head number of the devices where the addition/subtraction operation result will be stored (BIN 32 bits)

Internal Devices
Bit

J

R, ZR

Word

\

Bit

U

Word

Zn

\G

Constants
K, H

Other

S1

––

S2
S1

––
––

D

––

Function
D+
(1) Adds 32-bit BIN data designated by

S1

to 32-bit BIN data designated by

result of the addition at the device designated by
S1

+1

S2

S1

b31 b16 b15 b0
567890 (BIN)

(2) The values for
(BIN 32 bits).

S1

,

S2

and

D

+1

S2

b31 b16 b15 b0
123456 (BIN)

D

S2

, and stores the

.
D +1

D

b31 b16 b15 b0
691346 (BIN)

can be designated at between

2147483648 and 2147483647

(3) Judgment of whether the data is positive or negative is made on the basis of the most
significant bit (b31).
• 0: Positive
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag in this case does not go ON.
K2147483647
(7FFFFFFFH)

+K2
(00000002H)

K 2147483647
(80000001H)

K 2147483648 +K 2
K2147483646
(80000000H)
(FFFFFFFEH) (7FFFFFFEH)

6-28

Since bit 31 value is "1",
result of operation takes a negative value.
Since bit 31 value is "0",
result of operation takes a positive value.

D+(P),D-(P)

D(1) Subtracts 32-bit BIN data designated by

from 32-bit BIN data designated by

S1

stores the result of the subtraction at the device designated by
S1

+1

S1

S2

b31 b16 b15 b0
567890 (BIN)

(2) The values for
(BIN 32 bits).

S1

,

S2

and

D

+1

D +1

S2

b31 b16 b15 b0
123456 (BIN)

D

S2

1

and

.

2

D

b31 b16 b15 b0
444434 (BIN)

can be designated at between

2147483648 and 2147483647

(3) Judgment of whether the data is positive or negative is made on the basis of the most
significant bit (b31).

3
4

• 0: Positive
• 1: Negative

4

(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag in this case does not go ON.
K 2147483648 K2
K2147483646
(80000000H)
(00000002H) (7FFFFFFEH)
K2147483647
(7FFFFFFFH)

K 2147483647
K 2
(FFFFFFFEH) (80000001H)

6

Since bit 31 value is "0",
result of operation takes a positive value.
Since bit 31 value is "1",
result of operation takes a negative value.

7
8

Operation Error
(1) There are no operation errors associated with the D+(P) or D-(P) instruction.

(1) The following program adds 28-bit data from X10 to X2B to the data at D9 and D10 when X0
goes ON, and outputs the result of the operation to Y30 to Y4B.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

(2) The following program subtracts the data from M0 to M23 from the data at D0 and D1 when
XB goes ON, and stores the result at D10 and D11.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

6-29

6.2 Arithmetic Operation Instructions
6.2.2 BIN 32-bit addition and subtraction operations (D+(P),D-(P))

Program Example

*(P),/(P)

6.2.3

BIN 16-bit multiplication and division operations (*(P),/(P))

*(P),/(P)

Basic

High
performance

Process Redundant Universal

indicates an instruction symbol of * , / .
Command

*, /

S1

S2

D

S1

S2

D

Command

*P, / P

P

S1

: Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored

S2

: Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored

D

: Head number of the devices where the multiplication/division operation result will be stored (BIN 32 bits)

(BIN 16 bits)
(BIN 16 bits)

Setting
Data

Internal Devices
Bit

J

R, ZR

Word

\

Bit

Word

U

Zn

\G

Constants
K, H

Other

S1

––

S2

––
––

D

––

Function
*
(1) Multiplies BIN 16-bit data designated by

S1

and BIN 16-bit data designated by

stores the result in the device designated by

b15

b0

D

b0
1234 (BIN)

D

b31 b16 b15 b0
7006652 (BIN)

is a bit device, designation is made from the lower bits.

Example

(3) Values for

K1.......... Lower 4 bits (b0 to b3)
K4.......... Lower 16 bits (b0 to b15)
K8.......... 32 bits (b0 to b31)
S1

and

S2

(4) Judgments whether

can be designated between
S1

,

S2

, and

most significant bit (b15 for
• 0: Positive
• 1: Negative

6-30

D

b15

5678 (BIN)

, and

.

S2

S1

(2) If

D

S2

S1

D

, and

32768 and 32767 (BIN, 16 bits).

are positive or negative are made on the basis of the
S2

, for

D

and b31).

*(P),/(P)

/
(1) Divides BIN 16-bit data designated by

and BIN 16-bit data designated by

S1

the result in the device designated by

D

S1

S2

b0
5678 (BIN)

, and stores

D
b0

b15
1234 (BIN)

2

Remainder
D 1

b15
b0 b15
b0
742 (BIN)
4 (BIN)

(2) If a word device has been used, the result of the division operation is stored as 32 bits, and
both the quotient and remainder are stored; if a bit device has been used, 16 bits are used
and only the quotient is stored.
Quotient: Stored at the lower 16 bits.
Remainder: Stored at the upper 16 bits (Stored only when using a word device).
(3) Values for

S1

and

S2

1

.
Quotient

b15

S2

can be designated between

3
4
4

32768 and 32767 (BIN 16 bits).

(4) Judgment whether values for S1 , S2 , D and D +1 are positive or negative is made on the
basis of the most significant bit (b15). (Sign is attached to both the quotient and remainder.)
• 0: Positive

6

• 1: Negative

7

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• Attempt to divide

S2

by 0.

(Error code: 4100)

(1) The following program multiplies "5678" by "1234" in BIN and stores the result at D3 and D4
when X5 turns ON.
[List Mode]
Step

Instruction

Device

(2) The following program multiplies BIN data at X8 to XF by BIN data at X10 to X1B, and
outputs the result of the multiplication to Y30 to Y3F.
[Ladder Mode]

[List Mode]
Instruction

Step

Device

(3) The following program divides, when X3 is turned ON, the data at X8 to XF by 3.14 and
outputs the operation result at Y30 to Y3F.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

6-31

6.2 Arithmetic Operation Instructions
6.2.3 BIN 16-bit multiplication and division operations (*(P),/(P))

Program Example

[Ladder Mode]

8

D*(P),D/(P)

6.2.4

BIN 32-bit multiplication and division operations (D*(P),D/(P))

D*(P),D/(P)

Basic

High
performance

Process Redundant Universal

indicates an instruction symbol of D * D/ .
Command

D* , D/

S1

S2

D

S1

S2

D

Command

D* P,D/P

P

S1

: Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored

S2

: Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored

(BIN 32 bits)
(BIN 32 bits)
D

: Head number of the devices where the multiplication/division operation result will be stored (BIN 64 bits)

Internal Devices

Setting
Data

Bit

J

R, ZR

Word

\

Bit

U

Word

Constants
K, H

Zn

\G

Other

S1

––

S2

––
––

D

––

Function
D*
(1) Multiplies BIN 32-bit data designated by

S1

and BIN 32-bit data designated by

stores the result in the device designated by
S1

S1

S2

b31 b16 b15 b0
567890 (BIN)

D

D

S2

b31 b16 b15 b0
123456 (BIN)

S2

, and

.
D

D

D

b63 b48 b47 b32 b31 b16 b15
70109427840 (BIN)

b0

(2) If D is a bit device, only the lower 32 bits of the multiplication result will be considered, and
the upper 32 bits cannot be designated.
Example

K1.......... Lower 4 bits (b0 to b3)
K4.......... Lower 16 bits (b0 to b15)
K8.......... Lower 32 bits (b0 to b31)

If the upper 32 bits of the bit device are required for the result of the multiplication operation,
first temporarily store the data in a word device, then transfer the word device data to the bit
device by designating (
(3) The values for
(BIN 32 bits).

S1

and

(4) Judgments whether

S1

D

S2

,

+2) and (

• 1: Negative

6-32

+3) data.

can be designated at between
S2

, and

most significant bit (b31 for
• 0: Positive

D

S1

D

and

2147483648 and 2147483647

are positive or negative are made on the basis of the
S2

, b63 for

D

).

D*(P),D/(P)

D/
(1) Divides BIN 32-bit data designated by
the result in the device designated by
S1

S1

S2

b31 b16 b15 b0
567890 (BIN)

and BIN 32-bit data designated by

S1
D

S2

, and stores

.
D

S2

b31 b16 b15 b0
123456 (BIN)

D

b31 b16 b15
4 (BIN)

D

2

D

b0 b31 b16 b15 b0
74066 (BIN)

(2) With a word device, the division operation result is stored in 64 bits and both the quotient
and remainder are stored. With a bit device, only the quotient is stored as the operation
result in 32 bits.
Quotient :
Remainder :
(3) The values for
(BIN 32 bits).

Stored at the lower 32 bits.
Stored at the upper 32 bits (Stored only when using a word device).
S1

and

S2

can be designated at between

(4) Judgment whether values for S1 , S2 ,
basis of the most significant bit (b31).

D

1

and

D

2147483648 and 2147483647

+2 are positive or negative is made on the

3
4
4
6

(Sign is attached to both the quotient and remainder.)
• 0: Positive

7

• 1: Negative

8

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) is turned ON,
and the corresponding error code is stored into SD0.
S2

by 0.

(Error code: 4100)

Program Example
(1) The following program multiplies the BIN data at D7 and D8 by the BIN data at D18 and D19
when X5 is ON, and stores the result at D1 to D4.
[Ladder Mode]

[List Mode]
Instruction

Step

Device

(2) The following program outputs the value resulting when the data at X8 to XF is multiplied by
3.14 to Y30 to Y3F when X3 is ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

6-33

6.2 Arithmetic Operation Instructions
6.2.4 BIN 32-bit multiplication and division operations (D*(P),D/(P))

• Attempt to divide

B+(P),B-(P)

6.2.5

BCD 4-digit addition and subtraction operations (B+(P),B-(P))

B+(P),B-(P)
B+(P), B-(P)

High
performance

Basic

When two data are set (

D

+

S

D

,

D

-

D

S

Process Redundant Universal

)

indicates an instruction symbol of B+/B .
Command

B+, B

S

D

S

D

Command

B+P, B P

P

S

: Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored

D

: Head number of the devices where the data to be added to/subtracted from is stored (BCD 4 digits)

(BCD 4 digits)

Setting
Data

Internal Devices
Bit

J

R, ZR

Word

\

Bit

U

Word

Constants
K, H

Zn

\G

Other
––

S

––

D

––

Function
B+
(1) Adds the BCD 4-digit data designated by

and the BCD 4-digit data designated by

D

stores the result of the addition at the device designated by
D
5

6

D

S
7

8

1

2

S

, and

.

D
3

(2) 0 to 9999 (BCD 4 digits) can be assigned to

4

6

and

S

D

9

1

2

.

(3) If the result of the addition operation exceeds 9999, the higher bits are ignored.
The carry flag in this case does not go ON.
6

4

3

2

3

5

8

3

0

0

1

5

B(1) Subtracts the BCD 4-digit data designated by

and the BCD 4-digit data designated by

S

and stores the result of the subtraction at the device designated by
D
0

6

D

S

7

8

0

2

D

3

4

0

4

4

4

Digits exceeding the designated
number of digits are assumed to be 0.

(2) 0 to 9999 (BCD 4 digits) can be assigned to

6-34

S

and

D

.

.

D

,

B+(P), B-(P)

(3) The following will result if an underflow is generated by the subtraction operation:
The carry flag in this case does not go ON.
0

0

0

1

0

0

1
0

3

9

9

9

8

2

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The

S

or

D

BCD data is outside the 0 to 9999 range.

3

(Error code: 4100)

4

Program Example
(1) The following program adds BCD data 5678 and 1234, stores it at D993, and at the same
time outputs it to from Y30 to Y3F.
[Ladder Mode]

4
6

Stores 5678 in BCD to D993.

7

Adds 1234 in BCD to the value at D993,
and stores the result to D993.
Outputs the data in D993 to Y30 to Y3F.

8
[List Mode]
Instruction

Device

(2) The following program subtracts the BCD data 4321 from 7654, stores the result at D10, and
at the same time outputs it to Y30 to Y3F.
[Ladder Mode]
Stores 7654 in BCD to D10.
Subtracts the value in D10 from 4321 in BCD,
and stores the result to D10.
Outputs the data in D10 to Y30 to Y3F.

[List Mode]
Step

Instruction

Device

6-35

6.2 Arithmetic Operation Instructions
6.2.5 BCD 4-digit addition and subtraction operations (B+(P),B-(P))

Step

B+(P), B-(P)

When three data are set ( S1 + S2

D

,

S1

- S2

)

D

indicates an instruction symbol of B+/B- .
Command

B+, B-

S1

S2

D

S1

S2

D

Command

B+P,B-P

P

S1

: Data to be added to/subtracted from or head number of the devices where the data to be added

S2

: Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored

D

: Head number of the devices where the addition/subtraction operation result will be stored (BCD 4 digits)

to/subtracted from is stored (BCD 4 digits)
(BCD 4 digits)

Setting
Data

Internal Devices
Bit

J

R, ZR

Word

\

Bit

U

Word

Constants
K, H

Zn

\G

Other

S1

––

S2

––
––

D

––

Function
B+
(1) Adds the BCD 4-digit data designated by

and the BCD 4-digit data designated by

S1

stores the result of the addition at the device designated by

6

7

8

1

2

, and

.
D

S2

S1

5

D

S2

3

(2) 0 to 9999 (BCD 4 digits) can be assigned to

4

S1

,

6

S2

and

D

9

1

2

.

(3) If the result of the addition operation exceeds 9999, the higher bits are ignored.
The carry flag in this case does not go ON.
6

4

3

2

3

5

8

3

0

0

1

5

B(1) Subtracts the BCD 4-digit data designated by

S1

and the BCD 4-digit data designated by

and stores the result of the subtraction at the device designated by

0

6

D

S2

S1
7

8

0

2

D

3

0

4

4

4

4

Digits exceeding the designated
number of digits are assumed to be 0.

(2) 0 to 9999 (BCD 4 digits) can be assigned to

6-36

S1

,

S2

and

D

.

.

S2

,

B+(P), B-(P)

(3) The following will result if an underflow is generated by the subtraction operation:
The carry flag in this case does not go ON.
0

0

0

1

0

0

1
0

3

9

9

9

8

2

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The

S1

,

S2

D

or BCD data is outside the 0 to 9999 range.

3

(Error code: 4100)

4

Program Example
(1) The following program adds the D3 BCD data and the Z1 BCD data when X20 goes ON, and
outputs the result to Y8 to Y17.
[Ladder Mode]

[List Mode]
Step

4
6

Instruction

Device

7
(2) The following program subtracts the BCD data at D20 from the BCD data at D10 when X20
goes ON, and stores the result at R10.
[Ladder Mode]

8

[List Mode]
Step

Instruction

Device

6.2 Arithmetic Operation Instructions
6.2.5 BCD 4-digit addition and subtraction operations (B+(P),B-(P))

6-37

DB+(P),DB-(P)

6.2.6

BCD 8-digit addition and subtraction operations
(DB+(P),DB-(P))

DB+(P),DB-(P)

High
performance

Basic

When two data are set ((

D

+1, D )+(

S

+1,

S

) (

D

+1,

D

), (

D

+1,

Process Redundant Universal

)-(

D

S

+1,

S

) (

D

+1,

))

D

indicates an instruction symbol of DB+/DB- .
Command

DB+, DB-

S

D

S

D

Command

DB+P. DB-P

Setting
Data

P

S

: Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored
(BCD 8 digits)

D

: Head number of the devices where the data to be added to/subtracted from is stored (BCD 8 digits)

Internal Devices
Bit

J

R, ZR

Word

\

Bit

U

Word

Constants
K, H

Zn

\G

Other
––

S

––

D

––

Function
DB+
(1) Adds the BCD 8-digit data designated by

D

and the BCD 8-digit data designated by

stores the result of the addition at the device designated by
D

D

S

S

D

D

S

, and

.
D

(Upper 4 digits)(Lower 4 digits)

(Upper 4 digits)(Lower 4 digits)

(Upper 4 digits)(Lower 4 digits)

0 9 8 7 1 0 6 8

0 0 3 2 3 4 5 6

1 0 1 9 4 5 2 4

Digits exceeding the designated number
of digits are assumed to be 0.

(2) 0 to 99999999 (BCD 8 digits) can be assigned to

S

and

D

.

(3) If the result of the addition operation exceeds 99999999, the upper bits will be ignored.
The carry flag in this case does not go ON.
9 9 0 0 0 0 0 0

0 1 6 5 4 3 2 1

0 0 6 5 4 3 2 1

DB(1) Subtracts the BCD 8-digit data designated by

D

and the BCD 8-digit data designated by

and stores the result of the subtraction at the device designated by
D +1

D

S +1

S

D +1

D

(Upper 4 digits) (Lower 4 digits)

(Upper 4 digits) (Lower 4 digits)

(Upper 4 digits) (Lower 4 digits)

0 9 8 7 1 0 6 8

0 0 3 2 3 4 5 6

0 9 5 4 7 6 1 2

Digits exceeding the designated number
of digits are assumed to be 0.

6-38

D

.

S

,

DB+(P),DB-(P)

(2) 0 to 99999999 (BCD 8 digits) can be assigned to

S

and

D

.

(3) The following will result if an underflow is generated by the subtraction operation: The carry
flag in this case does not go ON.
1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 9

9 9 9 9 9 9 9 9

1
2

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The

S

or

D

BCD data is outside the 0 to 99999999 range.

(Error code: 4100)

Program Example

3
4
4

(1) The following program adds the BCD data 12345600 and 34567000, stores the result at
D887 and D888, and at the same time outputs them to from Y30 to Y4F.
[Ladder Mode]

6

Stores 12345600 in BCD to D887 and D888.

7

Adds 34567000 in BCD to the value in D887 and D888,
and stores the result to D887 and D888.
Outputs the data in D887 and D888 to Y30 to Y4F.

8

[List Mode]
Instruction

Device

(2) The following program subtracts the BCD data 98765432 from 12345678, stores the result
at D100 and D101, and at the same time outputs it from Y30 to Y4F.
[Ladder Mode]
Stores 98765432 in BCD to D100 and D101.
Subtracts the value in D100 and D101 from 12345678
in BCD, and stores the result to D100 and D101.
Outputs the data in D100 and D101 to T30
to Y4F.

[List Mode]
Step

Instruction

Device

6-39

6.2 Arithmetic Operation Instructions
6.2.6 BCD 8-digit addition and subtraction operations (DB+(P),DB-(P))

Step

DB+(P),DB-(P)

When three data are set (( S1 +1, S1 )+( S2 +1, S2 ) (

D

+1,

D

), ( S1 +1, S1 )-( S2 +1, S2 ) ( D +1,

indicates an instruction symbol of DB+/ DB

D

))

.

Command

DB+, DB-

S1

S2

D

S1

S2

D

Command

DB+P, DB-P

P

S1

: Data to be added to/subtracted from or head number of the devices where the data to be added

S2

: Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored

to/subtracted from is stored (BCD 8 digits)
(BCD 8 digits)
: Head number of the devices where the addition/subtraction operation result is stored (BCD 8 digits)

D

Setting
Data

Internal Devices
Bit

R, ZR

Word

J

\

Bit

U

Word

Zn

\G

Constants
K, H

Other

S1

––

S2

––
––

D

––

Function
DB+
(1) Adds the BCD 8-digit data designated by

S1

and the BCD 8-digit data designated by

stores the result of the addition at the device designated by
S1 +1

S1

S2 +1

S2

D

, and

.

D +1

D

(Upper 4 digits) (Lower 4 digits)

(Upper 4 digits) (Lower 4 digits)

(Upper 4 digits) (Lower 4 digits)

5 6 7 8 9 1 2 3

0 1 2 3 4 5 6 7

5 8 0 2 3 6 9 0

+

S2

Digits exceeding the designated number
of digits are assumed to be 0.

(2) 0 to 99999999 (BCD 8 digits) can be assigned to

S1

,

S2

and

D

.

(3) If the result of the addition operation exceeds 99999999, the upper bits will be ignored.
The carry flag in this case does not go ON.
9 9 0 0 0 0 0 0

6-40

0 1 6 5 4 3 2 1

0 0 6 5 4 3 2 1

DB+(P),DB-(P)

DB(1) Subtracts the BCD 8-digit data designated by

S1

and the BCD 8-digit data designated by

and stores the result of the subtraction at the device designated by
S1 +1

S1

(Upper 4 digits) (Lower 4 digits)
5 6 7 8 9 1 2 3

S2 +1

D +1

S2

(Upper 4 digits) (Lower 4 digits)

S2

,

.

D

2

D

(Upper 4 digits) (Lower 4 digits)

0 1 2 3 4 5 6 7

5 5 5 5 4 5 5 6

3

Digits exceeding the designated
number of digits are assumed to be 0.

(2) 0 to 99999999 (BCD 8 digits) can be assigned to

1

S1

,

S2

and

D

.

4

(3) The following will result if an underflow is generated by the subtraction operation:
The carry flag in this case does not go ON.
1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 9

4

9 9 9 9 9 9 9 9

Operation Error

6

(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The

S1

,

S2

D

or BCD data is outside the 0 to 99999999 range. (Error code: 4100)

Program Example

7
8

(1) The following program adds the BCD data at D3 and D4 to the BCD data at Z1 and Z2 when
X20 goes ON, and stores the result at R10 and R11.
[Ladder Mode]

[List Mode]
Instruction

6.2 Arithmetic Operation Instructions
6.2.6 BCD 8-digit addition and subtraction operations (DB+(P),DB-(P))

Step

Device

6-41

B*(P),B/(P)

6.2.7

BCD 4-digit multiplication and division operations
(B*(P),B/(P))

B*(P),B/(P)

Basic

High
performance

Process Redundant Universal

indicates an instruction symbol of B * ,B/ .
Command

B * , B/

S1

S2

D

S1

S2

D

Command

B * P, B/P

P

S1

: Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored
(BCD 4 digits)

S2

: Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored
(BCD 4 digits)

D

: Head number of the devices where the multiplication/division operation result will be stored (BCD 8 digits)

Internal Devices

Setting
Data

Bit

J

R, ZR

Word

\

Bit

U

Word

Constants
K, H

Zn

\G

Other

S1

––

S2

––
––

D

––

Function
B*
(1) Multiplies BCD data designated by
in the device designated by

D

6

and BCD data designated by
D +1
(Upper 4 digits)

S2

7

8

S2

, and stores the result

.

S1

5

S1

0

8

7

6

(2) 0 to 9999 (BCD 4 digits) can be assigned to

0

and

S1

9

4
S2

D
(Lower 4 digits)

7

3

9

8

2

.

B/
(1) Divides BCD data designated by
the device designated by

D

6

and BCD data designated by

S2

7

8

/

0

S2

, and stores the result in

.

S1

5

S1

8

D (Quotient)
7

6

0

0

0

6

D +1 (Remainder)
0

4

2

2

Digits exceeding the designated number of digits are
assumed to be 0.

(2) Uses 32 bits to store the result of the division as quotient and remainder
Quotient (BCD 4 digits)
:Stored at the lower 16 bits.
Remainder (BCD 4 digits) :Stored at the upper 16 bits.
(3) If

6-42

D

has been designated as a bit device, the remainder of the operation will not be stored.

B*(P),B/(P)

Operation Error

1

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The

or

S1

S2

BCD data is outside the 0 to 9999 range.

• Attempt to divide

(Error code: 4100)

by 0.

S2

(Error code: 4100)

2
3

Program Example
(1) The following program multiplies, when X20 is turned ON, the BCD data at X0 to XF by the
BCD data at D8 and stores the operation result at D0 to D1.
[Ladder Mode]

[List Mode]

4

Device

Instruction

Step

4

6
[Operation]
D8
XF
9

7

5

X0
3

8

6

4

2

8

4

Multiplier

Multiplicand

7

D1 (Upper 4 digits) D0 (Lower 4 digits)
2

8

5

4

2

6

Multiplication result

(2) The following program divides 5678 by the BCD data 1234, stores the result at D502 and
D503, and at the same time outputs the quotient to Y30 to Y3F.
[Ladder Mode]

[List Mode]
Device

Instruction

Step

6.2 Arithmetic Operation Instructions
6.2.7 BCD 4-digit multiplication and division operations (B*(P),B/(P))

[Operation]
D502
5

6

7

8

8

/

1

2

3

4

0

0

0

D503
4

0

0

Y30
4

Quotient
Y3F
0

0

7

4

2

Remainder

Quotient

6-43

DB*(P),DB/(P)

6.2.8

BCD 8-digit multiplication and division operations
(DB*(P),DB/(P))

DB*(P),DB/(P)

Basic

High
performance

Process Redundant Universal

indicates an instruction symbol of DB * ,DB/ .
Command

DB * , DB/

S1

S2

D

S1

S2

D

Command

DB * P, DB/P

P

S1

: Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored
(BCD 8 digits)

S2

: Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored
(BCD 8 digits)

D

: Head number of the devices where the multiplication/division operation result will be stored (BCD 16 digits)

Internal Devices

Setting
Data

Bit

J

R, ZR

Word

\

Bit

U

Word

Constants
K, H

Zn

\G

Other

S1

––

S2

––
––

D

––

Function
DB*
(1) Multiplies the BCD 8-digit data designated by S1 and the BCD 8-digit data designated by
and stores the product at the device designated by D .
S1

9

9

S1

+1
9

9

9

9

S2

9

9

9

9

9

9

S2

9

9

D +2

D +3
9

9

+1

9

9

9

9

S2

9

9

9

D +1
8

0

0

D

0

0

0

0

0

1

(2) If D has designated a bit device, the lower 8 digits (lower 32 bits) will be used for the
product, and the higher 8 digits (upper 32 bits) cannot be designated.
K1 ....Lower 1 digit (b0 to 3), K4 ....Lower 4 digits (b0 to 15), K8.....Lower 8 digits (b0 to 31)
(3) 0 to 99999999 (BCD 8 digits) can be assigned to

S1

and

S2

.

DB/
(1) Divides 8-digit BCD data designated by S1 and 8-digit BCD data designated by
stores the result in the device designated by D .
S1 +1

5

6

7

8

Quotient

6-44

S2 +1

S1

9

1

2

3

/

0

1

2

S2

3

4

5

6

7

D +1
(Upper 4 digits)

Digits exceeding the designated number of digits
are assumed to be 0
D
D +3
D +2
(Lower 4 digits) Remainder (Upper 4 digits)
(Lower 4 digits)

0

0

0

0

0

0

4

5

0

1

2

3

3

6

0

8

S2

, and

,

DB*(P),DB/(P)

(2) 64 bits are used for the result of the division operation, and stored as quotient and
remainder.

1

Quotient (BCD 8 digits)
:Stored at the lower 32 bits.
Remainder (BCD 8 digits) :Stored at the upper 32 bits.
(3) If

D

has been designated as a bit device, the remainder of the operation will not be stored.

Operation Error

3

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The

S1

2

or

S2

BCD data is outside the 0 to 99999999 range.

• Attempt to divide

(Error code: 4100)

by 0.

S2

(Error code: 4100)

4
4

Program Example
(1) The following program multiplies the BCD data 67347125 and 573682, stores the result from
D502 to D505, and at the same time outputs the upper 8 digits to Y30 to Y4F.
[Ladder Mode]

[List Mode]

7

Device

Instruction

Step

6

8
[Operation]

0 0 5 7 3 6 8 2

Multiplicand

Multiplier

D504

D503

D502

0 0 3 9

2 0 9 5

1 5 3 6

4 2 5 0

Y4F
Y30
0 0 3 9 2 0 9 5

(2) The following program divides the BCD data from X20 to X3F by the BCD data at D8 and D9
when X0B goes ON, and stores the result from D765 to D768.
[Ladder Mode]

[List Mode]
Device

Instruction

Step

[Operation]
D9 (Upper 4 digits) D8 (Lower 4 digits)
X3F
9

9

8

6

4

3

2

X20
1
/

5

1

2

6

3

7

4

8

Divisor

Dividend
D766
(Upper 4 digits)
0

0

0

0

D765
(Lower 4 digits)
0

Quotient

0

0

6

D768
(Upper 4 digits)
0

8

2

8

D767
(Lower 4 digits)
1

8

3

3

Remainder

6-45

6.2 Arithmetic Operation Instructions
6.2.8 BCD 8-digit multiplication and division operations (DB*(P),DB/(P))

6 8 3 4 7 1 2 5

D505

E+(P),E-(P)

6.2.9

Addition and subtraction of floating decimal point data
(Single precision) (E+(P),E-(P))

E+(P),E-(P)

Ver.
High
performance

Basic

Process Redundant Universal

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

When two data are set ((

D

+1, D )+(

S

+1,

S

) (

D

+1,

D

), (

D

+1,

D

)-(

S

+1,

S

) (

D

+1,

D

))

indicates an instruction symbol of E+/E- .
Command

E+, E-

S

D

S

D

Command

E+P, E-P

P

S

: Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored

D

: Head number of the devices where the data to be added to/subtracted from is stored (real number)

(real number)

Setting
Data

Internal Devices
Bit

J

R, ZR

Word

\

Bit

Word

U

\G

Constants
E

Zn

S

––

––

––

D

––

––

––

Other
––

––

––

*1:Available only in multiple Universal model QCPU

Function
E+
(1) Adds the 32-bit floating decimal point type real number designated at
floating decimal point type real number designated at
designated at

D

S

D

and the 32-bit

, and stores the sum in the device

.

D +1

D

S +1

S

D +1

D

+
32-bit floating-point
real number

32-bit floating-point
real number

(2) Values which can be designated at
0, 2-126

S

and

D

32-bit floating-point
real number

and which can be stored, are as follows:

| Designated value (stored value) | < 2128

E(1) Subtracts a 32-bit floating decimal point type real number designated by D and a 32-bit
floating decimal point type real number designated by S , and stores the result at a device
designated by D .
D +1

D

32-bit floating-point
real number

6-46

S +1

S

32-bit floating-point
real number

D +1

D

32-bit floating-point
real number

E+(P),E-(P)
(2) Values which can be designated at
0, 2-126

S

and

D

and which can be stored, are as follows:

| Designated value (stored value) | < 2128

1

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.

2

• The contents of the designated device or the result of the addition are not "0", or not within
the following range:
(Error code: 4100)

3

0, 2-126
| Contents of designated device | < 2128
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU)
(Error code: 4100)

4

• The value of the specified device is 0.*2
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU)
(Error code: 4100)
*2: There are CPU modules that will not result in an operation error if
Refer to Section 3.2.4 for details.

0 is specified.

6

• The result of addition and subtraction exceeds the following range. (The overflow occurs.)
(For the Universal model QCPU only)
2128

| Result of addition and subtraction |

4

(Error code: 4141)

• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU only)
(Error code: 4140)

7
8

Program Example

[Ladder Mode]

[List Mode]
Instruction

Step

Device

[Operation]
D4

D3

5961.437

D11

D10

12003.200

D4

D3

17964.637

(2) The following program subtracts the 32-bit floating decimal point type real number at D10
and D11 from the 32-bit floating decimal point type real numbers at D20 and D21, and stores
the result of the subtraction at D20 and D21.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
D21
D20
97365.203

D11
D10
76059.797

D21
D20
21305.406

6-47

6.2 Arithmetic Operation Instructions
6.2.9 Addition and subtraction of floating decimal point data (Single precision) (E+(P),E-(P))

(1) The following program adds the 32-bit floating decimal point type real numbers at D3 and D4
and the 32-bit floating decimal point type real numbers at D10 and D11 when X20 goes ON,
and stores the result at D3 and D4.

E+(P),E-(P)

When three data are set (( S1 +1, S1 )+( S2 +1, S2 ) (

D

+1,

), ( S1 +1, S1 )-( S2 +1, S2 ) ( D +1,

D

D

indicates an instruction symbol of E+/E-.
Command

E+, E-

S1

S2

D

S1

S2

D

Command

E+P, E-P

P

S1

: Data to be added to/subtracted from or head number of the devices where the data to be added

S2

: Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored

D

: Head number of the devices where the addition/subtraction operation result is stored (real number)

to/subtracted from is stored (real number)
(real number)

Setting
Data

Internal Devices
Bit

J

R, ZR

Word

\

Bit

U

Word

\G

Constants
E

Zn

Other

S1

––

––

––

––

S2

––

––

––

––

D

––

––

––

––

––

*1:Available only in multiple Universal model QCPU

Function
E+
(1) Adds the 32-bit floating decimal point type real number designated at
floating decimal point type real number designated at
designated at

D

S2

S1

and the 32-bit

, and stores the sum in the device

.

S1 +1

S2 +1

S1

D +1

S2

D

+
32-bit floating-point
real number

32-bit floating-point
real number

(2) Values which can be designated at
0, 2-126

S1

,

S2

and

D

32-bit floating-point
real number

and which can be stored, are as follows:

| Designated value (stored value) | < 2128

E(1) Subtracts a 32-bit floating decimal point type real number designated by
floating decimal point type real number designated by
designated by

D

S1 +1

S2 +1

S1

, and stores the result at a device
D +1

S2

32-bit floating-point
real number

(2) Values which can be designated at

6-48

and a 32-bit

.

32-bit floating-point
real number

0, 2-126

S2

S1

S1

and

S2

and

D

32-bit floating-point
real number
D

| Designated value (stored value) | < 2128

which can be stored, are as follows:

))

E+(P),E-(P)

Operation Error

1

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The contents of the designated device or the result of the addition are not "0", or not within
the following range:
0, 2-126
| Contents of designated device | < 2128
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU)
(Error code: 4100)
• The value of the specified device is 0.*2
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU)
(Error code: 4100)
*2: There are CPU modules that will not result in an operation error if
Refer to Section 3.2.4 for details.

| Result of addition and subtraction |

3
4
4

0 is specified.

• The result of addition and subtraction exceeds the following range. (The overflow occurs.)
(For the Universal model QCPU only)
2128

2

6

(Error code: 4141)

• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU only)
(Error code: 4140)

7
8

Program Example
(1) The following program adds the 32-bit floating decimal point type real numbers at D3 and D4
and the 32-bit floating decimal point type real numbers at D10 and D11 when X20 goes ON,
and outputs the result to R0 and R1.
[List Mode]
Instruction

Step

Device

[Operation]
D4

D3

5961.437

D11

D10

12003.200

R1

R0

17964.637

(2) The following programs subtracts the 32-bit floating decimal point type real numbers at D20
and D21 from the 32-bit floating decimal point type real numbers at D11 and D10, and stores
the result at D30 and D31.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
D11

D10

97365.203

D21

D20

76059.797

D31

D30

21305.406

6-49

6.2 Arithmetic Operation Instructions
6.2.9 Addition and subtraction of floating decimal point data (Single precision) (E+(P),E-(P))

[Ladder Mode]

ED+(P),ED-(P)

6.2.10

Addition and subtraction of floating decimal point data
(Double precision) (ED+(P),ED-(P))

ED+(P),ED-(P)

Basic

When two data are set ((
(

+3,

D

D

+2,

D

+1,

D

)-(

D

S

+3,

+3,

D

S

+2,

+2,

D

S

+1,

+1,

Process Redundant Universal

)+(

S

+3,

S

+2,

S

+1, S ) (

) (

D

+3,

D

+2,

D

+1,

D

S

High
performance

D

D

+3,

D

+2,

D

+1,

D

),

))

indicates an instruction symbol of ED+/ED-.
Command

ED+, ED-

S

D

S

D

Command

ED+P, ED-P

P

S

: Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored

D

: Head number of the devices where the data to be added to/subtracted from is stored (real number)

(real number)

Setting
Data

Internal Devices
Bit

Word

J

R, ZR

Bit

\
Word

U

S

––

––

D

––

––

\G

Constants
E

Zn

Other
––

––

––

Function
ED+
(1) Adds the 64-bit floating decimal point type real number designated at
floating decimal point type real number designated at
designated at

D

64-bit floating-point
real number

D

S +3 S +2 S +1

S

64-bit floating-point
real number

(2) Values which can be designated at

6-50

and the 64-bit

, and stores the sum in the device

.

D +3 D +2 D +1

0, 2-1022

S

D

S

and

D

D +3 D +2 D +1

D

64-bit floating-point
real number

and which can be stored, are as follows:

| Designated value (stored value) | < 21024

ED+(P),ED-(P)

ED(1) Subtracts a 64-bit floating decimal point type real number designated by
floating decimal point type real number designated by
designated by

D

and a 64-bit

1

, and stores the result at a device

.

D +3 D +2 D +1

2
D

64-bit floating-point
real number

S +3 S +2 S +1

D +3 D +2 D +1

S

64-bit floating-point
real number

(2) Values which can be designated at
0, 2-1022

S

D

S

and

D

D

3

64-bit floating-point
real number

and which can be stored, are as follows:

4

| Designated value (stored value) | < 21024

4

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The contents of the designated device or the result of the addition are not "0", or not within
the following range:
(Error code: 4140)
0, 2-1022

| Contents of designated device | < 21024

• The value of the designated device is

0.

| Result of operation |

[List Mode]
Step

Instruction

Device

[Operation]
D4 D3

5961.437

D13 D12 D11 D10
12003.200

D6 D5

D4 D3

17964.637

(2) The following program subtracts the 64-bit floating decimal point type real number at D10 to
D13 from the 64-bit floating decimal point type real numbers at D20 to D23, and stores the
result of the subtraction at D20 to D23.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
D23 D22 D21 D20

D13 D12 D11 D10

D23 D22 D21 D20

97365.203

76059.797

21305.406

6-51

6.2 Arithmetic Operation Instructions
6.2.10 Addition and subtraction of floating decimal point data (Double precision) (ED+(P),ED-(P))

(1) The following program adds the 64-bit floating decimal point type real numbers at D3 to D6
and the 64-bit floating decimal point type real numbers at D10 to D13 when X20 goes ON,
and stores the result at D3 to D6.

D6 D5

8

(Error code: 4141)

Program Example

[Ladder Mode]

7

(Error code: 4140)

• The result of addition/subtraction exceeds the following range (Operation results in an
overflow):
21024

6

ED+(P),ED-(P)

When three data are set(( S1 +3, S1 +2, S1 +1, S1 )+( S2 +3, S2 +2, S2 +1, S2 ) (
( S1 +3, S1 +2, S1 +1, S1 )-( S2 +3, S2 +2, S2 +1, S2 ) (

D

+3,

+2,

D

D

+1,

D

D

+3,

D

+2,

D

+1,

D

),

))

indicates an instruction symbol of ED+/ED-.
Command

ED+, ED-

S1

S2

D

S1

S2

D

Command

ED+P, ED-P

Setting
Data

P

S1

: Data to be added to/subtracted from or head number of the devices where the data to be added
to/subtracted from is stored (real number)

S2

: Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored
(real number)

D

: Head number of the devices where the addition/subtraction operation result is stored (real number)

Internal Devices
Bit

R, ZR

Word

J

\

Bit

U

Word

Constants
E

Zn

\G

Other

S1

––

––

––

S2

––

––

––

D

––

––

––

––

Function
ED+
(1) Adds the 64-bit floating decimal point type real number designated at
floating decimal point type real number designated at
designated at
S1 +3

D

S2

S1

and the 64-bit

, and stores the sum in the device

.

S1 +2 S1 +1

S2 +3

S1

S2 +2

S2 +1

D +3

S2

D +2 D +1

D

+
64-bit floating-point
real number

64-bit floating-point
real number

(2) Values which can be designated at
0, 2-1022

S1

,

S2

64-bit floating-point
real number

and

D

and which can be stored, are as follows:

| Designated value (stored value) | < 21024

ED(1) Subtracts a 64-bit floating decimal point type real number designated by
floating decimal point type real number designated by
designated by
S1 +3

S1 +2

D

S1 +1

S1

S2 +3

S2 +2

S2 +1

D +3 D +2 D +1

S2

64-bit floating-point
real number

(2) Values which can be designated at

6-52

S1

and a 64-bit

, and stores the result at a device

.

64-bit floating-point
real number

0, 2-1022

S2

S1

and

S2

D

64-bit floating-point
real number

and

D

which can be stored, are as follows:

| Designated value (stored value) | < 21024

ED+(P),ED-(P)

Operation Error

1

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The contents of the designated device or the result of the addition are not "0", or not within
the following range:
(Error code: 4140)
0, 2-1022

| Contents of designated device | < 21024

• The value of the specified device is

0.

(Error code: 4140)

• The result of addition/subtraction exceeds the following range (Operation results in an
overflow):
21024

| Result of operation |

2
3
4

(Error code: 4141)

4

Program Example
(1) The following program adds the 64-bit floating decimal point type real numbers at D3 to D6
and the 64-bit floating decimal point type real numbers at D10 to D13 when X20 goes ON,
and outputs the result at R0 to R3.
[Ladder Mode]

[List Mode]

7

Device

Instruction

Step

6

8
[Operation]
D6 D5

D4 D3

D13 D12 D11 D10

R3 R2

12003.200

R1 R0

17964.637

(2) The following programs subtracts the 64-bit floating decimal point type real numbers at D20
to D23 from the 64-bit floating decimal point type real numbers at D10 to D13, and stores the
result at D30 to D33.
[Ladder Mode]
SM 400

[List Mode]
10

20

30

Step

Device

Instruction

SM 400
20

30

[Operation]
D13 D12 D11 D10

D23 D22 D21 D20

D33 D32 D31 D30

97365.203

76059.797

21305.406

6-53

6.2 Arithmetic Operation Instructions
6.2.10 Addition and subtraction of floating decimal point data (Double precision) (ED+(P),ED-(P))

5961.437

E*(P),E/(P)

6.2.11

Multiplication and division of floating decimal point data
(Single precision) (E*(P),E/(P))

E*(P),E/(P)

Ver.
Basic

High
performance

Process Redundant Universal

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

indicates an instruction symbol of E* , E/ .
Command

E* , E/

S1

S2

D

S1

S2

D

Command

E* P, E/P

P

Setting
Data

S1

: Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored
(real number)

S2

: Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored
(real number)

D

: Head number of the devices where the multiplication/division operation result will be stored (real number)

Internal Devices
Bit

R, ZR

Word

J

\

Bit

U

Word

Constants
E

Zn

\G

Other

S1

––

––

––

*1

––

S2

––

––

––

*1

––

D

––

––

––

*1

––

*1:Available only in multiple Universal model QCPU

Function
E*
(1) Multiplies the 32-bit floating decimal point real number designated by
floating decimal point real number designated by
device designated by
S1 +1

D

by the 32-bit

and stores the operation result at the

.
S2 +1

S1

32-bit floating-point
real number

D +1

S2

32-bit floating-point
real number

(2) Values which can be designated at
0, 2-126

S2

S1

S1

,

S2

and

D

D

32-bit floating-point
real number

and which can be stored, are as follows:

| Designated value (stored value) | < 2128

E/
(1) Divides the 32-bit floating decimal point real number designated by
decimal point real number designated by
designated by

D

S2

S1

and stores the operation result at the device

.

S1 +1

S2 +1

S1

S2

D +1

D

/
32-bit floating-point
real number

6-54

by the 32-bit floating

32-bit floating-point
real number

32-bit floating-point
real number

E*(P),E/(P)

(2) Values which can be designated at
0, 2-126

S1

,

S2

and

D

and which can be stored, are as follows:

1

| Designated value (stored value) | < 2128

Operation Error

2

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device or the result of multiplication is not within the following
range:
0, 2-126
| Contents of designated device | < 2128
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU)
(Error code: 4100)
• The value of the designated device is 0.*2
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU)
(Error code: 4100)

• The result of multiplication and division exceeds the following range.
(The overflow occurs.)(For the Universal model QCPU only)
| Result of addition and subtraction |

4
4
6

*2: There are CPU modules that will not result in an operation error if -0 is specified.
Refer to Section 3.2.4 for details.

2128

3

(Error code: 4141)

• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU only)
(Error code: 4140)

7
8

Program Example

[Ladder Mode]

[List Mode]
Instruction

Step

Device

[Operation]
D3

D4

36.7896

D11

D10

11.9278

R1

R0

438.8190

(2) The following program divides the 32-bit floating decimal point real numbers at D10 and D11
by the 32-bit floating decimal point real numbers at D20 and D21, and stores the result at
D30 and D31.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
D11

D10

52171.39

D21

D20

9.73521

D31

D30

5359.041

6-55

6.2 Arithmetic Operation Instructions
6.2.11 Multiplication and division of floating decimal point data (Single precision) (E*(P),E/(P))

(1) The following program multiplies the 32-bit floating decimal point real numbers at D3 and D4
and the 32-bit floating decimal point real numbers at D10 and D11, and stores the result at
R0 and R1.

ED*(P),ED/(P)

6.2.12

Multiplication and division of floating decimal point data
(Double precision) (ED*(P),ED/(P))

ED*(P),ED/(P)

Basic

High
performance

Process Redundant Universal

indicates an instruction symbol of ED*, ED/.
Command

ED*, ED/

S1

S2

D

S1

S2

D

Command

ED* P, ED/P

P

: Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored

S1

(real number)
: Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored

S2

(real number)
: Head number of the devices where the multiplication/division operation result will be stored (real number)

D

Internal Devices

Setting
Data

Bit

Word

R, ZR

J

\

Bit

Word

U

\G

Zn

Constants
E

Other

S1

––

––

––

S2

––

––

––

D

––

––

––

––

Function
ED*
(1) Multiplies the 64-bit floating decimal point real number designated by S1 by the 64-bit
floating decimal point real number designated by S2 and stores the operation result at the
device designated by D .
S1 +3

S1 +2

S1 +1

64-bit floating-point
real number

S1

S2 +3

S2 +1

D +3 D +2 D +1

S2

64-bit floating-point
real number

(2) Values which can be designated at
0, 2-1022

S2 +2

S1

,

S2

and

D

64-bit floating-point
real number
D

and which can be stored, are as follows:

| Designated value (stored value) | < 21024

(3) When the operation results in -0 or an underflow, the result is processed as 0.

6-56

ED*(P),ED/(P)

ED/
(1) Divides the 64-bit floating decimal point real number designated by S1 by the 64-bit floating
decimal point real number designated by S2 and stores the operation result at the device
designated by D .
S1 +3

S1 +2

S1 +1

64-bit floating-point
real number

S1

S2 +3

S2

D +3 D +2 D +1

64-bit floating-point
real number

(2) Values which can be designated at
0, 2-1022

S2 +1

S2 +2

S1

,

S2

and

D

64-bit floating-point
real number
D

1
2
3

and which can be stored, are as follows:

4

| Designated value (stored value) | < 21024

(3) When the operation results in -0 or an underflow, the result is processed as 0.

4

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device or the result of multiplication is not within the following
range:
(Error code: 4140)
0, 2-1022

| Contents of designated device | < 21024

• The value of the designated device is
• The value of

S2

0.

(Error code: 4140)

at division operation is 0.

(Error code: 4100)

6
7
8

• The result of multiplication/division exceeds the following range (Operation results in an
overflow):
21024

| Result of operation |

(Error code: 4141)

(1) The following program multiplies the 64-bit floating decimal point real numbers at D3 to D6
and the 64-bit floating decimal point real numbers at D10 to D13, and stores the result at R0
to R3.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
D6 D5

D4 D3

36.7896

D13 D12 D11 D10
11.9278

R3 R2

R1 R0

438.8190

6-57

6.2 Arithmetic Operation Instructions
6.2.12 Multiplication and division of floating decimal point data (Double precision) (ED*(P),ED/(P))

Program Example

ED*(P),ED/(P)

(2) The following program divides the 64-bit floating decimal point real numbers at D10 to D13
by the 64-bit floating decimal point real numbers at D20 to D23, and stores the result at D30
to D33.
[Ladder Mode]

[List Mode]
Step

Instruction

[Operation]
D13 D12 D11 D10
52171.39

6-58

D23 D22 D21 D20
9.73521

D33 D32 D31 D30
5359.041

Device

BK+(P),BK-(P)

6.2.13

Block addition and subtraction (BK+(P),BK-(P))

1
BK+(P),BK-(P)

Basic

High
performance

Process Redundant Universal

2
3

indicates an instruction symbol of BK+, BK- .
Command

BK+, BK-

S1

S2

D

n

S2

S2

D

n

4

Command

BK+P, BK-P

P

4

S1

: Head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits)

S2

: Data for additing/subtracting or head number of the devices where the data for additing/subtracting is stored
(BIN 16 bits)

D

: Head number of the devices where the operation result will be stored (BIN 16 bits)

7

n : Number of addition/subtraction data blocks (BIN 16 bits)
Setting
Data

Internal Devices
Bit

R, ZR

Word

J

\

Bit

U

Word

S1

––

––

S2

––

––

D

––

––

Zn

\G

Constants
$

Other

––

––

––

––
––

BK+
(1) Adds n points of BIN data from the device designated by
the device designated by

S1 +2
S1 +(n 2)
S1 +(n 1)

S2

S1

and n-points of BIN data from

and stores the result from the device designated by

b15
b0
1234 (BIN)
4567 (BIN)
2000 (BIN)

S2
S2 +1
S2 +2

n
1234 (BIN)
4000 (BIN)

b15
b0
4000 (BIN)
1234 (BIN)
1234 (BIN)

S2 +(n 2)
S2 +(n 1)

5000 (BIN)
4321 (BIN)

n

D
D +1
D +2

D

b15
b0
5234 (BIN)
5801 (BIN)
3234 (BIN)

D +(n 2)
D +(n 1)

onward.

n

3766 (BIN)
8321 (BIN)

(2) Block addition is performed in 16-bit units.
(3) The constant designated by
S1
S1 +1
S1 +2
S1 +(n 2)
S1 +(n 1)

b15
b0
1234 (BIN)
4567 (BIN)
2000 (BIN)
n
1234 (BIN)
4000 (BIN)

S2

can be between

S2

32768 and 32767 (BIN 16-bit data).

b15
b0
4321 (BIN)

D
D +1
D +2

b15
b0
5555 (BIN)
8888 (BIN)
2321 (BIN)

D +(n 2)
D +(n 1)

n
3087 (BIN)
8321 (BIN)

6-59

6.2 Arithmetic Operation Instructions
6.2.13 Block addition and subtraction (BK+(P),BK-(P))

Function

S1 +1

8

––

n

S1

6

BK+(P),BK-(P)

(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag in this case does not go ON.

K32767 +K2
(7FFFH) (0002H)

K 32767
(8001H)

K 32767 +K 2
(8001H) (FFFEH)

K32767
(7FFFH)

BK(1) Subtracts n points of BIN data from the device designated by
from the device designated by
onward.
b15
8765
8888
9325

S1
S1
S1

S1
S1

+1
+2

b0
(BIN)
(BIN)
(BIN)
n

+(n 2) 5000
+(n 1) 4352

b15
1234
5678
9876

S2

S2

(BIN)
(BIN)

S2
S2

and n-points of BIN data

and stores the result from the device designated by

S2

S2

S1

+1
+2

b0
(BIN)
(BIN)
(BIN)
n

+(n 2)
+(n 1)

4321
4000

(BIN)
(BIN)

D
D +1
D +2
D +(n 2)
D +(n 1)

D

b15
b0
7531 (BIN)
3210 (BIN)
551 (BIN)
n
679
352

(BIN)
(BIN)

(2) Block subtraction is performed in 16-bit units.
(3) The constant designated by
b15
8765
8888
9325

S1
S1
S1

S1
S1

+1
+2

b0
(BIN)
(BIN)
(BIN)

32768 and 32767 (BIN 16-bit data).
b15

b15
8880

S2

n

+(n 2) 5000
+(n 1) 4352

can be between

S2

(BIN)
(BIN)

b0
(BIN)

D
D +1
D +2
D +(n 2)
D +(n 1)

b0
115 (BIN)
8 (BIN)
445 (BIN)

n

3880 (BIN)
4528 (BIN)

(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag in this case does not go ON.

K 32768 K2
(8000H)
(0002H)

K32766
(7FFEH)

K32767
(7FFFH)

32767
(8001H)

K 2
(FFFEH)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The n-bit range from the
• The device ranges of
and

D

6-60

D

S2

and

D

)

• The device ranges of
and

S1

,

S1

)

or

D

device exceeds the range of that device.
(Error code: 4101)

overlap. (Except when the same device is assigned to

S1

(Error code: 4101)
S2

and

D

overlap. (Except when the same device is assigned to

S2

(Error code: 4101)

BK+(P),BK-(P)

Program Example

1

(1) The following program adds, when X20 is turned ON, the data stored at D100 to D103 to the
data stored at R0 to R3 and stores the operation result into the area starting from D200.
[Ladder Mode]

[List Mode]
Step

2

Device

Instruction

3
4

[Operation]
b15
D100 6789
D101 7821
D102 5432
D103 3520
D0

b0
(BIN)
(BIN)
(BIN)
(BIN)

R0
R1
R2
R3

b15
1234
2032
3252
1000

b0
(BIN)
(BIN)
(BIN)
(BIN)

b15
D200 8023
D201 9853
D202 2180
D203 2520

b0
(BIN)
(BIN)
(BIN)
(BIN)

4

4

6

(2) The following program subtracts, when X1C is turned ON, the constant 8765 from the data
at D100 to D102 and stores the operation result into the area starting from R0.
[Ladder Mode]

[List Mode]
Step

7

Device

Instruction

8
[Operation]
b15
8765

b0
(BIN)

R0
R1
R2

b15
b0
3580 (BIN)
64 (BIN)
5263 (BIN)

6.2 Arithmetic Operation Instructions
6.2.13 Block addition and subtraction (BK+(P),BK-(P))

b15
b0
D100 12345 (BIN)
D101 8701 (BIN)
D102 3502 (BIN)

6-61

DBK+(P),DBK-(P)

6.2.14

BIN 32-bit data block addition and subtraction operations
(DBK+(P),DBK-(P))

DBK+(P),DBK-(P)

Ver.
Basic

High
performance

Process Redundant Universal

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.
QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

indicates an instruction symbol of DBK+, DBK- .
Command

DBK+,DBK-

S1

S2

D

n

S1

S2

D

n

Command

DBKP+,DBK-P

P

S1

: Head number of the devices where the data to be added and subtracted are stored (BIN 32 bits)

S2

: Addition and subtraction data or head number of the devices where the addition and subtraction data are
stored (BIN 32 bits)

D : Head number of the devices where the addition and subtraction operation result will be stored (BIN 32 bits)
n: Number of addition and subtraction data blocks (BIN 16 bits)

Setting
Data

Internal Devices
Bit

Word

R, ZR

J
Bit

\
Word

U

S1

––

––

S2

––

––

D

––

––

n

––

Zn

\G

Constants
K,H

Other

––

––
––

––

––
––

Function
DBK+
(1) This instruction adds BIN 32-bit data stored in n-point devices starting from the device
specified by

S1

to BIN 32-bit data stored in n-point devices starting from the device specified

by S2 or a constant. and then stores the operation result into the nth device specified by
and up,
When a device is specified for
S1 ＋1,
S1 ＋3,
S1 ＋5,

b31
b0
-30000 (BIN)
40000 (BIN)
S1 ＋2
-50000 (BIN) n
S1 ＋4

S1 ＋n 1, S1 ＋n 2 60000

6-62

S2 ＋1,

S1

(BIN)

S2 ＋3,

＋

S2 ＋5,

D

S2

b31
b0
50000 (BIN)
20000 (BIN)
S2 ＋2
-10000 (BIN) n
S2 ＋4
S2

S2 ＋n 1, S2 ＋n 2 -20000

(BIN)

D ＋1,
D ＋3,
D ＋5,

D
D ＋2
D ＋4

b31
b0
20000 (BIN)
60000 (BIN)
-60000 (BIN) n

D ＋n 1, D ＋n 2 40000

(BIN)

DBK+(P),DBK-(P)
When a constant is specified for
S1 ＋1,
S1 ＋3,
S1 ＋5,

b31
b0
-30000 (BIN)
40000 (BIN)
S1 ＋2
-50000 (BIN) n
S1 ＋4

S2

S1

S1 ＋n 1, S1 ＋n 2 60000

＋

S2 ＋1,

S2

b31
b0
50000 (BIN)

D ＋1,
D ＋3,
D ＋5,

D
D ＋2
D ＋4

b31
b0
20000 (BIN)
90000 (BIN)
0 (BIN) n

1
2

D ＋n 1, D ＋n 2 110000 (BIN)

(BIN)

3

(2) Block addition is executed in 32-bit units.
(3) The constant in the device specified by
(BIN 32-bit data).

S2

can be between

2147483648 to 2147483647

4

(4) If the value specified by n is 0, the instruction will be not processed.
(5) The following will happen if an overflow occurs in an operation result:
The carry flag in this case is not turned on.

4

K 2147483647
・K2147483647+K2
(7FFFFFFFH) (00000002H ) ( 80000001H)

6

K2147483647
・ K 2147483647 +K 2
(80000001H) ( FFFFFFFEH) (7FFFFFFFH)

7

DBK(1) This instruction subtracts BIN 32-bit data stored in the n-point devices starting from the
device specified by

S2

or a constant from BIN 32-bit data stored in n-point devices starting

from the device specified by
specified by

D

S1

S1 ＋5,

b31
b0
-55555 (BIN)
33333 (BIN)
S1 ＋2
44444 (BIN) n
S1 ＋4

S2 ＋1,

S1

S1 ＋n 1, S1 ＋n 2 13579

S2 ＋3,
S2 ＋5,

S2

b31
b0
44445 (BIN)
3333 (BIN)
S2 ＋2
-10000 (BIN) n
S2 ＋4
S2

S2 ＋n 1, S2 ＋n 2 12345

(BIN)

When a constant is specified for
S1 ＋1,
S1 ＋3,
S1 ＋5,

b31
b0
-99999 (BIN)
99999 (BIN)
S1 ＋2
-59999 (BIN) n
S1 ＋4

(BIN)

S1 ＋n 1, S1 ＋n 2 79999

D
D ＋2
D ＋4

b31
b0
-1000000 (BIN)
30000 (BIN)
54444 (BIN) n

D ＋n 1, D ＋n 2

1234 (BIN)

S2

S1

b31
S2 ＋1,

D ＋1,
D ＋3,
D ＋5,

S2

b0
9999 (BIN)

(BIN)

D ＋1,
D ＋3,
D ＋5,

D
D ＋2
D ＋4

b31
b0
-109998 (BIN)
90000 (BIN)
69998 (BIN) n

D ＋n 1, D ＋n 2

70000 (BIN)

(2) Block subtraction is executed in 32-bit units.
(3) The constant in the device specified by
(BIN 32-bit data).

S2

can be between

2147483648 to 2147483647

(4) If the value specified by n is 0, the instruction will be not processed.
(5)

D
S2

specifies out of the range of n-point devices starting from the device specified by

S1

and

.

However,

S1

and

S2

can specify the same device.

6-63

6.2 Arithmetic Operation Instructions
6.2.14 BIN 32-bit data block addition and subtraction operations (DBK+(P),DBK-(P))

S1 ＋3,

8

and up,

When a device is specified for
S1 ＋1,

, and then stores the operation result into the nth device

DBK+(P),DBK-(P)

(6) The following will happen if an overflow occurs in an operation result:
The carry flag in this case is not turned on.

K 2147483647
・K2147483647 −K−2
(7FFFFFFFH) (00000002H ) ( 80000001H )

K2147483647
・ K 2147483647 −K2
(80000001H) ( FFFFFFFEH ) ( 7FFFFFFFH )

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• A negative value is specified for n.

(Error code: 4100)

• The range of the n-point devices starting from the device specified by S1 , S2 , or D
exceeds the specified device range.
(Error code: 4101)
• The range of the n-point devices starting from the device specified by
range of the n-point devices starting from the device specified by
that

S1

and

D

D

overlaps with the

S1

. (Exclude the case

specify the same device.

(Error code: 4101)

• The range of the n-point devices starting from the device specified by
range of the n-point devices starting from the device specified by

D

.

overlaps with the

S2

(Error code: 4101)

(1) The following program adds the value data stored at R0 to R5 to the constant, and then
stores the operation result into D30 to D35, when M0 is turned on.
[Ladder Mode]

[List Mode]
Device

Instruction

Step

[Operation]
b31
600000
R1,R0
-800000
R3,R2
R5,R4
-123456

b0
＋

123456

b31
723456
D31,D30
-676544
D33,D32
D35,D34
0

b0

(2) The following program subtracts the value data stored at D50 to D59 from the value data
stored at D100 to D109, and then stores the operation result into R100 to R109, when M0 is
turned on.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
b31
D101,D100
D103,D102
D105,D104
D107,D106
D109,D108

6-64

b0
12345
54321
-12345
-54321
99999

b31
D51,D50
D53,D52
D55,D54
D57,D56
D58,D58

b0
11111
-11111
22222
-22222
33333

b31
R101,R100
R103,R102
R105,R104
R107,R106
R109,R108

b0
1234
65432
-34567
-32099
66666

$+(P)

6.2.15

Linking character strings ($+(P))

1
$+(P)

Basic

When two data are set (

D

+

D

S

High
performance

2

Process Redundant Universal

)

3

Command

$+

$+

S

D

$+P

S

D

4

Command

$+P

Setting
Data

4

S

: Data for linking or head number of the devices where the data for linking is stored (character string)

D

: Head number of the devices where the data to be linked is stored (character string)

Internal Devices
Bit

R, ZR

Word

J
Bit

\

U

Word

S

––

––

D

––

––

Constants
$

Zn

\G

6

Other

7

––
––

––

8

Function
by

D

S

after the character string data designated

and stores the result into the area starting with the device number designated by

D

.

The object of character string data is that character string data stored from device numbers
designated at
D
D +1
D +2

D

and

S

to that stored at "00H".

b15
b8 b7
b0
42H (B) 41H (A)
44H (D) 43H (C)
00H
45H (E)

S
S +1
S +2
S +3

"ABCDE"

b15
b8 b7
b0
32H (2) 31H (1)
34H (4) 33H (3)
36H (6) 35H (5)
00H
"123456"

D
D
D
D

+1
+2
+3
+4
D +5

b15
b8 b7
42H (B) 41H
44H (D) 43H
31H (1) 45H
33H (3) 32H
35H (5) 34H
00H
36H

b0
(A)
(C)
(E)
(2)
(4)
(6)

"ABCDE123456"

(2) When character strings are linked, the "00H", which indicates the end of character string
data designated at

D

, is ignored, and the character string designated at

the last character of the

D

S

is appended to

string.

6-65

6.2 Arithmetic Operation Instructions
6.2.15 Linking character strings ($+(P))

(1) Links the character string data designated by

$+(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The entire character string linked from the device number designated by D to the final
device number of the relevant device cannot be stored.
(Error code: 4101)
• The storage device numbers for the character strings designated by
• The character string of

and

S

D

exceeds 16383 characters.

S

and D overlap.
(Error code: 4101)
(Error code: 4101)

Program Example
(1) The following program links the character string stored from D10 to D12 to the character
string "ABCD" when X0 is ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
D10
D11
D12

b15
b8 b7
b0
62 H (b)
61H (a)
64 H (d)
63 H (c)
00H
65 H (e)

+

"ABCD"

D10
D11
D12
D13
D14

b15
b8 b7
61H
62 H (b)
63 H
64 H (d)
65 H
41H (A)
43H (C)
42H
44H
00H

Automatically stores "00H".

6-66

b0
(a)
(c)
(e)
(B)
(D)

$+(P)

When three data are set ( S1 + S2

D

)

1
Command

$+

$+

S1

S2

D

$+P

S1

S2

D

2

Command

$+P

Setting
Data

3

S1

: Data for linking or head number of the devices where the data for linking is stored (character string)

S2

: Data to be linked or head number of the devices where the data to be linked is stored (character string)

D

: Head number of the devices where the linking result will be stored (character string)

Internal Devices
Bit

Word

R, ZR

J
Bit

\
Word

U

Zn

\G

Constants
$

4

Other

S1

––

––

––

S2

––

––

––

D

––

––

––

4

6

––

7

Function
(1) Links the character string data designated by
by
S1
S1

after the character string data designated

and stores the result into the area starting with the device number designated by

b15
b8 b7
b0
46H (F) 48H (H)
+1 2DH ( ) 41H (A)
00H
+2

b15
b8 b7
b0
35H (5) 31H (1)
S2 +1 39H (9)
33H (3)
S2 +2
41H (A)
00H
S2

b15
b8 b7
46H (F) 48H
D
D +1 2DH ( ) 41H
D +2 35H (5) 31H
D +3 39H (9) 33H
00H
41H
D +4

D

.

b0
(H)
(A)
(1)
(3)
(A)

(2) When character strings are linked, the "00H" which indicates the end of character string data
indicated by

S1

, is ignored, and the character string indicated by

character of the

S1

S2

8

is appended to the last

string.

6-67

6.2 Arithmetic Operation Instructions
6.2.15 Linking character strings ($+(P))

S1

S1

S2

$+(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The entire character string linked from the device number designated by D to the final
device number of the relevant device cannot be stored.
(Error code: 4101)
• The storage device numbers for the character strings designated by

S1

• The storage device numbers for the character strings designated by

S2

• The character string of

S1

,

S2

and

D

exceeds 16383 characters.

and S2 overlap.
(Error code: 4101)
and D overlap.
(Error code: 4101)
(Error code: 4101)

Program Example
(1) The following program links the character string stored from D10 to D12 with the character
string "ABCD" when X0 is ON, and stores them in D100 onwards.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
b15
b8 b7
b0
61H (a)
D10 62 H (b)
63 H (c)
D11 64 H (d)
00H
65 H (e)
D12

+

"ABCD"

b15
b8 b7
61H
D100 62 H (b)
63 H
D101 64 H (d)
65 H
D102 41H (A)
42H
D103 43H (C)
00H
44H
D104
Automatically stores "00H".

6-68

b0
(a)
(c)
(e)
(B)
(D)

INC(P),DEC(P)

6.2.16

Incrementing and decrementing 16-bit BIN data
(INC(P),DEC(P))

1

INC(P),DEC(P)

Basic

High
performance

Process Redundant Universal

2
3

indicates an instruction symbol of INC/DEC.

4

Command

INC, DEC

D

4

Command
P

INCP, DECP

D

Setting
Data

: Head number of devices for INC (+1)/DEC (

Internal Devices
Bit

Word

J

R, ZR

6

1) operation (BIN 16 bits)

\

Bit

D

U

Word

Zn

\G

Constants

Other

7

––

D

8

Function
INC
D

(16-bit data).

D
b15

D
b0

b15

5678 (BIN)

b0
5679 (BIN)

(2) When INC/INCP operation is executed for the device designated by
32767, the value

32768 is stored at the device designated by

D

D

, whose content is

.

DEC
(1) Subtracts 1 from the device designated by

D

(16-bit data).

D
b15

D
b0

5678 (BIN)

b15
1

b0
5677 (BIN)

(2) When DEC/DECP operation is executed for the device designated by
32768, the value 32767 is stored at the device designated by

D

D

, whose content is

.

Operation Error
(1) There are no operation errors associated with the INC(P)/DEC(P) instruction.

6-69

6.2 Arithmetic Operation Instructions
6.2.16 Incrementing and decrementing 16-bit BIN data (INC(P),DEC(P))

(1) Adds 1 to the device designated by

INC(P),DEC(P)

Program Example
(1) The following program outputs the present value at the counter C0 to C20 to the area Y30 to
Y3F in BCD, every time X8 is turned ON. (When present value is less than 9999)
[Ladder Mode]
Outputs the present value of C (D+Z1) to
Y30 to Y3F in BCD.
Executes Z1 + 1.
Sets Z1 at "0" when Z1=21 or X7
(reset input) is ON.

[List Mode]
Step

Instruction

Device

(2) The following is a down counter program.
[Ladder Mode]
Transfers 100 to D8 when X7 goes ON.
In the state M38=OFF, decrement at D8 (D8 - 1) is
executed when X8 goes from OFF to ON.
At D8=0, M38 goes ON.

[List Mode]
Step

6-70

Instruction

Device

DINC(P),DDEC(P)

6.2.17

Incrementing and decrementing 32-bit BIN data
(DINC(P),DDEC(P))

1

DINC(P),DDEC(P)

Basic

High
performance

Process Redundant Universal

2
3

indicates an instruction symbol of DINC/DDEC.

4

Command

DINC, DDEC

D

4

Command
P

DINCP, DDECP

D

Setting
Data

6

: Head number of devices for DINC(+1) or DDEC(-1) operation (BIN 32 bits)

Internal Devices
Bit

D

J

R, ZR

Word

\

Bit

U

Word

Zn

\G

Constants

Other

7

––

D

8

Function
DINC

D +1

D

(32-bit data).

D

D +1

b31 b16 b15 b0
73500 (BIN)

D

b31 b16 b15 b0
73501 (BIN)

(2) When DINC/DINCP operation is executed for the device designated by
2147483647, the value

D

, whose content is

2147483648 is stored at the device designated by

D

.

DDEC
(1) Subtracts

1 from the device designated by
D +1

D

b31 b16 b15 b0
73500 (BIN)

D

(32-bit data).
D +1

1

D

b31 b16 b15 b0
73499 (BIN)

(2) When DDEC/DDECP operation is executed for the device designated by
is 0, the value

1 is stored at the device designated by

D

D

, whose content

.

Operation Error
(1) There are no operation errors associated with the DINC(P) or DDEC(P).

6-71

6.2 Arithmetic Operation Instructions
6.2.17 Incrementing and decrementing 32-bit BIN data (DINC(P),DDEC(P))

(1) Adds 1 to the device designated by

DINC(P),DDEC(P)

Program Example
(1) The following program adds 1 to the data at D0 and D1 when X0 is ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

(2) The following program adds 1 to the data set at X10 to X27 when X0 goes ON, and stores
the result at D3 and D4.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

(3) The following program subtracts 1 from the data at D0 and D1 when X0 goes ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

(4) The following program subtracts 1 from the data set at X10 to X27 when X0 goes ON, and
stores the result at D3 and D4.
[Ladder Mode]

[List Mode]
Step

6-72

Instruction

Device

BCD(P),DBCD(P)

6.3 Data conversion instructions
6.3.1

1

Conversion from BIN data to 4-digit and 8-digit BCD
(BCD(P),DBCD(P))

2

BCD(P),DBCD(P)
BCD(P), DBCD(P)

Basic

High
performance

Process Redundant Universal

3
4

indicates an instruction symbol of BCD/DBCD.

4

Command

BCD, DBCD

S

D

S

D

Command

BCDP, DBCDP

Setting
Data

P

S

: BIN data or head number of the devices where the BIN data is stored (BIN 16/32 bits)

D

: Head number of the devices where BCD data will be stored (BCD 4/8 digits)

Internal Devices
Bit

J

R, ZR

Word

\

Bit

U

Word

Zn

\G

6
7

Constants
K, H

Other
––

S

––

D

––

BCD
device designated by

D

to BCD data, and stores it at the

.

-32768 16384 8192 4096 2048 1024 512

S BIN 9999

S

0

0

1

0

0

1

1

256

128

64

32

16

8

4

2

1

1

0

0

0

0

1

1

1

1

Must always be "0".
8000 4000 2000 1000 800

D BCD 9999 1

0

0

1

1

BCD conversion

400

200

100

80

40

20

10

8

4

2

1

0

0

1

1

0

0

1

1

0

0

1

Thousands digits Hundreds digits

Tens digits

Ones digits

DBCD
Converts BIN data (0 to 99999999) at the device designated by
the device designated by

D

S

to BCD data, and stores it at

.
S (Lower 16 bits)

231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20

S +1 (Upper 16 bits)

0 0 0 0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1

100

101

102

104

105

106

BCD conversion

8
4
2
1
8
4
2
1
8
4
2
1
8
4
2
1
8
4
2
1
8
4
2
1
8
4
2
1
8
4
2
1

107

Must always be "0" (upper 5 digits).

103

S BIN 99999999

D BCD 99999999 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
Ten
millions
digits

Millions
digits

Hundred
thousands
digits

Ten
Thousands Hundreds
thousands digits
digits
digits

D +1 (Upper 4 digits)

Tens
digits

Ones
digits

D (Lower 4 digits)

6-73

6.3 Data conversion instructions
6.3.1 Conversion from BIN data to 4-digit and 8-digit BCD (BCD(P),DBCD(P))

Function
Converts BIN data (0 to 9999) at the device designated by

8

BCD(P), DBCD(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The data of

S

is other than 0 to 9999 at BCD instruction.

• The data of

S

or

S

(Error code: 4100)

+1 is other than 0 to 99999999 at DBCD instruction.
(Error code: 4100)

Program Example
(1) The following program outputs the present value of C4 from Y20 to Y2F to the BCD display
device.

Output
power supply

0 1 0 1

0 1 1 0

0 1 1 1

Y23
Y22
Y21
Y20
8
4
2
1

Y27
Y26
Y25
Y24
80
40
20
10

800
400
200
100

8000
4000
2000
1000

Y2B
Y2A
Y29
Y28

COM
Y2F
Y2E
Y2D
Y2C

Programmable Controller Output Module

1 0 0 0

7-segment display unit

[Ladder Mode]

[List Mode]
Step

Instruction

Device

(2) The following program outputs 32-bit data from D0 to D1 to Y40 to Y67.
Programmable Controller Output Module
Y67 to Y64

Y63 to Y60

Y5F to Y5C

Y5B to Y58

Y57 to Y54

Y53 to Y50

Y4F to Y4C

Y4B to Y48

Y47 to Y44

Output
power supply

7-segment display unit

[Ladder Mode]

[List Mode]
Step

6-74

Instruction

Device

Y43 to Y40

BIN(P),DBIN(P)

6.3.2

Conversion from BCD 4-digit and 8-digit data to BIN data
(BIN(P),DBIN(P))

1

BIN(P),DBIN(P)

High
performance

Basic

Process Redundant Universal

2
3

indicates an instruction symbol of BIN/DBIN.

4

Command

BIN, DBIN

S

D

S

D

Command

BINP, DBINP

P

S

: BCD data or head number of the devices where the BCD data is stored (BCD 4/8 digits)

D

: Head number of the devices where BIN data will be stored (BIN 16/32 bits)

Internal Devices

Setting
Data

4

Bit

J

R, ZR

Word

\

Bit

U

Word

Zn

\G

Constants
K, H

6
Other
––

S

––

D

7

––

8

Function
BIN
designated by

D

to BIN data, and stores at the device

.
8000 4000 2000 1000 800

S

S

BCD 9999

1

0

0

1

1

400

200

100

80

40

20

10

8

4

2

1

0

0

1

1

0

0

1

1

0

0

1

Thousands digits Hundreds digits

Tens digits

Ones digits

BIN conversion
32768 16384 8192 4096 2048 1024 512

D BIN 9999

0

0

1

0

0

1

1

256

128

64

32

16

8

4

2

1

1

0

0

0

0

1

1

1

1

Always filled with 0s.

DBIN
Converts BCD data (0 to 99999999) at device designated by
.

102

103

104

105

106

S

8
4
2
1
8
4
2
1
8
4
2
1
8
4
2
1
8
4
2
1
8
4
2
1
8
4
2
1
8
4
2
1

107

S +1

100

D

to BIN data, and stores at the

101

device designated by

S

S BCD 99999999 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
Ten
millions
digits

Millions
digits

Hundred
thousands
digits

Ones
digits

231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20

D +1

Ten
Thousands Hundreds Tens
thousands digits
digits
digits
digits
BIN conversion
D

D BIN 99999999

0 0 0 0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1
Always filled with 0s.

6-75

6.3 Data conversion instructions
6.3.2 Conversion from BCD 4-digit and 8-digit data to BIN data (BIN(P),DBIN(P))

Converts BCD data (0 to 9999) at device designated by

BIN(P),DBIN(P)

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• When values other than 0 to 9 are designated to any digits of

S

(Error code: 4100)
When the QCPU is used, the error above can be suppressed by turning ON SM722.
However, the instruction is not executed regardless of whether SM722 is turned ON or OFF
if the designated value is out of the available range.
For the BINP/DBINP instruction, the next operation will not be performed until the command
(execution condition) is turned from OFF to ON regardless of the presence/absence of an
error.

Program Example
(1) The following program converts the BCD data at X10 to X1B to BIN when X8 is ON, and stores it
at D8.

8
4
2
1
COM
0
1
1
0
X13
X12
X11
X10

80
40
20
10
COM
0
0
1
1
X17
X16
X15
X14

COM
X1F
X1E
X1D
X1C

Input
power supply

0
X1B
0
X1A
1
X19
0
X18

Can be used
in other purposes.

800
400
200
100
COM

BCD digital switch

Programmable Controller input module

[Ladder Mode]

[List Mode]
Step

6-76

Instruction

Device

BIN(P),DBIN(P)

(2) The following program converts the BCD data at X10 to X37 to BIN when X8 is ON, and stores it
at D0 and D1.
(Addition of the BIN data converted from BCD at X20 to X37 and the BIN data converted
from BCD at X10 to X1F)
BCD digital switch

2
Input power supply

X37 to X34

X33 to X30

X2F to X2C

X2B to X28

X27 to X24

1

X23 to X20

X1F to X1C

X1B to X18

X17 to X14

X13 to X10

3

Programmable Controller Output Module

[Ladder Mode]

4

[List Mode]
Step

Instruction

Device

4
6
7
If the data set at X10 to X37 is a BCD value which exceeds 2147483647, the value at D0
and D1 will be a negative value, because it exceeds the range of numerical values that can
be handled by a 32-bit device.

8

6.3 Data conversion instructions
6.3.2 Conversion from BCD 4-digit and 8-digit data to BIN data (BIN(P),DBIN(P))

6-77

FLT(P),DFLT(P)

6.3.3

Conversion from BIN 16 and 32-bit data to floating decimal
point (Single precision) (FLT(P),DFLT(P))

FLT(P),DFLT(P)

Ver.
Basic

High
performance

Process Redundant Universal

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

indicates an instruction symbol of FLT/DFLT.
Command

FLT, DFLT

S

D

S

D

Command

FLTP, DFLTP

P

S

: Integer data to be converted to 32-bit floating decimal point data or head number of the devices where the

D

: Head number of the devices where the converted 32-bit floating decimal point data will be stored

integer data is stored (BIN 16/32 bits)
(real number)
Setting
Data

Internal Devices
Bit

Word

J

R, ZR

\

Bit

Word

U

Constants
K, H

Zn

\G

Other
––

S
D

––

––

––

*1

*1:Available only in multiple Universal model QCPU

Function
FLT
(1) Converts 16-bit BIN data designated by

S

to 32-bit floating decimal point type real number,

and stores at device number designated by

D

S

.
D +1

D

BIN 16 bits
32-bit floating-point
real number

(2) BIN values between

32768 to 32767 can be designated by

S

.

DFLT
(1) Converts 32-bit BIN data designated by

S

to 32-bit floating decimal point type real number,

and stores at device number designated by
S +1
Upper 16 bits

S

6-78

.
D +1

D

Lower 16 bits

BIN 32 bits

(2) BIN values between

D

32-bit floating-point
real number

2147483648 to 2147483647 can be designated by

S

+1 and

S

.

FLT(P),DFLT(P)

(3) Due to the fact that 32-bit floating decimal point type real numbers are processed by simple
32-bit processing, the number of significant digits is 24 bits if the display is binary and
approximately 7 digits if the display is decimal.

1

For this reason, if the integer exceeds the range of 16777216 to 16777215 (24-bit BIN
value), errors can be generated in the conversion value.
As for the conversion result, the 25th bit from the upper bit of the integer is always filled with
1 and 26th bit and later bits are truncated.

2

Integer
b31
b24 b23
b16 b15
b8 b7
b0
222030030 0 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0

3

After conversion
Result of operation
is 222030032.
Truncation
Always filled with 1

b31
b24 b23
b16 b15
b8 b7
b0
372588919 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 1

4

Result of operation
is 372588928.
Truncation
Always filled with 1

6

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The result exceeds the following range (The overflow occurs.)
(For the Universal model QCPU only)
2128

4

| Operation result |

(Error code: 4141)

7
8

6.3 Data conversion instructions
6.3.3 Conversion from BIN 16 and 32-bit data to floating decimal point (Single precision)
(FLT(P),DFLT(P))

6-79

FLT(P),DFLT(P)

Program Example
(1) The following program converts the BIN 16-bit data at D20 to a 32-bit floating decimal point
type real number and stores the result at D0 and D1.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
D20

Integer
conversion

D1

15923

D0
15923

BIN value

32-bit floating-point
real number

(2) The following program converts the BIN 32-bit data at D20 and D21 to a 32-bit floating
decimal point type real number, and stores the result at D0 and D1.
[Ladder Mode]

[List Mode]
Step

Instruction

[Operation]
D21

D20

Integer
conversion

16543521

D20

173963112
BIN value

D0

16543521

BIN value
D21

D1

Integer
conversion

32-bit floating-point
real number
An error is generated in operation results since
the number of significant digits is "7".
D1
D0
173963120
32-bit floating-point
real number

6-80

Device

FLTD(P),DFLTD(P)

6.3.4

Conversion from BIN 16 and 32-bit data to floating decimal
point (Double precision) (FLTD(P),DFLTD(P))

1

FLTD(P),DFLTD(P)

High
performance

Basic

Process Redundant Universal

2
3

indicates an instruction symbol of FLTD/DFLTD.

4

Command

FLTD, DFLTD

S

D

S

D

4

Command

FLTDP, DFLTDP

P

S

: Integer data to be converted to 64-bit floating decimal point data or head number of the devices where the

6

integer data is stored (BIN 16/32 bits)
D

: Head number of the devices where the converted 64-bit floating decimal point data will be stored

7

(real number)
Setting
Data

Internal Devices
Bit

R, ZR

Word

J

\

Bit

Word

S

––

––

D

––

––

U

Constants
K, H

Zn

\G

Other
––

––

––

FLTD
S

to 64-bit floating decimal point type real number,

and stores at device number designated by

D

.

D +3 D +2 D +1

S

D

BIN 16 bits
64-bit floating-point
real number

(2) BIN values between

32768 to 32767 can be designated by

S

.

DFLTD
(1) Converts 32-bit BIN data designated by

S

to 64-bit floating decimal point type real number,

and stores at device number designated by
S +1

S

Upper 16 bits

Lower 16 bits

BIN 32 bits

(2) BIN values between

D

.
D +3 D +2 D +1

D

64-bit floating-point
real number

2147483648 to 2147483647 can be designated by

S

+1 and

S

.

6-81

6.3 Data conversion instructions
6.3.4 Conversion from BIN 16 and 32-bit data to floating decimal point (Double precision)
(FLTD(P),DFLTD(P))

Function
(1) Converts 16-bit BIN data designated by

8

FLTD(P),DFLTD(P)

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The result exceeds the following range (Operation results in an overflow):
21024

| Operation result |

(Error code: 4141)

Program Example
(1) The following program converts the BIN 16-bit data at D20 to a 64-bit floating decimal point
type real number and stores the result at D0 to D3.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
D20
15923

Conversion to real number D3 D2 D1 D0
15923

BIN value

64-bit floating-point
real number

(2) The following program converts the BIN 32-bit data at D20 and D21 to a 64-bit floating
decimal point type real number, and stores the result at D0 to D3.
[Ladder Mode]

[List Mode]
Step

[Operation]
D21

D20

16543521
BIN value

6-82

Conversion to real number D3 D2

D1 D0

16543521
64-bit floating-point
real number

Instruction

Device

INT(P),DINT(P)

6.3.5

Conversion from floating decimal point data to BIN16- and
32-bit data (Single precision) (INT(P),DINT(P))

1

INT(P),DINT(P)

Ver.
High
performance

Basic

Process Redundant Universal

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

indicates an instruction symbol of INT/DINT.

S

D

S

D

4

Command

INTP, DINTP

P

3
4

Command

INT, DINT

2

S

: 32-bit floating decimal point data to be converted to BIN value or head number of the devices where the

D

: Head number of the devices where the converted BIN value will be stored (BIN 16/32 bits)

6

floating decimal point data is stored (real number)

Setting
Data
S

Internal Devices
Bit

Word

J

R, ZR

\

Bit

––

U

Word

Constants
E

Zn

\G

––

7
Other
––

*1
––

D

8

––

*1:Available only in multiple Universal model QCPU

INT
(1) Converts the 32-bit floating decimal point real number designated at
and stores it at the device number designated at D .
S +1

S

into BIN 16-bit data

S

D
BIN16-bit

32-bit floating-point
real number

(2) The range of 32-bit floating decimal point type real numbers that can be designated at
or S is from 32768 to 32767.
(3) Stores integer values stored at

D

S

+1

as BIN 16-bit values.

(4) After conversion, the first digit after the decimal point of the real number is rounded off.

DINT
(1) Converts 32-bit floating decimal point type real number designated by
and stores the result at the device number designated by D .
S +1

S

32-bit floating-point
real number

D +1

D

Upper 16 bits

Lower 16 bits

S

to BIN 32-bit data,

BIN 32 bits

(2) The range of 32-bit floating decimal point type real numbers that can be designated at
or S is from 2147483648 to 2147483647.

S

+1

6-83

6.3 Data conversion instructions
6.3.5 Conversion from floating decimal point data to BIN16- and 32-bit data (Single precision)
(INT(P),DINT(P))

Function

INT(P),DINT(P)

(3) The integer value stored at

D

+1 and

D

is stored as BIN 32 bits.

(4) After conversion, the first digit after the decimal point of the real number is rounded off.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The contents of the designated device or the result of the addition are not "0", or not within
the following range(For the Universal model QCPU only):
0, 2-126

| Contents of designated device | < 2128

(Error code: 4140)

• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU only)
(Error code: 4140)
• The 32-bit floating decimal point type data designated by
used was outside the

S

when the INT instruction was

31768 to 32767 range.

(Error code: 4100)

• The 32-bit floating decimal point type data designated by
was used was outside the

S

when the DINT instruction

2147483648 to 2147483647 range.

(Error code: 4100)

Program Example
(1) The following program converts the 32-bit floating decimal point type real number at D20
and D21 to BIN 16-bit data, and stores the result at D0.
[Ladder Mode]

[List Mode]
Step

[Operation]
D20
D21
25915.6796

Integer
conversion

BIN value

32-bit floating-point
real number
D20
D21
-33562.3211
32-bit floating-point
real number

6-84

D0
25916

Integer
conversion

An operation error occurs
since "setting data < -32768."

Instruction

Device

INT(P),DINT(P)

(2) The following program converts the 32-bit floating decimal point type real number at D20
and D21 to BIN 32-bit data and stores the result at D0 and D1.
[Ladder Mode]

[List Mode]
Step

Instruction

1

Device

2
[Operation]
D20
D21
-574968.321

Integer
conversion

32-bit floating-point
real number

D1
D0
-574968

4

BIN value

32-bit floating-point
real number
D20
D21
2147483649.22

3

Integer
conversion

4

An operation error occurs
since "setting data > 2147483647."

6
7
8

6.3 Data conversion instructions
6.3.5 Conversion from floating decimal point data to BIN16- and 32-bit data (Single precision)
(INT(P),DINT(P))

6-85

INTD(P),DINTD(P)

6.3.6

Conversion from floating decimal point data to BIN16- and
32-bit data (Double precision) (INTD(P),DINTD(P))

INTD(P),DINTD(P)

High
performance

Basic

Process Redundant Universal

indicates an instruction symbol of INTD/DINTD.
Command

INTD, DINTD

S

D

S

D

Command

INTDP, DINTDP

P

: 64-bit floating decimal point data to be converted to BIN value or head number of the devices where the

S

floating decimal point data is stored (real number)
: Head number of the devices where the converted BIN value will be stored (BIN 16/32 bits)

D

Internal Devices

Setting
Data

Bit

Word

J

R, ZR

Bit

\

U

Word

S

––

––

D

––

––

Constants
E

Zn

\G

Other

––

––
––

––

Function
INTD
(1) Converts the 64-bit floating decimal point real number designated at
and stores it at the device number designated at
S +3 S +2 S +1

D

into BIN 16-bit data

S

.
D

S

BIN 16 bit
64-bit floating-point
real number

(2) The range of 64-bit floating decimal point type real numbers that can be designated at
S

+3,

S

+2,

S

+1 or

S

is from

(3) Stores integer values stored at

32768 to 32767.
D

as BIN 16-bit values.

(4) The converted data is the value rounded 64-bit floating-point real number to the first digit
after the decimal point.

DINTD
(1) Converts 64-bit floating decimal point type real number designated by
and stores the result at the device number designated by
S +3 S +2 S +1

64-bit floating-point
real number

6-86

S

D

.

D +1

D

Upper 16 bits

Lower 16 bits

BIN 32 bit

S

to BIN 32-bit data,

INTD(P),DINTD(P)

(2) The range of 64-bit floating decimal point type real numbers that can be designated at
S

+3,

S

+2,

S

+1 or

S

is from

(3) The integer value stored at

D

2147483648 to 2147483647.
+1 and

D

1

is stored as BIN 32 bits.

(4) The converted data is the value rounded 64-bit floating-point real number to the first digit
after the decimal point.

Operation Error

3

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range:
0, 2-1022

2

0.

(Error code: 4140)

• The 64-bit floating decimal point type data designated by
was used was outside the

S

(Error code: 4100)
S

4

when the INTD instruction

31768 to 32767 range.

• The 64-bit floating decimal point type data designated by
was used was outside the

4

21024

| value of specified device |

• The value of the designated device is

(Error code: 4140)

6

when the DINTD instruction

2147483648 to 2147483647 range.

(Error code: 4100)

7

Program Example
(1) The following program converts the 64-bit floating decimal point type real number at D20 to
D23 with BIN 16-bit data, and stores the result at D0.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

D0
D23 D22 D21 D20 Conversion to integer
25916
25915.6796
BIN value
64-bit floating-point real number
D23 D22 D21 D20 Conversion to integer
33562.3211
An operation erroe occurs because the specified data is larger than -32768.
64-bit floating-point real number

(2) The following program converts the 64-bit floating decimal point type real number at D20 to
D23 with BIN 32-bit data and stores the result at D0 and D1.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
D1
D0
574968
BIN value

D23 D22 D21 D20 Conversion to integer
2147483649.22
An operation erroe occurs because the
specified data is larger than 2147483647.
64-bit floating-point real number

6-87

6.3 Data conversion instructions
6.3.6 Conversion from floating decimal point data to BIN16- and 32-bit data (Double precision)
(INTD(P),DINTD(P))

[Operation]

D23 D22 D21 D20 Conversion to integer
574968.321
64-bit floating-point real number

8

DBL(P)

6.3.7

Conversion from BIN 16-bit to BIN 32-bit data (DBL(P))

DBL(P)

Basic

High
performance

Process Redundant Universal

Command

DBL

DBL

S

D

DBLP

S

D

Command

DBLP

Setting
Data

S

: BIN 16-bit data or head number of the devices where the BIN 16-bit data is stored (BIN 16 bits)

D

: Head number of the devices where the converted BIN 32-bit data will be stored (BIN 32 bits)

Internal Devices
Bit

Word

R, ZR

J

\

Bit

U

Word

\G

Zn

Constants
K, H

Other
––

S

––

D

––

Function
Converts BIN 16-bit data at device designated by
result at a device designated by

D

S
BIN 16-bit data

S

to BIN 32-bit data with sign, and stores the

.
D +1

D

Upper 16 bits

Lower 16 bits

BIN 32-bit data

Operation Error
(1) There are no errors associated with the DBL(P) instruction.

Program Example
(1) The following program converts the BIN 16-bit data stored at D100 to BIN 32-bit data when
X20 is ON, and stores at R100 and R101.
[Ladder Mode]

[List Mode]
Step

[Operation]
D100
FB2EH
( 1234)

6-88

R101 R100
FFFFFB2EH
( 1234)

Instruction

Device

WORD(P)

6.3.8

Conversion from BIN 32-bit to BIN 16-bit data (WORD(P))

1
WORD(P)

Basic

High
performance

Process Redundant Universal

3

Command

WORD

WORD

S

D

WORDP

S

D

4

Command

WORDP

Setting
Data

S

: BIN 32-bit data or head number of the devices where the BIN 32-bit data is stored (BIN 32 bits)

D

: Head number of the devices where the converted BIN 16-bit data will be stored (BIN 16 bits)

Internal Devices
Bit

Word

R, ZR

2

J

\

Bit

U

Word

\G

Zn

Constants
K, H

4
Other

6

––

S

––

D

––

7
8

Function
Converts BIN 32-bit data at device designated by
result at a device designated by D .

S

to BIN 16-bit data with sign, and stores the

S +1

S

Upper 16 bits

Lower 16 bits

D
BIN 16-bit data

BIN 32-bit data

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The contents of the data designated by
32767.

S

+1 and

S

are outside the range of 32768 to
(Error code: 4100)

Program Example
(1) The following program converts the BIN 32-bit data at R100 and R101 to BIN 16-bit data
when X20 is ON, and stores it at D100.
[Ladder Mode]
[List Mode]
Step

Instruction

Device

[Operation]
R101 R100
FFFF8253 H
(-32173)

D100
8253H
(-32173)

6-89

6.3 Data conversion instructions
6.3.8 Conversion from BIN 32-bit to BIN 16-bit data (WORD(P))

Devices can be designated in the range from -32768 to 32767.

GRY(P),DGRY(P)

6.3.9

Conversion from BIN 16 and 32-bit data to Gray code
(GRY(P),DGRY(P))

GRY(P),DGRY(P)

Basic

High
performance

Process Redundant Universal

indicates an instruction symbol of GRY, DGRY.
Command

GRY, DGRY

S

D

S

D

Command

GRYP, DGRYP

Setting
Data

P

S

: BIN data or head number of the devices where the BIN data is stored (BIN 16/32 bits)

D

: Head number of the devices where the converted Gray code will be stored (BIN 16/32 bits)

Internal Devices
Bit

J

R, ZR

Word

\

Bit

U

Word

Zn

\G

Constants
K, H

Other
––

S

––

D

Function
GRY
Converts BIN 16-bit data at the device designated by
device designated by

D

S

to Gray code, and stores result at

.
16 bits

S BIN 1234

b15
0 0

0

0

0

1

0

0

1

1

0

1

0

0

1

b0
0

D Gray code 1234

b15
0 0

0

0

0

1

1

0

1

0

1

1

1

0

1

b0
1

DGRY
Converts BIN 32-bit data at the device designated by
device designated by

D

to Gray code, and stores result at

.
S +1 (Upper 16 bits)

S BIN 305419896

S

S (Lower 16 bits)

b31
b16 b15
b0
000 100 1000 110 1000 10 10 1100 1111000

D +1

D

b31
b16 b15
b0
D Gray code 305419896 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 0 0

6-90

––

GRY(P),DGRY(P)

Operation Error

1

(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The data at

S

is a negative number.

(Error code: 4100)

Program Example

3

(1) The following program converts the BIN data at D100 to Gray code when X10 is ON, and
stores result at D200.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[List Mode]
Step

Instruction

4
4

(2) The following program converts the BIN data at D10 and D11 to Gray code when X1C is ON,
and stores it at D100 and D101.
[Ladder Mode]

2

6
7

Device

8

6.3 Data conversion instructions
6.3.9 Conversion from BIN 16 and 32-bit data to Gray code (GRY(P),DGRY(P))

6-91

GBIN(P),DGBIN(P)

6.3.10

Conversion of Gray code to BIN 16 and 32-bit data
(GBIN(P),DGBIN(P))

GBIN(P),DGBIN(P)

Basic

High
performance

Process Redundant Universal

indicates an instruction symbol of GBIN/DGBIN.
Command

GBIN, DGBIN

S

D

S

D

Command

GBINP, DGBINP

P

S

: Gray code data or head number of the devices where the Gray code data is stored (BIN 16/32 bits)

D

: Head number of the devices where the converted BIN data will be stored (BIN 16/32 bits)

Internal Devices

Setting
Data

Bit

J

R, ZR

Word

\

Bit

U

Word

Zn

\G

Constants
K, H

Other
––

S

––

D

––

Function
GBIN
Converts Gray code data at device designated by
designated by

D

S

to BIN 16-bit data and stores at device

.
16 bit

b15
S Gray code 1234 0 0

0

0

0

1

1

0

1

0

1

1

1

0

1

b0
1

b15
0 0

0

0

0

1

0

0

1

1

0

1

0

0

1

b0
0

D BIN 1234

DGBIN
Converts Gray code data at device designated by
designated by

D

S

to BIN 32-bit data and stores at device

.
S +1 (Upper 16 bits)

S (Lower 16 bits)

b31
b16 b15
b0
S Gray code 305419896 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 0 0

D +1

D BIN 305419896

6-92

D

b31
b16 b15
b0
00010010001101000101011001111000

GBIN(P),DGBIN(P)

Operation Error

1

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• Data at

S

• Data at

S

when the GBIN instruction was issued is outside the 0 to 32767 range.
(Error code: 4100)
when the DGBIN instruction was issued is outside the 0 to 2147483647 range.
(Error code: 4100)

(1) The following program converts the Gray code data at D100 when X10 is ON to BIN data,
and stores the result at D200.

4

[List Mode]
Step

Instruction

Device

6

(2) The following program converts the Gray code data at D10 and D11 to BIN data when X1C
is ON, and stores the result at D0 and D1.
[Ladder Mode]

3
4

Program Example

[Ladder Mode]

2

[List Mode]
Step

Instruction

7
8

Device

6.3 Data conversion instructions
6.3.10 Conversion of Gray code to BIN 16 and 32-bit data (GBIN(P),DGBIN(P))

6-93

NEG(P),DNEG(P)

6.3.11

Complement of 2 of BIN 16- and 32-bit data (sign reversal)
(NEG(P),DNEG(P))

NEG(P),DNEG(P)

High
performance

Basic

Process Redundant Universal

indicates an instruction symbol of NEG/DNEG.
Command

NEG, DNEG

D
Command

NEGP, DNEGP

P

D

D

: Head number of the devices where the data for which complement of 2 is performed is stored
(BIN 16/32 bits)

Setting
Data

Internal Devices
Bit

J

R, ZR

Word

\

Bit

U

Word

Zn

\G

Constants

Other
––

D

Function
NEG
(1) Reverses the sign of the 16-bit device designated by
by

D

and stores at the device designated

D

.
16 bit
b15
1 0

Before execution D
1

Sign conversion

After execution

D

1

0

1

0

1

0

1

0

1

0

1

0

1

b0
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

b15
0 1

0

1

0

1

0

1

0

1

0

1

0

1

1

b0
0

(2) Used when reversing positive and negative signs.

6-94

-21846

21846

NEG(P),DNEG(P)

DNEG
(1) Reverses the sign of the 32-bit device designated by
by

D

D

and stores at the device designated

1

.

2

32 bit
b31
1 1

Before
execution D
1
Sign
conversion -

1

1

1

1

0

1

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

0

1

0

0

1

0

0

1

b0
0 0

b31
0 0

After
execution D

1

b0
0 0

0

0

0

0

0

1

0

1

1

-218460

3
4
218460

4

(2) Used when reversing positive and negative signs.

Operation Error

6

(1) There are no operation errors associated with the NEG(P) or DNEG(P) instruction.

7

Program Example
(1) The following program calculates a total for the data at D10 through D20 when XA goes ON,
and seeks an absolute value if the result is negative.

8

[Ladder Mode]
M3 is turned ON if D10 < D20.
6.3 Data conversion instructions
6.3.11 Complement of 2 of BIN 16- and 32-bit data (sign reversal) (NEG(P),DNEG(P))

Executes "D10 - D20".
Calculates the absolute value
(complement of 2) when M3 is ON.

[List Mode]
Step

Instruction

Device

6-95

ENEG(P)

6.3.12

Floating-point sign invertion (Single precision) (ENEG(P))

ENEG(P)

Ver.
Basic

High
performance

Process Redundant Universal

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

Command

ENEG

ENEG

D

ENEGP

D

Command

ENEGP

D

: Head number of the devices where the 32-bit floating decimal point data whose sign is to be reversed is
stored (real number)

Internal Devices

Setting
Data

Bit

Word

J

R, ZR

––

D

\

Bit

Word

U

\G

––

Zn

Constants

Other
––

*1

*1:Available only in multiple Universal model QCPU

Function
(1) Reverses the sign of the 32-bit floating decimal point type real number data designated by
D , and stores at the device designated by D .
(2) Used when reversing positive and negative signs.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The contents of the designated device or the result of the addition are not "0", or not within
the following range(For the Universal model QCPU only):
0, 2-126
| Contents of designated device | < 2128
(Error code: 4140)
• The value of the specified device is 0, unnormalized number, nonnumeric, and ± .
(For the Universal model QCPU only)
(Error code: 4140)

Program Example
(1) The following program inverts the sign of the 32-bit floating decimal point type real number
data at D100 and D101 when X20 goes ON, and stores result at D100 and D101.
[Ladder Mode]

[List Mode]
Step

[Operation]
D101

D100

1.2345

6-96

D101

D100

1.2345

Instruction

Device

EDNEG(P)

6.3.13

Floating-point sign invertion (Double precision)
(EDNEG(P))

1

EDNEG(P)

Basic

High
performance

Process Redundant Universal

2
3

Command

EDNEG

EDNEG

D

EDNEGP

D

4

Command

EDNEGP

4

: Head number of the devices where the 64-bit floating decimal point data whose sign is to be reversed is

D

6

stored (real number)
Internal Devices

Setting
Data

Bit

Word

R, ZR

J

\

Bit

Word

U

––

D

Zn

\G

Constants

Other

7

––

8

Function
(1) Reverses the sign of the 64-bit floating decimal point type real number data designated by
D

, and stores at the device designated by

.

D

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range:
0, 2

-1022

(Error code: 4140)

1024

| value of specified device | < 2

• The value of the designated device is

0.

(Error code: 4140)

Program Example
(1) The following program inverts the sign of the 64-bit floating decimal point type real number
data at D100 to D103 when X20 goes ON, and stores result at D100 to D103.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
D3 D2

D1 D0

D3 D2

D1 D0

1.2345

6-97

6.3 Data conversion instructions
6.3.13 Floating-point sign invertion (Double precision) (EDNEG(P))

(2) Used when reversing positive and negative signs.

BKBCD(P)

6.3.14

Conversion from block BIN 16-bit data to BCD 4-digit data
(BKBCD(P))

BKBCD(P)

Basic

High
performance

Process Redundant Universal

Command

BKBCD

BKBCD

S

D

n

BKBCDP

S

D

n

Command

BKBCDP

S

: Head number of the devices where BIN data is stored (BIN 16 bits)

D

: Head number of the devices where the converted BCD data will be stored (BCD 4 digits)

n : Number of variable data blocks (BIN 16 bits)
Setting
Data

Internal Devices
Bit

Word

R, ZR

J

\

Bit

Word

U

\G

Zn

Constants
K, H

Other

S

––

––

––

D

––

––

––

n

––

Function
(1) Converts BIN data (0 to 9999) n points from device designated by
D

.

Must always be "0".

8192
4096
2048
1024
512
256
128
64
32
16
8
4
2
1

result following the device designated by

S

BIN 1234

00000 100110 10010

S +1

BIN 5678

000 10 11000 10 1110

S +2

BIN 1545

0000011000001001

S +(n

2) BIN 4321

000 10000 1110000 1

S +(n

1) BIN 5555

000 10 101101100 11

n

8000
4000
2000
1000
800
400
200
100
80
40
20
10
8
4
2
1

BCD conversion

D

BCD 1234 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0

D +1

BCD 5678 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0

D +2

BCD 1545 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0 1

D +(n 2) BCD 4321 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1
D +(n 1) BCD 5555 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

6-98

n

S

to BCD, and stores

BKBCD(P)

Operation Error

1

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The range of the device n points from a device designated by
relevant device.
• The data n points from the device designated by
• The

S

and

D

S

,

D

or exceeds the
(Error code: 4101)

is outside the 0 to 9999 range.
(Error code: 4100)

S

devices overlap.

(Error code: 4101)

2
3
4

Program Example
(1) The following program converts, when X20 is turned ON, the BIN data stored at D100 to
D102 to BCD and stores the operation result into the area starting from D200.
[Ladder Mode]

[List Mode]
Step

Instruction

4
6

Device

7
[Operation]
8192
4096
2048
1024
512
256
128
64
32
16
8
4
2
1

8

D100 BIN 5432

000 10 10 100 111000

D101 BIN 4444

000 1000 10 10 11100

D102 BIN 3210

0000110010001010
3

8000
4000
2000
1000
800
400
200
100
80
40
20
10
8
4
2
1

D0

6.3 Data conversion instructions
6.3.14 Conversion from block BIN 16-bit data to BCD 4-digit data (BKBCD(P))

BCD
conversion

D200 BCD 5432 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0
D201 BCD 4444 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
D202 BCD 3210 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0

6-99

BKBIN(P)

6.3.15

Conversion from block BCD 4-digit data to block BIN 16-bit
data (BKBIN(P))

BKBIN(P)

Basic

High
performance

BKBIN

S

D

n

BKBINP

S

D

n

Process Redundant Universal

Command

BKBIN
Command

BKBINP
S

: Head number of the devices where BCD data is stored (BCD 4 digits)

D

: Head number of the devices where the converted BIN data will be stored (BIN 16 bits)

n : Number of variable data blocks (BIN 16 bits)
Setting
Data

Internal Devices
Bit

Word

R, ZR

J

\

Bit

Word

U

\G

Zn

Constants
K, H

Other

S

––

––

––

D

––

––

––

n

––

Function
(1) Converts BCD data (0 to 9999) n points from device designated by
D

.

8000
4000
2000
1000
800
400
200
100
80
40
20
10
8
4
2
1

result following the device designated by

D

BCD 1234 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0

D +1

BCD 5678 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0

D +2

BCD 1545 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0 1

D +(n

2) BCD 4321 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1

D +(n

1) BCD 5555 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

n

8192
4096
2048
1024
512
256
128
64
32
16
8
4
2
1

BIN conversion

6-100

S

BIN 1234

00000100110 100 10

S +1

BIN 5678

000 10 11000 10 1110

S +2

BIN 1545 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1

S +(n

2) BIN 4321 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1

S +(n

1) BIN 5555 0 0 0 1 0 1 0 1 1 0 1 1 0 0 1 1

n

S

to BIN, and stores

BKBIN(P)

Operation Error

1

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The n-bit range from the
• The data n points at the

S

S

,

D

, or device exceeds the range of that device.
(Error code: 4101)

device is outside the 0 to 9999 range.
(Error code: 4100)

• The

S

and

D

devices overlap.

(Error code: 4101)

2
3
4

Program Example
(1) The following program converts, when X20 is turned ON, the BCD data stored at D100 to
D102 to BIN and stores the operation result into the area starting from D200.
[Ladder Mode]

[List Mode]
Step

Instruction

4
6

Device

7
[Operation]
8000
4000
2000
1000
800
400
200
100
80
40
20
10
8
4
2
1

8

D100 BCD 8080 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0
D101 BCD 7654 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0
D102 BCD 9999 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
6.3 Data conversion instructions
6.3.15 Conversion from block BCD 4-digit data to block BIN 16-bit data (BKBIN(P))

8192
4096
2048
1024
512
256
128
64
32
16
8
4
2
1

BIN conversion
(when D0=3)

D200 BIN 8080

00 01111110010000

D201 BIN 7654

00 0111 011110 0110

D202 BIN 9999

0 010 0111000 01111

6-101

ECON(P)

6.3.16

Single precision to Double precision conversion
(ECON(P))

ECON(P)

Basic

High
performance

Process Redundant Universal

Command

ECON

ECON

S

D

ECONP

S

D

Command

ECONP
S

: Conversion source data, or head number of the device where conversion source data is stored

D

: Head number of the device where the converted data is stored (Real number (double precision))

(Real number (single precision))

Setting
Data

Internal Devices
Bit

Word

R, ZR

J

\

Bit

Word

U

S

––

––

D

––

––

Constants
E

Zn

\G

Other
––

––

––

Function
Converts 32-bit floating-point real number specified for

S

into 64-bit floating-point real

number, and stores the conversion result to the device specified for
S +1

S

D +3

32-bit floating-point real number

D +2

D +1

D

.

D

64-bit floating-point real number

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range:
0,2

-126

| value of specified device |

• The value of the specified device is

6-102

(Error code: 4140)

128

2

0, unnormalized number, nonnumeric, and ± .
(Error code: 4140)

ECON(P)

Program Example

1

(1) The program which converts 32-bit floating-point real number of the devices, D10 to D11,
into 64-bit floating-point real number when X0 turns ON, and outputs the conversion result to
the devices, D0 to D3.
[Ladder Mode]

2

[List Mode]
Step

Instruction

Device

3
4
4
6
7
8

6.3 Data conversion instructions
6.3.16 Single precision to Double precision conversion (ECON(P))

6-103

EDCON(P)

6.3.17

Double precision to Single precision conversion
(EDCON(P))

EDCON(P)

High
performance

Basic

Process Redundant Universal

Command

EDCON

EDCON

S

D

EDCONP

S

D

Command

EDCONP
S

: Conversion source data, or head number of the device where conversion source data is stored

D

: Head number of the device where the converted data is stored (Real number (single precision))

(Real number (double precision))

Setting
Data

Internal Devices
Bit

Word

R, ZR

J

\

Bit

Word

S

––

––

D

––

––

U

Constants
E

Zn

\G

––

Other
––

––

––

Function
Converts 64-bit floating-point real number specified for

S

into 32-bit floating-point real

number, and stores the conversion result to the device specified for
S +3

S +2

S +1

D +1

S

D

.

D

32-bit floating-point real number

64-bit floating-point real number

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The value of the specified device is not in the following range:
0,2-1022

| value of specified device |

• The value of the designated device is

(Error code: 4140)

21024
0.

(Error code: 4140)

• The result exceeds the following range (Conversion results in an overflow):
2128

6-104

| Conversion result |

(Error code: 4141)

EDCON(P)

Program Example

1

(1) The program which converts 64-bit floating-point real number of the devices, D10 to D13,
into 32-bit floating-point real number when X0 turns ON, and outputs the conversion result to
the devices, D0 to D1.
[Ladder Mode]

2

[List Mode]
Step

Instruction

Device

3
4
4
6
7
8

6.3 Data conversion instructions
6.3.17 Double precision to Single precision conversion (EDCON(P))

6-105

MOV(P),DMOV(P)

6.4 Data Transfer Instructions
6.4.1

16-bit and 32-bit data transfers (MOV(P),DMOV(P))

MOV(P),DMOV(P)

Basic

High
performance

Process Redundant Universal

indicates an instruction symbol of MOV/DMOV.
Command

MOV, DMOV

S

D

S

D

Command

MOVP, DMOVP

Setting
Data

P

S

: Data to be transferred or the number of the device where the data to be transferred is stored (BIN 16/32 bits)

D

: Number of the device where the data will be transferred (BIN 16/32 bits)

Internal Devices
Bit

J

R, ZR

Word

\

Bit

U

Word

Constants
K, H

Zn

\G

Other
––

S

––

D

––

Function
MOV
(1) Transfers the 16-bit data from the device designated by
Before transfer S

b15
1 0

D

b15
1 0

1

1

0

1

0

0

0

1

1

S

to the device designated by

1

0

0

1

b0
0

1

0

0

1

b0
0

Transfer
After transfer

1

1

0

1

0

0

0

1

1

DMOV
(1) Transfers 32-bit data at the device designated by

S

to the device designated by

S +1
Before transfer S

b15
1 0

1

1

S
0

1

0

D

b15
1 0

1

1

b0 b15
0 0 1

1

Transfer

D +1
After transfer

D

0

1

0

b0 b15
0 0 1

1

1

0

0

1

b0
0

0

0

1

b0
0

D
1

Operation Error
(1) There are no operation errors associated with the MOV(P) or DMOV(P) instruction.

6-106

.

D

.

MOV(P),DMOV(P)

Program Example

1

(1) The following program stores input data from X0 to XB at D8.
[Ladder Mode]

[List Mode]
Step

Instruction

2

Device

3
(2) The following program stores the constant K155 at D8 when X8 goes ON.
[Ladder Mode]

4

[List Mode]
Instruction

Step

Device

4
009BH

6

b8b7
b15
b0
D8 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1

(3) The following program stores the data from D0 and D1 at D7 and D8.
[Ladder Mode]

7

[List Mode]
Step

Instruction

Device

8
(4) The following program stores the data from X0 to X1F at D0 and D1.
[List Mode]
Step

Instruction

6.4 Data Transfer Instructions
6.4.1 16-bit and 32-bit data transfers (MOV(P),DMOV(P))

[Ladder Mode]

Device

6-107

EMOV(P)

6.4.2

Floating-point data transfer (Single precision) (EMOV(P))

EMOV(P)

Ver.
Basic

High
performance

Process Redundant Universal

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

Command

EMOV

EMOV

S

D

EMOVP

S

D

Command

EMOVP

Setting
Data

S

: Data to be transferred or number of the device to which the data to be transferred is stored (real number)

D

: The number of the device to which the transferred data will be stored (real number)

Internal Devices
Bit

R, ZR

Word

J

\

Bit

Word

U

Zn

\G

S

––

––

*1

D

––

––

*1

Constants
E

––
––

*1:Available only in multiple Universal model QCPU

Function
Transfers 32-bit floating decimal point type real number data being stored at the device
designated by

S

to a device designated by
S +1

D
S

.

S

D +1

D

Transfer
4.23542

4.23542

32-bit floating-point
real number

32-bit floating-point
real number

Operation Error
(1) There are no operation errors associated with the EMOV(P) instruction.

6-108

Other

––

EMOV(P)

Program Example

1

(1) The following program stores the real numbers at D10 and D11 at D0 and D1.
[Ladder Mode]

[List Mode]
Step

Instruction

2

Device

3
[Operation]
D11
D10
36.475

D1

4

D0
36.475

(2) The following program stores the real number
[Ladder Mode]

4

1.23 at D10 and D11 when X8 is ON.

[List Mode]
Step

Instruction

6

Device

7

[Operation]
D11
1.23

D10

8

1.23

6.4 Data Transfer Instructions
6.4.2 Floating-point data transfer (Single precision) (EMOV(P))

6-109

EDMOV(P)

6.4.3

Floating-point data transfer (Double precision) (EDMOV(P))

EDMOV(P)

Basic

High
performance

Process Redundant Universal

Command

EDMOV

EDMOV

S

D

EDMOVP

S

D

Command

EDMOVP

Setting
Data

S

: Data to be transferred or number of the device to which the data to be transferred is stored (real number)

D

: The number of the device to which the transferred data will be stored (real number)

Internal Devices
Bit

Word

R, ZR

J

\

Bit

U

Word

S

––

––

D

––

––

\G

Zn

Constants
E

Other
––

––

––

Function
Transfers 64-bit floating decimal point type real number data being stored at the device
designated by
S +3

S +2

S

to a device designated by

S +1

S

4.23542
64-bit floating-point real number

Transfer

D +3

D
S

.

D +2

D +1

D

4.23542
64-bit floating-point real number

Operation Error
(1) There are no operation errors associated with the EDMOV(P) instruction.

6-110

EDMOV(P)

Program Example

1

(1) The following program stores the 64-bit floating decimal point type real number at D10 to
D13 at D0 to D3.
[Ladder Mode]

[List Mode]
Step

Instruction

2

Device

3
4

[Operation]
D13 D12 D11 D10
36.475

D3 D2

D1 D0

36.475

(2) The following program stores the real number
[Ladder Mode]

4
1.23 at D10 to D13 when X8 is ON.

6

[List Mode]
Step

Instruction

Device

7
[Operation]

8

D13 D12 D11 D10

6.4 Data Transfer Instructions
6.4.3 Floating-point data transfer (Double precision) (EDMOV(P))

6-111

$MOV(P)

6.4.4

Character string transfers ($MOV(P))

$MOV(P)

Basic

High
performance

Process Redundant Universal

Command

$MOV

$MOV

S

D

$MOVP

S

D

Command

$MOVP

: Character string to be transferred (maximum string length: 32 characters) or head number of the devices

S

where the character string to be transferred is stored
(character string)
D

Setting
Data

: Head number of the devices where the transferred character string will be stored (character string)

Internal Devices
Bit

Word

R, ZR

J

\

Bit

U

Word

S

––

––

D

––

––

\G

Zn

Constants
$

Other
––

––

––

Function
(1) Transfers the character string data designated by

S

to the devices from the device

designated by D and onward.
The character string data enclosed in " (double quotes) or devices from the number
specified by

S

to the device number storing "00H" are transferred all at once.

b0
b15
b8 b7
2nd character 1st character
S
S + 1 4th character 3rd character
S + 2 6th character 5th character
00H

b0
b15
b8 b7
2nd character 1st character
D
D + 1 4th character 3rd character
D + 2 6th character 5th character

nth character

nth character

00H

Indicates the end of character string.

(2) Processing will be performed without error even in cases where the range for the devices
storing the character data to be transferred (

S

to

S

+n) overlaps with the range of the

devices which will store the character string data after it has been transferred (

D

to

D

+n).

The following occurs when the character string data that had been stored from D10 to D13 is
transferred to D11 to D14:
b15
b8 b7
b0
D10 32 H (2)
31 H (1)
D11 34 H (4)
33 H (3)
D12 36 H (6)
35 H (5)
D13
00 H
D14

6-112

D10
D11
D12
D13
D14

b15
32 H
32 H
34 H
36 H

b8 b7
31 H
(2)
(2)
31 H
33 H
(4)
35 H
(6)
00 H

b0
(1) Character string before
(1) transfer is remained.
(3)
(5)

$MOV(P)

(3) If the "00H" code is being stored at lower bytes of
higher bytes and the lower bytes of
S
S +1
S +2

b15
b8 b7
b0
42 H (B) 41 H (A)
44 H (D) 43 H (C)
45 H (E) 00 H

D

D
D +1
D +2

Upper byte is not transferred.

S

+n, "00H" will be stored at both the

+n.

1

b15
b8 b7
b0
42 H (B) 41 H (A)
44 H (D) 43 H (C)
00 H
00 H

2

At the upper byte position,
"00H" is automatically stored.

3

Operation Error

4

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• There is no "00H" code stored between the device number designated by S and the
relevant device.
(Error code: 4101)
• The entire character string linked from the device number designated by D to the final
device number of the relevant device cannot be stored.
(Error code: 4101)
• The character string of

S

exceeds 16383 characters.

(Error code: 4101)

4
6
7

Program Example
(1) The character string data stored in D10 to D12 is transferred to D20 to D22 when X0 goes
ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device
6.4 Data Transfer Instructions
6.4.4 Character string transfers ($MOV(P))

[Operation]
b15
b8 b7
b0
D10 4DH (M) 2AH ( * )
D11 45H (E) 45H (E)
00H
D12

b15
b8 b7
b0
D20 4DH (M) 2AH ( * )
D21 45H (E) 45H (E)
D22
00H

(2) When X is turned ON, the character string "ABCD" is transferred to D20 and D21.
[Ladder Mode]

8

[List Mode]
Step

Instruction

Device

6-113

CML(P),DCML(P)

6.4.5

16-bit and 32-bit negation transfers (CML(P),DCML(P))

CML(P),DCML(P)

High
performance

Basic

Process Redundant Universal

indicates an instruction symbol of CML, DCML.
Command

CML, DCML

S

D

S

D

Command

CMLP, DCMLP

Setting
Data

P

S

: Data to be reversed or the number of the device where data to be reversed is stored (BIN 16/32 bits)

D

: Number of the device where the reversing result will be stored (BIN 16/32 bits)

Internal Devices
Bit

J

R, ZR

Word

\

Bit

U

Word

Constants
K, H

Zn

\G

––

S

––

D

Function
CML
(1) Inverts 16-bit data designated by
designated by

D

bit by bit, and transfers the result to the device

S

.

Before execution S

b15
1 0

D

b15
0 1

After execution

1

1

0

1

0

0

0

1

1

1

0

0

1

b0
0

0

1

1

0

b0
1

Inversion
0

0

0

1

1

1

1

0

0

DCML
(1) Inverts 32-bit data designated by
designated by

D

bit by bit, and transfers the result to the device

S

.
S +1

Before execution S

b15
1 0

1

S
0

1

1

0

D

b15
0 1

0

0

b0 b15
0 0 1

1

Inversion

D +1
After execution

1

0

1

b0 b15
1 1 0

0

1

0

0

1

b0
0

1

1

0

b0
1

D
0

Operation Error
(1) There are no operation errors associated with the CML(P) or DCML(P) instruction.

6-114

Other

––

CML(P),DCML(P)

Program Example

1

(1) The following program inverts the data from X0 to X7, and transfers result to D0.
[Ladder Mode]

[List Mode]
Step

Instruction

2

Device

3
[Operation]

4

If "Number of bits of S < Number of bits of D "
X7
X0
11010000

These bits are all regarded as 0.

4

b0
b15
b8 b7
D0 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1

6

(2) The following program inverts the data at M16 to M23, and transfers the result to Y40 to
Y47.
[Ladder Mode]

[List Mode]
Step

Instruction

7

Device

8
[Operation]
M23
M16
01011100

These bits are all regarded as 0.

Y40
Y4B Y48Y47
111110100011

(3) The following program inverts the data at D0 when X3 is ON, and stores the result at D16.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
D0

b15
b8 b7
b0
1101100110101111

b15
b8 b7
b0
D16 0 0 1 0 0 1 1 0 0 1 0 1 0 0 0 0

6-115

6.4 Data Transfer Instructions
6.4.5 16-bit and 32-bit negation transfers (CML(P),DCML(P))

If "Number of bits of S < Number of bits of D "

CML(P),DCML(P)

(4) The following program inverts the data at X0 to X1F, and transfers results to D0 and D1.
[Ladder Mode]

[List Mode]
Device

Instruction

Step

[Operation]
If "Number of bits of S < Number of bits of D "
X1B

These bits are all regarded as 0.

X8 X7

0100

b31

b28 b27

X0

011100101100

b24

b8 b7

D0, 1 1 1 1 1 1 0 1 1

b0

100011010011

(5) The following program inverts the data at M16 to M35, and transfers it to Y40 to Y63.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
If "Number of bits of S < Number of bits of D "

These bits are all regarded as 0.

M35
0 10 0

M24 M23
M16
0 1 1 10 0 10 1 10 0

Y63
Y56
1 1 1 1 10 1 1

Y48 Y47
Y40
10 0 0 1 10 10 0 1 1

(6) Inverts the data at D0 and D1 when X3 is ON, and stores the result at D16 and D17.
[Ladder Mode]

[List Mode]
Step

[Operation]

6-116

b31
b24
D0,D1 0 0 0 0 0 1 0 0

b8 b7
b0
0 11100101100

b31
b24
D16,D17 1 1 1 1 1 0 1 1

b8 b7
b0
1000 110 100 11

Instruction

Device

BMOV(P)

6.4.6

Block 16-bit data transfers (BMOV(P))

1
BMOV(P)

High
performance

Basic

Process Redundant Universal

3

Command

BMOV

BMOV

S

D

n

BMOVP

S

D

n

4

Command

BMOVP
S

: Head number of the devices where the data to be transferred is stored (BIN 16 bits)

D

: Head number of the devices of transfer destination (BIN 16 bits)

n : Number of transfers (when using an intelligent function module device (U

\G

4

): 1 to 6144 (QnA only))

(BIN 16 bits)
Setting
Data

Internal Devices
Bit

Word

2

J

R, ZR

\

Bit

Word

U

Constants
K, H

Zn

\G

Other

S

––

––

D

––

––

n

6

––

7
8

Function
points from the device designated by
b15
1234 H
5678 H
7FF0 H

S +(n-1)

6FFFH
553F H

to location n

.

B0

S
S +1
S +2

S +(n-2)

D

S

b15
Block
transfer
n

B0

D
D +1
D +2

1234 H
5678 H
7FF0 H

D +(n-1)
D +(n-2)

6FFF H
553F H

n

(2) Transfers can be accomplished even in cases where there is an overlap between the source
and destination device.
In the case of transmission to the smaller device number, transmission is from S ; for
transmission to the larger device number, transmission is from S + (n 1).
However, as shown in the example below, when transferring data from R to ZR, or from ZR
to R, the range to be transferred (source) and the range of destination must not overlap.
Transfer from R to R, or from ZR to ZR can be performed without any problem.
• ZR transfer range ((specified head No. of ZR) to (specified head No. of ZR + the number
of transfers -1))
• R transfer range ((specified head No. of R + file register block No.
head No. of R + file register block No.

32768) to (specified

32768 + the number of transfers -1))

6-117

6.4 Data Transfer Instructions
6.4.6 Block 16-bit data transfers (BMOV(P))

(1) Transfers in batch 16-bit data of n points from the device designated by

BMOV(P)
Example
Transfer ranges of ZR and R overlap when transferring 10000 blocks of data from ZR30000
(source) to R10 (block No.1 of the destination).
• ZR transfer range

(30000) to (30000+10000-1)

• R transfer range

(10+(1

32768)) to (10+(1

(30000) to (39999)
32768)+10000-1)

(32778) to (42777)
Therefore, the range 32778 to 39999 overlaps and the data is not correctly transferred.
Source of transfer

Destination of transfer

ZR0

R0
Overlapped

Block No. 0

ZR30000

R32767
R10

ZR39999

R10009

Block No. 1

(3) When S is a word device and D is a bit device, the object for the word device will be the
number of bits designated by the bit device digit designation.
If K1Y30 has been designated by
will become the object.
b15

S

D100

D

, the lower four bits of the word device designated by

b4 b3 b2 b1b0

D +2

D +1

D

1011
Y3B

S +1 D101

0011 n

S +2 D102

0111

(4) If bit device has been designated for
same number of digits.

S

and

Y38 Y37

Y34 Y33

Y30

011100111011
n

D

, then

S

and

D

should always have the

(5) When using a link direct device and an intelligent function module device for
either of

S

or

D

S

S

and

D

, only

can be used.

(6) Selection whether to check a device range
Whether to check a device range during execution of the BMOV instruction can be selected
with the device range check inhibit flag (SM237) (only when the conditions for subset
processing are established).
While SM237 is ON, whether S to S + (n) -1 and D to D + (n) - 1 are within the device
range or not are not checked.
For details of SM237, refer to Appendix 3 SPECIAL RELAY LIST.

SM237 can be used only for the Universal model QCPU whose first 5 digits of
serial number is 10012 or later.

6-118

BMOV(P)

Operation Error

1

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The device range of n points from

or

S

D

exceeds the corresponding device range.
(Error code: 4101)

2
3

Program Example
(1) The following program outputs the lower 4 bits of data at D66 to D69 to Y30 to Y3F in 4-point
units.
[Ladder Mode]

4

[List Mode]

4

Device

Instruction

Step

6
[Operation]
Before execution (source of transfer)
After execution (destination of transfer)
b15
b4b3 b0
D66
1110 1
1 1 0 1 Y33 to Y30
0 0 0 0 Y37 to Y34
D67
00000
0 0 1 1 Y3B to Y38
D68
10011
1 1 0 1 Y3F to Y3C
D69
0 110 1

7
8

Ignored

[Ladder Mode]

[List Mode]
Step

Device

Instruction

[Operation]
X2F

X2CX2B

X28X27

X24X23

X20

Before execution 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 0
After execution (destination of transfer)
b15

b4 b3

b0

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 D100
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 D101
4 points
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 D102
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 D103
Filled with 0s.

6-119

6.4 Data Transfer Instructions
6.4.6 Block 16-bit data transfers (BMOV(P))

(2) The following program outputs the data at X20 to X2F to D100 to D103 in 4-point units.

FMOV(P)

6.4.7

Identical 16-bit data block transfers (FMOV(P))

FMOV(P)

Basic

High
performance

FMOV

S

D

n

FMOVP

S

D

n

Process Redundant Universal

Command

FMOV
Command

FMOVP
S

: Data to be transferred or the head number of the devices where the data to be transferred is stored

D

: Head number of the devices of transfer destination (BIN 16 bits)

(BIN 16 bits)

n : Number of transfers (BIN 16 bits)
Setting
Data

Internal Devices
Bit

Word

J

R, ZR

\

Bit

U

Word

Constants
K, H

Zn

\G

Other
––

S

––

D

––

n

––

Function
(1) Transfers 16-bit data at the device designated by
one designated by

D

to n points of devices starting from the

S

.
b15

b15
S

(2) In cases where

S

b0

Transfer

3456 H

b0

D
D +1
D +2

3456 H
3456 H
3456 H

D +(n-2)
D +(n-1)

3456 H
3456 H

designates a word device and

D

n

a bit device, the number of bits

designated by digit designation for the bit device will be the object bits for the word device.
If K1Y30 has been designated by
will become the object.

D

, the lower 4 bits of the word device designated by
D +3

b15

S D100

b4 b3 b2 b1b0

Y3F

Y3C Y3B

D +1

Y38 Y37

Y34 Y33

D
Y30

1 01 1 1 01 11 01 1 1 01 1
n

1 011

(3) If bit device has been designated for
same number of digits.

6-120

Transfer

D +2

S

and

D

, then

S

and

D

should always have the

S

S

FMOV(P)
(4) Selection whether to check a device range
Whether to check a device range during execution of the FMOV instruction can be selected
with the device range check inhibit flag (SM237) (only when the conditions for subset
processing are established).
While SM237 is ON, whether D to D + (n) - 1 is within the device range or not is not
checked.
For details of SM237, refer to Appendix 3 SPECIAL RELAY LIST.

1
2

SM237 can be used only for the Universal model QCPU whose first 5 digits of
serial number is 10012 or later.

3
4

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The device range of n points from

or exceeds the corresponding device range.
(Error code: 4101)

D

4
6

Program Example
(1) The following program outputs the lower 4 bits of D0 when XA goes ON to Y10 to Y23 in
4-bit units.
[Ladder Mode]
[List Mode]
Step

Device

Instruction

7
8

[Operation]
b15

b4 b3 b2 b1 b0

Ignored

Transfer

1
1
1
1
1

0
0
0
0
0

1
1
1
1
1

1
1
1
1
1

Y13 to Y10
Y17 to Y14
Y1B to Y18 5 points
Y1F to Y1C
Y23 to Y20

(2) The following program outputs the data at X20 through X23 to D100 through D103 when XA
goes ON.
[Ladder Mode]
[List Mode]
Step

Device

Instruction

[Operation]
X2F

X2CX2B

X28X27

X24X23

X20

Before execution 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0
Ignored

After execution (destination of transfer)
b15

b4 b3

b0

0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 D100
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 D101
4 points
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 D102
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 D103
Filled with 0s.

6-121

6.4 Data Transfer Instructions
6.4.7 Identical 16-bit data block transfers (FMOV(P))

D0 1 1 0 1 1 0 1 1 1 0 0 1 1 0 1 1

DFMOV(P)

6.4.8

Identical 32-bit data block transfers (DFMOV(P))

DFMOV(P)

Ver.
Basic

High
performance

Process Redundant Universal

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.
QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

Command

DFMOV

DFMOV

S

D

n

DFMOVP

S

D

n

Command

DFMOVP
S

: Data to be transferred or head number of the devices where the data to be transferred are stored (BIN 32 bits)

D

: Head number of the devices of transfer destination (BIN 32 bits)

n : Number of transfers (BIN 16 bits)
Setting
Data

Internal Devices
Bit

J

R, ZR

Word

\

Bit

U

Word

Constants
K, H

Zn

\G

Other
––

S

––

D

––

n

––

Function
(1) This instruction transfers 32-bit data of the device specified by
starting from the device specified by

D

S

to the n-point devices

.
b31

b31
S ＋1,

S

b0 Transfer
1234567H

D ＋1,
D ＋3,
D ＋5,

D
D ＋2
D ＋4

D ＋n 1, D ＋n 2

b0
1234567H
1234567H
1234567H

n

1234567H

(2) If S specifies data of a device with digit specification, the amount of data to be transferred
will be the amount of the data specified digit.
If K5Y0 is specified by
will be the object.
Y1F

S

, the lower 20 bits (five digits) of the word device specified by

Y14 Y13

Y0
S ＋1,

Ignored

S

20 bits (five digits) data
b31

b20 b19

b0
D ＋3,

0
・
・
b20 b19 ・

Transfer b31

20 bits (five digits) data

D ＋2
・
・
・

b0
D ＋(2n

0
Filled with 0s

D

D ＋1,

0

6-122

S

1), D ＋(2n

2)

DFMOV(P)

(3) If

D

specifies data of a device with digit specification, the amount of data stored in the

device specified by

If K5Y0 is specified by
object.
If both

and

S

specified by

D

D

1

will be transferred.

D

D

, the lower 20 bits of the word device specified by

will be the

S

2

specify data of a device with digit specification, the amount of data

will be transferred regardless of the number of digits.

b31

b20 b19

b0
S ＋1,

3

S

Amount of data specified digits by D

4

Transfer
D ＋n

D ＋1

…

Y14n+19

Y14n

D

Y27

Y14 Y13

Y0

4
6

(4) If the value specified by n is 0, the instruction will be not processed.
(5) Whether to check a device range during the execution of the FMOV instruction can be
selected with the device range check inhibit flag (SM237). (Only when the conditions of the
subset processing are established)

Operation Error

7
8

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• The value specified by n is negative.

(Error code: 4100)

D

.

(Error code: 4101)

Program Example
(1) The following program stores the value data stored at Y0 to Y13(20 bits) into D10 to
D17,when M0 is turned on,
[Ladder Mode]

[List Mode]
Device

Instruction

Step

[Operation]
Y1F
1

1

1

1

1

1

1

1

1

1

1

Y14 Y13
1 1 1

0

1

0

1

0

Ignored

1

0

1

0

1

0

1

0

1

0

1

Y0
0 1

20 bits (five digits) data

b31
0

0

0

0

0

0

0

0

0

0

b20 b19
0 0 1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

b0
1

0

1

D11,D10

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

D13,D12

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

D15,D14

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

D17,D16

Transfer

20 bits (five digits)
Filled with 0s

6-123

6.4 Data Transfer Instructions
6.4.8 Identical 32-bit data block transfers (DFMOV(P))

• The range of n-point devices, to be transferred, exceeds the range of devices specified by

XCH(P),DXCH(P)

6.4.9

16-bit and 32-bit data exchanges (XCH(P),DXCH(P))

XCH(P),DXCH(P)

Basic

High
performance

Process Redundant Universal

indicates an instruction symbol of XCH, DXCH.
Command

XCH, DXCH

D1

D2

D1

D2

Command

XCHP, DXCHP

P

,

D1

Setting
Data

D2

: Head number of the devices where the data to be exchanged is stored (BIN 16/32 bits)

Internal Devices
Bit

Word

J

R, ZR

\

Bit

U

Word

Zn

\G

Other

D1

––

D2

––

Function
XCH
(1) Conducts 16-bit data exchange between

D1

and

D2

.
D2

D1

b15
b8 b7
b0
1111 00001111 0000

b15
b8 b7
b0
Before execution 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1

After execution

D1

D2

b15
b8 b7
b0
1111000011110000

b15
b8 b7
b0
0111000000000111

DXCH
(1) Conducts 32-bit data exchange between
D1 +1

D1

After execution

b31
0000

D1

b16 b15
000111

b31
Before execution 1 1 1 1

6-124

Constants

+1

b0
0000

D1

b16 b15
111111

b0
1111

D1

+1,

D1

and

D2

+1,

D2

D2+1

b31
0000

b16 b15
111111

D2 +1

b31
1111

b16 b15
000111

.
D2

b0
1111

D2

b0
0000

XCH(P),DXCH(P)

Operation Error

1

(1) There are no errors associated with the XCH (P) and DXCH (P) instruction.

2

Program Example
(1) The following program exchanges the present value of T0 with the contents of D0 when X8
goes ON.
[Ladder Mode]

3

[List Mode]
Instruction

Step

4

Device

4
(2) The following program exchanges the contents of D0 with the data from M16 to M31 when
X10 goes ON.
[Ladder Mode]

[List Mode]
Step

Instruction

6

Device

7
(3) The following program exchanges the contents of D0 and D1 with the data at M16 to M47
when X10 goes ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[List Mode]
Step

Instruction

Device

6-125

6.4 Data Transfer Instructions
6.4.9 16-bit and 32-bit data exchanges (XCH(P),DXCH(P))

(4) The following program exchanges the contents of D0 and D1 with those of D9 and D10
when M0 goes ON.
[Ladder Mode]

8

BXCH(P)

6.4.10

Block 16-bit data exchanges (BXCH(P))

BXCH(P)

Basic

High
performance

Process Redundant Universal

Command

BXCH

BXCH

D1

D2

n

BXCHP

D1

D2

n

Command

BXCHP

D1

n
Setting
Data

,

D2

: Head number of the devices where the data to be exchanged is stored (BIN 16 bits)
: Number of exchanges (BIN 16 bits)

Internal Devices
Bit

Word

J

R, ZR

\

Bit

Word

U

Zn

\G

Constants
K, H

Other

D1

––

––

––

D2

––

––

––

n

––

Function
(1) Exchanges 16-bit data of n points from device designated by
from device designated by
D1
D1 +1
D1 +2

D1 +(n
D1 +(n

D1
D1 +1
D1 +2

D1 +(n
D1 +(n

6-126

D2

D1

and 16-bit data of n points

.

b15
b8 b7
b0
0000 111100001111

D2

1111111100000000

D2

+1

110000 11110000 11

0000000011111111

D2

+2

1111111100000000

n

b15
b8 b7
b0
00 11001100 110011

2) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

D2

+(n

2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

D2

+(n

1) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

b15
b8 b7
b0
00 11001100110011

D2

110000 11110000 11

D2

+1

1111111100000000

1111111100000000

D2

+2

0000000011111111

n

n

b15
b8 b7
b0
0000 111100001111

2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

D2

+(n

2) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

1) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

D2

+(n

1) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

n

BXCH(P)

Operation Error

1

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The range of the device of n points from a device designated by
relevant device.
• The

D1

and

D2

D1

,

D2

devices overlap.

or exceeds the
(Error code: 4101)
(Error code: 4101)

Program Example

3
4

(1) The following program exchanges 16-bit data for 3 points from D200 for 16-bit data for 3
points from R0 when X1C goes ON.
[Ladder Mode]

2

[List Mode]
Step

Instruction

4

Device

6
7

[Operation]
b15
b8 b7
b0
R0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1

D201 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D202 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

R2 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0

b15
b8 b7
b0
D200 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1

b15
b8 b7
b0
R0 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1

D201 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

R1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

D202 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0

R2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

8

6.4 Data Transfer Instructions
6.4.10 Block 16-bit data exchanges (BXCH(P))

b15
b8 b7
b0
D200 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1

6-127

SWAP(P)

6.4.11

Upper and lower byte exchanges (SWAP(P))

SWAP(P)

Basic

High
performance

Process Redundant Universal

Command

SWAP

SWAP

D

SWAPP

D

Command

SWAPP

D

: Head number of the devices where the data is stored (BIN 16 bits)

Internal Devices

Setting
Data

Bit

R, ZR

Word

J

\

Bit

Word

U

\G

Zn

Constants

Other
––

D

Function
(1) Exchanges the higher and lower 8 bits of the device designated by
b15

D

b8 b7

b4 b3

.

b0

0 10 1010 11010 10 10

b15

D

b12 b11

D

b12 b11

b8 b7

b4 b3

b0

10 10 10 100 10 10 10 1

Operation Error
(1) There are no operation errors associated with the SWAP(P) instruction.

Program Example
(1) The following program exchanges the higher 8 bits and lower 8 bits of R10 when X10 goes
ON.
[Ladder Mode]

[List Mode]
Step

[Operation]
b15

b12 b11

b8 b7

b4 b3

b0

R10 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

b15

b12 b11

b8 b7

b4 b3

b0

R10 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

6-128

Instruction

Device

CJ,SCJ,JMP

6.5 Program Branch Instructions
6.5.1

1

Pointer branch instructions (CJ,SCJ,JMP)

2

CJ,SCJ,JMP

Basic

High
performance

Process Redundant Universal

3
4

Command

CJ

CJ

P**

SCJ

P**

JMP

P**

Command

SCJ
JMP
Label

4
6

Command

P**

7

P** : Pointer number of jump destination (Device name)
Setting
Data

Internal Devices
Bit

Word

R, ZR

J
Bit

P

\
Word

U

\G

Zn

Constants

Other
P

8

––

CJ
(1) Executes the program specified by the pointer number within the same program file, when
the execution command is ON.
(2) When the execution command is OFF, the program at the next step is executed.
ON
Execution command OFF

CJ

Executed at each scan

SCJ
(1) Executes the program specified by the pointer number within the same program file starting
with the scan immediately after OFF ON of the execution command.
(2) When the execution command is OFF or turned ON OFF, the program at the next step is
executed.
ON
Execution command OFF

SCJ

1 scan

Executed at each scan

6-129

6.5 Program Branch Instructions
6.5.1 Pointer branch instructions (CJ,SCJ,JMP)

Function

CJ,SCJ,JMP

JMP
(1) Unconditionally executes program of designated pointer number within the same program
file.

Note the following points when using the jump instruction.
1. After the timer coil has gone ON, accurate measurements cannot be made if
there is an attempt to jump the timer of a coil that has been turned ON using the
CJ, SCJ or JMP instructions.
2. Scan time is shortened if the CJ, SCJ or JMP instruction is used to force a jump
to the OUT instruction.
3. Scan time is shortened if the CJ, SCJ or JMP instruction is used to force a jump
to the rear.
4. The CJ, SCJ, and JMP instructions can be used to jump to a step prior to the
step currently being executed. However, it is necessary to consider methods to
get out of the loop so that the watchdog timer does not time out in the process.
P8

X0
Y40

When X3 is
ON, the loop
is closed.

X7
CJ

P9

CJ

P8

X3

P9

Exits the loop when
X7 is turned ON.

X6
Y42

5. The device to which a jump has been made with the CJ, SCJ or JMP does not
change.
XB
10

CJ

P19

XC
14

Y43
XB

16
P19
18

Y49
X9

Jumps to label P19
when XB turns ON.
Y43 and Y49 remain
unchanged regardless
of whether XB and XC are
turned ON/OFF during the
execution of CJ instruction.

Y4C

6. The label (P*) occupies step 1.
X8
10

CJ

P9

M33
14
Occupies 1 step
16
P9
18

Y30
M3
Y36
M36
Y39
X9

21

Y3B

7. The jump instructions can be used only for pointer numbers within the same
program file.
8. If a jump is made to a pointer number inside the skip range during a skip
operation, program execution will be taken up following the pointer number of
the jump destination.

6-130

CJ,SCJ,JMP

Operation Error

1

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The pointer number designated does not come prior to the END instruction.
(Error code: 4210)
• A pointer number which is not in use as a label in the same program has been
designated.
(Error code: 4210)
• A common pointer has been designated.

2
3

(Error code: 4210)

4

Program Example
(1) The following program jumps to P3 when X9 goes ON.
[Ladder Mode]
[List Mode]
Instruction

Step

4
Device

6
7
(2) The following program jumps to P3 from the next scan after XC goes ON.
[Ladder Mode]
[List Mode]
Instruction

Step

8

Device

(1) When using the Universal model QCPU with the SCJ instruction, inserting "AND SM400" (or
the NOP instruction) in immediately before the SCJ instruction is required.
[Program example1]
[Ladder Mode]
[List Mode]
Instruction

Step
0
1
2

[Program example2]
[Ladder Mode]

LD
AND
SCJ

Device
M0
SM400
P0

[List Mode]
Step
0
1
2
3

Instruction
LD
OUT
AND
SCJ

Device
M0
Y0
SM400
P0

6-131

6.5 Program Branch Instructions
6.5.1 Pointer branch instructions (CJ,SCJ,JMP)

Caution

GOEND

6.5.2

Jump to END (GOEND)

GOEND

Basic

High
performance

Process Redundant Universal

Command

GOEND

GOEND

Setting
Data

Internal Devices
Bit

Word

R, ZR

J
Bit

\

U

Word

––

\G

Zn

Constants

Other

––

Function
(1) Jumps to the FEND or END instruction in the same program file.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The GOEND instruction has been executed after the execution of the CALL, ECALL
instruction, and prior to the execution of the RET instruction.
(Error code: 4211)
• The GOEND instruction has been executed after the execution of the FOR instruction,
and prior to the execution of the NEXT instruction.
(Error code: 4200)
• The GOEND instruction has been executed during an interrupt program but prior to the
execution of the IRET instruction.
(Error code: 4221)
• The GOEND instruction was executed between the CHKCIR and CHKEND instruction
block.
(Error code: 4230)
• The GOEND instruction was executed between the IX and IXEND instruction block.
(Error code: 4231)

Program Example
(1) The following program jumps to the END instruction if D0 holds a negative number.
[Ladder Mode]

[List Mode]
Step

6-132

Instruction

Device

DI,EI,IMASK

6.6 Program Execution Control Instructions
1

6.6.1

Interrupt disable/enable instructions, interrupt program mask
(DI,EI,IMASK)

2

DI,EI,IMASK

Basic

High
performance

Process Redundant Universal

3
4

When the Basic model QCPU is used

4
DI

DI

6

Sequence program

IMASK

IMASK

EI

S

7

EI

: Interrupt mask data or head number of the devices where the interrupt mask data is stored (BIN 16 bits)

S

Setting
Data
S

Internal Devices
Bit

Word

J

R, ZR

Bit

––

\
Word

U

Zn

\G

Constants

Other

––

DI
(1) Disables the execution of an interrupt program until the EI instruction has been executed,
even if a start cause for the interrupt program occurs.
(2) A DI state is entered when power is turned ON or when the CPU module is reset.

EI
The EI instruction is used to clear the interrupt disable state resulting from the execution of
the DI instruction, and to create a state in which the interrupt program designated by the
interrupt pointer number certified by the IMASK instruction can be executed.
When the IMASK instruction is not executed, I32 to I47 are disabled.
Sequence program
DI
Sequence program
EI
FEND

Even if a cause of interrupt occurs during
the execution of the sequence program
between the DI and EI instructions, execution
of the interrupt program is suspended until
the processing of the sequence program
is completed.

Interrupt programs

6-133

6.6 Program Execution Control Instructions
6.6.1 Interrupt disable/enable instructions, interrupt program mask (DI,EI,IMASK)

Function

In

8

DI,EI,IMASK

IMASK
(1) Enables/disables the execution of the interrupt program marked by the designated interrupt
pointer by using the bit pattern of 8 points from the device designated by

S

.

• 1(ON)......Interrupt program execution enabled
• 0(OFF) .... Interrupt program execution disabled
(2) The interrupt pointer numbers corresponding to the individual bits are as shown below:
b15 b14 b13 b12 b11 b10 b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

I8

I7

I6

I5

I4

I3

I2

I1

I0

S

I15 I14

I13 I12 I11 I10

I9

S+1

I31 I30

I29 I28 I27 I26

I25 I24

I23 I22 I21 I20

I19 I18 I17 I16

S+2

I47 I46

I45 I44 I43 I42

I41 I40 I39 I38 I37 I36

I35 I34 I33 I32

S+3

I63 I62

I61 I60 I59

I57 I56 I55 I54 I53 I52

I51 I50 I49 I48

S+4

I79 I78

I77 I76 I75 I74

I73 I72 I71 I70 I69

I68

I67 I66 I65 I64

S+5

I95 I94

I93 I92 I91 I90

I89 I88 I87 I86 I85 I84

I83 I82 I81 I80

S+6

I111 I110 I109 I108 I107 I106 I105 I104 I103 I102 I101 I100 I99 I98 I97 I96

S+7

I127 I126 I125 I124 I123 I122 I121 I120 I119 I118 I117 I116 I115 I114 I113 I112

I58

(3) When the power is turned ON or when the CPU module has been reset, the execution of
interrupt programs I0 to I31,I48 to I127 is enabled, and the execution of interrupt programs
I32 to I47 is disabled.
(4) The statuses of devices S , S +1, S +2, and S +3 to S +7 are stored in SD715 to SD717
and SD781 to SD785 (storage area for the IMASK instruction mask pattern).
(5) Although the special registers are separated as SD715 to SD717 and SD781 to SD785,
device numbers should be designated as

S

to

S

+7 successively.

1. An interrupt pointer occupies 1 step.
I 10
Stored at step 50

X1C
Y10

50
X5
53

Y30

55

IRET

2. For the information on interrupt conditions, link direct devices, refer to the
QnUCPU User’s Manual(Function Explanation, Program Fundamentals) or
Qn(H)/QnPH/QnPRHCPU User’s Manuall(Function Explanation, Program
Fundamentals)
3. The DI state (interrupt disabled) is active during the execution of an interrupt
program. Do not insert the EI instructions in interrupt programs to attempt the
execution of multiple interrupts, with interrupt programs running inside interrupt
programs.
4. If there are the EI and DI instructions within a master control, these instructions
will be executed regardless of the execution/non-execution status of the MC
instruction.

6-134

DI,EI,IMASK

Operation Error

1

(1) There are no operation errors associated with the DI, EI or IMASK instruction.

2

Program Example
(1) The following program is designed to enable the execution of only the interrupt programs
having the interrupt pointer numbers I1 and I3 while X0 is ON.
[Ladder Mode]

3

[List Mode]
Step

Instruction

4

Device

4
6
7
8

6.6 Program Execution Control Instructions
6.6.1 Interrupt disable/enable instructions, interrupt program mask (DI,EI,IMASK)

6-135

DI,EI,IMASK

When the High Performance model QCPU/Process CPU/Redundant CPU/Universal model
QCPU is used

DI

DI
Sequence program

IMASK

IMASK

S

EI

EI

: Head number of the devices where the interrupt mask data is stored (BIN 16 bits)

S

Setting
Data
S

Internal Devices
Bit

Word

J

R, ZR

Bit

––

\
Word

U

Zn

\G

Constants

Other

––

Function
DI
(1) Disables the execution of an interrupt program until the EI instruction has been executed,
even if a start cause for the interrupt program occurs.
(2) A DI state is entered when power is turned ON or when the CPU module is reset.

EI
The EI instruction is used to clear the interrupt disable state resulting from the execution of
the DI instruction, and to create a state in which the interrupt program designated by the
interrupt pointer number enabled by the IMASK instruction and the fixed cycle execution
type program can be executed.
When the IMASK instruction is not executed, I32 to I47 are disabled.
Sequence program
DI
Sequence program
EI
FEDN
In

6-136

Interrupt programs

Even if a cause of interrupt occurs during
the execution of the sequence program
between the DI and EI instructions,
execution of the interrupt program is
suspended until the processing of the
sequence program is completed.

DI,EI,IMASK

IMASK
(1) Enables/disables the execution of the interrupt program marked by the designated interrupt
pointer by using the bit pattern of 16 points from the device designated by

S

1

.

• 1(ON)...... Interrupt program execution enabled

2

• 0(OFF).... Interrupt program execution disabled
(2) The interrupt pointer numbers corresponding to the individual bits are as shown below:
b15 b14 b13 b12 b11 b10 b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

I8

I7

I6

I5

I4

I3

I2

I1

I0

S

I15 I14

I13 I12 I11 I10

I9

S +1

I31 I30

I29 I28 I27 I26

I25 I24

I23 I22 I21 I20

I19 I18 I17 I16

S +2

I47 I46

I45 I44 I43 I42

I41 I40 I39 I38 I37 I36

I35 I34 I33 I32

S +3

I63 I62

I61 I60 I59

I57 I56 I55 I54 I53 I52

I51 I50 I49 I48

S +4

I79 I78

I77 I76 I75 I74

I73 I72 I71 I70 I69

I68

I67 I66 I65 I64

S +5

I95 I94

I93 I92 I91 I90

I89 I88 I87 I86 I85 I84

I83 I82 I81 I80

S +6

I111 I110 I109 I108 I107 I106 I105 I104 I103 I102 I101 I100 I99 I98 I97 I96

S +7

I127 I126 I125 I124 I123 I122 I121 I120 I119 I118 I117 I116 I115 I114 I113 I112

S +8

I143 I142 I141 I140 I139 I138 I137 I136 I135 I134 I133 I132 I131 I130 I129 I128

S +9

I159 I158 I157 I156 I155 I154 I153 I152 I151 I150 I149 I148 I147 I146 I145 I144

S +10

I175 I174 I173 I172 I171 I170 I169 I168 I167 I166 I165 I164 I163 I162 I161 I160

S +11

I191 I190 I189 I188 I187 I186 I185 I184 I183 I182 I181 I180 I179 I178 I177 I176

S +12

I207 I206 I205 I204 I203 I202 I201 I200 I199 I198 I197 I196 I195 I194 I193 I192

S +13

I223 I222 I221 I220 I219 I218 I217 I216 I215 I214 I213 I212 I211 I210 I209 I208

S +14

I239 I238 I237 I236 I235 I234 I233 I232 I231 I230 I229 I228 I227 I226 I225 I224

S +15

I255 I254 I253 I252 I251 I250 I249 I248 I247 I246 I245 I244 I243 I242 I241 I240

I58

3
4
4
6
7
8

(4) The status of devices S , S +1, S +2, and S +3 to S +15 are stored in SD715 to SD717
and SD781 to SD793 (storage area for the IMASK instruction mask pattern).
(5) Although the special registers are separated as SD715 to SD717 and SD781 to SD793,
device numbers should be designated as

S

to

S

+15 successively.

1. An interrupt pointer occupies 1 step.
T10
Stored at step 50

X1C
Y10

50
X5
53

Y30

55

IRET

• For the information on interrupt conditions, link direct devices, refer to the
QnUCPU User’s Manual(Function Explanation, Program Fundamentals) or
Qn(H)/QnPH/QnPRHCPU User’s Manuall(Function Explanation, Program
Fundamentals)
2. The DI state (interrupt disabled) is active during the execution of an interrupt
program. Do not insert the EI instructions in interrupt programs to attempt the
execution of multiple interrupts, with interrupt programs running inside interrupt
programs.
3. If there are the EI and DI instructions within a master control, these instructions
will be executed regardless of the execution/non-execution status of the MC
instruction.

6-137

6.6 Program Execution Control Instructions
6.6.1 Interrupt disable/enable instructions, interrupt program mask (DI,EI,IMASK)

(3) When the power is turned ON or when the CPU module has been reset, the execution of
interrupt programs I0 to I31,I48 to I255 is enabled, and the execution of interrupt programs
I32 to I47 is disabled.

DI,EI,IMASK

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by S exceeds the range of the corresponding device.
(For the Universal model QCPU only.)
(Error code: 4101)

Program Example
(1) The following program creates an execution enabled state for the interrupt program marked
by the interrupt pointer number when X0 is ON.
[Ladder Mode]

[List Mode]
Step

6-138

Instruction

Device

IRET

6.6.2

Recovery from interrupt programs (IRET)

1
IRET

Basic

High
performance

Process Redundant Universal

2
3

I

**

IRET

4

IRET

Setting
Data
––

Internal Devices
Bit

Word

R, ZR

J
Bit

\

U

Word

\G

Zn

Constants

Other

4

––

6

Function
7

(1) Indicates the completion of interrupt program processing.
(2) Returns to sequence program processing following the execution of the IRET instruction.

8

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
(Error code: 4220)

• The IRET instruction was executed before the interrupt program is executed.
(Error code: 4223)
• The END, FEND, GOEND, or STOP instruction has been executed after the generation of
an interrupt and prior to the execution of the IRET instruction.
(Error code: 4221)
• The IRET instruction was executed during the fixed scan execution type program.
(For the Universal model QCPU only)
(Error code: 4223)

6-139

6.6 Program Execution Control Instructions
6.6.2 Recovery from interrupt programs (IRET)

• There is no pointer corresponding to the interrupt number.

IRET

Program Example
(1) The following program adds 1 to D0 if M0 is ON when the number 3 interrupt is generated.
[Ladder Mode]

[List Mode]
Step

6-140

Instruction

Device

RFS(P)

6.7 I/O Refresh Instructions
1

6.7.1

I/O refresh (RFS(P))

2
RFS(P)

Basic

High
performance

Process Redundant Universal

3
4

Command

RFS

RFS

S

n

RFSP

S

n

4

Command

RFSP

6

: Head number of the devices to be refreshed (bits)

S

n : Number of refreshes (BIN 16 bits)
Setting
Data
S

Internal Devices
Bit

Word

J

R, ZR

\

Bit

U

Word

\G

––

(Only X, Y)

n

Zn

Constants
K, H

Other
––
––

7
8

Function
(2) Fetching of input from or sending output to an external source is conducted in batch only
after the execution of the END instruction, so it is not possible to output a pulse signal to an
outside source during the execution of a scan.
When the I/O refresh instruction is executed, the inputs (X) or outputs (Y) of the
corresponding device numbers are refreshed forcibly midway through program execution.
Therefore, a pulse signal can be output to an external source during a scan.
(3) Use direct access inputs (DX) or direct access outputs (DY) to refresh inputs (X) or outputs
(Y) in 1-point units.
[Program based on the RFS instruction]
Command
X0

RFS

K1

Refreshes X0

X0
Y20
Command
RFS

Y20

K1

Refreshes Y20

[Program based on direct access input and direct access output]
DX0
DY20
Direct access input

Direct access output

6-141

6.7 I/O Refresh Instructions
6.7.1 I/O refresh (RFS(P))

(1) 1. Refreshes only the device being scanned during a scan, and functions to fetch input from
external sources or to output data to an output module.

RFS(P)

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The range n points from the device designated by

S

exceeds the proximate I/O range.
(Error code: 4101)

Program Example
(1) The following program refreshes X100 to X11F and Y200 to Y23F when M0 goes ON.
[Ladder Mode]

[List Mode]
Step

6-142

Instruction

Device

UDCNT1

6.8 Other Convenient Instructions
6.8.1

1
Counter 1-phase input up or down (UDCNT1)

2

UDCNT1

Basic

High
performance

Process Redundant Universal

3
4

Command

UDCNT1

UDCNT1

:

S

S

+ 0: Input number for count input (bits)

S

+ 1: For setting count up/down (bits)

S

D

n

4

•OFF: Count up (add numbers when counting)
•ON: Count down (subtract numbers when counting)

6

: Number of the counter to be enabled to start counting with the UDCNT1 instruction (Device name)

D

n : Value to set (BIN 16 bits)
Setting
Data

Internal Devices
Bit

Word

J

R, ZR

Bit

\
Word

U

\G

Zn

Constants
K, H

Other

S

(Only X)*1

––

––

––

––

D

––

*1(Only C)

––

––

––

n

*2

*2

7
8

––

*2

*1: Only the X device can be used for

. However, the X device can be used only in the range of number of I/O points
(the number of accessible points to actual I/O modules).
*2: Local devices and the file registers set for individual programs cannot be used.
S

(1) When the input designated at S goes from OFF to ON, the present value of the counter
designated at D will be updated.
(2) The direction of the count is determined by the ON/OFF status of the input designated by
S +1.
• OFF : Count up (counts by adding to the present value)
• ON : Count down (counts by subtracting from the present value)
(3) Count processing is conducted as described below:
• When the count is going up, the counter contact designated at D goes ON when the
present value becomes identical with the setting value designated by n. However, the
present value count will continue even when the contact of the counter designated at
goes ON. (See Program Example (1))

D

• When the count is going down, the counter for the contact designated at D goes OFF
when the present value reaches the set value 1. (See Program Example (1))

6-143

6.8 Other Convenient Instructions
6.8.1 Counter 1-phase input up or down (UDCNT1)

Function

UDCNT1

• The counter designated at D is a ring counter. If it is counting up when the present value
is 32767, the present value will become 32768. Further, if it is counting down when the
present value is 32768, the present value will become 32767. The count processing
performed on the present value is as shown below:
32768

32767

2

1

0

1

2

32766

32767

When counting up
When counting down

(4) The UDCNT1 instruction triggers counting when the execution command is turned
OFF ON and suspends counting when the execution command is turned ON OFF.
When the execution command is turned OFF ON again, the counting resumes from the
suspended value.
(5) The RST instruction clears the present value of the counter designated at
contact OFF.

D

and turns the

1. With the UDCNT1 instruction, the argument device data is registered in the
work area of the CPU module and counting operation is processed as a system
interrupt. (The device data registered in the work area is cleared by turning the
execution command OFF, or turning the STOP/RUN switch STOP RUN.) For
this reason, the pulses that can be counted must have longer ON and OFF
times than the interrupt interval of the CPU module. The interrupt interval of
individual modules is shown below:
CPU Module Type Name
High Performance model QCPU, Process CPU,
Universal model QCPU

Interrupt Interval
1 ms

2. The set value cannot be changed during counting directed by the UDCNT1
instruction (while the execution command is ON). To change the set value, turn
OFF the execution command.
3. Counters which have been designated by the UDCNT1 instruction cannot be
used by other instructions. If they are used by other instructions, they will not be
capable of returning an accurate count.
4. The UDCNT1 instruction can be used as many as 6 times within all the
programs being executed. The seventh and the subsequent UDCNT1
instructions are not processed.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by

6-144

S

exceeds the range of the corresponding device.
(Error code: 4101)

UDCNT1

Program Example

1

(1) This program uses C0 (Up/Down counter) to count the number of times X0 goes from OFF
to ON after X20 has gone ON.
[Ladder Mode]

2

[List Mode]
Instruction

Step

Device

3
4

[Operation]
X20

4

X0
X1

Up

Down

Up

6

C0 present value 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0- 1- 2- 3- 2- 1 0 1 1
C0 contact

7
8

6.8 Other Convenient Instructions
6.8.1 Counter 1-phase input up or down (UDCNT1)

6-145

UDCNT2

6.8.2

Counter 2-phase input up or down (UDCNT2)

UDCNT2

Basic

High
performance

Process Redundant Universal

Command

UDCNT2

UDCNT2

:

S

S
S

S

D

n

+ 0: Input number for count input (A phase pulse) (bits)
+ 1: Input number for count input (B phase pulse) (bits)

: Number of the counter to be enabled to start counting with the UDCNT2 instruction (Device name)

D

n : Value to set (BIN 16 bits)
Setting
Data

Internal Devices
Bit

Word

J

R, ZR

Bit

\
Word

U

\G

Zn

Constants
K, H

Other

S

(Only X)*1

––

––

––

––

D

––

*1(Only C)

––

––

––

n

*2

*2

––

*2

*1: Only the X device can be used for

. However, the X device can be used only in the range of number of I/O points
(the number of accessible points to actual I/O modules).
*2: Local devices and the file registers set for individual programs cannot be used.
S

Function
(1) The present value of the counter designated by D is updated depending on the status of the
input designated by S (A phase pulse) and the status of the input designated by S +1 (B
phase pulse).
(2) Direction of the count is determined in the following manner:
• When S is ON, if S +1 goes from OFF to ON, count up operation is performed (values
are added to the present value of the counter).
• When S is ON, if S +1 goes from ON to OFF, count down operation is performed (values
are subtracted from the present value of the counter).
• No count operation is performed if

S

is OFF.

(3) Count processing is conducted as described below:
• When the count is going up, the counter contact designated at D goes ON when the
present value becomes identical with the setting value designated by n. However, the
present value count will continue even when the contact of the counter designated at
goes ON. (See Program Example (1))
• When the count is going down, the counter for the contact designated at D goes OFF
when the present value reaches the set value 1. (See Program Example (1))

6-146

D

UDCNT2

• The counter designated at D is a ring counter. If it is counting up when the present value
is 32767, the present value will become 32768. Further, if it is counting down when the
present value is 32768, the present value will become 32767. The count processing
performed on the present value is as shown below:
32768

32767

2

1

0

1

2

32766

32767

1
2

When counting up
When counting down

(4) Count processing conducted according to the UDCNT2 instruction begins when the count
command goes from OFF to ON, and is suspended when it goes from ON to OFF.
When the execution command is turned OFF to ON again, the counting resumes from the
suspended value.
(5) The RST instruction clears the present value of the counter designated at
contact OFF.

D

4

execution command OFF, or turning the STOP/RUN switch STOP RUN.) For
this reason, the pulses that can be counted must have longer ON and OFF
times than the interrupt interval of the CPU module. The interrupt interval of
individual modules is shown below:
CPU Module Type Name
Universal model QCPU

7

1 ms

(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
exceeds the range of the corresponding device.
(Error code: 4101)

6-147

6.8 Other Convenient Instructions
6.8.2 Counter 2-phase input up or down (UDCNT2)

Operation Error

S

6

8

Interrupt Interval

2. The set value cannot be changed during counting directed by the UDCNT2
instruction (while the execution command is ON). To change the set value, turn
OFF the execution command.
3. Counters designated by the UDCNT2 instruction cannot be used by any other
instruction. If they are used by other instructions, they will not be capable of
returning an accurate count.
4. The UDCNT2 instruction can be used as many as 5 times within all the
programs being executed. The sixth and the subsequent UDCNT2 instructions
are not processed.

• The device specified by

4

and turns the

1. With the UDCNT2 instruction, the argument device data is registered in the
work area of the CPU module and counting operation is processed as a system
interrupt. (The device data registered in the work area is cleared by turning the

High Performance model QCPU, Process CPU,

3

UDCNT2

Program Example
(1) The following program performs a count operation as instructed by C0 (count up or down) on
the status of X0 and X1 after X20 has gone ON.
[Ladder Mode]
[List Mode]
Device

Instruction

Step

[Operation]
X20
X0
X1
COM present value 0 1
C0 contact

6-148

2

3

4

5

4

3

2

1

0

1

2

1

1

TTMR

6.8.3

Teaching timer (TTMR)

1
TTMR

Basic

High
performance

Process Redundant Universal

2
3

Command

TTMR

TTMR

D

n

4
D

:

D

+ 0: The device where measurement value is stored (BIN 16 bit)

D

+ 1: For CPU module system use (BIN 16 bit)

4

n : Measurement value multiplier (BIN 16 bits)
Internal Devices

Setting
Data

Bit

D

––

n

––

Word

J

R, ZR

\

Bit

Word

U

\G

Zn

Constants
K, H

––

Other

6

––
––

Function

7
8

(1) Measures the time while the execution command is ON in units of seconds, and stores the
multiplied value of the measured time by the multiplier specified by n at the device
designated by D .
D

+0 or

D

+1 when the execution command is turned

(3) The multipliers that can be designated by n are as shown below:
n

Multiplier

0

1

1

10

2

100

1. Time measurements are conducted when the TTMR instruction is executed.
Using the JMP or similar instruction to jump the TTMR instruction will make it
impossible to get an accurate measurement.
2. Do not change the multiplier designated by n while the TTMR instruction is
being executed. Changing this multiplier will result in an inaccurate value being
returned.
3. The TTMR instruction can also be used in low speed execution type programs.
4. The device designated by D +1 is used by the system of the CPU module, so
users should not change its value. If users do change this value, the value
stored in the device designated by D will no longer be accurate.
(4) No processing is performed when the value specified by "n" is other than 0 to 2.

6-149

6.8 Other Convenient Instructions
6.8.3 Teaching timer (TTMR)

(2) Clears the device designated by
OFF ON.

TTMR

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU only.)
(Error code: 4101)

Program Example
(1) The following program stores the amount of time that X0 is ON at D0.
[Ladder Mode]

[List Mode]
Step

6-150

Instruction

Device

STMR

6.8.4

Special function timer (STMR)

1
STMR

High
performance

Basic

Process Redundant Universal

2
3

Command

STMR

STMR

n

S

D

4
S

: Timer number (word)

4

n : Value to set (BIN 16 bits).
D

Setting
Data
S

:

D

+ 0: Off delay timer output (bits)

D

+ 1: One shot timer output after OFF (bits)

D

+ 2: One shot timer output after ON (bits)

D

+ 3: ON delay and Off delay timer output (bits)

Internal Devices
Bit

Word

––

*1

R, ZR
––

J
Bit

\
Word

6
U

\G

Constants
K, H

Zn

––

––
––

––

7

––

n
D

Other

––

––

8

*1:Can be used only by timer (T) data

(1) The STMR instruction uses the 4 points from the device designated by
types of timer output.

D

to perform four

• OFF delay timer output ( D +0)
Goes ON at the leading edge of the command for the STMR instruction, and after the
trailing edge of the command, goes OFF when the amount of time designated by n has
passed.
• One shot timer output after OFF ( D +1)
Goes ON at the trailing edge of the command for the STMR instruction, and goes OFF
when the amount of time designated by n has passed.
• One shot timer output after ON ( D +2)
Goes ON at the leading edge of the command for the STMR instruction, and goes OFF
either when the amount of time designated by n has passed, or when the command for
the STMR instruction goes OFF.
• ON delay timer output ( D +3)
Goes ON at the trailing edge of the timer coil, and after the trailing edge of the command
for the STMR instruction, goes OFF when the amount of time designated by n has
passed.
(2) The timer coil designated by S turns ON at the leading edge and trailing edge of the
command for the STMR instruction, and starts measurement of the present value.
• The timer coil measures to the point where the value reaches the set value designated by
n, then enters a time up state and goes OFF.
• If the command for the STMR instruction goes OFF before the timer coil reaches the time
up state, it will remain ON. Timer measurement is continued at this time. When the STRM
instruction command goes ON once again, the present value will be cleared to 0 and
measurement will begin once again.

6-151

6.8 Other Convenient Instructions
6.8.4 Special function timer (STMR)

Function

STMR

(3) The timer contact goes ON at the leading edge of the command for the STMR instruction,
and after the trailing edge is reached, the timer coil goes OFF at the trailing edge of the
STMR instruction command.
The timer contact is used by the CPU module system, and cannot be used by the user.
Command for
STMR instruction
S (Coil)
S (Contact)

D +0

OFF delay timer

D +1

One-shot timer after OFF

D +2

One-shot timer after ON

D +3

ON delay timer + OFF delay timer

Setting value
designated by n

Set value
designated by n

Set value
Set value
designated by n designated by n

(4) Measurement of the present value of the timer specified by the STMR instruction is
executed regardless of the command ON/OFF status of the STMR instruction.
If the STMR instruction is jumped with the JMP or similar instruction, it will not be possible to
get accurate measurement.
(5) Measurement unit for the timer designated by

D

is identical to the low speed timer.

(6) A value between 0 to 32767 can be set for n.
No operation if n is other than 0 to 32767.
(7) The timer designated by S cannot be used by the OUT instruction.
If the STMR instruction and the OUT instruction use the same timer number, accurate
operation will not be conducted.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU only.)
(Error code: 4101)

6-152

STMR

Program Example

1

(1) The following program turns Y0 and Y1 ON and OFF once each second (flicker) when X20
is ON.
(Uses 100 ms timer)
[Ladder Mode]

2

[List Mode]
Step

Instruction

3

Device

4
4
[Timing Chart]

6

X20
M1, Y0

7

M2, Y1
M3
1 sec

8

1 sec

6.8 Other Convenient Instructions
6.8.4 Special function timer (STMR)

6-153

ROTC

6.8.5

Rotary table shortest direction control (ROTC)

ROTC

Basic

High
performance

Process Redundant Universal

Command

ROTC

ROTC

S

:

S

n1

n2

S

+0

: Measures the number of table rotations (for system use) (BIN 16 bits)

S

+1

: Call station number (BIN 16 bits)

S

+2

: Call item number (BIN 16 bits)

D

n1 : Number of divisions of table (2 to 32767) (BIN 16 bits)
n2 : Number of low-speed sections (value from 0 to less than n1) (BIN 16 bits)
D

Setting
Data
S

:

D

+0

: A phase input signal (bits)

D

+1

: B phase input signal (bits)

D

+2

: 0 point detection input signal (bits)

D

+3

: High speed forward rotation output signal (for system use) (bits)

D

+4

: Low speed forward rotation output signal (for system use) (bits)

D

+5

: Stop output signal (for system use) (bits)

D

+6

: Low speed reverse rotation output signal (for system use) (bits)

D

+7

: High speed reverse rotation output signal (for system use) (bits)

Internal Devices
Bit

R, ZR

Word

––

J
Bit

\
Word

U

\G

Zn

Constants
K, H

––

n1

––
––

n2
D

Other

––
––

––

––

Function
(1) This control functions to enable shortest direction control of the rotary table to the position of
the station number designated by S +1 in order to remove or deposit an item whose number
has been designated by
by n1.

S

+2 on a rotary table with equal divisions of the value designated

(2) The item number and station number are controlled as items allocated by counterclockwise
rotation.
(3) The system uses S +0 as a counter to instruct it as to what item is at which number counting
from station number 0. Do not rewrite the sequence program data.
Accurate controls will not be possible in cases where users have rewritten the data.
(4) The value of n2 should be less than the number of table divisions specified by n1.
(5)

D +0 and D +1 are A and B phase input signals that are used to detect whether the direction
of the rotary table rotation is forward or reverse.

The direction of rotation is judged by whether the B phase pulse is at its leading or trailing
edge when the A phase pulse is ON:
• When the B phase is at the leading edge: Forward rotation (clockwise rotation)
• When the B phase is at the trailing edge: Reverse rotation (counterclockwise rotation)

6-154

ROTC

(6)

D +2 is the 0 point detection output signal that goes ON when item number 0 has arrived at
the No. 0 station.
When the device designated by D +2 goes ON while the ROTC instruction is being

executed, S +0 is cleared.
It is best to perform this clear operation first, then to begin shortest direction control with the
ROTC instruction.
(7) The data from D +3 to D +7 consists of output signals needed to control the table's
operation.
The output signal of one of the devices from D +3 to D +7 will go ON in response to the
execution results of the ROTC instruction.
(8) If the command for the ROTC instruction is OFF, clears all
shortest direction control.

D

+3 to

D

+7 without performing

(9) The ROTC instruction can be used only one time in all programs where it is executed.
Attempts to use it more than one time will result in inaccurate operations.
(10) No processing is performed when the value of
than n1.

S

+0 to

S

+2, or the value of n2 is greater

Operation Error

1
2
3
4
4
6
7

(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by S or D exceeds the range of the corresponding device.
(For the Universal model QCPU only.)
(Error code: 4101)

8

6.8 Other Convenient Instructions
6.8.5 Rotary table shortest direction control (ROTC)

6-155

ROTC

Program Example
(1) The following program deposits the item at section D2 on a 10-division rotary table at the
station at section D1, and the two sections ahead and behind this determine the rotation
direction and control speed of the motor when the table is being rotated at low speed.
[Ladder Mode]

[List Mode]
Device

Instruction

Step

Station No. 0
0 point detection
X002
8

9
0

7

Part
X000

6
1

Detection
switch
2

Forward
rotation
3

Station No. 1

6-156

5

X001
4

Rotary table

RAMP

6.8.6

Ramp signal (RAMP)

1
RAMP

Basic

High
performance

Process Redundant Universal

2
3

Command

RAMP

n1

RAMP

n2

D1

n3

D2

4
n1 : Initial value (BIN 16 bits)
n2 : Final value (BIN 16 bits)
D1

:

4

D1

+0

: Present value (BIN 16 bits)

D1

+1

: Number of executions (BIN 16 bits)

n3 : Number of shifts (BIN 16 bits)
D2

:

+0

: Completion device (bits)

D2

+1

: Bit for selecting data retaining at completion (bit)

Internal Devices

Setting
Data

Bit

6

D2

J

R, ZR

Word

Bit

\

U

Word

\G

Zn

Constants
K, H

Other

n1

––

n2

––
––

D1

n3

––

7
8

––
––

D2

––

––

(1) When the execution command is ON, the following processing is executed.
• Shifts from the value specified by n1 to the value specified by n2 in the number of times
specified by n3.
• For n3, designate the number of scans (number of shifts) required for shift from n1 to n2.
No operation if other than 01 or D1=1 and D2 0

Executes COS-1 operation and outputs
the result of operation to Y40 to Y4F ( 4 )

[List Mode]
Step

Instruction

Device

[Operations involved if X0 and X20 to X33 designate a value of
D0
0 0 0 1

1

X0 ON

BCD value
X33 X30
0

2

BCD value
X2F X20
7 6 5 0
BCD value

7-318

3

Transfer

D1
0 0 0 0

MOV

BCD value

Transfer

D2
7 6 5 0

MOV

BCD value

4

BACOS operation Y4F Y40
0 1 4 0
BACOS
BCD value

0.7650]

BATAN(P)

7.12.34

BCD type TAN -1 operations (BATAN(P))

1
BATAN(P)

Basic

High
performance

Process Redundant Universal

2
3

Command

BATAN

BATAN

S

D

BATANP

S

D

4

Command

BATANP

Setting
Data
S

S

: Number of the device where data of which the TAN-1 (inverse tangent) value is obtained is stored
(BCD 4 digits)

D

: Head number of the devices where the operation result will be stored (BCD 4 digits)

Internal Devices
Bit

J

R, ZR

Word

Bit

\
Word

––

U

Zn

\G

6

Constants

––

6

Other
––

7

––

D

8

Function
(1) Performs TAN-1 (inverse tangent) on value designated by
D

.
S +1

S
TAN

1

(

Sign

and stores operation results

S +2

Integer part . Decimal fraction part )

(2) A sign for the operation data is set at

S

D

.

If the operation data is a positive value, this is set at "0", and if it is a negative value, it is set
at "1".
(3) The part before the decimal point and fraction part are stored at
as BCD values.

S

+1 and

S

+2 respectively,

(Values from 0 to 9999.9999 can be set.)
(4) Operation results stored at
degrees (degree units).

D

are BCD values between 0 and 90 degrees, and 270 and 360

(5) Calculation results are a value from which the decimal fraction part has been rounded.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The operation data designated by

S

is not a BCD value.

(Error code: 4100)

• The device specified by S exceeds the range of the corresponding device.
(For the Universal model QCPU only.)
(Error code: 4101)

7-319

7.12 Special function instructions
7.12.34 BCD type TAN -1 operations (BATAN(P))

(angles) at device designated by

S

BATAN(P)

Program Example
(1) The following program performs a TAN-1 operation on the sign (positive when X0 is OFF,
and negative when X0 is ON), the BCD 4-digit integer part from X20 to X2F and the BCD
4-digit decimal fraction part from X30 to X3F, and outputs the calculated angle in 4 BCD
digits from Y40 to Y4F.
[Ladder Mode]
Sets the sign of a TAN value (

1

)

Sets the integer part of a TAN value (

2

)

Sets the decimal fraction part of a TAN value (
Executes TAN-1 operation and outputs
the result of operation to Y40 to Y4F ( 4 )

[List Mode]
Step

Instruction

Device

[Operations involved when X0 and X20 to X2F designate a value of 1.2654]
D0
0 0 0 0

1

X0 OFF

BCD value
X2F X20
0 0 0 1

2

MOV

BCD value
X3F X30
2 6 5 4
BCD value

7-320

Transfer

3

Transfer
MOV

D1
0 0 0 1
BCD value
D2
2 6 5 4
BCD value

4

BATAN operation Y4F Y40
0 0 5 2
BATAN

BCD value

3

)

LIMIT(P),DLIMIT(P)

7.13 Data Control Instructions
1

7.13.1

Upper and lower limit controls for BIN 16-bit and BIN 32-bit
data (LIMIT(P),DLIMIT(P))

2

LIMIT(P),DLIMIT(P)

Basic

High
performance

Process Redundant Universal

3
4

indicates an instruction symbol of LIMIT/DLIMIT.
Command

LIMIT, DLIMIT

S1

S2

S3

D

S1

S2

S3

D

Command
P

LIMITP, DLIMITP

6
7

S1

: Lower limit value (minimum output threshold value) (BIN 16/32 bits)

S2

: Upper limit value (maximum output threshold value) (BIN 16/32 bits)

S3

: Input value to be controlled by the upper and lower limit control (BIN 16/32 bits)

D

: Head number of the devices where the output value controlled by the upper and lower limit control will be
stored (BIN 16/32 bits)

Internal Devices

Settng
Data

Bit

Word

R, ZR

J
Bit

\
Word

U

Constants
K, H

Zn

\G

S2

––

S3

––
––

––

Function
LIMIT
(1) Controls the output value to be stored at the device designated by D by checking whether
the input value (BIN 16 bits) designated by S3 is within the range of upper and lower limit
values specified by S1 and S2 or not.
Output value is controlled in the way shown below:
• When

S1

Lower limit value

S3

Input value .................... S1 Lower limit value

D

Output value

• When

S2

Upper limit value

S3

Input value .................... S2

D

Output value

• When

S1

Lower limit value

S3

Input value

Upper limit value

Upper ......... S3 Input value

Output value

D

Output value ( D )

Value designated
by S1

(2) Values in the range from

Value designated by S2
Input value( S3 )

32768 and 32767 can be designated at

S1

,

S2

, and

S3

.

7-321

7.13 Data Control Instructions
7.13.1 Upper and lower limit controls for BIN 16-bit and BIN 32-bit data (LIMIT(P),DLIMIT(P))

––

D

8

Other

S1

S2

6

LIMIT(P),DLIMIT(P)

(3) When control based only on upper limit values is performed, the lower limit value designated
at

S1

is set at " 32678".

(4) When control based only on lower limit values is performed, the upper limit value designated
at

S2

is set at "32767".

DLIMIT
(1) The function controls the output value to be stored at the device designated by ( D ,

D

+1) by

checking whether the input value (BIN 32 bits) designated by ( S3 ,

S3 +1) is within the range

of upper and lower limit values specified by ( S1 ,

+1) or not.

S1 +1

S1

When Lower limit value
S2 +1
S2
When Upper limit value
S1 +1

S1

When Lower limit value

S3 +1

S1

+1) and ( S2 ,
S1 +1

S3

Input value
S3 +1

S3

Input value
S3 +1

S3

S2 +1

Input value

S2

Upper limit value

S2

S1

D +1

D

Lower limit value

Output value

S2 +1

D +1

S2

D

Upper limit value

Output value

S3 +1

D +1

S3

Input value

D

Output value

Output value ( D +1, D )

Value designated by S2 +1, S2
Output value ( S3 +1, S3 )
0

Value designated by S1 +1, S1

(2) The values designated by ( S1 , S1 +1), ( S2 ,
2147483648 to 2147483647.

S2

+1), or ( S3 ,

S3

+1) are within the range of

(3) To perform controls based only on the upper limit value, set the lower limit value designated
by ( S1 ,

S1

+1) to " 2147483648".

(4) To perform controls based only on the lower limit value, set the upper limit value designated
by ( S2 ,

S2

+1) to "2147483647".

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The lower limit value designated by
S2

7-322

.

S1

is larger than the upper limit value designated by
(Error code: 4100)

LIMIT(P),DLIMIT(P)

Program Example

1

(1) The following program conducts limit controls from 500 to 5000 on the data set as BCD
values from X20 to X2F, and stores the result at D1 when X0 is turned ON.
[Ladder Mode]

[List Mode]
Step

Instruction

2

Device

3
4
6

[Operation]
• D1 becomes 500 if D0
Example

500.

D0 400 D1 500

• D1 becomes the value of D0 when 500
Example

6

5000.

D0 1300 D1 1300

• D1 becomes 5000 when 5000
Example

D0

7

D0.

D0 9600 D1 5000

(2) The following program conducts limit value controls from 10000 to 1000000 on the data set
as BCD values from X20 to X3F when X0 is turned ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device
7.13 Data Control Instructions
7.13.1 Upper and lower limit controls for BIN 16-bit and BIN 32-bit data (LIMIT(P),DLIMIT(P))

[Operation]
• (D11, D10) become 10000 if (D1, D0) are less than 10000.
Example

(D1,D0) 400 (D11,D10) 10000

• (D11, D10) become the value of (D1, D0) if 10000
Example

(D1, D0)

1000000.

(D1,D0) 345678 (D11,D10) 345678

• (D11, D10) become 1000000 if 1000000
Example

8

(D1, D0).

(D1,D0) 9876543 (D11,D10) 1000000

7-323

BAND(P),DBAND(P)

7.13.2

BIN 16-bit and 32-bit dead band controls (BAND(P),DBAND(P))

BAND(P),DBAND(P)

Basic

High
performance

Process Redundant Universal

indicates an instruction symbol of BAND/DBAND.
Command

BAND,DBAND

S1

S2

S3

D

S1

S2

S3

D

Command
P

BANDP,DBANDP

S1

: Lower limit value of dead band (no output band) (BIN 16/32 bits)

S2

: Upper limit value of dead band (no output band) (BIN 16/32 bits)

S3

: Input value to be controlled by a dead band control (BIN 16/32 bits)

D

: Head number of the devices where the output value controlled by the dead band control will be stored
(BIN 16/32 bits)

Internal Devices

Setting
Data

Bit

Word

J

R, ZR

\

Bit

U

Word

Zn

\G

Constants
K, H

Other

S1

––

S2

––

S3

––
––

D

––

Function
BAND
(1) Controls the output value to be stored at the device designated by
the input value (BIN 16 bits) designated by

S3

D

by checking whether

is within the range of dead band upper and

lower limit values specified by S1 and S2 or not.
Output value is controlled in the way shown below:
• When

S1

Lower limit value

S3

Input value ..........

Input value -

S1

Lower

D

Output value

• When

S2

Upper limit value

S3

Input value

......... S3 Input value -

S2

Upper

D

Output value

• When

S1

Lower limit value

S3

Input value

Upper ..... 0

D

Output value

S2

S3

Output value ( D )
Dead band
lower limit value ( S1 )
Input value ( S2 )

0
Dead band upper
limit value ( S3 )

(2) The values that can be designated by
32767.

7-324

S1

,

S2

, and

S3

are in the range of from

32768 to

BAND(P),DBAND(P)

(3) The output value stored at D is a signed 16-bit BIN value. Therefore, if the operation results
exceed the range of from 32768 to 32767, the following will take place:
Dead band lower limit value

When :

Input value
Output value

S3

.................10

S1

............................................ 32768

32768

10

1

8000H

AH

7FF6H

2
32758

DBAND

3

(1) Controls the output value to be stored at the device designated by
the input value (BIN 32 bits) designated by ( S3 ,
and lower limit values specified by ( S1 ,

S1

S3

D

by checking whether

+1) is within the range of dead band upper

+1) and ( S2 ,

S2

+1) or not.

4

Output value is controlled in the way shown below:
S1 +1

S3 +1

S1

When Lower limit value
S2 +1

S2

When Upper limit value
S1 +1

When Lower limit value

S1 +1

S3

Input value
S3 +1

S3 +1
S3
Input value
S3 +1

S1

S3 +1

S3

Input value

S3

Input value

S2 +1

D +1

Input value

S2

Upper limit value

D

Output value
D +1

0

6

D

Output value

S2 +1
S2
Upper limit value

S3

D +1

S1

Lower limit value

6

D

Output value

7

Output value ( D +1, D )
Dead band lower
limit value ( S1 , S1 +1)

8

Input value ( S3 , S3 +1)

0

Dead band upper
limit value ( S2 , S2 +1)
S2

+1), or ( S3 ,

S3

+1) are within the range of from

(3) The output value stored at D , D +1 is a signed 32-bit BIN value. Therefore, if the operation
results exceed the range of from 2147483648 to 2147483647, the following takes place:
When :

Dead band lower limit value ( S1 ,
Input value ( S3 ,
Output value

S3

S1

+1).....1000

+1) ............................... 2147483648

2147483648 1000 80000000H 000003E8H
7FFFFC18H 2147482648

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The lower limit value designated by
S2

.

S1

is greater than the upper limit value designated by
(Error code: 4100)

7-325

7.13 Data Control Instructions
7.13.2 BIN 16-bit and 32-bit dead band controls (BAND(P),DBAND(P))

(2) The values designated by ( S1 , S1 +1), ( S2 ,
2147483648 to 2147483647.

BAND(P),DBAND(P)

Program Example
(1) The following program performs the dead band control by applying the lower and upper
limits of 0 and 1000 for the data set in BCD at X20 to X2F and stores the result of control at
D1 when X0 is turned ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
• "0" is stored at D1 if 0 D0 1000.
Example

D0 500 D1 0

• The value of (D0)
Example

1000 is stored at D1 if 1000

D0.

D0 7000 D1 6000

(2) The following program performs the dead band control by applying the lower and upper
limits of 10000 and 10000 for the data set at D0 and D1 and stores the result of control at
D10 and D11 when X0 is turned ON
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
• The value (D1, D0)
Example

( 10000) is stored at (D11, D10) if (D1, D0) ( 10000).

(D1, D0)

12345 (D11, D10)

• The value 0 is stored at (D11, D10) if
Example

7-326

(D1, D0)

10000.

(D1, D0) 6789 (D11, D10) 0

• The value (D1, D0)
Example

10000

2345

10000 is stored at (D11, D10) if 10000

(D1, D0) 50000 (D11, D10) 40000

(D1, D0).

ZONE(P),DZONE(P)

7.13.3

Zone control for BIN 16-bit and BIN 32-bit data
(ZONE(P),DZONE(P))

1

ZONE(P),DZONE(P)

Basic

High
performance

Process Redundant Universal

2
3

indicates an instruction symbol of ZONE/DZONE.
Command

ZONE,DZONE

S1

S2

S3

D

S1

S2

S3

D

Command
P

ZONEP,DZONEP

: Negative bias value to be added to an input value (BIN 16/32 bits)

S2

: Positive bias value to be added to an input value (BIN 16/32 bits)

S3

: Input value used for a zone control (BIN 16/32 bits)

D

: Head number of the devices where the output value controlled by the zone control will be stored
(BIN 16/32 bits).

Bit

Word

J

R, ZR

Bit

\

U

Word

\G

6
6

S1

Internal Devices

Setting
Data

Constants
K, H

Zn

7
Other

S1

––

S2

––

S3

––
––

Function
ZONE
device number designated by

or

S1
D

S2

to input value designated by

S3

, and stores at

.

Bias values are calculated in the following manner:
• When

S3

Input value

0.......

• When

S3

Input value

0................................................................... 0

• When

S3

Input value

0.......

S3

S3

Input value +

Input value +

S1

S2

Negative bias value

Positive bias value

D

Output value

D

Output value

D

Output value

Output value ( D )

Positive bias value ( S2 )

0

Input value ( S3 )
Negative bias value ( S1 )

7-327

8

7.13 Data Control Instructions
7.13.3 Zone control for BIN 16-bit and BIN 32-bit data (ZONE(P),DZONE(P))

––

D

(1) Adds bias value designated by

4

ZONE(P),DZONE(P)
(2) The values that can be designated by
32767.

S1

,

S2

, and

S3

are in the range of from

32768 to

(3) The output value stored at D is a signed 16-bit BIN value. Therefore, if the operation results
exceed the range of 32768 to 32767, the following will take place:
Negative bias value

When :

Input value
Output value

S3

S1

.............................. 100

............................................ 32768

32768 + ( 100)

8000H + FF9C

7F9CH

32668

DZONE
(1) Adds bias value designated by ( S1 ,
S3

S1

+1) or ( S2 ,

S2

+1) to input value designated by ( S3 ,

+1), and stores the result at device number designated by (

,

D

D

+1).

Addition of the bias value is performed as follows:
S3 +1
When

S3 +1

S3
0

Input value
S3 +1

S1 +1
S1
+ Negative bias value

S3

Input value

S3

When

Input value

0

When

S3 +1
S3
Input value

0

0
S2 +1
S2
+ Positive bias value

S3
S3 +1
Input value

D +1

D

Output value
D
D +1
Output value
D
D +1
Output value

Output value ( D +1, D )

Positive bias value
( S2 , S2 +1)
Input value
( S3 , S3 +1)

0

Negative bias value
( S1 , S1 +1)

(2) The values designated by ( S1 , S1 +1), ( S2 ,
2147483648 to 2147483647.
(3) The value stored at (

D

,

D

S2

+1), or ( S3 ,

S3

+1) is a signed 32-bit BIN value.

Therefore, if the operation results exceed the range of from
the following takes place:
When :

Negative bias value ( S1 ,
Input value ( S3 ,
Output value

+1) are within the range of from

S3

S1

2147483648 to 2147483647,

+1).................. 1000

+1) ............................... 2147483648

2147483648 + ( 1000)
7FFFFC18

80000000H + FFFFFC18H

2147482648.

Operation Error
(1) There are no operation errors associated with the ZONE(P) or DZONE(P) instructions.

7-328

ZONE(P),DZONE(P)

Program Example

1

(1) The following program performs zone control by applying negative and positive bias values
of 100 to 100 for the data set at D0 and stores the result of control at D1 when X0 is turned
ON.
[Ladder Mode]

2

[List Mode]
Step

Instruction

3

Device

4
[Operation]
• The value (D0) + ( 100) is stored at D1 if D0
Example

D0

200 D1

• The value 0 is stored at D1 if D0

300

6

0.

• The value of (D0) + 100 is stored at D1 if 0
Example

6

0.

D0.

D0 700 D1 800

7

(2) The following program performs zone control by applying negative and positive bias values
of 10000 to 10000 for the data set at D0 and D1 and stores the result of control at D10 and
D11 when X1 is turned ON.
[Ladder Mode]

Step

Device

Instruction

7.13 Data Control Instructions
7.13.3 Zone control for BIN 16-bit and BIN 32-bit data (ZONE(P),DZONE(P))

[Operation]
• The value (D1, D0) + ( 10000) is stored at (D11, D10) if (D1, D0)
Example

(D1,D0)

12345 (D11,D10)

• The value 0 is stored at (D11, D10) if (D1, D0)

0.

22345
0.

• The value (D1, D0) + 10000 is stored at (D11, D10) if 0
Example

8

[List Mode]

(D1, D0).

(D1,D0) 50000 (D11,D10) 60000

7-329

(SCL(P),DSCL(P))

7.13.4

Scaling (Point-by-point coordinate data) (SCL(P),DSCL(P))

(SCL(P),DSCL(P))

Ver.
Basic

High
performance

Process Redundant Universal

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.
QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

indicates an instruction symbol of SCL/DSCL.
Command

SCL.DSCL

S1

S2

D

S1

S2

D

Command

SCLP.DSCLP

P

Setting
Data

S1

: Input values for scaling or head number of the device where input values are stored(BIN 16/32 bits)

S2

: Head number of the devices where scaling conversion data are stored(BIN 16/32 bits)

D

: Head number of the devices where output values depending on scaling are stored(BIN 16/32 bits).

Internal Devices
Bit

S1

––

S2

––

D

––

Word

J

R, ZR

Bit

\

U

Word

\G

Constants
K, H

Zn

Other
––

––

––

––

––

––

)

Function
SCL(P)
(1) This instruction executes scaling for the scaling conversion data (16-bit data units) specified
by

S2

with the input value specified by

S1

, and then stores the operation result into the

devices specified by D .
The scaling conversion is executed based on the scaling conversion data stored in the
device specified by

and up.

S2

Y

Scaling conversion data component
Setting item

Device assignment

Number of coordinate points

S2

X coordinate

S2

＋1

Y coordinate

S2

＋2

X coordinate

S2

＋3

Y coordinate

S2

＋4

Point 1

Point 2

Point 2

Output
value： D

Point 3

Point n
Point 1
Point n−1

X coordinate

S2

＋2n−1

Y coordinate

S2

＋2n

Point n

X

Input value： S1

※n indicates the number of coordinates
specified by (S2).

Operation error

Operable range

Operation error

(2) If the value does not result in an integer, this instruction rounds the value to the whole
number.
(3) Set the X coordinate of the scaling conversion data in ascending order.
(4) Set the input value
devices).

7-330

S1

within the range of the scaling conversion data (within the range of

S2

(SCL(P),DSCL(P))
(5) If some specified points have same X coordinates, the Y coordinate data of the highest point
number will be output.

1

(6) Specify the number of coordinate points of scaling conversion data from 1 to 32767.

DSCL(P)
(1) This instruction executes scaling for the scaling conversion data (32-bit data units) specified
by

S2

with the input value specified

S1

, and then stores the operation result into the devices

specified by D .
The scaling conversion is executed based on the scaling conversion data stored in the
device specified by

3

and up.

S2

2

Scaling conversion data component
Setting item

Point 1

Device assignment
S2

＋1

，S2

X coordinate

S2

＋3

，S2

＋2

Y coordinate

S2

＋5

，S2

＋4

X coordinate

S2

＋7

，S2

＋6

Number of coordinate points

Point 2
Y coordinate

S2

＋9

，S2

Operation
error

Operation error

Operable range
Input value： S1

X

6

Point n−1
＋8

X coordinate

S2

＋4n−1 ， S2

＋4n−2

Y coordinate

S2

＋4n＋1 ， S2

＋4n

Point n

4

Y

※n indicates the number of coordinates
specified by (S2).

Output D
value：

Point n

6

Point 1
Point 2

7

(2) If the value does not result in an integer, this instruction rounds the value to the whole
number.
(3) Set the X coordinate of the scaling conversion data in ascending order.
(4) Set the input value
and

S2

S1

within the range of the scaling conversion data (within the range of

S2

8

+1 devices).

(5) If some specified points have same X coordinates, the Y coordinate data of the highest point
number will be output.
7.13 Data Control Instructions
7.13.4 Scaling (Point-by-point coordinate data) (SCL(P),DSCL(P))

(6) Specify the number of coordinate points of scaling conversion data from 1 to 32767.

7-331

(SCL(P),DSCL(P))

(1) There are two searching methods that depend on whether SM750 is on or off.
SM750

Searching method

Range of number of searches

OFF

Sequential search

1

Number of times

32767

ON

Binary search

1

Number of times

15

(2) When the scaling conversion data are set in ascending order, the searching
methods change from one to the other depending on the SM750 status.
Therefore, the processing speed also changes. The number of searches
determines the processing speed. Fewer number of serches make the
processing run faster.
(a) If the data processing speed with the sequential search rises:
If the number of coordinates is highest and the input value S1 is within
the coordinate range from 1 to 15 point, the number of sequential
searches will be 15 or smaller. Therefore, the data processing speed with
the sequential search will rise.
(b) If the data processing speed with the binary search rises:
f the maximum number of searches is 15 and the input value S1 is out of
the coordinate range, 16 or over, the number of binary searches will be
equal to the number of sequential numbers or smaller. Therefore, the
data processing speed with the binary search will rise.
Number of coordinate points=32767

Number of sequential searches=32767
Number of binary searches=15
The processing speed with binary search
rises since the number of binary searches is
smaller than the number of sequential searches.

S1

S1
Number of sequential searches=1
Number of binary searches=15
The processing speed with sequential searches
rises since the number of binary searches is
larger than the number of sequential searches.

7-332

(SCL(P),DSCL(P))

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• The X coordinates of the scaling conversion data positioned before the point specified by
S1

are not set in ascending order. (However, this error is not detected when SM750 is on.)
(Error code: 4100)

• The input value specified by

S1

is out of the range of the scaling conversion data set.
(Error code: 4100)

• The number of X and Y coordinates of the device specified by
1 to 32767.
• The number of X and Y coordinates of the device specified by
range.

S2

S2

is out of the range from
(Error code: 4100)
is out of the specified
(Error code: 4101)

Program Example

1
2
3
4
6
6

(1) The following program executes scaling for the scaling conversion data of which the devices
specified at D100 and up are set with the input value specified at D0, and then outputs the
data at D20.
[Ladder Mode]

7

[List Mode]
Step

Instruction

Device

8

[Operation]
7.13 Data Control Instructions
7.13.4 Scaling (Point-by-point coordinate data) (SCL(P),DSCL(P))

Scaling conversion data component
Setting item

Device Setting contents

Number of coordinate points

D100

K5

X coordinate

D101

K5

Point 1

Point 2

Point 3

Point 4

Point 5

Y coordinate

D102

K13

X coordinate

D103

K10

Y coordinate

D104

K15

X coordinate

D105

K17

Y coordinate

D106

K13

X coordinate

D107

K20

Y coordinate

D108

K8

X coordinate

D109

K25

Y coordinate

D110

K22

Y

Point 2
Point 1 （10，15）
（5，13）
D20＝11
（Output value）

Point 3
（17，13）
Point 4
（20，8）

Point 5
（25，4）

D0＝18
（Output value）

X

7-333

SCL2,DSCL2

7.13.5

Scaling (Point-by-point coordinate data)
(SCL2(P),DSCL2(P))

SCL2,DSCL2

Ver.
Basic

High
performance

Process Redundant Universal

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.
QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

indicates an instruction symbol of SCL/DSCL.
Command

SCL.DSCL

S1

S2

D

S1

S2

D

Command

SCLP.DSCLP

P

S1

: Input values for scaling or head number of the device where input values are stored(BIN 16/32 bits)

S2

: Head number of the devices where scaling conversion data are stored(BIN 16/32 bits)

D

: Head number of the devices where output values depending on scaling are stored(BIN 16/32 bits).

Internal Devices

Setting
Data

Bit

S1

––

S2

––

D

––

Word

J

R, ZR

\

Bit

Word

U

Constants
K, H

Zn

\G

Other
––

––

––

––

––

––

Function
SCL2
(1) This instruction executes scaling for the scaling conversion data (16-bit data units) specified
by

S2

with the input value specified by

S1

, and then stores the operation result into the

devices specified by D .
The scaling conversion is executed based on the scaling conversion data stored in the
device specified by

S2

and up.
Y

Scaling conversion data component
Setting item
Number of coordinate points

X coordinate

Device assignment
S2

Point 1

S2

＋1

Point 2

S2

＋2

Point n

S2

＋n

Point 1

S2

＋n＋1

Point 2

S2

＋n＋2

Point 2
Point 3

Output
D
value：

Point n−1
Point n

Y coordinate

Point 1

X

Input value： S1
Point n

S2

＋2n

Operation error

Operable range

Operation error

※n indicates the number of coordinates
specified by (S2).

(2) If the value does not result in an integer, this instruction rounds the value to the whole
number.
(3) Set the X coordinate of the scaling conversion data in ascending order.

7-334

SCL2,DSCL2
(4) Set the input value
devices).

S1

within the range of the scaling conversion data (within the range of

S2

(5) If some specified points have same X coordinates, the Y coordinate data of the highest point
number will be output.

DSCL2(P)
(1) This instruction executes scaling for the scaling conversion data (32-bit data units) specified
by

S2

with the input value specified

S1

3

and up.

S2

4

Scaling conversion data component
Setting item

Device assignment

Number of coordinate points

S2

＋1

， S2

Point 1

S2

＋3

， S2

＋2

Point 2

S2

＋5

， S2

＋4

X coordinate

Y coordinate

2

, and then stores the operation result into the devices

specified by D .
The scaling conversion is executed based on the scaling conversion data stored in the
device specified by

1

Y
Operation
error

Operation error

Operable range
Input value： S1

6

X

Point n−1

Point n

S2

＋2n＋1

， S2

＋2n

Point 1

S2

＋2n＋3

， S2

＋2n＋2

Point 2

S2

＋2n＋5

， S2

＋2n＋4

Point n

S2

＋4n＋1

， S2

＋4n

Output D
value：

6

Point n
Point 1
Point 2

7

※n indicates the number of coordinates
specified by (S2).

(2) If the value does not result in an integer, this instruction rounds the value to the whole
number.

8

(3) Set the X coordinate of the scaling conversion data in ascending order.
(4) Set the input value
and

S2

S1

within the range of the scaling conversion data (within the range of

S2

+1 devices).

(6) Specify the number of coordinate points of scaling conversion data from 1 to 32767.

When the coordinates of the scaling conversion data are set in ascending order,
the searching methods change from one to the other depending on the SM750
status. Therefore, the processing speed also change. The number of searches
determines the processing speed. Fewer number of searches make the
processing run faster.
For details, refer to Section 7.13.4.

7-335

7.13 Data Control Instructions
7.13.5 Scaling (Point-by-point coordinate data) (SCL2(P),DSCL2(P))

(5) If some specified points have same X coordinates, the Y coordinate data of the highest point
number will be output.

SCL2,DSCL2

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• The X coordinates are not set in ascending order.
• The input value specified by

S1

(Error code: 4100)

is out of the range of the scaling conversion data set.
(Error code: 4100)

• The number of X and Y coordinates of the device specified by
1 to 32767.
• The number of X and Y coordinates of the device specified by
range.

S2

S2

is out of the range from
(Error code: 4100)
is out of the specified
(Error code: 4101)

Program Example
(1) The following program executes scaling for the scaling conversion data of which the devices
specified at D100 and up are set with the input value specified at D0, and then outputs the
data at D20.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
Scaling conversion data component
Setting item
Device Setting contents
Number of coordinate points

D110

K5

Point 1

D111

K7

Point 2

D112

K13

Point 3

D113

K15

Point 4

D114

K18

Point 5

D115

K20

Point 1

D116

K-14

Point 2

D117

K-7

X coordinate

Y coordinate

7-336

Point 3

D118

Point 4

D119

K-11

Point 5

D120

K-18

K-15

Y

D0=11
(Input value)
X
Point 2
(13, -7)
Point 3
(15, -9)

D200=-9
(Output value)
Point 1
(7, -14)

Point 4
(18, -11)
Point 5
(20, -13)

RSET(P)

7.14 File register switching instructions
1

7.14.1

Switching file register numbers (RSET(P))

2
RSET(P)

High
performance

Basic

Process Redundant Universal

3
4

Command

RSET

RSET

S

RSETP

S

6

Command

RSETP

S

: Block number data used to change the block number or the number of the device where the block number
data is stored (BIN 16 bits)

Internal Devices

Setting
Data

Bit

Word

J

R, ZR

\

Bit

Word

U

Zn

\G

Constants
K, H

Other

6
7

––

S

8

Function

Example
When switching block number from block No. 0 to block No. 1

Processing executed to file registers

S Setting of a
block number

R0 Block 0

(
R32767

Presently
used file
register

R0

)

R0

Block 1

File register
used after the
execution of
RSET
R32767 instruction

(

)

Block n

R32767

When a file register (R) is refreshed and the block No. of the file register is
switched with the RSET instruction, follow restrictions.
For the restrictions on file registers, refer to Section 3.10.

7-337

7.14 File register switching instructions
7.14.1 Switching file register numbers (RSET(P))

(1) Changes the file register block number used in the program to the block number stored in
the device designated at S .
Following the block number change, all file registers used in the sequence program are
processed to the file register of the block number after the change.

RSET(P)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The block number designated by

S

does not exist.

(Error code: 4100)

• There is no file register for the specified block No.

(Error code: 4101)

Program Example
(1) The following program compares R0 of block No. 0 and block No. 1.
[Ladder Mode]
Designates block No. 0
Executes reading R0 of block No.0
Designates block No. 1
Executes reading R0 of block No.1

Compares the read values

[List Mode]
Step

Instruction

Device

[Operation]
Block No. 0
R0
R1
R2
R3
R4
R5

-3216
5001
128
-7981
9610
0

Block No. 1

D0

D1
-3216

756

Y41 turns ON since D0,DT>,DT<=,DT<,DT>=)

7.15.7

Date comparison (DT=,DT<>,DT>,DT<=,DT<,DT>=)

(DT=,DT<>,DT>,DT<=,DT<,DT>=)

Ver.
High
performance

Basic

Process Redundant Universal

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.
QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

indicates an instruction symbol of DT=/DT<>/DT<=/DT>/DT>=.

LD
Command

AND
Command

OR

S1 : Head number of the devices where the data to be compared are stored (BIN 16 bits)
S2 : Head number of the devices where the data to be compared are stored (BIN 16 bits)

n : Value of the data to be compared or the number of the stored data to be compared (BIN 16 bits)
Setting
Data

Internal Devices
Bit

Word

R, ZR

J

\

Bit

Word

U

Zn

\G

Constants
K, H

Other

S1

––

––

––

––

S2

––

––

––

––

n

––

––

Function
(1) This instruction compares the date data specified by
date data specified by
compared.

S1

S1

with those specified by

S2

, or the

with current date data. Setting n can determine the data to be

(a) Comparison of given date data
• This instruction treats the date data specified by S1 and S2 as a normally open
contact, and then compares the data in accordance with the value of n.
Data range
S1

Year

S1

＋1

Month

S1

＋2

Day

Data range

（1980∼2079）
Comparison
（1∼12）
operator
（1∼31）

S2

Year

（1980∼2079）

S2

＋1

Month

（1∼12）

S2

＋2

Day

（1∼31）

Comparison
operation result

(b) Comparison of current date data
• This instruction treats the date data specified by S1 and the current date data as a
normally open contact, and then compares the data in accordance with the value of
n.
Data range
S1

7-356

Year

（1980∼2079）

S1

＋1

Month

（1∼12）

S1

＋2

Day

（1∼31）

Comparison
operator

Current date

Comparison
operation result

(DT=,DT<>,DT>,DT<=,DT<,DT>=)

When either S1 or S2 corresponds to any of the following in comparing given or
current date data with given date data, the operation error (error code: 4101) or a
malfunction may occurs.
• The range of the devices to be used for the index modification is specified over
the range of the device specified by
• File registers are specified by

S1

or

S1

or

S2

without a register set.

S2

3

(3) This instruction sets the year of four digits selected from 1980 to 2079 with the BIN value
S1

or

S2

S1

+1 or

S2

S1

+2 or

S2

6

+2.

(6) This instruction specifies the following values at n so that the data to be compared can be
specified.
The bit configuration specified at n is as follows.
This instruction specifies 0 at bits from 3rd to 14th.
The instruction will be non-conductive status without
specifying 0 regardless of the operation result.

b15 b14
0/1

6

+1.

(5) This instruction sets the day selected from 1 to 31 (1st to 31st) for with the BIN value
specified by

4

.

(4) This instruction sets the month selected from 1 to 12 (January to December) with the BIN
value specified by

2

.

(2) This instruction sets BIN values for each item.
specified by

1

b3
0

b2

b1

7
8

b0

0/1 0/1 0/1
Day

If this instruction specifies 1 (on) at 15th bit, the
instruction compares S1 with the current date in
accordance with the bit condition specified at 0 to 2nd
bit.

7.15 Clock instructions
7.15.7 Date comparison (DT=,DT<>,DT>,DT<=,DT<,DT>=)

Month
Year

(a) Date data to be compared (from 0 to 2nd bit)
• 0: Does not compare specified date data (year/month/day).
• 1: Compares specified date data (year/month/day).
(b) Operation data to be compared (15th bit)
• 0: Compares the date data specified by

S1

with the date data specified by

• 1: Compares the date data specified by

S1

with the current date data.

• Ignores the date data specified by

S2

S2

.

.

7-357

(DT=,DT<>,DT>,DT<=,DT<,DT>=)

(c) The following table shows processing details of bits to be compared.
n value for

n value for

comparison of

comparison of

Date to be

specified date data

specified date data

compared

with given date data

with current date data

0001H

8001H

Day

Comparison of days ( S1 +2)

0002H

8002H

Month

Comparison of months ( S1 +1)

0003H

8003H

Month, day

Comparison of months ( S1 +1) and days ( S1 +2)

0004H

8004H

Year

Comparison of years ( S1 )

0005H

8005H

Year, day

Comparison of years ( S1 ) and days ( S1 +2)

0006H

8006H

Year, month

Comparison of years ( S1 ) and months ( S1 +1)

0007H

8007H

Year, month, day

Processing details

Comparison of years ( S1 ), months ( S1 +1),
and days ( S1 +2)

Other than 0001H to 0007H,8001H to 8007H

No objects

No comparison of years ( S1 ), months ( S1 +1),
and days ( S1 +2) (Non-conductive)

(7) If the data stored in the devices to be compared are not recognized as date data, SM709 will
be turned on after the instruction execution and no-conductive status will be made. Even if
they are not recognized as date data but the range of the devices is within the setting range,
SM709 will not be turned on.
Moreover, if the range of devices specified by S1 to S1 +2 or S2 to S2 +2 exceeds the range of
specified devices, SM709 will be turned on after the instruction execution and no-conductive
status will be made.
Once SM709 is turned on, on-status will be retained till when the CPU modules are reset or
powered off. Therefore, turn off SM709 if necessary.
(8) The following table shows the comparison operation results for each instruction.
Instruction
symbols in
DT=
DT<>
DT>
DT<=
DT<
DT>=

7-358

Condition
S1

=
>

S1

S1

<

Conductive status

S2

S2

symbols in

DT<>

S2

S2

S1

Instruction

DT=

S2

S2

S1

S1

Comparison
operation result

DT>
DT<=
DT<
DT>=

Condition
S2

S1

S2

=
>

S2

S2

S1

S1

S1

S2

S1

S1

Comparison
operation result

<

S2

No-conductive
status

(DT=,DT<>,DT>,DT<=,DT<,DT>=)

(a) The following figure shows the comparison example of dates.
A

2006/1/1

B

1

C

2007/1/1
2008/1/1
2009/1/1
(2006/9/22) (2007/6/23)
(2008/8/8)

The following table shows the conductive states resulting from performing the
comparison operation of the dates A, B, and C shown above.
Even if the objects to be compared are under the same condition, the comparison
operation results vary depending on the objects selected.

3

Comparison condition

Comparison
objects

2

A,DT>,DT<=,DT<,DT>=)

• Date B: 2007/03/29
• Date C: 2008/02/31 (This date is settable, though it does not exist.)
Comparison condition

Comparison
objects

A,DT>,DT<=,DT<,DT>=)

Operation Error
(1) Any operation errors do not occur in DT=,DT<>,DT>,DT<=,DT<,DT>= instruction.

Program Example
(1) The following program compares the data stored in D0 with the data (year, month, and day)
stored in D10, and makes Y33 be conductive status when the data stored in D0 meet the
data stored in D10.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

(2) The following program compares the data stored in D0 with the current date data (year and
month), and makes Y33 be conductive status when the data stored in D0 do not meet the
current date data, when M0 is turned on.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

(3) The following program compares the data stored in D0 with the data (year and day) stored in
D10, and makes Y33 be conductive status when the data value stored in D10 is smaller than
the data value stored in D0, when M0 is turned on.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

(4) The following program compares the data stored in D0 with the current date data (year), and
makes Y33 be conductive status when the value of the current date data is the data value
stored in D0 or larger.
[Ladder Mode]

[List Mode]
Step

7-360

Instruction

Device

(TM=,TM<>,TM>,TM<=,TM<,TM>=)

7.15.8

Clock comparison (TM=,TM<>,TM>,TM<=,TM<,TM>=)

1
(TM=,TM<>,TM>,TM<=,TM<,TM>=)

Ver.
Basic

High
performance

Process Redundant Universal

QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later.

2

QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.

(TM=,TM<>,TM>,TM<=,TM<,TM>=)

3
indicates an instruction symbol of DT＝/DT＜＞/DT＜/DT＜＝/DT＞/DT＞＝.

LD

S1

S2

n

S1

S2

n

S1

S2

n

4

Command

AND

6

Command

OR

S1

6

: Head number of the devices where the data to be compared are stored (BIN 16 bits)

7

: Head number of the devices where the data to be compared are stored (BIN 16 bits)
n : Value of the data to be compared or the number of the stored data to be compared (BIN 16 bits)

S2

Internal Devices

Setting
Data

Bit

R, ZR

Word

J

\

Bit

U

Word

Zn

\G

Constants
K, H

Other

S1

––

––

––

––

S2

––

––

––

––

n

––

––

(1) This instruction compares the clock data specified by
clock data specified by
compared.

S1

with those specified by

S1

S1

, or the

with the current time data. Setting n determines the data to be

(a) Comparison of given clock data
• This instruction treats the clock data specified by

S1

and the clock data specified by

as a normally open contact, and compares the data in accordance with the value
of n.
S1

Data range
Hour

（0∼23）

S1

＋1

Minute

（0∼59）

S1

＋2

Second

（0∼59）

Data range
S2
Comparison
operator

Hour

（0∼23）

S2

＋1

Minute

（0∼59）

S2

＋2

Second

（0∼59）

Comparison
operation result

7-361

7.15 Clock instructions
7.15.8 Clock comparison (TM=,TM<>,TM>,TM<=,TM<,TM>=)

Function

S1

8

(TM=,TM<>,TM>,TM<=,TM<,TM>=)

(b) Comparison of current time data
• This instruction treats the clock data specified by S1 and the current time data as a
normally open contact, and compares the data in accordance with the value of n.
• This instruction treats the clock data specified by
data.

S1

as dummy data and ignores the

Data range
S1

Hour

（0∼23）

S1

＋1

Minute

（0∼59）

S1

＋2

Second

（0∼59）

Comparison
operator

Current time

Comparison
operation result

When either S1 or S1 corresponds to any of the following conditions in comparing
given or current time data with specified clock data, the operation error (error
code: 4101) or a malfunction may occurs.
• The range of the devices to be used for the index modification is specified over
the range of the device specified by
• File registers are specified by

or

S1

S1

or

S1

without a register set.

S1

.

(2) This instructions set BIN values for each item.
(3) This instructions sets the time selected from 0 to 23 (midnight to 23 o'clock) with the BIN
value specified by

S1

or

S1

. (Uses the 24-hour clock.)

(4) This instructions sets the minute selected from 0 to 59 (0 to 59 minutes) with BIN value
specified by

S1

+1 or

S1

+1.

(5) This instructions sets the second selected from 0 to 59 (0 to 59 seconds) with BIN value
specified by

S1

+2 or

S1

+2.

(6) This instructions specifies the following values at n so that the data to be compared can be
specified.
The bit configuration specified at n is as follows.
This instruction specifies 0 at bits from 3rd to 14th.
The instruction will be non-conductive status without
specifying 0 regardless of the operation result.

b15 b14
0/1

b3
0

b2

b1

b0

0/1 0/1 0/1
Second

If this instruction specifies 1 (on) at 15th bit, the
instruction compares S1 with the current date in
accordance with the bit condition specified at 0 to 2nd
bit.

Minute
Hour

(a) Clock data to be compared (from 0 to 2nd bit)
• 0: Does not compare specified clock data (hour/minute/second).
• 1: Compares specified clock data (hour/minute/second).
(b) Operation data to be compared (15th bit)
• 0: Compares the clock data specified by

S1

with the clock data specified by

• 1: Compares the clock data specified by

S1

with the current time data.

Ignores the clock data specified by

7-362

S1

.

S1

.

(TM=,TM<>,TM>,TM<=,TM<,TM>=)

(c) The following table shows processing details of bits to be compared.

1

n value for

n value for

comparison of

comparison of

Time to be

pecified clock data with

specified clock data with

compared

given clock data

current time data

0001H

8001H

Second

Comparison of seconds ( S1 +2)

0002H

8002H

Minute

Comparison of minutes ( S1 +1)

0003H

8003H

Minute,

Comparison of minutes ( S1 +1) and seconds

second

days ( S1 +2)

Hour

Comparison of hours ( S1 )

Hour,

Comparison of hours ( S1 ) and

second

seconds ( S1 +2)

Hour, minute

Comparison of hours ( S1 ) and minutes ( S1 +1)

Hour, minute,

Comparison of hours ( S1 ), minutes ( S1 +1),

second

and seconds ( S1 +2)

0004H

8004H

0005H

8005H

0006H

8006H

0007H

8007H

Other than 0001H to 0007H,

No objects

8001H to 8007H

Processing details

2
3
4

No comparison of hours ( S1 ), minutes ( S1 +1),

6
6

and seconds ( S1 +2) (Non-conductive)

(7) If the data stored in the devices to be compared are not recognized as date data, SM709 will
be turned on after the instruction execution and no-conductive status will be made. Once
SM709 is turned on, on-status will be retained till when the CPU modules are reset or
powered off. Therefore, turn off SM709 if necessary.
Moreover, if the range of devices specified by S1 to S1 +2 or S1 to S1 +2 exceeds the range of
specified devices, SM709 will be turned on and no-conductive status will be made.

7
8

(8) The following table shows the comparison operation results for each instruction.

TM=
TM<>
TM>
TM<=
TM<
TM>=

Condition
S1

S1

S2

Conductive status
S2

S1

S1

TM<>

S2

>

<

S2

S2

Instruction
symbols in
TM=

= S2

S1

S1

Comparison
operation result

TM>
TM<=
TM<
TM>=

Condition
S2

S1

S2

=

>

S2

No-conductive
status

S2

S1

S1

S1
S2

S1

S1

Comparison
operation result

<

S2

7-363

7.15 Clock instructions
7.15.8 Clock comparison (TM=,TM<>,TM>,TM<=,TM<,TM>=)

Instruction
symbols in

(TM=,TM<>,TM>,TM<=,TM<,TM>=)

(a) The following figure shows the comparison example of time.
A

0 Midnight

6:00
4:50:55

B

C

18:00
0 Midnight
N00n
22:47:05
14:08:58

The following table shows the conductive states resulting from performing the
comparison operation of the dates A, B, and C shown above.
Even if the objects to be compared are under the same condition, the comparison
operation results vary depending on the objects selected.
Comparison objects

Comparison condition
A,TM>,TM<=,TM<,TM>=instruction.

7-364

(TM=,TM<>,TM>,TM<=,TM<,TM>=)

Program Example

1

(1) The following program compares the data stored in D0 with the data (hour, minute, and
second) stored in D10, and makes Y33 be conductive status when the data stored in D0
meet the data stored in D10.
[Ladder Mode]

2

[List Mode]
Step

Instruction

3

Device

4
(2) The following program compares the data stored in D0 with the current time data (hour and
minute), and makes Y33 be conductive status when the data stored in D0 do not meet the
current date data, when M0 is turned on.
[Ladder Mode]

6

[List Mode]
Step

Instruction

Device

6
7

(3) The following program compares the data stored in D0 with the data (hour and second)
stored in D10, and makes Y33 be conductive status when the data value stored in D10 is
smaller than the data value stored in D0, when M0 is turned on.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[List Mode]
Step

Instruction

Device

7-365

7.15 Clock instructions
7.15.8 Clock comparison (TM=,TM<>,TM>,TM<=,TM<,TM>=)

(4) The following program compares the data stored in D0 with the current time data (hour), and
makes Y33 be conductive status when the value of the current time data is the data value
stored in D0 or larger.
[Ladder Mode]

8

S(P).DATERD

7.16 Expansion Clock Instructions
7.16.1

Reading expansion clock data (S(P).DATERD)

S(P).DATERD

Ver.
Basic

High
performance

Ver.

Ver.

Process Redundant Universal

The first 5 digits of the serial No. are "07032" or higher.

Command

S.DATERD

S.DATERD

D

SP.DATERD

D

Command

SP.DATERD

D

Setting
Data

: Head number of the devices where the read clock data will be stored (BIN 16 bits)

Internal Devices

D

Bit

R, ZR

Word

J

\

Bit

U

Word

Zn

\G

––

Constants

Other

––

Function
(1) Reads "year, month, day, hour, minute, second, day of the week, and millisecond" from the
clock element of the CPU module, and stores it as BIN value into the device specified by D
or later device.

Clock element

(2) The "year" at

D

D
D
D
D
D
D
D
D

Year
Month
+1
+2
Day
+3 Hour (24-hour clock)
Minute
+4
Second
+5
+6 Day of week
+7 Millisecond

(1980 to 2079)
(1 to 12)
(1 to 31)
(0 to 23)
(0 to 59)
(0 to 59)
(0 to 6)
(0 to 999)

is stored as 4-digit year indication.

(3) The "day of the week" at

D

+6 is stored as 0 to 6 to represent the days Sunday to Saturday.

Day of week

Sunday

Monday

Tuesday

Wednesday

Thursday

Friday

Saturday

Stored data

0

1

2

3

4

5

6

(4) Compensation is made automatically for leap years.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU only.)
(Error code: 4101)

7-366

S(P).DATERD

Program Example

1

(1) The following program outputs the following clock data as BCD values:
Year .................... Y70 to Y7F
Month ................. Y68 to Y6F
Day ..................... Y60 to Y67
Hour.................... Y58 to Y5F
Minute................. Y50 to Y57
Second ............... Y48 to Y4F
Week .................. Y44 to Y47
Millisecond.......... Y38 to Y43

2
3
4

[Ladder Mode]

6
Outputs "Year"
Outputs "Month"

6

Outputs "Day"
Outputs "Hour"

7

Outputs "Minute"
Outputs "Second"

8

Outputs "Day of Week"
Outputs "Millisecond"
7.16 Expansion Clock Instructions
7.16.1 Reading expansion clock data (S(P).DATERD)

[List Mode]
Step

Instruction

Device

[Operation]
BCD

Y7F
2

Clock data
2005, 12, 24

12:57:39 Sunday 530

D0
D1
D2
D3
D4
D5
D6
D7

2005
12
24
12
57
39
0
530
BIN

Y6F
1
Y5F
1
Y4F
3

Y70
0

5

Y68 Y67

Y60

2

4

2

Y58 Y57

Y50

2

7

5

(Year)

(Month, Day)

(Hour, Minute)

Y48 Y47 Y44
9

Y43
5

0

0

(Second, Day of week)

Y38
3

0

(Millisecond)

7-367

S(P).DATERD

Caution
(1) This instruction reads clock data and stores those to a specified device even if a wrong clock
data is set to the CPU module. (example: Feb. 30th)
When setting clock data with the DATEWR instruction or GX Developer, make sure to set a
correct data.
(2) Time error of reading a clock data of millisecond is a maximum of 2ms. (Difference between
the data memorized by clock element inside of the CPU module and the data read by this
function.)
(3) Specifying digit for the bit device can be used only when the following conditions (a) and (b)
are met.
(a) Digit specification: K4
(b) Head of device: multiple of 16
When the above conditions (a) and (b) are not met, INSTRCT CODE ERR.
(error code: 4004) will occur.

7-368

S(P).DATE+

7.16.2

Expansion clock data addition operation (S(P).DATE+)

1
S(P).DATE+

Ver.
Basic

Ver.

High
performance

Ver.

Process Redundant Universal

The first 5 digits of the serial No. are "07032" or higher.

2
3

Command

S.DATE+

S.DATE+

S1

S2

D

SP.DATE+

S1

S2

D

4

Command

SP.DATE+

Setting
Data

6

S1

: Head number of the devices where the clock data to be adjusted by addition is stored (BIN 16 bits)

S2

: Head number of the devices where the time data to be added for adjustment is stored (BIN 16 bits)

D

: Head number of the devices where the result of addition of clock (time) data will be stored (BIN 16 bits)

Internal Devices
Bit

Word

R, ZR

J

\

Bit

Word

U

Zn

\G

S1

––

––

S2

––

––

D

––

––

Constants

6

Other

7
8

Function

S1
S1 +1
S1 +2
S1 +3
S1 +4

Hour
Minute
Second
-Millisecond

Setting data
(0 to 23)
(0 to 59)
(0 to 59) +

S2
S2 +1
S2 +2
S2 +3
S2 +4

(0 to 999)

Hour
Minute
Second
-Millisecond

Setting data
(0 to 23)
(0 to 59)
(0 to 59)

D
D
D
D
D

(0 to 999)

+1
+2
+3
+4

S1

, and stores the

Hour
Minute
Second
-Millisecond

Setting data
(0 to 23)
(0 to 59)
(0 to 59)
(0 to 999)

For example, adding the time 7:48:10:500 to 6:32:40:875 would result in the following
operation:
S1
S1 +1
S1 +2

Hour: 6

Minute: 32
Second: 40
S1 +3
-S1 +4 Millisecond: 875

S2

+

S2 +1
S2 +2

Hour: 7

Minute: 48
Second: 10
S2 +3
-S2 +4 Millisecond: 500

D
D
D
D
D

Hour: 14
+1 Minute: 20
+2 Second: 51
+3
-+4 Millisecond: 375

7-369

7.16 Expansion Clock Instructions
7.16.2 Expansion clock data addition operation (S(P).DATE+)

(1) Adds the time data designated by S2 to the clock data designated by
result into the area starting from the device designated by D .

S(P).DATE+

(2) If the results of the addition of time exceed 24 hours, 24 hours will be subtracted from the
sum to make the final operation result.
For example, when the time 20:20:20:500 is added to 14:20:30:875, the result is not
34:40:51:375, but 10:40:51:375.
Hour: 14

S1

S2

S1 +1
S1 +2

Minute: 20
Second: 30
S1 +3
-S1 +4 Millisecond: 875

Hour: 20

S2 +1
S2 +2

Minute: 20
Second: 20
S2 +3
-S2 +4 Millisecond: 500

+

D
D
D
D
D

Hour: 10
+1 Minute: 40
+2 Second: 51
+3
-+4 Millisecond: 375

Devices, S1 +3, S2 +3, and D +3 are not used for operation.
A clock data read by the S(P).DATERD instruction can be directly added.
D
D
D
D
D

Hour
Minute
+1
Second
+2
+3 Day of week
+4 Millisecond

When the clock data is read by the S(P).DATERD instruction,
day of week is inserted between "second" and "millisecond".
If the S(P).DATE+ instruction is used to read the clock data,
the data can be directly used for addition since it does not perform
the calculation for the day of a week.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The data set by

S1

and

S2

is outside the range. (See Function (1).)

(Error code: 4100)

• The device specified by S1 , S2 or D exceeds the range of the corresponding device.
(For the Universal model QCPU only.)
(Error code: 4101)

Caution
(1) Specifying digit for the bit device can be used only when the following conditions (a) and (b)
are met.
(a) Digit specification: K4
(b) Head of device: multiple of 16
When the above conditions (a) and (b) are not met, INSTRCT CODE ERR.
(error code:4004) will occur.

7-370

S(P).DATE+

Program Example

1

(1) The following program adds 1 hour to the clock data read from the clock element, and stores
the results into the area starting from D100 when X20 is turned ON.
[Ladder Mode]
Reads out the clock element
data to D0 or later.

2
3

Sets the time to D10 or later.

4
6
6

[List Mode]
Step

Instruction

7

Device

8

7.16 Expansion Clock Instructions
7.16.2 Expansion clock data addition operation (S(P).DATE+)

[Operation]
• Time data read operation by the SP.DATERD instruction
Clock element

D0
D1
D2
D3
D4
D5
D6

05
5
17
10
23
41
2
100

Year
Month
Day
Hour
Minute
Time data
Second
Day of week
Millisecond Time data

• Addition by the SP.DATE+ instruction
D3 Hour: 10
D4 Minute: 23
D5 Second: 41
D6 2 (Tuesday)
D7 Millisecond: 100

+

Hour: 1
D10
D11 Minute: 0
D12 Second: 0
-D13

D100 Hour: 11
D101 Minute: 23
D102 Second: 41
-D103

D14 Millisecond: 0

D104 Millisecond: 100

7-371

S(P).DATE-

7.16.3

Expansion clock data subtraction operation (S(P).DATE-)

S(P).DATE-

Ver.
Basic

Ver.

High
performance

Ver.

Process Redundant Universal

The first 5 digits of the serial No. are "07032" or higher.

Command

S.DATE-

S.DATE-

S1

S2

D

SP.DATE-

S1

S2

D

Command

SP.DATE-

Setting
Data

S1

: Head number of the devices where the clock time data to be adjusted by substraction is stored (BIN 16 bits)

S2

: Head number of the devices where time data to be subtracted for adjustment is stored (BIN 16 bits)

D

: Head number of the devices where the result of subtraction of clock (time) data will be stored (BIN 16 bits)

Internal Devices
Bit

Word

R, ZR

J

\

Bit

Word

U

Zn

\G

S1

––

––

S2

––

––

D

––

––

Constants

Other

Function
(1) Subtracts the time data designated by S2 from the clock data designated by
the result into the area starting from the device designated by D .
S1
S1 +1
S1 +2
S1 +3
S1 +4

Hour
Minute
Second
-Millisecond

Setting data
(0 to 23)
(0 to 59)
(0 to 59) -

S2
S2 +1
S2 +2
S2 +3
S2 +4

(0 to 999)

Hour
Minute
Second
-Millisecond

Setting data
(0 to 23)
(0 to 59)
(0 to 59)

D
D
D
D
D

(0 to 999)

+1
+2
+3
+4

Hour
Minute
Second
-Millisecond

S1

, and stores

Setting data
(0 to 23)
(0 to 59)
(0 to 59)
(0 to 999)

For example, when the clock time 3:50:10:500 is subtracted from the clock time
10:40:20:875, the operation is performed as follows:
S1
S1 +1
S1 +2

Hour: 10

Minute: 40
Second: 20
S1 +3
-S1 +4 Millisecond: 875

7-372

S2

-

S2 +1
S2 +2

Hour: 3

Minute: 50
Second: 10
S2 +3
-S2 +4 Millisecond: 500

D
D
D
D
D

Hour: 6
+1 Minute: 50
+2 Second: 10
+3
-+4 Millisecond: 375

S(P).DATE-

(2) If the subtraction results in a negative number, 24 will be added to the result to make a final
operation result.
For example, when the clock time 10:42:12:500 is subtracted from 4:50:32:875, the result is
not 6:8:20:375, but 18:8:20:375.
S1

Hour: 4

Hour: 10

S2

S1 +1
S1 +2

Minute: 50
Second: 32
S1 +3
-S1 +4 Millisecond: 875

-

S2 +1
S2 +2

Minute: 42
Second: 12
S2 +3
-S2 +4 Millisecond: 500

D
D
D
D
D

Hour: 18
+1 Minute: 8
+2 Second: 20
+3
-+4 Millisecond: 375

2
3
4

Devices, S1 +3, S2 +3, and D +3 are not used for operation.
A clock data read by S(P).DATERD instruction can be directly subtracted.
D
D
D
D
D

1

Hour
Minute
+1
Second
+2
+3 Day of week
+4 Millisecond

6
6

When the clock data is read by the S(P).DATERD instruction,
day of week is inserted between "second" and "millisecond".

7

If the S(P).DATE- instruction is used to read the clock data,
the data can be directly used for subtraction since it does not
perform the calculation for the day of the week.

8

Operation Error

• The data set by

S1

and

S2

is outside the range. (See Function (1).)

(Error code: 4100)

• The device specified by S1 , S2 or D exceeds the range of the corresponding device.
(For the Universal model QCPU only.)
(Error code: 4101)

Caution
(1) Specifying digit for the bit device can be used only when the following conditions (a) and (b)
are met.
(a) Digit specification: K4
(b) Head of device: multiple of 16
When the above conditions (a) and (b) are not met, INSTRCT CODE ERR.
(error code:4004) will occur.

7-373

7.16 Expansion Clock Instructions
7.16.3 Expansion clock data subtraction operation (S(P).DATE-)

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.

S(P).DATE-

Program Example
(1) The following program subtracts the time data stored in the area starting from D10 from the
clock data read from the clock element when X1C is turned ON, and stores the result into
the area starting from D100.
[Ladder Mode]
Reads out the clock element
data to D0 or later.

Sets the time to D10 or later.

[List Mode]
Step

Instruction

Device

[Operation]
• Time data read operation by the SP.DATERD instruction
Clock element

D0
D1
D2
D3
D4
D5
D6
D7

05
2
23
8
42
1
3
997

Year
Month
Day
Hour
Minute
Time data
Second
Day of week
Millisecond Time data

• Subtraction by the SP.DATE- instruction
D3 Hour: 8
D4 Minute: 42
D5 Second: 1
D6 3 (Wednesday)
D7 Millisecond: 997

-

D10 Hour: 10
D11 Minute: 40
D12 Second: 10
-D13

D100 Hour: 22
D101 Minute: 1
D102 Second: 51
-D103

D14 Millisecond: 500

D104 Millisecond: 497

8:42:1:997 - 10:40:10:500

-2:1:51:497
Adds 24 to this value

22:1:51:497

7-374

7.17 Program control instructions
1
(1) Processing when the execution type is converted with the program control instruction is as
follows.

Executed Instruction

3

Execution type before change
PSCAN
Scan execution type

PSTOP

No change-remains

POFF

Stand-by type

that.
No change-remains
stand-by type

Low speed execution
type execution is
Low speed execution type

from the next scan after

Becomes scan
execution type.

stopped, becomes scan
execution type from the
next scan.
(Execution from step 0)

4

next scan.
Becomes stand-by type. Becomes stand-by type

Initial execution type

PLOW

Output turned OFF in

scan type execution.

Becomes low speed
execution type.

6

Ignored
Low speed execution

Low speed execution

type execution is

type execution is

stopped, and output is

stopped, becomes

turned OFF in the next

stand-by type from next

scan. Becomes

scan.

stand-by type from the

6
No change -remains low
speed execution type.

Fixed scan execution type

execution type.

7

next scan after that.
Output turned OFF in

Becomes scan

2

next scan.
Becomes stand-by type. Becomes stand-by type
from the next scan after

8

Becomes low speed
execution type.

that.

7-375

7.17 Program control instructions

Once the fixed scan execution type program is changed to another execution
type, it cannot be returned to the fixed scan execution type.

(2) As program execution type conversions by PSCAN and PSTOP instructions occur at the
END processing, such conversions are impossible during program execution.
When different execution types have been set for the same program in the same scan, the
execution type will be that specified by the execution switching command that was executed
last.
END processing
Execution
program name

GHI

"ABC"

END processing
GHI

GHI

PSTO executes "ABC"
PSCAN executes "DEF"

*1 DEF

END processing
*1

GHI

Converts "DEF" into the scan execution
type program and "ABC" to the stand-by
type program

*1: The order of "GHI" and "DEF" program execution is determined by the program settings parameters.

Switching from the fixed scan execution type program to the execution type program is
performed in the following timing.
(a) For the Universal model QCPU
The execution type is changed when the execution of the fixed scan execution type is
stopped at the END processing after the program control instruction execution.
(b) For the CPU modules other than the Universal model QCPU
The execution of the fixed scan execution type is stopped at the execution of the
program control instruction, and the execution type is changed at the END processing.
(3) When the POFF instruction is executed, the output is turned OFF at the next scan, and the
execution type will be the stand-by type at the second next scan and later.
If executed prior to the output OFF processing, the program control instruction is ignored.

7-376

PSTOP(P)

7.17.1

Program standby instruction (PSTOP(P))

1
PSTOP(P)

Basic

High
performance

Process Redundant Universal

3

Command

PSTOP

PSTOP

S

PSTOPP

S

4

Command

PSTOPP

S

Setting
Data
S

: Character string for the name of the program file to be set in the stand-by status or head number of the
devices where the character string data is stored (character string)

Internal Devices
Bit

Word

R, ZR

2

J
Bit

\

U

Word

––

Constants
$

Zn

\G

––

Other

6
6

––

7

Function
(1) Places the file name program stored in the device designated by

S

in the stand-by status.

8

(2) Only the programs stored in the drive No. 0 (program memory/internal RAM) can be set as
the stand-by type.
(3) The specified program is placed in the stand-by status when END processing is performed.

(5) It is not necessary to designate the extension (.QPG) with the file name.
(Only .QPG files will be acted on.)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The program with the file name specified by

S

• The program type of the file name specified by
• The file name storage destination device of
device.

S

does not exist.
S

(Error code: 2410)

is the SFC program. (Error code: 2412)

exceeds the range of the corresponding
(Error code: 4101)

Program Example
(1) The following program places the program with the file name ABC in the stand-by status
when X0 goes ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

7-377

7.17 Program control instructions
7.17.1 Program standby instruction (PSTOP(P))

(4) This instruction will be given priority even in cases when a program execution type has been
designated in the parameters.

POFF(P)

7.17.2

Program output OFF standby instruction (POFF(P))

POFF(P)

Basic

High
performance

Process Redundant Universal

Command

POFF

POFF

S

POFFP

S

Command

POFFP

S

Setting
Data
S

: File name of the program to be set in the standby status by turning OFF the output, or the device where the
file name is stored (character string)

Internal Devices
Bit

Word

R, ZR

J
Bit

\
Word

––

U

\G

Zn

Constants
$

––

Other
––

Function
(1) Changes the execution type of the program with the file name stored in the device
designated by

S

.

• Scan execution type:

Turns OFF outputs at the next scan (Non-execution
processing). Programs are set as the stand-by type after
the subsequent scan.

• Low speed execution type: Stops the execution of the low speed execution type
program and turns OFF outputs at the next scan. Programs
are set as the stand-by type after the subsequent scan.
(2) Only the programs stored in the drive No. 0 (program memory) can be set as the stand-by
type.
(3) This instruction will be given priority even in cases when a program execution type has been
designated in the parameters.
(4) It is not necessary to designate the extension (.QPG) with the file name.
(Only .QPG files will be acted on.)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The program with the file name specified by

S

does not exist.
(Error code: 2410)

• The file name storage destination device of
device.

7-378

S

exceeds the range of the corresponding
(Error code: 4101)

POFF(P)

Remark
1. Non-execution processing is identical to the processing that is conducted when
the condition contacts for the individual coil instructions are in the OFF state.
The operation results for the individual coil instructions following non-execution
processing will be as follows, regardless of the ON/OFF status of the individual
contacts:
OUT instruction
SET instruction
RST instruction
SFT instruction
Basic instruction
Application instruction
PLS instruction
Pulse generation
instruction ( P)
Current value of low speed/high speed timer
Current value of retentive timer
Current value of counter

...... Forced OFF

1
2
3
4

...... Maintains status

Processing identical to
...... when condition contacts
are OFF
...... 0

6
6

...... Preserves

7

Program Example

8

(1) The following program makes the program with the file name ABC non-executionable and
places it in the standby status when X0 is turned ON.
[Ladder Mode]

[List Mode]
Instruction

7.17 Program control instructions
7.17.2 Program output OFF standby instruction (POFF(P))

Step

Device

7-379

PSCAN(P)

7.17.3

Program scan execution registration instruction (PSCAN(P))

PSCAN(P)

Basic

High
performance

Process Redundant Universal

Command

PSCAN

PSCAN

S

PSCANP

S

Command

PSCANP

S

Setting
Data
S

: File name of the program to be set as a scan execution type, or head number of the devices where the file
name is stored (character string)

Internal Devices
Bit

Word

J

R, ZR

\

Bit

Word

––

U

Constants
$

Zn

\G

––

Other
––

Function
(1) Sets the program whose file name is being stored at the device designated by
execution type.

S

in the scan

(2) Only the programs stored in the drive No. 0 (program memory/internal RAM) can be set as
the scan execution type.
(3) Designated programs assume the scan execution type with END processing.
Example
When programs A, B, and C exist and program A performs "PSCAN" of program D.
A

B

C

END

A

B

C

END

Program D
is executed

Execution of
PSCAN
Scan

D

Scan

(4) This instruction will be given priority even in cases when a program execution type has been
designated in the parameters.
(5) It is not necessary to designate the extension (.QPG) with the file name.
(Only .QPG files will be acted on.)

7-380

PSCAN(P)

Operation Error

1

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The program with the file name specified by

S

does not exist.

2

(Error code: 2410)
• The file name storage destination device of
device.

S

exceeds the range of the corresponding
(Error code: 4101)

• The specified file name is the SFC program, and the SFC program for the other file name
has been already started. (Dual activation error of the SFC program)
(For the Universal model QCPU)
(Error code: 4131)
(For the High Performance model QCPU, Process CPU, Redundant CPU)
(Error code: 2504)

Program Example

4
6
6

(1) The following program sets the program with file name ABC as scan execution type when
X0 is turned ON.
[Ladder Mode]

3

[List Mode]
Step

Instruction

7

Device

8

7.17 Program control instructions
7.17.3 Program scan execution registration instruction (PSCAN(P))

7-381

PLOW(P)

7.17.4

Program low speed execution registration instruction
(PLOW(P))

PLOW(P)

Basic

High
performance

Process Redundant Universal

Command

PLOW

PLOW

S

PLOWP

S

Command

PLOWP

S

Setting
Data
S

: File name of the program to be set as a low speed execution type, or head number of the devices where the
file name is stored (character string)

Internal Devices
Bit

R, ZR

Word

J
Bit

\

U

Word

––

Zn

\G

Constants
$

Other

––

––

Function
(1) Sets the program whose file name is being stored at the device designated by
low-speed execution type.

S

in

(2) Only the programs stored in the drive No. 0 (program memory/internal RAM) can be set as
the low speed execution type.
(3) Designated programs assume the low speed execution type with END processing.
Example
When programs A, B, and C exist and program A performs "PLOW" of program D.
(Assume that the constant scan has been set.)
Waiting for constant
A

B

C

END

A

B

C

Execution of
PLOW
Scan

END

D

Program D
is executed
Scan

(4) This instruction will be given priority even in cases when a program execution type has been
designated in the parameters.
(5) It is not necessary to designate the extension (.QPG) with the file name.
(Only .QPG files will be acted on.)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The program with the designated file name does not exist.

(Error code: 2410)

• There is a CHK instruction contained within the program whose file name has been
designated.
(Error code: 4235)

7-382

PLOW(P)

Program Example

1

(1) The following program sets the program with file name ABC as low-speed execution type
when X0 is turned ON.
[Ladder Mode]

[List Mode]
Step

Instruction

2

Device

3
4
6
6
7
8

7.17 Program control instructions
7.17.4 Program low speed execution registration instruction (PLOW(P))

7-383

PCHK

7.17.5

Program execution status check instruction (PCHK)

PCHK

Basic

LDPCHK

High
performance

Process Redundant Universal

File name

PCHK
Command

ANDPCHK

PCHK

File name

Command

ORPCHK
File name

PCHK

S

Setting
Data

: File name of the program whose execution status will be checked (character string)

Internal Devices
Bit

Word

R, ZR

J
Bit

\
Word

U

\G

Zn

Constants
$

––

S

Other
––

Function
(1) Checks whether the program of the specified file name is in execution or not
(non-execution).
(2) The instruction is in conduction when the program of the specified file name is in execution,
and the instruction is in non-conduction when the program is in non-execution.
(3) Specify the file name without an extension (.QPG).
For example, specify "ABC" when the file name is ABC.QPG.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The program with the designated file name does not exist.

(Error code: 2410)

Program Example
(1) Program that keeps Y10 ON when the program file "ABC.QPG" is being executed.
PCHK

"ABC"
Execution
Non-execution

7-384

Y10

PCHK

Remark
Non-execution indicates that the program execution type is a stand-by type.
Execution indicates that the program execution type is a scan execution type
(including during output OFF (during non-execution processing)), low speed
execution type or fixed scan execution type.

1
2
3

The PCHK instruction is in conduction when the program of the specified file
name (target program) is in execution, and the instruction is in non-conduction
when the program is in non-execution.
When the target program is set to non-execution (stand-by type) with the POFF
instruction, the PCHK instruction is in conduction while the non-execution
processing of the target program is being performed.
At the END processing of the scan where the non-execution processing is
completed, the target program is put into non-execution (stand-by type), and the
PCHK instruction is brought into non-conduction.
Therefore, note that if the PCHK instruction is executed for the program where the
non-execution processing has been completed by the POFF instruction, the
PCHK instruction may be brought into conduction.
The following chart shows the operation performed when program A executes the
POFF instruction of program B and program C executes the PCHK instruction of
program B with the programs being executed in order of program A, program B
and program C.

END processing
Scan
execution

Scan
execution

Program A

Scan
execution

Scan
execution

Scan
execution

Scan
execution

Program B

END processing END processing

Scan
execution

Scan
execution

Scan
execution

Program C
POFF instruction is
executed in program B

Non-execution processing
is performed.

Continuity

PCHK B
Non-continuity

7-385

6
6
7
8

7.17 Program control instructions
7.17.5 Program execution status check instruction (PCHK)

Program B execution type change
(Scan execution type to stand-by type)

4

WDT(P)

7.18 Other instructions
7.18.1

Resetting watchdog timer (WDT(P))

WDT(P)

Basic

High
performance

Process Redundant Universal

Command

WDT

WDT
Command

WDTP

WDTP

Setting
Data

Internal Devices
Bit

Word

J

R, ZR

Bit

\

U

Word

––

\G

Zn

Constants

Other

––

Function
(1) Resets watchdog timer during the execution of a sequence program.
(2) Used in cases where the scan time exceeds the value set for the watchdog timer due to
prevailing conditions.
If the scan time exceeds the watchdog timer setting value on every scan, change the
watchdog timer settings at the peripheral device parameter settings.
(3) Make sure that the setting for t1 from step 0 to the WDT instruction and the setting for t2
from the WDT instruction to the END (FEND) instruction do not exceed the setting value of
the watchdog timer.
Step 0

END (FEND)

WDT

T1

T2

(4) The WDT instruction can be used two or more times during a single scan, but care should be
taken in such cases, because of the time required until the output goes OFF during the
generation of an error.
(5) Scan time values stored at the special register will not be cleared even if the WDT or WDTP
instruction is executed.
Accordingly, there are times when the value for the scan time for the special register is
greater than the value of the watchdog timer set at the parameters.

7-386

WDT(P)

Operation Error

1

(1) There are no operation errors associated with the WDT(P) instruction.

2

Program Example
(1) The following program has a watchdog timer setting of 200 ms, when due to the execution
conditions program execution requires 300 ms from step 0 to the END (FEND) instruction.

4

[When WDT instruction is used]
Program where
scan time is
300 ms.

Program where
scan time is
150 ms.

6

WDT
END

3

Program where
scan time is
150 ms.

6

END

7
8

7.18 Other instructions
7.18.1 Resetting watchdog timer (WDT(P))

7-387

DUTY

7.18.2

Timing pulse generation (DUTY)

DUTY

Basic

High
performance

Process Redundant Universal

Command

DUTY

DUTY

n1

n2

D

n1 : Number of scans for ON (BIN 16 bits)
n2 : Number of scans for OFF (BIN 16 bits)
: User timing clock (SM420 to SM424, SM430 to M434) (bits)

D

Setting
Data

Internal Devices
Bit

Word

J

R, ZR

\

Bit

U

Word

\G

Constants
K, H

Zn

n1

––

n2
D

Other

––
*1

––

––
*1: Only SM420 to SM424, SM430 to SM434 can be used.

Function
(1) Turns the user timing clock (SM420 to SM424, SM430 to M434), designated by D , ON for
the duration equivalent to the number of scans specified by n1, and OFF for the duration
equivalent to the number of scans specified by n2.
ON
SM420 to SM424 OFF
SM430 to SM434

n1 scans

n2 scans

(2) Scan execution type programs use SM420 to SM424, and low speed execution type
programs use SM430 to SM434.
(3) The following will take place if both n1 and n2 have been set for 0:
(a) n1 0, n2 0

SM420 to SM424 and SM430 to SM434 will stay OFF.

(b) n1 0, n2 0

SM420 to SM424 and SM430 to SM434 will stay ON.

(4) The data designated by n1, n2, and D is registered with the system when the DUTY
instruction is executed, and the timing pulse is turned ON and OFF by END processing.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The device designated by

D

is not from SM420 to SM424 or SM430 to SM434.
(Error code: 4101)

• The values of n1 and n2 are less than 0.

7-388

(Error code: 4100)

DUTY

Program Example

1

(1) The following program turns SM420 ON for 1 scan, and OFF for 3 scans if X0 is ON.
[Ladder Mode]

[List Mode]
Step

2
Instruction

Device

3
4

[Operation]
ON
X0

OFF

6

ON
SM420

OFF
1 scan

3 scans

6
7
8

7.18 Other instructions
7.18.2 Timing pulse generation (DUTY)

7-389

TIMCHK

7.18.3

Time check instruction (TIMCHK)

TIMCHK

Ver.
Basic

High
performance

Process Redundant Universal

Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.

command

TIMCHK

TIMCHK

Setting
Data

S1

S1

: Device where the measured current value will be stored (BIN 16 bits)

S2

: Device where the set value of measurement is stored (BIN 16 bits)

D

: Device to be turned ON at time-out (bits)

Internal Devices
Bit

R, ZR

Word

J
Bit

\

U

Word

\G

––

S1

S2

Zn

D

Constants
K, H

––

Other
––
––

S2

––

D

––

––

Function
(1) Measures the ON time of the device used as a condition, and turns ON the device specified
by

S2

by

D

if the condition device remains ON for longer than the time set to the device specified
.

(2) The current value of the device specified by S1 is cleared to 0 and the device specified by
is turned OFF at the leading edge of the execution command.
The current value of the device designated by
designated by

D

S1

D

and the ON status of the device

are retained after the execution command turns OFF.

(3) Set the set value of measurement in units of 100ms.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• The device that cannot be specified has been specified.

(Error code: 4100)

Program Example
(1) Program where the ON time of X0 is set to 5s, the current value storage device to D0, and
the device that will turn ON at time-out to Y10.
[Ladder Mode]

[List Mode]
Step

7-390

Instruction

Device

ZRRDB(P)

7.18.4

Direct 1-byte read from file register (ZRRDB(P))

1
ZRRDB(P)

Basic

High
performance

Process Redundant Universal

2
3

Command

ZRRDB

ZRRDB

n

D

ZRRDBP

n

D

4

Command

ZRRDBP

6

n : Serial byte number for the file register to be read (BIN 32 bits)
D

Setting
Data

: Number of the device where the read data will be stored (BIN 16 bits)

Internal Devices
Bit

Word

J

R, ZR

\

Bit

U

Word

Constants
K, H

Zn

\G

n

Other

6

––
––

D

––

7
8

Function
(1) Reads the serial byte number designated by n that does not signify a block number, and
stores at the lower 8 bits of the device designated by

.

will become 00H.

D

File register
ZR0
ZR32767
ZR32768

Area for
block No. 0
Area for
block No. 1

b15
D

n Serial byte number
ZR65535
ZR65536

b8B7

B0

00H
Read-out contents

Area for
block No. 2

(2) The correspondence between file register numbers and serial byte numbers is as indicated
below:
b15
b8b7
b0
Serial byte No. 0
ZR0 Serial byte No. 1
Serial byte No. 2
ZR1 Serial byte No. 3
Serial byte No. 4
ZR2 Serial byte No. 5
ZR2500 Serial byte No. 5001
ZR2501 Serial byte No. 5003
ZR2502 Serial byte No. 5005
ZR2503 Serial byte No. 5007

Serial byte No. 5000
Serial byte No. 5002
Serial byte No. 5004
Serial byte No. 5006

Data when an even
number is designated
Data when an odd
number is designated

7-391

7.18 Other instructions
7.18.4 Direct 1-byte read from file register (ZRRDB(P))

The upper 8 bits designated by

D

ZRRDB(P)

(a) If the value of n has been designated as 23560, the data at the lower 8 bits of ZR11780
will be read.

n

23560

Read destination
b0
b15
b8 b7
designation
ZR11780
43H
21H

b8 b7

b15
D

00H

b0
21H

Data is stored

(b) If the value of n has been designated as 43257, the data at the upper 8 bits of ZR21628
will be read.

n

43257

Read destination
b15
b8 b7
b0
designation
93H
42H
ZR21628

b8 b7

b15
D

b0
93H

00H

Data is stored

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• A device number (serial byte number) that exceeds the range of allowable designations
has been designated.
(Error code: 4101)

Program Example
(1) The following program reads the lower bits of ZR16000 and the upper bits of R16003, and
stores results at D100 and D101 when X0 is ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
Serial byte No. 32000
(Lower bits of R16000)
Serial byte No. 32007
(Upper bits of R16003)

7-392

b15
R16000
R16001
R16002
R16003

b8 b7
8FH
42H
12H
93H

b0
25H
32H
34H
00H

b15
D100
D101

b8 b7
00H
00H

b0
25H
93H

ZRWRB(P)

7.18.5

File register direct 1-byte write (ZRWRB(P))

1
ZRWRB(P)

Basic

High
performance

Process Redundant Universal

3

Command

ZRWRB

ZRWRB

n

S

ZRWRBP

n

S

4

Command

ZRWRBP

6

n : Serial byte number for the file register to be written (BIN 32 bits)
D

Setting
Data

2

: Number of the device where the data to be written is stored (BIN 16 bits)

Internal Devices
Bit

Word

R, ZR

J

\

Bit

Word

U

Zn

\G

Constants
K, H

Other

n

––

S

––

Function

6
7
8

(1) Writes the lower bits of data stored in the device designated by S that does not signify a
block number to the file register of the serial byte number designated by n.
S

File register
ZR0

n Serial byte number

ZR32767
ZR32768
Write destination
designation

Area for
block No. 0
Area for
block No. 1

Writing the data
S

ZR65535
ZR65536

b15
b8b7
Ignored

b0

Contents to
be written

Area for
block No. 2

(2) The correspondence between file register numbers and serial byte numbers is as indicated
below:
b15
b8b7
b0
Serial byte No. 0
ZR0 Serial byte No. 1
Serial byte No. 2
ZR1 Serial byte No. 3
Serial byte No. 4
ZR2 Serial byte No. 5
ZR2500 Serial byte No. 5001
ZR2501 Serial byte No. 5003
ZR2502 Serial byte No. 5005
ZR2503 Serial byte No. 5007

Serial byte No. 5000
Serial byte No. 5002
Serial byte No. 5004
Serial byte No. 5006

Storage destination
when an even number is designated
Storage destination
when an odd number is designated

7-393

7.18 Other instructions
7.18.5 File register direct 1-byte write (ZRWRB(P))

The upper 8 bits of data in the device designated by are ignored.

ZRWRB(P)

If n 12340 is specified, the data will be written to the lower 8 bits of ZR11170.

n

Write destination
b0
b15
b8 b7
designation
43H
21H
ZR11170

12340

b15

b8 b7
43H

S

b15
b8 b7
b0
54H
Ignored

b0
54H

If n 43257 is specified, the data will be written to the upper 8 bits of ZR21628.

n

43257

Write destination
b15
b8 b7
b0
designation
ZR21628
12H
50H

b15

b8 b7

S

b15
b8 b7
b0
43H
Ignored

b0
50H

43H

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error
code is stored into SD0.
• A device number (serial byte number) that exceeds the range of allowable designations
has been designated.
(Error code: 4101)

Program Example
(1) The following program writes the data at the lower bits of D100 and D101 to the lower bits of
R16000 and the upper bits of R16003 when X0 is turned ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

[Operation]
Serial byte No. 32000
(Lower bits of R16000)
Serial byte No. 32007
(Upper bits of R16003)

b8 b7

b15
R16000
R16001
R16002
R16003

54H
4AH
ABH
99H

b15
R16000
R16001
R16002
R16003

7-394

b0

b8 b7
54H
4AH
ABH
01H

D100

59H
BAH
80H
77H

b15
b8 b7
b0
D101 Ignored
01H

b0
10H
BAH
80H
77H

b15
b8 b7
b0
10H
Ignored

ADRSET(P)

7.18.6

Indirect address read operations (ADRSET(P))

1
ADRSET(P)

Basic

High
performance

Process Redundant Universal

3

Command

ADRSET

ADRSET

S

D

ADRSETP

S

D

4

Command

ADRSETP

6

S

: Number of the device whose indirect address is read out (Device name)

D

: Number of the device where the indirect address of the device designated by

Internal Devices

Setting
Data

Bit

Word

2

J

R, ZR

\

Bit

U

Word

S

will be stored (BIN 32 bits)

Zn

\G

S

––

D

––

Constants

Other

6
7
8

Function
(1) Stores the indirect address of the device designated by

ADRSET W100 D100

D

at

D

+1 and

D

.

is used when an indirect device address
7.18 Other instructions
7.18.6 Indirect address read operations (ADRSET(P))

The address stored at the device designated by
is performed by the sequence program.

S

Stores the address of W100 address to D101 and D100.

MOV K1234 @D100

Reads the contents of D100.

Writes 1234 to the address
specified by D100 and D101.
Device area

D0
D1

D100
Address of W100
D101

(2) A bit device designation cannot be made at

S

W100

1234

.

Operation Error
(1) There are no operation errors associated with the ADRSET(P) instruction.
Remark
See Section 3.4 for further information on indirect designations.

7-395

KEY

7.18.7

Numerical key input from keyboard (KEY)

KEY

High
performance

Basic

Process Redundant Universal

Command

KEY

KEY

S

n

S

D1

D2

: Head number of the devices (X) to which a numeral will be input (bits)

n : Number of digits of the numeral to be input (BIN 16 bits)
D1

: Head number of the devices where the input numeral will be stored (BIN 16 bits)

D2

: Number of the bit device to turn ON at the completion of input (bits)

Internal Devices

Setting
Data

Bit

\

Bit

––

(Only X)

S

J

R, ZR

Word

U

Word

\G

––

Constants
K, H

Zn
––

n

Other
––
––

––

D1

––

D2

––

––

––

––

Function
(1) Fetches ASCII data from the 8 points of input (X) designated by S , converts it to
hexadecimal values and stores the result in the area starting from the device designated by
D1

.
n

Designation of
the number of
digits to be input

b12 b11
b8b7
b4 b3
b0
Number of digits that are input
5 digits 6 digits 7 digits 8 digits
2 digits 3 digits 4 digits
1 digit

b15
D1
D1 +1
D1 +2

Input module
S
S
S
S
S
S
S
S
S

+1
+2
+3
+4
+5
+6
+7
+8

"0" (30H) to "9" (39H)
"A" (41H) to "F" (46H)
Strobe signal

For example, in a case where the number of digits (n) has been set at 5, and the values "31",
"33", "35", "37" and "39" have been input through X10 to X18 of the input module, the
following will take place:
Number of digits
of input data D0

b15
D10
D11
D12

7-396

b12b11

b8 b7

5

b4 b3

b0

5
3H
0H

5H
0H

7H
0H

9H
1H

Input module
X10
X11
X12
X13
X14
X15
X16
X17
X18

The first input value

" 1
3
5
7
9 "
(31H)(33H)(35H)(37H)(39H)

Strobe signal

KEY

(2) Numerical input to input (X) designated by
S

S

undergoes bit development at

S

through

+7 and is input as the ASCII code corresponding to the numbers.

ASCII code which can be input is from 30H (0) to 39H (9), and from 41H (A) to 46H (F).
(1 H)
(3 H)
b7
b4 b3
b0
"1"(31 H)= 0 0 1 1 0 0 0 1

Input module

2

S
S +1
S +2
S +3
S +4
S +5
S +6
S +7

(3) After ASCII code is input to S to
designated numbers internally.

1

3

S

+7, the strobe signal at

S

+8 goes ON to incorporate the

The strobe signal should be held at its ON or OFF status for more than one scan of the
sequence program.
If this time is less than 1 scan, there will be cases when the data is correctly incorporated.

4
6
6

Execution command
Condition contact for
the execution of KEY
instruction

ON for 1 scan OFF for 1 scan
or longer
or longer

7

Strobe signal ( S +8)
ASCII code input
( S to S +7)

31H

Fetches "1"

32H

Fetches "2"

33H

8

34H

Fetches "3"

Fetches "4"

The KEY instruction cannot be executed if the execution command turns OFF.
(5) The digits for the numbers actually fetched to

D1

will be stored at the device designated by

D1 , and these will be converted to the ASCII codes input at
hexadecimal BIN values, and stored.

D1

+1 and

D1

+2, converted to

Execution command
Condition contact for the
execution of KEY instruction
Strobe signal ( S
ASCII code input
( S to S 7)

8)
31H

D1
1
D1 1 0 0 0 1
D1 2 0 0 0 0

33H

35H

37H

39H

2
0 0 1 3
0 0 0 0

3
0 1 3 5
0 0 0 0

4
1 3 5 7
0 0 0 0

5
3 5 7 9
0 0 0 1

(6) The number of digits that can be designated by n is from 1 to 8.

7-397

7.18 Other instructions
7.18.7 Numerical key input from keyboard (KEY)

(4) Be sure to keep the execution command (condition contact for the KEY instruction) ON until
the specified number of digits has been input.

KEY

(7) Fetching of the input data is completed when any of the inputs shown below has been made.
At the completion, the bit device designated by

D2

is turned ON.

• When the number of digits specified by n has been input
• When the "0DH" code has been input
For example, the operations at the location designated if n

5 will be as indicated below:

Execution command

When the
designated
number of digits
are input

Strobe signal
( S +8)
ASCII code input
( S to S +7)

31H

D1
1
D1 +1 0 0 0 1
D1 +2 0 0 0 0

42H

35H

37H

39H

2
0 0 1 B
0 0 0 0

3
0 1 B 5
0 0 0 0

4
1 B 5 7
0 0 0 0

5
B 5 7 9
0 0 0 1

42H

35H

0DH

2
0 0 1 B
0 0 0 0

3
0 1 B 5
0 0 0 0

3
0 1 B 5
0 0 0 0

Processing
completed ( D2 )

Execution command

When 0DH code
is input

Strobe signal
( S +8)
ASCII code input
( S to S +7)

31H

D1
1
D1 +1 0 0 0 1
D1 +2 0 0 0 0
Processing
completed ( D2 )

If input processing is to be performed a second time, it is necessary to clear the number of
digits input and the input data stored at
program.
If

D1

is not cleared and

D2

D1

, and turn OFF the designated device at the user

not turned OFF, the next input processing cannot be performed.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The device designated by

D

is not an input (X) device.

(Error code: 4100)

• The number of digits designated by n are outside the range of from 1 to 8.
(Error code: 4100)

7-398

KEY

Program Example

1

(1) The following program fetches data of the 5 or fewer digits from the numerical key pad
connected to X20 to X28, and stores it to the area starting from D0 when X0 is turned ON.
[Ladder Mode]

2
3

Clears the previous input data
Sets the number of digits to be input

4
6

Resets the data input completion fag

6
[List Mode]
Step

Instruction

7

Device

8

7.18 Other instructions
7.18.7 Numerical key input from keyboard (KEY)

[Operation]
Input module

" 1

2

3

4

5"

Numerical keypad
(Strobe signal)

X20
X21
X22
X23
X24
X25
X26
X27
X28

b15 b12b11 b8 b7 b4 b3 b0
5
D0
D1 2H 3H 4H 5H
D2 0H 0H 0H 1H

7-399

ZPUSH(P),ZPOP(P)

7.18.8

Batch save or recovery of index register
(ZPUSH(P),ZPOP(P))

ZPUSH(P),ZPOP(P)

Basic

High
performance

Process Redundant Universal

indicates an instruction symbol of ZPUSH/ZPOP.
Command

ZPUSH, ZPOP

D
Command

ZPUSHP, ZPOPP

P

D

Setting
Data
D

: Head number of the devices to/from which contents of an index register are saved/recovered (BIN 16 bits)

Internal Devices
Bit

D

Word

R, ZR

J

\

Bit

Word

––

U

Zn

\G

Constants

Other

––

Function
ZPUSH
(1) Saves the contents of the following index registers to after the device specified by
(When contents of an index register are saved,
increased by 1.)

D

D

.

+ 0 (the number of saves made) is

• Basic model QCPU: Z0 to Z9
• High Performance model QCPU/Process CPU/Redundant CPU:
Z0 to Z15
• Universal model QCPU: Z0 to Z19
(2) The ZPOP instruction is used for data recovery. Nesting is possible within the ZPUSH to
ZPOP cycle.
(3) If nesting has been done, each time the ZPUSH instruction is executed, the field used
following D will be added to, so a field large enough to accommodate the number of times
the instruction will be used should be maintained from the beginning.
(4) The composition of the field used following
• When Basic model QCPU is used
D +0
+1
+2

D

is as shown below:

Number of saves
Z0
Z1
1st nesting
(15 words for the 1st nesting)

+10
+11
+15
+16
+17

7-400

Z9
Reserved by the
system (5 words)
Z0
Z1

2nd nesting

ZPUSH(P),ZPOP(P)
• When using a High Performance model QCPU/Process CPU/Redundant CPU
D +0 Number of saves
+1
Z0
+2
Z1

1
1st nesting
(18 words for the 1st nesting)

+16
+17
+18
+19
+20

2

Z15
Reserved by the
system (2 words)
Z0
Z1

3

2nd nesting

• When Universal model QCPU is used

4

D +0 Number of saves
+1
Z0
+2
Z1

6

1st nesting
(22 words for the 1st nesting)
+20
+21
+22
+23
+24

Z19

6

Reserved by the
system (2 words)
Z0
Z1

2nd nesting

7

ZPOP
(1) Recovers the contents saved in the area starting from the device designated by D to the
index register. (When the saved content is read out to the index register, D + 0 (the number
of saves made) is decreased by 1.)

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The range for the number of points to be used at
exceeds the corresponding device range.
• The contents of

D

D

and later by the ZPUSH(P) instruction
(Error code: 4101)

+ 0 (number of saves made) is 0 in the ZPOP(P) instruction.
(Error code: 4100)

Program Example
(1) The following program saves the contents of the index register to the fields following D0
before calling the subroutine following P0 that uses the index register.
[Ladder Mode]
[List Mode]
Step

Instruction

Device

7-401

7.18 Other instructions
7.18.8 Batch save or recovery of index register (ZPUSH(P),ZPOP(P))

Operation Error

8

UNIRD(P)

7.18.9

Reading Module Information (UNIRD(P))

UNIRD(P)

Basic

High
performance

UNIRD

n1

D

n2

UNIRDP

n1

D

n2

Process Redundant Universal

Command

UNIRD
Command

UNIRDP

n1: Value obtained by dividing the head I/O number of the reading module information source by 16 (0 to FFn)
(BIN 16 bits)
D

: Head number of the devices where the module information will be stored (device name)

n2: The number of points of read data (0 to 256) (BIN 16 bits)
Internal Devices

Setting
Data

Bit

J

R, ZR

Word

\

Bit

Word

n1

U

\G

Zn

Constants
K, H

––
––

D

––

n2

––

Other
––

––

––
––

Function
(1) Reads the module information as much as designated by n2 from the module designated by
n1 (value obtained by dividing the head I/O number by 16), and stores that information into
the area starting from the device designated by

D

.

(Reads the status of the actually installed modules instead of the module type designated by
I/O assignment.)

Remark
The value of n1 is designated by the higher 3 digits of the head I/O number of the
slot from which the module information is read, when it is expressed in 4 digits in
hexadecimal notation.

QY10

QY10

QY41P

Q68ADV

QX10

QX10

QX10

QX10

CPU module

Power supply module

X0000 X0010 X0020 X0030 0040 Y0050 Y0070 Y0080
to
to
to
to
to
to
to
to
X000F X001F X002F X003F 004F Y006F Y007F Y008F

Head input number
is read as K4 or H4

7-402

UNIRD(P)
The details of the module information are described as follows:
Bit

1

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Individual module
information
Bit

Item

b0
b1

Number of I/O points

b2

b4

Module type

b5

b7

000: 16 points

001: 32 points

010: 48 points

011: 64 points

100: 128 points

101: 256 points

110: 512 points

111: 1024 points

3

000: Input module

b3

b6

2

Meaning

001: Output module

4

010: I/O mixed module
011: Intelligent function module

External supply power status
(For future expansion)
Presence/absence of fuse
blown

1: External supply power is connected.

0: External supply power is not connected.

1: Some modules have fuse blown.

0: Normal

Online module replacement 1: Module information on the extension base unit is tried to be read during online
b8

status/
execution from the standby
system

b9
b10
b11

Minor/medium error status
Module error status
Module standby status

b13

Empty

b14

Q module

b15

Module installation status

6

system.*1
0: Other than above
1: Minor/medium error occurred

7

0: Normal

00: No module error

01: Minor error

10: Medium error

11: Serious error

1: Normal

0: Module error occurred

8

Fixed to 0
0: Q series module
1: Modules are installed.

0: No modules are installed.

*1: The Universal model QCPU used in the multiple CPU system is turned ON during the online
module change of the module controlled by the other CPU.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
[High Performance model QCPU, Process CPU, Redundant CPU and Universal model
QCPU]
• When n1 is other than 0 to FFH

(Error code: 4100)

• When n2 is other than 0 to 256

(Error code: 4100)

• When a total of n1 and n2 is equal to or greater than 257
[Q00/Q01CPU]

(Error code: 4100)

• When n1 is other than 0 to 3FH

(Error code: 4100)

• When n2 is other than 0 to 64

(Error code: 4100)

• When a total of n1 and n2 is equal to or greater than 65
[Q00JCPU]

(Error code: 4100)

• When n1 is other than 0 to FH

(Error code: 4100)

• When n2 is other than 0 to 16

(Error code: 4100)

• When n1 and n2 is equal to or greater than 17

(Error code: 4100)

7-403

7.18 Other instructions
7.18.9 Reading Module Information (UNIRD(P))

b12

module change or from the CPU module of standby system in the redundant

6

UNIRD(P)

Program Example
(1) The following program stores the module information at I/O numbers 10H to 20H into the
devices starting from D0 when X10 is turned ON.
Card information

Device

X/Y0 module information

D0

X/Y10 module information

D1

X/Y20 module information
:
X/YFE0 module information
X/YFF0 module information

[Ladder Mode]

[List Mode]
Step

Instruction

Device

Readout result (When read to D0)
(a) 32-point intelligent function module for Q series
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D0

1

0

0

1

0

0

0

0

0

0

0

1

1

0

0

1

32-point module
Intelligent function module
No external power supply connected
No blown-fuse error existing
Execution other than during online module
change or from the standby system
No module error existing
Module ready status
(Empty)
Q series module
Module installed
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

All of these bits turn 0 because information is stored to "D0."
A module is installed as latter 16 points of a 32-point module.

• With a 48- or 64-point module, the same contents as those of D1 are stored in D2 or D2
and D3 respectively.

7-404

UNIRD(P)

(b) 32-point module for A series

1

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1

D0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

For an A series module, all of these bits turn 0 because information is not stored.

2

A series module

3

Module is installed
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

4

All of these bits turn 0 because information is stored to "D0."
A module is installed as latter 16 points of a 32-point module.

• With a 48- or 64-point module, the same contents as those of D1 are stored in D2 or D2
and D3 respectively.

6
6

(c) Empty slot
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

7

0

For an empty slot, all of these bits turn 0.

8

(d) Performing online module replacement
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

(e) Module information on the extension base unit is tried to be read from the standby
system of the redundant system in separate mode.
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

Execution from the standby system
(Module information on the extension base unit is tried
to be read from the standby system of the redundant
system in separate mode.)

7-405

7.18 Other instructions
7.18.9 Reading Module Information (UNIRD(P))

Performing online module replacement

7.18.10

Reading module model name(TYPERD(P))
Ver.
High
performance

Basic

Process Redundant Universal

Universal model QCPU: The serial number (first five digits) is "11043" or later.

Command

TYPERD

TYPERD

n

D

TYPERDP

n

D

Command

TYPERDP
.
Internal device

Setting
data

Bit

Word

*6

R, ZR

J
Bit

\

U

Word

n

––

––

D

––

––

Zn

\G

Constant
K, H

Others
––

––

––

Set Data
Setting data
n

Description
Value obtained by dividing the start I/O number of a module
whose model name is to be read by 16

Execution result of the instruction

D +0
D

D +1 to D +9 Module model name

Setting range
0 to FFH,
3E0 to 3E3H
Within each
device range

Set by

Data type

User

BIN 16 bits

System

BIN 16 bits
Character string

Function
(1) This instruction reads the module information stored in the area starting from the I/O number
specified by "n", and stores it in the area starting from the device specified by
The following 6 modules (Q series only) support the instruction.
• CPU module
• Input module
• Output module
• I/O combined module
• Intelligent function module
• GOT (bus connection)

7-406

D

.

(2) Specify the start I/O number of a module whose model name is to be read by "n" as follows:
• Specify the value obtained by dividing the start I/O number of the target module by 16.

1

Power CPU
supply module QX10 QX10 QX10
module

2

QX10

Q68
ADV

QY41
P

QY10 QY10

3E00H 0000H 0010H 0020H 0030H 0040H 0050H 0070H 0080H

Start I/O number configured in
the I/O assignment setting

3

Specify the start I/O number by K3 or H3.
When the target module is a CPU module itself,
specify the start I/O number by H3E0.

4

• When the target module occupies two slots
The start I/O number to be specified may differ from that of the mounted module.
For the start I/O number, refer to the manual of each module.
Specify the value obtained by dividing the start I/O number of the target module by 16.
Example) QJ71GP21S-SX
Specify a value to which 0010H, start I/O number of the mounted module, is added.

0030H 0040H 0050H 0060H 0070H 0080H

6
7

Power
supply CPU QJ71G P21S-SX Empty Empty Empty Empty Empty Empty
module module

3E00H 0000H 0010H

6

8

Start I/O number configured in
the I/O assignment setting

Specify the start I/O number by K1 or H1.

Power
Q20UDH Q20UDH Q20UDH QY41
supply CPU
CPU
CPU
CPU
P
module module

Q68
ADV

QY41
P

QY10 QY10

3E00H 3E10H 3E20H 3E30H 0000H 0010H 0020H 0030H 0040H

Start I/O number configured in
the I/O assignment setting

Specify the start I/O number by H3E3.

Or, the model name can be read by specifying the start I/O number of a module controlled
by another CPU.

7-407

7.18 Other instructions
7.18.10 Reading module model name(TYPERD(P))

• When the target module is a CPU module in multiple CPU systems
Specify the value obtained by dividing the start I/O number of the target CPU module by
16.

(3)

D +0 and D +1 to D +9 store the execution result of the instruction and module model
name, respectively.

A value stored in

D

is as follows:

(a) When the model name has been written to the target module (example: QJ71GP21-SX)
b15

to

b8 b7

b0

0

D
○+0
D
○+1

Nine words are used.

to

4AH (J)

Stores 0.
Indicates that the model name
that has been written to
the target module is stored.

51H (Q)

D
○+2

31H (1)

37H (7)

D
○+3

50H (P)

47H (G)

D
○+4

31H (1)

32H (2)

D
○+5

53H (S)

2DH (-)

D
○+6

00H

58H (X)

D
○+7

00H

00H

D
○+8

00H

00H

D
○+9

00H

00H

Stores the model name that has been
written to the target module
(stored in ASC II).

Stores the remaining model name and
00H to the 12th to 17th devices and
the 18th device, respectively.

The following table shows the examples of model names stored in
Target module

Stored model name

CPU module

Q06UDEHCPU

Intelligent function module

QJ71GP21-SX

GOT

GOT1000

D

+1 to

D

+9.

(b) When the model name has not been written to the target module (example: QX40)
b15

to

b8 b7

Nine words are used.

to

b0

1

D
○+0

Stores 1.

D
○+1

4AH (N)

49H (I)

D
○+2

55H (U)

50H (P)

D
○+3

5FH (_)

54H (T)

D
○+4

36H (6)

31H (1)

D
○+5

00H

00H

D
○+6

00H

00H

D
○+7

00H

00H

D
○+8

00H

00H

D
○+9

00H

00H

Indicates that the character
string consists of module type and
the number of points is stored.
Stores the character string consists
of module type and the number of points.
(stored in ASC II).

Stores the remaining model name and
00H to the 12th to 17th devices and
the 18th device, respectively.

The following table shows the examples of character strings stored in
Target module
Input module

INPUT_16

Output module

OUTPUT_32

I/O combined module

MIXED_64

Intelligent function module

INTELLIGENT_128

[Character string indicating module type]
• Input module: INPUT
• Output module: OUTPUT
• I/O combined module: MIXED
• Intelligent function module*1: INTELLIGENT
• 1: Includes the QI60 and GOT.

7-408

Stored character string

D

+1 to

D

+9..

[Character string indicating the number of points]
• 16 points:_16

1

• 32 points:_32
• 48 points:_48

2

• 64 points:_64
• 128 points:_128

3

• 256 points:_256
• 512 points:_512
• 1024 points:_1024

4

(c) Others
• The specified slot is empty or the target module is during online module change.
• The specified value (n) is not the start I/O number.
• The specified value (n) is within the allowable setting range, but cannot be set in the
I/O assignment setting screen of the PLC parameter dialog box.
b15

to

to

-1

D
○+0

Nine words are used.

b8 b7

6
6

b0
Stores -1.

00H

00H

D
○+2

00H

00H

D
○+3

00H

00H

D
○+4

00H

00H

D
○+5

00H

00H

D
○+6

00H

00H

D
○+7

00H

00H

D
○+8

00H

00H

D
○+9

00H

00H

7

Indicates that the model
name is not stored.

8

Stores 00H.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
• The target module cannot be communicated due to a failure.
• Devices by 10 words starting from the device specified by

D

• The specified value (n) is except 0 to FFH and 3E0 to 3E3H.

(Error code: 2110)
exceed the device range.
(Error code: 4101)
(Error code: 4101)

7-409

7.18 Other instructions
7.18.10 Reading module model name(TYPERD(P))

D
○+1

Program Example
(1) The following program stores the model name of a module having the start I/O number
0020H in the area starting from the device specified by
[Ladder Mode]

Step

7-410

D

when X0 is turned on.

[List Mode]
Instruction

Device

TRACE,TRACER

7.18.11

Trace Set/Reset (TRACE,TRACER)

1
TRACE,TRACER

Basic

High
performance

Process Redundant Universal

2
3

Command

TRACE

TRACE

4

Command

TRACER

TRACER

6
Setting
Data

Internal Devices
Bit

Word

R, ZR

J
Bit

\

U

Word

––

Zn

\G

Constants

Other

6

––

Function
The sampling trace function collects the specified device data of a CPU module consecutively at
the specified timing.
With the sampling trace function, the traced results obtained through the specified number of
trace operations will be stored in the trace file of the memory card when SM800, SM801, and
SM802 are turned ON.
Trace ends by
number of trace
after trigger

TRACER
Trace reset

Number of trace
after trigger
Total number of traces

SM800
(Preparation for trace)

SM801
(Starting trace)

SM802
(During the execution of trace)

SM803
(Trigger for trace)

SM804
(After the execution of trace
trigger)
SM805
(Completion of trace)

7-411

8

7.18 Other instructions
7.18.11 Trace Set/Reset (TRACE,TRACER)

TRACE
Trace start request Trigger condition enabled

7

TRACE,TRACER

TRACE
(1) The TRACE instruction turns ON SM803, executes sampling by the number of times set for
"After trigger number of times" in the Trace condition settings, latches the data and stops
sampling trace.
(2) The sampling is stopped if SM801 is turned OFF during the trace execution.
(3) After the TRACE instruction is executed and the trace is completed, SM805 is turned ON.
(4) Once the TRACE instruction is executed, the second and the subsequent TRACE
instructions are ignored.
When the TRACER instruction is executed, the TRACE instruction is enabled again.

TRACER
(1) The TRACER instruction resets the TRACE instruction. When the TRACER instruction is
executed, the TRACE instruction is enabled again.
(2) When the TRACER instruction is executed, SM803 to SM805 are turned OFF.
Remark
1. For details of the trace, refer to the QnUCPU User's Manual (Function
Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's
Manual (Function Explanation, Program Fundamentals).
2. For trace execution with GX Developer, refer to the GX Developer Operating
Manual.

Operation Error
(1) There are no operation errors associated with the TRACE or TRACER instruction.

Program Example
(1) The following program executes the TRACE instruction when X0 is turned ON, and resets
the TRACE instruction with the TRACER instruction when X1 is turned ON.
[Ladder Mode]

[List Mode]
Step

7-412

Instruction

Device

SP.FWRITE

7.18.12

Writing Data to Designated File (SP.FWRITE)

1
SP.FWRITE

High
performance

Basic

Process Redundant Universal

2
3

Command

SP.FWRITE

U0

SP.FWRITE

S0

D0

S1

S2

D1

4
Setting
Data

Internal Devices
Bit

R, ZR

Word

J
Bit

\
Word

U

Zn

\G

Constants
K, H

––

S0

$

Other

––

––

D0

––

––

––

––

––

S1

––

––

––

––

––

S2

––

––

––

––

––

D1

*1

*1

Meaning

Data

Setting Range

Set by

U0

Dummy

––

––

S0

Drive designation

2

User

––

––

Data Type

Item

Contents/Setting Data

Setting Range

Set by

D0

Execution/
completion
type

Designate the execution type.
0000H : Write binary data
0100H : Write data after CSV format conversion

0000H
0100H

User

D0

+1

(Not used)

Used by system

––

System

D0

+2

Writing
result (No.
of written
data)

Contains the number of actually written data
against the data designated by S2 . The unit
of the value depends on data type specified at
D0 +7.

––

System

D0

+3

(Not used)

––

––

––

File
position

Set the file position when binary data writing
is specified by D0 .
00000000H
:Starting at the beginning of the file
00000001H to FFFFFFFEH:
From the specified position
The unit of the value depends
on data type specification.
FFFFFFFFH : Addition starts from the end
of the file.
When CSV format write is specified at D0
• For the High Performance model QCPU of
which the first 5 digits of the serial number
are "01111" or lower, always set the
beginning (0H) of the file.
• For the High Performance model QCPU/
Process CPU/Redundant CPU/Universal
model QCPU of which the first 5 digits of
the serial number are "01112" or higher, set
the file position.
00000000H to FFFFFFFEH
: Starting at the beginning of
the file
FFFFFFFFH
: Addition starts at the end of the file.

D0

D0
D0

+4
+5

BIN 16 bits

00000000H to
FFFFFFFFH

User

7-413

7
8

7.18 Other instructions
7.18.12 Writing Data to Designated File (SP.FWRITE)

Head number of the devices storing the control data. The following control data is required.
Device

6

––

*1: Local devices and the devices designated for individual programs cannot be used.

Setting

6

SP.FWRITE

Setting

Meaning

Data

Setting Range

Set by

Data Type

When binary write is specified at D0 , always
set 0.
When CSV format write is specified at D0 ,

No. of
D0

+6

columns

set the number of columns where data will be

designation 0

D0

0H to
FFFFH

written.
: No columns. Regarded as

User

(0 to 65535)

one row.
Other than 0 : Set to the specified number of
columns.
D0

+7

Data type 0: Word
specification 1: Byte

0,1

User

Head number of the devices storing a file name. A file name is expressed as follows:

Device

Item

Contents/Setting Data

Setting Range

Set by

Designate the character string of a file name.

• When omitting an extension, also omit
the "." (Period).
S1

to

S1
S1

+

File name
character
string

• Limit the file name within 8 characters +
period + 3 characters.
• When 9 or more characters are used,

BIN 16 bits

Character
string

User

the extension is ignored regardless of its
presence, and "BIN" or "CSV" is
automatically assigned as an extension.
Head number of the devices storing the data. Written data is expressed as follows:

Device

Item

Contents/Setting Data

Setting Range

Set by

Designate the number of data to request

No. of
S2

S2

request
write data

writing (word units).
This data should be designated in units of
words even when byte is designated by
D0

S2

+1 to

S2

+

Write data

1 to 480
1 to 32767 *2

User

+7.

Data to request writing.

0000H to
FFFFH

Bit device that turned ON at the completion of the processing.
( D1 +1 is also turned ON at error completion.)

Device

Item
Completion

D1

D1

signal
Error

D1

+1

completion
signal

Contents/Setting Data
Indicates the completion of the processing.
ON: Completed OFF: Not completed

Setting Range
––

Indicates whether the processing is normally
completed or abnormally completed.
ON: Error completion

Bit

System
––

OFF: Normal completion

*2: Indicates the range applicable only for the Universal model QCPU.

7-414

Set by

SP.FWRITE

Caution
(1) At

1
S0

(drive designation), only the ATA card drive (2) can be set.

Note that when the Flash card is loaded, the SP.FWRITE instruction cannot be used to
perform writing.
The SRAM card, standard RAM or standard ROM drive cannot be set.

2
3

(2) For CSV setting, the data written are decimal values.
Example Character "A" (41H)
"65" is written.
Handling range: -32768 to 32767
(3) For binary write, the word-specified file position setting range is 00000000H to 7FFFFFFFH
and FFFFFFFFH.

4
6
6
7
8

7.18 Other instructions
7.18.12 Writing Data to Designated File (SP.FWRITE)

7-415

SP.FWRITE

Function
(1) The designated number of data is written to the designated file.
Set the execution/completion type in the control data to designate whether to write binary
data without any conversion or to convert binary data into CSV format data before writing it.
(The writing target is the ATA card only.)
(2) The execution completion bit device ( D1 ) is automatically turned ON at the END processing
after the completion of the instruction is detected. The bit device is turned OFF at the
execution of the END instruction in the next scan.
Use this bit device as the execution completion flag for the SP.FWRITE instruction.
When this instruction is completed abnormally, the error completion device ( D1 +1) is turned
ON/OFF in synchronization with the processing complete ( D1 ) device. Use this device as the
error completion flag for this instruction.
SM721 is turned ON during the execution of the instruction.
This instruction cannot be executed while SM721 is ON. (If an attempt is made, no
processing is performed.)
When an error is detected at the execution of the instruction (before SM721 is turned ON),
the processing complete device ( D1 ), the error completion device ( D1 +1), and SM721 are
not turned ON.
(3) Be sure to use in units of words to designate the No. of request write data ( S2 ) and the file
position ( D0 +4 and

D0

+5).

The following shows the method for writing binary data when No. of request write data and
file position are specified.
Control data
D0+0

H0000

D0+1

-

D0+2

K3

D0+3

-

D0+4

K1

Execution/completion type
(Not used)
Number of written
result data
(Not used)
Head position of the file to be written

D0+5
D0+6

-

Designation of the number of columns

D0+7

K0

Data type specification

Data device
D1+0 K3

File data (in byte unites)
H00
H00

D1+1 H33 22
Total

H22
H33

D1+2 H55 44
Data to
be written

H44
H55

D1+2 H77 66

H66
H77
H00
H00
H00

7-416

One word
shift

SP.FWRITE
(4) When writing binary data
(a) If the extension of the target file is omitted, ".BIN" is used as an extension.
(b) When the designated file does not exist, a new file is created and the data is added/
saved from the beginning of the file.
The attributes of this new file are set using the archive attributes.
(c) When the size of the data exceeds that of the existing area in the file during the writing,
the excess data is added/saved.

1
2
3

(d) If the file position specified is greater than the existing file size:
• The High Performance model QCPU of which the first 5 digits of the serial number
are "01111" or lower results in an error.
• The High Performance model QCPU/Process CPU/Redundant CPU/Universal
model QCPU of which the first 5 digits of the serial number are "01112" or higher
performs writing at point 0 and is completed normally.
(e) An error occurs when the saving space becomes full while data is added and saved.
In such a case, the data that is successfully added/saved remains in the medium.
The error completion is indicated after as much data as possible is added/saved.
(5) When writing data after CSV format conversion
(a) If the extension is omitted, ".CSV" is used as an extension.
(b) When the existing file is specified:
[High Performance model QCPU of which the first 5 digits of the serial number are
"01111" or lower]
File contents are all deleted and data are saved, starting at the beginning.
[High Performance model QCPU/Process CPU/Redundant CPU/Universal model
QCPU of which the first 5 digits of the serial number are "01112" or higher]

• When FFFFFFFFH is set at ( D0 +4,
file.

D0

D0

6
6
7
8

+5), file contents are all deleted and

+5), data are saved, starting at the end of the

(c) When the designated file does not exist, a new file is created and the data is added/
saved from the beginning of the file.
The attributes of this new file are set using the archive attributes.
(d) An error occurs when the saving space becomes full while data is added and saved.
In such a case, the data that is successfully added/saved remains in the medium.
The error completion is indicated after as much data as possible is added/saved.

7-417

7.18 Other instructions
7.18.12 Writing Data to Designated File (SP.FWRITE)

• When other than FFFFFFFFH is set at ( D0 +4,
data are saved, starting at the beginning.

4

SP.FWRITE

(e) When the designated number of columns is "0", the data is stored as single-row data in
CSV format file.
Example
When data is written after CSV format conversion and the designated No. of columns is
"0":
SP.FWRITE U0 K2 D10 D20 D99 M0

* Designation in word units

D10

H0100

Execution/completion type

D11

-

D12

K0

D13

-

Not used
Number of written result data (In normal completion,
it is the same number as the number of data to be written.)
Not used

D14

K0

D15

K0

D16

K0

Designation of the number of columns

D17

K0

Data type specification

D20

H4241

D21

H4443

D22

H0045

D099

K7

D100

K0

D101

K10

D102

K20

D103

K30

D104

K40

D105

K-50

D106

K100

File name (If a file name consists of 8 or less
characters, "00"s are filled in the remaining area.)
"ABCDE"

Number of data to be written
Data to be written

Data to be written to the file

0 , 10 , 20 , 30 , 40 , -50 , 100 CR LF

Data to be read out to EXCEL file

7-418

SP.FWRITE

(f)

When data is written after CSV format conversion and the designated number of
columns is other than "0", the data is stored as table data with designated number of
columns in a CSV format file.
Example
When data is written after CSV format conversion and the designated No. of columns is
other than "0":

1
2
3

SP.FWRITE U0 K2 D10 D20 D99 M0
* Designation in word units

4
D10

H0100

Execution/completion type

D11

K0

D12

K0

D13

K0

In the module
Number of written result data (In normal completion,
it is the same number as the number of data to be written.)
Not used

D14

K0

D15

K0

D16

K3

No. of columns designation

D17

K0

Data type specification

D20

H4241

File name

D21

H4443

"ABCD"

D22

H0000

D099

K7

D100

K0

D101

K10

D102

K20

D103

K30

D104

K40

6
6
7

K-50

D106

K100

Number of data to be written
Data to be written
7.18 Other instructions
7.18.12 Writing Data to Designated File (SP.FWRITE)

D105

8

Data to be written to the file

0 , 10 , 20 CR LF
30 ,

40 ,

-50 CR LF

100 CR LF

Data to be read to EXCEL file

7-419

SP.FWRITE

(g) When data is added by the High Performance model QCPU/Process CPU/Redundant
CPU/Universal model QCPU of which the first 5 digits of the serial number are 01112 or
higher:
[Specify the file to which data will be written.] (If a file exists, delete it and create a new
file again.)
Execution type
= CSV format
Column designation
= 4H*3*5
Data type specification = Word

File position
= 0H (New file is created)
Write head device = D0
= 6H*3
Number of data
Device data
(Data to be written)

Column
1
Starting row

Row 1

1

5

Row 2

,

,

Column
2
2

6

,

Column
3
3

,

Column
4
4

CR LF

*3
CR LF

K6

D0

K1

D1

K2

D2

K3

D3

K4

D4

K5

D5

K6

D6

K5

D7

K7

D8

K8

D9

K9

D10

K10

D11

K11

D12

K12

D13

Number of write points

[In the addition mode, make addition from the end of the file.]
Execution type
= CSV format
Column designation
= 3H*3*5
Data type specification = Word

File position
= FFFFFFFH (Continuation mode)
Write head device = D7
= 8H*3
Number of data
Device data
(Data to be written)
K6
D0

Column
1
Row 1

1

5

Row 2

Column
2
,

,

2

6

,

3

Row 3

Row 4

Row 5

7

10

13

,

,

,

8

11

14

,

4

CR LF

*4
Present starting row

Column
4

Column
3

,

,

9

12

*3
CR LF

*5
CR LF

CR LF

CR LF

*5

K1

D1

K2

D2

K3

D3

K4

D4

K5

D5

K6

D6

K8

D7

K7

D8

K8

D9

K9

D10

K10

D11

K11

D12

K12

D13

K13

D14

K14

D15

Number of write points

*3: Unless the "number of write points" is set to an integral multiple of "column designation", the
column numbers will be random.
*4: Since the last data is always followed by the line feed code, addition normally starts at the
beginning of the new row in the addition mode.
*5: If, in the addition mode, "column designation" is changed from that in the previous writing, the
column numbers are shifted.

(h) Do not execute the SP.FWRITE instruction in an interrupt program.
(If execute it, the operation is not guaranteed.)

7-420

SP.FWRITE

Operation Error

1

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• Drive specified by drive designation device
card.
• Values specified in control data
range.

S0

contains the medium other than the ATA
(Error code: 4100)

2

and the subsequent devices are out of the setting
(Error code: 4100)

3

• Value designated by "No. of request write data" ( S2 ) is out of the setting range, or
exceeds the device range designated by ( S2 +1) or the subsequent devices.
(Error code: 4101)

4

D0

• Empty space in the ATA card is insufficient.

(Error code: 4100)

• No free space is found when an attempt is made to create a new file.
(Error code: 4100)
• Invalid device is designated.

(Error code: 4004)

• Access error occurred in the ATA card.

(Error code: 4100)

• An unusable value is set for a file name ( S1 ).

(Error code: 4100)

• The attribute of a file name ( S1 ) is "read only".

(Error code: 4100)

• The device specified by D0 or D1 exceeds the range of the corresponding device.
(For the Universal model QCPU only.)
(Error code: 4101)

6
6
7
8

7.18 Other instructions
7.18.12 Writing Data to Designated File (SP.FWRITE)

7-421

SP.FWRITE

Program Example
(1) When X10 is turned ON, the following program adds four bytes of binary data (00H, 01H,
02H, and 03H) to file "ABCD.BIN" in the memory card inserted to drive 2.
• Assume that 8 points from

D0

are reserved for the control data devices.

[Ladder Mode]
Sets the execution/completion type
Sets the file position
Sets the file name
Sets the number of request write data

Sets the data to be written.

Normal completion display

Error completion display

[List Mode]
Step

7-422

Instruction

Device

SP.FWRITE

(2) When X10 is turned ON, the following program creates a file named "ABCD.CSV" in the
memory card inserted to drive 1, and writes four bytes of data (00H, 01H, 02H, and 03H) as
two-column table data in CSV format.

1

• The written file is displayed as follows:
[Ladder Mode]

2
Sets the execution/completion type
Sets the designation of the number of columns

3

Sets the file name

4

Sets the number of request write data

Sets the data to be written.

6

Normal completion display

6

Error completion display

7
8

[List Mode]
Step

Instruction

0
2

,
,

1
3

D0

7.18 Other instructions
7.18.12 Writing Data to Designated File (SP.FWRITE)

• Assume that 8 points from

Device

are reserved for the control data devices.

, CR LF Contents of the file to be written
, CR LF

Data to be read to the EXCEL file

7-423

SP.FREAD

7.18.13

Reading Data from Designated File (SP.FREAD)

SP.FREAD

High
performance

Basic

Process Redundant Universal

Command

SP.FREAD

SP.FREAD

Setting
Data

Internal Devices
Bit

R, RZ

Word

J
Bit

\
Word

U

D0

S0

U0

S1

Zn

\G

D1

Constants
K, H

––

S0

D2

$

Other

––

––

D0

––

––

––

––

––

S1

––

––

––

––

––

D1

––

––

––

––

––

D2

*1

*1

––
––

––

*1: Local devices and the devices designated for individual programs cannot be used.

Setting

Meaning

Data

Setting Range

Set by

U0

Dummy

––

––

S0

Drive designation

2

User

Data Type

Head number of the devices storing the control data
The following control data is required.

Device

D0

D0

+1

Item

Contents/Setting Data

Setting Range

Set by

Execution/
completion
type

Designate the execution type.
0000H: Read binary data
0100H: Read data after CSV format conversion

0000H
0100H

User

(Not used)

Used by system

––

System

D0

Designate the number of data to request
reading.
D0

+2

No. of
request
read data

(Unit: Word)

1 to 480

Even when byte is specified at D0 +7 by data

1 to 32767*2

User

type specification, specify the value in units of
words (16 bits), not in units of bit devices.
D0

+3

(Not used)

––

––

*2: Indicates the range applicable only for the Universal model QCPU.

7-424

––

BIN 16 bits

SP.FREAD

Setting

Meaning

Data

Setting Range

Set by

Data Type

Designate the file position to start reading when
binary data reading is designated by D0 .
00000000H: Starting at the beginning of the file
00000001H to FFFFFFFEH
:From the designated position
The unit for the value is
determined by word/byte unit
designation.
FFFFFFFFH: Setting disabled

D0

+4

D0

+5

File
position

D0

When CSV format read is specified at D0
• For the High Performance model QCPU of
which the first 5 digits of the serial number
are "01111" or lower, always set the
beginning (0H) of the file.
• For the High Performance model QCPU/
Process CPU/Redundant CPU/Universal
model QCPU of which the first 5 digits of the
serial number are "01112" or higher, set the
file position (Row).
00000000H: Read starts at the beginning of
the file.
00000001H to FFFFFFFEH
:Read starts at the specified row.
FFFFFFFFH: Read continues, starting at the
previous read position.

D0

+6

No. of
columns
designation

D0

+7

Data type 0: Word
specification 1: Byte

2
3
00000000H to
FFFFFFFFH

4

User

6
6
7
8
0H to FFFFH
(0 to 65535)

User

0,1

User

BIN 16 bits

7.18 Other instructions
7.18.13 Reading Data from Designated File (SP.FREAD)

When binary read is specified at D0 , always
set 0.
When CSV format read is specified at D0 , set
the number of columns from where data will
be read.
0: No columns. Regarded as one row.
Other than 0: Regarded as the specified
number of columns.

Head number of the devices storing a file name. A file name is expressed as follows:

Device

Item

Contents/Setting Data

Setting Range

Set by

Character
string

User

Setting Range

Set by

––

System

––

System

Designate the character string of a file name.

S1
S1

to

S1 +

File name
character
string

• When omitting an extension, also omit
the "." (Period).
• Limit the file name within 8 characters +
period + 3 characters.
• When 9 or more characters are used,
the extension is ignored regardless of its
presence, and "BIN" or "CSV" is
automatically assigned as an extension.

Head number of the devices for storing the read data.

Device

Item

Contents/Setting Data
Contains the number of actually read data

D1

D1

Reading
against the data designated by D0 +2. The
result (No. of
unit on the value depends on data type
read data)
specification.

D1

+1 to

D1

+

Reading
data

Read data

1

7-425

SP.FREAD

Setting

Meaning

Data

Setting Range

Set by

Setting Range

Set by

Data Type

Bit device that turned ON at the completion of the processing.
( D2 +1 is also turned ON at error completion.)

Device

D2

D2

D2

+1

Item

Contents/Setting Data

Completion
signal

Indicates the completion of the processing.
ON: Completed
OFF: Not completed

Error
completion
signal

Indicates whether the processing is normally
completed or abnormally completed.
ON: Error completion
OFF: Normal completion

––

Bit

System
––

Caution
(1) At

S0

(drive designation), only the ATA card drive (2) can be set.

Note that when the Flash card is loaded, the SP.FREAD instruction cannot be used to
perform read.
The SRAM card, standard RAM or standard ROM drive cannot be set.
(2) For CSV setting, the data written are decimal values.
Example
"65" is written.
Character "A" (41H)
Handling range: -32768 to 32767
(3) For binary read, the word-specified file position setting range is 00000000H to 7FFFFFFFH.

Function
(1) Data is read from the designated file.
Set the execution/completion type in the control data to designate whether to read binary
data without any conversion or to convert binary data into CSV format data before reading it.
(The reading target is the ATA card only.)
(2) The execution completion bit device ( D2 ) is automatically turned ON at the END processing
after the completion of the instruction is detected. The bit device is turned OFF at the
execution of the END instruction in the next scan.
Use this bit device as the execution completion flag for the SP.FWRITE instruction.
When this instruction is completed abnormally, the error completion device ( D2 +1) is turned
ON/OFF in synchronization with the execution completion ( D2 ) device. Use this device as
the error completion flag for this instruction.
SM721 is turned ON during the execution of the instruction.
This instruction cannot be executed while SM721 is ON. (If an attempt is made, no
processing is performed.)
When an error is detected at the execution of the instruction (before SM721 is turned ON),
the processing complete device ( D1 ), the error completion device ( D1 +1), and SM721 are
not turned ON.

7-426

SP.FREAD

(3) Be sure to use word units to designate the number of request read data ( D0 +2), file position
( D0 +4 and D0 +5), and read data device size ( D1 ).
The following shows how the individual device data is read in binary data reading operation.

1

Control data
D0+0

H0000

Execution/completion type

D0+1

-

(Not used)

D0+2

K3

Number of request read data

D0+3

-

(Not used)

D0+4

K1

D0+5

2
3

Location to start reading in the file

D0+6

-

Designation of columns

D0+7

K0

Data type specification

Data device

4

File data (in byte units)

D1+0 K3

6

H00
H11

D1+1 H33 22
Total

H22

6

H33
D1+2 H55 44

Read data

H44
H55

D1+3 H77

7

H66
H77
H88

8

H99
HAA

(4) When reading binary data

(b) When the designated file does not exist, an error occurs.
(c) If the position specified is greater than the existing file size:
• The High Performance model QCPU of which the first 5 digits of the serial number
are "01111" or lower results in an error.
• The High Performance model QCPU/Process CPU/Redundant CPU/Universal
model QCPU of which the first 5 digits of the serial number are '01112' or higher will
perform reading at point 0 and will be completed normally.
(5) When reading data after CSV format conversion
(a) The elements in CSV format file (cells for EXCEL) are read by each row. The numerical
value and character strings are converted into binary data and stored in the device.
(b) If the extension is omitted, ".CSV" is used as an extension.
(c) When the designated file does not exist, an error occurs.
(d) The elements designated by the number of request read data ( D0 +2) are read from the
beginning of the file.
When the last data of the file is reached before the specified number of data are read:
• The High Performance model QCPU of which the first 5 digits of the serial number
are "01111" or lower results in an error.
• The High Performance model QCPU/Process CPU/Redundant CPU/Universal
model QCPU whose the first 5 digits of the serial number are '01112' or higher reads
the data up to the point where the reading is possible.

7-427

7.18 Other instructions
7.18.13 Reading Data from Designated File (SP.FREAD)

(a) If the extension of the target file is omitted, ".BIN" is used as an extension.

SP.FREAD

(e) When the designated number of columns is 0, the data is read by ignoring the rows in
CSV format file.
Example When data is read after CSV format conversion and the designated No. of
columns is 0:

Data created by EXCEL

Measured value

Main / sub item
Length
Temperature

Data saved in the CSV format
Main / sub item
, , Measured value CR LF
Length
, 1 , 3 CR LF
Temperature , -21 , CR LF

Data to be read into devices

SP.FREAD U0 K2 D10 D20 D99 M0
Data that was read
File name
Control data
Control data

Loaded data
Stores the number of read data

Read
data

7-428

D10

H0100

Execution/completion type

D11

-

Number of unused read data

D12

K9

Request

D13

-

Not used

D14

K0

D15

K0

D16

K0

Designation of the number of columns

D17

K0

Data type specification

D20

H4241

File name

D21

H4443

"ABCDE"

D22

H0045

D099

K9

Number of read result data
Conversion data (0) is stored since "Main/sub item" is nonnumeric data.

Main/sub item

D100

K0

Data between , and ,

D101

K0

Conversion data (0) is stored since " " is nonnumeric data.

Measured value

D102

K0

Conversion data (0) is stored since "Measured value" is nonnumeric data.

Length

D103

K0

Conversion data (0) is stored since "Length" is nonnumeric data.

1

D104

K1

Since " 1 " is a numeric value, it is converted to a binary value.

3

D105

K3

Since " 3 " is a numeric value, it is converted to a binary value.

Temperature

D106

K0

Conversion data (0) is stored since "Temperature" is nonnumeric data.

-21

D107

K-21

Since " -21 " is a numeric value, it is converted to a binary value.

Data between , and CR

D108

K0

Conversion data (0) is stored since " " is nonnumeric data.

SP.FREAD
If the number of columns varies in each row, the data is also read by ignoring the rows.

1
Such file cannot be created using EXCEL. This happens when CSV file is
modified by a user.

2

Example If the number of columns varies in each row when the data is read:

3

Main / sub item
, , Measured value , Excess CR LF
Length
CR LF
Temperature , -21 , CR LF

4
6

Data to be read into devices

SP.FREAD U0 K2 D10 D20 D99 M0

6

Data that was read
File name
Control data
Control data

7
D10

H0100

D11

-

D12

K7

D13

-

D14

K0

D15

K0

D16

K0

Designation of the number of columns

D17

K0

Data type specification

D20

H4241

File name

D21

H4443

"ABCD"

D22

H0000

D099

K7

Execution/completion type
Not used

8

Number of request read data
Not used

Stores the number of read data

Read
data

Number of read result data

Main/sub item

D100

K0

Conversion data (0) is stored since "Main/sub item" is nonnumeric data.

Data between , and ,

D101

K0

Conversion data (0) is stored since " " is nonnumeric data.

Measured value

D102

K0

Conversion data (0) is stored since "Measured value" is nonnumeric data.

Excess

D103

K0

Conversion data (0) is stored since "Excess" is nonnumeric data.

Length

D104

K0

Conversion data (0) is stored since "Length" is nonnumeric data.

Temperature

D105

K0

Conversion data (0) is stored since "Temperature" is nonnumeric data.

-21

D106

K-21

Since " -21 " is a numeric value, it is converted to a binary value.

7-429

7.18 Other instructions
7.18.13 Reading Data from Designated File (SP.FREAD)

Loaded data

SP.FREAD

(f)

When data is read after CSV format conversion and the designated number of columns
is other than 0, the data is read as the table with designated number of columns in CSV
format file. The elements outside of the designated columns are ignored.
Example When data is read after CSV format conversion and the designated No. of
columns is other than "0":

Data created by EXCEL

Measured value

Main / sub item
Length
Temperature

Data saved in the CSV format
Main / sub item
, , Measured value CR LF
Length
, 1 , 3 CR LF
Temperature , -21 , CR LF

Elements outside the designated
number of columns are ignored.

Data to be read into devices

SP.FREAD U0 K2 D10 D20 D99 M0
Data that was read
File name
Control data

Control data

D10

Loaded data
Stores the number of read data

Read
data

7-430

H0100

D11

-

D12

K6

Execution/completion type
Not used
Number of request read data
Not used

D13

-

D14

K0

D15

K0

D16

K2

Designation of the number of columns

D17

K0

Data type specification

D20

H4241

File name

D21

H4443

"ABCD"

D22

H0000

D099

K6

Number of read result data

Main/sub item

D100

K0

Conversion data (0) is stored since "Main/sub item" is nonnumeric data.

Data between , and ,

D101

K0

Conversion data (0) is stored since " " is nonnumeric data.

Length

D102

K0

Conversion data (0) is stored since "Length" is nonnumeric data.

1

D103

K1

Since " 1 " is a numeric value, it is converted to a binary value.

Temperature

D104

K0

Conversion data (0) is stored since "Temperature" is nonnumeric data.

-21

D105

K-21

Since " -21 " is a numeric value, it is converted to a binary value.

SP.FREAD
If the number of columns varies in each row, the elements outside of the designated columns are
ignored and "0" is added to the places where elements do not exist.

1

Example

2

If the number of columns varies in each row when the data is read:

Main / sub item
, , Measured value , Excess CR LF
Length
CR LF
Temperature , -21 , CR LF
Elements outside the designated
number of columns are ignored.

3
4

Data to be read into devices

SP.FREAD U0 K2 D10 D20 D99 M0

6

Data that was read
File name
Control data

6

Control data

D10

H0100

D11

-

D12

K6

D13

-

D14

K0

D15

K0

D16

K2

Designation of the number of columns

D17

K0

Data type specification

D20

H4241

File name

D21

H4443

"ABCD"

D22

H0000

D099

K6

Number of read result data

Main/sub item

D100

K0

Conversion data (0) is stored since "Main/sub item" is nonnumeric data.

Data between , and ,

D101

K0

Conversion data (0) is stored since " " is nonnumeric data.

Length

D102

K0

Conversion data (0) is stored since "Length" is nonnumeric data.

No data

D103

K0

No data Since no element exists here, conversion data (D) is added.

Temperature

D104

K0

Conversion data (0) is stored since "Temperature" is nonnumeric data.

-21

D105

K-21

Since " -21 " is a numeric value, it is converted to a binary value.

Read
data

7

Not used
Number of request read data
Not used

8

7-431

7.18 Other instructions
7.18.13 Reading Data from Designated File (SP.FREAD)

Loaded data
Stores the number of read data

Execution/completion type

SP.FREAD

(g) With the High Performance model QCPU/Process CPU/Redundant CPU/Universal
model QCPU whose first 5 digits of the serial number are "01112" or later, it is possible
to divide read operation into multiple times.
[Specify the row desired to start read.]
Execution type
= CSV format Starting row number
Read head device
Column designation
= 4H
Data type specification = Word
Number of data

= 2H
= D0
= 6H
Device data
(Data to be read out)

Column
1
Row 1

Starting row

1

Row 2

Column
2
,

5

2

,

Column
3
,

6

3

,

Column
4
,

7

4

,

8

CR LF

CR LF

K6

D0

K5

D1

K6

D2

K7

D3

K8

D4

K9

D5

K10

D6

Number of read points

D7
9

,

10

,

11

,

12

CR LF

D8

Next starting
position

Row 3

D9
D10
D11
D12

Row 4

13

,

14

,

15

,

Row 5

17

,

18

,

19

,

16

CR LF

D13

CR LF

[In the continuation mode, read continues from the end of the previous read position.]
Execution type
= CSV format Starting row number
Read head device
Column designation
= 4H
Data type specification = Word
Number of data

= FFFFFFFH (Continuation mode)
= D7
= 5H
Device data
(Data to be read out)

Column
1
Row 1

5

,

,

2

6

,

,

Column
3
3

7

,

,

Column
4
4

8

CR LF

CR LF

Present starting
position

Row 2

1

Column
2

Row 3

9

,

10

,

11

,

12

CR LF

K6

D0

K5

D1

K6

D2

K7

D3

K8

D4

K9

D5

K10

D6

K5

D7

K11

D8

K12

D9

K13

D10

K14

D11

K15

D12

Number of read points

D13
13

,

14

,

15

,

Row 5

17

,

18

,

19

,

16

CR LF

Next starting
position

Row 4

20

CR LF

• When read is performed in the continuation mode, the previous addition cannot be made
normally if the "execution type", "column designation" and "Data type specification"
settings differ from those at the previous time.
• The previous addition cannot be made normally if the SP.FREAD instruction or
SP.FWRITE instruction with another setting is executed while data is being read
continuously in the continuation mode.

7-432

SP.FREAD

(h) When data is read after CSV format conversion, the numerical values that are out of
range or the elements other than numerical values in the object CSV format file are
converted into 0H.
(i)

When data is read after CSV format conversion, numerical values are read and
converted as follows:
Numerical Values in
CSV Format
Without
Word

a sign

device

With a
sign

(j)

-32768 to -1

0 to 32767

32768 to 65535

32768 to 65535

0 to 32767

32768 to 65535

-32768 to -1

0 to 32767

-32768 to -1

1
2
3
4

Do not execute this instruction in an interrupt program.
(Otherwise, a malfunction may result.)

6

Operation Error

6

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• Drive specified by drive designation device ( S0 ) contains the medium other than the ATA
card.
(Error code: 4100)
• Values designated in control data ( D0 ) and the subsequent devices are out of the setting
range. (Excluding D0 +2)
(Error code: 4100)

7
8

• Value designated by number of data blocks to be read ( D0 +2) is out of the setting range.
(Error code: 4101)
(Error code: 4004)

• File name designated by file name character string ( S1 ) or the subsequent devices does
not exist in the designated drive.
(Error code: 2410)
• Size of read data exceeds the size of reading device.

(Error code: 4101)

• When binary data is read, the number of data in the file is less than the size designated by
the number of request read data ( D0 +2).
(High Performance model QCPU of which the first 5 digits of the serial number are '01111'
or lower)
(Error code: 4100)
• Access error occurred in the ATA card.

(Error code: 4100)

• The device specified by D0 or D2 exceeds the range of the corresponding device.
(For the Universal model QCPU only.)
(Error code: 4101)

7-433

7.18 Other instructions
7.18.13 Reading Data from Designated File (SP.FREAD)

• Invalid device is designated.

SP.FREAD

Program Example
(1) The following program reads 4 bytes of binary data from the beginning of file "ABCD.BIN" in
the memory card inserted to drive 2 when X10 is turned ON.
• Assume that 8 points from (D0) are reserved for the control data devices.
• Assume that 100 bytes from D20 are reserved for the reading devices.
[Ladder Mode]
Sets the execution/completion type
Sets the number of request read data
Sets the file position
Sets the file name

Normal completion display

Error completion display

[List Mode]
Step

7-434

Instruction

Device

SP.FREAD

(2) The following program reads file "ABCD.CSV" in the PC card inserted to slot 0 as
two-column table data in CSV format when X10 is turned ON.

1

• Assume that 8 points from (D0) are reserved for the control data devices.
• Assume that 100 bytes from D20 are reserved for the reading devices.

2

• Assume that the target CSV format file contains numerical values only.
[Ladder Mode]

3

Sets the execution/completion type
Sets the number of request read data
Sets the designation of number of columns

4

Sets the file name

6
Normal completion display

6
Error completion display

7
8

[List Mode]
Step

Instruction

Device

7.18 Other instructions
7.18.13 Reading Data from Designated File (SP.FREAD)

7-435

SP.DEVST

7.18.14

Writing Data to Standard ROM (SP.DEVST)

SP.DEVST

High
performance

Basic

Process Redundant Universal

Command

SP.DEVST

SP.DEVST

n1

S

n2

D

n1: Write offset of the device data storage file (specified in units of 16-bit words) (BIN 32-bit)
S : Head device number written to the standard ROM (device name)
n2: The number of write points (BIN 16-bit)
D

:

D
D

Setting
Data

+0 : FCompletion device (bit)
+1 : FError completion device (bit)

Internal Devices
Bit

Word

R, ZR

J
Bit

\
Word

U

n1

––

––

S

––

––

n2

––

––

D

*1

––

*1

Zn

\G

Constants
K,H

Other
––

––

––
––

––

––

––

*1:Devices assigned as local devices can not be used.

Function
(1) Writes device data for the number of points specified at n2 of the device S to the write
offset, which is specified for n1, of the device data storage file in the standard ROM.
n1 is the offset from the head of device data storage file and specified by word offset (in units
of 16-bit words).
Standard ROM

Head device
number S

Write offset n1

Device data
storage file

Write offset of device
data stofage file
Write
offset

Number of
n2 points

16-bit

+0
+1
+2

(2) Since the device data write position completion device ( D +0) in the standard ROM
automatically turns ON at execution of the END instruction, which detects the completion of
this instruction, and turns OFF with the END instruction of next scan, it is used as an
execution completion flag of this instruction.
(3) When this instruction is completed in error, the error completion device ( D +1) turns ON/
OFF at the same timing with the completion device ( D +0). This device is used as an error
completion flag of this instruction.

7-436

SP.DEVST

(4) SM721 turns ON during execution of this instruction.
When SM721 has already turned ON, this instruction can not be executed. (If executed, no
processing is performed.)
(5) When an error is detected at execution of this instruction, the completion device (
error completion device ( D +1) and SM721 do not turn ON.

D

+0),

Operation Error

1
2
3

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The write offset specified at n1 is out of the device data storage file range.
(Error code: 4100)
• The number of n2 points from the write offset specified at n1 is out of the device data
storage file range.
(Error code: 4100)
• The range for the number of n2 points from the device
device.

S

exceeds the corresponding
(Error code: 4141)

4
6
6

• The device data storage file is not set at "PLC file" of PLC parameter on GX Developer.
(Error code: 2410)
• The device specified by

D

exceeds the range of the corresponding device.
(Error code: 4101)

7
8

Program Example
(1) The program which writes the ten points of data from D100 to the device data storage file in
the standard ROM when M0 turns ON.
[List Mode]
Step

Instruction

Device

Caution
(1) The value written to the standard ROM is the value at execution of this instruction.
(2) The standard ROM write count index (SD687 and SD688) is increased by the execution of
the SP.DEVST instruction. If the standard ROM write count index exceeds hundred
thousand times, FLASH ROM ERROR (error code: 1610) occurs.
(3) To prevent the number of ROM writes from increasing due to executing instruction
carelessly, set the specification of writing to standard ROM instruction count (SD695) to
restrict the number of writes a day.
Exceeding the number of writes (the default values are 36 times.) set causes OPERATION
ERROR (error code: 4113).

7-437

7.18 Other instructions
7.18.14 Writing Data to Standard ROM (SP.DEVST)

[Ladder Mode]

(S(P).DEVLD)

7.18.15

Read Data from Standard ROM (S(P).DEVLD)

(S(P).DEVLD)

Basic

High
performance

Process Redundant Universal

Command

S.DEVLD

S.DEVLD

n1

D

n2

SP.DEVLD

n1

D

n2

Command

SP.DEVLD

n1 : Read offset of the device data storage file (specified in units of 16-bit words) (BIN 32-bit)
D
: Head device number read from the standard ROM (device name)
n2 : The number of reading points (BIN 16-bit)
Setting
Data

Internal Devices
Bit

Word

R, ZR

J
Bit

\
Word

U

n1

––

––

D

––

––

n2

––

––

\G

Constants
E

Zn

Other
––

––

––
––

Function
(1) Reads device data for the number of points specified at n2 from the read offset, which is
specified for n1, of the device data storage file in the standard ROM, and stores the data to
the device specified for D .
n1 is the offset from the head of device data storage file and specified by word offset (in units
of 16-bit words).
Standard ROM

Head device
number D

Read offset n1

Device data storage file
Read offset of device data
storge file
Read
offset

Number of
n2 points

7-438

+0
+1
+2

16-bit

(S(P).DEVLD)

Operation Error

1

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The address specified at n1 is out of the standard ROM range.

(Error code: 4100)

• The number of n2 points from the address specified at n1 is out of the standard ROM
range.
(Error code: 4100)
• The range for the number of n2 points from the device
device.

D

exceeds the corresponding
(Error code: 4101)

• The device data storage file is not set at "PLC file" of PLC parameter on GX Developer.
(Error code: 2410)

3
4
6

Program Example
(1) The program which reads the ten points of data from D100 to the device data storage file in
the standard ROM when M0 turns ON.
[Ladder Mode]

2

[List Mode]
Step

Instruction

Device

6
7
8

7.18 Other instructions
7.18.15 Read Data from Standard ROM (S(P).DEVLD)

7-439

PLOADP

7.18.16

Load Program from Memory Card (PLOADP)

PLOADP

High
performance

Basic

Process Redundant Universal

Command

PLOADP

PLOADP

S

S

D

: Drive No. storing the program to be loaded, character string data of the file name, or head number of the
devices storing the character string data (BIN 16 bits) *1

D

Setting
Data
S
D

: Device that turns ON for 1 scan by the instruction completion (bits)
Internal Devices
Bit

R, ZR

Word

J

\

Bit

Word

––
*2

U

\G

Zn

Constants
$

Other

––
––

––

––
––

––

*1: Designated as ":". Example) 1:MAIN
*2: Local devices cannot be used.

Function
(1) The program stored in the memory card or standard ROM is transferred to the program
memory (drive 0).
If the transferred program is not registered to the program setting of the PLC parameter
dialog box, its program setting in the CPU module is set to the standby type.
At this time, the program setting of the PLC parameter dialog box does not change.
(To transfer a program with the PLOADP instruction, a continuous free space is required in
the program memory.)
(2) The program added using the PLOADP instruction is assigned the lowest number among
the unused program Nos.
(To assign a program number manually, store the program number to be assigned in
SD720.)
The following example assumes that "MAIN6" is added by the PLOADP instruction.
(a) When the program Nos. have been set consecutively, the new program is added at the
end of the preset program Nos.
When programs No. 1 to 5 have been set, the new program is added as program No. 6.
Program No. Program name
1
MAIN1
2
MAIN2
MAIN3
3
MAIN4
4
MAIN5
5

7-440

Adds "MAIN6" by the
PLOADP instruction.

Program No. Program name
1
MAIN1
2
MAIN2
MAIN3
3
4
MAIN4
5
MAIN5
MAIN6
6

Added at the end.

PLOADP

(b) When there are multiple open program Nos., the program designated by the PLOADP
instruction is added to the lowest number among them to be added.
(The open program Nos. are made when programs are deleted by the PUNLOADP
instruction.)
When programs No. 2 and 4 are open, the new program is added as program No. 2.
Program No.
1
2
3
4
5

Program name
MAIN1
Empty
MAIN3
Empty
MAIN5

Adds "MAIN6" by the
PLOADP instruction.

Program No.
1
2
3
4
5

Program name
MAIN1
MAIN6
MAIN3
Empty
MAIN5

Added to the smallest program
number which is empty.

1
2
3
4

(3) Drive Nos. 1, 2, and 4 can be specified. (Drive 3 cannot be specified.)
• Drive 1: Memory card (RAM)
• Drive 2: Memory card (ROM)

6

• Drive 4: Standard ROM
(4) An extension (.QPG) need not be specified for the file name.
(5) The bit device specified by D is turned ON during the END processing of the scan where
this instruction is completed. The bit device is turned OFF at the next END processing.
(6) The PLOADP, PUNLOADP and PSWAPP instructions cannot be executed simultaneously.
If two or more of the above instructions are executed simultaneously, the instruction
executed later will not be executed.
When using the above instructions, provide interlocks manually to avoid simultaneous
execution.

6
7
8

(7) Do not execute this instruction in an interrupt program.
(Otherwise, a malfunction may result.)

(9) The PLC file settings of the loaded program are set as follows:
(a) File usage for each program
All the usage of file register, device initial value, comment, and local device of the
program transferred by this instruction are set as "Use PLC file setting".
However, an error will be returned if both of the conditions below are met when the
program is transferred using this instruction.
• Setting is made so that local devices are used in the PLC file setting.
• The number of programs in the program memory exceeds the number of programs
set at the parameters.
To use local devices in the program transferred by this instruction, register a dummy
program file in the parameter, delete the dummy file with the PUNLOADP instruction,
and then load the program with the PLOADP instruction.
(b) I/O refresh setting
Nothing is set for both input and output for the I/O refresh setting of the program
transferred by this instruction.

7-441

7.18 Other instructions
7.18.16 Load Program from Memory Card (PLOADP)

(8) To execute the program that was transferred to the program memory with the PLOADP
instruction, execute the scan execution type with the PSCAN instruction (See Section
7.17.3).

PLOADP

(10) The "PLOADP instruction" and "Write during RUN" processing cannot be executed
simultaneously.
(a) When a write during RUN request is given during processing of the PLOADP
instruction, write during RUN is delayed.
Write during RUN is started after the processing of the PLOADP instruction is
completed.
(b) When the PLOADP instruction is executed during write during RUN, the processing of
the PLOADP instruction is delayed.
The processing of the PLOADP instruction is started after completion of write during
RUN.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• File name does not exist at the drive number designated by
• The drive No. designated by

S

S

.

(Error code: 2410)

is invalid.

(Error code: 4100)

• There is not enough memory to load the specified program in drive 0.
(Error code: 2413)
• The number of files registered in the program memory is as much number as the one
indicated in the table below.
(Error code: 4101)
• The program No. stored in SD720 is already used, or larger than the largest program
number shown in the table below.
(Error code: 4101)
• The program file which has the same name as the program file to be loaded already
exists.
(Error code: 2410)
• The file size of the local devices cannot be reserved.

(Error code: 2401)

CPU Model Name

Program Memory (No. of Files)

Largest Program No.

Q02 (H) CPU

28

28

Q06HCPU

60

60

Q12HCPU

124

124

Q25HCPU

124

124

Q12PHCPU

124

124

Q25PHCPU

124

124

Program Example
(1) The following program transfers "ABCD.QPG" stored in drive 4 to drive 0 and places the
program in standby status when M0 is turned ON.
[Ladder Mode]

[List Mode]
Step

7-442

Instruction

Device

PUNLOADP

7.18.17

Unload Program from Program Memory (PUNLOADP)

1
PUNLOADP

Basic

High
performance

Process Redundant Universal

2
3

Command

PUNLOADP

PUNLOADP

S

D

4
S

: Character string data of the program file name to be unloaded, or head number of the devices storing the

D

: Device turned ON for 1 scan on completion of the instruction (bits)

character string data (BIN 16 bits)

Setting
Data
S
D

Internal Devices
Bit

R, ZR

Word

J
Bit

\
Word

––
*1

U

\G

6
Constants
$

Zn

Other

––
––

––

––

––

6

––

*1: Local devices cannot be used.

Function

7
8

(1) The standby program stored in the program memory (drive 0) is deleted from the program
memory.

(2) The program No. deleted by the PUNLOADP instruction is made "Empty".
When programs No. 1 to 5 have been set in the program setting of the PLC parameter dialog
box, deleting program No. 2 with this instruction makes program No. 2 open.
Program No.
1
2
3
4
5

Program name
MAIN1
MAIN2
MAIN3
MAIN4
MAIN5

Deletes "MAIN2" by the
PUNLOADP instruction.

Program No.
1
2
3
4
5

Program name
MAIN1
Empty
MAIN3
MAIN4
MAIN5

Program No. 2
is deleted.

(3) An extension (.QPG) need not be specified for the file name.
(4) The bit device specified by D is turned ON during the END processing of the scan where
this instruction is completed. The bit device is turned OFF at the next END processing.
(5) The PLOADP, PUNLOADP and PSWAPP instructions cannot be executed simultaneously.
If two or more of the above instructions are executed simultaneously, the instruction
executed later will not be executed.
When using the above instructions, provide interlocks manually to avoid simultaneous
execution.

7-443

7.18 Other instructions
7.18.17 Unload Program from Program Memory (PUNLOADP)

(The program set as the "scan execution type" with the PSCAN instruction or the program
set as the "low speed execution type" with the PLOW instruction cannot be deleted.)

PUNLOADP

(6) When the Programmable Controller is powered OFF, then ON or the CPU module is reset
after execution of the PUNLOADP instruction, the following operation is performed.
(a) When boot setting has been made in the PLC parameter dialog box, the program where
the boot setting has been made is transferred to the program memory.
When the program deleted by the PUNLOADP instruction is not to be executed, delete
the corresponding program name from the boot setting and program setting of the PLC
parameter dialog box.
(b) When boot setting has not been made in the PLC parameter dialog box, "FILE SET
ERROR (error code: 2400)" occurs.
1) When the program deleted by the PUNLOADP instruction is not to be executed,
delete the corresponding program name from the program setting of the PLC
parameter dialog box.
2) When the program deleted by the PUNLOADP instruction is to be executed again,
write the corresponding program to the CPU module.
(7) Do not execute this instruction in an interrupt program.
(Otherwise, a malfunction may result.)
(8) The program to be deleted from the program memory by this instruction should be set to the
"standby execution type" with the PSTOP instruction beforehand. (See Section 7.17.1)
(9) The "PUNLOADP instruction" and "write during RUN" processing cannot be executed
simultaneously.
(a) When a write during RUN request is given during processing of the PUNLOADP
instruction, write during RUN is delayed.
Write during RUN is started after the processing of the PUNLOADP instruction is
completed.
(b) When the PUNLOADP instruction is executed during write during RUN, the processing
of the PUNLOADP instruction is delayed.
The processing of the PUNLOADP instruction is started after completion of write during
RUN.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The file name designated by
• The program designated by

S
S

does not exist.

(Error code: 2410)

is not in standby status or is being executed.
(Error code: 4101)

Program Example
(1) The following program deletes "ABCD.QPG" stored in drive 0 from the memory when M0
turns from OFF to ON.
[Ladder Mode]

[List Mode]
Step

7-444

Instruction

Device

PSWAPP

7.18.18

Load + Unload (PSWAPP)

1
PSWAPP

Basic

High
performance

Process Redundant Universal

2
3

Command

PSWAPP

PSWAPP

S1

S2

D

4
S1

: Character string data of the file name of the program to be unloaded, or head number of the devices storing
the character string data (BIN 16 bits)

S2

: Drive No. storing the program to be loaded, character string data of the file name, or head number of the

6

devices storing the character string data (BIN 16 bits) *1
D

Setting
Data

: Device turned ON for 1 scan on completion of the instruction (bits)
Internal Devices
Bit

R, ZR

Word

J
Bit

\
Word

U

\G

Zn

Constants
$

6
Other

S1

––

––

––

S2

––

––

––

D

*2

––

––

––

––

*1: Designated as ":". Example) 1:MAIN
*2: Local devices cannot be used.

(1) The standby type program stored in the program memory (drive 0) designated by S1 is
deleted from the program memory, and at the same time, the program stored in the memory
card or standard ROM designated by S2 is transferred to the program memory and placed in
standby status.
(When the program is transferred to the program memory, the program must have a
continuous free space.)
The program set as the "scan execution type" with the PSCAN instruction or the program set
as the "low speed execution type" with the PLOW instruction cannot be deleted.
(2) The program to be transferred to the program memory by the PSWAPP instruction will have
the program No. of the program to be deleted from the program memory.
(If there is an open program No. before the program to be deleted from the program
memory, the program to be transferred to the program memory will not have the open
program No.)
When program No. 2 is "Empty", the program transferred to the program memory is
registered as program No. 3 by the program swapping of program No. 3 with this instruction.
Program name
MAIN1
Empty
MAIN3
MAIN4
MAIN5

Swaps "MAIN3" with "MAIN6"
by the PSWAPP instruction.

Program No.
1
2
3
4
5

Program name
MAIN1
Empty
MAIN6
MAIN4
MAIN5

MAIN6 enters

7-445

8

7.18 Other instructions
7.18.18 Load + Unload (PSWAPP)

Function

Program No.
1
2
3
4
5

7

PSWAPP

(3) Drive Nos. 1, 2, and 4 can be specified. (Drive 3 cannot be specified.)
• Drive 1: Memory card (RAM)
• Drive 2: Memory card (ROM)
• Drive 4: Standard ROM
(4) An extension (.QPG) need not be specified for the file name.
(5) The bit device specified by D is turned ON during the END processing of the scan where
this instruction is completed. The bit device is turned OFF at the next END processing.
(6) The PLOADP, PUNLOADP and PSWAPP instructions cannot be executed simultaneously.
If two or more of the above instructions are executed simultaneously, the instruction
executed later will not be executed.
When using the above instructions, provide interlocks manually to avoid simultaneous
execution.
(7) When the Programmable Controller is powered OFF, then ON or the CPU module is reset
after execution of the PSWAPP instruction, the following operation is performed.
(a) When boot setting has been made in the PLC parameter dialog box, the program where
the boot setting has been made is transferred to the program memory.
When the program replaced by the PSWAPP instruction is to be executed, change the
boot setting and program setting of the PLC parameter dialog box for the corresponding
program name.
(b) When boot setting has not been made in the PLC parameter dialog box, "FILE SET
ERROR (error code: 2400)" occurs.
1) When the program replaced by the PSWAPP instruction is to be executed, change
the program setting of the PLC parameter dialog box for the corresponding program
name.
2) To execute the program set in the program setting of the PLC parameter dialog box,
write the corresponding program to the CPU module again.
(8) Do not execute this instruction in an interrupt program.
(Execution of this instruction in an interrupt program can cause a malfunction.)
(9) The PLC file settings of the program on which the PSWAPP instruction has been conducted
are set as follows:
(a) File usage for each program
All the usage of file register, device initial value, comment, and local device of the
program after the execution of the PSWAPP instruction are set as "Use PLC file
setting".
(b) I/O refresh setting
Nothing is set for both input and output for the I/O refresh setting of the program after
the PSWAPP instruction has been executed.
(10) The "PSWAPP instruction" and "write during RUN" processing cannot be executed
simultaneously.
(a) When a write during RUN request is given during processing of the PSWAPP
instruction, write during RUN is delayed.
Write during RUN is started after the processing of the PSWAPP instruction is
completed.
(b) When the PSWAPP instruction is executed during write during RUN, the processing of
the PSWAPP instruction is delayed.
The processing of the PSWAPP instruction is started after completion of write during
RUN.

7-446

PSWAPP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• The drive No. or the file name designated by

S1

or

S2

does not exist.
(Error code: 2410)

• The drive No. designated by

S1

is invalid.

(Error code: 4100)

• There is not enough memory to load the specified program in drive 0.

1
2
3

(Error code: 2413)
• The program designated by

S1

is not in standby status or is being executed.
(Error code: 4101)

Program Example

6

(1) The following program deletes "EFGH.QPG" stored in drive 0 from the memory, transfers
"ABCD.QPG" stored in drive 4 to drive 0, and places the program in standby status when M0
is turned from OFF to ON.
[Ladder Mode]

4

6

[List Mode]
Step

Instruction

7

Device

8

7.18 Other instructions
7.18.18 Load + Unload (PSWAPP)

7-447

RBMOV(P)

7.18.19

High-speed Block Transfer of File Register (RBMOV(P))

RBMOV(P)

High
performance

Basic

Process Redundant Universal

Command

RBMOV

RBMOV

S

D

n

RBMOVP

S

D

n

Command

RBMOVP
S
D

n
Setting
Data

: Head number of the devices where the data to be transferred is stored (BIN 16 bits)
: Head number of the devices of transfer destination (BIN 16 bits)
: Number of data to be transferred (BIN 16 bits)

Internal Devices
Bit

Word

J

R, ZR

\

Bit

Word

U

Constants
K, H

Zn

\G

Other

S

––

––

D

––

––

n

––

Function
(1) Transfers in batch 16-bit data of n points from the device designated by
points from the device designated by
b15

D

1234H
5678H
7FF0H

S +(n-2)
S +(n-1)

6FFFH
553FH

b15

Block
transfer
n

to location n

.

b0

S
S +1
S +2

S

b0

D
D +1
D +2

1234H
5678H
7FF0H

D +(n-2)
D +(n-1)

6FFFH
553FH

n

(2) The transfer is available even if there is an overlap between the source and destination
devices.
For the transmission to the smaller number of device, the data is transferred from S . For the
transmission to the larger number of device, the data is transferred from S +(n-1).
However, as shown in the example below, when transferring data from R to ZR, or from ZR
to R, the range to be transferred (source) and the range of destination must not overlap.
• ZR transfer range ((specified head No. of ZR) to (specified head No. of ZR + the number
of transfers -1))
R transfer range ((specified head No. of R + file register block No. 32768) to (specified
head No. of R + file register block No. 32768 + the number of transfers -1))

7-448

RBMOV(P)

Example
Transfer ranges of ZR and R overlap when transferring 10000 points of data from ZR30000
(source) to R10 (block No.1 of the destination).
• ZR transfer range

(30000) to (30000+10000-1)

(30000) to (39999)

2

• R transfer range

(10+(1 32768)) to (10+(1 32768)+10000-1)
(32778) to (42777)
Therefore, the range 32778 to 39999 overlaps.
Source of transfer

ZR0

1

3

Destination of transfer
R0

Overlapped

4

Block No. 0

ZR30000

R32767
R10

ZR39999

R10009

6
Block No. 1

6
(3) When S is a word device and D is a bit device, the number of bits designated by the bit
device digit specification will be transferred. If K1Y30 has been designated by D , the lower
four bits of the word device designated by S will be transferred.
S

b15
R100

b4b3b2b1b0
1011

D +2

S +1 R101

0011 n

S +2 R102

0111

D +1

8

D

Y3B Y38Y37 Y34Y33 Y30
011100111011
n

(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
S

or

• The file register is not specified for either

exceeds the corresponding device range.
(Error code: 4101)

D

S

or

D

.

(Error code: 4101)

7-449

7.18 Other instructions
7.18.19 High-speed Block Transfer of File Register (RBMOV(P))

Operation Error

• The device range of n points from

7

RBMOV(P)

Program Example
(1) The following program outputs the lower four bits of data in R66 to R69 to Y30 through Y3F
in units of 4 points.
[Ladder Mode]

[List Mode]
Step

Before execution
(source of transfer)
b15
b4b3 b0
R66
1110 1
R67
00000
R68
10011
R69
0 110 1

Instruction

Device

After execution
(destination of transfer)
1
0
0
1

1
0
0
1

0
0
1
0

1
0
1
1

Y33 to Y30
Y37 to Y34
Y3B to Y38
Y3F to Y3C

Ignored

(2) The following program outputs the data in X20 to X2F to R100 to R103 in units of 4 points.
[Ladder Mode]

[List Mode]
Step

Before
execution

Instruction

Device

X2F X2C X2B X28X27 X24X23 X20
10 0 0 0 1 1 10 1 10 0 10 0

After execution
(destination of transfer)
b15
b4 b3
b0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 R100
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 R101
4 points
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 R102
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 R103
Filled with 0s

7-450

RBMOV(P)

The RBMOV (P) instruction is useful to batch transfer a large quantity of file
register data with the QnHCPU/QnPHCPU/QnPRHCPU.
For the QnUCPU, the processing speed of the RBMOV instruction is equivalent to
that of the BMOV instruction.
The comparison of processing speed between the RBMOV and BMOV
instructions is as follows:
(1)Transfer from file registers to internal devices/internal devices to file registers
CPU

Instruction

RBMOV
QnHCPU
QnPHCPU
QnPRHCPU
BMOV

1 word

Target memory where
file register is stored

Min.

Min.

Max.
775.0 µs

SRAM card

22.0 µs

305.0 µs

2900.0 µs

Flash card *1

22.5 µs

405.0 µs

3950.0 µs

Standard RAM

7.5 µs

76.2 µs

720.0 µs

384.0 µs

3900.0 µs

418.0 µs

4250.0 µs

45.5 µs

215.0 µs

1850.0 µs

49.5 µs

540.0 µs

5150.0µs

17.5 µs

177.0 µs

1700.0 µs

500.0 µs

5050.0 µs

SRAM card

8.0 µs

SRAM card

Standard RAM
SRAM card

18.0 µs

Flash card *1

572.0 µs

7

5800.0 µs

121.5 µs

145.1 µs

1111.5 µs

1135.1 µs

SRAM card*2

-

-

-

-

-

-

Flash card *2

-

-

-

-

-

-

Standard RAM

7.3 µs

13.8 µs

116.5 µs

124.2 µs

1106.5 µs

1114.2 µs

SRAM card*2

-

-

-

-

-

-

Flash card *2

-

-

-

-

-

-

Standard RAM

9.4 µs

31.3 µs

118.5 µs

141.3 µs

1108.5 µs

1131.3 µs

SRAM card

9.4 µs

31.4 µs

178.5 µs

201.3 µs

1708.5 µs

1731.3 µs

Flash card *1

9.4 µs

32.1 µs

278.5 µs

301.3 µs

2708.5 µs

2731.3 µs

Standard RAM

5.0 µs

11.6 µs

114.5 µs

122.3 µs

1104.5 µs

1112.3 µs

SRAM card

5.1 µs

11.7 µs

174.5 µs

182.3 µs

1704.5 µs

1712.3 µs

Flash card *1

5.0 µs

11.6 µs

274.5 µs

282.3 µs

2704.5 µs

2712.3 µs

Standard RAM

11.3 µs

16.8 µs

120.7 µs

127.1 µs

1110.7 µs

1117.1 µs

SRAM card

11.2 µs

16.7 µs

180.7 µs

187.1 µs

1710.7 µs

1717.1 µs

Flash card *1

11.3 µs

16.8 µs

280.7 µs

287.1 µs

2710.7 µs

2717.1 µs

Standard RAM

4.8 µs

6.6 µs

114.7 µs

117.1 µs

1104.7 µs

1107.1 µs

SRAM card

4.8 µs

6.6 µs

147.7 µs

177.1 µs

1704.7 µs

1707.1 µs

Flash card *1

4.8 µs

6.5 µs

274.7 µs

277.1 µs

2704.7 µs

2707.1 µs

Standard RAM

9.2 µs

15.1 µs

61.0 µs

68.6 µs

531.0 µs

538.6 µs

SRAM card

9.4 µs

15.6 µs

165.0 µs

172.6 µs

1576.0 µs

1583.6 µs

Q10UDE(H)CPU

Flash card *1

9.4 µs

15.7 µs

260.0 µs

267.6 µs

2526.0 µs

2533.6 µs

Q13UDE(H)CPU

Standard RAM

4.1 µs

5.6 µs

56.0 µs

58.6 µs

526.0 µs

528.6 µs

SRAM card

4.5 µs

6.1 µs

160.0 µs

162.6 µs

1571.0 µs

1573.6 µs

Flash card *1

4.3 µs

6.2 µs

255.0 µs

257.6 µs

2521.0 µs

2523.6 µs

BMOV

RBMOV
Q02UCPU
BMOV

RBMOV
Q03UD(E)CPU
BMOV

Q04UD(E)HCPU
Q06UDE(H)CPU

Q20UDE(H)CPU
Q26UDE(H)CPU

RBMOV

BMOV

*1 : When file registers are stored in the Flash card, no processing is performed for transfer from
internal devices to file registers.
*2 : Unusable for the Q00UCPU and Q01UCPU.

7-451

8

7.18 Other instructions
7.18.19 High-speed Block Transfer of File Register (RBMOV(P))

34.9 µs

Q01UCPU

4

6

12.2 µs

RBMOV

3

6

Standard RAM

Q00UCPU

2

10000 words

Max.
91.0 µs

Flash card *1

BMOV

Min.

20.0 µs

Standard RAM

QnCPU

Max.

Standard RAM

Flash card *1

RBMOV

1000 words

1

RBMOV(P)

(2)Transfer from file registers to file registers
CPU

QnHCPU

Instruction

RBMOV

QnPHCPU
QnPRHCPU

BMOV

RBMOV
QnCPU
BMOV

RBMOV

1 word

Target memory where
file register is stored

Min.

1000 words
Max.

Min.

10000 words

Max.

Min.

Max.

Standard RAM

20.0 µs

91.0 µs

775.0 µs

SRAM card

22.5 µs

545.0 µs

5300.0 µs

Standard RAM

7.5 µs

77.0 µs

720.0 µs

SRAM card

8.5 µs

692.0 µs

7050.0 µs

Standard RAM

45.5 µs

215.0 µs

1850.0 µs

SRAM card

50.0 µs

870.0 µs

8350.0 µs

Standard RAM

17.5 µs

179.0 µs

1700.0 µs

SRAM card
Standard RAM

18.5 µs
12.6 µs

839.0 µs
35.3 µs

232.5 µs

8600.0 µs

256.1 µs

2211.5 µs

2235.1 µs

Q00UCPU

SRAM card*2

-

-

-

-

-

-

Q01UCPU

Standard RAM

7.7 µs

14.2 µs

227.5 µs

234.2 µs

2206.5 µs

2214.2 µs

BMOV

RBMOV
Q02UCPU
BMOV

RBMOV
Q03UD(E)CPU
BMOV
Q04UD(E)HCPU
Q06UDE(H)CPU

RBMOV

Q10UDE(H)CPU
Q13UDE(H)CPU
Q20UDE(H)CPU
Q26UDE(H)CPU

BMOV

SRAM card*2

-

-

-

-

-

-

Standard RAM

9.6 µs

31.5 µs

228.5 µs

252.3 µs

2208.5 µs

2231.3 µs

SRAM card

9.6 µs

31.5 µs

378.5 µs

401.3 µs

3708.5 µs

3731.3 µs

Standard RAM

5.2 µs

11.8 µs

224.5 µs

232.3 µs

2204.5 µs

2212.3 µs

SRAM card

5.2 µs

11.8 µs

374.5 µs

382.3 µs

3704.5 µs

3712.3 µs

Standard RAM

11.2 µs

16.7 µs

230.7 µs

237.1 µs

2210.7 µs

2217.1 µs

SRAM card

11.6 µs

16.7 µs

380.7 µs

387.1 µs

3710.7 µs

3717.1 µs

Standard RAM

4.9 µs

6.7 µs

224.7 µs

227.1 µs

2204.7 µs

2207.1 µs

SRAM card

5.2 µs

6.7 µs

374.7 µs

377.1 µs

3704.7 µs

3707.1 µs

Standard RAM

9.3 µs

15.5 µs

118.0 µs

124.6 µs

1102.0 µs

1107.6 µs

SRAM card

9.7 µs

15.5 µs

365.0 µs

371.6 µs

3571.0 µs

3578.6 µs

Standard RAM

4.3 µs

6.2 µs

113.0 µs

115.6 µs

1096.0 µs

1098.6 µs

SRAM card

4.5 µs

6.1 µs

360.0 µs

362.6 µs

3566.0 µs

3568.6 µs

*1 : Unusable for the Q00UCPU and Q01UCPU.

7-452

I

INDEX

I

Index-1

[Symbols]
- (BIN 16-bit subtraction operations).................... 6-22
$+ (Linking character strings) ...................... 6-65,6-67
$=, $<>, $>, $<=, $<, $>= (Character string data
comparisons) ....................................................... 6-11
$MOV (Character string transfers) .................... 6-112
* (BIN 16-bit multiplication operations) ................ 6-30
+ (BIN 16-bit addition operations)........................ 6-22
/ (BIN 16-bit division operations) ......................... 6-30
<(BIN 16-bit data comparisons)............................. 6-2
<=(BIN 16-bit data comparisons)........................... 6-2
<>(BIN 16-bit data comparisons)........................... 6-2
=(BIN 16-bit data comparisons)............................. 6-2
>(BIN 16-bit data comparisons)............................. 6-2
>=(BIN 16-bit data comparisons)........................... 6-2
[Numerics]
16-bit data block transfers (FMOV) ......... 6-120,6-122
16-bit data checks (SUM) .................................... 7-69
16-bit data exchange (XCH) .............................. 6-124
16-bit data exclusive NOR operation (WXNR)..... 7-27
16-bit data searches (SER) ................................. 7-66
16-bit dead band controls (BAND)..................... 7-324
16-bit exclusive OR operations (WXOR) ............. 7-19
16-bit negation transfers (CML) ......................... 6-114
16-bit transfers (MOV) ....................................... 6-106
1-bit shift to left of n-bit data (BSFL) ............ 7-49,7-51
1-bit shift to right of n-bit data (BSFR) ......... 7-49,7-51
1-word shift to left of n-word data (DSFL).... 7-54,7-56
1-word shift to right of n-word data (DSFR)
..................................................................... 7-54,7-56
32-bit data checks (DSUM) ................................. 7-69
32-bit data exchanges (DXCH).......................... 6-124
32-bit data exclusive NOR operation (DXNR) ..... 7-27
32-bit data searches (DSER)............................... 7-66
32-bit dead band controls (DBAND) .................. 7-324
32-bit exclusive OR operations (DXOR) .............. 7-19
32-bit negation transfers (DCML) ...................... 6-114
32-bit transfers (DMOV) .................................... 6-106
4-bit dissociation of 16-bit data (DIS) .................. 7-77
4-bit linking of 16-bit data (UNI) ........................... 7-79
7-segment decode (SEG) .................................... 7-75
[A]
A contact operation start (LD)................................ 5-2
A contact parallel connection (OR) ........................ 5-2
A contact series connection (AND)........................ 5-2
ACOS (COS-1 operation on floating-point data (Single
precision)) .......................................................... 7-267
ACOSD (COS-1 operation on floating-point data
(Double precision)) ............................................ 7-269
Addition
Addition of floating decimal point (Double precision)
(ED+)........................................................ 6-50,6-52
Addition of floating decimal point (Single precision)
(E+) .......................................................... 6-46,6-48
BCD 4-digit addition (B+) ................................. 6-34
BCD 8-digit addition (DB+)............................... 6-38

Index - 2

BIN 16-bit addition operations (+) .................... 6-22
BIN 32-bit addition operations (D+).................. 6-26
Block addition (BK+)................................. 6-59,6-62
Addition and subtraction of floating decimal point data
(Double precision) (ED+, ED-) ..................... 6-50,6-52
Addition and subtraction of floating decimal point data
(Single precision) (E+, E-)............................ 6-46,6-48
ADRSET (Indirect address read) ....................... 7-395
ANB (Ladder block series connections)............... 5-10
AND (=, <>, >, <=, <, >=) (BIN 16-bit data
comparisons) ......................................................... 6-2
AND (A contact series connection) ........................ 5-2
AND (D=, D<>, D>, D<=, D<, D>=) (BIN 32-bit data
comparisons) ......................................................... 6-4
AND (E=, E<>, E>, E<=, E<, E>=) (Floationg decimal
point data comparisons(Single precision))............. 6-6
AND (ED=, ED<>, ED>, ED<=, ED<, ED>=) (Floationg
decimal point data comparisons(Double precision))
............................................................................... 6-8
And inverse (ANI) .................................................. 5-3
AND($=, $<>, $>, $<=, $<, $>=) (Character string data
comparisons) ....................................................... 6-11
ANDF (Pulse series connections / trailing edge
leading edg) ..................................................... 5-5,5-7
ANDP (Pulse series connections / leading edge
leading edg) ..................................................... 5-5,5-7
ANDPI, ANDFI ....................................................... 5-8
ANI (B contact series connection) ......................... 5-2
Annunciator output (OUT F) ................................ 5-28
Application instructions ........................................ 2-29
Arithmetic operation instructions.......................... 2-16
ASC (Conversion from hexadecimal BIN to ASCII)
........................................................................... 7-228
ASIN (SIN-1 operation on floating-point data (Single
precision)) .......................................................... 7-262
ASIND (SIN-1 operation on floating-point data (Double
precision)) .......................................................... 7-265
ATAN (TAN-1 operation on floating-point data (Single
precision)) .......................................................... 7-271
ATAND (TAN-1 operation on floating-point data
........................................................................... 7-273
[B]
B- (BCD 4-digit subtraction) ................................. 6-34
B contact operation start (LDI) ............................... 5-2
B* (BCD 4-digit multiplication) ............................. 6-42
B+ (BCD 4-digit addition) ..................................... 6-34
B/ (BCD 4-digit division)....................................... 6-42
BACOS (BCD type COS-1 operation) ................ 7-317
BAND (16-bit dead band controls) ..................... 7-324
Basic instructions ................................................. 2-10
BASIN (BCD type SIN-1 operation).................... 7-315
BATAN (BCD type TAN-1 operation) ................. 7-313
Batch recovery of index register (ZPOP) ........... 7-400
Batch reset of bit devices (BKRST) ..................... 7-64
Batch save of index register (ZPUSH) ............... 7-400
BCD (BIN data to 4-digit) ..................................... 6-73
BCD 4-digit addition and subtraction operations (B+,
B-) ........................................................................ 6-34

BCD 4-digit multiplication and division operations (B*,
B/) ........................................................................ 6-42
BCD 4-digit square roots (BSQR)...................... 7-306
BCD 8-digit addition and subtraction operations (DB+,
DB-) ..................................................................... 6-38
BCD 8-digit multiplication and division operations
(DB*, DB/)............................................................ 6-44
BCD 8-digit square roots (BDSQR) ................... 7-306
BCD conversion
Conversion from BIN data to 4-digit BCD (BCD)
......................................................................... 6-73
Conversion from BIN data to 8-digit BCD (DBCD)
......................................................................... 6-73
BCD type COS operations (BCOS) ................... 7-311
BCD type COS-1 operations (BACOS) .............. 7-317
BCD type SIN operation (BSIN) ........................ 7-309
BCD type SIN-1 operation (BASIN) ................... 7-315
BCD type TAN operation (BTAN) ...................... 7-313
BCD type TAN-1 operations (BATAN) ............... 7-319
BCDDA (Conversion from BCD 4-digit to decimal
ASCII) ................................................................ 7-189
BCOS (BCD type COS operations) ................... 7-311
BDSQR (BCD 8-digit square roots) ................... 7-306
BIN (BCD 4-digit data to BIN data)...................... 6-75
BIN 16-bit addition and subtraction operations (+, -)
............................................................................. 6-22
BIN 16-bit data comparisons (=, <>, >, <=, <, >=)
............................................................................... 6-2
BIN 16-bit data sort operations (SORT) .............. 7-95
BIN 16-bit multiplication and division operations (*, /)
............................................................................. 6-30
BIN 16-bit to BIN 32-bit (DBL) ............................. 6-88
BIN 16-bit to Gray code (GRY)............................ 6-90
BIN 32-bit addition and subtraction operations (D+, D-)
............................................................................. 6-26
BIN 32-bit block data comparisons (DBKCMP …,
DBKCMP … P) .................................................... 6-18
BIN 32-bit data block addition and subtraction
operations (DBK+(P),DBK-(P))............................ 6-62
BIN 32-bit data comparisons (D=, D<>, D>, D<=, D<,
D>=)....................................................................... 6-4
BIN 32-bit data sort operations (DSORT)............ 7-95
BIN 32-bit data to BIN 16-bit data (WORD)......... 6-89
BIN 32-bit data to Gray code (DGRY) ................. 6-90
BIN 32-bit multiplication and division operations (D*,
D/)........................................................................ 6-32
BIN block data comparisons (BKCMP …) ... 6-15,6-18
BINDA (Conversion from BIN 16-bit data to decimal
ASCII) ................................................................ 7-183
BINHA (Conversion from BIN 16-bit data to
hexadecimal ASCII)........................................... 7-186
Bit data .................................................................. 3-3
Bit device output reverse (FF) ............................. 5-40
Bit device shifts (SET) ......................................... 5-44
Bit processing instructions................................... 2-34
Bit reset for word devices (BRST) ....................... 7-59
Bit set for word devices (BSET)........................... 7-59
Bit tests (TEST/DTEST) ...................................... 7-61
BK- (Block subtraction)................................ 6-59,6-62

BK+ (Block addition) .................................... 6-59,6-62
BKAND (Block logical products) ............................ 7-9
BKBCD (Conversion from block BIN 16-bit data to
BCD 4-digit data) ................................................. 6-98
BKBIN (Conversion from block BCD 4-digit data to
block BIN 16-bit data) ........................................ 6-100
BKCMP … (BIN block data comparisons).... 6-15,6-18
BKOR (Block logical sum operations).................. 7-17
BKRST (Batch reset of bit devices) ..................... 7-64
BKXNR (Block exclusive NOR operations).......... 7-33
BKXOR (Block exclusive OR operations) ............ 7-25
Block 16-bit exchanges (BXCH) ........................ 6-126
Block 16-bit transfers (BMOV) ........................... 6-117
Block addition (BK+) .................................... 6-59,6-62
Block exclusive NOR operations (BKXNR).......... 7-33
Block exclusive OR operations (BKXOR) ............ 7-25
Block logical products (BKAND) ............................ 7-9
Block logical sum operations (BKOR).................. 7-17
Block subtraction (BK-) ................................ 6-59,6-62
BMOV (Block 16-bit data transfers) ................... 6-117
BREAK (Forced end of FOR to NEXT instruction loop)
........................................................................... 7-108
BRST (Bit reset for word devices) ....................... 7-59
BSET (Bit set for word devices)........................... 7-59
BSFL (1-bit shift to left of n-bit data) ............ 7-49,7-51
BSFR (1-bit shift to right of n-bit data) ......... 7-49,7-51
BSIN (BCD type SIN operation)......................... 7-309
BSQR (BCD 4-digit square roots)...................... 7-306
BTAN (BCD type TAN operation) ...................... 7-313
BTOW (Data linking in byte units)........................ 7-85
Buffer memory access instructions...................... 2-41
BXCH (Block 16-bit data exchanges) ................ 6-126
[C]
Calculation of averages for 16-bit or 32-bit data
(MEAN(P),DMEAN(P)) ...................................... 7-103
Calculation of totals for 16-bit data (WSUM) ....... 7-99
Calculation of totals for 32-bit data (DWSUM)
................................................................. 7-101,7-103
CALL (Subroutine program calls) ...................... 7-110
Cautions on programming ................................... 3-27
Changing check format of CHK instruction (CHKCIR,
CHKEND) .......................................................... 7-179
Character string data ........................................... 3-11
Character string data comparisons...................... 6-11
Character string length detection (LEN) ............ 7-204
Character string processing instructions.............. 2-43
Character string search (INSTR) ...7-239,7-241,7-243
Character string transfers ($MOV)..................... 6-112
CHKCIR (Changing check format of CHK instruction)
........................................................................... 7-179
CHKEND (Changing check format of CHK instruction)
........................................................................... 7-179
CHKST, CHK (Special format failure checks).... 7-175
CJ (Pointer branch instruction) .......................... 6-129
Clock comparison (TM=,TM,TM>,TM=)............. 7-361
Clock data addition operation (DATE+) ............. 7-348
Clock data subtraction operation (DATE-) ......... 7-350
Clock instructions................................................. 2-52

Index - 3

I

CML (16-bit negation transfers) ......................... 6-114
COM (Refresh instruction) ............. 7-134,7-137,7-141
Common logarithm operation on floating-point data
(Double precision) (LOG10D(P)) ....................... 7-302
Common logarithm operation on floating-point data
(Single precision) (LOG10(P)) ........................... 7-300
Comparison operation instruction table ............... 2-10
Comparison operation instructions ........................ 6-2
Comparisons (BIN 16-bit data) .............................. 6-2
Comparisons (BIN 32-bit data) .............................. 6-4
Comparisons (Character string data) .................. 6-11
Complement of 2 of BIN 16-bit data (NEG) ......... 6-94
Complement of 2 of BIN 32-bit data (DNEG) ...... 6-94
COMRD (Reading device comment data) ......... 7-201
Conditions for execution of instructions ............... 3-33
Connection instructions
Association instruction table............................... 2-7
Ladder block parallel connection (ORB) .......... 5-10
Ladder block series connection (ANB)............. 5-10
Linking character strings ($+)........................... 6-65
Contact instruction ................................................. 2-6
Contact instructions
Operation start (LD, LDI).................................... 5-2
Parallel connection (OR, ORI)............................ 5-2
Pulse operation start (LDF, LDP) ................. 5-5,5-7
Pulse parallel connection (ORF,ORP) ......... 5-5,5-7
Pulse serial connection (ANF, ANP) ............ 5-5,5-7
Series connection (AND, ANI)............................ 5-2
Conversion
BCD 4-digit to BIN (BIN) .................................. 6-75
BCD 8-digit to BIN (DBIN)................................ 6-75
BIN 16-bit to BIN 32-bit (DBL).......................... 6-88
BIN 16-bit to floating decimal point (Double
precision) (FLTD) ............................................. 6-81
BIN 16-bit to floating decimal point (Single
precision) (FLT)................................................ 6-78
BIN 16-bit to Gray code (GRY) ........................ 6-90
BIN 32-bit to BIN 16-bit (WORD) ..................... 6-89
BIN 32-bit to floating decimal point (Double
precision) (DFLTD)........................................... 6-81
BIN 32-bit to floating decimal point (Single
precision) (DFLT) ............................................. 6-78
BIN 32-bit to Gray code (DGRY)...................... 6-90
BIN to BCD 4-digit (BCD)................................. 6-73
BIN to BCD 8-digit (DBCD) .............................. 6-73
Double precision to Single precision (EDCON)
....................................................................... 6-104
Floating decimal point data to BIN 16-bit (Double
precision) (INTD).............................................. 6-86
Floating decimal point data to BIN 16-bit (Single
precision) (INT) ................................................ 6-83
Floating decimal point data to BIN 32-bit (Single
precision) (DINT).............................................. 6-83
Floating decimal point data to BIN32-bit (Double
precision) (DINTD) ........................................... 6-86
Gray code to BIN 16-bit (GBIN) ....................... 6-92
Gray code to BIN 32-bit (DGBIN)..................... 6-92
Single precision to Double precision (ECON)
....................................................................... 6-102

Index - 4

Conversion from ASCII to hexadecimal BIN (HEX)
........................................................................... 7-230
Conversion from BCD 4-digit to decimal ASCII
(BCDDA) ............................................................ 7-189
Conversion from BCD 8-digit to decimal ASCII
(DBCDDA) ......................................................... 7-189
Conversion from BIN 16-bit to character string (STR)
........................................................................... 7-206
Conversion from BIN 16-bit to decimal ASCII (BINDA)
........................................................................... 7-183
Conversion from BIN 16-bit to floating decimal point
(Double precision) (FLTD) ................................... 6-81
Conversion from BIN 16-bit to floating decimal point
(Single precision) (FLT) ....................................... 6-78
Conversion from BIN 16-bit to hexadecimal ASCII
(BINHA) ............................................................. 7-186
Conversion from BIN 32-bit to character string (DSTR)
........................................................................... 7-206
Conversion from BIN 32-bit to decimal ASCII
(DBINDA) ........................................................... 7-183
Conversion from BIN 32-bit to floating decimal point
(Double precision) (DFLTD)................................. 6-81
Conversion from BIN 32-bit to floating decimal point
(Single precision) (DFLT)..................................... 6-78
Conversion from BIN 32-bit to hexadecimal ASCII
(DBINHA) ........................................................... 7-186
Conversion from block BCD 4-digit data to block BIN
16-bit data (BKBIN)............................................ 6-100
Conversion from block BIN 16-bit data to BCD 4-digit
data (BKBCD) ...................................................... 6-98
Conversion from character string to BIN 16-bit (VAL)
........................................................................... 7-212
Conversion from character string to BIN 32-bit (DVAL)
........................................................................... 7-212
Conversion from character string to floating decimal
point (EVAL) ...................................................... 7-224
Conversion from decimal ASCII to BCD 4-digit
(DABCD) ............................................................ 7-198
Conversion from decimal ASCII to BCD 8-digit
(DDABCD) ......................................................... 7-198
Conversion from decimal ASCII to BIN 16-bit (DABIN)
........................................................................... 7-192
Conversion from decimal ASCII to BIN 32-bit
(DDABIN) ........................................................... 7-192
Conversion from floating decimal point to character
string (ESTR) ..................................................... 7-217
Conversion from floating-point angle to radian (Double
precision) (RADD).............................................. 7-277
Conversion from floating-point angle to radian (Single
precision) (RAD) ................................................ 7-275
Conversion from floating-point radian to angle (Double
precision) (DEGD) .........................7-281,7-283,7-285
Conversion from floating-point radian to angle (Single
precision) (DEG) ................................................ 7-279
Conversion from hexadecimal ASCII to BIN 16-bit
(HABIN) ............................................................. 7-195
Conversion from hexadecimal ASCII to BIN 32-bit
(DHABIN) ........................................................... 7-195

Conversion from hexadecimal BIN to ASCII (ASC)
........................................................................... 7-228
Conversion of Gray code to BIN 16-bit (GBIN).... 6-92
Conversion of Gray code to BIN 32-bit (DGBIN)
............................................................................. 6-92
Conversion to BIN
BCD 4-digit to BIN 16-bit (BIN) ........................ 6-75
BCD 8-digit to BIN 32-bit (DBIN)...................... 6-75
Floating decimal point data to BIN 16-bit (Double
precision) (INTD).............................................. 6-86
Floating decimal point data to BIN 16-bit (Single
precision) (INT) ................................................ 6-83
Floating decimal point data to BIN 32-bit (Double
precision) (DINTD) ........................................... 6-86
Floating decimal point data to BIN 32-bit (Single
precision) (DINT).............................................. 6-83
Conversion to floating decimal point (Double
precision) (FLTD, DFLTD) ................................... 6-81
Conversion to floating decimal point (Single precision)
(FLT, DFLT)......................................................... 6-78
COS (COS operation on floating-point data (Single
precision)).......................................................... 7-254
COS operation on floating-point data (Double
precision) (COSD) ............................................. 7-256
COS operation on floating-point data (Single
precision) (COS)................................................ 7-254
COS-1 operation on floating-point data (Double
precision) (ACOSD)........................................... 7-269
COS-1 operation on floating-point data (Single
precision) (ACOS) ............................................. 7-267
COSD (COS operation on floating-point data (Double
precision)).......................................................... 7-256
Count 1-phase input or down (UDCNT1) .......... 6-143
Count 2-phase input or down (UDCNT2) .......... 6-146
Counters (OUT C) ............................................... 5-26
[D]
D- (BIN 32-bit subtraction operations .................. 6-26
D(P).DDRD(Reading Devices to Another CPU)
........................................................................... 10-17
D(P).DDWR(Writing Devices to Another CPU)
........................................................................... 10-13
D* (BIN 32-bit multiplication operations).............. 6-32
D+ (BIN 32-bit addition operations) ..................... 6-26
D/ (BIN 32-bit division operations)....................... 6-32
D=, D<>, D>, D<=, D<, D>= (BIN 32-bit data
comparisons) ......................................................... 6-4
DABCD (Conversion from decimal ASCII to BCD
4-digit)................................................................ 7-198
DABIN (Conversion from decimal ASCII to BIN 16-bit)
........................................................................... 7-192
DAND (Logical products with 32-bit data) ............. 7-3
Data control instructions ...................................... 2-49
Data conversion instruction table ........................ 2-22
Data conversion instructions ............................... 6-73
Data dissociation in byte units (WTOB)............... 7-85
Data link instructions ........................................... 2-59
Data linking in byte units (BTOW) ....................... 7-85
Data processing instructions ............................... 2-35

Data table operation instructions ......................... 2-40
DATE- (Clock data subtraction operation) ......... 7-350
Date comparison (DT=,DT,DT>,DT=)................ 7-356
DATE+ (Clock data addition operation) ............. 7-348
DATERD (Reading clock data) .......................... 7-344
DATEWR (Writing clock data) ........................... 7-346
DB- (BCD 8-digit subtraction) .............................. 6-38
DB* (BCD 8-digit multiplication)........................... 6-44
DB+ (BCD 8-digit addition) .................................. 6-38
DB/ (BCD 8-digit division) .................................... 6-44
DBAND (32-bit dead band controls) .................. 7-324
DBCD (Conversion from BIN to BCD 8-digit) ...... 6-73
DBCDDA (Conversion from BCD 8-digit to decimal
ASCII) ................................................................ 7-189
DBIN (BCD 8-digit to BIN 16-bit conversion) ....... 6-75
DBINDA (Conversion from BIN 32-bit to decimal
ASCII) ................................................................ 7-183
DBINHA (Conversion from BIN 32-bit to hexadecimal
ASCII) ................................................................ 7-186
DBK- .................................................................... 6-63
DBK+ ................................................................... 6-62
DBL (BIN 16-bit to BIN 32-bit) ............................. 6-88
DCML (32-bit negation transfers) ...................... 6-114
DDABCD (Conversion from decimal ASCII to BCD
8-digit)................................................................ 7-198
DDABIN (Conversion from decimal ASCII to BIN
32-bit)................................................................. 7-192
DDEC (Decrementing 32-bit BIN)........................ 6-71
Debugging and failure diagnosis instructions ...... 2-42
DEC (Decrementing 16-bit BIN) .......................... 6-69
DECO (Decoding from 8 to 256 bits) ................... 7-71
Decoding from 8 to 256 bits (DECO) ................... 7-71
Decrement
BIN 16-bit (DEC) .............................................. 6-69
BIN 32-bit (DDEC)............................................ 6-71
Decrementing 16-bit BIN (DEC) .......................... 6-69
Decrementing 32-bit BIN (DDEC)........................ 6-71
DEG (Conversion from floating-point radian to angle
(Single precision)).............................................. 7-279
DEGD (Conversion from floating-point radian to angle
(Double precision)) ........................7-281,7-283,7-285
Deleting data from data tables (FDEL) .............. 7-157
Deletion of character string (STRDEL(P)) ......... 7-243
DELTA (Pulse conversion of direct output).......... 5-42
Designating data.................................................... 3-3
Designation of modification values in index
modification (IXDEV, IXSET) ............................. 7-148
Device range check ............................................. 3-27
DFLT (Conversion from BIN 32-bit to floating decimal
point (Single precision)) ....................................... 6-78
DFLTD (Conversion from BIN 32-bit to floating
decimal point (Double precision)) ........................ 6-81
DFRO (Reading 2-word data from intelligent function
modules) ............................................................ 7-160
DGBIN (Conversion of Gray code to BIN 16-bit)
............................................................................. 6-92
DGRY (BIN 32-bit to Gray code) ......................... 6-90
DHABIN (Conversion from hexadecimal ASCII to BIN
32-bit)................................................................. 7-195

Index - 5

I

DI (Interrupt disable) .......................................... 6-133
Digit designation .................................................... 3-4
Digit designation of bit devices .............................. 3-4
DINC (Incrementing 32-bit BIN)........................... 6-71
DINT (Floating decimal point data to BIN 32-bit (Single
precision)) ............................................................ 6-83
DINTD (Floating decimal point data to BIN 32-bit
(Double precision)) .............................................. 6-86
Direct 1-byte read from file register (ZRRDB).... 7-391
DIS (4-bit grouping of 16-bit data) ....................... 7-77
Display instructions.............................................. 2-41
Dissociation of random data (NDIS) .................... 7-81
Division
BCD 4-digit (B/) ................................................ 6-42
BCD 8-digit division (DB/) ................................ 6-44
BIN 16-bit (/)..................................................... 6-30
Division of floating decimal point(Double precision)
(ED/)................................................................. 6-56
Division of floating decimal point(Single precision)
(E/) ................................................................... 6-54
DLIMIT (Upper and lower limit controls for BIN 32-bit)
........................................................................... 7-321
DMAX (Maximum value search for 32-bit data)... 7-89
DMEAN(P) ......................................................... 7-103
DMIN (Minimum value search for 32-bit data) ..... 7-92
DMOV (32-bit transfers) .................................... 6-106
DNEG (Complement of 2 of BIN 32-bit data) ...... 6-94
DOR (Logical sums of 32-bit data) ...................... 7-11
Double precision to Single precision conversion
(EDCON) ........................................................... 6-104
Double word data .................................................. 3-6
DRCL (Left rotation of 32-bit data) ...................... 7-44
DRCR (Right rotation of 32-bit data) ................... 7-41
DROL (Left rotation of 32-bit data) ...................... 7-44
DROR (Right rotation of 32-bit data) ................... 7-41
DSCL(P) ............................................................ 7-331
DSCL2(P) .......................................................... 7-335
DSER (32-bit data searches)............................... 7-66
DSFL (1-word shift to left of n-word data).... 7-54,7-56
DSFR (1-word shift to right of n-word data)
..................................................................... 7-54,7-56
DSORT (BIN 32-bit data sort).............................. 7-95
DSTR (Conversion from BIN 32-bit to character string)
........................................................................... 7-206
DSUM (32-bit data checks) ................................. 7-69
DTEST (Bit tests)................................................. 7-61
DTO (Writing 2-word data to intelligent function
modules) ............................................................ 7-163
DUTY (Timing pulse generation) ....................... 7-388
DVAL (Conversion from character string to BIN 32-bit)
........................................................................... 7-212
DWSUM (Calculation of totals for 32-bit data)
................................................................. 7-101,7-103
DXCH (16-bit data exchanges).......................... 6-124
DXNR (32-bit data exclusive NOR operation) ..... 7-27
DXOR (32-bit exclusive OR operations) .............. 7-19
DZONE (Zone control for BIN 32-bit data)
....................................................... 7-327,7-330,7-334

Index - 6

[E]
E- (Subtraction of floating decimal point data (Single
precision)) .................................................... 6-46,6-48
E* (Multiplication of floating decimal point data (Single
precision)) ............................................................ 6-54
E+ (Addition of floating decimal point data (Single
precision)) .................................................... 6-46,6-48
E/ (Dividion of floating decimal point data (Single
precision)) ............................................................ 6-54
E=, E<>, E>, E<=, E<, E>= (Floationg decimal point
data comparisons(Single precision)) ..................... 6-6
ECALL (Sub-routine calls between program files)
........................................................................... 7-120
ECON (Single precision to Double precision
conversion) ........................................................ 6-102
ED- (Subtraction of floating decimal point data
(Double precision)) ...................................... 6-50,6-52
ED* (Multiplication of floating decimal point data
(Double precision)) .............................................. 6-56
ED+ (Addition of floating decimal point data (Double
precision)) .................................................... 6-50,6-52
ED/ (Dividion of floating decimal point data (Double
precision)) ............................................................ 6-56
ED=,ED<>,ED>,ED<=,ED<,ED>= (Floationg decimal
point data comparisons (Double precision)) .......... 6-8
EDCON (Double precision to Single precision
conversion) ........................................................ 6-104
EDMOV (Floating-point data transfer (Double
precision)) .......................................................... 6-110
EDNEG (Floating-point sign invertion (Double
precision)) ............................................................ 6-97
EFCALL (Output OFF calls between program files)
........................................................................... 7-125
EGF (Pulse operation results / leading edge) ...... 5-18
EGP (Pulse operation results / trailing edge)....... 5-18
EI (Interrupt enable) ........................................... 6-133
EMOD (Floating decimal point to BCD) ............. 7-245
EMOV (Floating-point data transfer (Single precision))
........................................................................... 6-108
ENCO (Encoding from 256 to 8 bits) ................... 7-73
Encoding from 256 to 8 bits (ENCO) ................... 7-73
END (End sequence program) ............................ 5-53
End main routine program (FEND) ...................... 5-51
End sequence program (END) ............................ 5-53
ENEG (Floating-point sign invertion(Single precision))
............................................................................. 6-96
EREXP (From BCD format data to floating decimal
point).................................................................. 7-248
Error display and annunciator reset instruction (LEDR)
........................................................................... 7-172
ESTR (Conversion from floating decimal point to
character string) ................................................. 7-217
EVAL (Conversion from character string to floating
decimal point) .................................................... 7-217
EXP (Exponent operation on floating-point data
(Single precision)) .............................................. 7-291
Expansion clock data addition operation (S.DATE+)
........................................................................... 7-366

Expansion clock data subtraction operation (S.DATE-)
........................................................................... 7-366
EXPD (Exponent operation on floating-point data
(Double precision)) ............................................ 7-294
Exponent operation on floating-point data (Double
precision) (EXPD).............................................. 7-294
Exponent operation on floating-point data (Single
precision) (EXP) ................................................ 7-291
Exponentiation operation on floating-point data
(Single precision) (POW(P)) .............................. 7-283
Exponentiation operation on floating-point data
(Single precision) (POWD(P)) ........................... 7-285
Extracting character string data from the left (LEFT)
........................................................................... 7-232
Extracting character string data from the right (RIGHT)
........................................................................... 7-232
[F]
FCALL (Subroutine program output OFF calls)
........................................................................... 7-116
FDEL (Deleting data from data tables) .............. 7-157
FEND (End main routine program)...................... 5-51
FF (Bit device output reverse) ............................. 5-40
FIFR (Reading oldest data from data tables) .... 7-153
FIFW (Writing data to the data tables)............... 7-151
File register direct 1-byte write (ZRWRB).......... 7-393
File setting for comments (QCDSET) ................ 7-342
FINS (Inserting data in data tables)................... 7-157
Fixed cycle pulse output (PLSY) ....................... 6-162
Floating decimal point data comparisons (Double
precision) (ED=, ED<>, ED>, ED<=, ED<, ED>=)
............................................................................... 6-8
Floating decimal point data comparisons (Single
precision) (E=, E<>, E>, E<=, E<, E>=) ................ 6-6
Floating decimal point to BCD (EMOD)............. 7-245
Floating-point data transfer (Double precision)
(EDMOV) ........................................................... 6-110
Floating-point data transfer (Single precision) (EMOV)
........................................................................... 6-108
Floating-point sign invertion (Double precision)
(EDNEG) ............................................................. 6-97
Floating-point sign invertion (Single precision) (ENEG)
............................................................................. 6-96
FLT (Conversion from BIN 16-bit to floating decimal
point (Single precision))....................................... 6-78
FLTD (Conversion from BIN 16-bit to floating decimal
point (Double precision)) ..................................... 6-81
FMOV (16-bit data block transfers) ......... 6-120,6-122
FOR (FOR to NEXT) ......................................... 7-105
FOR to NEXT (FOR, NEXT).............................. 7-105
Forced end of FOR to NEXT instruction loop (BREAK)
........................................................................... 7-108
FPOP (Reading newest data from data tables)
........................................................................... 7-155
FROM (Reading from other CPU shared memory)
............................................................................. 9-12
FROM (Reding 1-word data from intelligent function
modules)............................................................ 7-160

From BCD format data to floating decimal point
(EREXP) ............................................................ 7-248
[G]
GBIN (Conversion of Gray code to BIN 16-bit).... 6-92
GOEND (Jump to END)..................................... 6-132
GRY (BIN 16-bit to Gray code) ............................ 6-90
[H]
HABIN (Conversion from hexadecimal ASCII to BIN
16-bit)................................................................. 7-195
HEX (Conversion from ASCII to hexadecimal BIN)
........................................................................... 7-230
High speed retentive timer (OUTH ST)................ 5-22
High speed timer (OUTH T)................................. 5-22
High-speed block transfer of file register (RBMOV)
........................................................................... 7-448
HOUR (Time data conversion) .......................... 7-354
How to read instruction tables ............................... 2-4
How to read instructions ........................................ 4-2
[I]
I/O refrech (RFS) ............................................... 6-141
I/O refresh instruction table.................................. 2-27
Identical 32-bit data block transfers (DFMOV(P))
........................................................................... 6-122
IMASK (Interrupt program mask)....................... 6-133
INC (Incrementing 16-bit BIN) ............................. 6-69
Increment
BIN 16-bit (INC)................................................ 6-69
BIN 32-bit (DINC) ............................................. 6-71
Incrementing 16-bit BIN (INC) ............................. 6-69
Incrementing 32-bit BIN (DINC)........................... 6-71
Index modification................................................ 3-12
Indirect address read (ADRSET) ....................... 7-395
Indirect specification ............................................ 3-23
Inserting data in data tables (FINS) ................... 7-157
Insertion of character string (STRINS(P)).......... 7-241
INSTR (Character string search) ...7-239,7-241,7-243
Instructions for data link....................................... 2-59
INT (Floating decimal point data to BIN 16-bit (Single
precision)) ............................................................ 6-83
INTD (Floating decimal point data to BIN 16-bit
(Double precision)) .............................................. 6-86
Interrupt disable (DI) .......................................... 6-133
Interrupt enable (EI)........................................... 6-133
Interrupt program mask (IMASK)....................... 6-133
INV (Operation results inversion)......................... 5-15
Inversion
Bit device output reverse (FF).......................... 5-40
Operation results inversion (INV) ..................... 5-15
IRET (Recovery from interrupt programs) ......... 6-139
IX, IXEND (Index modification of entire ladder)
........................................................................... 7-144
IXDEV (Designation of modification values in index
modification) ...................................................... 7-148
IXSET (Designation of modification values in index
modification) ...................................................... 7-148

Index - 7

I

[J]
JMP (Pointer branch)......................................... 6-129
Jump to END (GOEND)..................................... 6-132
[K]
KEY (Numerical key input from keyboard)......... 7-396
[L]
Ladder block parallel connections (ORB) ............ 5-10
Ladder block series connections (ANB) .............. 5-10
LD ($=, $<>, $>, $<=, $<, $>=) (Character string data
comparisons) ....................................................... 6-11
LD (=, <>, >, <=, <, >=) (BIN 16-bit data comparisons)
............................................................................... 6-2
LD (A contact operation start)................................ 5-2
LD (D=, D<>, D>, D<=, D<, D>=) (BIN 32-bit data
comparisons) ......................................................... 6-4
LD (E=, E<>, E>, E<=, E<, E>=) (Floationg decimal
point data comparisons(Single precision)) ............ 6-6
LD (ED=, ED, ED>, ED<=, ED<, ED>=) (Floationg
decimal point data comparisons(Double precision))
............................................................................... 6-8
LDF (Pulse operation start / trailing edge) ....... 5-5,5-7
LDI (B contact operation start)............................... 5-2
LDP (Pulse operation start / leading edge)...... 5-5,5-7
LDPI, LDFI ............................................................. 5-7
Leading edge output (PLS).................................. 5-37
LEDR (Error display and annunciator reset instruction)
........................................................................... 7-172
LEFT (Extracting character string data from the left)
........................................................................... 7-232
Left rotation of 16-bit data (ROL, RCL)................ 7-38
Left rotation of 32-bit data (DROL, DRCL) .......... 7-44
LEN (Character string length detection) ............ 7-204
LIMIT (Upper and lower limit controls for BIN 16-bit)
........................................................................... 7-321
Link refresh instructions....................................... 2-59
Linking character strings ($+) ...................... 6-65,6-67
Linking of random data (NUNI) ............................ 7-81
Load (LD)............................................................... 5-2
Load + unload (PSWAPP) ................................. 7-445
Load inverse (LDI) ................................................. 5-2
Load program from Memory Card (PLOADP) ... 7-440
LOG (Natural logarithm operation on floating-point
data (Single precision))............................ 7-296,7-302
LOGD (Natural logarithm operation on floating-point
data (Double precision)) .................................... 7-298
Logical operation instructions .............................. 2-29
Logical product ...................................................... 7-2
Logical products with 16-bit data (WAND)............. 7-3
Logical products with 32-bit data (DAND) ............. 7-3
Logical sum ........................................................... 7-2
Logical sums of 16-bit data (WOR) ..................... 7-11
Logical sums of 32-bit data (DOR) ...................... 7-11
Low speed retentive timer (OUTH ST) ................ 5-22
Low speed timer (OUT T) .................................... 5-22

Index - 8

[M]
Master control instructions ................................... 5-47
Matrix input (MTR) ............................................. 6-166
MAX (Maximum value search for 16-bit data) ..... 7-89
Maximum value search for 16-bit data (MAX) ..... 7-89
Maximum value search for 32-bit data (DMAX) ... 7-89
MC (Setting the master control) ........................... 5-47
MCR (Resetting the master control) .................... 5-47
MEAN(P)............................................................ 7-103
MEF (Pulse operation results / trailing edge)....... 5-17
MEP (Pulse operation results / leading edge) ..... 5-17
MIDR (Random selection from character strings)
........................................................................... 7-235
MIDW (Random replacement in character strings)
........................................................................... 7-235
MIN (Minimum value search for 16-bit data)........ 7-92
Minimum value search for 16-bit data (MIN)........ 7-92
Minimum value search for 32-bit data (DMIN) ..... 7-92
MOV (16-bit transfers) ....................................... 6-106
MPP (Operation results pop) ............................... 5-12
MPS (Operation results push) ............................. 5-12
MRD (Operation results read).............................. 5-12
MTR (Matrix input) ............................................. 6-166
Multiplication
BCD 4-digit (B*)................................................ 6-42
BCD 8-digit (DB*) ............................................. 6-44
BIN 16-bit (*) .................................................... 6-30
BIN 32-bit (D*) .................................................. 6-32
Multiplication of floating decimal point (Double
precision) (ED*) ................................................ 6-56
Multiplication of floating decimal point (Single
precision) (E*) .................................................. 6-54
Multiplication and division of floating decimal point
(Double precision)(ED*, ED/) ............................... 6-56
Multiplication and division of floating decimal point
(Single precision)(E*, E/) ..................................... 6-54
[N]
Natural logarithm operation on floating-point data
(Double precision) (LOGD) ................................ 7-298
Natural logarithm operation on floating-point data
(Single precision) (LOG) .......................... 7-296,7-302
n-bit shift to left of 16-bit data (SFL) .................... 7-46
n-bit shift to right of 16-bit data (SFR).................. 7-46
n-bit shift to right or left of n-bit data (SFTBR(P),
SFTBL(P))............................................................ 7-51
n-bit shift to right or left of n-word data (SFTWR(P),
SFTWL(P))........................................................... 7-56
NEG (complement of 2 of BIN 16-bit data) .......... 6-94
Network refresh instruction (ZCOM) ...................... 8-2
NEXT (FOR to NEXT)........................................ 7-105
No operation (NOP, NOPLF, PAGE) ................... 5-57
NOP ..................................................................... 5-57
NOP (No operation) ............................................. 5-57
NOPLF (No operation page change) ................... 5-57
Number of steps .................................................. 3-34
Numerical key input (KEY)................................. 7-396
Numerical key input from keyboard (KEY)......... 7-396
NUNI (Linking of random data) ............................ 7-81

[O]
Operation errors .................................................. 3-27
Operation results inversion (INV) ........................ 5-15
Operation results pop (MPP) ............................... 5-12
Operation results push (MPS) ............................. 5-12
Operation results read (MRD) ............................. 5-12
Operation start (LD, LDI) ....................................... 5-2
OR ($=, $<>, $>, $<=, $<, $>=) (Character string data
comparisons) ....................................................... 6-11
OR (=, <>, >, <=, <, >=) (BIN 16-bit data comparisons)
............................................................................... 6-2
OR (A contact parallel connection)........................ 5-2
OR (D=, D<>, D>, D<=, D<, D>=) (BIN 32-bit data
comparisons) ......................................................... 6-4
OR (E=, E<>, E>, E<=, E<, E>=) (Floationg decimal
point data comparisons (Single precision)) ........... 6-6
OR (ED=, ED<>, ED>, ED<=, ED<, ED>=) (Floationg
decimal point data comparisons (Double precision))
............................................................................... 6-8
Or inverse (ORI) .................................................... 5-2
ORB (Ladder block parallel connections) ............ 5-10
ORF (Pulse parallel connection / trailing edge)
......................................................................... 5-5,5-7
ORI (B contact parallel connection)....................... 5-2
ORP (Pulse parallel connection / leading edge)
......................................................................... 5-5,5-7
ORPI, ORFI ........................................................... 5-8
Other convenient instructions ................................ 2-6
Other instructions ................................................ 5-55
Application instructions .................................... 2-29
Sequence instructions........................................ 2-6
OUT
Annunciator output (OUT F)............................. 5-28
Counters (OUT C)............................................ 5-26
High speed retentive timer (OUTH ST)............ 5-22
High speed timer (OUTH T) ............................. 5-22
Low speed retentive timer (OUT ST) ............... 5-22
Low speed timer (OUT T) ................................ 5-22
Output (OUT) ................................................... 5-20
Out instructions (OUT)......................................... 5-20
Output instruction table.......................................... 2-8
Output instructions (OUT).................................... 5-20
Output of sub-routine program OFF calls (FCALL)
........................................................................... 7-116
Output OFF calls between program files (EFCALL)
........................................................................... 7-125
Output reverse (FF) ............................................. 5-40
[P]
PAGE (No operation page change)..................... 5-57
Page change (NOPLF) ........................................ 5-57
Page change (PAGE n) ....................................... 5-57
Parallel connection (OR, ORI) ............................... 5-2
Parallel connections (ORB) ................................. 5-10
PCHK (Program low speed execution registeration
instruction) ......................................................... 7-384
PLF (Trailing edge output)................................... 5-37
PLOADP (Load program from Memory Card) ... 7-440

PLOW (Program low speed execution registration)
........................................................................... 7-382
PLS (Leading edge output).................................. 5-37
PLSY (Fixed cycle pulse output)........................ 6-162
POFF (Program output OFF standby instruction)
........................................................................... 7-378
Pointer branching instruction (CJ, SCJ, JMP) ... 6-129
Pop (MPP) ........................................................... 5-12
PR (Print ASCII code instruction) ...................... 7-166
PRC (Print comment instruction) ....................... 7-169
Print ASCII code instruction (PR) ...................... 7-166
Print comment instruction (PRC) ....................... 7-169
Program branch instruction table......................... 2-27
Program control instructions ................................ 2-56
Program execution control instruction table......... 2-27
Program low speed execition registration instruction
(PCHK) .............................................................. 7-384
Program low speed execution registration (PLOW)
........................................................................... 7-382
Program output OFF standby instruction (POFF)
........................................................................... 7-378
Program scan execution registration instruction
(PSCAN) ............................................................ 7-380
Program standby instruction (PSTOP) .............. 7-377
PSCAN (Program scan execution registration
instruction) ......................................................... 7-380
PSTOP (Program standby instruction) .............. 7-377
PSWAPP (Load + unload) ................................. 7-445
Pulse conversion
(DELTA) ........................................................... 5-42
(EGF, EGP)...................................................... 5-18
(MEF, MEP) ..................................................... 5-17
Pulse conversion of direct output (DELTA).......... 5-42
Pulse density measurement (SPD).................... 6-160
Pulse NOT operation start, pulse NOT series
connection, pulse NOT parallel connection LDPI,LDFI,
ANDPI,ANDFI,ORPI,ORFI) ................................... 5-7
Pulse operation results
Operation result conversions (MEF, MEP)....... 5-17
Pulse conversions of edge relay operation results
(EGF, EGP)...................................................... 5-18
Pulse operation start (LDF, LDP)..................... 5-5,5-7
Pulse parallel connection (ORF, ORP) ............ 5-5,5-7
Pulse series connection (ANDF, ANDP)................ 5-5
Pulse width modulation (PWM).......................... 6-164
PUNLOADP (Unload program from program memory)
........................................................................... 7-443
Push (MPS) ......................................................... 5-12
PWM (Pulse width modulation).......................... 6-164
[Q]
QCDSET (File setting for comments) ................ 7-342
QCPU dedicated instructions............................... 2-60
QDRSET(Setting files for file register use) ........ 7-339
[R]
RAD (Conversion from floating-point angle to radian
(Single precision)).............................................. 7-275

Index - 9

I

RADD (Conversion from floating-point angle to radian
(Double precision)) ............................................ 7-277
RAMP (Ramp signal) ......................................... 6-157
Ramp signal (RAMP) ......................................... 6-157
Random number generation (RND/SRND)........ 7-304
Random selection from and replacement in character
strings (MIDR) ................................................... 7-235
Random selection replacement in character strings
(MIDW) .............................................................. 7-235
RBMOV (High-speed block transfer of file register)
........................................................................... 7-448
RCL (Left rotation of 16-bit data) ......................... 7-38
RCR (Right rotation of 16-bit data) ...................... 7-35
Read (MRD) ........................................................ 5-12
Read data from standard ROM (S.DEVLD)....... 7-438
Reading 1-word data from intelligent function modules
(FROM).............................................................. 7-160
Reading 2-word data from intelligent function modules
(DFRO) .............................................................. 7-160
Reading clock data (DATERD) .......................... 7-344
Reading data from designated file (SP.FREAD) 7-424
Reading device comment data (COMRD) ......... 7-201
Reading expansion clock data (S.DATERD) ..... 7-366
Reading from other CPU shared memory (FROM)
............................................................................. 9-12
Reading module information (UNIRD) ............... 7-402
Reading newest data from data tables (FPOP)
........................................................................... 7-155
Reading oldest data from data tables (FIFR) .... 7-153
Reading routing information (RTREAD) ................ 8-6
Real number data .................................................. 3-8
Recovery from interrupt programs (IRET) ......... 6-139
Refresh instruction (COM) ................................. 7-134
Related programming manuals ............................. 1-2
Resetting devices (RST).............................. 5-32,5-35
Resetting the annunciators (RST F) .................... 5-35
Resetting the master control (MCR) .................... 5-47
Resetting watchdog timer (WDT) ...................... 7-386
RET (Return from sub-routine programs) .......... 7-115
Return from sub-routine programs (RET) .......... 7-115
Revercing
Bit device output reverse (FF).......................... 5-40
Floating-point sign invertion (Double precision)
(EDNEG) .......................................................... 6-97
Floating-point sign invertion (Single precision)
(ENEG)............................................................. 6-96
Operation results inversion (INV) ..................... 5-15
RFS (I/O refresh) ............................................... 6-141
RIGHT (Extracting character string data from the right)
........................................................................... 7-232
Right rotation of 16-bit data (ROR, RCR) ............ 7-35
Right rotation of 32-bit data (DROR, DRCL)........ 7-41
RND (Random number generation and series update)
........................................................................... 7-304
ROL (Left rotation of 16-bit data) ......................... 7-38
ROR (Right rotation of 16-bit data) ...................... 7-35
Rotary table shortest direction control (ROTC)
........................................................................... 6-154
Rotation instructions ............................................ 2-32

Index - 10

ROTC (Rotary table shortest direction control)
........................................................................... 6-154
RSET (Switching file register numbers) ............. 7-337
RST
Resetting devices (RST) .................................. 5-32
Resetting the annunciators (RST F)................. 5-35
RTREAD (Reading routing information) ................ 8-6
RTWRITE (Writing routing information) ................. 8-8
[S]
S.DATE- (Expansion clock data subtraction operation)
........................................................................... 7-366
S.DATE+ (Expansion clock data addition operation)
........................................................................... 7-366
S.DATERD (Reading expansion clock data) ..... 7-366
S.DEVLD (Read data from standard ROM) ....... 7-438
S.TO (Write to host CPU shared memory) ............ 9-4
Scaling (Point-by-point coordinate data) (SCL(P),
DSCL(P)) ........................................................... 7-330
Scaling (Point-by-point coordinate data) (SCL2(P),
DSCL2(P)) ......................................................... 7-334
SCJ (Pointer branching instruction) ................... 6-129
SCL(P) ............................................................... 7-330
SCL2 .................................................................. 7-334
SECOND (Time data conversion)...................... 7-352
SEG (7-segment decode) .................................... 7-75
Sequence instructions ........................................... 2-6
Sequence program stop (STOP) ......................... 5-55
SER (16-bit data searches) ................................. 7-66
Series connection (AND, ANI) ............................... 5-2
Series connections (ANB).................................... 5-10
SET
Setting devices (SET) ...................................... 5-30
Setting the annunciators (SET F) ..................... 5-35
Setting devices (SET) .................................. 5-30,5-35
Setting files for file register use (QDRSET) ....... 7-339
Setting the annunciators (SET F) ........................ 5-35
Setting the master control (MC) ........................... 5-47
SFL (n-bit shift to left of 16-bit data) .................... 7-46
SFR (n-bit shift to right of 16-bit data).................. 7-46
SFT (Bit device shifts).......................................... 5-44
SFTBL(P) ............................................................. 7-52
SFTBR(P) ............................................................ 7-51
SFTWL(P) ............................................................ 7-57
SFTWR(P) ........................................................... 7-56
Shift instruction ............................................ 5-44,7-46
(Application instructions) .................................. 2-29
Shift instruction table
(Sequence instructions) ..................................... 2-6
SIN (SIN operation on floating-point data (Single
precision)) .......................................................... 7-250
SIN operation on floating-point data (Double
precision) (SIND) ............................................... 7-252
SIN operation on floating-point data (Single precision)
(SIN) .................................................................. 7-250
SIN-1 operation on floating-point data (Double
precision) (ASIND) ............................................. 7-265
SIN-1 operation on floating-point data (Single
precision) (ASIN) ............................................... 7-262

SIND (SIN operation on floating-point data (Double
precision)).......................................................... 7-252
Single precision to Double precision conversion
(ECON).............................................................. 6-102
SORT (BIN 16-bit data sort) ................................ 7-95
SP.CONTSW (System switching instruction) ...... 11-2
SP.DEVST (Writing data to standard ROM)...... 7-436
SP.FREAD (Reading data from designated file)
........................................................................... 7-424
SP.FWRITE (Writing data to designated file) .... 7-413
SPD (Pulse density measurement) ................... 6-160
Special format failure checks (CHKST, CHK) ... 7-175
Special function instructions ................................ 2-46
Special timer (STMR) ........................................ 6-151
SQR (Square root operation for floating-point data
(Single precision)).............................................. 7-287
SQRD (Square root operation for floating-point data
(Double precision)) ............................................ 7-289
Square root operation for floating-point data (Double
precision) (SQRD) ............................................. 7-289
Square root operation for floating-point data (Single
precision) (SQR)................................................ 7-287
SRND (Random number generation and series
updates)............................................................. 7-304
STMR (Special function timer)........................... 6-151
STOP (Sequence program stop) ......................... 5-55
STR (Conversion from BIN 16-bit to character string)
........................................................................... 7-206
Structure creation instructions ............................. 2-38
Subrotine program calls (CALL) ........................ 7-110
Subroutine calls (XCALL) .................................. 7-129
Subroutine calls between program files (ECALL)
........................................................................... 7-120
Subroutine program output OFF calls (FCALL)
........................................................................... 7-116
Subset processing ............................................... 3-25
Subtraction
BCD 4-digit subtraction (B-) ............................. 6-34
BCD 8-digit subtraction (DB-) .......................... 6-38
BIN 16-bit subtraction operations (-) ................ 6-22
BIN 32-bit subtraction operations (D-) ............. 6-26
Block subtraction (BK-) ............................ 6-59,6-62
Subtraction of floating decimal point data (Double
precision) (ED-)........................................ 6-50,6-52
Subtraction of floating decimal point data (Single
precision) (E-) .......................................... 6-46,6-48
SUM (16-bit data checks) .................................... 7-69
SWAP (Upper and lower byte exchanges) ........ 6-128
Switching file register numbers (RSET)............. 7-337
Switching instructions .......................................... 2-51
System Switching (SP.CONTSW) ....................... 11-2
[T]
TAN (TAN operation on floating-point data (Single
precision)).......................................................... 7-258
TAN operation on floating-point data (Double
precision)(TAND)............................................... 7-260
TAN operation on floating-point data (Single
precision)(TAN) ................................................. 7-258

TAN-1 operation on floating-point data (Double
precision)(ATAND)............................................. 7-273
TAN-1 operation on floating-point data (Single
precision)(ATAN) ............................................... 7-271
TAND (TAN operation on floating-point data (Double
precision)) .......................................................... 7-260
Teaching timer (TTMR)...................................... 6-149
Termination instruction table.................................. 2-9
TEST (Bit tests) ................................................... 7-61
TIMCHK (Time check instruction)...................... 7-390
Time check instruction (TIMCHK)...................... 7-390
Time data conversion (HOUR) ......7-354,7-356,7-361
Time data conversion (SECOND)...................... 7-352
Timer (OUT T) ..................................................... 5-22
Timing pulse generation (DUTY) ....................... 7-388
TO (Writing 1-word data to intelligent function
modules) ............................................................ 7-163
TRACE (Trace set) ............................................ 7-411
TRACER (Trace reset) ...................................... 7-411
TTMR (Teaching timer)...................................... 6-149
Types of Instructions.............................................. 2-2
[U]
UDCNT1 (Counter 1-phase input up or down) .. 6-143
UDCNT2 (Counter 2-phase input up or down) .. 6-146
UNI (4-bit linking of 16-bit data) ........................... 7-79
UNIRD (Reading module information) ............... 7-402
Unload program from program memory (PUNLOADP)
........................................................................... 7-443
Up / Down counter
Count 1-phase input or dawn (UDCNT1) ....... 6-143
Count 2-phase input or down (UDCNT2) ....... 6-146
Upper and lower byte exchanges (SWAP) ........ 6-128
Upper and lower limit controls for BIN 32-bit (DLIMIT)
........................................................................... 7-321
[V]
VAL (Conversion from character string to BIN 16-bit)
........................................................................... 7-212
[W]
WAND (Logical products with 16-bit data)............. 7-3
WDT (Resetting watchdog timer)....................... 7-386
WOR (Logical sums of 16-bit data)...................... 7-11
WORD (Conversion from BIN 32-bit to BIN 16-bit)
............................................................................. 6-89
Word data .............................................................. 3-4
Word device bit designation................................... 3-3
Writing 1-word data to intelligent function modules
(TO) ................................................................... 7-163
Writing 2-word data to intelligent function modules
(DTO)................................................................. 7-163
Writing clock data (DATEWR) ........................... 7-346
Writing data to designated file (SP.FWRITE) .... 7-413
Writing data to standard ROM (SP.DEVST) ...... 7-436
Writing data to the data tables (FIFW)............... 7-151
Writing routing information (RTWRITE) ................. 8-8
Writing to the CPU shared memory of host CPU... 9-2

Index - 11

I

S.TO................................................................... 9-4
TO ...................................................................... 9-7
WSUM (Calculation of totals for 16-bit data) ....... 7-99
WTOB (Data dissociation in byte units) ............... 7-85
WXNR (16-bit data exclusive NOR operation)..... 7-27
WXNR (16-bit data non-exclusive logical sum
operations)........................................................... 7-30
WXOR (16-bit exclusive OR operations) ..... 7-19,7-22
[X]
XCALL (Subroutine program call)...................... 7-129
XCH (32-bit data exchange) .............................. 6-124
[Z]
ZCOM (Network refresh instruction) ...................... 8-2
ZONE (Zone control for BIN 16-bit)
....................................................... 7-327,7-330,7-334
Zone control for BIN 16-bit (ZONE)
....................................................... 7-327,7-330,7-334
Zone control for BIN 32-bit data (DZONE)
....................................................... 7-327,7-330,7-334
ZPOP (Batch recovery of index register) ........... 7-400
ZPUSH (Batch save of index register)............... 7-400
ZRRDB (Direct 1-byte read from file register).... 7-391
ZRWRB (File register direct 1-byte write) .......... 7-393

Index - 12

Warranty

Please confirm the following product warranty details before using this product.

1. Gratis Warranty Term and Gratis Warranty Range
If any faults or defects (hereinafter "Failure") found to be the responsibility of Mitsubishi occurs during use of the
product within the gratis warranty term, the product shall be repaired at no cost via the sales representative or
Mitsubishi Service Company.
However, if repairs are required onsite at domestic or overseas location, expenses to send an engineer will be
solely at the customer's discretion. Mitsubishi shall not be held responsible for any re-commissioning,
maintenance, or testing on-site that involves replacement of the failed module.
[Gratis Warranty Term]
The gratis warranty term of the product shall be for one year after the date of purchase or delivery to a designated
place.
Note that after manufacture and shipment from Mitsubishi, the maximum distribution period shall be six (6) months,
and the longest gratis warranty term after manufacturing shall be eighteen (18) months. The gratis warranty term of
repair parts shall not exceed the gratis warranty term before repairs.
[Gratis Warranty Range]
(1) The range shall be limited to normal use within the usage state, usage methods and usage environment, etc.,
which follow the conditions and precautions, etc., given in the instruction manual, user's manual and caution
labels on the product.
(2) Even within the gratis warranty term, repairs shall be charged for in the following cases.
1. Failure occurring from inappropriate storage or handling, carelessness or negligence by the user. Failure
caused by the user's hardware or software design.
2. Failure caused by unapproved modifications, etc., to the product by the user.
3. When the Mitsubishi product is assembled into a user's device, Failure that could have been avoided if
functions or structures, judged as necessary in the legal safety measures the user's device is subject to or
as necessary by industry standards, had been provided.
4. Failure that could have been avoided if consumable parts (battery, backlight, fuse, etc.) designated in the
instruction manual had been correctly serviced or replaced.
5. Failure caused by external irresistible forces such as fires or abnormal voltages, and Failure caused by force
majeure such as earthquakes, lightning, wind and water damage.
6. Failure caused by reasons unpredictable by scientific technology standards at time of shipment from
Mitsubishi.
7. Any other failure found not to be the responsibility of Mitsubishi or that admitted not to be so by the user.

2. Onerous repair term after discontinuation of production
(1) Mitsubishi shall accept onerous product repairs for seven (7) years after production of the product is
discontinued.
Discontinuation of production shall be notified with Mitsubishi Technical Bulletins, etc.
(2) Product supply (including repair parts) is not available after production is discontinued.

3. Overseas service
Overseas, repairs shall be accepted by Mitsubishi's local overseas FA Center. Note that the repair conditions at
each FA Center may differ.

4. Exclusion of loss in opportunity and secondary loss from warranty liability
Regardless of the gratis warranty term, Mitsubishi shall not be liable for compensation of damages caused by any
cause found not to be the responsibility of Mitsubishi, loss in opportunity, lost profits incurred to the user by Failures
of Mitsubishi products, special damages and secondary damages whether foreseeable or not , compensation for
accidents, and compensation for damages to products other than Mitsubishi products, replacement by the user,
maintenance of on-site equipment, start-up test run and other tasks.

5. Changes in product specifications
The specifications given in the catalogs, manuals or technical documents are subject to change without prior notice.

6. Product application
(1) In using the Mitsubishi MELSEC programmable controller, the usage conditions shall be that the application will
not lead to a major accident even if any problem or fault should occur in the programmable controller device,
and that backup and fail-safe functions are systematically provided outside of the device for any problem or
fault.
(2) The Mitsubishi programmable controller has been designed and manufactured for applications in general
industries, etc. Thus, applications in which the public could be affected such as in nuclear power plants and
other power plants operated by respective power companies, and applications in which a special quality
assurance system is required, such as for Railway companies or Public service purposes shall be excluded
from the programmable controller applications.
In addition, applications in which human life or property that could be greatly affected, such as in aircraft,
medical applications, incineration and fuel devices, manned transportation, equipment for recreation and
amusement, and safety devices, shall also be excluded from the programmable controller range of
applications.
However, in certain cases, some applications may be possible, providing the user consults their local
Mitsubishi representative outlining the special requirements of the project, and providing that all parties
concerned agree to the special circumstances, solely at the users discretion.

Microsoft, Windows, Windows NT are registered trademarks of Microsoft Corporation in the United States and other
countries.
Pentium and Celeron are trademarks of Intel Corporation in the United States and other countries.
Ethernet is a trademark of Xerox Co., Ltd. in the United States.
CompactFlash is a trademark of SanDisk Corporation.
VxWorks, Tornado, WindPower, WindSh and WindView are registered trademarks of Wind River Systems, Inc.
Other company names and product names used in this document are trademarks or registered trademarks of respective
owners.

SH(NA)-080809ENG-C 1/2

SAFETY PRECAUTIONS
(Always read these cautions before using the product)
Before using this product, please read this manual and the related manuals introduced in this manual, and pay
full attention to safety to handle the product correctly.
Please store this manual in a safe place and make it accessible when required. Always forward a copy of the
manual to the end user.

A-1

REVISIONS
*The manual number is given on the bottom left of the back cover.
Print Date

*Manual Number

Revision

Dec., 2008

SH (NA)-080809ENG-A First edition

Mar., 2009

SH (NA)-080809ENG-B Partial corrections
Section 3.3, 3.8, 5.1.3, 6.1.7, 6.2.14, 7.3.3, 7.11.18, 7.11.19, 7.12.1.5,12.7, 7.12.11, 7.12.25,
7.12.26, 7.13.4, 7.13.5, 7.15.7, 7.15.8

Jul., 2009

SH (NA)-080809ENG-C Revision because of function support by the Universal model QCPU having a
serial number "11043" or later
Partial corrections
Section 2.1, 2.5.6, 2.5.18, 2.5.20, 7.6.9, 7.12.7, 7.12.11, 12.1.3, 12.1.4, APPENDIX 1.2, 1.3, 1.4.2,
3, 5.1
Additions
Section 2.5.16, 7.16, 7.18.10
Modification
Section 2.5.21
Section 9.14
Section 9.15.3

2.5.22, Section 2.5.22
7.6.1, Section 9.15
7.16.3, Section 9.1

2.5.21, Section 9.13

7.16, Section 9.15.1

7.16.2,

7.18.9, Section 9.2

7.18.11, Section 9.3

7.18.12,

7.18.15, Section 9.7

7.18.16,

Section 9.4

7.18.13, Section 9.5

7.18.14, Section 9.6

Section 9.8

7.18.17, Section 9.9

7.18.18, Section 9.10

Section 9.11.1
Chapter 10

9.1.1, Section 9.11.2
11, Chapter 11

7.6.10,

7.16.1, Section 9.15.2

9.1.2, Section 9.12

7.18.19, Section 9.11

9.1,

9.2, Section 9.12.1

9.2.1,

10

Japanese Manual Version SH-080804-B

This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses.
Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may
occur as a result of using the contents noted in this manual.
© 2008 MITSUBISHI ELECTRIC CORPORATION

A-2

INTRODUCTION
This manual explains the common instructions required for programming of the QCPU.
• The common instructions refer to all instructions except those dedicated to special function
modules (such as AJ71QC24 and AJ71PT32-S3) and to AD57 models, as well as PID control instructions, SFC
instructions and ST instructions.
Before using this product, please read this manual and the relevant manuals carefully and develop familiarity with
the functions and performance of the Q series programmable controller to handle the product correctly.
■ Relevant CPU module
CPU module

Basic model QCPU
High Perfomance model QCPU
Process CPU
Redundant CPU

Model

Q00JCPU, Q00CPU, Q01CPU
Q02CPU, Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU
Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU
Q12PRHCPU, Q25PRHCPU
Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU,
Q04UDHCPU, Q06UDHCPU, Q10UDHCPU, Q13UDHCPU,

Universal model QCPU

Q20UDHCPU, Q26UDHCPU, Q03UDECPU, Q04UDEHCPU,
Q06UDEHCPU, Q10UDEHCPU, Q13UDEHCPU,
Q20UDEHCPU

A-3

CONTENTS
SAFETY PRECAUTIONS ..................................................................................................................A - 1
REVISIONS .......................................................................................................................................A - 2
INTRODUCTION ...............................................................................................................................A - 3
CONTENTS .......................................................................................................................................A - 4
MANUALS........................................................................................................................................A - 14

Common Instructions 1/2
1. GENERAL DESCRIPTION
1.1

Related Programming Manuals

1-2

1.2

Abbreviations and Generic Names

1-5

2. INSTRUCTION TABLES

2 - 1 to 2 - 62

2.1

Types of Instructions

2-2

2.2

How to Read Instruction Tables

2-4

2.3

Sequence Instructions

2-6

2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.4

2.5

Contact instructions ...................................................................................................... 2 - 6
Association instructions ................................................................................................ 2 - 7
Output instructions........................................................................................................ 2 - 8
Shift instructions ........................................................................................................... 2 - 8
Master control instructions............................................................................................ 2 - 9
Termination instructions ............................................................................................... 2 - 9
Other instructions ......................................................................................................... 2 - 9

Basic instructions

2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.4.8

2 - 10

Comparison operation instructions ............................................................................. 2 - 10
Arithmetic operation instructions ................................................................................ 2 - 16
Data conversion instructions ...................................................................................... 2 - 22
Data transfer instructions............................................................................................ 2 - 24
Program branch instructions....................................................................................... 2 - 27
Program execution control instructions ...................................................................... 2 - 27
I/O refresh instructions ............................................................................................... 2 - 27
Other convenient instructions ..................................................................................... 2 - 28

Application Instructions

2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.5.8
2.5.9
2.5.10

A-4

1 - 1 to 1 - 8

2 - 29

Logical operation instructions ..................................................................................... 2 - 29
Rotation instructions ................................................................................................... 2 - 32
Shift instructions ......................................................................................................... 2 - 33
Bit processing instructions.......................................................................................... 2 - 34
Data processing instructions ...................................................................................... 2 - 35
Structure creation instructions .................................................................................... 2 - 38
Data table operation instructions ................................................................................ 2 - 40
Buffer memory access instructions............................................................................. 2 - 41
Display instructions..................................................................................................... 2 - 41
Debugging and failure diagnosis instructions ............................................................. 2 - 42

2.5.11
2.5.12
2.5.13
2.5.14
2.5.15
2.5.16
2.5.17
2.5.18
2.5.19
2.5.20
2.5.21
2.5.22

Character string processing instructions .................................................................... 2 - 43
Special function instructions ....................................................................................... 2 - 46
Data control instructions ............................................................................................. 2 - 49
Switching instructions ................................................................................................. 2 - 51
Clock instructions ....................................................................................................... 2 - 52
Expansion clock instruction ........................................................................................ 2 - 55
Program control instructions....................................................................................... 2 - 56
Other instructions ....................................................................................................... 2 - 57
Instructions for Data Link............................................................................................ 2 - 59
Multiple CPU dedicated instruction............................................................................. 2 - 60
Multiple CPU high-speed transmission dedicated instruction..................................... 2 - 60
Redundant system instructions (For Redundant CPU) .............................................. 2 - 61

3. CONFIGURATION OF INSTRUCTIONS

3 - 1 to 3 - 48

3.1

Configuration of Instructions

3-2

3.2

Designating Data

3-3

3.2.1
3.2.2
3.2.3
3.2.4
3.2.5

Using bit data................................................................................................................ 3 - 3
Using word (16 bits) data.............................................................................................. 3 - 4
Using double word data (32 bits).................................................................................. 3 - 6
Using real number data ................................................................................................ 3 - 8
Using character string data......................................................................................... 3 - 11

3.3

Indexing

3 - 12

3.4

Indirect Specification

3 - 23

3.5

Reducing Instruction Processing Time

3 - 25

3.5.1
3.5.2

Subset Processing...................................................................................................... 3 - 25
Operation processing with standard device registers (Z)
(only Universal model QCPU) ............................................................................ 3 - 26

3.6

Cautions on Programming (Operation Errors)

3 - 27

3.7

Conditions for Execution of Instructions

3 - 33

3.8

Counting Step Number

3 - 34

3.9

Operation when the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device

3 - 39

3.10 Precautions for Use of File Registers

4. HOW TO READ INSTRUCTIONS
5. SEQUENCE INSTRUCTIONS
5.1

Contact Instructions

5.1.1
5.1.2
5.1.3
5.2

4 - 1 to 4 - 4
5 - 1 to 5 - 60
5-2

Operation start, series connection, parallel connection (LD,LDI,AND,ANI,OR,ORI).... 5 - 2
Pulse operation start, pulse series connection, pulse parallel connection
(LDP,LDF,ANDP,ANDF,ORP,ORF) ..................................................................... 5 - 5
Pulse NOT operation start, pulse NOT series connection, pulse NOT parallel connection
(LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI) ............................................................... 5 - 7

Association Instructions

5.2.1
5.2.2

3 - 44

5 - 10

Ladder block series connection and parallel connection (ANB,ORB) ........................ 5 - 10
Operation results push,read,pop (MPS,MRD,MPP) ................................................... 5 - 12

A-5

5.2.3
5.2.4
5.2.5
5.3

Output Instructions

5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
5.4

5.6

5.7

Comparison Operation Instructions

6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.2

A-6

6 - 1 to 6 - 168
6-2

BIN 16-bit data comparisons (=,<>,>,<=,<,>=) ............................................................. 6 - 2
BIN 32-bit data comparisons (D=,D<>,D>,D<=,D<,D>=) ............................................. 6 - 4
Floating decimal point data comparisons (Single precision)
(E=,E<>,E>,E<=,E<,E>=)..................................................................................... 6 - 6
Floating decimal point data comparisons (Double precision)
(ED=,ED<>,ED>,ED<=,ED<,ED>=) ..................................................................... 6 - 8
Character string data comparisons ($=,$<>,$>,$<=,$<,$>=) ..................................... 6 - 11
BIN block data comparisons (BKCMP … ,BKCMP … P) ............................................ 6 - 15
BIN 32-bit block data comparisons (DBKCMP … ,DBKCMP … P) ............................ 6 - 18

Arithmetic Operation Instructions

6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9

5 - 55

Sequence program stop (STOP) ................................................................................ 5 - 55
No operations (NOP,NOPLF,PAGE n) ....................................................................... 5 - 57

6. BASIC INSTRUCTIONS
6.1

5 - 51

End main routine program (FEND)............................................................................. 5 - 51
End sequence program (END) ................................................................................... 5 - 53

Other instructions

5.7.1
5.7.2

5 - 47

Setting and resetting the master control (MC,MCR)................................................... 5 - 47

Termination Instructions

5.6.1
5.6.2

5 - 44

Bit device shifts (SFT(P))............................................................................................ 5 - 44

Master Control Instructions

5.5.1

5 - 20

Out instruction (excluding timers, counters, and annunciators) (OUT)....................... 5 - 20
Timers (OUT T,OUTH T) ............................................................................................ 5 - 22
Counter (OUT C) ........................................................................................................ 5 - 26
Annunciator output (OUT F) ....................................................................................... 5 - 28
Setting devices (except for annunciators) (SET) ........................................................ 5 - 30
Resetting devices (except for annunciators) (RST).................................................... 5 - 32
Setting and resetting the annunciators (SET F,RST F) .............................................. 5 - 35
Leading edge and trailing edge outputs (PLS,PLF).................................................... 5 - 37
Bit device output reverse (FF) .................................................................................... 5 - 40
Pulse conversions of direct outputs (DELTA(P)) ........................................................ 5 - 42

Shift Instructions

5.4.1
5.5

Operation results inversion (INV) ............................................................................... 5 - 15
Operation result conversions (MEP,MEF) .................................................................. 5 - 17
Pulse conversions of edge relay operation results (EGP,EGF).................................. 5 - 18

6 - 22

BIN 16-bit addition and subtraction operations (+(P),-(P)) ......................................... 6 - 22
BIN 32-bit addition and subtraction operations (D+(P),D-(P)) .................................... 6 - 26
BIN 16-bit multiplication and division operations (*(P),/(P))........................................ 6 - 30
BIN 32-bit multiplication and division operations (D*(P),D/(P)) .................................. 6 - 32
BCD 4-digit addition and subtraction operations (B+(P),B-(P)) .................................. 6 - 34
BCD 8-digit addition and subtraction operations (DB+(P),DB-(P)) ............................. 6 - 38
BCD 4-digit multiplication and division operations (B*(P),B/(P)) ................................ 6 - 42
BCD 8-digit multiplication and division operations (DB*(P),DB/(P)) ........................... 6 - 44
Addition and subtraction of floating decimal point data (Single precision)
(E+(P),E-(P)) ...................................................................................................... 6 - 46

6.2.10 Addition and subtraction of floating decimal point data (Double precision)
(ED+(P),ED-(P)) ................................................................................................. 6 - 50
6.2.11 Multiplication and division of floating decimal point data (Single precision)
(E*(P),E/(P)) ....................................................................................................... 6 - 54
6.2.12 Multiplication and division of floating decimal point data (Double precision)
(ED*(P),ED/(P)) .................................................................................................. 6 - 56
6.2.13 Block addition and subtraction (BK+(P),BK-(P))......................................................... 6 - 59
6.2.14 BIN 32-bit data block addition and subtraction operations (DBK+(P),DBK-(P)) ........ 6 - 62
6.2.15 Linking character strings ($+(P)) ................................................................................ 6 - 65
6.2.16 Incrementing and decrementing 16-bit BIN data (INC(P),DEC(P)) ............................ 6 - 69
6.2.17 Incrementing and decrementing 32-bit BIN data (DINC(P),DDEC(P)) ....................... 6 - 71
6.3

Data conversion instructions

6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
6.3.13
6.3.14
6.3.15
6.3.16
6.3.17
6.4

6.5

Conversion from BIN data to 4-digit and 8-digit BCD (BCD(P),DBCD(P)) ................. 6 - 73
Conversion from BCD 4-digit and 8-digit data to BIN data (BIN(P),DBIN(P)) ............ 6 - 75
Conversion from BIN 16 and 32-bit data to floating decimal point (Single precision)
(FLT(P),DFLT(P)) ............................................................................................... 6 - 78
Conversion from BIN 16 and 32-bit data to floating decimal point (Double precision)
(FLTD(P),DFLTD(P)).......................................................................................... 6 - 81
Conversion from floating decimal point data to BIN16- and
32-bit data (Single precision) (INT(P),DINT(P)) ................................................. 6 - 83
Conversion from floating decimal point data to BIN16- and
32-bit data (Double precision) (INTD(P),DINTD(P)) ........................................... 6 - 86
Conversion from BIN 16-bit to BIN 32-bit data (DBL(P)) ............................................ 6 - 88
Conversion from BIN 32-bit to BIN 16-bit data (WORD(P))........................................ 6 - 89
Conversion from BIN 16 and 32-bit data to Gray code (GRY(P),DGRY(P)) .............. 6 - 90
Conversion of Gray code to BIN 16 and 32-bit data (GBIN(P),DGBIN(P))................. 6 - 92
Complement of 2 of BIN 16- and 32-bit data (sign reversal) (NEG(P),DNEG(P)) ...... 6 - 94
Floating-point sign invertion (Single precision) (ENEG(P)) ........................................ 6 - 96
Floating-point sign invertion (Double precision) (EDNEG(P)) .................................... 6 - 97
Conversion from block BIN 16-bit data to BCD 4-digit data (BKBCD(P))................... 6 - 98
Conversion from block BCD 4-digit data to block BIN 16-bit data (BKBIN(P)) ......... 6 - 100
Single precision to Double precision conversion (ECON(P)) ................................... 6 - 102
Double precision to Single precision conversion (EDCON(P))................................. 6 - 104

Data Transfer Instructions

6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
6.4.9
6.4.10
6.4.11

6 - 106

16-bit and 32-bit data transfers (MOV(P),DMOV(P))................................................ 6 - 106
Floating-point data transfer (Single precision) (EMOV(P)) ....................................... 6 - 108
Floating-point data transfer (Double precision) (EDMOV(P)) ................................... 6 - 110
Character string transfers ($MOV(P))....................................................................... 6 - 112
16-bit and 32-bit negation transfers (CML(P),DCML(P)) .......................................... 6 - 114
Block 16-bit data transfers (BMOV(P)) ..................................................................... 6 - 117
Identical 16-bit data block transfers (FMOV(P)) ....................................................... 6 - 120
Identical 32-bit data block transfers (DFMOV(P))..................................................... 6 - 122
16-bit and 32-bit data exchanges (XCH(P),DXCH(P)) ............................................. 6 - 124
Block 16-bit data exchanges (BXCH(P)) .................................................................. 6 - 126
Upper and lower byte exchanges (SWAP(P)) .......................................................... 6 - 128

Program Branch Instructions

6.5.1
6.5.2

6 - 73

6 - 129

Pointer branch instructions (CJ,SCJ,JMP) ............................................................... 6 - 129
Jump to END (GOEND)............................................................................................ 6 - 132

A-7

6.6

Program Execution Control Instructions

6.6.1
6.6.2
6.7
6.8

Interrupt disable/enable instructions, interrupt program mask (DI,EI,IMASK) .......... 6 - 133
Recovery from interrupt programs (IRET) ................................................................ 6 - 139

I/O Refresh Instructions

6.7.1

Logical operation instructions

7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.2

7.3

7.4

7.5

A-8

7 - 46

7 - 59

Bit set and reset for word devices (BSET(P),BRST(P)) ............................................. 7 - 59
Bit tests (TEST(P),DTEST(P)).................................................................................... 7 - 61
Batch reset of bit devices (BKRST(P)) ....................................................................... 7 - 64

Data processing instructions

7.5.1
7.5.2
7.5.3
7.5.4

7 - 35

n-bit shift to right or left of 16-bit data (SFR(P),SFL(P)) ............................................. 7 - 46
1-bit shift to right or left of n-bit data (BSFR(P),BSFL(P)) .......................................... 7 - 49
n-bit shift to right or left of n-bit data (SFTBR(P),SFTBL(P)) ...................................... 7 - 51
1-word shift to right or left of n-word data (DSFR(P),DSFL(P)) .................................. 7 - 54
n-bit shift to right or left of n-word data (SFTWR(P),SFTWL(P)) ................................ 7 - 56

Bit processing instructions

7.4.1
7.4.2
7.4.3

7-2

Right rotation of 16-bit data (ROR(P),RCR(P)) .......................................................... 7 - 35
Left rotation of 16-bit data (ROL(P),RCL(P)) .............................................................. 7 - 38
Right rotation of 32-bit data (DROR(P),DRCR(P)) ..................................................... 7 - 41
Left rotation of 32-bit data (DROL(P),DRCL(P))......................................................... 7 - 44

Shift instruction

7.3.1
7.3.2
7.3.3
7.3.4
7.3.5

7 - 1 to 7 - 452

Logical products with 16-bit and 32-bit data (WAND(P),DAND(P)).............................. 7 - 3
Block logical products (BKAND(P)) .............................................................................. 7 - 9
Logical sums of 16-bit and 32-bit data (WOR(P),DOR(P))......................................... 7 - 11
Block logical sum operations (BKOR(P)).................................................................... 7 - 17
16-bit and 32-bit exclusive OR operations (WXOR(P),DXOR(P)) .............................. 7 - 19
Block exclusive OR operations (BKXOR(P)) .............................................................. 7 - 25
16-bit and 32-bit data exclusive NOR operations (WXNR(P),DXNR(P)).................... 7 - 27
Block exclusive NOR operations (BKXNR(P))............................................................ 7 - 33

Rotation instruction

7.2.1
7.2.2
7.2.3
7.2.4

6 - 143

Counter 1-phase input up or down (UDCNT1) ......................................................... 6 - 143
Counter 2-phase input up or down (UDCNT2) ......................................................... 6 - 146
Teaching timer (TTMR) ............................................................................................ 6 - 149
Special function timer (STMR).................................................................................. 6 - 151
Rotary table shortest direction control (ROTC) ........................................................ 6 - 154
Ramp signal (RAMP)................................................................................................ 6 - 157
Pulse density measurement (SPD) .......................................................................... 6 - 160
Fixed cycle pulse output (PLSY) .............................................................................. 6 - 162
Pulse width modulation (PWM) ................................................................................ 6 - 164
Matrix input (MTR).................................................................................................... 6 - 166

7. APPLICATION INSTRUCTIONS
7.1

6 - 141

I/O refresh (RFS(P)) ................................................................................................. 6 - 141

Other Convenient Instructions

6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
6.8.7
6.8.8
6.8.9
6.8.10

6 - 133

7 - 66

16-bit and 32-bit data searches (SER(P),DSER(P))................................................... 7 - 66
16-bit and 32-bit data checks (SUM(P),DSUM(P))..................................................... 7 - 69
Decoding from 8 to 256 bits (DECO(P)) ..................................................................... 7 - 71
Encoding from 256 to 8 bits (ENCO(P)) ..................................................................... 7 - 73

7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10
7.5.11
7.5.12
7.5.13
7.5.14
7.5.15
7.6

Structure creation instructions

7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.6.7
7.6.8
7.6.9
7.6.10
7.6.11
7.6.12
7.6.13
7.7

7.8.2
7.9

7 - 160

Reading 1-/2-word data from the intelligent function module
(FROM(P),DFRO(P))........................................................................................ 7 - 160
Writing 1-/2-word data to intelligent function module (TO(P),DTO(P)) ..................... 7 - 163

Display instructions

7.9.1
7.9.2
7.9.3

7 - 151

Writing data to the data table (FIFW(P))................................................................... 7 - 151
Reading oldest data from tables (FIFR(P))............................................................... 7 - 153
Reading newest data from data tables (FPOP(P)) ................................................... 7 - 155
Deleting and inserting data from and in data tables (FDEL(P),FINS(P)).................. 7 - 157

Buffer memory access instruction

7.8.1

7 - 105

FOR to NEXT instruction loop (FOR,NEXT)............................................................. 7 - 105
Forced end of FOR to NEXT instruction loop (BREAK(P))....................................... 7 - 108
Subroutine program calls (CALL(P)) ........................................................................ 7 - 110
Return from subroutine programs (RET) .................................................................. 7 - 115
Subroutine program output OFF calls (FCALL(P)) ................................................... 7 - 116
Subroutine calls between program files (ECALL(P)) ................................................ 7 - 120
Subroutine output OFF calls between program files (EFCALL(P))........................... 7 - 125
Subroutine program call (XCALL)............................................................................. 7 - 129
Refresh instruction (COM)........................................................................................ 7 - 134
Select Refresh Instruction (COM)............................................................................. 7 - 137
Select Refresh Instruction (CCOM) .......................................................................... 7 - 141
Index modification of entire ladder (IX,IXEND)......................................................... 7 - 144
Designation of modification values in index modification of entire ladders
(IXDEV,IXSET)................................................................................................. 7 - 148

Data Table Operation Instructions

7.7.1
7.7.2
7.7.3
7.7.4
7.8

7-segment decode (SEG(P)) ...................................................................................... 7 - 75
4-bit dissociation of 16-bit data (DIS(P))..................................................................... 7 - 77
4-bit linking of 16-bit data (UNI(P)) ............................................................................. 7 - 79
Dissociation or linking of random data (NDIS(P),NUNI(P)) ........................................ 7 - 81
Data dissociation and linking in byte units (WTOB(P),BTOW(P)) .............................. 7 - 85
Maximum value search for 16- and 32-bit data (MAX(P),DMAX(P)) .......................... 7 - 89
Minimum value search for 16- and 32-bit data (MIN(P),DMIN(P)) ............................. 7 - 92
BIN 16 and 32 bits data sort operations (SORT,DSORT) .......................................... 7 - 95
Calculation of totals for 16-bit data (WSUM(P)) ......................................................... 7 - 99
Calculation of totals for 32-bit data (DWSUM(P))..................................................... 7 - 101
Calculation of averages for 16-bit or 32-bit data (MEAN(P),DMEAN(P)) ................. 7 - 103

7 - 166

Print ASCII code instruction (PR) ............................................................................. 7 - 166
Print comment instruction (PRC) .............................................................................. 7 - 169
Error display and annunciator reset instruction (LEDR) ........................................... 7 - 172

7.10 Debugging and failure diagnosis instructions

7 - 175

7.10.1 Special format failure checks (CHKST,CHK) ........................................................... 7 - 175
7.10.2 Changing check format of CHK instruction (CHKCIR,CHKEND) ............................. 7 - 179
7.11 Character string processing instructions

7 - 183

7.11.1 Conversion from BIN 16-bit or 32-bit to decimal ASCII (BINDA(P),DBINDA(P))...... 7 - 183
7.11.2 Conversion from BIN 16-bit or 32-bit data to hexadecimal ASCII
(BINHA(P),DBINHA(P)).................................................................................... 7 - 186

A-9

7.11.3 Conversion from BCD 4-digit and 8-digit to decimal ASCII data
(BCDDA(P),DBCDDA(P))................................................................................. 7 - 189
7.11.4 Conversion from decimal ASCII to BIN 16-bit and 32-bit data
(DABIN(P),DDABIN(P)).................................................................................... 7 - 192
7.11.5 Conversion from hexadecimal ASCII to BIN 16-bit and 32-bit data
(HABIN(P),DHABIN(P)).................................................................................... 7 - 195
7.11.6 Conversion from decimal ASCII to BCD 4-digit or 8-digit data
(DABCD(P),DDABCD(P))................................................................................. 7 - 198
7.11.7 Reading device comment data (COMRD(P)) ........................................................... 7 - 201
7.11.8 Character string length detection (LEN(P)) .............................................................. 7 - 204
7.11.9 Conversion from BIN 16-bit or 32-bit to character string (STR(P),DSTR(P)) ........... 7 - 206
7.11.10 Conversion from character string to BIN 16-bit or 32-bit data (VAL(P),DVAL(P)) .... 7 - 212
7.11.11 Conversion from floating decimal point to character string data (ESTR(P))............. 7 - 217
7.11.12 Conversion from character string to floating decimal point data (EVAL(P)) ............. 7 - 224
7.11.13 Conversion from hexadecimal BIN to ASCII (ASC(P)) ............................................. 7 - 228
7.11.14 Conversion from ASCII to hexadecimal BIN (HEX(P)) ............................................. 7 - 230
7.11.15 Extracting character string data from the right or left (RIGHT(P),LEFT(P)).............. 7 - 232
7.11.16 Random selection from and replacement in character strings (MIDR(P),MIDW(P))
........................................................................................................................ 7 - 235
7.11.17 Character string search (INSTR(P)) ......................................................................... 7 - 239
7.11.18 Insertion of character string (STRINS(P))................................................................. 7 - 241
7.11.19 Deletion of character string (STRDEL(P)) ................................................................ 7 - 243
7.11.20 Floating decimal point to BCD (EMOD(P)) ............................................................... 7 - 245
7.11.21 From BCD format data to floating decimal point (EREXP(P)) .................................. 7 - 248
7.12 Special function instructions
7.12.1
7.12.2
7.12.3
7.12.4
7.12.5
7.12.6
7.12.7
7.12.8
7.12.9
7.12.10
7.12.11
7.12.12
7.12.13
7.12.14
7.12.15
7.12.16
7.12.17
7.12.18
7.12.19
7.12.20
7.12.21
7.12.22
7.12.23
7.12.24

A-10

7 - 250

SIN operation on floating-point data (Single precision) (SIN(P)) .............................. 7 - 250
SIN operation on floating-point data (Double precision) (SIND(P)) .......................... 7 - 252
COS operation on floating-point data (Single precision) (COS(P)) .......................... 7 - 254
COS operation on floating-point data (Double precision) (COSD(P)) ...................... 7 - 256
TAN operation on floating-point data (Single precision) (TAN(P))............................ 7 - 258
TAN operation on floating-point data (Double precision) (TAND(P))........................ 7 - 260
SIN-1 operation on floating point data (Single precision) (ASIN(P)) ......................... 7 - 262
SIN-1 operation on floating-point data (Double precision) (ASIND(P)) ..................... 7 - 265
COS -1 operation on floating-point data (Single precision) (ACOS(P)) .................... 7 - 267
COS -1 operation on floating-point data (Double precision) (ACOSD(P)) ................ 7 - 269
TAN -1 operation on floating-point data (Single precision) (ATAN(P))...................... 7 - 271
TAN -1 operation on floating-point data (Double precision) (ATAND(P)).................. 7 - 273
Conversion from floating-point angle to radian (Single precision) (RAD(P)) ............ 7 - 275
Conversion from floating-point angle to radian (Double precision) (RADD(P)) ........ 7 - 277
Conversion from floating-point radian to angle (Single precision) (DEG(P)) ............ 7 - 279
Conversion from floating-point radian to angle (Double precision) (DEGD(P)) ........ 7 - 281
Exponentiation operation on floating-point data (Single precision) (POW(P)).......... 7 - 283
Exponentiation operation on floating-point data (Single precision) (POWD(P)) ....... 7 - 285
Square root operation for floating-point data (Single precision) (SQR(P)) ............... 7 - 287
Square root operation for floating-point data (Double precision) (SQRD(P)) ........... 7 - 289
Exponent operation on floating-point data (Single precision) (EXP(P)).................... 7 - 291
Exponent operation on floating-point data (Double precision) (EXPD(P))................ 7 - 294
Natural logarithm operation on floating-point data (Single precision) (LOG(P)) ....... 7 - 296
Natural logarithm operation on floating-point data (Double precision) (LOGD(P)) ... 7 - 298

7.12.25 Common logarithm operation on floating-point data (Single precision)
(LOG10(P))....................................................................................................... 7 - 300
7.12.26 Common logarithm operation on floating-point data (Double precision)
(LOG10D(P)) .................................................................................................... 7 - 302
7.12.27 Random number generation and series updates (RND(P),SRND(P)) ..................... 7 - 304
7.12.28 BCD 4-digit and 8-digit square roots (BSQR(P),BDSQR(P)) ................................... 7 - 306
7.12.29 BCD type SIN operation (BSIN(P))........................................................................... 7 - 309
7.12.30 BCD type COS operations (BCOS(P)) ..................................................................... 7 - 311
7.12.31 BCD type TAN operation (BTAN(P)) ........................................................................ 7 - 313
7.12.32 BCD type SIN -1 operations (BASIN(P)) ................................................................... 7 - 315
7.12.33 BCD type COS -1 operation (BACOS(P)) ................................................................. 7 - 317
7.12.34 BCD type TAN -1 operations (BATAN(P)) ................................................................ 7 - 319
7.13 Data Control Instructions

7 - 321

7.13.1 Upper and lower limit controls for BIN 16-bit and BIN 32-bit data
(LIMIT(P),DLIMIT(P)) ....................................................................................... 7 - 321
7.13.2 BIN 16-bit and 32-bit dead band controls (BAND(P),DBAND(P)) ............................ 7 - 324
7.13.3 Zone control for BIN 16-bit and BIN 32-bit data (ZONE(P),DZONE(P))................... 7 - 327
7.13.4 Scaling (Point-by-point coordinate data) (SCL(P),DSCL(P)).................................... 7 - 330
7.13.5 Scaling (Point-by-point coordinate data) (SCL2(P),DSCL2(P))................................ 7 - 334
7.14 File register switching instructions

7 - 337

7.14.1 Switching file register numbers (RSET(P))............................................................... 7 - 337
7.14.2 Setting files for file register use (QDRSET(P)) ......................................................... 7 - 339
7.14.3 File setting for comments (QCDSET(P)) .................................................................. 7 - 342
7.15 Clock instructions
7.15.1
7.15.2
7.15.3
7.15.4
7.15.5
7.15.6
7.15.7
7.15.8

7 - 344

Reading clock data (DATERD(P)) ............................................................................ 7 - 344
Writing clock data (DATEWR(P)) ............................................................................. 7 - 346
Clock data addition operation (DATE+(P)) ............................................................... 7 - 348
Clock data subtraction operation (DATE-(P)) ........................................................... 7 - 350
Time data conversion (from Hour/Minute/Second to Second) (SECOND(P)) .......... 7 - 352
Time data conversion (from Second to Hour/Minute/Second ) (HOUR(P)).............. 7 - 354
Date comparison (DT=,DT<>,DT>,DT<=,DT<,DT>=) .............................................. 7 - 356
Clock comparison (TM=,TM<>,TM>,TM<=,TM<,TM>=).......................................... 7 - 361

7.16 Expansion Clock Instructions

7 - 366

7.16.1 Reading expansion clock data (S(P).DATERD) ....................................................... 7 - 366
7.16.2 Expansion clock data addition operation (S(P).DATE+)........................................... 7 - 369
7.16.3 Expansion clock data subtraction operation (S(P).DATE-)....................................... 7 - 372
7.17 Program control instructions
7.17.1
7.17.2
7.17.3
7.17.4
7.17.5

Program standby instruction (PSTOP(P)) ................................................................ 7 - 377
Program output OFF standby instruction (POFF(P))................................................ 7 - 378
Program scan execution registration instruction (PSCAN(P)) .................................. 7 - 380
Program low speed execution registration instruction (PLOW(P)) ........................... 7 - 382
Program execution status check instruction (PCHK)................................................ 7 - 384

7.18 Other instructions
7.18.1
7.18.2
7.18.3
7.18.4

7 - 375

7 - 386

Resetting watchdog timer (WDT(P))......................................................................... 7 - 386
Timing pulse generation (DUTY) .............................................................................. 7 - 388
Time check instruction (TIMCHK)............................................................................. 7 - 390
Direct 1-byte read from file register (ZRRDB(P))...................................................... 7 - 391

A-11

7.18.5
7.18.6
7.18.7
7.18.8
7.18.9
7.18.10
7.18.11
7.18.12
7.18.13
7.18.14
7.18.15
7.18.16
7.18.17
7.18.18
7.18.19

File register direct 1-byte write (ZRWRB(P)) ............................................................ 7 - 393
Indirect address read operations (ADRSET(P)) ....................................................... 7 - 395
Numerical key input from keyboard (KEY) ............................................................... 7 - 396
Batch save or recovery of index register (ZPUSH(P),ZPOP(P)) .............................. 7 - 400
Reading Module Information (UNIRD(P))................................................................. 7 - 402
Reading module model name(TYPERD(P))............................................................. 7 - 406
Trace Set/Reset (TRACE,TRACER) ........................................................................ 7 - 411
Writing Data to Designated File (SP.FWRITE)......................................................... 7 - 413
Reading Data from Designated File (SP.FREAD) .................................................... 7 - 424
Writing Data to Standard ROM (SP.DEVST)............................................................ 7 - 436
Read Data from Standard ROM (S(P).DEVLD)........................................................ 7 - 438
Load Program from Memory Card (PLOADP).......................................................... 7 - 440
Unload Program from Program Memory (PUNLOADP) ........................................... 7 - 443
Load + Unload (PSWAPP) ....................................................................................... 7 - 445
High-speed Block Transfer of File Register (RBMOV(P)) ........................................ 7 - 448

Common Instructions 2/2
8. INSTRUCTIONS FOR DATA LINK
8.1

Network refresh instructions

8.1.1
8.2

Writing to the CPU Shared Memory of Host CPU

9.1.1
9.1.2
9.2

9 - 1 to 9 - 18
9-2

Write to Host CPU Shared Memory (S(P).TO) ............................................................. 9 - 4
Writing to host station CPU shared memory (TO(P), DTO(P))..................................... 9 - 7

Reading from the CPU Shared Memory of another CPU

9.2.1

8-6

Reading routing information (S(P)/Z(P).RTREAD) ....................................................... 8 - 6
Registering routing information (S(P)/Z(P).RTWRITE)................................................. 8 - 8

9. Multiple CPU dedicated instruction
9.1

8-2

Refresh instruction for the designated module (S(P)/J(P)/G(P).ZCOM)....................... 8 - 2

Reading/Writing Routing Information

8.2.1
8.2.2

8 - 1 to 8 - 10

9 - 11

Reading from Other CPU Shared Memory (FROM(P), DFRO(P)) ............................. 9 - 12

10. QCPU INSTRUCTIONS
10.1 Overview

10 - 1 to 10 - 20
10 - 2

10.2 Writing Devices to Another CPU (D(P).DDWR)

10 - 13

10.3 Reading Devices from Another CPU (D(P).DDRD)

10 - 17

11. QCPU INSTRUCTIONS
11.1 System Switching Instruction (SP.CONTSW)

12. ERROR CODES
12.1 Error Code List

11 - 1 to 11 - 4
11 - 2

12 - 1 to 12 - 84
12 - 2

12.1.1 Error codes ................................................................................................................. 12 - 3
12.1.2 Reading an error code................................................................................................ 12 - 3
12.1.3 Error code list (1000 to 1999) ..................................................................................... 12 - 4

A-12

12.1.4
12.1.5
12.1.6
12.1.7
12.1.8
12.1.9

Error code list (2000 to 2999) ................................................................................... 12 - 16
Error code list (3000 to 3999) ................................................................................... 12 - 34
Error code list (4000 to 4999) ................................................................................... 12 - 51
Error code list (5000 to 5999) ................................................................................... 12 - 66
Error code list (6000 to 6999) ................................................................................... 12 - 68
Error code list (7000 to 10000) ................................................................................. 12 - 78

12.2 Canceling of Errors

12 - 83

APPENDICES

App - 1 to App - 198

Appendix 1 OPERATION PROCESSING TIME

App - 2

Appendix 1.1
Appendix 1.2
Appendix 1.3

Definition .....................................................................................................App - 2
Operation Processing Time of Basic Model QCPU.....................................App - 3
Operation Processing Time of High Performance Model QCPU/Process CPU/
Redundant CPU ........................................................................................App - 21
Appendix 1.4
Operation Processing Time of Universal Model QCPU.............................App - 50
Appendix 1.4.1 Subset instruction processing time............................................................App - 50
Appendix 1.4.2 Processing time of instructions other than subset instruction ...................App - 66

Appendix 2 CPU PERFORMANCE COMPARISON

App - 114

Appendix 2.1
Appendix 2.1.1
Appendix 2.1.2
Appendix 2.1.3
Appendix 2.1.4
Appendix 2.1.5
Appendix 2.1.6
Appendix 2.1.7

Comparison of Q with AnNCPU, AnACPU, and AnUCPU ......................App - 114
Usable devices ........................................................................................App - 114
I/O control mode......................................................................................App - 115
Data that can be used by instructions .....................................................App - 115
Timer comparison....................................................................................App - 116
Comparison of counters ..........................................................................App - 117
Comparison of display instructions..........................................................App - 117
Instructions whose designation format has been changed
(Except dedicated instructions for AnACPU and AnUCPU) ....................App - 118
Appendix 2.1.8 AnACPU and AnUCPU dedicated instructions........................................App - 119
Appendix 3 SPECIAL RELAY LIST

App - 120

Appendix 4 SPECIAL REGISTER LIST

App - 146

Appendix 5 APPLICATION PROGRAM EXAMPLES
Appendix 5.1

INDEX

App - 198
n

Concept of Programs which Perform Operations of X , X ....................App - 198
n

Index - 1 to Index - 12

A-13

MANUALS
To understand the main specifications, functions, and usage of the CPU module, refer to the basic manuals.
Read other manuals as well when using a different type of CPU module and its functions.
Order each manual as needed, referring to the following list.
The numbers in the "CPU module" and the respective modules are as follows.
Nunber

CPU module

1)

Basic model QCPU

2)

High Perfomance model QCPU

3)

Process CPU

4)

Redundant CPU

5)

Universal model QCPU
:Basic manual,

Manual name

:Other CPU module manuals

Description

< Manual number (model code) >
■User’s manual

Specifications of the hardware (CPU modules,

QCPU User's Manual
(Hardware design, Maintenance and Inspection)
< SH-080483ENG (13JR73) >

power supply modules, base units, extension cables, and
memory cards), system maintenance and inspection,
troubleshooting, and error codes

QnUCPU User’s Manual
Functions, methods, and devices for programming
(Function Explanation, Program Fundamentals)
< SH-080807ENG (13JZ27) >

Qn(H)/QnPH/QnPRHCPU User's Manual
(Function Explanation, Program Fundamentals)

Functions, methods, and devices for programming

< SH-080808ENG (13JZ28) >
QnUCPU User's Manual
(Communication via Built-in Ethernet Port)
< SH-080811ENG (13JZ29) >

Functions for the communication via built-in Ethernet
port of the CPU module

■Programming Manual
QCPU Programming Manual (Common Instructions) How to use sequence instructions, basic instructions,
< SH-080809ENG (13JW10) > and application instructions
QCPU (Q Mode)/QnACPU Programming Manual
(SFC)

System configuration, performance specifications,

functions, programming, debugging, and error codes
< SH-080041 (13JF60) > for SFC (MELSAP3) programs

QCPU (Q Mode) Programming Manual (MELSAP-L) Programming methods, specifications, and functions
< SH-080072 (13JC03) > for SFC (MELSAP-L) programs
QCPU (Q Mode) Programming Manual
(Structured Text)

Programming methods using structured languages
< SH-080366E (13JF68) >

QCPU (Q Mode) / QnACPU Programming Manual
(PID Control Instructions)

Dedicated instructions for PID control
< SH-080040 (13JF59) >

QnPH/QnPRHCPU Programming Manual
(Process Control Instructions)
< SH-080316E (13JF59) >

A-14

Describes the dedicated instructions for performing process control.

CPU module
1)

2)

3)

4)

5)

Related Manuals

Manual name

Description

< Manual number (model code) >
CC-Link IE Controller Network Reference Manual

Specifications, procedures and settings before system operation, parameter

< SH-080668ENG (13JV16) > setting, programming, and troubleshooting of the CC-Link IE controller network module
Q Corresponding MELSECNET/H Network System Reference Explains the specifications for a MELSECNET/H network system for PLC to PLC
Manual (PLC to PLC network)

network. It explains the procedures and settings up to operation, setting the parame-

< SH-080049 (13JF92) > ters, programming and troubleshooting.
Q Corresponding MELSECNET/H Network System Refer- Explains the specifications for a MELSECNET/H network system for remote I/O
ence Manual (Remote I/O network)

network. It explains the procedures and settings up to operation, setting the

< SH-080124 (13JF96) > parameters, programming and troubleshooting.
Type MELSECNET, MELSECNET/B Data Link System
Reference Manual

< IB-66530 (13JF70) >
Q Corresponding Ethernet Interface Module
User's Manual (Application)
< SH-080010 (13JF70) >

Describes the general concept, specifications, and part names and settings for
MELSECNET (II) and MELSECNET/B.
Describes various functions of the Ethernet module: e-mail function, PLC CPU
status monitoring, communication via MELSECNET/H or MELSECNET/10 network system, communication using data link instructions, file transfer (using FTP)
and other functions.

A-15

MEMO

A-16

8

7

INSTRUCTIONS
FOR DATA LINK

7
7
7

Category

Processing Details

Reference

7

section

Network refresh instructions

Refreshes the specified network module.

Section 8.1

Routing information

Reading the data specified by routing parameters.

Section 8.2.1

read/write instructions

Writing routing data to the area specified by routing parameters.

Section 8.2.2

7
7

Remark
In this chapter, instruction names are abbreviated as follows if not specified
particularly.
• S(P)/J(P)/G(P).ZCOM
• S(P)/Z(P).RTREAD

ZCOM

• S(P)/Z(P).RTWRITE

8

RTWRITE

RTREAD

8-1

ZCOM

8.1 Network refresh instructions
8.1.1

Refresh instruction for the designated module
(S(P)/J(P)/G(P).ZCOM)

ZCOM

Basic

High
performance

Process Redundant Universal

Command

S.ZCOM

S.ZCOM

Jn

SP.ZCOM

Jn

S.ZCOM

Un

SP.ZCOM

Un

Command

SP.ZCOM
Command

S.ZCOM
Command

SP.ZCOM
Jn : Network No. of host station (BIN 16 bits)
Un : Head I/O number of host station network module (BIN 16 bits)
Setting
Data

Internal Devices
Bit

Word

R, ZR

J

\

Bit

––

U

Word

\G

Zn

Constants

Other

––

The ZCOM instruction is used to perform refresh at any timing during execution of a
sequence program.
The targets of refresh performed by the ZCOM instruction are indicated below.
• Refresh of CC-Link IE controller network (when refresh parameters are set)
• Refresh of MELSECNET/H (when refresh parameters are set)
• Auto refresh of CC-Link (when refresh device is set)
• Auto refresh of intelligent function module (when auto refresh is set)

Function
(1) When the ZCOM instruction is executed, the CPU module temporarily suspends processing
of the sequence program and conducts refresh processing of the network modules
designated by Jn/Un.
Execution of ZCOM
instruction
END

0

Refresh
processing

8-2

Execution of ZCOM
instruction

Refresh
Refresh
processing processing

Execution of ZCOM
instruction
END

Refresh
processing

Refresh
processing

ZCOM

(2) The ZCOM instruction does not perform the following processing.

1

(a) Communication processing between CPU module and programming tool
(b) Monitor processing of other station

2

(c) Read processing of buffer memory of other intelligent function module by serial
communication module.
(d) Low-speed cyclic data transmission of MELSECNET/H

3

(3) PLC to PLC network*1
(a) When the scan time for the sequence program of host station is longer than the scan
time for the other station, the ZCOM instruction is used to ensure the data reception
from the other station.
(1) Example of data communications when the ZCOM instruction is not used
Control station
program

0

END

0

0

END

6

END

6

Link scan

Normal station
program

4

0

0

END

END

7

0

(2) Example of data communications when the ZCOM instruction is used
Control station 0
program

END

0

END

0

8

END

Link scan

END

0

ZCOM

END

8.1 Network refresh instructions
8.1.1 Refresh instruction for the designated module (S(P)/J(P)/G(P).ZCOM)

Normal station 0
program

0

ZCOM

ZCOM

For details of the transmission delay time on the PLC to PLC network*1, refer to the
manual below:
• CC-Link IE Controller Network Reference Manual
• Q Corresponding MELSECNET/H Network System Reference Manual
(PLC to PLC network)
(b) When the link scan time is longer than the sequence program scan time, data
communications will not be faster even if the ZCOM instruction is used.
END
Sequence program 0 ZCOM

END 0 ZCOM

END 0 ZCOM

0 ZCOM

END

Link scan
*1 : Controller network in CC-Link IE controller network.

8-3

ZCOM

(4) Remote I/O network
The link refresh of the remote master station is performed by the "END processing" of the
CPU module.
Since link scan is performed at completion of link refresh, link scan 'synchronizes' with the
program of the CPU module.
When the ZCOM instruction is used at the remote master station, link refresh is performed at
the point of ZCOM instruction execution, and link scan is performed at completion of link
refresh.
Hence, use of the ZCOM instruction at the remote master station speeds up send/receive
processing to/from the remote I/O station.
(1) When the ZCOM instruction is not used
Remote master
station program

0

END

0

END

0

END

0

Link refresh
Link scan
Link refresh
Remote I/O station
network refresh
I/O refresh
I/O module
Auto refresh
Intelligent
function module

(2) When the ZCOM instruction is used

Remote master
station program

0

ZCOM

ZCOM

ZCOM
END

0

END

0

END

0

Link refresh

Link scan
Link refresh
Remote I/O station
network refresh
I/O refresh
I/O module
Auto refresh
Intelligent
function module

For details of the transmission delay time on the remote I/O network, refer to the manual
below:
• Q Corresponding MELSECNET/H Network System Reference Manual
(Remote I/O network)
(5) The ZCOM instruction can be used as many times as desired in sequence programs.
However, note that each execution of a refresh operation will lengthen the sequence
program scan time by the amount of time required for the refresh operation.

8-4

ZCOM
(6) Designating "Un" in the argument enables the target designation of the intelligent function as
well as the network modules.
In this case, the auto refresh is performed for the buffer memory of the intelligent function
modules. (It replaces the FROM/TO instructions.)
(7) Only with the universal model QCPU, interruption of processing is enabled during the
execution of the ZCOM instruction. However, when refresh data are used in an interrupted
program, the data can split.

1. The ZCOM instruction cannot be used in a fixed cycle execution type program
or interrupt program.
2. The Redundant CPU has restrictions on use of the ZCOM instruction.
Refer to the manual below for details.
• QnPRHCPU User's Manual (Redundant System)

1
2
3
4
6

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• When the specified network number is not connected to the host station
(Error code: 4102)
• When the module specified with the head I/O number is not a network module or link
module (Except Universal model QCPU)
(Error code: 2111)
• When the module specified with the head I/O number is not a network module or link
module (Only Universal model QCPU)
(Error code: 4102)

Program Example
(1) The following program conducts a link refresh for the network module of network No. 6 while
X0 is ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

(2) The following program conducts a link refresh for the network module mounted to the
position whose head I/O number is a X/Y30 to X/Y4F while X0 is ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

8-5

7
8

8.1 Network refresh instructions
8.1.1 Refresh instruction for the designated module (S(P)/J(P)/G(P).ZCOM)

To conduct only communication with peripheral device, use the COM instruction
(refer to Section 7.6.9, 9.1).

6

RTREAD

8.2 Reading/Writing Routing Information
8.2.1

Reading routing information (S(P)/Z(P).RTREAD)

RTREAD

Basic

High
performance

Process Redundant Universal

Command

S.RTREAD

S.RTREAD

n

D

SP.RTREAD

n

D

Command

SP.RTREAD

Setting
Data

n

: Transfer destination network No. (1 to 239) (BIN 16 bits)

D

: Head number of the devices that stores the read data (Device name)

Internal Devices
Bit

Word

R, ZR

J
Bit

\
Word

n
D

U

\G

Zn

Constants
K, H

Other

––
––

––

––

––

––

Function
(1) Reads data from transfer destination network number specified by n, using routing
information set by the routing parameters, and stores it into the area starting from D .
(2) If no data for the transfer destination network number specified by n is set at the routing
parameters, stores 0 into the area starting from D .
(3) The contents of the data stored in the area starting from

D

is as indicated below.

(Individual data ranges)
D +0
+1
+2

Relay network number
Relay station number
Dummy

(1 to 239)
(1 to 120)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• When data specified by n is other than 1 to 239.

(Error code: 4100)

• The device specified by D exceeds the range of the corresponding device.
(For the Universal model QCPU only.)
(Error code: 4101)

8-6

RTREAD

Program Example

1

(1) The following program reads the routing information for the network number specified by D0
when X0 is turned ON.
[Ladder Mode]

[List Mode]
Step

Instruction

2

Device

3

[Operation]
D0

1

D1

10

3
D2
D3 Dummy

4

[Content of routing parameter setting]
Transfer
Relay network Relay station
destination
number
network number number
1
10
3

2
3

10
10

6

2
1

6
7
8

8.2 Reading/Writing Routing Information
8.2.1 Reading routing information (S(P)/Z(P).RTREAD)

8-7

RTWRITE

8.2.2

Registering routing information (S(P)/Z(P).RTWRITE)

RTWRITE

Basic

High
performance

Process Redundant Universal

Command

S.RTWRITE

S.RTWRITE

n

S

SP.RTWRITE

n

S

Command

SP.RTWRITE

Setting
Data

n

: Transfer destination network No. (1 to 239) (BIN 16 bits)

S

: Head number of the devices where the data to be written is stored (Device name)

Internal Devices
Bit

Word

R, ZR

J
Bit

\

n
S

U

Word

\G

Zn

Constants
K, H

––
––

Other
––

––

––

––

Function
(1) Registers routing data of S or later in the area for the transfer destination network number
specified by n in the routing parameters.
(2) The following shows the contents of data to be set at

S

or later.

(Individual data ranges)
S +0
+1
+2

Relay network number
Relay station number
Dummy

(0 to 239)
(0 to 120)

(3) If data for the transfer destination network number specified by n is set in the routing
parameters, it is used to update the data in the area starting from S .
(4) If all data in S or later ( S +0 to S +2) is 0, the data for the transfer destination network
number specified by n is deleted from the routing parameters.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
• When data specified by n is other than 1 to 239.

(Error code: 4100)

• When the data of

(Error code: 4100)

S

or later exceeds each setting ranges.

• When the total number of routing information registered in the routing parameter of the
network parameters and routing information registered with the RTWRITE instruction
exceeds 64.
(Error code: 4100)
• The device specified by S exceeds the range of the corresponding device.
(For the Universal model QCPU only.)
(Error code: 4101)

8-8

RTWRITE

Program Example

1

(1) The following program writes the routing information specified by D1 to D3 to the network
module of the network number specified by D0 when X0 is turned ON.
[Ladder Mode]

[List Mode]
Step

Instruction

2

Device

3
4
[Operation]
D0

1

D1

20

D2
1
D3 Dummy

[Content of routing parameter setting]

6

Transfer
Relay network Relay station
destination
number
network number number
20
1
1

2
3

10
10

2
1

6
7
8

8.2 Reading/Writing Routing Information
8.2.2 Registering routing information (S(P)/Z(P).RTWRITE)

8-9

MEMO

8-10

9

MULTIPLE
CPU DEDICATED
INSTRUCTION

9
7
7
7
7
7

Category

Processing Details

Writing to the CPU shared

Writes device data of the host CPU to the CPU shared

memory of host CPU

memory of the host CPU module.

Reading from the CPU shared

Reads device data from the CPU shared memory of another

memory of another CPU

CPU module to the host CPU.

Reference

7

section
Section 9.1
Section 9.2

9-1

7

9.1 Writing to the CPU Shared Memory of Host CPU
The S.TO or TO instruction is used to write to the CPU shared memory of the host station in the
multiple CPU system.
The following table indicates the usability of the S.TO and TO instructions.

CPU Module Type Name
Basic model QCPU

Q00CPU, Q01CPU

S.TO Instruction

TO Instruction

Usable

Usable

Usable

Unusable

Usable

Unusable

Unusable

Unusable

Usable

Usable

Q02CPU, Q02HCPU,
High Performance model QCPU

Q06HCPU, Q12HCPU,
Q25HCPU
Q02PHCPU, Q06PHCPU,

Process CPU

Q12PHCPU, Q25PHCPU

Redundant CPU

Q12PRHCPU, Q25PRHCPU
Q00UCPU, Q01UCPU,
Q02UCPU, Q03UDCPU,
Q04UDHCPU, Q06UDHCPU,
Q10UDHCPU, Q13UDHCPU,
Q20UDHCPU, Q26UDHCPU,
Q03UDECPU,

Universal model QCPU

Q04UDEHCPU,
Q06UDEHCPU,
Q10UDEHCPU,
Q13UDEHCPU,
Q20UDEHCPU,
Q26UDEHCPU

(1) Operation of S.TO instruction
The S.TO instruction can write data to the CPU shared memory of the host CPU module.
The following figure shows the processing performed when the S.TO instruction is executed
in CPU No. 1.

CPU No. 1
Device
memory

Data
write

CPU No. 2
CPU
shared
memory

Device
memory

CPU
shared
memory

Intelligent
function module
Buffer
memory

[ SP.TO H3E0 n2 n3 n4 D ]
Designation of CPU shared memory in CPU No. 1

9-2

(2) Operation of the TO instruction
The TO instruction can write device memory data to the following memories.

9

• CPU shared memory of host CPU module
• Buffer memory of intelligent function module
The following figure shows the processing performed when the TO instruction is executed in
CPU No. 1.

7
7

CPU No. 1
Device
memory

Data
write

Intelligent
function module

CPU No. 2
CPU
shared
memory

Device
memory

CPU
shared
memory

7

Buffer
memory

7
Writes data

7
[ TO H3E0 n2

S

n3 ]

7

Designation of CPU shared memory in CPU No. 1

[ TO H0 n2

S

n3 ]

7

Designation of intelligent function module

Remark
Refer to Section 7.8.2 when writing to the buffer memory of the intelligent function
module by the TO instruction.

9-3

9.1 Writing to the CPU Shared Memory of Host CPU

Both of the S.TO and TO instructions can be used for the Basic model QCPU
(Q00CPU or Q01CPU) and Universal model QCPU to write data to the CPU
shared memory. However, use of the TO instruction is recommended, since use of
S.TO instruction reduces the number of steps and processing time.

S(P).TO

9.1.1

Write to Host CPU Shared Memory (S(P).TO)

S(P).TO

Ver.
Basic

Ver.
High
performance

Process Redundant Universal

Basic model QCPU:The first 5 digits of serial No is "04122" or higher.
Hight performance modele QCPU:Function version B or later.

Command

S.TO

S.TO

n1

n2

n3

n4

D

SP.TO

n1

n2

n3

n4

D

Command

SP.TO

n1 : Head I/O number of the host CPU (BIN 16 bits)
n2 : CPU shared memory address of the write destination host CPU (BIN 16 bits)
•Basic model QCPU: 0 to 511
•High Performance model QCPU, Process CPU, Universal model QCPU: 0 to 4095
n3 : Head number of the devices where data to be written is stored (BIN 16 bits)
n4 : Number of data blocks to be written (BIN 16 bits)
•Basic model QCPU: 1 to 320
•High Performance model QCPU, Process CPU: 1 to 256
•Universal model QCPU: 1 to 2048
D

Setting
Data

: Device of the host CPU which is turned ON for one scan by the completion of writing (bits)

Internal Devices
Bit

Word

R, ZR

J
Bit

\
Word

U

n1

––

––

n2

––

––

n3

––

––

n4

––

––

Zn

\G

Constants
K, H

Other
––
––

––

––
––

––

D

––

Function
(1) Writes device data of words n3 to n4 to the CPU shared memory address specified by n2 of
the host CPU module or later address.
When writing is completed, the completion bit specified by

D

turns ON.

Host CPU
CPU shared memory
of host CPU (n1)

Device memory
n3

n2

n4
Writes the
data of n4
words

9-4

S(P).TO

(a) CPU shared memory address of the Basic model QCPU

9

CPU shared memory address
0(0H) Host CPU operation information area
96(60H)
System area
192(C0H)
Host CPU refresh area

Write designation
prohibited area

7

*3

User free area

Write designation
permitted area

7

511(1FFH)

(b) CPU shared memory address of the High Performance model QCPU, Process CPU and
Universal model

7

QCPU*4
CPU shared memory address
0(0H) Host CPU operation information area
512(200H)
System area
2048(800H)
*3
Host CPU refresh area

User free area

7
Write designation
prohibited area

7
Write designation
permitted area

7

4095(0FFFH)
*3 : Usable as a user free area when auto refresh setting is not made.
In addition, even when auto refresh setting is made, the auto refresh send range or later is
usable as a user free area.
*4 : Data cannot be written to the multiple CPU high speed transmission area of the Universal
model QCPU with the S(P).TO instruction.

(3) The S.TO instruction can be executed once to one scan for each CPU.
When execution condition is established at two or more places at the same time, the S.TO
instruction executed later is not processed since handshake is established automatically.
(4) The number of data that can be written varies depending on the target CPU module.
CPU module
Basic model QCPU

Number of Write Points
1 to 320

High Performance model QCPU Process CPU

1 to 256

Universal model QCPU

1 to 2048

Writing data to CPU shared memory can be performed using the intelligent
function module device.
For intelligent function module device, refer to the QnUCPU User's Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU
User's Manual (Function Explanation, Program Fundamentals).

9-5

9.1 Writing to the CPU Shared Memory of Host CPU
9.1.1 Write to Host CPU Shared Memory (S(P).TO)

(2) When the number of write points is 0, no processing is performed and the completion device
does not turn ON, either.

7

S(P).TO

Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an
error code is stored into SD0.
(1) When the specified data is outside the following range

(Error code: 4101)

• When the number of write points (n4) is outside the specified range of the setting data.
• When the head of the CPU shared memory address (n2) of the write destination host
CPU exceeds the CPU shared memory address range
• When the CPU shared memory address (n2) + the number of write points (n4) of the write
destination host CPU exceeds the CPU shared memory address range
• When the head number of the devices (n3) where the data to be written is stored + the
number of write points (n4) exceeds the device range
(2) When the host CPU operation information area, system area or host CPU refresh area is
specified to the CPU shared memory address (n2) of the write destination
(High Performance model QCPU, Process CPU)
(Basic model QCPU, Universal model QCPU)

(Error code: 4101)
(Error code: 4111)

(3) When the head I/O number (n1) of the host CPU is other than that of the host CPU
(High Performance model QCPU, Process CPU)
(Basic model QCPU, Universal model QCPU)

(Error code: 2107)
(Error code: 4112)

(4) No CPU module is installed at the position specified by the head I/O number of the CPU
module.
(Error code: 2110)
(5) When the head I/O number (n1) of the host CPU is other than 3E0H/3E1H/3E2H/3E3H
(Error code: 4100)
(6) When the specified instruction is improper

(Error code: 4002)

(7) When the specified number of devices is wrong

(Error code: 4003)

(8) When the unusable device is specified

(Error code: 4004)

Program Example
(1) The following program stores 10 points of data from D0 into address 800H of the CPU
shared memory of CPU No. 1 when X0 is turned ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

Remark
The n1 is specified by the first 3 digits of the hexadecimal 4 digits which represent
the head I/O number of the slot mounted to the CPU module.

9-6

CPU Slot

Slot 0

Slot 1

Slot 2

Head I/O number

3E00

3E10

3E20

3E30

n1

3E0

3E1

3E2

3E3

TO(P), DTO(P)

9.1.2

Writing to host station CPU shared memory (TO(P), DTO(P))

9
Ver.
Basic

High
performance

Process Redundant Universal

Q00CPU/Q01CPU whose first 5 digits of the serial No. is "04122" or higher

7

TO(P), DTO(P)

7

indicates an instruction symbol of TO/DTO.

Command

TO,DTO

n1

n2

S

n3

n1

n2

S

n3

7

Command

TOP,DTOP

P

7
n1 : Head I/O number of the host CPU (BIN 16 bits)
• Basic model QCPU
: 3E0H
• Universal model QCPU: 3E0H to 3E3H

7

n2 : CPU shared memory address of the write destination host CPU (BIN 16 bits)
• Basic model QCPU

: 192 to 511

• Universal model QCPU: 2048 to 4095, 10000 to 24335*2
S

7

: Data to be written or head number of the devices where the data to be written is stored (BIN 16 bits)

n3 : Number of data blocks to be written (BIN 16 bits)
• Basic model QCPU

: TO(P): 1 to 320, DTP(P) : 1 to 160

• Universal model QCPU: TO(P): 1 to 14336*2, DTP(P) : 1 to 7168*2
Setting
Data

Internal Devices
Bit

Word

R, ZR

J
Bit

\
Word

U

\G

Zn

Constants
K, H

Other
U

7

n1
n2

––

n3

*2:

––
––

The setting range varies depending on the auto refresh setting range of the multiple CPU high speed
transmission function.

Function
TO
(1) Writes device data of words S to n3 to the CPU shared memory address specified by n2 of
the host CPU module or later address.
Host CPU
CPU shared memory
of host CPU (n1)

Device memory
S

n2

n3
Writes the
data of n3
words

9-7

9.1 Writing to the CPU Shared Memory of Host CPU
9.1.2 Writing to host station CPU shared memory (TO(P), DTO(P))

––

S

TO(P), DTO(P)
When a constant is specified to S , writes the same data (value specified to
of n3 words from the specified CPU shared memory.

Constant
5
S
(When "5" is designated
for S )

n2
Writes the
same data to
the area of n3
words

S

) to the area

CPU shared memory
of host CPU (n1)
5
5
5
n3 words
5

(a) CPU shared memory addresses of the Basic model QCPU
CPU shared memory address
0(0H) Host CPU operation information area
96(60H)

System area

192(C0H)

Write designation
prohibited area

*2

Host CPU refresh area

Write designation
permitted area

User free area
511(1FFH)

(b) CPU shared memory address of the Universal model QCPU*3
CPU shared memory address
0(0H)
512(200H)

Host CPU operation information area
Write designation
prohibited area

System area

2048(800H)

*2

Host CPU refresh area

User free area
4096(1000H)
Unusable
10000(2710H)

Write designation
permitted area

Multiple CPU high speed
transmission area
24335(5F0FH)

*2 : Usable as a user free area when auto refresh setting is not made.
In addition, even when auto refresh setting is made, the auto refresh send range or later is
usable as a user free area.
*3 : With Q02UCPU, data can not be written to the multiple CPU high speed transmission area.

(2) No processing is performed when the number of write points is 0.
(3) The number of write data varies depending on the target CPU module.
CPU module
Basic model QCPU
Universal model QCPU

9-8

Number of Write Points
1 to 320
1 to 14336

TO(P), DTO(P)

DTO
(1) Writes device data of words S to (n3×2) to the CPU shared memory address specified by
n2 of the host CPU module or later address.

9

Host CPU
CPU shared memory
of host CPU (n1)

Device memory

7

n2

S

n3 2

7

Writes the
data of (n3 2)
words

When a constant is specified to S , writes the same data (value specified to
of (n3×2) words from the specified CPU shared memory.

S

) to the area

CPU shared memory
of host CPU (n1)
n2
Constant
5
S
(When "5" is designated
Writes the same
for S )
data to the area
of (n3 2) words

5
5
5

7
7

(n3 2)
words

7

5

7

(2) No processing is performed when the number of write points is 0.
(3) The number of data that can be written varies depending on the target CPU module.
CPU mode

7

Number of Write Points

Basic model QCPU

1 to 160

Universal model QCPU

1 to 7168

9.1 Writing to the CPU Shared Memory of Host CPU
9.1.2 Writing to host station CPU shared memory (TO(P), DTO(P))

Writing data to CPU shared memory can be performed using the intelligent
function module device.
For intelligent function module device, refer to the QnUCPU User's Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU
User's Manual (Function Explanation, Program Fundamentals).

9-9

TO(P), DTO(P)

Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an
error code is stored into SD0.
(1) When the specified data is outside the following range

(Error code: 4101)

• When the number of write points (n3) is outside the specified range of the setting data.
• When the CPU shared memory address (n2) of the write destination host CPU + the
number of write points (n3) exceeds the CPU shared memory range
• When the head number of the devices that stores the data to be written (
of write points (n3) exceeds the device range

S

) + the number

• When the head of CPU shared memory address (n2) of the write destination host CPU is
outside the write permitted area.
(2) When the head of CPU shared memory address (n2) of the write destination host CPU is an
invalid value.
(Error code: 4111)
(3) When the I/O number specified in (n1) is other than that of the host CPU (Exclude the case
when the multiple CPU high speed transmisson area of other CPU is used.)
(Error code: 4112)
(4) No CPU module is installed at the position specified by the head I/O number of the CPU
module.
(Error code: 2110)

Program Example
(1) The following program stores 10 points of data from D0 into address 10000 of the CPU
shared memory of CPU No. 1 when X0 is turned ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

(2) The following program stores 20 points of data from D0 into address 10000 of the CPU
shared memory of CPU No. 4 when X0 is turned ON.
[Ladder Mode]

[List Mode]
Step

Instruction

Device

Remark
The n1 is specified by the first 3 digits of the hexadecimal 4 digits which represent
the head I/O number of the slot mounted to the CPU module.

9-10

CPU Slot

Slot 0

Slot 1

Slot 2

Head I/O number

3E00

3E10

3E20

3E30

n1

3E0

3E1

3E2

3E3

9.2 Reading from the CPU Shared Memory of another CPU
9
The FROM(P)/DFRO(P) instruction of Multiple CPU system can be read from the following
memories.

7

• Buffer memory of intelligent function module
• CPU shared memory of other CPU module
• CPU shared memory of host CPU module (applicable for the Basic model QCPU and
Universal model QCPU)

7

The following figure shows the processing performed when the FROM(P) instruction is executed
in CPU No. 1.

7
7

CPU No. 1

Intelligent
function module

CPU No. 2

7

Data read

Device
memory

*1

Data
read

CPU
shared
memory

Device
memory

CPU
shared
memory

Buffer
memory

7
7

Reads data

n1 n2 D n3]

Designation of CPU shared memory of CPU No. 2
[ FROM H3E0

n1 n2 D n3]

Designation of CPU shared memory of CPU No. 1
[ FROM H0

n1 n2 D n3]

Designation of intelligent function module
*1 : Applicable for the Basic model QCPU and Universal model QCPU

Remark
Refer to Section 7.8.1 for reading the buffer memory of the intelligent function
module with the FROM/DFRO instruction.

9-11

9.2 Reading from the CPU Shared Memory of another CPU

[ FROM H3E1

FROM(P),DFRO(P)

9.2.1

Reading from Other CPU Shared Memory (FROM(P),
DFRO(P))

FROM(P),DFRO(P)

Ver.

Ver.
High
performance

Basic

Process Redundant Universal

Basic model QCPU:The first 5 digits of serial No is "04122" or higher.
High performance model QCPU:Function version B or later.

(1) When Basic model QCPU, Universal model QCPU is used

indicates an instruction symbol of FROM/DFRO.

Command

FROM,DFRO

n1

n2

D

n3

n1

n2

D

n3

Command

FROMP,DFROP

P

n1 : Head I/O number of the reading target CPU module (BIN 16 bits)
• Basic model QCPU
: 3E0H to 3E2H
• Universal model QCPU: 3E0H to 3E3H
n2 : Head address of data to be read (BIN 16 bits)
• Basic model QCPU

: 0 to 512

• Universal model QCPU: 0 to 4095, 10000 to 24335*3
D

: Head number of the devices where the read data is stored (BIN 16 bits)

n3 : Number of read data (BIN 16 bits)
• Basic model QCPU

: FROM(P): 1 to 512, DFRO(P) : 1 to 256

• Universal model QCPU: FROM(P): 1 to 14336*3, DRRO(P) : 1 to 7168*3
Setting
Data

Internal Devices
Bit

n1

––

n2

––

D

––

n3

––

Word

R, ZR

J

\

Bit

Word

U

\G

Zn

Constants
K, H

Other
U

––
––

––

––
––

*3: The setting range varies depending on the auto refresh setting range of the multiple CPU high speed
communication function.

Function
FROM
(1) Reads the data of n3 words from the CPU shared memory address designated by n2 of the
CPU module designated by n1, and stores that data into the area starting from the device
designated by D .
CPU shared memory of
the designated CPU (n1)

Device memory
D

n2

n3
Reads the
data of n3
words

9-12

FROM(P),DFRO(P)
(a) CPU shared memory address of the Basic model QCPU
CPU shared memory address

9

0(0H) Host CPU operation information area
96(60H)
System area
192(C0H)
Host CPU refresh area

*4

7

Read designation
permitted area

User free area

7

511(1FFH)

(b) CPU shared memory address of the Universal model QCPU*5

7

CPU shared memory address
0(0H)
512(200H)

Host CPU operation information area

7

System area

2048(800H)

*4

Host CPU refresh area

7

User free area
4096(1000H)
Unusable
10000(2710H)

Read designation
permitted area

7

Multiple CPU high speed
transmisson area

7

24335(5F0FH)

(2) When 0 is specified in n3 as the number of data to be read, no processing is performed.
(3) The number of data to be read changes depending on the target CPU module.
CPU Module

Number of Read Points
1 to 512

Basic model QCPU

1 to 14336

Universal model QCPU

DFRO
(1) Reads the data of (n3×2) words from the CPU shared memory address designated by n2 of
the CPU module designated by n1, and stores that data into the area starting from the
device designated by D .
Device memory
D

CPU shared memory of the
designated CPU (n1)
n2

Reads the data
of (n3 2)
words

n3

9-13

9.2 Reading from the CPU Shared Memory of another CPU
9.2.1 Reading from Other CPU Shared Memory (FROM(P), DFRO(P))

*4 : Usable as a user free area when auto refresh setting is not made.
When auto refresh setting is made, the auto refresh send range and later are usable as a user
free area.
*5 : With Q02UCPU, data can not be written to the multiple CPU high speed transmission area.

FROM(P),DFRO(P)
(2) When 0 is specified in n3 as the number of data to be read, no processing is performed.
(3) The number of data to be read changes depending on the target CPU module.
CPU Module

Number of Read Points

Basic model QCPU

1 to 256

Universal model QCPU

1 to 7168

Read of data from the CPU shared memory can also be performed using the
intelligent function module devices.
For intelligent function module device, refer to the QnUCPU User's Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU
User's Manual (Function Explanation, Program Fundamentals).

Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an
error code is stored into SD0.
(1) When the specified data is outside the following range.

(Error code: 4101)

• The head of the CPU shared memory address (n2) which performs reading is outside the
CPU shared memory range.
• The address of the CPU shared memory (n2) which performs reading plus the number of
read points (n3) is outside the CPU shared memory range.
• The read data storage device number (D) plus the number of read points (n3) is outside
the specified device range.
(2) The CPU module does not exist in the position specified by the CPU module head I/O
number.
(Error code: 2110)
(3) When the head of the CPU shared memory address (n2) which performs reading is an
invalid value. (4097 to 9999)
(Error code: 4101)

9-14

FROM(P),DFRO(P)

Program Example

9

(1) The following program stores 10 points of data from address C0H of the CPU shared
memory of CPU No. 2 into the area starting from D0 when X0 is turned ON.
[Ladder Mode]

7

[List Mode]
Step

Instruction

Device

7
(2) The following program stores 20 points of data from address 10000 of the CPU shared
memory of CPU No. 4 into the area starting from D0 when X0 is turned ON.
[Ladder Mode]

7

[List Mode]
Step

Instruction

7

Device

7
Remark
The n1 is specified by the first 3 digits of the hexadecimal 4digits which represent
the head I/O number of the slot mounted to the CPU module.
CPU Slot

Slot 0

Slot 1

Slot 2

Head I/O number

3E00

3E10

3E20

3E30

n1

3E0

3E1

3E2

3E3

7
7

The QCPU provides automatic interlocks for the FROM and TO instructions.
9.2 Reading from the CPU Shared Memory of another CPU
9.2.1 Reading from Other CPU Shared Memory (FROM(P), DFRO(P))

9-15

FROM(P),DFRO(P)

(2) When High Performance model QCPU, Process CPU is used

Command

FROM

FROM

n1

n2

D

n3

FROMP

n1

n2

D

n3

Command

FROMP

n1 : Head I/O number of the reading target CPU module (BIN 16 bits)
n2 : Head address of data to be read (BIN 16 bits)
D

: Head number of the devices where the read data is stored (BIN 16 bits)

n3 : Number of read data (BIN 16 bits)
Setting
Data

Internal Devices
Bit

n1

––

n2

––

D

––

n3

––

J

R, ZR

Word

\

Bit

U

Word

\G

Zn

Constants
K, H

Other
U

––
––

––

––
––

Function
(1) Reads the data of n3 words from the CPU shared memory address designated by n2 of the
CPU module designated by n1, and stores that data into the area starting from the device
designated by D .
CPU shared memory of
the designated CPU (n1)

Device memory
n2

D

n3
Reads the
data of n3
words

CPU shared memory address of the High Performance model QCPU and Process CPU
CPU shared memory address
0(0H) Host CPU operation information area
512(200H)

System area

2048(800H)
Host CPU refresh area

*1

Read designation
permitted area

User free area
4095(0FFFH)
*1 : Usable as a user free area when auto refresh setting is not made.
When auto refresh setting is made, the auto refresh send range and later are usable as a user
free area.

(2) When 0 is specified in n3 as the number of data to be read, no processing is performed.
(3) The number of data to be read changes depending on the target CPU module.
CPU Module
High Performance model QCPU
Process CPU

9-16

Number of Read Points
1 to 4096

FROM(P),DFRO(P)

Read of data from the CPU shared memory can also be performed using the
intelligent function module devices.
For intelligent function module device, refer to the QnUCPU User's Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU
User's Manual (Function Explanation, Program Fundamentals).

9
7
7

Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an
error code is stored into SD0.
(1) When the specified data is outside the following range.

(Error code: 4101)

• The head address of the CPU shared memory (n2) from which read will be performed is
outside the CPU shared memory range.
• The address of the CPU shared memory (n2) from which data is read plus the number of
read points (n3) is outside the CPU shared memory range.
• The read data storage device number (D) plus the number of read points (n3) is outside
the specified device range.
(2) The CPU module does not exist in the position specified by the CPU module head I/O
number.
(Error code: 2110)
(3) When the head of read CPU shared memory address (n2) is an invalid value.
(4097 to 9999)
(Error code: 4101)

7
7
7
7
7

Program Example

[Ladder Mode]

[List Mode]
Step

Instruction

Device

Remark
The n1 is specified by the first 3 digits of the hexadecimal 4digits which represent
the head I/O number of the slot mounted to the CPU module.
CPU Slot

Slot 0

Slot 1

Slot 2

Head I/O number

3E00

3E10

3E20

3E30

n1

3E0

3E1

3E2

3E3

The QCPU provides automatic interlocks for the FROM and TO instructions.

9-17

9.2 Reading from the CPU Shared Memory of another CPU
9.2.1 Reading from Other CPU Shared Memory (FROM(P), DFRO(P))

(1) The following program stores data of 10 points from address 800H of the CPU shared
memory of CPU No. 2. into the area starting from D0 when X0 is turned ON.

MEMO

9-18

10

7

QCPU INSTRUCTIONS

10
7
7
7
7

Category

Processing Details

Write instruction to another CPU Writes devices to another CPU.
Read instruction from another
CPU

Reads devices from another CPU.

Reference

7

section
Section 10.2
Section 10.3

10-1

7

10.1 Overview
The multiple CPU high-speed transmission dedicated instruction directs the Universal model
QCPU to write/read device data to/from the Universal model QCPU in another CPU.
The following shows an operation when CPU No.1 writes device data to CPU No.2 with the
multiple CPU high-speed transmission dedicated instruction.

CPU No.2

CPU No.1
User program
DP.DDWR U3E1 D0 D100 D200 M0

D0

D0

D100
Writing
D200

The multiple CPU high-speed transmission dedicated instruction in either host
CPU or another CPU (target CPU module of instruction) is available only for the
following CPU modules.
• Q03UDCPU, Q04UDHCPU, Q06UDHCPU
The first five digits of serial numeber is 10012 or higer.
• Q10UDHCPU, Q13UDHCPU, Q20UDHCPU, Q26UDHCPU
• QnUDE (H) CPU
(1) Parameter setting and system configuration to execute the multiple CPU high-speed
transmission dedicated instruction
The multiple CPU high-speed transmission dedicated instruction can be executed in the
following parameter setting and system configuration.
• CPU No.1 uses QnUD(H)CPU or QnUDE(H)CPU.
• The multiple CPU high speed main base unit (Q3 DB) is used.
• "Use multiple CPU high speed transmission" is selected in the Multiple CPU settings
screen of PLC parameter.

10-2

(2)

Writable/readable devices
(a) Writable/readable device names
The following table shows the devices that can be written to/read from the Univesal
model QCPU in another CPU with the multiple CPU high-speed transmission dedicated
instruction.

Category

Type

Device name

Setting of target

Internal user device

X, Y, M, L, B, F, SB

Word device

T, ST, C, D, W, SW

10

Remarks

device

Requirements for the setting
Bit device

7

• Digits are specified by 16 bits (4 digits).

7

• The start bit device is multiples of
16(10H).

7

––
Requirements for the setting

Internal system device

• Digits are specified by 16 bits (4 digits).

SM

Bit device

• The start bit device is multiples of

7

16(10H).

File register

Word device

SD

––

Word device

R, ZR

––
:Settable

:Settable with conditions

SB, SW, SM, and SD include system information area. Take care not to destroy
the system information when writing data to the devices above with the
D(P).DDWR instruction of the multiple CPU high-speed transmission dedicated
instruction.

7
7
7

(3) Specification method of a device and writable/readable device range

(a) Device specification
The device specification is a method to directly specify a device in another CPU to be
written/read.
Program for device specification with the DP.DDWR instruction
X0
DP.DDWR H3E1

D0

D100

D200

M0

Directly specifies "D200", a
device in another CPU to be
written.

In the device specification, data can be written/read within the device range of host CPU.
For example, when data register in host CPU is 12k points and data register in another CPU
is 16k points, data can be written/read by 12k points from the start of the data register in
another CPU.

10-3

10.1 Overview

There are two methods for specifying a device in another CPU: device specification and
string specification. They differ in writable/readable device range to another CPU.

Writable/readable device range in device specification
Host CPU

Another CPU

D0

D0

Data register
(12k points)

Data register
(16k points)

D12287

Writable/readable

D12287
D12288
Not writable/not readable
D16383

(b) String specification
The string specification is a method to specify a device in another CPU to be written/
read by character string.
Program for string specification with the DP.DDWR instruction
X0
DP.DDWR H3E1

D0

D100

"D200"

M0

Specifies "D200", a device in another CPU
to be written by characer string.

In the string specification, data can be written to/read from all device ranges of another
CPU.
For example, when data register in host CPU is 12k points and data register in another
CPU is 16k points, data can be written/read by 16k points from the start of the data
register in another CPU.
Writable/readable device range in string specification
Host CPU
D0

to

Another CPU
D0

Data register
(12k points)

to

Data register
(16k points)
Writable/readable

D12287

D16383

Remark
The following explains precautions for string specification.
• The number of characters that can be specified is 32.
• Whether "0" is appended at the start of the device number or not, the devices
are processed as the same.
• For example, both "D1" and "D0001" are processed as "D1".
• Whether a device is specified by upper case character or lower-case character,
they are processed as the same.
• For example, both "D1" and "d1" are processed as "D1".
• If a device not existing in another CPU is specified by a character string, the
instruction will be completed abnormally.

10-4

(4) Managing the multiple CPU high speed transmission area
(a) The multiple CPU high speed transmission area is managed by blocks in units of 16
words.
The following table shows the number of blocks that can be used in each CPU and the
number of blocks used in the instruction.
System area

C Number of CPU modules

2k points

2

46

110

3

22

54

4

14

35

7

*1: For setting of the system area, refer to the QCPU User's Manual (Multiple CPU System).

(b) The following shows configuration of the multiple CPU high speed transmission area
when the multiple CPU system is configured with three CPU modules and the system
area size is 1k word.
Multiple CPU high speed Multiple CPU high speed Multiple CPU high speed
transmission area in
transmission area in
transmission area in
CPU No.1
CPU No.2
CPU No.3
Area to be sent from CPU No.1 to CPU No.s 2 and 3
Receive area from
CPU No.1

Send area to
CPU No.1

Receive area to
CPU No.2

22
blocks

7

22
blocks

Send area to
CPU No.3

Receive area to
CPU No.2

22
blocks

10.1 Overview

Area to sent from CPU No.3 to CPU No.s 1 and 2
22
blocks

Send area to 22
CPU No.1 blocks

Receive area to
CPU No.3

22
blocks

Receive area to
CPU No.3

Send area to 22
CPU No.2 blocks

(5) The number of blocks used for the instruction
The number of blocks used for the instruction depends on the number of write points.
The following table shows the number of blocks used for the instruction.
Number of write/read points specified by
the instruction

7

7

22
blocks

Area to be sent from CPU No.2 to CPU No.s 1 and 3
22
blocks

7

7

22
blocks
Receive area from
CPU No.1

10

*1

1k points

22 Send area to
blocks CPU No.2
22 Send area to
blocks CPU No.3

7

D(P).DDWR instruction

1 to 4

1

5 to 20

2

21 to 36

3

37 to 52

4

53 to 68

5

69 to 84

6

85 to 100

7

D(P).DDRD instruction

1

10-5

(6) The multiple CPU high-speed transmission dedicated instructions that can be executed
concurrently
For the Universal model QCPU, the multiple CPU high-speed transmission dedicated
instructions can be concurrently executed within the range satisfying the following formula.
The number of blocks that
can be used in each CPU

Total number of blocks used for the
instructions concurrently executed

When the number of blocks used for the multiple CPU high-speed transmission dedicated
instructions exceeds the total number of blocks in the multiple CPU high speed transmission
area, the instruction will not be executed in the scan (no processing) but executed at the
next scan.
Note that the instruction will be completed abnormally when the number of empty blocks in
the multiple CPU high speed transmission area is less than the setting values of SD796 to
SD799 (maximum number of used blocks for multiple CPU high-speed transmission
dedicated instruction setting) at the execution of the instruction.
The following table shows execution possibility of the multiple CPU high-speed transmission
dedicated instructions when the number of empty blocks in the multiple CPU high speed
transmission area is less than the number of blocks used for the multiple CPU high-speed
transmission dedicated instructions or the setting values of SD796 to SD799.
Magnitude relation between the number of blocks
used for the instructions*1 and
the number of empty Number of blocks used
blocks for the instruction*1

Magnitude relation

Number of empty blocks*2

Number of blocks used
Number of empty blocks*2
for the instruction*1

between SD setting value
and the number of empty blocks
SD setting value*3

Number of empty blocks*2

SD setting value*3

Number of empty blocks*2

Executed

Not executed (no processing)
Completed abnormally

*1:The number of blocks used for the multiple CPU high-speed transmission dedicated instruction.
*2:The number of empty blocks in the multiple CPU high-speed transmission area.
*3:Setting values from SD796 of SD799.

10-6

(7) Interlock when using the multiple CPU high-speed transmission dedicated instruction
(a) Special relays SM796 to SM799 (maximum number of used blocks for multiple CPU
high-speed transmission dedicated instruction setting) can be used as an interlock for
the multiple CPU high-speed transmission dedicated instruction.
When executing the multiple CPU high-speed transmission dedicated instructions
concurrently, use SM796 to SM799 as an interlock for the instructions.

7
10
7

When using special relays SM796 to SM799, set the maximum number of blocks
for the instruction used for each CPU to special registers SD796 to SD799. (For
example, when the maximum number of blocks for the multiple CPU high-speed
transmission dedicated instruction to be executed to CPU No.3 is 5, set 5 to
SD798.)
When the multiple CPU high speed transmission area becomes equal to or less
than the number of blocks set at SD796 to SD799, the corresponding special
relay (SM796 to SM799) turns on.
CPU No.1

CPU No.2
Multiple CPU high speed transmission area Multiple CPU high speed transmission area

Execution
command

SM
797
DP.DDWR

H3E1

Number of request blocks:4

Turns on when the number of empty blocks
is less than the number of blocks used for
the DP.DDWR instruction.
(The DP.DDWR instruction is not executed.)

Send area
(1 2)

Receive area
(1 2)

7

Lnsufficient for writing a request from
the DP.DDWR instruction.

2) has been increased.

Send area
(1 2)

Receive area
(1 2)

H3E1
During use
Number of request blocks:4

Number of empty blocks:
8

Turns off as empty blocks by the number of blocks
used for the DP.DDWR instruction became available
(The DP.DDWR instruction can be written.)
The request from the DP.DDWR instruction can be written.

10-7

10.1 Overview

CPU No.2
Multiple CPU high speed transmission area Multiple CPU high speed transmission area

DP.DDWR

7
7

Number of empty blocks:
2

Empty area of the request blocks in send area (1

SM
797

7

During use

CPU No.1

Execution
command

7

(b) Program example when SM796 to SM799 are used as an interlock
The following shows a program that executes the D.DDWR instruction to CPU No.2 at
the rise of X0, and executes the D.DDWR instruction to CPU No.3 at the rise of X1.
The maximum number of used blocks for multiple CPU hight speed transmission dedicated
SM402
0

MOV

K7

SD797

Turn-on for one
scan after RUN

Maximum number of
used blocks
(CPU No.2)

MOV

K7

SD798
Maximum number of
used blocks
(CPU No.3)

8

SM402
MOV

K100

D1

Turn-on for one
scan after RUN

Mumber of write points
to CPU No.2

MOV

K100

D3
Mumber of write points
to CPU No.3

The DDWR instruction is executed to CPU No.2 at the rise of X0
X0
11

SET

M0

Execution command of the
DDWR instruction to CPU No.2

M0

During execution the
DDWR instruction to
CPU No.3

SM797

14

D.DDWRH3E1

D0
Completion
status
(CPU No.2)

During execution Number of used
of the DDWR
blocks information
instruction to
(CPU No.2)
CPU No.3

ZR0

ZR0

M1

Write data
to CPU No.2

Write data
to CPU No.2

Completion
devaice
(CPU No.2)

RST

M0
During execution of the
DDWR instruction to CPU No.2

The DDWR instruction is executed to CPU No.3 at the rise of X1
X1
29

SET

M3

During execution of the DDWR
instruction to CPU No.3

M3

During execution the
DDWR instruction to
CPU No.3

SM798

32

D.DDWRH3E2
During execution Number of used
of the DDWR
blocks information
instruction to
(CPU No.3)
CPU No.3

D2
Completion
status
(CPU No.3)

ZR1000

ZR1000

M4

Write data
to CPU No.3

Write data
to CPU No.3

Completion
device
(CPU No.3)

RST

M3
During execution of the
DDWR instruction to CPU No.3

10-8

(8) Program example when the multiple CPU high-speed transmission dedicated instructions
are executed to CPU modules by turns
When the multiple CPU high-speed transmission dedicated instructions are executed to
Universal model QCPUs by turns, release an interlock to prevent the concurrent execution.
Use the cyclic transmission area device (from U3En¥G10000) as an interlock.
The following shows a program example when the multiple CPU high-speed transmission
dedicated instructions are executed at CPU No.s 1 and 2 by turns.
Program example when the multiple CPU high-speed transmission dedicated instruction is
executed at CPU No.1
SM402
MOV

K7

SD797
Maximum number
of used blocks
(CPU No.2)

Turn-on for one scan
after RUN

10
7
7
7

X0
SET

M0
During execution of the
DDWR instruction

Write command

U3E0¥G10000.0 is turned on while CPU No.1 is executing the DP.DDWR instruction.

M0

7

U3E1¥G10000.0

SM797
SET

During execution
of the DDWR
instruction

CPU No.2 is
during execution
of the instruction

U3E0¥
G10000.0
CPU No.1 is during
execution of the
instruction

Number of used
blocks information
(CPU No.2)

MOV

K100

7
7
7

D1
Number of
write points

H3E1

D0

ZR100

ZR100

Completion
status

M1
Completion
device

RST

M0

During execution of
the DDWR instruction

U3E0¥G10000.0 is turned on while CPU No.1 is executing the DP.DDWR instruction.

M1
SET
Completion device

U3E0¥
G10000.0
CPU No.1 is during of
the instruction

10-9

10.1 Overview

DP.DDWR

Program example when the multiple CPU high-speed transmission dedicated instruction is
executed at CPU No.2
SM402
MOV

K1

Turn-on for one
scan after RUN

SD796
Maximum number of
used blocks
(CPU No.1)

X20
SET

M0
During execution the
DDRD instruction

Read instruction

U3E1¥G10000.0 is turned on while CPU No.2 is executing the DP.DDRD instruction.

M0

U3E0¥G10000.0

SM796
SET

During execution
of the DDWR
instruction

CPU No.1 is
during execution
of the instruction

U3E1¥
G10000.0
CPU No.2 is during
execution of the
instruction

Number of used
blocks information
(CPU No.1)

MOV

K50

D1
Read instruction

DP.DDRD

H3E0

D0

D1000

D1000

Completion
status

M1
Completion
devaice

RST

M0
During execution of
the DDRD instruction

U3E1¥G10000.0 is turned off at the completion of the DP.DDRD instruction.

M1
RST
Completion device

U3E1¥
G10000.0
CPU No.2 is during of
execution the instruction

(9) Program example when data exceeding 100 words are written/read with the multiple CPU
high-speed transmission dedicated instruction
The maximum number of write/read points that can be processed with the multiple CPU
high-speed transmission dedicated instruction is 100 words. Data exceeding 100 words can
be written/read by executing the multiple CPU high-speed transmission dedicated
instruction at several times.
The following shows a program example using the D(P).DDWR instruction of the multiple
CPU high-speed transmission dedicated instruction. The similar program can be used when
using the D(P).DDRD instruction of the multiple CPU high-speed transmission dedicated
instruction.

10-10

(a) Program example when one D(P).DDWR instruction is executThe following shows a
program example that writes ZR0 to ZR999 (1000 points) in CPU No.1 to ZR0 to ZR999
in CPU No.2 with the D.DDWR instruction.
In the following program example, the next D.DDWR instruction is executed after the
completion device of the D.DDWR instruction (M2) turns on so that only one D.DDWR
instruction may be executed.

7
10

Program example when one D(P).DDWR instruction is executed

7

The maximum number of used blocks for multiple CPU high-speed
transmission dedicated instruction setting is set to CPU No.2
SM402
0

MOV

K7

Turn-on for one
scan after

SD797
Maximum number of
used blocks
(CPU No.2)

MOV

K100

D1
Number of
write points

Data writing is started at the rise of the write command (X0)
X0

M0

Write
comman

During
writing

7
7
7

37

RST

Z2

7
SET

M0
During writing

M0
68

SET

M1

7

During execution of
the DDWR instruction

During
writing

M4
10.1 Overview

Execution request of the next
DDWR instruction

The DDWR instruction is executed
M1

SM797

71

D.DDWR H3E1

D0
Completion
status

During execution Number of used
of the DDWR
blocks information
instruction
(CPU No.2)

ZR0Z2
Write
destination

ZR0Z2
source/write

RST

M2
Completion
device

M1

During execution of the
DDWR instruction

When the DDWR instruction is completed abnomally, the annunciator is turned on and data writing is stopped
M2

M3

Completion
device

Error
completion
device

98

SET

RST

F0

M0
During
writing

Next data writing is requested at nomal completion of the DDWR instruction
M2

M3

Completion
device

Error
completion
device

134

+

K100

<

Z2

K1000

PLS

=

Z2

K1000

RST

Z2

M4
Execution request of the
next DDWR instruction

M0
During writing

173

END

10-11

(b) Program example when the D(P).DDWR instructions are executed concurrently
The following shows a program example that writes ZR0 to ZR999 (1000 points) in CPU
No.1 to ZR0 to ZR999 in CPU No.2 with the D.DDWR instruction.
As shown on the program example, multiple CPU device write/read instructions can be
executed concurrently.
When reading/writing devices with the multiple CPU high-speed transmission dedicated
instructions concurrently, the more the total number of blocks in the multiple CPU high
speed transmission area (send area), the more the time taken to complete reading/
writing with the multiple CPU high-speed transmission dedicated instruction can be
shortened.
Program example when the D(P).DDWR instructions are executed concurrently
The maximum number of used blocks for multiple CPU high-speed
transmission dedicated instruction setting is set to CPU No.2
SM402
0

MOV

K7

MOV

K100

MOV

K100

Turn-on for one
scan after RUN

Data writing is started at the rise of the write command (X0)
X0
M0
39
Write
comma

RST
SET

SET

M7

SET

Z2
M0

During writing

M1

M2
During execution of
the DDWR instruction 2

Execution request of the next
DDWR instruction

The first DDWR instruction is executed
SM797
M1
94

D.DDWR H3E1

D0
Completion
status 1

During execution Number of used
blocks information
of the DDWR
(CPU No.2)
instruction 1

ZR0Z2
Write
destination

ZR0Z2
source write

RST

The second DDWR instruction is executed

M3
Completion
device 1

M1

During execution of the
DDWR instruction 1

SM797
D.DDWR H3E1

D2
Completion
status 2

During execution Number of used 3
blocks information
of the DDWR
(CPU No.2)
instruction 2

ZR100Z2
Write
destination

ZR100Z2 M5
source write

RST

When the DDWR instruction is completed abnomally, the annunciator is turned on and data writing is stopped
M3
M4
158
SET
Completion
device 1

Error
completion
device 1

M5

M6

Completion
device 2

Error
completion
device 2

M2

During execution of the
DDWR instruction 2

F0

M0
During
writing

Next data writing is requested at nomal completion of the second DDWR instruction
M5
M6
197
Error
completion
device 2

Completion
device 2

DDWR instruction
error display

RST

Completion
device 2

D3

Number of
write points 2

During execution of
the DDWR instruction 1

During
writing

M2

D1

Number of
write points 1

During
writing

First DDWR instruction, Second DDWR instruction
M0
70

126

SD797

Maximum number of
used blocks
(CPU No.2)

+

K200

<

Z2

K1000

PLS

=

Z2

K1000

RST

Z2
M7
Execution request of the
next DDWR instruction

M0
During writing

241

10-12

END

D(P).DDWR

10.2 Writing Devices to Another CPU (D(P).DDWR)
7
D(P).DDWR

Ver.
Basic

High
performance

Process Redundant Universal

10

Q03UDCPU, Q04UDHCPU, Q06UDHCPU: that the first 5 digits of serial number is 10012 or higer QnUDE(H)CPU.

7
Command

D.DDWR

D.DDWR

n

S1

S2

D1

D2

DP.DDWR

n

S1

S2

D1

D2

7

Command

DP.DDWR

7
Setting
data

Internal device
Bit

n *2

––

S1 *3

––

S2 *3
D1 *3
D2 *3

Word*6

R, ZR

J
Bit

\
Word

U

\G

Zn

Constant
K, H

Others

––
*4

*5

––

––

––

––

––

––

––

––

––

––

––

––

––

––

––

*7

––

*5

*2: Index modification cannot be made to setting data n.
*3: Index modification cannot be made to setting data from S1 to D2 .

7
7
7

*4: Local devices cannot be used.
*5: File registers cannot be used per program.
*6: FD @ (indirect specification) cannot be used.
*7: FX and FY cannot be used.

Setting data
n

Description
The result of dividing the start I/O number of another CPU by 16
CPU No.1: 3E0H, CPU No.2: 3E1H, CPU No.3: 3E2H, CPU No.4: 3E3H

S1

Start device of the host CPU that stores control data

S2

Start device of the host CPU that stores data to be written

D1
S

Start device of another CPU that stores write data

D2

Completion device

Data type
BIN 16 bits

Device name
Device*6
Character string*7
Bit

*6: By specifying a file register (R, ZR), data can be written to devices in another CPU, outside the range of host
CPU.
*7: By specifying the start device by " ", devices can be written to devices in another CPU, outside the range of
host CPU.

10-13

10.2 Writing Devices to Another CPU (D(P).DDWR)

Set Data

D(P).DDWR

Control Data
Device

Item

Setting data

Setting range

Set by

––

System

1 to 100

User

An execution result upon completion of the
S1

+0

Completion status

instruction is stored.
0000(H): No errors (normal completion)
Other than 0000(H): Error code (error completion)

S1

+1

Number of write
points

Set the number of write points in units of words.

Function
(1) In multiple CPU system, data stored in a device specified by host CPU ( S2 ) or later is stored
by the number of write points specified by ( D2 +1) into a device specified by another CPU (n)
( D1 ) or later.
Start device nimber of the strage
iocation where write data has stored

Strat devaice number of the
storageiocation for write data

S2

Host CPU
(CPU that repuests writing)

Another CPU n
(CPU to be read)

D1

Number of write points

S1 +1

(2) Whether to complete the D(P).DDWR instruction normally can be checked by the
completion device ( D2 +0) and completion status display device ( D2 +1).
(a)

Completion device ( D2 +0)
Turns on at END processing in the scan where the instruction has been completed, and
turns off at the next END processing.

(b)

Completion status display device ( D2 +1)
This device turns on/off depending on the status upon completion of the instruction.
• Normal completion: Off
• Error completion: Turns on at END processing in the scan where the instruction has
been completed, and turns off at the next END processing (At error completion, an
error code is stored at control data ( S1 +0): Completion status)).

10-14

D(P).DDWR

(3) The number of blocks used for the instruction depends on the number of write points (refer
to Section 12.1).
Number of blocks used for the instruction
Number of write points

D(P).DDWR

specified by the instruction

instruction

1 to 4

1

5 to 20

2

21 to 36

3

37 to 52

4

53 to 68

5

69 to 84

6

85 to 100

7

7
10
7

(4) The instruction will be completed abnormally when there are no empty blocks in the multiple
CPU high speed transmission area.
Set the number of blocks used for the instruction at special registers (SD796 to SD799), and
use the special relays (SM796 to SM799)as an interlock prevent error completion (refer to
Section 12.1).

7
7
7

Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
(1) Specified another CPU is wrong or the multiple CPU high-speed transmission dedicated
instruction cannot be used in the setting
(Error code: 4350)
• The reserved CPU has been specified.

7
7

• Unmounted CPU has been specified.
• Another CPU start I/O number divided by 16n is out of 3E0H to 3E3H.

• The instruction was executed with the Q02UCPU.
• Host CPU has been specified.
• The CPU where the instruction cannot be executed has been specified.
(2) The instruction cannot be executed with the CPU.

(Error code: 4351)

• Another CPU does not support this instruction.
(3) The number of devices is wrong.

(Error code: 4352)

(4) The device that cannot be used for the instruction has been specified.

(Error code: 4353)

(5) A device has been specified by the character string that cannot be used. (Error code: 4354)
(6) The number of write points ( S1 +1)is other than 0 to 100.

(Error code 4354)

10-15

10.2 Writing Devices to Another CPU (D(P).DDWR)

• The instruction was executed without setting "Use multiple CPU high speed
transmission".

D(P).DDWR
In any of the following cases, the instruction is completed abnormally, and an error code is
stored into a device specified at completion status storage device ( S1 +0).
(1) The request of the instruction to the target CPU is more than the acceptable value (no empty
blocks exist in the multiple CPU high speed transmission area).
(Error code: 0010H)
(2) A device for another CPU specified at
range.

S1

cannot be used at another CPU, or is out of device
(Error code: 1001H)

(3) The number of write points set with the D(P).DDWR instruction is 0.
(Error code: 1080H)
(4) The response of the instruction from another CPU cannot be returned (no empty blocks exist
in the multiple CPU high speed transmission area).
(Error code: 1003H)

Program Example
(1) This program stores data by 10 words starting from DO in host CPU into W10 or later in CPU
No.2 when XO turns on.
[Ladder mode]
K10

D101

The number of write points "10" is
stored into D101, setting device of
the number of write points (S1+1)
of control data.

W10

M100

D0 to D9 in host CPU are stored into
W10 to W19 in CPU No.2.

X0
MOVP
Execution command
of the instruction

DP.DDWR
M100

H3E1

D100

D0

M101
Normal completion Program

Completion device

M101
Error completion Program

Caution
(1) Digit specification of bit device is possible for n,
specification of bit device is made to

S2

or

D1

S2

, and

D1

. Note that when the digit

, the following conditions must be met.

• Digits are specified by 16 bits (4 digits).
• The start bit device is multiples of 16 (10H).
(2) Execute this instruction after checking that the write target CPU is powered on. Not doing so
may end up no processing.
(3) If changing a range of the device specified at setting data between after execution of the
instruction and turn-on of the completion device, data to be stored by system (completion
status, completion device) cannot be stored normally.
(4) SB, SW, SM, and SD include system information area. Take care not to destroy the system
information when writing data to the devices above with the D(P).DDWR instruction of the
multiple CPU high-speed transmission dedicated instruction.

10-16

D(P).DDRD

10.3 Reading Devices from Another CPU (D(P).DDRD)
7
D(P).DDRD

Ver.
High
performance

Basic

Process Redundant Universal

10

Q03UDCPU, Q04UDHCPU, Q06UDHCPU: that the first 5 digits of serial number is 10012 or higer
QnUDE(H)CPU.

Command

D.DDRD

D.DDRD

n

S1

S2

D1

D2

DP.DDRD

n

S1

S2

D1

D2

7
7

Command

DP.DDRD

Setting
data

Internal device
Bit

n *2

––

S1 *3

––

S2 *3

––

D1
S *3

––

D2 *3

*3

Word

R, ZR

J
Bit

\
Word

U

\G

Zn

7

Constant
K, H

Others

––
*3

*3

––

*4

*4
*4

7

––

––

––

––

––

––

––

––

––

––

––

––

––

*2: Index modification cannot be made to setting data n.

7
7

*3: Index modification cannot be made to setting data from S1 to D2 .
*4: Local devices cannot be used.
*5: File registers cannot be used per program.
*6: FD @
(indirect specification) cannot be used.
*7: FX and FY cannot be used.

Setting data
n

Description
The result of dividing the start I/O number of another CPU by 16
CPU No.1: 3E0H, CPU No.2: 3E1H, CPU No.3: 3E2H, CPU No.4: 3E3H

S1

Start device of the host CPU that stores control data

S2

Start device of another CPU that stores data to be read

D1
S

Start device of the host CPU that stores read data

D2

Completion device

Data type
BIN 16 bits

Device name
Device*6
Character string*7
Bit

*6: By specifying a file register (R, ZR), data can be read to devices in another CPU, outside the range of host
CPU.
*7: By specifying the start device by " ", devices can be read to devices in another CPU, outside the range of host
CPU.

10-17

10.3 Reading Devices from Another CPU (D(P).DDRD)

Set Data

D(P).DDRD

Control Data
Device

Item

Setting data

Setting range

Set by

––

System

1 to 100

User

An execution result upon completion of the
S1

Completion status

+0

instruction is stored.
0000(H): No errors (normal completion)
Other than 0000(H): Error code (error completion)

S1

Number of read

+1

Set the number of read points in units of words.

points

(1)

In multiple CPU system, data stored in a device specified by another CPU (n) ( D1 ) or later is
stored by the number of read points specified by ( S1 +1) into a device specified by host CPU
( S2 ) or later.
Strat device number of the storage
location where read has been stored

Start device number of the
storage location for read data
Host CPU
(CPU that requests reading)

D2

Another CPU n
(CPU to be read)

S1

Number of read points

S1 +1

(2) Whether to complete the D(P).DDRD instruction normally can be checked by the completion
device ( D2 +0) and completion status display device ( D2 +1).
(a) END processing in scan data that CPU completed the instruction turns on the device
and the next END processing turns off the device.
(b) This device turns on/off depending on the status upon completion of the instruction.
• Normal completion: Off
• Error completion: Turns on at END processing in the scan where the instruction has
been completed, and turns off at the next END processing (At error completion, an
error code is stored at control data ( S1 +0): Completion status)).
(3) The number of blocks used for the instruction depends on the number of read points (refer to
Section 12.1).
Number of blocks used for the instruction
Number of read points
specified by the instruction
1 to 100

(4)

D(P).DDRD instruction
1

The instruction will be completed abnormally when there are no empty blocks in the multiple
CPU high speed transmission area.
Set the number of blocks used for the instruction at special registers (SD796 to SD799), and
use the special relays (SM796 to SM799)as an interlock prevent error completion (refer to
Section 12.1).

10-18

D(P).DDRD

Operation Error

7

In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
(1) Specified another CPU is wrong or the multiple CPU high-speed transmission dedicated
instruction cannot be used in the setting
(Error code: 4350).
• The reserved CPU has been specified.

10
7

• Unmounted CPU has been specified.
• The result of dividing the start I/O number of another CPU by 16n is outside the range of
3E0H to 3E3H.
• The instruction was executed without setting "Use multiple CPU high speed
transmission".

7
7

• The instruction was executed with the Q02UCPU.
• Host CPU has been specified.
• The CPU where the instruction cannot be executed has been specified.
(2) The instruction cannot be executed with the CPU.

7

(Error code: 4351)

• Another CPU does not support this instruction.
(3) The number of devices is wrong.

(Error code: 4352)

(4) The device that cannot be used for the instruction has been specified.

(Error code: 4353)

(5) A device has been specified by the character string that cannot be used.(Error code: 4354)
(6) The number of read points ( S1 +1)is other than 0 to 100.

7
7

(Error code: 4355)

In any of the following cases, the instruction is completed abnormally, and an error code is

(1) The request of the instruction to the target CPU is more than the acceptable value (no empty
blocks exist in the multiple CPU high speed transmission area).
(Error code: 0010H)
(2) A device for another CPU specified at
range.

S2

cannot be used at another CPU, or is out of device
(Error code: 1001H)

(3) The number of read points set with the D(P).DDRD instruction is 0.

(Error code: 1081H)

(4) The response of the instruction from another CPU cannot be returned (no empty blocks exist
in the multiple CPU high speed transmission area).
(Error code: 1003H)

10-19

10.3 Reading Devices from Another CPU (D(P).DDRD)

stored into a device specified at completion status storage device ( S1 +0).

D(P).DDRD

Program Example
(1) This program stores data by 10 words starting from DO in CPU No.2 into W10 or later in host
CPU when XO turns on.
[Ladder mode]
X0
MOVP

K10

D101

D0

W10

M100

Execution command
of the instruction

DP.DDRD
M100

H3E1

D100

M101
Normal completion Program

Completion device

M101
Error completion Program

Caution
(1) Digit specification of bit device is possible for n,
specification of bit device is made to

S2

or

D1

S2

, and

D1

. Note that when the digit

, the following conditions must be met.

• Digits are specified by 16 bits (4 digits).
• The start bit device is multiples of 16 (10H).
(2) Execute this instruction after checking that the read target CPU is powered on. Not doing so
may end up no processing.
(3)

10-20

If changing a range of the device specified at setting data between after execution of the
instruction and turn-on of the completion device, data to be stored by system (completion
status, completion device) cannot be stored normally.

11

7

QCPU INSTRUCTIONS

7
11
7
7
7

Category

Processing Details

Reference

Switches between the control system and standby system at
System switching instruction

the END processing of the scan executed with the

7

section
Section 11.1

SP.CONTSW instruction.

11-1

7

SP.CONTSW

11.1 System Switching Instruction (SP.CONTSW)
SP.CONTSW

Basic

High
performance

Process Redundant Universal

Command

SP.CONTSW

Setting
Data
S
D

SP.CONTSW

S

D

S

: Value other than 0 and used to identify the processing that issued the system switching request (BIN 16 bits)

D

: Error completion device number (bits)

Internal Devices
Bit

R, ZR

Word

––

J
Bit

\
Word

U

\G

Zn

Constants
K, H

Other

––
*1

––

––
––

––

*1: The bit specification for the word device is available.

Function
(1) Switches between the control system and standby system at the END processing of the
scan executed with the SP.CONTSW instruction.
(2) When using the SP.CONTSW instruction for system switching, the "manual switching enable
flag (SM1592)" must have been turned ON (enabled) in advance.
(3)

S is provided to identify the processing block of the program where system switching
occurred when multiple SP.CONTSW instructions are used.

At S , specify a value within the ranges -32768 to -1 and 1 to 32767 (1H to FFFFH).
The S value specified for the SP.CONTSW instruction is stored into the "system switching
instruction argument (SD6)" of the error common information when the system switching is
normally completed. *2
When multiple SP.CONTSW instructions are executed during the same scan, the argument
of the SP.CONTSW instruction executed first is stored into the system switching instruction
argument (SD6).
(4) When system switching is normally completed, the S value specified for the SP.CONTSW
instruction is stored into the "system switching instruction argument (SD1602)" of the new
control system CPU module. *3
By reading the SD1602 value from the new control system CPU module, which the
SP.CONTSW instruction was used for system switching can be confirmed.
*2 : The S value specified for the SP.CONTSW instruction can be confirmed in the error common information
of the PLC diagnostics dialog box on GX Developer.
*3 : The new control system CPU module means the CPU module that was switched from the standby system
to the control system by the SP.CONTSW instruction.

11-2

SP.CONTSW

(5) The error completion device is turned ON by the control system CPU module when system
switching by the SP.CONTSW instruction was unsuccessful.
(a) When OPERATION ERROR is detected due to any of the following reasons at the
execution of the SP.CONTSW instruction, the error completion device is turned ON
during the instruction execution.
• 0 is specified at

S

7

of the executed SP.CONTSW instruction.

• The "manual switching enable flag (SM1592)" is OFF.
• The SP.CONTSW instruction was executed by the standby system in the separate
mode.

(b) If systems could not be switched due to any of the reasons given in the following table,
the error completion device turns ON when system switching is executed in the END
processing.
Reason No.

11
7

• The SP.CONTSW instruction was executed in the debug mode.

7

Reasons for System Switching Failure

0

Normally completed

1

Tracking cable is disconnected or faulty.

7

Hardware fault, power-off, reset or watchdog timer error occurred in the standby

2

system.

7

3

Watchdog timer error occurred in the control system.

4

Preparations being made for tracking transfer.

5

Communication time-out.

6

Stop error occurred in the standby system. (Excluding watchdog timer error)

7

Operating status different between the control system and standby system.

8

Memory copy being executed from the control system to the standby system.

9

Write during RUN being executed.

7

Network fault detected by the standby system.

When the error completion device was turned ON due to unsuccessful system
switching, 16 is stored into the "reason(s) for system switching (SD1588)" and the reason
No. of the above table into the "reason(s) for system switching failure (SD1589)".
(6) Use a user program or GX Developer to turn OFF the error completion bit that has turned
ON.
If normal system switching is performed by the execution of the SP.CONTSW instruction
with the error completion device ON, the error completion device of the new standby system
CPU module is also turned OFF.
When system switching is performed due to a factor other than the SP.CONTSW instruction,
however, the error completion device is not turned OFF.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and
an error code is stored into SD0.
S

is 0 at execution of the SP.CONTSW instruction.
(Error code: 4100)

• The manual switching enable flag (SM1592) is OFF (disable) at execution of the
SP.CONTSW instruction.
(Error code: 4120)
• The SP.CONTSW instruction was executed by the standby system CPU module in the
separate mode.
(Error code: 4121)
• The SP.CONTSW instruction was executed in the debug mode.

(Error code: 4121)

11-3

11.1 System Switching Instruction (SP.CONTSW)

10

• The value specified at

7

SP.CONTSW

(2) If system switching was unsuccessful, the error flag (SM0) is turned ON and an error code is
stored into SD0.
• The tracking cable is disconnected or faulty.

(Error code: 6220)

• Hardware fault, power-off, reset or watchdog timer error occurred in the standby system.
(Error code: 6220)
• Watchdog timer error occurred in the control system.

(Error code: 6220)

• Preparations are being made for tracking transfer.

(Error code: 6220)

• Communication time-out occurred.

(Error code: 6220)

• Stop error, excluding watchdog timer error, occurred in the standby system.
(Error code: 6220)
• The operating status differs between the control system and standby system.
(Error code: 6220)
• Memory copy is being executed from the control system to the standby system.
(Error code: 6220)
• Write during RUN is being executed.

(Error code: 6220)

• Network fault was detected by the standby system.

(Error code: 6220)

Program Example
(1) The following program executes system switching on the leading edge of the system
switching command (M100).
If the system switching command (M100) remains ON, the SP.CONTSW instruction is also
executed by the new control system CPU module after system switching. Therefore, M101 is
added to the execution conditions as a consecutive switching prevention flag.
[Ladder Mode]

[List Mode]
Step

11-4

Instruction

Device

12

6

ERROR CODES

6
6
12
6
6
6
6

12-1

12.1 Error Code List
The CPU module uses the self diagnostics function to display error information (on the LED) and
stores the information into the special relay SM and special register SD, when an error occurs in
the following situations:
• When the Progammable Controller is powered ON.
• When the CPU module is switched from STOP to RUN.
• While the CPU module is running.
If an error occurs when a communication request is issued from the peripheral device, intelligent
function module or network system to the CPU module, the CPU module returns the error code
(4000H to 4FFFH) to the request source.
The following describes the description of errors which occur in the CPU module and the
corrective actions for the errors.
(1) How to read the error code list
The following describes how to read Section 12.1.3 Error code list (1000 to 1999) to Section
12.1.9 Error code list (7000 to 10000).
(a) Error code, common information and individual information
Alphanumeric characters in the parentheses of the titles indicate the special register
numbers where each information is stored.
(b) Compatible CPU
QCPU
Q00J/Q00/Q01
Qn(H)
QnPH
QnPRH
QnU
Each CPU module
model name

12-2

: Indicates all the Q series CPU modules.
: Indicates the Basic model QCPU.
: Indicates the High Performance model QCPU.
: Indicates the Process CPU.
: Indicates the Redundant CPU.
: Indicates the Universal model QCPU.
: Indicates the relevant specific CPU module.
(Example: Q02U)

12.1.1

Error codes

1

Errors are detected by the self diagnostic function of the CPU module or detected during
communication with the CPU module.
The relation between the error detection pattern, error detection location and error code is shown
in Table 12.1.

3

Table12.1Reference destination
Error detection pattern

Error detection
location

Error code

Reference

12

Detection by the self
diagnostics function of CPU

CPU module

1000 to 10000*1*2 Section 12.1.3 to 12.1.9

CPU module

4000H to 4FFFH

module

Serial communication
module, etc.

Detection at communication
with CPU module

7000H to 7FFFH

CC-Link module

B000H to BFFFH

Ethernet module

C000H to CFFFH

CC-Link IE controller
network

E000H to EFFFH

2

• QCPU User’s Manual (Hardware design,

6

Maintenance and Inspection)
Serial Communication User’s Manual, etc.
CC-Link System Master/Local Module User’s

6

Manual
Ethernet Interface Module User’s Manual

7

CC-Link IE Controller Network Reference
Manual

• MELSECNET/H mode
Q Corresponding MELSECNET/H Network
MELSECNET/H
network module

F000H to FFFFH

System Reference Manual

8

• MELSECNET/10 mode
For QnA/Q4AR MELSECNET/10 Network
System Reference Manual

*1: CPU module error codes are classified into minor, moderate, major errors as shown below.

• Minor error:

12.1.2

Reading an error code

When an error occurs, reading an error code, error message or the like can be executed with GX
Developer.
For the details of the operation method, refer to the operating manual for GX Developer.

12-3

12.1 Error Code List
12.1.1 Error codes

Errors that may allow the CPU module to continue the operation, e.g., battery error.
(Error code: 1300 to 10000)
• Moderate error: Errors that may cause the CPU module to stop the operation, e.g., WDT error.
(Error code: 1300 to 10000)
• Major error:
Errors that may cause the CPU module to stop the operation, e.g., RAM error.
(Error code: 1000 to 1299)
Determine the error level, i.e. whether the operation can be continued or stopped, by referring to
"Operating Statuses of CPU" described in Section 12.1.3 to 12.1.9 "Error Code List"
*2: When detected an error code without being noted in the reference table, please contact your local
Mitsubishi representive.

12.1.3

Error code list (1000 to 1999)

The following shows the error messages from the error code 1000 to 1999, the contents and
causes of the errors, and the corrective actions for the errors.
Error
Code

Error Contents and Cause

Corrective Action

1000

[MAIN CPU DOWN]
Runaway or failure of CPU module or failure of
main CPU
• Malfunctioning due to noise or other reason
• Hardware fault
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

• Take noise reduction measures.
• Reset the CPU module and RUN it again.If the
same error is displayed again, this suggests a
CPU module hardware fault.(Contact your local
Mitsubishi representative.)

1001

[MAIN CPU DOWN]
Runaway or failure of CPU module or failure of
main CPU
• Malfunctioning due to noise or other reason
• Hardware fault
• Accessed to outlying devices with the device
range checks disabled (SM237 is turned on)(This
error occurs only when BMOV, FMOV, and
DFMOV instructions are executed.)
(Universal model QCPU only)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

• Take noise reduction measures.
• Reset the CPU module and RUN it again.If the
same error is displayed again, this suggests a
CPU module hardware fault.(Contact your local
Mitsubishi representative.)
• Check the devices specified by BMOV, FMOV,
and DFMOV instructions and correct the device
settings.
(Universal model QCPU only)

[MAIN CPU DOWN]
Runaway or failure of CPU module or failure of
main CPU
• Malfunctioning due to noise or other reason
• Hardware fault
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

• Take noise reduction measures.
• Reset the CPU module and RUN it again.If the
same error is displayed again, this suggests a
CPU module hardware fault.(Contact your local
Mitsubishi representative.)

[MAIN CPU DOWN]
Runaway or failure of CPU module or failure of
main CPU
• Malfunctioning due to noise or other reason
• Hardware fault
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

• Take noise reduction measures.
• Reset the CPU module and RUN it again.If the
same error is displayed again, this suggests a
CPU module hardware fault.(Contact your local
Mitsubishi representative.)

[MAIN CPU DOWN]
Boot operation was performed in the transfer
destination without formatting.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON

• Before performing boot operation by the
parameter, select "Clear program memory" to
clear the program memory.

1002
1003

1004

1005

12-4

LED Status
CPU Status

Corresponding
CPU

QCPU
RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

Qn(H)
QnPH
QnPRH

Error
Code
1006
1007

1008

1009

Error Contents and Cause
[MAIN CPU DOWN]
Runaway or failure of CPU module or failure of
main CPU
• Malfunctioning due to noise or other reason
• Hardware fault
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always
[MAIN CPU DOWN]
• A failure is detected on the power supply module,
CPU module, main base unit, extension base
unit or extension cable.
• When using the redundant base unit, the
redundant power supply module failure in both
systems and/or the redundant base unit failure
are detected.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

Corrective Action

LED Status
CPU Status

Corresponding
CPU

1
• Take noise reduction measures.
• Reset the CPU module and RUN it again.If the
same error is displayed again, this suggests a
CPU module hardware fault.(Contact your local
Mitsubishi representative.)

Qn(H)
QnPH
QnPRH

2
3

Reset the CPU module and RUN it again.If the
same error is detected again, it is considered that
the power supply module, CPU module, main base
unit, extension base unit or extension cable is
faulty.
(Contact your local Mitsubishi representative.)

Q00J/Q00/Q01*4
Qn(H)*6
QnPH
QnPRH
QnU

6
6

[END NOT EXECUTE]
Entire program was executed without the execution
of an END instruction.
• When the END instruction is executed it is read
as another instruction code, e.g. due to noise.
• The END instruction has been changed to
another instruction code somehow.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• When an END instruction executed

• Take noise reduction measures.
• Reset the CPU module and RUN it again. If the
same error is displayed again, this suggests a
CPU module hardware fault. (Contact your local
Mitsubishi representative.)

1020

[SFCP. END ERROR]
The SFC program cannot be normally terminated
due to noise or other reason.
• The SFC program cannot be normally terminated
due to noise or any similar cause.
• The SFC program cannot be normally terminated
for any other reason.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• When SFC program is executed

• Take noise reduction measures.
• Reset the CPU module and RUN it again. If the
same error is displayed again, this suggests a
CPU module hardware fault. (Contact your local
Mitsubishi representative.)

Q00J/Q00/Q01*4
QnPH
QnU

1035

[MAIN CPU DOWN]
Runaway or error of the CPU module was
detected.
• Malfunction due to noise etc.
• Hardware failure
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

• Take measures against noise.
• Reset the CPU module and run it again. If the
same error is displayed again, the CPU module
has hardware failure.(Contact your local
Mitsubishi representative, explaining a detailed
description of the problem.)

QnU

1010

RUN:
Off
ERR.:
Flicker

7
QCPU

CPU Status:
Stop

8

Function version is B or later.
The module whose first 5 digits of serial No. is "04101" or later.

12-5

12.1 Error Code List
12.1.3 Error code list (1000 to 1999)

*4
*6

12

Error
Code

Error Contents and Cause

Corrective Action

1101

[RAM ERROR]
The sequence program storing program memory in
the CPU module is faulty.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset/ When an END instruction
executed

• Take noise reduction measures.
• Reset the CPU module and RUN it again. If the
same error is displayed again,this suggests a
CPU module hardware fault.(Contact your local
Mitsubishi representative.)

1102

[RAM ERROR]
• The work area RAM in the CPU module is faulty.
• The standard RAM and extended RAM in the
CPU module are faulty.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset/ When an END instruction
executed

• Take noise reduction measures.
• Reset the CPU module and RUN it again. If the
same error is displayed again,this suggests a
CPU module hardware fault.(Contact your local
Mitsubishi representative.)

[RAM ERROR]
The device memory in the CPU module is faulty.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

1103

1104

[RAM ERROR]
• The device memory in the CPU module is faulty.
• The device out of range is accessed due to
indexing, and the device for system is
overwritten.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset/ When an END instruction
executed
[RAM ERROR]
The address RAM in the CPU module is faulty.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset
[RAM ERROR]
The CPU memory in the CPU module is faulty.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

1105

*4
*8
*9

12-6

[RAM ERROR]
The CPU shared memory in the CPU module is
faulty.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

• Take noise reduction measures.
• When indexing is performed, check the value of
index register to see if it is within the device
range.
• Reset the CPU module and RUN it again. If the
same error is displayed again,this suggests a
CPU module hardware fault.(Contact your local
Mitsubishi representative.)

• Take noise reduction measures.
• Reset the CPU module and RUN it again.If the
same error is displayed again, this suggests a
CPU module hardware fault. (Contact your local
Mitsubishi representative.)

LED Status
CPU Status

Corresponding
CPU

QCPU

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

Qn(H)*8
QnPH*8
QnPRH*9

QCPU

Q00J/Q00/Q01
QnU
• Take noise reduction measures.
• Reset the CPU module and RUN it again.If the
same error is displayed again, this suggests a
CPU module hardware fault. (Contact your local
Mitsubishi representative.)

Function version is B or later.
The module whose first 5 digits of serial No. is "08032" or later.
The module whose first 5 digits of serial No. is "09012" or later.

Qn(H)*4
QnPH
QnPRH
QnU

Error
Code

1106

Error Contents and Cause
[RAM ERROR]
The battery is dead.
The program memory in the CPU module is faulty.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• STOP

RUN/When an END instruction

executed
1107

1108

1109

1110

1111

1113

*7
*8
*9

LED Status
CPU Status

• Check the battery to see if it is dead or not. If
dead, replace the battery.
• Take noise reduction measures.
• Format the program memory, write all files to the
PLC, then reset the CPU module, and RUN it
again.
If the same error is displayed again, the possible
cause is a CPU module hardware fault. (Contact
your local Mitsubishi representative, explaining a
detailed description of the problem.)

1
Qn(H)
QnPH*7
QnPRH

[TRK. CIR. ERROR]
A fault was detected by the initial check of the
tracking hardware.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

2
3

[RAM ERROR]
The work area RAM in the CPU module is faulty.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset
[RAM ERROR]
The work area RAM in the CPU module is faulty.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

Corresponding
CPU

QnPRH

12
6

Qn(H)*8
QnPH*8
QnPRH*9
This suggests a CPU module hardware fault.
(Contact your local Mitsubishi representative.)

RUN:
Off
ERR.:
Flicker

7

CPU Status:
Stop

8

[TRK. CIR. ERROR]
A tracking hardware fault was detected.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset
[TRK. CIR. ERROR]
A tracking hardware fault was detected during
running.
• The tracking cable was disconnected and
reinserted without the standby system being
powered off or reset.
• The tracking cable is not secured by the
connector fixing screws.
• The error occurred at a startup since the
redundant system startup procedure was not
followed.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• During running

6

QnPRH

12.1 Error Code List
12.1.3 Error code list (1000 to 1999)

1112

Corrective Action

• Start after checking that the tracking cable is
connected.
If the same error is displayed again, the cause is
the hardware fault of the tracking cable or CPU
module. (Please contact your local Mitsubishi
representative, explaining a detailed description
of the problem.)
• Confirm the redundant system startup procedure,
and execute a startup again. For details, refer to
the QnPRHCPU User's Manual (Redundant
System).

The module whose first 5 digits of serial No. is "07032" or later.
The module whose first 5 digits of serial No. is "08032" or later.
The module whose first 5 digits of serial No. is "09012" or later.

12-7

Error
Code

Error Contents and Cause

Corrective Action

1115

[TRK. CIR. ERROR]
A fault was detected by the initial check of the
tracking hardware.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

1116

[TRK. CIR. ERROR]
A tracking hardware fault was detected during
running.
• The tracking cable was disconnected and
reinserted without the standby system being
powered off or reset.
• The tracking cable is not secured by the
connector fixing screws.
• The error occurred at a startup since the
redundant system startup procedure was not
followed.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• During running

• Start after checking that the tracking cable is
connected.
If the same error is displayed again, the cause is
the hardware fault of the tracking cable or CPU
module. (Please contact your local Mitsubishi
representative, explaining a detailed description
of the problem.)
• Confirm the redundant system startup procedure,
and execute a startup again. For details, refer to
the QnPRHCPU User's Manual (Redundant
System).

1150

[RAM ERROR]
The memory of the CPU module in the Multiple
CPU high speed transmission area is faulty.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

• Take noise reduction measures.
• Reset the CPU module and RUN it again.
If the same error is displayed again, the CPU
module has hardware failure. Contact your local
Mitsubishi representative, explaining a detailed
description of the problem.

1160

[RAM ERROR]
The program memory in the CPU module is
overwritten.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At program execution

• Take noise reduction measures.
• Format the program memory, write all files to the
PLC, then reset the CPU module, and RUN it
again.
If the same error is displayed again, the CPU
module has hardware failure. Contact your local
Mitsubishi representative, explaining a detailed
description of the problem.

1161

[RAM ERROR]
The data of the device memory built in the CPU
module is overwritten.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At program execution

• Take noise reduction measures.
If the same error is displayed again, the CPU
module has hardware failure. Contact your local
Mitsubishi representative, explaining a detailed
description of the problem.

1162

[RAM ERROR]
The error of the data held by the battery in the CPU
module is detected. (It occurs when the automatic
format is not set.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

• Take noise reduction measures.
• Change the CPU main body or SRAM card
battery.
If the same error is displayed again, the CPU
module has hardware failure. Contact your local
Mitsubishi representative, explaining a detailed
description of the problem.

*10

12-8

LED Status
CPU Status

Corresponding
CPU

This suggests a CPU module hardware fault.
(Contact your nearest Mitsubishi representative.)

The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.

QnPRH

RUN:
Off
ERR.:
Flicker

QnU*10

CPU Status:
Stop

QnU

Error
Code

1164

1200

Error Contents and Cause
[RAM ERROR]
The destruction of the data stored in the standard
RAM is detected.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• When instruction executed

LED Status
CPU Status

Corresponding
CPU

1

• Take noise reduction measures.
If the same error is displayed again, the CPU
module has hardware failure. Contact your local
Mitsubishi representative, explaining a detailed
description of the problem.

QnU*11

2

[OPE. CIRCUIT ERR.]
The operation circuit for index modification in the
CPU module does not operate normally.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

1201

[OPE. CIRCUIT ERR.]
The hardware (logic) in the CPU module does not
operate normally.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

1202

[OPE. CIRCUIT ERR.]
The operation circuit for sequence processing in
the CPU module does not operate normally.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

1204

[OPE. CIRCUIT ERR.]
The hardware (logic) in the CPU module does not
operate normally.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• When an END instruction executed

1205

[OPE. CIRCUIT ERR.]
The operation circuit for sequence processing in
the CPU module does not operate normally.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• When an END instruction executed

3
12
6

QCPU

6
RUN:
Off
ERR.:
Flicker

This suggests a CPU module hardware fault.
(Contact your local Mitsubishi representative.)

7

CPU Status:
Stop

8

12.1 Error Code List
12.1.3 Error code list (1000 to 1999)

1203

[OPE. CIRCUIT ERR.]
The operation circuit for index modification in the
CPU module does not operate normally.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• When an END instruction executed

*11

Corrective Action

QnPRH

The Q10UD(E)HCPU, Q13UD(E)HCPU, Q20UD(E)HCPU, .Q26UD(E)HCPU only.

12-9

Error
Code

[FUSE BREAK OFF]
There is an output module with a blown fuse.
■Collateral information
• Common Information:Module No.(Slot No.)
[For Remote I/O
network]Network No./
Station No.
• Individual Information:–
■Diagnostic Timing
• Always

1300

1310

1311

• Check FUSE. LED of the output modules and
replace the module whose LED is lit.
(The module with a blown fuse can also be
identified using GX Developer.
Check the special registers SD1300 to SD1331
to see if the bit corresponding to the module is
"1".)
• When a GOT is bus-connected to the main base
unit or extension base unit, check the connection
status of the extension cable and the earth status
of the GOT.

Check ERR. LED of the output modules and
replace the module whose LED is lit.
(The module with a blown fuse can also be
identified using GX Developer. Check the special
registers SD130 to SD137 to see if the bit
corresponding to the module is "1".)

[I/O INT. ERROR]
An interruption has occurred although there is no
interrupt module.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• During interrupt

Any of the mounted modules is experiencing a
hardware fault. Therefore, check the mounted
modules and change the faulty module. (Contact
your local Mitsubishi representative.)

[I/O INT. ERROR]
An interrupt request from other than the interrupt
module was detected.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• During interrupt

Take action so that an interrupt will not be issued
from other than the interrupt module.

[LAN CTRL.DOWN]
The H/W self-diagnostics detected a LAN controller
failure.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

1321

Corrective Action

[FUSE BREAK OFF]
There is an output module with a blown fuse.
■Collateral information
• Common Information:Module No.(Slot No.)
[For Remote I/O
network]Network No./
Station No.
• Individual Information:–
■Diagnostic Timing
• Always

[I/O INT. ERROR]
An interrupt request from the module where
interrupt pointer setting has not been made in the
PLC parameter dialog box was detected.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• During interrupt

1320

*1
*4
*5
*13

Error Contents and Cause

• Correct the interrupt pointer setting in the PLC
system setting of the PLC parameter dialog box.
• Take measures so that an interrupt is not issued
from the module where the interrupt pointer
setting in the PLC system setting of the PLC
parameter dialog box has not been made.
Correct the interrupt setting of the network
parameter. Correct the interrupt setting of the
intelligent function module buffer memory.
Correct the basic program of the QD51.

This suggests a CPU module hardware fault.
(Contact your local Mitsubishi representative.)

CPU operation can be set in the parameters at error occurrence. (LED indication varies.)
Function version is B or later.
Function version is A.
This applies to the Built-in Ethernet port QCPU.

12-10

LED Status
CPU Status

RUN:
Off/On
ERR.:
Flicker/On

Corresponding
CPU

Qn(H)
QnPH
QnPRH
QnU

CPU Status:
Stop/
Continue*1
Q00J/Q00/Q01

QCPU

RUN:
Off
ERR.:
Flicker

Q00J/Q00/Q01*4
QnU

CPU Status:
Stop

Q00J/Q00/Q01 *5
QnPRH
QnU

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

QnU*13

Error
Code

1401

1402

1403

*2

LED Status
CPU Status

Corrective Action

[SP. UNIT DOWN]
• There was no response from the intelligent
function module/special function module in the
initial processing.
• The size of the buffer memory of the intelligent
function module/special function module is
invalid.
• The unsupported module is mounted.
■Collateral information
• Common Information:Module No.(Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset/When intelligent function
module is accessed

When the unsupported module is mounted, remove
it.
When the corresponding module is supported, this
suggests the intelligent function module/special
function module, CPU module and/or base unit is
expecting a hardware fault (Contact your local
Mitsubishi representative.)

[SP. UNIT DOWN]
The intelligent function module/special function
module was accessed in the program, but there
was no response.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:Program error location
■Diagnostic Timing
• When an intelligent function module access
instruction is executed

This suggests the intelligient function module/
special function module , CPU module and/or base
unit is expecting a hardware fault (Contact your
local Mitsubishi representative.)

[SP. UNIT DOWN]
• The unsupported module is mounted.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• When an END instruction executed

When the unsupported module is mounted, remove
it.
When the corresponding module is supported, this
suggests the intelligent function module/special
function module , CPU module and/or base unit is
expecting a hardware fault (Contact your local
Mitsubishi representative.)

[SP. UNIT DOWN]
• There was no response from the intelligent
function module/special function module when
the END instruction is executed.
• An error is detected at the intelligent function
module/special function module.
• The I/O module (intelligent function module/
special function module) is nearly removed,
completely removed, or mounted during running.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• Always

The CPU module, base module and/or the
intelligent function module/special function module
that was accessed is experiencing a hardware
fault. (Contact your local Mitsubishi representative.)

[CONTROL-BUS. ERR.]
When performing a parameter I/O allocation the
intelligent function module/special function module
could not be accessed during initial
communications.
(On error occurring, the head I/O number of the
corresponding intelligent function module/special
function module is stored in the common
information.)
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

Reset the CPU module and RUN it again. If the
same error is displayed again, the intelligent
function module/special function module, CPU
module or base unit is faulty. (Contact your local
Mitsubishi representative.)

Corresponding
CPU

1
2
3
12
6

RUN:
Off/On
ERR.:
Flicker/On

6

CPU Status:
Stop/
Continue*2

7
QCPU

8

12.1 Error Code List
12.1.3 Error code list (1000 to 1999)

1411

Error Contents and Cause

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

In the QCPU, either error stop or continue can be selected for each intelligent function module by the parameters.

12-11

Error
Code

Error Contents and Cause
[CONTROL-BUS. ERR.]
The FROM/TO instruction is not executable, due to
a control bus error with the intelligent function
module/special function module.
(On error occurring, the program error location is
stored in the individual information.)
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:Program error location
■Diagnostic Timing
• During execution of FROM/TO instruction set

1412

[CONTROL-BUS. ERR.]
In a multiple CPU system, a CPU module
incompatible with the multiple CPU system is
mounted.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

1413

[CONTROL-BUS. ERR.]
An error is detected on the system bus.
• Self-diagnosis error of the system bus.
• Self-diagnosis error of the CPU module
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always
[CONTROL-BUS. ERR.]
• Fault of a loaded module was detected.
• In a multiple CPU system, a CPU module
incompatible with the multiple CPU system is
mounted.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• Always

1414

[CONTROL-BUS. ERR.]
An error is detected on the system bus.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• Always

*4

Function version is B or later.

12-12

Corrective Action

LED Status
CPU Status

Reset the CPU module and RUN it again. If the
same error is displayed again, the intelligent
function module/special function module, CPU
module or base unit is faulty. (Contact your local
Mitsubishi representative.)

QCPU

• Remove the CPU module incompatible with the
multiple CPU system from the main base unit, or
replace the CPU module incompatible with the
multiple CPU system with a CPU module
compatible with the multiple CPU system.
• The intelligent function module, CPU module or
base unit is faulty. (Contact your local Mitsubishi
representative.)

Reset the CPU module and RUN it again. If the
same error is displayed again, the intelligent
function module, CPU module or base unit is faulty.
(Contact your local Mitsubishi representative.)

• Remove the CPU module incompatible with the
multiple CPU system from the main base unit, or
replace the CPU module with a CPU module
compatible with the multiple CPU system.
• Reset the CPU module and RUN it again. If the
same error is displayed again, the intelligent
function module, CPU module or base unit is
faulty. (Contact your local Mitsubishi
representative.)

Reset the CPU module and RUN it again. If the
same error is displayed again, the intelligent
function module, CPU module or base unit is faulty.
(Contact your local Mitsubishi representative.)

Corresponding
CPU

Q00J/Q00/Q01*4
Qn(H)*4
QnPH

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

QCPU

Q00J/Q00/Q01*4
Qn(H)*4
QnPH
QnU

Q00J/Q00/Q01*4
Qn(H)
QnPH
QnPRH
QnU

Error
Code

Error Contents and Cause

Corrective Action

LED Status
CPU Status

[CONTROL-BUS. ERR.]
Fault of the main or extension base unit was
detected.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• When an END instruction executed
1415

1416

[CONTROL-BUS. ERR.]
Fault of the main or extension base unit was
detected.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power-ON/ At reset/ When an END instruction
executed

1418

[CONTROL-BUS.ERR.]
In the redundant system, at power-on/reset or
switching system, the control system cannot
access the extension base unit since it failed to
acquire the access right.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power-ON/ At reset/ At Switching execution

1430

[MULTI-C.BUS ERR.]
The error of host CPU is detected in the Multiple
CPU high speed bus.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

*4
*8
*9
*10

1

Qn(H)*4
QnPH
QnPRH
QnU

2

Qn(H)

*8

QnPH*8

Qn(H)*4
QnPH
QnU

RUN:
Off
ERR.:
Flicker

Q00/Q01*4
QnU

12
6
6
7
8

Reset the CPU module and RUN it again. If the
CPU Status:
same error is displayed again, the intelligent
Stop
function module, CPU module or base unit is faulty.
(Contact your local Mitsubishi representative.)
QnPRH

Reset the CPU module and RUN it again. If the
same error is displayed again, the CPU module,
the Q6 WRB, or hardware of extension cable is
faulty. (Contact your local Mitsubishi representative,
explaining a detailed description of the problem.)

Reset the CPU module and RUN it again. If the
same error is displayed again, the CPU module has
hardware failure. (Contact your local Mitsubishi
representative, explaining a detailed description of
the problem.)

QnPRH*9

QnU*10

Function version is B or later.
The module whose first 5 digits of serial No. is "08032" or later.
The module whose first 5 digits of serial No. is "09012" or later.
The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.

12-13

12.1 Error Code List
12.1.3 Error code list (1000 to 1999)

1417

[CONTROL-BUS. ERR.]
A reset signal error was detected on the system
bus.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

Q00J/Q00/Q01

3

Reset the CPU module and RUN it again. If the
same error is displayed again, the intelligent
function module, CPU module or base unit is faulty.
(Contact your local Mitsubishi representative.)

[CONTROL-BUS. ERR.]
System bus fault was detected at power-on or
reset.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset
[CONTROL-BUS. ERR.]
In a multiple CPU system, a bus fault was detected
at power-on or reset.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

Corresponding
CPU

Error
Code

Error Contents and Cause

Corrective Action

1431

[MULTI-C.BUS ERR.]
The communication error with other CPU is
detected in the Multiple CPU high speed bus.
■Collateral information
• Common Information:Module No. (CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

• Take noise reduction measures.
• Check the main base unit mounting status of the
CPU module.
• Reset the CPU module and RUN it again. If the
same error is displayed again, the CPU module
has hardware failure. (Contact your local
Mitsubishi representative, explaining a detailed
description of the problem.)

1432

[MULTI-C.BUS ERR.]
The communication time out with other CPU is
detected in the Multiple CPU high speed bus.
■Collateral information
• Common Information:Module No. (CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

Reset the CPU module and RUN it again. If the
same error is displayed again, the CPU module has
hardware failure. (Contact your local Mitsubishi
representative, explaining a detailed description of
the problem.)

[MULTI-C.BUS ERR.]
The communication error with other CPU is
detected in the Multiple CPU high speed bus.
■Collateral information
• Common Information:Module No. (CPU No.)
• Individual Information:–
■Diagnostic Timing
• Always

• Take noise reduction measures.
• Check the main base unit mounting status of the
CPU module.
• Reset the CPU module and RUN it again. If the
same error is displayed again, the CPU module
has hardware failure. (Contact your local
Mitsubishi representative, explaining a detailed
description of the problem.)

1433
1434

1435

1436

[MULTI-C.BUS ERR.]
The error of the Multiple CPU high speed main
base unit is detected. (The error of the Multiple
CPU high speed bus is detected.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

1437

1439

[MULTI-C.BUS ERR.]
An error of the multiple CPU high speed main base
unit was detected. (An error of the multiple CPU
high speed bus was detected.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

1500

[AC/DC DOWN]
• A momentary power supply interruption has
occurred.
• The power supply went off.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

*10

Reset the CPU module and RUN it again. If the
same error is displayed again, the CPU module has
hardware failure. (Contact your local Mitsubishi
representative, explaining a detailed description of
the problem.)

RUN:
Off
ERR.:
Flicker

Corresponding
CPU

QnU*10

CPU Status:
Stop

• Take noise reduction measures.
• Check the main base unit mounting status of the
CPU module.
• Reset the CPU module and RUN it again. If the
same error is displayed again, the CPU module
has hardware failure. (Contact your local
Mitsubishi representative, explaining a detailed
description of the problem.)

Reset the CPU module and RUN it again. If the
same error is displayed again, the CPU module has
hardware failure. (Contact your local Mitsubishi
representative, explaining a detailed description of
the problem.)

Check the power supply.

The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.

12-14

LED Status
CPU Status

RUN:
On
ERR.:
Off
CPU Status:
Continue

QCPU

Error
Code

1510

1520

1600

1601

*3
*6
*12
*14

[SINGLE PS. DOWN]
The power supply voltage of either of redundant
power supply modules on the redundant base unit
dropped.
■Collateral information
• Common Information:Base No./ Power supply No.
• Individual Information:–
■Diagnostic Timing
• Always

Corrective Action

Check the power supplied to the redundant power
supply modules mounted on the redundant base
unit.

Hardware fault of the redundant power supply
module. (Contact your local Mitsubishi
representative, explaining a detailed description of
the problem.)

[BATTERY ERROR*3]
• The battery voltage in the CPU module has
dropped below stipulated level.
• The lead connector of the CPU module battery is
not connected.
• The lead connector of the CPU module battery is
not securely engaged.
■Collateral information
• Common Information:Drive Name
• Individual Information:–
■Diagnostic Timing
• Always

• Change the battery.
• If the battery is for program memory, standard
RAM or for the back-up power function, install a
lead connector.
• Check the lead connector of the CPU module for
looseness. Firmly engage the connector if it is
loose.

[FLASH ROM ERROR]
The number of writing to flash ROM (standard ROM
and system securement area) exceeds 100,000
times.
(Number of writings >100,000 times)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• When writing to ROM

Corresponding
CPU

1

[SINGLE PS. ERROR]
On the redundant base unit, the one damaged
redundant power supply module was detected.
■Collateral information
• Common Information:Base No./ Power supply No.
• Individual Information:–
■Diagnostic Timing
• Always

[BATTERY ERROR*3]
Voltage of the battery on memory card has dropped
below stipulated level.
■Collateral information
• Common Information:Drive Name
• Individual Information:–
■Diagnostic Timing
• Always

LED Status
CPU Status

RUN:
On
ERR.:
On
CPU Status:
Continue

Qn(H)*6
QnPH*6
QnPRH
QnU*12

2
3
12
6

QCPU
RUN:
On
ERR.:
Off

6
7

CPU Status:
Continue
Qn(H)
QnPH
QnPRH

Change the battery.

8

QnU*14

Change the CPU module.

RUN:
On
ERR.:
On

QnU

CPU Status:
Continue

BAT. LED is displayed at BATTERY ERROR.
The module whose first 5 digits of serial No. is "04101" or later.
The module whose first 5 digits of serial No. is "10042" or later.
The Universal model QCPU except the Q00UJCPU, Q00UCPU, and Q01UCPU.

12-15

12.1 Error Code List
12.1.3 Error code list (1000 to 1999)

1610

Error Contents and Cause

12.1.4

Error code list (2000 to 2999)

The following shows the error messages from the error code 2000 to 2999, the contents and
causes of the errors, and the corrective actions for the errors.
Error
Code
(SD0)

2000

Replace the CPU module incompatible with the
multiple CPU system with a CPU module
compatible with the multiple CPU system.

[UNIT VERIFY ERR.]
The I/O module status is different from the I/O
module information at power ON.
• I/O module (or intelligent function module) is not
installed properly or installed on the base unit.
■Collateral information
• Common Information:Module No. (Slot No.)
[For Remote I/O network]
Network No./Station No.
• Individual Information:–
■Diagnostic Timing
• When an END instruction executed

Read the error common information at the GX
Developer, and check and/or change the module
that corresponds to the numerical value (module
number) there.
Alternatively, monitor special registers SD150 to
SD157 using GX Developer, and check and replace
the module where the bit of its data is "1".

[UNIT VERIFY ERR.]
I/O module information power ON is changed.
• I/O module (or intelligent function module/special
function module) not installed properly or
installed on the base unit.
■Collateral information
• Common Information:Module No. (Slot No.)
[For Remote I/O network]
Network No./Station No.
• Individual Information:–
■Diagnostic Timing
• When an END instruction executed

• Read the common information of the error using
the peripheral device, and check and/or change
the module that corresponds to the numerical
value (module number) there.
• Alternatively, monitor the special registers
SD1400 to SD1431 at a peripheral device, and
change the fuse at the output module whose bit
has a value of "1".
• When a GOT is bus-connected to the main base
unit or extension base unit, check the connection
status of the extension cable and the grounding
status of the GOT.

[BASE LAY ERROR]
• More than applicable number of extension base
units have been used.
• When a GOT was bus-connected, the CPU
module was reset while the power of the GOT
was OFF.
■Collateral information
• Common Information:Base No.
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

2010

Corrective Action

[UNIT VERIFY ERR.]
In a multiple CPU system, a CPU module
incompatible with the multiple CPU system is
mounted.
■Collateral information
• Common Information:Module No. (Slot No.)
[For Remote I/O network]
Network No./Station No.
• Individual Information:–
■Diagnostic Timing
• When an END instruction executed

[UNIT VERIFY ERR.]
During operation, a module was mounted on the
slot where the empty setting of the CPU module
was made.
■Collateral information
• Common Information:Module No. (CPU No.)
• Individual Information:–
■Diagnostic Timing
• When an END instruction executed

2001

*1
*2
*3

Error Contents and Cause

Corresponding
CPU

Qn(H)*3
QnPH

RUN:
Off/On
ERR.:
Flicker/On

Q00J/Q00/Q01

CPU Status:
Stop/
Continue*1

During operation, do not mount a module on the
slot where the empty setting of the CPU module
was made.

Qn(H)
QnPH
QnPRH
QnU

RUN:
Off/On
ERR.:
Flicker/On

Q00J/Q00/Q01*3
QnU

CPU Status:
Stop/
Continue*2

• Use the allowable number of extension base
units or less.
• Power on the Progammable Controller and GOT
again.

CPU operation can be set in the parameters at error occurrence. (LED indication varies.)
Either error stop or continue can be selected for each module by the parameters.
The function version is B or later.

12-16

LED Status
CPU Status

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

Q00J/Q00/Q01*3
QnPRH
Q00UJ
Q00U/Q01U
Q02U

Error
Code
(SD0)

Error Contents and Cause

Corrective Action

LED Status
CPU Status

Corresponding
CPU

1

[BASE LAY ERROR]
The QA1S6 B, QA6 B, or
QA6ADP+A5 B/A6 B was used as the base unit.
2011

■Collateral information
• Common Information:Base No.
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

Q00J/Q00/Q01*3
QnPH
QnPRH
QnU

Do not use the QA1S6 B, QA6 B, or
QA6ADP+A5 B/A6 B as the base unit.

3

[BASE LAY ERROR]
The GOT is bus-connected to the main base unit of
the redundant system.
The following errors are detected in the CPU
redundant system compatible with the extension
base unit.
• The base unit other than the Q6 WRB is
connected to the extension stage No.1.
• The base unit is connected to any one of the
extension stages No.2 to No.7, although the
Q6 WRB does not exist in the extension stage
2012

No.1 .
• The other system CPU module is incompatible
with the extension base unit.
• The Q5 B, QA1S6 B, QA6 B or
QA6ADP+A5 B/A6 B is connected.
• The number of slots of the main base unit for
both systems is different.
Information of the Q6 WRB cannot be read

2

12
• Remove a bus connection cable for GOT
connection connected to the main base unit.

6

• Use the Q6 WRB (fixed to the extension stage
No.1)
• Use the CPU module compatible with the
extension base unit for the other system.

6

• Do not use the Q5 B, QA1S6 B, QA6 B or
QA6ADP+A5 B/A6 B for the base unit.
• Use the main base unit which has the same
number of slots.
• Hardware failure of the Q6 WRB. (Contact your
local Mitsubishi representative, explaining a
detailed description of the problem.)

correctly.
■Collateral information
• Common Information:Base No.
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

RUN:
Off
ERR.:
Flicker

QnPRH*6

7
8

CPU Status:
Stop

[BASE LAY ERROR]
Stage number of the Q6 WRB is recognized as

[EXT.CABLE ERR.]
The following errors are detected in the redundant
system.
• At power-on/reset, the standby system has
detected the error in the path between the control
system and the Q6 WRB.
2020

• The standby system has detected the error in the
path between the host system CPU and the
Q6 WRB at END processing.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power-ON/At reset/ When an END instruction
executed

*3
*6

Hardware failure of the Q6 WRB. (Contact your

12.1 Error Code List
12.1.4 Error code list (2000 to 2999)

2013

other than extension stage No.1 in the redundant
system.
■Collateral information
• Common Information:Base No.
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

local Mitsubishi representative, explaining a
detailed description of the problem.)

Check to see if the extension cable between the
main base unit and the Q6 WRB is connected
correctly. If not, connect it after turning OFF the
main base unit where the extension cable will be
connected.
If the cable is connected correctly, hardware of the

QnPRH*6

CPU module, Q6 WRB, or extension cable is
faulty. (Contact your local Mitsubishi representative,
explaining a detailed description of the problem.)

The function version is B or later.
The module whose first 5 digits of serial No. is "09012" or later.

12-17

Error
Code
(SD0)

2100

*3

[SP. UNIT LAY ERR.]
The slot to which the QI60 is mounted is set to
other than Inteli (intelligent function module) or
Interrupt (interrupt module) in the I/O assignment of
PLC parameter.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

Make setting again to match the PLC parameter I/O
assignment with the actual loading status.

Qn(H)*3
QnPH
QnPRH

[SP. UNIT LAY ERR.]
• In the I/O assignment setting of PLC parameter,
Inteli (intelligent function module) was allocated
to an I/O module or vice versa.
• In the I/O assignment setting of PLC parameter,
a module other than CPU (or nothing) was
allocated to the location of a CPU module or vice
versa.
• In the I/O assignment setting of the PLC
parameter, switch setting was made to the
module that has no switch setting.
• In the I/O assignment setting of the PLC
parameter dialog box, the number of points
assigned to the intelligent function module is less
than the number of points of the mounted
module.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

• Make the PLC parameter’s I/O assignment
setting again so it is consistent with the actual
status of the intelligent function module and the
CPU module.
• Delete the switch setting in the I/O assignment
setting of the PLC parameter.

Qn(H)
QnPH
QnPRH
QnU

[SP. UNIT LAY ERR.]
13 or more A-series special function modules
(except for the A1SI61) that can initiate an interrupt
to the CPU module have been installed.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

The function version is B or later.

12-18

Corresponding
CPU

Corrective Action

RUN:
Off
ERR.:
Flicker

[SP. UNIT LAY ERR.]
• In the parameter I/O allocation settings, an Inteli
(intelligent function module) was allocated to a
location reserved for an I/O module or vice versa.
• In the parameter I/O allocation settings, a module
other than CPU (or nothing) was allocated to a
location reserved for a CPU module or vice
versa.
Reset the parameter I/O allocation setting to
• In the I/O assignment setting of the PLC
conform to the actual status of the intelligent
parameter dialog box, the number of points
function module and the CPU module.
assigned to the intelligent function module is less
than the number of points of the mounted
module.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

2101

LED Status
CPU Status

Error Contents and Cause

Reduce the A series special function modules
(except the A1SI61) that can make an interrupt
start to the CPU module to 12 or less.

CPU Status:
Stop

Q00J/Q00/Q01

Qn(H)

Error
Code
(SD0)

2102

Error Contents and Cause
[SP. UNIT LAY ERR.]
Seven or more A1SD51S have been installed.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset
[SP. UNIT LAY ERR.]
• Two or more QI60/A1SI61 modules are mounted
in a single CPU system.
• Two or more QI60/A1SI61 modules are set to the
same control CPU in a multiple CPU system.
• Two or more A1SI61 modules are loaded in a
multiple CPU system.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

2103

LED Status
CPU Status

Corresponding
CPU

1
Keep the number of A1SD51S to six or fewer.

Qn(H)

2
• Reduce the number of QI60/A1SI61 modules
mounted in the single CPU system to one.
• Change the number of QI60/A1SI61 modules set
to the same control CPU to only one in the
multiple CPU system.
• Reduce the number of A1SI61 modules to only
one in the multiple CPU system. When using an
interrupt module with each QCPU in a multiple
CPU system, replace it with the QI60. (Use one
A1SI61 module + max. three QI60 modules or
only the QI60 modules.)

[SP. UNIT LAY ERR.]
Two or more QI60, A1SI61 interrupt modules have
been mounted.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

Install only 1 QI60, A1SI61 module.

[SP. UNIT LAY ERR.]
Two or more QI60 modules are mounted.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

Reduce the QI60 modules to one.

3
Qn(H)*3
QnPH

6

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

12

Qn(H)
QnPRH

6
7

• Reduce the QI60 modules to one.
• Make interrupt pointer setting to the second QI60
module and later.

Q00J/Q00/Q01*5

Q00J/Q00/Q01*3
QnU

The function version is B or later.
The module whose first 5 digits of serial No. is "04101" or later.

12-19

8

12.1 Error Code List
12.1.4 Error code list (2000 to 2999)

[SP. UNIT LAY ERR.]
Two or more QI60 modules where interrupt pointer
setting has not been made are mounted.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

*3
*5

Corrective Action

Error
Code
(SD0)

2106

*6
*7
*9

Error Contents and Cause

Corrective Action

Corresponding
CPU

[SP.UNIT LAY ERR.]
• Two or more MELSECNET/H modules are
mounted.
• Two or more CC-Link IE controller network
modules are mounted.
• Two or more Ethernet modules are mounted.
■Collateral information
• Common Information:Module No.
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

• Reduce the number of MELSECNET/H modules
to one.
• Reduce the number of CC-Link IE controller
network modules to one.
• Reduce the number of Ethernet modules to one.

Q00UJ

[SP.UNIT LAY ERR.]
• Five or more MELSECNET/H and CC-Link IE
controller network modules in total are mounted
in the entire system.
• Two or more MELSECNET/H modules are
mounted in the entire system.
• Two or more CC-Link IE controller network
modules are mounted in the entire system.
• Two or more Ethernet modules are mounted in
the entire system.
■Collateral information
• Common Information:Module No.
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

• Reduce the number of MELSECNET/H and CCLink IE controller network modules to four or less
in total in the entire system.
• Reduce the number of MELSECNET/H modules
to one in the entire system.
• Reduce the number of CC-Link IE controller
network modules to one in the entire system.
• Reduce the number of Ethernet modules to one
in the entire system.

Q00U/Q01U

[SP.UNIT LAY ERR.]
• Three or more MELSECNET/H and CC-Link IE
controller network modules in total are mounted
in the entire system.
• Three or more Ethernet interface modules are
mounted in the entire system.
■Collateral information
• Common Information:Module No.
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

• Reduce the MELSECNET/H and CC-Link IE
controller network modules up to two or less in
the entire system.
• Reduce the Ethernet interface modules up to two
or less in the entire system.

[SP.UNIT LAY ERR.]
• Five or more MELSECNET/H and CC-Link IE
controller network modules in total are mounted
in the entire system.
• Five or more Ethernet interface modules are
mounted in the entire system.
■Collateral information
• Common Information:Module No.
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

• Reduce the MELSECNET/H and CC-Link IE
controller network modules up to four or less in
the entire system.
• Reduce the Ethernet interface modules up to four
or less in the entire system.

[SP.UNIT LAY ERR.]
• Three or more CC-Link IE controller network
modules are mounted in the entire system.
• Five or more MELSECNET/H and CC-Link IE
controller network modules in total are mounted
in the entire system.
■Collateral information
• Common Information:Module No.
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

• Reduce the CC-Link IE controller network
modules up to two or less in the entire system.
• Reduce the total number of the MELSECNET/H
and CC-Link IE controller network modules up to
four or less in the entire system.

The module whose first 5 digits of serial No. is "09012" or later.
The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
The module whose first 5 digits of serial No. is "10042" or later.

12-20

LED Status
CPU Status

RUN:
Off
ERR.:
Flicker

Q02U

CPU Status:
Stop

QnU*7

Qn(H)*6
QnPH*9
QnPRH*9

Error
Code
(SD0)

2106

Error Contents and Cause

Corrective Action

Corresponding
CPU

1

[SP. UNIT LAY ERR.]
• Five or more MELSECNET/H modules have
been installed.
• Five or more Ethernet interface modules have
been installed.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

• Reduce the number of MELSECNET/H modules
to four or less.
• Reduce the number of Ethernet modules to four
or less.

[SP. UNIT LAY ERR.]
• Two or more MELSECNET/H modules were
installed.
• Two or more Ethernet modules were installed.
• Three or more CC-Link modules were installed.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

• Reduce the MELSECNET/H modules to one or
less.
• Reduce the Ethernet modules to one or less.
• Reduce the CC-Link modules to two or less.

[SP. UNIT LAY ERR.]
• The same network number or same station
number is duplicated in the MELSECNET/H
network system.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

LED Status
CPU Status

Qn(H)
QnPH
QnPRH

2
3

• Check the network number and station number.

12
Q00J/Q00/Q01

6
RUN:
Off
ERR.:
Flicker

Q00J/Q00/Q01
Qn(H)
QnPH
QnPRH

CPU Status:
Stop

2107

[SP. UNIT LAY ERR.]
The start X/Y set in the PLC parameter’s I/O
assignment settings is overlapped with the one for
another module.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

Make the PLC parameter’s I/O assignment setting
again so it is consistent with the actual status of the
intelligent function module/special function
modules.

QCPU

2108

[SP. UNIT LAY ERR.]
• Network module A1SJ71LP21, A1SJ71BR11,
A1SJ71AP21, A1SJ71AR21, or A1SJ71AT21B
dedicated for the A2USCPU has been installed.
• Network module A1SJ71QLP21 or
A1SJ71QBR11 dedicated for the Q2AS has been
installed.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

Replace the network module for the A2USCPU or
the network module for the Q2ASCPU with the
MELSECNET/H module.

Qn(H)

6
7
8

12.1 Error Code List
12.1.4 Error code list (2000 to 2999)

12-21

Error
Code
(SD0)

Error Contents and Cause

Corrective Action

[SP. UNIT ERROR]
• The location designated by the FROM/TO
instruction set is not the intelligent function
module/special function module.
• The module that does not include buffer memory
has been specified by the FROM/TO instruction.
• The intelligent function module/special function
module, Network module being accessed is
faulty.
• Station not loaded was specified using the
instruction whose target was the CPU share
memory.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:Program error location
■Diagnostic Timing
• When instruction executed

2110

[SP. UNIT ERROR]
• The location designated by a link direct device

LED Status
CPU Status

Corresponding
CPU

Q00J/Q00/Q01
Qn(H)*3
QnPH
QnPRH
QnU

• Read the individual information of the error using
the GX Developer, check the FROM/TO
instruction that corresponds to that numerical
value (program error location), and correct when
necessary.
• The intelligent function module/special function
module that was accessed is experiencing a
hardware fault. Therefore, change the faulty
module. Alternatively, contact your local
Mitsubishi representative.

(J \ ) is not a network module.
• The I/O module (intelligent function module/
special function module) was nearly removed,
completely removed, or mounted during running.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:Program error location
■Diagnostic Timing
• When instruction executed

2111

[SP. UNIT ERROR]
• The module other than intelligent function
module/special function module is specified by
the intelligent function module/special function
module dedicated instruction.
Or, it is not the corresponding intelligent function
module/special function module.
• There is no network No. specified by the network
dedicated instruction.
Or the relay target network does not exit.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:Program error location
■Diagnostic Timing

2112

• When instruction executed/STOP

CPU Status:
Stop/
Continue*1

• When instruction executed/STOP

RUN

RUN

CPU operation can be set in the parameters at error occurrence. (LED indication varies.)
The function version is B or later.

12-22

QCPU

Read the individual information of the error using a
peripheral device, and check the special function
module /special function module dedicated
instruction (network instruction) that corresponds to
the value (program error part) to make modification.

[SP. UNIT ERROR]
The module other than network module is specified
bythe network dedicated instruction.
■Collateral information
• Common Information:FFFFH (fixed)
• Individual Information:Program error location
■Diagnostic Timing

2113

*1
*3

RUN:
Off/On
ERR.:
Flicker/On

Qn(H)
QnPH

Error
Code
(SD0)

2114

Error Contents and Cause

2117

RUN

[SP. UNIT ERROR]
• An instruction that does not allow the under the
control of another CPU to be specified is being
used for a similar task.
• Instruction was executed for the A or QnA
module under control of another CPU.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:Program error location
■Diagnostic Timing
• When instruction executed/ STOP

Qn(H)*3
QnPH
QnU

Q00J/Q00/Q01*3
Qn(H)*3
QnPH
Read the individual information of the error using
the GX Developer, check the program
corresponding that value (program error location),
and make correction.

7
Q00J/Q00/
Q01*3
Qn(H)*3
QnPH
QnU

• When performing the online module change in a
multiple CPU system, correct the program so that
access will not be made to the intelligent function
module controlled by the other CPU.
• When accessing the intelligent function module
controlled by the other CPU in a multiple CPU
system, set the online module change setting to
be “disabled” by parameter.

6
6

RUN:
Off/On
ERR.:
Flicker/On
CPU Status:
Stop/Continue

12

Qn(H)*3
QnPH
QnU*7

The function version is B or later.
The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.

12-23

8

12.1 Error Code List
12.1.4 Error code list (2000 to 2999)

function module device (U \ G) is specified.

2
3

RUN

■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:Program error location
■Diagnostic Timing
• When instruction executed

*3
*7

Q00J/Q00/Q01*3

RUN

[SP. UNIT ERROR]
When the online module change setting is set to be
“enabled” in the PLC parameter in a multiple CPU
system, intelligent function module controlled by
other CPU using the FROM instruction/intelligent
2118

1

[SP. UNIT ERROR]
A CPU module that cannot be specified in the
instruction dedicated to the multiple CPU system
was specified.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:Program error location
■Diagnostic Timing
• When instruction executed/ STOP

Corresponding
CPU

RUN

[SP. UNIT ERROR]
An instruction, which on execution specifies the
host CPU, has been used for specifying other
CPUs. (An instruction that does not allow other
stations to be specified).
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:Program error location
■Diagnostic Timing
• When instruction executed/ STOP

2116

LED Status
CPU Status

[SP. UNIT ERROR]
An instruction, which on execution specifies other
stations, has been used for specifying the host
CPU. (An instruction that does not allow the host
CPU to be specified).
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:Program error location
■Diagnostic Timing
• When instruction executed/ STOP

2115

Corrective Action

Error
Code
(SD0)

Error Contents and Cause

Corrective Action

LED Status
CPU Status

Corresponding
CPU

[SP. UNIT LAY ERR.]
The locations of the Q5 B/Q6 B, QA1S6 B/
QA6 B, and QA6ADP+A5 B/A6 B are
improper.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

2120

[SP. UNIT LAY ERR.]
The CPU module is installed to other than the CPU
slot and slots 0 to 2.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

2121

Q00J/Q00/Q01*4
Qn(H)
QnPH

Check the location of the base unit.

Check the loading position of the CPU module and
reinstall it at the correct slot.

Qn(H)
QnPH

[SP. UNIT LAY ERR.]
The QA1S6 B/QA6 B and QA6ADP+A5 B/
A6 B are used for the main base unit.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

2122

2124

*4
*7

[SP. UNIT LAY ERR.]
• A module is mounted on the 65th slot or later
slot.
• A module is mounted on the slot whose number
is greater than the number of slots specified at
[Slots] in [Standard setting] of the base setting.
• A module is mounted on the slot whose number
of I/O points exceeds 4096 points.
• A module is mounted on the slot whose number
of I/O points strides 4096 points.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

• Remove the module mounted on the 65th slot or
later slot.
• Remove the module mounted on the slot whose
number is greater than the number of slots
specified at [Slots] in [Standard setting] of the
base setting.
• Remove the module mounted on the slot whose
number of I/O points exceeds 4096 points.
• Replace the module with the one whose number
of occupied points does not exceed 4096 points.

[SP. UNIT LAY ERR.]
• A module is mounted on after the 25th slot (on
after the 17th slot for the Q00UJ).
• A module is mounted on the slot whose number
is later than the one set in the "Base setting" on
the I/O assignment tab of PLC parameter in GX
Developer.
• A module is mounted on the slot for which I/O
points greater than 1024 (greater than 256 for
the Q00UJ) is assigned.
• A module is mounted on the slot for which I/O
points is assigned from less than 1024 to greater
than 1024 (from less than 256 to greater than
256 for the Q00UJ).
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

• Remove the module mounted on after the 25th
(on after the 17th slot for the Q00UJ).
• Remove the module mounted on the slot whose
number is later than the one set in the "Base
setting" on the I/O assignment tab of PLC
parameter in GX Developer.
• Remove the module mounted on the slot for
which I/O points greater than 1024 (greater than
256 for the Q00UJ) is assigned.
• Replace the end module with the one whose
number of occupied points is within 1024 (within
256 for the Q00UJ).

The function version is A.
The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.

12-24

Qn(H)
QnPH
QnPRH

Replace the main base unit with a usable one.

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

Qn(H)
QnPH
QnPRH
QnU*7

Q00UJ
Q00U/Q01U

Error
Code
(SD0)

2124

Error Contents and Cause

Corrective Action

[SP. UNIT LAY ERR.]
• A module is mounted on the 37th slot or later
slot.
• A module is mounted on the slot whose number
is greater than the number of slots specified at
[Slots] in [Standard setting] of the base setting.
• A module is mounted on the slot whose number
of I/O points exceeds 2048 points.
• A module is mounted on the slot whose number
of I/O points strides 2048 points.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

• Remove the module mounted on the 37th slot or
later slot.
• Remove the module mounted on the slot whose
number is greater than the number of slots
specified at [Slots] in [Standard setting] of the
base setting.
• Remove the module mounted on the slot whose
number of I/O points exceeds 2048 points.
• Replace the module with the one whose number
of occupied points does not exceed 2048 points.

[SP. UNIT LAY ERR.]
• A module is mounted on the 25th slot or later
slot. (The 17th slot or later slot for the Q00J.)
• A module is mounted on the slot whose number
is greater than the number of slots specified at
[Slots] in [Standard setting] of the base setting.
• A module is mounted on the slot whose number
of I/O points exceeds 1024 points. (256 points for
the Q00J.)
• A module is mounted on the slot whose number
of I/O points strides 1024 points. (256 points for
the Q00J.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

• Remove the module mounted on the 25th slot or
later slot. (The 17th slot or later slot for the
Q00J.)
• Remove the module mounted on the slot whose
number is greater than the number of slots
specified at [Slots] in [Standard setting] of the
base setting.
• Remove the module mounted on the slot whose
number of I/O points exceeds 1024 points. (256
points for the Q00J.)
• Replace the module with the one whose number
of occupied points does not exceed 1024 points.
(256 points for the Q00J.)

[SP. UNIT LAY ERR.]
5 or more extension base units were added. (3
bases for Q00J)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

*4

Corresponding
CPU

1
2
Q02U

3
12
6
RUN:
Off
ERR.:
Flicker

Q00J/Q00/Q01

6
7

CPU Status:
Stop

8
Remove 5 or more extension base units. (3 bases
for Q00J)

Q00J/Q00/Q01*4

• Install a usable module.
• The intelligent function module/special function
module is experiencing a hardware fault.
(Contact your local Mitsubishi representative.)

QCPU

The function version is A.

12-25

12.1 Error Code List
12.1.4 Error code list (2000 to 2999)

2125

[SP. UNIT LAY. ERR.]
• A module which the QCPU cannot recognise has
been installed.
• There was no response form the intelligent
function module/special function module.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

LED Status
CPU Status

Error
Code
(SD0)

LED Status
CPU Status

Corresponding
CPU

Error Contents and Cause

Corrective Action

2126

[SP. UNIT LAY. ERR.]
CPU module locations in a multiple CPU system
are either of the following.
• There are empty slots between the QCPU and
QCPU/motion controller.
• A module other than the High Performance
model QCPU/Process CPU (including the motion
controller) is mounted on the left-hand side of the
High Performance model QCPU/Process CPU.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

• Mount modules on the available slots so that the
empty slots will be located on the right-hand side
of the CPU module.
• Remove the module mounted on the left-hand
side of the High Performance model QCPU/
Process CPU, and mount the High Performance
model QCPU/Process CPU on the empty slot.
Mount the motion CPU on the right-hand side of
the High Performance model QCPU/Process
CPU.

Qn(H)*3
QnPH

2128

[SP.UNIT LAY ERR.]
The unusable module is mounted on the extension
base unit in the redundant system.
■Collateral information
• Common Information:Module No.
• Individual Information:–
■Diagnostic Timing
• At power-ON/ At reset

• Remove the unusable module from the extension
base unit.

QnPRH*6

[SP. UNIT VER. ERR.]
In a multiple CPU system, the control CPU of the
intelligent function module incompatible with the
multiple CPU system is set to other than CPU No.1.
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/
At writing to progurammable controller

• Change the intelligent function module for the
one compatible with the multiple CPU system
(function version B).
• Change the setting of the control CPU of the
intelligent function module incompatible with the
multiple CPU system to CPU No.1.

2150

[SP. UNIT VER. ERR.]
Either of the following modules incompatible with
the redundant system has been mounted in a
redundant system.
• CC-Link IE controller network modules
• MELSECNET/H modules
• Ethernet modules
■Collateral information
• Common Information:Module No. (Slot No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/
At writing to progurammable controller

2151

*3
*6
*10

RUN:
Off
ERR.:
Flicker

Use either of the following modules compatible with
the redundant system.
• CC-Link IE controller network modules
• MELSECNET/H modules
• Ethernet modules

The function version is B or later.
The module whose first 5 digits of serial No. is "09012" or later.
The Universal model QCPU except the Q00UJCPU.

12-26

CPU Status:
Stop

Q00J/Q00/Q01
QnPH
QuU*10

QnPRH

Error
Code
(SD0)

Error Contents and Cause
[MISSING PARA.]
There is no parameter file in the drive specified as
valid parameter drive by the DIP switches.
■Collateral information
• Common Information:Drive Name
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/ STOP

2200

Corresponding
CPU

1
• Check and correct the valid parameter drive
settings made by the DIP switches.
• Set the parameter file to the drive specified as
valid parameter drive by the DIP switches.

Qn(H)
QnPH
QnPRH

3
Set the parameter file to the program memory.

Q00J/Q00/Q01

12
6
Set a parameter file in a drive to be valid.

QuU

RUN:
Off
ERR.:
Flicker

RUN

6

2211

[BOOT ERROR]
File formatting is failed at a boot.
■Collateral information
• Common Information:Drive name
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

• Reboot.
• CPU module hardware fault. (Contact your local
Mitsubishi representative, explaining a detailed
description of the problem.)

Qn(H)
QnPRH
QnU

2220

[RESTORE ERROR]
• The device information (number of points)
backuped by the device data backup function is
different from the number of device points of the
PLC parameter.
After this error occurred, perform restore per
power-on/reset until the number of device points is
identical to the number of device points in the PLC
parameter, or until the backup data is deleted.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

• Set the number of device points at the time of
backup to the device point setting in [PLC
parameter]. Then, turn ON from OFF power
supply, or reset the CPU and cancel reset.
• Delete the backuped data, and turn ON from
OFF power supply, or reset the CPU and cancel
reset.

QnU

Check the boot setting.

CPU Status:
Stop

Q00J/Q00/Q01*3
Qn(H)
QnPH
QnPRH
QnU

The function version is B or later.

12-27

7
8

12.1 Error Code List
12.1.4 Error code list (2000 to 2999)

2210

[BOOT ERROR]
The contents of the boot file are incorrect.
■Collateral information
• Common Information:Drive name
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

*3

2

RUN

[MISSING PARA.]
Parameter file does not exist in all drives where
parameters will be valid.
■Collateral information
• Common Information:Drive Name
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/ STOP

LED Status
CPU Status

RUN

[MISSING PARA.]
There is no parameter file at the program memory.
■Collateral information
• Common Information:Drive Name
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/ STOP

Corrective Action

Error
Code
(SD0)

Error Contents and Cause

Corrective Action

2221

[RESTORE ERROR]
• The device information backuped by the device
data backup function is incomplete. (Turning
power supply OFF or reset is suspected.)
Do not return the data when this error occurs. Also,
delete the incomplete device information at the time
of this error occurrence.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

Reset the CPU module and run it again.

2225

[RESTORE ERROR]
The model name of the restoration destination CPU
module is different from the one of the backup
source CPU module.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

Execute a restore for the CPU module whose name
is same as the backup source CPU module.

2226

[RESTORE ERROR]
• ·The backup data file is destroyed. (The content
of the file is different from the check code.
• Reading the backup data from the memory card
is not successfully completed.
• Since the write protect switch of the SRAM card
is set to on (write inhibited), the checked
"Restore for the first time only" setting cannot be
performed.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

2227

[RESTORE ERROR]
Writing the backup data to the restoration
destination drive is not successfully completed.
■Collateral information
• Common Information:File name/Drive name
• Individual Information:–
■Diagnostic Timing
• At power ON/ At reset

2300

[ICM. OPE. ERROR]
• A memory card was removed without switching
the memory card in/out switch OFF.
• The memory card in/out switch is turned ON
although a memory card is not actually installed.
■Collateral information
• Common Information:Drive name
• Individual Information:–
■Diagnostic Timing
• When memory card is inserted or removed

*1
*11

RUN:
Off
ERR.:
Flicker

Corresponding
CPU

QnU

CPU Status:
Stop
• Execute a restore of other backup data because
the backup data may be destructed.
• Set the write protect switch of the SRAM card to
off (write enabled).

Execute a restore for the other CPU module too
because the CPU module may be damaged.

• Remove memory card after placing the memory
card in/out switch OFF.
• Turn on the card insert switch after inserting a
memory card.

CPU operation can be set in the parameters at error occurrence. (LED indication varies.)
The Universal model QCPU except the Q00UJCPU, Q00UCPU, and Q01UCPU.

12-28

LED Status
CPU Status

RUN:
Off/On
ERR.:
Flicker/On
CPU Status:
Stop/
Continue*1

Qn(H)
QnPH
QnPRH
QnU*11

Error
Code
(SD0)

Error Contents and Cause
[ICM. OPE. ERROR]
• The memory card has not been formatted.
• Memory card format status is incorrect.
• The QCPU file does not exist in the Flash card.
■Collateral information
• Common Information:Drive name
• Individual Information:–
■Diagnostic Timing
• When memory card is inserted or removed/When
memory card is inserted

2301

2302

*1
*3
*11

LED Status
CPU Status

Corresponding
CPU

1
Qn(H)
QnPH
QnPRH

• Format memory card.
• Reformat memory card.
• Write the QCPU file the Flash card

2

QnU*11

3
Format SRAM card after changing battery of SRAM
card.
Write a parameter, which set the file register at "Not
available", in CPU, and then perform the ioperation.

RUN:
Off/On
ERR.:
Flicker/On
CPU Status:
Stop/

12
QnU*11

6

Continue*1

6

[ICM. OPE. ERROR]
A memory card that cannot be used with the CPU
module has been installed.
■Collateral information
• Common Information:Drive name
• Individual Information:–
■Diagnostic Timing
• When memory card is inserted or removed

• Format memory card.
• Reformat memory card.
• Check memory card.

[FILE SET ERROR]
Automatic write to standard ROM was performed
on the CPU module that is incompatible with
automatic write to standard ROM.
(Memory card where automatic write to standard
ROM was selected in the boot file was fitted and
the parameter enable drive was set to the memory
card.)
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/ At writing to
progurammable controller

• Execute automatic write to standard ROM on the
CPU module which is compatible with automatic
write to standard ROM.
• Using GX Developer, perform write of
parameters and programs to standard ROM.
• Change the memory card for the one where
automatic write to standard ROM has not been
set, and perform boot operation from the memory
card.

[FILE SET ERROR]
The file designated at the PLC file settings in the
parameters cannot be found.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/ At writing to
progurammable controller

• Read the individual information of the error using
peripheral device, check to be sure that the
parameter drive name and file name correspond
to the numerical values there (parameter
number), and correct.
• Create a file created using parameters, and load
it to the CPU module.

Qn(H)
QnPH
QnPRH
QnU*11

7
8

RUN:
Off
ERR.:
Flicker

Qn(H)*3
QnPH
QnPRH

CPU Status:
Stop

QCPU

CPU operation can be set in the parameters at error occurrence. (LED indication varies.)
The function version is B or later.
The Universal model QCPU except the Q00UJCPU, Q00UCPU, and Q01UCPU.

12-29

12.1 Error Code List
12.1.4 Error code list (2000 to 2999)

2400

[ICM. OPE. ERROR]
SRAM card failure is detected. (It occurs when
automatic format is not set.)
Writing parameters was performed duruing setting
file registers.
■Collateral information
• Common Information:Drive name
• Individual Information:–
■Diagnostic Timing
• When memory card is inserted or removed/When
memory card is inserted

Corrective Action

Error
Code
(SD0)

Error Contents and Cause
[FILE SET ERROR]
Program memory capacity was exceeded by
performing boot operation or automatic write to
standard ROM.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/
At writing to progurammable controller
[FILE SET ERROR]
Program memory capacity was exceeded by
performing boot operation.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/
At writing to progurammable controller
[FILE SET ERROR]
The file specified by parameters cannot be made.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/ At writing to
progurammable controller

2401

[FILE SET ERROR]
• Although setting is made to use the device data
storage file, there is no empty capacity required
for creating the device data storage file in the
standard ROM.
• When the latch data backup function (to standard
ROM) is used, there is no empty capacity
required for storing backup data in standard
ROM. (The parameter number "FFFFH" is
displayed for the error individual information.)
• Standard RAM capacity is insufficient that error
history of the module cannot be stored.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/ At writing to
progurammable controller
[FILE OPE. ERROR]
• The specified program does not exist in the
program memory.
This error may occur when the ECALL, EFCALL,
PSTOP, PSCAN, POFF or PLOW instruction is
executed.
• The specified file does not exist.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Program error location
■Diagnostic Timing
• When instruction executed

2410

*1
*3

Corrective Action

Corresponding
CPU

Qn(H)*3
QnPH
QnPRH
• Check and correct the parameters (boot setting).
• Delete unnecessary files in the program memory.
• Choose "Clear program memory" for boot in the
parameter so that boot is started after the
program memory is cleared.

QnU

• Read the individual information of the error using
the peripheral device, check to be sure that the
parameter drive name and file name correspond
to the numerical values there (parameter
number), and correct.
• Check the space remaining in the memory card.

RUN:
Off
ERR.:
Flicker

• Read the individual information of the error using
the peripheral device, check to be sure that the
program corresponds to the numerical values
there (program location), and correct.
Create a file created using parameters, and load
it to the CPU module.
• In case a specified file does not exist, write the
file to a target memory and/or check the file
specified with the instruction again.

QCPU

CPU Status:
Stop

Secure the empty capacity of the standard ROM.

CPU operation can be set in the parameters at error occurrence. (LED indication varies.)
The function version is B or later.

12-30

LED Status
CPU Status

QnU

RUN:
Off/On
ERR.:
Flicker/On
CPU Status:
Stop/
Continue*1

Qn(H)
QnPH
QnPRH
QnU

Error
Code
(SD0)

2411

2412

2413

Read the individual information of the error using
the peripheral device, check to be sure that the
program corresponds to the numerical values there
(program location), and correct.

[FILE OPE. ERROR]
The SFC program file is one that cannot be
designated by the sequence program.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Program error location
■Diagnostic Timing
• When instruction executed

Read the individual information of the error using
the peripheral device, check to be sure that the
program corresponds to the numerical values there
(program location), and correct.

[FILE OPE. ERROR]
No data has been written to the file designated by
the sequence program.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Program error location
■Diagnostic Timing
• When instruction executed

Read the individual information of the error using
the peripheral device, check to be sure that the
program corresponds to the numerical values there
(program location), and correct.
Check to ensure that the designated file has not
been write protected.

[CAN'T EXE. PRG.]
• There is a program file that uses a device that is
out of the range set in the PLC parameter device
setting.
• After the PLC parameter setting is changed, only
the parameter is written into the PLC.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/ STOP

• At power ON/At reset/ STOP

LED Status
CPU Status

Corresponding
CPU

1

[FILE OPE. ERROR]
• The file is the one which cannot be specified by
the sequence program (such as comment file).
• The specified program exists in the program
memory, but has not been registered in the
program setting of the Parameter dialog box.
This error may occur when the ECALL, EFCALL,
PSTOP, PSCAN or POFF instruction is executed.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Program error location
■Diagnostic Timing
• When instruction executed

Qn(H)
QnPH
QnPRH
QnU

RUN:
Off/On
ERR.:
Flicker/On

• Read the common information of the error using
the peripheral device, check to be sure that the
parameter device allocation setting and the
program file device allocation correspond to the
numerical values there (file name), and correct if
necessary.
• If PLC parameter device setting is changed,
batch-write the parameter and program file into
the PLC.

CPU Status:
Stop/
Continue*1

Qn(H)
QnPH
QnPRH
QnU

3

6
6

Qn(H)
QnPH
QnPRH

7
8

QCPU
RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

When the index modification of the PLC parameter
is changed, batch-write the parameter and program
file into the PLC.

2

12

RUN

[CAN'T EXE. PRG.]
After the index modification of the PLC parameter is
changed, only the parameter is written to the PLC.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:–
■Diagnostic Timing

*1

Corrective Action

QnU

RUN

CPU operation can be set in the parameters at error occurrence. (LED indication varies.)

12-31

12.1 Error Code List
12.1.4 Error code list (2000 to 2999)

2500

Error Contents and Cause

Error
Code
(SD0)

Error Contents and Cause
[CAN'T EXE. PRG.]
There are multiple program files although "none"
has been set at the PLC parameter program
settings.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/ STOP

2501

• At power ON/At reset/ STOP

• At power ON/At reset/ STOP

• At power ON/At reset/ STOP

2504

RUN

Check whether the program version

The function version is B or later.

12-32

QCPU

is
.QPG, and check the file contents to be
sure they are for a sequence program.
RUN:
Off
ERR.:
Flicker
Create a program using GX Developer or PX
Developer for which the PLC type has been set to
the redundant CPU (Q12PRH/Q25PRH), and write
it to the CPU module.

CPU Status:
Stop

QnPRH

QCPU

• Check program configuration.
• Check parameters and program configuration.
Qn(H)
QnPH
QnPRH
QnU

RUN

[CAN'T EXE. PRG.]
There are two or more SFC programs.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/ STOP

Q00J/Q00/Q01

RUN

[CAN'T EXE. PRG.]
Two or more SFC normal programs or control
programs have been designated.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:–
■Diagnostic Timing

*3

• Delete unnecessary program files.
• Match the program name with the program
contents.

[CAN'T EXE. PRG.]
There are no program files at all.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:–
■Diagnostic Timing

2503

Qn(H)
QnPH
QnPRH
QnU

Edit the PLC parameter program setting to "yes".
Alternatively, delete unneeded programs.

RUN

[CAN'T EXE. PRG.]
The program file is not the one for the redundant
CPU.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/ STOP

Corresponding
CPU

RUN

[CAN'T EXE. PRG.]
The program file is incorrect.
Alternatively, the file contents are not those of a
sequence program.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:–
■Diagnostic Timing
2502

LED Status
CPU Status

RUN

[CAN'T EXE. PRG.]
• There are three or more program files.
• The program name differs from the program
contents.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/ STOP

Corrective Action

RUN

Reduce the SFC programs to one.

Q00J/Q00/Q01*3

Error
Code
(SD0)

2700

2710

Error Contents and Cause

Corrective Action

[REMOTE PASS.FAIL]
The count of remote password mismatches
reached the upper limit.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

Check for illegal accesses. If any illegal access is
identified, take actions such as disabling
communication of the connection.
If no illegal access is identified, clear the error and
perform the following. (Clearing the error also
clears the count of remote password mismatches.)
• Check if the remote password sent is correct.
• Check if the remote password has been locked.
• Check if concurrent access was made from
multiple devices to one connection by UDP.
• Check if the upper limit of the remote password
mismatch count is too low.

[SNTP OPE.ERROR]
Time setting failed when the programmable
controller was powered ON or reset.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• When time setting function is executed

• Check if the time setting function is set up
correctly.
• Check if the specified SNTP server is operating
normally, or if any failure has occurred on the
network connected to the specified SNTP server
computer.

LED Status
CPU Status

Corresponding
CPU

1
RUN:
ON
ERR.:
ON

2

CPU Status:
Continue
QnU*8

3
12

RUN:
Off/ON
ERR.:
Flicker/ON

6

CPU Status:
Stop/Continue

6
7
8

12.1 Error Code List
12.1.4 Error code list (2000 to 2999)

*8

This applies to the Built-in Ethernet port QCPU.

12-33

12.1.5

Error code list (3000 to 3999)

The following shows the error messages from the error code 3000 to 3999, the contents and
causes of the errors, and the corrective actions for the errors.
Error
Code
(SD0)

Error Contents and Cause

Corrective Action

[PARAMETER ERROR]
In a multiple CPU system, the intelligent function
module under control of another CPU is specified in
the interrupt pointer setting of the PLC parameter.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP
RUN/
At writing to progurammable controller

• Specify the head I/O number of the intelligent
function module under control of the host CPU.
• Delete the interrupt pointer setting of the
parameter.

LED Status
CPU Status

Qn(H)*1
QnPH
QnU*10

[PARAMETER ERROR]
The PLC parameter settings for timer time limit
setting, the RUN-PAUSE contact, the common
pointer number, general data processing, number
of empty slots, system interrupt settings, baud rate
setting, and service processing setting are outside
the range that can be used by the CPU module.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

Corresponding
CPU

QCPU

RUN/

At writing to progurammable controller
[PARAMETER ERROR]
In a program memory check, the check capacity
has not been set within the range applicable for the
CPU module.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing

3000

• At power ON/At reset/STOP

RUN/

At writing to progurammable controller
[PARAMETER ERROR]
The parameter settings in the error individual
information (special register SD16) are illegal.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

• Read the individual information of the error using
the peripheral device, check the parameter item
corresponding to the numerical value (parameter
No.), and correct it.
• Rewrite corrected parameters to the CPU
module, reload the CPU power supply and/or
reset the module.
• If the same error occurs, it is thought to be a
hardware error. (Contact your local Mitsubishi
representative.)

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

QnPH
QnPRH*5

QCPU

RUN/

At writing to progurammable controller
[PARAMETER ERROR]
The ATA card is set to the memory card slot when
the specified drive for the file register is set to
“memory card (ROM)” and [Use the following file]
or [Use the same file name as the program] (either
one is allowed) is set in the PLC file setting.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

RUN/

At writing to progurammable controller

*1
*5
*10
*11

The function version is B or later.
The module whose first 5 digits of serial No. is "07032" or later.
The Universal model QCPU except the Q00UJCPU.
The Universal model QCPU except the Q00UJCPU, Q00UCPU, and Q01UCPU.

12-34

QnU*11

Error
Code
(SD0)

3001

Error Contents and Cause

[PARAMETER ERROR]
The parameter settings are corrupted.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

RUN/

At writing to progurammable controller

Corrective Action

• At power ON/At reset/STOP

RUN/

2
3
12

At writing to progurammable controller

3002

QCPU

Qn(H)
QnPH
QnPRH

RUN/

[PARAMETER ERROR]
When [Use the following file] is set for the file
register in the PLC file setting of the PLC parameter
dialog box and the capacity of file register is not set,
the file register file does not exist in the specified
target memory.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing

Corresponding
CPU

1

• Read the individual information of the error using
the peripheral device, check the parameter item
corresponding to the numerical value (parameter
No.), and correct it.
• Rewrite corrected parameters to the CPU
module, reload the CPU power supply and/or
reset the module.
• If the same error occurs, it is thought to be a
hardware error. (Contact your local Mitsubishi
representative.)

[PARAMETER ERROR]
When "Use the following file" is selected for the file
register in the PLC file setting of the PLC parameter
dialog box, the specified file does not exist although
the file register capacity has been set.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

LED Status
CPU Status

• Read the individual information of the error using
the peripheral device, check the parameter item
corresponding to the numerical value (parameter
No.), and correct it.
• Rewrite corrected parameters to the CPU
module, reload the CPU power supply and/or
reset the module.
• If the same error occurs, it is thought to be a
hardware error. (Contact your local Mitsubishi
representative.)

RUN:
Off
ERR.:
Flicker

6
6

CPU Status:
Stop

7
QnU*10

8

At writing to progurammable controller

• At power ON/At reset/STOP

QnU

RUN/

At writing to progurammable controller

*10

The Universal model QCPU except the Q00UJCPU.

12-35

12.1 Error Code List
12.1.5 Error code list (3000 to 3999)

[PARAMETER ERROR]
When [Use the following file.] is set for the device
data storage file in [PLC file] of [PLC parameter],
and [Capacity] is not set, the device data storage
file does not exist in the target memory.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing

Error
Code
(SD0)

Error Contents and Cause
[PARAMETER ERROR]
The automatic refresh range of the multiple CPU
system exceeded the file register capacity.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• When an END instruction executed
[PARAMETER ERROR]
The number of devices set at the PLC parameter
device settings exceeds the possible CPU module
range.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing

3003

• At power-On/ At reset/ STOP

RUN/

At writing to progurammable controller
[PARAMETER ERROR]
The parameter file is incorrect.
Alternatively, the contents of the file are not
parameters.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing

3004

• At power-On/ At reset/ STOP

Corrective Action

3005

• At power-ON/ At reset/ STOP

[PARAMETER ERROR]
• The high speed interrupt is set in a Q02CPU.
• The high speed interrupt is set in a multiple CPU
system.
• The high speed interrupt is set when aQA1S6 B
or QA6 B is used.
• No module is installed at the I/O address
designated by the high speed interrupt.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing

3006

• At power-On/ At reset/ STOP

RUN/

At writing to progurammable controller

*1
*4
*7
*9
*10

QCPU

Check whether the parameter file version
is
.QPA, and check the file contents to be
sure they are parameters.

• Read the individual information of the error using
the peripheral device, check the parameter item
corresponding to the numerical value (parameter
No.), and correct it.
• Write the modified parameter items to the CPU
module again, and power-on the Programmable
Controller or reset the CPU module.
• When the same error occurs again, the hardware
is faulty. Contact your local Mitsubishi
representative, explaining a detailed description
of the problem.
• Delete the setting of the Q02CPU' s high speed
interrupt. To use high speed interrupts, change
the CPU module to one of the Q02H/Q06H/
Q12H/Q25HCPU.
• To use a multiple CPU system, delete the setting
of the high-speed interrupt. To use high speed
interrupts, change the system to a single CPU
system.
• To use either the QA1S6 B or QA6 B, delete
the setting of the high speed interrupt. To use
high speed interrupts, do not use the QA1S6 B/
QA6 B.
• Re-examine the I/O address designated by the
high speed interrupt setting.

The function version is B or later.
The module whose first 5 digits of serial No. is "04012" or later.
The module whose first 5 digits of serial No. is "09012" or later.
The module whose first 5 digits of serial No. is "10042" or later.
The Universal model QCPU except the Q00UJCPU.

12-36

QnU*10

• Read the individual information of the error using
the peripheral device, check the parameter item
corresponding to the numerical value (parameter
No.), and correct it.
• If the error is still generated following the
correction of the parameter settings, the possible
cause is the memory errorm of the CPU module's
program memory or the memory card. (Contact
your local Mitsubishi representative.)

RUN/

RUN

Corresponding
CPU

Qn(H)*1
QnPH

Change the file register file for the one refreshenabled in the whole range.

At writing to progurammable controller

[PARAMETER ERROR]
The contents of the parameter are broken.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing

LED Status
CPU Status

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop
Qn(H)*7
QnPH*9
QnPRH*9

Qn(H)*4

Error
Code
(SD0)

3007

Error Contents and Cause
[PARAMETER ERROR]
The parameter file in the drive specified as valid
parameter drive by the DIP switches is inapplicable
for the CPU module.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power-On/ At reset/ STOP

Corrective Action

LED Status
CPU Status

Corresponding
CPU

1
Create parameters using GX Developer, and write
them to the drive specified as valid parameter drive
by the DIP switches.

QnPRH

3

RUN/

At writing to progurammable controller

3009

[PARAMETER ERROR]
In a multiple CPU system, the modules for AnS, A,
Q2AS and QnA have been set to multiple control
CPUs.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power-On/ At reset/ STOP

Re-set the parameter I/O assignment to control
them under one CPU module. (Change the
parameters of all CPUs in the multiple CPU
system.)

RUN/

At writing to progurammable controller

3010

[PARAMETER ERROR]
The parameter-set number of CPU modules differs
from the actual number in a multiple CPU system.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power-On/ At reset/ STOP

2

Match the number of (CPU modules in multiple
CPU setting) - (CPUs set as empty in I/O
assignment) with that of actually mounted CPU
modules.

12
Qn(H)*1
RUN:
Off
ERR.:
Flicker

6
6

CPU Status:
Stop
Qn(H)*1
QnPH

7

RUN/

At writing to progurammable controller

3012

[PARAMETER ERROR]
Multiple CPU setting or control CPU setting differs
from that of the reference CPU settings in a
multiple CPU system.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing

Match the multiple CPU setting or control CPU
setting in the PLC parameter with that of the
reference CPU (CPU No.1) settings.

Q00/Q01*1
Qn(H)*1
QnU

RUN/

12.1 Error Code List
12.1.5 Error code list (3000 to 3999)

• At power-On/ At reset/ STOP

8

At writing to progurammable controller

*1

The function version is B or later.

12-37

Error
Code
(SD0)

Error Contents and Cause
[PARAMETER ERROR]
Multiple CPU auto refresh setting is any of the
followings in a multiple CPU system.
• When a bit device is specified as a refresh
device, a number other than a multiple of 16 is
specified for the refresh-starting device.
• The device specified is other than the one that
may be specified.
• The number of send points is an odd number.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power-On/ At reset/ STOP

Corrective Action

LED Status
CPU Status

Corresponding
CPU

Check the following in the multiple CPU auto
refresh setting and make correction.
• When specifying the bit device, specify a multiple
of 16 for the refresh starting device.
• Specify the device that may be specified for the
refresh device.
• Set the number of send points to an even
number.

Qn(H)*1
QnPH

Check the following in the multiple CPU auto
refresh setting and make correction.
• The total number of transmission points is within
the maximum number of refresh points.

Q00/Q01*1

RUN/

At writing to progurammable controller
[PARAMETER ERROR]
In a multiple CPU system, the multiple CPU auto
refresh setting is any of the following.
• The total number of transmission points is
greater than the maximum number of refresh
points.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing

3013

• At power-On/ At reset/ STOP

RUN/

At writing to progurammable controller
[PARAMETER ERROR]
In a multiple CPU system, the multiple CPU auto
refresh setting is any of the following.
• The device specified is other than the one that
may be specified.
• The number of send points is an odd number.
• The total number of send points is greater than
the maximum number of refresh points.
• The setting of the refresh range crosses over the
boundary between the internal user device and
the extended data register (D) or extended link
register (W).
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power-On/ At reset/ STOP

RUN:
Off
ERR.:
Flicker
Check the following in the multiple CPU auto
refresh setting and make correction.
• Specify the device that may be specified for the
refresh device.
• Set the number of send points to an even
number.
• Set the total number of send points within the
range of the maximum number of refresh points.
• Set the refresh range so that it does not cross
over the boundary between the internal user
device and the extended data register (D) or
extended link register (W).

CPU Status:
Stop

QnU*10

RUN/

At writing to progurammable controller
[PARAMETER ERROR]
• In a multiple CPU system, the online module
change parameter (multiple CPU system
parameter) settings differ from those of the
reference CPU.
• In a multiple CPU system, the online module
change setting is enabled although the CPU
module mounted does not support online module
chang parameter.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power-On/ At reset/ STOP
RUN/
At writing to progurammable controller

3014

*1
*8
*10

• Match the online module change parameter with
that of the reference CPU.
• If the CPU module that does not support online
module change is mounted, replace it with the
CPU module that supports online module
change.

The function version is B or later.
The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
The Universal model QCPU except the Q00UJCPU.

12-38

Qn(H)
QnPH
QnU*8

Error
Code
(SD0)

3015

Error Contents and Cause
[PARAMETER ERROR]
In a multiple CPU system configuration, the CPU
verified is different from the one set in the
parameter setting.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number/CPU No.
■Diagnostic Timing
• At power-On/ At reset/ STOP

Corrective Action

LED Status
CPU Status

Corresponding
CPU

1
Read the individual information of the error using
the peripheral device, check the parameter item
corresponding to the numerical value (parameter
No./CPU No.) and parameter of target CPU, and
correct them.

2
3

RUN/

At writing to progurammable controller
[PARAMETER ERROR]
The CPU module incompatible with multiple CPU
synchronized boot-up is set as the target for the
synchronized boot-up in the [Multiple CPU
synchronous startup setting].
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number/ CPU
No.
■Diagnostic Timing
• At power ON/ At reset/
At writing to progurammable controller

Delete the CPU module incompatible with multiple
CPU synchronized boot-up from the setting.

3040

[PARAMETER ERROR]
The parameter file is damaged.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

With GX Developer, write [PLC parameter/Network
parameter/Remote password] to a valid drive then
reload the power supply for system and/or reset the
CPU module. If the same error occurs, it is thought
to be hardware error. (Contact your local Mitsubishi
representative.)

3041

[PARAMETER ERROR]
Parameter file of intelligent function module is
damaged.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

With GX Developer, write [Intelligent function
module parameter] to a valid drive to write the
parameters then reload the power supply for
system and/or reset the CPU module. If the same
error occurs, it is thought to be a hardware error.
(Contact your local Mitsubishi representative.)

3016

*5
*8

12
6
6
RUN:
Off
ERR.:
Flicker

7

CPU Status:
Stop

8

Qn(H)*5
• With GX Developer, write [PLC parameter/
Network parameter/Remote password] to a valid
drive then reload the power supply for system
and/or reset the CPU module. If the same error
occurs, it is thought to be a hardware error.
(Contact your local Mitsubishi representative.)
• When a valid drive for parameter is set to other
than [program memory], set the parameter file
(PARAM) at the boot file setting to be able to
transmit to the program memory.
With GX Developer, write [PLC parameter/
Network parameter/Remote password] to a valid
drive then reload the power supply for system
and/or reset the CPU module. If the same error
occurs, it is thought to be hardware error.
(Contact your local Mitsubishi representative.)

QnPH*5
QnPRH*5

The module whose first 5 digits of serial No. is "07032" or later.
The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.

12-39

12.1 Error Code List
12.1.5 Error code list (3000 to 3999)

3042

[PARAMETER ERROR]
The system file that have stored the remote
password setting information is damaged.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

QnU*8

Error
Code
(SD0)

Error Contents and Cause
[LINK PARA. ERROR]
In a multiple CPU system, the CC-Link IE controller
network module controlled by another CPU is
specified as the head I/O number of the CC-Link IE
controller network module.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power-ON/ At reset/ STOP

• At power-ON/ At reset/ STOP

RUN

[LINK PARA. ERROR]
• The CC-Link IE controller network module is
specified for the head I/O number of network
parameter in the MELSECNET/H.
• The MELSECNET/H module is specified for the
head I/O number of network parameter in the
CC-Link IE controller network.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power-ON/ At reset/ STOP

*7
*9

• Delete the network parameter of the CC-Link IE
controller network module controlled by another
CPU.
• Change the setting to the head I/O number of the
CC-Link IE controller network module controlled
by host CPU.

Qn(H)*7
QnPH*9
QnU

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

Qn(H)*7
QnPH*9

• Check the network parameter and actual
mounting status, and if they differ, make them
matched. When network parameters are
modified, write them to the CPU module.
• Check the setting of extension base unit stage
number.
• Check the connection status of extension base
unit and extension cable. When the GOT is busconnected to the main base unit or extension
base unit, also check its connection status.
If an error occurs even after performing the
above checks, the hardware may be faulty.
(Contact your local Mitsubishi representative,
explaining a detailed description of the problem.)

RUN

The module whose first 5 digits of serial No. is "09012" or later.
The module whose first 5 digits of serial No. is "10042" or later.

12-40

Corresponding
CPU

Reset the CPU module.

RUN

[LINK PARA. ERROR]
• The number of modules actually mounted is
different from that is set in Network parameter for
MELSECNET/H.
• The head I/O number of the actually mounted
module is different from the one set in the
network parameter of the CC-Link IE controller
network.
• Data cannot be handled in the parameter exists.
• The network type of CC-Link IE controller
network is overwritten during power-on. (When
changing the network type, switch RESET to
RUN.)
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing

3100

LED Status
CPU Status

RUN

[LINK PARA. ERROR]
The network parameter of the CC-Link IE controller
network operating as the normal station is
overwritten to the control station.
Or, the network parameter of the CC-Link IE
controller network operating as the control station is
overwritten to the normal station.
(The network parameter is updated on the module
by resetting.)
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power-ON/ At reset/ STOP

Corrective Action

QnPRH*9
QnU

Error
Code
(SD0)

Error Contents and Cause

[LINK PARA. ERROR]
• Although the CC-Link IE controller network
module is mounted, network parameter for the
CC-Link IE controller network module is not set.
• Although the CC-Link IE controller network and
MELSECNET/H modules are mounted, network
parameter for the MELSECNET/H module is not
set.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power-ON/ At reset/ STOP

RUN

[LINK PARA. ERROR]
In a multiple CPU system, the MELSECNET/H
under control of another CPU is specified as the
head I/O number in the network setting parameter
of the MELSECNET/H.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

3100

1

• Check the network parameter and actual
mounting status, and if they differ, make them
matched. When network parameters are
modified, write them to the CPU module.
• Check the setting of extension base unit stage
number.
• Check the connection status of extension base
unit and extension cable. When the GOT is busconnected to the main base unit or extension
base unit, also check its connection status.
If an error occurs even after performing the
above checks, the hardware may be faulty.
(Contact your local Mitsubishi representative,
explaining a detailed description of the problem.)

Qn(H)*7

2

9

QnPH*

QnPRH*9
QnU

3
12

• Delete the MELSECNET/H network parameter of
the MELSECNET/H under control of another
CPU.
• Change the setting to the head I/O number of the
MELSECNET/H under control of the host CPU.

Q00/Q01*1
Qn(H)*1
QnPH
QnU*10

6
6

RUN:
Off
ERR.:
Flicker

Reset the CPU module.

CPU Status:
Stop

7
Qn(H)*1
QnPH
QnPRH
QnU

8

RUN

• Check the network parameters and actual
mounting status, and if they differ, make them
matched.
If any network parameter has been corrected,
write it to the CPU module.
• Check the extension base unit stage No. setting.
• Check the connection status of the extension
base units and extension cables.
When the GOT is bus-connected to the main
base unit and extension base units, also check
the connection status.
If the error occurs after the above checks, the
possible cause is a hardware fault. (Contact your
local Mitsubishi representative, explaining a
detailed description of the problem.)

QCPU

• Set the mode switch of MELSECNET/H module*5
within the range.

The function version is B or later.
The module whose first 5 digits of serial No. is "07032" or later.
The module whose first 5 digits of serial No. is "09012" or later.
The module whose first 5 digits of serial No. is "10042" or later.
The Universal model QCPU except the Q00UJCPU.

12-41

12.1 Error Code List
12.1.5 Error code list (3000 to 3999)

• The mode switch of MELSECNET/H module*5 is
outside the range.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing

*1
*5
*7
*9
*10

Corresponding
CPU

RUN

[LINK PARA. ERROR]
• The number of modules actually mounted is
different from that is set in Network parameter for
MELSECNET/H.
• The head I/O number of actually installed
modules is different from that designated in the
network parameter of MELSECNET/H.
• Some data in the parameters cannot be handled.
• The network type of MELSECNET/H is
overwritten during power-on. (When changing
the network type, switch RESET to RUN.)

• At power ON/At reset/STOP

LED Status
CPU Status

RUN

[LINK PARA. ERROR]
The network parameter of the MELSECNET/H
operating as the normal station is overwritten to the
control station.
Or, the network parameter of the MELSECNET/H
operating as the control station is overwritten to the
normal station. (The network parameter is updated
on the module by resetting.)
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

Corrective Action

Error
Code
(SD0)

Error Contents and Cause
[LINK PARA. ERROR]
The link refresh range exceeded the file register
capacity.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• When an END instruction executed
[LINK PARA. ERROR]
• When the station number of the MELSECNET/H
module is 0, the PLC-to-PLC network parameter
has been set.
• When the station number of the MELSECNET/H
module is other than 0, the remote master
parameter setting has been made.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

• At power ON/At reset/STOP

RUN

[LINK PARA. ERROR]
• The network No. specified by a network
parameter is different from that of the actually
mounted network.
• The head I/O No. specified by a network
parameter is different from that of the actually
mounted I/O unit.
• The network class specified by a network
parameter is different from that of the actually
mounted network.
• The network refresh parameter of the
MELSECNET/H, MELSECNET/10 is out of the
specified area.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

*1
*7
*9
*10

Qn(H)*1
QnPH
QnPRH

Change the file register file for the one that enables
entire range refresh.

QnU*10

Qn(H)*1
QnPH
QnPRH

Correct the type or station number of the
MELSECNET/H module in the network parameter
to meet the used system.

Qn(H)*7
QnPH*9
• Check the network parameters and mounting
status, and if they differ, match the network
parameters and mounting status.
If any network parameter has been corrected,
write it to the CPU module.
• Confirm the setting of the number of extension
stages of the extension base units.
• Check the connection status of the extension
base units and extension cables.
When the GOT is bus-connected to the main
base unit and extension base units, also check
their connection status.
If the error occurs after the above checks, the
cause is a hardware fault. (Contact your local
Mitsubishi representative, explaining a detailed
description of the problem.)

Use a module that supports the MELSECNET/H
multi-remote I/O network.

RUN

The function version is B or later.
The module whose first 5 digits of serial No. is "09012" or later.
The module whose first 5 digits of serial No. is "10042" or later.
The Universal model QCPU except the Q00UJCPU.

12-42

Corresponding
CPU

RUN:
Off
ERR.:
Flicker

QnPRH*9
QnU

CPU Status:
Stop

QCPU

RUN

[LINK PARA. ERROR]
A multi-remote I/O network was configured using a
module that does not support the MELSECNET/H
multi-remote I/O network.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

LED Status
CPU Status

RUN

[LINK PARA. ERROR]
The refresh parameter for the CC-Link IE controller
network is outside the range.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
3101

Corrective Action

QnPH

Error
Code
(SD0)

Error Contents and Cause
[LINK PARA. ERROR]
• The system A of the MELSECNET/H remote
master station has been set to other than Station
No. 0.
• The system B of the MELSECNET/H remote
master station has been set to Station No. 0.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

Corrective Action

LED Status
CPU Status

Corresponding
CPU

1
• Set the system A of the MELSECNET/H remote
master station to Station No. 0.
• Set the system B of the MELSECNET/H remote
master station to any of Station No. 1 to 64.

QnPRH

3

RUN

[LINK PARA. ERROR]
Since the number of points of the B/W device set in
[Device] of the PLC parameter is lower than the
number of B/W refresh device points shown in the
following table when parameters of the
MELSECNET/H are not set, the refresh between
the CPU module and the MELSECNET/H cannot

12
6

be performed..
Refresh
device

3101

1
No. of
2
mountable
network
modules 3

4

No. of refresh device
points of B device
8192 points
(8192 points×1
module)
8192 points
(4096 points×2
modules)
6144 points
(2048 points×3
modules)
8192 points
(2048 points×4
modules)

No. of refresh device
points of W device
8192 points
(8192 points×1
module)
8192 points
(4096 points×2
modules)
6144 points
(2048 points×3
modules)
8192 points
(2048 points×4
modules)

Set the refresh parameter of the MELSECNET/H in
accordance with the number of points of B/W
devices set in [Device] of the PLC parameter.

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

Qn(H)*7
QnPH*7
QnPRH*7
QnU

Set the network refresh range so that it does not
cross over the boundary between the internal user
device and the extended data register (D) or
extended link register (W).

QnU

RUN

The module whose first 5 digits of serial No. is "09012" or later.

12-43

12.1 Error Code List
12.1.5 Error code list (3000 to 3999)

*7

7

RUN

[LINK PARA. ERROR]
The setting of the network refresh range crosses
over the boundary between the internal user device
and the extended data register (D) or extended link
register (W).
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

6

8

■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

2

Error
Code
(SD0)

Error Contents and Cause

Corrective Action

LED Status
CPU Status

[LINK PARA. ERROR]
A CC-Link IE controller network parameter error
was detected.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

RUN

[LINK PARA. ERROR]
• The network module detected a network
parameter error.
• A MELSECNET/H network parameter error was
detected.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

• At power ON/At reset/STOP

*7
*9

• Correct and write the network parameters.
• If the error occurs after correction, it suggests a
hardware fault. (Contact your local Mitsubishi
representative.)

QCPU

Refer to the troubleshooting of the network module,
and if the error is due to incorrect pairing setting,
reexamine the pairing setting of the network
parameter.

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

Mount the CC-Link IE controller network module
whose first 5 digits of serial No. is "09042" or later.

Set group cyclic function in function version D or
later of CC-Link IE controller network.

QnU

QnU*9

Q00J/Q00/Q01
Examine the paring setting for the network
parameter in the control staion.

RUN

The module whose first 5 digits of serial No. is "09012" or later.
The module whose first 5 digits of serial No. is "10042" or later.

12-44

QnPRH

RUN

[LINK PARA. ERROR]
Paring setting in CC-Link IE controller network
modules installed in CPUs except for redundant
CPUs was performed.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

QnPRH*9
QnU

RUN

[LINK PARA. ERROR]
Group cyclic function in CC-Link IE controller
network that does not correspond to group cyclic
function is set.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

QnPH*9

RUN

[LINK PARA. ERROR]
The CC-Link IE controller network module whose
first 5 digits of serial No. is "09041" or earlier is
mounted.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

Qn(H)*7

RUN

[LINK PARA. ERROR]
The station No. specified in pairing setting are not
correct.
• The stations are not numbered consecutively.
• Pairing setting has not been made for the CPU
module at the normal station.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing

3102

Corresponding
CPU

Qn(H)*9
QnPH*9
QnU*9

Error
Code
(SD0)

3102

Error Contents and Cause
[LINK PARA. ERROR]
• LB/LW own station send range at LB/LW4000 or
later was set.
• LB/LW setting (2) was performed.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

3103

RUN

3104

*1
*7
*10

Examine the network range assignments for the
network parameter in the control station.

Q00J/Q00/Q01

2
3

• Delete the Ethernet network parameter of
Ethernet interface module under control of
another station.
• Change the setting to the start I/O number of
Ethernet interface module under control of the
host station.

Q00/Q01*1
Qn(H)*1
QnPH

12

QnU*10

6
6
QCPU

• Correct and write the network parameters.
• If the error occurs after correction, it suggests a
hardware fault. (Contact your local Mitsubishi
representative.)

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

QnPRH*7

• Correct and write the network parameters.
• If the error occurs after correction, it suggests a
hardware fault. (Contact your local Mitsubishi
representative.)

7
8

RUN

[LINK PARA. ERROR]
• The Ethernet, MELSECNET/H and
MELSECNET/10 use the same network number.
• The network number, station number or group
number set in the network parameter is out of
range.
• The specified I/O number is outside the range of
the used CPU module.
• The Ethernet-specific parameter setting is not
normal.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

1

QCPU

RUN

The function version is B or later.
The module whose first 5 digits of serial No. is "09012" or later.
The Universal model QCPU except the Q00UJCPU.

12-45

12.1 Error Code List
12.1.5 Error code list (3000 to 3999)

[LINK PARA. ERROR]
• Ethernet module whose network type is set to
“Ethernet (main base)” is mounted on the
extension base unit in the redundant system.
• Ethernet module whose network type is set to
“Ethernet (extension base)” is mounted on the
main base unit in the redundant system.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

Corresponding
CPU

RUN

[LINK PARA. ERROR]
• Although the number of modules has been set to
one or greater number in the Ethernet module
count parameter setting, the number of actually
mounted module is zero.
• The start I/O No. of the Ethernet network
parameter differs from the I/O No. of the actually
mounted module.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

LED Status
CPU Status

RUN

[LINK PARA. ERROR]
In a multiple CPU system, Ethernet interface
module under control of another station is specified
to the start I/O number of the Ethernet network
parameter.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

Corrective Action

Error
Code
(SD0)

Error Contents and Cause
[LINK PARA. ERROR]
In a multiple CPU system, the CC-Link module
under control of another station is specified as the
head I/O number of the CC-Link network
parameter.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

• At power ON/At reset/STOP

RUN

[LINK PARA. ERROR]
• CC-Link module whose station type is set to
“master station (compatible with redundant
function)” is mounted on the extension base unit
in the redundant system.
• CC-Link module whose station type is set to
“master station (extension base)” is mounted on
the main base unit in the redundant system.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

*1
*7
*10

Corresponding
CPU

Q00/Q01*1

• Delete the CC-Link network parameter of the
CC-Link module under control of another station.
• Change the setting to the start I/O number of the
CC-Link module under control of the host station.

Qn(H)*1
QnPH
QnU*10

RUN:
Off
ERR.:
Flicker

• Correct and write the network parameters.
• If the error occurs after correction, it suggests a
hardware fault. (Contact your local Mitsubishi
representative.)

RUN

The function version is B or later.
The module whose first 5 digits of serial No. is "09012" or later.
The Universal model QCPU except the Q00UJCPU.

12-46

LED Status
CPU Status

RUN

[LINK PARA. ERROR]
• Though the number of CC-Link modules set in
the network parameters is one or more, the
number of actually mounted modules is zero.
• The start I/O number in the common parameters
is different from that of the actually mounted
module.
• The station type of the CC-Link module count
setting parameters is different from that of the
actually mounted station.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing

3105

Corrective Action

QCPU

CPU Status:
Stop

QnPRH*7

Error
Code
(SD0)

Error Contents and Cause
[LINK PARA. ERROR]
The CC-Link link refresh range exceeded the file
register capacity.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• When an END instruction executed

3106

[LINK PARA. ERROR]
The network refresh parameter for CC-Link is out of
range.
■Collateral information
• Common Information:File name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

3107

3201

*1

RUN

[SFC PARA. ERROR]
The block parameter setting is illegal.
■Collateral information
• Common Information:File name
• Individual Information:Parameter number
■Diagnostic Timing
• STOP

2
3

Check the parameter setting.

QCPU

12
6
Set the network refresh range so that it does not
cross over the boundary between the internal user
device and the extended data register (D) or
extended link register (W).

QnU
RUN:
Off
ERR.:
Flicker

7

CPU Status:
Stop
Check the parameter setting.

6

QCPU

8

RUN

[SFC PARA. ERROR]
The parameter setting is illegal.
• Though Block 0 was set to "Automatic start" in
the SFC setting of the PLC parameter dialog box,
Block 0 does not exist.
■Collateral information
• Common Information:File name
• Individual Information:Parameter number
■Diagnostic Timing
• STOP

Qn(H)*1
QnPH
QnPRH
QnU

Change the file register file for the one refreshenabled in the whole range.

Read the common information of the error using
the peripheral device, check error step
corresponding to its numerical value (program error
location), and correct the problem.

Q00J/Q00/Q01*1
QnPH
QnPRH
QnU

Qn(H)
QnPH
QnPRH

RUN

The function version is B or later.

12-47

12.1 Error Code List
12.1.5 Error code list (3000 to 3999)

3200

Corresponding
CPU

1

RUN

[LINK PARA. ERROR]
• The CC-Link parameter setting is incorrect.
• The set mode is not allowed for the version of the
mounted CC-Link module.
■Collateral information
• Common Information:File name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

LED Status
CPU Status

RUN

[LINK PARA. ERROR]
The setting of the network refresh range crosses
over the boundary between the internal user device
and the extended data register (D) or extended link
register (W).
■Collateral information
• Common Information:File name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset/STOP

Corrective Action

Error
Code
(SD0)

Error Contents and Cause
[SFC PARA. ERROR]
The number of step relays specified in the device
setting of the PLC parameter dialog box is less than
that used in the program.
■Collateral information
• Common Information:File name
• Individual Information:Parameter number
■Diagnostic Timing

3202

• STOP

RUN

[SFC PARA. ERROR]
The execution type of the SFC program specified in
the program setting of the PLC parameter dialog
box is other than scan execution.
■Collateral information
• Common Information:File name
• Individual Information:Parameter number
■Diagnostic Timing

3203

• At power-ON/ At reset/ STOP

LED Status
CPU Status

Corresponding
CPU

Qn(H)
QnPH
QnPRH
Read the common information of the error using
the peripheral device, check error step
corresponding to its numerical value (program error
location), and correct the problem.
Qn(H)
QnPH
QnPRH
QnU

RUN*3

[SP. PARA ERROR]
The start I/O number in the intelligent function
module parameter set on GX Configurator differs
from the actual I/O number.
■Collateral information
• Common Information:File name

3300

Corrective Action

Check the parameter setting.

QCPU

• Individual Information:Parameter number*2
■Diagnostic Timing
• At power-On/ At reset/ STOP

RUN/
RUN:
Off
ERR.:
Flicker

At writing to progurammable controller
[SP. PARA ERROR]
• The refresh setting of the intelligent function
module exceeded the file register capacity.
• The intelligent function module set in GX
Configurator differs from the actually mounted
module.
■Collateral information
• Common Information:File name

• Change the file register file for the one which
allows refresh in the whole range.
• Check the parameter setting.

• Individual Information:Parameter number*2
■Diagnostic Timing
• At power-On/ At reset/ STOP

CPU Status:
Stop

Q00J/Q00/Q01
Qn(H)*1
QnPH
QnPRH
QnU

RUN/

At writing to progurammable controller
[SP. PARA ERROR]
The intelligent function module's refresh parameter
setting is outside the available range.
■Collateral information
• Common Information:File name

3301

• Individual Information:Parameter number*2
■Diagnostic Timing
• At power-On/ At reset/ STOP

Check the parameter setting.

QCPU

RUN/

At writing to progurammable controller
[SP. PARA ERROR]
The setting of the refresh parameter range crosses
over the boundary between the internal user device
and the extended data register (D) or extended link
register (W).
■Collateral information
• Common Information:File name
• Individual Information:Parameter number*2
■Diagnostic Timing
• At power-On/ At reset/ STOP

Set the refresh parameter range so that it does not
cross over the boundary between the internal user
device and the extended data register (D) or
extended link register (W).

QnU

RUN/

At writing to progurammable controller

*1
*2
*3

The function version is B or later.
Parameter No. is the value gained by dividing the head I/O number of parameter in the intelligent function module set by GX Configurator by 10H.
The diagnostic timing of CPU modules except for Universal QCPU can be performed only when switching the CPU modules to run.

12-48

Error
Code
(SD0)

3302

Error Contents and Cause
[SP. PARA ERROR]
The intelligent function module's refresh parameter
are abnormal.
■Collateral information
• Common Information:File name
• Individual Information:Parameter number*2
■Diagnostic Timing
• At power-On/ At reset/ STOP

Corrective Action

LED Status
CPU Status

Corresponding
CPU

1
Check the parameter setting.

QCPU

RUN/

3

At writing to progurammable controller

3303

[SP. PARA ERROR]
In a multiple CPU system, the automatic refresh
setting or other parameter setting was made to the
intelligent function module under control of another
station.
■Collateral information
• Common Information:File name/ Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power-On/ At reset/ STOP

• Delete the automatic refresh setting or other
parameter setting of the intelligent function
module under control of another CPU.
• Change the setting to the automatic refresh
setting or other parameter setting of the
intelligent function module under control of the
host CPU.

At writing to progurammable controller

3400

6

Change the head I/O number of the target module
to be within the 0H to 0FF0H range.

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

Qn(H)*1
QnPH
QnPRH
QnU*7

6
7
8

Change the head I/O number of the target module
to be within the 0H to 07E0H range.

Q02U

Change the head I/O number of the target module
of the remote password for the number within the
following range.
• Q00JCPU: 0H to 1E0H
• Q00CPU/Q01CPU: 0H to 3E0H

Q00J/Q00/Q01*1

RUN

The function version is B or later.
Parameter No. is the value gained by dividing the head I/O number of parameter in the intelligent function module set by GX Configurator by 10H.
The module whose first 5 digits of serial No. is "09012" or later.

12-49

12.1 Error Code List
12.1.5 Error code list (3000 to 3999)

*1
*2
*7

QnU*10

12

RUN

[REMOTE PASS. ERR.]
The head I/O number of the target module of the
remote password is outside the following range.
• Q00JCPU: 0H to 1E0H
• Q00CPU/Q01CPU: 0H to 3E0H
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/STOP

Qn(H)*1
QnPH

RUN

[REMOTE PASS. ERR.]
The head I/O number of the target module of the
remote password is set to other than 0H to 07E0H.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/STOP

Q00/Q01*1

RUN/

[REMOTE PASS. ERR.]
The head I/O number of the target module of the
remote password is set to other than 0H to 0FF0H.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/STOP

2

Error
Code
(SD0)

Error Contents and Cause
[REMOTE PASS. ERR.]
Position specified as the head I/O number of the
remote password file is incorrect due to one of the
following reasons:
• Module is not loaded.
• Other than a the intelligent function module (I/O
module)
• Intelligent function module other than serial
communication module, modem interface
module or Ethernet module
• Serial communication module or Ethernet
module of function version A
The intelligent function module where remote
password is available is not mounted.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/STOP

• At power ON/At reset/STOP

*1
*10

RUN

The function version is B or later.
The Universal model QCPU except the Q00UJCPU.

12-50

Corresponding
CPU

Qn(H)*1
QnPH
QnPRH
QnU

RUN:
Off
ERR.:
Flicker
Mount any of the following modules in the position
specified for the head I/O number of the remote
password.
• Serial communication module of function version
B or later
• Ethernet module of function version B or later
• Modem interface module of function version B or
later

CPU Status:
Stop
Q00J/Q00/Q01*1

RUN

[REMOTE PASS. ERR.]
Serial communication module, modem interface
module or Ethernet module of function version B or
later controlled by another CPU was specified in a
multiple CPU system.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/STOP

LED Status
CPU Status

Mount serial communication module, modem
interface module or Ethernet module of function
version B or later in the position specified in the
head I/O No. of the remote password file.

RUN

[REMOTE PASS. ERR.]
Any of the following modules is not mounted on the
slot specified for the head I/O number of the remote
password.
• Serial communication module of function version
B or later
• Ethernet module of function version B or later
• Modem interface module of function version B or
later
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing

3401

Corrective Action

• Change it for the Ethernet module of function
version B or later connected by the host CPU.
• Delete the remote password setting.

Qn(H)*1
QnPH
QnU*10

12.1.6

Error code list (4000 to 4999)

The following shows the error messages from the error code 4000 to 4999, the contents and
causes of the errors, and the corrective actions for the errors.

1
2

Error
Code
(SD0)

4000

Error Contents and Cause

Corrective Action

LED Status
CPU Status

[INSTRCT. CODE ERR]
• The program contains an instruction code that
cannot be decoded.
• An unusable instruction is included in the
program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/STOP

Corresponding
CPU

3
12

QCPU

6

RUN

When instruction executed

4001

[INSTRCT. CODE ERR]
The program contains a dedicated instruction for
SFC although it is not an SFC program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/STOP

Q00J/Q00/Q01*2
Qn(H)
QnPH
QnPRH
QnU

6
7

RUN

When instruction executed

4002

• At power ON/At reset/STOP

Read the common information of the error using a
peripheral device, check error step corresponding
to its numerical value (program error location), and
correct the problem.

8

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

RUN

When instruction executed

4003

[INSTRCT. CODE ERR]
The number of devices for the dedicated instruction
specified by the program is incorrect.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/STOP

QCPU

RUN

When instruction executed

4004

[INSTRCT. CODE ERR]
The device which cannot be used by the dedicated
instruction specified by the program is specified.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/STOP

RUN

When instruction executed

*2

The function version is B or later.

12-51

12.1 Error Code List
12.1.6 Error code list (4000 to 4999)

[INSTRCT. CODE ERR]
• The name of dedicated instruction specified by
the program is incorrect.
• The dedicated instruction specified by the
program cannot be executed by the specified
module.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing

Error
Code
(SD0)

Error Contents and Cause

Corrective Action

LED Status
CPU Status

[MISSING END INS.]
There is no END (FEND) instruction in the
program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing

4010

• At power ON/At reset/STOP

QCPU

RUN

[CAN'T SET(P)]
The total number of internal file pointers used by
the program exceeds the number of internal file
pointers set in the parameters.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing

4020

• At power ON/At reset/STOP

• At power ON/At reset/STOP

RUN:
Off
ERR.:
Flicker

RUN

[CAN'T SET(P)]
• The common pointer Nos. assigned to files
overlap.
• The local pointer Nos. assigned to files overlap.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing

4021

Read the common information of the error using a
peripheral device, check error step corresponding
to its numerical value (program error location), and
correct the problem.

Qn(H)
QnPH
QnPRH
QnU

CPU Status:
Stop

RUN

QCPU

[CAN'T SET(I)]
The allocation pointer Nos. assigned by files
overlap.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing

4030

• At power ON/At reset/STOP

RUN

[OPERATION ERROR]
The instruction cannot process the contained data.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4100

*1
*11

Corresponding
CPU

QCPU

[OPERATION ERROR]
Access error of ATA card occurs by
SP.FREAD/SP.FWRITE instructions.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

• Take measurements against noise.
• Reset and restart the CPU module.
When the same error is displayed again, the
ATA card has hardware failure.
(Please consult your local Mitsubishi service
center or representative, explaining a detailed
description of the problem.)

[OPERATION ERROR]
The file being accessed by other functions with
SP.FWRITE instruction was accessed.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

• Stop the file accessed with other functions to
execute SP.FWRITE instruction.
• Stop the access with othrer functions and the
SP.FWRITE instructuion to execute at same
time.

CPU Status:
Stop/

Qn(H)
QnPH
QnPRH
QnU*11

Continue*1

CPU operation can be set in the parameters at error occurrence. (LED indication varies.)
The Universal model QCPU except the Q00UJCPU, Q00UCPU, and Q01UCPU.

12-52

RUN:
Off/On
ERR.:
Flicker/On

QnU*11

Error
Code
(SD0)

Error Contents and Cause
[OPERATION ERROR]
• The number of setting data dealt with the
instruction exceeds the applicable range.
• The storage data and constant of the device
specified by the instruction exceeds the
applicable range.
• When writing to the host CPU shared memory,
the write prohibited area is specified for the write
destination address.
• The range of storage data of the device specified
by the instruction is duplicated.
• The device specified by the instruction exceeds
the range of the number of device points.
• The interrupt pointer No. specified by the
instruction exceeds the applicable range.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4101

[OPERATION ERROR]
• The storage data of file register specified by the
instruction exceeds the applicable range. Or, file
register is not set.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

Corrective Action

Corresponding
CPU

1
2
QCPU

3
12

Read the common information of the error using
the peripheral device, check error step
corresponding to its numerical value (program error
location), and correct the problem.

RUN:
Off/On
ERR.:
Flicker/On

6
6

CPU Status:
Stop/
Continue*1

QnU*10

7
8
QnU

12.1 Error Code List
12.1.6 Error code list (4000 to 4999)

[OPERATION ERROR]
• The block data that crosses over the boundary
between the internal user device and the
extended data register (D) or extended link
register is specified (including 32-bit binary, real
number (single precision, double precision),
indirect address, and control data)
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

*1
*10

LED Status
CPU Status

CPU operation can be set in the parameters at error occurrence. (LED indication varies.)
The Universal model QCPU except the Q00UJCPU.

12-53

Error
Code
(SD0)

Error Contents and Cause

Corrective Action

LED Status
CPU Status

Corresponding
CPU

[OPERATION ERROR]
In a multiple CPU system, the link direct device
(J \ ) was specified for the network module
under control of another station.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

• Delete from the program the link direct device
which specifies the network module under
control of another CPU.
• Using the link direct device, specify the network
module under control of the host CPU.

Q00/Q01*2
Qn(H)*2
QnPH
QnU*10

[OPERATION ERROR]
• The network No. or station No. specified for the
dedicated instruction is wrong.
• The link direct device (J \ ) setting is incorrect.
• The module No./ network No./number of
character strings exceeds the range that can be
specified.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4102

[OPERATION ERROR]
• The specification of character string
(" ") specified by dedicated instruction cannot be
used for the character string.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4103

[OPERATION ERROR]
The configuration of the PID dedicated instruction
is incorrect.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4105

[OPERATION ERROR]
PLOADP/PUNLOADP/PSWAPP instructins were
executed while setting program memory check.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4107

[OPERATION ERROR]
33 or more multiple CPU dedicated instructions
were executed from one CPU module.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

*1
*2
*5
*10

QCPU

Read the common information of the error using
the peripheral device, check error step
corresponding to its numerical value (program error
location), and correct the problem.

QnU

CPU Status:
Stop/
Continue*1
Q00J/Q00/
Q01*2
Qn(H)
QnPRH
QnU

• Delete the program memory check setting.
• When using the program memory check, delete
PLOADP/PUNLOADP/PSWAPP instructions.

Using the multiple CPU dedicated instruction
completion bit, provide interlocks to prevent one
CPU module from executing 33 or more multiple
CPU dedicated instructions.

CPU operation can be set in the parameters at error occurrence. (LED indication varies.)
The function version is B or later.
The module whose first 5 digits of serial No. is "07032" or later.
The Universal model QCPU except the Q00UJCPU.

12-54

RUN:
Off/On
ERR.:
Flicker/On

QnPH*5

Q00/Q01*2
Qn(H)*2
QnPH
Q00U/Q01U
Q02U

Error
Code
(SD0)

Error Contents and Cause

4109

[OPERATION ERROR]
With high speed interrupt setting PR, PRC,
UDCNT1, UDCNT2, PLSY or PWM instruction is
executed.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4111

[OPERATION ERROR]
An attempt was made to perform write/read to/from
the CPU shared memory write/read disable area of
the host station CPU module with the instruction.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4112

[OPERATION ERROR]
The CPU module that cannot be specified with the
multiple CPU dedicated instruction was specified.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4113

[OPERATION ERROR]
• When the SP.DEVST instruction is executed, the
number of writing to the standard ROM of the day
exceeds the value specified by SD695.
• The value outside the specified range is set to
SD695.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4121

*1
*2
*3
*10

[OPERATION ERROR]
• In the separate mode, the control system
switching instruction (SP. CONTSW) was
executed in the standby system CPU module.
• In the debug mode, the control system switching
instruction (SP. CONTSW) was executed.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

LED Status
CPU Status

Corresponding
CPU

1
Delete the high-speed interrupt setting.
When using high-speed interrupt, delete the PR,
PRC, UDCNT1, UDCNT2, PLSY and PWM
instructions.

Qn(H)*3

RUN:
Off/On
ERR.:
Flicker/On

Read the common information of the error using
GX Developer, and check and correct the error step
corresponding to that value (program error
location).

CPU Status:
Stop/

2
3

Q00/Q01*2
QnU

Continue*1

12
6

Q00/Q01*2
QnU*10

6
7

• Check that the number of execution of the
SP.DEVST instruction is proper.
• Execute the SP.DEVST instruction again the
following day or later day. Or, arrange the value
of SD695.
• Correct the value of SD695 so that it does not
exceed the range.

To execute control system switching by the SP.
CONTSW instruction, turn ON the manual system
switching enable flag (special register SM1592).

RUN:
Off/On
ERR.:
Flicker/On

QnU

CPU Status:
Stop/Continue

RUN:
Off/On
ERR.:
Flicker/On

QnPRH

CPU Status:
Stop/
Continue*1

• Reexamine the interlock signal for the SP.
CONTSW instruction, and make sure that the SP.
CONTSW instruction is executed in the control
system only. (Since the SP. CONTSW instruction
cannot be executed in the standby system, it is
recommended to provide an interlock using the
operation mode signal or like.)
• As the SP. CONTSW instruction cannot be
executed in the debug mode, reexamine the
interlock signal related to the operation mode.

8

RUN:
Off/On
ERR.:
Flicker/On

QnPRH

CPU Status:
Stop/
Continue*1

CPU operation can be set in the parameters at error occurrence. (LED indication varies.)
The function version is B or later.
The module whose first 5 digits of serial No. is "04012" or later.
The Universal model QCPU except the Q00UJCPU.

12-55

12.1 Error Code List
12.1.6 Error code list (4000 to 4999)

4120

[OPERATION ERROR]
Since the manual system switching enable flag
(special register SM1592) is OFF, manual system
switching cannot be executed by the control system
switching instruction (SP. CONTSW).
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

Corrective Action

Error
Code
(SD0)

4122

Error Contents and Cause

Corrective Action

[OPERATION ERROR]
• The dedicated instruction was executed to the
module mounted on the extension base unit in
the redundant system.
• The instruction for accessing the intelligent
function module mounted on the extension base
unit from the standby system at separate mode
was executed.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

• Delete the dedicated instruction for the module
mounted on the extension base unit.
• Delete the instruction for accessing the intelligent
function module mounted on the extension base
unit from the standby system.

[OPERATION ERROR]
Instructions to read SFC step comment
(S(P).SFCSCOMR) and SFC transition condition
comment (S(P).SFCTCOMR) are executed for the
comment file in ATA card
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When END/other instruction executed

4130

Target comment file is to be other than the
comment file in ATA card.

4140

[OPERATION ERROR]
Operation where the input data is special value
("-0", unnormalized number, nonnumeric,
) is
performed.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

Read the common information of the error using
the peripheral device, check the error step
corresponding to the numerical value (program
error part), and correct it.

4141

[OPERATION ERROR]
Overflow occurs at operation.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4200

[FOR NEXT ERROR]
No NEXT instruction was executed following the
execution of a FOR instruction.
Alternatively, there are fewer NEXT instructions
than FOR instructions.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

QnPRH*6

CPU Status:
Stop/Continue

RUN:
Off/On
ERR.:
Flicker/On

Qn(H)*4
QnPH*5
QnPRH

RUN:
Off/On
ERR.:
Flicker/On
CPU Status:
Stop/Continue

Read the common information of the error using
the peripheral device, check the error step
corresponding to the numerical value (program
error part), and correct it.

Read the common information of the error using
the peripheral device, check error step
corresponding to its numerical value (program error
location), and correct the problem.

CPU operation can be set in the parameters at error occurrence. (LED indication varies.)
The module whose first 5 digits of serial No. is "07012" or later.
The module whose first 5 digits of serial No. is "07032" or later.
The module whose first 5 digits of serial No. is "09012" or later.

12-56

Corresponding
CPU

Continue*1

Check the SFC program specified by the
instruction. Or, check the executing status of the
SFC program.

*1
*4
*5
*6

RUN:
Off/On
ERR.:
Flicker/On

CPU Status:
Stop/

[OPERATION ERROR]
The SFC program is started up by the instruction
while the other SFC program has not yet been
completed.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4131

LED Status
CPU Status

QnU
RUN:
Off/On
ERR.:
Flicker/On
CPU Status:
Stop/
Continue*1

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

QCPU

Error
Code
(SD0)

Error Contents and Cause

Corrective Action

4201

Read the common information of the error using
the peripheral device, check error step
corresponding to its numerical value (program error
location), and correct the problem.

4202

[FOR NEXT ERROR]
More than 16 nesting levels are programmed.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

Keep nesting levels at 16 or under.

4203

[FOR NEXT ERROR]
A BREAK instruction was executed although no
FOR instruction has been executed prior to that.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4210

4211

4212

[CAN'T EXECUTE(P)]
The RET instruction exists before the FEND
instruction of the main routine program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4213

[CAN'T EXECUTE(P)]
More than 16 nesting levels are programmed.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

2
3
12
6
6

Read the common information of the error using
the peripheral device, check error step
corresponding to its numerical value (program error
location), and correct the problem.

RUN:
Off
ERR.:
Flicker

7
QCPU

CPU Status:
Stop

8

12.1 Error Code List
12.1.6 Error code list (4000 to 4999)

[CAN'T EXECUTE(P)]
There was no RET instruction in the executed
subroutine program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

Corresponding
CPU

1

[FOR NEXT ERROR]
A NEXT instruction was executed although no FOR
instruction has been executed.
Alternatively, there are more NEXT instructions
than FOR instructions.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

[CAN'T EXECUTE(P)]
The CALL instruction is executed, but there is no
subroutine at the specified pointer.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

LED Status
CPU Status

Read the common information of the error using
the peripheral device, check error step
corresponding to its numerical value (program error
location), and correct the problem.

Keep nesting levels at 16 or under.

12-57

Error
Code
(SD0)

Error Contents and Cause

4220

[CAN'T EXECUTE(I)]
Though an interrupt input occurred, the
corresponding interrupt pointer does not exist.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4221

[CAN'T EXECUTE(I)]
An IRET instruction does not exist in the executed
interrupt program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed
[CAN'T EXECUTE(I)]
The IRET instruction exists before the FEND
instruction of the main routine program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4225

[CAN'T EXECUTE(I)]
The interrupt pointer for the module mounted on
the extension base unit is set in the redundant
system.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power-ON/At reset

4230

[INST. FORMAT ERR.]
The number of CHK and CHKEND instructions is
not equal.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed
[INST. FORMAT ERR.]
The number of IX and IXEND instructions is not
equal.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4231

Corresponding
CPU

Read the common information of the error using
the peripheral device, check error step
corresponding to its numerical value (program error
location), and correct the problem.

RUN:
Off
ERR.:
Flicker

QnU

CPU Status:
Stop

Delete the setting of interrupt pointer for the module
mounted on the extension base unit, since it cannot
be used.

QnPRH*6

Qn(H)
QnPH
Read the common information of the error using
the peripheral device, check error step
corresponding to its numerical value (program error
location), and correct the problem.

The module whose first 5 digits of serial No. is "09012" or later.

12-58

LED Status
CPU Status

QCPU

[CAN'T EXECUTE(I)]
• The IRET instruction was executed in the fixed
scan execution type program.
• The STOP instruction was executed in the fixed
scan execution type program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4223

*6

Corrective Action

QCPU

Error
Code
(SD0)

4235

Error Contents and Cause

Corrective Action

LED Status
CPU Status

Corresponding
CPU

1

[INST. FORMAT ERR.]
The configuration of the check conditions for the
CHK instruction is incorrect.
Alternatively, a CHK instruction has been used in a
low speed execution type program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

Qn(H)
QnPH

3

[MULTI-COM.ERROR]
• The multiple CPU high-speed transmission
dedicated instruction used in the program
specifies the wrong CPU module. Or, the setting
in the CPU module is incompatible with the
multiple CPU high-speed transmission dedicated
instruction.
• The reserved CPU is specified.
• The uninstalled CPU is specified.
• The head I/O number of the target CPU/16 (n1)
is outside the range of 3EH to 3E3H.
4350

• The CPU module where the instruction cannot be
executed is specified.
• The instruction is executed in a single CPU
system.
• The host CPU is specified.
• The instruction is executed without setting the
"Use multiple CPU high speed communication".
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4352

[MULTI-COM.ERROR]
The number of devices for the multiple CPU highspeed transmission dedicated instruction specified
by the program is wrong.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

*7

12
6
6
Read the common information of the error using
the peripheral device, check error step
corresponding to its numerical value (program error
location), and correct the problem.

RUN:
Off
ERR.:
Flicker

7

CPU Status:
Stop

8
QnU*7

12.1 Error Code List
12.1.6 Error code list (4000 to 4999)

4351

[MULTI-COM.ERROR]
• The multiple CPU high-speed transmission
dedicated instruction specified by the program
cannot be executed to the specified target CPU
module.
• The instruction name is wrong.
• The instruction unsupported by the target CPU
module is specified.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

2

The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.

12-59

Error
Code
(SD0)

Error Contents and Cause

4353

[MULTI-COM.ERROR]
The device which cannot be used for the multiple
CPU high-speed transmission dedicated instruction
specified by the program is specified.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4354

[MULTI-COM.ERROR]
The character string which cannot be handled by
the multiple CPU high-speed transmission
dedicated instruction is specified.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4355

[MULTI-COM.ERROR]
The number of read/write data (number of request/
receive data) for the multiple CPU high-speed
transmission dedicated instruction specified by the
program is not valid.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

• STOP

LED Status
CPU Status

Corresponding
CPU

QnU*7

Read the common information of the error using
the peripheral device, check error step
corresponding to its numerical value (program error
location), and correct the problem.

QnU*7

RUN:
Off
ERR.:
Flicker

[SFCP. CODE ERROR]
No SFCP or SFCPEND instruction in SFC
program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing

4400

CPU Status:
Stop

Qn(H)
QnPH
QnPRH

RUN

[CAN'T SET(BL)]
The block number designated by the SFC program
exceeds the range.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing

4410

• STOP

RUN

[CAN'T SET(BL)]
Block number designations overlap in SFC
program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing

4411

• STOP

Write the program to the CPU module again using
GX Developer.

RUN

[CAN'T SET(S)]
A step number designated in an SFC program
exceeds the range.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing

4420

• STOP

*2
*7

Corrective Action

RUN

The function version is B or later.
The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.

12-60

Q00J/Q00/Q01*2
Qn(H)
QnPH
QnPRH
QnU

Error
Code
(SD0)

4421

Error Contents and Cause
[CAN'T SET(S)]
Total number of steps in all SFC programs exceed
the maximum.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• STOP

4422

[CAN'T SET(S)]
Step number designations overlap in SFC program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• STOP

4423

2
3
12
6

Correct the total number of step relays so that it
does not exceed the total number of (maximum
step No.+1) of each block.

6

RUN:
Off
ERR.:
Flicker
• Write the program to the CPU module again
using GX Developer.
• After correcting the setting of the SFC data
device, write it to the CPU module.
• After correcting the device setting range set in
the PLC parameter, write it to the CPU module.

7

CPU Status:
Stop

8
Q00J/Q00/Q01*2
QnU

RUN

RUN

[SFC EXE. ERROR]
The SFC program cannot be executed.
• The structure of the SFC program is illegal.
■Collateral information
• Common Information:File name/Drive name
• Individual Information:–
■Diagnostic Timing
• STOP

*2

Write the program to the CPU module again using
GX Developer.

[SFC EXE. ERROR]
The SFC program cannot be executed.
• The block parameter setting is abnormal.
■Collateral information
• Common Information:File name/Drive name
• Individual Information:–
■Diagnostic Timing
• STOP

4432

Q00J/Q00/Q01*2
Qn(H)
QnPH
QnPRH
QnU

12.1 Error Code List
12.1.6 Error code list (4000 to 4999)

4431

Corresponding
CPU

1

RUN

[SFC EXE. ERROR]
The SFC program cannot be executed.
• The data of the block data setting is illegal.
• The SFC data device of the block data setting is
beyond the device setting range set in the PLC
parameter.
■Collateral information
• Common Information:File name/Drive name
• Individual Information:–
■Diagnostic Timing
• STOP

LED Status
CPU Status

RUN

[CAN'T SET(S)]
The total number of (maximum step No.+1) of each
block exceeds the total number of step relays.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• STOP

4430

RUN

Corrective Action

Write the program to the CPU module again using
GX Developer.

RUN

The function version is B or later.

12-61

Error
Code
(SD0)

Error Contents and Cause

LED Status
CPU Status

Corresponding
CPU

[SFCP. FORMAT ERR.]
The numbers of BLOCK and BEND instructions in
an SFC program are not equal.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing

4500

• STOP

RUN

[SFCP. FORMAT ERR.]
The configuration of the STEP* to TRAN* to TSET
to SEND instructions in the SFC program is
incorrect.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing

4501

• STOP

Qn(H)
QnPH
QnPRH

Write the program to the CPU module again using
the peripheral device.

RUN

[SFCP. FORMAT ERR.]
The structure of the SFC program is illegal.
• STEPI* instruction does not exist in the block of
the SFC program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing

4502

• STOP

• STOP

• STOP

RUN

The function version is B or later.

12-62

CPU Status:
Stop

• Write the program to the CPU module again
using GX Developer.
• Read the common information of the error using
GX Developer, and check and correct the error
step corresponding to that value (program error
location).

RUN

[SFCP. FORMAT ERR.]
The structure of the SFC program is illegal.
• The step specified in the TAND instruction does
not exist.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing

4504

RUN:
Off
ERR.:
Flicker

RUN

[SFCP. FORMAT ERR.]
The structure of the SFC program is illegal.
• The step specified in the TSET instruction does
not exist.
• In jump transition, the host step number was
specified as the destination step number.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing

4503

*2

Corrective Action

Write the program to the CPU module again using
GX Developer.

Q00J/Q00/Q01*2
Qn(H)
QnPH
QnPRH
QnU

Error
Code
(SD0)

4505

Error Contents and Cause
[SFCP. FORMAT ERR.]
The structure of the SFC program is illegal.
• In the operation output of a step, the SET Sn/
BLmSn or RST Sn/BLmSn instruction was
specified for the host step.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• STOP

4506

RUN

[SFCP. FORMAT ERR.]
The structure of the SFC program is illegal.
• In a reset step, the host step number was
specified as the destination step.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• STOP

4600

4601

[SFCP. OPE. ERROR]
Exceeds device range that can be designated by
the SFC program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

Corresponding
CPU

1
2
Read the common information of the error using
GX Developer, and check and correct the error step
corresponding to that value (program error
location).

RUN:
Off
ERR.:
Flicker

Q00J/Q00/Q01*2
QnU

CPU Status:
Stop

3
12
6
6
7

Read common information of the error using the
peripheral device, check error step corresponding
to its numerical value (program error location), and
correct the problem.

RUN:
Off/On
ERR.:
Flicker/On
CPU Status:
Stop/

Qn(H)
QnPH
QnPRH

8

Continue*1

[SFCP. OPE. ERROR]
The START instruction in an SFC program is
preceded by an END instruction.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

12.1 Error Code List
12.1.6 Error code list (4000 to 4999)

*1
*2

LED Status
CPU Status

RUN

[SFCP. OPE. ERROR]
The SFC program contains data that cannot be
processed.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4602

Corrective Action

CPU operation can be set in the parameters at error occurrence. (LED indication varies.)
The function version is B or later.

12-63

Error
Code
(SD0)

Error Contents and Cause
[SFCP. EXE. ERROR]
The active step information at presumptive start of
the SFC program is incorrect.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing

4610

• STOP

RUN

[SFCP. EXE. ERROR]
Key-switch was reset during RUN when
presumptive start was designated for SFC
program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing

4611

• STOP

4620

4621

[BLOCK EXE. ERROR]
Startup was attempted at a block that does not exist
in the SFC program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

*2

[STEP EXE. ERROR]
Startup was executed at a block in the SFC
program that was already started up.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

The function version is B or later.

12-64

Read common information of the error using the
peripheral device, check error step corresponding
to its numerical value (program error location), and
correct the problem.
The program is automatically subjected to an initial
start.

LED Status
CPU Status

Corresponding
CPU

RUN:
On
ERR.:
On
CPU Status:
Continue

Qn(H)
QnPH
QnPRH

RUN

[BLOCK EXE. ERROR]
Startup was executed at a block in the SFC
program that was already started up.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

4630

Corrective Action

Read common information of the error using the
peripheral device, check error step corresponding
to its numerical value (program error location), and
correct the problem.

• Read the common information of the error using
GX Developer, and check and correct the error
step corresponding to that value (program error
location).
• Turn ON if the special relay SM321 is OFF.

Read common information of the error using the
peripheral device, check error step corresponding
to its numerical value (program error location), and
correct the problem.

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

Q00J/Q00/Q01*2
Qn(H)
QnPH
QnPRH
QnU

Qn(H)
QnPH
QnPRH

Error
Code
(SD0)

4631

4632

4633

Error Contents and Cause
[STEP EXE. ERROR]
• Startup was attempted at the step that does not
exist in the SFC program.
Or, the step that does not exist in the SFC
program was specified for end.
• Forced transition was executed based on the
transition condition that does not exit in the SFC
program.
Or, the transition condition for forced transition
that does not exit in the SFC program was
canceled.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

Corrective Action

LED Status
CPU Status

Corresponding
CPU

1

Q00J/Q00/Q01*2
Qn(H)
QnPH
QnPRH
QnU

• Read the common information of the error using
the peripheral device, and check and correct the
error step corresponding to that value (program
error location).
• Turn ON if the special relay SM321 is OFF.

[STEP EXE. ERROR]
There were too many simultaneous active steps in
blocks that can be designated by the SFC program.
■Collateral information
• Common Information:Program error location
• Individual Information:–
Read common information of the error using the
■Diagnostic Timing
• When instruction executed
peripheral device, check error step corresponding
to its numerical value (program error location), and
[STEP EXE. ERROR]
There were too many simultaneous active steps in correct the problem.
all blocks that can be designated.
■Collateral information
• Common Information:Program error location
• Individual Information:–
■Diagnostic Timing
• When instruction executed

2
3
12

RUN:
Off
ERR.:
Flicker

6

CPU Status:
Stop

Qn(H)
QnPH
QnPRH
QnU

6
7
8

12.1 Error Code List
12.1.6 Error code list (4000 to 4999)

*2

The function version is B or later.

12-65

12.1.7

Error code list (5000 to 5999)

The following shows the error messages from the error code 5000 to 5999, the contents and
causes of the errors, and the corrective actions for the errors.
Error
Code
(SD0)

5000

5001

12-66

LED Status
CPU Status

Corresponding
CPU

Error Contents and Cause

Corrective Action

[WDT ERROR]
• The scan time of the initial execution type
program exceeded the initial execution
monitoring time specified in the PLC RAS setting
of the PLC parameter.
■Collateral information
• Common Information:Time (value set)
• Individual Information:Time (value actually
measured)
■Diagnostic Timing
• Always

• Read the individual information of the error from
the peripheral device, check its value (time), and
shorten the scan time.
• Change the initial execution monitoring time or
the WDT value in the PLC RAS setting of the
PLC parameter.
• Resolve the endless loop caused by jump
transition.

Qn(H)
QnPH
QnPRH
QnU

[WDT ERROR]
• The power supply of the standby system is
turned OFF.
• The tracking cable is disconnected or connected
without turning off or resetting the standby
system.
• The tracking cable is not secured by the
connector fixing screws.
■Collateral information
• Common Information:Time (value set)
• Individual Information:Time (value actually
measured)
■Diagnostic Timing
• Always

• Since power-off of the standby system increases
the control system scan time, reset the WDT
value, taking the increase of the control system
scan time into consideration.
• When the tracking cable is disconnected during
operation, securely connect it and restart the
CPU module. If the same error is displayed
again, the tracking cable or CPU module has a
hardware fault. (Contact your local Mitsubishi
representative, explaining a detailed description
of the problem.)

QnPRH

[WDT ERROR]
• The scan time of the program exceeded the
WDT value specified in the PLC RAS setting of
the PLC parameter.
■Collateral information
• Common Information:Time (value set)
• Individual Information:Time (value actually
measured)
■Diagnostic Timing
• Always

• Read the individual information of the error using
the peripheral device, check its value (time), and
shorten the scan time.
• Change the initial execution monitoring time or
the WDT value in the PLC RAS setting of the
PLC parameter.
• Resolve the endless loop caused by jump
transition.

[WDT ERROR]
• The power supply of the standby system is
turned OFF.
• The tracking cable is disconnected or connected
without turning off or resetting the standby
system.
• The tracking cable is not secured by the
connector fixing screws.
■Collateral information
• Common Information:Time (value set)
• Individual Information:Time (value actually
measured)
■Diagnostic Timing
• Always

• Since power-off of the standby system increases
the control system scan time, reset the WDT
value, taking the increase of the control system
scan time into consideration.
• When the tracking cable is disconnected during
operation, securely connect it and restart the
CPU module. If the same error is displayed
again, the tracking cable or CPU module has a
hardware fault. (Contact your local Mitsubishi
representative, explaining a detailed description
of the problem.)

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop
QCPU

QnPRH

Error
Code
(SD0)

Error Contents and Cause
[PRG. TIME OVER]
The program scan time exceeded the constant
scan setting time specified in the PLC RAS setting
of the PLC parameter.
■Collateral information
• Common Information:Time (value set)
• Individual Information:Time (value actually
measured)
■Diagnostic Timing
• Always

5010

5011

[PRG. TIME OVER]
The low speed program execution time specified in
the PLC RAS setting of the PLC parameter
exceeded the excess time of the constant scan.
■Collateral information
• Common Information:Time (value set)
• Individual Information:Time (value actually
measured)
■Diagnostic Timing
• Always

Corrective Action

LED Status
CPU Status

Corresponding
CPU

1
Qn(H)
QnPH
QnPRH
QnU
• Review the constant scan setting time.
• Review the constant scan setting time and low
speed program execution time in the PLC
parameter so that the excess time of constant
scan can be fully secured.

3
Qn(H)
QnPH
QnPRH

Review the constant scan setting time in the PLC
parameter so that the excess time of constant scan
can be fully secured.

[PRG. TIME OVER]
The scan time of the low speed execution type
program exceeded the low speed execution watch
time specified in the PLC RAS setting of the PLC
parameter dialog box.
■Collateral information
• Common Information:Time (value set)
• Individual Information:Time (value actually
measured)
■Diagnostic Timing
• Always

Read the individual information of the error using
the peripheral device, check the numerical value
(time) there, and shorten scan time if necessary.
Change the low speed execution watch time in the
PLC RAS setting of the PLC parameter dialog box.

12
6

RUN:
On
ERR.:
On

[PRG. TIME OVER]
The program scan time exceeded the constant
scan setting time specified in the PLC RAS setting
of the PLC parameter.
■Collateral information
• Common Information:Time (value set)
• Individual Information:Time (value actually
measured)
■Diagnostic Timing
• Always

2

6

CPU Status:
Continue
Q00J/Q00/Q01

7
8
Qn(H)
QnPH

12.1 Error Code List
12.1.7 Error code list (5000 to 5999)

12-67

12.1.8

Error code list (6000 to 6999)

The following shows the error messages from the error code 6000 to 6999, the contents and
causes of the errors, and the corrective actions for the errors.
Error
Code
(SD0)

Error Contents and Cause

Corrective Action

LED Status
CPU Status

Corresponding
CPU

[FILE DIFF.]
In a redundant system, the control system and
standby system do not have the same programs
and parameters.
The file type detected as different between the two
systems can be checked by the file name of the
error common information.

6000

6001

12-68

• The program is different.
(File name = ********.QPG)
• The PLC parameters/network parameters/
redundant parameters are different.
(File name = PARAM.QPA)
• The remote password is different.
(File name = PARAM.QPA)
• The intelligent function module parameters are
different.
(File name = IPARAM.QPA)
• The device initial values are different.
(File name = ********.QDI)
• The capacity of each write destination within the
CPU for online pchange of multiple program
blocks is different.
(File name = MBOC.QMB)
(This can be detected from the standby system
of the redundant system.)
■Collateral information
• Common Information:File name
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/
At tracking cable connection/At changing to
backup mode/At completion of write during RUN/
At system switching/At switching both systems
into RUN
[FILE DIFF.]
In a redundant system, the valid parameter drive
settings (SW2, SW3) made by the DIP switches are
not the same.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/At tracking cable
connection/At operation mode change

• Match the programs and parameters of the
control system and standby system.
• Verify the systems by either of the following
procedures 1), 2) to clarify the differences
between the files of the two systems, then
correct a wrong file, and execute “Write to PLC“
again.
1) After reading the programs/parameters of
System A using
GX Developer or PX Developer, verify them
with those of System B.
2) Verify the programs/parameters of GX
Developer or PX Developer saved in the
offline environment with those written to the
CPU modules of both systems.
• When the capacity of each write destination
within the CPU for online change of multiple
program blocks is different between the two
systems, take corrective action 1) or 2).
1) Using the memory copy from control system
to standby system, copy the program memory
from the control system to the standby
system.
2) Format the CPU module program memories
of both systems. (For the capacity of each
write destination within the CPU for online
change of multiple program blocks, set the
same value to both systems.)

Match the valid parameter drive settings (SW2,
SW3) by the DIP switches of the control system
and standby system.

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

QnPRH

Error
Code
(SD0)

6010

Error Contents and Cause
[OPE. MODE DIFF.]
The operational status of the control system and
standby system in the redundant system is not the
same.
(This can be detected from the standby system of
the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

6020

[OPE. MODE DIFF.]
At power ON/reset, the RUN/STOP switch settings
of the control system and standby system are not
the same in a redundant system.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

6030

[UNIT LAY. DIFF.]
• In a redundant system, the module configuration
differs between the control system and standby
system.
• The network module mode setting differs
between the two systems.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common Information:Module No.
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/At tracking cable
connection/At operation mode change

LED Status
CPU Status

Corresponding
CPU

1
Synchronise the operation statuses of the control
system and standby system.

RUN:
On
ERR.:
On

2

CPU Status:
Continue

3
12

Set the RUN/STOP switches of the control system
and standby system to the same setting.

6
6
QnPRH

• Match the module configurations of the control
system and standby system.
• In the redundant setting of the network
parameter dialog box, match the mode setting of
System B to that of System A.

7

RUN:
Off
ERR.:
Flicker

8

CPU Status:
Stop

12.1 Error Code List
12.1.8 Error code list (6000 to 6999)

6035

[UNIT LAY. DIFF.]
In a redundant system, the CPU module model
name differs between the control system and
standby system.
(This can be detected from the standby system of
the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/At tracking cable
connection/At operation mode change

Corrective Action

Match the model names of the control system and
standby system.

12-69

Error
Code
(SD0)

Error Contents and Cause

Corrective Action

6036

[UNIT LAY. DIFF.]
A difference in the remote I/O configuration of the
MELSECNET/H multiplexed remote I/O network
between the control system and standby system of
a redundant system was detected.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common Information:Module No.
• Individual Information:–
■Diagnostic Timing
• Always

Check the network cables of the MELSECNET/H
multiplexed remote I/O network for disconnection.

6040

[CARD TYPE DIFF.]
In a redundant system, the memory card
installation status (installed/not installed) differs
between the control system and standby system.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

Match the memory card installation statuses (set/
not set) of the control system and standby system.

6041

[CARD TYPE DIFF.]
In a redundant system, the memory card type
differs between the control system and standby
system.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

Match the memory card types of the control system
and standby system.

6050

6060

12-70

[CAN'T EXE. MODE]
The function inexecutable in the debug mode or
operation mode (backup/separate mode) was
executed.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always
[CPU MODE DIFF.]
In a redundant system, the operation mode
(backup/separate) differs between the control
system and standby system.
(This can be detected from the standby system of
the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/At tracking cable
connection

LED Status
CPU Status

Corresponding
CPU

RUN:
Off
ERR.:
Flicker

Execute the function executable in the debug mode
or operation mode (backup/separate mode).

CPU Status:
Stop

QnPRH

RUN:
On
ERR.:
On
CPU Status:
Continue

Match the operation modes of the control system
and standby system.

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

Error
Code
(SD0)

6061

Error Contents and Cause
[CPU MODE DIFF.]
In a redundant system, the operation mode
(backup/separate) differs between the control
system and standby system.
(This can be detected from the standby system of
the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• When an END instruction executed

6062

[CPU MODE DIFF.]
Both System A and B are in the same system
status (control system).
(This can be detected from the system B of the
redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset/At tracking cable
connection

6100

[TRK. TRANS. ERR.]
• An error (e.g. retry limit exceeded) occurred in
tracking data transmission.
(This error may be caused by tracking cable
removal or other system power-off (including
reset).)
• The error occurred at a startup since the
redundant system startup procedure was not
followed.
■Collateral information
• Common Information:Tracking transmission data
classification
• Individual Information:–
■Diagnostic Timing
• Always

LED Status
CPU Status

Corresponding
CPU

1
2

Match the operation modes of the control system
and standby system.
RUN:
Off
ERR.:
Flicker

3
12

CPU Status:
Stop
Power the CPU module (System B) which resulted
in a stop error, OFF and then ON.

6
6
QnPRH

7
8

• Check the CPU module or tracking cable. If the
error still occurs, this indicates the CPU module
or tracking cable is faulty. (Contact your local
Mitsubishi representative, explaining a detailed
description of the problem.)
• Confirm the redundant system startup procedure,
and execute a startup again.

RUN:
On
ERR.:
On

12.1 Error Code List
12.1.8 Error code list (6000 to 6999)

6101

[TRK. TRANS. ERR.]
• A timeout error occurred in tracking (data
transmission).
(This error may be caused by tracking cable
removal or other system power-off (including
reset).)
• The error occurred at a startup since the
redundant system startup procedure was not
followed.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common Information:Tracking transmission data
classification
• Individual Information:–
■Diagnostic Timing
• Always

Corrective Action

CPU Status:
Continue

12-71

Error
Code
(SD0)

Error Contents and Cause

6102

[TRK. TRANS. ERR.]
A data sum value error occurred in tracking (data
reception).
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

6103

[TRK. TRANS. ERR.]
• A data error (other than sum value error)
occurred in tracking (data reception).
(This error may be caused by tracking cable
removal or other system power-off (including
reset).)
• The error occurred at a startup since the
redundant system startup procedure was not
followed.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

6105

[TRK. TRANS. ERR.]
• An error (e.g. retry limit exceeded) occurred in
tracking (data transmission).
(This error may be caused by tracking cable
removal or other system power-off (including
reset).)
• The error occurred at a startup since the
redundant system startup procedure was not
followed.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common Information:Tracking transmission data
classification
• Individual Information:–
■Diagnostic Timing
• Always

6106

[TRK. TRANS. ERR.]
• A timeout error occurred in tracking (data
transmission).
(This error may be caused by tracking cable
removal or other system power-off (including
reset).)
• The error occurred at a startup since the
redundant system startup procedure was not
followed.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common Information:Tracking transmission data
classification
• Individual Information:–
■Diagnostic Timing
• Always

12-72

Corrective Action

LED Status
CPU Status

Corresponding
CPU

• Check the CPU module or tracking cable. If the
error still occurs, this indicates the CPU module
or tracking cable is faulty. (Contact your local
Mitsubishi representative, explaining a detailed
description of the problem.)
• Confirm the redundant system startup procedure,
and execute a startup again.
RUN:
On
ERR.:
On
CPU Status:
Continue

• Check the CPU module or tracking cable. If the
error still occurs, this indicates the CPU module
or tracking cable is faulty. (Contact your local
Mitsubishi representative, explaining a detailed
description of the problem.)
• Confirm the redundant system startup procedure,
and execute a startup again.

QnPRH

Error
Code
(SD0)

Error Contents and Cause

6107

[TRK. TRANS. ERR.]
A data sum value error occurred in tracking (data
reception).
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

6108

[TRK. TRANS. ERR.]
• A data error (other than sum value error)
occurred in tracking (data reception).
(This error may be caused by tracking cable
removal or other system power-off (including
reset).)
• The error occurred at a startup since the
redundant system startup procedure was not
followed.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

Corrective Action

LED Status
CPU Status

Corresponding
CPU

1
2
3

• Check the CPU module or tracking cable. If the
error still occurs, this indicates the CPU module
or tracking cable is faulty. (Contact your local
Mitsubishi representative, explaining a detailed
description of the problem.)
• Confirm the redundant system startup procedure,
and execute a startup again.

12
6
6
RUN:
On
ERR.:
On

Reexamine the tracking capacity.

6111

[TRK. SIZE ERROR]
The control system does not have enough file
register capacity for the file registers specified in
the tracking settings.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• When an END instruction executed

Switch to the file registers of which capacity is
greater than the file registers specified in the
tracking settings.

6112

[TRK. SIZE ERROR]
File registers greater than those of the standby
system were tracked and transmitted from the
control system.
(This can be detected from the standby system of
the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• When an END instruction executed

Switch to the file registers of which capacity is
greater than the file registers specified in the
tracking settings.

7
QnPRH

8

CPU Status:
Continue

12.1 Error Code List
12.1.8 Error code list (6000 to 6999)

6110

[TRK. SIZE ERROR]
The tracking capacity exceeded the allowed range.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common Information:Tracking capacity excess
error factor
• Individual Information:–
■Diagnostic Timing
• When an END instruction executed

12-73

Error
Code
(SD0)

6120

6130

6140

6200

12-74

Error Contents and Cause

Corrective Action

[TRK. CABLE ERR.]
• A start was made without the tracking cable
being connected.
• A start was made with the tracking cable faulty.
• As the tracking hardware on the CPU module
side was faulty, communication with the other
system could not be made via the tracking cable.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

Make a start after connecting the tracking cable. If
the same error still occurs, this indicates the
tracking cable or CPU module side tracking
transmission hardware is faulty.
(Contact your local Mitsubishi representative,
explaining a detailed description of the problem.)

[TRK. DISCONNECT]
• The tracking cable was removed.
• The tracking cable became faulty while the CPU
module is running.
• The CPU module side tracking hardware
became faulty.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

• If the tracking cable was removed, connect the
tracking cable to the connectors of the CPU
modules of the two systems.
• When the error is not resolved after connecting
the tracking cable to the connectors of the CPU
modules of the two systems and resetting the
error, the tracking cable or CPU module side
tracking hardware is faulty.
(Contact your local Mitsubishi representative,
explaining a detailed description of the problem.)

[TRK.INIT. ERROR]
• The other system did not respond during initial
communication at power ON/reset.
• The error occurred at a startup since the
redundant system startup procedure was not
followed.
(This can be detected from the control system or
standby system of the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

• Power the corresponding CPU module OFF and
then ON again, or reset it and then unreset. If the
same error still occurs, this indicates the CPU
module is faulty. (Contact your local Mitsubishi
representative, explaining a detailed description
of the problem.)
• Confirm the redundant system startup procedure,
and execute a startup again.

[CONTROL EXE.]
The standby system has been switched to the
control system in a redundant system. (Detected by
the CPU that was switched from the standby
system to the control system)
Since this error code does not indicate the error
information of the CPU module but indicates its
status, the error code and error information are not
stored into SD0 to 26, but are stored into the error
log every system switching.
(Check the error information by reading the error
log using GX Developer.)
■Collateral information
• Common Information:Reason(s) for system
switching
• Individual Information:–
■Diagnostic Timing
• Always

LED Status
CPU Status

Corresponding
CPU

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

RUN:
On
ERR.:
On
CPU Status:
Continue

QnPRH

–

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

RUN:
On
ERR.:
Off
CPU Status:
No error

Error
Code
(SD0)

6210

6220

[STANDBY]
The control system has been switched to the
standby system in a redundant system. (Detected
by the CPU that was switched from the control
system to the standby system)
Since this error code does not indicate the error
information of the CPU module but indicates its
status, the error code and error information are not
stored into SD0 to 26, but are stored into the error
log every system switching.
(Check the error information by reading the error
log using GX Developer.)
■Collateral information
• Common Information:Reason(s) for system
switching
• Individual Information:–
■Diagnostic Timing
• Always

Corrective Action

LED Status
CPU Status

Corresponding
CPU

1

–

2

RUN:
On
ERR.:
Off

3

CPU Status:
No error

12
6

[CAN'T SWITCH]
System switching cannot be executed due to
standby system error/ tracking cable error/ online
module change in execution at separate mode.
Causes for switching system at control system are
as follows:
• System switching by SP. CONTSW instruction
• System switching request from network module
■Collateral information
• Common Information:Reason(s) for system switching
• Individual Information:Reason(s) for system switching
failure
■Diagnostic Timing
• At switching execution

• Check the status of the standby system and
resolve the error.
• Complete the online module change.

[STANDBY SYS. DOWN]
Any of the following errors was detected in the
backup mode.
• The standby system has not started up in the
redundant system.
• The standby system has developed a stop error
in the redundant system.
• The CPU module in the debug mode was
connected to the operating control system.
(This can be detected from the control system of
the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

• Check whether the standby system is on or not,
and if it is not on, power it on.
• Check whether the standby system has been
reset or not, and if it has been reset, unreset it.
• Check whether the standby system has
developed a stop error or not, and if it has
developed the error, remove the error factor and
restart it.
• When the CPU module in the debug mode was
connected to the control system operating in the
backup mode, make connection so that the
control system and standby system are
combined correctly.

RUN:
On
ERR.:
On

6
QnPRH

7

CPU Status:
No error

8

RUN:
On
ERR.:
On

12.1 Error Code List
12.1.8 Error code list (6000 to 6999)

6300

Error Contents and Cause

CPU Status:
Continue

12-75

Error
Code
(SD0)

6310

6311

6312

6313

6400

12-76

Error Contents and Cause

Corrective Action

LED Status
CPU Status

[CONTROL SYS. DOWN]
Any of the following errors was detected in the
backup mode.
• The control system has not started up in the
redundant system.
• The control system has developed a stop error in
the redundant system.
• The CPU module in the debug mode was
connected to the operating standby system.
• The error occurred at a startup since the
redundant system startup procedure was not
followed.
(This can be detected from the standby system of
the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

• The standby system exists but the control system
does not exist.
• Check whether the system other than the
standby system is on or not, and if it is not on,
power it on.
• Check whether the system other than the
standby system has been reset or not, and if it is
RUN:
has been reset, unreset it.
Off
• Check whether the system other than the
ERR.:
standby system has developed a stop error or
Flicker
not, and if has developed the error, remove the
error factor, set the control system and standby
CPU Status:
system to the same operating status, and restart.
Stop
• When the CPU module in the debug mode was
connected to the control system operating in the
backup mode, make connection so that the
control system and control system are combined
correctly.
• Confirm the redundant system startup procedure,
and execute a startup again.

[CONTROL SYS. DOWN]
• As consistency check data has not transmitted
from the control system in a redundant system,
the other system cannot start as a standby
system.
• The error occurred at a startup since the
redundant system startup procedure was not
followed.
(This can be detected from the standby system of
the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

• Replace the tracking cable. If the same error still
occurs, this indicates the CPU module is faulty.
(Contact your local Mitsubishi representative,
explaining a detailed description of the problem.)
• Confirm the redundant system startup procedure,
and execute a startup again.

[CONTROL SYS. DOWN]
The control system detected the error of the system
configuration and informed it to the standby system
(host system) in the redundant system.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset
[PRG. MEM. CLEAR]
The memory copy from control system to standby
system was executed, and the program memory
was cleared.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At execution of the memory copy from control
system to standby system

Restart the system after checking that the
connection between base unit and the system
configuration (type/number/parameter of module)
are correct.

After the memory copy from control system to
standby system is completed, switch power OFF
and then ON, or make a reset.

Corresponding
CPU

QnPRH

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

RUN:
Off
ERR.:
Flicker

QnPRH*1

CPU Status:
Stop

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

QnPRH

Error
Code
(SD0)

6410

6500

6501

Error Contents and Cause
[MEM.COPY EXE]
The memory copy from control system to standby
system was executed.
(This can be detected from the control system of
the redundant system.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At execution of the function of copying memory
from control system to standby system

Corrective Action

LED Status
CPU Status

Corresponding
CPU

1
–

RUN:
On
ERR.:
On

2

CPU Status:
Continue

[TRK. PARA. ERROR]
The file register file specified in the tracking setting
of the PLC parameter dialog box does not exist.
■Collateral information
• Common Information:File name/Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset

Read the individual information of the error using
GX Developer, and check and correct the drive
name and file name. Create the specified file.

[TRK. PARA. ERROR]
The file register range specified in the device detail
setting of the tracking setting of the PLC parameter
dialog box exceeded the specified file register file
capacity.
■Collateral information
• Common Information:File name/Drive name
• Individual Information:Parameter number
■Diagnostic Timing
• At power ON/At reset

Read the individual information of the error using
GX Developer, and increase the file register
capacity.

3

QnPRH
RUN:
Off
ERR.:
Flicker

12
6
6

CPU Status:
Stop

7
8

12.1 Error Code List
12.1.8 Error code list (6000 to 6999)

12-77

12.1.9

Error code list (7000 to 10000)

The following shows the error messages from the error code 7000 to 10000, the contents and
causes of the errors, and the corrective actions for the errors.
Error
Code
(SD0)

7000

Error Contents and Cause

Corrective Action

[MULTI CPU DOWN]
• In the operating mode of a multiple CPU system,
a CPU error occurred at the CPU where "All
station stop by stop error of CPU " was selected.
• In a multiple CPU system, a CPU module
incompatible with the multiple CPU system was
mounted.
• CPU modules other than CPU No.1 were
removed from the base unit in operation, or
reset.
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• Always

• Read the individual information of the error using
GX Developer, identify the error of the CPU
module, and remove the error.
• Remove the CPU module incompatible with the
multiple CPU system from the main base unit.
• Check the mounting status of CPU modules
other than CPU No.1 and whether the CPU
modules were reset.

[MULTI CPU DOWN]
In a multiple CPU system, CPU other than CPU
No.1 cannot be started up due to stop error of the
CPU No.1 at power-on, which occurs to CPU No.2
to No.4.
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

7002

7003

*1
*6

• Reset the CPU module and RUN it again. If the
same error is displayed again, this suggests the
hardware fault of any of the CPU modules.
(Contact your local Mitsubishi representative.)
• Remove the CPU module incompatible with the
multiple CPU system from the main base unit.
Or, replace the CPU module incompatible with
the multiple CPU system with the compatible
one.

[MULTI CPU DOWN]
• There is no response from the target CPU
module in a multiple CPU system during initial
communication.
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

• Reset the CPU module and RUN it again. If the
same error is displayed again, this suggests the
hardware fault of any of the CPU modules.
(Contact your local Mitsubishi representative.)

The function version is B or later.
The Universal model QCPU except the Q00UJCPU.

12-78

Reset the CPU module and RUN it again. If the
same error is displayed again, this suggests the
hardware fault of any of the CPU modules. (Contact
your local Mitsubishi representative.)

Corresponding
CPU

Q00/Q01*1
Qn(H)*1
QnPH
QnU*6

Q00/Q01*1

Read the individual information of the error using
GX Developer, identify the error of the CPU
module, and remove the error.

[MULTI CPU DOWN]
• There is no response from the target CPU
module in a multiple CPU system during initial
communication.
• In a multiple CPU system, a CPU module
incompatible with the multiple CPU system was
mounted.
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

[MULTI CPU DOWN]
There is no response from the target CPU module
in a multiple CPU system at initial communication
stage.
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

LED Status
CPU Status

Qn(H)*1
QnPH
QnU*6

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

Q00/Q01*1
Qn(H)*1
QnPH

QnU*6

Q00/Q01*1
Qn(H)*1
QnPH

Error
Code
(SD0)

7004

Error Contents and Cause

Corrective Action

[MULTI CPU DOWN]
In a multiple CPU system, a data error occurred in
communication between the CPU modules.
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• Always

• Check the system configuration to see if modules
are mounted in excess of the number of I/O
points.
• When there are no problems in the system
configuration, this indicates the CPU module
hardware is faulty. (Contact your local Mitsubishi
representative, explaining a detailed description
of the problem.)

[MULTI EXE. ERROR]
• In a multiple CPU system, a faulty CPU module
was mounted.
• In a multiple CPU system, a CPU module
incompatible with the multiple CPU system was
mounted. (The CPU module compatible with the
multiple CPU system was used to detect an
error.)
• In a multiple CPU system, any of the CPU No. 2
to 4 was reset with power ON. (The CPU whose
reset state was cancelled was used to detect an
error.)
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

7010

• Read the individual information of the error using
GX Developer, and replace the faulty CPU
module.
• Replace the CPU module with the one
compatible with the multiple CPU system.
• Do not reset any of the No. 2 to 4 CPU modules.
• Reset CPU No. 1 and restart the multiple CPU
system.

[MULTI EXE. ERROR]
The Universal model QCPU (except Q02UCPU)
and Q172(H)CPU(N) are mounted on the same
base unit. (This may result in a module failure.)
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

*1
*4
*6

Q00/Q01*1
QnU*6

2

CPU Status:
Stop

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

Q00/Q01*1
Qn(H)*1
QnPH
QnU*6

12
6

Change the version of the PC CPU modulecompatible software package (PPC-DRV-01)*5 to
1.07 or later.

RUN:
Off
ERR.:
Flicker

7
Q00/Q01*1

8

CPU Status:
Stop

Replace the Q172(H)CPU(N) and Q173(H)CPU(N)
with the Motion CPU compatible with the multiple
CPU high-speed main base unit.

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

Qn(H)*4
QnPH*4

Check the QCPU and Motion CPU that can be
used in a multiple CPU system, and change the
system configuration.

RUN:
Off
ERR.:
Flicker
CPU Status:
Stop

The function version is B or later.
The module whose first 5 digits of serial No. is "09082" or later.
The Universal model QCPU except the Q00UJCPU.

12-79

12.1 Error Code List
12.1.9 Error code list (7000 to 10000)

failure.)
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

1

6

[MULTI EXE. ERROR]
The Q172(H)CPU(N) or Q173(H)CPU(N) is
mounted on the multiple CPU high-speed main
base unit (Q3 DB). (This may result in a module

RUN:
Off
ERR.:
Flicker

Corresponding
CPU

3

[MULTI EXE. ERROR]
The PC CPU module-compatible software package
(PPC-DRV-01)*5 whose version is 1.06 or earlier is
used in a multiple CPU system.
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

LED Status
CPU Status

Error
Code
(SD0)

Error Contents and Cause
[MULTI EXE. ERROR]
Either of the following settings was made in a
multiple CPU system.
• Multiple CPU automatic refresh setting was
made for the inapplicable CPU module.
• "I/O sharing when using multiple CPUs" setting
was made for the inapplicable CPU module.
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

• Correct the multiple CPU automatic refresh
setting.
• Correct the "I/O sharing when using multiple
CPUs" setting.

LED Status
CPU Status

RUN:
Off
ERR.:
Flicker

Corresponding
CPU

Q00/Q01*1
QnU*6

CPU Status:
Stop

[MULTI EXE. ERROR]
The system configuration for using the Multiple
CPU high speed transmission function is not met.
• The QnUCPU is not used for the CPU No.1.
• The Multiple CPU high speed main base unit

7011

(Q3 DB) is not used.
• Points other than 0 is set to the send range for
the CPU module incompatible with the multiple
CPU high speed transmission function.
• Points other than 0 is set to the send range for
the CPU module incompatible with the multiple
CPU.
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset
[MULTI EXE. ERROR]
The Q172(H)CPU(N) or Q173(H)CPU(N) is
mounted to the CPU slot or slots 0 to 2. (The
module may break down.)
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

7013

[MULTI CPU ERROR]
In the operating mode of a multiple CPU system, an
error occurred in the CPU where "system stop" was
not selected.
(The CPU module where no error occurred was
used to detect an error.)
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• Always

7020

[CPU LAY. ERROR]
An assignment error occurred in the CPUmountable slot (CPU slot, I/O slot 0, 1) in excess of
the number of CPU modules specified in the
multiple CPU setting of the PLC parameter dialog
box.
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

7030

*1
*3
*6

Corrective Action

• Change the system configuration to meet the
conditions for using the Multiple CPU high speed
transmission function.
• Set the send range of CPU, that does not
correspond to multiple CPU compatible area, at 0
point, when performing automatic refreshing in
multiple CPU compatible area.

• Check the QCPU and Motion CPU that can be
used in a multiple CPU system, and change the
system configuration.
• Remove the Motion CPU incompatible with the
multiple CPU system.

Read the individual information of the error using
the peripheral device, check the error of the CPU
module resulting in CPU module fault, and remove
the error.

QnU*3

CPU Status:
Stop

RUN:
Off
ERR.:
Flicker

QnU

CPU Status:
Stop

RUN:
On
ERR.:
On
CPU Status:
Continue

• Set the same value to the number of CPU
RUN:
modules specified in the multiple CPU setting of
Off
the PLC parameter dialog box and the number of ERR.:
mounted CPU modules (including CPU (empty)).
Flicker
• Make the type specified in the I/O assignment
setting of the PLC parameter dialog box
CPU Status:
consistent with the CPU module configuration.
Stop

The function version is B or later.
The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
The Universal model QCPU except the Q00UJCPU.

12-80

RUN:
Off
ERR.:
Flicker

Q00/Q01*1
Qn(H)*1
QnPH
QnU*6

Q00J/Q01/Q01*1
QnU

Error
Code
(SD0)

Error Contents and Cause

7031

[CPU LAY. ERROR]
An assignment error occurred within the range of
the number of CPUs specified in the multiple CPU
setting of the PLC parameter dialog box.
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

7032

[CPU LAY. ERROR]
• The number of CPU modules mounted in a
multiple CPU system is wrong.
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

7035

7036

8031

[CPU LAY. ERROR]
The CPU module has been mounted on the
inapplicable slot.
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

Corrective Action

LED Status
CPU Status

• Set the same value to the number of CPU
RUN:
modules specified in the multiple CPU setting of
Off
the PLC parameter dialog box and the number of ERR.:
mounted CPU modules (including CPU (empty)).
Flicker
• Make the type specified in the I/O assignment
setting of the PLC parameter dialog box
CPU Status:
consistent with the CPU module configuration.
Stop

Configure a system so that the number of
mountable modules of each CPU module does not
exceed the maximum number of mountable
modules specified in the specification.

Mount the CPU module on the applicable slot.

RUN:
Off
ERR.:
Flicker

Corresponding
CPU

1
Q00J/Q01/Q01*1
QnU

3
Q00/Q01

*1

QnU*6

12

CPU Status:
Stop
RUN:
Off
ERR.:
Flicker

Q00J/Q00/Q01*1
QnPRH
QnU

CPU Status:
Stop
• Mount the mounting slot of the CPU module
correctly.
• Correct the host CPU No. set by the multiple
CPU setting to the CPU No. determined by the
mounting position of the CPU module.

[INCORRECT FILE]
The error of stored file (enabled parameter file) is
detected.
■Collateral information
• Common Information:–
• Individual Information:File diagnostic information
■Diagnostic Timing
• At power-On/
• At reset/
• STOP
RUN/At writing to progurammable
controller

Write the file shown as SD17 to SD22 of individual
information to the drive shown as SD16(L) of
individual information, and turn ON from OFF the
power supply of the CPU module or cancel the
reset.
If the same error is displayed again, the CPU
module has hardware failure. Contact your local
Mitsubishi representative, explaining a detailed
description of the problem.

RUN:
Off
ERR.:
Flicker

6
QnU*3

RUN:
Off
ERR.:
Flicker

8
QnU

CPU Status:
Stop

9000

On/Off *2
Read the individual information of the error using
the peripheral device, and check the program
corresponding to the numerical value (annunciator
number).

CPU Status:
Continue

QCPU

RUN:
ERR.:
USER LED On
CPU Status:
Continue

*1
*3

7

CPU Status:
Stop

RUN:
On
ERR.:
[F**** ]
Annunciator (F) was set ON
■Collateral information
• Common Information:Program error location
• Individual Information:Annunciator number
■Diagnostic Timing
• When instruction executed

6

The function version is B or later.
The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.

12-81

12.1 Error Code List
12.1.9 Error code list (7000 to 10000)

[CPU RAY ERROR]
The host CPU No. set by the multiple CPU setting
and the host CPU No. determined by the mounting
position of the CPU module are not the same.
■Collateral information
• Common Information:Module No.(CPU No.)
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

2

Error
Code
(SD0)

[ERR ***-***]
Error detected by the CHK instruction.
■Collateral information
• Common Information:Program error location
• Individual Information:Failure No.
■Diagnostic Timing
• When instruction executed

9010

[BOOT OK]
Storage of data onto ROM was completed normally
in automatic write to standard ROM.
(BOOT LED also flickers.)
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• At power ON/At reset

9020

[CONT. UNIT ERROR]
In the multiple CPU system, an error occurred in
the CPU module other than the Process CPU/High
Performance model QCPU.
■Collateral information
• Common Information:–
• Individual Information:–
■Diagnostic Timing
• Always

10000

*1

Error Contents and Cause

The function version is B or later.

12-82

Corrective Action

Read the individual information of the error using
the peripheral device, and check the program
corresponding to the numerical value (error
number) there.

LED Status
CPU Status
RUN:
On
ERR.:
Off
USER LED On

Corresponding
CPU

Qn(H)
QnPH
QnPRH

CPU Status:
Continue

Use the DIP switches to set the valid parameter
drive to the standard ROM. Then, switch power on
again, and perform boot operation from the
standard ROM.

Check the details of the generated error by
connecting to the corresponding CPU module
using GX Developer.

RUN:
Off
ERR.:
Flicker

Qn(H)*1
QnPH
QnPRH

CPU Status:
Stop

RUN:
Off
ERR.:
Flicker
CPU Status:
Continue

Qn(H)*1
QnPH

12.2 Canceling of Errors
1
Q series CPU module can perform the cancel operation for errors only when the errors allow
the CPU module to continue its operation.
To cancel the errors, follow the steps shown below.
1) Eliminate the cause of the error.
2) Store the error code to be canceled in the special register SD50.
3) Energize the special relay SM50 (OFF ON).
4) The error to be canceled is canceled.

2
3

After the CPU module is reset by the canceling of the error, the special relays, special
registers, and LEDs associated with the error are returned to the status under which the
error occurred.
If the same error occurs again after the cancellation of the error, it will be registered again in
the error history.
When multiple enunciators(F) detected are canceled, the first one with No. F only is
canceled.

12
6
6

Refer to the following manual for details of error canceling.
QCPU User's Manual (Function Explanation, Program Fundamentals)

7
8

12-83

12.2 Canceling of Errors

(1) When the error is canceled with the error code to be canceled stored in the
SD50, the lower one digit of the code is neglected.
(Example)
If error codes 2100 and 2101 occur, and error code 2100 to cancel error code
2101.
If error codes 2100 and 2111 occur, error code 2111 is not canceled even if
error code 2100 is canceled.
(2) Errors developed due to trouble in other than the CPU module are not
canceled even if the special relay (SM50) and special register (SD50) are
used to cancel the error.
(Example)
Since "SP. UNIT DOWN" is the error that occurred in the base unit (including
the extension cable), intelligent function module, etc. the error cause cannot
be removed even if the error is canceled by the special relay (SM50) and
special register (SD50).
Refer to the error code list and remove the error cause.

MEMO

12-84

A

8

APPENDICES

8
8
8
A
8
8
8

App-1

Appendix 1 OPERATION PROCESSING TIME
Appendix 1.1 Definition
(1) Processing time taken by the QCPU is the total of the following processing times.
• Total of each instruction processing time
• END processing time (including I/O refresh time)
• Processing time for the function that increases the scan time
(2) Instruction processing time
This is the total of processing time of each instruction shown in Appendix 1.2, 1.3 and 1.4.
(3) END processing time, I/O refresh time, and processing time for the function that increases
the scan time
Refer to the following manual(s) for the END processing time, I/O refresh time, and
processing time for the function that increases the scan time.
(a) For QCPUs
• QnUCPU User's Manual (Functions Explanation, Program Fundamentals)
• Qn(H)/QnPH/QnPRHCPU User's Manual
(Functions Explanation, Program Fundamentals)

App-2

Appendix 1.2 Operation Processing Time of Basic Model
QCPU

8

The processing time for the individual instructions are shown in the table on the following pages.
Operation processing times can vary substantially depending on the nature of the sources and
destinations of the instructions, and the values contained in the following tables should therefore
be taken as a set of general guidelines to processing time rather than as being strictly accurate.
(1) Sequence instructions
Instruction

Q00JCPU

Q00CPU

Q01CPU

X0

0.20

0.16

0.10

A

D0.0

0.30

0.24

0.15

6

LD
LDI

8
8

Processing Time (µs)

Condition (Device)

8

AND
ANI
OR
ORI
LDP
LDF

7

X0

ANDP

0.30

ANDF
ORP

0.24

0.15

8

D0.0

ORF
ANB
ORB
––

0.20

0.16

0.10

0.20

0.16

0.10

0.30

0.24

0.15

0.20

0.16

0.10

17

9.5

9.4

18

14

14

Appendix1 OPERATION PROCESSING TIME
Appendix 1.2 Operation Processing Time of Basic Model QCPU

MPS
MRD
MPP
INV

When not executed
When executed

MEP

When not executed

MEF

When executed
When not executed

EGP

When executed

When not executed
EGF

When executed

(OFF

OFF)

(ON

ON)

(OFF

ON)

(ON

OFF)

(OFF

OFF)

(ON

ON)

(OFF

ON)

(ON

OFF)

App-3

Instruction

Y

D0.0

OUT

Processing Time (µs)

Condition (Device)
When not

(OFF

OFF)

changed

(ON

ON)

When

(OFF

ON)

changed

(ON

OFF)

When not

(OFF

OFF)

changed

(ON

ON)

When

(OFF

ON)

changed

(ON

OFF)

When OFF
F

App-4

20

19

0.55

1.1

0.88

0.55

When

K

When added

D

After time up

When

When added

When

When added

When

When not changed (ON

executed

When changed (OFF

When changed (OFF

0.96

0.60

0.88

0.55

1.1

0.88

0.55

1.1

0.88

0.55

D

1.2

0.96

0.60

1.1

0.88

0.55

1.1

0.88

0.55

K

1.1

0.88

0.55

D

1.2

0.96

0.60

0.20

0.16

0.10

0.20

0.16

0.10

0.20

0.16

0.10

0.40

0.32

0.20

0.40

0.32

0.20

ON)
ON)

When not changed (ON

When

1.2
1.1

K

After time up

ON)
ON)

0.40

0.32

0.20

0.50

0.44

0.25

When

When displayed

255

205

195

executed

Display completed

195

160

150

0.20

0.16

0.10

0.20

0.16

0.10

When not changed (OFF

When

When changed (ON

OFF)
OFF)

When not changed (ON

When

When changed (OFF

ON)
ON)

0.20

0.16

0.10

0.40

0.32

0.20

0.40

0.32

0.20

0.40

0.32

0.20

When not executed

0.20

0.16

0.10

When executed

0.20

0.16

0.10

When not executed

0.48

0.44

0.25

75

69

65

When displayed

When
executed

R

24

0.55

SM

Z

0.20

0.88

executed

D

0.32

0.88

When not executed

T, C

0.40

1.1

executed

F

0.20

1.1

After time up

When not executed

RST

0.32

200

When not executed

D0.0

0.40

155

executed

Y

0.10

210

When not executed

F

0.16

165

When not executed

D0.0

0.20

260

executed

SET

0.10

205

When not executed

Y

0.16

When displayed

executed

T

0.20

Display completed

When not executed

OUTH

Q01CPU

ON

executed

C

Q00CPU

When

When not executed
T

Q00JCPU

Display completed

When not executed

43

35

33

0.80

0.64

0.40

When executed

1.0

0.80

0.50

When not executed

0.40

0.32

0.20

When executed

0.60

0.48

0.30

When not executed

0.50

0.40

0.25

When executed

9.4

7.9

7.4

When not executed

––

0.32

0.20

When executed

––

0.48

0.30

Instruction

Condition (Device)

Processing Time (µs)
Q00JCPU

Q00CPU

Q01CPU

PLS

12

9.5

9.2

PLF

11

9.5

8.9

When not executed

0.68

0.40

0.25

When executed

7.5

6.2

5.7

When not executed

0.50

0.40

0.25

When executed

26

21

21

When not executed

0.48

0.40

0.25

Y

FF

DY0

DELTA

DY0

DELTAP
SFT
SFTP

When executed

58

45

43

When not executed

0.50

0.34

0.25

When executed

12

8.7

8.3
0.20

M0

0.40

0.32

D0.0

3.3

2.9

2.8

––

0.20

0.16

0.10

Error check performed

660

600

520

660

600

520

––

0.20

0.16

0.10

––

0.20

0.16

0.10

MC
MCR

8
8
8
8
A

No error check performed

FEND

(• Battery check)

END

(• Fuse blown check)

6

(• I/O module verification)
NOP
NOPLF
PAGE

8

(2) Basic instructions

LD =

AND =

Condition (Device)

Q00JCPU

Q00CPU

In conductive status

0.80

0.64

0.40

In non-conductive status

0.80

0.64

0.40

When not executed
When executed

LD < >

AND < >

When executed

Q01CPU

0.70

0.56

0.35

In conductive status

0.80

0.64

0.40

In non-conductive status

0.80

0.64

0.40

When not executed
OR =

Processing Time (µs)

0.70

0.56

0.35

In conductive status

0.80

0.64

0.40

In non-conductive status

0.80

0.64

0.40

In conductive status

0.80

0.64

0.40

In non-conductive status

0.80

0.64

0.40

When not executed

0.70

0.56

0.35

When executed

In conductive status

0.80

0.64

0.40

In non-conductive status

0.80

0.64

0.40

App-5

Appendix1 OPERATION PROCESSING TIME
Appendix 1.2 Operation Processing Time of Basic Model QCPU

The processing time when the instruction is not executed is calculated as follows:
Q00JCPU ··················································· 0.20 (No. of steps for each instruction + 1) µs
Q00CPU ····················································· 0.16 (No. of steps for each instruction + 1) µs
Q01CPU ····················································· 0.10 (No. of steps for each instruction + 1) µs
Instruction

7

Instruction

Condition (Device)

Q00JCPU

Q00CPU

Q01CPU

0.70

0.56

0.35

In conductive status

0.80

0.64

0.40

In non-conductive status

0.80

0.64

0.40

When not executed
OR < >

LD >

When executed

In conductive status

0.80

0.64

0.40

In non-conductive status

0.80

0.64

0.40

0.70

0.56

0.35

0.80

0.64

0.40

When not executed
AND >

When executed

In conductive status
In non-conductive status

0.80

0.64

0.40

0.70

0.56

0.35

In conductive status

0.80

0.64

0.40

In non-conductive status

0.80

0.64

0.40

When not executed
OR >

LD < =

When executed

In conductive status

0.80

0.64

0.40

In non-conductive status

0.80

0.64

0.40

0.70

0.56

0.35

0.80

0.64

0.40

When not executed
AND < =

When executed

In conductive status
In non-conductive status

0.80

0.64

0.40

0.70

0.56

0.35

In conductive status

0.80

0.64

0.40

In non-conductive status

0.80

0.64

0.40

When not executed
OR < =

LD <

When executed

In conductive status

0.80

0.64

0.40

In non-conductive status

0.80

0.64

0.40

0.70

0.56

0.35

0.80

0.64

0.40

When not executed
AND <

When executed

In conductive status
In non-conductive status

0.80

0.64

0.40

0.70

0.56

0.35

In conductive status

0.80

0.64

0.40

In non-conductive status

0.80

0.64

0.40

When not executed
OR <

LD > =

When executed

In conductive status

0.80

0.64

0.40

In non-conductive status

0.80

0.64

0.40

0.70

0.56

0.35

0.80

0.64

0.40

When not executed
AND > =

When executed

In conductive status
In non-conductive status

0.80

0.64

0.40

0.70

0.56

0.35

In conductive status

0.80

0.64

0.40

In non-conductive status

0.80

0.64

0.40

When not executed
OR > =

LDD =

ANDD =

When executed

In conductive status

1.0

0.80

0.50

In non-conductive status

1.0

0.80

0.50

When not executed

0.80

0.64

0.40

1.0

0.80

0.50

1.0

0.80

0.50

0.80

0.64

0.40

When executed

In conductive status
In non-conductive status

When not executed
ORD =

LDD < >

ANDD < >

App-6

Processing Time (µs)

When executed

In conductive status

1.0

0.80

0.50

In non-conductive status

1.0

0.80

0.50

In conductive status

1.0

0.80

0.50

In non-conductive status

1.0

0.80

0.50

When not executed
When executed

0.80

0.64

0.40

In conductive status

1.0

0.80

0.50

In non-conductive status

1.0

0.80

0.50

Instruction

Condition (Device)
When not executed

ORD < >

ANDD >

0.80

0.50

0.80

0.50

In conductive status

1.0

0.80

0.50

In non-conductive status

1.0

0.80

0.50

When not executed

0.80

0.64

0.40

1.0

0.80

0.50

In conductive status
In non-conductive status

1.0

0.80

0.50

0.80

0.64

0.40

In conductive status

1.0

0.80

0.50

In non-conductive status

1.0

0.80

0.50

In conductive status

1.0

0.80

0.50

In non-conductive status

1.0

0.80

0.50

When not executed
When executed

0.80

0.64

0.40

In conductive status

1.0

0.80

0.50

In non-conductive status

1.0

0.80

0.50

0.80

0.64

0.40

When not executed
ORD < =

When executed

LDD <

ANDD <

In conductive status

1.0

0.80

0.50

In non-conductive status

1.0

0.80

0.50

In conductive status

1.0

0.80

0.50

In non-conductive status

1.0

0.80

0.50

When not executed

0.80

0.64

0.40

When executed

In conductive status

1.0

0.80

0.50

In non-conductive status

1.0

0.80

0.50

0.80

0.64

0.40

When not executed
When executed

In conductive status

1.0

0.80

0.50

In non-conductive status

1.0

0.80

0.50

1.0

0.80

0.50

In conductive status

LDD > =

ANDD > =

In non-conductive status

1.0

0.80

0.50

When not executed

0.80

0.64

0.40

When executed

In conductive status

1.0

0.80

0.50

In non-conductive status

1.0

0.80

0.50

0.80

0.64

0.40

In conductive status

1.0

0.80

0.50

In non-conductive status

1.0

0.80

0.50

n=1

130

105

97

n = 96

205

175

165

n=1

130

105

98

n = 96

210

180

165

n=1

130

105

97

When not executed
ORD > =

When executed

BKCMP = S1 S2

n

D

BKCMP = P S1 S2
BKCMP<> S1 S2

n

D

n

D

BKCMP<>P S1 S2

D

BKCMP> S1 S2

n

D

n

BKCMP>P S1 S2

D

n

n = 96

210

180

165

BKCMP>= S1 S2

D

n

n=1

130

105

98

n = 96

205

175

165

BKCMP>=P S1 S2

D

n

App-7

8
8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.2 Operation Processing Time of Basic Model QCPU

ORD <

0.40

1.0

When executed

ANDD < =

Q01CPU

0.64

1.0

When not executed

LDD < =

Q00CPU

0.80

In conductive status

When executed

ORD >

Q00JCPU

In non-conductive status

When executed

LDD >

Processing Time (µs)

Instruction
BKCMP< S1 S2

Condition (Device)
n

D

Processing Time (µs)
Q00JCPU

Q00CPU

Q01CPU

n=1

130

105

98

BKCMP


ANDE < >

Single precision

Single precision

Single precision

When executed

When executed

When not executed
ORE < >

LDE >

ANDE >

Single precision

Single precision

Single precision

When executed

When executed

When not executed
Single precision

LDE < =

Single precision

ANDE < =

Single precision

1.5

1.2

1.0

In conductive status

45.0

37.5

34.5

In non-conductive status

37.0

31.0

29.0

In conductive status

45.5

37.5

35.0

In non-conductive status

46.5

38.5

35.5

When executed

When not executed
When executed

1.5

1.2

1.0

In conductive status

38.5

31.5

29.0

In non-conductive status

42.5

35.5

32.5

1.5

1.2

1.0

In conductive status

45.0

37.5

34.5

In non-conductive status

When not executed
ORE < =

Single precision

LDE <

Single precision

ANDE <

Single precision

When executed

37.5

31.5

28.5

In conductive status

45.5

37.5

35.0

In non-conductive status

46.5

38.5

35.5

When not executed

1.5

1.2

1.0

In conductive status

38.0

31.5

29.0

In non-conductive status

42.5

35.5

32.5

1.5

1.2

1.0

In conductive status

45.0

37.5

34.5

In non-conductive status

37.5

31.5

29.0

In conductive status

45.5

38.0

35.5

In non-conductive status

46.5

38.0

35.0

When not executed

1.5

1.2

1.0

In conductive status

38.5

32.0

29.0

In non-conductive status

42.5

35.5

32.5

When executed

When not executed
ORE <

LDE > =

ANDE > =

Single precision

Single precision

Single precision

When executed

When executed

App-17

8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.2 Operation Processing Time of Basic Model QCPU

ORE >

8

Instruction

Condition (Device)

Q00JCPU

Q00CPU

Q01CPU

1.5

1.2

1.0

In conductive status

45.0

38.5

34.5

In non-conductive status

37.5

31.0

28.5

When not executed
Single precision

ORE > =

E+ S

D

E+P S

Single precision
D

E+ S1 S2 D

Single precision

E+P S1 S2 D
E- S

D

E -P S

Single precision
D

E - S1 S2

D

E -P S1 S2
E* S1 S2

D
D

E*P S1 S2
E/ S1 S2
E/P S1 S2
INT
INTP
DINT
DINTP
FLT
FLTP
DFLT
DFLTP
ENEG

Single precision

Single precision
D

D

Single precision
D

Single precision

Single precision

Single precision

Single precision

EMOVP
ESTR
ESTRP
EVAL
EVALP

App-18

S

= 0, D = 0

29.5

25.0

23.0

S

= 2127, D = 2127

65.5

60.5

49.5

S1

= 0, S2 = 0

31.0

27.0

24.0

S1

= 2127, S2 = 2127

66.5

56.0

51.0

S

= 0, D = 0

29.5

25.0

23.0

S

= 2127, D = 2127

48.5

41.0

37.5

S1

= 0, S2 = 0

31.0

27.0

24.0

S1

= 2127, S2 = 2127

50.5

42.5

38.5

S1

= 0, S2 = 0

30.0

25.5

23.0

S1

= 2127, S2 = 2127

65.5

55.0

49.5

S1

= 0, S2 = 1

30.0

26.0

23.0

S1

= 2127, S2 = - 2126

69.5

57.5

53.0

S

=0

21.5

18.5

16.0

S

= 32766.5

38.0

32.0

29.5

S

=0

23.0

19.5

17.5

S

= 1234567890.3

42.0

35.5

32.0

S

=0

22.5

19.5

17.0

S

= 7FFFH

26.5

23.0

20.0

S

=0

23.0

20.0

17.5

S

= 7FFFFFFFH

26.0

23.5

19.5

S

=0

20.5

17.0

15.5

S

= E - 1.0

31.5

26.0

24.0

––

1.5

1.2

1.0

––

604.0

686.0

831.0

Decimal point format all 2-digit specification

138.0

148.0

196.0

Exponent format all 6-digit specification

164.0

177.0

214.0

ENEGP
EMOV

When executed

Processing Time (µs)

Instruction
SIN
SINP
COS
COSP
TAN
TANP
RAD
RADP
DEG
DEGP
SQR
SQRP
EXP
EXPP
LOG
LOGP

Q00JCPU

Q00CPU

Q01CPU

Single precision

204.0

173.0

157.0

Single precision

187.0

158.0

144.0

Single precision

224.0

190.0

173.0

Single precision

51.0

43.0

39.0

Single precision

51.0

43.0

39.0

Single precision

60.0

51.0

46.5

= - 10

306.0

259.0

235.0

S

=1

306.0

259.0

235.0

S

=1

73.0

61.5

56.0

= 10

301.0

255.0

232.0

––

12.5

11.0

10.0

––

13.5

12.0

11.0

S

Single precision

Single precision

S

RND
RNDP
SRND
SRNDP

Processing Time (µs)

Condition (Device)

8
8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.2 Operation Processing Time of Basic Model QCPU

App-19

Instruction

Condition/Number of Points Processed

Name

COM *2

––

920

880

––

––

150

135

n3 = 1

––

100

90

(0.5k words assigned equally to all CPUs)

memory of host CPU

n3 = 320

––

440

420

Read from CPU shared

n3 = 1

––

110

105

memory of another CPU

n3 = 320

––

305

290

n3 = 1

––

100

95

n3 = 320

––

440

425

n4 = 1

––

205

195

n4 = 320

––

545

525

Write to CPU shared memory
of host CPU
Write to CPU shared memory

S.TO

Q01CPU

shared memory

Read from CPU shared

TO

Q00CPU

Refresh range: 2k words

shared memory

FROM

Q00JCPU

With auto refresh of CPU
Without auto refresh of CPU

Processing Time (µs)

of host CPU

*2: If the processing overlaps those of the other CPUs in a multiple CPU system, the processing time increases
by a maximum of the following time.

For a system having only the main base unit
(Instruction processing time increase) = 4 0.54
processed) (number of other CPUs) (µs)

(number of points

For a system including extension base units
(Instruction processing time increase) = 4 1.30
processed) (number of other CPUs) (µs)

(number of points

(6) Table of the time to be added when file register, module access device or link direct device is
used
Instruction Name

data

Bit
Word

File register (ZR)

(Un\G

, U3En\G0 to G511)

App-20

)

Q00CPU

Q01CPU

Source

––

34

32

Destination

––

23

22

Source

––

13

12

Destination

––

9

8

Source

––

14

13

word

Destination

––

10

9

Source

99

82

77

Destination

167

137

129

Source

74

61

58

Destination

72

60

56

Double

Source

76

63

59

word

Destination

92

75

71

Source

178

147

137

Destination

303

248

233

Source

154

126

118

Destination

153

125

117

Double

Source

155

127

119

word

Destination

163

133

125

Word

Bit

Link direct device (Jn\

Location

Q00JCPU

Double

Bit
Module access device

Processing Time (µs)

Device Specification

Word

Appendix 1.3 Operation Processing Time of High Performance
Model QCPU/Process CPU/Redundant CPU

8

The processing time for the individual instructions are shown in the table on the following pages.
Operation processing time can vary substantially depending on the nature of the sources and
destinations of the instructions, and the values contained in the following tables should therefore
be taken as a set of general guidelines to processing times rather than as being strictly accurate.

Processing Time (µs)

Condition (Device)

Qn

QnH

QnPH

QnPRH

0.079

0.034

0.034

0.034

LD
LDI
AND

––

ANI

8
8

(1) Sequence instructions
Instruction

8

OR

A
6

ORI
LDP

7

LDF
ANDP

0.158

––

ANDF

0.068

0.068

0.068

ORP

8

ORF
ANB
ORB
MPS

––

0.034

0.034

0.034

0.079

0.034

0.034

0.034

0.173

0.073

0.073

0.073

0.158

0.068

0.068

0.068

MPP
INV

When not executed
When executed

MEP

When not executed

MEF

When executed

EGP
EGF

When not executed

When executed

(OFF

OFF)

(ON

ON)

(OFF

ON)

(ON

OFF)

App-21

Appendix1 OPERATION PROCESSING TIME
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU

0.079

MRD

Instruction

Processing Time (µs)

Condition (Device)

When not changed

When changed

(OFF

OFF)

(ON

ON)

(OFF

ON)

(ON

OFF)

When OFF
F

When

When added

When added

DELTA
DELTAP

When

App-22

When
executed

When added

When not changed (ON
When changed (OFF

ON)
ON)

When displayed
Display completed

When not changed (OFF
When changed (ON

0.27

0.27

0.27

0.27

0.27

K

0.63

0.27

0.27

0.27

D

0.63

0.27

0.27

0.27

0.63

0.27

0.27

0.27

0.63

0.27

0.27

0.27

K

0.63

0.27

0.27

0.27

D

0.63

0.27

0.27

0.27

0.63

0.27

0.27

0.27

0.63

0.27

0.27

0.27

K

0.63

0.27

0.27

0.27

D

0.63

0.27

0.27

0.27

OFF)
OFF)

0.158

0.068

0.068

0.068

0.158

0.068

0.068

0.068

0.158

0.068

0.068

0.068

0.47

0.20

0.20

0.20

161

69

69

69

0.47

0.20

0.20

0.20

0.158

0.068

0.068

0.068

0.158

0.068

0.068

0.068

0.158

0.068

0.068

0.068

When not executed

0.158

0.068

0.068

0.068

When executed

0.158

0.068

0.068

0.068

When not executed

0.47

0.20

0.20

0.20

When displayed

90

38

38

38

Display completed

0.47

0.20

0.20

0.20

When not executed

0.63

0.27

0.27

0.27

When executed

0.63

0.27

0.27

0.27

When not executed

0.24

0.10

0.10

0.10

When executed

0.24

0.10

0.10

0.10

When not executed

0.47

0.20

0.20

0.20

When executed

4.3

1.9

1.9

1.9

When not executed

0.40

0.17

0.17

0.17

When executed

0.40

0.17

0.17

0.17

1.0

0.44

0.44

0.44

––

DY0

1.2

0.27

After time up

When

SM

Y

1.2

0.63

After time up

When

When executed

FF

1.2

0.63

After time up

When not executed

PLF

2.8

54

executed

PLS

0.068

69.7

When not executed

R

0.068

54

SET

Z

0.068

69.7

When executed

D

0.158

54

When not executed

T, C

0.068

69.7

executed

RST

0.068

162

When not executed

F

0.068

126

executed

F

0.158

When displayed

When not executed

T

QnPRH

Display completed

executed

OUTH

QnPH

ON

When not executed

C

QnH

When

OUT

T

Qn

When not executed

0.47

0.20

0.20

0.20

When executed

0.47

0.20

0.20

0.20

When not executed

0.47

0.20

0.20

0.20

When executed

5.9

2.6

2.6

2.6

Instruction
SFT
SFTP

Condition (Device)

Processing Time (µs)
Qn

QnH

QnPH

QnPRH

When not executed

0.47

0.20

0.20

0.20

When executed

1.66

0.71

0.71

0.71

MC

––

0.24

0.10

0.10

0.10

MCR

––

0.079

0.034

0.034

0.034

Error check performed

380

150

150

500

380

150

150

500

––

0.079

0.034

0.034

0.034

––

0.079

0.034

0.034

0.034

FEND
END

(• Fuse blown check)
(• I/O module verification)

NOP
NOPLF
PAGE

8
8

No error check performed
(• Battery check)

8

8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU

App-23

(2) Basic instructions
The processing time when the instruction is not executed is calculated as follows:
Q02CPU ·····················································0.079 (No. of steps for each instruction + 1) µs
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU, Q02PHCPU, Q06PHCPU, Q12PHCPU,
Q25PHCPU, Q12PRHCPU, Q25PRHCPU 0.034 (No. of steps for each instruction + 1) µs

Instruction
LD =

AND =

Condition (Device)
In conductive status

LD < >

AND < >

LD >

AND >

LD < =

AND < =

App-24

QnPH

QnPRH

0.10

0.10

0.10

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

When

In conductive status

0.24

0.10

0.10

0.10

executed

In non-conductive status

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status

0.24

0.10

0.10

0.10

When not executed

0.24

0.10

0.10

0.10

In conductive status

0.24

0.10

0.10

0.10

In non-conductive status

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

When executed

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status

0.24

0.10

0.10

0.10

When not executed

0.24

0.10

0.10

0.10

In conductive status

0.24

0.10

0.10

0.10

In non-conductive status

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

When executed

When not executed
OR >

QnH

When not executed

When not executed
OR < >

Qn
0.24

In non-conductive status

When not executed
OR =

Processing Time (µs)

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status

0.24

0.10

0.10

0.10

When not executed

0.24

0.10

0.10

0.10

In conductive status

0.24

0.10

0.10

0.10

In non-conductive status

0.24

0.10

0.10

0.10

When executed

Instruction

Condition (Device)

Qn

QnH

QnPH

QnPRH

0.24

0.10

0.10

0.10

In conductive status

0.24

0.10

0.10

0.10

In non-conductive status

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

When not executed
OR < =

LD <

AND <

When executed

In conductive status
In non-conductive status

0.24

0.10

0.10

0.10

When not executed

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

When executed

In conductive status
In non-conductive status

When not executed
OR <

LD > =

AND > =

When executed

In conductive status

LDD =

ANDD =

ANDD < >

LDD >

ANDD >

LDD < =

ANDD < =

0.10

0.10

0.10

0.10

0.10

0.10

In non-conductive status

0.24

0.10

0.10

0.10

When not executed

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

In conductive status
In non-conductive status

When executed

In conductive status

0.10

0.10

0.10

0.10

0.10

0.10

0.24

0.10

0.10

0.10

0.24

0.10

0.10

0.10

0.55

0.24

0.24

0.24

In non-conductive status

0.39

0.17

0.17

0.17

When not executed
When executed

In non-conductive status

0.24
0.24

In conductive status

0.39

0.17

0.17

0.17

In conductive status

0.55

0.24

0.24

0.24

In non-conductive status

0.39

0.17

0.17

0.17

0.39

0.17

0.17

0.17

0.55

0.24

0.24

When executed

0.24

In conductive status

0.55

0.24

0.24

0.24

In conductive status

0.55

0.24

0.24

0.24

In non-conductive status

0.55

0.24

0.24

0.24

When not executed
When executed

In non-conductive status

0.39

0.17

0.17

0.17

In conductive status

0.55

0.24

0.24

0.24

In non-conductive status

0.55

0.24

0.24

0.24

When executed

0.39

0.17

0.17

0.17

In conductive status

0.55

0.24

0.24

0.24

In non-conductive status

0.55

0.24

0.24

0.24

In conductive status

0.55

0.24

0.24

0.24

In non-conductive status

0.55

0.24

0.24

0.24

When not executed

0.39

0.17

0.17

0.17

In conductive status

0.55

0.24

0.24

0.24

In non-conductive status

0.55

0.24

0.24

0.24

0.39

0.17

0.17

0.17

In conductive status

0.55

0.24

0.24

0.24

In non-conductive status

0.55

0.24

0.24

0.24

0.55

0.24

0.24

0.24

When executed

When executed

In conductive status
In non-conductive status

0.55

0.24

0.24

0.24

When not executed

0.39

0.17

0.17

0.17

In conductive status

0.55

0.24

0.24

0.24

In non-conductive status

0.55

0.24

0.24

0.24

0.39

0.17

0.17

0.17

In conductive status

0.55

0.24

0.24

0.24

In non-conductive status

0.55

0.24

0.24

0.24

When executed

When not executed
ORD < =

0.10
0.10

When not executed
ORD >

0.24

0.10

When not executed
ORD < >

0.10
0.10

When executed

App-25

8
8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU

LDD < >

0.10
0.10

0.24

When not executed
ORD =

0.10
0.10

0.24

When executed

In non-conductive status

0.24
0.24

In conductive status

When not executed
OR > =

Processing Time (µs)

Instruction

Condition (Device)
In conductive status

LDD <

ANDD <

0.24

0.24

0.24

0.17

0.17

In conductive status

0.55

0.24

0.24

0.24

In non-conductive status

0.55

0.24

0.24

0.24

0.39

0.17

0.17

0.17

0.55

0.24

0.24

0.24

0.55

0.24

0.24

0.24

0.55

0.24

0.24

0.24

In conductive status
In non-conductive status

In non-conductive status

0.55

0.24

0.24

0.24

When not executed

0.39

0.17

0.17

0.17

In conductive status

0.55

0.24

0.24

0.24

In non-conductive status

0.55

0.24

0.24

0.24

When executed

When executed

precision
LDE =

0.39

0.17

0.17

0.17

In conductive status

0.55

0.24

0.24

0.24

In non-conductive status

0.55

0.24

0.24

0.24

6.4

6.4

6.4

6.4

––

––

––

––

0.24

0.24

6.4

6.4

6.4

6.4

––

––

––

––

––

––

0.24

0.24

6.4

6.4

6.4

6.4

––

––

––

––

––

––

In conductive status
In non-conductive status

*1

Double
precision

In conductive status
In non-conductive status
When not executed

Single
precision
ANDE = *1

When
executed

In conductive status
In non-conductive status

When not executed
Double
precision

When
executed

In conductive status
In non-conductive status

When not executed
Single
precision
ORE = *1

Double

*1

App-26

When
executed

In conductive status
In non-conductive status

When not executed

precision

0.24

0.17

In conductive status

Single

QnPRH

0.24

0.55

When not executed
ORD > =

QnPH

0.24

0.39

When executed

ANDD > =

QnH

When not executed
When executed

LDD > =

Qn
0.55

In non-conductive status

When not executed
ORD <

Processing Time (µs)

When
executed

In conductive status
In non-conductive status

93

40

14.9

6.4

92

40

14.9

6.4

93

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

93

40

14.9

6.4

92

40

14.9

6.4

––

––

93

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

93

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

93

40

14.9

6.4

92

40

14.9

6.4

: The Qn/QnH changes in processing time depending on the serial No. of the CPU module.
Top
: The first 5 digits of the serial No. are "05031" or lower
Bottom : The first 5 digits of the serial No. are "05032" or higher
For the condition to be satisfied when the instruction is not executed, there is no differentiation between the
top and bottom.

Instruction

Condition (Device)

Single
precision

In conductive status
In non-conductive status

LDE<> *1

Double
precision

In conductive status
In non-conductive status
When not executed

Single
precision
ANDE<> *1

When
executed

In conductive status
In non-conductive status

When not executed
Double
precision

When
executed

In conductive status
In non-conductive status

When not executed
Single
precision
ORE<> *1

When
executed

In conductive status
In non-conductive status

When not executed
Double
precision

When
executed

In conductive status
In non-conductive status

When not executed
precision

In conductive status

LDE> *1

Double
precision

In non-conductive status

When not executed
Single
precision
ANDE> *1

When
executed

In conductive status
In non-conductive status

When not executed
Double
precision

*1

When
executed

In conductive status
In non-conductive status

QnH

92

40

14.9

6.4

92

40

14.9

6.4

92

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

92

40

14.9

6.4

93

40

14.9

6.4

0.55

0.24

92

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

93

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

93

40

14.9

6.4

92

40

14.9

6.4

92

40

14.9

6.4

92

40

14.9

6.4

92

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

92

40

14.9

6.4

93

40

14.9

6.4

0.55

0.24

92

40

14.9

6.4

92

40

14.9

6.4

QnPH

QnPRH

6.4

6.4

6.4

6.4

––

––

––

––

0.24

0.24

6.4

6.4

6.4

6.4

––

––

––

––

––

––

0.24

0.24

6.4

6.4

6.4

6.4

––

––

––

––

––

––

6.4

6.4

6.4

6.4

––

––

––

––

0.24

0.24

6.4

6.4

6.4

6.4

––

––

––

––

––

––

: The Qn/QnH changes in processing time depending on the serial No. of the CPU module.
Top
: The first 5 digits of the serial No. are "05031" or lower
Bottom : The first 5 digits of the serial No. are "05032" or higher
For the condition to be satisfied when the instruction is not executed, there is no differentiation between the
top and bottom.

App-27

8
8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU

Single

Processing Time (µs)
Qn

Instruction

Condition (Device)
When not executed
Single
precision

ORE> *1

When
executed

In conductive status
In non-conductive status

When not executed
Double
precision

Single
precision

When
executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status

LDE<= *1

Double
precision

In conductive status
In non-conductive status
When not executed

Single
precision
ANDE<= *1

When
executed

In conductive status
In non-conductive status

When not executed
Double
precision

When
executed

In conductive status
In non-conductive status

When not executed
Single
precision
ORE<= *1

When
executed

In conductive status
In non-conductive status

When not executed
Double
precision

Single
precision

When
executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status

LDE< *1

Double
precision
*1

App-28

In conductive status
In non-conductive status

Processing Time (µs)
Qn

QnH

QnPH

QnPRH

0.55

0.24

0.24

0.24

93

40

14.9

6.4

6.4

6.4

6.4

6.4

––

––

––

––

––

––

6.4

6.4

6.4

6.4

––

––

––

––

0.24

0.24

6.4

6.4

6.4

6.4

––

––

––

––

––

––

0.24

0.24

6.4

6.4

6.4

6.4

––

––

––

––

––

––

6.4

6.4

6.4

6.4

––

––

––

––

92

40

14.9

6.4

0.55

0.24

93

40

14.9

6.4

92

40

14.9

6.4

93

40

14.9

6.4

92

40

14.9

6.4

93

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

92

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

92

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

92

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

92

40

14.9

6.4

92

40

14.9

6.4

92

40

14.9

6.4

92

40

14.9

6.4

92

40

14.9

6.4

92

40

14.9

6.4

: The Qn/QnH changes in processing time depending on the serial No. of the CPU module.
Top
: The first 5 digits of the serial No. are "05031" or lower
Bottom : The first 5 digits of the serial No. are "05032" or higher
For the condition to be satisfied when the instruction is not executed, there is no differentiation between the
top and bottom.

Instruction

Condition (Device)
When not executed
Single
precision

ANDE< *1

When
executed

In conductive status
In non-conductive status

When not executed
Double
precision

When
executed

In conductive status
In non-conductive status

When not executed
Single
precision
ORE< *1

executed

In non-conductive status

When not executed
Double
precision

Single
precision
LDE>=

When

In conductive status

When
executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status

*1

precision

In non-conductive status
When not executed

Single
precision
ANDE>= *1

When
executed

In conductive status
In non-conductive status

When not executed
Double
precision

*1

When
executed

In conductive status
In non-conductive status

Qn

QnH

QnPH

QnPRH

0.55

0.24

0.24

0.24

6.4

6.4

6.4

6.4

––

––

––

––

––

––

0.24

0.24

6.4

6.4

6.4

6.4

––

––

––

––

––

––

6.4

6.4

6.4

6.4

––

––

––

––

0.24

0.24

6.4

6.4

6.4

6.4

––

––

––

––

––

––

92

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

92

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

93

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

93

40

14.9

6.4

92

40

14.9

6.4

93

40

14.9

6.4

92

40

14.9

6.4

93

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

92

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

92

40

14.9

6.4

92

40

14.9

6.4

: The Qn/QnH changes in processing time depending on the serial No. of the CPU module.
Top
: The first 5 digits of the serial No. are "05031" or lower
Bottom : The first 5 digits of the serial No. are "05032" or higher
For the condition to be satisfied when the instruction is not executed, there is no differentiation between the
top and bottom.

App-29

8
8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU

Double

In conductive status

Processing Time (µs)

Instruction

Condition (Device)
When not executed
Single
precision

When
executed

ORE>= *1

In non-conductive status

When not executed
Double
precision

When
executed

In conductive status
In non-conductive status

In conductive status

LD$ =

AND$ =

In conductive status

AND$ < >

App-30

0.24

6.4

6.4

6.4

6.4

––

––

––

––

––

––

16

16

92

40

14.9

6.4

92

40

14.9

6.4

0.55

0.24

92

40

14.9

6.4

92

40

14.9

6.4

38

16
15

15

15

0.23

0.23

0.23

In conductive status

39

17

17

17

In non-conductive status

32

14

14

14

0.56

0.24

0.24

0.24

In conductive status

40

17

17

17

In non-conductive status

33

14

14

14

32

14

14

14

In conductive status
In non-conductive status

40

17

17

17

When not executed

0.56

0.23

0.23

0.23

In conductive status

33

14

14

14

In non-conductive status

39

17

17

17

0.56

0.24

0.24

0.24

32

14

14

14

When executed

When executed

*1

QnPRH

0.24

34

When executed

LD$ >

QnPH

0.24

0.56

When not executed
OR$ < >

QnH

When not executed
When executed

LD$ < >

Qn
0.55

In non-conductive status

When not executed
OR$ =

Processing Time (µs)

In conductive status

39

17

17

17

In conductive status

In non-conductive status

32

14

14

14

In non-conductive status

40

17

17

17

: The Qn/QnH changes in processing time depending on the serial No. of the CPU module.
Top
: The first 5 digits of the serial No. are "05031" or lower
Bottom : The first 5 digits of the serial No. are "05032" or higher
For the condition to be satisfied when the instruction is not executed, there is no differentiation between the
top and bottom.

Instruction

Condition (Device)
When not executed

AND$ >

When executed

When executed

AND$ < =

14

14

14

17

17

17

0.56

0.24

0.24

0.24

32

14

14

14

In conductive status
In non-conductive status

14
0.23

In conductive status

39

17

17

17

In non-conductive status

32

14

14

14

0.56

0.24

0.24

0.24

40

17

17

17

In conductive status

33

14

14

14

In conductive status

In non-conductive status

32

14

14

14

In non-conductive status

40

17

17

17

When not executed

0.56

0.23

0.23

0.23

In conductive status

32

14

14

14

In non-conductive status

39

16

16

16
0.24

0.56

0.24

0.24

In conductive status

32

14

14

14

In non-conductive status

39

16

16

16

40

17

17

17

In non-conductive status

32

14

14

14

When not executed

0.56

0.23

0.23

0.23

In conductive status

39

16

16

16

In non-conductive status

32

14

14

14

D

BKCMP <> S1 S2

n
n

D

BKCMP <>P S1 S2

D

BKCMP > S1 S2

n

D

n

0.56

0.24

0.24

0.24

In conductive status

39

17

17

17

In non-conductive status

32

14

14

14

n=1

48

21

21

21

n = 96

142

61

61

61

n=1

48

21

21

21

n = 96

150

65

65

65

n=1

48

21

21

21

BKCMP >P S1 S2

D

n

n = 96

142

61

61

61

BKCMP >= S1 S2

D

n

n=1

48

21

21

21

n = 96

150

65

65

65

n=1

48

21

21

21

BKCMP >=P S1 S2

D

BKCMP < S1 S2

n

D

n

BKCMP 
 =

0.23

32

When executed

AND$ > =

0.23

33

When not executed

LD$ > =

0.23

0.56

When executed

OR$ <

0.56

When not executed

When executed

AND$ <

QnPRH

39

When not executed

LD$ <

QnPH

In non-conductive status

When executed

OR$ < =

QnH

In conductive status

In conductive status

LD$ < =

Qn

In non-conductive status

When not executed
OR$ >

Processing Time (µs)

Instruction
+

S

D

+P S

D

+P S1 S2
S

-P

D
S

D+ S

D

QnPRH

When executed

0.39

0.17

0.17

0.17

When executed

0.47

0.20

0.20

0.20

When executed

0.39

0.17

0.17

0.17

When executed

0.47

0.20

0.20

0.20

When executed

0.71

0.31

0.31

0.31

When executed

0.79

0.34

0.34

0.34

When executed

0.71

0.30

0.30

0.30

When executed

0.79

0.34

0.34

0.34

When executed

0.47

0.20

0.20

0.20

––

2.7

1.2

1.2

1.2

––

7.9

3.4

3.4

3.4

––

14

6.1

6.1

6.1

––

2.2

1.0

1.0

1.0

––

5.0

2.2

2.2

2.2

––

2.0

0.9

0.9

0.9

––

4.9

2.1

2.1

2.1

––

12

5.0

5.0

5.0

––

12

5.3

5.3

5.3

––

11

4.8

4.8

4.8

––

12

5.2

5.2

5.2

––

3.7

1.6

1.6

1.6

D

D+ S1 S2

D

D+P S1 S2
S

D

D

D-P S

D

D - S1 S2

D

D - P S1 S2
* S1 S2

D

D

* P S1 S2
/ S1 S2

D

D

/P S1 S2

D

D * S1 S2

D

D * P S1 S2
D/ S1 S2

B+ S

D

D

D/P S1 S2

D

D

B+P S

D

B+ S1 S2

D

B+P S1 S2
S

D

D

B-P S

D

B - S1 S2

D

B - P S1 S2
S

DB+P

D

D
S

D

DB+ S1 S2

D

DB+P S1 S2
DB -

QnPH

D

D

D+P S

DB+

QnH

D

- P S1 S2

B-

Qn

D

- S1 S2

D-

Processing Time (µs)

D

+ S1 S2

-

Condition (Device)

S

DB - P S

D

D
D

DB - S1 S2

D

DB - P S1 S2
B * S1 S2
B * P S1 S2

App-32

D

D
D

Instruction
B/

S1 S2

Qn

QnH

QnPH

QnPRH

––

3.8

1.6

1.6

1.6

––

24

10

10

10

––

27

12

12

12

1.8

0.78

0.78

0.78

1.8

0.78

0.78

0.78

D

B/P S1 S2

D

DB * S1 S2

DB/ S1 S2

D

D

DB/P S1 S2

S

precision

D

S
D

Double
precision

S

precision

D

E+P S1 S2

D

Double
precision
Single

E- S

precision

D

E -P S

D

Double
S

precision

D

E -P S1 S2

D

S1

precision

D

E*P S1 S2

D

S1

S1

E/P S1 S2

precision

D
D

S1

––

= 2127,

D

= 2127

203

87

––

––

= 0,

S2

=0

2.4

1.1

1.1

1.1

= 2127,

S2

= 2127

2.4

1.1

1.1

1.1

= 0,

S2

=0

209

90

––

––

= 2127,

S2

= 2127

209

90

––

––

= 0,

D

=0

1.8

0.78

0.78

0.78

= 2127,

D

= 2127

1.8

0.78

0.78

0.78

= 0,

D

=0

202

87

––

––

= 2127,

D

= 2127

202

87

––

––

= 0,

S2

=0

2.4

1.1

1.1

1.1

= 2127,

S2

= 2127

2.4

1.1

1.1

1.1

= 0,

S2

=0

210

90

––

––

= 2127,

S2

= 2127

210

90

––

––

= 0,

S2

=0

2.4

1.1

1.1

1.1

= 2126,

S2

= 2127

2.4

1.1

1.1

1.1

= 0,

S2

=0

222

96

––

––

= 2126,

S2

= 2127

222

96

––

––

= 0,

S2

=1

12

5.2

5.2

5.2

12

5.2

5.2

5.2

369

159

––

––

369

159

––

––

S1
S1

Double
precision

––

S1

Single
E/ S1 S2

87

S1

Double
precision

203

S1

Single
E* S1 S2

=0

S1

Double
precision

D

= 2127,
S1

S1

= 0,

= 2127,

S2
S2
S2

= - 2126
=1
= - 2126

App-33

8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU

Single
E - S1 S2

= 0,

S

precision

127

=2

S
S

=0

D

S1
S1

127

D

,

S1
S1

= 0,

=2
S

Single
E+ S1 S2

8

D

Single

E+P S

8
8

D

DB * P S1 S2

E+ S

Processing Time (µs)

Condition (Device)

Instruction
$+ S

Condition (Device)

Qn

QnH

QnPH

QnPRH

––

68

29

29

29

––

81

35

35

35

––

0.32

0.14

0.14

0.14

––

0.47

0.20

0.20

0.20

––

0.32

0.14

0.14

0.14

––

0.47

0.20

0.20

0.20

––

1.1

0.48

0.48

0.48

––

3.2

1.4

1.4

1.4

––

1.0

0.44

0.44

0.44

––

1.9

0.82

0.82

0.82

D

$+P S

D

$+ S1 S2
$+P S1 S2

D
D

INC
INCP
DINC
DINCP
DEC
DECP
DDEC
DDECP
BCD
BCDP
DBCD
DBCDP
BIN
BINP
DBIN
DBINP

Single
INT
INTP

S

=0

3.2

1.4

1.4

1.4

S

= 32766.5

3.2

1.4

1.4

1.4

S

=0

22

9.3

––

––

S

= 32766.5

22

9.3

––

––

S

=0

2.5

1.1

1.1

1.1

S

= 1234567890.3

2.5

1.1

1.1

1.1

S

=0

24

10

––

––

S

= 1234567890.3

24

10

––

––

S

=0

2.1

0.92

0.92

0.92

S

= 7FFFH

2.1

0.92

0.92

0.92

S

=0

22

9.6

––

––

S

= 7FFFH

22

9.6

––

––

S

=0

2.1

0.88

0.88

0.88

S

= 7FFFFFFFH

2.1

0.88

0.88

0.88

S

=0

26

11

––

––

S

= 7FFFFFFFH

26

11

––

––

precision
Double
precision
Single

DINT
DINTP

precision
Double
precision
Single

FLT
FLTP

precision
Double
precision
Single

DFLT
DFLTP

precision
Double
precision

App-34

Processing Time (µs)

Instruction

Condition (Device)

Processing Time (µs)
QnH

QnPH

QnPRH

––

4.5

1.9

1.9

1.9

––

4.7

2.0

2.0

2.0

––

4.7

2.0

2.0

2.0

––

5.3

2.3

2.3

2.3

––

18

7.7

7.7

7.7

––

32

14

14

14

––

3.6

1.6

1.6

1.6

––

4.3

1.8

1.8

1.8

––

3.9

1.7

1.7

1.7

n=1

38

17

17

17

n = 96

99

43

43

43

n=1

38

17

17

17

n = 96

99

43

43

43

0.24

0.10

0.10

0.10

MOV

––

––

––

––

MOVP

––

––

––

––

140*1

60*1

60*1

60*1

0.47

0.20

0.20

0.20

DMOV

––

––

––

––

DMOVP

––

––

––

––

147*1

64*1

64*1

64*1

––

0.63

0.27

0.27

0.27

––

40

17

17

17

––

0.40

0.17

0.17

0.17

––

0.55

0.24

0.24

0.24

DBLP
WORD
WORDP
GRY
GRYP
DGRY
DGRYP
GBIN
GBINP
DGBIN
DGBINP
NEG
NEGP
DNEG
DNEGP
ENEG
ENEGP
BKBCD S
BKBCDP S
BKBIN S
BKBINP S

n

D
D

n

n

D
D

n
S

S

= D0,

S

S

EMOV
EMOVP
$MOV
$MOVP
CML
CMLP
DCML
DCMLP

*1

= D0,

D

= D0,

= D0,

D

D

= D1

= J1 \ W1

D

= D1

= J1 \ W1

: The upper row indicates the processing time when A38B/A1S38B and the extension base are used.
The center row indicates the processing time when A38HB/A1S38HB is used.
The lower row indicates the processing time when Q312B is used.

App-35

8
8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU

Qn

DBL

Instruction

Condition (Device)

Processing Time (µs)
Qn

QnH

QnPH

QnPRH

n=1

17

7.1

7.1

7.1

n = 96

32

14

14

14

n=1

6.7

2.9

2.9

2.9

n = 96

14

6.1

6.1

6.1

––

1.3

0.54

0.54

0.54

BXCH D1 D2 n

n=1

31

13

13

13

BXCHP D1 D2 n

n = 96

84

36

36

36

––

3.7

1.6

1.6

1.6

CJ

––

3.2

1.4

1.4

1.4

SCJ

––

3.2

1.4

1.4

1.4

JMP

––

3.2

1.4

1.4

1.4

GOEND

––

0.39

0.34

0.34

0.34

DI

––

0.95

0.41

0.41

0.41

EI

––

1.3

0.54

0.54

0.54

IMASK

––

11

4.6

4.6

4.6

IRET

––

1.6

0.68

0.68

0.68

RFS

n=1

6.7

4.7

4.7

4.7

RFSP

n = 96

19

13

13

13

UDCNT1

––

15

6.5

6.5

––

UDCNT2

––

16

6.8

6.8

––

TTMR

––

10

4.4

4.4

––

STMR

––

20

7.1

7.1

––

ROTC

––

26

11

11

––

RAMP

––

18

7.7

7.7

––

SPD

––

19

8.3

8.3

––

PLSY

––

10

4.5

4.5

––

PWM

––

9.1

3.9

3.9

––

MTR

––

11

4.9

4.9

––

BMOV S
BMOVP S
FMOV S
FMOVP S

n

D
D

n

n

D
D

n

XCH
XCHP
DXCH
DXCHP

SWAP
SWAPP

App-36

(3) Application instructions
The processing time when the instruction is not executed is calculated as follows:
Q02CPU ·······················································0.079 (No. of steps for each instruction + 1) µs
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU, Q02PHCPU, Q06PHCPU, Q12PHCPU,
Q25PHCPU, Q12PRHCPU, Q25PRHCPU ·0.034 (No. of steps for each instruction + 1) µs

Instruction
WAND S

Condition (Device)

D

WANDP S

When executed

Processing Time ( µs)
Qn

QnH

QnPH

QnPRH

0.39

0.17

0.17

0.17

D

When executed

0.47

0.20

0.20

D

DANDP S1 S2

D

BKAND S1 S2

D

BKANDP S1 S2
WOR S

When executed

0.71

0.31

0.31

0.31

When executed

0.79

0.34

0.34

0.34

n=1

36

16

16

16

n = 96

74

32

32

32

When executed

0.40

0.17

0.17

0.17

When executed

0.47

0.20

0.20

0.20

When executed

0.71

0.31

0.31

0.31

When executed

0.79

0.34

0.34

0.34

n=1

36

16

16

16

n = 96

74

32

32

32

When executed

0.39

0.17

0.17

0.17

When executed

0.47

0.20

0.20

0.20

When executed

0.71

0.31

0.31

0.31

When executed

0.79

0.34

0.34

0.34

n=1

36

16

16

16

n = 96

74

32

32

32

D

DAND S1 S2

n
n

D

D

WORP S

D

WOR S1 S2

D

WORP S1 S2

D

DOR S1 S2

D

DORP S1 S2

D

BKOR S1 S2

D

BKORP S1 S2
WXOR S

D

WXORP S1 S2

DXORP S

n

D

D

WXOR S1 S2

DXOR S

n

D

WXORP S

7
8

D

D

DORP S

6

D

D
D

DXOR S1 S2

D

DXORP S1 S2

D

BKXOR S1 S2

D

BKXORP S1 S2

n
D

n

App-37

Appendix1 OPERATION PROCESSING TIME
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU

DOR S

A

D

DANDP S

8

0.20

WANDP S1 S2 D
DAND S

8

8

D

WAND S1 S2

8

Instruction

Condition (Device)

Processing Time (µs)
Qn

QnH

QnPH

QnPRH

When executed

0.40

0.17

0.17

0.17

When executed

0.47

0.20

0.20

0.20

When executed

0.71

0.31

0.31

0.31

When executed

0.79

0.34

0.34

0.34

n=1

36

16

16

16

n = 96

74

32

32

32

ROR D n

n=1

2.0

0.85

0.85

0.85

RORP D n

n = 15

2.0

0.85

0.85

0.85

RCR D n

n=1

1.6

0.68

0.68

0.68

RCRP D n

n = 15

1.6

0.68

0.68

0.68

ROL D n

n=1

2.0

0.85

0.85

0.85

ROLP D n

n = 15

2.0

0.85

0.85

0.85

RCL D n

n=1

1.6

0.68

0.68

0.68

RCLP D n

n = 15

1.6

0.68

0.68

0.68

DROR D n

n=1

3.9

1.7

1.7

1.7

DRORP D n

n = 31

4.0

1.7

1.7

1.7

DRCR D n

n=1

4.3

1.8

1.8

1.8

DRCRP D n

n = 31

4.3

1.9

1.9

1.9

DROL D n

n=1

3.9

1.7

1.7

1.7

DROLP D n

n = 31

4.0

1.7

1.7

1.7

DRCL D n

n=1

4.3

1.8

1.8

1.8

DRCLP D n

n = 31

4.3

1.9

1.9

1.9

SFR D n

n=1

1.7

0.75

0.75

0.75

SFRP D n

n = 15

2.0

0.85

0.85

0.85

SFL D n

n=1

1.7

0.75

0.75

0.75

SFLP D n

n = 15

2.0

0.85

0.85

0.85

BSFLR D n

n=1

20

8.6

8.6

8.6

BSFLRP D n

n = 96

24

10

10

10

BSFL D n

n=1

20

8.5

8.5

8.5

BSFLP D n

n = 96

23

10

10

10

DSFR D n

n=1

1.3

0.58

0.58

0.58

DSFRP D n

n = 96

25

11

11

11

DSFL D n

n=1

1.3

0.58

0.58

0.58

DSFLP D n

n = 96

26

11

11

11

WXNR S

D

WXNRP S

D

WXNR S1 S2

D

WXNRP S1 S2
DNXR S

D

D

DNXRP S

D

DNXR S1 S2

D

DNXRP S1 S2

D

BKNXOR S1 S2
BKNXORP S1 S2

App-38

n

D
D

n

Instruction

Condition (Device)

Processing Time (µs)
Qn

QnH

QnPH

QnPRH

n=1

7.6

3.3

3.3

3.3

BSETP D n

n = 15

7.6

3.3

3.3

3.3

BRST D n

n=1

7.6

3.3

3.3

3.3

BRSTP D n

n = 15

7.6

3.3

3.3

3.3

––

8.2

3.5

3.5

3.5

––

9.2

3.9

3.9

3.9

BKRST S n

n=1

18

7.8

7.8

7.8

BKRSTP S n

n = 96

19

8.2

8.2

8.2

BSET

n

D

TEST S1 S2

D

TESTP S1 S2

D

DTEST S1 S2

D

DTESTP S1 S2

SER S1 S2

DSERP

n

22

9.6

9.6

9.6

21

8.9

8.9

8.9

All match

115

49

49

49

None match

133

57

57

57

All match

23

9.9

9.9

9.9

None match

23

9.7

9.7

9.7

All match

142

61

61

61

None match

132

57

57

57

3.9

1.7

1.7

1.7

=0

4.7

2.0

2.0

2.0

= FFFFFFFFH

12

5.0

5.0

5.0

n=2

20

8.6

8.6

8.6

n=8

27

12

12

12

M1 = ON

21

9.1

9.1

9.1

M4 = ON

21

9.1

9.1

9.1

M1 = ON

28

12

12

12

M256 = ON

26

11

11

11

––

1.3

0.54

0.54

0.54

n=1

18

7.7

7.7

7.7

n=4

19

8.3

8.3

8.3

n=1

21

8.9

8.9

8.9

n=4

23

9.7

9.7

9.7

––

41

18

18

18

––

42

18

18

18

n=1

47

20

20

20

n = 96

99

43

43

43

n=1

45

19

19

19

n = 96

89

38

38

38

n = 96
n=1

n

D

S1 S2

All match
None match

n=1

n
D

DSER S1 S2

D

n

n = 96

SUM

S

SUMP

S

DSUM

DECOP S

n
n

D

ENCO S
ENCOP S

n

D

SEG
SEGP
DIS S
DISP S
UNI S

n

D

n

D

n

D

UNIP S

D

NDIS S1

D

NDISP S1
NUNI S1

n

S2

D

S2

D
D

WTOB S

D

WTOBP S

BTOWP S

n=8

S2

NUNIP S1

BTOW S

=0

n=2

n

D

S2

n
n

D

n

D
D

8

n

A
6
7
8

App-39

Appendix1 OPERATION PROCESSING TIME
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU

S
D

8

= FFFFH
S

DSUMP
DECO S

8

D

D

SERP S1 S2

8

Instruction

Condition (Device)

n

MAX S

D

MAXP S
MIN S

n

D

n

D

MINP S

n

D

DMAX S
DMAXP S
DMIN S

n

D

n

D

n

D

DMINP S

n

D

SORT S1 n S2 D1 D2

DSORT S1 n S2 D1 D2
WSUM S

n

D

Processing Time (µs)
Qn

QnH

QnPH

QnPRH

n=1

17

7.1

7.1

7.1

n = 96

136

59

59

59

n=1

17

7.1

7.1

7.1

n = 96

159

69

69

69

n=1

27

12

12

12

n = 96

181

78

78

78

n=1

27

12

12

12

n = 96

112

48

48

48

n=1

16

7.1

7.1

7.1

n = 96

14

6.2

6.2

6.2

n=1

17

7.1

7.1

7.1

n = 96

16

6.8

6.8

6.8

n=1

16.4

7.1

7.1

7.1

WSUMP S

D

n

n = 96

68.4

29.5

29.5

29.5

DWSUM S

D

n

n=1

18.9

8.2

8.2

8.2

n = 96

130.4

56.1

56.1

56.1

FOR n

n=0

2.3

1.0

1.0

1.0

NEXT

––

3.3

1.4

1.4

1.4

––

11

4.6

4.6

4.6

Internal file pointer

2.1

0.88

0.88

0.88

Common pointer

33

14

14

14

––

135

58

58

58

Return to original program

2.9

1.3

1.3

1.3

DWSUMP S

D

n

BREAK
BREAKP
CALL Pn
CALLP Pn
CALL Pn S1 to S5
CALLP Pn S1 to S5
RET
FCALL Pn
FCALLP Pn
FCALL Pn S1 to S5

Return to other program

20

8.5

8.5

8.5

Internal file pointer

3.6

1.6

1.6

1.6

Common pointer

20

8.7

8.7

8.7

––

134

57

57

57

––

77

33

33

33

––

162

70

70

70

––

78

34

34

34

––

200

86

86

86

FCALLP Pn S1 to S5
ECALL * Pn
ECALLP * Pn
*: Program name
ECALL * Pn S1 to S5
ECALLP * Pn S1 to S5
*: Program name
EFCALL * Pn
EFCALLP * Pn
*: Program name
EFCALL * Pn S1 to S5
EFCALLP * Pn S1 to S5
*: Program name

*1: Indicates extension of scan time to completion of instruction.

App-40

Instruction

Condition (Device)

Qn

QnH

QnPH

QnPRH

55

16

16

16

––

12

5.2

5.2

5.2

––

4.7

2.0

2.0

2.0

Number of contacts 1

48

21

21

21

COM

––

IX
IXEND
IXDEV + IXSET

Processing Time (µs)

93

40

40

40

Number of data points 0

11

4.5

4.5

4.5

FIFWP

Number of data points 96

11

4.5

4.5

4.5

FIFR

Number of data points 1

13

5.6

5.6

5.6

FIFRP

Number of data points 96

32

14

14

14

FPOP

Number of data points 1

16

7.0

7.0

7.0

FPOPP

Number of data points 96

16

7.0

7.0

7.0

FINS

Number of data points 0

20

8.4

8.4

8.4

FINSP

Number of data points 96

36

15

15

15

FDEL

Number of data points 1

19

7.5

7.5

7.5

FDELP

Number of data points 96

39

15

15

15

––

––

––

––

––

––

––

––

47

22

22

22

––

––

––

––

––

––

––

––

476

437

437

437

––

––

––

––

––

––

––

––

51

24

24

24

––

––

––

––

––

––

––

––

478

437

437

437

––

––

––

––

––

––

––

––

48

20

20

20

––

––

––

––

––

––

––

––

479

412

412

412

––

––

––

––

––

––

––

––

50

23

23

23

––

––

––

––

––

––

––

––

457

416

416

416

n3 = 1

FROM n1 n2 D n3
FROMP n1 n2 D n3

n3 = 1000

*1

n3 = 1

DFRO n1 n2 D n3
DFROP n1 n2 D n3

n3 = 500

*1

n3 = 1

TO n1 n2 D n3
TOP n1 n2 D n3

n3 = 1000

*1

n3 = 1

DTO n1 n2 D n3
DTOP n1 n2 D n3

n3 = 500

*1

Variable 1 character

33

11

11

––

Variable 32 character

48

18

18

––

SM701OFF

21

7.8

7.8

––

SM701ON

PR
PRC
LED

*1

––

181

16

16

––

When displayed

––

––

––

––

Display completed

––

––

––

––

: The upper row indicates the processing time when A38B/A1S38B and the extension base are used.
The center row indicates the processing time when A38HB/A1S38HB is used.
The bottom row indicates the processing times taken when the Q312B is used to execute the instruction for
the QJ71C24 in slot 0.
The FROM/TO instruction differs in processing time according to the number of slots and the loaded
modules.
(The QnCPU/QnHCPU also differs in processing time according to the extension base type.)

App-41

8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU

Number of contacts 14
FIFW

8

Instruction
LEDC

LEDR

Qn

QnH

QnPH

QnPRH

When displayed

––

––

––

––

Display completed

––

––

––

––

0.40

0.17

0.17

0.17

103

44

44

44

5.8

2.5

2.5

2.5

No display

no display

LED instruction execution
CHKST

CHK

1 contact no error

24

10

10

10

150 contact no error

1676

721

721

721

1 contact error

88

38

38

38

10 steps

5.8

2.5

2.5

2.5

All internal devices

––

––

––

––

File register 8k points

––

––

––

––

SLT execution completion

––

––

––

––

––

––

––

––

––

Start

––

––

––

––

SLTR
STRA

no display

––

CHKCIR

SLT

Processing Time (µs)

Condition (Device)

STRA execution completion

––

––

––

––

STRAR

––

––

––

––

––

PTRA

––

––

––

––

––

PTRAR

––

––

––

––

––

When operating

––

––

––

––

Trace in progress

––

––

––

––

=1

15

6.7

6.7

6.7

= - 32768

24

10

10

10

=1

43

18

18

18

= - 2147483648

86

37

37

37

=1

18

7.7

7.7

7.7

= FFFFH

19

8.2

8.2

8.2

=1

23

10

10

10

= FFFFFFFFH

24

10

10

10

=1

23

9.8

9.8

9.8

= 9999

21

8.9

8.9

8.9

=1

22

9.5

9.5

9.5

= 99999999

29

13

13

13

=1

57

25

25

25

= - 32768

58

25

25

25

=1

92

40

40

40

= - 2147483648

106

46

46

46

=1

13

5.8

5.8

5.8

= FFFFH

15

6.4

6.4

6.4

=1

22

9.5

9.5

9.5

= FFFFFFFFH

25

11

11

11

PTRAEXE
PTRAEXEP
BINDA

S

BINDAP
S

DBINDA

S

DBINDAP
S

BINHA

S

BINHAP
S

DBINHA

S

DBINHAP
S

BCDDA

S

BCDDAP
S

DBCDDA

S

DBCDDAP
S

DABIN

S

DABINP
S

DDABIN

S

DDABINP
S

HABIN

S

HABINP
S

DHABIN

S

DHABINP
S

App-42

Instruction

Qn

QnH

QnPH

QnPRH

=1

16

6.9

6.9

6.9

= 9999

17

7.2

7.2

7.2

=1

25

11

11

11

= 99999999

29

13

13

13

––

40

17

17

17

DABCD

S

DABCDP
S

DDABCD

S

DDABCDP
S

COMRD
COMRDP

18

8.0

8.0

8.0

86

37

37

37

––

53

23

23

23

––

123

53

53

53

––

95

41

41

41

––

166

72

72

72

––

564

243

243

243

Decimal point format all 2-digit specification

100

43

43

43

Exponent format all 6-digit specification

127

55

55

55

n=1

64

28

28

28

n = 96

289

125

125

125

n=1

60

26

26

26

n = 96

343

148

148

148

n=1

49

21

21

21

n = 96

131

56

56

56

n=1

50

21

21

21

n = 96

131

56

56

56

––

53

23

23

23

––

128

55

55

55

LENP
STR
STRP
DSTR
DSTRP
VAL
VALP
DVAL
DVALP
ESTR
ESTRP

EVALP
ASC S
ASCP S
HEX S

n

D

n

D

n

D

HEXP S

D

RIGHT S

n
n

D

RIGHTP S

D

LEFT S

n

LEFTP S

D
D

n

n

MIDR
MIDRP
MIDW
MIDWP

No match

INSTR
INSTRP

Match

58

25

25

25

Head

55

24

24

24

End

58

25

25

25

App-43

8
8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU

1 character
96 characters

LEN

EVAL

Processing Time (µs)

Condition (Device)

Instruction

Processing Time (µs)

Condition (Device)

Qn

QnH

QnPH

QnPRH

––

527

227

227

227

––

1656

713

713

713

SIN

Single precision

115

50

50

50

SINP

Double precision

1945

837

––

––

COS

Single precision

122

53

53

53

COSP

Double precision

2618

1127

––

––

TAN

Single precision

123

53

53

53

TANP

Double precision

2618

1127

––

––

ASIN

Single precision

111

48

48

48

ASINP

Double precision

2491

1072

––

––

ACOS

Single precision

115

49

49

49

ACOSP

Double precision

2367

1019

––

––

ATAN

Single precision

157

68

68

68

ATANP

Double precision

3140

1352

––

––

RAD

Single precision

17

7.2

7.2

7.2

RADP

Double precision

24

10

––

––

DEG

Single precision

17

7.2

7.2

7.2

DEGP

Double precision

23

9.9

––

––

SQR

Single precision

28

12

12

12

SQRP

Double precision

1812

780

––

––

129

56

56

56

2386

1026

––

––

113

49

49

49

2146

924

––

––

––

3.9

1.7

1.7

1.7

––

3.5

1.5

1.5

1.5

EMOD
EMODP
EREXP
EREXPP

= - 10

S

Single precision
EXP

S

EXPP

= - 10

S

Double precision

Single precision
LOG

S

=1

S

=1

S

LOGP
S

Double precision

S

RND
RNDP
SRND
SRNDP

App-44

=1

= 10
=1
= 10

Instruction

Condition (Device)

QnH

QnPH

QnPRH

=0

6.2

2.7

2.7

2.7

= 9999

38

16

16

16

=0

6.2

2.7

2.7

2.7

= 99999999

38

16

16

16

––

12

5.1

5.1

5.1

––

12

5.2

5.2

5.2

––

12

5.2

5.2

5.2

––

20

8.7

8.7

8.7

––

21

9.0

9.0

9.0

––

22

9.6

9.6

9.6

––

10

4.3

4.3

4.3

––

11

4.7

4.7

4.7

––

9.8

4.2

4.2

4.2

––

11

4.9

4.9

4.9

––

9.1

3.9

3.9

3.9

––

11

4.6

4.6

4.6

––

6.8

2.9

2.9

2.9

––

205

88

88

88

––

147

63

63

63

––

13

5.5

5.5

5.5

––

15

6.4

6.4

6.4

S

BSQRP
S

S

BDSQRP
S

BSIN
BSINP
BCOS
BCOSP
BTAN
BTANP
BASIN
BASINP
BACOS
BACOSP
BATAN
BATANP
LIMIT
LIMITP
DLIMIT
DLIMITP
BAND
BANDP
DBAND
DBANDP
ZONE
ZONEP
DZONE
DZONEP
RSET
RSETP
QDRSET
QDRSETP
QCDSET
QCDSETP
DATERD
DATERDP
DATEWR
DATEWRP

App-45

8
8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU

Qn

BSQR

BDSQR

Processing Time (µs)

Instruction
DATE+
DATE+P
DATE DATE - P
SECOND
SECONDP
HOUR
HOURP
MSG

PKEY
PSTOP
PSTOPP
POFF
POFFP
PSCAN
PSCNAP
PLOW
PLOWP
WDT
WDTP
DUTY
ZRRDB
ZRRDBP
ZRWRB
ZRWRBP
ADRSET
ADRSETP
KEY
ZPUSH
ZPUSHP
ZPOP
ZPOPP
EROMWR
EROMWRP

App-46

Condition (Device)

Processing Time (µs)
Qn

QnH

QnPH

QnPRH

No digit increase

13

5.4

5.4

5.4

Digit increase

13

5.4

5.4

5.4

No digit increase

12

5.2

5.2

5.2

Digit increase

12

5.2

5.2

5.2

––

10

4.5

4.5

4.5

––

12

5.2

5.2

5.2

1 character

3.0

1.3

1.3

1.3

32 characters

3.0

1.3

1.3

1.3

Initial time

20

8.6

8.6

8.6

No reception

19

8.2

8.2

8.2

––

79

34

34

34

––

79

34

34

34

––

75

32

32

32

––

80

34

34

––

––

5.9

2.6

2.6

2.6

––

9.3

4.0

4.0

4.0

––

7.9

3.4

3.4

3.4

––

9.4

4.0

4.0

4.0

––

4.9

2.1

2.1

2.1

––

17

7.3

7.3

––

––

11

4.7

4.7

4.7

––

5.1

2.2

2.2

2.2

––

––

––

––

––

Instruction

Processing Time (µs)

Condition (Device)

Qn

QnH

QnPH

QnPRH

ZCOM

––

691

289

289

289

READ

––

––

––

––

––

SREAD

––

––

––

––

––

WRITE

––

––

––

––

––

SWRITE

––

––

––

––

––

SEND

––

––

––

––

––

RECV

––

––

––

––

––

REQ

––

––

––

––

––

ZNFR

––

––

––

––

––

ZNTO

––

––

––

––

––

MELSECNET/10

––

––

––

––

MELSECNET (II)

––

––

––

––

MELSECNET/10

––

––

––

––

ZNRD

ZNWR

MELSECNET (II)

––

––

––

––

RFRP

––

––

––

––

––

RTOP

––

––

––

––

––

8
8
8
8
A
6
7

(4) Processing time for QCPU instructions (QCPU instructions only)
(a) Instructions available from function version A
Instruction
UNIRD
TRACE

Processing Time (µs)

Condition (Device)
––

Qn

QnH

QnPH

QnPRH

79

34

34

34

Start

176

76

76

76

STRA execution completion

6.3

2.7

2.7

2.7

––

19

8.2

8.2

8.2

SP.FWRITE

––

84

36

36

36

SP.FREAD

––

82

35

35

35

PLOADP

––

58

25

25

––

PUNLOADP

––

272

117

117

––

PSWAPP

––

308

133

133

––

1 point

45.5

20

20

20

1000 points

215

91

91

91

1 point

49.5

22

22

22

1000 points

540

305

305

305

When standard RAM is used
RBMOV
When SRAM card is used

App-47

Appendix1 OPERATION PROCESSING TIME
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU

TRACER

8

(b) Instructions available from function version B
Instruction

Processing Time (µs)

Condition/Number of Points Processed

Qn

QnH

QnPH

QnPRH

720

660

660

––

860

730

730

––

––

43

20

20

20

n3 = 1

59

29

29

––

n3 = 1000

530

500

500

––

Refresh range: 2k words
(0.5k words
With auto refresh of

assigned equally to all CPUs)

CPU shared memory

COM *1

Refresh range: 4k words
(1k words assigned equally to all
CPUs)

Without auto refresh of
CPU shared memory
Reading from CPU
shared memory of
another CPU
FROM *1

Reading buffer memory

n3 = 1

of intelligent function
module*2

n3 = 1000

Writing to CPU shared

S.TO

memory of host CPU

S (P).DATERD
S (P).DATE+

*3

S (P).DATE-

*3

*3

Main base unit

51

24

24

––

Extension base unit

54

27

27

––

Main base unit

540

480

480

––

Extension base unit

1100

1050

1050

––

74

33

33

––

n2 = 256

126

54

54

––

––

25

11

11

11

––

38

17

17

17

––

38

17

17

17

n3 = 1 ("TO" instruction)
n4 = 1 ("S.TO instruction")

Reading data of the
expansion clock
Expansion clock data
addition operation
Expansion clock data
subtraction operation

*1

: If the processing overlaps those of the other CPUs in a multiple CPU system, the processing time
increases by a maximum of the following time.

For system having only the main base unit
(Instruction processing time increase) = 0.54
processed) (number of other CPUs) (µs)

(number of points

For system including extension base units
(Instruction processing time increase) = 1.30
processed) (number of other CPUs) (µs)
*2
*3

(number of points

: In a multiple CPU system, the instruction processing time for the intelligent function module under control
of the host CPU is equal to that for the intelligent function module under control of another CPU.
: Products with the first 5 digits of the serial No. "07032" or higher are applicable.

(5) Redundant system instructions (for redundant CPU)
Instruction
SP.CONTSW

App-48

Condition (Device)
––

Processing Time (µs)
Qn

QnH

QnPH

QnPRH

––

––

––

9.6

(6) Table of the time to be added when file register, module access device or link direct device is
used
Instruction

data
Bit

When standard
RAM is used

Word
Double word

File register (ZR)
When SRAM
card is used
(Q2MEM-1MBS,
Q2MEM-2MBS)

Bit
Word
Double word
Bit

Module access device
(Un\G

, U3En\G0 to G4095)

Word
Double word
Bit

Link direct device (Jn\

)

Word
Double word

Processing Time (µs)

Device Specification
Location

Qn

QnH

QnPH

QnPRH

Source

5.56

2.40

2.40

2.40

Destination

4.44

1.91

1.91

1.91
1.12

Source

2.60

1.12

1.12

Destination

3.76

1.62

1.62

1.62

Source

2.83

1.22

1.22

1.22

Destination

4.00

1.72

1.72

1.72
2.25

Source

5.22

2.25

2.25

Destination

4.09

1.76

1.76

1.76

Source

2.25

0.97

0.97

0.97

Destination

3.42

1.47

1.47

1.47

Source

2.49

1.07

1.07

1.07

Destination

3.65

1.57

1.57

1.57

Source

35.56

15.31

15.31

15.31

Destination

65.08

28.01

28.01

28.01

Source

32.76

14.10

14.10

14.10

Destination

28.84

12.41

12.41

12.41
14.20

Source

32.99

14.20

14.20

Destination

29.07

12.51

12.51

12.51

Source

75.67

32.57

32.57

32.57

Destination

138.65

59.67

59.67

59.67
31.30

Source

72.73

31.30

31.30

Destination

137.32

59.10

59.10

59.10

Source

72.96

31.40

31.40

31.40

Destination

137.55

59.20

59.20

59.20

8
8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU

App-49

Appendix 1.4 Operation Processing Time of Universal
Model QCPU
The processing time for the individual instructions are shown in the table on the following pages.
Operation processing times can vary substantially depending on the nature of the sources and
destinations of the instructions, and the values contained in the following tables should therefore
be taken as a set of general guidelines to processing time rather than as being strictly accurate.

Appendix 1.4.1

Subset instruction processing time

The following describes the subset instruction processing time.

1. The subset instruction processing time table shown in (1) applies when the device
used in an instruction satisfies either of the conditions (a) and (b).
2. Since the processing time of each instruction is not constant due to the cache
function in the Universal model QCPU, the minimum value and the maximum
value are described.
(1) Subset instruction processing time table
(a)

When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU.
Processing Time (µs)

Category

Instruction

Condition (Device)

Q00UJCPU
Min.

Max.

Q00UCPU
Min.

Max.

Q01UCPU
Min.

Max.

Q02UCPU
Min.

Max.

LD
LDI
AND
ANI
OR
ORI
LDP

When executed

0.120

0.080

0.060

0.040

LDF
ANDP
ANDF
ORP
Sequence

ORF

instruction

LDPI
LDFI

When executed

0.360

0.240

0.180

0.120

ANDPI
ANDFI
ORPI
ORFI

When executed

0.480

0.320

0.240

0.160

0.120

0.080

0.060

0.040

0.120

0.080

0.060

0.040

OUT

SET
RST

App-50

When not changed
When changed
When not executed
When executed

When not changed
When changed

Processing Time (µs)
Category

Instruction

Condition (Device)

Q00UJCPU
Min.

LD=

In conductive status
In non-conductive status

Max.

0.360

Q00UCPU
Min.

Max.

0.240

Q01UCPU
Min.

Max.

0.180

Q02UCPU
Min.

Max.

0.120

8

When not executed
AND=

When executed

In conductive status

0.360

0.240

0.180

0.120

In non-conductive status

8

When not executed
OR=

LD<>

When executed

In conductive status

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

A

0.360

0.240

0.180

0.120

6

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

In non-conductive status

In conductive status
In non-conductive status
When not executed

AND<>

When executed

In conductive status

LD>

When executed

8

In non-conductive status

When not executed
OR<>

8

In conductive status
In non-conductive status

In conductive status
In non-conductive status

7

When not executed
AND>

When executed

In conductive status
In non-conductive status

8

When not executed
OR>
Basic
LD<=

In conductive status
In non-conductive status

In conductive status
In non-conductive status
When not executed

AND<=

When executed

In conductive status
In non-conductive status

When not executed
OR<=

LD<

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status
When not executed

AND<

When executed

In conductive status
In non-conductive status

When not executed
OR<

LD>=

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status
When not executed

AND>=

When executed

In conductive status
In non-conductive status

When not executed
OR>=

When executed

In conductive status
In non-conductive status

App-51

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

instruction

When executed

Processing Time (µs)
Category

Instruction

Condition (Device)

Q00UJCPU
Min.

LDD=

In conductive status
In non-conductive status

Max.

Q00UCPU
Min.

Max.

Q01UCPU
Min.

Max.

Q02UCPU
Min.

Max.

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

0.360

0.240

0.180

0.120

When not executed
ANDD=

When executed

In conductive status
In non-conductive status

When not executed
ORD=

LDD<>

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status
When not executed

ANDD<>

When executed

In conductive status
In non-conductive status

When not executed
ORD<>

LDD>

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status
When not executed

ANDD>

When executed

In conductive status
In non-conductive status

When not executed
ORD>
Basic
instruction

LDD<=

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status
When not executed

ANDD<=

When executed

In conductive status
In non-conductive status

When not executed
ORD<=

LDD<

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status
When not executed

ANDD<

When executed

In conductive status
In non-conductive status

When not executed
ORD<

LDD>=

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status
When not executed

ANDD>=

When executed

In conductive status
In non-conductive status

When not executed
ORD>=

App-52

When executed

In conductive status
In non-conductive status

Processing Time (µs)
Category

Instruction

Condition (Device)

Q00UJCPU
Min.

+ S

D

+ S1 S2
- S

D

D

- S1 S2
D+ S

D
D

D + S1 S2
D- S

D

D

D - S1 S2

D

Max.

Q01UCPU
Min.

Max.

Q02UCPU
Min.

Max.

When executed

0.360

0.240

0.180

0.120

When executed

0.480

0.320

0.240

0.160

When executed

0.360

0.240

0.180

0.120

When executed

0.480

0.320

0.240

0.160

When executed

0.360

0.240

0.180

0.120

When executed

0.480

0.320

0.240

0.160

When executed

0.360

0.240

0.180

0.120

When executed

0.480

0.320

0.240

0.160

D

When executed

0.420

0.300

0.240

0.180

/ S1 S2

D

When executed

0.520

0.400

0.340

0.280

When executed

0.500

0.380

0.320

0.260

When executed

0.640

0.520

0.460

0.400

D/ S1 S2
B+ S

B- S

D
D

D

B + S1 S2

D

D

When executed

3.100

12.300

3.100

12.300

3.100

12.300

3.300

8.300

When executed

5.900

13.500

5.900

13.500

5.900

13.500

4.600

6.200

When executed

3.150

12.300

3.150

12.300

3.150

12.300

3.300

9.000

B - S1 S2

D

When executed

5.950

13.600

5.950

13.600

5.950

13.600

4.600

8.200

B * S1 S2

D

When executed

3.700

12.100

3.700

12.100

3.700

12.100

4.000

8.200

When executed

4.000

14.000

4.000

14.000

4.000

14.000

4.200

12.400

B/ S1 S2

E+ S

D

= 0,

D

=0

0.420

0.300

0.240

0.180

= 2127,

D

= 2127

0.420

0.300

0.240

0.180

= 0,

S2

=0

0.540

0.380

0.300

0.220

= 2127,

S2

= 2127

0.540

0.380

0.300

0.220

= 0,

D

=0

0.420

0.300

0.240

0.180

= 2127,

D

= 2127

0.420

0.300

0.240

0.180

= 0,

S2

=0

0.540

0.380

0.300

0.220

= 2127,

S2

= 2127

0.540

0.380

0.300

0.220

= 0,

S2

=0

0.420

0.300

0.240

0.180

S1

= 2127,

S2

= 2127

0.420

0.300

0.240

0.180

S1

= 2127,

S2

= 2127

Single
D

S

precision
S

E + S1 S2

E- S

Single
D

precision

S1
S1

Single
D

S

precision
S

E - S1 S2

E * S1 S2

E/ S1 S2

Single
D

precision

S1
S1

Single
D

precision

S1

Single
D

precision

4.900

18.900

4.900

18.900

4.900

18.900

5.100

14.100

INC

When executed

0.240

0.160

0.120

0.080

DINC

When executed

0.240

0.160

0.120

0.080

DEC

When executed

0.240

0.160

0.120

0.080

DDEC

When executed

0.240

0.160

0.120

0.080

BCD

When executed

0.320

0.240

0.200

0.160

DBCD

When executed

0.400

0.320

0.280

0.240

BIN

When executed

0.260

0.180

0.140

0.100

DBIN

When executed

0.260

0.180

0.140

0.100

App-53

8
8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

instruction

Q00UCPU
Min.

* S1 S2

D * S1 S2

Basic

Max.

Processing Time (µs)
Category

Instruction

Condition (Device)

Q00UJCPU
Min.

0.220

0.180

0.140

=0

0.300

0.220

0.180

0.140

= 7FFFFFFFH

0.300

0.220

0.180

0.140

=0

0.300

0.220

0.180

0.140

= 32766.5

0.300

0.220

0.180

0.140

=0

0.300

0.220

0.180

0.140

= 1234567890.3

0.300

0.220

0.180

0.140

0.240
0.240
0.240
0.240
0.240
4.200
4.600
4.850
5.150
6.800 11.300
7.450 11.900
4.100
4.600

0.160
0.160
0.160
0.160
0.160
4.200
4.600
4.850
5.150
6.800 11.300
7.450 11.900
4.100
4.600

0.120
0.120
0.120
0.120
0.120
4.200
4.600
4.850
5.150
6.800 11.300
7.450 11.900
4.100
4.600

0.080
0.080
0.080
0.080
0.080
4.100
4.500
4.700
5.100
6.300
8.900
5.900
9.500
4.100
4.600

4.800
4.600
6.150
2.250
2.400
2.700
6.500
4.000
8.000

5.200
8.250
10.600
8.100
8.200
2.800
6.800
8.150
12.200

4.800
4.600
6.150
2.250
2.400
2.700
6.500
4.000
8.000

5.200
8.250
10.600
8.100
8.200
2.800
6.800
8.150
12.200

4.800
4.600
6.150
2.250
2.400
2.700
6.500
4.000
8.000

5.200
8.250
10.600
8.100
8.200
2.800
6.800
8.150
12.200

4.800
4.600
5.300
2.500
2.800
2.350
5.950
3.000
6.600

5.200
7.900
8.500
6.000
7.900
2.450
6.000
6.950
10.600

3.500
3.500
3.500

10.100
10.100
10.100

3.500
3.500
3.500

10.100
10.100
10.100

3.500
3.500
3.500

10.100
10.100
10.100

1.900
1.900
1.900

10.100
10.100
10.100

S

Single

DINT

Basic

0.300

S

precision

S

precision

S

MOV

––

DMOV

––

EMOV

––

CML

––

DCML

––

SM237=

instruction

n=1
n=96
n=1
n=96
n=1

ON
SM237=

BMOV

OFF
SM=237
=ON
SM237=

FMOV

n=96
n=1
n=96

OFF
XCH

––

DXCH

––

SM237=

n=1
n=96
n=1
n=96

ON
SM237=

DFMOV

OFF
CJ

––

SCJ

––

JMP

––

WAND S

D

WAND S1 S2
DAND S

D

D

DAND S1 S2
WOR S

D

WOR S1 S2
DOR S

WXOR S

D
D

WXOR S1 S2
DXOR S

D

D

DXNR S1 S2

App-54

D

D

WXNR S1 S2
DXNR S

D

D

DXOR S1 S2
WXNR S

D

D

Application DOR S1 S2
instruction

D

D

Max.

= 7FFFH

Single

INT

Q02UCPU
Min.

=0

S
S

Max.

0.140

S

precision

Q01UCPU
Min.

0.180

Single

DFLT

Max.

0.220

S

precision

Min.

0.300

Single

FLT

Max.

Q00UCPU

When executed

0.360

0.240

0.180

0.120

When executed

0.480

0.320

0.240

0.160

When executed

0.360

0.240

0.180

0.120

When executed

0.480

0.320

0.240

0.160

When executed

0.360

0.240

0.180

0.120

When executed

0.480

0.320

0.240

0.160

When executed

0.360

0.240

0.180

0.120

When executed

0.480

0.320

0.240

0.160

When executed

0.360

0.240

0.180

0.120

When executed

0.480

0.320

0.240

0.160

When executed

0.360

0.240

0.180

0.120

When executed

0.480

0.320

0.240

0.160

When executed

0.360

0.240

0.180

0.120

When executed

0.480

0.320

0.240

0.160

When executed

0.360

0.240

0.180

0.120

When executed

0.480

0.320

0.240

0.160

Processing Time (µs)
Category

Instruction

Condition (Device)

ROR D n

RCR D n

ROL D n

RCL D n

DROR D n

DRCR D n

DROL D n

Application

DRCL D n

instruction
SFR D n

SFL D n

DSFR D n

DSFL D n

Min.

Max.

Min.

Max.

2.250

10.800

2.250

10.800

2.250

10.800

2.300

7.800

2.250

10.800

2.350

10.800

2.350

10.800

2.400

7.800

n=1

2.250

10.800

2.250

10.800

2.250

10.800

2.300

3.900

n = 15

2.250

10.800

2.250

10.800

2.250

10.800

2.400

4.100

n=1

2.250

10.800

2.350

10.800

2.350

10.800

2.500

4.600

n = 15

2.250

10.800

2.350

10.800

2.350

10.800

2.400

4.600

n=1

2.250

11.500

2.300

11.500

2.300

11.500

2.400

7.500

n = 15

2.250

11.500

2.300

11.500

2.300

11.500

2.500

7.500

n=1

2.350

11.500

2.350

11.500

2.350

11.500

2.400

10.300

n = 31

2.350

11.500

2.350

11.500

2.350

11.500

2.500

10.300

n=1

2.350

13.300

2.350

13.300

2.350

13.300

2.500

12.700

n = 31

2.350

14.900

2.350

14.900

2.350

14.900

2.500

12.700

n=1

2.350

10.800

2.350

10.800

2.350

10.800

2.500

11.800

n = 31

2.350

10.800

2.350

10.800

2.350

10.800

2.500

11.800

n=1

2.350

13.300

2.350

13.300

2.350

13.300

2.500

5.100

n = 31

2.350

13.300

2.350

13.300

2.350

13.300

2.500

5.100

n=1

2.350

9.900

2.350

9.900

2.350

9.900

2.400

6.100

n = 15

2.350

9.900

2.350

9.900

2.350

9.900

2.300

5.700

n=1

2.350

9.850

2.350

9.850

2.350

9.850

2.400

4.300

n = 15

2.350

9.850

2.350

9.850

2.350

9.850

2.400

4.300

n=1

3.250

15.500

3.250

15.500

3.250

15.500

3.300

12.000

n = 96

32.600

45.000

32.600

45.000

32.600

45.000

32.600

42.200

n=1

3.200

15.500

3.200

15.500

3.200

15.500

3.300

8.200

n = 96

32.600

45.100

32.600

45.100

32.600

45.100

32.600

37.700

=0

3.100

8.950

3.100

8.950

3.100

8.950

3.400

6.700

= FFFFH

3.000

8.850

3.000

8.850

3.000

8.850

3.500

6.700

2.100

7.700

2.100

7.700

2.100

7.700

2.100

5.900

––

1.500

7.500

1.500

7.500

1.500

7.500

1.200

6.300

Internal file pointer

4.800

5.400

4.800

5.400

4.800

5.400

2.700

4.800

Common pointer

7.100

30.500

7.100

30.500

7.100

30.500

4.400

5.700

––

50.200

62.000

50.200

62.000

50.200

62.000

28.700

42.600

FOR
CALL Pn

Q02UCPU

Max.

n=1

When executed

SEG

Q01UCPU

Min.

CALL Pn S1 to S5

Remark
For the instructions for which a leading edge instruction ( P) is not described,
the processing time is the same as an ON execution instruction.
Example MOVP instruction, WANDP instruction etc.

App-55

8
8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

S

Q00UCPU

Max.

n = 15

S

SUM

Q00UJCPU

Min.

(b) When using Q03UD(E)HCPU, Q04UD(E)HCPU, Q06UD(E)HCPU,
Q10UD(E)HCPU,Q13UD(E)HCPU, Q20UD(E)HCPU, Q26UD(E)HCPU
Processing Time (µs)
Category

Instruction

Condition (Device)

Q03UD(E)CPU
Min.

Max.

Q04/Q06UD(E)HCPU
Min.

Max.

Q10/Q13/Q20/
Q26UD(E)HCPU
Min.

Max.

LD
LDI
AND
ANI
OR
ORI
LDP

When executed

0.020

0.0095

0.0095

When executed

0.060

0.0285

0.0285

When executed

0.080

0.038

0.038

0.020

0.0095

0.0095

0.020

0.0095

0.0095

LDF
ANDP
ANDF
Sequence

ORP

instruction

ORF
LDPI
LDFI
ANDPI
ANDFI
ORPI
ORFI
OUT
SET
RST

App-56

When not changed
When changed
When not executed

Processing Time (µs)
Category

Instruction

Condition (Device)

Q03UD(E)CPU
Min.

LD=

In conductive status
In non-conductive status

Max.

Q04/
Q06UD(E)HCPU
Min.

Max.

Q10/Q13/Q20/
Q26UD(E)HCPU
Min.

8

Max.

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

8

When not executed
AND=

When executed

In conductive status

8

In non-conductive status

When not executed
OR=

LD<>

When executed

In conductive status

8

In non-conductive status

In conductive status
In non-conductive status

A

When not executed
AND<>

When executed

In conductive status

0.060

0.0285

0.0285

In non-conductive status

6

When not executed
OR<>

LD>

When executed

In conductive status

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

In non-conductive status

In conductive status
In non-conductive status

7

When not executed
AND>

When executed

In conductive status

8

In non-conductive status

When not executed
OR>
instruction

LD<=

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

Basic

When not executed
AND<=

When executed

In conductive status
In non-conductive status

When not executed
OR<=

LD<

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status
When not executed

AND<

When executed

In conductive status
In non-conductive status

When not executed
OR<

LD>=

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status
When not executed

AND>=

When executed

In conductive status
In non-conductive status

When not executed
OR>=

When executed

In conductive status
In non-conductive status

App-57

Processing Time (µs)
Category

Instruction

Condition (Device)

Q03UD(E)CPU
Min.

LDD=

In conductive status
In non-conductive status

Max.

Q04/
Q06UD(E)HCPU
Min.

Max.

Q10/Q13/Q20/
Q26UD(E)HCPU
Min.

Max.

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

0.060

0.0285

0.0285

When not executed
ANDD=

When executed

In conductive status
In non-conductive status

When not executed
ORD=

LDD<>

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status
When not executed

ANDD<>

When executed

In conductive status
In non-conductive status

When not executed
ORD<>

LDD>

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status
When not executed

ANDD>

When executed

In conductive status
In non-conductive status

When not executed
ORD>
Basic
instruction

LDD<=

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status
When not executed

ANDD<=

When executed

In conductive status
In non-conductive status

When not executed
ORD<=

LDD<

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status
When not executed

ANDD<

When executed

In conductive status
In non-conductive status

When not executed
ORD<

LDD>=

When executed

In conductive status
In non-conductive status

In conductive status
In non-conductive status
When not executed

ANDD>=

When executed

In conductive status
In non-conductive status

When not executed
ORD>=

App-58

When executed

In conductive status
In non-conductive status

Processing Time (µs)
Category

Instruction

Condition (Device)

Q03UD(E)CPU
Min.

+ S

D

+ S1 S2
- S

D

D

- S1 S2
D+ S

D
D

D + S1 S2
D- S

D

D

D - S1 S2

D

Max.

Min.

When executed

0.060

0.0285

0.0285

When executed

0.080

0.038

0.038

When executed

0.060

0.0285

0.0285

When executed

0.080

0.038

0.038

When executed

0.060

0.0285

0.0285

When executed

0.080

0.038

0.038

When executed

0.060

0.0285

0.0285

When executed

0.080

0.038

0.038

When executed

0.120

0.057

0.057

/ S1 S2

D

When executed

0.220

0.110

0.110

When executed

0.200

0.095

0.095

When executed

0.340

0.170

0.170

B+ S
B+

D

D

S1 S2

B- S

D

D

D

8
8
8
A
6

When executed

3.300

5.500

3.000

4.100

3.000

4.100

When executed

4.600

6.200

4.200

5.900

4.200

5.900

When executed

3.300

4.400

2.900

3.800

2.900

3.800

B - S1 S2

D

When executed

4.600

6.300

4.200

4.600

4.200

4.600

B * S1 S2

D

When executed

4.000

4.800

3.400

4.800

3.400

4.800

When executed

4.200

5.700

3.700

5.200

3.700

5.200

B/ S1 S2

E + S1 S2

E- S

= 0,

D

=0

0.120

0.057

0.057

= 2127,

D

= 2127

0.120

0.057

0.057

= 0,

S2

=0

0.140

0.0665

0.0665

= 2127,

S2

= 2127

0.140

0.0665

0.0665

= 0,

D

=0

0.120

0.057

0.057

= 2127,

D

= 2127

0.120

0.057

0.057

= 0,

S2

=0

0.140

0.0665

0.0665

= 2127,

S2

= 2127

0.140

0.0665

0.0665

= 0,

S2

=0

0.120

0.057

0.057

S1

= 2127,

S2

= 2127

0.120

0.057

0.057

S1

= 2127,

S2

= 2127

Single
D

precision

S
S

Single
D

precision

S1
S1

Single
D

E - S1 S2

E * S1 S2

E/ S1 S2

precision

S
S

Single
D

precision

S1
S1

Single
D

precision

S1

Single
D

precision

4.500

5.600

3.900

4.900

0.285

INC

When executed

0.040

0.019

0.019

DINC

When executed

0.040

0.019

0.019

DEC

When executed

0.040

0.019

0.019

DDEC

When executed

0.040

0.019

0.019

BCD

When executed

0.120

0.057

0.057

DBCD

When executed

0.200

0.095

0.095

BIN

When executed

0.060

0.0285

0.0285

DBIN

When executed

0.060

0.0285

0.0285

7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

E+ S

D

8

Max.

D

D/ S1 S2

instruction

Min.

Q10/Q13/Q20/
Q26UD(E)HCPU

* S1 S2

D * S1 S2

Basic

Max.

Q04/Q06UD(E)HCPU

App-59

Processing Time (µs)
Category

Instruction

Condition (Device)

Q03UD(E)CPU
Min.

FLT

DFLT

INT

DINT

= 7FFFH

0.100

0.0475

0.0475

=0

0.100

0.0475

0.0475

= 7FFFFFFFH

0.100

0.0475

0.0475

=0

0.100

0.0475

0.0475

= 32766.5

0.100

0.0475

0.0475

=0

0.100

0.0475

0.0475

= 1234567890.3

0.100

0.0475

0.0475

0.040
0.040
0.040
0.040
0.040
6.300
8.200

0.019
0.019
0.019
0.019
0.019

0.019
0.019
0.019
0.019
0.019

5.400

7.000

5.400

7.000

8.200

10.600

3.900

5.100

3.900

5.100

6.000

7.800

2.900

3.700

2.900

3.700

7.100

8.800

5.900

7.600

5.900

7.600

9.300

11.900

4.400

5.700

4.400

5.700

7.100

9.100

3.400

4.300

3.400

4.300

5.300

5.900

4.200

4.800

4.200

4.800

7.000

8.000

3.400

3.800

3.400

3.800

5.900

6.800

2.800

3.200

2.800

3.200

5.300

7.600

4.400

6.800

4.400

6.800

7.400

12.200

3.600

5.800

3.600

5.800

6.300

11.000

3.000

5.200

3.000

5.200

S

Single

S
S

Single
precision

S
S

MOV

––

DMOV

––

EMOV

––

CML

––

DCML

––
*1

n=1

Basic
instruction

BMOV

n = 96

SM237=OFF
SM237=ON

*1

SM237=OFF*1
SM237=ON

*1

*1

n=1
FMOV

SM237=OFF
SM237=ON

*1

*1

n = 96
XCH
DXCH

DFMOV*2

CJ
SCJ
JMP

App-60

Max.

=0

Single

precision

Min.

0.0475

S

S

Max.

0.0475

S

precision

Min.

Q10/Q13/Q20/
Q26UD(E)HCPU

0.100

Single
precision

Max.

Q04/Q06UD(E)HCPU

SM237=OFF
SM237=ON

*1

2.500
2.900
1.800
2.300
1.800
2.300
––
2.800
3.700
2.100
2.900
2.100
2.900
SM237=OFF
2.600
3.750
2.250
3.150
2.250
3.150
n=1
SM237=ON
2.050
2.250
1.750
1.750
1.750
1.750
SM237=OFF
5.850
7.350
4.200
5.500
4.200
5.500
n=96
SM237=ON
5.300
6.000
3.650
4.150
3.650
4.150
––
1.800
2.800
1.400
2.400
1.400
2.400
––
1.800
2.800
1.400
2.400
1.400
2.400
––
1.800
2.800
1.100
2.400
1.100
2.400
*1 : Can be used onliy for the Q03UDCPU, Q04UDHCPU and Q06UDHCPU whose first 5 digits of serial
number is “10012” or later.
*2 : Can be used onliy for the Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q13UD(E)HCPU and
Q26UD(E)HCPU whose first 5 digits of serial number is “10012” or later.
––

Processing Time (µs)
Category

Instruction

Condition (Device)

Q03UD(E)CPU
Min.

WAND S

D

WAND S1 S2
DAND S

D

D

DAND S1 S2
WOR S

D

WOR S1 S2
DOR S

WXOR S

D
D

WXOR S1 S2
DXOR S

D

D

WXNR S1 S2
DXNR S

D

D

DXOR S1 S2
WXNR S

D

D

Application DOR S1 S2
instruction

D

D

D

DXNR S1 S2

D

Max.

Q04/Q06UD(E)HCPU
Min.

Max.

Q10/Q13/Q20/
Q26UD(E)HCPU
Min.

8

Max.

When executed

0.060

0.0285

0.0285

When executed

0.080

0.038

0.038

When executed

0.060

0.0285

0.0285

When executed

0.080

0.038

0.038

When executed

0.060

0.0285

0.0285

When executed

0.080

0.038

0.038

When executed

0.060

0.0285

0.0285

When executed

0.080

0.038

0.038

When executed

0.060

0.0285

0.0285

When executed

0.080

0.038

0.038

When executed

0.060

0.0285

0.0285

When executed

0.080

0.038

0.038

When executed

0.060

0.0285

0.0285

When executed

0.080

0.038

0.038

When executed

0.060

0.0285

0.0285

When executed

0.080

0.038

0.038

8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

App-61

Processing Time (µs)
Category

Instruction

Condition (Device)

n=1
ROR D n

RCR D n

ROL D n

RCL D n

DROR D n

DRCR D n

DROL D n

Application

DRCL D n

instruction
SFR D n

SFL D n

DSFR D n

DSFL D n

S

Q04/Q06UD(E)HCPU

Q10/Q13/Q20/
Q26UD(E)HCPU

Min.

Max.

Min.

Max.

Min.

Max.

2.300

3.100

1.700

2.500

1.700

2.500

n = 15

2.400

3.100

1.800

2.500

1.800

2.500

n=1

2.300

3.900

1.700

3.200

1.700

3.200

n = 15

2.400

4.100

1.700

3.200

1.700

3.200

n=1

2.400

3.300

1.800

3.200

1.800

3.200

n = 15

2.400

3.300

1.800

3.200

1.800

3.200

n=1

2.400

2.700

1.800

2.100

1.800

2.100

n = 15

2.400

2.800

1.800

2.200

1.800

2.200

n=1

2.400

3.400

1.900

2.700

1.900

2.700

n = 31

2.500

3.400

1.900

2.700

1.900

2.700

n=1

2.500

4.800

1.900

4.200

1.900

4.200

n = 31

2.500

4.900

1.900

4.200

1.900

4.200

n=1

2.500

3.900

1.800

3.200

1.800

3.200

n = 31

2.500

3.900

1.800

3.300

1.800

3.300

n=1

2.500

4.800

1.900

3.800

1.900

3.800

n = 31

2.500

4.600

1.900

3.800

1.900

3.800

n=1

2.400

3.900

1.700

2.600

1.700

2.600

n = 15

2.300

3.900

1.800

2.600

1.800

2.600

n=1

2.400

4.300

1.800

2.700

1.800

2.700

n = 15

2.400

4.300

1.800

2.700

1.800

2.700

n=1

2.700

4.800

2.200

4.300

2.200

4.300

n = 96

32.600

35.900

23.900

26.100

23.900

26.100

n=1

2.700

4.600

2.100

4.000

2.100

4.000

n = 96

32.600

35.300

23.700

25.800

23.700

25.800

=0

3.400

4.300

2.900

3.600

2.900

3.600

= FFFFH

3.500

4.200

2.900

3.600

2.900

3.600

S

SUM

Q03UD(E)CPU

SEG

When executed

2.100

2.800

1.500

2.100

1.500

2.100

FOR

––

1.200

2.400

0.870

2.100

0.870

2.100

Internal file pointer

2.600

4.000

2.300

3.600

2.300

3.600

Common pointer

4.000

5.300

3.200

4.900

3.200

4.900

––

28.700

33.400

26.100

29.300

26.100

29.300

CALL Pn
CALL Pn S1 to S5

Remark
For the instructions for which a leading edge instruction ( P) is not described,
the processing time is the same as an ON execution instruction.
Example MOVP instruction, WANDP instruction etc.

App-62

(2) Table of the time to be added when file register, module access device is used

8

(a) When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU
Device name

data
Bit

When standard
RAM is used

Word
Double word
Bit

File register
(R)

When SRAM
card is used
(Q2MEM-1MBS,
Q2MEM-2MBS)

Word
Double word
Bit

When SRAM
card is used
(Q3MEM-4MBS,
Q3MEM-8MBS)

Word
Double word
Bit

When standard
RAM is used

Word
Double word

File register

Bit

(ZR)/
data register
(D)/Extended

When SRAM
card is used
(Q2MEM-1MBS,
Q2MEM-2MBS)

link register

Word
Double word

(W))

Bit
When SRAM
card is used
(Q3MEM-4MBS,
Q3MEM-8MBS)

Word
Double word

Module access device
(Multiple CPU high speed transmission area)
(U3En\G10000)

Bit
Word
Double word

Processing Time (µs)

Location

Q00UJCPU

Q00UCPU

Q01UCPU

Q02UCPU

Source

0.100

0.100

0.100

0.100

Destination

0.220

0.220

0.220

0.220

Source

0.100

0.100

0.100

0.100

Destination

0.100

0.100

0.100

0.100

Source

0.200

0.200

0.200

0.200

Destination

0.200

0.200

0.200

0.200

Source

––

––

––

0.220

Destination

––

––

––

0.420

Source

––

––

––

0.220

Destination

––

––

––

0.180

Source

––

––

––

0.440

Destination

––

––

––

0.380

Source

––

––

––

0.160

Destination

––

––

––

0.320

Source

––

––

––

0.160

Destination

––

––

––

0.140
0.320

Source

––

––

––

Destination

––

––

––

0.300

Source

0.220

0.180

0.160

0.140

Destination

0.280

0.320

0.300

0.280

Source

0.220

0.180

0.160

0.140

Destination

0.220

0.180

0.160

0.140

Source

0.320

0.280

0.260

0.240

Destination

0.320

0.280

0.260

0.240

Source

––

––

––

0.260

Destination

––

––

––

0.480

Source

––

––

––

0.260

Destination

––

––

––

0.220

Source

––

––

––

0.480

Destination

––

––

––

0.420

Source

––

––

––

0.200

Destination

––

––

––

0.380

Source

––

––

––

0.200

Destination

––

––

––

0.180

Source

––

––

––

0.360

Destination

––

––

––

0.340

Source

––

––

––

––

Destination

––

––

––

––

Source

––

––

––

––

Destination

––

––

––

––

Source

––

––

––

––

Destination

––

––

––

––

App-63

8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

Extended

Device Specification

(b) When using Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU,
Q13UDE(H)CPU,Q20UD(E)HCPU and Q26UD(E)HCPU
Device name

data

Bit
When standard
RAM is used

Word
Double word
Bit

File register
(R)

When SRAM
card is used
(Q2MEM-1MBS,
Q2MEM-2MBS)

Word
Double word
Bit

When SRAM
card is used
(Q3MEM-4MBS,
Q3MEM-8MBS)

Word
Double word
Bit

When standard
RAM is used

Word
Double word

File register

Bit

(ZR)/
Extended
data register
(D)/Extended

When SRAM
card is used
(Q2MEM-1MBS,
Q2MEM-2MBS)

link register

Word
Double word

(W))

Bit
When SRAM
card is used
(Q3MEM-4MBS,
Q3MEM-8MBS)

Word
Double word
Bit

Module access device
(Multiple CPU high speed transmission area)
(U3En\G10000)

Word
Double word

App-64

Processing Time (µs)

Device Specification
Location

Q03UD(E)CPU

Q04/Q06UD(E)HCPU

Q10/Q13/Q20/
Q26UD(E)HCPU

Source

0.100

0.048

0.048

Destination

0.100

0.038

0.038

Source

0.100

0.048

0.048

Destination

0.100

0.038

0.038

Source

0.200

0.095

0.095

Destination

0.200

0.086

0.086

Source

0.220

0.200

0.200

Destination

0.180

0.162

0.162

Source

0.220

0.200

0.200

Destination

0.180

0.162

0.162

Source

0.440

0.399

0.399

Destination

0.380

0.361

0.361

Source

0.160

0.152

0.152

Destination

0.140

0.133

0.133

Source

0.160

0.152

0.152

Destination

0.140

0.133

0.133

Source

0.320

0.304

0.304

Destination

0.300

0.295

0.295

Source

0.120

0.057

0.057

Destination

0.120

0.048

0.048

Source

0.120

0.057

0.057

Destination

0.120

0.048

0.048

Source

0.220

0.105

0.105

Destination

0.220

0.095

0.095

Source

0.240

0.209

0.209

Destination

0.200

0.171

0.171

Source

0.240

0.209

0.209

Destination

0.200

0.171

0.171

Source

0.460

0.409

0.409

Destination

0.400

0.371

0.371

Source

0.180

0.162

0.162

Destination

0.160

0.143

0.143

Source

0.180

0.162

0.162

Destination

0.160

0.143

0.143

Source

0.340

0.314

0.314

Destination

0.320

0.304

0.304

Source

0.220

0.181

0.181

Destination

0.140

0.105

0.105

Source

0.220

0.181

0.181

Destination

0.140

0.105

0.105

Source

0.500

0.437

0.437

Destination

0.340

0.285

0.285

(3) Table of the time to be added when F/T(ST)/C device is used in OUT/SET/RST instruction

8

(a) When using Q00UJCPU, Q00UCPU, Q01UCPU amd Q02UCPU.
Instruction
name

Device name

Condition
When not executed

F

When executed

OUT

When executed

F

When executed

F

2.900

2.900

2.100

116.000

116.000

68.800

Display completed

116.000

116.000

116.000

61.600

0.360

0.240

0.180

0.120

After time up

0.360

0.240

0.180

0.120

When added

0.360

0.240

0.180

0.120

0.120

0.080

0.006

0.004

When displayed

116.000

116.000

116.000

68.600

Display completed

116.000

116.000

116.000

65.700

0.120

0.080

0.006

0.004

When displayed

55.800

55.800

55.800

26.500

Display completed

29.200

29.200

29.200

21.600

When not executed

0.360

0.240

0.180

0.120

When executed

0.360

0.240

0.180

0.120

When executed

T(ST), C

Q02UCPU

2.900

When not executed
RST

Q01UCPU

116.000

When not executed
SET

Q00UCPU

When displayed

When not executed
T(ST), C

Processing Time (µs)
Q00UJCPU

(b) When using Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(EHCPU,
Q13UD(E)HCPU, Q20UD(E)HCPU and Q26UD(E)HCPU
Instruction
name

Condition
When not executed

OUT
T(ST), C

When executed

1.940

1.570

1.570

39.930

38.090

38.090

Display completed

39.750

37.980

37.980

0.060

0.030

0.030

0.060

0.030

0.030

0.000

0.000

0.000

When displayed

42.900

40.600

40.600

Display completed

39.270

37.900

37.900

0.000

0.000

0.000

After time up

When not executed
SET

F

When executed

When not executed
F
RST
T(ST), C

When displayed

45.260

36.600

36.600

Display completed

19.020

16.190

16.190

When not executed

0.060

0.030

0.030

When executed

0.060

0.030

0.030

When executed

A
6
7

Q10/Q13/Q20/
Q26UD(E)HCPU

When displayed

When not executed
When executed

Q04/Q06UD(E)HCPU

8

App-65

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

F

Q03UD(E)CPU

8

8

Processing Time (µs)
Device name

8

Appendix 1.4.2

Processing time of instructions other than subset instruction

The following table shows the processing time of instructions other than subset instructions.
(1) Table of the processing time of instructions other than subset instructions
(a) When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU
Processing Time (µs)
Category

Instruction

Condition (Device)

Q00UJCPU
Min.

Max.

Q00UCPU
Min.

Max.

Q01UCPU
Min.

Max.

Q02UCPU
Min.

Max.

ANB
ORB
MPS

––

0.120

0.080

0.060

0.040

0.120

0.080

0.060

0.040

0.120

0.080

0.060

0.040

0.120

0.080

0.060

0.040

MRD
MPP
INV

Sequence
instruction

When executed

MEP

When not executed

MEF

When executed

EGP

When not executed

EGF

When executed

PLS

––

1.800

1.900

1.800

1.900

1.800

1.900

1.300

1.600

PLF

––

1.800

1.900

1.800

1.900

1.800

1.900

1.600

1.700

FF

DELTA

SFT

When not executed
When executed
When not executed
When executed
When not executed
When executed

0.240
1.700

1.800

0.240
4.000

14.700

0.240
1.800

12.600

0.160
1.700

1.800

0.160
4.000

14.700

0.160
1.800

12.600

0.120
1.700

1.800

0.120
4.000

14.700

0.120
1.800

12.600

0.080
1.200

1.500

0.080
2.800

3.600

0.800
1.600

6.600

MC

––

0.240

0.160

0.120

0.080

MCR

––

0.120

0.080

0.060

0.040

FEND
END

App-66

When not executed

Error check performed

250.000

250.000

250.000

250.000

250.000

250.000

175.000

252.000

No error check performed

250.000

250.000

250.000

250.000

250.000

250.000

175.000

221.000

Processing Time (µs)
Category Instruction

Condition (Device)

Q00UJCPU
Min.

Sequence
instruction

Q00UCPU
Min.

Max.

Q01UCPU
Min.

Max.

Q02UCPU
Min.

Max.

8

NOP
NOPLF

––

0.120

0.080

0.060

0.040

PAGE
LDE=

ANDE=

ORE=

LDE< >

ANDE< >

ORE< >

LDE>

Basic

Max.

ANDE>

instruction

LDE<=

ANDE<=

ORE<=

LDE<

ANDE<

ORE<

In conductive status

4.400

20.900

4.400

20.900

4.400

20.900

4.700

10.100

precision

In non-conductive status

4.400

20.900

4.400

20.900

4.400

20.900

4.700

10.100

Single
precision

Single

When not executed
When

In conductive status

executed In non-conductive status
When not executed
In conductive status

0.360

0.240

0.180

0.120

4.200

19.600

4.200

19.600

4.200

19.600

4.200

12.500

4.200

19.600

4.200

19.600

4.200

19.600

4.400

11.900

0.360

0.240

0.180

0.120

4.200

17.400

4.200

17.400

4.200

17.400

4.600

10.800

executed In non-conductive status

4.200

17.400

4.200

17.400

4.200

17.400

4.500

9.800

Single

In conductive status

4.400

20.900

4.400

20.900

4.400

20.900

4.700

7.700

precision

In non-conductive status

4.400

20.900

4.400

20.900

4.400

20.900

4.600

8.200

precision

Single
precision

Single

When

When not executed
When

In conductive status

executed In non-conductive status
When not executed
In conductive status

0.360

0.240

0.180

0.120

4.200

19.600

4.200

19.600

4.200

19.600

4.300

14.200

4.200

19.600

4.200

19.600

4.200

19.600

4.400

14.200

0.360

0.240

0.180

17.400

4.200

17.400

4.200

17.400

4.600

6.700

executed In non-conductive status

4.200

17.400

4.200

17.400

4.200

17.400

4.400

6.600

Single

In conductive status

4.400

20.900

4.400

20.900

4.400

20.900

4.700

13.700

precision

In non-conductive status

4.400

20.900

4.400

20.900

4.400

20.900

4.600

13.700

precision

Single
precision

Single

When not executed
When

In conductive status

executed In non-conductive status
When not executed
In conductive status

0.360

0.240

0.180

4.200

19.600

4.200

19.600

4.200

19.600

4.300

8.100

4.200

19.600

4.200

19.600

4.200

19.600

4.200

8.100

0.360

0.240

0.180

0.120

17.400

4.200

17.400

4.200

17.400

4.600

executed In non-conductive status

4.200

17.400

4.200

17.400

4.200

17.400

4.400

8.100

Single

In conductive status

4.400

20.900

4.400

20.900

4.400

20.900

4.700

11.100

precision

In non-conductive status

4.400

20.900

4.400

20.900

4.400

20.900

4.700

9.600

precision

Single
precision

Single

When not executed
When

In conductive status

executed In non-conductive status
When not executed
In conductive status

0.360

0.240

0.180

8.500

0.120

4.200

19.600

4.200

19.600

4.200

19.600

4.100

7.800

4.200

19.600

4.200

19.600

4.200

19.600

4.400

8.200

0.360

0.240

0.180

0.120

4.200

17.400

4.200

17.400

4.200

17.400

4.500

executed In non-conductive status

4.200

17.400

4.200

17.400

4.200

17.400

4.400

9.800

Single

In conductive status

4.400

20.900

4.400

20.900

4.400

20.900

4.700

11.500

precision

In non-conductive status

4.400

20.900

4.400

20.900

4.400

20.900

4.700

10.900

precision

Single
precision

Single
precision

When

When not executed
When

In conductive status

executed In non-conductive status
When not executed
When

In conductive status

executed In non-conductive status

0.360

0.240

0.180

10.300

0.120

4.200

19.600

4.200

19.600

4.200

19.600

4.300

9.200

4.200

19.600

4.200

19.600

4.200

19.600

4.400

9.400

0.360

0.240

0.180

8
A
6
7
8

0.120

4.200

When

8

0.120

4.200

When

8

0.120

4.200

17.400

4.200

17.400

4.200

17.400

4.600

10.400

4.200

17.400

4.200

17.400

4.200

17.400

4.400

9.800

App-67

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

ORE>

Single

Processing Time (µs)
Category

Instruction

LDE>=

ANDE>=

ORE>=

LDED=

ANDED=

ORED=

LDED<>

Basic

ANDED<>

instruction

ORED<>

LDED>

ANDED>

ORED>

LDED<=

ANDED<=

ORED<=

App-68

Condition (Device)

Q00UJCPU

Max.

Min.

Max.

Min.

Max.

20.900

4.400

20.900

4.400

20.900

4.700

12.200

20.900

4.400

20.900

4.400

20.900

4.700

11.800

Single

In conductive status
In non-conductive status

4.400

precision

Single

When

In conductive status

executed In non-conductive status
When not executed
In conductive status

Q02UCPU

Min.

precision
Single

Q01UCPU

Max.

4.400

When not executed

Q00UCPU

Min.

0.360

0.240

0.180

0.120

4.200

19.600

4.200

19.600

4.200

19.600

4.100

6.700

4.200

19.600

4.200

19.600

4.200

19.600

4.400

7.000

0.360

0.240

0.180

0.120

4.200

17.400

4.200

17.400

4.200

17.400

4.600

14.000

executed In non-conductive status

4.200

17.400

4.200

17.400

4.200

17.400

4.500

14.300

Double

In conductive status

4.700

37.400

4.700

37.400

4.700

37.400

4.200

21.000

precision

In non-conductive status

4.700

37.400

4.700

37.400

4.700

37.400

5.100

21.900

precision

Double
precision

Double

When

When not executed
When

In conductive status

executed In non-conductive status
When not executed
In conductive status

0.360

0.240

0.180

0.120

4.500

34.700

4.500

34.700

4.500

34.700

3.800

17.800

4.500

34.700

4.500

34.700

4.500

34.700

4.100

18.100

0.360

0.240

0.180

0.120

4.700

33.200

4.700

33.200

4.700

33.200

4.100

23.800

executed In non-conductive status

4.700

33.200

4.700

33.200

4.700

33.200

4.900

25.500

Double

In conductive status

4.700

37.400

4.700

37.400

4.700

37.400

5.100

23.500

precision

In non-conductive status

4.700

37.400

4.700

37.400

4.700

37.400

4.200

22.600

precision

Double
precision

Double

When

When not executed
When

In conductive status

executed In non-conductive status
When not executed
In conductive status

0.360

0.240

0.180

0.120

4.500

34.700

4.500

34.700

4.500

34.700

4.000

18.800

4.500

34.700

4.500

34.700

4.500

34.700

4.000

18.700

0.360

0.240

0.180

0.120

4.700

33.200

4.700

33.200

4.700

33.200

5.000

25.200

executed In non-conductive status

4.700

33.200

4.700

33.200

4.700

33.200

4.100

23.400

Double

In conductive status

4.700

37.400

4.700

37.400

4.700

37.400

5.100

25.100

precision

In non-conductive status

4.700

37.400

4.700

37.400

4.700

37.400

4.200

23.400

precision

Double
precision

Double

When

When not executed
When

In conductive status

executed In non-conductive status
When not executed
In conductive status

0.360

0.240

0.180

0.120

4.500

34.700

4.500

34.700

4.500

34.700

4.000

19.500

4.500

34.700

4.500

34.700

4.500

34.700

4.100

19.700

0.360

0.240

0.180

0.120

4.700

33.200

4.700

33.200

4.700

33.200

5.000

24.200

executed In non-conductive status

4.700

33.200

4.700

33.200

4.700

33.200

4.900

25.800

Double

In conductive status

4.700

37.400

4.700

37.400

4.700

37.400

4.200

22.500

precision

In non-conductive status

4.700

37.400

4.700

37.400

4.700

37.400

4.200

13.500

precision

Double
precision

Double
precision

When

When not executed
When

In conductive status

executed In non-conductive status
When not executed
When

In conductive status

executed In non-conductive status

0.360

0.240

0.180

0.120

4.500

34.700

4.500

34.700

4.500

34.700

4.000

19.600

4.500

34.700

4.500

34.700

4.500

34.700

4.100

19.700

0.360

0.240

0.180

0.120

4.700

33.200

4.700

33.200

4.700

33.200

5.000

26.300

4.700

33.200

4.700

33.200

4.700

33.200

5.000

25.200

Processing Time (µs)
Category

Instruction

LDED<

ANDED<

ORED<

LDED>=

ANDED>=

ORED>=

LD$=

Condition (Device)

Basic
instruction

LD$>

LD$<=

4.700

37.400

5.100

25.000

precision

In non-conductive status

4.700

37.400

4.700

37.400

4.700

37.400

4.200

24.100

Double
precision

Double
precision

When not executed

0.360

0.240

0.180

0.120

When

In conductive status

4.500

34.700

4.500

34.700

4.500

34.700

4.000

19.400

executed

In non-conductive status

4.500

34.700

4.500

34.700

4.500

34.700

4.100

19.700

When not executed
When
executed

0.360

0.240

0.180

0.120

In conductive status

4.700

33.200

4.700

33.200

4.700

33.200

5.000

25.100

In non-conductive status

4.700

33.200

4.700

33.200

4.700

33.200

5.000

25.100

Double

In conductive status

4.700

37.400

4.700

37.400

4.700

37.400

4.200

13.100

precision

In non-conductive status

4.700

37.400

4.700

37.400

4.700

37.400

4.300

13.100

Double
precision

Double
precision

When not executed

0.360

0.240

0.180

0.120

When

In conductive status

4.500

34.700

4.500

34.700

4.500

34.700

3.900

19.500

executed

In non-conductive status

4.500

34.700

4.500

34.700

4.500

34.700

4.100

19.800

When not executed

0.360

0.240

0.180

0.120

When

In conductive status

4.700

33.200

4.700

33.200

4.700

33.200

5.000

25.100

executed

In non-conductive status

4.700

33.200

4.700

33.200

4.700

33.200

4.200

18.500

In conductive status

8.300

38.500

8.300

38.500

8.300

38.500

5.500

14.900

In non-conductive status

8.300

38.500

8.300

38.500

8.300

38.500

5.500

15.600

When executed

When executed

0.360

0.240

0.180

In conductive status

7.200

37.300

7.200

37.300

7.200

37.300

5.200

13.800

7.200

37.300

7.200

37.300

7.200

37.300

5.300

14.500

0.360

0.240

0.180

7.500

36.600

7.500

36.600

7.500

36.600

5.500

14.900

In non-conductive status

7.500

36.600

7.500

36.600

7.500

36.600

5.300

14.600

In conductive status

8.300

39.300

8.300

39.300

8.300

39.300

5.600

15.200

In non-conductive status

8.300

39.300

8.300

39.300

8.300

39.300

5.600

15.400

When executed

0.240

0.180

0.120

In conductive status

8.000

38.200

8.000

38.200

8.000

38.200

4.300

21.500

In non-conductive status

8.000

38.200

8.000

38.200

8.000

38.200

4.500

23.400

0.360

0.240

0.180

0.120

In conductive status

8.300

37.300

8.300

37.300

8.300

37.300

5.400

17.700

In non-conductive status

8.300

37.300

8.300

37.300

8.300

37.300

5.300

19.400

In conductive status

8.300

41.600

8.300

41.600

8.300

41.600

6.400

19.200

In non-conductive status

8.300

41.600

8.300

41.600

8.300

41.600

5.600

20.100

When executed

When executed

When executed

0.360

0.240

0.180

0.120

In conductive status

8.000

38.100

8.000

38.100

8.000

38.100

4.500

15.400

In non-conductive status

8.000

38.100

8.000

38.100

8.000

38.100

4.600

15.300

0.360

0.240

0.180

0.120

In conductive status

8.200

35.700

8.200

35.700

8.200

35.700

5.400

20.000

In non-conductive status

8.200

35.700

8.200

35.700

8.200

35.700

5.400

22.100

In conductive status

8.300

39.200

8.300

39.200

8.300

39.200

5.800

12.800

In non-conductive status

8.300

39.200

8.300

39.200

8.300

39.200

6.300

13.900

When executed

0.360

0.240

0.180

8
8
8
A
6
7
8

0.120

In conductive status

0.360

8

0.120

In non-conductive status

When not executed
AND$<=

Max.

37.400

When not executed
OR$>

Min.

4.700

When not executed
AND$>

Max.

37.400

When not executed
OR$< >

Min.

4.700

When not executed
AND$< >

Q02UCPU

Max.

0.120

In conductive status

7.100

36.500

7.100

36.500

7.100

36.500

6.000

16.000

In non-conductive status

7.100

36.500

7.100

36.500

7.100

36.500

6.100

16.200

App-69

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

LD$< >

Q01UCPU

Min.

In conductive status

When not executed
OR$=

Q00UCPU

Max.

Double

When not executed
AND$=

Q00UJCPU
Min.

Processing Time (µs)
Category

Instruction

Condition (Device)

Q00UJCPU
Min.

When not executed
OR$<=

When
executed

LD$<

7.400

35.600

7.400

35.600

7.400

35.600

4.700

14.600

35.600

7.400

35.600

7.400

35.600

4.600

14.400

7.400

40.000

7.400

40.000

7.400

40.000

4.800

17.000

40.000

7.400

40.000

7.400

40.000

5.500

18.000

BKCMP<> S1 S2

D

n

Basic
instruction

BKCMP> S1 S2

BKCMP<= S1 S2

BKCMP< S1 S2

n

D

n

D

BKCMP>= S1 S2

n

D

DBKCMP = S1 S2

D

n

DBKCMP<> S1 S2

D

n

DBKCMP> S1 S2

DBKCMP<= S1 S2

DBKCMP< S1 S2

DBKCMP>= S1 S2

App-70

n

D

n

D

n

D

n

D

D

n

0.240

0.180

0.120

In conductive status

8.000

37.300

8.000

37.300

8.000

37.300

5.900

13.400

8.000

37.300

8.000

37.300

8.000

37.300

6.200

14.500

0.360

0.240

0.180

0.120

In conductive status

8.300

35.600

8.300

35.600

8.300

35.600

6.200

18.700

In non-conductive status

8.300

35.600

8.300

35.600

8.300

35.600

5.400

19.700

In conductive status

7.400

38.300

7.400

38.300

7.400

38.300

4.800

10.000

In non-conductive status

7.400

38.300

7.400

38.300

7.400

38.300

5.500

11.200

When
executed
n

0.360

In non-conductive status

0.360

0.240

0.180

0.120

In conductive status

7.200

37.300

7.200

37.300

7.200

37.300

4.400

21.600

In non-conductive status

7.200

37.300

7.200

37.300

7.200

37.300

4.500

21.800

When not executed

D

Max.

0.120

7.400

When
executed

BKCMP = S1 S2

0.180

Q02UCPU
Min.

7.400

When not executed

OR$>=

Max.

In conductive status

When
executed

AND$>=

0.240

Q01UCPU
Min.

In conductive status

When not executed

LD$>=

Max.

In non-conductive status

When
executed

OR$<

0.360

Q00UCPU
Min.

In non-conductive status

When not executed
AND$<

Max.

0.360

0.240

0.180

0.120

In conductive status

8.200

36.400

8.200

36.400

8.200

36.400

5.400

15.400

In non-conductive status

8.200

36.400

8.200

36.400

8.200

36.400

5.300

15.300

8.200

22.600

n=1

15.300 36.100 15.300 36.100 15.300 36.100

n = 96

64.500 85.500 64.500 85.500 64.500 85.500 57.400 72.500

n=1

15.300 36.100 15.300 36.100 15.300 36.100

n = 96

66.600 87.500 66.600 87.500 66.600 87.500 59.500 74.500

8.200

22.500

n=1

15.300 36.100 15.300 36.100 15.300 36.100

n = 96

66.600 87.500 66.600 87.500 66.600 87.500 59.500 74.400

8.200

23.100

n=1

15.300 36.100 15.300 36.100 15.300 36.100

n = 96

64.500 85.500 64.500 85.500 64.500 85.500 57.400 72.400

8.200

22.500

n=1

15.300 36.100 15.300 36.100 15.300 36.100

n = 96

66.600 87.500 66.600 87.500 66.600 87.500 59.500 74.500

8.300

23.000

n=1

15.300 36.100 15.300 36.100 15.300 36.100

n = 96

64.500 85.500 64.500 85.500 64.500 85.500 57.400 72.400

8.200

22.500

n=1

15.800 36.300 15.800 36.300 15.800 36.300

n = 96

64.900 85.700 64.900 85.700 64.900 85.700 60.700 78.400

9.350

29.000

n=1

15.700 36.300 15.700 36.300 15.700 36.300

n = 96

67.000 87.700 67.000 87.700 67.000 87.700 62.500 80.300

9.350

28.900

n=1

15.800 36.300 15.800 36.300 15.800 36.300

n = 96

67.000 87.700 67.000 87.700 67.000 87.700 62.600 80.300

9.350

29.000

n=1

15.700 36.300 15.700 36.300 15.700 36.300

n = 96

64.800 85.700 64.800 85.700 64.800 85.700 60.800 78.400

9.350

29.000

n=1

15.800 36.300 15.800 36.300 15.800 36.300

n = 96

67.000 87.700 67.000 87.700 67.000 87.700 62.700 80.400

n=1

15.700 36.300 15.700 36.300 15.700 36.300

n = 96

64.800 85.700 64.800 85.700 64.800 85.700 60.700 78.400

9.350

9.300

29.000

29.000

Processing Time (µs)
Category

Instruction

DB + S

D

DB + S1 S2
DB - S

Condition (Device)

D

D

Q00UJCPU

Q00UCPU

Q01UCPU

Q02UCPU

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

When executed

5.750

13.300

5.750

13.300

5.750

13.300

4.900

7.500

When executed

5.650

13.200

5.650

13.200

5.650

13.200

5.200

11.000

When executed

5.750

12.700

5.750

12.700

5.750

12.700

4.900

10.200

DB - S1 S2

D

When executed

5.650

12.600

5.650

12.600

5.650

12.600

5.200

8.600

DB * S1 S2

D

When executed

8.750

40.200

8.750

40.200

8.750

40.200

8.300

22.200

When executed

5.750

21.500

5.750

21.500

5.750

21.500

6.100

19.200

DB/ S1 S2

ED + S

D

Double
precision

D

ED + S1 S2

ED -

S

Double
precision

D

Double
precision

D

ED - S1 S2

Double
precision

D

ED * S1 S2

Double
precision

D

Basic
instruction ED / S1 S2

D

DBK + S1 S2

DBK - S1 S2

DFLTD

INTD

DINTD

4.500

26.700

4.500

26.700

4.500

26.700

4.800

16.800

= 21023,

D

= 21023

5.800

32.900

5.800

32.900

5.800

32.900

4.800

16.800

= 0,

S2

=0

5.450

35.400

5.450

35.400

5.450

35.400

7.100

20.100

= 21023,

S2

= 21023

6.750

41.400

6.750

41.400

6.750

41.400

7.100

20.100

= 0,

D

=0

5.200

25.900

5.200

25.900

5.200

25.900

5.000

17.300

= 21023,

D

= 21023

6.000

27.700

6.000

27.700

6.000

27.700

5.000

17.300

= 0,

S2

=0

5.550

32.900

5.550

32.900

5.550

32.900

6.000

16.300

= 21023,

S2

= 21023

5.750

33.900

5.750

33.900

5.750

33.900

6.000

16.300

= 0,

S2

=0

5.550

34.400

5.550

34.400

5.550

34.400

10.500

22.300

S1

= 21023,

S2

= 21023

5.950

39.100

5.950

39.100

5.950

39.100

10.500

22.300

S1

= 21023,

S2

= 21023

8.050

44.200

8.050

44.200

8.050

44.200

7.500

27.200

S

S1
S1

S
S

S1
S1

S1

n

D

D

n

n

n=1

13.500

28.500

13.500

28.500

13.500

28.500

12.100

19.700

n = 96

63.100

78.200

63.100

78.200

63.100

78.200

61.700

69.300

n=1

13.500

28.500

13.500

28.500

13.500

28.500

12.100

20.600

n = 96

63.100

78.200

63.100

78.200

63.100

78.200

61.700

70.200

n=1

10.100

24.200

10.100

24.200

10.100

24.200

7.050

19.200

n = 96

59.800

73.900

59.800

73.900

59.800

73.900

59.400

68.900

n=1

10.100

24.200

10.100

24.200

10.100

24.200

7.050

19.900

n = 96

59.800

73.900

59.800

73.900

59.800

73.900

59.400

69.600

––

15.400

64.300

15.400

64.300

15.400

64.300

14.400

34.000

––

19.700

71.000

19.700

71.000

19.700

71.000

9.200

22.900

=0

3.100

19.600

3.100

19.600

3.100

19.600

4.000

8.900

= 7FFFH

3.350

19.900

3.350

19.900

3.350

19.900

3.400

9.000

=0

3.200

20.400

3.200

20.400

3.200

20.400

4.100

10.800

= 7FFFFFFFH

3.450

20.500

3.450

20.500

3.450

20.500

3.600

10.800

=0

3.200

22.900

3.200

22.900

3.200

22.900

3.500

9.300

= 32766.5

4.100

34.300

4.100

34.300

4.100

34.300

5.100

19.500

=0

3.200

23.000

3.200

23.000

3.200

23.000

2.600

6.800

= 1234567890.3

4.050

33.500

4.050

33.500

4.050

33.500

3.400

11.700

D

$ + S1 S2
FLTD

=0

n

D

BK - S1 S2

D

D

Double
precision

S
S

Double
precision

S
S

Double
precision
Double
precision

S
S

S
S

App-71

8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

BK + S1 S2

$+ S

Double
precision

D

= 0,

S

8

Processing Time (µs)
Category

Instruction

Condition (Device)

Q00UCPU

Q01UCPU

Q02UCPU

Max.

Min.

Max.

Min.

Max.

Min.

Max.

DBL

When executed

3.300

5.900

3.300

5.900

3.300

5.900

2.700

3.800

WORD

When executed

3.000

7.250

3.000

7.250

3.000

7.250

2.900

7.000

GRY

When executed

3.350

7.500

3.350

7.500

3.350

7.500

2.700

6.100

DGRY

When executed

3.000

7.200

3.000

7.200

3.000

7.200

2.900

4.600

GBIN

When executed

4.600

9.700

4.600

9.700

4.600

9.700

4.000

8.200

DGBIN

When executed

5.550

10.700

5.550

10.700

5.550

10.700

5.500

8.000

NEG

When executed

3.300

6.850

3.300

6.850

3.300

6.850

2.400

4.100

DNEG

When executed

3.050

5.700

3.050

5.700

3.050

5.700

2.500

4.300

ENEG

EDNEG

BKBCD S

n

D

Floating point = 0

3.100

7.350

3.100

7.350

3.100

7.350

2.500

3.400

Floating point = -1.0

3.350

11.700

3.350

11.700

3.350

11.700

2.700

4.500

Floating point = 0

3.000

21.200

3.000

21.200

3.000

21.200

2.200

3.500

Floating point = -1.0

3.100

22.900

3.100

22.900

3.100

22.900

2.400

3.500

n=1

8.700

27.600

8.700

27.600

8.700

27.600

9.700

22.000

n = 96

84.200

104.000

84.200

104.000

84.200

104.000

74.200

86.500

n=1

8.450

28.100

8.450

28.100

8.450

28.100

8.900

16.300

n = 96

56.100

75.800

56.100

75.800

56.100

75.800

58.500

65.100

ECON

––

3.100

21.300

3.100

21.300

3.100

21.300

4.300

6.800

EDCON

––

5.050

24.000

5.050

24.000

5.050

24.000

2.800

5.400

––

2.900

22.900

2.900

22.900

2.900

22.900

3.200

7.800

6.250

30.100

6.250

30.100

6.250

30.100

4.500

13.900

15.500

39.300

15.500

39.300

15.500

39.300

15.400

17.500

n=1

8.400

20.900

8.400

20.900

8.400

20.900

8.700

15.200

BKBIN S

D

n

EDMOV

Character string to be
$MOV
Basic

transferred = 0
Character string to be
transferred = 32

instruction
BXCH D1 D2 n

n = 96

67.100

79.900

67.100

79.900

67.100

79.900

67.200

74.000

SWAP

––

3.300

3.550

3.300

3.550

3.300

3.550

2.400

2.700

GOEND

––

DI

––

8.400

1.800

EI

––

4.300

12.300

4.300

12.300

4.300

12.300

3.100

3.800

IMASK

––

12.900

40.600

12.900

40.600

12.900

40.600

9.800

25.000

IRET
RSF X n

RSF Y n

App-72

Q00UJCPU

Min.

––

0.550
2.800

8.400

1.000

0.550
2.800

8.400

0.550
2.800

1.000

0.500

1.000

2.200

1.000

n=1

7.500

26.500

7.500

26.500

7.500

26.500

4.300

16.100

n = 96

11.400

30.400

11.400

30.400

11.400

30.400

11.400

23.700

n=1

7.300

26.300

7.300

26.300

7.300

26.300

3.800

10.000

n = 96

10.900

29.900

10.900

29.900

10.900

29.900

8.500

15.200

UDCNT1

––

1.500

7.100

1.500

7.100

1.500

7.100

1.000

2.000

UDCNT2

––

1.500

6.300

1.500

6.300

1.500

6.300

1.000

4.000

TTMR

––

5.300

20.900

5.300

20.900

5.300

20.900

3.900

6.100

STMR

––

8.900

49.800

8.900

49.800

8.900

49.800

7.200

30.000

ROTC

––

52.300

52.600

52.300

52.600

52.300

52.600

15.200

16.100

RAMP

––

7.400

30.900

7.400

30.900

7.400

30.900

5.900

18.300

SPD

––

1.500

6.300

1.500

6.300

1.500

6.300

1.000

2.800

PLSY

––

6.400

7.100

6.400

7.100

6.400

7.100

3.500

4.700

PWM

––

3.900

4.600

3.900

4.600

3.900

4.600

3.400

3.400

MTR

––

10.100

61.400

10.100

61.400

10.100

61.400

20.500

28.400

Processing Time (µs)
Category

Instruction

Condition (Device)

BKAND S1 S2

n

D

BKOR S1 S2

n

D

BKXOR S1 S2

D

n

BKXNR S1 S2

D

n

BSFR D n

BSFL D n

SFTBR D n1 n2

SFTBL D n1 n2

SFTWR D n1 n2

SFTWL D n1 n2

Q00UCPU

Q01UCPU

Q02UCPU

Max.

Min.

Max.

Min.

Max.

Min.

Max.

n=1

13.600

28.500

13.600

28.500

13.600

28.500

12.100

20.100

n = 96

63.200

78.200

63.200

78.200

63.200

78.200

57.400

63.200

n=1

13.500

28.500

13.500

28.500

13.500

28.500

7.700

13.200

n = 96

63.100

78.200

63.100

78.200

63.100

78.200

57.400

62.800

n=1

13.600

28.300

13.600

28.300

13.600

28.300

7.800

13.200

n = 96

63.100

78.000

63.100

78.000

63.100

78.000

57.300

62.800

n=1

13.500

28.300

13.500

28.300

13.500

28.300

7.800

14.100

n = 96

63.100

78.000

63.100

78.000

63.100

78.000

57.400

62.900

n=1

5.050

21.100

5.050

21.100

5.050

21.100

3.700

6.300

n = 96

9.000

34.800

9.000

34.800

9.000

34.800

10.200

12.800

n=1

4.800

19.100

4.800

19.100

4.800

19.100

4.500

8.900

n = 96

8.550

34.300

8.550

34.300

8.550

34.300

10.100

14.300

n1 = 16 / n2 = 1

10.300

46.500

10.300

46.500

10.300

46.500

8.800

43.400

n1 = 16 / n2 = 15

10.300

46.400

10.300

46.400

10.300

46.400

8.750

43.400

n1 = 16 / n2 = 1

10.500

49.800

10.500

49.800

10.500

49.800

8.050

45.100

n1 = 16 / n2 = 15

10.500

49.800

10.500

49.800

10.500

49.800

8.050

45.100

n1 = 16 / n2 = 1

7.950

24.000

7.950

24.000

7.950

24.000

6.500

22.800

n1 = 16 / n2 = 15

7.950

24.100

7.950

24.100

7.950

24.100

6.500

22.800

n1 = 16 / n2 = 1

8.700

23.600

8.700

23.600

8.700

23.600

7.350

23.600

n1 = 16 / n2 = 15

8.650

23.700

8.650

23.700

8.650

23.700

7.300

23.700

n=1

4.550

4.750

4.550

4.750

4.550

4.750

3.000

3.400

n = 15

4.550

4.750

4.550

4.750

4.550

4.750

3.000

3.500

BSET D n
Application
instruction

Q00UJCPU

Min.

4.600

4.750

4.600

4.750

4.600

4.750

3.000

3.400

4.600

4.750

4.600

4.750

4.600

4.750

3.000

3.400

TEST

When executed

7.250

13.200

7.250

13.200

7.250

13.200

4.400

6.900

DTEST

When executed

6.950

12.900

6.950

12.900

6.950

12.900

4.500

7.000

BKRST D n

n

D

D

n

11.600

7.350

11.600

7.350

11.600

4.300

5.200

22.600

10.100

22.600

10.100

22.600

6.500

13.200

All match

6.650

6.800

6.650

6.800

6.650

6.800

5.000

5.300

6.650

6.800

6.650

6.800

6.650

6.800

5.000

5.300

n=

All match

34.000

42.300

34.000

42.300

34.000

42.300

32.300

35.900

96

None match

34.000

42.300

34.000

42.300

34.000

42.300

32.400

35.900

All match

8.000

16.300

8.000

16.300

8.000

16.300

6.800

10.200

None match

8.000

16.300

8.000

16.300

8.000

16.300

6.800

10.200

n=

All match

54.100

62.600

54.100

62.600

54.100

62.600

52.800

56.300

96

None match

54.100

62.600

54.100

62.600

54.100

62.600

52.800

56.300

=0

4.100

4.200

4.100

4.200

4.100

4.200

3.700

4.100

= FFFFFFFFH

4.100

4.200

4.100

4.200

4.100

4.200

3.800

4.100

n=2

8.850

23.000

8.850

23.000

8.850

23.000

6.000

16.400

n=8

13.600

36.600

13.600

36.600

13.600

36.600

8.100

15.200

7.650

11.900

7.650

11.900

7.650

11.900

5.300

6.300

n=1
DSER S1 S2

7.350
10.100

None match

n=1
SER S1 S2

n=1
n = 96

S

DSUM S

D
S

DECO S

D

n

n=2
ENCO S

D

n

n=8

M1 = ON
M4 = ON

7.500

11.700

7.500

11.700

7.500

11.700

5.200

6.200

M1 = ON

14.600

27.800

14.600

27.800

14.600

27.800

10.400

17.900

M256 = ON

10.600

23.700

10.600

23.700

10.600

23.700

5.700

13.300

App-73

8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

n=1
n = 15

BRST D n

8

Processing Time (µs)
Category

Instruction

DIS S

UNI S

n

D

n

D

Q00UCPU

Q01UCPU

Q02UCPU

Max.

Min.

Max.

Min.

Max.

Min.

Max.

n=1

6.500

14.800

6.500

14.800

6.500

14.800

5.000

10.900

n=4

6.900

15.200

6.900

15.200

6.900

15.200

5.400

11.300

n=1

6.800

15.100

6.800

15.100

6.800

15.100

5.500

8.900

n=4

7.500

15.900

7.500

15.900

7.500

15.900

6.200

9.600

When executed

4.750

18.700

4.750

18.700

4.750

18.700

11.000

16.300

NUNI

When executed

4.750

18.700

4.750

18.700

4.750

18.700

10.600

16.000

n=1

6.600

14.900

6.600

14.900

6.600

14.900

5.000

6.500

n = 96

37.700

46.100

37.700

46.100

37.700

46.100

36.000

38.400

n=1

7.350

15.600

7.350

15.600

7.350

15.600

5.100

6.100

n = 96

32.100

40.500

32.100

40.500

32.100

40.500

29.900

32.000

n=1

8.250

24.900

8.250

24.900

8.250

24.900

4.300

6.900

n = 96

34.200

51.600

34.200

51.600

34.200

51.600

32.000

34.300

n=1

8.250

24.800

8.250

24.800

8.250

24.800

4.400

6.800

n = 96

34.200

51.600

34.200

51.600

34.200

51.600

30.300

34.800

n=1

6.800

34.900

6.800

34.900

6.800

34.900

4.800

14.200

n = 96

60.300

89.200

60.300

89.200

60.300

89.200

56.400

68.000

n=1

7.600

35.700

7.600

35.700

7.600

35.700

4.800

9.300

n = 96

59.400

90.000

59.400

90.000

59.400

90.000

55.400

62.800

n=1

10.100

28.900

10.100

28.900

10.100

28.900

6.200

12.200

n = 96

52.100

92.400

52.100

92.400

52.100

92.400

6.200

13.100

n=1

9.300

29.000

9.300

29.000

9.300

29.000

6.200

10.500

n = 96

43.600

89.600

43.600

89.600

43.600

89.600

6.100

10.500

n=1

6.700

15.000

6.700

15.000

6.700

15.000

4.800

6.200

n = 96

28.900

37.100

28.900

37.100

28.900

37.100

26.900

28.700

n=1

8.600

26.800

8.600

26.800

8.600

26.800

5.500

7.000

n = 96

56.200

74.700

56.200

74.700

56.200

74.700

53.000

56.300

n=1

5.850

19.800

5.850

19.800

5.850

19.800

4.300

17.300

n = 96

17.300

38.200

17.300

38.200

17.300

38.200

16.000

35.500

n=1

6.900

23.300

6.900

23.300

6.900

23.300

5.750

21.900

n = 96

29.400

49.900

29.400

49.900

29.400

49.900

29.200

48.600

––

1.000

1.100

1.000

1.100

1.000

1.100

0.980

1.400

n

D

MAX S

MIN S

n

D

BTOW S

n

D

n

D

DMAX S

DMIN S

D

n

n

D

SORT S1 n S2 D1 D2

DSORT S1 n S2 D1 D2

instruction

Q00UJCPU
Min.

NDIS

WTOB S

Application

Condition (Device)

WSUM S

DWSUM S

MEAN S

n

D

D

n

D n

DMEAN S

D n

NEXT
BREAK
RET

FCALL Pn
FCALL Pn S1 to S5
ECALL * Pn
*: Program name
ECALL * Pn S1 to S5

––

4.700

25.000

4.700

25.000

4.700

25.000

21.300

17.900

Return to original program

4.100

19.500

4.100

19.500

4.100

19.500

2.000

3.000

Return to other program

4.700

16.700

4.700

16.700

4.700

16.700

2.300

4.900

Internal file pointer

5.400

5.400

5.400

5.400

5.400

5.400

3.300

5.300

Common pointer

7.600

30.500

7.600

30.500

7.600

30.500

4.900

6.600

––

50.400

62.700

50.400

62.700

50.400

62.700

19.800

23.700

––

105.000 214.000 105.000 214.000 105.000 214.000

75.700

134.000

––

164.000 271.000 164.000 271.000 164.000 271.000 109.000 173.000

––

105.000 214.000 105.000 214.000 105.000 214.000

76.200

134.000

––

164.000 271.000 164.000 271.000 164.000 271.000

90.500

170.000

3.800

6.400

*: Program name
EFCALL * Pn
*: Program name
EFCALL * Pn S1 to S5
*: Program name
XCALL

App-74

––

5.100

6.700

5.100

6.700

5.100

6.700

Processing Time (µs)
Category

Instruction

Condition (Device)

Q00UJCPU

Q01UCPU

Q02UCPU

Max.

Min.

Max.

Min.

Max.

Min.

Max.

18.100

89.100

18.100

89.100

18.100

89.100

12.800

79.000

33.300

132.000

33.300

132.000

33.300

132.000

24.900

119.000

33.300

132.000

33.300

132.000

33.300

132.000

24.900

119.000

78.600

231.000

78.600

231.000

78.600

231.000

54.000

212.000

78.600

231.000

78.600

231.000

78.600

231.000

54.000

212.000

18.100

89.000

18.100

89.000

18.100

89.000

12.800

79.000

15.700

71.600

15.700

71.600

15.700

71.600

8.600

76.500

40.200

152.000

40.200

152.000

40.200

152.000

26.300

135.000

45.800

153.000

45.800

153.000

45.800

153.000

26.100

135.000

––

––

––

––

––

––

––

––

18.200

89.000

18.200

89.000

18.200

89.000

7.250

54.300

Number of data points = 0

6.100

14.200

6.100

14.200

6.100

14.200

3.700

10.100

Number of data points = 96

6.100

14.200

6.100

14.200

6.100

14.200

3.800

5.200

When selecting I/O refresh only
When selecting CC-Link refresh
only (Master station side)
When selecting CC-Link refresh
only (Local station side)
When selecting MELSECNET/H
refresh only (Control station side)
When selecting MELSECNET/H
refresh only (Normal station side)
When selecting intelli auto
refresh only

COM
CCOM

Q00UCPU

Min.

When selecting I/O outside the
group only (Input only)
When selecting I/O outside the
group only (Output only)
When selecting I/O outside the
group only (Both I/O)
When selecting refresh of multiple CPU high speed transmission
area only
When selecting communication
with peripheral device

FIFW
Application
instruction

FIFR

FINS

FDEL

7.500

15.600

7.500

15.600

7.500

15.600

4.400

5.800

37.000

45.000

37.000

45.000

37.000

45.000

33.500

35.200

Number of data points = 0

7.600

15.600

7.600

15.600

7.600

15.600

4.400

10.800

Number of data points = 96

7.600

15.600

7.600

15.600

7.600

15.600

4.400

10.800

Number of data points = 0

6.900

15.000

6.900

15.000

6.900

15.000

5.000

10.700

Number of data points = 96

36.600

44.700

36.600

44.700

36.600

44.700

4.400

10.900

Number of data points = 0

8.000

16.100

8.000

16.100

8.000

16.100

4.900

11.300

Number of data points = 96

37.300

45.500

37.300

45.500

37.300

45.500

34.200

35.900

17.400

74.700

17.400

74.700

17.400

74.700

12.100

71.300

n3 = 1
FROM n1 n2 D n3

n3 = 1000

406.000 498.500 406.000 498.500 406.000 498.500 402.600 495.100

n3 = 1
DFRO n1 n2 D n3

19.600

n3 = 500
n3 = 1

TO n1 n2 S n3

16.400

n3 = 1000

19.600

85.600

14.600

81.800

69.600

16.400

69.600

16.400

69.600

11.700

63.400

85.100

18.600

85.100

18.600

85.100

14.200

78.500

1.500

7.100

1.500

7.100

1.500

7.100

5.100

5.100

38.900

109.000

38.900

109.000

38.900

109.000

35.700

89.200

=1

5.600

13.900

5.600

13.900

5.600

13.900

4.900

6.500

= -32768

7.800

16.200

7.800

16.200

7.800

16.200

7.200

8.700

=1

6.200

14.500

6.200

14.500

6.200

14.500

5.700

7.100

= -2147483648

11.000

19.200

11.000

19.200

11.000

19.200

10.400

12.200

LED instruction execution

S

no

D
S

S

DBINDA S

85.600

381.300 471.200 381.300 471.200 381.300 471.200 375.900 464.300

no display

display
BINDA S

18.600

n3 = 500
No display

LEDR

19.600

381.300 471.200 381.300 471.200 381.300 471.200 375.900 464.300

n3 = 1
DTO n1 n2 S n3

85.600

406.000 498.500 406.000 498.500 406.000 498.500 402.600 495.100

D
S

App-75

8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

FPOP

Number of data points = 0
Number of data points = 96

8

Processing Time (µs)
Category

Instruction

Condition (Device)

Min.

Max.

Min.

Max.

=1

5.050

13.400

5.050

13.400

5.050

13.400

4.400

5.900

= FFFFH

5.050

13.400

5.050

13.400

5.050

13.400

4.400

5.800

=1

5.600

13.900

5.600

13.900

5.600

13.900

5.200

6.700

= FFFFFFFFH

5.600

13.900

5.600

13.900

5.600

13.900

5.100

6.500

=1

4.850

13.200

4.850

13.200

4.850

13.200

4.300

5.800

= 9999

5.300

13.600

5.300

13.600

5.300

13.600

4.700

6.100

=1

5.300

13.600

5.300

13.600

5.300

13.600

4.800

6.300

= 99999999

6.200

14.500

6.200

14.500

6.200

14.500

5.600

7.100

=1

7.000

18.500

7.000

18.500

7.000

18.500

6.500

9.000

= -32768

6.950

18.500

6.950

18.500

6.950

18.500

6.300

8.900

=1

9.450

21.000

9.450

21.000

9.450

21.000

9.400

12.000

= -2147483648

9.450

21.000

9.450

21.000

9.450

21.000

9.100

11.600

=1

5.650

17.100

5.650

17.100

5.650

17.100

4.900

7.500

= FFFFH

5.750

17.300

5.750

17.300

5.750

17.300

5.100

8.100

=1

6.800

18.200

6.800

18.200

6.800

18.200

6.000

8.500

= FFFFFFFFH

7.100

18.600

7.100

18.600

7.100

18.600

6.300

8.900

=1

5.650

17.200

5.650

17.200

5.650

17.200

5.000

7.500

= 9999

5.700

17.200

5.700

17.200

5.700

17.200

5.000

7.500

=1

6.850

18.300

6.850

18.300

6.850

18.300

6.200

8.800

= 99999999

6.850

18.300

6.850

18.300

6.850

18.300

6.200

8.800

185.000 188.000 185.000 188.000 185.000 188.000

S
D
S

S
D
S

S

DBCDDA S

D
S

S
D
S

S

DDABIN S

D
S

Application
instruction

S

HABIN S

D
S

S

DHABIN S

D
S

S

DABCD S

D
S

S

DDABCD S

D
S

COMRD
LEN

App-76

Q02UCPU

Max.

D

DBINHA S

DABIN S

Q01UCPU

Min.

S

BCDDA S

Q00UCPU

Max.

S

BINHA S

Q00UJCPU

Min.

97.300

97.400

1 character

4.700

16.200

4.700

16.200

4.700

16.200

4.100

6.600

––

96 characters

20.600

32.900

20.600

32.900

20.600

32.900

19.800

22.400

STR

––

9.800

36.500

9.800

36.500

9.800

36.500

6.900

14.400

DSTR

––

12.100

40.400

12.100

40.400

12.100

40.400

10.200

20.800

VAL

––

12.200

40.900

12.200

40.900

12.200

40.900

9.800

23.900

DVAL

––

19.400

45.600

19.400

45.600

19.400

45.600

14.000

33.100

ESTR

––

29.700

87.800

29.700

87.800

29.700

87.800

22.100

52.400

Processing Time (µs)
Category

Instruction

Condition (Device)

EVAL

ASC S

HEX S

D

D

RIGHT S

LEFT S

D

Q01UCPU

Q02UCPU

Min.

Max.

Min.

Max.

Min.

Max.

Decimal point format
all 2-digit specification

23.900

70.400

23.900

70.400

23.900

70.400

23.300

36.500

Exponent format
all 6-digit specification

23.700

70.300

23.700

70.300

23.700

70.300

23.300

36.400

n=1

10.200

41.800

10.200

41.800

10.200

41.800

5.600

19.700

n = 96

31.900

66.600

31.900

66.600

31.900

66.600

30.200

44.700

n=1

8.600

43.400

8.600

43.400

8.600

43.400

7.500

23.100

n = 96

77.100

115.000

77.100

115.000

77.100

115.000

37.500

53.300

n=1

10.900

29.600

10.900

29.600

10.900

29.600

7.600

11.400

n = 96

41.400

60.300

41.400

60.300

41.400

60.300

36.300

46.000

n=1

10.600

29.300

10.600

29.300

10.600

29.300

6.500

16.100

n = 96

41.300

60.200

41.300

60.200

41.300

60.200

36.200

46.200

––

11.700

30.600

11.700

30.600

11.700

30.600

9.500

19.100

n

n

n

MIDR

––

12.400

24.000

12.400

24.000

12.400

24.000

10.300

18.200

No match

22.000

38.200

22.000

38.200

22.000

38.200

19.300

29.000

Head

13.300

29.600

13.300

29.600

13.300

29.600

10.300

20.000

End

21.900

38.100

21.900

38.100

21.900

38.100

51.100

60.800

MIDW

INSTR

Q00UCPU

Max.

n

D

Q00UJCPU

Min.

Match

EMOD

––

11.600

24.000

11.600

24.000

11.600

24.000

10.300

15.300

EREXP

––

19.700

28.000

19.700

28.000

19.700

28.000

19.300

22.300

47.000

102.000

47.000

102.000

47.000

102.000

44.300

96.700

70.100

134.000

70.100

134.000

70.100

134.000

58.800

112.000

46.400

93.600

46.400

93.600

46.400

93.600

39.000

78.100

44.500

70.600

44.500

70.600

44.500

70.600

36.000

69.200

S

= 128 /

D

= 40 /

n=1
STRINS S

D

n
S

= 128 /

D

= 40 /

8
8
8
8
A
6
7
8

n = 48
Application

= 128 /

D

= 40 /

n=1
STRDEL

S

D

n
S

= 128 /

D

= 40 /

n = 48
SIN

Single precision

6.400

13.900

6.400

13.900

6.400

13.900

4.500

9.900

COS

Single precision

6.100

13.500

6.100

13.500

6.100

13.500

4.300

8.200

TAN

Single precision

8.300

15.000

8.300

15.000

8.300

15.000

5.100

7.200

ASIN

Single precision

7.300

15.600

7.300

15.600

7.300

15.600

6.100

13.700

ACOS

Single precision

8.100

16.500

8.100

16.500

8.100

16.500

6.800

11.100

ATAN

Single precision

5.350

12.000

5.350

12.000

5.350

12.000

4.000

6.900

SIND

Double precision

13.400

51.300

13.400

51.300

13.400

51.300

9.600

26.000

COSD

Double precision

14.700

51.700

14.700

51.700

14.700

51.700

10.000

26.900

TAND

Double precision

17.400

54.400

17.400

54.400

17.400

54.400

11.400

25.300

ASIND

Double precision

22.600

60.300

22.600

60.300

22.600

60.300

12.100

30.800

ACOSD

Double precision

19.700

60.000

19.700

60.000

19.700

60.000

11.700

28.000

ATAND

Double precision

15.000

51.800

15.000

51.800

15.000

51.800

9.700

22.000

RAD

Single precision

3.200

10.300

3.200

10.300

3.200

10.300

2.500

4.800

RADD

Double precision

5.200

43.100

5.200

43.100

5.200

43.100

4.100

16.400

DEG

Single precision

3.200

11.500

3.200

11.500

3.200

11.500

2.500

4.700

DEGD

Double precision

5.150

43.800

5.150

43.800

5.150

43.800

5.000

18.100

SQR

Single precision

3.900

12.300

3.900

12.300

3.900

12.300

3.500

9.300

SQRD

Double precision

7.000

45.700

7.000

45.700

7.000

45.700

5.700

25.400

= -10

6.350

13.800

6.350

13.800

6.350

13.800

4.000

13.000

=1

6.350

13.800

6.350

13.800

6.350

13.800

4.000

13.000

EXP S

Single
D

S

precision
S

App-77

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

S

instruction

Processing Time (µs)
Category

Instruction

Double

EXPD S

LOG S

Condition (Device)

D

Min.

Max.

Min.

Max.

= -10

15.800

52.700

15.800

52.700

15.800

52.700

8.800

27.600

S

=1

15.400

52.500

15.400

52.500

15.400

52.500

8.500

27.300

S

=1

5.800

14.900

5.800

14.900

5.800

14.900

4.100

8.100

= 10

7.450

16.500

7.450

16.500

7.450

16.500

6.200

10.300

=1

11.000

48.900

11.000

48.900

11.000

48.900

9.500

28.300

= 10

12.600

51.300

12.600

51.300

12.600

51.300

11.100

29.900

precision
Double
D

S

precision

Q02UCPU

Max.

S

LOGD S

Q01UCPU

Min.

S

Single

Q00UCPU

Max.

precision

D

Q00UJCPU

Min.

S

RND

––

1.950

5.450

1.950

5.450

1.950

5.450

1.200

2.300

SRND

––

2.750

4.550

2.750

4.550

2.750

4.550

1.400

2.400

=0

2.500

6.800

2.500

6.800

2.500

6.800

1.800

3.300

= 9999

6.400

15.500

6.400

15.500

6.400

15.500

5.100

8.800

=0

2.600

6.050

2.600

6.050

2.600

6.050

1.900

3.700

= 99999999

8.450

17.600

8.450

17.600

8.450

17.600

7.500

10.900

S

BSQR S

D
S

S

BDSQR S

D
S

BSIN
Application BCOS
instruction
BTAN

––

11.500

32.800

11.500

32.800

11.500

32.800

8.700

20.200

––

10.400

32.500

10.400

32.500

10.400

32.500

7.800

14.400

––

12.100

33.700

12.100

33.700

12.100

33.700

9.000

17.000

BASIN

––

13.300

32.800

13.300

32.800

13.300

32.800

12.200

15.100

BACOS

––

13.400

33.700

13.400

33.700

13.400

33.700

13.100

14.900

BATAN

––

12.600

31.400

12.600

31.400

12.600

31.400

11.400

15.700

12.200

22.100

12.200

22.100

12.200

22.100

8.950

19.500

27.300

61.000

27.300

61.000

27.300

61.000

19.400

55.200

POW S1 S2

POWD S1 S2

App-78

S1

= 12.3 E + 5

S2

= 3.45 E + 0

Double

S1

= 12.3 E + 5

precision

S2

= 3.45 E + 0

Single
D

precision

D

LOG10

Single precision

8.200

16.500

8.200

16.500

8.200

16.500

5.950

14.800

LOG10D

Double precision

15.100

48.000

15.100

48.000

15.100

48.000

12.400

46.500

LIMIT

––

5.350

5.500

5.350

5.500

5.350

5.500

5.200

5.400

DLIMIT

––

6.000

6.150

6.000

6.150

6.000

6.150

5.700

5.900

BAND

––

5.450

12.400

5.450

12.400

5.450

12.400

5.400

6.300

DBAND

––

6.050

11.900

6.050

11.900

6.050

11.900

5.800

6.900

ZONE

––

6.250

10.700

6.250

10.700

6.250

10.700

5.200

11.100

DZONE

––

6.000

11.900

6.000

11.900

6.000

11.900

5.700

10.800

Processing Time (µs)
Category

Instruction

Condition (Device)

Q00UJCPU

Q00UCPU

Q01UCPU

Q02UCPU

8

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

14.900

50.100

14.900

50.100

14.900

50.100

14.700

48.000

8

15.800

50.900

15.800

50.900

15.800

50.900

19.600

50.400

8

13.900

53.100

13.900

53.100

13.900

53.100

13.700

51.000

8

16.600

56.600

16.600

56.600

16.600

56.600

20.400

56.200

13.400

52.400

13.400

52.400

13.400

52.400

12.800

50.300

14.200

54.100

14.200

54.100

14.200

54.100

17.300

53.500

Point No.1

SM750
= ON

< S1 <
Point No.2
Point No.9
< S1 <
Point No.10

SCL

S1 S2

D

Point No.1

SM750
= OFF

< S1 <
Point No.2
Point No.9
< S1 <
Point No.10

A

Point No.1

SM750
= ON

< S1 <
Point No.2

< S1 <
Point No.10
DSCL S1 S2

D

< S1 <
Point No.2

< S1 <
Point No.10

instruction

Point No.1
< S1 <
Point No.2

12.300

53.200

12.300

53.200

11.500

51.100

8
15.000

57.600

15.000

57.600

15.000

57.600

18.100

57.100

14.200

53.300

14.200

53.300

14.200

53.300

13.200

51.200

14.900

55.000

14.900

55.000

14.900

55.000

18.000

54.500

15.000

53.500

15.000

53.500

15.000

53.500

14.000

51.300

16.300

56.400

16.300

56.400

16.300

56.400

19.300

55.800

13.400

52.700

13.400

52.700

13.400

52.700

13.100

50.500

14.200

54.300

14.200

54.300

14.200

54.300

18.100

53.700

12.300

53.200

12.300

53.200

12.300

53.200

12.100

51.000

15.000

57.600

15.000

57.600

15.000

57.600

18.900

57.100

Point No.9
< S1 <
Point No.10

D

53.200

Point No.1

SM750
= OFF

< S1 <
Point No.2
Point No.9
< S1 <
Point No.10
Point No.1

SM750
= ON

< S1 <
Point No.2
Point No.9
< S1 <
Point No.10

DSCL2 S1 S2

D

Point No.1

SM750
= OFF

< S1 <
Point No.2
Point No.9
< S1 <
Point No.10

App-79

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

SM750
= ON

12.300

Point No.9

Application

SCL2 S1 S2

7

Point No.1

SM750
= OFF

6

Point No.9

Processing Time (µs)
Category

Instruction

Condition (Device)

RSET

QDRSET

Q00UJCPU

Q01UCPU

Q02UCPU

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Standard RAM

6.800

26.900

6.800

26.900

6.800

26.900

3.000

16.400

SRAM card

––

––

––

––

––

––

3.000

16.400

SRAM card to standard RAM

––

––

––

––

––

––

230.000

327.000

Standard RAM to SRAM card

––

––

––

––

––

––

997.000

1066.000

SRAM card to standard ROM

––

––

––

––

––

––

525.000

690.000

Standard ROM to SRAM card

––

––

––

––

––

––

490.000

655.000

DATERD

––

5.600

27.800

5.600

27.800

5.600

27.800

5.100

14.700

DATEWR

––

7.800

42.100

7.800

42.100

7.800

42.100

7.100

23.000

No digit increase

14.200

41.200

14.200

41.200

14.200

41.200

6.500

13.100

QCDSET

DATE +

DATE -

Digit increase

14.200

41.200

14.200

41.200

14.200

41.200

5.700

21.200

No digit increase

15.100

41.200

15.100

41.200

15.100

41.200

6.500

11.500

Digit increase

15.100

41.200

15.100

41.200

15.100

41.200

5.700

17.200

SECOND

––

5.800

20.500

5.800

20.500

5.800

20.500

2.600

5.900

HOUR

––

6.200

22.500

6.200

22.500

6.200

22.500

3.000

5.300

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.400

8.200

25.500

8.200

25.500

6.500

25.500

8.200

25.500

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

Comparison
of specified
date
LDDT =

Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

When not executed
Application

Comparison

instruction

of specified
ANDDT=

date
Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

0.480

Comparison
of specified
ORDT=

date
Comparison
of current
date
Comparison
of specified
date

LDDT <>

Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

0.320

0.240

0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.200

23.400

8.200

25.500

8.200

25.500

6.500

25.500

7.200

23.400

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

When not executed

App-80

Q00UCPU

0.480

0.320

0.240

0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.300

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.300

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.400

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.400

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

Processing Time (µs)
Category

Instruction

Condition (Device)

Q00UJCPU

Min.
When not executed
Comparison
of specified
ANDDT<>

date
Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

of specified
ORDT<>

date
Comparison
of current
date
Comparison
of specified
date

LDDT>

Comparison
of current
date

Application

status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

of specified
ANDDT>

date
Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

of specified
ORDT>

date
Comparison
of current
date
Comparison
of specified
date

LDDT<=

Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

0.320

Max.

Min.

0.240

0.160

8.200

25.500

6.500

25.500

7.200

23.400

8.200

25.500

8.200

25.500

6.500

25.500

7.200

23.400

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

0.480

0.320

0.240

25.500

8.200

25.500

6.500

25.500

7.400

23.300

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.300

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.400

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.400

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

0.320

0.240

0.160

8.200

25.500

8.200

25.500

8.200

25.500

7.200

23.400

8.200

25.500

8.200

25.500

8.200

25.500

7.200

23.400

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

0.480

0.320

8
8
8

0.160

8.200

0.480

8

Max.

25.500

When not executed
Comparison

Min.

Q02UCPU

8.200

When not executed
Comparison

Max.

Q01UCPU

0.240

0.160

8.200

25.500

8.200

25.500

8.200

25.500

7.400

23.300

8.200

25.500

8.200

25.500

8.200

25.500

7.400

23.300

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.400

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.400

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

App-81

A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

instruction

In conductive

Min.

0.480

When not executed
Comparison

Max.

Q00UCPU

Processing Time (µs)
Category

Instruction

Condition (Device)

Q00UJCPU

Min.
When not executed
Comparison
of specified
ANDDT<=

date
Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

When not executed
Comparison
of specified
ORDT<=

date
Comparison
of current
date
Comparison
of specified
date

LDDT<

Comparison
of current
date

Application
instruction

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

When not executed
Comparison
of specified
ANDDT<

date
Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

When not executed
Comparison
of specified
ORDT<

date
Comparison
of current
date
Comparison
of specified
date

LDDT>=

Comparison
of current
date

App-82

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

Max.
0.480

Q00UCPU

Min.

Max.
0.320

Q01UCPU

Min.

Max.
0.240

Q02UCPU

Min.

Max.
0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.200

23.400

8.200

25.500

8.200

25.500

6.500

25.500

7.200

23.400

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

0.480

0.320

0.240

0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.300

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.300

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.400

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.400

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

0.480

0.320

0.240

0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.200

23.400

8.200

25.500

8.200

25.500

6.500

25.500

7.200

23.400

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

0.480

0.320

0.240

0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.300

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.300

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.400

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.400

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

Processing Time (µs)
Category

Instruction

Condition (Device)

Q00UJCPU

Min.
When not executed
Comparison
of specified
ANDDT>=

date
Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

When not executed
Comparison
of specified
ORDT>=

date
Comparison
of current
date
Comparison
of specified
ciock

LDTM=

Comparison
of current
ciock

Application

status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

When not executed
Comparison
of specified
ANDTM=

ciock
Comparison
of current
ciock

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

When not executed
Comparison
of specified
ORTM=

ciock
Comparison
of current
ciock
Comparison
of specified
ciock

LDTM<>

Comparison
of current
ciock

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

0.480

Min.

Max.
0.320

Q01UCPU

Min.

Max.
0.240

Q02UCPU

Min.

0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.200

23.400

8.200

25.500

8.200

25.500

6.500

25.500

7.200

23.400

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.200

0.480

0.320

0.240

25.500

8.200

25.500

6.500

25.500

7.400

23.300

8.200

25.500

8.200

25.500

6.500

25.500

7.400

23.300

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.300

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.300

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.100

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.100

0.320

0.240

0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.000

23.000

8.200

25.500

8.200

25.500

6.500

25.500

7.000

23.000

6.500

23.100

6.500

23.100

6.500

23.100

5.600

21.900

6.500

23.100

6.500

23.100

6.500

23.100

5.600

21.900

0.480

0.320

0.240

8
8
8

0.160

8.200

0.480

8

Max.

0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.200

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.300

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.300

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.100

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.100

App-83

A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

instruction

In conductive

Max.

Q00UCPU

Processing Time (µs)
Category

Instruction

Condition (Device)

Q00UJCPU

Min.
When not executed
Comparison
of specified
ANDTM<>

ciock
Comparison
of current
ciock

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

When not executed
Comparison
of specified
ORTM<>

ciock
Comparison
of current
ciock
Comparison
of specified
ciock

LDTM>

Comparison
of current
ciock

Application
instruction

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

When not executed
Comparison
of specified
ANDTM>

ciock
Comparison
of current
ciock

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

When not executed
Comparison
of specified
ORTM>

ciock
Comparison
of current
ciock
Comparison
of specified
ciock

LDTM<=

Comparison
of current
ciock

App-84

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

Max.
0.480

Q00UCPU

Min.

Max.
0.320

Q01UCPU

Min.

Max.
0.240

Q02UCPU

Min.

Max.
0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.000

23.000

8.200

25.500

8.200

25.500

6.500

25.500

7.000

23.000

6.500

23.100

6.500

23.100

6.500

23.100

5.600

21.900

6.500

23.100

6.500

23.100

6.500

23.100

5.600

21.900

0.480

0.320

0.240

0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.200

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.300

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.300

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.100

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.100

0.480

0.320

0.240

0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.000

23.000

8.200

25.500

8.200

25.500

6.500

25.500

7.000

23.000

6.500

23.100

6.500

23.100

6.500

23.100

5.600

21.900

6.500

23.100

6.500

23.100

6.500

23.100

5.600

21.900

0.480

0.320

0.240

0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.200

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.300

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.300

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.100

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.100

Processing Time (µs)
Category

Instruction

Condition (Device)

Q00UJCPU

Min.
When not executed
Comparison
of specified
ANDTM<=

ciock
Comparison
of current
ciock

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

When not executed
Comparison
of specified
ORTM<=

ciock
Comparison
of current
ciock
Comparison
of specified
ciock

LDTM<

Comparison
of current
ciock

Application

status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

When not executed
Comparison
of specified
ANDTM<

ciock
Comparison
of current
ciock

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

When not executed
Comparison
of specified
ORTM<

ciock
Comparison
of current
ciock
Comparison
of specified
ciock

LDTM>=

Comparison
of current
ciock

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

0.480

Min.

Max.
0.320

Q01UCPU

Min.

Max.
0.240

Q02UCPU

Min.

0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.000

23.000

8.200

25.500

8.200

25.500

6.500

25.500

7.000

23.000

6.500

23.100

6.500

23.100

6.500

23.100

5.600

21.900

6.500

23.100

6.500

23.100

6.500

23.100

5.600

21.900

0.480

0.320

0.240

25.500

8.200

25.500

6.500

25.500

7.300

23.200

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.300

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.300

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.100

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.100

0.320

0.240

0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.000

23.000

8.200

25.500

8.200

25.500

6.500

25.500

7.000

23.000

6.500

23.100

6.500

23.100

6.500

23.100

5.600

21.900

6.500

23.100

6.500

23.100

6.500

23.100

5.600

21.900

0.480

0.320

0.240

8
8
8

0.160

8.200

0.480

8

Max.

0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.200

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.200

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.000

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.300

8.200

25.500

8.200

25.500

6.500

25.500

7.300

23.300

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.100

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.100

App-85

A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

instruction

In conductive

Max.

Q00UCPU

Processing Time (µs)
Category

Instruction

Condition (Device)

Q00UJCPU

Min.
When not executed
In conductive

Comparison
of specified
ANDTM>=

ciock

status
In nonconductive
status
In conductive

Comparison
of current
ciock

status
In nonconductive
status

Max.
0.240

Min.

Max.
0.160

8.200

25.500

8.200

25.500

6.500

25.500

7.000

23.000

8.200

25.500

8.200

25.500

6.500

25.500

7.000

23.000

6.500

23.100

6.500

23.100

6.500

23.100

5.600

21.900

6.500

23.100

6.500

23.100

6.500

23.100

5.600

21.900

0.480

0.320

0.240

0.160

8.200

25.500

6.500

25.500

7.000

23.000

8.200

25.500

8.200

25.500

6.500

25.500

7.000

23.000

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.100

6.500

23.100

6.500

23.100

6.500

23.100

5.900

22.100

––

9.250

51.000

9.250

51.000

9.250

51.000

7.500

23.400

No digit increase

16.800

75.400

16.800

75.400

16.800

75.400

9.100

23.400

Digit increase

16.800

75.400

16.800

75.400

16.800

75.400

8.900

22.200

No digit increase

17.600

75.300

17.600

75.300

17.600

75.300

9.000

22.200

Digit increase

16.900

75.300

16.900

75.300

16.900

75.300

9.800

22.100

PSTOP

––

82.200

199.000

82.200

199.000

82.200

199.000

61.400

84.500

POFF

––

82.600

198.000

82.600

198.000

82.600

198.000 121.000 246.000

PSCAN

––

83.600

200.000

83.600

200.000

83.600

200.000 126.000 232.000

WDT

––

2.900

12.000

2.900

12.000

2.900

12.000

1.300

3.000

DUTY

––

7.700

27.500

7.700

27.500

7.700

27.500

4.900

24.300

TIMCHK

––

5.350

24.500

5.350

24.500

5.350

24.500

7.400

23.300

File register of standard RAM

4.100

4.200

4.100

4.200

4.100

4.200

2.400

2.600

ORTM>=

ciock

status
In nonconductive
status
In conductive

Comparison
of current
ciock
S.DATERD
S.DATE +

S.DATE -

ZRRDB

ZRWRB

App-86

Min.

0.320

Q02UCPU

25.500

of specified

instruction

Max.

Q01UCPU

8.200

Comparison

Application

Min.

0.480

When not executed
In conductive

Max.

Q00UCPU

status
In nonconductive
status

File register of SRAM card

––

––

––

––

––

––

2.500

2.800

File register of standard RAM

5.400

5.500

5.400

5.500

5.400

5.500

3.100

3.300

File register of SRAM card

––

––

––

––

––

––

3.300

3.600

ADRSET

––

2.400

6.650

2.400

6.650

2.400

6.650

4.200

4.900

ZPUSH

––

9.200

20.500

9.200

20.500

9.200

20.500

6.900

14.000

ZPOP

––

9.000

15.500

9.000

15.500

9.000

15.500

7.500

12.500

Processing Time (µs)
Category

Instruction

Condition (Device)

Q00UJCPU

Q00UCPU

Q01UCPU

Q02UCPU

8

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

29.400

91.700

29.400

91.700

29.400

91.700

20.600

55.000

8

29.500

91.600

29.500

91.600

29.500

91.600

20.600

66.100

8

79.900

214.000

79.900

214.000

79.900

214.000

102.000

180.000

When mounting CC-Link
module
(Master station side)
When mounting CC-Link
module
(Local station side)
When mounting
MELSECNET/H,

S.ZCOM

CC-Link IEcontroller
network module(Control

8

station side)
When mounting

A

MELSECNET/H,
CC-Link IEcontroller

79.900

214.000

79.900

214.000

79.900

214.000

29.800

102.000

network module(Normal

6

station side)
––

9.200

57.700

9.200

57.700

9.200

57.700

6.700

33.500

instruction

––

10.900

67.100

10.900

67.100

10.900

67.100

8.300

26.000

n2 = 1

6.000

33.100

6.000

33.100

6.000

33.100

4.000

29.100

n2 = 16

16.500

43.600

16.500

43.600

16.500

43.600

12.500

37.600

48.50

141.30

43.50

139.90

43.40

139.80

32.40

134.20

Start

174.000

174.000

174.000

174.000

174.000

174.000

96.600

103.000

––

5.100

15.500

5.100

15.500

5.100

15.500

3.800

13.600

––

––

12.200

34.900

12.200

34.900

9.400

31.300

––

––

121.500

145.100

121.500

145.100

118.500

141.300

––

––

––

––

––

––

9.400

31.400

––

––

––

––

––

––

178.500

201.300

S.RTWRITE
UNIRD n1 D n2
TYPERD
TRACE
TRACER

When standard
RAM is used
RBNOV S

D

n

When SRAM
card is used

1 point
1000
points
1 point
1000
points

SP.FWRITE

––

––

––

––

––

––

––

9.200

12.100

SP.FREAD

––

––

––

––

––

––

––

489.000

544.000

SP.DEVST

––

––

––

––

––

––

––

87.000

144.000

S.DEVLD

––

––

––

––

––

––

––

127.000

140.000

App-87

7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

Application S.RTREAD

Processing Time (µs)
Category

Instruction

Condition (Device)
Writing to host

S.TO n1 n2 n3 n4

CPU shared

D

memory
Writing to host
TO n1 n2

CPU shared

n3

S

memory
Writing to host
DTO n1 n2

CPU shared

n3

S

memory
Multiple

Reading from

CPU

host CPU shared

dedicated
instruction

memory
FROM n1 n2

D

n3

n3

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

64.600

78.100

64.600

78.100

64.600

78.100

64.600

78.100

115.000 126.000 115.000 126.000 115.000 126.000 154.000 126.000
12.700

62.200

12.700

62.200

8.300

58.200

n3 = 320

63.500

112.300

63.500

112.300

63.500

112.300

56.200

107.800

n3 = 1

13.500

62.300

13.500

62.300

13.500

62.300

8.600

58.300

n3 = 320

112.900 160.800 112.900 160.800 112.900 160.800 106.800 157.300

n3 = 1

12.100

58.700

12.100

58.700

12.100

58.700

8.400

52.600

n3 = 320

56.000

101.700

56.000

101.700

56.000

101.700

51.700

96.600

24.400

82.900

24.400

82.900

24.400

82.900

16.600

37.000

152.000 243.000 152.000 243.000 152.000 243.000 153.000 185.000

n3 = 1000 418.000 518.000 418.000 518.000 418.000 518.000 432.000 485.000
n3 = 1

12.100

58.700

12.100

58.700

12.100

58.700

8.800

53.400

n3 = 320

97.400

143.700

97.400

143.700

97.400

143.700

94.900

139.600

24.800

94.200

24.800

94.200

24.800

94.200

16.600

47.300

Reading from

n3 = 1

other CPU

n3 = 320

shared memory

Q02UCPU

62.200

n3 = 1

memory

Q01UCPU

12.700

n3 = 320

host CPU shared

Q00UCPU

n3 = 1

other CPU
Reading from

DFRO n1 n2

n4 = 320

Reading from
shared memory

D

n4 = 1

Q00UJCPU

276.000 367.000 276.000 367.000 276.000 367.000 278.000 339.000

n3 = 1000 799.000 892.000 799.000 892.000 799.000 892.000 841.000 892.000

Remark
For the instructions for which a rise execution instruction ( P) is not specified,
the processing time is the same as an ON execution instruction.
Example WORDP instruction and TOP instruction

App-88

(b) When using Q03UD(E)JCPU, Q04UD(E)HCPU, Q06UD(E)HCPU,
Q10UD(E)HCPU, Q13UD(E)HCPU, Q20UD(E)HCPU and Q26UD(E)HCPU

8

Processing Time (µs)
Category

Instruction

Condition (Device)

Q03UD(E)CPU
Min.

Max.

Q04/Q06UD(E)HCPU
Min.

Max.

Q10/Q13/Q20/
Q26UD(E)HCPU
Min.

Max.

8

ANB
ORB
MPS

––

0.020

0.0095

0.0095

8

0.020

0.0095

0.0095

8

0.020

0.0095

0.0095

0.020

0.0095

0.0095

MRD
MPP
INV

Sequence
instruction

When not executed
When executed

MEP

When not executed

MEF

When executed

EGP

When not executed

EGF

When executed

PLS

––

1.300

1.600

0.890

1.100

0.890

1.100

PLF

––

1.500

1.600

0.940

1.200

0.940

1.200

FF

DELTA

SFT
MC

A

When not executed
When executed

0.040
1.200

When not executed
When executed

––

1.500

0.790

0.040
2.800

When not executed
When executed

0.0185

3.600

1.600

0.0185
0.910

0.790

0.0185
2.400

0.040

3.200

1.100

0.040

2.400

2.700

1.100

2.700

0.0185

0.0185

FEND

108.000

130.000

75.800

89.300

75.800

89.300

No error check performed

107.000

124.000

75.800

89.800

75.800

89.800

NOP
––

0.020

0.0095

0.0095

PAGE

App-89

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

––

Error check performed

NOPLF

8

0.0185

MCR
END

7

3.200
0.0185

0.0185

0.040

0.910
0.0185

0.0185
3.300

6

Processing Time (µs)
Category Instruction

LDE=

ANDE=

ORE=

LDE< >

ANDE< >

ORE< >

LDE>

Basic

ANDE>

instruction

ORE>

LDE<=

ANDE<=

ORE<=

LDE<

ANDE<

ORE<

App-90

Condition (Device)

Single

In conductive status

precision

In non-conductive status

Single
precision

Single
precision

When not executed
When

Q03UD(E)CPU

Q04/
Q06UD(E)HCPU

Min.

Max.

Min.

Max.

Min.

Max.

3.700

4.700

3.300

4.300

3.300

4.300

3.800

5.000

3.400

4.500

3.400

4.500

In conductive status

0.060

0.0285

3.300

5.800

3.000

5.100

3.000

5.100

When not executed

3.500

5.600

3.000

5.200

3.000

5.200

4.500

3.200

When

In conductive status

executed In non-conductive status

0.060
3.600

0.0285
4.200

Single

In conductive status

3.500

4.800

3.200

4.300

In non-conductive status

4.000

4.700

3.600

4.200

When not executed

3.900

4.500

3.500

4.000

Single

Single
precision

When

In conductive status

0.060

executed In non-conductive status

3.300

5.100

3.000

4.800

When not executed

3.500

5.000

3.100

4.600

6.000

3.300

When

In conductive status

executed In non-conductive status

0.060
3.600

5.500

In conductive status

3.500

5.800

3.100

5.300

In non-conductive status

3.800

5.000

3.300

4.600

When not executed

3.700

4.900

3.300

4.400

Single
precision

When

In conductive status

0.060
3.500

4.700

3.100

4.200

When not executed

3.600

4.500

3.100

4.000

5.100

3.300

When

In conductive status

0.060
3.600

4.600

Single

In conductive status

3.500

4.800

3.200

4.500

In non-conductive status

3.800

5.600

3.400

5.200

When not executed

3.800

5.600

3.400

5.100

Single

Single
precision

When

In conductive status

0.060
3.200

4.600

2.800

4.200

When not executed

3.500

5.000

3.100

4.500

5.800

3.400

When

In conductive status

0.060
3.700

5.400

Single

In conductive status

3.800

5.700

3.300

5.300

In non-conductive status

4.000

5.400

3.500

4.900

When not executed

4.000

5.200

3.500

4.900

Single

Single
precision

When

In conductive status

0.060
3.400

4.600

3.000

4.200

When not executed

3.500

4.900

3.100

4.400

5.200

3.300

When

In conductive status

0.060
3.600

0.0285

0.0285

0.0285

0.0285

0.0285

0.0285

executed In non-conductive status

executed In non-conductive status

0.0285

0.0285

precision

precision

0.0285

0.0285

executed In non-conductive status

executed In non-conductive status

0.0285

0.0285

precision

precision

0.0285

0.0285

executed In non-conductive status

executed In non-conductive status

0.0285

0.0285

Single

Single

0.0285

0.0285

precision

precision

0.0285

executed In non-conductive status

precision

precision

Q10/Q13/Q20/
Q26UD(E)HCPU

0.0285
4.900

0.0285

0.0285

Processing Time (µs)
Category

Instruction

Condition (Device)

Q03UD(E)CPU
Min.

LDE>=

ANDE>=

ORE>=

LDED=

ANDED=

ORED=

LDED<>

Basic

ANDED<>

instruction

ORED<>

ANDED>

ORED>

LDED<=

ANDED<=

ORED<=

Min.

Max.

Single

In conductive status

3.800

6.000

3.300

5.500

precision

In non-conductive status

3.800

5.900

3.400

5.400

Single
precision

Single

When not executed
When

In conductive status

executed In non-conductive status
When not executed

Max.

0.0285

4.800

2.900

4.600

3.500

5.400

3.100

5.100

0.0285

5.200

3.300

4.700

3.500

5.200

3.200

4.700

Double

In conductive status

4.100

7.700

3.500

7.200

3.500

7.200

precision

In non-conductive status

4.300

8.100

3.800

7.400

3.800

7.400

Double
precision

Double
precision

When not executed
When

In conductive status

0.060

0.0285

0.0285

3.600

7.600

3.200

7.000

3.200

7.000

When not executed

3.900

7.700

3.400

7.400

3.400

7.400

In conductive status

0.060

0.0285

3.800

8.800

3.400

8.300

3.400

8.300

Double

In conductive status

4.000

9.300

3.700

8.800

3.700

8.800

precision

In non-conductive status

4.400

8.200

3.900

7.700

3.900

7.700

4.100

7.900

3.500

7.500

3.500

7.500

precision

Double
precision

When not executed
When

In conductive status

executed In non-conductive status
When not executed
When

In conductive status

executed In non-conductive status

0.060

0.0285

7.600

3.300

7.200

3.300

7.200

3.800

7.700

3.400

7.300

3.400

7.300

0.0285

0.0285

Double

In conductive status

4.100

9.300

3.700

8.900

3.700

8.900

precision

In non-conductive status

3.800

8.900

3.400

8.400

3.400

8.400

When not executed

4.300

8.100

3.800

7.500

3.800

7.500

4.100

7.800

3.500

7.200

3.500

7.200

Double
precision

Double
precision

When

In conductive status

executed In non-conductive status
When not executed
When

In conductive status

executed In non-conductive status

Double

In conductive status

precision

In non-conductive status

Double
precision

Double
precision

When not executed
When

In conductive status

executed In non-conductive status
When not executed
When

In conductive status

executed In non-conductive status

0.060

0.0285

0.0285

3.800

7.700

3.300

7.300

3.300

7.300

4.000

7.900

3.500

7.500

3.500

7.500

0.060
4.100

0.0285

0.0285

9.300

3.700

8.800

3.700

8.800

4.100

9.300

3.700

8.800

3.700

8.800

4.000

8.000

3.500

7.400

3.500

7.400

4.100

9.400

3.600

8.800

3.600

8.800

0.060
3.800

7.700

0.0285
3.300

7.200

A
6
7
8

0.0285

3.800

0.060

8

0.0285

executed In non-conductive status

Double

8

0.0285

executed In non-conductive status

When

8

0.0285

3.600

When

8

0.0285

3.200

0.060

Min.

executed In non-conductive status

precision

In conductive status

0.060

Q10/Q13/Q20/
Q26UD(E)HCPU

0.0285
3.300

7.200

App-91

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

LDED>

Max.

Q04/
Q06UD(E)HCPU

Processing Time (µs)
Category

Instruction

LDED<

ANDED<

ORED<

LDED>=

ANDED>=

ORED>=

LD$=

AND$=

Basic
instruction

Condition (Device)

Double

In conductive status

precision

In non-conductive status

Double
precision

Double
precision

When not executed
In conductive status

When
executed

In non-conductive status

When not executed
When

In conductive status

executed

In non-conductive status

LD$< >

AND$< >

LD$>

AND$>

LD$<=

AND$<=

App-92

Min.

Max.

Min.

Max.

Min.

Max.

4.300

8.300

3.800

7.600

3.800

7.600

3.700

7.900

3.500

7.400

3.500

7.400

0.060

0.0285

0.0285

3.800

7.800

3.300

7.300

3.300

7.300

3.900

7.900

3.400

3.900

3.400

3.900

0.060

0.0285

0.0285

4.100

9.600

3.700

9.200

3.700

9.200

In conductive status

4.000

9.600

3.700

9.200

3.700

9.200

In non-conductive status

4.100

9.600

3.600

9.000

3.600

9.000

4.100

9.600

3.600

8.900

3.600

8.900

Double
precision

Double
precision

When not executed
In conductive status

When
executed

In non-conductive status

When not executed
When

In conductive status

executed

In non-conductive status

0.060

0.0285

0.0285

3.800

7.900

3.400

7.400

3.400

7.400

3.900

8.100

3.400

7.500

3.400

7.500

0.060

0.0285

0.0285

In conductive status

4.100

9.600

3.700

9.200

3.700

9.200

In non-conductive status

4.000

7.200

3.600

6.600

3.600

6.600

When not executed

5.300

8.900

4.700

8.100

4.700

8.100

4.700

9.000

4.200

8.200

4.200

8.200

When executed

In conductive status
In non-conductive status

When executed

In conductive status
In non-conductive status

0.060

0.0285

0.0285

4.400

6.800

3.900

6.400

3.900

6.400

4.500

6.700

4.000

6.300

4.000

6.300

0.060

0.0285

0.0285

In conductive status

5.100

8.200

4.200

7.600

4.200

7.600

In non-conductive status

5.000

8.100

4.000

7.200

4.000

7.200

When not executed

4.800

8.100

4.300

7.500

4.300

7.500

4.700

8.400

4.200

7.800

4.200

7.800

When executed

In conductive status
In non-conductive status

When executed

In conductive status
In non-conductive status

0.060

0.0285

0.0285

4.300

5.500

4.100

5.100

4.100

5.100

4.500

5.900

4.400

5.400

4.400

5.400

0.060

0.0285

0.0285

In conductive status

5.200

7.300

4.100

6.700

4.100

6.700

In non-conductive status

5.100

7.200

4.100

6.700

4.100

6.700

When not executed

4.800

7.200

4.300

6.700

4.300

6.700

4.800

7.700

4.200

7.100

4.200

7.100

When executed

In conductive status
In non-conductive status

When not executed
OR$>

Q10/Q13/Q20/
Q26UD(E)HCPU

Double

When not executed
OR$< >

Q04/
Q06UD(E)HCPU

precision

When not executed
OR$=

Q03UD(E)CPU

When executed

In conductive status
In non-conductive status

0.060

0.0285

0.0285

4.500

7.100

4.000

6.700

4.000

6.700

4.600

7.600

4.300

7.000

4.300

7.000

0.060

0.0285

0.0285

In conductive status

5.100

6.800

4.300

6.200

4.300

6.200

In non-conductive status

5.200

7.200

4.300

6.600

4.300

6.600

When not executed

5.000

6.300

4.400

5.700

4.400

5.700

4.800

6.400

4.200

5.800

4.200

5.800

When executed

In conductive status
In non-conductive status

0.060

0.0285

0.0285

Processing Time (µs)
Category

Instruction

Condition (Device)

Q03UD(E)CPU
Min.

When not executed
OR$<=

When
executed

LD$<

7.200

4.400

7.200

In non-conductive status

7.600

4.400

7.100

4.400

7.100

4.800

8.100

4.500

7.500

4.500

7.500

In non-conductive status

5.000

8.300

4.500

7.900

4.500

7.900

In conductive status

4.500

7.100

4.000

6.600

4.000

6.600

4.900

7.500

4.400

7.100

4.400

7.100

Basic
instruction

BKCMP<> S1 S2

4.100

7.200

4.100

7.200

In non-conductive status

5.000

8.100

4.100

7.600

4.100

7.600

In conductive status

4.800

6.700

4.500

6.200

4.500

6.200

In non-conductive status

5.000

6.700

4.400

6.300

4.400

6.300

BKCMP<= S1 S2

BKCMP< S1 S2

n

D

n

D

n

D

BKCMP>= S1 S2

DBKCMP = S1 S2

DBKCMP<> S1 S2

DBKCMP> S1 S2

DBKCMP<= S1 S2

DBKCMP< S1 S2

DBKCMP>= S1 S2

n

D

D

n

n

D

n

D

n

D

n

D

D

n

0.0285

0.0285

In conductive status

4.400

6.800

4.100

6.300

4.100

6.300

In non-conductive status

4.500

7.000

4.200

6.600

4.200

6.600

In conductive status

0.060
5.400

6.600

0.0285
4.100

5.800

0.0285
4.100

A
6
7

5.800

5.300

6.300

4.100

5.700

4.100

5.700

n=1

8.200

10.700

7.500

10.000

7.500

10.000

n = 96

57.400

61.800

46.400

48.700

46.400

48.700

n=1

8.200

10.700

7.500

10.000

7.500

10.000

n = 96

59.500

63.300

45.600

50.400

45.600

50.400

n=1

8.200

10.800

7.500

10.100

7.500

10.100

n = 96

59.500

63.400

47.700

50.500

47.700

50.500

n=1

8.200

10.600

7.500

10.000

7.500

10.000

n = 96

57.400

61.700

46.400

49.000

46.400

49.000

n=1

8.300

10.600

7.500

10.000

7.500

10.000

n = 96

59.500

63.600

47.600

50.500

47.600

50.500

n=1

8.200

10.900

7.500

10.000

7.500

10.000

n = 96

57.400

62.000

46.400

48.900

46.400

48.900

n=1

9.250

14.000

8.600

13.000

8.600

13.000

n = 96

60.700

67.500

47.900

52.800

47.900

52.800

n=1

9.250

14.000

8.600

13.000

8.600

13.000

n = 96

60.700

67.500

47.900

52.800

47.900

52.800

n=1

9.250

14.000

8.600

13.000

8.600

13.000

n = 96

60.700

67.500

47.900

52.800

47.900

52.800

n=1

9.250

14.000

8.600

13.000

8.600

13.000

n = 96

60.700

67.500

47.900

52.800

47.900

52.800

n=1

9.250

14.000

8.600

13.000

8.600

13.000

n = 96

60.700

67.500

47.900

52.800

47.900

52.800

n=1

9.250

14.000

8.600

13.000

8.600

13.000

n = 96

60.700

67.500

47.900

52.800

47.900

52.800

In non-conductive status

8

0.0285

7.800

0.060

8

App-93

8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

BKCMP> S1 S2

n

D

0.0285

5.100

When
executed
n

0.060

8

0.0285

In non-conductive status

When not executed

D

0.0285

In conductive status

When
executed

BKCMP = S1 S2

0.0285

4.400

0.060

8

Max.

7.700

When not executed

OR$>=

0.0285

Min.

4.600

When
executed

AND$>=

0.060

Max.

4.700

When not executed

LD$>=

Min.

In conductive status

When
executed

OR$<

Max.

Q10/Q13/Q20/
Q26UD(E)HCPU

In conductive status

When not executed
AND$<

Q04/
Q06UD(E)HCPU

Processing Time (µs)
Category

Instruction

DB + S

D

DB + S1 S2
DB - S

Condition (Device)

D

D

Q04/
Q06UD(E)HCPU

Q10/Q13/Q20/
Q26UD(E)HCPU

Min.

Max.

Min.

Max.

Min.

Max.

When executed

4.900

7.000

4.600

6.400

4.600

6.400

When executed

5.200

7.300

4.800

6.700

4.800

6.700

When executed

4.900

6.600

4.700

6.000

4.700

6.000

DB - S1 S2

D

When executed

5.200

7.500

4.800

6.600

4.800

6.600

DB * S1 S2

D

When executed

8.300

12.100

8.100

11.600

8.100

11.600

When executed

6.100

9.100

5.800

8.800

5.800

8.800

DB/ S1 S2

ED + S

D

Double
precision

D

ED + S1 S2

ED - S

Double
precision

D

Double
precision

D

ED - S1 S2

Double
precision

D

ED * S1 S2

Double
precision

D

Basic
instruction ED / S1 S2

D

DBK + S1 S2

DBK - S1 S2

DFLTD

INTD

DINTD

D

=0

4.800

8.000

4.300

7.200

4.300

7.200

= 21023,

D

= 21023

4.800

8.000

4.300

7.200

4.300

7.200

= 0,

S2

=0

5.500

9.800

4.800

9.200

4.800

9.200

= 21023,

S2

= 21023

5.500

9.800

4.800

9.200

4.800

9.200

= 0,

D

=0

5.000

8.200

4.400

7.500

4.400

7.500

= 21023,

D

= 21023

5.000

8.200

4.400

7.500

4.400

7.500

= 0,

S2

=0

4.400

8.100

3.800

7.500

3.800

7.500

= 21023,

S2

= 21023

4.400

8.100

3.800

7.500

3.800

7.500

= 0,

S2

=0

5.800

9.500

5.100

8.800

5.100

8.800

S1

= 21023,

S2

= 21023

5.800

9.500

5.100

8.800

5.100

8.800

S1

= 21023,

S2

= 21023

6.600

10.600

5.900

10.000

5.900

10.000

n=1

9.100

11.200

8.500

10.600

8.500

10.600

n = 96

60.700

62.900

44.600

47.000

44.600

47.000

n=1

9.700

12.000

8.900

11.300

8.900

11.300

n = 96

61.300

63.600

45.600

47.900

45.600

47.900

n=1

7.000

10.700

6.450

9.950

6.450

9.950

n = 96

59.400

63.100

43.700

47.500

43.700

47.500

n=1

7.000

10.700

6.450

9.950

6.450

9.950

n = 96

59.400

63.100

43.700

47.500

43.700

47.500

––

8.800

14.600

8.100

13.900

8.100

13.900

––

7.300

11.100

6.500

10.300

6.500

10.300

=0

2.300

5.000

1.800

4.700

1.800

4.700

= 7FFFH

2.500

5.200

2.200

4.800

2.200

4.800

=0

2.400

5.200

2.000

4.900

2.000

4.900

= 7FFFFFFFH

2.700

5.400

2.300

5.100

2.300

5.100

=0

2.700

4.100

2.200

4.100

2.200

4.100

= 32766.5

3.700

5.900

3.200

5.600

3.200

5.600

=0

2.600

3.900

2.200

3.400

2.200

3.400

= 1234567890.3

3.400

5.600

3.000

5.100

3.000

5.100

S

S1
S1

S
S

S1
S1

S1

n

D

D

n

n

D

$ + S1 S2
FLTD

= 0,

S

n

D

BK - S1 S2

$+ S

Double
precision

D

BK + S1 S2

App-94

Q03UD(E)CPU

D

Double
precision

S
S

Double
precision

S
S

Double
precision
Double
precision

S
S

S
S

Processing Time (µs)
Category

Instruction

Condition (Device)

Q03UD(E)CPU

Q04/
Q06UD(E)HCPU

Q10/Q13/Q20/
Q26UD(E)HCPU

Min.

Max.

Min.

Max.

Min.

Max.

DBL

When executed

2.700

3.400

2.300

2.700

2.300

2.700

WORD

When executed

2.900

4.300

2.600

3.600

2.600

3.600

GRY

When executed

2.700

3.900

2.300

3.400

2.300

3.400

DGRY

When executed

2.900

3.500

2.500

3.000

2.500

3.000

GBIN

When executed

4.000

4.800

3.800

4.300

3.800

4.300

DGBIN

When executed

5.500

6.100

5.000

5.900

5.000

5.900

NEG

When executed

2.400

3.900

2.000

3.300

2.000

3.300

DNEG

When executed

2.500

3.700

2.500

3.300

2.500

3.300

ENEG

EDNEG

BKBCD S

n

D

Floating point = 0

2.500

3.300

2.300

2.800

2.300

2.800

Floating point = -1.0

2.700

4.500

2.500

3.900

2.500

3.900

Floating point = 0

2.200

3.500

1.800

3.100

1.800

3.100

Floating point = -1.0

2.400

3.500

1.900

3.000

1.900

3.000

n=1

6.600

8.900

5.900

8.200

5.900

8.200

n = 96

71.300

74.100

61.000

63.400

61.000

63.400

6.500

9.800

5.600

9.300

5.600

9.300

56.300

59.500

49.200

52.500

49.200

52.500

ECON

––

2.600

5.400

2.100

4.500

2.100

4.500

EDCON

––

2.800

5.400

2.500

5.400

2.500

5.400

––

2.300

5.500

1.700

5.000

1.700

5.000

4.000

6.300

3.400

5.600

3.400

5.600

14.600

16.500

11.400

13.300

11.400

13.300

n=1

6.200

7.900

5.500

7.300

5.500

7.300

D

n

EDMOV

Character string to be
$MOV
Basic

transferred = 0
Character string to be
transferred = 32

instruction
BXCH D1 D2 n

n = 96

67.000

68.800

47.300

49.300

47.300

49.300

SWAP

––

2.400

2.700

1.900

2.200

1.900

2.200

GOEND

––

DI

––

1.800

2.200

1.500

1.800

1.500

EI

––

3.100

3.800

3.000

3.300

3.000

3.300

IMASK

––

9.800

13.300

7.200

10.500

7.200

10.500

IRET
RSF X n

0.500

0.500

1.000

––

0.500

1.000

1.800

1.000

n=1

4.200

5.900

3.700

5.600

3.700

5.600

n = 96

11.400

13.800

10.700

12.400

10.700

12.400

n=1

3.800

4.800

3.400

4.800

3.400

4.800

n = 96

8.500

9.500

8.100

8.900

8.100

8.900

UDCNT1

––

0.900

1.500

0.500

0.983

0.500

0.983

UDCNT2

––

0.900

1.700

0.600

1.300

0.600

1.300

TTMR

––

3.900

6.100

3.400

5.400

3.400

5.400

STMR

––

6.800

13.500

5.800

12.500

5.800

12.500

ROTC

––

9.000

10.500

8.000

9.400

8.000

9.400

RAMP

––

5.900

8.800

5.200

8.400

5.200

8.400

SPD

––

0.900

1.900

0.500

1.400

0.500

1.400

PLSY

––

1.900

2.200

1.500

1.800

1.500

1.800

PWM

––

1.200

1.600

0.900

1.200

0.900

1.200

MTR

––

10.400

19.800

9.400

10.000

9.400

10.000

RSF Y n

App-95

8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

n=1
n = 96

BKBIN S

8

Processing Time (µs)
Category

Instruction

Condition (Device)

Q03UD(E)CPU
Min.

BKAND S1 S2

n

D

BKOR S1 S2

n

D

BKXOR S1 S2

D

n

BKXNR S1 S2

D

n

BSFR D n

BSFL D n

SFTBR D n1 n2

SFTBL D n1 n2

SFTWR D n1 n2

SFTWL D n1 n2

Min.

Min.

Max.

Max.

n=1

9.000

11.700

8.300

11.000

8.300

11.000

n = 96

57.400

63.100

43.800

47.300

43.800

47.300

n=1

7.700

10.000

7.700

9.500

7.700

9.500

n = 96

57.400

61.900

44.300

45.800

44.300

45.800

n=1

7.800

10.100

7.300

9.200

7.300

9.200

n = 96

57.300

61.500

43.800

45.800

43.800

45.800

n=1

7.800

9.600

7.600

8.900

7.600

8.900

n = 96

57.400

61.400

43.900

45.300

43.900

45.300

n=1

3.700

5.400

3.200

4.800

3.200

4.800

n = 96

6.900

9.000

5.800

7.700

5.800

7.700

n=1

4.100

5.900

3.400

5.100

3.400

5.100

n = 96

7.100

9.100

6.000

7.900

6.000

7.900

n1 = 16 / n2 = 1

7.950

17.500

7.600

16.900

7.600

16.900

7.950

17.500

7.550

16.900

7.550

16.900

n1 = 16 / n2 = 1

7.950

17.900

7.500

17.400

7.500

17.400

n1 = 16 / n2 = 15

7.900

17.800

7.500

17.300

7.500

17.300

n1 = 16 / n2 = 1

5.950

10.600

4.600

8.700

4.600

8.700

n1 = 16 / n2 = 15

5.900

10.600

4.600

8.700

4.600

8.700

n1 = 16 / n2 = 1

5.950

10.700

4.550

8.700

4.550

8.700

n1 = 16 / n2 = 15

5.950

10.700

4.600

8.800

4.600

8.800

Application

n=1

3.000

3.400

2.500

2.800

2.500

2.800

n = 15

3.000

3.500

2.500

2.800

2.500

2.800

n=1

3.000

3.400

2.600

2.800

2.600

2.800

n = 15

3.000

3.400

2.500

2.800

2.500

2.800

TEST

When executed

4.400

5.300

3.700

4.700

3.700

4.700

DTEST

When executed

4.500

5.400

3.900

4.800

3.900

4.800

n=1

4.300

4.600

3.700

4.100

3.700

4.100

n = 96

6.000

6.800

5.100

6.000

5.100

6.000

4.900

5.300

4.200

4.600

4.200

4.600

BRST D n

BKRST D n

n=1
SER S1 S2

n

D

DSER S1 S2

D

n

All match
None match

5.000

5.300

4.200

4.600

4.200

4.600

n=

All match

32.300

32.900

25.900

26.300

25.900

26.300

96

None match

32.400

32.900

25.900

26.300

25.900

26.300

All match

6.100

6.500

5.400

5.700

5.400

5.700

None match

6.200

6.600

5.500

5.900

5.500

5.900

n=

All match

52.800

54.200

41.200

41.800

41.200

41.800

96

None match

52.800

54.200

41.200

41.800

41.200

41.800

=0

3.700

4.100

3.300

3.600

3.300

3.600

= FFFFFFFFH

3.800

4.100

3.200

3.700

3.200

3.700

n=2

6.000

7.500

5.300

6.900

5.300

6.900

n=8

8.100

9.300

6.800

7.800

6.800

7.800

M1 = ON

5.300

5.700

4.700

5.100

4.700

5.100

M4 = ON

5.200

5.700

4.600

5.000

4.600

5.000

M1 = ON

10.400

11.400

9.000

10.000

9.000

10.000

M256 = ON

5.700

6.800

5.100

6.100

5.100

6.100

n=1

S

DSUM S

D
S

DECO S

D

n

n=2
ENCO S

D

n

n=8

App-96

Q10/Q13/Q20/
Q26UD(E)HCPU

n1 = 16 / n2 = 15

BSET D n
instruction

Max.

Q04/
Q06UD(E)HCPU

Processing Time (µs)
Category

Instruction

Q04/
Q06UD(E)HCPU

Q10/Q13/Q20/
Q26UD(E)HCPU

Max.

Min.

Max.

Min.

Max.

n=1

4.400

5.300

3.800

4.600

3.800

4.600

n=4

4.800

5.700

4.000

5.000

4.000

5.000

n=1

5.000

5.300

3.500

4.800

3.500

4.800

n=4

5.600

6.000

4.000

5.100

4.000

5.100

NDIS

When executed

11.000

13.100

11.000

13.200

11.000

13.200

NUNI

When executed

10.600

12.700

7.300

13.200

7.300

13.200

DIS S

D

n

UNI S

D

n

WTOB S

D

n

BTOW S

D

n

MIN S

n

D

n

D

DMAX S

DMIN S

D

n

n

D

SORT S1 n S2 D1 D2

DSORT S1 n S2 D1 D2

WSUM S

DWSUM S

MEAN S

n

D

D

n

D n

DMEAN S

D n

n=1

5.000

6.500

4.400

5.800

4.400

5.800

n = 96

36.000

38.400

28.200

29.300

28.200

29.300

n=1

5.100

6.100

4.600

5.500

4.600

5.500

n = 96

29.900

32.000

22.800

23.800

22.800

23.800

n=1

4.300

6.900

4.000

6.100

4.000

6.100

n = 96

31.200

33.500

24.700

27.000

24.700

27.000

n=1

4.400

6.800

4.000

6.000

4.000

6.000

n = 96

30.300

34.800

26.500

28.300

26.500

28.300

n=1

4.800

9.100

4.800

8.100

4.800

8.100

n = 96

56.400

62.200

47.100

49.600

47.100

49.600

n=1

4.800

6.800

4.300

5.900

4.300

5.900

n = 96

55.400

60.200

45.400

47.400

45.400

47.400

n=1

6.200

9.300

5.600

8.800

5.600

8.800

n = 96

6.200

9.400

5.600

8.600

5.600

8.600

n=1

6.200

9.300

5.600

8.200

5.600

8.200

n = 96

6.100

9.100

5.600

8.400

5.600

8.400

n=1

4.800

6.200

4.200

5.500

4.200

5.500

n = 96

26.900

28.700

21.300

22.300

21.300

22.300

n=1

5.500

7.000

4.800

6.100

4.800

6.100

n = 96

53.000

56.300

42.700

44.000

42.700

44.000

n=1

4.300

8.650

3.900

7.800

3.900

7.800

n = 96

16.000

21.400

12.900

18.000

12.900

18.000

n=1

5.700

10.600

5.300

9.950

5.300

9.950

n = 96

29.200

35.200

23.000

28.800

23.000

28.800

NEXT

––

0.940

1.400

0.770

1.200

0.770

1.200

BREAK

––

10.400

5.500

9.100

5.000

9.100

5.000

RET

FCALL Pn
FCALL Pn S1 to S5
ECALL * Pn
*: Program name
ECALL * Pn S1 to S5

Return to original program

2.000

3.000

1.600

2.600

1.600

2.600

Return to other program

2.300

3.700

2.000

3.100

2.000

3.100

Internal file pointer

3.100

4.400

2.700

3.600

2.700

3.600

Common pointer

4.000

5.700

3.600

5.100

3.600

5.100

––

19.300

21.500

16.500

18.600

16.500

18.600

––

70.300

82.300

65.900

77.600

65.900

77.600

––

101.000

114.000

91.800

105.000

91.800

105.000

––

70.700

82.800

66.200

78.100

66.200

78.100

––

86.500

107.000

78.800

91.600

78.800

91.600

––

3.800

5.700

3.700

5.200

3.700

5.200

*: Program name
EFCALL * Pn
*: Program name
EFCALL * Pn S1 to S5
*: Program name
XCALL

App-97

8
8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

instruction

Q03UD(E)CPU
Min.

MAX S

Application

Condition (Device)

Processing Time (µs)
Category

Instruction

Condition (Device)

Q03UD(E)CPU

When selecting I/O refresh only
When selecting CC-Link refresh
only (Master station side)
When selecting CC-Link refresh
only (Local station side)
When selecting MELSECNET/H
refresh only (Control station side)
When selecting MELSECNET/H
refresh only (Normal station side)
When selecting intelli auto
refresh only

COM
CCOM

When selecting I/O outside the
group only (Input only)
When selecting I/O outside the
group only (Output only)
When selecting I/O outside the
group only (Both I/O)

Q04/
Q06UD(E)HCPU

Q10/Q13/Q20/
Q26UD(E)HCPU

Min.

Max.

Min.

Max.

Min.

Max.

12.800

29.100

12.400

28.600

12.400

28.600

16.000

39.500

15.500

39.100

15.500

39.100

16.100

39.500

15.500

39.100

15.500

39.100

34.700

70.400

34.400

69.800

34.400

69.800

34.700

70.400

34.400

69.800

34.400

69.800

12.800

33.200

12.800

33.200

12.800

33.200

7.900

21.100

7.700

20.700

7.700

20.700

16.900

44.800

16.500

44.200

16.500

44.200

22.600

52.600

22.400

52.600

22.400

52.600

13.000

33.800

12.700

33.200

12.700

33.200

7.250

18.800

7.100

18.500

7.100

18.500

3.700

5.300

3.200

4.600

3.200

4.600

When selecting refresh of multiple CPU high speed transmission
area only
When selecting communication
with peripheral device
Number of data points = 0

FIFW
Application
instruction

FIFR

FPOP

FINS

FDEL

Number of data points = 96

3.800

4.400

3.300

3.800

3.300

3.800

Number of data points = 0

4.300

5.000

3.800

4.400

3.800

4.400

Number of data points = 96

33.500

35.500

24.800

25.700

24.800

25.700

Number of data points = 0

4.300

5.900

3.800

5.300

3.800

5.300

Number of data points = 96

4.300

5.900

3.700

5.400

3.700

5.400

Number of data points = 0

4.800

5.900

3.700

5.300

3.700

5.300

Number of data points = 96

4.300

5.900

3.700

5.300

3.700

5.300

Number of data points = 0

4.900

6.500

4.200

5.800

4.200

5.800

Number of data points = 96

34.200

35.900

25.400

25.900

25.400

25.900

n3 = 1

10.800

24.100

10.700

23.600

10.700

23.600

n3 = 1000

392.600

413.300

390.900

410.200

390.900

410.200

n3 = 1

13.600

27.700

12.600

26.700

12.600

26.700

n3 = 500

392.600

413.300

390.900

410.200

390.900

410.200

n3 = 1

10.200

21.900

9.600

21.300

9.600

21.300

n3 = 1000

373.700

394.100

372.500

390.800

372.500

390.800

n3 = 1

13.000

26.700

12.000

25.700

12.000

25.700

n3 = 500

373.700

394.100

372.500

390.800

372.500

390.800

2.400

2.600

1.900

2.000

1.900

2.000

28.100

39.400

24.400

35.800

24.400

35.800

=1

4.900

6.500

4.300

5.600

4.300

5.600

= -32768

7.200

8.700

6.500

8.000

6.500

8.000

=1

5.700

7.100

4.900

6.300

4.900

6.300

= -2147483648

10.400

12.000

9.600

11.000

9.600

11.000

FROM n1 n2 D n3

DFRO n1 n2 D n3

TO n1 n2 S n3

DTO n1 n2 S n3

No display
LEDR

no display

LED instruction execution
display
S

BINDA S

D
S

S

DBINDA S

D
S

App-98

no

Processing Time (µs)
Category

Instruction

Condition (Device)

Min.

Max.

Min.

Max.

=1

4.400

5.900

3.800

5.200

3.800

5.200

= FFFFH

4.400

5.800

3.700

5.200

3.700

5.200

=1

5.200

6.700

4.600

6.000

4.600

6.000

= FFFFFFFFH

5.100

6.500

4.600

6.000

4.600

6.000

=1

4.300

5.800

3.600

5.000

3.600

5.000

= 9999

4.700

6.100

4.100

5.400

4.100

5.400

=1

4.800

6.300

4.000

5.500

4.000

5.500

= 99999999

5.600

7.100

4.900

6.300

4.900

6.300

=1

6.500

8.500

5.800

7.800

5.800

7.800

= -32768

6.300

8.300

5.600

7.700

5.600

7.700

=1

9.400

11.500

8.500

10.500

8.500

10.500

= -2147483648

9.100

11.200

8.100

10.200

8.100

10.200

=1

4.900

7.100

4.400

6.400

4.400

6.400

= FFFFH

5.100

7.300

4.600

6.500

4.600

6.500

=1

6.000

8.100

5.300

7.300

5.300

7.300

= FFFFFFFFH

6.300

8.500

5.600

7.700

5.600

7.700

=1

5.000

7.100

4.400

6.300

4.400

6.300

= 9999

5.000

7.100

4.300

6.300

4.300

6.300

=1

6.200

8.300

5.500

7.400

5.500

7.400

= 99999999

6.200

8.300

5.500

7.500

5.500

7.500

51.600

52.400

50.900

51.200

50.900

51.200

D

S

DBINHA S

D
S

S
D
S

S

DBCDDA S

D
S

S

DABIN S

D
S

S

DDABIN S

Application

S

HABIN S

S

S

S
D
S

COMRD
LEN

8
A
6
7
8

––

1 character

4.100

6.200

3.600

5.500

3.600

5.500

96 characters

19.800

22.200

16.800

18.700

16.800

18.700

STR

––

6.900

11.100

6.600

10.400

6.600

10.400

DSTR

––

10.200

12.500

9.600

11.500

9.600

11.500

VAL

––

9.800

14.200

8.900

13.000

8.900

13.000

DVAL

––

14.000

18.700

12.700

16.800

12.700

16.800

ESTR

––

18.700

24.100

17.900

23.100

17.900

23.100

App-99

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

D
S

DDABCD S

8

D
S

DABCD S

8

D
S

DHABIN S

8

D
S

instruction

Q10/Q13/Q20/
Q26UD(E)HCPU

Max.

S

BCDDA S

Q04/
Q06UD(E)HCPU

Min.
S

BINHA S

Q03UD(E)CPU

Processing Time (µs)
Category

Instruction

Condition (Device)

Decimal point format
all 2-digit specification

EVAL

Exponent format
all 6-digit specification

ASC S

D

n

HEX S

D

n

RIGHT S

LEFT S

n

D

D

n

Q03UD(E)CPU

Q04/
Q06UD(E)HCPU

Q10/Q13/Q20/
Q26UD(E)HCPU

Min.

Max.

Min.

Max.

Min.

Max.

23.300

30.400

22.800

29.000

22.800

29.000

23.300

30.500

22.500

29.000

22.500

29.000

n=1

5.600

9.000

5.400

8.300

5.400

8.300

n = 96

28.700

32.100

25.200

28.400

25.200

28.400

n=1

6.000

9.700

5.400

9.000

5.400

9.000

n = 96

35.600

39.800

31.300

35.000

31.300

35.000

n=1

7.600

9.400

7.300

6.600

7.300

6.600

n = 96

36.300

40.000

29.200

31.600

29.200

31.600

n=1

6.500

8.900

5.900

8.200

5.900

8.200

n = 96

36.200

39.700

29.200

31.500

29.200

31.500

MIDR

––

9.500

12.100

8.100

10.300

8.100

10.300

MIDW

––

10.300

12.000

8.800

10.200

8.800

10.200

No match
INSTR

Match

19.300

21.800

16.600

18.400

16.600

18.400

Head

10.300

12.800

9.100

10.900

9.100

10.900

End

51.100

54.200

42.700

44.900

42.700

44.900

EMOD

––

10.300

11.800

9.600

11.000

9.600

11.000

EREXP

––

19.300

21.000

18.800

20.100

18.800

20.100

41.100

54.200

35.300

47.600

35.300

47.600

56.700

81.400

48.600

61.700

48.600

61.700

39.000

49.500

34.800

44.600

34.800

44.600

36.000

45.200

29.200

38.100

29.200

38.100

S

= 128 /

D

= 40 /

n=1
STRINS S

D

n
S

Application

= 128 /

D

= 40 /

n = 48

instruction
S

= 128 /

D

= 40 /

n=1
STRDEL

S

D

n
S

= 128 /

D

= 40 /

n = 48

App-100

SIN

Single precision

4.500

6.200

4.100

5.700

4.100

5.700

COS

Single precision

4.300

6.000

4.000

5.600

4.000

5.600

TAN

Single precision

5.100

7.200

5.100

6.700

5.100

6.700

ASIN

Single precision

6.100

8.900

5.900

8.500

5.900

8.500

ACOS

Single precision

6.800

9.300

6.700

8.900

6.700

8.900

ATAN

Single precision

4.000

6.500

3.900

6.000

3.900

6.000

SIND

Double precision

8.800

14.300

8.500

13.800

8.500

13.800

COSD

Double precision

9.300

15.100

8.800

14.600

8.800

14.600

TAND

Double precision

11.200

16.900

10.800

16.500

10.800

16.500

ASIND

Double precision

12.000

17.100

11.600

16.600

11.600

16.600

ACOSD

Double precision

11.700

16.500

11.200

16.200

11.200

16.200

ATAND

Double precision

9.500

14.200

9.100

13.800

9.100

13.800

RAD

Single precision

2.500

4.800

2.100

4.300

2.100

4.300

RADD

Double precision

4.000

9.600

3.600

9.200

3.600

9.200

DEG

Single precision

2.500

4.700

2.200

4.400

2.200

4.400

DEGD

Double precision

4.300

9.000

3.800

9.000

3.800

9.000

SQR

Single precision

3.000

4.600

2.600

4.300

2.600

4.300

SQRD

Double precision

5.600

11.500

5.200

11.000

5.200

11.000

Processing Time (µs)
Category

Instruction

EXP S

Condition (Device)

Single
D

Min.

Max.

Min.

Max.

= -10

4.000

6.100

3.800

5.500

3.800

5.500

=1

4.000

6.100

3.800

5.600

3.800

5.600

= -10

8.700

13.900

8.200

13.500

8.200

13.500

S

=1

8.400

13.600

8.000

13.200

8.000

13.200

S

=1

4.100

6.900

3.800

6.400

3.800

6.400

= 10

5.600

8.200

5.200

7.700

5.200

7.700

=1

8.100

13.000

7.700

12.500

7.700

12.500

= 10

9.700

14.800

9.200

14.300

9.200

14.300

S

Double

LOG S

S

precision
Single

D

precision
S

LOGD S

Double
D

S

precision
S

RND

––

1.200

2.300

0.800

1.800

0.800

1.800

SRND

––

1.400

2.400

1.100

2.000

1.100

2.000

=0

1.800

3.300

1.600

2.800

1.600

2.800

= 9999

5.100

8.800

5.100

8.000

5.100

8.000

=0

1.900

3.400

1.500

3.000

1.500

3.000

= 99999999

7.500

10.200

7.500

9.900

7.500

9.900

S

BSQR S

8
8
8
8
A
6

D
S

S

BDSQR S

7

D
S

Application
instruction

Q10/Q13/Q20/
Q26UD(E)HCPU

Max.

precision

D

Q04/
Q06UD(E)HCPU

Min.

S

EXPD S

Q03UD(E)CPU

––

8.600

15.100

8.100

14.500

8.100

14.500

BCOS

––

7.800

14.400

7.800

13.700

7.800

13.700

BTAN

––

9.000

13.800

9.000

13.300

9.000

13.300

BASIN

––

10.600

13.400

10.100

12.800

10.100

12.800

BACOS

––

11.600

14.400

11.100

14.100

11.100

14.100

BATAN

––

9.800

11.700

9.100

10.900

9.100

10.900

8.750

11.400

8.400

10.900

8.400

10.900

18.600

27.200

18.200

26.500

18.200

26.500

POW S1 S2

POWD S1 S2

D

D

Single

S1

= 12.3 E + 5

precision

S2

= 3.45 E + 0

Double

S1

= 12.3 E + 5

S2

= 3.45 E + 0

precision

LOG10

Single precision

LOG10D

Double precision

LIMIT

––

5.900

8.550

5.700

8.050

5.700

8.050

DLIMIT

––

11.500

19.400

11.100

18.600

11.100

18.600

BAND

––

2.800

3.100

2.400

2.700

2.400

2.700

DBAND

––

3.200

3.500

2.800

3.000

2.800

3.000

ZONE

––

3.000

4.300

2.700

3.800

2.700

3.800

DZONE

––

3.600

5.100

3.300

4.600

3.300

4.600

App-101

8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

BSIN

Processing Time (µs)
Category

Instruction

Condition (Device)

Q03UD(E)CPU

Q04/
Q06UD(E)HCPU

Q10/Q13/Q20/
Q26UD(E)HCPU

Min.

Max.

Min.

Max.

Min.

Max.

13.200

23.600

12.300

22.500

12.300

22.500

13.300

23.600

12.600

22.700

12.600

22.700

12.000

23.100

11.400

22.200

11.400

22.200

14.100

25.300

12.800

23.900

12.800

23.900

12.800

23.800

11.900

23.000

11.900

23.000

12.900

23.900

12.100

23.000

12.100

23.000

11.500

22.400

10.900

21.500

10.900

21.500

13.800

24.900

12.700

23.600

12.700

23.600

12.700

24.200

11.900

23.300

11.900

23.300

12.900

24.600

12.100

23.300

12.100

23.300

12.300

23.400

11.500

22.600

11.500

22.600

13.700

25.000

12.600

23.900

12.600

23.900

12.600

23.800

11.800

22.900

11.800

22.900

13.000

23.900

12.200

22.800

12.200

22.800

11.500

22.400

11.000

21.400

11.000

21.400

13.900

24.900

12.800

23.600

12.800

23.600

Point No.1

SM750
= ON

< S1 <
Point No.2
Point No.9
< S1 <
Point No.10

SCL S1 S2

D

Point No.1

SM750
= OFF

< S1 <
Point No.2
Point No.9
< S1 <
Point No.10
Point No.1

SM750
= ON

< S1 <
Point No.2
Point No.9
< S1 <
Point No.10

DSCL S1 S2

D

Point No.1

SM750
= OFF

< S1 <
Point No.2
Point No.9

Application

< S1 <
Point No.10

instruction

Point No.1

SM750
= ON

< S1 <
Point No.2
Point No.9
< S1 <
Point No.10

SCL2 S1 S2

D

Point No.1

SM750
= OFF

< S1 <
Point No.2
Point No.9
< S1 <
Point No.10
Point No.1

SM750
= ON

< S1 <
Point No.2
Point No.9
< S1 <
Point No.10

DSCL2 S1 S2

D

Point No.1

SM750
= OFF

< S1 <
Point No.2
Point No.9
< S1 <
Point No.10

App-102

Processing Time (µs)
Category

Instruction

Condition (Device)

QCDSET

Q04/
Q06UD(E)HCPU

Q10/Q13/Q20/
Q26UD(E)HCPU

Min.

Max.

Min.

Max.

Min.

Max.

Standard RAM

3.000

6.300

2.700

5.900

2.700

5.900

SRAM card

3.000

6.400

2.600

5.800

2.600

5.800

SRAM card to standard RAM

120.000

134.000

115.000

134.000

115.000

134.000

RSET

QDRSET

Q03UD(E)CPU

Standard RAM to SRAM card

533.000

560.000

520.000

553.000

520.000

553.000

SRAM card to standard ROM

306.000

346.000

305.000

346.000

305.000

346.000

Standard ROM to SRAM card

311.000

342.000

300.000

334.000

300.000

334.000

DATERD

––

3.200

5.000

2.500

4.200

2.500

4.200

DATEWR

––

4.900

9.700

4.100

8.900

4.100

8.900

No digit increase

5.100

8.000

4.700

6.600

4.700

6.600

Digit increase

5.700

8.000

4.600

6.500

4.600

6.500

No digit increase

5.800

8.500

4.600

7.000

4.600

7.000

Digit increase

5.700

7.400

4.600

6.500

4.600

6.500

SECOND

––

2.600

3.900

2.200

3.400

2.200

3.400

HOUR

––

2.900

4.800

2.400

4.300

2.400

4.300

7.400

11.400

6.800

10.900

6.800

10.900

7.400

11.600

6.800

10.900

6.800

10.900

5.900

10.000

5.500

9.700

5.500

9.700

5.900

10.100

5.500

9.700

5.500

9.700

DATE +

DATE -

Comparison
of specified
date
LDDT =

Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

When not executed

Application

Comparison
of specified
ANDDT=

date
Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

11.400

6.500

10.700

6.500

10.700

7.200

11.400

6.500

10.700

6.500

10.700

5.700

9.900

5.300

9.300

5.300

9.300

5.700

9.900

5.300

9.300

5.300

9.300

of specified
ORDT=

date
Comparison
of current
date
Comparison
of specified
date

LDDT <>

Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

0.008

8
8
A
6
7
8

0.038

7.200

When not executed
Comparison

0.038

8

0.038

0.038

7.400

11.500

6.700

10.800

6.700

10.800

7.400

11.500

6.700

10.800

6.700

10.800

5.900

10.000

5.400

9.600

5.400

9.600

5.900

10.000

5.400

9.600

5.400

9.600

7.400

11.400

6.800

10.900

6.800

10.900

7.400

11.600

6.800

10.900

6.800

10.900

5.900

10.000

5.500

9.700

5.500

9.700

5.900

10.100

5.500

9.700

5.500

9.700

App-103

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

instruction

0.008

8

Processing Time (µs)
Category

Instruction

Condition (Device)

Q03UD(E)CPU
Min.

When not executed
Comparison
of specified
ANDDT<>

date
Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

Comparison
of specified
ORDT<>

date
Comparison
of current
date
Comparison
of specified

Application
instruction

date
LDDT>

Comparison
of current
date

status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

of specified
ANDDT>

date
Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

Comparison
of specified
ORDT>

date
Comparison
of current
date

App-104

status
In nonconductive
status
In conductive
status
In nonconductive
status

Min.

Max.
0.038

Max.
0.038

11.400

6.500

10.700

6.500

10.700

7.200

11.400

6.500

10.700

6.500

10.700

5.700

9.900

5.300

9.300

5.300

9.300

5.700

9.900

5.300

9.300

5.300

9.300

0.008

0.038

0.038

7.400

11.500

6.700

10.800

6.700

10.800

7.400

11.500

6.700

10.800

6.700

10.800

5.900

10.000

5.400

9.600

5.400

9.600

5.900

10.000

5.400

9.600

5.400

9.600

7.400

11.400

6.800

10.900

6.800

10.900

7.400

11.600

6.800

10.900

6.800

10.900

5.900

10.000

5.500

9.700

5.500

9.700

5.900

10.100

5.500

9.700

5.500

9.700

0.008

0.038

0.038

7.200

11.400

6.500

10.700

6.500

10.700

7.200

11.400

6.500

10.700

6.500

10.700

5.700

9.900

5.300

9.300

5.300

9.300

5.700

9.900

5.300

9.300

5.300

9.300

When not executed
In conductive

Min.

7.200

When not executed
Comparison

Q10/Q13/Q20/
Q26UD(E)HCPU

0.008

When not executed
In conductive

Max.

Q04/
Q06UD(E)HCPU

0.008

0.038

0.038

7.400

11.500

6.700

10.800

6.700

10.800

7.400

11.500

6.700

10.800

6.700

10.800

5.900

10.000

5.400

9.600

5.400

9.600

5.900

10.000

5.400

9.600

5.400

9.600

Processing Time (µs)
Category

Instruction

Condition (Device)

Comparison
of specified
date
LDDT<=

Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

Q03UD(E)CPU

of specified
ANDDT<=

date
Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

Max.

Min.

Max.

Min.

Max.

7.400

11.400

6.800

10.900

6.800

10.900

7.400

11.600

6.800

10.900

6.800

10.900

5.900

10.000

5.500

9.700

5.500

9.700

5.900

10.100

5.500

9.700

5.500

9.700

0.008

Comparison
of specified
ORDT<=

date
Comparison
of current
date

instruction

Comparison
of specified
date
LDDT<

Comparison
of current
date

In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

11.400

6.500

10.700

6.500

10.700

7.200

11.400

6.500

10.700

6.500

10.700

5.700

9.900

5.300

9.300

5.300

9.300

5.700

9.900

5.300

9.300

5.300

9.300

0.008

of specified
ANDDT<

date
Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

6.700

10.800

6.700

10.800

7.400

11.500

6.700

10.800

6.700

10.800

5.900

10.000

5.400

9.600

5.400

9.600

5.900

10.000

5.400

9.600

5.400

9.600

7.400

11.400

6.800

10.900

6.800

10.900

7.400

11.600

6.800

10.900

6.800

10.900

5.900

10.000

5.500

9.700

5.500

9.700

5.900

10.100

5.500

9.700

5.500

9.700

0.008

Comparison
of specified
ORDT<

date
Comparison
of current
date

status
In nonconductive
status
In conductive
status
In nonconductive
status

0.038

0.038

7.200

11.400

6.500

10.700

6.500

10.700

7.200

11.400

6.500

10.700

6.500

10.700

5.700

9.900

5.300

9.300

5.300

9.300

5.700

9.900

5.300

9.300

5.300

9.300

0.008

0.038

8
8
8
A
6
7

0.038

11.500

When not executed
In conductive

0.038

7.400

When not executed
Comparison

0.038

8

0.038

7.400

11.500

6.700

10.800

6.700

10.800

7.400

11.500

6.700

10.800

6.700

10.800

5.900

10.000

5.400

9.600

5.400

9.600

5.900

10.000

5.400

9.600

5.400

9.600

App-105

8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

Application

status

0.038

7.200

When not executed
In conductive

Q10/Q13/Q20/
Q26UD(E)HCPU

Min.

When not executed
Comparison

Q04/
Q06UD(E)HCPU

Processing Time (µs)
Category

Instruction

Condition (Device)

Comparison
of specified
date
LDDT>=

Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

Q03UD(E)CPU

of specified
ANDDT>=

date
Comparison
of current
date

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

Max.

Min.

Max.

Min.

Max.

7.400

11.400

6.800

10.900

6.800

10.900

7.400

11.600

6.800

10.900

6.800

10.900

5.900

10.000

5.500

9.700

5.500

9.700

5.900

10.100

5.500

9.700

5.500

9.700

0.008

Comparison
of specified
ORDT>=

date
Comparison
of current
date

Application
instruction

Comparison
of specified
ciock
LDTM=

Comparison
of current
ciock

status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

of specified
ANDTM=

ciock
Comparison
of current
ciock

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

6.500

10.700

6.500

10.700

7.200

11.400

6.500

10.700

6.500

10.700

5.700

9.900

5.300

9.300

5.300

9.300

5.700

9.900

5.300

9.300

5.300

9.300

0.008

Comparison
of specified
ORTM=

ciock
Comparison
of current
ciock

App-106

status
In nonconductive
status
In conductive
status

0.038

0.038

7.400

11.500

6.700

10.800

6.700

10.800

7.400

11.500

6.700

10.800

6.700

10.800

5.900

10.000

5.400

9.600

5.400

9.600

5.900

10.000

5.400

9.600

5.400

9.600

7.300

11.500

6.700

10.800

6.700

10.800

7.300

11.500

6.700

10.800

6.700

10.800

5.800

9.900

5.400

9.500

5.400

9.500

5.800

9.900

5.400

9.500

5.400

9.500

0.008

0.038

0.038

7.000

11.500

6.300

10.800

6.300

10.800

7.000

11.500

6.300

10.800

6.300

10.800

5.500

9.900

5.100

9.500

5.100

9.500

5.500

9.900

5.100

9.500

5.100

9.500

When not executed
In conductive

0.038

11.400

When not executed
Comparison

0.038

7.200

When not executed
In conductive

Q10/Q13/Q20/
Q26UD(E)HCPU

Min.

When not executed
Comparison

Q04/
Q06UD(E)HCPU

0.008

0.038

0.038

7.300

11.500

6.600

10.800

6.600

10.800

7.300

11.500

6.600

10.800

6.600

10.800

5.900

9.900

5.300

9.500

5.300

9.500

Processing Time (µs)
Category

Instruction

Condition (Device)

Comparison
of specified
ciock
LDTM<>

Comparison
of current
ciock

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

Q03UD(E)CPU

of specified
ANDTM<>

ciock
Comparison
of current
ciock

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

Max.

Min.

Max.

Min.

Max.

7.300

11.500

6.700

10.800

6.700

10.800

7.300

11.500

6.700

10.800

6.700

10.800

5.800

9.900

5.400

9.500

5.400

9.500

5.800

9.900

5.400

9.500

5.400

9.500

0.008

Comparison
of specified
ORTM<>

ciock
Comparison
of current
ciock

instruction

Comparison
of specified
ciock
LDTM>

Comparison
of current
ciock

In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

11.500

6.300

10.800

6.300

10.800

7.000

11.500

6.300

10.800

6.300

10.800

5.500

9.900

5.100

9.500

5.100

9.500

5.500

9.900

5.100

9.500

5.100

9.500

0.008

of specified
ANDTM>

ciock
Comparison
of current
ciock

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

6.600

10.800

6.600

10.800

7.300

11.500

6.600

10.800

6.600

10.800

5.900

9.900

5.300

9.500

5.300

9.500

5.900

9.900

5.300

9.500

5.300

9.500

7.300

11.500

6.700

10.800

6.700

10.800

7.300

11.500

6.700

10.800

6.700

10.800

5.800

9.900

5.400

9.500

5.400

9.500

5.800

9.900

5.400

9.500

5.400

9.500

0.008

Comparison
of specified
ORTM>

ciock
Comparison
of current
ciock

status
In nonconductive
status
In conductive
status
In nonconductive
status

0.038

0.038

7.000

11.500

6.300

10.800

6.300

10.800

7.000

11.500

6.300

10.800

6.300

10.800

5.500

9.900

5.100

9.500

5.100

9.500

5.500

9.900

5.100

9.500

5.100

9.500

0.008

0.038

8
8
8
A
6
7

0.038

11.500

When not executed
In conductive

0.038

7.300

When not executed
Comparison

0.038

8

0.038

7.300

11.500

6.600

10.800

6.600

10.800

7.300

11.500

6.600

10.800

6.600

10.800

5.900

9.900

5.300

9.500

5.300

9.500

5.900

9.900

5.300

9.500

5.300

9.500

App-107

8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

Application

status

0.038

7.000

When not executed
In conductive

Q10/Q13/Q20/
Q26UD(E)HCPU

Min.

When not executed
Comparison

Q04/
Q06UD(E)HCPU

Processing Time (µs)
Category

Instruction

Condition (Device)

Comparison
of specified
ciock
LDTM<=

Comparison
of current
ciock

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

Q03UD(E)CPU

of specified
ANDTM<=

ciock
Comparison
of current
ciock

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

Max.

Min.

Max.

Min.

Max.

7.300

11.500

6.700

10.800

6.700

10.800

7.300

11.500

6.700

10.800

6.700

10.800

5.800

9.900

5.400

9.500

5.400

9.500

5.800

9.900

5.400

9.500

5.400

9.500

0.008

Comparison
of specified
ORTM<=

ciock
Comparison
of current
ciock

Application
instruction

Comparison
of specified
ciock
LDTM<

Comparison
of current
ciock

status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

of specified
ANDTM<

ciock
Comparison
of current
ciock

In conductive
status
In nonconductive
status
In conductive
status
In nonconductive
status

6.300

10.800

6.300

10.800

7.000

11.500

6.300

10.800

6.300

10.800

5.500

9.900

5.100

9.500

5.100

9.500

5.500

9.900

5.100

9.500

5.100

9.500

0.008

Comparison
of specified
ORTM<

ciock
Comparison
of current
ciock

App-108

status
In nonconductive
status
In conductive
status
In nonconductive
status

0.038

0.038

7.300

11.500

6.600

10.800

6.600

10.800

7.300

11.500

6.600

10.800

6.600

10.800

5.900

9.900

5.300

9.500

5.300

9.500

5.900

9.900

5.300

9.500

5.300

9.500

7.300

11.500

6.700

10.800

6.700

10.800

7.300

11.500

6.700

10.800

6.700

10.800

5.800

9.900

5.400

9.500

5.400

9.500

5.800

9.900

5.400

9.500

5.400

9.500

0.480

0.320

0.240

8.200

25.500

8.200

25.500

6.500

25.500

8.200

25.500

8.200

25.500

6.500

25.500

6.500

23.100

6.500

23.100

6.500

23.100

6.500

23.100

6.500

23.100

6.500

23.100

When not executed
In conductive

0.038

11.500

When not executed
Comparison

0.038

7.000

When not executed
In conductive

Q10/Q13/Q20/
Q26UD(E)HCPU

Min.

When not executed
Comparison

Q04/
Q06UD(E)HCPU

0.480

0.320

0.240

8.200

25.500

8.200

25.500

6.500

25.500

8.200

25.500

8.200

25.500

6.500

25.500

6.500

23.100

6.500

23.100

6.500

23.100

6.500

23.100

6.500

23.100

6.500

23.100

Processing Time (µs)
Category

Instruction

Condition (Device)

Comparison
of specified
ciock

In conductive
status
In nonconductive
status

LDTM<

Comparison
of current
ciock

In conductive
status
In nonconductive
status

Q03UD(E)CPU

of specified
ANDTM<

ciock

In conductive
status
In nonconductive
status

Comparison
of current
ciock

In conductive
status
In nonconductive
status

Max.

Min.

Max.

Min.

Max.

7.300

11.500

6.700

10.800

6.700

10.800

7.300

11.500

6.700

10.800

6.700

10.800

5.800

9.900

5.400

9.500

5.400

9.500

5.800

9.900

5.400

9.500

5.400

9.500

0.480

Comparison
of specified
Application

ORTM<

instruction

ciock

of current

S.DATE +

In conductive
status
In nonconductive
status

0.240

25.500

8.200

25.500

6.500

25.500

8.200

25.500

8.200

25.500

6.500

25.500

6.500

23.100

6.500

23.100

6.500

23.100

6.500

23.100

6.500

23.100

6.500

23.100

0.480

0.320

8.200

25.500

8.200

25.500

6.500

25.500

8.200

25.500

8.200

25.500

6.500

25.500

6.500

23.100

6.500

23.100

6.500

23.100

6.500

23.100

6.500

23.100

6.500

23.100

––

9.250

51.000

9.250

51.000

9.250

51.000

No digit increase

16.800

75.400

16.800

75.400

16.800

75.400
75.400

Digit increase

16.800

75.400

16.800

75.400

16.800

17.600

75.300

17.600

75.300

17.600

75.300

Digit increase

16.900

75.300

16.900

75.300

16.900

75.300

PSTOP

––

82.200

199.000

82.200

199.000

82.200

199.000

POFF

––

82.600

198.000

82.600

198.000

82.600

198.000

PSCAN

––

83.600

200.000

83.600

200.000

83.600

200.000

WDT

––

2.900

12.000

2.900

12.000

2.900

12.000

DUTY

––

7.700

27.500

7.700

27.500

7.700

27.500

TIMCHK

––

5.350

24.500

5.350

24.500

5.350

24.500

File register of standard RAM

4.100

4.200

4.100

4.200

4.100

4.200

ZRRDB

ZRWRB

8
8
8
A
6
7

0.240

No digit increase

S.DATE -

8

File register of SRAM card

––

––

––

––

––

––

File register of standard RAM

5.400

5.500

5.400

5.500

5.400

5.500

File register of SRAM card

––

––

––

––

––

––

ADRSET

––

2.400

6.650

2.400

6.650

2.400

6.650

ZPUSH

––

9.200

20.500

9.200

20.500

9.200

20.500

ZPOP

––

9.000

15.500

9.000

15.500

9.000

15.500

App-109

8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

S.DATERD

In nonconductive
status

Comparison
ciock

status

0.320

8.200

When not executed
In conductive

Q10/Q13/Q20/
Q26UD(E)HCPU

Min.

When not executed
Comparison

Q04/
Q06UD(E)HCPU

Processing Time (µs)
Category

Instruction

Condition (Device)

Q03UD(E)CPU

Q04/
Q06UD(E)HCPU

Q10/Q13/Q20/
Q26UD(E)HCPU

Min.

Max.

Min.

Max.

Min.

Max.

19.600

26.500

19.300

26.000

19.300

26.000

19.600

26.500

19.100

26.200

19.100

26.200

53.500

73.500

53.000

72.700

53.000

72.700

29.800

41.200

29.800

40.600

29.800

40.600

5.900

11.000

5.400

10.500

5.400

10.500

When mounting CC-Link
module
(Master station side)
When mounting CC-Link
module
(Local station side)
When mounting
MELSECNET/H,

S.ZCOM

CC-Link IEcontroller
network module(Control
station side)
When mounting
MELSECNET/H,
CC-Link IEcontroller
network module(Normal
station side)

Application S.RTREAD
instruction S.RTWRITE

––

UNIRD n1 D

n2

––

6.700

11.100

6.000

10.400

6.000

10.400

n2 = 1

4.000

8.400

3.700

8.000

3.700

8.000

n2 = 16

12.500

17.000

12.200

16.600

12.200

16.600

29.800

53.000

29.500

52.300

29.500

52.300

Start

46.600

48.300

43.800

44.700

43.800

44.700

––

3.300

6.800

2.600

6.000

2.600

6.000

11.300

16.800

9.200

15.100

9.200

15.100

120.700

127.100

61.000

68.600

61.000

68.600

11.200

16.700

9.400

15..600

9.400

15.600

180.700

187.100

165.000

172.600

165.000

172.600

11.100

6.000

10.400

6.000

10.400

TYPERD
TRACE
TRACER

When standard
RAM is used
RBNOV S

D

n

When SRAM
card is used

App-110

1 point
1000
points
1 point
1000
points

SP.FWRITE

––

6.700

SP.FREAD

––

5.900

11.000

5.400

10.500

5.400

10.500

SP.DEVST

––

4.500

36.500

4.000

34.500

4.000

34.500

S.DEVLD

––

11.000

17.800

10.000

17.000

10.000

17.000

Processing Time (µs)
Category

Instruction

Condition (Device)

Writing to host
S.TO n1 n2 n3 n4

CPU shared

D

memory
Writing to host
TO n1 n2

CPU shared

n3

S

memory
Writing to host
DTO n1 n2

CPU shared

n3

S

memory
Multiple

Reading from

CPU

host CPU shared

dedicated
instruction

memory
FROM n1 n2

D

n3

Reading from

n3

DP.DDWR n

D.DDRD n

34.700

34.900

33.500

34.400

33.500

34.400

n4 = 320

85.900

87.600

75.200

75.500

75.200

75.500

n3 = 1

4.700

23.800

5.200

23.300

5.200

23.300

n3 = 320

57.500

76.200

47.100

64.500

47.100

64.500

n3 = 1

5.300

23.800

5.800

23.300

5.800

23.300

n3 = 320

111.300

128.400

91.500

108.500

91.500

108.500

n3 = 1

5.000

23.800

4.300

23.300

4.300

23.300

n3 = 320

51.400

65.600

44.400

60.700

44.400

60.700

n3 = 1

11.600

17.700

10.600

13.900

10.600

13.900

142.000

149.000

142.000

149.000

422.000

448.000

422.000

448.000

Reading from

n3 = 1

5.200

23.800

5.600

23.300

5.600

23.300

n3 = 320

96.400

113.200

83.600

100.800

83.600

100.800

n3 = 1

12.900

20.800

12.200

17.100

12.200

17.100

other CPU

n3 = 320

277.000

299.000

274.000

291.000

274.000

291.000

shared memory

n3 = 1000

838.000

860.000

835.000

857.000

835.000

857.000

n=1

34.700

34.900

33.500

34.400

33.500

34.400

n=16

85.900

87.600

75.200

75.500

75.200

75.500

n=96

5.600

10.200

3.300

9.900

3.300

9.900

D1 D2

Reads devices
from another
CPU.

DP.DDRD n S1 S2 D1 D2

n4 = 1

463.000

D1 D2

instruction

Max.

160.000

sion dedicated

Min.

431.000

transmisS1 S2

Max.

n=1

36.700

42.400

34.300

39.200

34.300

39.200

n=16

5.000

12.100

3.100

10.500

3.100

10.500

n=96

59.100

66.800

55.300

65.100

55.300

65.100

n=1

3.300

12.700

2.400

9.600

2.400

9.600

n=16

50.900

64.400

45.200

48.200

45.200

48.200

n=96

11.600

17.700

10.600

13.900

10.600

13.900

n=1

142.000

160.000

142.000

149.000

142.000

149.000

n=16

431.000

463.000

422.000

448.000

422.000

448.000

n=96

6.700

12.600

2.800

9.900

2.800

9.900

Remark
the instructions for which a rise execution instruction ( P) is not specified, the
processing time is the same as an ON execution instruction.
Example WORDP instruction and TOP instruction

App-111

8
8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

speed

Min.

142.000

Writes devices to
another CPU.
S1 S2

Max.

n3 = 320

D.DDWR n S1 S2 D1 D2

CPU high-

Min.

n3 = 1000

Reading from

Multiple

Q10/Q13/Q20/
Q26UD(E)HCPU

other CPU

memory
D

Q04/
Q06UD(E)HCPU

shared memory
host CPU shared
DFRO n1 n2

Q03UD(E)CPU

(2) Table of the time to be added when file register, module access device or link direct device is used
(a) When using Q00UJCPU, Q00UCPUI, Q01UCPU and Q02UCPU
Device name

data
Bit

When standard
RAM is used

Word
Double word

When SRAM
File register (R)

card is used
(Q2MEM-1MBS,
Q2MEM-2MBS)

When SRAM
card is used
(Q3MEM-4MBS,
Q3MEM-8MBS)

Bit
Word
Double word
Bit
Word
Double word
Bit

When standard
RAM is used

Word
Double word

When SRAM
File register (ZR)

card is used
(Q2MEM-1MBS,
Q2MEM-2MBS)

When SRAM
card is used
(Q3MEM-4MBS,
Q3MEM-8MBS)

Bit
Word
Double word
Bit
Word
Double word
Bit

Module access device
(Un\G

, U3En\G0 to G4095)

Word
Double word
Bit

Link direct device
(Jn\

)

Word
Double word

App-112

Processing Time (µs)

Device Specification
Location

Q00UJCPU

Q00UCPU

Q01UCPU

Source

0.100

0.100

0.100

0.100

Destination

0.100

0.100

0.100

0.100

Q02UCPU

Source

0.100

0.100

0.100

0.100

Destination

0.100

0.100

0.100

0.100

Source

0.100

0.100

0.100

0.200

Destination

0.100

0.100

0.100

0.200

Source

––

––

––

0.220

Destination

––

––

––

0.180

Source

––

––

––

0.220

Destination

––

––

––

0.180

Source

––

––

––

0.440

Destination

––

––

––

0.380

Source

––

––

––

0.160

Destination

––

––

––

0.140

Source

––

––

––

0.160

Destination

––

––

––

0.140

Source

––

––

––

0.320

Destination

––

––

––

0.300

Source

0.120

0.120

0.120

0.120
0.120

Destination

0.120

0.120

0.120

Source

0.120

0.120

0.120

0.120

Destination

0.120

0.120

0.120

0.120

Source

0.120

0.120

0.120

0.220

Destination

0.120

0.120

0.120

0.220

Source

––

––

––

0.240

Destination

––

––

––

0.200

Source

––

––

––

0.240

Destination

––

––

––

0.200

Source

––

––

––

0.460

Destination

––

––

––

0.400

Source

––

––

––

0.180

Destination

––

––

––

0.160

Source

––

––

––

0.180

Destination

––

––

––

0.160

Source

––

––

––

0.340

Destination

––

––

––

0.320

Source

––

––

––

12.000

Destination

––

––

––

17.300

Source

––

––

––

9.700

Destination

––

––

––

33.000

Source

––

––

––

24.200

Destination

––

––

––

34.800

Source

––

––

––

32.900

Destination

––

––

––

67.300

Source

––

––

––

37.200

Destination

––

––

––

37.000

Source

––

––

––

39.500

Destination

––

––

––

41.900

(b) When using Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU,
Q13UD(E)HCPU, Q20UD(E)HCPU and Q26UD(E)HCPU
Device name

data

Bit
When standard
RAM is used

Word
Double word

When SRAM
File register (R)

card is used
(Q2MEM-1MBS,
Q2MEM-2MBS)

When SRAM
card is used
(Q3MEM-4MBS,
Q3MEM-8MBS)

Bit
Word
Double word
Bit
Word
Double word
Bit

When standard
RAM is used

Word
Double word

File rExtended
Extended link
register (W))
egister (ZR)

card is used
(Q2MEM-1MBS,
Q2MEM-2MBS)

When SRAM
card is used
(Q3MEM-4MBS,
Q3MEM-8MBS)

Bit
Word
Double word
Bit
Word
Double word
Bit

Module access device
(Un\G

, U3En\G0 to G4095)

Word
Double word
Bit

Link direct device
(Jn\

)

Word
Double word

Device Specification

Q04/

Q10/Q13/Q20/

Q06UD(E)HCPU

Q26UD(E)HCPU

0.100

0.048

0.048

Destination

0.100

0.038

0.038

Source

0.100

0.048

0.048

Destination

0.100

0.038

0.038

Source

0.200

0.095

0.095

Destination

0.200

0.086

0.086

Source

0.220

0.200

0.200

Destination

0.180

0.162

0.162

Location

Q03UD(E)CPU

Source

Source

0.220

0.200

0.200

Destination

0.180

0.162

0.162

Source

0.440

0.399

0.399

Destination

0.380

0.361

0.361

Source

0.160

0.152

0.152

Destination

0.140

0.133

0.133

Source

0.160

0.152

0.152

Destination

0.140

0.133

0.133

Source

0.320

0.304

0.304

Destination

0.300

0.295

0.295

Source

0.120

0.057

0.057

Destination

0.120

0.048

0.048

Source

0.120

0.057

0.057

Destination

0.120

0.048

0.048

Source

0.220

0.105

0.105

Destination

0.220

0.095

0.095

Source

0.240

0.209

0.209

Destination

0.200

0.171

0.171

Source

0.240

0.209

0.209

Destination

0.200

0.171

0.171

Source

0.460

0.409

0.409

Destination

0.400

0.371

0.371

Source

0.180

0.162

0.162

Destination

0.160

0.143

0.143

Source

0.180

0.162

0.162

Destination

0.160

0.143

0.143

Source

0.340

0.314

0.314

Destination

0.320

0.304

0.304

Source

11.700

11.200

11.200

Destination

15.400

15.300

15.300

Source

9.460

9.410

9.410

Destination

19.000

19.000

19.000

Source

11.000

10.900

10.900

Destination

18.800

18.700

18.700

Source

32.700

31.300

31.300

Destination

52.300

29.900

29.900

Source

28.500

17.300

17.300

Destination

27.500

14.700

14.700

Source

30.300

18.100

18.100

Destination

30.600

15.700

15.700

App-113

8
8
8
8
A
6
7
8

Appendix1 OPERATION PROCESSING TIME
Appendix 1.4 Operation Processing Time of Universal Model QCPU

data register (D)/

When SRAM

Processing Time (µs)

Appendix 2 CPU PERFORMANCE COMPARISON
Appendix 2.1 Comparison of Q with AnNCPU, AnACPU, and AnUCPU
Appendix 2.1.1

Usable devices
TableApp.2.1 Device Comparison

Device name

Number of I/O points*9

Number of I/O device points*8

QCPU

2048 points*1

Internal relay

Step
relay

8192 points*1
8192 points

2048 points*1

Latch relay
Sequence
program

8192 points

Same with I/O devices points of each CPU
Total 2048 points

Total 8192 points

8192 points

points*1

points*1

1024

1024 points*1

2048 points*1

Link relay

2048 points*1
1024 points

8192 points*1
2048 points

512 points*1

2048 points*1

2048

0 points*1

Retentive timers

512 points*1

Counter

––
––
A1N: 256 points
A2U: 512 points
A2A: 512 points
A2N: 512 points
A2U-S1: 1024 points A2A-S1: 1024 points A2N-S1: 1024 points
A3U: 2048 points
A3A: 2048 points
A3N: 2048 points
––
––
A4U: 4096 points

––

Edge relay

Timer

AnNCPU

––

Annunciator

Link special relay

AnACPU

*1

8192 points*1

2048 points*6

SFC

AnUCPU

Q02
Q02H
Q06H
Q12H
Q25H
Q02PH
Q06PH
Q12PH
4096
Q00J: 256 points Q00UJ: 256 points
points
Q25PH
Q00U:
1024
points
Q00: 1024 points
Q12PRH
Q01: 1024 points Q01U: 1024 points Q25PRH
Q03UD(E)
Q04UD(E)H
Q06UD(E)H
Q10UD(E)H
Q13UD(E)H
Q20UD(E)H
Q26UD(E)H
Q02U : 2048 points

1024 points*1

––

2048 points

2048 points

256 points

––

8192 points

4096 points
56 points

Total 2048 points
1024 points

1024 points

Total 256 points
256 points

Data register

11136

points*1

12288 points*1

8192 points

6144 points

1024 points

Link register

2048 points*1
1024 points

8192 points*1
2048 points

8192 points

4096 points
56 points

1024 points

Link special register
Function input

16 points (FX0 to FXF)*7

Function output

16 points (FY0 to FYF)*7
2048 points
5 points (FD0 to FD4)
2048 points

Special relay
Function register
Special register

1000 points
1000 points

Link direct device

Designated by J

Intelligent function module
device
Index
register

Z

Designated by U
10 points (Z0 to
Z9)

V*2

File register

32768 points/
block*5
(R0 to R32767)

Accumulator*3
Nesting
Pointer
Interrupt pointers
SFC blocks
SFC transition devices
Decimal constants
Hexadecimal constants
Real number constants*6
Character string

App-114

––
––

256 points
––

256 points

\

––

\G

––

16 points (Z0 to Z15)

7 points (Z, Z1 to Z6)

1 point (Z)

––

7 points (V, V1 to V6)

1 point (V)

32768 points/block(R0 to R32767)*10

8192 points/block(R0 to R8191)

––

300 points
128 points
126*6
––

E±

15 points
512 points
4096 points
128 points
256 points
320 points
512 points
K - 2147483648 toK2147483647
H0 to HFFFFFFFF
1.17550-38 to E ± 3.40282+38
"QnACPU",

"ABCD"*4

2 points
8 points
256 points
32 points
––
––

––
––

*1
*2
*3

: The number of device points can be changed at the parameters.
: QCPU uses V as an edge relay.
: Instructions that used accumulators with the AnNCPU, AnACPU, and AnUCPU have different formats with
the QCPU.
*4 : Can only be used by the $MOV instruction with the Q00JCPU, Q00CPU, and Q01CPU.
*5 : The Q00JCPU does not have file registers.
*6 : Applicable to products with the first 5 digits of the serial number 04122 or higher
(Q00JCPU, Q00CPU, and QCPU).
*7 : Each 5 points of FX0 to FX4 and FY0 to FY4 can be used on the programs.
*8 : The number of points that can be used on the programs
*9 : The number of accessible points to actual I/O modules
*10 : The Q00UJCPU does not have file registers.%ParaEnd%

Appendix 2.1.2

I/O control mode

8
8
8
8

TableApp.2.2 I/O Control Mode
I/O control mode

QCPU

AnUCPU

AnACPU

AnNCPU

Partial refresh instructions
Direct

Dedicated instruction*1

I/O method

Direct access input

––

––

––

Direct access output

––

––

––

––

––

Direct mode

––

*2

6

––

––

*1

*2

Symbol in table
: Usable, ––: Unusable
: The DOUT, DSET, and SRST instructions are direct output dedicated instructions.
There are no dedicated instructions for direct input.
: Switching between the refresh mode and direct mode is conducted with an AnNCPU DIP switch.

Data that can be used by instructions
TableApp.2.3 Data That Can Be Used by Instruction

Setting Data

QCPU

AnUCPU

AnACPU

AnNCPU

––

––

––

Bit device

Word data

Word device

Bit device

(Bit specification required)

(Digit specification required)

(Digit

(Digit

(Digit

specification

specification

specification

required)

required)

required)

Word device

Double word data

Bit device

(Digit specification required)

(Digit

(Digit

(Digit

specification

specification

specification

required)

required)

required)

Word device
Real number data

*1

Character string data

*2

*1
*2

––
––

––

Symbols in table
: Applicable to products with the first 5 digits of the serial number 04122 or higher
(Q00JCPU, Q00CPU, and Q01CPU).
: Usable with only the MOV instruction for the Q00JCPU, Q00CPU, and Q01CPU.

––

: Usable, –– : Unusable

App-115

7
8

Appendix2 CPU PERFORMANCE COMPARISON
Appendix 2.1 Comparison of Q with AnNCPU, AnACPU, and AnUCPU

Appendix 2.1.3

Bit data

A

*2

Refresh mode

Appendix 2.1.4

Timer comparison
TableApp.2.4 Timer Comparison

Function

QCPU

Measurement
unit

Change of measurement unit at the parameter is enabled.
QCPU

Low speed timer

AnUCPU

AnACPU

AnNCPU

100ms (default value)
Fixed at 100ms

: 1 to 1000ms (1ms unit)

K100
T0

Designation
method

K100
T0

10ms (default value)
Change of measurement unit at the parameter is enabled.
Measurement
unit

QnUCPU

: 0.01 to 100ms (0.01ms unit)

Fixed at 10ms

QCPU(Other than QnUCPU)
: 0.1 to 100ms (0.1ms unit)

High speed timer

High speed timer specification
H
T0

Designation
method

K100
T200

K100

High speed timer setting: Conducted by sequence program
Measurement
unit
Retentive timers

Same measurement unit as low speed timer

Designation

unit

K100
T0

Same measurement unit as high speed timer

High speed timer specification

High speed retentive timer

Fixed at 100ms

K100
ST0

method
Measurement

High speed timer setting: Conducted at parameters

H
K100
ST0

Designation

None

method
High speed timer setting: Conducted by sequence program
Setting range for set values
Processing for set value 0

Index modification

1 to 32767

1 to 32767

Momentarily ON

No maximum (does not time out)

Contact

Enabled (only Z0 and Z1 are usable)

Enabled

Disabled

Coil

Enabled (only Z0 and Z1 are usable)

Disabled

Disabled

Enabled (Z0 to Z15 are

usable)*1

Disabled

Disabled

Present value Enabled (Z0 to Z15 are

usable)*1

Enabled

Enabled

Set value

Update processing for present value
Contact ON/OFF processing

*1

When OUT Tn instruction is executed

When END processing is done

: The Q00J/Q00/Q01CPU can use Z0 to Z9.
The Universal model QCPU can use Z0 to Z19.

(1) Cautions on using timers
QCPU updates the present value of timers and turns ON/OFF the contacts of them at the
execution of OUT T
instruction.
Therefore, if "Present value Set value" when the timer coil is turned ON, the contact of
that timer is turned ON.
When creating a program in which the operation of the timer contact triggers the operation of
another timer, create the program for the timer that operates later first.
In the following cases, all timers go ON at the same scan if the program is created in the
order the timers operate.
• With high speed timers, if the set value is smaller than a scan time.
• With slow timers, if "1" is set.

App-116

Example

8

• For timers T0 to T2, the program is created in the order the timer operates later.
T1

T0

X0

K1
T2

T2 timer starts measurement from the next scan after turning the contact of T1 ON.

K1
T1

T1 timer starts measurement from the next scan after turning the contact of T0 ON.

K1
T0

T0 timer starts measurement when X0 is turned ON.

8
8
8

• For timers T0 to T2, the program is created in the order of timer operation.
X0

K1
T0

T0

A

T0 timer starts measurement when X0 is turned ON.

K1
T1

T1

6
Contacts of T1 and T2 timers are turned ON when contact of T0 is turned ON.

K1
T2

7

Appendix 2.1.5

Comparison of counters

8

TableApp.2.5 Comparison of Counters
Function

QCPU

AnACPU

AnNCPU

K100
C0

Contact

• Enabled (only Z0 and Z1 are usable)

• Enabled

• Disabled

Coil

• Enabled (only Z0 and Z1 are usable)

• Disabled

• Disabled

Set value

• Disabled

• Disabled

• Disabled

• Enabled (Z0 to Z15 are usable)*1

• Enabled

• Enabled

• When OUT Cn instruction is executed

• When END processing is done

Present
value
Update processing for present value
Contact ON/OFF processing

*1: The Q00J/Q00/Q01CPU can use Z0 to Z9.
The Universal model QCPU can use Z0 to Z19.

Appendix 2.1.6

Comparison of display instructions
TableApp.2.6 Comparison of Display Instructions

Instruction

QCPU
• When SM701 is OFF: Output continued until

PR*1

00H encountered
• When SM701 is ON: 16 characters output

AnUCPU

AnACPU

AnNCPU

• When M9049 is OFF: Output continued until 00H
encountered
• When M9049 is ON: 16 characters output

• When SM701 is OFF: 32-character comment
PRC*1

output
• When SM701 is ON: Upper 16 characters

16-character comment output

output
*1: Unusable for the Q00J/Q00/Q01CPU.

App-117

Appendix2 CPU PERFORMANCE COMPARISON
Appendix 2.1 Comparison of Q with AnNCPU, AnACPU, and AnUCPU

K100
C0

Designation method

Index modification

AnUCPU

Appendix 2.1.7

Instructions whose designation format has been
changed (Except dedicated instructions for
AnACPU and AnUCPU)

Because the QCPU does not have accumulators (A0, A1), the format of AnUCPU, AnACPU and
AnNCPU instructions that used accumulators has been changed.
TableApp.2.7 Instructions Whose Expression Has Changed
QCPU

Function

Instruction Format
ROR

D

n

16-bit
rotation to right

n

ROL

D

n

• D : Rotation data

ROL

n

RCL

D

n

• D : Rotation data
• SM700 is used for
carry flag.

RCL

n

DROR

D n

• D : Rotation data

DROR

n

DRCR

D

• D : Rotation data
• SM700 is used for
carry flag.

DRCR

n

DROL

D n

• D : Rotation data

DROL

n

DRCL

D

• D : Rotation data
• SM700 is used for
carry flag.

DRCL

n

n

n

SER

32-bit data search

DSER S1 S2 D n

S1 S2 D n

SUM

S D

DSUM

S D

Partial refresh

RFS

D n

8-character ASCII conversion

$MOV (Character string) D

Carry flag set

SET

SM700

Carry flag reset

RST

SM700

data bit check
16-bit
data bit check

Jump to END instruction

n

RCR

16-bit data search

16-bit

ROR

• D : Rotation data
• SM700 is used for
carry flag.

32-bit
rotation to left

• D : Rotation data

D n

32-bit
rotation to right

GOEND

CHKST
CHK instruction*1

• Search results are
stored at the D and
D+1 devices.
• Search results are
stored at the D and
D+1 devices.
• Check results are
stored at the D
device.
• Check results are
stored at the D
device.
• Dedicated
instruction is added.
––
• No dedicated
instruction
• No dedicated
instruction
• Dedicated
instruction is added.
• The CHKST
instruction is added.

CHK

*1: Unusable for the Q00J/Q00/Q01CPU.

App-118

Instruction Format

RCR

16-bit
rotation to left

AnUCPU/AnACPU/AnNCPU
Remarks

Remarks
• Rotation data are set
at A0.
• Rotation data are set
at A0.
• M9012 is used for
carry flag.
• Rotation data are set
at A0.
• Rotation data are set
at A0.
• M9012 is used for
carry flag.
• Rotation data are set
at A0 and A1.
• Rotation data are set
at A0 and A1.
• M9012 is used for
carry flag.
• Rotation data are set
at A0 and A1.
• Rotation data are set
at A0 and A1.
• M9012 is used for
carry flag.

SER

S1 S2 n

• Search results are
stored at A0 and A1.

DSER

S1 S2 n

• Search results are
stored at A0 and A1.

SUM

S

• Check results are
stored at A0.

DSUM

S

• Check results are
stored at A0.

SEG

D n

ASC

(Character string) D

• Only when M9052 is
ON
––

STC

––

CLC

––

CJ

P255

• P255: END instruction
designation

CJ Pn

––
P254

CHK

Appendix 2.1.8

AnACPU and AnUCPU dedicated instructions

8

(1) Method of expression of dedicated instructions
Dedicated instructions based on the LEDA, LEDB, LEDC, SUB, and LEDR instructions, that
are used with the AnACPU or AnUCPU have been changed for the same format as the
basic instructions and the application instructions for the QCPU.
The instructions that cannot be converted due to the absence of the corresponding
instructions in the QCPU are converted into OUT SM1255/OUT SM999 (for the Q00J/Q00/
Q01CPU).
The instructions that have been converted into OUT SM1255/OUT SM999 should be
replaced by other instructions or deleted.

8
8
8

TableApp.2.8 Method of Expression of Dedicated Instruction
QCPU

AnUCPU/AnACPU

Command
LEDA(B)

Command
Instruction name S

D

n

A

Instruction name

LEDC/SUB

S

LEDC/SUB

D

LEDC/SUB

n

6
7

LEDR
: S, D, and n indicate data used by instructions.

8
(2) Dedicated instructions whose names have been changed

TableApp.2.9 Method of Expression of Dedicated Instruction
QCPU

AnUCPU/AnACPU

Floating point addition

Function

E+

ADD

Floating point subtraction

E

SUB

Floating point multiplication

E*

MUL

Floating point division

E/

DIV

Data dissociation

NDIS

DIS

Data association

NUNI

UNI

CHKCIR,CHKEND

CHK, CHKEND

Updating check patterns

App-119

Appendix2 CPU PERFORMANCE COMPARISON
Appendix 2.1 Comparison of Q with AnNCPU, AnACPU, and AnUCPU

Dedicated instructions for the AnUCPU or AnACPU which have the same instruction name
as is used for basic instructions and application instructions have undergone name changes
in the QCPU.

Appendix 3 SPECIAL RELAY LIST
Special relays, SM, are internal relays whose applications are fixed in the Programmable
Controller.
For this reason, they cannot be used by sequence programs in the same way as the normal
internal relays.
However, they can be turned ON or OFF as needed in order to control the CPU module.
The heading descriptions in the following special relay lists are shown in 3.1.
TableApp.3.1 Explanation of special relay list
Item

Function of Item

Number

• Indicates special register number

Name

• Indicates name of special relay

Meaning

• Indicates contents of special relay

Explanation

• Discusses contents of special relay in more detail
• Indicates whether the relay is set by the system or user, and, if it is set by the system, when setting is performed.

S

: Set by system

U

: Set by user (sequence programs or test operations from GX Developer)

S/U

: Set by both system and user


Set by
(When set)

Indicated only for registers set by system
Each END

: Set during each END processing

Initial

: Set only during initial processing (when power supply is turned ON, or when going from STOP

Status change

: Set only when there is a change in status

Error

: Set when error occurs

to RUN)

Instruction execution : Set when instruction is executed
Request

: Set only when there is a user request (through SM, etc.)

System switching

: Set when system switching is executed.

• Indicates the corresponding special relay (M9

) of the ACPU.

Corresponding

(When the contents are changed, the special relay is represented M9

ACPU M9

Q00J/Q00/Q01 and QnPRH.)

format change. Incompatible with the

• New indicates the special relay newly added to the Q series CPU module.
Indicates the corresponding CPU module type name.
QCPU

: Indicates all the Q series CPU modules.

Q00J/Q00/Q01

: Indicates the Basic model QCPU.

Corresponding

Qn(H)

: Indicates the High Performance model QCPU.

CPU

QnPH

: Indicates the Process CPU.

QnPRH

: Indicates the Redundant CPU.

QnU

: Indicates the Universal model QCPU

Each CPU module model name: Indicates the relevant specific CPU module. (Example: Q02U)

For details on the following items, refer to the following manuals:
• Networks
Manual of the corresponding network module
• SFC
QCPU(Q mode)/QnACPU Programming Manual (SFC)

POINT
Do not change the values of special relays set by the system with user program or
device test operations.
Doing so may result in system downtime or communication fault.

App-120

(1) Diagnostic Information

8

TableApp.3.2 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

M9

SM0

SM1

Diagnostic errors

Self-diagnostic error

OFF : No error
ON : Error

OFF : No self-diagnosis
errors
ON : Self-diagnosis

• Turns ON if an error occurs as a result of diagnosis.
(Includes when an annunciator is ON, and when an
error is detected with CHK instruction)
• Remains ON even if the condition is restored to
normal thereafter.

S (Error)

New

Qn(H)
QnPH
QnPRH

• Turns ON if an error occurs as a result of diagnosis.
(Includes when an annunciator is ON)
• Remains ON even if the condition is restored to
normal thereafter.

S (Error)

New

Q00J/Q00/Q01
QnU

• Turns ON if an error occurs as a result of diagnosis.
(Does not include when an annunciator is ON or
when an error is detected by the CHK instruction)
• Remains ON even if the condition is restored to
normal thereafter.

S (Error)

M9008

Qn(H)
QnPH
QnPRH

• Turns ON if an error occurs as a result of diagnosis.
(Does not include when an annunciator is ON)
• Remains ON even if the condition is restored to
normal thereafter.

S (Error)

New

Error common
information

OFF : No error common
information
ON : Error common
information

• When SM0 is ON, turns ON if there is error common
information

S (Error)

New

SM16

Error individual
information

OFF : No error individual
information
ON : Error individual
information

• When SM0 is ON, turns ON if there is error individual
information

S (Error)

New

SM50

Error reset

OFF

• Conducts error reset operation

SM51

SM53

Battery low

AC/DC DOWN
detection

OFF : Normal
ON : Battery low

OFF : Normal
ON : Battery low

OFF : AC/DC DOWN not
detected
ON : AC/DC DOWN
detected

U

New

• Turns ON if battery voltage at CPU module or
memory card drops below rated value.
• Remains ON even if the battery voltage returns to
normal thereafter.
• Synchronizes with the BAT. LED.

S (Error)

M9007

Qn(H)
QnPH
QnPRH
QnU

• Turns ON if battery voltage at CPU module drops
below rated value.
• Remains ON even if the battery voltage returns to
normal thereafter.
• Synchronous with ERR. LED

S (Error)

New

Q00J/Q00/Q01

• Same as SM51, but turns OFF subsequently when
battery voltage returns to normal.

S (Error)

M9006

S (Error)

M9005

• Turns ON if an instantaneous power failure of within
10ms occurs during use of the DC power supply
module.
Reset when the power supply is switched OFF, then
ON.

A

Q00J/Q00/Q01
QnU

QCPU

• Turns ON if an instantaneous power failure of within
20ms occurs during use of the AC power supply
module.
Reset when the power supply is switched OFF, then
ON.

8

QCPU

App-121

7
8

Appendix 3 SPECIAL RELAY LIST

SM52

Battery low latch

8

8

SM5

ON: Error reset

8

TableApp.3.2 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

M9
SM56

SM60

Operation error

OFF : Normal
ON : Operation error

• ON when operation error is generated
• Remains ON if the condition is restored to normal
thereafter.

S (Error)

M9011

Blown fuse detection

OFF : Normal
ON : Module with blown
fuse

• Turns ON if there is at least one output module
whose fuse has blown.
• Remains ON if the condition is restored to normal
thereafter.
• Blown fuse status is checked even for remote I/O
station output modules.

S (Error)

M9000

S (Error)

M9002

QCPU

SM61

I/O module verify error

OFF : Normal
ON : Error

• Turns ON if the I/O module differs from the status
registered at power on.
• Remains ON if the condition is restored to normal
thereafter.
• I/O module verification is also conducted for remote
I/O station modules.

SM62

Annunciator detection

OFF : Not detected
ON : Detected

• Goes ON if even one annunciator (F) goes ON.

S (Instruction
execution)

M9009

SM80

CHK detection

OFF : Not detected
ON : Detected

• Goes ON if error is detected by CHK instruction.
• Remains ON if the condition is restored to normal
thereafter.

S (Instruction
execution)

New

SM90

Corresponds
to SD90

M9108

SM91

Corresponds
to SD91

M9109

SM92

Corresponds
to SD92

M9110

SM93

Corresponds
to SD93

SM94

Corresponds
to SD94

SM95

Startup of monitoring
timer for step transition
(Enabled only when
SFC program exists)

OFF : Not started(monitoring
timer reset)
ON : Started(monitoring
timer started)

Corresponds
to SD95

M9111
• Goes ON when measurement of
step transition monitoring timer is
commenced.
• Resets step transition monitoring
timer when it goes OFF.

M9112
U
M9113

SM96

Corresponds
to SD96

M9114

SM97

Corresponds
to SD97

New

SM98

Corresponds
to SD98

New

SM99

Corresponds
to SD99

New

SM100

Serial communication
function using flag

OFF : Serial communication
function is not used.
ON : Serial communication
function is used.

• Stores the setting of whether the serial
communication function is used or not in the serial
communication setting parameter

S (Power-ON or
reset)

SM101

Communication
protocol status flag

OFF : GX Developer
ON : MC protocol
communication device

• Stores whether the device that is communicating via
the RS-232 interface is GX Developer or MC protocol
communication device

S (RS232
communication)

SM110

Protocol error

OFF : Normal
ON : Abnormal

• Turns ON when an abnormal protocol was used to
make communication in the serial communication
function.
• Remains ON if the condition is restored to normal
thereafter

S (Error)

S (Error)

U

SM111

Communication status

OFF : Normal
ON : Abnormal

• Turns ON when the mode used to make
communication was different from the setting in the
serial communication function.
• Remains ON if the condition is restored to normal
thereafter.

SM112

Error information clear

ON : Cleared

• Turns ON when the error codes stored in SM110,
SM111, SD110 and SD111 are cleared. (Activated
when turned from OFF to ON)

SM113

Overrun error

OFF : Normal
ON : Abnormal

• Turns ON when an overrun error occurred in the
serial communication error.

S (Error)

SM114

Parity error

OFF : Normal
ON : Abnormal

• Turns ON when a parity error occurred in the serial
communication error.

S (Error)

SM115

Framing error

OFF : Normal
ON : Abnormal

• Turns ON when a framing error occurred in the serial
communication error.

S (Error)

OFF : Completed
ON : Not being executed or
Not completed

• Turns ON when the data is written to the program
cache memory.
• Turns OFF when the program memory batch transfer
is completed.
• Remains ON if the program memory batch transfer is
not executed after the data is written to the program
cache memory.

S (When status
changed)

SM165

Program memory
batch transfer
execution status

*6: The relevant modules are as follows:
• The Universal model QCPU whose serial number (first five digits) is "10012" or later.
• Q13UDHCPU, Q26UDHCPU
*7: The module whose first 5 digits of serial No. is "10102" or later.

App-122

Qn(H)
QnPH
QnPRH

New

Qn(H)
QnPH
QnPRH

Q00/Q01
Q00UJ
Q00U
Q01U
Q02U*7

New

QnU*6

(2) System information
TableApp.3.3 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

8
Corresponding
CPU

M9
SM202

LED OFF command

OFF

ON : LED OFF

• When this relay goes from OFF to ON, the LEDs
corresponding to the individual bits at SD202 go off

U

New

SM203

STOP contact

STOP status

• Goes ON at STOP status

S (Status change)

M9042

SM204

PAUSE contact

PAUSE status

• Goes ON at PAUSE status

S (Status change)

M9041

SM206

PAUSE enable coil

OFF : PAUSE disabled
ON : PAUSE enabled

• PAUSE status is entered if this relay is ON when the
PAUSE contact goes ON

U

M9040

SM210

Clock data set request

OFF : Ignored
ON : Set request

• When this relay goes from OFF to ON and after END
instruction execution of subsequent scan, clock data
stored in SD210 to SD213 are written to the CPU
module.

U

M9025

SM211

Clock data error

OFF : No error
ON : Error

• ON when error is generated in clock data (SD210 to
SD213) value, and OFF if no error is detected.

S (Request)

M9026

SM213

Clock data read
request

OFF : Ignored
ON : Read request

• When this relay is ON, clock data is read to SD210 to
SD213 as BCD values.

U

M9028

SM220

CPU No.1 preparation
completed

OFF : CPU No.1 preparation
uncompleted
ON : CPU No.1 preparation
completed

Turned ON when access can be made to the CPU
module No.1 from the other CPU module at power-on
or reset operation. SM220 is used as interlock for
accessing the CPU module No.1 when the multiple
CPU synchronous setting is asynchronous.

SM221

CPU No.2 preparation
completed

OFF : CPU No.2 preparation
uncompleted
ON : CPU No.2 preparation
completed

Turned ON when access can be made to the CPU
module No.2 from the other CPU module at power-on
or reset operation. SM221 is used as interlock for
accessing the CPU module No.2 when the multiple
CPU synchronous setting is asynchronous.
Turned ON when access can be made to the CPU
module No.3 from the other CPU module at power-on
or reset operation. SM222 is used as interlock for
accessing the CPU module No.3 when the multiple
CPU synchronous setting is asynchronous.
Turned ON when access can be made to the CPU
module No.4 from the other CPU module at power-on
or reset operation. SM223 is used as interlock for
accessing the CPU module No.4 when the multiple
CPU synchronous setting is asynchronous.

Qn(H)
QnPH
QnPRH
QnU

QCPU

8
8
8
A

QnU

8
7

S (When status
changed)

New

SM222

CPU No.3 preparation
completed

OFF : CPU No.3 preparation
uncompleted
ON : CPU No.3 preparation
completed

SM223

CPU No.4 preparation
completed

OFF : CPU No.4 preparation
uncompleted
ON : CPU No.4 preparation
completed

SM235

Online module change
flag

OFF : Online module change
is not in progress
ON : Online module change
in progress

• Turns on during online module change. (for host
CPU)

SM236

Online module change
complete flag

OFF : Online module change
incomplete
ON : Online module change
complete

• Turns ON for one scan after online module change is
complete.
• This contact point can only be used by the scan
program. (for host CPU)

S (When online
module change is
complete)

New

SM237

Device range check
inhibit flag

OFF : Device range checked
ON : Device range not
checked

• Selects whether to check a device range during
execution of the BMOV, FMOV or DFMOV instruction
(only when the conditions for subset processing are
established).

U

New

QnU*8

8
QnU*5

New
QnPH

QnU*6

*5: The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
*6: The relevant modules are as follows:
• The Universal model QCPU whose serial number (first five digits) is "10012" or later.
• Q13UDHCPU, Q26UDHCPU
*8: The Universal model QCPU except the Q00UJCPU.

App-123

Appendix 3 SPECIAL RELAY LIST

S (During online
module change)

TableApp.3.3 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

M9

SM240

SM241

SM242

SM243

SM244

SM245

No. 1 CPU reset flag

OFF : No. 1 CPU reset
cancel
ON : No. 1 CPU resetting

• Goes OFF when reset of the No. 1 CPU is canceled.
• Comes ON when the No. 1 CPU is resetting
(including the case where the CPU module is
removed from the base).
The other CPUs are also put in reset status.

No. 2 CPU reset flag

OFF : No. 2 CPU reset
cancel
ON : No. 2 CPU resetting

• Goes OFF when reset of the No. 2 CPU is canceled.
• Comes ON when the No. 2 CPU is resetting
(including the case where the CPU module is
removed from the base).
The other CPUs result in "MULTI CPU DOWN" (error
code: 7000).

No. 3 CPU reset flag

OFF : No. 3 CPU reset
cancel
ON : No. 3 CPU resetting

• Goes OFF when reset of the No. 3 CPU is canceled.
• Comes ON when the No. 3 CPU is resetting (including the case where the CPU module is removed from
the base).
The other CPUs result in "MULTI CPU DOWN" (error
code: 7000).

No. 4 CPU reset flag

OFF : No. 4 CPU reset
cancel
ON : No. 4 CPU resetting

• Goes OFF when reset of the No. 4 CPU is canceled.
• Comes ON when the No. 4 CPU is resetting (including the case where the CPU module is removed from
the base).
The other CPUs result in "MULTI CPU DOWN" (error
code: 7000).

No. 1 CPU error flag

OFF : No. 1 CPU normal
ON : No. 1 CPU during stop
error

• Goes OFF when the No. 1 CPU is normal (including
a continuation error).
• Comes ON when the No. 1 CPU is during a stop
error.

No. 2 CPU error flag

OFF : No. 2 CPU normal
ON : No. 2 CPU during stop
error

• Goes OFF when the No. 2 CPU is normal (including
a continuation error).
• Comes ON when the No. 2 CPU is during a stop
error.

SM246

No. 3 CPU error flag

OFF : No. 3 CPU normal
ON : No. 3 CPU during stop
error

• Goes OFF when the No. 3 CPU is normal (including
a continuation error).
• Comes ON when the No. 3 CPU is during a stop
error.

SM247

No. 4 CPU error flag

OFF : No. 4 CPU normal
ON : No. 4 CPU during stop
error

• Goes OFF when the No. 4 CPU is normal (including
a continuation error).
• Comes ON when the No. 4 CPU is during a stop
error

OFF : Ignored
ON : Read

• When this relay goes from OFF to ON, maximum
loaded I/O number is read to SD250.

SM250

Max. loaded I/O read

Q00/Q01*1
Qn(H)*1
QnPH
QnU*8

S (Status change)

New
Qn(H)*1
QnPH
QnU*5

Q00/Q01*1
Qn(H)*1
QnPH
QnU*8

S (Status change)

New

QnU*5
U

New
Qn(H)
QnPH
QnPRH

• Effective for the batch refresh (also effective for the
low speed cyclic)
• Designate whether to receive arrival stations only or
to receive all slave stations in the MELSECNET/H.

SM254

All stations refresh
command

OFF : Refresh arrival station
ON : Refresh all stations

• Designate whether to receive arrival stations only or
to receive all slave stations in the CC-Link IE
controller network .
• Effective for the batch refresh (also effective for the
low speed cyclic)
• Specify whether to receive only arrival station or all
stations in the MELSECNET/H or CC-Link IE
controller network.

*1: This applies to the CPU of function version B or later.
*2: The module whose first 5 digits of serial No. is "09012" or later.
*5: The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
*6: The module whose first 5 digits of serial No. is "10042" or later.
*8: The Universal model QCPU except the Q00UJCPU.

App-124

Qn(H)*1
QnPH

Qn(H)*2
U

New

QnPH*6
QnPRH*6

QnU

TableApp.3.3 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

8

M9
SM255

OFF : Operative network
ON : Standby network

• Goes ON for standby network(If no designation has
been made concerning active or standby, active is
assumed.)

OFF : Reads
ON : Does not read

New

• For refresh from link to CPU module (B, W, etc.)
indicate whether to read from the link module.

U

New

OFF : Writes
ON : Does not write

• For refresh from CPU module to link (B, W, etc.),
designate whether to write to the link module.

U

New

OFF : Operative network
ON : Standby network

• Goes ON for standby network
(If no designation has been made concerning active
or standby, active is assumed.)

S (Initial)

New

OFF : Reads
ON : Does not read

• For refresh from link to CPU module (B, W, etc.)
indicate whether to read from the link module.

U

New

SM262

OFF : Writes
ON : Does not write

• For refresh from CPU module to link (B, W, etc.),
designate whether to write to the link module.

U

New

SM265

OFF : Operative network
ON : Standby network

• Goes ON for standby network
(If no designation has been made concerning active
or standby, active is assumed.)

S (Initial)

New

OFF : Reads
ON : Does not read

• For refresh from link to CPU module (B, W, etc.)
indicate whether to read from the link module.

U

New

OFF : Writes
ON : Does not write

• For refresh from CPU module to link (B, W, etc.),
designate whether to write to the link module.

U

New

OFF : Operative network
ON : Standby network

• Goes ON for standby network
(If no designation has been made concerning active
or standby, active is assumed.)

S (Initial)

New

OFF : Reads
ON : Does not read

• For refresh from link to CPU module (B, W, etc.)
indicate whether to read from the link module.

U

New

OFF : Writes
ON : Does not write

• For refresh from CPU module to link (B, W, etc.),
designate whether to write to the link module.

U

New

OFF : Normal
ON : Error

• Goes ON when a CC-Link error is detected in any of
the installed CC-Link module. Goes OFF when
normal operation is restored.

S (Status change)

New

U

New

S (Initial)

M9100

SM256
SM257

SM260

SM261

SM266

MELSECNET/10,
MELSECNET/H
module 2 information

MELSECNET/10,
MELSECNET/H
module 3 information

SM267

SM270

SM271

MELSECNET/10,
MELSECNET/H
module 4 information

SM272

SM280

CC-Link error

SM315

Communication
reserved time delay
enable/disable flag

OFF : Without delay
ON : With delay

• This flag is enabled when the time reserved for
communication processing is set in SD315.
• Turns ON to delay the END processing by the time
set in SD315 in order to perform communication
processing.
(The scan time increases by the period set in
SD315.)
• Turns OFF to perform the END processing without a
delay of the time set in SD315 when there is no
communication processing. (Defaults to OFF)

SM320

Presence/absence of
SFC program

OFF : SFC program absent
ON : SFC program present

• Turns ON when an SFC program is registered.
• OFF when an SFC program is not registered.

OFF : SFC program not
executed (stop)
ON : SFC program executed
(start)

• Initial value is set at the same value as SM320.
(Goes ON automatically if SFC program is present.)
• Turn this relay from ON to OFF to stop program
execution.
• Turn this relay from OFF to ON to resume program
execution.

SM321

Start/stop SFC
program

S (Initial)/U

M9101form
at change

8
8
8
Qn(H)
QnPH
QnPRH

A
8
7
8

Q00J/Q00/Q01

Q00J/Q00/Q01*1
Qn(H)
QnPH
QnPRH
QnU

*1: This applies to the CPU of function version B or later.

App-125

Appendix 3 SPECIAL RELAY LIST

S (Initial)

MELSECNET/10,
MELSECNET/H
module 1 information

TableApp.3.3 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

M9

SM322

SFC program start
status

OFF : Initial start
ON : Resume start

SM323

Presence/absence of
continuous transition
for entire block

OFF : Continuous transition
not effective
ON : Continuous transition
effective

SM324

Continuous transition
prevention flag

OFF : When transition is
executed
ON : When no transition

• The SFC program starting mode in the SFC setting
of the PLC parameter dialog box is set as the initial
value.
AT initial start: OFF
At continued start: ON

S (Initial)/U

M9102form
at change

Set the presence/absence of continuous transition for
the block where "Continuous transition bit" of the SFC
data device has not been set.

U

M9103

S (Instruction
execution)

M9104

S (Status change)

New

S (Initial)/U

M9196

U

New

• OFF during operation in the continuous transition
mode or during continuous transition, and ON when
continuous transition is not executed.
• Always ON during operation in the no continuous
transition mode.

SM325

Output mode at block
stop

OFF : OFF
ON : Preserves

Select whether the coil outputs of the active steps are
held or not at the time of a block stop.
• As the initial value, the output mode at a block stop in
the parameter is OFF when the coil outputs are OFF,
and ON when the coil outputs are held.
• All coil outputs go OFF when this relay is OFF.
• Coil outputs are preserved when this relay is ON.

SM326

SFC device clear
mode

OFF : Clear device
ON : Preserves device

Selects the device status when the stopped CPU is run
after the sequence program or SFC program has been
modified when the SFC program exists.

Output during end step
execution

OFF : Hold step output
turned OFF (cleared)
ON : Hold step output held

Select the device status at the time of switching from
STOP to program write to RUN.(All devices except the
step relay)

SM327

S (Initial)/U

New

Clear processing
mode when end step
is reached

Qn(H)
QnPH
QnPRH
QnU
Q00J/Q00/Q01*1

U

SM328

Q00J/Q00/Q01*1
Qn(H)
QnPH
QnPRH
QnU

OFF : Clear processing is
performed.
ON : Clear processing is not
performed.

Select whether clear processing will be performed or
not if active steps other than the ones being held exist
in the block when the end step is reached.?
• When this relay turns OFF, all active steps are
forcibly terminated to terminate the block.
• When this relay is ON, the execution of the block is
continued as-is.
• If active steps other than the ones being held do not
exist when the end step is reached, the steps being
held are terminated to terminate the block.

U

New

Q00J/Q00/Q01*1
QnU

Select whether the low speed execution type program
will be executed in the asynchronous mode or in the
synchronous mode.
• Asynchronous mode (this relay is turned OFF.)
Mode in which the operation of the low speed
execution type program is performed continuously
within the excess time.
• Synchronous mode (this relay is turned ON.)
Mode in which the operation of the low speed
execution type program is not performed
continuously and operation is performed from the
next scan if there is excess time.

U

New

Qn(H)
QnPH

S (Status change)

New

SM330

Operation mode for
low speed execution
type program

OFF : Asynchronous mode
ON : Synchronous mode

SM331

Normal SFC program
execution status

OFF : Not executed
ON : Being executed

• Indicates whether the normal SFC program is being
executed or not.
• Used as an SFC control instruction execution
interlock.

Qn(H)*3
QnPH*4
QnPRH

Program execution
management SFC
program execution
status

OFF : Not executed
ON : Being executed

• Indicates whether the program execution
management SFC program is being executed or not.
• Used as an SFC control instruction execution
interlock.

SM390

Access execution flag

ON indicates completion of
intelligent function module
access

• The status of the intelligent function module access
instruction executed immediately before is stored.
(This data is overwritten when the intelligent function
module access instruction is executed again.)
• Used by the user in a program as a completion bit.

S (Status change)

New

Qn(H)
QnPH
QnPRH

SM391

GINT instruction
execution completion
flag

OFF : Not executed
ON : Execution completed

Indicates execution status of the S(P).GINT instruction.
• Turned OFF before the instruction is executed.
• Turned ON after the instruction is completed.

S (Instruction
execution)

New

QnU

SM332

*1: This applies to the CPU of function version B or later.
*3: The module whose first 5 digits of serial No. is "04122" or later.
*4: The module whose first 5 digits of serial No. is "07032" or later.

App-126

(3) System clocks/counters

8

TableApp.3.4 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

M9
SM400

Always ON

ON
OFF

Always OFF

ON
OFF

• Normally is ON

S (Every END
processing)

• Normally is OFF

S (Every END
processing)

M9036
QCPU

SM401

SM402

After RUN, ON for 1
scan only

• After RUN, ON for 1 scan only.
• This connection can be used for scan execution type
programs only.
• When an initial execution type program is used, this
relay turns OFF at the END processing of the scan
execution type program in the first scan after RUN.

ON
OFF

1 scan

ON
OFF

Initial
execution
type program

• After RUN, OFF for 1 scan only.
• This connection can be used for scan execution type
programs only.
• When an initial execution type program is used, this
relay turns OFF at the END processing of the scan
execution type program in the first scan after RUN.
SM403

After RUN, OFF for 1
scan only

ON
OFF

1 scan

ON
OFF
Initial
execution
type program

Low speed execution
type programON for 1
scan only after RUN

SM405

Low speed execution
type programAfter
RUN, OFF for 1 scan
only

ON
OFF
ON
OFF

SM409

0.01 second clock

0.005s

SM410

0.1 second clock

0.05s

SM411

0.2 second clock

0.1s

SM412

1 second clock

0.5s

SM413

2 second clock

1s

SM414

2n second clock

0.5s

S (Every END
processing)

ns

Qn(H)
QnPH
QnPRH
QnU

S (Every END
processing)

New

Q00J/Q00/Q01

S (Every END
processing)

M9039

Qn(H)
QnPH
QnPRH
QnU

1 scan of scan
execution type
program

New

1 scan

• After RUN, ON for 1 scan only.
• This connection can be used for low speed execution type
programs only.

S (Every END
processing)

New

1 scan

• After RUN, OFF for 1 scan only.
• This connection can be used for low speed execution type
programs only.

S (Every END
processing)

New

• Repeatedly changes between ON and OFF at 5-ms
interval.
• When Programmable Controller power supply is
turned ON or a CPU module reset is performed,
goes from OFF to start.
(Note that the ON-OFF status changes when the
designated time has elapsed during the execution of
the program.)

S (Status change)

New

Qn(H)
QnPH

Qn(H)
QnPH
QnPRH
QnU

M9031
S (Status change)
M9032

M9033
• This relay alternates between ON and OFF at
intervals of the time (unit: s) specified in SD414.
• When Programmable Controller power supply is
turned ON or a CPU module reset is performed,
goes from OFF to start.
(Note that the ON-OFF status changes when the
designated time has elapsed during the execution of
the program.)

8
7

Q00J/Q00/Q01

M9030
• Repeatedly changes between ON and OFF at each
designated time interval.
• When Programmable Controller power supply is
turned ON or a CPU module reset is performed,
goes from OFF to start.
(Note that the ON-OFF status changes when the
designated time has elapsed during the execution of
the program.)

A

8

1s

ns

M9038

S (Every END
processing)

0.05s
0.1s

8

• After RUN, OFF for 1 scan only.

0.005s

8

S (Status change)

QCPU

M9034form
at change

App-127

Appendix 3 SPECIAL RELAY LIST

SM404

M9037

1 scan of scan
execution type
program

• After RUN, ON for 1 scan only.

8

TableApp.3.4 Special relay
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

M9

SM415

2n (ms) clock

SM420

User timing clock No.0

SM421

User timing clock No.1

SM422

User timing clock No.2

SM423

User timing clock No.3

SM424

User timing clock No.4

• This relay alternates between ON and OFF at
intervals of the time (unit: ms) specified in SD415.
• When Programmable Controller power supply is
turned ON or a CPU module reset is performed,
goes from OFF to start.
(Note that the ON-OFF status changes when the
designated time has elapsed during the execution of
the program.)

n(ms)
n(ms)

n2 scan

n2 scan

• Relay repeats ON/OFF switching at fixed scan
intervals.
• When Programmable Controller power supply is
turned ON or a CPU module reset is performed,
goes from OFF to start.
(For the redundant CPU, however, this relay is
always OFF after system switching.)
• The ON/OFF intervals are set with the DUTY
instruction

DUTY
n1 scan

SM430

User timing clock No.5

SM431

User timing clock No.6

SM432

User timing clock No.7

SM433

User timing clock No.8

SM434

User timing clock No.9

n1

n2

S (Status change)

New

Qn(H)
QnPH
QnPRH
QnU

M9020
M9021
M9022
M9023
S (Every END
processing)

QCPU
M9024

SM420

n1: ON scan interval
n2: OFF scan interval

• For use with SM420 to SM424 low speed programs

S (Every END
processing)

New

Qn(H)
QnPH

(4) Scan information
TableApp.3.5 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

M9
SM510

Low speed program
execution flag

OFF : Completed or not
executed
ON : Execution under way.

SM551

Reads module service
interval

OFF : Ignored
ON : Read

• Goes ON when low speed execution type program is
executed.
• When this relay goes from OFF to ON, the module
service interval designated by SD550 is read to
SD551 to SD552.

S (Every END
processing)

New

Qn(H)
QnPH

U

New

Qn(H)
QnPH
QnPRH

Set by
(When Set)

Corresponding
ACPU

(5) I/O refresh
TableApp.3.6 Special relay
Number

Name

Meaning

Explanation

Corresponding
CPU

M9

SM580

Program to program I/
O refresh

OFF : Not refreshed
ON : Refreshed

*1: This applies to the CPU of function version B or later.

App-128

• When this special relay is turned ON, I/O refresh is
performed after execution of the first program, and
the next program is then executed.
When a sequence program and an SFC program are
to be executed, the sequence program is executed,
I/O refresh is performed, and the SFC program is
then executed.

U

New

Q00J/Q00/Q01*1

(6) Memory cards
TableApp.3.7 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

8
Corresponding
CPU

8

M9
SM600

Memory card usable
flags

OFF : Unusable
ON : Use enabled

• ON when memory card is ready for use by user

S (Status change)

New

SM601

Memory card protect
flag

OFF : No protect
ON : Protect

• Goes ON when memory card protect switch is ON

S (Status change)

New

SM602

Drive 1 flag

OFF : No drive 1
ON : Drive 1 present

• Turns ON when the mounted memory card is RAM

S (Status change)

New

SM603

Drive 2 flag

OFF : No drive 2
ON : Drive 2 present

• Turns ON when the mounted memory card is ROM

S (Status change)

New

SM604

Memory card in-use
flag

OFF : Not used
ON : In use

• Goes ON when memory card is in use

S (Status change)

New

SM605

Memory card remove/
insert prohibit flag

OFF : Remove/insert enabled
ON : Remove/insert
prohibited

• Goes ON when memory card cannot be inserted or
removed

SM609

Memory card remove/
insert enable flag

OFF : Remove/insert
prohibited
ON : Remove/insert enabled

• Turned ON by user to enable the removal/insertion
of memory card.
• Turned OFF by the system after the memory card is
removed.
• This contact can be used only when SM604 and
SM605 are OFF.

SM620

Drive 3/4 usable flags

OFF : Unusable
ON : Use enabled

• Always ON

Drive 3 flag

OFF : No drive 3
ON : Drive 3 present

SM622

• Always ON

8
Qn(H)
QnPH
QnPRH
QnU*1

U

8

New

A
S/U

New

S (Initial)

New

S (Initial)

New

QCPU
Q00J/Q00/Q01
Qn(H)
QnPH
QnPRH

8
7

QnU*2
Drive 4 flag

OFF : No drive 4
ON : Drive 4 present

• Always ON

SM624

Drive 3/4 in-use flag

OFF : Not used
ON : In use

• Goes ON when the file within Drive 3 (standard
RAM) or Drive 4 (standard ROM) is used.

File register use

OFF : File register not used
ON : File register in use

SM640

• Goes ON when file register is in use

S (Initial)

New

QCPU

S (Status change)

New

Qn(H)
QnPH
QnPRH
QnU

S (Status change)

New

Q00J/Q00/Q01
Qn(H)
QnPH
QnPRH
QnU*2

*1: The Universal model QCPU except the Q00UJCPU, Q00UCPU, and Q01UCPU.
*2: The Universal model QCPU except the Q00UJCPU.

App-129

8

Appendix 3 SPECIAL RELAY LIST

SM623

TableApp.3.7 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

M9
SM650

SM660

Comment use

Boot operation

OFF : File register not used
ON : File register in use

• Goes ON when comment file is in use

S (Status change)

New

Qn(H)
QnPH
QnPRH
QnU

OFF : Internal memory
execution
ON : Boot operation in
progress

• Goes ON while boot operation is in process
• Goes OFF if boot designation switch is OFF

S (Status change)

New

Qn(H)
QnPH
QnPRH

OFF : Program memory
execution
ON : Boot operation in
progress

• Goes ON while boot operation is in process

S (Status change)

New

Q00J/Q00/Q01
QnU*1

SM671

Latch data backup to
standard ROM
completion flag

OFF : Not completed
ON : Completed

• Turned ON when latch data backup to the standard
ROM is completed.
• Time when the latch data backup to the standard
ROM was performed is stored in SD672 or later.

S (Status change)

New

QnU

SM672

Memory card file
register access range
flag

OFF : Within access range
ON : Outside access range

• Goes ON when access is made to area outside the
range of file register of memory card(Set within END
processing.)
• Reset at user program

S/U

New

Qn(H)
QnPH
QnPRH

SM675

Error completion of
latch data backup to
standard ROM

OFF : No Error
ON : Error

• Turned ON when data cannot be backuped to the
standard ROM by the latch data backup normally.
• Turned OFF when data is backuped to the standard
ROM by the latch data backup normally.

S

New

U

New

SM676

Specification of
restration repeated
execution

OFF : Not specified
ON : Specified

• If latch data backup is performed when SM676 is
ON, restore the data every time turning ON from
OFF the power supply from the next power-on.
• Delete the backuped latch data, or restore the data
every time turning ON from OFF the power supply
until the latch data backup operation will be executed
again.

SM680

Program memory write
error

OFF : Write error
ON : Write not executed/
normal

• Turns ON if a write error is detected at writing to
program memory (flash ROM).
Turns OFF by the write direction.

S (At write)

New

SM681

Program memory
writing flag

OFF : During writing
ON : Write not executed

• Turns ON when writing to the program memory (flash
ROM) is in progress, and turns OFF when writing is
completed.

S (At write)

New

SM682

Program memory
overwrite count error
flag

OFF : Overwrite count is
100,000 or more
ON : Overwrite count is less
than 100,000

• Turns ON when the overwrite count of program
memory (flash ROM) reaches 100,000.

S (At write)

New

SM685

Standard ROM write
error

OFF : Write error
ON : Write not executed/
normal

• Turns ON when write error is detected at writing to
standard ROM (flash ROM).
• Turns OFF by the write direction.

S (At write)

New

SM686

Standard ROM writing
flag

OFF : During overwriting
ON : Overwrite not executed

• Turns ON when writing to the standard ROM (flash
ROM) is in progress, and turns OFF when writing is
completed.

S (At write)

New

SM687

Standard ROM
overwrite count error
flag

OFF : Overwrite count is
100,000 or more
ON : Overwrite count is less
than 100,000

• Turns ON when the overwrite count of standard
ROM (flash ROM) reaches 100,000.
(It is necessary to change CPU module.)

S (At write)

New

SM691

Backup start
preparation status flag

OFF : Backup start
preparation not
completed
ON : Backup start
preparation completed

Turns on when the backup start preparation is
completed.

S (Status change)

New

Restoration complete
flag

OFF : Restoration not
completed
ON : Restoration completed

Turns on when restoration of the backup data in the
memory card is completed.

SM692

QnU

QnU*3
S (Status change)

New

*1: The Universal model QCPU except the Q00UJCPU, Q00UCPU, and Q01UCPU.
*3: The modules whose serial number (first five digits) is "10102" or later are the relevant models. (Except the Q00UJCPU, Q00UCPU, and Q01UCPU)

App-130

(7) Instruction-Related Special Relays
TableApp.3.8 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

8

M9
Carry flag

OFF : Carry OFF
ON : Carry ON

SM701

Number of output
characters selection

Switching the number of
output characters and the
output pattern

• Used for the PR, PRC, BINDA, DBINDA, BINHA,
DBINHA, BCDDA, DBCDDA, or COMRD instruction

SM702

Search method

OFF : Search next
ON : 2-part search

SM703

Sort order

OFF : Ascending order
ON : Descending order

SM704

Block comparison

OFF : Non-match found
ON : All match

SM700

SM709

DT/TM instruction
improper data
detection flag

OFF : Improper data not
detected
ON : Improper data detected

SM710

CHK instruction
priority ranking flag

OFF : Conditions priority
ON : Pattern priority

EI flag

OFF : During DI
ON : During EI

SM715

SM716

Block comparison
(Except an interrupt
program)

• Carry flag used in application instruction

M9012

QCPU

U

M9049

Qn(H)
QnPH
QnPRH
QnU

• Designates method to be used by search instruction.
• Data must be arranged for 2-part search.

U

New

• The sort instruction is used to designate whether
data should be sorted in ascending order or in
descending order.

U

New

• Goes ON when all data conditions have been met for
the BKCMP instruction.

S (Instruction
execution)

New

• Goes ON when all data conditions have been met for
the DBKCMP instruction.

S (Instruction
execution)

New

S (Instruction
execution) or U

New

• Remains as originally set when OFF.
• CHK priorities updated when ON.

S (Instruction
execution)

New

Qn(H)
QnPH
QnPRH

• ON when EI instruction is being executed.

S (Instruction
execution)

New

QCPU

Turns on when the data to be compared by the DT or
TM instruction is not recognized as date data or time
data, or the device (3 words) to be compared exceeds
the specified device range.

OFF : Mismatch found
ON : No mismatch

Turns on when all data conditions are confirmed that
they are met by the DBKCMP instruction.
(Initial execution type program, scan execution type
program, stand-by type program executed from initial
execution type program or scan execution type
program)

Block comparison
(Interrupt program)

OFF : Mismatch found
ON : No mismatch

SM718

Block comparison
(Interrupt program
(I45))

OFF : Mismatch found
ON : No mismatch

Turns on when all data conditions are confirmed that
they are met by the DBKCMP instruction.
(Interrupt program (I45) or Stand-by type program
executed from interrupt program (I45))

SM720

Comment read
completion flag

OFF : Comment read not
completed
ON : Comment read
completed

SM721

SM722

File being accessed

BIN/DBIN instruction
error disabling flag

OFF : Error detection
performed
ON : Error detection not
performed

• Turns on only during one scan when the processing
of the COMRD or PRC instruction is completed.
• Turns on only during one scan when the processing
of the COMRD instruction is completed.

8

QCPU

8
QnU*2

A
8
7

QnU*2
S (Instruction
execution)

New

8

QnU*3

S (Status change)

New

Qn(H)
QnPH
QnPRH
QnU

• Switches ON while a file is being accessed by the
SP. FWRITE, SP. FREAD, COMRD, PRC, or LEDC
instruction.

Qn(H)
QnPH

• Switches ON while a file is being accessed by the
SP. FWRITE, SP. FREAD, COMRD or LEDC instruction.

Qn(H)
QnPH
QnPRH

S (Status change)

New

• Switches ON while a file is being accessed by the
SP. FWRITE, SP. FREAD, COMRD or SP.DEVST
instruction.

QnU

• Turns ON while the ATA card or standard ROM is
being accessed.

QnU*1

• Turned ON when "OPERATION ERROR" is
suppressed for BIN or DBIN instruction.

8

U

New

QCPU

*1: The module whose first 5 digits of serial No. is "09042" or later.
*2: The relevant modules are as follows:
• The Universal model QCPU whose serial number (first five digits) is "10102" or later.
• Q00UJCPU, Q00UCPU, Q01UCPU
*3: The relevant modules are as follows:
• The Universal model QCPU whose serial number (first five digits) is "10102" or later.
• Q00UCPU, Q01UCPU

App-131

Appendix 3 SPECIAL RELAY LIST

SM717

Turns on when all data conditions are confirmed that
they are met by the DBKCMP instruction.
(Interrupt program, fixed scan execution type program,
stand-by type program executed from interrupt program
or fixed scan execution type program)

OFF : File not accessed
ON : File being accessed

S (Instruction
execution)

TableApp.3.8 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

M9

SM734

XCALL instruction
execution condition
designation

OFF : Not executed by
execution condition
risen
ON : Executed by execution
condition risen

SM735

SFC comment readout
instruction in
execution flag

OFF : SFC comment readout
instruction is
inactivated.
ON : SFC comment readout
instruction is
activating.

• Turns on the instructions, (S(P).SFCSCOMR) to
read the SFC step comments and (S(P).
SFCTCOMR) to read the SFC transition condition
comments.

SM738

MSG instruction
reception flag

OFF : Instruction not
executed
ON : Instruction execution

• Goes ON when MSG instruction is executed

S (Instruction
execution)

New

Qn(H)
QnPRH

SM750

Scaling instruction
search method setting

OFF : Search next
ON : 2-part search

Determines a search method when the scaling
instruction is executed.

U

New

QnU*8

SM774

PID bumpless
processing
(for complete
derivative)

OFF : Matched
ON : Not matched

• Specifies whether to match the set value (SV) with
the process value (PV) or not in the manual mode.

U

New

Q00J/Q00/Q01*4
Qn(H)
QnPRH
QnU

OFF : Performs link refresh
ON : Performs no link
refresh

• Select whether link refresh processing will be
performed or not when only communication with the
CPU module is made at the execution of the COM
instruction.

U

New

Q00J/Q00/Q01
Qn(H)
QnPH

OFF : Performs refresh
processes other than
an I/O refresh
ON : Performs refresh set
by SD778

• Select whether to perform refresh processes other
than an I/O refresh set by SD778 when the COM or
CCOM instruction is executed.

U

New

QnPH*3
QnPRH
QnU

SM775

Selection of refresh
processing during
COM/CCOM
instruction execution

• During OFF, XCALL instructions will not be executed
even if execution condition is risen.
• During ON, XCALL instructions will be executed
when execution condition is risen.

U

New

S (status change)

New

Qn(H)*1

Qn(H)*2
QnPH*3
QnPRH*3

Q00J/Q00/Q01*4
Qn(H)*5

SM776

Enable/disable local
device at CALL

OFF : Local device disabled
ON : Local device enabled

• Set whether the local device of the subroutine
program called at execution of the CALL instruction
is valid or invalid.

U

New

SM777

Enable/disable local
device in interrupt
program

OFF : Local device disabled
ON : Local device enabled

• Set whether the local device at execution of the
interrupt program is valid or invalid.

Qn(H)
QnPH
QnPRH

U

New

QnU*9

SM794

PID bumpless
processing(for
incomplete derivative)

OFF : Matched
ON : Not matched

• Specifies whether to match the set value (SV) with
the process value (PV) or not in the manual mode.

U

New

Q00J/Q00/Q01*4

*1: The module whose first 5 digits of serial No. is "06082" or later.
*2: The module whose first 5 digits of serial No. is "07012" or later.
*3: The module whose first 5 digits of serial No. is "07032" or later.
*4: This applies to the CPU module of function version B or later.
*5: The module whose first 5 digits of serial No. is "04012" or later.
*6: The module whose first 5 digits of serial No. is "05032" or later.
*8: The relevant modules are as follows:
• The Universal model QCPU whose serial number (first five digits) is "10102" or later.
• Q00UJCPU, Q00UCPU, Q01UCPU
*9: The Universal model QCPU except the Q00UJCPU.

App-132

Qn(H)*6
QnPRH
QnU

TableApp.3.8 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

8

M9

SM796

Block information
using multiple CPU
high-speed
transmission
dedicated instruction
(for CPU No.1)

OFF : Block is secured
ON : Block set by SD796
cannot be secured

• Turns ON when the number of the remaining blocks
of the dedicated instruction transmission area used
for the multiple CPU high-speed transmission
dedicated instruction(target CPU= CPU No.1) is less
than the number of blocks specified by SD796.
Turns ON at instruction execution. Turns OFF when
the empty area exists at END processing.

SM797

Block information
using multiple CPU
high-speed
transmission
dedicated instruction
(for CPU No.2)

OFF : Block is secured
ON : Block set by SD797
cannot be secured

• Turns ON when the number of the remaining blocks
of the dedicated instruction transmission area used
for the multiple CPU high-speed transmission
dedicated instruction (target CPU= CPU No.2) is less
than the number of blocks specified by SD797.
Turns ON at instruction execution. Turns OFF when
the empty area exists at END processing.

S (When
instruction/END
processing
executed)

SM798

Block information
using multiple CPU
high-speed
transmission
dedicated instruction
(for CPU No.3)

OFF : Block is secured
ON : Block set by SD798
cannot be secured

• Turns ON when the number of the remaining blocks
of the dedicated instruction transmission area used
for the multiple CPU high-speed transmission
dedicated instruction (target CPU= CPU No.3) is less
than the number of blocks specified by SD798.
Turns ON at instruction execution. Turns OFF when
the empty area exists at END processing.

S (When
instruction/END
processing
executed)

SM799

Block information
using multiple CPU
high-speed
transmission
dedicated instruction
(for CPU No.4)

OFF : Block is secured
ON : Block set by SD799
cannot be secured

• Turns ON when the number of the remaining blocks
of the dedicated instruction transmission area used
for the multiple CPU high-speed transmission
dedicated instruction(target CPU= CPU No.4) is less
than the number of blocks specified by SD799.
Turns ON at instruction execution. Turns OFF when
the empty area exists at END processing.

S (When
instruction/END
processing
executed)

S (When
instruction/END
processing
executed)

New

New

8
8
QnU*7

A
New

8

*7: The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.

(8) Debug

7

TableApp.3.9 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

M9
SM800

Trace preparation

OFF : Not ready
ON : Ready

• Switches ON when the trace preparation is
completed

Trace start

OFF : Suspend
ON : Start

SM802

Trace execution in
progress

OFF : Suspend
ON : Start

• Switches ON during execution of trace.
• Trace is triggered when this relay switches from OFF
to ON. (Identical to TRACE instruction execution
status)

S (Status change)

New

U

M9047

S (Status change)

M9046

U

M9044

SM803

Trace trigger

OFF

SM804

After trace trigger

OFF : Not after trigger
ON : After trigger

• Switches ON after trace is triggered.

S (Status change)

New

SM805

Trace completed

OFF : Not completed
ON : End

• Switches ON at completion of trace

S (Status change)

M9043

SM826

Trace error

OFF : Normal
ON : Errors

• Switches ON if error occurs during execution of trace

S (Status change)

New

ON : Forced registration
enabled
OFF : Forced registration
disabled

• Even when the trace condition or the trigger
condition is established, the sampling trace setting
can be set to the CPU module by turning SM829 ON
and registering the sampling trace setting by GX
Developer.

U

New

SM829

Forced registration
specification of trace
setting

ON: Start

Qn(H)
QnPH
QnPRH
QnU*1

QnU*1

*1: The Universal model QCPU except the Q00UJCPU.

App-133

8

Appendix 3 SPECIAL RELAY LIST

SM801

• Trace is started when this relay switches ON.
• Trace is suspended when this relay switches OFF.
(All related special Ms switches OFF.)

8

New

(9) A to Q conversion correspondences
Special relays SM1000 to SM1255 are the relays which correspond to ACPU special relays
M9000 to M9255 after A to Q conversion.
(However, the Basic model QCPU and Redundant CPU do not support the A to Q
conversion.)
These special relays are all set by the system, and cannot be set by the user program.
To turn them ON/OFF by the user program, change the special relays in the program into
those of QCPU.
However, some of SM1084 and SM1200 to SM1255 (corresponding to M9084 and M9200 to
M9255 before conversion) can be turned ON/OFF by the user program, if they could be
turned ON/OFF by the user program before conversion.For details on the ACPU special
relays, see the user's manuals for the individual CPUs, and MELSECNET or MELSECNET/
B Data Link System Reference Manuals

POINT
Check "Use special relay/special register from SM/SD1000" for "A-PLC" on the
PLC system tab of PLC parameter in GX Developer when the converted special
relays are used with the High Performance model QCPU, Process CPU, and
Universal model QCPU.
When not using the converted special relays, uncheck "Use special relay/special
register from SM/SD1000" to save the time taken for processing special relays.

Remark
The following are additional explanations about the Special Relay for Modification
column.
When a special relay for modification is provided, the device number should
be changed to the provided QCPU special relay.
When
is provided, the converted special relay can be used for the device
number.
When

is provided, the device number does not work with QCPU.

TableApp.3.10 Special relay
ACPU
Special
Relay

M9000

M9002

Special
Relay after
Conversion

SM1000

SM1002

Special
Relay for
Modification

–

–

Name

Fuse blown

I/O module verify
error

Meaning

Details

OFF : Normal
ON : Module with blown
fuse

• Turned on when there is one or more output modules of
which fuse has been blown.
• Remains ON if the condition is restored to normal
thereafter.
• Output modules of remote I/O stations are also checked
fore fuse condition.

OFF : Normal
ON : Error

• Turned on if the status of I/O module is different form
entered status when power is turned on.
• Remains ON if the condition is restored to normal
thereafter.
• I/O module verification is done also to remote I/O station
modules.
• Reset is enabled only when special registers SD1116 to
SD1123 are reset.

*1: The relevant modules are as follows:
• The Universal model QCPU whose serial number (first five digits) is "10102" or later.
• Q00UJCPU, Q00UCPU, Q01UCPU

App-134

Corresponding
CPU

Qn(H)
QnPH
QnU*1

TableApp.3.11 Special relay
ACPU
Special
Relay

Special
Special
Relay after
Relay for
Conversion Modification

Name

Meaning

Details
• Turns ON if an instantaneous power failure of within 20ms
occurs during use of the AC power supply module.
• Reset when the power supply is switched OFF, then ON.

M9005

SM1005

–

AC DOWN
detection

OFF : AC DOWN not
detected
ON : AC DOWN detected

M9006

SM1006

–

Battery low

OFF : Normal
ON : Battery low

• Turns ON when the battery voltage drops to or below the
specified.
• Turns OFF when the battery voltage returns to normal
thereafter.

M9007

SM1007

–

Battery low latch

OFF : Normal
ON : Battery low

• Turns ON when the battery voltage drops to or below the
specified.
• Remains ON if the battery voltage returns to normal
thereafter.

M9008

SM1008

SM1

Self-diagnosis
error

OFF : No error
ON : Error

• Turned on when error is found as a result of selfdiagnosis.

M9009

SM1009

SM62

Annunciator
detection

OFF : No F number detected
ON : F number detected

• Turned on when OUT F of SET F instruction is
executed.
• Switched off when SD1124 data is cleared to zero.

M9011

SM1011

SM56

Operation error
flag

OFF : No error
ON : Error

• Turned on when operation error occurs during execution
of application instruction.
• Remains ON if the condition is restored to normal
thereafter.

Carry flag

OFF : Carry OFF
ON : Carry ON

• Carry flag used in application instruction.

SM1012

M9016

SM1016

Data memory clear
flag

OFF : lgnored
ON : Output claered

• Clears the data memory including the latch range (other
than special relays and special registers) in remote run
mode from computer, etc. when SM1016 is on.

M9017

SM1017

Data memory clear
flag

OFF : lgnored
ON : Output claered

• Clears the unlatched data memory (other than special
relays and special registers) in remote run mode from
computer, etc. when SM1017 is on.

M9020

SM1020

–

User timing clock
No.0

M9021

SM1021

–

User timing clock
No.1

–

User timing clock
No.2

SM1023

–

Qn(H)
QnPH
QnU*1

8
A
8

Qn(H)
QnPH

7
8

• Relay which repeats on/off at intervals of predetermined
scan.
• When power is turned on or reset is per-formed, the clock
starts with off.
Set the intervals of on/off by DUTY instruction.

DUTY n1 n2 SM1020
n2 scan

n2 scan

n1: ON scan interval
n2: OFF scan interval
* : If DUTY instruction, which specified from SM 1020 to
SM 1024 of User timing clock in programs other than a
program for a Universal model QCPU, changes the
programmable controller to the Universal model
QCPU, the special relays SM 420 to 424 will be
replaced.
(Universal model QCPUs cannot specify the special
relays from SM 1020 to SM1024.)

n1 scan

M9023

8

User timing clock
No.3

M9024

SM1024

–

User timing clock
No.4

M9025

SM1025

–

Clock data set
request

OFF : Ignored
ON : Set request present
used

• Writes the clock data stored in SD1025 to SD1028 to the
CPU module after the END instruction is executed in the
scan in which SM1025 turned from OFF to ON.

M9026

SM1026

–

Clock data error

OFF : No error
ON : Error

• Switched on by clock data (SD1025 to SD1028) error

M9028

SM1028

–

Clock data read
request

OFF : Ignored
ON : Read request

• Reads clock data to SD1025 to SD1028 in BCD when
SD1028 is on.

Batch processing
of data
communications
requests

OFF : Batch processing not
conducted
ON : Batch processing
conducted

• The SM1029 relay is turned on using a sequence program
to process all data communication requests accepted
during one scan in the END processing of that scan.
• The batch processing of the data communication requests
can be turned on and off during running.
• The default is OFF (processed one at a time for each END
processing in the order in which data communication
requests are accepted).

M9029

SM1029

M9030

SM1030

–

0.1 second clock

0.05s

M9031

SM1031

–

0.2 second clock

0.1s

M9032

SM1032

–

1 second clock

0.5s

M9033

SM1033

–

2 second clock

1s

Qn(H)
QnPH
QnU*1

Qn(H)
QnPH

0.05s

0.1s

0.5s

• 0.1 second, 0.2 second, 1 second and 2 second, clocks
are generated.
• Not turned on or off per scan but turned on and off even
during scan if corresponding time has elapsed.
• Starts with off when Programmable Controller power
supply is turned on or CPU module reset is performed.

Qn(H)
QnPH
QnU*1

1s

*1: The relevant modules are as follows:
• The Universal model QCPU whose serial number (first five digits) is "10102" or later.
• Q00UJCPU, Q00UCPU, Q01UCPU

App-135

Appendix 3 SPECIAL RELAY LIST

SM1022

8
8

• Turns ON if an instantaneous power failure of within 10ms
occurs during use of the DC power supply module.
• Reset when the power supply is switched OFF, then ON.

M9012

M9022

SM700

Corresponding
CPU

TableApp.3.11 Special relay
ACPU
Special
Relay

Special
Relay after
Conversion

Special
Relay for
Modification

M9034

SM1034

–

M9036

SM1036

–

Name

2n minute clock(1
minute clock)*2

Always ON

Meaning

Details
• Alternates between ON and OFF according to the
seconds specified at SD414. (Default: n = 30)
• Not turned on or off per scan but turned on and off even
during scan if corresponding time has elapsed.
• Starts with off when Programmable Controller power
supply is turned on or CPU module reset is performed.

ns
ns

ON
OFF

• Used as dummy contacts of initialization and application
instruction in sequence program.
• SM1038 and SM1037 are turned on and off without regard
to position of key switch on CPU module front. SM1038
and SM1039 are under the same condition as RUN status
except when the key switch is at STOP position, and
turned off and on. Switched off if the key switch is in STOP
position. SM1038 is on for one scan only and SM1039 is
off for one scan only if the key switch is not in STOP
position.

M9037

SM1037

–

Always OFF

ON
OFF

M9038

SM1038

–

ON for 1 scan only
after RUN

ON
OFF

1 scan

M9039

SM1039

–

RUN flag(After
RUN, OFF for 1
scan only)

ON
OFF

1 scan

M9040

SM1040

SM206

PAUSE enable coil

OFF : PAUSE disabled
ON : PAUSE enabled

M9041

SM1041

SM204

PAUSE status
contact

OFF : PAUSE not in effect
ON : PAUSE in effect

M9042

SM1042

SM203

STOP status
contact

OFF : STOP not in effect
ON : STOP in effect

• Switched on when the RUN key switch or RUN/STOP
switch is in STOP position.

M9043

SM1043

SM805

Sampling trace
completed

OFF : Sampling trace in
progress
ON : Sampling trace
completed

• Turned on upon completion of sampling trace performed
the number of times preset by parameter after STRA
instruction is executed.
Reset when STRAR instruction is executed.

OFF
M9044

SM1044

M9045

SM1045

M9046

SM1046

SM803

SM802

Sampling trace

ON

ON Same as STRA
instruction
execution
OFF Same as STRAR
instruction
execution

• When RUN key switch is at PAUSE position or pause
contact has turned on and if SM1040 is on, PAUSE mode
is set and SM1041 is turned on.

• Turning on/off SM1044 can execute STRA/STRAR
instruction.
(SM1044 is forcibly turned on/off by a peripheral device.)
When switched from OFF to ON: STRA instruction
When switched from ON to OFF: STRAR instruction
The value stored in SD1044 is used as the condition for
the sampling trace.
At scanning, at time
Time (10 ms unit)

Watchdog timer
(WDT) reset

OFF : Does not reset WDT
ON : Resets WDT

• The SM1045 relay is turned on to reset the WDT when the
ZCOM instruction and data communication request batch
processing are executed (used when the scan time
exceeds 200 ms).

Sampling trace

OFF : Trace not in progress
ON : Trace in progress

• Switched on during sampling trace.
• Sampling trace is not executed unless SM1047 is turned
ON.
Sampling trace is suspended when SM1047 goes OFF.

M9047

SM1047

SM801

Sampling trace
preparations

M9049

SM1049

SM701

Switching the
number of output
characters

OFF : Output until NULL
code encountered
ON : 16 characters output

• When SM1049 is OFF, characters up to NULL (00H) code
are output.
• When SM1049 is ON, ASCII codes of 16 characters are
output.

OFF : Enabled
ON : Disable

• Switched ON to disable the CHG instruction.
• Switched ON when program transfer is requested.
Automatically switched OFF when transfer is complete.

OFF : 7SEG segment display
ON : I/O partial refresh

• When SM1052 is ON, the SEG instruction is executed as
an I/O partial refresh instruction.
When SM1052 is OFF, the SEG instruction is executed as
a 7-SEG display instruction.

M9051

SM1051

M9052

SM1052

SEG instruction
switch

*1: The relevant modules are as follows:
• The Universal model QCPU whose serial number (first five digits) is "10102" or later.
• Q00UJCPU, Q00UCPU, Q01UCPU
*2: minute clock indicates the name of the special relay (M9034) of the ACPU.

App-136

Qn(H)
QnPH
QnU*1

Qn(H)
QnPH

Qn(H)
QnPH
QnU*1

Qn(H)
QnPH

Qn(H)
QnPH
QnU*1

OFF : Sampling trace
suspended
ON : Sampling trace started

CHG instruction
execution disable

Corresponding
CPU

Qn(H)
QnPH

TableApp.3.11 Special relay
ACPU
Special
Relay
M9056

Special
Special
Relay after
Relay for
Conversion Modification
SM1056

Name

Meaning

Main side P, I set
request

OFF : Other than when P, I
set being requested
ON : P, I set being
requested

M9057

SM1057

Sub side P, I set
request

OFF : Other than when P, I
set being requested
ON : P, I set being
requested

M9058

SM1058

Main side P, I set
completion

Momentarily ON at P, I set
completion

M9059

SM1059

Sub program P, I
set completion

Momentarily ON at P, I set
completion

M9060

SM1060

Sub program 2 P, I
set request

OFF : Other than when P, I
set being requested
ON : P, I set being
requested

M9061

SM1061

Sub program 3 P, I
set request

OFF : Other than when P, I
set being requested
ON : P, I set being
requested

M9070

SM1070

A8UPU/
A8PUJrequired
search time*3

OFF : Read time not
shortened
ON : Read time shortened

Details

8
8

• Provides P, I set request after transfer of the other
program (for example subprogram when main program is
being run) is complete during run. Automatically switched
off when P, I setting is complete.

8
• Turned ON once when the P, I set has been completed,
and then turned OFF again.

8
• Provides P, I set request after transfer of the other
program (for example subprogram when main program is
being run) is complete during run. Automatically switched
off when P, I setting is complete.

• Turned ON to shorten the search time in the A8UPU/
A8PUJ.
(In this case, the scan time is extended by 10 %.)
It is set whether the error checks below are performed or not
when the END instruction is processed (to set the END
instruction processing time).
• Check for fuse blown.
• Check of battery
• Collation check of I/O module

M9084

SM1084

Error check

OFF : Error check executed
ON : No error check

M9091

SM1091

Operation error
details flag

OFF : No error
ON : Error

• Turns ON when the detail factor of the operation error is
stored into SD1091.
• Remains ON if the condition is restored to normal
thereafter.

M9100

SM1100

Presence/absence
of SFC program

OFF : SFC programs not
used
ON : SFC programs used

• Turned on if the SFC program is registered.
• Turned off if the SFC program is not registered.

SM320

Corresponding
CPU

SM1101

SM321

Start/stop SFC
program

OFF : SFC programs stop
ON : SFC programs start

M9102

SM1102

SM322

SFC program start
status

OFF : Initial start
ON : Resume start

• The SFC program start mode in the SFC setting of the
PLC parameter dialog box is set as the initial value.
At initial start: OFF
At continue start: ON

Qn(H)
QnPH

8
7
8

Appendix 3 SPECIAL RELAY LIST

M9101

• The value in SM1100 is set as the initial value.
(The relay automatically turns ON when the SFC program
is present.)
• When this relay turns from ON to OFF, execution of the
SFC program stops.
• When this relay turns from OFF to ON, execution of the
SFC program resumes.

A

*3: The A8UPU/A8PUJ is not available for the QCPU/QnACPU.

App-137

TableApp.3.11 Special relay
ACPU
Special
Relay
M9103

Special
Relay after
Conversion

Special
Relay for
Modification

SM1103

SM323

Presence/absence
of continuous
transition

OFF : Continuous transition
not effective
ON : Continuous transition
effective

• Set whether continuous transition will be performed for the
block where the "continuous transition bit" of the SFC
information device is not set.

OFF : When transition is
completed
ON : When no transition

• OFF during operation in the continuous transition mode or
during continuous transition, and ON when continuous
transition is not executed.
• Always ON during operation in the no continuous
transition mode.

OFF : Monitoring timer reset
ON : Monitoring timer reset
start

• Turns ON when the measurement of the step transition
monitoring timer is started.
Turning this relay OFF resets the step transition
monitoring timer.

Name

M9104

SM1104

SM324

Continuous
transition
suspension flag

M9108

SM1108

SM90

Step transition
monitoring timer
start (equivalent of
SD90)

M9109

SM1109

SM91

Step transition
monitoring timer
start (equivalent of
SD91)

M9110

SM1110

SM92

Step transition
monitoring timer
start (equivalent of
SD92)

M9111

SM1111

SM93

Step transition
monitoring timer
start (equivalent of
SD93)

M9112

SM1112

SM94

Step transition
monitoring timer
start (equivalent of
SD94)

M9113

SM1113

SM95

Step transition
monitoring timer
start (equivalent of
SD95)

M9114

SM1114

SM96

Step transition
monitoring timer
start (equivalent of
SD96)

M9196

M9197

SM1196

SM325

Operation output
at block stop

SM1197
Switch between
blown fuse and I/O
verify error display

M9198

M9199

Meaning

Qn(H)
QnPH

OFF : Coil output OFF
ON : Coil output ON

SM
1197

SM
1198

I/O numbers
to be
displayed

OFF

OFF

X/Y0 to 7F0

ON

OFF

X/Y800 to
FF0

OFF

ON

X/Y1000 to
17F0

ON

ON

X/Y1800 to
1FF0

SM1198

Data recovery of
online sampling
trace/status latch

SM1199

Corresponding
CPU

Details

OFF : Data recovery disabled
ON : Data recovery enabled

• Selects the operation output when block stop is executed.
ON : Retains the ON/OFF status of the coil being used
by using operation output of the step being
executed at block stop.
OFF : All coil outputs are turned off. (Operation output
by the SET instruction is retained regardless of
the ON/OFF status of SM1196.)

Switches I/O numbers in the fuse blow module storage
registers (SD1100 to SD1107) and I/O module verify error
storage registers (SD1116 to SD1123) according to the
combination of ON/OFF of the SM1197 and SM1198.

• Recovers the setting data stored in the CPU module at
restart when sampling trace/status latch is executed.
• SM1199 should be ON to execute again. (Unnecessary
when writing the data again from peripheral devices.)

(10) QCPU with built-in Ethernet port
TableApp.3.12 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

M9
SM1270

SM1273

Time setting function
(SNTP client)
execution
Remote password
mismatch count clear

OFF : No time setting function
(SNTP client) execution
ON : Time setting function
(SNTP client) execution

Set this to ON when executing the time setting function
(SNTP client).
(Only when the time setting function is in "Use" with the
time setting parameter.)

U

OFF : Normal
ON : Clear

To clear the acumulated numeber (SD979 to 999) of
mismatched remote passwords, the setting SM1273 is
executed.

U

* 1: This applies to the Built-in Ethernet port QCPU.

App-138

New
QnU*1
New

(11) Process control instructions

8

TableApp.3.13 Special relay
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

M9
SM1500

SM1501

Hold mode

OFF : No-hold
ON : Hold

• Specifies whether or not to hold the output value
when a range over occurs for the S.IN instruction
range check.

U

Hold mode

OFF : No-hold
ON : Hold

• Specifies whether or not the output value is held
when a range over occurs for the S.OUT instruction
range check.

U

New
QnPH
QnPRH
New

(12) For redundant systems (Host system CPU information *1)

TableApp.3.14 Special relay
Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

A
Corresponding
CPU

M9

SM1510

Operation mode

SM1511

System A identification
flag

SM1513

Debug mode status
flag

SM1515

Control system
judgment flag

SM1516

Standby system
judgment flag

• Turns on when the operating mode is redundant
system separate.

S (Each END)

New

7

• Distinguishes between system A and system B.
• The flag status does not change even if the tracking cable is disconnected.

SM1511
SM1512

System A

System B

When TRK. CABLE ERR.
(error code: 6210) occurs (Unknown)

ON

OFF

OFF

OFF

OFF : Not in debug mode
ON : Debug mode

ON

S (Initial)

New

8
QnPRH

OFF

• Turns on when the redundant system operating
mode is set to debug mode.

S (Initial)

New

S (Status change)

New

• Indicates operation system status.
• The flag status does not change even if the tracking cable is disconnected.

Control
system

Standby
system

When TRK. CABLE ERR.
(error code: 6210) occurs (Unknown)

SM1515

ON

OFF

OFF

SM1516

OFF

ON

OFF

8

Appendix 3 SPECIAL RELAY LIST

SM1512

System B identification
flag

OFF : Redundant system
backup mode, standalone system
ON : Redundant system
separate mode

8
8

SM1510 to SM1599 are only valid for redundant systems.
All off for standalone systems.

Number

8

*1: The information of the host CPU module is stored.

App-139

TableApp.3.13 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

M9
• Turns on when the CPU module is started up by the
system switching (switching from the standby system
to the control system). Remains OFF when the
standby system is switched to the control system by
a power-ON startup.

S (Status change)

New

1 scan

• Turns ON once switch between standby system to
control system, (ON for 1 scan only) occurs.
• This status flag can only be used for scan execution
type programs.

S (Each END)

New

1 scan

• On the last operation Control System was System
B,if power supply is supplied, or reset is released on
both SYSTEM together,After RUN, ON for 1 scan
only by System A side.

S (Each END)

New

OFF : Power supply on
startup
ON : Operation system
switch start up

SM1517

CPU module startup
status

SM1518

Standby system to
control system
switching status flag

ON
OFF

SM1519

Previous Control
System Identification
Flag

ON
OFF

SM1520

SM1520

Block 1

SM1521

SM1521

Block 2

SM1522

SM1522

Block 3

SM1523

SM1523

Block 4

SM1524

SM1524

Block 5

SM1525

SM1525

Block 6

SM1526

SM1526

Block 7

SM1527

SM1527

Block 8

SM1528

SM1528

Block 9

SM1529

SM1529

Block 10

SM1530

SM1530

Block 11

SM1531

SM1531

Block 12

SM1532

SM1532

Block 13

SM1533

SM1533

Block 14

SM1534

Block 15

SM1535

Block 16

SM1536

SM1536

Block 17

SM1537

SM1537

Block 18

SM1538

SM1538

Block 19

SM1539

SM1539

Block 20

SM1540

SM1540

Block 21

SM1541

SM1541

Block 22

SM1542

SM1542

Block 23

SM1543

SM1543

Block 24

SM1544

SM1544

Block 25

SM1545

SM1545

Block 26

SM1546

SM1546

Block 27

SM1547

SM1547

Block 28

SM1548

SM1548

Block 29

SM1534
SM1535

Data tracking transfer
trigger specification

App-140

OFF : No trigger
ON : Trigger

• When data is transferred
based on the tracking
setting of the redundant
parameter dialog box, the
target block is specified
as trigger.
• When "Auto Tracking
block No.1" is enabled in
the tracking setting,
SM1520 is turned ON by
the system at power ON/
STOP to RUN. In other
cases, SM1520 to
SM1583 are turned ON
by the user.

QnPRH

S (initial)/U

New

TableApp.3.13 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

8

M9
SM1549

Block 30

SM1550

SM1550

Block 31

SM1551

SM1551

Block 32

SM1552

SM1552

Block 33

SM1553

SM1553

Block 34

SM1554

SM1554

Block 35

SM1555

SM1555

Block 36

SM1556

SM1556

Block 37

SM1557

SM1557

Block 38

SM1558

SM1558

Block 39

SM1559

SM1559

Block 40

SM1560

SM1560

Block 41

SM1561

SM1561

Block 42

SM1562

SM1562

Block 43

SM1563

SM1563

Block 44

SM1564

SM1564

Block 45

SM1565

SM1565

Block 46

SM1566

Block 47

SM1567

Block 48

SM1568

SM1568

Block 49

SM1569

SM1569

Block 50

SM1570

SM1570

Block 51

SM1571

SM1571

Block 52

SM1572

SM1572

Block 53

SM1573

SM1573

Block 54

SM1574

SM1574

Block 55

SM1575

SM1575

Block 56

SM1576

SM1576

Block 57

SM1577

SM1577

Block 58

SM1578

SM1578

Block 59

SM1579

SM1579

Block 60

SM1580

SM1580

Block 61

SM1581

SM1581

Block 62

SM1582

SM1582

Block 63

SM1583

SM1583

Block 64

SM1566
SM1567

Data tracking transfer
trigger specification

OFF : No trigger
ON : Trigger

SM1590

System switching
enable/disable flag
from network module

OFF : System switching
request issuing module
absent
ON : System switching
request issuing module
present

SM1591

Standby system error
detection disable flag
at system switching

ON : Error is not detected by
new standby system at
system switching
OFF : Error is detected by
new standby system at
system switching

SM1592

Enable/disable user
system switching

OFF : Disable user system
switching
ON : Enable user system
switching

8
8
8
• When data is transferred
based on the tracking setting of the redundant
parameter dialog box, the
target block is specified
as trigger.
• When "Auto tracking
block No. 1" is enabled in
the tracking setting,
SM1520 is turned ON by
the system at power ON/
STOP to RUN. In other
cases, SM1520 to
SM1583 are turned ON
by the user.

• Turns ON when a system switching request is issued
from the network module. The module No. that
issued system switching can be checked by SD1590.
• Turns OFF when all bits of SD1590 are OFF.

A
S (initial)/U

8

New

7
QnPRH

8

S (Each END)

New

This flag is used to determine if the new standby station
detects 6210:STANDBY during system switching.
This applies to the following switching methods:
• System switching from GX Developer
• System switching using dedicated instruction
• System switching by the intelligent function module

U

New

• This flag enables system switching by the user from
GX Developer or by dedicated instruction.
(SP.CONTSW).

U

New

Appendix 3 SPECIAL RELAY LIST

SM1549

App-141

TableApp.3.13 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

M9

SM1593

Setting to access
extension base unit of
standby system CPU

OFF : Error
ON : Ignored

Sets the operation for the case accessing buffer
memory of the intelligent function module mounted on
the extension base unit from the standby system CPU
in separate mode.
OFF : “OPERATION ERROR” (error code: 4112) will be
returned when accessing buffer memory of the
intelligent function module on the extension base
unit from the standby system CPU.
ON : No processing is performed when accessing
buffer memory of intelligent function module on
the extension base unit from the standby system
CPU.
• When SM1595 is turned from OFF to ON, memory
copy from control system to standby system starts.
Note that when SM1595 is turned from OFF to ON,
memory copy does not start if the I/O No. of the copy
destination (standby system CPU module: 3D1H) is
not stored in SD1595.

SM1595

Memory copy to other
system start flag

OFF : Start memory copy
ON : No memory copy
initiated

SM1596

Memory copy to other
system status flag

OFF : Memory copy not
executed
ON : Memory copy executed

• Turns on while memory is copied to other system.
• Turns off when memory copy execution has
completed.

SM1597

Memory copy to other
system completion
flag

OFF : Memory copy not
completed
ON : Memory copy
completed

• Turns on once the memory copying to the other
system has completed.

SM1598

Copy contents of
standard ROM during
memory copy

OFF : Copy standard ROM
data
ON : Standard ROM data is
not copied

• If set to on by user, the standard ROM data is not
copied to the other system while memory copy is
executing.

QnPRH*2

U
New

S (Starting to
copy/finish)

QnPRH

S (finish)/U
New
U

*2: The module whose first 5 digits of serial No. is “09012” or later.

(13) For redundant system (Other system CPU information *1)
SM1600 to SM1650 only valid for the CPU redundant system backup mode, so they cannot
be refreshed during the separate mode.
Either the backup mode or the separate mode is valid for the SM4651 to SM1699.
SM1600 to SM1699 are all turned off for stand-alone system.
TableApp.3.14 Special relay

Number

Name

Meaning

Explanation

Set by
(When Set)

Corresp
onding
Host
SM
*2

SM1600

Other system error
flag

OFF : No error
ON : Error

• Turns on when an error occurs during redundant
system. Error check (Turns on single bit of SD1600.)
• Is off when no errors are present

S (Each END)

–

SM1610

Other system
diagnostics error

OFF : No error
ON : Error

• Turns on when a diagnostics error occurs. (Includes
error detection when annunciator is ON, and by CHK
instruction)
• Corresponds to status of SM0 at other system

S (Each END)

SM0

SM1611

Other systems self
diagnostics error.

OFF : No self diagnostics
error occurred
ON : Self diagnostics error
occurred

• Turns on when a self diagnostics error occurs.
(Does not include error detection when annunciator
is ON, and by CHK instruction)
• Corresponds to status of SM1 at other system

S (Each END)

SM1

SM1615

Other system common
error information

OFF : No common error
information present
ON : Common error
information present

• Turns on when there is common error information at
other system
• Corresponds to status of SM5 at other system

S (Each END)

SM5

SM1626

Error individual
information for other
systems

OFF : No individual error
information present
ON : Individual error
information present

• Turns on when there is individual error information at
other system
• Corresponds to status of SM16 at other system

S (Each END)

SM16

SM1649

Standby system
cancel error flag

OFF to ON:
Cancels error of standby
system

By turning this relay from OFF to ON, the continue error
that occurred in the standby system CPU module can
be canceled.
Use SD1649 to specify the error code of the error to be
canceled.

U

–

*1 Stores other system CPU diagnostic information and system information.
*2 This shows the special relay(SM

App-142

) for the host system CPU.

Corresponding
CPU

QnPRH

QnPRH

(14) For redundant system (tracking)
Either the backup mode or the second mode is valid for SM1700 to SM1799.
All is turned off for stand-alone system.

8

TableApp.3.15 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

M9
SM1700

Transfer trigger
completion flag

OFF : Transfer not completed
ON : Transfer completed

• Turns on for one scan, once transfer of block 1 to
block 64 is completed.
(1)

SM1709

Manual system
switching disable/
enable setting during
online program
change redundant
tracking

ON : Manual system
switching enabled
(Disable canceled)
OFF : Manual system
switching disabled

(2)

(3)

(1)

SM1710

Transfer tracking data
during online program
change enable flag

OFF : No device tracking
ON : Transfer device
memory

(2)

(3)

Turning this relay from OFF to ON enables
manual system switching during online program
change redundant tracking.
After the manual system switching disable status
is canceled, the system automatically turns off
SM1709.
System switching due to any of the following
conditions is executed even during online
program change redundant tracking, regardless of
the status of this relay.
•Power off, reset, hardware failure, CPU stop error
In either of the following statuses, the system
switching disable status can also be canceled by
this relay.
•Multiple-block online program change redundant
tracking execution status
•File batch online program change redundant
tracking execution status

8

S (status change)

8
A

S (When
executed)/U

New

QnPRH

8
7
8

U

Appendix 3 SPECIAL RELAY LIST

Set whether the tracking of the following data will
be executed or not during online program change
redundant tracking.
•Device memory
(Including SM/SD that will automatically execute
tracking)
•PIDINIT information, S.PIDINIT information, SFC
information
SM1710 can be also used to set whether tracking
will be executed or not while online change of
multiple program blocks or batch of files is being
performed to ensure consistency of both systems.
This SM is also transferred form control system
CPU module to standby system CPU module by
tracking data.

8

App-143

TableApp.3.15 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

M9
SM1712

SM1712

Block 1

SM1713

SM1713

Block 2

SM1714

SM1714

Block 3

SM1715

SM1715

Block 4

SM1716

SM1716

Block 5

SM1717

SM1717

Block 6

SM1718

SM1718

Block 7

SM1719

SM1719

Block 8

SM1720

SM1720

Block 9

SM1721

SM1721

Block 10

SM1722

SM1722

Block 11

SM1723

SM1723

Block 12

SM1724

SM1724

Block 13

SM1725

SM1725

Block 14

SM1726

SM1726

Block 15

SM1727

SM1727

Block 16

SM1728

SM1728

Block 17

SM1729

SM1729

Block 18

SM1730

SM1730

Block 19

SM1731

SM1731

Block 20

SM1732

SM1732

Block 21

SM1733

SM1733

Block 22

SM1734

SM1734

Block 23

SM1735

Block 24

SM1736

Block 25

SM1737

SM1737

Block 26

SM1738

SM1738

Block 27

SM1739

SM1739

Block 28

SM1740

SM1740

Block 29

SM1741

SM1741

Block 30

SM1742

SM1742

Block 31

SM1743

SM1743

Block 32

SM1744

SM1744

Block 33

SM1745

SM1745

Block 34

SM1746

SM1746

Block 35

SM1747

SM1747

Block 36

SM1748

SM1748

Block 37

SM1749

SM1749

Block 38

SM1750

SM1750

Block 39

SM1751

SM1751

Block 40

SM1752

SM1752

Block 41

SM1753

SM1753

Block 42

SM1754

SM1754

Block 43

SM1755

SM1755

Block 44

SM1756

SM1756

Block 45

SM1757

SM1757

Block 46

SM1758

SM1758

Block 47

SM1759

SM1759

Block 48

SM1735
SM1736

Transfer trigger
completion flag

App-144

OFF : Transfer uncompleted
ON : Transfer completed

Turns ON only during one
scan when the transmission
of the corresponding block is
completed.

S (status change)

New

QnPRH

TableApp.3.15 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

8

M9
SM1760

SM1760

Block 49

SM1761

SM1761

Block 50

SM1762

SM1762

Block 51

SM1763

SM1763

Block 52

SM1764

SM1764

Block 53

SM1765

SM1765

Block 54

SM1766

SM1766

Block 55

SM1767

Block 56

SM1768

Block 57

SM1769

Block 58

SM1770

SM1770

Block 59

SM1771

SM1771

Block 60

SM1772

SM1772

Block 61

SM1773

SM1773

Block 62

SM1774

SM1774

Block 63

SM1775

SM1775

Block 64

SM1767
SM1768

Transfer trigger
completion flag

SM1769

OFF : Transmission
uncompleted
ON : Transmission end

8
Turns ON only during one
scan when the transmission
of the corresponding block is
completed.

8
S (status change)

New

QnPRH

8
A

(15) Redundant power supply module information
TableApp.3.16 Special relay
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

8
Corresponding
CPU

M9

SM1780

SM1781

SM1783

• Turns ON when one or more redundant power
supply modules with input power OFF are detected.
• Turns on if any of SD1780 bits is on.
• Turns off if all bits of SD1780 are off.
• Turns OFF when the main base unit is not the
redundant main base unit (Q38RB).
• When the multiple CPU system is configured, the
flags are stored only to the CPU No.1.

S (Each END)

Power supply failure
detection flag

OFF : No faulty redundant
power supply module
detected
ON : Faulty redundant
power supply module
detected

• Turns ON when one or more faulty redundant power
supply modules are detected.
• Turns on if any of SD1781 bits is on.
• Turns off if all bits of SD1781 are off.
• Turns OFF when the main base unit is not the
redundant main base unit (Q38RB).
• When the multiple CPU system is configured, the
flags are stored only to the CPU No.1.

S (Each END)

OFF : No momentary power
failure detected
ON : Momentary power
failure detected

• Turns ON when a momentary power failure of the
input power supply to the power supply 1 or 2 is
detected one or more times. After turning ON,
remains ON even if the power supply recovers from
the momentary power failure.
• Turns OFF the flag (SM1782, SM1783) of the power
supply 1/2 when the CPU module starts.
• When the input power to one of the redundant power
supply modules turns OFF the corresponding flag
turns OFF.
• Turns OFF when the main base unit is not the
redundant main base unit (Q38RB).
• When the multiple CPU system is configured, the
flags are stored only to the CPU No.1.

S (Each END)

Momentary power
failure detection flag
for power supply 1 *1

Momentary power
failure detection flag
for power supply 2 *1

7
8

New

Qn(H)*2
QnPH*2
QnPRH
QnU*3

*1: The "power supply 1" indicates the redundant power supply module mounted on the POWER 1 slot of the redundant base unit (Q38RB/Q68RB/Q65WRB).
The "power supply 2" indicates the redundant power supply module mounted on the POWER 2 slot of the redundant base unit (Q38RB/Q68RB/Q65WRB).
*2: The module whose first 5 digits of serial No. is "04012" or later.
However, for the multiple CPU system configuration, this applies to all CPU modules whose first 5 digits of serial No. are "07032" or later.
*3: The module whose first 5 digits of serial No. is "10042" or later.

App-145

Appendix 3 SPECIAL RELAY LIST

SM1782

Power supply off
detection flag

OFF : No redundant power
supply module with
input power OFF
detected
ON : Redundant power
supply module with
input power OFF
detected

Appendix 4 SPECIAL REGISTER LIST
The special registers, SD, are internal registers with fixed applications in the Programmable
Controller.
For this reason, it is not possible to use these registers in sequence programs in the same way
that normal registers are used.
However, data can be written as needed in order to control the CPU modules.
Data stored in the special registers are stored as BIN values if no special designation has been
made to the contrary.
The heading descriptions in the following special register lists are shown in 4.1.
TableApp.4.1 Descriptions of the special register lists headings
Item
Number

Function of Item
• Indicates special register number

Name

• Indicates name of special register

Meaning

• Indicates contents of special register

Explanation

• Discusses contents of special register in more detail

Set by
(When set)

• Indicates whether the relay is set by the system or user, and, if it is set by the system, when setting is performed.

S
: Set by system
U
: Set by user (sequence programs or test operations from GX Developer)
S/U
: Set by both system and user

Indicated only for registers set by system
Each END
: Set during each END processing
Initial
: Set only during initial processing (when power supply is turned ON, or when going from STOP to RUN)
Status change
: Set only when there is a change in status
Error
: Set when error occurs
Instruction execution
: Set when instruction is executed
Request
: Set only when there is a user request (through SM, etc.)
System switching
: Set when system switching is executed.
• Indicates corresponding special register in ACPU

Corresponding ACPU
M9

Corresponding CPU

(When the contents are changed, the special register is represented D9
and QnPRH.)
• New indicates the special register newly added to the Q series CPU module.

format change. Incompatible with the Q00J/Q00/Q01

Indicates the relevant CPU module.
QCPU
: Indicates all the Q series CPU modules.
Q00J/Q00/Q01
: Indicates the Basic model QCPU.
Qn(H)
: Indicates the High Performance model QCPU.
QnPH
: Indicates the Process CPU.
QnPRH
: Indicates the Redundant CPU.
QnU
: Indicates the Universal model QCPU
Each CPU type name
: Can be applied only to the specific CPU. (e.g. Q02U)

For details on the following items, refer to the following manuals:
• Networks

Manual of the corresponding network module

• SFC

QCPU(Q mode)/QnACPU Programming Manual (SFC)

POINT
Do not change the values of special relays set by the system with user program or
device test operations.
Doing so may result in system downtime or communication fault.

App-146

(1) Diagnostic Information

8

TableApp.4.2 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
SD0

Diagnostic
errors

Diagnosis error
code

• Error codes for errors found by diagnosis are stored as BIN data.
• Contents identical to latest fault history information.

S (Error)

D9008
format
change

8

• Year (last two digits) and month that SD0 data was updated is stored as
BCD 2-digit code.
SD1

SD2

b15 to
b8 b7 to
b0
Year (0 to 99) Month (1 to 12)
Clock time for
diagnosis error
occurrence

Clock time for
diagnosis error
occurrence

(Example) October, 1995
9510H

8

• The day and hour that SD0 was updated is stored as BCD 2-digit code.

b15 to
b8 b7 to
b0
Day (1 to 31) Hour (0 to 23)

(Example) 10 a.m. on 25th
2510H

S (Error)

New

A

• The minute and second that SD0 data was updated is stored as BCD 2digit code.
SD3

b15
to
b8 b7
to
b0
Minutes (0 to 59) Seconds (0 to 59)

(Example) 35 min. 48 sec.
3548H

8

Category codes which help indicate what type of information is being
stored in the common information areas (SD5 through SD15) and the
individual information areas (SD16 through SD26) are stored here.
The category code for judging the error information type is stored.

b15
b8 b7
b0
to
to
Individual information Common information
category codes
category codes

7

• The common information category codes store the following codes:
0 : No error

Error
information
categories

Error information
category code

1: Unit/module No./ CPU No./Base No.*
2: File name/Drive name
3: Time (value set)
4: Program error location
5: System switching cause (for Redundant CPU only)
6: Reason(s) for tracking capacity excess error (specific to Redundant
CPU)
7: Base No./Power supply No. (The first 5 digits of serial number 10072
or higer are chosen for Universal model QCPU.)
8: Tracking transmission data classification (specific to Redundant CPU)
*: For a multiple CPU system that consists of the Basic model QCPU,
High Performance model QCPU, Process CPU, Universal model
QCPU the module number or CPU number is stored depending on the
error that occurred.
(Refer to the corresponding error code for which number has been
stored.)
CPU No. 1: 1, CPU No. 2: 2, CPU No. 3: 3, CPU No. 4: 4
• The individual information category codes store the following codes:
0: No error
1: (Empty)
2: File name/Drive name
3: Time (value actually measured)
4: Program error location
5: Parameter number
6: Annunciator number
7: CHK instruction failure No. (except for the Basic model QCPU and the
Universal model QCPU)
8: Reason(s) for system switching failure (specific to Redundant CPU)
12: File diagnostic information (specific to the Universal model QCPU)
13: Parameter No./CPU No. (specific to the Universal model QCPU)

QCPU

S (Error)

8

Appendix 4 SPECIAL REGISTER LIST

SD4

8

New

App-147

TableApp.4.2 Special register
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

D9
• Common information corresponding to the error codes (SD0) is stored
here.
• The following ten types of information are stored here:
• The error common information type can be judged by the "common information category code" in SD4. (The values of the "common information
category code" stored in SD4 correspond to following 1) to 8).)
1)
Slot No.

SD5

SD6

Number
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15

SD7

SD8

SD9

SD10

SD11

SD12

SD13

Error common
information

Error common
information

(Empty)

*1: For a multiple CPU system that consists of the Basic model QCPU, High
Performance model QCPU, Process CPU, Universal model QCPU, the
slot number or CPU number is stored depending on the error that
occurred.
Slot 0 in the multiple CPU system is the one on the slot on the right of the
rightmost CPU module.
(Refer to the corresponding error code for which number has been
stored.)
No. 1 CPU: 1, No. 2 CPU: 2, No. 3 CPU: 3, No. 4 CPU: 4
*2: If a fuse blown or I/O verify error occurred in the module loaded in the
MELSECNET/H remote I/O station, the network number is stored into the
upper 8 bits and the station number into the lower 8 bits.
Use the I/O No. to check the module where the fuse blown or I/O verify
error occurred.
*3: 255 is stored into SD5 of the Basic model QCPU when an instruction, etc.
has been executed for the module later than the one on the last slot
where a module can be mounted.
*4: Definitions of base No. and slot No.

Value used to identify the base unit on which the CPU module has
been mounted. The following shows the definition of the base No.

Base No.
Definition
Indicates the main base unit mounted with the CPU
0
module.
1 to 7
Indicates the extension base unit. The stage
number setting made by the stage number setting
connector on the extension base unit is the base
No.
When stage number setting is extension 1:
Base No. = 1
when stage number setting is extension 7:
Base No. = 7

SD14

SD15

Meaning
Slot No./CPU No./Base No. 1, 2, 3, 4
I/O No. 5


Value used to identify the slot of each base unit and the module
mounted on that slot.
•The I/O slot 0 (slot on the right side of the CPU slot) of the main base
unit is defined as the slot of "Slot No. = 0".
•The slot Nos. are consecutively assigned to the slots of the base
units in order of the main base unit and extension base units 1 to 7.
•When the number of base unit slots has been set in the I/O
assignment setting of the PLC parameter dialog box, the slot Nos.
are assigned for only the number of set slots.
*5: When 0FFFFH is stored into SD6 (I/O No.), the I/O No. cannot be
identified due to overlapping I/O No., etc. in the I/O assignment setting of
the PLC parameter dialog box. Therefore, identify the error location using
SD5.

2)

File name/Drive name
(Example) File name =
Number
Meaning
ABCDEFGH. IJK
SD5
Drive
b15 to b8 b7 to b0
SD6
42H(B) 41H(A)
SD7
File name
44H(D) 43H(C)
SD8
(ASCII code: 8 characters)
46H(F) 45H(E)
SD9
48H(H) 47H(G)
SD10 Extension 6
2EH(.)
49H(I) 2EH(.)
(ASCII
code:
3
characters)
SD11
4BH(K) 4AH(J)
SD12
SD13
(Empty)
SD14
SD15

App-148

S (Error)

New

QCPU

TableApp.4.2 Special register
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

8

D9

8

SD5

8
SD6

3)

Number
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15

SD7

SD8

4)

SD9

Error common
information
SD10

SD11

Error common
information

8

Time (value set)

Meaning
Time : 1 s units (0 to 999 s)
Time : 1ms units (0 to 65535ms)

A
(Empty)

8

Program error location

Meaning
Number
SD5
File name
SD6
(ASCII code: 8 characters)
SD7
SD8
2EH(.)
SD9 Extension 6
(ASCII code: 3 characters)
SD10
SD11
Pattern 7
SD12
Block No.
SD13
Step No./transition condition
Sequence step No. (L)
SD14
Sequence step No. (H)
SD15

7
S (Error)

New

QCPU

8

*7 : Contents of pattern data

SD12

to
to

4 3 2 1 0
0 0

(Not used)

(Bit number)

Appendix 4 SPECIAL REGISTER LIST

15 14
0 0

SFC block designation present
(1)/absent (0)
SFC step designation present
(1)/absent (0)

SD13

SFC transition designation present
(1)/absent (0)

SD14

SD15

App-149

TableApp.4.2 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
5)

Reason(s) for system switching

Number
SD5

SD5

Meaning
System switching condition 13
Control system switching
instruction argument

SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15

SD6

SD7

(Empty)

*13: Details of reason(s) for system switching

0 : No system switching condition
(default)
1 : Power-OFF, reset, hardware failure,
watchdog timer error
2 : Stop error
(except watchdog timer error)
3 : System switching request by
network module
16 : Control system switching instruction
17 : Control system switching request
from GX Developer

SD8

SD9

6)

SD10
Error common
information

SD11

SD12

Error common
information

SD13

SD14

SD15

b15

b8

b14 b13 b12 b11 b10 b9

b7 b6 b5 b4 b3 b2 b1

QnPRH

New

QnPH*1
QnPRH

b0

1
(SM1535)
(Block16)

0

0

0

0

0

0

1
(SM1528)
(Block9)

0

0

0

0

0

0

0

1
(SM1520)
(Block1)

SD6

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SD7

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SD8

1
(SM1583)
(Block64)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1
(SM1568)
(Block49)

SD9

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SD15

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Power supply No.

Number
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15

Meaning
Base No.
Power supply No.

(Empty)

1: Power supply 1 fault
2: Power supply 2 fault
"Power
Redundant power supply module
supply
mounted on POWER 1 slot of redundant
module 1": base unit (Q38RB, Q68RB, Q65WRB)
Redundant power supply module
"Power
mounted on POWER 2 slot of redundant
supply
module 2": base unit (Q38RB, Q68RB, Q65WRB)

*1: The module whose first 5 digits of serial No. is "07032" or later.
*2: The module whose first 5 digits of serial No. is "10042" or later.

App-150

New

Reason(s) for tracking capacity excess error
The block No. when the data amount that can be tracked (100k) is
exceeded is indicated by the bit pattern of the corresponding special
relay.

SD5

7)

S (Error)

Qn(H)*1
S (Error)

QnU*2

TableApp.4.2 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

8

D9

8
SD5

8
SD6

8
SD7

A
8)

Number
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15

SD8

SD9

SD10

Tracking transmission data classification
Stores the data classification during tracking.

Error common
information

Error common
information

Meaning
Data type 15

8
7

(Empty)

8

*15: Details of data classification

b15 b14 to b6 b5
0

b4

b3

b2

b1

b0

S (Error)

New

QnPRH

Each bit
0: Not sent
1: Being sent
Device data

Appendix 4 SPECIAL REGISTER LIST

SD11

Signal flow
PIDINIT/S. PIDINIT
instruction data
SFC execution data

SD12

System switching
request
Operation mode
change request
System data

SD13

SD14

SD15

App-151

TableApp.4.2 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
• Individual information corresponding to error codes (SD0) is stored here.
• There are the following eight different types of information are stored.
• The error individual information type can be judged by the "individual
information category code" in SD4. (The values of the "individual information category code" stored in SD4 correspond to following 1) to 8),
12), and 13).)

SD16

1)

(Empty)

2)

File name/Drive name

SD17

Number
Meaning
SD16
Drive
SD17
File name
SD18
SD19 (ASCII code: 8 characters)
SD20
2EH(.)
SD21 Extension 6
SD22 (ASCII code: 3 characters)
SD23
SD24
(Empty)
SD25
SD26

SD18

3)

SD19

Time (value actually measured)

Number
SD16
SD17
SD18
SD19
SD20
SD21
SD22
SD23
SD24
SD25
SD26

SD20

4)

SD21

(Example) File name =
ABCDEFGH. IJK
b15 to b8 b7 to b0
42H(B) 41H(A)
44H(D) 43H(C)
46H(F) 45H(E)
48H(H) 47H(G)
49H(I)
2EH(.)
4BH(K) 4AH(J)

Meaning
Time : 1 s units (0 to 999 s)
Time : 1ms units (0 to 65535ms)

(Empty)

Program error location

SD22

Number
Meaning
SD16
SD17
File name
SD18
(ASCII code: 8 characters)
SD19
2EH(.)
SD20 Extension 6
(ASCII code: 3 characters)
SD21
SD22
Pattern 7
SD23
Block No.
SD24
Step No./transition No.
Sequence step No. (L)
SD25
Sequence step No. (H)
SD26

SD23

*7 : Contents of pattern data

Error individual
information

Error individual
information

15 14
0 0

to
to

4 3 2 1 0
0 0

(Bit number)

SFC block designation
present (1)/absent (0)

(Not used)

SFC step designation
present (1)/absent (0)

SD24

SFC transition designation
present (1)/absent (0)

SD25

SD26

5) Parameter No. 6) Annunciator number /
7) CHK instruction
malfunction number
Number
Meaning
SD16 Parameter No. 16
SD17
SD18
SD19
SD20
SD21
(Empty)
SD22
SD23
SD24
SD25
SD26

Number
SD16
SD17
SD18
SD19
SD20
SD21
SD22
SD23
SD24
SD25
SD26

Meaning
No.

(Empty)

*16: For details of the parameter No., refer to the User's Manual
(Function Explanation, Program Fundamentals) of the CPU
module used.

App-152

S (Error)

New

QCPU

*6 : Extensions are shown below.
TableApp.4.3 Extension name
SDn

SDn+1

Higher 8 bits Lower 8 bits

Extension

Higher 8 bits

Name

8
File Type

51H

50H

41H

QPA

51H

50H

47H

QPG

51H

43H

44H

QCD

51H

44H

49H

QDI

Initial device value

51H

44H

52H

QDR

File register

51H

44H

4CH

QDL

51H

54H

44H

QTD

51H

46H

44H

QFD

Parameters

8

• Sequence program
• SFC program
Device comment

8

Local device
(Other than the Basic model QCPU)
Sampling trace data
Breakdown history data
(Other than the Basic model QCPU and
the Universal model QCPU)

51H

53H

54H

QST

8

(Other than the Basic model QCPU)

A

SP.DEVST/S.DEVLD instruction file
(For Universal model QCPU only)

8
7
8

Appendix 4 SPECIAL REGISTER LIST

App-153

TableApp.4.2 Special register
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

D9
8)

Reason(s) for system switching failure

Number
SD16
SD17
SD18
SD19
SD20
SD21
SD22
SD23
SD24
SD25
SD26

Meaning
System switching prohibition
condition 14

(Empty)

*14: Details of reason(s) for system switching failure

SD26

Error individual
information

0 : Normal switching completion
(default)
1 : Tracking cable fault (cable
removal, cable fault, internal
circuit fault, hardware fault)
2 : Hardware failure, power OFF,
reset or watchdog timer error
occurring in standby system
3 : Hardware failure, power OFF,
reset or watchdog timer error
occurring in control system
4 : Preparing for tracking
5 : Time limit exceeded
6 : Standby system is in stop error
(except watchdog timer error)
7 : Operation differs between two
systems (in backup mode only)
8 : During memory copy from control
system to standby system
9 : Online program change
10 : Error detected by network
module of standby system
11 : System switching being executed
12 : Online module change in
progress

Error individual
information

12)

Failuer information (H)

New

drive No.(L)

File name
(ASCll: 8 characters)
EXtension *6
2EH(.)
(ASCll; 3 characters)
Failure information 2
(CRC value that is read)
Failure information 3
(CRC value that is calculated)

QnU

Parameter No./CPU No.

Number
SD16
SD17
SD18
SD19
SD20
SD21
SD22
SD23
SD24
SD25
SD26

App-154

S (Error)

File diagnostic information

SD16
SD17
SD18
SD19
SD20
SD21
SD22
SD23
SD24
SD25
SD26

13)

QnPRH

Meaning
Parameter No.*16
CPU No. (1 to 4)

(Empty)

TableApp.4.2 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

8

D9
SD50

Error reset

Error number that
performs error
reset

• Stores error number that performs error reset

U

8

New

• All corresponding bits go 1(ON) when battery voltage drops.
• Subsequently, these remain 1(ON) even after battery voltage has been
returned to normal.
b15

SD51

Battery low
latch

Bit pattern
indicating where
battery voltage
drop occurred

to
0

8

b3 b2 b1 b0

CPU error
alarm
error

1

S (Error)

New

8

1: This does not apply to Basic model QCPU.
• In the alarm, data can be held within the time specified for battery low.
• The error indicates the complete discharge of the battery.

QCPU

SD52

Battery low

Bit pattern
indicating where
battery voltage
drop occurred

• Same configuration as SD51 above
• After the alarm is detected (ON), the alarm turns OFF by error detection
(ON). (For the Universal model QCPU only)
• Turns to 0 (OFF) when the battery voltage returns to normal thereafter.

S (Error)

SD53

AC/DC DOWN
detection

Number of times
for AC/DC DOWN
detection

• Every time the input voltage falls to or below 85% (AC power)/65% (DC
power) of the rating during operation of the CPU module, the value is
incremented by 1 and stored in BIN code.
• The counter repeats increment and decrement of the value ;
0
32767
-32768
0

S (Error)

D9005

SD60

Number of
module with
blown fuse

Number of module
with blown fuse

• Value stored here is the lowest station I/O number of the module with
the blown fuse.

S (Error)

D9000

SD61

I/O module
verify error
number

I/O module verify
error module
number

• The lowest I/O number of the module where the I/O module verification
number took place.

S (Error)

D9002

A

New

8
7
8

Appendix 4 SPECIAL REGISTER LIST

App-155

TableApp.4.2 Special register
Number

Name

Corresponding
ACPU

Explanation

Set by
(When Set)

• The first annunciator number (F number) to be detected is stored here.

S (Instruction
execution)

D9009

• Stores the number of annunciators searched.

S (Instruction
execution)

D9124

Meaning

Corresponding
CPU

D9
SD62

Annunciator
number

Annunciator
number

SD63

Number of
annunciators

Number of
annunciators

When F goes ON due to OUT F or SET F instruction, the F numbers which
go progressively ON from SD64 through SD79 are registered.
The F numbers turned OFF by RST F instruction are deleted from SD64 SD79, and the F numbers stored after the deleted F numbers are shifted to
the preceding registers.
Execution of the LEDR instruction shifts the contents of SD64 to SD79 up
by one.
After 16 annunciators have been detected, detection of the 17th will not be
stored from SD64 through SD79.

SD64
SD65
SD66
SD67
SD68

Table of
detected
annunciator
numbers

SD63 0
Annunciator
detection number

SD73
SD74
SD75
SD76
SD77
SD78
SD79
SD80

CHK number

CHK number

SD90
SD91
SD92
SD93
SD94
SD95
SD96

D9127
D9128
D9129
D9130

SD62 0 50 50 50 50 50 50 50 50 50 50 50 99 (Number
detected)

SD70

SD72

D9126

SET SET SET RST SET SET SET SET SET SET SET
F50 F25 F99 F25 F15 F70 F65 F38 F110 F151 F210 LEDR

SD69

SD71

D9125

Step transition
monitoring timer
setting value
(Enabled only
when SFC
program exists)

SD97
SD98
SD99

App-156

F number for timer
set value and time
over error

SD64
SD65
SD66
SD67
SD68
SD69
SD70
SD71
SD72
SD73
SD74
SD75
SD76
SD77
SD78
SD79

1

2

3

2

3

4

5

6

7

8

9

8 (Number of
annunciators
detected)

0 50 50 50 50 50 50 50 50 50 50 50 99
0 0 25 25 99 99 99 99 99 99 99 99 15
0 0 0 99 0 15 15 15 15 15 15 15 70
0 0 0 0 0 0 70 70 70 70 70 70 65
0 0 0 0 0 0 0 65 65 65 65 65 38
0 0 0 0 0 0 0 0 38 38 38 38 110
0 0 0 0 0 0 0 0 0 110 110 110 151
0 0 0 0 0 0 0 0 0 0 151 151 210
0 0 0 0 0 0 0 0 0 0 0 210 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0

QCPU
S (Instruction
execution)

to

b8 b7

to

New

New
New

(Number
detected)

New
New
New
New
S (Instruction
execution)

New
D9108

• Set the annunciator number (F number) that will
be turned ON when the step transition
monitoring timer setting or monitoring timeout
occurs.

b15

D9132

New

• Error codes detected by the CHK instruction are stored as BCD code.
Corresponds to
SM90
Corresponds to
SM91
Corresponds to
SM92
Corresponds to
SM93
Corresponds to
SM94
Corresponds to
SM95
Corresponds to
SM96
Corresponds to
SM97
Corresponds to
SM98
Corresponds to
SM99

D9131

D9109
D9110

b0

D9111
D9112

F number setting
(0 to 255)

Timer time limit
setting
(1 to 255s:
(1s units))

• Turning ON any of SM90 to SM99 during an
active step starts the timer, and if the transition
condition next to the corresponding step is not
met within the timer time limit, the set
annunciator (F) turns ON.

U
D9113
D9114
New
New
New

Qn(H)
QnPH
QnPRH

TableApp.4.2 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

8

D9

SD100

Transmission
speed storage
area

Stores the
transmission
speed specified in
the serial
communication
setting.

96
576

: 9.6kbps,
: 57.6kbps,

b15

SD101

Communication
setting storage
area

Stores the
communication
setting specified in
the serial
communication
setting.

192
1152

: 19.2kbps,
: 115.2kbps

384 : 38.4kbps,

b6 b5 b4 b3

to

Write during RUN setting
0: Disabled
1: Enabled

to

S (Power-ON or
reset)

8
New

8

b0

Sumcheck presence
0: Absent
1: Present

S (Power-ON or
reset)

New

Q00/Q01
Q00UJ
Q00U
Q01U
Q02U*4

A

* : Since the data is used by the system, it is undefined.

CH1
transmission
speed setting
(RS-232)

Stores the preset
transmission
speed when GX
Developer is
used.

96
: 9600bps,
192 : 19.2kbps, 384
: 38.4kbps,
576 : 57.6kbps,
1152 : 115.2kbps
*: Other than RS-232 connection holds the data at RS-232 connection.
(When disconnected, the default value is 1152.)

Data sending
result storage
area

Stores the data
sending result
when the serial
communication
function is used.

Stores the error code at the timeout sending data.

SD111

Data receiving
result storage
area

Stores the data
receiving result
when the serial
communication
function is used.

Stores the error code at the time of receiving data.

S (Error)

SD118

Amount of
battery
consumption

Amount of battery
consumption

Displays the current amount of battery consumption.
The value range:1 to 2(Q00UJCPU, Q00UCPU, Q01UCPU,
Q02UCPU, Q03UD(E)CPU, Q04UD(E)HCPU)
1 to 3(Q06UD(E)HCPU)
1 to 4(Q10UD(E)HCPU, Q20UD(E)HCPU,
Q13UD(E)HCPU, Q26UD(E)HCPU)

SD105

SD110

0
: No waiting time
10 to 150: Waiting time (unit: ms)
Defaults to 0.

S (Power-ON or
reset)

New

S

New

Qn(H)
QnPH
QnPRH
QnU*3

New

Q00/Q01
Q00UJ
Q00U
Q01U
Q02U*4

S (Status
change)

New

QnU*4

S (Status
change)

New

QnU

S (Error)

8

Stores the factor which makes the battery life-prolonging function valid.
When SD119 is other than 0, the battery life-prolonging function is valid.

SD119

Battery lifeprolonging
factor

Battery lifeprolonging factor

b15

to

0:No factor
1:Foctor

b2 b1 b0

b0: CPU switch setting
b1: Backup in execution by
latch data backup function
(to standard ROM)

*3: This applies to Universal model QCPUs except for the Built-in Ethernet port QCPU.
*4: The module whose first 5 digits of serial No. is "10102" or later.

App-157

7
8

Appendix 4 SPECIAL REGISTER LIST

Transmission
wait time
storage area

Stores the
transmission wait
time specifed in
the serial
communication
setting.

SD102

8

TableApp.4.2 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
• The numbers of output modules whose fuses have blown are input as a
bit pattern (in units of 16 points).
(If the module numbers are set by parameter, the parameter-set
numbers are stored.)

SD130
SD131
SD132
SD133
SD134

Fuse blown
module

SD135

Bit pattern in units
of 16 points,
indicating the
modules whose
fuses have blown
0: No blown fuse
1: Blown fuse
present

SD130

b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1
1
0 0 0 (YC0) 0 0 0 (Y80) 0 0 0 0 0 0 0 0

1
SD131 (Y1F0)
0
SD137

0

0

0

0

0

0

0

(Y7B0)

1

1
(Y1A0)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

(Y730)

SD136

0

0

0

0

Indicates fuse blow.

• When I/O modules, of which data are different from those entered at
power-ON, have been detected, the I/O module numbers (in units of 16
points) are entered in bit pattern. (Preset I/O module numbers set in
parmeters when parameter setting has been performed.)

SD150
SD151
SD152

SD154

0

• Not cleared even if the blown fuse is replaced with a new one.
This flag is cleared by error resetting operation

SD137

SD153

1

0

I/O module
verify error

SD155
SD156
SD157

App-158

Bit pattern, in units
of 16 points,
indicating the
modules with
verify errors.
0: No I/O verify
errors
1: I/O verify error
present

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 (X Y)
0
1
SD151 0
0 0 0 0 0 ( X Y) 0 0 0 0 0 0 0 0 0
190
SD150 0

1

SD157 0 ( X Y) 0
7E0

0

0

0

0

0

0

0

0

0

0

0

Indicates an I/O module verify error.
• Not cleared even if the blown fuse is replaced with a new one.
This flag is cleared by error resetting operation.

0

0

S (Error)

New

Q00J/Q00/Q01

(2) System information

8

TableApp.4.4 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9

8

• The CPU switch status is stored in the following format:

b15

to

b12 b11 to

b8 b7

3)

Status of switch

Status of CPU
switch

b4 b3

2)

Empty

to

b0

8

1)

0: RUN
1: STOP
2: L.CLR

1): CPU switch status

SD200

to

S (Every END
processing)

2): Memory card
switch

Always OFF

3): DIP switch

b8 through b12 correspond to
SW1 through SW5 of system
setting switch 1.
0: OFF, 1: ON.
b13 through b15 are empty.

New

Qn(H)
QnPH
QnPRH

A
8

• The CPU switch status is stored in the following format:

to

b15

b8 b7

to

b4 b3
2)

Empty

to

b0

1)

1):

CPU switch status

0: RUN
1: STOP

2):

Memory card switch

Always OFF

S (Every END
processing)

New

Q00J/Q00/Q01

b15

b8 b7

to

b4 b3
2)

Empty

to

b0

1)

CPU switch status

0: RUN
1: STOP

2):

Memory card switch

Always OFF

S (when RUN/
STOP/RESET
switch changed)

New

QnU

S (Status
change)

New

Q00J/Q00/Q01
Qn(H)
QnPH
QnPRH

S (Status
change)

New

QnU

• The following bit patterns store the status of the LEDs on the CPU
module:
• 0 is off, 1 is on, and 2 is flicker.

b15

to

8)

SD201

LED status

Status of
CPU-LED

b12b11
7)

to

6)

b8 b7
5)

to

4)

b4 b3
3)

to

2)

b0
1)

1): RUN
5): BOOT
2): ERR.
6): Empty
Mode bit pattern
3): USER
7): Empty
0: OFF 1: Green
4): BAT.
8): MODE
2: Orange
(The Basic model QCPU does not include 3) to 8).)
• The following bit patterns store the status of the LEDs on the CPU
module:
• 0 is off, 1 is on, and 2 is flicker.

b15
8)

to

b12b11
7)

6)

to

b8 b7
5)

4)

to

b4 b3
3)

to

2)

b0
1)

1): RUN
5): BOOT
2): ERROR
6): Empty
3): USER
7): Empty
4): BAT.
8): MODE
(The Q00UJCPU, Q00UCPU, and Q01UCPU do not include 5).)

App-159

Appendix 4 SPECIAL REGISTER LIST

1):

7
8

• The CPU switch status is stored in the following format:

to

8

TableApp.4.4 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
• Specify the LEDs to be turned off using this register, and turn SM202
from OFF to ON to turn off the specified LEDs.
USER and BOOT can be specified as the LEDs to be turned off.
• Specify the LEDs to be turned off in the following bit pattern.
(Turned off at 1, not be turned off at 0.)

b15
SD202

LED off
command

b8
Fixed
to 0

Bit pattern of LED
that is turned off

b4
Fixed
to 0

b0
Fixed
to 0

U

New

Qn(H)
QnPH
QnPRH
QnU

S (Every END
processing)

D9015
format
change

QCPU

S (status
change)

New

QnU

USER
LED
BOOT
LED
(The Q00UJCPU, Q00UCPU, and Q01UCPU cannot specify the BOOT
LED.)
• The CPU operating status is stored as indicated in the following figure:

to

b15

b12 b11

to

b8 b7

to
2)

1): Operating status
of CPU
SD203

Operating
status of CPU

Operating status
of CPU

2): STOP/PAUSE
cause

Note: Priority is
earliest first

0:
1:
2:
3:

to

b4 b3

b0

1)

RUN
STEP-RUN (For the QnACPU only)
STOP
PAUSE

0: Instruction in remote operation program
from RUN/STOP switch ("RUN/STOP/
RESET switch" for Basic model QCPU)
1: Remote contact
2: Remote operation from GX Developer/
serial communication, etc.
3: Internal program instruction
4: Error

• The LED display color of the LED status shown in SD201 1) to 8).
b15

b12

b11

b8 b7

b4 b3

b0

1)RUN LED
0: OFF
1: Green
2)ERROR LED
0: OFF
1: Red

SD204

LED display
color

CPU-LED display
color

3)USER LED
0: OFF
1: Red
4)BAT. LED
0: OFF
1: Yellow
2: Green
5)BOOT LED
0: OFF
1: Green
6)Empty
7)Empty
8)MODE LED
0: OFF
1: Green

(The Q00UJCPU, Q00UCPU, and Q01UCPU do not include 5).)

App-160

TableApp.4.4 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

8

D9

SD207

Priorities 1 to 4

SD208

Priorities 5 to 8

8

• When error is generated, the LED display (flicker) is made according to
the error number setting priorities.
(The Basic model QCPU supports only the annunciator (error item No.
7).
• The Universal model QCPU sets execution/non-execution of LED
display of the error corresponding to the each priority ranking when the
error occurs.
• The setting areas for priorities are as follows:

b15 to b12 b11 to b8
SD207 Priority 4
Priority 3
SD208 Priority 8
Priority 7
SD209
Priority 11

D9038

8

b7 to b4 b3 to b0
Priority 2
Priority 1
Priority 6
Priority 5
Priority 10 Priority 9

D9039
format
change

(Priority 11 is valid when Redundant CPU is used.)
LED display
priority ranking

SD209

Priorities 9 to 11

Default Value
SD207 = 4321H(0000H for Basic model QCPU)
SD208 = 8765H(0700H for Basic model QCPU)
(0765H for Redundant CPU)
SD209 = 00A9H(0000H for Basic model QCPU)
(0B09H for Redundant CPU)
• No display is made if "0" is set.
• In case of the Basic model QCPU, the ERR. LED turns ON when the
annunciator turns ON, if "7" has been set to either of priorities 1 to 11.
• In case of the Basic model QCPU, the ERR. LED does not turn ON
when the annumciator turns ON, if "7" has not been set to either of
priorities 1 to 11.
However, even if "0" has been set, information concerning CPU module
operation stop (including parameter settings) errors will be indicated by
the LEDs without conditions.

U

Q00J/ Q00/Q01*9
Qn(H)
QnPH
QnPRH
QnU

Clock data

Clock data (year,
month)

b15 to b12 b11 to

b8 b7 to

b4 b3 to

7
8

b0 Example:
D9025

July, 1993
9307H
Year

A
8

New

• The year (last two digits) and month are stored as BCD code as shown
below:
SD210

8

Month

• The day and hour are stored as BCD code as shown below:

Clock data

b8 b7 to

b4 b3 to

Clock data (day,
hour)

b0 Example:

31st, 10 a.m.
3110H
Day

S (Request)/U

D9026

QCPU

Hour

• The minutes and seconds (after the hour) are stored as BCD code as
shown below:
SD212

Clock data

Clock data
(minute, second)

b15 to b12 b11 to

b8 b7

to

b4 b3

to

b0 Example:

35 min, 48 s
3548H
Minute

D9027

Second

*9: Function version is B or later.

App-161

Appendix 4 SPECIAL REGISTER LIST

b15 to b12 b11 to
SD211

TableApp.4.4 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
• The year (first two digits) and the day of the week are stored as BCD
code as shown below.
b15 to b12 b11 to

b8 b7

to

b4 b3

to

b0 Example:

1993, Friday
1905H
SD213

Clock data

Clock data
(higher digits of
year, day of week)

Day of the week
0
Sunday
1
Monday
2
Tuesday
3 Wednesday
4 Thursday
5
Friday
6 Saturday

Higher digits of year (19 or 20)

S (Request)/U

D9028

• LED display ASCII data (16 characters) stored here.
(On the Basic model QCPU, the registers store the message (16
characters of ASCII data) at error occurrence (including annunciator
ON).

SD220

SD221

b15

SD220

SD222

SD221
SD223

SD222
LED display
data

LED display data

SD224

SD223
SD224

SD225

SD225
SD226

SD226

SD227
SD227

to

b8 b7

15th character from
the right
13th character from
the right
11th character from
the right
9th character from
the right
7th character from
the right
5th character from
the right
3rd character from
the right
1st character from
the right

to

QCPU

b0

16th character from
the right
14th character from
the right
12th character from
the right
10th character from
the right
8th character from
the right
6th character from
the right
4th character from
the right
2nd character from
the right

S (When
changed)

New

S (During online
module change)

New

• The LED display device data at the time of CHK is not stored in the
Basic model QCPU and the Universal model QCPU.

SD235

Module to which
online module
change is being
performed

The header I/O
number of the
module to which
online module
change is being
performed /10H

• 10H is added to the value of the header I/O number of which the online
module change is being performed.

SD240

Base mode

0: Automatic
mode
1: Detail mode

• Stores the base mode.

S (Initial)

New

SD241

Extension stage
number

0: Main base only
1 to 7: Extension
stage number

• Stores the maximum number of the extension bases being installed.

S (Initial)

New

App-162

QnPH
QnPRH

QCPU

TableApp.4.4 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

8

D9

b7

A/Q base
differentiation

Base type
differentiation
0: QA**B is
installed
(A mode)
1: Q**B is installed
(Q mode)

Fixed to 0

Main base unit
1st extension
base
2nd extension
base
to
7th extension
base

b4
Installed Q base
presence/
absence
SD242

Base type
differentiation
0: Base not
installed
1: Q**B is installed

8

b2 b1 b0

to

S (Initial)

New

Fixed to 0
when the
base is not
installed.

Qn(H)
QnPH
QnPRH

8

b2 b1 b0

Fixed to 0

to
Main base unit
1st extension base
2nd extension base

S (Initial)

New

Q00J/Q00/Q01

A

to
4th extension base
b7
Fixed to 0

Installed Q base
presence/
absence

8

8

b2 b1 b0

to
Main base unit
1st extension
base
2nd extension
base
to
7th extension
base

Base type
differentiation
0: Base not
installed
1: Q**B is installed

Fixed to 0
when the
base is not
installed.

7
S (Initial)

New

QnU

8

• The bits from the third extension stage to the seventh extension stage
are fixed to "0" in the Q00UJCPU.
• The bits from the fifth extension stage to the seventh extension stage are
fixed to "0" in the Q00UCPU, Q01UCPU, and Q02UCPU.
b15 to b12 b11 to b8 b7 to b4 b3 to b0
Extension Extension
SD243 Extension
3
2
1

No. of base
slots

No. of base slots

SD244

SD243

SD244

No. of base
slots (Operation
status)

SD250

• As shown above, each area stores the number of slots being installed.
• The bits from the third extension stage to the seventh extension stage
are fixed to "0" in the Q00UJCPU.
• The bits from the fifth extension stage to the seventh extension stage are
fixed to "0" in the Q00UCPU, Q01UCPU, and Q02UCPU.
b15 to b12 b11 to b8 b7 to b4 b3 to b0
Extension Extension Extension Main
3
2
1
to Fixed to Fixed to Extension
SD244 Fixed
0
0
0
4

S (Initial)

New

Qn(H)
QnPH
QnPRH
QnU

SD243
No. of base slots

S (Initial)

• As shown above, each area stores the number of slots being installed.
(Number of set slots when parameter setting has been made)

SD245

SD246

Main

Extension Extension Extension
SD244 Extension
7
6
5
4

No. of base
slots (Mounting
status)

No. of base slots

Loaded
maximum I/O

Loaded maximum
I/O No.

b15 to b12 b11 to b8 b7 to b4 b3 to b0
Extension Extension Main
SD245 Extension
3
2
1
to Fixed to Fixed to Extension
SD246 Fixed
0
0
0
4

Q00J/Q00/Q01

New

Q00J/Q00/Q01*9

S (Initial)

• As shown above, each area stores the number of module-mounted slots
of the base unit (actual number of slots of the installed base unit).
• When SM250 goes from OFF to ON, the upper 2 digits of the final I/O
number plus 1 of the modules loaded are stored as BIN values.

S (Request
END)

New

Qn(H)
QnPH
QnPRH

• The upper 2 digits of the final I/O number plus 1 of the modules loaded
are stored as BIN values.

S (Initial)

New

Q00J/Q00/Q01
QnU

*9: Function version is B or later.

App-163

Appendix 4 SPECIAL REGISTER LIST

SD243

TableApp.4.4 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
Number of
modules installed

SD254

SD256
SD257
SD258

SD259

MELSECNET/
10.
MELSECNET/H
information

Information from 1st module

SD255

• Indicates the number of mounted MELSECNET/10 modules or
MELSECNET/H modules.

I/O No.

• Indicates I/O number of mounted MELSECNET/10 module or
MELSECNET/H module

Network
No.

• Indicates network No. of mounted MELSECNET/10 module or
MELSECNET/H module

Group
number

• Indicates group No. of mounted MELSECNET/10 module or
MELSECNET/H module

Station
No.

• Indicates station No. of mounted MELSECNET/10 module or
MELSECNET/H module

Standby
information

• In the case of standby stations, the module number of the standby
station is stored. (1 to 4)

QCPU

S (Initial)

New
Qn(H)
QnPH
QnPRH

SD260
to
SD264

Information from
2nd module

• Configuration is identical to that for the first module.

QnU*10

SD265
to
SD269

Information from
3rd module

• Configuration is identical to that for the first module.

SD270
to
SD274

Information from
4th module

Qn(H)
QnPH
QnPRH

• Configuration is identical to that for the first module.

QnU*11

1) When Xn0 of the mounted CC-Link module turns ON, the bit of the
corresponding station turns to 1 (ON).
2) When either Xn1 or XnF of the mounted CC-Link module turns OFF, the
bit of the corresponding station turns to 1 (ON).
3) Turns to 1 (ON) when communication between the mounted CC-Link
module and CPU module cannot be made.

Information
of 3)

SD280

CC-Link error

Error detection
status

b15 to b12 b11 to
Empty

Information
of 2)

b8 b7

to

Information
of 1)

b4 b3

to

b0
1st
module
2nd
module
3rd
module
4th
module

The above module Nos. n are in order of the head I/O numbers.
(However, the one where parameter setting has not been made is not
counted.)

*10: The Universal model QCPU except the Q00UJCPU, Q00UCPU, and Q01UCPU.
*11: The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.

App-164

S (Error)

New

Qn(H)
QnPH
QnPRH

TableApp.4.4 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

8

D9

8

1) When Xn0 of the mounted CC-Link module turns ON, the bit of the
corresponding station turns to 1 (ON).
2) When either Xn1 or XnF of the mounted CC-Link module turns OFF, the
bit of the corresponding station turns to 1 (ON).
3) Turns to 1 (ON) when communication between the mounted CC-Link
module and CPU module cannot be made.

Information
of 3)

SD281

CC-Link error

Error detection
status

b15 to b12 b11 to
Empty

Information
of 2)

b8 b7

to

8

Information
of 1)

b4 b3

to

b0

Qn(H)*14

5st
module
6nd
module
7rd
module
8th
module

S (Error)

New

QnPH*14
QnPRH*15

A

The above module Nos. n are in order of the head I/O numbers.
(However, the one where parameter setting has not been made is not
counted.)
SD286

• The number of points assigned to M is stored with 32 bits.
• Even if the points assigned to M are 32k points or less, the points are
stored.

Points assigned to
B (for extension)

• The number of points assigned to B is stored with 32 bits.
• Even if the points assigned to B are 32k points or less, the points are
stored.

SD290

Number of points
assigned for X

• Stores the number of points currently set for X devices

SD291

Number of points
assigned for Y

• Stores the number of points currently set for Y devices

Number of points
assigned for M

• Stores the number of points currently set for M devices

Number of points
assigned for L

• Stores the number of points currently set for L devices

Number of points
assigned for B

• Stores the number of points currently set for B devices

SD295

Number of points
assigned for F

• Stores the number of points currently set for F devices

SD296

Number of points
assigned for SB

• Stores the number of points currently set for SB devices

SD297

Number of points
assigned for V

• Stores the number of points currently set for V devices

SD298

Number of points
assigned for S

• Stores the number of points currently set for S devices

SD299

Number of points
assigned for T

• Stores the number of points currently set for T device

Number of points
assigned for ST

• Stores the number of points currently set for ST devices

Number of points
assigned for C

• Stores the number of points currently set for C devices

SD302

Number of points
assigned for D

• Stores the number of points currently set for D devices

SD303

Number of points
assigned for W

• Stores the number of points currently set for W devices

SD304

Number of points
assigned for SW

• Stores the number of points currently set for SW devices

SD287
SD288

Device
assignment

SD289

SD292
SD293
SD294

SD300
SD301

Device
assignment
(Same as
parameter
contents)

Device
assignment
(Same as
parameter
contents)

8
S (Initial)

New

QnU*16

7
8

S (Initial)

New

QCPU

S (Initial)

New

*14: The module whose first 5 digits of serial No. is "08032" or later.
*15: The module whose first 5 digits of serial No. is "09012" or later.
*16: The module whose first 5 digits of serial No. is "10042" or later.

App-165

Appendix 4 SPECIAL REGISTER LIST

Points assigned to
M (for extension)

8

TableApp.4.4 Special register
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

D9
16 bit modification
Number of points
assigned for Z

Device
assignment
(Same as
parameter
contents)

Number of points
assigned for ZR
(for extension)

• Stores the number of ZR device points (except the number of points of
extended data register (D) and extended link register (W)). The number
of assignment points of ZR device is stored into this SD only when 1k
point or more is set to the extended data register (D) and extended link
register (W).

Number of points
assigned for D (for
inside + for
extension)

• Stores the total number of points of the extended data register (D) and
data register in internal device memory area (stores the value in 32-bit
binary).

Number of points
assigned for W
(for inside + for
extension)

• Stores the total number of points of the extended link register (W) and
link register in internal device memory area (stores the value in 32-bit
binary).

Time reserved for
communication
processing

• Reserves the designated time for communication processing with GX
Developer or other units.
• The greater the value is designated, the shorter the response time for
communication with other devices (GX Developer, serial communication
units) becomes.
• If the designated value is out of the range above, it is processed that no
setting is made.
• Setting range: 1 to 100 ms
• Note that the scan time becomes longer by the designated time.

SD340

No. of modules
installed

• Indicates the number of mounted Ethernet module.

SD341

I/O No.

• Indicates I/O No. of mounted Ethernet module

SD342

Network
No.

• Indicates network No. of mounted Ethernet module

Group No.

• Indicates group No. of mounted Ethernet module

Station
No.

• Indicates station No. of mounted Ethernet module

Empty

• Empty
(With QCPU, the Ethernet module IP address of the 1st module is stored
in buffer memory.)

Empty

• Empty
(With QCPU, the Ethernet module error code of the 1st module is read
with the ERRRD instruction.)

SD305

SD306
SD307
SD308
SD309
SD310
SD311

SD315

Device
assignment
(assignment
including the
number of
points set to the
extended data
register (D) and
extended link
register (W))

Time reserved
for
communication
processing

SD343
SD344

Ethernet
information

SD345 to
SD346

SD347
SD348 to
SD354
SD355 to
SD361

Ethernet
information

SD362 to
SD368

Information of 1st module

Device
assignment
(Index register)

• Stores the number of points of index register (Z) to be modified in the
range of 16 bits.
(The assignment is set by the ZR device index modification setting
parameter.)

Information from
2nd module

• Configuration is identical to that for the first module.

Information from
3rd module

• Configuration is identical to that for the first module.

Information from
4th module

• Configuration is identical to that for the first module.

*10: The Universal model QCPU except the Q00UJCPU, Q00UCPU, and Q01UCPU.
*11: The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
*17: The Universal model QCPU except the Q00UJCPU.

App-166

S (Initial)

New

QnU

S (Initial)

New

QnU*17

U

New

Q00J/Q00/Q01
Qn(H)
QnPH
QnPRH

QCPU

S (Initial)

New

Qn(H)
QnPH
QnPRH
QnU*10

S (Initial)

New

Qn(H)
QnPH
QnPRH
QnU*11

TableApp.4.4 Special register
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

8

D9

SD380

Ethernet
instruction
reception status

Instruction
reception status of
1st module

b15 to b8 b7 b6 b5 b4 b3 b2 b1 b0
0
Not used
Instruction reception
status of channel 1
Instruction reception
status of channel 2
Instruction reception
status of channel 3
Instruction reception
status of channel 4
Instruction reception
status of channel 5
Instruction reception
status of channel 6
Instruction reception
status of channel 7
Instruction reception
status of channel 8

8
8
8
S (Instruction
execution)

New

QnPRH

ON: Received (Channel is being used.)
OFF: Not received (Channel is not used.)
SD381

SD382

SD383

Ethernet
instruction
reception
status

Instruction
reception status of
2nd module

• Configuration is identical to that for the first module.

Instruction
reception status of
3rd module

• Configuration is identical to that for the first module.

Instruction
reception status of
4th module

• Configuration is identical to that for the first module.

A
8
7
8

Appendix 4 SPECIAL REGISTER LIST

App-167

TableApp.4.4 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
Number of
multiple CPUs

SD393

Q00/Q01*9
QnU

• The number of CPU modules that comprise the multiple CPU system is
stored. (1 to 3, Empty also included)
• The CPU module types of No. 1 CPU to 3 and whether the CPU
modules are mounted or not are stored.

SD394

b15 to b12 b11 to
b8 b7
b0
to b4 b3 to
Empty (0) CPU No.3
CPU No.2
CPU No.1
S (Initial)

CPU mounting
information

SD394

Q00/Q01*9

CPU module mounted or
not mounted
0: Not mounted
1: Mounted

SD395

Multiple CPU
system
information

Multiple CPU
number

SD396

No. 1 CPU
operation status

SD397

No. 2 CPU
operation status

CPU module type
0: PLC CPU
1: Motion CPU
2: PC CPU

• In a multiple CPU system configuration, the CPU number of the host
CPU is stored.
CPU No. 1: 1, CPU No. 2: 2, CPU No. 3: 3, CPU No. 4: 4

No. 3 CPU
operation status

SD399

No. 4 CPU
operation statu

Q00/Q01*9
S (Initial)

New

Qn(H)*9
QnPH
QnU

The operation information of each CPU No. is stored.
(The information on the number of multiple CPUs indicated in SD393 is
stored.)

b15 b14

to
Vacancy

to
b8 b7 to
b4 b3
b0
Classification Operation status

mounted
0: Not mounted
1: Mounted
SD398

New

Q00/Q01*9
QnU*17
S (END
processing
error)

0: Normal
1: Minor fault
2: Medium fault
3: Major fault
FH: Reset

New

0: RUN
2: STOP
3: PAUSE
4: Initial
FH: Reset
QnU*11

*9: Function version is B or later.
*11: The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
*17: The Universal model QCPU except the Q00UJCPU.

(3) System clocks/counters
TableApp.4.5 Special register
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

D9
SD412
SD414
SD415

SD420

SD430

1 second
counter

Number of counts
in 1-second units

2n second clock
setting
2nms clock
setting

2n second clock
units

Scan counter

Low speed scan
counter

App-168

2nms clock units

Number of counts
in each scan

Number of counts
in each scan

• Following programmable controller CPU module RUN, 1 is added each
second
• Count repeats from 0 to 32767 to -32768 to 0
• Stores value n of 2n second clock (Default is 30)
• Setting can be made between 1 and 32767
• Stores value n of 2nms clock (Default is 30)
• Setting can be made between 1 and 32767
• Incremented by 1 for each scan execution after the CPU module is set to
RUN.
(Not counted by the scan in an initial execution type program.)
• Count repeats from 0 to 32767 to -32768 to 0
• Incremented by 1 for each scan execution after the CPU module is set to
RUN.
• Count repeats from 0 to 32767 to -32768 to 0
• Incremented by 1 for each scan execution after the CPU module is set to
RUN.
• Count repeats from 0 to 32767 to -32768 to 0
• Used only for low speed execution type programs

S (Status
change)

D9022

U

New

U

New

S (Every END
processing)

New

S (Every END
processing)

New

Q00J/Q00/Q01

S (Every END
processing)

New

Qn(H)
QnPH

QCPU

Qn(H)
QnPH
QnPRH
QnU

(4) Scan information

8

TableApp.4.6 Special register
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

D9
SD500

Execution
program No.

Program No. in
execution

• Program number of program currently being executed is stored as BIN
value.

SD510

Low speed
excution type
program No.

Low speed
execution type
program No. in
execution

• Program number of low speed excution type program No. currently
being executed is stored as BIN value.
• Enabled only when SM510 is ON.

Current scan time
(in 1 ms units)

SD520

Current scan
time
SD521

Current scan time
(in 100 s units)

SD522

Initial scan time
(in 1 ms units)
Initial scan time

SD523

Initial scan time
(in 100 s units)

SD524

Minimum scan
time (in 1 ms
units)

Minimum scan
time
SD525

Minimum scan
time (in 100 s
units)

SD526

Maximum scan
time (in 1 ms
units)

Maximum scan
time

SD528

SD529

SD532

SD533

SD534

SD535

Current scan
time for low
speed execution
type programs

Minimum scan
time for low
speed execution
type programs

Maximum scan
time for low
speed execution
type programs

SD540
END processing
time
SD541

Current scan time
(in 1 ms units)
Current scan time
(in 100 s units)
Minimum scan
time (in 1 ms
units)
Minimum scan
time (in 100 s
units)
Maximum scan
time (in 1 ms
units)
Maximum scan
time (in 100 s
units)
END processing
time (in 1 ms
units)
END processing
time (in 100 s
units)

• Stores the scan time of an initial execution type program into SD522 and
SD523.
(Measurement is made in 100 s units. (For the Universal model QCPU,
in 1 s units.))
SD522: Stores the ms place. (Storage range: 0 to 65535)
SD523: Stores the s place. (Storage range: 0 to 900 (For the Universal
model QCPU, storage range is 0 to 999))
• Stores the minimum value of the scan time except that of an initial
execution type program into SD524 and SD525. (Measurement is made
in 100 s units. (For the Universal model QCPU, in 1 s units.))
SD524: Stores the ms place. (Storage range: 0 to 65535)
SD525: Stores the s place. (Storage range: 0 to 900 (For the Universal
model QCPU, storage range is 0 to 999))

S (Every END
processing)

New

Qn(H)
QnPH

S (Every END
processing)

D9018
format
change

S (Every END
processing)

New

S (Status
change)

8
8
8

QCPU

A
8

S (First END
processing)

New

S (Every END
processing)

D9017
format
change

S (Every END
processing)

New

7
Qn(H)
QnPH
QnPRH
QnU

8

D9019
format
change

• Stores the maximum value of the scan time except that of an initial
execution type program into SD526 and SD527. (Measurement is made
in 100 s units. (For the Universal model QCPU, in 1 s units.))
SD526: Stores the ms place. (Storage range: 0 to 65535)
SD527: Stores the s place. (Storage range: 0 to 900 (For the Universal
model QCPU, storage range is 0 to 999))

S (Every END
processing)

• Stores the current scan time of a low speed execution type program into
SD528 and SD529.
(Measurement is made in 100 s units.)
SD528: Stores the ms place. (Storage range: 0 to 65535)
SD529: Stores the s place. (Storage range: 0 to 900)

S (Every END
processing)

New

• Stores the minimum value of the scan time of a low speed execution
type program into SD532 and SD533.
(Measurement is made in 100 s units.)
SD532: Stores the ms place. (Storage range: 0 to 65535)
SD533: Stores the s place. (Storage range: 0 to 900)

S (Every END
processing)

New

• Stores the maximum value of the scan time except that of the first scan
of a low speed execution type program into SD534 and SD535.
(Measurement is made in 100 s units.)
SD534: Stores the ms place. (Storage range: 0 to 65535)
SD535: Stores the s place. (Storage range: 0 to 900)

S (Every END
processing)

New

• Stores the time from the end of a scan execution type program to the
start of the next scan into SD540 and SD541.
(Measurement is made in 100 s units.(For the Universal model QCPU,
in 1 s units.))
SD540: Stores the ms place. (Storage range: 0 to 65535)
SD541: Stores the s place. (Storage range: 0 to 900) (Storage range: 0
to 900 (For the Universal model QCPU, storage range is 0 to 999))

S (Every END
processing)

New

New

Qn(H)
QnPH

Qn(H)
QnPH
QnPRH
QnU

App-169

Appendix 4 SPECIAL REGISTER LIST

SD527

Maximum scan
time (in 100 s
units)

• The current scan time is stored into SD520 and SD521.
(Measurement is made in 100 s units. (For the Universal model QCPU,
in 1 s units.))
SD520: Stores the ms place. (Storage range: 0 to 65535)
SD521: Stores the s place. (Storage range: 0 to 900 (For the
Universal model QCPU, storage range is 0 to 999))
(Example) When the current scan time is 23.6ms, the following values are
stored.
SD520 = 23
SD521 = 600

New

Qn(H)
QnPH
QnPRH
QnU

TableApp.4.6 Special register
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

D9
SD524
Minimum scan
time

Minimum scan
time (in 1 ms
units)

SD525

Minimum scan
time (in 100 s
units)

SD526

Maximum scan
time (in 1 ms
units)

Maximum scan
time
SD527

Maximum scan
time (in 100 s
units)

SD540

END processing
time (in 1 ms
units)

END processing
time
SD541

END processing
time (in 100 s
units)

SD542

Constant scan
wait time (in 1 ms
units)

Constant scan
wait time
SD543

Constant scan
wait time (in 100
s units)

SD544

Cumulative
execution time for
low speed
execution type
programs
(in 1 ms units)

Cumulative
execution time
for low speed
execution type
programs
SD545

SD546
Execution time
for low speed
execution type
programs

Cumulative
execution time for
low speed
execution type
programs
(in 100 s units)
Execution time for
low speed
execution type
programs
(in 1 ms units)

SD547

Execution time for
low speed
execution type
programs
(in 100 s units)

SD548

Scan execution
type program
execution time (in
1 ms units)

Scan execution
type program
execution time
SD549

Scan execution
type program
execution time (in
100 s units)

SD548

Scan program
execution time
(in 1 ms units)
Scan program
execution time

SD549

SD550

Service interval
measurement
module

SD551
Service interval
time
SD552

App-170

Scan program
execution time
(in 100 s units)

Unit/module No.
Module service
interval
(in 1 ms units)
Module service
interval
(in 100 s units)

• Stores the minimum value of the scan time into SD524 and SD525.
(Measurement is made in 100 s units.)
SD524: Stores the ms place. (Storage range: 0 to 65535)
SD525: Stores the s place. (Storage range: 0 to 900)

S (Every END
processing)

New
• Stores the maximum value of the scan time into SD526 and SD527.
(Measurement is made in 100 s units.)
SD526: Stores the ms place. (Storage range: 0 to 65535)
SD527: Stores the s place. (Storage range: 0 to 900)

S (Every END
processing)

• Stores the time from when the scan program ends until the next scan
starts into SD540 and SD541.
(Measurement is made in 100 s units.)
SD540: Stores the ms place. (Storage range: 0 to 65535)
SD541: Stores the s place. (Storage range: 0 to 900)

S (Every END
processing)

New

• Stores the wait time for constant scan setting into SD542 and SD543.
(Measurement is made in 100 s units. (For the Universal model QCPU,
in 1 s units.))
SD542: Stores the ms place. (Storage range: 0 to 65535)
SD543: Stores the s place. (Storage range: 0 to 900 (For the Universal
model QCPU, storage range is 0 to 999))

S (Every END
processing)

New

• Stores the cumulative execution time of a low speed execution type
program into SD544 and SD545.
(Measurement is made in 100 s units.)
SD544: Stores the ms place. (Storage range: 0 to 65535)
SD545: Stores the s place. (Storage range: 0 to 900)
• Cleared to 0 after the end of one low speed scan.

S (Every END
processing)

New

Q00J/Q00/Q01

QCPU

Qn(H)
QnPH

• Stores the execution time of a low speed execution type program during
one scan into SD546 and SD547.
(Measurement is made in 100 s units.)
SD546: Stores the ms place. (Storage range: 0 to 65535)
SD547: Stores the s place. (Storage range: 0 to 900)
• Stored every scan.

S (Every END
processing)

New

• Stores the execution time of a scan execution type program during one
scan into SD548 and SD549.
(Measurement is made in 100 s units.)
SD548: Stores the ms place. (Storage range: 0 to 65535)
SD549: Stores the s place. (Storage range: 0 to 900)
• Stored every scan.

S (Every END
processing)

New

Qn(H)
QnPH
QnPRH

• Stores the execution time of a scan program during one scan into
SD548 and SD549.
(Measurement is made in 100 s units. (For the Universal model QCPU,
in 1 s units.))
SD548: Stores the ms place. (Storage range: 0 to 65535)
SD549: Stores the s place. (Storage range: 0 to 900 (For the Universal
model QCPU, storage range is 0 to 999))
• Stored every scan.

S (Every END
processing)

New

Q00J/Q00/Q01
QnU

U

New

• Sets I/O number for module that measures service interval.

• Stores the service interval for the module specified in SD550 into SD551
and SD552 when SM551 is turned ON.
(Measurement is made in 100 s units.)
SD551: Stores the ms place. (Storage range: 0 to 65535)
SD552: Stores the s place. (Storage range: 0 to 900)

S (Request)

New

Qn(H)
QnPH
QnPRH

(5) Memory card

8

TableApp.4.7 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
• Indicates the type of the memory card installed.
b15

to

b8 b7

to

b4 b3

to

8

b0

0

SD600

Memory card
typs

Drive 1
(RAM) type

Memory card typs

0: Does not exist
1: SRAM card

0: Does not exist
(1: SRAM)
Drive 2 type
2: ATA card
3: Flash card

S (Initial and
card removal)

New

Qn(H)
QnPH
QnPRH
QnU

(The bits for the drive 1 (RAM) type and drive 2 (ROM) type are fixed to "0"
in the Q00UJCPU, Q00UCPU, and Q01UCPU.)
SD602

SD603

Drive 1
(Memory card
RAM) capacity
Drive 2
(Memory card
ROM) capacity

Drive 1 capacity

• Drive 1 capacity is stored in 1 k byte units.
• (Empty capacity after format is stored.)

S (Initial and
card removal)

New

Drive 2 capacity

• Drive 2 capacity is stored in 1 k byte units.*1

S (Initial and
card removal)

Qn(H)
QnPH
QnPRH

New

QnU*2

S (Status
change)

New

Qn(H)
QnPH
QnPRH

• The use conditions for memory card are stored as bit patterns .
(In use when ON)
• The significance of these bit patterns is indicated below:

Memory card
use conditions

Memory card use
conditions

b0 : Boot operation (QBT)

b8 : Not used

b1 : Parameters (QPA)

b9 : CPU fault history (QFD)

b2 : Device comments (QCD)

b10 : Not used

b3 : Device initial value (QDI)

b11 : Local device (QDL)

b4 : File register R (QDR)

b12 : Not used

b5 : Sampling trace (QTD)

b13 : Not used

b6 : Not used

b14 : Not used

b7 : Not used

b15 : Not used

A
8
7
8

Memory card use
conditions

b0 : Boot operation (QBT)*1

b8 : Not used

b1 : Parameters (QPA)

b9 : Not used

b2 : Device comments (QCD)

b10 : Not used

b3 : Device initial value (QDI)*2

b11 : Local device (QDL)

b4 : File register R (QDR)

b12 : Not used

b5 : Sampling trace (QTD)

b13 : Not used

b6 : Not used

b14 : Not used

b7 : Backup data (QBP) *3

b15 : Not used

S (Status
change)

New

QnU*2

*1: Turned ON at boot start and OFF at boot completion.
*2: Turned ON when reflection of device initial value is started and OFF
when reflection of device initial value is completed.
*3: The module whose first 5 digits of serial No. is "10102" or later.

When the Q2MEM-8MBA is used, value stored in the special register SD603 differs depending on the combination of the serial number of the High
Performance model QCPU and the manufacture control number of the ATA card.
For details, refer to QCPU User's Manual (Hardware Design, Maintenance and Inspection).
The Universal model QCPU except the Q00UJCPU, Q00UCPU, and Q01UCPU.

App-171

Appendix 4 SPECIAL REGISTER LIST

Memory card
use conditions

*2:

8

• The use conditions for memory card are stored as bit patterns .
(In use when ON)
• The significance of these bit patterns is indicated below:

SD604

*1:

8

TableApp.4.7 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
• Indicates the drive 3/4 type.
b15

SD620

Drive 3/4 typs

Drive 3/4 typs

to
0

to

b8 b7

b4 b3

to

b0

Drive 3
(Standrd
RAM)

Fixed to 1

Drive 4
(Standrd
ROM)

Fixed to 3

S (Initial)

New

Qn(H)
QnPH
QnPRH
QnU

S (Initial)

New

Q00J/Q00/Q01

• Drive 3 capacity is stored in 1 k byte units.
(Empty capacity after format is stored.)

S (Initial)

New

Qn(H)
QnPH
QnPRH
QnU

• Drive 3 capacity is stored in 1k byte units.

S (Initial)

New

Q00J/Q00/Q01

• Drive 4 capacity is stored in 1 k byte units.
(Empty capacity after format is stored.)

S (Initial)

New

Qn(H)
QnPH
QnPRH
QnU

S (Initial)

New

Q00J/Q00/Q01

S (Status
change)

New

Qn(H)
QnPH
QnPRH

S (Status
change)

New

QnU

S (Status
change)

New

Q00J/Q00/Q01

(The bits for the drive 3 (standard RAM) type is fixed to "0" in the
Q00UJCPU.)
• Indicates the drive 3/4 type.
b15

b8 b7 to

to
0

b4 b3 to

b0

0: Absent
Drive 3
(Standard RAM) 1: Present
Fixed to
Drive 4
(Standrd ROM) "3 (FLASH ROM)"

SD622

SD623

Drive 3
(Standard RAM)
capacity

Drive 4
(Standard
ROM) capacity

Drive 3 capacity

Drive 4 capacity

• Drive 4 capacity is stored in 1k byte units.
• The conditions for usage for drive 3/4 are stored as bit patterns.
(In use when ON)
• The significance of these bit patterns is indicated below:

Drive 3/4 use
conditions

Drive 3/4 use
conditions

b0 : Boot operation (QBT)

b8 : Not used

b1 : Parameters (QPA)

b9 : CPU fault history (QFD)

b2 : Device comments (QCD)

b10 : SFC trace (QTS)

b3 : Device initial value (QDI)

b11 : Local device (QDL)

b4 : File register (QDR)

b12 : Not used

b5 : Sampling trace (QTD)

b13 : Not used

b6 : Not used

b14 : Not used

b7 : Not used

b15 : Not used

• The conditions for usage for drive 3/4 are stored as bit patterns.
(In use when ON)
• The significance of these bit patterns is indicated below:

SD624

Drive 3/4 use
conditions

Drive 3/4 use
conditions

b0 : Not used

b8 : Module error log*2

b1 : Parameters (QPA)

b9 : Not used

b2 : Device comments (QCD)

b10 : Not used

b3 : Device initial value (QDI)*1

b11 : Local device (QDL)

b4 : File register (QDR)

b12 : Not used

b5 : Sampling trace (QTD)

b13 : Not used

b6 : Not used

b14 : Not used

b7 : Not used

b15 : Not used

*1: Turned ON at boot start and OFF at boot completion.
*2: The modules whose first 5 digits of serial No. is "11043" or later.
• The conditions for usage for drive 3/4 are stored as bit patterns.
b15

SD624

Drive 3/4 use
conditions

Drive 3/4 use
conditions

to
0

to
b5 b4
0 0 0

0

b0
0

Boot operation (QBT)
0: Not used 1: In use
File register (QDR)
0: Not used 1: In use

SD640

File register
drive

Drive number:

• Stores drive number being used by file register

S (Status
change) *10

New

Q00J/Q00/Q01
Qn(H)
QnPH
QnPRH
QnU*3

*3: The Universal model QCPU except the Q00UJCPU.
*10: On the Basic model QCPU, data is set at STOP to RUN or RSET instruction execution after parameter execution.

App-172

TableApp.4.7 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

8
Corresponding
CPU

D9

SD642

b15
b8
to
2nd character
4th character
6th character
8th character
1st character of
SD645
extension

SD641
SD642
SD643
SD644

SD643
SD644
SD645

SD646
File register file
name

File register file
name

SD645
SD646

File register
capacity

File register
capacity

3rd character of
the extension

b7

b0
to
1st character
3rd character
5th character
7th character

S (Status
change)

New

b15
b8
to
2nd character (A)
4th character (N)
6th character ( )
8th character ( )

2EH(.)

8

2nd character of
the extension

1st character of
the extension (Q)
3rd character of
the extension (R)

b7
b0
to
1st character (M)
3rd character (I)
5th character ( )
7th character ( )

8

QnU*3

A
S (Initial)

New

Q00J/Q00/Q01

8

2EH(.)
2nd character of
the extension (D)

• Stores the data capacity of the currently selected file register in 1 k word
units.

S (Status
change)

New

S (Initial)

SD648

Qn(H)
QnPH
QnPRH

• Stores file register file name (MAIN.QDR) selected at parameters as
ASCII code.

SD641
SD642
SD643
SD644

SD646

SD647

8

• Stores file register file name (with extension) selected at parameters or
by use of QDRSET instruction as ASCII code.

SD641

File register
block number

File register block
number

• Stores the currently selected file register block number.

Comment drive

Comment drive
number

• Stores the comment drive number selected at the parameters or by the
QCDSET instruction.

S (Status
change) *10

Qn(H)
QnPH
QnPRH
QnU*3
Q00J/Q00/Q01

D9035

7
8

Q00J/Q00/Q01
Qn(H)
QnPH
QnPRH
QnU*3

• Stores the comment file name (with extension) selected at the
parameters or by the QCDSET instruction in ASCII code.

SD651
SD652
SD653
SD654
SD655

Comment file
name

Comment file
name

SD656

Boot designation
file drive number

SD660

SD662

SD664
SD665

SD666

b15
b8
to
2nd character
4th character
6th character
8th character
1st character of
SD655
the extension
3rd character of
SD656
the extension

SD651
SD652
SD653
SD654

b7

b0
to
1st character
3rd character
5th character
7th character

S (Status
change)

New

S (Initial)

New

Qn(H)
QnPH
QnPRH
QnU

2EH(.)
2nd character of
the extension

• Stores the drive number where the boot designation file (*.QBT) is being
stored.
• Stores the file name of the boot designation file (*.QBT).

SD661

SD663

New

Boot operation
designation file

File name of boot
designation file

b15
b8
to
2nd character
4th character
6th character
8th character
1st character of
SD665
the extension
3rd character of
SD666
the extension

SD661
SD662
SD663
SD664

b7

b0
to
1st character
3rd character
5th character
7th character

S (Initial)

New

Qn(H)
QnPH
QnPRH
QnU*4

2EH(.)
2nd character of
the extension

*3: The Universal model QCPU except the Q00UJCPU.
*4: The Universal model QCPU except the Q00UJCPU, Q00UCPU, and Q01UCPU.
*10: On the Basic model QCPU, data is set at STOP to RUN or RSET instruction execution after parameter execution.

App-173

Appendix 4 SPECIAL REGISTER LIST

SD650

S (Status
change)

TableApp.4.7 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9

SD670

Parameter
enable drive
information

Parameter enable
drive No.

• Stores information of parameter storage destination drive which is
enabled.
0: Drive 0 (Program memory)
1: Drive 1 (SRAM card)
2: Drive 2 (Flash card/ATA card)
4: Drive 4 (Standard ROM)
(Only drive 0 and drive 4 are valid in the Q00UJCPU, Q00UCPU, and
Q01UCPU.)

S (Initial)

New

S (Status
change)

New

Indicates the status of the latch data backup function.
Presence/
absence of
backup data

Status
0

SD671

Status of latch
data backup
function

Status display

No backup data

Absent

Restore operation at
turning power supply
ON from OFF
Restoring not executed
Restoring executed when
turning power supply
ON from OFF the
following time

1

Restore ready
completion

2

Restore execution
completion

3

Backup execution wait

Restoring not executed

4

Restore repeated
execution ready
completion

Restoring executed
when turning power
supply ON from OFF

Restoring not executed

Present

• "2 Restore ready completion" is a status immediately after restoring
data.
"3 Backup execution wait" is a status after turning power supply ON from
OFF at "2 Restore ready completion".
• Stores the last 2 digits of year and month when backup is performed in
2-digit BCD code.
Backup time (Year
and month)

SD672

b15 to b12 b11 to

b8 b7 to

b4 b3 to

b0 Example:

July, 1993
9307H
Year

QnU

Month

• Stores the day and hour when backup is performed in 2-digit BCD code.

b15 to b12 b11 to

b8 b7 to

b4 b3 to

Backup time (Day
and hour)

SD673

b0 Example:

31st, 10 a.m.
3110H
Day

Hour

• Stores the minute and second when backup is performed in 2-digit BCD
code.
SD674

Backup
information

Backup time
(Minute and
second)

b15 to b12 b11 to

b8 b7

b4 b3

to

to

b0 Example:

35 min., 48 sec.
3548H
Minute

Second

• Stores the first 2 digits of year and day of week when backup is
performed in BCD code.
b15 to b12 b11 to

b8 b7

to

b4 b3

to

b0 Example:

1993, Friday
1905H
SD675

Backup time (Year
and day of week)

Higher digits of year (0 to 99)

App-174

Day of the week
0
Sunday
1
Monday
2
Tuesday
3 Wednesday
4 Thursday
5
Friday
6 Saturday

S (At write)

New

Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
• Stores the last 2 digits of year and month when data is restored in 2-digit
BCD code.
Restore time
(Year and month)

SD676

b15 to b12 b11 to

b8 b7 to

b4 b3 to

b0 Example:

8

July, 1993
9307H
Year

Month

• Stores the day and time when data is restored in 2-digit BCD code.

b15 to b12 b11 to

b8 b7 to

b4 b3 to

Restore time (Day
and time)

SD677

8

b0 Example:

31st, 10 a.m.
3110H
Day

8

Hour

• Stores the minute and second when data is restored in 2-digit BCD
code.
SD678

Backup data
restration
information

Restore time
(Minute and
second)

b15 to b12 b11 to

b8 b7

b4 b3

to

to

b0 Example:

35 min., 48 sec.
3548H
Minute

S (Initial)

A

New

Second

8

• Stores the first 2 digits of year and day of week when data is restored in
BCD code.
b15 to b12 b11 to

b8 b7

to

b4 b3

to

b0 Example:

1993, Friday
1905H
Restore time
(Year and day of
week)

SD679

SD681

SD686

S (At write)

New

Program
memory write
count index

Write count index
up to present

• Stores the index value for the number of write operations to the program
memory (flash ROM) up to the present in BIN 32-bit value.
When the index value exceeds 100 thousand times, "FLASH ROM
ERROR" (error code: 1610) occurs. (The index value is calculated even
when exceeding 100 thousand times.)
Note) The write count does not equal to the index value.(Since a flash
ROM write life is prolonged by the system, 1 is added to the write count
index when writing is performed twice or so.).

S (At write)

New

Standard ROM
write (transfer)
status

Write (transfer)
status display (percentage)

Displays the status of writing (transferring) the standard ROM (flash ROM)
in percentage. (0 to 100%) "0" is set when the write direction is set.

S (At write)

New

Write count index
up to present

• Stores the index value for the number of write operations to the standard
ROM (flash ROM) up to the present in BIN 32-bit value.
When the index value exceeds 100 thousand times, "FLASH ROM
ERROR" (error code: 1610) occurs. (The index value is calculated even
when exceeding 100 thousand times.)
Note) The write count does not equal to the index value. (Since a flash
ROM write life is prolonged by the system, 1 is added to the write count
index when the total write capacity after the previous count up reaches
about 1M byte.)

S (At write)

New

Backup error
factor

Stores the factor of the error that occurred in the backup.
0H : No error
100H: Memory card not inserted
200H: Size of backup target data exceeded
300H: Memory card write inhibit setting
400H: Memory card write error
500H: Backup target data read error (from program memory)
503H: Backup target data read error (from standard RAM)
504H: Backup target data read error (from standard ROM)
510H: Backup target data read error (from system data)

SD689

S (Backup error
occurrence)

New

SD690

Standard ROM
write count index

Backup error
factor

Backup status

Backup status

Stores the current backup status.
0 : Before backup start
1 : Backup start prepared
2 : Backup start preparation completed
3 : Backup in execution
4 : Backup completed
FF: Backup error

7
8

Displays the status of writing (transferring) the program memory (flash
ROM) in percentage. (0 to 100%) "0" is set when the write direction is set.

SD687

SD688

QnU

Write (transfer)
status display
(percentage)

SD682

SD683

Higher digits of year (0 to 99)

Day of the week
0
Sunday
1
Monday
2
Tuesday
3 Wednesday
4 Thursday
5
Friday
6 Saturday

Appendix 4 SPECIAL REGISTER LIST

Program
memory write
(transfer) status

8

QnU*1

S (Status
change)

New

*1: The module whose first 5 digits of serial No. is "10102" or later. (Except the Q00UJCPU, Q00UCPU, and Q01UCPU)

App-175

Number

Name

Meaning

Backup
execution status

Backup execution
status display
(Percentage)

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

D9
SD691

SD692

Restoration error
factor

• Displays the execution status of data backup to the memory card in
percentage (0 to 100%).
• "0" is set when the backup starts.

New

S (Status
change)

New

U

New

QnU

S (Backup in
operation)

New

QnU*1

Current restoration
status

SD694

Restoration
execution status

Restoration
execution status
display
(Percentage)

• Displays the execution status of restoration to the CPU module in
percentage (0 to 100%).
• "0" is set before the restoration.
Sets "0" (Before restoring), however, when the restoration is completed
only during the automatic restoration.

SD698
SD699

New

S (Status
change)

Restoration
status

SD697

S (Error
occurrence)

Factor of error
occurred in the
restoration

SD693

SD696

New

Stores the factor of an error that occurred in the restoration.
Each error factor is as follows:
800H: The CPU module model name is not matched.
801H: The file password is set only for the restoration destination data or is
not matched.
810H: The verified backup data file is not matched or the backup data read
failed.
Stores the current restoration execution status.
Each error factor is as follows:
0 : Before restoration start
1 : Restoration in execution
2 : Restoration completed
FF: Restoration error
Sets "0" (Before restoring), however, when the restoration is completed
only during the automatic restoration.

SD695

S (Status
change)

Specification of
writing to standard ROM
instruction count

Specification of
writing to standard
ROM instruction
count

Available
memory in
memory card

Available memory
in memory card

Backup data
capacity

Backup data
capacity

• Specifies the maximum number of executions of the writing to standard
ROM instruction (SP.DEVST) to write to the standard ROM per day.
• When the number of executions of the writing to standard ROM
instruction exceeds the number of times set by SD695, “OPERATION
ERROR” (error code: 4113) occurs.
• The setting range for SD695 is 1 to 32767. If 0 or value outside the
range is set, “OPERATION ERROR” (error code: 4113) occurs at
execution of the writing to standard ROM instruction.
Stores the available memory in memory card. (Stores the value in 32-bit
binary.)

QnU*1

Stores the backup data capacity. (Stores the value in 32-bit binary.)

*1: The module whose first 5 digits of serial No. is "10102" or later. (Except the Q00UJCPU, Q00UCPU, and Q01UCPU)

App-176

(6) Instruction-Related Registers
TableApp.4.8 Special register
Number

Name

Meaning

8
Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
SD705
Mask pattern

Mask pattern

SD706

U

New

S (During
execution)

New

Q00J/Q00/Q01
Qn(H)
QnPH
QnPRH

• Patterns masked by use of the IMASK instruction are stored in the
following manner:

SD715
SD716

• During block operations, turning SM705 ON makes it possible to use the
mask pattern being stored at SD705 (or at SD705 and SD706 if double
words are being used) to operate on all data in the block with the
masked values.

IMASK
instruction mask
pattern

b1

b0

SD715 l15

to

l1

l0

SD716 l31

to

l17

l16

SD717 l47

to

l33

l32

b15
Mask pattern

SD717

8
8
8

QCPU

A

SD718
Accumulator

Accumulator

Program No.
designation for
PLOADP
instruction

Program No.
designation for
PLOADP
instruction

• For use as replacement for accumulators used in A series programs.

S/U

New

Stores the program number of the program to be loaded by the PLOADP
instruction when designated.
Designation range: 1 to 124

U

New

SD719

SD720

SD738

• Stores the message designated by the MSG instruction.

SD739
SD740
SD741
SD742
SD743
SD744
SD745
SD746
SD747
SD748

SD750
SD751
SD752

SD754
SD755
SD756
SD757
SD758
SD759
SD760
SD761
SD762
SD763
SD764
SD765
SD766
SD767
SD768

Message
storage

Message storage

SD738
SD739
SD740
SD741
SD742
SD743
SD744
SD745
SD746
SD747
SD748
SD749
SD750
SD751
SD752
SD753
SD754
SD755
SD756
SD757
SD758
SD759
SD760
SD761
SD762
SD763
SD764
SD765
SD766
SD767
SD768
SD769

b15
b8
to
2nd character
4th character
6th character
8th character
10th character
12th character
14th character
16th character
18th character
20th character
22nd character
24th character
26th character
28th character
30th character
32nd character
34th character
36th character
38th character
40th character
42nd character
44th character
46th character
48th character
50th character
52nd character
54th character
56th character
58th character
60th character
62nd character
64th character

b7

7

b0
to
1st character

3rd character
5th character
7th character
9th character
11th character
13th character
15th character
17th character
19th character
21st character
23rd character
25th character
27th character
29th character
31st character
33rd character
35th character
37th character
39th character
41st character
43rd character
45th character
47th character
49th character
51st character
53rd character
55th character
57th character
59th character
61st character
63rd character

8

8

S (During
execution)

New

QCPU

SD769

App-177

Appendix 4 SPECIAL REGISTER LIST

SD749

SD753

Qn(H)
QnPH

TableApp.4.8 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
• Specify the limit of each PID loop as shown below.
SD774
to
SD775

SD774

PID limit setting
(for complete
derivative)

PID limit setting
(for complete
derivative)

0: With limit
1: Without limit

b1

b0

SD774 Loop16

to

Loop2

Loop1

SD775 Loop32

to

Loop18

Loop17

b15

U

New

Qn(H)
QnPRH
QnU

U

New

Q00J/Q00/Q01*9

U

New

U

New

• Specify the limit of each PID loop as shown below.
0: With limit
1: Without limit

to

b15

SD774

b8

b7

to

b1

b0

Loop8

to

Loop2

Loop1

• Selects whether or not the data is refreshed when the COM instruction is
executed.
• Designation of SD778 is made valid when SM775 turns ON.

b15 b14
SD778 0/1

to
0

b5 b4 b3 b2 b1 b0
0/1 0/1 0/1 0/1 0/1
I/O refresh
CC-Link refresh
MELSECNET/H
refresh
Automatic refresh of
intelligent function
modules
Automatic refresh of
CPU shared memory
(Fixed to "0" for
Redundant CPU)
Execution/nonexecution of
communication with
CPU module

SD778

Refresh
processing
selection when
the COM/
CCOM
instruction is
executed

b0 to b14:
0: Do not
refresh
1: Refresh
b15 bit
0: Communication
with CPU
module is
executed
1: Communication
withCPU
module is
nonexecuted

Q00J/Q00/Q01*9

• Refresh between multiple CPUs by COM instruction is performed under
the following occasion.
Receiving operation from other device: b4 of SD778(refresh in the CPU
shared memory) is turned to 1.
Sending operation from host CPU : b15 of SD778(communication with
peripheral device is executed/nonexecuted) is turned to 0.
• Selects whether or not the data is refreshed when the COM instruction is
executed.
• Designation of SD778 is made valid when SM775 turns ON.

b15 b14 to
0
SD778 0/1

b6 b5 b4 b3 b2 b1 b0
0/1 0/1 0/1 0/1 0/1 0/1
I/O refresh
CC-Link refresh
CC-Link IE controller
network or
MELSECNET/H refresh
Automatic refresh of
intelligent function
modules
Reading input/output
from group outside
multiple CPU system
Auto refresh using the
multiple CPU high speed
transmission area of
multiple CPU system
Execution/nonexecution of
communication with
CPU module

• Refresh between multiple CPUs by COM instruction is performed under
the following occasion.
Receiving operation from other device: b4 of SD778(refresh in the CPU
shared memory) is turned to 1.
Sending operation from host CPU : b15 of SD778(communication with
peripheral device is executed/nonexecuted) is turned to 0.
• When b2 (refresh of the CC-Link IE controller network and
MELSECNET/H) of SD778 is 1, the CC-Link IE controller network and
MELSECNET/H perform refresh.
Therefore, if there are many refresh points, processing time for the COM
instruction will be extended.

*9: Function version is B or later.
*11: The module whose first 5 digits of serial No. is "04012" or later.
*12: The module whose first 5 digits of serial No. is "07032" or later.
*13: The module whose first 5 digits of serial No. is "09012" or later.

App-178

Qn(H)*11

Qn(H)*13
QnPH*12
QnPRH

TableApp.4.8 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9

8

• Selects whether or not the data is refreshed when the COM, CCOM
instruction is executed.
• Designation of SD778 is made valid when SM775 turns ON.

b15 b14 to
SD778 0/1
0

SD778

Refresh
processing
selection when
the COM/
CCOM
instruction is
executed

b6 b5 b4 b3 b2 b1 b0
0/1 0/1 0/1 0/1 0/1 0/1
I/O refresh
CC-Link refresh
Refresh of
MELSECNET/H and
CC-Link IE controller
network
Automatic refresh of
intelligent function
modules

b0 to b14:
0: Do not
refresh
1: Refresh
b15 bit
0: communication
with peripheral
device is
executed
1: communication
with peripheral
device is
nonexecuted

8

U

New

QnU

Auto refresh using
QCPU standard area of
multiple CPU system and
reading input/output from
group outside.

8

• Stores the mask patterns masked by the IMASK instruction as follows:

b15

Mask pattern of
IMASK
instruction

b1

b0

SD781 l63

to

l49

l48

SD782 l79

to

l65

l64

Mask pattern

to
SD793 l255

8
A

Auto refresh using the
multiple CPU high speed
transmission area of
multiple CPU system
Execution/nonexecution of
communication with
CPU module

SD781
to
SD793

8

7
S (During
execution)

New

Qn(H)
QnPH
QnPRH
QnU

S (During
execution)

New

Q00J/Q00/Q01

U

New

Qn(H)*13
QnPRH
QnU

U

New

Q00J/Q00/Q01*9

8

l241 l240

to

(The Q00UJCPU, Q00UCPU, and Q01UCPU cannot use the special
registers SD786 to SD793.)

b15
SD781
to
SD785

Mask pattern of
IMASK
instruction

Mask pattern

b1

b0

SD781 l63

to

l49

l48

SD782 l79

to

l65

l64

to

to

SD785 l127

l113 l112

to

• Specify the limit of each PID loop as shown below.
SD794
to
SD795

SD794

PID limit setting
(for incomplete
derivative)

PID limit setting
(for incomplete
derivative)

0: With limit
1: Without limit

b1

b0

SD794 Loop16

b15
to

Loop2

Loop1

SD795 Loop32

to

Loop18

Loop17

• Specify the limit of each PID loop as shown below.
0: With limit
1: Without limit

b15

to

SD794

b8

b7
Loop8

to

b1

b0

Loop2

Loop1

*9: Function version is B or later.
*13: The module whose first 5 digits of serial No. is "09012" or later.

App-179

Appendix 4 SPECIAL REGISTER LIST

• Stores the mask patterns masked by the IMASK instruction as follows:

TableApp.4.8 Special register
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

D9

SD796

SD797

SD798

SD799

Maximum
number of
blocks used for
the multiple
CPU highspeed
transmission
dedicated
instruction
setting (for CPU
No.1)
Maximum
number of
blocks used for
the multiple
CPU highspeed
transmission
dedicated
instruction
setting (for CPU
No.2)
Maximum
number of
blocks used for
the multiple
CPU highspeed
transmission
dedicated
instruction
setting (for CPU
No.3)
Maximum
number of
blocks used for
the multiple
CPU highspeed
transmission
dedicated
instruction
setting (for CPU
No.4)

Maximum number
of blocks range for
dedicated
instructions
Range: 1 to 7
(Default: 2 Or
when setting other
than 1 to 7, the
register operates
as 7).

• Specifies the maximum number of blocks used for the multiple CPU
high-speed transmission dedicated instruction (target CPU=CPU No.1).
When the dedicated instruction of Multiple CPU transmission is
executed to the CPU No.1, and the number of empty blocks of the
dedicated instruction transmission area is less than the setting value of
this register, SM796 is turned ON, which is used as the interlock signal
for consecutive execution of the dedicated instruction of Multiple CPU
transmission.

U (At 1 scan
after RUN)

New

• Specifies the maximum number of blocks used for the multiple CPU
high-speed transmission dedicated instruction (target CPU=CPU No.2).
When the dedicated instruction of Multiple CPU transmission is
executed to the CPU No.2, and the number of empty blocks of the
dedicated instruction transmission area is less than the setting value of
this register, SM797 is turned ON, which is used as the interlock signal
for consecutive execution of the dedicated instruction of Multiple CPU
transmission.

U (At 1 scan
after RUN)

New

QnU*14*15
• Specifies the maximum number of blocks used for the multiple CPU
high-speed transmission dedicated instruction (target CPU=CPU No.3).
When the dedicated instruction of Multiple CPU transmission is
executed to the CPU No.3, and the number of empty blocks of the
dedicated instruction transmission area is less than the setting value of
this register, SM798 is turned ON, which is used as the interlock signal
for consecutive execution of the dedicated instruction of Multiple CPU
transmission.

U (At 1 scan
after RUN)

New

• Specifies the maximum number of blocks used for the multiple CPU
high-speed transmission dedicated instruction (target CPU=CPU No.4).
When the dedicated instruction of Multiple CPU transmission is
executed to the CPU No.4, and the number of empty blocks of the
dedicated instruction transmission area is less than the setting value of
this register, SM799 is turned ON, which is used as the interlock signal
for consecutive execution of the dedicated instruction of Multiple CPU
transmission.

U (At 1 scan
after RUN)

New

*14: The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
*15: The range is from 1 to 9 for the Q03UDCPU, Q04UDCPU, and Q06UDHCP whose first 5 digits of serial number is "10012" or earlier.
(Default: 2 Or when setting other than 1 to 9, the register operates as 9).

App-180

(7) Debug
TableApp.4.9 Special register
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

8
Corresponding
CPU

D9

SD840

Debug function
usage

Debug function
usage

Stores the status of the debug function usage as shown below.
0: Forced ON/OFF for external I/O
1: Executional conditioned device test
2 to 15:Absent (0 fix)
b15
to
b2 b1 b0

0

S (Status
change)

8
New

QnU*1

Forced ON/OFF for
external I/O
Executional conditioned
device test

8
8

(0: Not used, 1: Used)

*1: The module whose first 5 digits of serial No. is "10042" or later.

(8) Redundant CPU information (host system CPU information*1)

A

TableApp.4.10 Special register
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

8

D9

SD952

History of
memory copy
from control
system to
standby system

Latest status of
memory copy
from control
system to standby
system

Stores the completion status of the memory copy from control system to
standby system executed last.
1)
Stores the same value as stored into SD1596 at normal completion/
abnormal completion of the memory copy from control system to
standby system.
2)
Backed up for a power failure, this special register holds the status of
memory copy from control system to standby system executed last.
3)
Cleared to 0 by latch clear operation.

S (Status
change)

New

QnPRH

7
8

*1: The host system CPU information is stored.

(9) Remote password count
TableApp.4.11 Special register
Name

Meaning

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
SD979

Direct
MELSOFT
connection

SD980 to
SD995

Connection
1 to 16

SD998

MELSOFT
connection
using TCP port

SD999

FTP
communi
cation port

Count of unlock
processing
failures

Stores the count of unlock processing failures.
Range: 0 to FFFEH (FFFFH when the limit is exceeded)

S(Status
change)

New

QnU*1

*1: This applies to the Built-in Ethernet port QCPU.

App-181

Appendix 4 SPECIAL REGISTER LIST

Number

Set by
(When Set)

(10) A to Q conversion
ACPU special registers D9000 to D9255 correspond to Q special registers SD1000 to
SD1255 after A to Q/QnA conversion.
(However, the Basic model QCPU and Redundant CPU do not support the A to Q
conversion.)
These special registers are all set by the system, and cannot be set by the user program.
To set data by the user program, correct the program for use of the QCPU special registers.
However, some of SD1200 to SD1255 (corresponding to D9200 to 9255 before conversion)
can be set by the user program if they could be set by the user program before conversion.
For details on the ACPU special registers, refer to the user's manual for the corresponding
CPU, and MELSECNET or MELSECNET/B Data Link System Reference Manuals.

POINT
Check "Use special relay/special register from SM/SD1000" for "A-PLC" on the
PLC system tab of PLC parameter in GX Developer when the converted special
registers are used with the High Performance model QCPU, Process CPU, and
Universal model QCPU.
When not using the converted special registers, uncheck "Use special relay/
special registers from SM/SD1000" to save the time taken for processing special
registers.

Remark
Supplemental explanation on "Special Register for Modification" column
For the device numbers for which a special register for modification is
specified, modify it to the special register for QCPU.
For the device numbers for which
conversion can be used.
Device numbers for which

App-182

is specified, special register after

is specified do not function for QCPU.

TableApp.4.13 Special register
ACPU
Special
Register

D9000

Special
Register
after
Conversion

Special
Register for
Modification

–

SD1000

Name

Fuse blown

Meaning

Number of module
with blown fuse

Corresponding
CPU

Details

• When fuse blown modules are detected, the first I/O number of the
lowest number of the detected modules is stored in hexadecimal.
(Example: When fuses of Y50 to 6F output modules have blown,
"50" is stored in hexadecimal)
To monitor the number by peripheral devices, perform monitor
operation given in hexadecimal.
(Cleared when all contents of SD1100 to SD1107 are reset to 0.)
• Fuse blow check is executed also to the output modules of remote
I/O stations.

Qn(H)
QnPH

8
8

QnU*1

8

• Stores the module numbers corresponding to setting switch
numbers or base slot numbers when fuse blow occurred.

AJ02 I/O module

D9001

–

SD1001

Fuse blown

Number of module
with blown fuse

Setting
switch

Stored
data

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

8

Extension base unit
Base unit
slot No.
0
1
2
3

Stored
data
4
5
6
7

Qn(H)
QnPH

8

• For the remote I/O station, the value of (module I/O No./10H) + 1 is
stored.

D9002

D9008

–

SD1005

SD1008

SD0

I/O module
verify error

AC DOWN
counter

Self-diagnostic
error

I/O module verify
error module number

Number of times for
AC DOWN

Self-diagnostic error
number

• When the AC power supply module is used, 1 is added at
occurrence of an instantaneous power failure of within 20ms.
(The value is stored in BIN code.) It is reset when the power supply
is switched from OFF to ON.
• When the DC power supply module is used, 1 is added at
occurrence of an instantaneous power failure of within 10ms.
(The value is stored in BIN code.) It is reset when the power supply
is switched from OFF to ON.
• When error is found as a result of self-diagnosis, error number is
stored in BIN code.

7
Qn(H)
QnPH
QnU*1

8

Qn(H)
QnPH
QnU*1
Qn(H)
QnPH
QnU*1
Qn(H)
QnPH
QnU*1

*1: The relevant modules are as follows:
• The Universal model QCPU whose serial number (first five digits) is "10102" or later.
• Q00UJCPU, Q00UCPU, Q01UCPU

App-183

Appendix 4 SPECIAL REGISTER LIST

D9005

–

SD1002

• If I/O modules, of which data are different from data entered, are
detected when the power is turned on, the first I/O number of the
lowest number unit among the detected units is stored in
hexadecimal. (Storing method is the same as that of SD1000.)
To monitor the number by peripheral devices, perform monitor
operation given in hexadecimal.
(Cleared when all contents of SD1116 to SD1123 are reset to 0.)
• I/O module verify check is executed also to the modules of remote
I/O terminals.

A

TableApp.4.13 Special register
ACPU
Special
Register

D9009

D9010

D9011

D9014

Special
Register
after
Conversion

Special
Register for
Modification

Name

Meaning

Corresponding
CPU

Details

Annunciator
detection

F number at which
external failure has
occurred

• When one of F0 to 2047 is turned on by OUT F or
SET F instruction, the F number, which has been detected earliest
among the F numbers which have turned on, is stored in BIN code.
• SD1009 can be cleared by RST F or LEDR instruction.
If another F number has been detected, the clearing of SD1009
causes the next number to be stored in SD1009.

Error step

Step number at which
operation error has
occurred.

• When operation error has occurred during execution of application
instruction, the step number, at which the error has occurred, is
stored in BIN code.
Thereafter, each time operation error occurs, the contents of
SD1010 are renewed.

SD1011

Error step

Step number at which
operation error has
occurred.

• When operation error has occurred during execution of application
instruction, the step number, at which the error has occurred, is
stored in BIN code. Since the step number is stored into SD1011
when SM1011 turns from OFF to ON, the data of SD1011 is not
updated unless SM1011 is cleared by a user program.

SD1014

I/O control
mode

I/O control mode
number

• The I/O control mode set is returned in any of the following
numbers:
0: Both input and output in direct mode
1: Input in refresh mode, output in direct mode
3: Both input and output in refresh mode

SD1009

SD62

SD1010

Qn(H)
QnPH
QnU*1

Qn(H)
QnPH

• The operation status of CPU as shown below are stored in
SD1015.
b15 to b12 b11 to

Remote RUN/STOP
by computer

D9015

SD1015

SD203

Operating
status of CPU

Operating status of
CPU

0

RUN

1

STOP

2

PAUSE 1

Status in program
0

Except below

1

STOP
Instruction
execution

b8 b7

to

b4 b3

to

b0

CPU key switch
0

RUN

1

STOP

2

PAUSE 1

3

STEP RUN

Remains the same in
remote RUN/STOP
mode.
Remote RUN/STOP
by parameter setting
0

RUN

1

STOP

2

PAUSE 1

*1: When the CPU mdoule is in RUN mode and SM1040 is off, the
CPU module remains in RUN mode if changed to PAUSE mode.

*1: The relevant modules are as follows:
• The Universal model QCPU whose serial number (first five digits) is "10102" or later.
• Q00UJCPU, Q00UCPU, Q01UCPU

App-184

Qn(H)
QnPH
QnU*1

TableApp.4.13 Special register
ACPU
Special
Register

D9016

Special
Register
after
Conversion

Special
Register for
Modification

Name

Program
number

SD1016

Meaning

0: Main program
(ROM)
1: Main program
(RAM)
2: Subprogram 1
(RAM)
3: Subprogram 2
(RAM)
4: Subprogram 3
(RAM)
5: Subprogram 1
(ROM)
6: Subprogram 2
(ROM)
7: Subprogram 3
(ROM)
8: Main program

Corresponding
CPU

Details

8
8
8

• Indicates which sequence program is run presently. One value of 0
to B is stored in BIN code.

Qn(H)
QnPH

8
A

(E2PROM)
9: Subprogram 1
(E2PROM)
A: Subprogram 2

8

(E2PROM)
B: Subprogram 3
(E2PROM)
D9017

SD1017

SD524

Scan time

Minimum scan time
(10 ms units)

• If scan time is smaller than the content of SD1017, the value is
newly stored at each END. Namely, the minimum value of scan
time is stored into SD1017 in BIN code.

D9018

SD1018

SD520

Scan time

Scan time
(10 ms units)

• At every END, the scan time is stored in BIN code and always
rewritten.

Scan time

Maximum scan time
(10 ms units)

• If scan time is larger than the content of SD1019, the value is newly
stored at each END. Namely, the maximum value of scan time is
stored into SD1019 in BIN code.

D9019

D9020

SD1019

SD526

SD1020

SD1021

D9022

SD1022

–

SD412

Constant scan time
(User sets in 10 ms
units)

1 to 200

: Set. Program is executed at intervals of (set
value) 10 ms.

Scan time

Scan time
(1 ms units)

• At every END, the scan time is stored in BIN code and always
rewritten.

1 second
counter

Count in units of 1s.

• When the PC CPU starts running, it starts counting 1 every
second.
• It starts counting up from 0 to 32767, then down to -32768 and
then again up to 0. Counting repeats this routine.

QnU*1

8
Qn(H)
QnPH

• The year (last two digits) and month are stored as BCD code as
shown below.
D9025

SD1025

–

Clock data

Clock data
(year, month)

b15 to b12 b11 to

b8 b7 to

b4 b3 to

b0 Example:

1987, July
H8707

Year

Qn(H)
QnPH

Month

• The day and hour are stored as BCD code as shown below.

b15 to b12 b11 to
D9026

SD1026

–

Clock data

b8 b7 to

b4 b3 to b0

Clock data
(day, hour)

Day

QnU*1

Example:
31st, 10 a.m.
H3110

Hour

• The minute and second are stored as BCD code as shown below.

b15 to b12 b11 to
D9027

SD1027

–

Clock data

Clock data
(minute, second)

b8 b7 to

b4 b3 to b0 Example:

35 min, 48 sec.
H3548
Minute

7

Second

*1: The relevant modules are as follows:
• The Universal model QCPU whose serial number (first five digits) is "10102" or later.
• Q00UJCPU, Q00UCPU, Q01UCPU

App-185

Appendix 4 SPECIAL REGISTER LIST

D9021

Constant scan

• Sets the interval between consecutive program starts in multiples
of 10 ms.
0
: No setting

Qn(H)
QnPH

TableApp.4.13 Special register
ACPU
Special
Register

Special
Register
after
Conversion

Special
Register for
Modification

Name

Meaning

Corresponding
CPU

Details

• The day of the week is stored as BCD code as shown below.
b15

D9028

D9035

D9036

–

SD1028

SD1035

SD648

Clock data

Extension file
register

to

b8 b7

to

b4 b3

to

b0

Example:
Friday
H0005
Day of the week

Clock data
(day of week)

Use block No.

b12 b11

Always set "0"

0

Sunday

1

Monday

Qn(H)
QnPH

2

Tuesday

QnU*1

3

Wednesday

4

Thursday

5

Friday

6

Saturday

• Stores the block No. of the extension file register being used in
BCD code.
• Designate the device number for the extension file register for
direct read and write in 2 words at SD1036 and SD1037 in BIN
data.
Use consecutive numbers beginning with R0 of block No. 1 to
designate device numbers.

SD1036

Extension file
registerfor
designation of
device number
D9037

to

Device number when
individual devices
from extension file
register are directly
accessed

SD1037

Extension file register
0
Block No.1
to
area
16383
16384
to

SD1037,SD1036
Device No. (BIN data)

Block No.2
area

to

D9038

SD1038

SD207

Priorities 1 to 4
LED display
priority ranking

• Sets priority of ERROR LEDs which illuminate (or flicker) to
indicate errors with error code numbers.
• Configuration of the priority setting areas is as shown below.

SD207
SD208

D9039

D9044

D9049

SD1039

SD208

Priorities 5 to 7

b15 to b12 b11 to b8 b7 to
b4 b3 to
b0
Priority 4
Priority 3
Priority 2
Priority 1

Priority 7

Priority 6

Priority 5

• For details, refer to the applicable CPUs User's Manual and the
ACPU Programming manual (Fundamentals).

SD1044

For sampling
trace

Step or time during
sampling trace

• Turned on/off with a peripheral device.
When STRA or STRAR instruction is executed, the value stored in
SD1044 is used as the sampling trace condition.
At scanning--------0
At time--------------Time (10 msec unit)
The value is stored into SD1044 in BIN code.

SD1049

Work area for
SFC

Block number of
extension file register

• Stores the block number of the expansion file register which is
used as the work area for the execution of a SFC program in a
binary value.
• Stores "0" if an empty area of 16K bytes or smaller, which cannot
be expansion file register No. 1, is used or if SM320 is OFF.

D9050

SD1050

SFC program
error number

Error code generated
by SFC program

• Stores error code of errors occurred in the SFC program in BIN
code.
0 : No error
80: SFC program parameter error
81: SFC code error
82: Number of steps of simultaneous execution exceeded
83: Block start error
84: SFC program operation error

D9051

SD1051

Error block

Block number where
error occurred

• Stores the block number in which an error occurred in the SFC
program in BIN code.
In the case of error 83 the starting block number is stored.

D9052

SD1052

Error step

Step number where
error occurred

• Stores the step number, where error code 84 occurred in an SFC
program, in BIN value.
• Stores "0" when error code 80, 81 or 82 occurred.
• Stores the block stating step number when error code 83 occurs.

*1: The relevant modules are as follows:
• The Universal model QCPU whose serial number (first five digits) is "10102" or later.
• Q00UJCPU, Q00UCPU, Q01UCPU

App-186

Qn(H)
QnPH

TableApp.4.13 Special register
ACPU
Special
Register

Special
Register
after
Conversion

Special
Register for
Modification

Name

Meaning

Corresponding
CPU

Details

D9053

SD1053

Error transition

Transition condition
number where error
occurred

• Stores the transition condition number, where error code 84 occurred
in an SFC program, in BIN value.
Stores "0" when error code 80, 81, 82 or 83 occurred.

D9054

SD1054

Error sequence
step

Sequence step
number where error
occurred

• Stores the sequence step number of transfer condition and
operation output in which error 84 occurred in the SFC program in
BIN code.

D9055

• Stores the step number when status latch is executed.
• Stores the step number in a binary value if status latch is executed
in a main sequence program.
• Stores the block number and the step number if status latch is
executed in a SFC program.

Status latch
execution step
number

Status latch step

SD1072

PLC
communication
check

Data check of serial
communication
module

• In the self-loopback test of the serial communication module, the
serial communication module writes/reads data automatically to
make communication checks.

SD1085

Register for
setting time
check value

1 s to 65535 s

• Sets the time check time of the data link instructions (ZNRD,
ZNWR) for the MELSECNET/10.
• Setting range : 1 s to 65535 s (1 to 65535)
• Setting unit
:1s
• Default value : 10 s (If 0 has been set, default 10 s is applied)

SD1055

SD812

Block No.
(BIN)
Upper 8 bits

D9072

D9085

Number of
special
functions
modules over

Number of special
functions modules
over

• For details, refer to the manual of each microcomputer program
package.

D9091

SD1091

Detailed error
code

Self-diagnosis
detailed error code

• Stores the detail code of cause of an instruction error.

SD1094

Head I/O
number of I/O
module to be
replaced

Head I/O number of I/
O module to be
replaced

• Stores the first two digits of the head I/O number of the I/O module,
which will be dismounted/mounted online (with power on), in BIN
value.
Example) Input module X2F0 H2F

SD251

Qn(H)
QnPH

Qn(H)
QnPH

8
7
Qn(H)
QnPH
QnU*1

DIP switch
information

DIP switch
information

D9095

0

SW1
SW2
SW3
SW4
SW5

Qn(H)
QnPH

*1: The relevant modules are as follows:
• The Universal model QCPU whose serial number (first five digits) is "10102" or later.
• Q00UJCPU, Q00UCPU, Q01UCPU

App-187

Appendix 4 SPECIAL REGISTER LIST

SD200

8

Qn(H)
QnPH

b15 to b5 b4 b3 b2 b1 b0
SD1095

A

Qn(H)
QnPH

• The DIP switch information of the CPU module is stored in the
following format.
0: OFF
1: ON

D9095

8
8

Lower 8 bits

SD1090

D9094

8

Step No.
(BIN)

D9090

8

TableApp.4.13 Special register
ACPU
Special
Register

Special
Register
after
Conversion

D9100

SD1100

D9101

SD1101

D9102

SD1102

Special
Register for
Modification

Name

Meaning

Corresponding
CPU

Details

• Output module numbers (in units of 16 points), of which fuses have
blown, are entered in bit pattern. (Preset output module numbers
when parameter setting has been performed.)

b15 b14b13b12b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

D9103

SD1103

–
D9104

SD1104

D9105

SD1105

D9106

SD1106

D9107

SD1107

D9108

SD1108

D9109

SD1109

D9110

SD1110

D9111

SD1111

D9112

SD1112

D9113

SD1113

D9114

SD1114

D9116

SD1116

D9117

SD1117

D9118

SD1118

D9119

SD1119

D9121

0

0

SD1101 0

0

0

SD1107 0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Qn(H)
QnPH

0

Y7
B0

0

0

0

0

0

0

0

Y7
30

0

0

0

QnU*1

(YC0)

1

(Y80)

1

Indicates fuse blow.
• Fuse blow check is executed also to the output module of remote I/
O station.
(If normal status is restored, clear is not performed. Therefore, it is
required to perform clear by user program.)
• Set the value of the step transition monitoring timer and the
annunciator number (F number) that will be turned ON when the
monitoring timer times out.

b15

–

Step transfer
monitoring timer
setting

Timer setting valve
and the F number at
time out

to

b8 b7

F number setting
(02 to 255)

to

b0
Qn(H)
QnPH

Timer time limit setting
(1 to 255 s:(1 s units))

• By turning ON any of SM1108 to SM1114, the monitoring timer
starts. If the transition condition following a step which corresponds
to the timer is not established within set time, set annunciator (F) is
turned on.)
• When I/O modules, of which data are different from those entered
at power-ON, have been detected, the I/O module numbers (in
units of 16 points) are entered in bit pattern. (Preset I/O module
numbers set in parmeters when parameter setting has been
performed.)

–
D9120

Fuse blown
module

Bit pattern in units of
16 points, indicating
the modules whose
fuses have blown

SD1100 0

SD1120

I/O module
verification error

Bit pattern, in units of
16 points, indicating
the modules with
verification errors.

b15 b14b13b12b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 XY

SD1116 0

0

SD1117 0

0

0

0

0

SD1123 0

0

0

0

XY
7B0

1

1

0

XY
190

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SD1121

Indicates an I/O module verify error.
D9122

SD1122

D9123

SD1123

D9124

SD1124

• I/O module verify check is executed also to remote I/O station
modules.
(If normal status is restored, clear is not performed. Therefore, it is
required to perform clear by user program.)

SD63

Number of
annuciator
detections

Number of annuciator
detections

• When one of F0 to 255 (F0 to 2047 for AuA and AnU) is turned on
by SET F instruction 1 is added to the contents of SD63. When
RST F or LEDR instruction is executed, 1 is subtracted from the
contents of SD63.
• Quantity, which has been turned on by SET F instruction is stored
into SD63 in BIN code. The value of SD63 is maximum 16.

*1: The relevant modules are as follows:
• The Universal model QCPU whose serial number (first five digits) is "10102" or later.
• Q00UJCPU, Q00UCPU, Q01UCPU

App-188

Qn(H)
QnPH
QnU*1

TableApp.4.13 Special register
Special
Register
after
Conversion

Special
Register for
Modification

D9125

SD1125

SD64

D9126

SD1126

SD65

D9127

SD1127

SD66

ACPU
Special
Register

Name

Meaning

Corresponding
CPU

Details

8

• When any of F0 to 2047 is turned on by SET F instruction, the
annunciator numbers (F numbers) that are turned on in order are
registered into SD1125 to SD1132.
• The F number turned off by RST F instruction is erased from any of
SD1125 to SD1132, and the F numbers stored after the erased F
number are shifted to the preceding registerers.
By executing LEDR instruction, the contents of SD1125 to SD1132
are shifted upward by one.
When there are 8 annunciator detections, the 9th one is not stored
into SD1125 to SD1132 even if detected.

8
8

SET SET SET RST SET SET SET SET SET SET SET
F50 F25 F99 F25 F15 F70 F65 F38 F110 F151 F210 LEDR

D9128

SD1128

SD67
Annunciator
detection
number

D9129

D9130

D9131

D9132

SD1129

SD1130

SD1131

SD1132

SD68

SD69

SD70

SD71

Annunciator
detection number

SD1009

0

50 50 50 50 50 50 50 50 50 50 50 99

SD1124

0

1

SD1125

0

50 50 50 50 50 50 50 50 50 50 50 99

SD1126

0

0

25 25 99 99 99 99 99 99 99 99 15

SD1127

0

0

0

99

0

15 15 15 15 15 15 15 70

SD1128

0

0

0

0

0

0

70 70 70 70 70 70 65

SD1129

0

0

0

0

0

0

0

65 65 65 65 65 38

SD1130

0

0

0

0

0

0

0

0

38 38 38 38 110

SD1131

0

0

0

0

0

0

0

0

0 110 110 110 151

SD1132

0

0

0

0

0

0

0

0

0

2

3

2

3

4

5

6

7

8

8

8

8

Qn(H)
QnPH
QnU*1

A
8
7

0 151 151 210

8

*1: The relevant modules are as follows:
• The Universal model QCPU whose serial number (first five digits) is "10102" or later.
• Q00UJCPU, Q00UCPU, Q01UCPU

Appendix 4 SPECIAL REGISTER LIST

App-189

(11) QCPU with built-in Ethernet port
TableApp.4.14 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
Operation
result

SD1270

Stores
operationresult.

Stores the operation result of the time setting function.
0: Not executed
1: Success
FFFFH: Failure
Stores years (last two digits of the Christian Era) and monthes by two digits of
BCD code.

b15 to b12 b11 to

b8 b7 to

b4 b3 to

b0 Example:

SD1271

July, 1993
9307H
Year

Month

Stores dates and hours acquired with time setting function by two digits of
BCD code.

b15 to b12 b11 to

b8 b7 to

b4 b3 to

b0 Example:

SD1272

31st, 10 a.m.
3110H

SD1273

Time setting function

Day

Hour

Stores minutes and seconds acquired with time setting function by two digits
of BCD code.
Execution
time

Stores time
acquired with time
setting function.

b15 to b12 b11 to

b8 b7

b4 b3

to

to

b0 Example:

35 min., 48 sec.
3548H
Minute

S (status
change)

Second

Stores years (first two digits of the Christian Era) and days acquierd with time
setting function.
b15 to b12 b11 to

b8 b7

to

b4 b3

to

b0 Example:

1993, Friday
1905H
SD1274

Higher digits of year (0 to 99)

Required
response
time

SD1275

Stores time
required for clock
time aquisition.

SD1276

New

Day of the week
0
Sunday
1
Monday
2
Tuesday
3 Wednesday
4 Thursday
5
Friday
6 Saturday

Stores time taken from transmission to SNTP server to clook time setup at
CPU.
Range: 0 to FFFEH (Unit: ms)
FFFFH when the above limit is exceeded.
Specify this when a connection is to be invalidated forcibly on the user
program. If invalidation is specified for a connection, it stops communication
and does not respond. (When a remote password is used and frequent unlock
processing errors have occurred on a connection, this is useful for temporarily
inhibiting access to the connection.)
b15b14

to

b1 b0

SD1276
Connection 1
Connection 2
Connection 15

SD1277

Forced
connection
invalidation

Specifies forced
connection
invalidation.

Connection 16
b15b14 b13 b12
SD1277 0

to
0

U

b4 b3 b2 b1 b0
0
MELSOFT communication
port (UDP/IP)
MELSOFT communication
port (TCP/IP)
FTP communication port
Directconnection to
MELSOFT

0: Valid (default)
1: Invalid
This register is to be invalidated if a socket communication is used as an
open system.

*1: This applies to the Built-in Ethernet port QCPU.

App-190

QnU*1

TableApp.4.15 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

8

D9

8

Open completion status of connections (whose open system is socket
communication) using socket communication functions is stored.
All bits corresponding to connections using any communications other than
the socket communication are fixed to "0".
b15b14

SD1282

Open completion
signal

Stores open
completion status

b1 b0

to

SD1282
Connection 1
Connection 2
to
Connection 15

S (Status
change)

New

QnU*2

Connection 16

8

0 : Open processing is not completed.
1 : Open processing is completed.
Open request status of connections using socket communication functions is
stored.
All bits corresponding to connections using any communications other than
the socket communication are fixed to "0".
b15b14

SD1284

Open request
signal

Stores open
request status

8

A

b1 b0

to

SD1284
Connection 1
Connection 2
to
Connection 15

S (Status
change)

New

QnU*2

8

Connection 16

0 : No open requests
1 : In open request

7

Reception status of connections using socket communication functions is
stored.
All bits corresponding to connections using any communications other than
the socket communication are fixed to "0".
b15b14

8

b1 b0

to

SD1286

SD1286

Reception status
signal

Stores reception
status

Connection 1
Connection 2
to
Connection 15
Connection 16

S (Status
change)

New

QnU*2

S (Status
change)

New

QnU*2

Connection status of built-in Ethernet port is stored.
b15
SD1288

SD1288

Built-in Ethernet
port connection
status

Stores connection
status of built-in
Ethernet port

to

b11 b10 b9

to

b0

1/0

Connection status
0 : Not connected with or disconnected from hubs or devices.
1 : Connected to hubs or devices

It may take several seconds for the QCPU to determine whether to connect or
disconnect a built-in Ethernet port.

*2: The built-in Ethernet port QCPU whose serial number (first five digits) is "11012" or later is targeted.

App-191

Appendix 4 SPECIAL REGISTER LIST

For TCP (Normal reception mode)
0 : Data have not been received.
1 : Data have been received.
For TCP (Fixed length reception mode)
0 : Data have not been received
,or received data size has not been reached to valid buffer size.
1 : Received data size has been reached to valid buffer size.
For UDP
0 : Data have not been received.
1 : Data have been received.

(12) Fuse blown module
TableApp.4.16 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
SD1300
SD1301
SD1302
SD1303

Bit pattern in units
of 16 points,
indicating the
modules whose
fuses have blown
0 : No blown fuse
1 : Blown fuse
present

SD1304
SD1305
SD1306
SD1307

Fuse blown
module

SD1308
SD1309
to
SD1330

• The numbers of output modules whose fuses have blown are input as a
bit pattern (in units of 16 points).
(If the module numbers are set by parameter, the parameter-set
numbers are stored.)
• Also detects blown fuse condition at remote station output modules

SD1300
SD1301

b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1
1
0 0 0 (YC0) 0 0 0 (Y80) 0 0 0 0 0 0 0 0
1
(Y1F0)

0

0

0

0

1
(Y1A0)

0

0

0

0

0

0

1
SD1331

0

0

0

0

Y1F
B0

0

0

0

0

0

0

0

D9100
D9101
D9102
D9103
D9104
D9105
S (Error)

D9106
D9107

1
0

0

0

0

0

0

0

Y1F
30

New
New

Indicates fuse blow.
• Not cleared even if the blown fuse is replaced with a new one.
This flag is cleared by error resetting operation.

SD1331

Qn(H)
QnPH
QnPRH
QnU

New

(13) I/O module verification
TableApp.4.17 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
SD1400
SD1401
SD1402
Bit pattern, in units
of 16 points,
indicating the
modules with
verification errors.
0 : No I/O
verification
errors
1 : I/O verification
error present

SD1403
SD1404
SD1405
SD1406
SD1407

I/O module
verify error

SD1408
SD1409
to
SD1430

• When the I/O modules whose I/O module information differs from that
registered at power-ON are detected, the numbers of those I/O modules
are entered in bit pattern.
(If the I/O numbers are set by parameter, the parameter-set numbers
are stored.)
• Also detects I/O module information.

SD1400

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X0Y

SD1401

0

SD1431

0

0
1

XY

1FE0

1

0

0

0

0

XY
190

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D9116
D9117
D9118
D9119
D9120
D9121
S (Error)

D9122
D9123

Qn(H)
QnPH
QnPRH
QnU

New
New

Indicates an I/O module verify error.
• Not cleared even if the blown fuse is replaced with a new one.
This flag is cleared by error resetting operation.

SD1431

New

(14) Process control instructions
TableApp.4.18 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9
SD1500
SD1501

Basic period

SD1502

Process control
instruction detail
error code

Process control
instruction detail
error code

SD1503

Process control
instruction
generated error
location

SD1506
SD1507

SD1508

Basic period tome

• Set the basic period (1 second units) use for the process control
instruction using floating point data.

U

New

• Shows the detailed error contents for the error that occurred in the
process control instruction.

S (Error)

New

Process control
instruction
generated error
location

• Shows the error process block that occurred in the process control
instruction.

S (Error)

New

Dummy device

Dummy device

• Used to specify dummy devices by a process control instruction.

U

New

QnPH
QnPRH

Function
availability
selection for
process control
instruction

• Selects the availability (enabled/disabled) of the function for process
b0
control instructions.
Bumpless function
b15 b14
to
b2 b1 b0
availability setting
SD1508 0
0 1/0
0
for the S.PIDP
instrunction
Bumpless function
0: Enabled
availability for the
1: Disabled
S.PIDP instruction
(Default: 0)

U

New

QnPH
QnPRH

Floating point
pointsdata
data==

App-192

SD1501

SD1500
QnPH

(15) For redundant systems (Host system CPU information *1)

8

SD1510 to SD1599 are only valid for redundant systems.
They are all set to 0 for stand-alone systems.
TableApp.4.19 Special register
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

8
Corresponding
CPU

D9

8

The LED status for BACKUP, CONTROL, SYSTEM A, SYSTEM B is
stored in the following format:

b15 to b10b9 b8 b7 b6 b5 b4 b3 b2 to b0

0

SD1585

Redundant
system LED
status

4 LED states
• BACKUP
• CONTROL
• SYSTEM A
• SYSTEM B

0
BACKUP
0: Off
1: On (red)
5: On (orange-yellow)
2: Flicker(red) 6: Flicker
(orange-yellow)
3: On(green)
4: Flicker(green)

SYSTEM B
0: Off
1: On
2: Flicker
SYSTEM A
0: Off
1: On
2: Flicker

SD1588

Reason(s) for
system
switching failure
conditions

Reason(s) for
system switching
that occurred in
host station

Reason(s) for
system switching
failure No.

New

A

CONTROL
0: Off
1: On

Stores the reason(s) for system switching on the host system.
The following values are stored corresponding to the methods for system
switching:
Initialized to 0 when the power supply is switched off and then on or the
RESET switch is set to the RESET position and then to the neutral
position.
0: Initial value (control system has not been switched)
1: Power off, Reset, H/W failure, WDT error,
2: CPU stop error (except WDT)
3: System switching request from network module
16: System switching dedicated instruction
17: System switching request from GX Developer
• Stores the reason(s) for system switching failure.
0: System switching normal (default)
1: Tracking cable is not connected , tracking cable error, FPGA circuit
failure.
2: H/W failure, power-OFF, Reset, WDT error on the standby system
3: H/W failure, power-OFF, Reset, WDT error on the Control system
4: Tracking data transfer initialization
5: Communication timeout
6: Serious error(except WDT error) on the Standby system
7: There is difference between both systems
(detected as Backup mode only)
8: During memory copy from control system to standby system
9: During online program change
10: During detection of intelligent function module failure on the standby
system
11: System switching being executed
• Resets to "0" when host system is powered on.
• Resets to "0" once system has been switched successfully.

QnPRH

8
7

S (when
condition occurs)

8

S(when system
is switched)

QnPRH

• Stores head address of network module which a system switch request
was initiated.
• Turns off automatically by system, after network error is reset by user.

SD1590

Network module
head address,
which requested
system
switching

SD1590

Network module
head address,
which requested
system switching

b15 to b11
0
0/1

to

b1 b0
0/1 0

Each bit
0:OFF
1:ON

Module 0: CPU module is invalid
as it is 2-slot model.
Module 1: Module on the right
side of the CPU module
to

S (Error/Status
change)

New

Module11: Module at the
rightmost end of the
12-slot base (Q312B)

QnPRH

• Please refer to SD1690 which stores the corresponding head address of
network module on other system.
SD1595

SD1596

Memory copy
target I/O
number

Memory copy
status

Memory copy
target I/O number

• Stores the memory copy target I/O No.(Standby system CPU module:
3D1H) of before SM1595 is turned from OFF to ON.

Memory copy
status

• Stores the execution result of Memory copy function.
0
: Memory copy successfully completed
4241H : Standby system power supply off
4242H : Tracking cable is disconnected or is damaged
4247H : Memory copy function is being executed
4248H : Unsupported memory copy destination I/O Number

U

New

S (Status
change)

New

*1: The information of the host CPU module is stored.

App-193

Appendix 4 SPECIAL REGISTER LIST

SD1589

Reason(s) for
system switching

8
S (status
change)

(16) For redundant systems (Other system CPU information *1)
SD1600 to SD1659 is only valid during the back up mode for redundant systems, and
refresh cannot be done when in the separate mode.
SD1651 to SD1699 are valid in either the backup mode or separate mode.
When a stand-alone system SD1600 to SD1699 are all 0.
TableApp.4.20 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU
SD

Corresponding
CPU

*2

• If an error is detected by the error check for redundant system, the
corresponding bit shown below turns ON. That bit turns OFF when the
error is cleared after that.

b15
SD1600

SD1600

System error
information

Each bit
0: OFF
1: ON

b2 b1 b0
Fixed to 0

Tracking cable is not
connected or damaged
Power-OFF, reset,
watchdog timer error or
hardware failure occurred
in other system
Other system stop error
(except watchdog timer
error)
Bit turns on when failing to
connect with other system.
The following causes are
shown below:
Tracking H/W failure
Host system WDT
error
Cannot recognize
other system therefore
causing error

System error
information

S(Every END)

–

• If any of b0, b1, b2 and b15 is ON, the other bits are all OFF.
• In the debug mode, b0, b1, b2 and b15 are all OFF.
Stores the reasons for system switching.
• Stores the reasons for system switching into SD1601 of both systems
when system switching occarred.
• Initialized to 0 at power OFF to ON/reset to unreset.
• The following shows values stored into this register.
0: Initial value (System switching has not occurred)
1: Power-OFF, Reset, H/W failure, WDT error,(*)
2: CPU stop error (except WDT)
3: System switching request by network module
16: System switching dedicated instruction
17: System switching request from GX Developer
*: When the system is switched by the power OFF/reset of the control
system, "1" is not stored into SD1601 of the new standby system.

SD1601

System
switching
results

System switching
results

SD1602

System
switching
dedicated
instruction
parameter

System switching
dedicated
instruction
parameter

• Stores the parameters for system switching dedicated instruction
SP.CONTSW.
(The parameters (SD1602) for SP.CONTSW are stored in both systems
A&B)
• SD1602 is only valid when "16" is stored in SD1601.
• This SD1602 is updated once system switch instruction SP.CONTSW is
activated.

S(when system
is switched)

SD1610

Other system
diagnostic error

Diagnostic error
code

• The error value sorted in BIN code.
• Stores SD0 of the other system CPU module

S(Every END)

SD0

Other system
diagnostic error
occurrence
time

Diagnostic error
occurrence time

• Stores the date and time when diagnostics error occurred corresponding
to error code stored in SD1610.
• Data format is the same as SD1 to SD3.
• Also, stores the value to SD1 to SD3.

S(Every END)

SD1 to
SD3

SD1614

Other system
error
information
category

Error information
category code

• Stores the category code corresponding to the error comment
information/individual information code.
• Data format is the same as SD4.
• Also, stores the value to SD4.

S(Every END)

SD4

SD1615
to
SD1625

Other system
error common
information

Error common
information

• Stores the common information corresponding to the error code stored
in this system CPU.
• Data composition is the same as SD5 to SD15.
• Also, stores the value to SD5 to SD15.

S(Every END)

SD5 to
SD15

SD1626
to
SD1636

Other system
error individual
information

Error individual
information

• Stores the individual information corresponding to the error code stored
in this system CPU.
• Data composition is the same as SD16 to SD26.
• Also, stores the value to SD16 to SD26.

S(Every END)

SD16 to
SD26

SD1611
SD1612
SD1613

*2: Shows the special register (SD

App-194

) for the host system CPU module.

S(when system
is switched)

QnPRH

TableApp.4.20 Special register
Number

Name

Set by
(When Set)

Meaning

Explanation

Error code of error
to be cleared

• Stores the error code of the error to be cleared by clearing a standby
system error.
• Stores the error code of the error to be cleared into this register and turn
SM1649 from OFF to ON to clear the standby system error.
• The value in the lowest digit (1 place) of the error code is ignored when
stored into this register.
(By storing 4100 in this register and resetting the error, errors 4100 to
4109 can be cleared.)

Corresponding
ACPU
SD

SD1649

Standby system
error cancel
command

8
Corresponding
CPU

*2

8

S(Every END)

8

Stores the operation information of the other system CPU module in the
following format.
"00FFH" I stored when a communication error occurs, or when in debug
mode.

b15
SD1650

SD1650

Other system
operating
information

to
0

8

b8 b7tob4 b3to b0

A

0:No error
1:Continue error
2:Stop error
F:Communication with
other system
disabled ( )

Other system
operating
information

8

0:RUN
2:STOP
3:PAUSE
F:Communication with
other system
disabled ( )

: Communication
with other system
disabled, debug
mode

S(Every END)

7
–

QnPRH

8

Note : A communication error is caused by the following:.
• When the power supply is switched off, or when the other system is
reset.
• H/W error occurs on either of system A or B.
• WDT error occurs.
• Tracking cable is not connected.
• Tracking cable is disconnected or damaged.

SD1690

Network module
head address,
which requested
system
switching on
host (control)
system

SD1690

b15 to b11
0
0/1

Network module
head address,
which requested
system switching
on host (control)
system

to

b1 b0
0/1 0

Appendix 4 SPECIAL REGISTER LIST

• Stores head address of network module which a system switch request
was initiated, using the following format.
• Turns off automatically by system, after network error is reset by user.

Each bit
0:OFF
1:ON

Module 0:
Module 1:
to
Module11:

CPU module is
invalid as it is 2slot model
Module on the
right side of the
CPU module
Module at the
rightmost end of
the 12-slot base
(Q312B)

S(Every END)

• Please refer to SD1590 which stores the corresponding head address of
network module on host system.

*2 : Shows the special register (SD

) for the host system CPU.

App-195

(17) For redundant systems (Trucking)
SD1700 to SD1779 is valid only for redundant systems.
These are all 0 for stand-alone systems.
TableApp.4.21 Special register
Number

Name

Meaning

Explanation

Set by
(When Set)

Corresponding
ACPU

Corresponding
CPU

D9
SD1700

SD1710

Tracking error
detection count

Waiting time for
online program
change
(standby
system)

App-196

Tracking error
detection count

• When the tracking error is detected, count is added by one.
• The counter repeats an increment and decrement of the value; 0
32767
- 32768
0

Waiting time for
online program
change (standby
system)

• Set in seconds the waiting time of the standby system CPU module from
when online program change to the control system CPU module is
completed by the online program change for redundancy function until
the online program change to the standby system CPU module starts.
• If no online program change request is issued to the standby system
CPU module within the preset time after completion of the online
program change to the control system CPU module, both system CPU
modules judge it as the failure of the online program change for
redundancy. In this case, both system CPU modules resume the
consistency check between system A & B suspended during the online
program change. Also, the control system CPU module is set to accept a
new request of online program change for redundancy.
• When both systems are powered on, 90 seconds are set to SD1710 as
the default value.
• Set the value within the range 90 to 3600 seconds. When the setting is 0
to 89 seconds, it is regarded as 90 seconds for operation. If the setting is
outside the allowed range, it is regarded other than 0 to 3600 seconds
for operation.
• The waiting time for a start of online program change to the standby
system CPU module is checked according to the SD1710 setting during
online change of multiple blocks and online change of batch of files for
redundancy.

S(Error)

QnPRH

New
U/ S (Initial)

QnPRH

(18) Redundant power supply module information
SD1780 to SD1789 are valid only for a redundant power supply system.
The bits are all 0 for a singular power supply system.

8

TableApp.4.22 Special register
Number

Name

Meaning

Set by
(When Set)

Explanation

Corresponding
ACPU

Corresponding
CPU

D9

8

• Stores the status of the redundant power supply module with input
power OFF in the following bit pattern.
• Stores 0 when the main base unit is not the redundant power main base
unit (Q38RB).
Input power OFF
detection status of
1
power supply 2

SD1780

Power supply
off detection
status

Power supply off
detection status

b15

to

Input power OFF
detection status of
power supply 1 1

b9 b8 b7

to

SD1780

to

b1 b0

to

Each bit
0: Input power ON status/ No
redundant power supply
module
1: Input power OFF status

8
S(Every END)

New

A

Main base unit
Extension base unit 1st stage
:
Extension base unit 7th stage
Main base unit
Extension base unit 1st stage
:
Extension base unit 7th stage

8

• When configuring multiple CPU, the status is stored to 1st CPU module.
• Stores the failure detection status of the redundant power supply module
in the following bit pattern. (The corresponding bit is cleared to 0 when
the input power to the faulty redundant power supply module is switched
OFF after detection of the redundant power supply module failure.)
• Stores 0 when the main base unit is not the redundant power main base
unit (Q38RB).
Failure detection
status of power
supply 2 1

SD1781

Power supply
failure detection
status

Power supply
failure detection
status

b15
SD1781

to
to

b9 b8 b7

Failure detection
status of power
supply 1 1
to
to

b1 b0

7
8
S(Every END)

New

Qn(H)*2
QnPH*2
QnPRH
QnU*3

Appendix 4 SPECIAL REGISTER LIST

Each bit
0: Redundant power supply
module failure not
detected/No redundant power
supply module
1: Redundant power supply
module failure detected
(Detectable for redundant
power supply module only)
Main base unit
Extension base unit 1st stage
:
Extension base unit 7th stage
Main base unit
Extension base unit 1st stage
:
Extension base unit 7th stage

• When configuring multiple CPU, the status is stored to 1st CPU module.

SD1782

Momentary
power failure
detection
counter for
power supply

Momentary power
failure detection
count for power
supply 1

1*1

SD1783

Momentary
power failure
detection
counter for
power supply
2*1

Momentary power
failure detection
count for power
supply 2

• Counts the number of times of momentary power failure of the power
supply 1/2.
• Monitors the status of the power supply 1/ 2 mounted on the redundant
power main base unit (Q38RB) and counts the number of times of
momentary power failure.
Status of power supply 1/power supply 2 mounted on the redundant
extension base unit is not monitored.
• When the CPU module starts, the counter of the power supply 1/ 2 is
cleared to 0.
• If the input power to one of the redundant power supply modules is
turned OFF, the corresponding counter is cleared to 0.
The counter is incremented by 1 every time the momentary power failure of
the power supply 1/ 2 is detected.(The counter repeats increment and
decrement of the value; 0
32767
– 32768
0 (The system monitor
of GX Developer shows the counter within the range between 0 and 65535.
• Stores 0 when the main base unit is not the redundant power main base
unit (Q38RB).
• When configuring multiple CPU, the status is stored to 1st CPU module.
• The counter repeats increment and decrement of the value, 0
32767
– 32768
0
(The system monitor of GX Developer shows the counter within the
range between 0 and 65535.

8

S(Every END)

New

S(Every END)

New

*1: The "power supply 1" in dicates the redundant power supply module mounted on the POWER 1 slot of the redundant base unit (Q38RB/68RB/Q65WRB).
The "power supply 2" indicates the redundant power supply module mounted on the POWER 2 slot of the redundant base unit (Q38RB/68RB/Q65WRB).
*2: The module whose first 5 digits of serial No. is "07032" or later.
However, for the multiple CPU system configuration, this applies to all CPU modules whose first 5 digits of serial No. are "07032" or later.
*3: The module whose first 5 digits of serial No. is "10042" or later.

App-197

Appendix 5 APPLICATION PROGRAM EXAMPLES
Appendix 5.1 Concept of Programs which Perform
Operations of Xn, n X
(1) Concept of programs which perform operations of Xn
Xn can be operated using e(nlogeX).
For example, the operation of 101.2 is e(1.2
sequence program as shown below.

loge10)

, which is represented in the form of a

Converts 10 into a real number format data
and stores the result in D0 and D1.
Executes Loge10 operation and stores the
result in D2 and D3.
Converts 12 into a real number format data
and stores the result into D4 and D5.
Divides D4 and D5 (12) by D0 and D1 (10),
and stores the result (1, 2) in D6 and D7 (1, 2).
Multiplies D2 and D3 (Loge10) by D6 and
D7 (1, 2) and stores the result in D8 and D9.
Executes Loge(D8, D9) operation and stores
the result in D10 and D11.

(2) Concept of program which performs operation of n X
n

1
X can be operated using e( n logeX) .
1

For example, the operation of 3 10 is e( 3

log e10)

, which is represented in the form of a

sequence program as shown below.
Converts 10 into a real number format data
and stores the result in D20 and D21.
Executes Loge10 operation and stores the
result in D22 and D23.
Converts 3 into a real number type data
and stores the result in D24 and D25.
Divides D22 and D23 (Loge10) by D24 and
D25 (3) and stores the result in D26 and D27.
Executes Loge(D26, D27) operation and
stores the result in D28 and D29.

App-198

I

INDEX

I

Index-1

[Symbols]
- (BIN 16-bit subtraction operations).................... 6-22
$+ (Linking character strings) ...................... 6-65,6-67
$=, $<>, $>, $<=, $<, $>= (Character string data
comparisons) ....................................................... 6-11
$MOV (Character string transfers) .................... 6-112
* (BIN 16-bit multiplication operations) ................ 6-30
+ (BIN 16-bit addition operations)........................ 6-22
/ (BIN 16-bit division operations) ......................... 6-30
<(BIN 16-bit data comparisons)............................. 6-2
<=(BIN 16-bit data comparisons)........................... 6-2
<>(BIN 16-bit data comparisons)........................... 6-2
=(BIN 16-bit data comparisons)............................. 6-2
>(BIN 16-bit data comparisons)............................. 6-2
>=(BIN 16-bit data comparisons)........................... 6-2
[Numerics]
16-bit data block transfers (FMOV) ......... 6-120,6-122
16-bit data checks (SUM) .................................... 7-69
16-bit data exchange (XCH) .............................. 6-124
16-bit data exclusive NOR operation (WXNR)..... 7-27
16-bit data searches (SER) ................................. 7-66
16-bit dead band controls (BAND)..................... 7-324
16-bit exclusive OR operations (WXOR) ............. 7-19
16-bit negation transfers (CML) ......................... 6-114
16-bit transfers (MOV) ....................................... 6-106
1-bit shift to left of n-bit data (BSFL) ............ 7-49,7-51
1-bit shift to right of n-bit data (BSFR) ......... 7-49,7-51
1-word shift to left of n-word data (DSFL).... 7-54,7-56
1-word shift to right of n-word data (DSFR)
..................................................................... 7-54,7-56
32-bit data checks (DSUM) ................................. 7-69
32-bit data exchanges (DXCH).......................... 6-124
32-bit data exclusive NOR operation (DXNR) ..... 7-27
32-bit data searches (DSER)............................... 7-66
32-bit dead band controls (DBAND) .................. 7-324
32-bit exclusive OR operations (DXOR) .............. 7-19
32-bit negation transfers (DCML) ...................... 6-114
32-bit transfers (DMOV) .................................... 6-106
4-bit dissociation of 16-bit data (DIS) .................. 7-77
4-bit linking of 16-bit data (UNI) ........................... 7-79
7-segment decode (SEG) .................................... 7-75
[A]
A contact operation start (LD)................................ 5-2
A contact parallel connection (OR) ........................ 5-2
A contact series connection (AND)........................ 5-2
ACOS (COS-1 operation on floating-point data (Single
precision)) .......................................................... 7-267
ACOSD (COS-1 operation on floating-point data
(Double precision)) ............................................ 7-269
Addition
Addition of floating decimal point (Double precision)
(ED+)........................................................ 6-50,6-52
Addition of floating decimal point (Single precision)
(E+) .......................................................... 6-46,6-48
BCD 4-digit addition (B+) ................................. 6-34
BCD 8-digit addition (DB+)............................... 6-38

Index - 2

BIN 16-bit addition operations (+) .................... 6-22
BIN 32-bit addition operations (D+).................. 6-26
Block addition (BK+)................................. 6-59,6-62
Addition and subtraction of floating decimal point data
(Double precision) (ED+, ED-) ..................... 6-50,6-52
Addition and subtraction of floating decimal point data
(Single precision) (E+, E-)............................ 6-46,6-48
ADRSET (Indirect address read) ....................... 7-395
ANB (Ladder block series connections)............... 5-10
AND (=, <>, >, <=, <, >=) (BIN 16-bit data
comparisons) ......................................................... 6-2
AND (A contact series connection) ........................ 5-2
AND (D=, D<>, D>, D<=, D<, D>=) (BIN 32-bit data
comparisons) ......................................................... 6-4
AND (E=, E<>, E>, E<=, E<, E>=) (Floationg decimal
point data comparisons(Single precision))............. 6-6
AND (ED=, ED<>, ED>, ED<=, ED<, ED>=) (Floationg
decimal point data comparisons(Double precision))
............................................................................... 6-8
And inverse (ANI) .................................................. 5-3
AND($=, $<>, $>, $<=, $<, $>=) (Character string data
comparisons) ....................................................... 6-11
ANDF (Pulse series connections / trailing edge
leading edg) ..................................................... 5-5,5-7
ANDP (Pulse series connections / leading edge
leading edg) ..................................................... 5-5,5-7
ANDPI, ANDFI ....................................................... 5-8
ANI (B contact series connection) ......................... 5-2
Annunciator output (OUT F) ................................ 5-28
Application instructions ........................................ 2-29
Arithmetic operation instructions.......................... 2-16
ASC (Conversion from hexadecimal BIN to ASCII)
........................................................................... 7-228
ASIN (SIN-1 operation on floating-point data (Single
precision)) .......................................................... 7-262
ASIND (SIN-1 operation on floating-point data (Double
precision)) .......................................................... 7-265
ATAN (TAN-1 operation on floating-point data (Single
precision)) .......................................................... 7-271
ATAND (TAN-1 operation on floating-point data
........................................................................... 7-273
[B]
B- (BCD 4-digit subtraction) ................................. 6-34
B contact operation start (LDI) ............................... 5-2
B* (BCD 4-digit multiplication) ............................. 6-42
B+ (BCD 4-digit addition) ..................................... 6-34
B/ (BCD 4-digit division)....................................... 6-42
BACOS (BCD type COS-1 operation) ................ 7-317
BAND (16-bit dead band controls) ..................... 7-324
Basic instructions ................................................. 2-10
BASIN (BCD type SIN-1 operation).................... 7-315
BATAN (BCD type TAN-1 operation) ................. 7-313
Batch recovery of index register (ZPOP) ........... 7-400
Batch reset of bit devices (BKRST) ..................... 7-64
Batch save of index register (ZPUSH) ............... 7-400
BCD (BIN data to 4-digit) ..................................... 6-73
BCD 4-digit addition and subtraction operations (B+,
B-) ........................................................................ 6-34

BCD 4-digit multiplication and division operations (B*,
B/) ........................................................................ 6-42
BCD 4-digit square roots (BSQR)...................... 7-306
BCD 8-digit addition and subtraction operations (DB+,
DB-) ..................................................................... 6-38
BCD 8-digit multiplication and division operations
(DB*, DB/)............................................................ 6-44
BCD 8-digit square roots (BDSQR) ................... 7-306
BCD conversion
Conversion from BIN data to 4-digit BCD (BCD)
......................................................................... 6-73
Conversion from BIN data to 8-digit BCD (DBCD)
......................................................................... 6-73
BCD type COS operations (BCOS) ................... 7-311
BCD type COS-1 operations (BACOS) .............. 7-317
BCD type SIN operation (BSIN) ........................ 7-309
BCD type SIN-1 operation (BASIN) ................... 7-315
BCD type TAN operation (BTAN) ...................... 7-313
BCD type TAN-1 operations (BATAN) ............... 7-319
BCDDA (Conversion from BCD 4-digit to decimal
ASCII) ................................................................ 7-189
BCOS (BCD type COS operations) ................... 7-311
BDSQR (BCD 8-digit square roots) ................... 7-306
BIN (BCD 4-digit data to BIN data)...................... 6-75
BIN 16-bit addition and subtraction operations (+, -)
............................................................................. 6-22
BIN 16-bit data comparisons (=, <>, >, <=, <, >=)
............................................................................... 6-2
BIN 16-bit data sort operations (SORT) .............. 7-95
BIN 16-bit multiplication and division operations (*, /)
............................................................................. 6-30
BIN 16-bit to BIN 32-bit (DBL) ............................. 6-88
BIN 16-bit to Gray code (GRY)............................ 6-90
BIN 32-bit addition and subtraction operations (D+, D-)
............................................................................. 6-26
BIN 32-bit block data comparisons (DBKCMP …,
DBKCMP … P) .................................................... 6-18
BIN 32-bit data block addition and subtraction
operations (DBK+(P),DBK-(P))............................ 6-62
BIN 32-bit data comparisons (D=, D<>, D>, D<=, D<,
D>=)....................................................................... 6-4
BIN 32-bit data sort operations (DSORT)............ 7-95
BIN 32-bit data to BIN 16-bit data (WORD)......... 6-89
BIN 32-bit data to Gray code (DGRY) ................. 6-90
BIN 32-bit multiplication and division operations (D*,
D/)........................................................................ 6-32
BIN block data comparisons (BKCMP …) ... 6-15,6-18
BINDA (Conversion from BIN 16-bit data to decimal
ASCII) ................................................................ 7-183
BINHA (Conversion from BIN 16-bit data to
hexadecimal ASCII)........................................... 7-186
Bit data .................................................................. 3-3
Bit device output reverse (FF) ............................. 5-40
Bit device shifts (SET) ......................................... 5-44
Bit processing instructions................................... 2-34
Bit reset for word devices (BRST) ....................... 7-59
Bit set for word devices (BSET)........................... 7-59
Bit tests (TEST/DTEST) ...................................... 7-61
BK- (Block subtraction)................................ 6-59,6-62

BK+ (Block addition) .................................... 6-59,6-62
BKAND (Block logical products) ............................ 7-9
BKBCD (Conversion from block BIN 16-bit data to
BCD 4-digit data) ................................................. 6-98
BKBIN (Conversion from block BCD 4-digit data to
block BIN 16-bit data) ........................................ 6-100
BKCMP … (BIN block data comparisons).... 6-15,6-18
BKOR (Block logical sum operations).................. 7-17
BKRST (Batch reset of bit devices) ..................... 7-64
BKXNR (Block exclusive NOR operations).......... 7-33
BKXOR (Block exclusive OR operations) ............ 7-25
Block 16-bit exchanges (BXCH) ........................ 6-126
Block 16-bit transfers (BMOV) ........................... 6-117
Block addition (BK+) .................................... 6-59,6-62
Block exclusive NOR operations (BKXNR).......... 7-33
Block exclusive OR operations (BKXOR) ............ 7-25
Block logical products (BKAND) ............................ 7-9
Block logical sum operations (BKOR).................. 7-17
Block subtraction (BK-) ................................ 6-59,6-62
BMOV (Block 16-bit data transfers) ................... 6-117
BREAK (Forced end of FOR to NEXT instruction loop)
........................................................................... 7-108
BRST (Bit reset for word devices) ....................... 7-59
BSET (Bit set for word devices)........................... 7-59
BSFL (1-bit shift to left of n-bit data) ............ 7-49,7-51
BSFR (1-bit shift to right of n-bit data) ......... 7-49,7-51
BSIN (BCD type SIN operation)......................... 7-309
BSQR (BCD 4-digit square roots)...................... 7-306
BTAN (BCD type TAN operation) ...................... 7-313
BTOW (Data linking in byte units)........................ 7-85
Buffer memory access instructions...................... 2-41
BXCH (Block 16-bit data exchanges) ................ 6-126
[C]
Calculation of averages for 16-bit or 32-bit data
(MEAN(P),DMEAN(P)) ...................................... 7-103
Calculation of totals for 16-bit data (WSUM) ....... 7-99
Calculation of totals for 32-bit data (DWSUM)
................................................................. 7-101,7-103
CALL (Subroutine program calls) ...................... 7-110
Cautions on programming ................................... 3-27
Changing check format of CHK instruction (CHKCIR,
CHKEND) .......................................................... 7-179
Character string data ........................................... 3-11
Character string data comparisons...................... 6-11
Character string length detection (LEN) ............ 7-204
Character string processing instructions.............. 2-43
Character string search (INSTR) ...7-239,7-241,7-243
Character string transfers ($MOV)..................... 6-112
CHKCIR (Changing check format of CHK instruction)
........................................................................... 7-179
CHKEND (Changing check format of CHK instruction)
........................................................................... 7-179
CHKST, CHK (Special format failure checks).... 7-175
CJ (Pointer branch instruction) .......................... 6-129
Clock comparison (TM=,TM,TM>,TM=)............. 7-361
Clock data addition operation (DATE+) ............. 7-348
Clock data subtraction operation (DATE-) ......... 7-350
Clock instructions................................................. 2-52

Index - 3

I

CML (16-bit negation transfers) ......................... 6-114
COM (Refresh instruction) ............. 7-134,7-137,7-141
Common logarithm operation on floating-point data
(Double precision) (LOG10D(P)) ....................... 7-302
Common logarithm operation on floating-point data
(Single precision) (LOG10(P)) ........................... 7-300
Comparison operation instruction table ............... 2-10
Comparison operation instructions ........................ 6-2
Comparisons (BIN 16-bit data) .............................. 6-2
Comparisons (BIN 32-bit data) .............................. 6-4
Comparisons (Character string data) .................. 6-11
Complement of 2 of BIN 16-bit data (NEG) ......... 6-94
Complement of 2 of BIN 32-bit data (DNEG) ...... 6-94
COMRD (Reading device comment data) ......... 7-201
Conditions for execution of instructions ............... 3-33
Connection instructions
Association instruction table............................... 2-7
Ladder block parallel connection (ORB) .......... 5-10
Ladder block series connection (ANB)............. 5-10
Linking character strings ($+)........................... 6-65
Contact instruction ................................................. 2-6
Contact instructions
Operation start (LD, LDI).................................... 5-2
Parallel connection (OR, ORI)............................ 5-2
Pulse operation start (LDF, LDP) ................. 5-5,5-7
Pulse parallel connection (ORF,ORP) ......... 5-5,5-7
Pulse serial connection (ANF, ANP) ............ 5-5,5-7
Series connection (AND, ANI)............................ 5-2
Conversion
BCD 4-digit to BIN (BIN) .................................. 6-75
BCD 8-digit to BIN (DBIN)................................ 6-75
BIN 16-bit to BIN 32-bit (DBL).......................... 6-88
BIN 16-bit to floating decimal point (Double
precision) (FLTD) ............................................. 6-81
BIN 16-bit to floating decimal point (Single
precision) (FLT)................................................ 6-78
BIN 16-bit to Gray code (GRY) ........................ 6-90
BIN 32-bit to BIN 16-bit (WORD) ..................... 6-89
BIN 32-bit to floating decimal point (Double
precision) (DFLTD)........................................... 6-81
BIN 32-bit to floating decimal point (Single
precision) (DFLT) ............................................. 6-78
BIN 32-bit to Gray code (DGRY)...................... 6-90
BIN to BCD 4-digit (BCD)................................. 6-73
BIN to BCD 8-digit (DBCD) .............................. 6-73
Double precision to Single precision (EDCON)
....................................................................... 6-104
Floating decimal point data to BIN 16-bit (Double
precision) (INTD).............................................. 6-86
Floating decimal point data to BIN 16-bit (Single
precision) (INT) ................................................ 6-83
Floating decimal point data to BIN 32-bit (Single
precision) (DINT).............................................. 6-83
Floating decimal point data to BIN32-bit (Double
precision) (DINTD) ........................................... 6-86
Gray code to BIN 16-bit (GBIN) ....................... 6-92
Gray code to BIN 32-bit (DGBIN)..................... 6-92
Single precision to Double precision (ECON)
....................................................................... 6-102

Index - 4

Conversion from ASCII to hexadecimal BIN (HEX)
........................................................................... 7-230
Conversion from BCD 4-digit to decimal ASCII
(BCDDA) ............................................................ 7-189
Conversion from BCD 8-digit to decimal ASCII
(DBCDDA) ......................................................... 7-189
Conversion from BIN 16-bit to character string (STR)
........................................................................... 7-206
Conversion from BIN 16-bit to decimal ASCII (BINDA)
........................................................................... 7-183
Conversion from BIN 16-bit to floating decimal point
(Double precision) (FLTD) ................................... 6-81
Conversion from BIN 16-bit to floating decimal point
(Single precision) (FLT) ....................................... 6-78
Conversion from BIN 16-bit to hexadecimal ASCII
(BINHA) ............................................................. 7-186
Conversion from BIN 32-bit to character string (DSTR)
........................................................................... 7-206
Conversion from BIN 32-bit to decimal ASCII
(DBINDA) ........................................................... 7-183
Conversion from BIN 32-bit to floating decimal point
(Double precision) (DFLTD)................................. 6-81
Conversion from BIN 32-bit to floating decimal point
(Single precision) (DFLT)..................................... 6-78
Conversion from BIN 32-bit to hexadecimal ASCII
(DBINHA) ........................................................... 7-186
Conversion from block BCD 4-digit data to block BIN
16-bit data (BKBIN)............................................ 6-100
Conversion from block BIN 16-bit data to BCD 4-digit
data (BKBCD) ...................................................... 6-98
Conversion from character string to BIN 16-bit (VAL)
........................................................................... 7-212
Conversion from character string to BIN 32-bit (DVAL)
........................................................................... 7-212
Conversion from character string to floating decimal
point (EVAL) ...................................................... 7-224
Conversion from decimal ASCII to BCD 4-digit
(DABCD) ............................................................ 7-198
Conversion from decimal ASCII to BCD 8-digit
(DDABCD) ......................................................... 7-198
Conversion from decimal ASCII to BIN 16-bit (DABIN)
........................................................................... 7-192
Conversion from decimal ASCII to BIN 32-bit
(DDABIN) ........................................................... 7-192
Conversion from floating decimal point to character
string (ESTR) ..................................................... 7-217
Conversion from floating-point angle to radian (Double
precision) (RADD).............................................. 7-277
Conversion from floating-point angle to radian (Single
precision) (RAD) ................................................ 7-275
Conversion from floating-point radian to angle (Double
precision) (DEGD) .........................7-281,7-283,7-285
Conversion from floating-point radian to angle (Single
precision) (DEG) ................................................ 7-279
Conversion from hexadecimal ASCII to BIN 16-bit
(HABIN) ............................................................. 7-195
Conversion from hexadecimal ASCII to BIN 32-bit
(DHABIN) ........................................................... 7-195

Conversion from hexadecimal BIN to ASCII (ASC)
........................................................................... 7-228
Conversion of Gray code to BIN 16-bit (GBIN).... 6-92
Conversion of Gray code to BIN 32-bit (DGBIN)
............................................................................. 6-92
Conversion to BIN
BCD 4-digit to BIN 16-bit (BIN) ........................ 6-75
BCD 8-digit to BIN 32-bit (DBIN)...................... 6-75
Floating decimal point data to BIN 16-bit (Double
precision) (INTD).............................................. 6-86
Floating decimal point data to BIN 16-bit (Single
precision) (INT) ................................................ 6-83
Floating decimal point data to BIN 32-bit (Double
precision) (DINTD) ........................................... 6-86
Floating decimal point data to BIN 32-bit (Single
precision) (DINT).............................................. 6-83
Conversion to floating decimal point (Double
precision) (FLTD, DFLTD) ................................... 6-81
Conversion to floating decimal point (Single precision)
(FLT, DFLT)......................................................... 6-78
COS (COS operation on floating-point data (Single
precision)).......................................................... 7-254
COS operation on floating-point data (Double
precision) (COSD) ............................................. 7-256
COS operation on floating-point data (Single
precision) (COS)................................................ 7-254
COS-1 operation on floating-point data (Double
precision) (ACOSD)........................................... 7-269
COS-1 operation on floating-point data (Single
precision) (ACOS) ............................................. 7-267
COSD (COS operation on floating-point data (Double
precision)).......................................................... 7-256
Count 1-phase input or down (UDCNT1) .......... 6-143
Count 2-phase input or down (UDCNT2) .......... 6-146
Counters (OUT C) ............................................... 5-26
[D]
D- (BIN 32-bit subtraction operations .................. 6-26
D(P).DDRD(Reading Devices to Another CPU)
........................................................................... 10-17
D(P).DDWR(Writing Devices to Another CPU)
........................................................................... 10-13
D* (BIN 32-bit multiplication operations).............. 6-32
D+ (BIN 32-bit addition operations) ..................... 6-26
D/ (BIN 32-bit division operations)....................... 6-32
D=, D<>, D>, D<=, D<, D>= (BIN 32-bit data
comparisons) ......................................................... 6-4
DABCD (Conversion from decimal ASCII to BCD
4-digit)................................................................ 7-198
DABIN (Conversion from decimal ASCII to BIN 16-bit)
........................................................................... 7-192
DAND (Logical products with 32-bit data) ............. 7-3
Data control instructions ...................................... 2-49
Data conversion instruction table ........................ 2-22
Data conversion instructions ............................... 6-73
Data dissociation in byte units (WTOB)............... 7-85
Data link instructions ........................................... 2-59
Data linking in byte units (BTOW) ....................... 7-85
Data processing instructions ............................... 2-35

Data table operation instructions ......................... 2-40
DATE- (Clock data subtraction operation) ......... 7-350
Date comparison (DT=,DT,DT>,DT=)................ 7-356
DATE+ (Clock data addition operation) ............. 7-348
DATERD (Reading clock data) .......................... 7-344
DATEWR (Writing clock data) ........................... 7-346
DB- (BCD 8-digit subtraction) .............................. 6-38
DB* (BCD 8-digit multiplication)........................... 6-44
DB+ (BCD 8-digit addition) .................................. 6-38
DB/ (BCD 8-digit division) .................................... 6-44
DBAND (32-bit dead band controls) .................. 7-324
DBCD (Conversion from BIN to BCD 8-digit) ...... 6-73
DBCDDA (Conversion from BCD 8-digit to decimal
ASCII) ................................................................ 7-189
DBIN (BCD 8-digit to BIN 16-bit conversion) ....... 6-75
DBINDA (Conversion from BIN 32-bit to decimal
ASCII) ................................................................ 7-183
DBINHA (Conversion from BIN 32-bit to hexadecimal
ASCII) ................................................................ 7-186
DBK- .................................................................... 6-63
DBK+ ................................................................... 6-62
DBL (BIN 16-bit to BIN 32-bit) ............................. 6-88
DCML (32-bit negation transfers) ...................... 6-114
DDABCD (Conversion from decimal ASCII to BCD
8-digit)................................................................ 7-198
DDABIN (Conversion from decimal ASCII to BIN
32-bit)................................................................. 7-192
DDEC (Decrementing 32-bit BIN)........................ 6-71
Debugging and failure diagnosis instructions ...... 2-42
DEC (Decrementing 16-bit BIN) .......................... 6-69
DECO (Decoding from 8 to 256 bits) ................... 7-71
Decoding from 8 to 256 bits (DECO) ................... 7-71
Decrement
BIN 16-bit (DEC) .............................................. 6-69
BIN 32-bit (DDEC)............................................ 6-71
Decrementing 16-bit BIN (DEC) .......................... 6-69
Decrementing 32-bit BIN (DDEC)........................ 6-71
DEG (Conversion from floating-point radian to angle
(Single precision)).............................................. 7-279
DEGD (Conversion from floating-point radian to angle
(Double precision)) ........................7-281,7-283,7-285
Deleting data from data tables (FDEL) .............. 7-157
Deletion of character string (STRDEL(P)) ......... 7-243
DELTA (Pulse conversion of direct output).......... 5-42
Designating data.................................................... 3-3
Designation of modification values in index
modification (IXDEV, IXSET) ............................. 7-148
Device range check ............................................. 3-27
DFLT (Conversion from BIN 32-bit to floating decimal
point (Single precision)) ....................................... 6-78
DFLTD (Conversion from BIN 32-bit to floating
decimal point (Double precision)) ........................ 6-81
DFRO (Reading 2-word data from intelligent function
modules) ............................................................ 7-160
DGBIN (Conversion of Gray code to BIN 16-bit)
............................................................................. 6-92
DGRY (BIN 32-bit to Gray code) ......................... 6-90
DHABIN (Conversion from hexadecimal ASCII to BIN
32-bit)................................................................. 7-195

Index - 5

I

DI (Interrupt disable) .......................................... 6-133
Digit designation .................................................... 3-4
Digit designation of bit devices .............................. 3-4
DINC (Incrementing 32-bit BIN)........................... 6-71
DINT (Floating decimal point data to BIN 32-bit (Single
precision)) ............................................................ 6-83
DINTD (Floating decimal point data to BIN 32-bit
(Double precision)) .............................................. 6-86
Direct 1-byte read from file register (ZRRDB).... 7-391
DIS (4-bit grouping of 16-bit data) ....................... 7-77
Display instructions.............................................. 2-41
Dissociation of random data (NDIS) .................... 7-81
Division
BCD 4-digit (B/) ................................................ 6-42
BCD 8-digit division (DB/) ................................ 6-44
BIN 16-bit (/)..................................................... 6-30
Division of floating decimal point(Double precision)
(ED/)................................................................. 6-56
Division of floating decimal point(Single precision)
(E/) ................................................................... 6-54
DLIMIT (Upper and lower limit controls for BIN 32-bit)
........................................................................... 7-321
DMAX (Maximum value search for 32-bit data)... 7-89
DMEAN(P) ......................................................... 7-103
DMIN (Minimum value search for 32-bit data) ..... 7-92
DMOV (32-bit transfers) .................................... 6-106
DNEG (Complement of 2 of BIN 32-bit data) ...... 6-94
DOR (Logical sums of 32-bit data) ...................... 7-11
Double precision to Single precision conversion
(EDCON) ........................................................... 6-104
Double word data .................................................. 3-6
DRCL (Left rotation of 32-bit data) ...................... 7-44
DRCR (Right rotation of 32-bit data) ................... 7-41
DROL (Left rotation of 32-bit data) ...................... 7-44
DROR (Right rotation of 32-bit data) ................... 7-41
DSCL(P) ............................................................ 7-331
DSCL2(P) .......................................................... 7-335
DSER (32-bit data searches)............................... 7-66
DSFL (1-word shift to left of n-word data).... 7-54,7-56
DSFR (1-word shift to right of n-word data)
..................................................................... 7-54,7-56
DSORT (BIN 32-bit data sort).............................. 7-95
DSTR (Conversion from BIN 32-bit to character string)
........................................................................... 7-206
DSUM (32-bit data checks) ................................. 7-69
DTEST (Bit tests)................................................. 7-61
DTO (Writing 2-word data to intelligent function
modules) ............................................................ 7-163
DUTY (Timing pulse generation) ....................... 7-388
DVAL (Conversion from character string to BIN 32-bit)
........................................................................... 7-212
DWSUM (Calculation of totals for 32-bit data)
................................................................. 7-101,7-103
DXCH (16-bit data exchanges).......................... 6-124
DXNR (32-bit data exclusive NOR operation) ..... 7-27
DXOR (32-bit exclusive OR operations) .............. 7-19
DZONE (Zone control for BIN 32-bit data)
....................................................... 7-327,7-330,7-334

Index - 6

[E]
E- (Subtraction of floating decimal point data (Single
precision)) .................................................... 6-46,6-48
E* (Multiplication of floating decimal point data (Single
precision)) ............................................................ 6-54
E+ (Addition of floating decimal point data (Single
precision)) .................................................... 6-46,6-48
E/ (Dividion of floating decimal point data (Single
precision)) ............................................................ 6-54
E=, E<>, E>, E<=, E<, E>= (Floationg decimal point
data comparisons(Single precision)) ..................... 6-6
ECALL (Sub-routine calls between program files)
........................................................................... 7-120
ECON (Single precision to Double precision
conversion) ........................................................ 6-102
ED- (Subtraction of floating decimal point data
(Double precision)) ...................................... 6-50,6-52
ED* (Multiplication of floating decimal point data
(Double precision)) .............................................. 6-56
ED+ (Addition of floating decimal point data (Double
precision)) .................................................... 6-50,6-52
ED/ (Dividion of floating decimal point data (Double
precision)) ............................................................ 6-56
ED=,ED<>,ED>,ED<=,ED<,ED>= (Floationg decimal
point data comparisons (Double precision)) .......... 6-8
EDCON (Double precision to Single precision
conversion) ........................................................ 6-104
EDMOV (Floating-point data transfer (Double
precision)) .......................................................... 6-110
EDNEG (Floating-point sign invertion (Double
precision)) ............................................................ 6-97
EFCALL (Output OFF calls between program files)
........................................................................... 7-125
EGF (Pulse operation results / leading edge) ...... 5-18
EGP (Pulse operation results / trailing edge)....... 5-18
EI (Interrupt enable) ........................................... 6-133
EMOD (Floating decimal point to BCD) ............. 7-245
EMOV (Floating-point data transfer (Single precision))
........................................................................... 6-108
ENCO (Encoding from 256 to 8 bits) ................... 7-73
Encoding from 256 to 8 bits (ENCO) ................... 7-73
END (End sequence program) ............................ 5-53
End main routine program (FEND) ...................... 5-51
End sequence program (END) ............................ 5-53
ENEG (Floating-point sign invertion(Single precision))
............................................................................. 6-96
EREXP (From BCD format data to floating decimal
point).................................................................. 7-248
Error display and annunciator reset instruction (LEDR)
........................................................................... 7-172
ESTR (Conversion from floating decimal point to
character string) ................................................. 7-217
EVAL (Conversion from character string to floating
decimal point) .................................................... 7-217
EXP (Exponent operation on floating-point data
(Single precision)) .............................................. 7-291
Expansion clock data addition operation (S.DATE+)
........................................................................... 7-366

Expansion clock data subtraction operation (S.DATE-)
........................................................................... 7-366
EXPD (Exponent operation on floating-point data
(Double precision)) ............................................ 7-294
Exponent operation on floating-point data (Double
precision) (EXPD).............................................. 7-294
Exponent operation on floating-point data (Single
precision) (EXP) ................................................ 7-291
Exponentiation operation on floating-point data
(Single precision) (POW(P)) .............................. 7-283
Exponentiation operation on floating-point data
(Single precision) (POWD(P)) ........................... 7-285
Extracting character string data from the left (LEFT)
........................................................................... 7-232
Extracting character string data from the right (RIGHT)
........................................................................... 7-232
[F]
FCALL (Subroutine program output OFF calls)
........................................................................... 7-116
FDEL (Deleting data from data tables) .............. 7-157
FEND (End main routine program)...................... 5-51
FF (Bit device output reverse) ............................. 5-40
FIFR (Reading oldest data from data tables) .... 7-153
FIFW (Writing data to the data tables)............... 7-151
File register direct 1-byte write (ZRWRB).......... 7-393
File setting for comments (QCDSET) ................ 7-342
FINS (Inserting data in data tables)................... 7-157
Fixed cycle pulse output (PLSY) ....................... 6-162
Floating decimal point data comparisons (Double
precision) (ED=, ED<>, ED>, ED<=, ED<, ED>=)
............................................................................... 6-8
Floating decimal point data comparisons (Single
precision) (E=, E<>, E>, E<=, E<, E>=) ................ 6-6
Floating decimal point to BCD (EMOD)............. 7-245
Floating-point data transfer (Double precision)
(EDMOV) ........................................................... 6-110
Floating-point data transfer (Single precision) (EMOV)
........................................................................... 6-108
Floating-point sign invertion (Double precision)
(EDNEG) ............................................................. 6-97
Floating-point sign invertion (Single precision) (ENEG)
............................................................................. 6-96
FLT (Conversion from BIN 16-bit to floating decimal
point (Single precision))....................................... 6-78
FLTD (Conversion from BIN 16-bit to floating decimal
point (Double precision)) ..................................... 6-81
FMOV (16-bit data block transfers) ......... 6-120,6-122
FOR (FOR to NEXT) ......................................... 7-105
FOR to NEXT (FOR, NEXT).............................. 7-105
Forced end of FOR to NEXT instruction loop (BREAK)
........................................................................... 7-108
FPOP (Reading newest data from data tables)
........................................................................... 7-155
FROM (Reading from other CPU shared memory)
............................................................................. 9-12
FROM (Reding 1-word data from intelligent function
modules)............................................................ 7-160

From BCD format data to floating decimal point
(EREXP) ............................................................ 7-248
[G]
GBIN (Conversion of Gray code to BIN 16-bit).... 6-92
GOEND (Jump to END)..................................... 6-132
GRY (BIN 16-bit to Gray code) ............................ 6-90
[H]
HABIN (Conversion from hexadecimal ASCII to BIN
16-bit)................................................................. 7-195
HEX (Conversion from ASCII to hexadecimal BIN)
........................................................................... 7-230
High speed retentive timer (OUTH ST)................ 5-22
High speed timer (OUTH T)................................. 5-22
High-speed block transfer of file register (RBMOV)
........................................................................... 7-448
HOUR (Time data conversion) .......................... 7-354
How to read instruction tables ............................... 2-4
How to read instructions ........................................ 4-2
[I]
I/O refrech (RFS) ............................................... 6-141
I/O refresh instruction table.................................. 2-27
Identical 32-bit data block transfers (DFMOV(P))
........................................................................... 6-122
IMASK (Interrupt program mask)....................... 6-133
INC (Incrementing 16-bit BIN) ............................. 6-69
Increment
BIN 16-bit (INC)................................................ 6-69
BIN 32-bit (DINC) ............................................. 6-71
Incrementing 16-bit BIN (INC) ............................. 6-69
Incrementing 32-bit BIN (DINC)........................... 6-71
Index modification................................................ 3-12
Indirect address read (ADRSET) ....................... 7-395
Indirect specification ............................................ 3-23
Inserting data in data tables (FINS) ................... 7-157
Insertion of character string (STRINS(P)).......... 7-241
INSTR (Character string search) ...7-239,7-241,7-243
Instructions for data link....................................... 2-59
INT (Floating decimal point data to BIN 16-bit (Single
precision)) ............................................................ 6-83
INTD (Floating decimal point data to BIN 16-bit
(Double precision)) .............................................. 6-86
Interrupt disable (DI) .......................................... 6-133
Interrupt enable (EI)........................................... 6-133
Interrupt program mask (IMASK)....................... 6-133
INV (Operation results inversion)......................... 5-15
Inversion
Bit device output reverse (FF).......................... 5-40
Operation results inversion (INV) ..................... 5-15
IRET (Recovery from interrupt programs) ......... 6-139
IX, IXEND (Index modification of entire ladder)
........................................................................... 7-144
IXDEV (Designation of modification values in index
modification) ...................................................... 7-148
IXSET (Designation of modification values in index
modification) ...................................................... 7-148

Index - 7

I

[J]
JMP (Pointer branch)......................................... 6-129
Jump to END (GOEND)..................................... 6-132
[K]
KEY (Numerical key input from keyboard)......... 7-396
[L]
Ladder block parallel connections (ORB) ............ 5-10
Ladder block series connections (ANB) .............. 5-10
LD ($=, $<>, $>, $<=, $<, $>=) (Character string data
comparisons) ....................................................... 6-11
LD (=, <>, >, <=, <, >=) (BIN 16-bit data comparisons)
............................................................................... 6-2
LD (A contact operation start)................................ 5-2
LD (D=, D<>, D>, D<=, D<, D>=) (BIN 32-bit data
comparisons) ......................................................... 6-4
LD (E=, E<>, E>, E<=, E<, E>=) (Floationg decimal
point data comparisons(Single precision)) ............ 6-6
LD (ED=, ED, ED>, ED<=, ED<, ED>=) (Floationg
decimal point data comparisons(Double precision))
............................................................................... 6-8
LDF (Pulse operation start / trailing edge) ....... 5-5,5-7
LDI (B contact operation start)............................... 5-2
LDP (Pulse operation start / leading edge)...... 5-5,5-7
LDPI, LDFI ............................................................. 5-7
Leading edge output (PLS).................................. 5-37
LEDR (Error display and annunciator reset instruction)
........................................................................... 7-172
LEFT (Extracting character string data from the left)
........................................................................... 7-232
Left rotation of 16-bit data (ROL, RCL)................ 7-38
Left rotation of 32-bit data (DROL, DRCL) .......... 7-44
LEN (Character string length detection) ............ 7-204
LIMIT (Upper and lower limit controls for BIN 16-bit)
........................................................................... 7-321
Link refresh instructions....................................... 2-59
Linking character strings ($+) ...................... 6-65,6-67
Linking of random data (NUNI) ............................ 7-81
Load (LD)............................................................... 5-2
Load + unload (PSWAPP) ................................. 7-445
Load inverse (LDI) ................................................. 5-2
Load program from Memory Card (PLOADP) ... 7-440
LOG (Natural logarithm operation on floating-point
data (Single precision))............................ 7-296,7-302
LOGD (Natural logarithm operation on floating-point
data (Double precision)) .................................... 7-298
Logical operation instructions .............................. 2-29
Logical product ...................................................... 7-2
Logical products with 16-bit data (WAND)............. 7-3
Logical products with 32-bit data (DAND) ............. 7-3
Logical sum ........................................................... 7-2
Logical sums of 16-bit data (WOR) ..................... 7-11
Logical sums of 32-bit data (DOR) ...................... 7-11
Low speed retentive timer (OUTH ST) ................ 5-22
Low speed timer (OUT T) .................................... 5-22

Index - 8

[M]
Master control instructions ................................... 5-47
Matrix input (MTR) ............................................. 6-166
MAX (Maximum value search for 16-bit data) ..... 7-89
Maximum value search for 16-bit data (MAX) ..... 7-89
Maximum value search for 32-bit data (DMAX) ... 7-89
MC (Setting the master control) ........................... 5-47
MCR (Resetting the master control) .................... 5-47
MEAN(P)............................................................ 7-103
MEF (Pulse operation results / trailing edge)....... 5-17
MEP (Pulse operation results / leading edge) ..... 5-17
MIDR (Random selection from character strings)
........................................................................... 7-235
MIDW (Random replacement in character strings)
........................................................................... 7-235
MIN (Minimum value search for 16-bit data)........ 7-92
Minimum value search for 16-bit data (MIN)........ 7-92
Minimum value search for 32-bit data (DMIN) ..... 7-92
MOV (16-bit transfers) ....................................... 6-106
MPP (Operation results pop) ............................... 5-12
MPS (Operation results push) ............................. 5-12
MRD (Operation results read).............................. 5-12
MTR (Matrix input) ............................................. 6-166
Multiplication
BCD 4-digit (B*)................................................ 6-42
BCD 8-digit (DB*) ............................................. 6-44
BIN 16-bit (*) .................................................... 6-30
BIN 32-bit (D*) .................................................. 6-32
Multiplication of floating decimal point (Double
precision) (ED*) ................................................ 6-56
Multiplication of floating decimal point (Single
precision) (E*) .................................................. 6-54
Multiplication and division of floating decimal point
(Double precision)(ED*, ED/) ............................... 6-56
Multiplication and division of floating decimal point
(Single precision)(E*, E/) ..................................... 6-54
[N]
Natural logarithm operation on floating-point data
(Double precision) (LOGD) ................................ 7-298
Natural logarithm operation on floating-point data
(Single precision) (LOG) .......................... 7-296,7-302
n-bit shift to left of 16-bit data (SFL) .................... 7-46
n-bit shift to right of 16-bit data (SFR).................. 7-46
n-bit shift to right or left of n-bit data (SFTBR(P),
SFTBL(P))............................................................ 7-51
n-bit shift to right or left of n-word data (SFTWR(P),
SFTWL(P))........................................................... 7-56
NEG (complement of 2 of BIN 16-bit data) .......... 6-94
Network refresh instruction (ZCOM) ...................... 8-2
NEXT (FOR to NEXT)........................................ 7-105
No operation (NOP, NOPLF, PAGE) ................... 5-57
NOP ..................................................................... 5-57
NOP (No operation) ............................................. 5-57
NOPLF (No operation page change) ................... 5-57
Number of steps .................................................. 3-34
Numerical key input (KEY)................................. 7-396
Numerical key input from keyboard (KEY)......... 7-396
NUNI (Linking of random data) ............................ 7-81

[O]
Operation errors .................................................. 3-27
Operation results inversion (INV) ........................ 5-15
Operation results pop (MPP) ............................... 5-12
Operation results push (MPS) ............................. 5-12
Operation results read (MRD) ............................. 5-12
Operation start (LD, LDI) ....................................... 5-2
OR ($=, $<>, $>, $<=, $<, $>=) (Character string data
comparisons) ....................................................... 6-11
OR (=, <>, >, <=, <, >=) (BIN 16-bit data comparisons)
............................................................................... 6-2
OR (A contact parallel connection)........................ 5-2
OR (D=, D<>, D>, D<=, D<, D>=) (BIN 32-bit data
comparisons) ......................................................... 6-4
OR (E=, E<>, E>, E<=, E<, E>=) (Floationg decimal
point data comparisons (Single precision)) ........... 6-6
OR (ED=, ED<>, ED>, ED<=, ED<, ED>=) (Floationg
decimal point data comparisons (Double precision))
............................................................................... 6-8
Or inverse (ORI) .................................................... 5-2
ORB (Ladder block parallel connections) ............ 5-10
ORF (Pulse parallel connection / trailing edge)
......................................................................... 5-5,5-7
ORI (B contact parallel connection)....................... 5-2
ORP (Pulse parallel connection / leading edge)
......................................................................... 5-5,5-7
ORPI, ORFI ........................................................... 5-8
Other convenient instructions ................................ 2-6
Other instructions ................................................ 5-55
Application instructions .................................... 2-29
Sequence instructions........................................ 2-6
OUT
Annunciator output (OUT F)............................. 5-28
Counters (OUT C)............................................ 5-26
High speed retentive timer (OUTH ST)............ 5-22
High speed timer (OUTH T) ............................. 5-22
Low speed retentive timer (OUT ST) ............... 5-22
Low speed timer (OUT T) ................................ 5-22
Output (OUT) ................................................... 5-20
Out instructions (OUT)......................................... 5-20
Output instruction table.......................................... 2-8
Output instructions (OUT).................................... 5-20
Output of sub-routine program OFF calls (FCALL)
........................................................................... 7-116
Output OFF calls between program files (EFCALL)
........................................................................... 7-125
Output reverse (FF) ............................................. 5-40
[P]
PAGE (No operation page change)..................... 5-57
Page change (NOPLF) ........................................ 5-57
Page change (PAGE n) ....................................... 5-57
Parallel connection (OR, ORI) ............................... 5-2
Parallel connections (ORB) ................................. 5-10
PCHK (Program low speed execution registeration
instruction) ......................................................... 7-384
PLF (Trailing edge output)................................... 5-37
PLOADP (Load program from Memory Card) ... 7-440

PLOW (Program low speed execution registration)
........................................................................... 7-382
PLS (Leading edge output).................................. 5-37
PLSY (Fixed cycle pulse output)........................ 6-162
POFF (Program output OFF standby instruction)
........................................................................... 7-378
Pointer branching instruction (CJ, SCJ, JMP) ... 6-129
Pop (MPP) ........................................................... 5-12
PR (Print ASCII code instruction) ...................... 7-166
PRC (Print comment instruction) ....................... 7-169
Print ASCII code instruction (PR) ...................... 7-166
Print comment instruction (PRC) ....................... 7-169
Program branch instruction table......................... 2-27
Program control instructions ................................ 2-56
Program execution control instruction table......... 2-27
Program low speed execition registration instruction
(PCHK) .............................................................. 7-384
Program low speed execution registration (PLOW)
........................................................................... 7-382
Program output OFF standby instruction (POFF)
........................................................................... 7-378
Program scan execution registration instruction
(PSCAN) ............................................................ 7-380
Program standby instruction (PSTOP) .............. 7-377
PSCAN (Program scan execution registration
instruction) ......................................................... 7-380
PSTOP (Program standby instruction) .............. 7-377
PSWAPP (Load + unload) ................................. 7-445
Pulse conversion
(DELTA) ........................................................... 5-42
(EGF, EGP)...................................................... 5-18
(MEF, MEP) ..................................................... 5-17
Pulse conversion of direct output (DELTA).......... 5-42
Pulse density measurement (SPD).................... 6-160
Pulse NOT operation start, pulse NOT series
connection, pulse NOT parallel connection LDPI,LDFI,
ANDPI,ANDFI,ORPI,ORFI) ................................... 5-7
Pulse operation results
Operation result conversions (MEF, MEP)....... 5-17
Pulse conversions of edge relay operation results
(EGF, EGP)...................................................... 5-18
Pulse operation start (LDF, LDP)..................... 5-5,5-7
Pulse parallel connection (ORF, ORP) ............ 5-5,5-7
Pulse series connection (ANDF, ANDP)................ 5-5
Pulse width modulation (PWM).......................... 6-164
PUNLOADP (Unload program from program memory)
........................................................................... 7-443
Push (MPS) ......................................................... 5-12
PWM (Pulse width modulation).......................... 6-164
[Q]
QCDSET (File setting for comments) ................ 7-342
QCPU dedicated instructions............................... 2-60
QDRSET(Setting files for file register use) ........ 7-339
[R]
RAD (Conversion from floating-point angle to radian
(Single precision)).............................................. 7-275

Index - 9

I

RADD (Conversion from floating-point angle to radian
(Double precision)) ............................................ 7-277
RAMP (Ramp signal) ......................................... 6-157
Ramp signal (RAMP) ......................................... 6-157
Random number generation (RND/SRND)........ 7-304
Random selection from and replacement in character
strings (MIDR) ................................................... 7-235
Random selection replacement in character strings
(MIDW) .............................................................. 7-235
RBMOV (High-speed block transfer of file register)
........................................................................... 7-448
RCL (Left rotation of 16-bit data) ......................... 7-38
RCR (Right rotation of 16-bit data) ...................... 7-35
Read (MRD) ........................................................ 5-12
Read data from standard ROM (S.DEVLD)....... 7-438
Reading 1-word data from intelligent function modules
(FROM).............................................................. 7-160
Reading 2-word data from intelligent function modules
(DFRO) .............................................................. 7-160
Reading clock data (DATERD) .......................... 7-344
Reading data from designated file (SP.FREAD) 7-424
Reading device comment data (COMRD) ......... 7-201
Reading expansion clock data (S.DATERD) ..... 7-366
Reading from other CPU shared memory (FROM)
............................................................................. 9-12
Reading module information (UNIRD) ............... 7-402
Reading newest data from data tables (FPOP)
........................................................................... 7-155
Reading oldest data from data tables (FIFR) .... 7-153
Reading routing information (RTREAD) ................ 8-6
Real number data .................................................. 3-8
Recovery from interrupt programs (IRET) ......... 6-139
Refresh instruction (COM) ................................. 7-134
Related programming manuals ............................. 1-2
Resetting devices (RST).............................. 5-32,5-35
Resetting the annunciators (RST F) .................... 5-35
Resetting the master control (MCR) .................... 5-47
Resetting watchdog timer (WDT) ...................... 7-386
RET (Return from sub-routine programs) .......... 7-115
Return from sub-routine programs (RET) .......... 7-115
Revercing
Bit device output reverse (FF).......................... 5-40
Floating-point sign invertion (Double precision)
(EDNEG) .......................................................... 6-97
Floating-point sign invertion (Single precision)
(ENEG)............................................................. 6-96
Operation results inversion (INV) ..................... 5-15
RFS (I/O refresh) ............................................... 6-141
RIGHT (Extracting character string data from the right)
........................................................................... 7-232
Right rotation of 16-bit data (ROR, RCR) ............ 7-35
Right rotation of 32-bit data (DROR, DRCL)........ 7-41
RND (Random number generation and series update)
........................................................................... 7-304
ROL (Left rotation of 16-bit data) ......................... 7-38
ROR (Right rotation of 16-bit data) ...................... 7-35
Rotary table shortest direction control (ROTC)
........................................................................... 6-154
Rotation instructions ............................................ 2-32

Index - 10

ROTC (Rotary table shortest direction control)
........................................................................... 6-154
RSET (Switching file register numbers) ............. 7-337
RST
Resetting devices (RST) .................................. 5-32
Resetting the annunciators (RST F)................. 5-35
RTREAD (Reading routing information) ................ 8-6
RTWRITE (Writing routing information) ................. 8-8
[S]
S.DATE- (Expansion clock data subtraction operation)
........................................................................... 7-366
S.DATE+ (Expansion clock data addition operation)
........................................................................... 7-366
S.DATERD (Reading expansion clock data) ..... 7-366
S.DEVLD (Read data from standard ROM) ....... 7-438
S.TO (Write to host CPU shared memory) ............ 9-4
Scaling (Point-by-point coordinate data) (SCL(P),
DSCL(P)) ........................................................... 7-330
Scaling (Point-by-point coordinate data) (SCL2(P),
DSCL2(P)) ......................................................... 7-334
SCJ (Pointer branching instruction) ................... 6-129
SCL(P) ............................................................... 7-330
SCL2 .................................................................. 7-334
SECOND (Time data conversion)...................... 7-352
SEG (7-segment decode) .................................... 7-75
Sequence instructions ........................................... 2-6
Sequence program stop (STOP) ......................... 5-55
SER (16-bit data searches) ................................. 7-66
Series connection (AND, ANI) ............................... 5-2
Series connections (ANB).................................... 5-10
SET
Setting devices (SET) ...................................... 5-30
Setting the annunciators (SET F) ..................... 5-35
Setting devices (SET) .................................. 5-30,5-35
Setting files for file register use (QDRSET) ....... 7-339
Setting the annunciators (SET F) ........................ 5-35
Setting the master control (MC) ........................... 5-47
SFL (n-bit shift to left of 16-bit data) .................... 7-46
SFR (n-bit shift to right of 16-bit data).................. 7-46
SFT (Bit device shifts).......................................... 5-44
SFTBL(P) ............................................................. 7-52
SFTBR(P) ............................................................ 7-51
SFTWL(P) ............................................................ 7-57
SFTWR(P) ........................................................... 7-56
Shift instruction ............................................ 5-44,7-46
(Application instructions) .................................. 2-29
Shift instruction table
(Sequence instructions) ..................................... 2-6
SIN (SIN operation on floating-point data (Single
precision)) .......................................................... 7-250
SIN operation on floating-point data (Double
precision) (SIND) ............................................... 7-252
SIN operation on floating-point data (Single precision)
(SIN) .................................................................. 7-250
SIN-1 operation on floating-point data (Double
precision) (ASIND) ............................................. 7-265
SIN-1 operation on floating-point data (Single
precision) (ASIN) ............................................... 7-262

SIND (SIN operation on floating-point data (Double
precision)).......................................................... 7-252
Single precision to Double precision conversion
(ECON).............................................................. 6-102
SORT (BIN 16-bit data sort) ................................ 7-95
SP.CONTSW (System switching instruction) ...... 11-2
SP.DEVST (Writing data to standard ROM)...... 7-436
SP.FREAD (Reading data from designated file)
........................................................................... 7-424
SP.FWRITE (Writing data to designated file) .... 7-413
SPD (Pulse density measurement) ................... 6-160
Special format failure checks (CHKST, CHK) ... 7-175
Special function instructions ................................ 2-46
Special timer (STMR) ........................................ 6-151
SQR (Square root operation for floating-point data
(Single precision)).............................................. 7-287
SQRD (Square root operation for floating-point data
(Double precision)) ............................................ 7-289
Square root operation for floating-point data (Double
precision) (SQRD) ............................................. 7-289
Square root operation for floating-point data (Single
precision) (SQR)................................................ 7-287
SRND (Random number generation and series
updates)............................................................. 7-304
STMR (Special function timer)........................... 6-151
STOP (Sequence program stop) ......................... 5-55
STR (Conversion from BIN 16-bit to character string)
........................................................................... 7-206
Structure creation instructions ............................. 2-38
Subrotine program calls (CALL) ........................ 7-110
Subroutine calls (XCALL) .................................. 7-129
Subroutine calls between program files (ECALL)
........................................................................... 7-120
Subroutine program output OFF calls (FCALL)
........................................................................... 7-116
Subset processing ............................................... 3-25
Subtraction
BCD 4-digit subtraction (B-) ............................. 6-34
BCD 8-digit subtraction (DB-) .......................... 6-38
BIN 16-bit subtraction operations (-) ................ 6-22
BIN 32-bit subtraction operations (D-) ............. 6-26
Block subtraction (BK-) ............................ 6-59,6-62
Subtraction of floating decimal point data (Double
precision) (ED-)........................................ 6-50,6-52
Subtraction of floating decimal point data (Single
precision) (E-) .......................................... 6-46,6-48
SUM (16-bit data checks) .................................... 7-69
SWAP (Upper and lower byte exchanges) ........ 6-128
Switching file register numbers (RSET)............. 7-337
Switching instructions .......................................... 2-51
System Switching (SP.CONTSW) ....................... 11-2
[T]
TAN (TAN operation on floating-point data (Single
precision)).......................................................... 7-258
TAN operation on floating-point data (Double
precision)(TAND)............................................... 7-260
TAN operation on floating-point data (Single
precision)(TAN) ................................................. 7-258

TAN-1 operation on floating-point data (Double
precision)(ATAND)............................................. 7-273
TAN-1 operation on floating-point data (Single
precision)(ATAN) ............................................... 7-271
TAND (TAN operation on floating-point data (Double
precision)) .......................................................... 7-260
Teaching timer (TTMR)...................................... 6-149
Termination instruction table.................................. 2-9
TEST (Bit tests) ................................................... 7-61
TIMCHK (Time check instruction)...................... 7-390
Time check instruction (TIMCHK)...................... 7-390
Time data conversion (HOUR) ......7-354,7-356,7-361
Time data conversion (SECOND)...................... 7-352
Timer (OUT T) ..................................................... 5-22
Timing pulse generation (DUTY) ....................... 7-388
TO (Writing 1-word data to intelligent function
modules) ............................................................ 7-163
TRACE (Trace set) ............................................ 7-411
TRACER (Trace reset) ...................................... 7-411
TTMR (Teaching timer)...................................... 6-149
Types of Instructions.............................................. 2-2
[U]
UDCNT1 (Counter 1-phase input up or down) .. 6-143
UDCNT2 (Counter 2-phase input up or down) .. 6-146
UNI (4-bit linking of 16-bit data) ........................... 7-79
UNIRD (Reading module information) ............... 7-402
Unload program from program memory (PUNLOADP)
........................................................................... 7-443
Up / Down counter
Count 1-phase input or dawn (UDCNT1) ....... 6-143
Count 2-phase input or down (UDCNT2) ....... 6-146
Upper and lower byte exchanges (SWAP) ........ 6-128
Upper and lower limit controls for BIN 32-bit (DLIMIT)
........................................................................... 7-321
[V]
VAL (Conversion from character string to BIN 16-bit)
........................................................................... 7-212
[W]
WAND (Logical products with 16-bit data)............. 7-3
WDT (Resetting watchdog timer)....................... 7-386
WOR (Logical sums of 16-bit data)...................... 7-11
WORD (Conversion from BIN 32-bit to BIN 16-bit)
............................................................................. 6-89
Word data .............................................................. 3-4
Word device bit designation................................... 3-3
Writing 1-word data to intelligent function modules
(TO) ................................................................... 7-163
Writing 2-word data to intelligent function modules
(DTO)................................................................. 7-163
Writing clock data (DATEWR) ........................... 7-346
Writing data to designated file (SP.FWRITE) .... 7-413
Writing data to standard ROM (SP.DEVST) ...... 7-436
Writing data to the data tables (FIFW)............... 7-151
Writing routing information (RTWRITE) ................. 8-8
Writing to the CPU shared memory of host CPU... 9-2

Index - 11

I

S.TO................................................................... 9-4
TO ...................................................................... 9-7
WSUM (Calculation of totals for 16-bit data) ....... 7-99
WTOB (Data dissociation in byte units) ............... 7-85
WXNR (16-bit data exclusive NOR operation)..... 7-27
WXNR (16-bit data non-exclusive logical sum
operations)........................................................... 7-30
WXOR (16-bit exclusive OR operations) ..... 7-19,7-22
[X]
XCALL (Subroutine program call)...................... 7-129
XCH (32-bit data exchange) .............................. 6-124
[Z]
ZCOM (Network refresh instruction) ...................... 8-2
ZONE (Zone control for BIN 16-bit)
....................................................... 7-327,7-330,7-334
Zone control for BIN 16-bit (ZONE)
....................................................... 7-327,7-330,7-334
Zone control for BIN 32-bit data (DZONE)
....................................................... 7-327,7-330,7-334
ZPOP (Batch recovery of index register) ........... 7-400
ZPUSH (Batch save of index register)............... 7-400
ZRRDB (Direct 1-byte read from file register).... 7-391
ZRWRB (File register direct 1-byte write) .......... 7-393

Index - 12

Warranty

Please confirm the following product warranty details before using this product.

1. Gratis Warranty Term and Gratis Warranty Range
If any faults or defects (hereinafter "Failure") found to be the responsibility of Mitsubishi occurs during use of the
product within the gratis warranty term, the product shall be repaired at no cost via the sales representative or
Mitsubishi Service Company.
However, if repairs are required onsite at domestic or overseas location, expenses to send an engineer will be
solely at the customer's discretion. Mitsubishi shall not be held responsible for any re-commissioning,
maintenance, or testing on-site that involves replacement of the failed module.
[Gratis Warranty Term]
The gratis warranty term of the product shall be for one year after the date of purchase or delivery to a designated
place.
Note that after manufacture and shipment from Mitsubishi, the maximum distribution period shall be six (6) months,
and the longest gratis warranty term after manufacturing shall be eighteen (18) months. The gratis warranty term of
repair parts shall not exceed the gratis warranty term before repairs.
[Gratis Warranty Range]
(1) The range shall be limited to normal use within the usage state, usage methods and usage environment, etc.,
which follow the conditions and precautions, etc., given in the instruction manual, user's manual and caution
labels on the product.
(2) Even within the gratis warranty term, repairs shall be charged for in the following cases.
1. Failure occurring from inappropriate storage or handling, carelessness or negligence by the user. Failure
caused by the user's hardware or software design.
2. Failure caused by unapproved modifications, etc., to the product by the user.
3. When the Mitsubishi product is assembled into a user's device, Failure that could have been avoided if
functions or structures, judged as necessary in the legal safety measures the user's device is subject to or
as necessary by industry standards, had been provided.
4. Failure that could have been avoided if consumable parts (battery, backlight, fuse, etc.) designated in the
instruction manual had been correctly serviced or replaced.
5. Failure caused by external irresistible forces such as fires or abnormal voltages, and Failure caused by force
majeure such as earthquakes, lightning, wind and water damage.
6. Failure caused by reasons unpredictable by scientific technology standards at time of shipment from
Mitsubishi.
7. Any other failure found not to be the responsibility of Mitsubishi or that admitted not to be so by the user.

2. Onerous repair term after discontinuation of production
(1) Mitsubishi shall accept onerous product repairs for seven (7) years after production of the product is
discontinued.
Discontinuation of production shall be notified with Mitsubishi Technical Bulletins, etc.
(2) Product supply (including repair parts) is not available after production is discontinued.

3. Overseas service
Overseas, repairs shall be accepted by Mitsubishi's local overseas FA Center. Note that the repair conditions at
each FA Center may differ.

4. Exclusion of loss in opportunity and secondary loss from warranty liability
Regardless of the gratis warranty term, Mitsubishi shall not be liable for compensation of damages caused by any
cause found not to be the responsibility of Mitsubishi, loss in opportunity, lost profits incurred to the user by Failures
of Mitsubishi products, special damages and secondary damages whether foreseeable or not , compensation for
accidents, and compensation for damages to products other than Mitsubishi products, replacement by the user,
maintenance of on-site equipment, start-up test run and other tasks.

5. Changes in product specifications
The specifications given in the catalogs, manuals or technical documents are subject to change without prior notice.

6. Product application
(1) In using the Mitsubishi MELSEC programmable controller, the usage conditions shall be that the application will
not lead to a major accident even if any problem or fault should occur in the programmable controller device,
and that backup and fail-safe functions are systematically provided outside of the device for any problem or
fault.
(2) The Mitsubishi programmable controller has been designed and manufactured for applications in general
industries, etc. Thus, applications in which the public could be affected such as in nuclear power plants and
other power plants operated by respective power companies, and applications in which a special quality
assurance system is required, such as for Railway companies or Public service purposes shall be excluded
from the programmable controller applications.
In addition, applications in which human life or property that could be greatly affected, such as in aircraft,
medical applications, incineration and fuel devices, manned transportation, equipment for recreation and
amusement, and safety devices, shall also be excluded from the programmable controller range of
applications.
However, in certain cases, some applications may be possible, providing the user consults their local
Mitsubishi representative outlining the special requirements of the project, and providing that all parties
concerned agree to the special circumstances, solely at the users discretion.

Microsoft, Windows, Windows NT are registered trademarks of Microsoft Corporation in the United States and other
countries.
Pentium and Celeron are trademarks of Intel Corporation in the United States and other countries.
Ethernet is a trademark of Xerox Co., Ltd. in the United States.
CompactFlash is a trademark of SanDisk Corporation.
VxWorks, Tornado, WindPower, WindSh and WindView are registered trademarks of Wind River Systems, Inc.
Other company names and product names used in this document are trademarks or registered trademarks of respective
owners.

SH(NA)-080809ENG-C 2/2



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